SystemVerilog / Verilog · Quantized matrix multiply for CNN inference · Course project (ECE 284)
A hardware design and verification repo for a 2D systolic-array GEMM core used with VGG16 under mixed-precision quantization. The work spans RTL simulation, FPGA bring-up, activation handling, and an ASIC-style physical-design experiment.
| Area | What we built |
|---|---|
| Architecture | Weight-stationary (WS) and output-stationary (OS) dataflows in a reconfigurable 2D array (Part3_Reconfigurable); baseline and SIMD-style variants in Part1_Vanilla and Part2_SIMD. |
| Quantization & ML | VGG16 QAT notebooks; greedy mixed-precision (4/2-bit) layer selection and sensitivity study (Part2_SIMD, Part5_Alpha/Alpha3_QuantStudy). |
| Nonlinearities | SFP (Special Function Processor) using LUTs for activations (sfp.v and Alpha1 SFP work under Part5_Alpha). |
| System validation | Hardware–software co-design on RFSoC 4×2 Pynq (Part5_Alpha/Alpha2_Pynq). |
| Physical design | OpenROAD flow (IHP 130 nm open PDK bundle in-tree) for synthesis, placement, and routing (Part5_Alpha/Alpha4_OpenROAD). |
Part1_Vanilla— Baseline systolic core, 4-bit QAT path, simulation + FPGA report layout.Part2_SIMD— SIMD-oriented hardware + 2-bit activation / 4-bit weight mixed-precision flow.Part3_Reconfigurable— WS ↔ OS switching without recompilation for the default testbench.Part4_Poster— Poster and related materials.Part5_Alpha— Milestones: SFP, Pynq integration, quantization study, OpenROAD.Part6_Report— Final write-up.Part7_ProgressReport— Progress snapshots.
Per-part notes and run hints (e.g. iverilog + filelist) live in each part’s own README.md where present.
- RTL / sim: Verilog / SystemVerilog, Icarus Verilog–style flows (
filelistunderhardware/sim). - ML: Jupyter (VGG16 QAT and quantization analysis).
- FPGA: Xilinx/Vivado project under Pynq alpha.
- ASIC: OpenROAD scripts and reports under
Alpha4_OpenROAD.
Academic coursework artifacts are provided as-is for portfolio and reproducibility. Not all generated vendor or PDK collateral is redistributable; treat large binary trees as reference-only when browsing.
If you landed here from a resume: the bullets above match the implementation → quantization → silicon path narrative; drill into Part1–Part3 for core RTL and Part5_Alpha for system and tapeout-style experiments.