feat: eliminate false sharing via cache-line alignment (#4)

[HawkinWay]

The Problem: False Sharing

Previously, write_idx and read_idx resided on the same 64-byte cache line. When the producer thread updated write_idx, the CPU hardware MESI protocol invalidated the entire cache line on the consumer core, creating severe Cache Line Bouncing and stalling execution despite using fine-grained Acquire-Release semantics.

Solution

• Applied alignas(hardware_destructive_interference_size) (or 64-byte fallback) to separate write_idx and read_idx onto distinct cache lines.
• Suppressed GCC -Winterference-size ABI warnings by providing explicit cache-line constants/flags where applicable.