feat(dcp): add depth-N native CKV prefetch

[FujitsuPolycom]

Summary

• add configurable depth-N lookahead for the B12X full-CKV prefill gather
• preserve depth 0 as the synchronous control and depth 1 as the default
• support the native 432-byte NVFP4 + BF16-RoPE cache writer
• keep stream ownership lazy and scoped to the active workspace/lane
• invalidate prefetched state on allocation/geometry changes and recover incomplete steps without host-blocking cleanup
• fall back to serial behavior during CUDA graph capture

Validation

• 50 focused policy/workspace tests passed
• depth 0/1/3, target/draft isolation, first-request discovery, dedicated per-lane ring allocation, generation replacement, profile cleanup, graph-capture fallback, and incomplete-step recovery are covered
• Ruff, compileall, and git diff checks passed
• ai01 TP4/DCP4/MTP3 native-432 depth 0/1/3 each returned the exact expected answer twice at 120,006 prompt tokens with the same SHA-256
• scheduler KV pool was 483,840 tokens in every arm; after lazy allocation depth 1 retained 566-655 MiB free/GPU and depth 3 retained 246-335 MiB
• short 64K prefill A/B was 3,171 tok/s at depth 0 and 3,180 tok/s at depth 3, which is neutral within measurement noise
  Test host: ai01 is an ASUS Pro WS WRX90E-SAGE SE system with an AMD Ryzen Threadripper PRO 9965WX, 128 GiB RAM, and 4x NVIDIA RTX PRO 6000 Blackwell 96 GB GPUs at 400 W, each on a PCIe 5.0 x16-capable link; IOMMU is off.

Scope

This is the full-CKV prefill lookahead layer only. Replicated indexer policy and selected-record sparse decode are separate PRs. Fork-only integration draft; no upstream PR has been opened.

Design document

GLM-5.2 Sparse CKV under Decode Context Parallelism is the canonical architecture, configuration, validation, and upstream-decomposition reference for this PR stack.

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