feat(dcp): replicate target sparse-indexer cache#2
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Summary
Dependency
This PR is intentionally stacked on #1, which provides lockstep physical-block allocation for mixed replicated/sharded MLA cache groups.
Validation
Physical DCP6/DCP8 hardware validation is pending; this PR currently claims arithmetic coverage only for those topologies. GMU 0.960 left insufficient transient indexer scratch for the 120K request; 0.955 passed with more than 1.2 GiB free after graph capture.
Test host: ai01 is an ASUS Pro WS WRX90E-SAGE SE with a Threadripper PRO 9965WX, 128 GiB RAM, and 4x RTX PRO 6000 Blackwell 96 GB GPUs at 400 W, each on a PCIe 5.0 x16-capable link; IOMMU is off.
Scope
Fork-only integration draft. No upstream PR has been opened.
Design document
GLM-5.2 Sparse CKV under Decode Context Parallelism is the canonical architecture, configuration, validation, and upstream-decomposition reference for this PR stack.