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feat(dcp): replicate target sparse-indexer cache#2

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FujitsuPolycom wants to merge 1 commit into
codex/kv-cache-lockstep-mla-groupsfrom
codex/replicated-target-indexer
Draft

feat(dcp): replicate target sparse-indexer cache#2
FujitsuPolycom wants to merge 1 commit into
codex/kv-cache-lockstep-mla-groupsfrom
codex/replicated-target-indexer

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@FujitsuPolycom

@FujitsuPolycom FujitsuPolycom commented Jul 20, 2026

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Summary

  • add an opt-in replicated K-cache for target-model B12X sparse-indexer layers under DCP
  • keep target MLA CKV DCP-sharded and keep MTP/draft indexer behavior unchanged
  • size replicated manager pages for the effective global layout
  • bypass DCP localization and the DCP top-k merge only for the replicated indexer cache
  • validate DCP2/DCP4/DCP6/DCP8 metadata arithmetic

Dependency

This PR is intentionally stacked on #1, which provides lockstep physical-block allocation for mixed replicated/sharded MLA cache groups.

Validation

  • model construction/default tests: 11 passed
  • full B12X sparse-indexer tests: 16 passed
  • focused builder/localization/arithmetic tests: 28 passed
  • real TP4/DCP4/MTP3 service boot passed with native 432-byte nvfp4_ds_mla + BF16 RoPE
  • 120,006-token exact needle retrieval passed twice with identical content hashes
  • 361,216-token GPU KV pool at GMU 0.955
  • short smoke: prefill 3,543 tok/s at 8K and 3,257 tok/s at 64K; C1 decode 64.2 and 68.4 tok/s
  • Ruff check and format check passed
  • git diff check passed

Physical DCP6/DCP8 hardware validation is pending; this PR currently claims arithmetic coverage only for those topologies. GMU 0.960 left insufficient transient indexer scratch for the 120K request; 0.955 passed with more than 1.2 GiB free after graph capture.

Test host: ai01 is an ASUS Pro WS WRX90E-SAGE SE with a Threadripper PRO 9965WX, 128 GiB RAM, and 4x RTX PRO 6000 Blackwell 96 GB GPUs at 400 W, each on a PCIe 5.0 x16-capable link; IOMMU is off.

Scope

Fork-only integration draft. No upstream PR has been opened.

Design document

GLM-5.2 Sparse CKV under Decode Context Parallelism is the canonical architecture, configuration, validation, and upstream-decomposition reference for this PR stack.

@FujitsuPolycom FujitsuPolycom added the verified Validated by focused tests label Jul 20, 2026
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@FujitsuPolycom
FujitsuPolycom force-pushed the codex/kv-cache-lockstep-mla-groups branch from f32818f to b260455 Compare July 21, 2026 04:31
@FujitsuPolycom
FujitsuPolycom force-pushed the codex/replicated-target-indexer branch from ffba4c1 to e9198c5 Compare July 21, 2026 04:31
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