feat(comm): add selected-record PCIe exchange

[FujitsuPolycom]

Summary

• add a generic selected-record CUDA-IPC exchange for world sizes 1-32
• write fixed-width records directly into each destination rank's IPC slab
• support aligned 16-byte vector copies and arbitrary byte-width fallback
• validate rank-wide geometry and bidirectional P2P reachability before transfer
• preserve graph-stable state with stream affinity and device-only barriers

The public API is exposed from sparkinfer.comm.pcie as
SelectedRecordExchange. GLM/vLLM union, remap, prefetch, and attention policy
remain outside Sparkinfer.

Sparkinfer rebase

The branch is based on local-inference-lab/sparkinfer@ec2cd4d. Python and CUDA
sources live under sparkinfer/comm/pcie, use Sparkinfer-prefixed JIT and test
gates, and are included in the built wheel. No b12x.distributed compatibility
package is added.

Validation

• focused CPU/source suite: 16 passed, 2 GPU-gated skips
• ai01 exact-image GPU gate: 2 passed at world sizes 2 and 4
• eager execution and CUDA graph replay passed
• exact 16-byte, 37-byte, and 432-byte copies passed
• source and destination offsets above 2 GiB passed
• wheel-content, Ruff, compileall, and import checks passed

Test host: ai01 is an ASUS Pro WS WRX90E-SAGE SE with a Threadripper PRO
9965WX, 128 GiB RAM, and 4x RTX PRO 6000 Blackwell 96 GB GPUs at 400 W.

Scope

Transport only. The copy-engine variant is intentionally stacked in the next PR.

AI-assisted implementation under human direction; the diff and validation
results were reviewed before publication.

Design document

GLM-5.2 Sparse CKV under Decode Context Parallelism is the canonical architecture, transport-contract, validation, and upstream-decomposition reference for this PR stack.