This repository contains source files related to the proposed memory controller.
./benchmarks/ -> directory to hold memory traces
./gen/ -> folder in which Vivado project is generated
./patches/ -> patch files used to update AMD MIG files in-place to instantiate OpenDRAM as the controller
./results/ -> holding the simulation log files.
./src/ -> source files for the OpenDRAM and the simulation infrastructure
- AMD Vivado Design Suite 2022.1
There are three scripts that must be executed as follows to instantiate OpenDRAM, AMD MIG PHY, and the simulation platform. Although our scripts are written for Ubuntu and do not directly work on Windows, users can execute the PowerShell scripts provided in each step to generate OpenDRAM through Windows Subsystem for Linux (WSL).
Please note that in order to use PowerShell scripts, user must:
- Ensure that the WSL is enabled and the command "wsl" works on their PowerShell.
- Ensure that Vivado can be executed through PowerShell using command "vivado".
The script below updates the source files for the indicated command scheduler version. It also updates the timing constraints files based on the desired memory part.
Ubuntu
./01_update_sources_linux.sh -cs [command_scheduler_version] -part [memory_part]
Windows
.\01_update_sources_powershell.ps1
** Unlike the Ubuntu script, the PowerShell script in this step does not accept any command-line arguments. Therefore, users should change the arguments as desired inside the file, where it calls the Ubuntu script.
Supported values for [command_scheduler_version]: a number between 1 to 5 (the version index)
Supported values for [memory_part]: the current version of the repo provides timing constraints for memory parts "mt40a256m16ge083e", and "mt40a512m8rh075e".
The script in step 2 creates a Vivado project, imports OpenDRAM sources, and generate AMD MIG and AMD AXI VIP. The Vivado project will open at the end of this script.
Ubuntu
./02_gen_opendram_linux.sh
Windows
.\02_gen_opendram_powershell.ps1
After executing this step, the MIG files get updated to instantiate OpenDRAM as the controller.
Ubuntu
./03_run_patches_linux.sh
Windows
.\03_run_patches_powershell.ps1
Users are able to run simulations using either the synthesizable MIG Traffic Generator (MIG TG, hereafter) or the non-synthesizable custom infrastructor (AXI VIP, hereafter), depending on the macros defined below.
The custom simulation infrastructure is developed using AMD AXI VIP, which reads memory access traces in a particular format and generates corresponding requests to the memory controller. Our infrustructure is able to mimic a multi-kernel system in which the arbitration is done in a round-robin fashion. Users can also define the size of stream buffer for kernels. Both type of simulations can be simply run through Vivado ISIM.
Setup parameters for the simulation infrastructure are accessible in the file below.
./src/axi_vip/sim_macros.svh
Macros in the file (For more clarity, please also read the comments in the file for each macro):
- USE_AXI_VIP: Flag to enable custom simulation infrastructure. Traffic generator is enabled if this macro is not defined.
- LINUX_OS: Flag to indicate the use of Linux OS.
- NUM_CORES: Number of accelerator kernels generating traffic.
- CORE_INDEX_WIDTH: Number of bits required to differenciate between kernels. Should be log2(NUM_CORES).
- XACT_GEN_ORDER_PATH: Path to generate the simulation report.
- MEM_TRACE_BASE_PATH: Base address for the memory traces.
- BENCHMARK_NAME: Name of the benchmark to run.
- INPUT_TRC_FORMAT: The infrastructure supports two trace formats. Select the desired one here.
- ADDR_OFFSET_LENGTH: Number of bits to mask from address LSB
- MANIPULATE_ADDR_WITH_TRACE_ID: Kernel ID is appeneded to the address MSB if defined.
- OUT_OF_ORDER_STAGES: Size of the stream buffer, defined for all kernels.
- WRITE: Character in the trace file that indicates a write request.
- READ: Character in the trace file that indicates a read request.
- AXI_ID_WIDTH: Width of the AXI ID. Must match the memory controller user interface.
- AXI_ADDR_WIDTH: Width of the AXI address. Must match the memory controller user interface.
- AXI_DATA_WIDTH: Width of the AXI data bus. Must match the memory controller user interface.
- WSTRB_WIDTH: Width of the write strobe signal. Calculated automatically based on the value of AXI_DATA_WIDTH
- AXI_BURST_LENGTH: Length of the AXI burst.
If you have any questions regarding this work, please contact the corresponding author of the paper, Ali Abbasi. Their email address is provided in the published manuscript linked below.
This repository accompanies the research paper:
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM
Ali Abbasi, Danesh Germchi, Amin Katani, Mohamed Hassan, and Rodolfo Pellizzoni. 2025.
🔗 ACM Digital Library: https://dl.acm.org/doi/10.1145/3772724
📊 Slides presented at the International Conference on Field-Programmable Technology (FPT2025): View Here
If you use OpenDRAM in your work, please cite us:
@article{10.1145/3772724,
author = {Abbasi, Ali and Germchi, Danesh and Katani, Amin and Hassan, Mohamed and Pellizzoni, Rodolfo},
title = {OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM},
year = {2025},
issue_date = {December 2025},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {18},
number = {4},
issn = {1936-7406},
url = {https://doi.org/10.1145/3772724},
doi = {10.1145/3772724},
journal = {ACM Trans. Reconfigurable Technol. Syst.},
month = dec,
articleno = {56},
numpages = {27},
keywords = {DRAM, Memory Controller, High-performance Memory, FPGA, Open-source}
}
This HDL design is licensed under the SolderPad Hardware License, Version 0.51. See the LICENSE.md file for details.