feat(pathgraph): add traverse_registers option to TimingGraph#5
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SDF models a register's clock-to-output arc as an IOPATH only, so a pure delay graph dead-ends at every flop data pin. With traverse_registers=True, each SETUP/SETUPHOLD timing check adds a data-to-clock edge carrying the check's setup time, modelling the forward cost of crossing the register boundary (data stable setup-before-clock, then propagation continues through the clock-to-output IOPATH). HOLD checks add no edge: hold is a minimum-arrival constraint with typically negative values that must not enter path delay sums.
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SDF models a register's clock-to-output arc as an IOPATH only, so a pure delay graph dead-ends at every flop data pin. With traverse_registers=True, each SETUP/SETUPHOLD timing check adds a data-to-clock edge carrying the check's setup time, modelling the forward cost of crossing the register boundary (data stable setup-before-clock, then propagation continues through the clock-to-output IOPATH). HOLD checks add no edge: hold is a minimum-arrival constraint with typically negative values that must not enter path delay sums.