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  1. 64-bit-SystemVerilog-Calculator-Design-Verification 64-bit-SystemVerilog-Calculator-Design-Verification Public

    64-bit FSM-based RTL calculator in SystemVerilog with memory-mapped I/O, dual sky130 SRAM banks, 32-bit ripple-carry adder, and layered UVM-style testbench achieving 99% functional coverage.

    SystemVerilog

  2. Python-Data-Analysis Python-Data-Analysis Public

    Data analysis project using NumPy for CSV processing and numerical operations, and Matplotlib for plotting CO₂ emission trends (1990–2014) from World Bank data. Python scripts demonstrating data lo…

    Python

  3. Tech-Onboarding Tech-Onboarding Public

    Forked from HackGT/tech-onboarding

    Tech Onboarding Project for familiarization with the HexLabs API.

    TypeScript

  4. UVM-Architecture-Example-GCD UVM-Architecture-Example-GCD Public

    End-to-end UVM verification architecture for an 8-bit GCD design. Includes driver/monitor/scoreboard infrastructure, randomized and directed sequences, multi-test regression flow, functional & togg…

    SystemVerilog

  5. dLLM-KV-Sparsity-Coding-Test dLLM-KV-Sparsity-Coding-Test Public

    Porting Sparse-dLLM (dynamic bidirectional KV cache eviction and delayed cache updates) to Fast-dLLM-v2 (1.5B & 7B); benchmarked on GSM8K and MATH at iso-accuracy.

    Python

  6. Website Website Public

    https://DennisHao1211.github.io/Website

    HTML