æSIP: μArch-aware ASIP–ISA Co-Design

æSIP is a hardware–software co-design framework for generating Application-Specific Instruction Set Processors (ASIPs). Given a set of workloads, it discovers a custom ISA and a pruned microarchitecture that minimize area / latency / power while remaining RV32IM-compatible.

The pipeline combines:

1. Program synthesis — discover rewrite rules over RV32IM
2. Equality saturation — explore equivalent programs via e-graphs (egglog)
3. ILP-based global extraction — pick instruction sets under area/latency trade-offs (Gurobi)
4. Don't-care hardware pruning — generate pruned ASIPs from μArch constraints
5. Ecosystem-level NRE optimization — share ASIPs across workloads via clustering

Evaluated on MiBench and Embench-IoT. Companion to the ISCA 2026 paper.

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Setup

The recommended path is the prebuilt Docker image — it bundles egglog, yosys, abc, OpenSTA, the RISC-V GNU toolchain, spike, verilator, and the esip conda environment.

Docker (recommended)

docker pull polasip/esip:rv32im

# Gurobi is required for ILP extraction. Mount your local install + license.
docker run -it --rm \
    -p 8888:8888 \
    --security-opt seccomp=unconfined \
    -v $(pwd):/workspace \
    -v $GUROBI_HOME:$GUROBI_HOME:ro \
    -e GUROBI_HOME=$GUROBI_HOME \
    -e GRB_LICENSE_FILE=$GUROBI_HOME/gurobi.lic \
    -e LD_LIBRARY_PATH=$GUROBI_HOME/lib \
    polasip/esip:rv32im \
    jupyter notebook --ip=0.0.0.0 --port=8888 --no-browser --allow-root

Note: the bundled gurobi_solver is built against Gurobi 12.0.x. If your version differs, rebuild from Extractor/src/ILP/gurobi/.

Build the image yourself

docker build -t aesip:local .

Local conda (no Docker)

You will also need the system tools listed in the Dockerfile (egglog, yosys, abc, OpenSTA, RISC-V GNU toolchain, spike, verilator) on your PATH.

conda env create -f environment.yml
conda activate esip
pip install -e .

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Running

Artifact evaluation notebook

The fastest way to reproduce paper results end-to-end:

jupyter notebook artifact_evaluation.ipynb

It reproduces the four main experiments (minimal instruction usage, area/power vs. PDAG, area–latency Pareto, ecosystem-level NRE).

Pipeline scripts

To run the co-design pipeline on individual programs or benchmark categories:

# Single program
./scripts_pipeline/run_pipeline.sh dijkstra_small_O3

# Multiple programs
./scripts_pipeline/run_pipeline.sh dijkstra_small_O3 basicmath_small_O3

# A whole benchmark category
./scripts_pipeline/run_pipeline.sh embench-iot
./scripts_pipeline/run_pipeline.sh automotive

# Clean intermediate .s files
./scripts_pipeline/run_pipeline.sh clean

Other entry points in scripts_pipeline/:

• run_multi_scale_variants.sh — sweep ASIP variants in parallel
• run_k_parallel.sh — ecosystem clustering across k values

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Repository layout

Path	Contents
frontend/	RV32IM assembly → e-graph frontend
Saturation/	Equality saturation rules and driver (egglog)
Extractor/	ILP-based global extraction (Gurobi)
backend/	ASIP RTL generation backend
program_synthesis/	Rewrite-rule synthesis from RV32IM
PdatScorrWrapper/	Don't-care hardware pruning (PDAT / SCORR)
pdk/, nre/	Standard-cell libraries and NRE estimation
aesip_sim_ibex/	Ibex-based RTL simulation harness
riscv_greenthumb/	Superoptimizer used by program synthesis
benchmark/, embench-iot/, mibench_script/	Workloads
artifact_evaluation.ipynb	Reproduces paper experiments

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Acknowledgments

æSIP is built on top of a number of open-source projects. Vendored code retains its original LICENSE; please consult the per-directory LICENSE / COPYING files for full terms.

Core dependencies (vendored in this repo):

• egglog — equality saturation engine (egglog/)
• GreenThumb — superoptimizer framework, RISC-V port under riscv_greenthumb/
• CVA6 — application-class RISC-V core (under PdatScorrWrapper/CoreSim/cores/cva6/)
• SERV — bit-serial RISC-V core (under PdatScorrWrapper/CoreSim/cores/serv/)
• Embench-IoT — embedded benchmark suite (embench-iot/)
• MiBench — embedded benchmark suite (mibench_script/)
• PULP common_cells and tech_cells_generic (vendored under CVA6)

Process design kits (under pdk/):

• SkyWater SKY130 — open-source 130 nm bulk-CMOS PDK; we use the high-density standard-cell library (sky130_fd_sc_hd__tt_025C_1v80.lib)
• EGFET PDK — electrolyte-gated FET standard-cell library for printed electronics, referred to as PPDK in this repo (PPDK_Standard_Library_1.0V_25C_TYP_X1.lib); see also Bleier et al., Printed Microprocessors (ISCA 2020)

External tools (installed by the Dockerfile):

• Yosys — logic synthesis
• Berkeley ABC — combinational synthesis & SCORR
• OpenSTA — static timing analysis
• CUDD — BDD library (OpenSTA dependency)
• synlig — SystemVerilog frontend for Yosys
• sv2v — SystemVerilog → Verilog
• RISC-V GNU toolchain — gcc + newlib
• Spike — RISC-V ISA simulator
• riscv-pk — proxy kernel
• Verilator — Verilog/SystemVerilog simulator
• lowRISC Ibex — small RV32 core, used in aesip_sim_ibex/
• FuseSoC — IP package manager
• Gurobi — commercial ILP solver (license required)

If you use æSIP, please also cite the upstream tools where applicable.