Fix MC68020 and A1200 chip-bus timing

[LinuxJedi]

Summary

• replace the flat 68020 cycle scaling with Cache Case and Worst Case timings transcribed from MC68020UM section 8.2
• require the complete instruction stream, including extension and immediate words, to hit the instruction cache before selecting Cache Case
• model the A1200 Alice data-return phase for chip RAM reads, cache fills, and custom-register reads while keeping writes posted
• keep the 68000/68010, 68030/68040, and 68060 timing paths unchanged
• document the timing model, limitations, and benchmark calibration

Benchmark results

Classic SysInfo 4.4 on the A1200 profile:

Measurement	Before corrections	After
CPU speed vs A1200	1.61x	1.10x
Chip speed vs A600	5.52x	3.55x

xSysInfo improves from 1.34x to 1.19x A1200. Its detected CPU clock is 13.76 MHz, so no workload-specific multiplier was added to chase the remaining difference.

Verification

• cargo test --locked (1,754 passed, 5 ignored)
• cargo test --manifest-path crates/m68k/Cargo.toml --lib --locked (93 passed)
• cargo clippy --all-targets --all-features --locked -- -D warnings
• cargo fmt --check
• git diff --check
• cargo build --release --locked
• deterministic SysInfo, xSysInfo, and A1200 timing-test ADF runs

The optional broad m68k integration target expects Musashi fixture binaries that are not present in this checkout; the applicable self-contained library suite passes.

[Copilot]

Pull request overview

This PR refines Copperline’s MC68020 + A1200 (AGA/Alice) timing model to better match real hardware by switching from a flat cycle-scaling approximation to datasheet/manual-derived timing tables and by modeling the A1200 chip-bus read data-return phase.

Changes:

• Replaced the prior “scaled-from-68000” 68020 timing approximation with MC68020UM section 8.2 integer timing tables (cache-case vs worst-case selection).
• Added per-instruction “all instruction-stream fetches hit” tracking so 68020 cache-case timing is only selected when opcode + extension + immediate words are resident.
• Updated A1200/Alice chip-bus timing to include an extra data-return phase for reads (chip RAM, cache fills, custom-register reads) while keeping writes posted, and documented the updated model.

Reviewed changes

Copilot reviewed 12 out of 12 changed files in this pull request and generated no comments.

Show a summary per file

File	Description
src/cpu.rs	Tracks per-instruction instruction-cache residency across opcode/extension/immediate fetches; adds targeted tests.
src/bus.rs	Adjusts A1200 (AGA/Alice) chip-bus timing to bill a read data-return phase; updates custom read behavior accordingly.
src/bus/tests.rs	Updates/renames AGA 68020 bus timing test expectations for read-vs-write behavior and fetch latch behavior.
README.md	Notes that 68020 integer timing is now selected from MC68020UM per-instruction totals.
docs/internals/timing.md	Documents the A1200 Alice data-return phase and the posted-write vs read-wait asymmetry.
docs/internals/cpu.md	Replaces the old 68020+ scaling narrative with the new MC68020UM table-driven timing model and its limitations.
crates/m68k/src/core/timing_060.rs	Extends finalize-cycle dispatch to route 68020/68EC020 through the new 68020 timing model.
crates/m68k/src/core/timing_020.rs	New module implementing MC68020UM section 8.2 integer timing tables plus unit tests.
crates/m68k/src/core/mod.rs	Exposes the new timing_020 module.
crates/m68k/src/core/memory.rs	Extends AddressBus with per-instruction fetch tracking hooks used by 68020 timing selection.
crates/m68k/src/core/execute.rs	Resets per-instruction fetch tracking each instruction and selects 68020 cache-case only when the full stream hit.
crates/m68k/src/core/cpu.rs	Adds per-instruction exception vector tracking to support exception timing selection in the 68020 model; updates comments and default init.

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