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1. axi-dma-cora-z7-07s axi-dma-cora-z7-07s Public

   A practical implementation of AXI DMA on Zynq-7000 (Cora Z7) using High-Performance (HP) Slave port. Includes a guide on polling mode configuration, interrupt mode configuration, and scatter-gather…

2. hdl-ci-cd-templates hdl-ci-cd-templates Public

   List of CI/CD templates for HDL developers built using GitHub Actions

3. vhdl-fir-library vhdl-fir-library Public

   A complete FIR filter design suite: VHDL hardware implementation

   Tcl

4. py-filter-designer py-filter-designer Public

   This repository contains a simple filter designer (built-with & hosted on streamlit)

   Python