Computer Architecture Project

A Python implementation of a simplified MIPS CPU datapath. The project combines a MIPS assembler, control unit, ALU, register file, memory module, and program-counter update logic to simulate the execution of instructions from input.txt.

This is a computer architecture course project. It focuses on instruction encoding and datapath/control-flow behavior rather than being a production-grade emulator.

Features

• MIPS assembly input loaded from input.txt
• Instruction encoding through Assembler.py
• Single-cycle-style execution loop in main.py
• Control signal generation through CU.py
• 32-register simulated register file
• ALU support for arithmetic, logical, shift, and set-less-than operations
• Program counter updates for sequential execution, branches, jumps, jr, and jal
• Memory read/write module with byte, half-word, and word access modes
• Sign/zero extension behavior for memory reads
• Experimental gate-level ALU implementation
• Includes ALU definition.pdf as a reference document

Supported Instructions

The assembler/control path covers the following MIPS instructions:

add  sub  addi
lw   sw   lh   lhu   sh   lb   lbu   sb
and  or   nor  andi  ori
sll  srl
beq  bne
slt  sltu slti
j    jr   jal

Project Structure

.
+-- main.py                 # Main CPU simulation loop
+-- Assembler.py            # MIPS instruction encoder
+-- CU.py                   # Control unit signal generation
+-- ALU.py                  # Main ALU implementation
+-- RegisterFile.py         # Simulated register file
+-- Memory.py               # PostgreSQL-backed data memory helper
+-- SignExtended.py         # Sign-extension helper class
+-- ALU-Gate level.py       # Experimental gate-level ALU code
+-- main_gate_leveler.py    # Incomplete/experimental gate-level runner
+-- input.txt               # Main sample program
+-- tested.txt              # Instruction examples
+-- savedinput.txt          # Additional saved input program
+-- ALU definition.pdf      # ALU reference document
+```

## Input Format

Instructions are written one per line in `input.txt`. Registers are written without `$`, operands are comma-separated, and immediates are decimal numbers.

Examples:

```text
add a0,a0,a0
addi a1,zero,1
sw t0,100,zero
lw t1,203,zero
beq t0,t1,1
bne t0,t1,-4
jal 80,0,0
jr ra,0,0

Load/store instructions use this simplified operand order:

instruction target_or_source_register,offset,base_register

Jump instructions still use the same three-operand parser shape, so unused operands are written as 0.

How It Works

1. Assembler.py reads input.txt and converts every instruction into a command/machine-code pair in FinalResults.
2. main.py starts the program counter at 0 and fetches the instruction at PC // 4.
3. RegisterFile.read(...) returns the two source register values.
4. CU.CU(...) generates control lines for ALU, memory, register write-back, branches, and jumps.
5. ALU.ALU(...) executes the selected arithmetic/logical operation.
6. Memory.Memory(...) handles reads and writes when memory control lines are active.
7. Write-back selects ALU output, memory output, or PC + 4 for jal.
8. update_PC(...) advances the PC or applies branch/jump behavior.

Requirements

• Python 3
• psycopg2 if running memory instructions through main.py
• Access to the PostgreSQL database expected by Memory.py

Install the database package with:

python3 -m pip install psycopg2-binary

How to Run

Edit input.txt, then run the CPU simulation:

python3 main.py

For a syntax-level check of the main modules:

python3 -m py_compile Assembler.py ALU.py RegisterFile.py CU.py SignExtended.py Memory.py main.py

Notes

• Memory.py uses PostgreSQL as backing storage for data memory.
• Database connection details are currently hard-coded in Memory.py; a safer version should move them into environment variables or a local config file.
• main_gate_leveler.py appears to be an unfinished experimental runner and is not the primary execution path.
• The repository includes generated .pyc / __pycache__ files, which are not needed for source-based development.
• The simulator prints internal execution traces such as PC, register reads, ALU output, and memory operations.
• Input parsing expects the exact simple format used in input.txt.

Possible Improvements

• Move database credentials out of source code
• Add a local in-memory or file-backed memory option
• Remove generated bytecode artifacts from version control
• Add automated tests for assembler, ALU, control unit, and memory access modes
• Add support for labels and symbolic branch/jump targets
• Improve error handling for invalid instructions and registers
• Finish or remove the experimental gate-level runner
• Add a structured execution report or final register/memory dump