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Raise implementation level of armv9.6 intrinsics to beta #437

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Raise implementation level of armv9.6 intrinsics to beta #437

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13 changes: 7 additions & 6 deletions main/acle.md
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Original file line number Diff line number Diff line change
Expand Up @@ -489,6 +489,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin
* Added [**Alpha**](#current-status-and-anticipated-changes) support
for Brain 16-bit floating-point vector multiplication intrinsics.
* Redesigned atomic store with hints intrinsics.
* Bumped armv9.6 intrinsics implementation to [**Beta**](#current-status-and-anticipated-changes)
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@mgabka mgabka May 27, 2026

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The Q1 2026 release already has happened, so this should go into a new section, however considering that we want to abandon quarterly releases, maybe we should have a section per calendar year? what do you think?


### References

Expand Down Expand Up @@ -2153,7 +2154,7 @@ are available.
#### Brain 16-bit floating-point vector multiplication support

This section is in
[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
[**Beta** state](#current-status-and-anticipated-changes) and might change or be
extended in the future.

`__ARM_FEATURE_SVE_BFSCALE` is defined to `1` if there is hardware
Expand Down Expand Up @@ -2410,7 +2411,7 @@ associated ACLE intrinsics are available. This implies that
##### Multiplication of modal 8-bit floating-point matrices

This section is in
[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
[**Beta** state](#current-status-and-anticipated-changes) and might change or be
extended in the future.

`__ARM_FEATURE_F8F16MM` is defined to `1` if there is hardware support
Expand Down Expand Up @@ -9582,7 +9583,7 @@ BFloat16 floating-point multiply vectors.
### SVE BFloat16 floating-point adjust exponent vectors instructions.

The specification for SVE BFloat16 floating-point adjust exponent vectors instructions is in
[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
[**Beta** state](#current-status-and-anticipated-changes) and might change or be
extended in the future.

#### BFSCALE
Expand Down Expand Up @@ -9965,7 +9966,7 @@ Lookup table read with 4-bit indices.
### SVE2 Multi-vector AES and 128-bit polynomial multiply long instructions

The specification for SVE2 Multi-vector AES and 128-bit polynomial multiply long instructions is in
[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
[**Beta** state](#current-status-and-anticipated-changes) and might change or be
extended in the future.

#### AESE, AESD, AESEMC, AESDIMC
Expand Down Expand Up @@ -13191,7 +13192,7 @@ Zero ZA vector groups
### SME2.2 instruction intrinsics

The specification for SME2.2 are in
[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
[**Beta** state](#current-status-and-anticipated-changes) and might change or be
extended in the future.

The intrinsics in this section are defined by the header file
Expand Down Expand Up @@ -13775,7 +13776,7 @@ While (resulting in predicate tuple)
### SVE2.2 and SME2.2 instruction intrinsics

The specification for SVE2.2 and SME2.2 are in
[**Alpha** state](#current-status-and-anticipated-changes) and might change or be
[**Beta** state](#current-status-and-anticipated-changes) and might change or be
extended in the future.

The functions in this section are defined by either the header file
Expand Down
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