diff --git a/riscv64/riscv64asm/arg.go b/riscv64/riscv64asm/arg.go
index 2b96b416..edc7a5ec 100644
--- a/riscv64/riscv64asm/arg.go
+++ b/riscv64/riscv64asm/arg.go
@@ -105,6 +105,7 @@ const (
 	arg_vtype_zimm10
 	arg_vtype_zimm11
 	arg_bimm12
+	arg_zimm6
 	arg_imm20
 	arg_jimm20
 	arg_shamt5
diff --git a/riscv64/riscv64asm/decode.go b/riscv64/riscv64asm/decode.go
index 390edfa9..72cb4e83 100644
--- a/riscv64/riscv64asm/decode.go
+++ b/riscv64/riscv64asm/decode.go
@@ -236,6 +236,11 @@ func decodeArg(aop argType, x uint32, index int) Arg {
 		imm := x << 12 >> 27
 		return Uimm{imm, true}
 
+	case arg_zimm6:
+		// 6-bit unsigned immediate from bit 26 (hi) and bits 19:15 (lo)
+		imm := (x >> 15) & 0x1f | (x >> 21) & 0x20
+		return Uimm{imm, true}
+
 	case arg_vtype_zimm10:
 		imm := x << 2 >> 22
 		return VType(imm)
diff --git a/riscv64/riscv64asm/objdumpext_test.go b/riscv64/riscv64asm/objdumpext_test.go
index acbd9256..73eaa434 100644
--- a/riscv64/riscv64asm/objdumpext_test.go
+++ b/riscv64/riscv64asm/objdumpext_test.go
@@ -291,7 +291,7 @@ func writeELF64(f *os.File, size int) error {
 	exts := "rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_" +
 		"zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zmmul1p0_" +
 		"zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_" +
-		"zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
+		"zvbb1p0_zvbc1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
 	b := buildRISCVAttributes(exts)
 	sect = elf.Section64{
 		Name:      uint32(len("\x00.text\x00")),
diff --git a/riscv64/riscv64asm/tables.go b/riscv64/riscv64asm/tables.go
index 1de060f1..e549374a 100644
--- a/riscv64/riscv64asm/tables.go
+++ b/riscv64/riscv64asm/tables.go
@@ -398,6 +398,8 @@ const (
 	VAESKF1_VI
 	VAESKF2_VI
 	VAESZ_VS
+	VANDN_VV
+	VANDN_VX
 	VAND_VI
 	VAND_VV
 	VAND_VX
@@ -405,8 +407,17 @@ const (
 	VASUBU_VX
 	VASUB_VV
 	VASUB_VX
+	VBREV8_V
+	VBREV_V
+	VCLMULH_VV
+	VCLMULH_VX
+	VCLMUL_VV
+	VCLMUL_VX
+	VCLZ_V
 	VCOMPRESS_VM
 	VCPOP_M
+	VCPOP_V
+	VCTZ_V
 	VDIVU_VV
 	VDIVU_VX
 	VDIV_VV
@@ -798,10 +809,16 @@ const (
 	VREMU_VX
 	VREM_VV
 	VREM_VX
+	VREV8_V
 	VRGATHEREI16_VV
 	VRGATHER_VI
 	VRGATHER_VV
 	VRGATHER_VX
+	VROL_VV
+	VROL_VX
+	VROR_VI
+	VROR_VV
+	VROR_VX
 	VRSUB_VI
 	VRSUB_VX
 	VS1R_V
@@ -1011,6 +1028,9 @@ const (
 	VWMUL_VX
 	VWREDSUMU_VS
 	VWREDSUM_VS
+	VWSLL_VI
+	VWSLL_VV
+	VWSLL_VX
 	VWSUBU_VV
 	VWSUBU_VX
 	VWSUBU_WV
@@ -1422,6 +1442,8 @@ var opstr = [...]string{
 	VAESKF1_VI:        "VAESKF1.VI",
 	VAESKF2_VI:        "VAESKF2.VI",
 	VAESZ_VS:          "VAESZ.VS",
+	VANDN_VV:          "VANDN.VV",
+	VANDN_VX:          "VANDN.VX",
 	VAND_VI:           "VAND.VI",
 	VAND_VV:           "VAND.VV",
 	VAND_VX:           "VAND.VX",
@@ -1429,8 +1451,17 @@ var opstr = [...]string{
 	VASUBU_VX:         "VASUBU.VX",
 	VASUB_VV:          "VASUB.VV",
 	VASUB_VX:          "VASUB.VX",
+	VBREV8_V:          "VBREV8.V",
+	VBREV_V:           "VBREV.V",
+	VCLMULH_VV:        "VCLMULH.VV",
+	VCLMULH_VX:        "VCLMULH.VX",
+	VCLMUL_VV:         "VCLMUL.VV",
+	VCLMUL_VX:         "VCLMUL.VX",
+	VCLZ_V:            "VCLZ.V",
 	VCOMPRESS_VM:      "VCOMPRESS.VM",
 	VCPOP_M:           "VCPOP.M",
+	VCPOP_V:           "VCPOP.V",
+	VCTZ_V:            "VCTZ.V",
 	VDIVU_VV:          "VDIVU.VV",
 	VDIVU_VX:          "VDIVU.VX",
 	VDIV_VV:           "VDIV.VV",
@@ -1822,10 +1853,16 @@ var opstr = [...]string{
 	VREMU_VX:          "VREMU.VX",
 	VREM_VV:           "VREM.VV",
 	VREM_VX:           "VREM.VX",
+	VREV8_V:           "VREV8.V",
 	VRGATHEREI16_VV:   "VRGATHEREI16.VV",
 	VRGATHER_VI:       "VRGATHER.VI",
 	VRGATHER_VV:       "VRGATHER.VV",
 	VRGATHER_VX:       "VRGATHER.VX",
+	VROL_VV:           "VROL.VV",
+	VROL_VX:           "VROL.VX",
+	VROR_VI:           "VROR.VI",
+	VROR_VV:           "VROR.VV",
+	VROR_VX:           "VROR.VX",
 	VRSUB_VI:          "VRSUB.VI",
 	VRSUB_VX:          "VRSUB.VX",
 	VS1R_V:            "VS1R.V",
@@ -2035,6 +2072,9 @@ var opstr = [...]string{
 	VWMUL_VX:          "VWMUL.VX",
 	VWREDSUMU_VS:      "VWREDSUMU.VS",
 	VWREDSUM_VS:       "VWREDSUM.VS",
+	VWSLL_VI:          "VWSLL.VI",
+	VWSLL_VV:          "VWSLL.VV",
+	VWSLL_VX:          "VWSLL.VX",
 	VWSUBU_VV:         "VWSUBU.VV",
 	VWSUBU_VX:         "VWSUBU.VX",
 	VWSUBU_WV:         "VWSUBU.WV",
@@ -2836,6 +2876,10 @@ var instFormats = [...]instFormat{
 	{mask: 0xfe00707f, value: 0xaa002077, op: VAESKF2_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
 	// VAESZ.VS vs2, vd
 	{mask: 0xfe0ff07f, value: 0xa603a077, op: VAESZ_VS, args: argTypeList{arg_vs2, arg_vd}},
+	// VANDN.VV vm, vs2, vs1, vd
+	{mask: 0xfc00707f, value: 0x04000057, op: VANDN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VANDN.VX vm, vs2, rs1, vd
+	{mask: 0xfc00707f, value: 0x04004057, op: VANDN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
 	// VAND.VI vm, vs2, simm5, vd
 	{mask: 0xfc00707f, value: 0x24003057, op: VAND_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
 	// VAND.VV vm, vs2, vs1, vd
@@ -2850,10 +2894,28 @@ var instFormats = [...]instFormat{
 	{mask: 0xfc00707f, value: 0x2c002057, op: VASUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VASUB.VX vm, vs2, rs1, vd
 	{mask: 0xfc00707f, value: 0x2c006057, op: VASUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
+	// VBREV8.V vm, vs2, vd
+	{mask: 0xfc0ff07f, value: 0x48042057, op: VBREV8_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
+	// VBREV.V vm, vs2, vd
+	{mask: 0xfc0ff07f, value: 0x48052057, op: VBREV_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
+	// VCLMULH.VV vm, vs2, vs1, vd
+	{mask: 0xfc00707f, value: 0x34002057, op: VCLMULH_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VCLMULH.VX vm, vs2, rs1, vd
+	{mask: 0xfc00707f, value: 0x34006057, op: VCLMULH_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
+	// VCLMUL.VV vm, vs2, vs1, vd
+	{mask: 0xfc00707f, value: 0x30002057, op: VCLMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VCLMUL.VX vm, vs2, rs1, vd
+	{mask: 0xfc00707f, value: 0x30006057, op: VCLMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
+	// VCLZ.V vm, vs2, vd
+	{mask: 0xfc0ff07f, value: 0x48062057, op: VCLZ_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
 	// VCOMPRESS.VM vs2, vs1, vd
 	{mask: 0xfe00707f, value: 0x5e002057, op: VCOMPRESS_VM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
 	// VCPOP.M vm, vs2, rd
 	{mask: 0xfc0ff07f, value: 0x40082057, op: VCPOP_M, args: argTypeList{arg_vm, arg_vs2, arg_rd}},
+	// VCPOP.V vm, vs2, vd
+	{mask: 0xfc0ff07f, value: 0x48072057, op: VCPOP_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
+	// VCTZ.V vm, vs2, vd
+	{mask: 0xfc0ff07f, value: 0x4806a057, op: VCTZ_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
 	// VDIVU.VV vm, vs2, vs1, vd
 	{mask: 0xfc00707f, value: 0x80002057, op: VDIVU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VDIVU.VX vm, vs2, rs1, vd
@@ -3636,6 +3698,8 @@ var instFormats = [...]instFormat{
 	{mask: 0xfc00707f, value: 0x8c002057, op: VREM_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VREM.VX vm, vs2, rs1, vd
 	{mask: 0xfc00707f, value: 0x8c006057, op: VREM_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
+	// VREV8.V vm, vs2, vd
+	{mask: 0xfc0ff07f, value: 0x4804a057, op: VREV8_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
 	// VRGATHEREI16.VV vm, vs2, vs1, vd
 	{mask: 0xfc00707f, value: 0x38000057, op: VRGATHEREI16_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VRGATHER.VI vm, vs2, zimm5, vd
@@ -3644,6 +3708,16 @@ var instFormats = [...]instFormat{
 	{mask: 0xfc00707f, value: 0x30000057, op: VRGATHER_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VRGATHER.VX vm, vs2, rs1, vd
 	{mask: 0xfc00707f, value: 0x30004057, op: VRGATHER_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
+	// VROL.VV vm, vs2, vs1, vd
+	{mask: 0xfc00707f, value: 0x54000057, op: VROL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VROL.VX vm, vs2, rs1, vd
+	{mask: 0xfc00707f, value: 0x54004057, op: VROL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
+	// VROR.VI vm, vs2, zimm6, vd
+	{mask: 0xf800707f, value: 0x50003057, op: VROR_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm6, arg_vd}},
+	// VROR.VV vm, vs2, vs1, vd
+	{mask: 0xfc00707f, value: 0x50000057, op: VROR_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VROR.VX vm, vs2, rs1, vd
+	{mask: 0xfc00707f, value: 0x50004057, op: VROR_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
 	// VRSUB.VI vm, vs2, simm5, vd
 	{mask: 0xfc00707f, value: 0x0c003057, op: VRSUB_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
 	// VRSUB.VX vm, vs2, rs1, vd
@@ -4062,6 +4136,12 @@ var instFormats = [...]instFormat{
 	{mask: 0xfc00707f, value: 0xc0000057, op: VWREDSUMU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VWREDSUM.VS vm, vs2, vs1, vd
 	{mask: 0xfc00707f, value: 0xc4000057, op: VWREDSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VWSLL.VI vm, vs2, zimm5, vd
+	{mask: 0xfc00707f, value: 0xd4003057, op: VWSLL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
+	// VWSLL.VV vm, vs2, vs1, vd
+	{mask: 0xfc00707f, value: 0xd4000057, op: VWSLL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
+	// VWSLL.VX vm, vs2, rs1, vd
+	{mask: 0xfc00707f, value: 0xd4004057, op: VWSLL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
 	// VWSUBU.VV vm, vs2, vs1, vd
 	{mask: 0xfc00707f, value: 0xc8002057, op: VWSUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
 	// VWSUBU.VX vm, vs2, rs1, vd
diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt
index db1fc8f4..9b40c587 100644
--- a/riscv64/riscv64asm/testdata/gnucases.txt
+++ b/riscv64/riscv64asm/testdata/gnucases.txt
@@ -1781,6 +1781,50 @@ d730209e|	vmv1r.v v1,v2
 57b2819e|	vmv4r.v v4,v8
 57b0839e|	vmv8r.v v0,v8
 
+# 33.2.1. Zvbb - Vector Basic Bit-manipulation
+d7812006|	vandn.vv v3,v2,v1
+d7812004|	vandn.vv v3,v2,v1,v0.t
+d7412506|	vandn.vx v3,v2,x10
+d7412504|	vandn.vx v3,v2,x10,v0.t
+d721254a|	vbrev.v v3,v2
+d7212548|	vbrev.v v3,v2,v0.t
+d721244a|	vbrev8.v v3,v2
+d7212448|	vbrev8.v v3,v2,v0.t
+d7a1244a|	vrev8.v v3,v2
+d7a12448|	vrev8.v v3,v2,v0.t
+d721264a|	vclz.v v3,v2
+d7212648|	vclz.v v3,v2,v0.t
+d7a1264a|	vctz.v v3,v2
+d7a12648|	vctz.v v3,v2,v0.t
+d721274a|	vcpop.v v3,v2
+d7212748|	vcpop.v v3,v2,v0.t
+d78120d6|	vwsll.vv v3,v2,v1
+d78120d4|	vwsll.vv v3,v2,v1,v0.t
+d74125d6|	vwsll.vx v3,v2,x10
+d74125d4|	vwsll.vx v3,v2,x10,v0.t
+d7b127d6|	vwsll.vi v3,v2,15
+d7b127d4|	vwsll.vi v3,v2,15,v0.t
+d7812056|	vrol.vv v3,v2,v1
+d7812054|	vrol.vv v3,v2,v1,v0.t
+d7412556|	vrol.vx v3,v2,x10
+d7412554|	vrol.vx v3,v2,x10,v0.t
+d7b12752|	vror.vi v3,v2,15
+d7b12750|	vror.vi v3,v2,15,v0.t
+d7812052|	vror.vv v3,v2,v1
+d7812050|	vror.vv v3,v2,v1,v0.t
+d7412552|	vror.vx v3,v2,x10
+d7412550|	vror.vx v3,v2,x10,v0.t
+
+# 33.2.2. Zvbc - Vector Carryless Multiplication
+d7a12032|	vclmul.vv v3,v2,v1
+d7a12030|	vclmul.vv v3,v2,v1,v0.t
+d7612532|	vclmul.vx v3,v2,x10
+d7612530|	vclmul.vx v3,v2,x10,v0.t
+d7a12036|	vclmulh.vv v3,v2,v1
+d7a12034|	vclmulh.vv v3,v2,v1,v0.t
+d7612536|	vclmulh.vx v3,v2,x10
+d7612534|	vclmulh.vx v3,v2,x10,v0.t
+
 # 32.2.4: Vector GCM/GMAC
 f7a120b2|	vghsh.vv v3,v2,v1
 f7a128a2|	vgmul.vv v3,v2
diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt
index a361d65e..50ed4b5e 100644
--- a/riscv64/riscv64asm/testdata/plan9cases.txt
+++ b/riscv64/riscv64asm/testdata/plan9cases.txt
@@ -1737,6 +1737,50 @@ d730209e|	VMV1RV V2, V1
 
 # Zvk: Vector Cryptography Extensions
 
+# 33.2.1. Zvbb - Vector Basic Bit-manipulation
+d7812006|	VANDNVV V1, V2, V3
+d7812004|	VANDNVV V1, V2, V0, V3
+d7412506|	VANDNVX X10, V2, V3
+d7412504|	VANDNVX X10, V2, V0, V3
+d721254a|	VBREVV V2, V3
+d7212548|	VBREVV V2, V0, V3
+d721244a|	VBREV8V V2, V3
+d7212448|	VBREV8V V2, V0, V3
+d7a1244a|	VREV8V V2, V3
+d7a12448|	VREV8V V2, V0, V3
+d721264a|	VCLZV V2, V3
+d7212648|	VCLZV V2, V0, V3
+d7a1264a|	VCTZV V2, V3
+d7a12648|	VCTZV V2, V0, V3
+d721274a|	VCPOPV V2, V3
+d7212748|	VCPOPV V2, V0, V3
+d78120d6|	VWSLLVV V1, V2, V3
+d78120d4|	VWSLLVV V1, V2, V0, V3
+d74125d6|	VWSLLVX X10, V2, V3
+d74125d4|	VWSLLVX X10, V2, V0, V3
+d7b127d6|	VWSLLVI $15, V2, V3
+d7b127d4|	VWSLLVI $15, V2, V0, V3
+d7812056|	VROLVV V1, V2, V3
+d7812054|	VROLVV V1, V2, V0, V3
+d7412556|	VROLVX X10, V2, V3
+d7412554|	VROLVX X10, V2, V0, V3
+d7b12752|	VRORVI $15, V2, V3
+d7b12750|	VRORVI $15, V2, V0, V3
+d7812052|	VRORVV V1, V2, V3
+d7812050|	VRORVV V1, V2, V0, V3
+d7412552|	VRORVX X10, V2, V3
+d7412550|	VRORVX X10, V2, V0, V3
+
+# 33.2.2. Zvbc - Vector Carryless Multiplication
+d7a12032|	VCLMULVV V1, V2, V3
+d7a12030|	VCLMULVV V1, V2, V0, V3
+d7612532|	VCLMULVX X10, V2, V3
+d7612530|	VCLMULVX X10, V2, V0, V3
+d7a12036|	VCLMULHVV V1, V2, V3
+d7a12034|	VCLMULHVV V1, V2, V0, V3
+d7612536|	VCLMULHVX X10, V2, V3
+d7612534|	VCLMULHVX X10, V2, V0, V3
+
 # Zvkg - Vector GCM/GMAC
 f7a120b2|	VGHSHVV V1, V2, V3
 f7a128a2|	VGMULVV V2, V3
diff --git a/riscv64/riscv64spec/spec.go b/riscv64/riscv64spec/spec.go
index 7c01a444..ce85cf20 100644
--- a/riscv64/riscv64spec/spec.go
+++ b/riscv64/riscv64spec/spec.go
@@ -47,6 +47,8 @@ var extensions = []string{
 	"rv_zvknha",
 	"rv_zvksed",
 	"rv_zvksh",
+	"rv_zvbb",
+	"rv_zvbc",
 	"rv64_a",
 	"rv64_c",
 	"rv64_d",
@@ -332,9 +334,12 @@ func inferFormats(argTypeList []string, op string) string {
 	case op == "VSLL_VI" || op == "VSRL_VI" || op == "VSRA_VI" || op == "VNSRL_WI" ||
 		op == "VNSRA_WI" || op == "VSSRL_VI" || op == "VSSRA_VI" || op == "VNCLIPU_WI" ||
 		op == "VNCLIP_WI" || op == "VSLIDEUP_VI" || op == "VSLIDEDOWN_VI" ||
-		op == "VRGATHER_VI":
+		op == "VRGATHER_VI" || op == "VWSLL_VI":
 		return "arg_vm, arg_vs2, arg_zimm5, arg_vd"
 
+	case op == "VROR_VI":
+		return "arg_vm, arg_vs2, arg_zimm6, arg_vd"
+
 	default:
 		var instStr []string
 		for _, arg := range argTypeList {