From 11e6c2d1c6b6e0bca989bc9fe8ecdae5151a95cf Mon Sep 17 00:00:00 2001 From: cuitiankai10342768 Date: Wed, 15 Jul 2026 17:09:49 +0800 Subject: [PATCH] riscv64: add tests for zicntr --- riscv64/riscv64asm/testdata/gnucases.txt | 5 +++++ riscv64/riscv64asm/testdata/plan9cases.txt | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt index db1fc8f4..997591a8 100644 --- a/riscv64/riscv64asm/testdata/gnucases.txt +++ b/riscv64/riscv64asm/testdata/gnucases.txt @@ -410,6 +410,11 @@ a260| ld x1,8(x2) 8624| fld f9,64(x2) 3eb0| fsd f15,32(x2) +# 8.1. "Zicntr" Extension for Base Counters and Timers +f32200c0| rdcycle x5 +f32210c0| rdtime x5 +f32220c0| rdinstret x5 + # 10.1: "Zihintpause" Extension for Pause Hint, Version 1.0.0 0f000001| pause diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt index a361d65e..ec90b79b 100644 --- a/riscv64/riscv64asm/testdata/plan9cases.txt +++ b/riscv64/riscv64asm/testdata/plan9cases.txt @@ -363,6 +363,11 @@ b35cbd49| BEXT X27, X26, X25 b3115228| BSET X5, X4, X3 1393f32b| BSETI $63, X7, X6 +# 8.1. "Zicntr" Extension for Base Counters and Timers +f32200c0| RDCYCLE X5 +f32210c0| RDTIME X5 +f32220c0| RDINSTRET X5 + # 10.1: "Zihintpause" Extension for Pause Hint, Version 1.0.0 0f000001| PAUSE