diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt
index db1fc8f4..11cf64ff 100644
--- a/riscv64/riscv64asm/testdata/gnucases.txt
+++ b/riscv64/riscv64asm/testdata/gnucases.txt
@@ -362,14 +362,6 @@ bb115260|	rolw x3,x4,x5
 bb56f760|	rorw x13,x14,x15
 13d87828|	orc.b x16,x17
 13d9896b|	rev8 x18,x19
-339a6a49|	bclr x20,x21,x22
-931bfc48|	bclri x23,x24,0xf
-b35cbd49|	bext x25,x26,x27
-13de8e48|	bexti x28,x29,0x8
-339f0f68|	binv x30,x31,x0
-9310016a|	binvi x1,x2,0x20
-b3115228|	bset x3,x4,x5
-1393f32b|	bseti x6,x7,0x3f
 4000|	addi x8,x2,4
 2041|	lw x8,64(x10)
 94d0|	sw x13,32(x9)
@@ -437,6 +429,16 @@ b313530a|	clmul	x7,x6,x5
 b333530a|	clmulh	x7,x6,x5
 b323530a|	clmulr	x7,x6,x5
 
+# 28.4.4. Zbs: Single-bit instructions
+339a6a49|	bclr x20,x21,x22
+931bfc48|	bclri x23,x24,0xf
+b35cbd49|	bext x25,x26,x27
+13de8e48|	bexti x28,x29,0x8
+339f0f68|	binv x30,x31,x0
+9310016a|	binvi x1,x2,0x20
+b3115228|	bset x3,x4,x5
+1393f32b|	bseti x6,x7,0x3f
+
 # "V" Standard Extension for Vector Operations, Version 1.0
 
 # 31.6: Configuration Setting Instructions
diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt
index a361d65e..0f689750 100644
--- a/riscv64/riscv64asm/testdata/plan9cases.txt
+++ b/riscv64/riscv64asm/testdata/plan9cases.txt
@@ -354,14 +354,6 @@ bb115260|	ROLW X5, X4, X3
 bb56f760|	RORW X15, X14, X13
 13d87828|	ORCB X17, X16
 13d9896b|	REV8 X19, X18
-339a6a49|	BCLR X22, X21, X20
-931bfc48|	BCLRI $15, X24, X23
-b35cbd49|	BEXT X27, X26, X25
-13de8e48|	BEXTI $8, X29, X28
-339f0f68|	BINV X0, X31, X30
-9310016a|	BINVI $32, X2, X1
-b3115228|	BSET X5, X4, X3
-1393f32b|	BSETI $63, X7, X6
 
 # 10.1: "Zihintpause" Extension for Pause Hint, Version 1.0.0
 0f000001|	PAUSE
@@ -390,6 +382,16 @@ b313530a|	CLMUL	X5, X6, X7
 b333530a|	CLMULH	X5, X6, X7
 b323530a|	CLMULR	X5, X6, X7
 
+# 28.4.4. Zbs: Single-bit instructions
+339a6a49|	BCLR X22, X21, X20
+931bfc48|	BCLRI $15, X24, X23
+b35cbd49|	BEXT X27, X26, X25
+13de8e48|	BEXTI $8, X29, X28
+339f0f68|	BINV X0, X31, X30
+9310016a|	BINVI $32, X2, X1
+b3115228|	BSET X5, X4, X3
+1393f32b|	BSETI $63, X7, X6
+
 # "V" Standard Extension for Vector Operations, Version 1.0
 
 # 31.6: Configuration Setting Instructions