Design did not meet timing

[dismilk]

Hello,yueniu,
I encountered a error ' design did not meet timing - Design failed to meet timing', and the failed timing checks (paths) is {zcu102_i/conv_fpga_1/inst/grp_conv_ichnl_fu_1422/dataflow_in_loop_U0/conv_ochnl_U0/grp_conv_buf_write_fu_2567/ap_enable_reg_pp0_iter1_reg/C --> zcu102_i/conv_fpga_1/inst/grp_conv_ichnl_fu_1422/dataflow_in_loop_U0/conv_ochnl_U0/out_buf_13_U/a0_conv_ochnl_out_bug5b_ram_U/ram_reg_bram_0/ENARDEN}
I set conv_fpga and fc_fpga as 300MHz,data motion network also 300MHz.
How could I solve this problem?
Thank you and look for your reply!

[Wanghaoshu]

@dismilk
Hello,dismilk
I have the same question you have. I would like to know if you have solved it