The pipelines thread srj.defaultObstacleMargin into the HD solvers (obstacleMargin: cms.srj.defaultObstacleMargin ?? 0.15), but the produced clearance does not track it.
Repro
Route bugreport01 at increasing defaultObstacleMargin and measure the smallest different-net trace-edge-to-edge gap in the output (via minimumDistanceBetweenSegments minus half-widths):
AutoroutingPipelineSolver4 (the default CapacityMeshAutorouter picks):
obstacleMargin=0 -> min gap 0.1135 mm
obstacleMargin=0.1 -> min gap 0.1257 mm
obstacleMargin=0.2 -> min gap 0.0992 mm <- smaller than margin=0
obstacleMargin=0.3 -> min gap 0.1139 mm
AutoroutingPipelineSolver2 (): flat 0.1130 mm for every margin 0…0.3.
Expected: the min produced gap grows monotonically with obstacleMargin.
Actual: it is noise around ~0.11mm (Pipeline4) or perfectly flat (Pipeline2).
Impact
There is no way to widen the router's clearance target. On a dense 2-layer board
(1.27mm module edge + a USB-C pad row) the router squeezes different-net copper to
~0.005-0.076mm - below JLC's 0.0889mm (3.5mil) floor - and raising
traceClearance/defaultObstacleMargin does nothing to fix it. Combined with #1507
(crossing penalty) this makes dense boards unroutable to a fab-clean DRC.
Repro test attached on request (routes the fixture at several margins and prints the min gap).
The pipelines thread
srj.defaultObstacleMargininto the HD solvers (obstacleMargin: cms.srj.defaultObstacleMargin ?? 0.15), but the produced clearance does not track it.Repro
Route
bugreport01at increasingdefaultObstacleMarginand measure the smallest different-net trace-edge-to-edge gap in the output (viaminimumDistanceBetweenSegmentsminus half-widths):AutoroutingPipelineSolver4 (the default
CapacityMeshAutorouterpicks):AutoroutingPipelineSolver2 (): flat 0.1130 mm for every margin 0…0.3.
Expected: the min produced gap grows monotonically with
obstacleMargin.Actual: it is noise around ~0.11mm (Pipeline4) or perfectly flat (Pipeline2).
Impact
There is no way to widen the router's clearance target. On a dense 2-layer board
(1.27mm module edge + a USB-C pad row) the router squeezes different-net copper to
~0.005-0.076mm - below JLC's 0.0889mm (3.5mil) floor - and raising
traceClearance/defaultObstacleMargindoes nothing to fix it. Combined with #1507(crossing penalty) this makes dense boards unroutable to a fab-clean DRC.
Repro test attached on request (routes the fixture at several margins and prints the min gap).