From 3247582ca738555cab8b42c1153caec1b1dd4933 Mon Sep 17 00:00:00 2001
From: anil08607 <anilkumar90875199@gmail.com>
Date: Fri, 24 Jul 2026 23:28:48 +0530
Subject: [PATCH] bump: upgrade @tscircuit/footprinter to v0.0.387

---
 package.json                                  |   2 +-
 ...ader-and-passives-autorouting-srj.snap.svg |  37 +++++++++++-
 ...fp16-with-header-and-passives-pcb.snap.svg |   2 +-
 ...ulator-power-rail-autorouting-srj.snap.svg |  36 +++++++++++-
 ...ut-sot23-regulator-power-rail-pcb.snap.svg |   2 +-
 ...sor-to-i2c-header-autorouting-srj.snap.svg |  55 ++++++++++++++++--
 ...ut-soic8-sensor-to-i2c-header-pcb.snap.svg |   2 +-
 .../allow-off-board-propagation-pcb.snap.svg  |   2 +-
 .../__snapshots__/header-pcb.snap.svg         |   2 +-
 .../__snapshots__/jumper-pcb.snap.svg         |   2 +-
 .../jumper.test.tsxrows-pcb.snap.svg          |   2 +-
 ...t.tsx-chip-fallback-pinlabels-pcb.snap.svg |   2 +-
 ...st.tsx-chip-with-pcbpinlabels-pcb.snap.svg |   2 +-
 ...tsx-jumper-fallback-pinlabels-pcb.snap.svg |   2 +-
 ....tsx-jumper-with-pcbpinlabels-pcb.snap.svg |   2 +-
 ...-pinheader-fallback-pinlabels-pcb.snap.svg |   2 +-
 ...x-pinheader-with-pcbpinlabels-pcb.snap.svg |   2 +-
 ...er-pinCount-default-footprint-pcb.snap.svg |   2 +-
 ...er-show-silkscreen-pin-labels-pcb.snap.svg |   2 +-
 .../pinrows-270-ccw-rotation-pcb.snap.svg     |   2 +-
 .../pinrows-90-ccw-rotation-pcb.snap.svg      |   2 +-
 .../__snapshots__/pinrows-pcb.snap.svg        |   2 +-
 ...b-courtyard-rect-rotation-180-pcb.snap.svg |   2 +-
 ...b-courtyard-rect-rotation-270-pcb.snap.svg |   2 +-
 ...cb-courtyard-rect-rotation-45-pcb.snap.svg |   2 +-
 ...cb-courtyard-rect-rotation-90-pcb.snap.svg |   2 +-
 ...h-pinrow-footprint-silkscreen-pcb.snap.svg |   2 +-
 ...repro1-packing-imported-board-pcb.snap.svg |   2 +-
 ...ttom-layer-courtyard-rotation-pcb.snap.svg |   2 +-
 ...pour-and-rect-pad-plated-hole-pcb.snap.svg |   2 +-
 ...2-pinheader-double-row-pcb-3d-pcb.snap.svg |   2 +-
 ...eader-double-row-pcb-3d-simple-3d.snap.png | Bin 558328 -> 349684 bytes
 .../repro126-courtyard-rotation-pcb.snap.svg  |   2 +-
 .../repro23-trace-overlap-pcb.snap.svg        |   2 +-
 ...o29-externally-connected-pins-pcb.snap.svg |   2 +-
 .../repro48-555-timer-pcb.snap.svg            |   2 +-
 .../repro49-same-net-not-combine-pcb.snap.svg |   2 +-
 ...en-rotation-counter-clockwise-pcb.snap.svg |   2 +-
 ...8-pcb-autolayout-out-of-board-pcb.snap.svg |   2 +-
 ...autolayout-components-overlap-pcb.snap.svg |   2 +-
 ...repro64-packing-outside-board-pcb.snap.svg |   2 +-
 ...sitive-accidental-contact-drc-pcb.snap.svg |   2 +-
 ...screen-rotation-counter-clockwise.test.tsx |   8 +--
 .../subcircuit-expose-nets-prop-pcb.snap.svg  |   2 +-
 ...it-exposed-nets-copper-pour01-pcb.snap.svg |   2 +-
 ...it-exposed-nets-copper-pour02-pcb.snap.svg |   2 +-
 46 files changed, 162 insertions(+), 56 deletions(-)

diff --git a/package.json b/package.json
index 11ce95fed..837e43dc8 100644
--- a/package.json
+++ b/package.json
@@ -41,7 +41,7 @@
     "@tscircuit/common": "^0.0.20",
     "@tscircuit/copper-pour-solver": "0.0.39",
     "@tscircuit/create-fdm-enclosure": "0.0.3",
-    "@tscircuit/footprinter": "^0.0.386",
+    "@tscircuit/footprinter": "^0.0.387",
     "@tscircuit/image-utils": "^0.0.8",
     "@tscircuit/infer-cable-insertion-point": "^0.0.2",
     "@tscircuit/infgrid-ijump-astar": "^0.0.35",
diff --git a/tests/breakout/__snapshots__/breakout-qfp16-with-header-and-passives-autorouting-srj.snap.svg b/tests/breakout/__snapshots__/breakout-qfp16-with-header-and-passives-autorouting-srj.snap.svg
index 9203145c2..610130d1f 100644
--- a/tests/breakout/__snapshots__/breakout-qfp16-with-header-and-passives-autorouting-srj.snap.svg
+++ b/tests/breakout/__snapshots__/breakout-qfp16-with-header-and-passives-autorouting-srj.snap.svg
@@ -16,12 +16,19 @@
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diff --git a/tests/breakout/__snapshots__/breakout-sot23-regulator-power-rail-pcb.snap.svg b/tests/breakout/__snapshots__/breakout-sot23-regulator-power-rail-pcb.snap.svg
index 888369b04..4a3b5417c 100644
--- a/tests/breakout/__snapshots__/breakout-sot23-regulator-power-rail-pcb.snap.svg
+++ b/tests/breakout/__snapshots__/breakout-sot23-regulator-power-rail-pcb.snap.svg
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diff --git a/tests/breakout/__snapshots__/fanout-soic8-sensor-to-i2c-header-autorouting-srj.snap.svg b/tests/breakout/__snapshots__/fanout-soic8-sensor-to-i2c-header-autorouting-srj.snap.svg
index e0a65360f..1961e715f 100644
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+++ b/tests/breakout/__snapshots__/fanout-soic8-sensor-to-i2c-header-autorouting-srj.snap.svg
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diff --git a/tests/components/normal-components/__snapshots__/allow-off-board-propagation-pcb.snap.svg b/tests/components/normal-components/__snapshots__/allow-off-board-propagation-pcb.snap.svg
index cb1d8033f..7cef7c164 100644
--- a/tests/components/normal-components/__snapshots__/allow-off-board-propagation-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/allow-off-board-propagation-pcb.snap.svg
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\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/header-pcb.snap.svg b/tests/components/normal-components/__snapshots__/header-pcb.snap.svg
index 68939339b..e9885f40c 100644
--- a/tests/components/normal-components/__snapshots__/header-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/header-pcb.snap.svg
@@ -1 +1 @@
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\ No newline at end of file
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\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/jumper-pcb.snap.svg b/tests/components/normal-components/__snapshots__/jumper-pcb.snap.svg
index 68da76343..2ea0ef456 100644
--- a/tests/components/normal-components/__snapshots__/jumper-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/jumper-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.771"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><text x="0" y="0" dx="0" dy="0" fill="#5da9e9" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(-1,0,0,1,209.5,443.75)" class="pcb-silkscreen-text pcb-silkscreen-bottom" data-pcb-silkscreen-text-id="pcb_component_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="bottom">ONE</text><text x="0" y="0" dx="0" dy="0" fill="#5da9e9" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(-1,0,0,1,336.5,443.75)" class="pcb-silkscreen-text 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stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="172" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="209.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="336.5" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="336.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="463.5" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="463.5" cy="300" r="25" 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diff --git a/tests/components/normal-components/__snapshots__/jumper.test.tsxrows-pcb.snap.svg b/tests/components/normal-components/__snapshots__/jumper.test.tsxrows-pcb.snap.svg
index a8b453c0b..2664f30a4 100644
--- a/tests/components/normal-components/__snapshots__/jumper.test.tsxrows-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/jumper.test.tsxrows-pcb.snap.svg
@@ -1 +1 @@
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r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="463.5" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.pin4"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="463.5" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="463.5" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.pin5"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="336.5" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="336.5" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.pin6"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="336.5" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="336.5" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-fallback-pinlabels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-fallback-pinlabels-pcb.snap.svg
index dea3cc9fd..c5afb4505 100644
--- a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-fallback-pinlabels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-fallback-pinlabels-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.560"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">IN</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">OUT</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">U2</text><g><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25"/></g></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">IN</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">OUT</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">U2</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U2.IN"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U2.OUT"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U2.GND"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-with-pcbpinlabels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-with-pcbpinlabels-pcb.snap.svg
index 82ef2dc21..5e60c4919 100644
--- a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-with-pcbpinlabels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-chip-with-pcbpinlabels-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.560"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,209.5,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">V+</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,336.5,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">G</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,463.5,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">SIGNAL</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,590.5,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">ENABLE</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">U1</text><g><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="172" y="262.5" width="75" height="75"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="209.5" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="336.5" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="336.5" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="463.5" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="463.5" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="590.5" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="590.5" cy="300" r="25"/></g></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,209.5,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">V+</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,336.5,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">G</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,463.5,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">SIGNAL</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,590.5,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">ENABLE</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">U1</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U1.VCC"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="172" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="209.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U1.GND"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="336.5" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="336.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U1.SIG"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="463.5" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="463.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="U1.EN"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="590.5" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="590.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-fallback-pinlabels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-fallback-pinlabels-pcb.snap.svg
index 5b6c8831c..8ada76f44 100644
--- a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-fallback-pinlabels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-fallback-pinlabels-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.560"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,336.5,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">DATA</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,463.5,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">CLK</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">J2</text><g><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="299" y="262.5" width="75" height="75"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="336.5" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="463.5" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="463.5" cy="300" r="25"/></g></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,336.5,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">DATA</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,463.5,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">CLK</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.DATA"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="299" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="336.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.CLK"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="463.5" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="463.5" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-with-pcbpinlabels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-with-pcbpinlabels-pcb.snap.svg
index d400b2f77..bc3c2979b 100644
--- a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-with-pcbpinlabels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-jumper-with-pcbpinlabels-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.560"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">A_PCB</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">B_PCB</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">C_PCB</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">J1</text><g><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25"/></g></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A_PCB</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B_PCB</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C_PCB</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.A"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.B"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.C"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-fallback-pinlabels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-fallback-pinlabels-pcb.snap.svg
index 9d7810cc7..ece06acc2 100644
--- a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-fallback-pinlabels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-fallback-pinlabels-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.560"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">MOSI</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">MISO</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,243.75)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">SS</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">P2</text><g><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25"/></g><g><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25"/></g></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">MOSI</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">MISO</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">SS</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">P2</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="P2.MOSI"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="P2.MISO"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="P2.SS"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-with-pcbpinlabels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-with-pcbpinlabels-pcb.snap.svg
index 3424dc16f..5b71d2b76 100644
--- a/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-with-pcbpinlabels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pcb-pin-labels.test.tsx-pinheader-with-pcbpinlabels-pcb.snap.svg
@@ -1 +1 @@
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\ No newline at end of file
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\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pin-header-pinCount-default-footprint-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pin-header-pinCount-default-footprint-pcb.snap.svg
index 1ce509a60..725f0a020 100644
--- a/tests/components/normal-components/__snapshots__/pin-header-pinCount-default-footprint-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pin-header-pinCount-default-footprint-pcb.snap.svg
@@ -1 +1 @@
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\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="150" y="50" width="500" height="500" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 150 550 L 650 550 L 650 50 L 150 50 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="5" data-type="pcb_board" data-pcb-layer="board"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,273,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">pin1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">pin2</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="25" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,527,232.5)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">pin3</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="35" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,173)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.pin1"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="235.5" y="262.5" width="75" height="75" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="273" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.pin2"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="400" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="400" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.pin3"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="527" cy="300" r="37.5" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="527" cy="300" r="25" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pinheader-show-silkscreen-pin-labels-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pinheader-show-silkscreen-pin-labels-pcb.snap.svg
index c918f9312..39a956464 100644
--- a/tests/components/normal-components/__snapshots__/pinheader-show-silkscreen-pin-labels-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pinheader-show-silkscreen-pin-labels-pcb.snap.svg
@@ -1 +1 @@
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y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333334" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,152.80000000000007,403.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333334" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,220.53333333333336,403.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">SDA</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333334" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,288.26666666666677,403.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">SCL</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="18.666666666666668" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,186.6666666666667,365.6)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none">P1_auto_showSilkscreenPinLabels_true</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="18.666666666666668" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,613.3333333333334,365.6)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_1" stroke="none">P2_auto_showSilkscreenPinLabels_false</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="18.666666666666668" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,186.6666666666667,98.93333333333334)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_2" stroke="none">P3_auto_showSilkscreenPinLabels_default</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333334" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,511.73333333333335,136.66666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_3" stroke="none">VCC</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333334" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,579.4666666666667,136.66666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_3" stroke="none">GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="13.333333333333334" text-anchor="middle" dominant-baseline="central" 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diff --git a/tests/components/normal-components/__snapshots__/pinrows-270-ccw-rotation-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pinrows-270-ccw-rotation-pcb.snap.svg
index e56f03cd2..e32b4b16f 100644
--- a/tests/components/normal-components/__snapshots__/pinrows-270-ccw-rotation-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pinrows-270-ccw-rotation-pcb.snap.svg
@@ -1 +1 @@
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diff --git a/tests/components/normal-components/__snapshots__/pinrows-90-ccw-rotation-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pinrows-90-ccw-rotation-pcb.snap.svg
index eb8f9b365..4ca15fd40 100644
--- a/tests/components/normal-components/__snapshots__/pinrows-90-ccw-rotation-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pinrows-90-ccw-rotation-pcb.snap.svg
@@ -1 +1 @@
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\ No newline at end of file
diff --git a/tests/components/normal-components/__snapshots__/pinrows-pcb.snap.svg b/tests/components/normal-components/__snapshots__/pinrows-pcb.snap.svg
index fbf847664..c2a9865bc 100644
--- a/tests/components/normal-components/__snapshots__/pinrows-pcb.snap.svg
+++ b/tests/components/normal-components/__snapshots__/pinrows-pcb.snap.svg
@@ -1 +1 @@
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diff --git a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-180-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-180-pcb.snap.svg
index 6af3a1d07..2d44bd454 100644
--- a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-180-pcb.snap.svg
+++ b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-180-pcb.snap.svg
@@ -1 +1 @@
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diff --git a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-270-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-270-pcb.snap.svg
index c4103eb7f..e35991462 100644
--- a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-270-pcb.snap.svg
+++ b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-270-pcb.snap.svg
@@ -1 +1 @@
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\ No newline at end of file
diff --git a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-45-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-45-pcb.snap.svg
index 58d9ddb4f..e5351127a 100644
--- a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-45-pcb.snap.svg
+++ b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-45-pcb.snap.svg
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diff --git a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-90-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-90-pcb.snap.svg
index 0eacd90bc..a99013d57 100644
--- a/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-90-pcb.snap.svg
+++ b/tests/components/primitive-components/__snapshots__/pcb-courtyard-rect-rotation-90-pcb.snap.svg
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diff --git a/tests/examples/__snapshots__/example23-chip-pinlable-with-pinrow-footprint-silkscreen-pcb.snap.svg b/tests/examples/__snapshots__/example23-chip-pinlable-with-pinrow-footprint-silkscreen-pcb.snap.svg
index b4d678d15..e91b5dba8 100644
--- a/tests/examples/__snapshots__/example23-chip-pinlable-with-pinrow-footprint-silkscreen-pcb.snap.svg
+++ b/tests/examples/__snapshots__/example23-chip-pinlable-with-pinrow-footprint-silkscreen-pcb.snap.svg
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diff --git a/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg b/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg
index 5bd8a3d3a..c749c1678 100644
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+++ b/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg
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diff --git a/tests/repros/__snapshots__/repro104-chip-bottom-layer-courtyard-rotation-pcb.snap.svg b/tests/repros/__snapshots__/repro104-chip-bottom-layer-courtyard-rotation-pcb.snap.svg
index 1b51b4067..90178f925 100644
--- a/tests/repros/__snapshots__/repro104-chip-bottom-layer-courtyard-rotation-pcb.snap.svg
+++ b/tests/repros/__snapshots__/repro104-chip-bottom-layer-courtyard-rotation-pcb.snap.svg
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diff --git a/tests/repros/__snapshots__/repro111-board-copperpour-and-rect-pad-plated-hole-pcb.snap.svg b/tests/repros/__snapshots__/repro111-board-copperpour-and-rect-pad-plated-hole-pcb.snap.svg
index 0af89bd19..c996c441d 100644
--- a/tests/repros/__snapshots__/repro111-board-copperpour-and-rect-pad-plated-hole-pcb.snap.svg
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diff --git a/tests/repros/__snapshots__/repro112-pinheader-double-row-pcb-3d-pcb.snap.svg b/tests/repros/__snapshots__/repro112-pinheader-double-row-pcb-3d-pcb.snap.svg
index 81916e453..8e6438b0a 100644
--- a/tests/repros/__snapshots__/repro112-pinheader-double-row-pcb-3d-pcb.snap.svg
+++ b/tests/repros/__snapshots__/repro112-pinheader-double-row-pcb-3d-pcb.snap.svg
@@ -1 +1 @@
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index 2e27fa0c4..31f7c176c 100644
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diff --git a/tests/repros/__snapshots__/repro23-trace-overlap-pcb.snap.svg b/tests/repros/__snapshots__/repro23-trace-overlap-pcb.snap.svg
index 3941c2da6..ca3e122b3 100644
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\ No newline at end of file
diff --git a/tests/repros/__snapshots__/repro29-externally-connected-pins-pcb.snap.svg b/tests/repros/__snapshots__/repro29-externally-connected-pins-pcb.snap.svg
index 22d56955c..0cf90009d 100644
--- a/tests/repros/__snapshots__/repro29-externally-connected-pins-pcb.snap.svg
+++ b/tests/repros/__snapshots__/repro29-externally-connected-pins-pcb.snap.svg
@@ -1 +1 @@
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diff --git a/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg b/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg
index ad45d92a7..fd463b8ca 100644
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+++ b/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg
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diff --git a/tests/repros/__snapshots__/repro49-same-net-not-combine-pcb.snap.svg b/tests/repros/__snapshots__/repro49-same-net-not-combine-pcb.snap.svg
index 2640c6b5c..246631262 100644
--- a/tests/repros/__snapshots__/repro49-same-net-not-combine-pcb.snap.svg
+++ b/tests/repros/__snapshots__/repro49-same-net-not-combine-pcb.snap.svg
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diff --git a/tests/repros/__snapshots__/repro57-silkscreen-rotation-counter-clockwise-pcb.snap.svg b/tests/repros/__snapshots__/repro57-silkscreen-rotation-counter-clockwise-pcb.snap.svg
index 085e46df2..6001e6a71 100644
--- a/tests/repros/__snapshots__/repro57-silkscreen-rotation-counter-clockwise-pcb.snap.svg
+++ b/tests/repros/__snapshots__/repro57-silkscreen-rotation-counter-clockwise-pcb.snap.svg
@@ -1 +1 @@
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diff --git a/tests/repros/__snapshots__/repro58-pcb-autolayout-out-of-board-pcb.snap.svg b/tests/repros/__snapshots__/repro58-pcb-autolayout-out-of-board-pcb.snap.svg
index 28188aa4e..04faffdb5 100644
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diff --git a/tests/repros/__snapshots__/repro59-pcb-autolayout-components-overlap-pcb.snap.svg b/tests/repros/__snapshots__/repro59-pcb-autolayout-components-overlap-pcb.snap.svg
index 86dba598d..10cb387b8 100644
--- a/tests/repros/__snapshots__/repro59-pcb-autolayout-components-overlap-pcb.snap.svg
+++ b/tests/repros/__snapshots__/repro59-pcb-autolayout-components-overlap-pcb.snap.svg
@@ -1 +1 @@
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diff --git a/tests/repros/__snapshots__/repro64-packing-outside-board-pcb.snap.svg b/tests/repros/__snapshots__/repro64-packing-outside-board-pcb.snap.svg
index e99a8efdd..ef7ad41ee 100644
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diff --git a/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg b/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg
index d7529b031..c04ac5cef 100644
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+++ b/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg
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class="pcb-hole-inner" fill="#FF26E2" cx="551.6190476190477" cy="185.71428571428578" r="9.523809523809524" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1_greenpill.pin2" data-pad-net-name="GND"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="600" cy="185.71428571428578" r="14.285714285714285" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="600" cy="185.71428571428578" r="9.523809523809524" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1_greenpill.pin3" data-pad-net-name="VDD"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="648.3809523809524" cy="185.71428571428578" r="14.285714285714285" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="648.3809523809524" cy="185.71428571428578" r="9.523809523809524" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_via" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="619.047619047619" cy="284.7619047619048" r="2.857142857142857" data-type="pcb_via" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="619.047619047619" cy="284.7619047619048" r="1.9047619047619049" data-type="pcb_via" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/repros/repro57-silkscreen-rotation-counter-clockwise.test.tsx b/tests/repros/repro57-silkscreen-rotation-counter-clockwise.test.tsx
index f1ead1dec..6ec737b8c 100644
--- a/tests/repros/repro57-silkscreen-rotation-counter-clockwise.test.tsx
+++ b/tests/repros/repro57-silkscreen-rotation-counter-clockwise.test.tsx
@@ -28,9 +28,9 @@ test("rotate silkscreen text ccw", async () => {
   expect(pcb_silkscreen_text).toMatchInlineSnapshot(`
     [
       {
-        "anchor_alignment": "center_left",
+        "anchor_alignment": "center_right",
         "anchor_position": {
-          "x": 1.41,
+          "x": 1.54,
           "y": -1.27,
         },
         "ccw_rotation": 90,
@@ -47,9 +47,9 @@ test("rotate silkscreen text ccw", async () => {
         "type": "pcb_silkscreen_text",
       },
       {
-        "anchor_alignment": "center_left",
+        "anchor_alignment": "center_right",
         "anchor_position": {
-          "x": 1.41,
+          "x": 1.54,
           "y": 1.27,
         },
         "ccw_rotation": 90,
diff --git a/tests/subcircuits/__snapshots__/subcircuit-expose-nets-prop-pcb.snap.svg b/tests/subcircuits/__snapshots__/subcircuit-expose-nets-prop-pcb.snap.svg
index 0ea16ca89..a19662e0a 100644
--- a/tests/subcircuits/__snapshots__/subcircuit-expose-nets-prop-pcb.snap.svg
+++ b/tests/subcircuits/__snapshots__/subcircuit-expose-nets-prop-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1363"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="132.00000000000003" width="666.6666666666667" height="336" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 468.00000000000006 L 733.3333333333335 468.00000000000006 L 733.3333333333335 134.66666666666669 L 66.66666666666669 134.66666666666669 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-trace" stroke="rgb(200, 52, 52)" fill="none" d="M 600 301.33333333333337 L 200.00000000000006 301.33333333333337" stroke-width="6.666666666666668" stroke-linecap="round" stroke-linejoin="round" shape-rendering="crispEdges" data-type="pcb_trace" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,226.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">net_GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,132.00000000000003)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,600,226.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">net_GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,600,132.00000000000003)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="251.33333333333337" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="301.33333333333337" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="550" y="251.33333333333337" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="600" cy="301.33333333333337" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="132.00000000000003" width="666.6666666666667" height="336" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 468.00000000000006 L 733.3333333333335 468.00000000000006 L 733.3333333333335 134.66666666666669 L 66.66666666666669 134.66666666666669 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-trace" stroke="rgb(200, 52, 52)" fill="none" d="M 600 301.33333333333337 L 200.00000000000006 301.33333333333337" stroke-width="6.666666666666668" stroke-linecap="round" stroke-linejoin="round" shape-rendering="crispEdges" data-type="pcb_trace" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,211.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">net_GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,132.00000000000003)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,600,211.33333333333337)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">net_GND</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,600,132.00000000000003)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.net_GND" data-pad-net-name="GND"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="251.33333333333337" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="301.33333333333337" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.net_GND" data-pad-net-name="GND"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="550" y="251.33333333333337" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="600" cy="301.33333333333337" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g></svg>
\ No newline at end of file
diff --git a/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour01-pcb.snap.svg b/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour01-pcb.snap.svg
index 18476ab3f..4a4c36041 100644
--- a/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour01-pcb.snap.svg
+++ b/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour01-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1362"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="66.6666666666666" width="666.6666666666667" height="466.66666666666663" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 533.3333333333333 L 733.3333333333335 533.3333333333333 L 733.3333333333335 66.6666666666666 L 66.66666666666669 66.6666666666666 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-copper-pour pcb-copper-pour-brep" d="M 720 520 L 80.00000000000006 520 L 80.00000000000006 79.99999999999994 L 720 79.99999999999994 L 720 520 Z M 382.00000000000006 366.66666666666663 L 515.3333333333334 366.66666666666663 L 515.3333333333334 233.33333333333326 L 382.00000000000006 233.33333333333326 L 382.00000000000006 366.66666666666663 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,448.66666666666674,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,618.0000000000001,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,533.3333333333334,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="398.66666666666674" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="448.66666666666674" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="618.0000000000001" cy="299.99999999999994" r="50" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="618.0000000000001" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><text x="400.00000000000006" y="113.33333333333329" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_0" data-pcb-layer="overlay">Expected: copper pour connects to A and C, but clears around B.</text><text x="400.00000000000006" y="133.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_1" data-pcb-layer="overlay">A is parent net.GND; C is child net.GND reached through exposedNets.</text><text x="400.00000000000006" y="153.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_2" data-pcb-layer="overlay">B is a separate child pin, so the pour should clear around it.</text></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="66.6666666666666" width="666.6666666666667" height="466.66666666666663" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 533.3333333333333 L 733.3333333333335 533.3333333333333 L 733.3333333333335 66.6666666666666 L 66.66666666666669 66.6666666666666 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-copper-pour pcb-copper-pour-brep" d="M 720 520 L 80.00000000000006 520 L 80.00000000000006 79.99999999999994 L 720 79.99999999999994 L 720 520 Z M 382.00000000000006 366.66666666666663 L 515.3333333333334 366.66666666666663 L 515.3333333333334 233.33333333333326 L 382.00000000000006 233.33333333333326 L 382.00000000000006 366.66666666666663 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,209.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,448.66666666666674,209.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,618.0000000000001,209.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,533.3333333333334,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.A" data-pad-net-name="GND"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.B"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="398.66666666666674" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="448.66666666666674" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.C" data-pad-net-name="GND"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="618.0000000000001" cy="299.99999999999994" r="50" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="618.0000000000001" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><text x="400.00000000000006" y="113.33333333333329" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_0" data-pcb-layer="overlay">Expected: copper pour connects to A and C, but clears around B.</text><text x="400.00000000000006" y="133.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_1" data-pcb-layer="overlay">A is parent net.GND; C is child net.GND reached through exposedNets.</text><text x="400.00000000000006" y="153.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_2" data-pcb-layer="overlay">B is a separate child pin, so the pour should clear around it.</text></svg>
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diff --git a/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour02-pcb.snap.svg b/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour02-pcb.snap.svg
index fa7ff1231..702cb7de6 100644
--- a/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour02-pcb.snap.svg
+++ b/tests/subcircuits/__snapshots__/subcircuit-exposed-nets-copper-pour02-pcb.snap.svg
@@ -1 +1 @@
-<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1362"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="66.6666666666666" width="666.6666666666667" height="466.66666666666663" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 533.3333333333333 L 733.3333333333335 533.3333333333333 L 733.3333333333335 66.6666666666666 L 66.66666666666669 66.6666666666666 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-copper-pour pcb-copper-pour-brep" d="M 720 520 L 80.00000000000006 520 L 80.00000000000006 79.99999999999994 L 720 79.99999999999994 L 720 520 Z M 382.00000000000006 366.66666666666663 L 515.3333333333334 366.66666666666663 L 515.3333333333334 233.33333333333326 L 382.00000000000006 233.33333333333326 L 382.00000000000006 366.66666666666663 Z M 618.0000000000001 366.66666666666663 L 631.0060000000001 365.3856666666666 L 643.5122000000001 361.5919999999999 L 655.038 355.43133333333327 L 665.1404666666667 347.1404666666666 L 673.4313333333334 337.03799999999995 L 679.5920000000001 325.51219999999995 L 683.3856666666668 313.006 L 684.6666666666667 299.99999999999994 L 683.3856666666668 286.9939999999999 L 679.5920000000001 274.48779999999994 L 673.4313333333334 262.96199999999993 L 665.1404666666667 252.85953333333327 L 655.038 244.56866666666662 L 643.5122000000001 238.40799999999993 L 631.0060000000001 234.61433333333326 L 618.0000000000001 233.33333333333326 L 604.9940000000001 234.61433333333326 L 592.4878000000001 238.40799999999993 L 580.9620000000001 244.56866666666662 L 570.8595333333334 252.85953333333327 L 562.5686666666668 262.96199999999993 L 556.4080000000001 274.48779999999994 L 552.6143333333334 286.9939999999999 L 551.3333333333334 299.99999999999994 L 552.6143333333334 313.006 L 556.4080000000001 325.51219999999995 L 562.5686666666668 337.03799999999995 L 570.8595333333334 347.1404666666666 L 580.9620000000001 355.43133333333327 L 592.4878000000001 361.5919999999999 L 604.9940000000001 365.3856666666666 L 618.0000000000001 366.66666666666663 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,448.66666666666674,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,618.0000000000001,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,533.3333333333334,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="398.66666666666674" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="448.66666666666674" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="618.0000000000001" cy="299.99999999999994" r="50" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="618.0000000000001" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><text x="400.00000000000006" y="113.33333333333329" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_0" data-pcb-layer="overlay">Expected: copper pour connects to A, but clears around B and C.</text><text x="400.00000000000006" y="133.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_1" data-pcb-layer="overlay">A is parent net.GND; child net.GND is not reached without exposedNets.</text><text x="400.00000000000006" y="153.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_2" data-pcb-layer="overlay">B and C are child pins, so the parent pour should clear around both.</text></svg>
\ No newline at end of file
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.1503"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="66.6666666666666" width="666.6666666666667" height="466.66666666666663" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 533.3333333333333 L 733.3333333333335 533.3333333333333 L 733.3333333333335 66.6666666666666 L 66.66666666666669 66.6666666666666 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-copper-pour pcb-copper-pour-brep" d="M 720 520 L 80.00000000000006 520 L 80.00000000000006 79.99999999999994 L 720 79.99999999999994 L 720 520 Z M 382.00000000000006 366.66666666666663 L 515.3333333333334 366.66666666666663 L 515.3333333333334 233.33333333333326 L 382.00000000000006 233.33333333333326 L 382.00000000000006 366.66666666666663 Z M 618.0000000000001 366.66666666666663 L 631.0060000000001 365.3856666666666 L 643.5122000000001 361.5919999999999 L 655.038 355.43133333333327 L 665.1404666666667 347.1404666666666 L 673.4313333333334 337.03799999999995 L 679.5920000000001 325.51219999999995 L 683.3856666666668 313.006 L 684.6666666666667 299.99999999999994 L 683.3856666666668 286.9939999999999 L 679.5920000000001 274.48779999999994 L 673.4313333333334 262.96199999999993 L 665.1404666666667 252.85953333333327 L 655.038 244.56866666666662 L 643.5122000000001 238.40799999999993 L 631.0060000000001 234.61433333333326 L 618.0000000000001 233.33333333333326 L 604.9940000000001 234.61433333333326 L 592.4878000000001 238.40799999999993 L 580.9620000000001 244.56866666666662 L 570.8595333333334 252.85953333333327 L 562.5686666666668 262.96199999999993 L 556.4080000000001 274.48779999999994 L 552.6143333333334 286.9939999999999 L 551.3333333333334 299.99999999999994 L 552.6143333333334 313.006 L 556.4080000000001 325.51219999999995 L 562.5686666666668 337.03799999999995 L 570.8595333333334 347.1404666666666 L 580.9620000000001 355.43133333333327 L 592.4878000000001 361.5919999999999 L 604.9940000000001 365.3856666666666 L 618.0000000000001 366.66666666666663 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,209.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,448.66666666666674,209.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,618.0000000000001,209.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,533.3333333333334,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J1.A" data-pad-net-name="GND"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.B"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="398.66666666666674" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="448.66666666666674" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through" data-pad-name="J2.C" data-pad-net-name="GND"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="618.0000000000001" cy="299.99999999999994" r="50" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="618.0000000000001" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><text x="400.00000000000006" y="113.33333333333329" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_0" data-pcb-layer="overlay">Expected: copper pour connects to A, but clears around B and C.</text><text x="400.00000000000006" y="133.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_1" data-pcb-layer="overlay">A is parent net.GND; child net.GND is not reached without exposedNets.</text><text x="400.00000000000006" y="153.33333333333326" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_2" data-pcb-layer="overlay">B and C are child pins, so the parent pour should clear around both.</text></svg>
\ No newline at end of file