$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */

[FPGAEveryday]

I am not sure how hard this one is to fix, but if I have either of the following in my board file Verilog:

`ifdef SOMETHING_NOT_DEFINED
$$ SOME_VARIABLE = 16
`endif

or

/*
$$ SOME_VARIABLE = 16
*/

SOME_VARIABLE will still be defined to 16 for the Silice code. I had wired through support for two different parallel OLED displays in my board verilog file with one commented out - the commented out block was after and set some of the same variables, and they still got set even though it was commented out.

[sylefeb]

Hi - thanks for this issue, that is a good point. I just updated the documentation with explanations on this:
https://github.com/sylefeb/Silice/blob/draft/learn-silice/Documentation.md#lua-pre-processor-in-frameworks
(in draft branch for now)

As explained in the updated documentation this happens because the preprocessor executes well before Verilog is parsed by the toolchain: these preprocessor directives are actually extracted from the Verilog glue file and appended to the Silice source. There are nevertheless a number of workarounds to achieve what you experimented with (I think?), that I documented.

Also, sorry for the long time it took to look into this!