Target real RISC-V cores for exhaustive XIF verification

[metasmile]

The current ev constraint model and fixtures are toy examples. The tool must validate itself against actual production RISC-V cores to become a complete verification platform.

Goal

Establish ev as a self-sufficient verification tool by modeling, testing, and exhaustively verifying the custom extension interfaces of at least two top-tier RISC-V cores.

Candidates

• CVA6 (OpenHW Group) — XIF interface, documented, production-grade. Already name-checked in sample.xif.yaml target field but never actually modeled.
• Ibex (lowRISC) — simpler ALU extension, well-documented, good for demonstrating the value of exhaustive over random.

Deliverables per core

1. XIF / extension interface spec analyzed and translated into ev constraint YAML
2. Realistic fixture files (e.g., rv32i_vector_mac.xif.yaml, simple_alu_ext.xif.yaml)
3. ev check passes with deterministic, auditable results
4. Any coverage gaps vs. existing random-simulation approaches documented
5. Results shared with the corresponding open-source core community

This is self-contained

SSCCS and Nexus do not need to change for this. ev produces Facts as JSON output. When the verification results are valid and complete, Nexus consumes them naturally through the existing ingestion pipeline (Facts in object storage → sync worker → knowledge graph). No cross-project coordination required.

Stacking order

1. Evaluate current constraint/projector gaps against real XIF specs
2. Implement missing constraint/projector types
3. Create CVA6 and/or Ibex fixture files
4. Run, validate, document

[metasmile]

#9가 추가되어 이슈 #7의 하위 태스크로 연결되었습니다.

현재 상태

PR #8 머지 완료. 달성한 것:

• CVA6 예제 코프로세서(cvxif_instr_pkg.sv) encoding space 검증 완료
• cva6_xif_ref.xif.yaml — 실제 RTL 기반 fixture

다음: #9

남은 CVA6 작업은 #9로 트래킹: verification suite(cvxif_custom_instr.sv)의 실제 funct3/funct7 매핑 반영 + Spike simulation channel 구현