CVA6 fixture RTL cross-check: align with actual cvxif_custom_instr.sv

[metasmile]

Goal

Update cva6_xif_ref.xif.yaml and cva6_xif_encoding.xif.yaml to match the actual CVA6 RTL encoding table (cvxif_custom_instr.sv) exactly. This depends on #17 (R4 format) and #18 (conditional fields) being completed first.

Background

The current fixture is a close approximation but has known discrepancies:

1. CUS_ADD_RS3 uses func2=01 (bits [26:25]), not funct7=32 — blocked by R4 format support: func2 field axis for ADD_RS3 #17
2. CUS_NOP forces rd=rs1=rs2=0 — blocked by LLM interpretation: --interpret flag for failure explanation #18
3. CUS_EXC has weighted rs1 distribution (0-9 high weight, 10/14 low weight) — optional
4. Hardware decoder (cvxif_instr_pkg.sv) uses mask-based matching that also considers rs2 bits for DOUBLE_RS1/DOUBLE_RS2 — should be verified

Tasks

1. After R4 format support: func2 field axis for ADD_RS3 #17: update funct7=32 → proper func2=01 for ADD_RS3 in both fixtures
2. After LLM interpretation: --interpret flag for failure explanation #18: add CUS_NOP encoding validation (funct3=001, funct7=0, rd=rs1=rs2=0)
3. Cross-check CUS_ADD_MULTI, CUS_U_ADD, CUS_S_ADD funct7 values against RTL
4. Add CUS_EXC test case with weighted distribution (optional)
5. Run ev verify and ev simulate on updated fixtures to confirm all pass
6. Verify the 6-instruction CVA6 XIF coprocessor encoding table is fully covered

References

• cva6/verif/env/corev-dv/custom/cvxif_custom_instr.sv — Primary DV encoding
• cva6/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv — Enum: CUS_ADD..CUS_S_ADD
• cva6/verif/env/corev-dv/custom/rv32x_instr.sv — R_FORMAT/R4_FORMAT declarations
• cva6/core/cvxif_example/include/cvxif_instr_pkg.sv — Hardware decoder mask table
• tests/fixtures/cva6_xif_ref.xif.yaml
• tests/fixtures/cva6_xif_encoding.xif.yaml

Dependencies

• R4 format support: func2 field axis for ADD_RS3 #17 — R4 format support (func2 field)
• LLM interpretation: --interpret flag for failure explanation #18 — Conditional field activation

Parent Issue

#13 — Phase 2: Spike simulation backend and CVA6 XIF exhaustive verification