Milestone: GPU compute backend on the GB10 (DGX Spark)
Hardware decoded from the box (nvidia-smi): NVIDIA GB10 — Grace Blackwell
superchip, 128 GB unified LPDDR5X, 20-core Grace, Blackwell tensor cores
(FP4/E2M1 native), CUDA 13.0. No discrete VRAM — the GPU reads the same
memory the CPU caches.
What that means for the architecture:
| Lever |
Effect |
| Unified memory |
no PCIe bottleneck, zero-copy: the cache slot buffers are already GPU-visible; the mxfp4 pool + trunk can sit fully resident (memory gate becomes the residency planner) |
| Blackwell FP4 |
the pool format we already emit (E2M1 values + E8M0 block scales) is the GPU's native math type |
| Bandwidth wall |
~273 GB/s unified; ~residency -> GB/token ~0; estimate 5-10 ms/token vs 7 s/token today (verify on the box, don't trust the estimate) |
Plan:
- Toolchain probe + equivalence gate on the box (small, run first):
nvcc --version, cuBLAS presence
- a ~40-line CUDA kernel that decodes the mxfp4 pool (2 values/byte, E8M0
scales, block32) to bf16/fp32, compared element-wise against the CPU
reference decode on the fixture — the scalar kernels (step 2) are the
oracle; GPU must match within fp32 accumulation tolerance
make gpu-probe target + fixture run on the box, paste back
- Engine
--backend gpu v1: mxfp4 decode kernel (zero-copy over the
existing cache slots) + cuBLAS GEMM for the expert chain and router;
--dump-state equivalence vs --backend cpu on the fixture (the
determinism gate extended to cross-backend)
- Residency tuning: with ~125 GB available, the gate plans pin-all-trunk
- ~90% pool residency; measure GB/token -> ~0 and the new sec/token
- Real-pool run on the box:
--backend gpu --preset server on the
existing ~/ds4f-mxfp4 pool
Verification policy: everything runs on the box (per the project rule —
verification on the compute machine); the Mac develops + gates the CPU
reference only.
Later (not this milestone): native FP4 GEMM (skip the decode), DSpark draft
running concurrently on the Grace CPU as the real prefetcher.
Milestone: GPU compute backend on the GB10 (DGX Spark)
Hardware decoded from the box (nvidia-smi): NVIDIA GB10 — Grace Blackwell
superchip, 128 GB unified LPDDR5X, 20-core Grace, Blackwell tensor cores
(FP4/E2M1 native), CUDA 13.0. No discrete VRAM — the GPU reads the same
memory the CPU caches.
What that means for the architecture:
Plan:
nvcc --version, cuBLAS presencescales, block32) to bf16/fp32, compared element-wise against the CPU
reference decode on the fixture — the scalar kernels (step 2) are the
oracle; GPU must match within fp32 accumulation tolerance
make gpu-probetarget + fixture run on the box, paste back--backend gpuv1: mxfp4 decode kernel (zero-copy over theexisting cache slots) + cuBLAS GEMM for the expert chain and router;
--dump-stateequivalence vs--backend cpuon the fixture (thedeterminism gate extended to cross-backend)
--backend gpu --preset serveron theexisting ~/ds4f-mxfp4 pool
Verification policy: everything runs on the box (per the project rule —
verification on the compute machine); the Mac develops + gates the CPU
reference only.
Later (not this milestone): native FP4 GEMM (skip the decode), DSpark draft
running concurrently on the Grace CPU as the real prefetcher.