From 4198c070a09e952741e8fa9c621c96ade4b57e0e Mon Sep 17 00:00:00 2001 From: Roy Date: Wed, 5 Nov 2025 20:31:58 +0000 Subject: [PATCH] Add oper status and hardware lane list attributes for CPU port. --- dataplane/saiserver/ports.go | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dataplane/saiserver/ports.go b/dataplane/saiserver/ports.go index b539b38bc..44c57221a 100644 --- a/dataplane/saiserver/ports.go +++ b/dataplane/saiserver/ports.go @@ -454,6 +454,8 @@ func (port *port) createCPUPort(ctx context.Context) (uint64, error) { AdminState: proto.Bool(true), AutoNegMode: proto.Bool(false), Mtu: proto.Uint32(1514), + OperStatus: saipb.PortOperStatus_PORT_OPER_STATUS_UP.Enum(), + HwLaneList: []uint32{}, } port.mgr.SetType(fmt.Sprint(id), saipb.ObjectType_OBJECT_TYPE_PORT) port.mgr.StoreAttributes(id, cpuPort)