diff --git a/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch b/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch index dd82e46153..8a2c392775 100644 --- a/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch +++ b/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch @@ -1,4 +1,4 @@ -From e8197b44ac58d76565180793e59b2ff39d0ff8a1 Mon Sep 17 00:00:00 2001 +From 97ce2bdaf4b2f91ebc9016642d5cc671eabce12f Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 5 Dec 2025 10:42:07 +0800 Subject: [RUYI PATCH] UPSTREAM: drm/ttm: add pgprot handling for RISC-V diff --git a/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch b/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch deleted file mode 100644 index a8bd9c03dd..0000000000 --- a/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 8c1d176b72034e3df9780310de7c4ea43d72c9ed Mon Sep 17 00:00:00 2001 -From: Ran Wang -Date: Fri, 20 Mar 2026 15:31:20 +0800 -Subject: [RUYI PATCH] XIANGSHAN: Flush all tlb in set_pte() - -Signed-off-by: Ran Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/pgtable.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h -index 9b2e967c9fe0..efd7617da903 100644 ---- a/arch/riscv/include/asm/pgtable.h -+++ b/arch/riscv/include/asm/pgtable.h -@@ -550,6 +550,7 @@ static inline int pte_same(pte_t pte_a, pte_t pte_b) - static inline void set_pte(pte_t *ptep, pte_t pteval) - { - WRITE_ONCE(*ptep, pteval); -+ __asm__ __volatile__ ("sfence.vma" : : : "memory"); - } - - void flush_icache_pte(struct mm_struct *mm, pte_t pte); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch b/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch index b8cb7f6ff0..85a75bc27b 100644 --- a/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch +++ b/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch @@ -1,4 +1,4 @@ -From 172fa2e5a76c1351ea1bb6903e1d03944ce8a778 Mon Sep 17 00:00:00 2001 +From 97be83a032e9301602d9de79b068c7f8643c14b5 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:33:43 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: add PCIe controllers for diff --git a/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch b/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch deleted file mode 100644 index eb448a6a4e..0000000000 --- a/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 72813582d41500d578c0d5b500c4224f33824e91 Mon Sep 17 00:00:00 2001 -From: Ran Wang -Date: Fri, 20 Mar 2026 15:36:58 +0800 -Subject: [RUYI PATCH] XIANGSHAN: Add two sbi calls - -Signed-off-by: Ran Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/sbi.h | 4 ++++ - arch/riscv/kernel/sbi.c | 12 ++++++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h -index ccc77a89b1e2..189956420b4c 100644 ---- a/arch/riscv/include/asm/sbi.h -+++ b/arch/riscv/include/asm/sbi.h -@@ -55,6 +55,8 @@ enum sbi_ext_base_fid { - SBI_EXT_BASE_GET_MVENDORID, - SBI_EXT_BASE_GET_MARCHID, - SBI_EXT_BASE_GET_MIMPID, -+ SBI_EXT_BASE_GET_MHARTID, -+ SBI_EXT_BASE_FLUSH_L2CACHE, - }; - - enum sbi_ext_time_fid { -@@ -664,6 +666,8 @@ unsigned long riscv_get_marchid(void); - unsigned long riscv_cached_mvendorid(unsigned int cpu_id); - unsigned long riscv_cached_marchid(unsigned int cpu_id); - unsigned long riscv_cached_mimpid(unsigned int cpu_id); -+long sbi_get_mhartid(void); -+long sbi_flush_l2cache(void); - - #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) - DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence); -diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c -index c443337056ab..05c27dd1e397 100644 ---- a/arch/riscv/kernel/sbi.c -+++ b/arch/riscv/kernel/sbi.c -@@ -646,6 +646,18 @@ int sbi_debug_console_read(char *bytes, unsigned int num_bytes) - return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; - } - -+long sbi_get_mhartid(void) -+{ -+ return __sbi_base_ecall(SBI_EXT_BASE_GET_MHARTID); -+} -+EXPORT_SYMBOL(sbi_get_mhartid); -+ -+long sbi_flush_l2cache(void) -+{ -+ return __sbi_base_ecall(SBI_EXT_BASE_FLUSH_L2CACHE); -+} -+EXPORT_SYMBOL(sbi_flush_l2cache); -+ - void __init sbi_init(void) - { - bool srst_power_off = false; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch b/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch index 43e4f49e7c..afac2af701 100644 --- a/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch +++ b/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch @@ -1,4 +1,4 @@ -From eb8e783adc4036ef80be48cfc8469b4be20fb577 Mon Sep 17 00:00:00 2001 +From 3690d132b79814fcc0c66ab440226e50704d3483 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:34:05 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for PioneerBox diff --git a/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch b/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch deleted file mode 100644 index 1aee7a490c..0000000000 --- a/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch +++ /dev/null @@ -1,250 +0,0 @@ -From 221755ad22855e46ff06ad063bde801c81b4bb75 Mon Sep 17 00:00:00 2001 -From: Ran Wang -Date: Fri, 20 Mar 2026 15:50:27 +0800 -Subject: [RUYI PATCH] XIANGSHAN: Add workaround to retry when access fault - -Signed-off-by: Ran Wang -Signed-off-by: Han Gao ---- - .../include/asm/bosc_mm_fault_workaround.h | 9 ++ - arch/riscv/kernel/Makefile | 2 + - arch/riscv/kernel/bosc_mm_fault_workaround.c | 91 +++++++++++++++++++ - arch/riscv/kernel/traps.c | 14 ++- - arch/riscv/mm/fault.c | 8 ++ - kernel/watchdog.c | 3 + - 6 files changed, 126 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/include/asm/bosc_mm_fault_workaround.h - create mode 100644 arch/riscv/kernel/bosc_mm_fault_workaround.c - -diff --git a/arch/riscv/include/asm/bosc_mm_fault_workaround.h b/arch/riscv/include/asm/bosc_mm_fault_workaround.h -new file mode 100644 -index 000000000000..33c7743052f6 ---- /dev/null -+++ b/arch/riscv/include/asm/bosc_mm_fault_workaround.h -@@ -0,0 +1,9 @@ -+#ifndef __BOSC_MM_FAULT_WORKAROUND_H__ -+#define __BOSC_MM_FAULT_WORKAROUND_H__ -+ -+#include -+ -+int bosc_kernel_fault_workaround(struct pt_regs *regs); -+int bosc_segment_fault_workaround(struct pt_regs *regs); -+ -+#endif -diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile -index a01f6439d62b..9d13ba5fbdd5 100644 ---- a/arch/riscv/kernel/Makefile -+++ b/arch/riscv/kernel/Makefile -@@ -46,6 +46,8 @@ endif - - always-$(KBUILD_BUILTIN) += vmlinux.lds - -+obj-y += bosc_mm_fault_workaround.o -+ - obj-y += head.o - obj-y += soc.o - obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o -diff --git a/arch/riscv/kernel/bosc_mm_fault_workaround.c b/arch/riscv/kernel/bosc_mm_fault_workaround.c -new file mode 100644 -index 000000000000..8d97984b7879 ---- /dev/null -+++ b/arch/riscv/kernel/bosc_mm_fault_workaround.c -@@ -0,0 +1,91 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BOSC_WORKAROUND_SEGMENT_FAULT_TRY_CNT 3 -+#define BOSC_WORKAROUND_KERNEL_FAULT_TRY_CNT 3 -+ -+static unsigned long last_segment_fault_addr = 0; -+static unsigned long last_kernel_fault_addr = 0; -+ -+static int segment_fault_workaround_cnt = 0; -+static int kernel_fault_workaround_cnt = 0; -+ -+#define CSR_FLUSH_PWR 0xBC1 -+#define FLUSH_PWR_FLUSH_L2_EN 0 -+#define FLUSH_PWR_FLUSH_L2_DONE 1 -+static void core_cache_ctrl(void) -+{ -+ uint64_t value = 0; -+ -+ smp_mb(); -+ -+ csr_set(CSR_FLUSH_PWR, BIT(0)); -+ value = csr_read(CSR_FLUSH_PWR); -+ while((value & BIT(FLUSH_PWR_FLUSH_L2_DONE)) == 0) { -+ value = csr_read(CSR_FLUSH_PWR); -+ } -+} -+ -+int bosc_kernel_fault_workaround(struct pt_regs *regs) -+{ -+ unsigned long addr = regs->badaddr; -+ -+ if (addr != last_kernel_fault_addr) { -+ kernel_fault_workaround_cnt = 0; -+ goto kernel_workaround; -+ } -+ -+ kernel_fault_workaround_cnt++; -+ -+ if (kernel_fault_workaround_cnt < BOSC_WORKAROUND_KERNEL_FAULT_TRY_CNT) -+ goto kernel_workaround; -+ -+ return 0; -+ -+kernel_workaround: -+ printk("##### BOSC KERNEL FAULT WORKAROUND, cnt:%d\n", kernel_fault_workaround_cnt); -+ last_kernel_fault_addr = addr; -+ printk("badaddr: 0x%lx\n", addr); -+ dump_stack(); -+ -+ asm volatile ("sfence.vma" ::: "memory"); -+ sbi_flush_l2cache(); -+ -+ return 1; -+} -+EXPORT_SYMBOL(bosc_kernel_fault_workaround); -+ -+int bosc_segment_fault_workaround(struct pt_regs *regs) -+{ -+ unsigned long addr = regs->badaddr; -+ -+ if (addr != last_segment_fault_addr) { -+ segment_fault_workaround_cnt = 0; -+ goto segment_workaround; -+ } -+ -+ segment_fault_workaround_cnt++; -+ -+ if (segment_fault_workaround_cnt < BOSC_WORKAROUND_SEGMENT_FAULT_TRY_CNT) -+ goto segment_workaround; -+ -+ return 0; -+ -+segment_workaround: -+ printk("##### BOSC SEGMENT FAULT WORKAROUND, cnt:%d\n", segment_fault_workaround_cnt); -+ last_segment_fault_addr = addr; -+ printk("badaddr: 0x%lx\n", addr); -+ dump_stack(); -+ -+ asm volatile ("sfence.vma" ::: "memory"); -+ sbi_flush_l2cache(); -+ -+ return 1; -+} -+EXPORT_SYMBOL(bosc_segment_fault_workaround); -diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c -index 47afea4ff1a8..41bba00da16a 100644 ---- a/arch/riscv/kernel/traps.c -+++ b/arch/riscv/kernel/traps.c -@@ -34,6 +34,9 @@ - #include - #include - -+#include -+#include -+ - int show_unhandled_signals = 1; - - static DEFINE_RAW_SPINLOCK(die_lock); -@@ -116,6 +119,9 @@ void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) - { - struct task_struct *tsk = current; - -+ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); -+ if (bosc_segment_fault_workaround(regs)) -+ return; - if (show_unhandled_signals && unhandled_signal(tsk, signo) - && printk_ratelimit()) { - pr_info("%s[%d]: unhandled signal %d code 0x%x at 0x" REG_FMT, -@@ -126,6 +132,7 @@ void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) - dump_instr(KERN_INFO, regs); - } - -+ printk("!!! BOSC DEBUG: bosc mm_fault workaround failed\n"); - force_sig_fault(signo, code, (void __user *)addr); - } - -@@ -137,8 +144,12 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, - if (user_mode(regs)) { - do_trap(regs, signo, code, addr); - } else { -- if (!fixup_exception(regs)) -+ if (!fixup_exception(regs)) { -+ if (bosc_kernel_fault_workaround(regs)) -+ return; -+ printk("!!! BOSC DEBUG: bosc mm_fault workaround failed\n"); - die(regs, str); -+ } - } - } - -@@ -150,6 +161,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, - #define DO_ERROR_INFO(name, signo, code, str) \ - asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ - { \ -+ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); \ - if (user_mode(regs)) { \ - irqentry_enter_from_user_mode(regs); \ - local_irq_enable(); \ -diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c -index 04ed6f8acae4..eed270e76581 100644 ---- a/arch/riscv/mm/fault.c -+++ b/arch/riscv/mm/fault.c -@@ -20,6 +20,9 @@ - #include - #include - -+#include -+#include -+ - #define CREATE_TRACE_POINTS - #include - -@@ -81,9 +84,14 @@ static void die_kernel_fault(const char *msg, unsigned long addr, - { - bust_spinlocks(1); - -+ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); - pr_alert("Unable to handle kernel %s at virtual address " REG_FMT "\n", msg, - addr); - -+ if (bosc_kernel_fault_workaround(regs)) -+ return; -+ -+ printk("!!! BOSC DEBUG: bosc mm_fault workaround failed\n"); - bust_spinlocks(0); - show_pte(addr); - die(regs, "Oops"); -diff --git a/kernel/watchdog.c b/kernel/watchdog.c -index 25d134306e14..4bc8448cd6ad 100644 ---- a/kernel/watchdog.c -+++ b/kernel/watchdog.c -@@ -32,6 +32,8 @@ - - #include - -+#include -+ - static DEFINE_MUTEX(watchdog_mutex); - - #if defined(CONFIG_HARDLOCKUP_DETECTOR) || defined(CONFIG_HARDLOCKUP_DETECTOR_SPARC64) -@@ -831,6 +833,7 @@ static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer) - smp_processor_id(), duration, - current->comm, task_pid_nr(current)); - report_cpu_status(); -+ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); - print_modules(); - print_irqtrace_events(current); - if (regs) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index 46b8b479dc..29dfacf6a1 100644 --- a/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,4 +1,4 @@ -From 97f3ca4bfb8cf08fc5f01da48adbd2e295d9bf62 Mon Sep 17 00:00:00 2001 +From e80454feebb2dfa5da9609ea55fce6f9519c8be2 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:39:22 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for diff --git a/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index 118243db74..1a055cfef7 100644 --- a/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,4 +1,4 @@ -From adfc1b75ef3710cc675487e2d856fe811e92c9cf Mon Sep 17 00:00:00 2001 +From 71bf5268f5ef1cc80ed546655694263fd3097451 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:40:09 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for diff --git a/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch b/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch index 0105843995..a5d596c0c0 100644 --- a/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch +++ b/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch @@ -1,4 +1,4 @@ -From 0fe3f721fe45c7b4cfd9c65eaea2e94c7d05d05a Mon Sep 17 00:00:00 2001 +From 0d419dceddbb45354691c13c2af18305fe6547b4 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:50 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for diff --git a/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch b/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch index e7d51ad4e9..33418a23c5 100644 --- a/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch +++ b/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch @@ -1,4 +1,4 @@ -From 9e5ebf3bb03d5951a1ac6273a557a7d3b42aaf5d Mon Sep 17 00:00:00 2001 +From 43537896ac9425049eb19027394a36723e71fa30 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:51 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for diff --git a/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index 0353c0d45c..b9c0dedbfc 100644 --- a/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,4 +1,4 @@ -From ca6b4bc1ae282908399370569de96b507b11a199 Mon Sep 17 00:00:00 2001 +From 1279d407915d0d8872feb831ab0057a57cfc7766 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:52 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for diff --git a/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index 849dbb07fb..45faa67a83 100644 --- a/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,4 +1,4 @@ -From ef69ecb5f71cc9ec10bbe973e96dec13a22d83c5 Mon Sep 17 00:00:00 2001 +From 4a6215528dd5e1ef5ed45e47dcc2156905f17457 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:53 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for diff --git a/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch b/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch index f9aa138c7a..afabfcf38d 100644 --- a/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch +++ b/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch @@ -1,4 +1,4 @@ -From 4cec01963100499caa46c4c97acb3d80549132f6 Mon Sep 17 00:00:00 2001 +From 220eda5b92a6554f6629a577c1a4f8c8c540ea62 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 14 Nov 2025 08:38:03 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add phy diff --git a/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch b/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch index d0b72dcb45..4953853a2a 100644 --- a/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch +++ b/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch @@ -1,4 +1,4 @@ -From 97f62d7522d266af5df939fe3f50a0e365d78d37 Mon Sep 17 00:00:00 2001 +From c617ae290d1fc44e19de8a6eabb0f9eb646b2a89 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 14 Oct 2025 09:48:29 +0800 Subject: [RUYI PATCH] UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 diff --git a/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch b/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch index de2b418bcf..c5d0087211 100644 --- a/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch +++ b/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch @@ -1,4 +1,4 @@ -From e140a5124e38afd1d68eb3c9da0a96a9bc0c1fd8 Mon Sep 17 00:00:00 2001 +From 030a12284f19a1cb1f1e7f9b99be40c5f772e430 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:32 +0100 Subject: [RUYI PATCH] UPSTREAM: rust: macros: Add support for 'imports_ns' to diff --git a/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch b/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch index a4878efc8e..1d4036d2b5 100644 --- a/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch +++ b/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch @@ -1,4 +1,4 @@ -From 6eec5416f899b995199e6a78acdba366552fe74b Mon Sep 17 00:00:00 2001 +From d90ef5c3db441ba7f0277b9d3d8dd93c6be76480 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:01 +0200 Subject: [RUYI PATCH] UPSTREAM: pwm: Export `pwmchip_release` for external use diff --git a/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch b/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch index 3a11557826..2372b43853 100644 --- a/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch +++ b/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch @@ -1,4 +1,4 @@ -From dc77d3e5fd4e58d58519c452e5ab3a3dc0d30352 Mon Sep 17 00:00:00 2001 +From d22b703423b02fef77f92c7c296b729cb930987e Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:02 +0200 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add Kconfig and basic data diff --git a/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch b/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch index ae5c79af9d..6f84a9b336 100644 --- a/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch +++ b/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch @@ -1,4 +1,4 @@ -From fad4bc85d938d1fa411bfc7c09b2c327dc21cad2 Mon Sep 17 00:00:00 2001 +From ccb66826aea8948cb3035bb3cb97dee900cc6a33 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:03 +0200 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add complete abstraction layer diff --git a/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch b/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch index abdc4b8594..52e33544ff 100644 --- a/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch +++ b/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch @@ -1,4 +1,4 @@ -From a8369a239ce03856b5d63e39d5c92586c0641c18 Mon Sep 17 00:00:00 2001 +From 8d6832a03f3e1f228dcf5140425930cc757b7bdb Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:33 +0100 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add module_pwm_platform_driver! diff --git a/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch b/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch index a2e4a4474c..b615b2a628 100644 --- a/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch +++ b/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch @@ -1,4 +1,4 @@ -From 0bed1f7ddadef9191b85230b6f078bf48a1ddfc1 Mon Sep 17 00:00:00 2001 +From 871900020c098bb21b573743517cd57c5ec7f81b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 25 Oct 2025 14:23:56 +0200 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Drop wrapping of PWM polarity and diff --git a/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch b/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch index aaf7682aaf..55ea08cfbf 100644 --- a/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch +++ b/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch @@ -1,4 +1,4 @@ -From ce0cfe6521836f8d1bff1dbb1dd784f8dbe2f0f1 Mon Sep 17 00:00:00 2001 +From 151e60806c4961978acb15059175ebf859943f2a Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:19:40 +0100 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Fix broken intra-doc link diff --git a/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch b/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch index 4a1351eb60..531fc8e38c 100644 --- a/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch @@ -1,4 +1,4 @@ -From 323a18dcdb57c3c4a56d687fff097af3249b0fe3 Mon Sep 17 00:00:00 2001 +From bd117df72465a339cb37c8f8f294b14b31cfff74 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:04 +0200 Subject: [RUYI PATCH] UPSTREAM: pwm: Add Rust driver for T-HEAD TH1520 SoC diff --git a/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch b/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch index 72b7b6e552..01819c9dc5 100644 --- a/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch +++ b/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch @@ -1,4 +1,4 @@ -From 1ff5f22be0212ca408aa7b7fb452742a1c0e44d8 Mon Sep 17 00:00:00 2001 +From ee6d3ec9107c0fd772c16584ca526ebe78cd30b0 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:05 +0200 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 PWM diff --git a/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch b/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch index b045d4a3cf..45a30f7acd 100644 --- a/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch +++ b/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch @@ -1,4 +1,4 @@ -From d512570ff756b751d74f27121ccd6784be182855 Mon Sep 17 00:00:00 2001 +From 65a1dab86ebddc9772731df5c32673238785b7b2 Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:25:02 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: Fix Rust formatting diff --git a/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch b/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch index 06d4f3cc31..2925a46886 100644 --- a/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch +++ b/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch @@ -1,4 +1,4 @@ -From b8e48fd0e9516c83f6a6193730b5d042ed5263bd Mon Sep 17 00:00:00 2001 +From 4053bab2d005ebc6eab1680de449edd8a6e5f903 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:35 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix clippy warning for redundant diff --git a/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch b/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch index b4384ef364..212c3eab71 100644 --- a/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch +++ b/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch @@ -1,4 +1,4 @@ -From e4ad935868f5592d06155265261be5934f1821ec Mon Sep 17 00:00:00 2001 +From 8a1293a6044b839a46bfd2af6ce741fffaec1cdd Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:34 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Use module_pwm_platform_driver! diff --git a/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch b/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch index f01d4fe843..581f11f37d 100644 --- a/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch +++ b/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch @@ -1,4 +1,4 @@ -From 04ac502626ab9c23c88cb52a8447f2a6d6871231 Mon Sep 17 00:00:00 2001 +From af00b8640fb223e6e97755df058706ff91f96ad7 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 9 Dec 2025 21:06:03 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix missing Kconfig dependencies diff --git a/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch b/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch index 4f6592382a..b70ceaaef4 100644 --- a/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch +++ b/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch @@ -1,4 +1,4 @@ -From c413ed4426b184f8cb2304ff2897825e2a215871 Mon Sep 17 00:00:00 2001 +From 1cfd24d0ebea3fd30addd6ab38dfb349a1ec08be Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:47 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add xtheadvector to the diff --git a/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch b/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch index 645a855fa1..b0ae390f9e 100644 --- a/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch +++ b/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch @@ -1,4 +1,4 @@ -From d86f79c2f13ca9a4c232cce2f5dd5020f18a9656 Mon Sep 17 00:00:00 2001 +From bd68ddac12b197d63d695ebee877c658babc4935 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:48 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add ziccrse for th1520 diff --git a/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch b/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch index 02c41e4add..bd025678fa 100644 --- a/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch +++ b/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch @@ -1,4 +1,4 @@ -From 6c54c277dfd8b9c53a91aac3aa08d80a40eef35d Mon Sep 17 00:00:00 2001 +From c97f4fa9442fe9725a615f5b29d980ecb8e34e1b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:49 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add zfh for th1520 diff --git a/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch b/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch index 1da5ef41e5..2c486fced0 100644 --- a/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch +++ b/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch @@ -1,4 +1,4 @@ -From 3ca9f9c1f974516ed56055f86fe810e70234d2e0 Mon Sep 17 00:00:00 2001 +From ddfa1f0d437d597ddc5ed035dbb6fd04295dd9a1 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:06 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM controller node diff --git a/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch b/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch index 16a6ff7a16..b5eca2e20a 100644 --- a/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch +++ b/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch @@ -1,4 +1,4 @@ -From 34e6c9de17b9ff861746760bfc9334e3fc3060cb Mon Sep 17 00:00:00 2001 +From 7df49938ca1e4c3188674cf01b6d943ceea80c9b Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:07 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM fan and thermal diff --git a/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch b/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch index 073023bb11..366f7e9343 100644 --- a/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch +++ b/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch @@ -1,4 +1,4 @@ -From 185f8436e47e0844df0a0d25fbb995a69a565fd1 Mon Sep 17 00:00:00 2001 +From 6a8f49b2e92014e689c4e68927683e244639e7c1 Mon Sep 17 00:00:00 2001 From: Lucas Zampieri Date: Fri, 24 Oct 2025 09:36:40 +0100 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: Add UltraRISC diff --git a/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch b/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch index a9e42fff55..0831bef573 100644 --- a/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch +++ b/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch @@ -1,4 +1,4 @@ -From 38033dfbe309976053db7684228a93e90a76f54f Mon Sep 17 00:00:00 2001 +From b013929e5a0773eea0cce650019592024dfacecb Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:41 +0100 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: Add diff --git a/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch b/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch index c47e05232b..a38920d845 100644 --- a/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch +++ b/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch @@ -1,4 +1,4 @@ -From 3f8b27c28b0516d4675130d799e52fe0e47cc190 Mon Sep 17 00:00:00 2001 +From 370b8af4c2f631e8d3a0e7984d878a7c80ed6d18 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:42 +0100 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Cache the interrupt diff --git a/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch b/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch index 35bf32dde3..50298bada1 100644 --- a/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch +++ b/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch @@ -1,4 +1,4 @@ -From 4ef8a6c6a0ad3046bd79c8e7ba68b55f65faba37 Mon Sep 17 00:00:00 2001 +From d347e2130641f7e7091dd8afbe67c9619baf88f0 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:43 +0100 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Add support for UltraRISC diff --git a/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch b/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch index d80cdc947a..bc65b7abfc 100644 --- a/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch +++ b/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch @@ -1,4 +1,4 @@ -From 88d1fb14b13933d5016b00a18582e2c2dec28c29 Mon Sep 17 00:00:00 2001 +From 5cfe296d78b80974d17bf71f4b20c59e5c4df2e7 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 2 Jan 2026 14:58:39 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: cpu_ops_sbi: smp_processor_id() returns diff --git a/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch index 8df22862a6..a73b5bae6d 100644 --- a/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ b/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -1,4 +1,4 @@ -From b73688a2f1f8a16a7bb9609da304ebfd1dd7f968 Mon Sep 17 00:00:00 2001 +From e9bf2921885bbc475e11a6f89d7d1325bf4ea382 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:29:59 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT diff --git a/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch b/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch index 398331aef3..38f0c36ca6 100644 --- a/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch +++ b/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch @@ -1,4 +1,4 @@ -From 10c6bee274527e1fa5cf933eade792a8269bfa6e Mon Sep 17 00:00:00 2001 +From 89018ba28165fc32aa888271948560c35503a2be Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:00 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: add optional diff --git a/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch b/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch index cb7815d689..cb75c0acf5 100644 --- a/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch +++ b/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch @@ -1,4 +1,4 @@ -From eef2e7554dce124c0d27d06663f545ebf8b06b4f Mon Sep 17 00:00:00 2001 +From ea61a74942a5004fa215d79c58105f1338ec541e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:01 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add optional reset support diff --git a/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch b/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch index 78d52fb913..64929819ae 100644 --- a/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch +++ b/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch @@ -1,4 +1,4 @@ -From 01d5441431b796aa0c7bef71294e87584b3a7ac2 Mon Sep 17 00:00:00 2001 +From e1c8bcfee6e779f426c1daae2fb82866708e10a9 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:02 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: switch predicates to bool diff --git a/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch b/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch index 2a381e6fb3..a3a82feb09 100644 --- a/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch +++ b/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch @@ -1,4 +1,4 @@ -From 513e5c7ca8e7b4847c1a9fa9328ecc1da6e03ca4 Mon Sep 17 00:00:00 2001 +From 981675f3ee85d491d051c4664c508128ac988504 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:03 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add a clock disable quirk diff --git a/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch b/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch index c71778c496..246aa58431 100644 --- a/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch +++ b/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch @@ -1,4 +1,4 @@ -From a5d94c358a562e2cf863fff92b78f0ee109abf10 Mon Sep 17 00:00:00 2001 +From 7c46eafe84df109f4c91da322c3c0936ca5e6f42 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:04 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: introduce sfa_size devtype data diff --git a/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch b/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch index f9a55c89ea..13087ca9aa 100644 --- a/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch @@ -1,4 +1,4 @@ -From 014a6255ae46191c6eae14aa9de40535b4226ff0 Mon Sep 17 00:00:00 2001 +From 53c83a343355c01284a123c0592f92e488eec006 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:05 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: support the SpacemiT K1 SoC diff --git a/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch b/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch index 8ad45c9e57..6fe980dae8 100644 --- a/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch +++ b/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch @@ -1,4 +1,4 @@ -From 0d6c9d0a071fcea507cb2b62195d329fbfd4e3fa Mon Sep 17 00:00:00 2001 +From f77dddee6ad705b31db5dd8e1d46b89de99b5994 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:35 -0600 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pci: spacemit: Introduce PCIe diff --git a/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch b/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch index 15f880c23c..c80fe8da68 100644 --- a/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch +++ b/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch @@ -1,4 +1,4 @@ -From e886894eecb01fde7c6d687a520c00f8f8c6577b Mon Sep 17 00:00:00 2001 +From a27cebcdff7f78becf2072cae2b951e1e7f41b1e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:37 -0600 Subject: [RUYI PATCH] UPSTREAM: PCI: spacemit: Add SpacemiT PCIe host driver diff --git a/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch b/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch index 9f87089128..07eb7775f3 100644 --- a/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch +++ b/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch @@ -1,4 +1,4 @@ -From dd167e5e356efc521fea95cca3dab9214d112f2f Mon Sep 17 00:00:00 2001 +From 1db3accfb97de5435d3b1a655351b544f98c89c2 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:17 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: dt-bindings: Add bindings for SpacemiT diff --git a/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch b/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch index 79edb29c56..7a21b86b45 100644 --- a/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch @@ -1,4 +1,4 @@ -From f80e4dd0f340bda7a0c1d1cbcb59d4a346aa00dd Mon Sep 17 00:00:00 2001 +From a978e202507f82d0e77d476e6346bc3100e2af3e Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:18 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: add i2s support for K1 SoC diff --git a/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch b/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch index 0efa4da8f2..2948efb926 100644 --- a/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch +++ b/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch @@ -1,4 +1,4 @@ -From affb820dfce75897605fbf89105fc1537a97d75b Mon Sep 17 00:00:00 2001 +From d14c1a3674a4d257ec1714aeb83e0c890a87e6fe Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 17 Sep 2025 08:59:07 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add UART pinctrl diff --git a/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch b/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch index 0351d09704..bfd2c0a2a3 100644 --- a/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch +++ b/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch @@ -1,4 +1,4 @@ -From 1df92e173f9dd68d0498d92fb07c15a5b2ddf8eb Mon Sep 17 00:00:00 2001 +From 09fc6e652c8500c58d3fe27c7be9bebf2b59bc5b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:54 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c8 adapter diff --git a/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch b/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch index 3b5e57ed41..0653225c30 100644 --- a/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch +++ b/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch @@ -1,4 +1,4 @@ -From b0c37d9383e9fff2cfae5d13e29a5b2fd134e33b Mon Sep 17 00:00:00 2001 +From 7aec3f89f4115172f971713a137996eabfdc10bb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:55 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define fixed regulators diff --git a/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch b/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch index 4b13e15e20..9a83a11db5 100644 --- a/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch +++ b/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch @@ -1,4 +1,4 @@ -From 7fc9ff12b887fdc874ebb28f553e807648b6a4d4 Mon Sep 17 00:00:00 2001 +From cc04c613686436bcdfd3c38b6ae7ea2d7241c0d7 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:56 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define regulator diff --git a/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch b/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch index c64be604a7..0e7a5aedef 100644 --- a/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch +++ b/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch @@ -1,4 +1,4 @@ -From a276be6d58f16c9c62bd6c0f76f6b2133fcfff5b Mon Sep 17 00:00:00 2001 +From 26663ffe8f0db3a92cf070903f9191745b97444f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:37 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c2 adapter diff --git a/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch b/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch index 5c72618d50..0d0bfb67b2 100644 --- a/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch +++ b/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch @@ -1,4 +1,4 @@ -From c34d30a8bde9d30953c0d83f0fa993d925f5e038 Mon Sep 17 00:00:00 2001 +From fffc0e28825613d507f1e6731d2f011415adf550 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:38 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c02 eeprom on diff --git a/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch b/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch index 3e089bc47b..f014ffc559 100644 --- a/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch +++ b/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch @@ -1,4 +1,4 @@ -From d0ff2694bd729289ac0e0a95bd0ad9c82b10cbe1 Mon Sep 17 00:00:00 2001 +From 27fd4e9ef652768f524108ac9cb344f6b83be392 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:39 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on diff --git a/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch b/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch index 2f6950c455..6a5e851bdf 100644 --- a/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch +++ b/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch @@ -1,4 +1,4 @@ -From 13fa4b662d56827d91fb4cbc78cbaf44253e90c9 Mon Sep 17 00:00:00 2001 +From 3f7306681f2f070c4888af54efa4240ca6d758a8 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 22 Oct 2025 20:18:38 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add Ethernet and PDMA to diff --git a/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch b/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch index e1ebb490cb..51c6e7be59 100644 --- a/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch +++ b/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch @@ -1,4 +1,4 @@ -From 3dafd093bd3316afd9db38030ed61ebb2382f469 Mon Sep 17 00:00:00 2001 +From 9e47855f7a253279381f70b063ba245703e3814d Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 23 Oct 2025 15:28:30 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add MusePi Pro board diff --git a/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch b/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch index 1d90bd8999..4e53d6e7ad 100644 --- a/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch +++ b/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch @@ -1,4 +1,4 @@ -From ba2b866292f1f2f274ff75a54e87fe7bc5dad3e2 Mon Sep 17 00:00:00 2001 +From 6a39505c993f5f01158a6f6a70f4ad76c6db5234 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:06 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable K1 SoC QSPI on diff --git a/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch b/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch index 6288d13917..845dd10c3b 100644 --- a/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch +++ b/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch @@ -1,4 +1,4 @@ -From 24c1c297e0c77c81c2e3a9ed9690f3e133986a22 Mon Sep 17 00:00:00 2001 +From a99210e73092a2a51e626e76bb6eb8ae63c8eb26 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 12 Nov 2025 04:44:42 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add OrangePi R2S board diff --git a/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch b/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch index d6b11da6e5..af827b2735 100644 --- a/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch +++ b/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch @@ -1,4 +1,4 @@ -From 1831ac73812e9bb0337b60cf0cbe5e61baaf4769 Mon Sep 17 00:00:00 2001 +From d6478eccb6e7703c6cda7c1146e5ed08bd362aaa Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:43 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder i2c2 node diff --git a/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch b/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch index 128376f03e..db9f77e153 100644 --- a/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch +++ b/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch @@ -1,4 +1,4 @@ -From 30931c3912167e96f982909390b4cb13d61548d5 Mon Sep 17 00:00:00 2001 +From 9a289212a972f7808021f2d5895dbff5dc2a5404 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:44 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define all missing I2C diff --git a/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch b/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch index 637f8129fd..a117d16322 100644 --- a/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch +++ b/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch @@ -1,4 +1,4 @@ -From 915b04c620188a1aac7cc9e8481bd1dc3069817d Mon Sep 17 00:00:00 2001 +From ea689de88bfd93717b97a988d285c2bcfee10d08 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 18 Nov 2025 14:08:06 +0800 Subject: [RUYI PATCH] UPSTREAM: rtc: spacemit: MFD_SPACEMIT_P1 as dependencies diff --git a/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch b/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch index 8765e4955a..0ac16df408 100644 --- a/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch +++ b/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch @@ -1,4 +1,4 @@ -From 6069d468c347c12814556df14bbe53dade5799be Mon Sep 17 00:00:00 2001 +From 22786d133cae491a4a2d7486ced9707305762fd1 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 27 Oct 2025 13:48:05 +0800 Subject: [RUYI PATCH] UPSTREAM: mfd: simple-mfd-i2c: Remove select I2C_K1 from diff --git a/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch b/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch index 29f66cd23f..a9a2a89eea 100644 --- a/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch +++ b/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch @@ -1,4 +1,4 @@ -From eef8f9cc817fec7a4c2229a9b9ee475a0efcf53b Mon Sep 17 00:00:00 2001 +From 6469b6c2dfd9d66deecc8708629891e31602adc2 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:01:59 +0100 Subject: [RUYI PATCH] UPSTREAM: driver: reset: spacemit-p1: add driver for diff --git a/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch b/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch index 9e03454da1..ab98a6d4ca 100644 --- a/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch +++ b/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch @@ -1,4 +1,4 @@ -From a33608232c9c99d13d018635c30ee0ff1983de7e Mon Sep 17 00:00:00 2001 +From 719033a111f6554842d971b2a40a5ef67c69d4d3 Mon Sep 17 00:00:00 2001 From: Yunhui Cui Date: Tue, 16 Dec 2025 09:47:19 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: remove irqflags.h inclusion in diff --git a/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch b/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch index 0fb3f34661..ee28c704dc 100644 --- a/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch +++ b/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch @@ -1,4 +1,4 @@ -From 34f41ea98d21a5605f1d5973259656f6e6557de0 Mon Sep 17 00:00:00 2001 +From db019f57db04d4ece4511823ca49186776ac1572 Mon Sep 17 00:00:00 2001 From: Zongmin Zhou Date: Thu, 20 Nov 2025 17:58:31 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv/atomic.h: use RISCV_FULL_BARRIER in diff --git a/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch b/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch index 0604111102..cf28af6f0f 100644 --- a/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch +++ b/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch @@ -1,4 +1,4 @@ -From 8030689f50a72fc225dd6c31ad77d6b868549463 Mon Sep 17 00:00:00 2001 +From 476b5a142396e7b932e3fd2d8af5632718cfb3d4 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:08 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Sanitize output on errors diff --git a/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch b/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch index c249232713..7a841d166c 100644 --- a/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch +++ b/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch @@ -1,4 +1,4 @@ -From cf1dda8a91f6866dead5cfac3205be1ea706a065 Mon Sep 17 00:00:00 2001 +From 3b06167014830657863b7333d0ed9be00567cf8f Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:09 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Provide helper to set pitch diff --git a/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch b/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch index d3d98f5867..56f4549640 100644 --- a/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch +++ b/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch @@ -1,4 +1,4 @@ -From 5a54ac19c87347a2165595055cab86383cefac4f Mon Sep 17 00:00:00 2001 +From 8050563879938dc6a528fb8e06da2fa438e114f5 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 16 Sep 2025 10:36:22 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/hypervdrm: Use vblank timer @@ -20,7 +20,7 @@ Signed-off-by: Han Gao 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -index 945b9482bcb3..6e6eb1c12a68 100644 +index 86696a9a32c5..208fb14e837a 100644 --- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c @@ -19,6 +19,8 @@ @@ -56,7 +56,7 @@ index 945b9482bcb3..6e6eb1c12a68 100644 }; static int hyperv_plane_atomic_check(struct drm_plane *plane, -@@ -321,6 +328,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) +@@ -322,6 +329,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) return ret; } diff --git a/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch b/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch index d6a9555b97..cdab38c37e 100644 --- a/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch +++ b/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch @@ -1,4 +1,4 @@ -From 82e88d4cfa7af6b1ae6ffc952a7d1903d2c8e3ea Mon Sep 17 00:00:00 2001 +From 3a566409d11abdf4ed3f08d0621eb8a348aa265f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:06 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi flag diff --git a/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch b/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch index 46bc6278e3..df245d7bd7 100644 --- a/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch +++ b/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch @@ -1,4 +1,4 @@ -From 4f4b809bc01cd7d00cf117b7e99a2a2b18a9d9f9 Mon Sep 17 00:00:00 2001 +From 9442e52784b43c32211b4e810635c32d91c7d43c Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:07 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Check the device specific address diff --git a/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch b/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch index 02e46aef2a..e53d537b75 100644 --- a/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch +++ b/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch @@ -1,4 +1,4 @@ -From 9dcbec59b17ddb9befc7e35efebe9f69ebeb2745 Mon Sep 17 00:00:00 2001 +From e81fc8efac9cdfbf8941cd958c7f14a70b05ced4 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:08 +0800 Subject: [RUYI PATCH] UPSTREAM: drm/radeon: Make MSI address limit based on diff --git a/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch b/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch index 5f8bf385cf..6a0b93617d 100644 --- a/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch +++ b/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch @@ -1,4 +1,4 @@ -From ed396d380559185d5e0dfad4f40fc5cd8c0382d1 Mon Sep 17 00:00:00 2001 +From e9d1d6424ea9a52e0ce1580012d17aa48ebc283a Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:09 +0800 Subject: [RUYI PATCH] UPSTREAM: ALSA: hda/intel: Make MSI address limit based diff --git a/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch b/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch index 9eb8c66514..1036dd7a87 100644 --- a/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch +++ b/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch @@ -1,4 +1,4 @@ -From f4bd9635e84e4d37d8e56a08bbd43581faeddc96 Mon Sep 17 00:00:00 2001 +From e2b86dfca9b04a702a70dd90f7c6af620e01f74e Mon Sep 17 00:00:00 2001 From: Michael Orlitzky Date: Wed, 7 Jan 2026 06:29:22 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: enable hardware clock diff --git a/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch b/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch index 0d1f78cb37..b5f9d9be9b 100644 --- a/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch +++ b/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch @@ -1,4 +1,4 @@ -From 4a0cc33492f3fc8e642380ddcf6f355a4ec6cfc1 Mon Sep 17 00:00:00 2001 +From d16888fafcae066525f88c792e413cc3400018cc Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:26 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT node diff --git a/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch b/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch index 0d20c75013..4cf0b017ff 100644 --- a/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch +++ b/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch @@ -1,4 +1,4 @@ -From 05c376f7568773671fcd81b7cc92e365126410d0 Mon Sep 17 00:00:00 2001 +From bf4a8b5e720e6d5a59e0bb296f971c97f2e459ff Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:27 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: fix the node order of diff --git a/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch index 5f97d6ec8f..21e30d751b 100644 --- a/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ b/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -1,4 +1,4 @@ -From 7b375e6d39b2d52853eaff4e1f70555adadc5253 Mon Sep 17 00:00:00 2001 +From 44e1df9c4c4219596fdc954025a00aa104ddd99e Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:53 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter for diff --git a/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch b/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch index 1a8e836f5a..d90930252e 100644 --- a/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch +++ b/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch @@ -1,4 +1,4 @@ -From 4274a55a8dac98543297e2416ea7c7f40c4f641a Mon Sep 17 00:00:00 2001 +From 0c38553b279ac02b2a359a7b4819fb73a88ea124 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:54 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define fixed regulators diff --git a/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch index 1be8407564..d905650557 100644 --- a/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ b/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -1,4 +1,4 @@ -From 0af31fdff636f13c96b48c14fe2dce73dbf55dfd Mon Sep 17 00:00:00 2001 +From 0158a4cea182893db9285ae888a490568bfb0c99 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:55 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC diff --git a/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch b/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch index 51bfee722a..65e1676bda 100644 --- a/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch +++ b/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch @@ -1,4 +1,4 @@ -From 0cb6f99b1dee1c78c2cb66de8612480e505be4b7 Mon Sep 17 00:00:00 2001 +From 2b6a2bbdc6760821fd7a9064c53288bc35c8aef3 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:27 -0600 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT diff --git a/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch b/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch index 9b069cb469..1cbf2f0e1e 100644 --- a/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch +++ b/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch @@ -1,4 +1,4 @@ -From 69d5a6d06db546fbe5f911a20eff130b7eb44927 Mon Sep 17 00:00:00 2001 +From 7301cd7cc4d2125fd7d73e478e7953cb4b1231d4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:28 -0600 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe PHY diff --git a/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch b/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch index 78fc295801..a28b820967 100644 --- a/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch +++ b/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch @@ -1,4 +1,4 @@ -From ec3144e3a9c21e5c60712fe8b72eb68e9f8c120f Mon Sep 17 00:00:00 2001 +From b7b89bae19eacd45891217afe462435355afe7c4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:29 -0600 Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY diff --git a/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch b/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch index 4a013ca623..23a912fdf4 100644 --- a/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch +++ b/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch @@ -1,4 +1,4 @@ -From 1fce0749e1bf54d192dde74d2c105f51a35ab4d4 Mon Sep 17 00:00:00 2001 +From cb491457b06017d38dedbedfb07cdec5c77a8aeb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:30 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator diff --git a/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch b/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch index ba9f3b4975..ef609732b6 100644 --- a/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch +++ b/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch @@ -1,4 +1,4 @@ -From cca8801247fe6e5967002d5519f537917e6a9bf5 Mon Sep 17 00:00:00 2001 +From 8ebfab2105d336f53b29a5971f076b60a2ee5e69 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:31 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related diff --git a/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch b/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch index c158eae42a..edc74d65d0 100644 --- a/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch +++ b/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch @@ -1,4 +1,4 @@ -From f388858d4abee4592cdb3e48a66ed3c681b5801f Mon Sep 17 00:00:00 2001 +From 2b4b7b00547de7db090321cbe060f0785bbe1c2b Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:51 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: add optional diff --git a/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch index 8df67ed42a..d3b292f234 100644 --- a/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch +++ b/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch @@ -1,4 +1,4 @@ -From ed3b67eff1ecc6048f6b6a76bff5a97ff2abb964 Mon Sep 17 00:00:00 2001 +From 45a6bb02347afa594bbae7babfc102a290c50a62 Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:52 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: k1: add reset support diff --git a/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch b/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch index 19f85450fa..176bb49c3f 100644 --- a/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch +++ b/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch @@ -1,4 +1,4 @@ -From 3aa8e6c84101edb3c499478758e4a82cc230af36 Mon Sep 17 00:00:00 2001 +From 657d162bba66c43fc3a57fcd6e53ed141c7625ef Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:53 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add reset property diff --git a/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch b/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch index eae9b4c51d..1e3c5f1464 100644 --- a/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch +++ b/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch @@ -1,4 +1,4 @@ -From 9d8fbb22b0d4fc7ec75661abcee3d71ca556f67a Mon Sep 17 00:00:00 2001 +From ad6fa0373403bcbf2e3a081de0862952e93bf85a Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 17 Oct 2025 22:49:52 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY diff --git a/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch b/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch index dd0a27e19d..ce5ed07b8d 100644 --- a/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch +++ b/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch @@ -1,4 +1,4 @@ -From 6fe75e59d1834ffff41681bcd52b6a1a83446f3e Mon Sep 17 00:00:00 2001 +From 978937fc8ad0698573d5ac3329dbeda4e1271432 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 17 Oct 2025 22:49:53 +0800 Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY diff --git a/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch b/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch index dc4568a151..33133ebf9d 100644 --- a/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch +++ b/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch @@ -1,4 +1,4 @@ -From 11169d35e4ee7faf38d3e24da227dd6ca781964d Mon Sep 17 00:00:00 2001 +From 2b433a56c490efe1d3b7f1959b4a3d984435e597 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:02 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for K1 diff --git a/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch b/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch index f327e7bfc3..3ade8356be 100644 --- a/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch +++ b/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch @@ -1,4 +1,4 @@ -From f38cd0cdcf8e8fecf3db47eb57caf5849e92aa36 Mon Sep 17 00:00:00 2001 +From 60ab55f64eb13e9141c5bcfb1ff3cc4e60bb4da3 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:03 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0 diff --git a/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch b/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch index ada9b260b3..160d49673d 100644 --- a/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch +++ b/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch @@ -1,4 +1,4 @@ -From 35bdc15291717adfaa52c4c9d060b5da8fac5ddf Mon Sep 17 00:00:00 2001 +From 10b5f752d64626320eaaf74011f5529216f78b0c Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:04 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on diff --git a/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch b/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch index 3e646a9468..38f67b4381 100644 --- a/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch +++ b/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch @@ -1,4 +1,4 @@ -From 58100bb2e0beb94bf6f7d14ee1fbc0ba755686ab Mon Sep 17 00:00:00 2001 +From 478df24a60b0581f53a916963c82d8343aafd642 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:22 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: convert drive diff --git a/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch b/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch index 39afc5d902..d442eb6694 100644 --- a/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch +++ b/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch @@ -1,4 +1,4 @@ -From 2038df152864bcab073a9afa519466c854b79d21 Mon Sep 17 00:00:00 2001 +From 5faf2537137da89b63a6dd0f45db560e43884bb2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:23 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC diff --git a/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch b/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch index 36707ca688..026ce4fb40 100644 --- a/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch +++ b/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch @@ -1,4 +1,4 @@ -From fa64b4a9c989f85c6522c5cb06ef127c6dab3d27 Mon Sep 17 00:00:00 2001 +From 2ca77029c54bb4a4d9a85faca5542299e38f0282 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:24 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: add initial pin support diff --git a/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch b/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch index 1885c27345..fe01a940c1 100644 --- a/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch +++ b/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch @@ -1,4 +1,4 @@ -From 57250a2d8e90085ff17ab7670d16519f41b64f28 Mon Sep 17 00:00:00 2001 +From dd0d5ad91e6226005daefdfc363c05a7c4089dfd Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:25 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: adjust drive strength diff --git a/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch b/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch index b203991c2d..d3156e2bc5 100644 --- a/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch +++ b/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch @@ -1,4 +1,4 @@ -From f3a4b85d5279965fc53d7163a005b2e64ff1327a Mon Sep 17 00:00:00 2001 +From 4d3f2ca4b8bf03c8f5764bd4e3a4755a87d96507 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:38 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon diff --git a/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch b/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch index 377503eb76..0b5aeb4e99 100644 --- a/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch +++ b/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch @@ -1,4 +1,4 @@ -From 0a07233b0f550ed136cd45130d55ac5e079fc795 Mon Sep 17 00:00:00 2001 +From 4ca7dd892e3dbd74973376cc721c85ece7df006b Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:39 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: support I/O power domain diff --git a/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch b/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch index 8f6837bba8..a953ffe5db 100644 --- a/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch +++ b/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch @@ -1,4 +1,4 @@ -From 404911e71521a30847ea8198f0e48c7d6c92dac5 Mon Sep 17 00:00:00 2001 +From 7e7f51d3fc168ccbde756bef719027fd2756f3b9 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:40 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pinctrl: update register diff --git a/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch b/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch index 9c1db3eb89..8b8b633d02 100644 --- a/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch +++ b/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch @@ -1,4 +1,4 @@ -From 33a192939d2dd110bc17a0f1c65a5c654c617d16 Mon Sep 17 00:00:00 2001 +From 1f57c45be3689590c431a322325a942d2901e7ec Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 25 Dec 2025 14:24:20 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: update ratified version of diff --git a/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch b/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch index 03b356c1c3..8632f73349 100644 --- a/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch +++ b/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch @@ -1,4 +1,4 @@ -From 8b082ec91bd4cfaf11f3a1b69d1b66ea599ba3f1 Mon Sep 17 00:00:00 2001 +From 8425255e16de969339af85fd2795543cf2be9c01 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:18 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add B ISA extension diff --git a/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch b/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch index f6b09dc50b..c652ef40f1 100644 --- a/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch +++ b/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch @@ -1,4 +1,4 @@ -From 293192824603c354264f56113a64fc91d889d750 Mon Sep 17 00:00:00 2001 +From 6cbec3202b4d49296d75d3affadb5eefe4743984 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:19 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add descriptions for diff --git a/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch b/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch index 347e39618f..099030ead4 100644 --- a/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch +++ b/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch @@ -1,4 +1,4 @@ -From 9f1f119c5d51420861951a5660e8714b87fcf2ce Mon Sep 17 00:00:00 2001 +From d0ef39b0cd8f2f7fdd998909bc6ee021fe3ac16c Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:20 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Ssccptr, Sscounterenw, diff --git a/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch b/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch index f4ee934072..47fccd8d5c 100644 --- a/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch +++ b/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch @@ -1,4 +1,4 @@ -From 1642e810c6656b4e941561a7bb884e733c44a2f6 Mon Sep 17 00:00:00 2001 +From 1d68e1c298a704de7dcb9aa56f680650c887b572 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:21 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Sha and its comprised diff --git a/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch b/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch index 7eef93f3d7..a783a6a155 100644 --- a/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch +++ b/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch @@ -1,4 +1,4 @@ -From 815614b3265facda28aaa4572e120d8f049a9c79 Mon Sep 17 00:00:00 2001 +From 6c758ac967a8de6127491a395f361b7031c10667 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:59 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA diff --git a/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch b/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch index 1f0aba5728..908e74991b 100644 --- a/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch +++ b/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch @@ -1,4 +1,4 @@ -From 039b44e9b855295ac8945486ffea47d65240d000 Mon Sep 17 00:00:00 2001 +From e145877df03e9a22048d70a6df37565741c52bef Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:19:00 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA diff --git a/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch b/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch index 8f2845d570..9cc4198638 100644 --- a/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch +++ b/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch @@ -1,4 +1,4 @@ -From 3a49674fb8ec24236b9a789e322ccc05b66c4d65 Mon Sep 17 00:00:00 2001 +From da3921d821fb8fc226467e03f7c4e9547f1bebef Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:40 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU diff --git a/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch b/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch index 10acec0266..ad33a9bcb8 100644 --- a/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch +++ b/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch @@ -1,4 +1,4 @@ -From 9e4be2e7c734325e83668eba93f9e2dbc1220efa Mon Sep 17 00:00:00 2001 +From de3d7ed88147aebae73ec5f42e045e4238eae7a3 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:41 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT diff --git a/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch index f8b908b4e1..581f2654b6 100644 --- a/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ b/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -1,4 +1,4 @@ -From 57ea95edd2da52d808cbd5a6d874d1cb368dea05 Mon Sep 17 00:00:00 2001 +From 0c563395177127fadd547b5db1ccfd04a9c16977 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:42 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add diff --git a/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch index 9699a897cf..7bae75be65 100644 --- a/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ b/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -1,4 +1,4 @@ -From 7d7a00a794501c279b94f46e44c33a60cc0ecf71 Mon Sep 17 00:00:00 2001 +From ef6567dabee9b15b35444d738ddd223bba73bbaf Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:43 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add diff --git a/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch b/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch index 0f66a78fa3..eb346ddbd0 100644 --- a/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch +++ b/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch @@ -1,4 +1,4 @@ -From 90385ee4dee92d3b318cb4a03b5de245c87b06f2 Mon Sep 17 00:00:00 2001 +From 8e6028a04fddc05779e162a8306ec8f0e290946a Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:44 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and diff --git a/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch b/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch index f038974db6..49c6e610c1 100644 --- a/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch +++ b/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch @@ -1,4 +1,4 @@ -From b4a0b52d7cdbe329b44301f63847faf1c8631060 Mon Sep 17 00:00:00 2001 +From d8089feae87ad613be7fe448ae79b3f785e8744b Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:45 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add initial support for diff --git a/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch b/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch index f252517e9d..47897f776b 100644 --- a/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch +++ b/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch @@ -1,4 +1,4 @@ -From 377151dae3f25558fd27556e52c4f0854c988c8b Mon Sep 17 00:00:00 2001 +From 61e63997cecc9eb549744cbe7688cd6f77265382 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:46 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board diff --git a/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch b/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch index ec9ea29ffd..afef29e668 100644 --- a/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch +++ b/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch @@ -1,4 +1,4 @@ -From 2503ec0c2acbeba44796cf9a39cd65176b1b41b8 Mon Sep 17 00:00:00 2001 +From 75570444f9b7f29881d04479bc6f1727d37f53b6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 19 Dec 2025 09:28:18 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: Hide common clock driver from diff --git a/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch b/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch index 02f0837e38..2b42a0972e 100644 --- a/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch +++ b/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch @@ -1,4 +1,4 @@ -From 5fd55e32b05d7b1c89471933925ea500ab96dc8f Mon Sep 17 00:00:00 2001 +From 58da181f8fee4e3f7af2a1cfe8708acb62d1b3f2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 21:52:08 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: prepare common ccu header diff --git a/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch b/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch index 07bf26b3d3..5dc8e89514 100644 --- a/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch +++ b/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch @@ -1,4 +1,4 @@ -From 882ae01390f0d71acbaa666ad62660f1690558cb Mon Sep 17 00:00:00 2001 +From c52fe85b94bae057810710b424cbb6f7497aa8d7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 08:07:23 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: extract common ccu functions diff --git a/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch b/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch index 195fb33162..b8301bbf76 100644 --- a/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch +++ b/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch @@ -1,4 +1,4 @@ -From 597e2f7d18294ec1b59dc52d5be6ac61f4ef6075 Mon Sep 17 00:00:00 2001 +From 1dadb848fd39698b7cecc8d424161d3a1652a452 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 3 Jan 2026 14:14:36 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: add platform SoC prefix to diff --git a/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch b/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch index 1bbdfdf4b9..f2bd1b002d 100644 --- a/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch +++ b/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch @@ -1,4 +1,4 @@ -From 195ce637ead66f8aff72ecf491637b937ab32985 Mon Sep 17 00:00:00 2001 +From 37095deb7ea0ea8d388930e4fdf433a994d29c51 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 05:34:39 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: fix auxiliary device id diff --git a/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch b/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch index eb8a0da4ac..5b0b3c0bbf 100644 --- a/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch +++ b/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch @@ -1,4 +1,4 @@ -From 4887997f9fc66c19a62763d21f3beb9036a5470b Mon Sep 17 00:00:00 2001 +From 49261bf8d197d630f32c6a54165fcbe3aad3c5cc Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 1 Nov 2025 20:56:42 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: k3: add clock diff --git a/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch b/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch index 3bd158963f..96035ae024 100644 --- a/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch +++ b/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch @@ -1,4 +1,4 @@ -From f461f20d8d5d33bdf1d9fa07acf5a6337f03e57c Mon Sep 17 00:00:00 2001 +From 7c8f2552576b5ef6a1ae9a1bd2b110a50dcf3633 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 31 Oct 2025 20:40:46 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_mix: add inverted enable diff --git a/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch b/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch index 6dfcedf96e..2ddb21e2b7 100644 --- a/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch +++ b/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch @@ -1,4 +1,4 @@ -From a7ce4c7a2f5e9b248b21befc2f291b0d3ae3b195 Mon Sep 17 00:00:00 2001 +From f7657a9e6b3d91927ebb7a35c3f3092378c5f8aa Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 27 Oct 2025 21:41:24 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_pll: add plla type clock diff --git a/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch b/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch index 8ce677d1e4..a98118158f 100644 --- a/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch +++ b/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch @@ -1,4 +1,4 @@ -From 22c56093a5cbcc8d011f81d4523ee8160d5caa5f Mon Sep 17 00:00:00 2001 +From c5d576f1d3fffff794dcb2f9bfce1fd8afbbef56 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 20 Dec 2025 21:28:15 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: extract common header diff --git a/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch b/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch index ca7b6c2396..3125f4a4ed 100644 --- a/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch +++ b/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch @@ -1,4 +1,4 @@ -From 878e4e3217cc3b8b51d6d5480b8c6c8120d47144 Mon Sep 17 00:00:00 2001 +From dab0ffb790023615ccdc8e736b12d107c416cc83 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sun, 2 Nov 2025 21:17:17 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: add the clock tree diff --git a/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch b/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch index c049403590..0e13a0bee6 100644 --- a/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch +++ b/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch @@ -1,4 +1,4 @@ -From c8b8aab18243d5ad3ee4a6b980f1448aee344adb Mon Sep 17 00:00:00 2001 +From 566fcedda50493fdac4cf1d88354555164577b90 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:49 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: Add K3 reset diff --git a/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch b/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch index 6775e0de91..c8f32ba7a9 100644 --- a/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch +++ b/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch @@ -1,4 +1,4 @@ -From f58dcbda59da2a11300427e92f4c1abb7c6898f7 Mon Sep 17 00:00:00 2001 +From e0766e7503cd6e4f874013061c4df306cf4a9540 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:50 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: Create subdirectory for SpacemiT diff --git a/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch b/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch index 326c078c60..5218ff3c62 100644 --- a/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch +++ b/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch @@ -1,4 +1,4 @@ -From 1928fc1030c03e43f009ef60762dac1829c39b0c Mon Sep 17 00:00:00 2001 +From b2aa1a3066056632c7182ef5ac38340b5b14f5f9 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:51 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Extract common K1 reset code diff --git a/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch b/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch index 3e39a6ab56..251d00a39b 100644 --- a/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch +++ b/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch @@ -1,4 +1,4 @@ -From ba7026a22c43e830be9a0dccce75c3867b2bcaad Mon Sep 17 00:00:00 2001 +From 4c225ec987cb2053efdd142d8abf8bb02ebb1121 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:52 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Add SpacemiT K3 reset driver diff --git a/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch b/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch index 87f1321e5c..fc4d1c180c 100644 --- a/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch +++ b/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch @@ -1,4 +1,4 @@ -From 69b50555993d0e015534df599be1be5f756f84ea Mon Sep 17 00:00:00 2001 +From 404eff5e632be9663a75c9d1c490d8f56b121d6b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 6 Jan 2026 11:09:32 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: gpio: spacemit: add compatible diff --git a/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch b/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch index 7b6a45b12a..e442687036 100644 --- a/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch @@ -1,4 +1,4 @@ -From 409dadffdee997565a81b01180b046890adbdd47 Mon Sep 17 00:00:00 2001 +From 5926baabc063083c74e19f79f6caa78d3830e043 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 6 Jan 2026 11:09:33 +0800 Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit: Add GPIO support for K3 SoC diff --git a/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch b/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch index a2882d0c20..8f33f33fb9 100644 --- a/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch +++ b/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch @@ -1,4 +1,4 @@ -From ea85c56c78cbe48a0e645e57bb5d0151fa6f9bfa Mon Sep 17 00:00:00 2001 +From c0f9160d762fe57a9b53602372b37198d2ad5fc2 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 20 Jan 2026 18:00:01 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Disable ETH PHY sleep diff --git a/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch b/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch index 412075183b..46720dd038 100644 --- a/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch +++ b/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch @@ -1,4 +1,4 @@ -From 8731712faebb3034f523e3ed6e95191f5e47a01b Mon Sep 17 00:00:00 2001 +From 773b8c05e06091b578891911eeff117b405029a2 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:10 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: clock: thead,th1520-clk-ap: Add diff --git a/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch b/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch index e28d1d6f4f..64f304df30 100644 --- a/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch +++ b/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch @@ -1,4 +1,4 @@ -From 43765d604a0ac503f549b2772fc89a67b6df8779 Mon Sep 17 00:00:00 2001 +From 633624709863afc1b51408b875f42181a2e72fb2 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:12 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add C910 bus clock diff --git a/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch b/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch index 0f3eeb5de1..ce108a583e 100644 --- a/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch +++ b/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch @@ -1,4 +1,4 @@ -From 00eda1e45b3379884782a9a27d245fcff13f8772 Mon Sep 17 00:00:00 2001 +From 45fffc60883bc1f85479379c30d0c9771bf2d73b Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:13 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support setting PLL diff --git a/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch b/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch index 2518407886..628f0a6d60 100644 --- a/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch +++ b/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch @@ -1,4 +1,4 @@ -From 17338e1f386a810ea7bbe685d7cf3953dae6a51f Mon Sep 17 00:00:00 2001 +From 52617b1d3610227d206fb38f5fde1cfeeb213fbb Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:14 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add macro to define diff --git a/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch b/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch index 5e088a3818..4aa1be25ed 100644 --- a/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch +++ b/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch @@ -1,4 +1,4 @@ -From fc08e30c489223facf41c8c180c1d3685bad9ee9 Mon Sep 17 00:00:00 2001 +From bc39dc8773ca6dc48b317957a658017dbde02f04 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:15 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support CPU frequency diff --git a/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch b/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch index ee84bea6d5..f0b4698266 100644 --- a/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch +++ b/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch @@ -1,4 +1,4 @@ -From 216580fd5ff0f2f9d1b045a0eebd53199b169c09 Mon Sep 17 00:00:00 2001 +From 8f647c44bb22dd0196ff6853795c4f0184e64b0f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 1 Feb 2026 18:00:01 +0800 Subject: [RUYI PATCH] UPSTREAM: net: spacemit: display phy driver information diff --git a/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch b/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch index 71279bcd12..c255e2902b 100644 --- a/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch +++ b/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch @@ -1,4 +1,4 @@ -From a000c3124b2434f1d7da679574181a5b8295c9b8 Mon Sep 17 00:00:00 2001 +From c782e1f412db9ce5888fcbe1308dba4c872f3c6f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 27 Jan 2026 10:58:49 +0800 Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Use PDR for pin direction, diff --git a/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch b/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch index 315761b942..acdbf52e2f 100644 --- a/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch +++ b/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch @@ -1,4 +1,4 @@ -From 9a9a68a7eddae8077db583fd6db0e31a7e837eab Mon Sep 17 00:00:00 2001 +From aa414e48229dc861d14cbbc8f68b96518d390f55 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Fri, 26 Dec 2025 11:32:27 -0600 Subject: [RUYI PATCH] UPSTREAM: phy: Kconfig: spacemit: add COMMON_CLK diff --git a/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch b/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch index 661b7fce58..458610c6be 100644 --- a/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch +++ b/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch @@ -1,4 +1,4 @@ -From 13956aef479172118fb402bab2ecea2f30a4a744 Mon Sep 17 00:00:00 2001 +From a0a9fabc15452e81c179b036d17a57ed00e1ba9d Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 25 Dec 2025 15:46:32 +0800 Subject: [RUYI PATCH] UPSTREAM: mfd: Kconfig: Default MFD_SPACEMIT_P1 to 'm' diff --git a/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch index f0ab6e429d..a272afc143 100644 --- a/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch +++ b/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch @@ -1,4 +1,4 @@ -From c37e910069a44317c77ac4d11b37028e5c7a3473 Mon Sep 17 00:00:00 2001 +From a4fc20e9548ce112196421b63ebe0ae151978397 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 23 Dec 2025 10:24:51 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: sdhci: add reset support diff --git a/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch b/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch index d3ca21faa5..0a8bbb6113 100644 --- a/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch +++ b/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch @@ -1,4 +1,4 @@ -From cbbdae1821a5dd4f90a95e88d5c536f2421da1b6 Mon Sep 17 00:00:00 2001 +From f2ab06c62c043be194f5704ea040192c919d5ab1 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Mon, 3 Nov 2025 11:18:13 -0500 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Fix call to diff --git a/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch b/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch index a2ed1e4b8d..ff85f56c29 100644 --- a/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch +++ b/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch @@ -1,4 +1,4 @@ -From d25027971bf83bf11dd914b3ce914fa9ada558c4 Mon Sep 17 00:00:00 2001 +From 01c7afb37293f8274d577acd592a1c6f97b8fbef Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Wed, 4 Feb 2026 01:21:48 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: diff --git a/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch b/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch index b6309ec5fd..8508268b39 100644 --- a/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch +++ b/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch @@ -1,4 +1,4 @@ -From 8c3cf0715b0fdf641d78f56c2a4a207b6fb93525 Mon Sep 17 00:00:00 2001 +From 2aa0cd948f924b6efe91a62370729599c711b60c Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 3 Feb 2026 20:16:12 +0100 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Handle number of hardware diff --git a/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch b/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch index ec4bffaa6b..d60263eb5b 100644 --- a/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch +++ b/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch @@ -1,4 +1,4 @@ -From fd2ed2a093642f9ae52054344b23d1c512e4d4b6 Mon Sep 17 00:00:00 2001 +From 395317c0c69e903fa5a663ebf87b3f57ee0c3aa7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 9 Jan 2026 19:34:30 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Use multiple iATU windows for diff --git a/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch b/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch index 35a46d601c..6bc42d0c73 100644 --- a/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch +++ b/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch @@ -1,4 +1,4 @@ -From b88d7d9315cd6748d47a8ced520004d8f68ec0fc Mon Sep 17 00:00:00 2001 +From 1474b5e2b184b4ebd68e60bf501ee8c8940bbfc2 Mon Sep 17 00:00:00 2001 From: Thomas Gerner Date: Tue, 20 Jan 2026 09:59:26 +0100 Subject: [RUYI PATCH] UPSTREAM: pinctrl: th1520: Fix typo diff --git a/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch b/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch index 88cfd245f1..e11d1b87ef 100644 --- a/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch +++ b/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch @@ -1,4 +1,4 @@ -From e3974191639e3270eddc65bb437b729a750e5dc7 Mon Sep 17 00:00:00 2001 +From 3925d60ee24f34a9cdb4d9014b867388be990164 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:56 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add module support for platform diff --git a/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch b/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch index 53a32a761a..65e6563973 100644 --- a/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch +++ b/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch @@ -1,4 +1,4 @@ -From 3918539e5418b2d1151b2a2e086601ded67796a3 Mon Sep 17 00:00:00 2001 +From 0bece09cf85e2707fde8ad276dd6c46b150d6097 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:57 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Split PCIe controller header diff --git a/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch b/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch index 666272aa6c..a170a309af 100644 --- a/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch +++ b/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch @@ -1,4 +1,4 @@ -From 4fb7d19f2e7e5112722787c8f89b8ca56f6943be Mon Sep 17 00:00:00 2001 +From 1eb042051f3e2906d1caa4c5ab624056b0991758 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:58 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Move PCIe RP common functions to diff --git a/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch b/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch index c0c607ce23..17aeae1b45 100644 --- a/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch +++ b/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch @@ -1,4 +1,4 @@ -From 169a3b6c0054a1a90e9a56316ce2530a6e1d21ad Mon Sep 17 00:00:00 2001 +From 3a5a11f7bc5c3ab8c769fc5b75f92bd4c1da3788 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:59 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add support for High Perf diff --git a/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch b/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch index 45d4cc96d9..b2abcc9136 100644 --- a/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch +++ b/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch @@ -1,4 +1,4 @@ -From 668b64875b3a39ad0c809fd84baba5596b3f93c1 Mon Sep 17 00:00:00 2001 +From 44e86a41e45f097ea3716174df8988299502fbf4 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:49:55 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use phylink's interface mode diff --git a/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch b/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch index e6e34a7195..1c8feb9296 100644 --- a/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch +++ b/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch @@ -1,4 +1,4 @@ -From 821bb874c9ee51f801501a53f0bfaff22992f2fb Mon Sep 17 00:00:00 2001 +From 43f0647cb3c08ebc84b841e37b0d55747e913beb Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:00 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: s32: move PHY_INTF_SEL_x diff --git a/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch b/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch index 2109b174e4..a21895259f 100644 --- a/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch +++ b/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch @@ -1,4 +1,4 @@ -From 90e4dd06e790973bb6661abbcb3f3e584ec56f1e Mon Sep 17 00:00:00 2001 +From 117b92c58e2f5cd407352654edc8faf142ee0657 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:05 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add phy_intf_sel and ACTPHYIF diff --git a/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch index 9a20bd485f..1ee02b4963 100644 --- a/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch +++ b/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch @@ -1,4 +1,4 @@ -From 624275e49ff1dc397c4e821f30d8afcc4c8f621e Mon Sep 17 00:00:00 2001 +From 113a8840b97620b513498119a2b35fbf442c0c9b Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:10 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add stmmac_get_phy_intf_sel() @@ -33,7 +33,7 @@ index 865531d6cd3b..a628b5039448 100644 int stmmac_suspend(struct device *dev); void stmmac_dvr_remove(struct device *dev); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 41b270a48630..efe313a59b33 100644 +index 1ceedd74e429..bd705136ccc0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3035,6 +3035,26 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv) diff --git a/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch b/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch index b7fa7e6a46..5e6fdda67c 100644 --- a/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch +++ b/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch @@ -1,4 +1,4 @@ -From f194dd514161599163226c56b2674969caea19ca Mon Sep 17 00:00:00 2001 +From d63a611184e9b8f84b7f4aefa950b64c8da7edc1 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:15 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add support for configuring the @@ -22,7 +22,7 @@ Signed-off-by: Han Gao 2 files changed, 35 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index efe313a59b33..0f7fda75f7fe 100644 +index bd705136ccc0..e86b1378bc8b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3055,6 +3055,36 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface) diff --git a/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch b/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch index 9563df2a93..d68f286dd0 100644 --- a/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch +++ b/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch @@ -1,4 +1,4 @@ -From 89d282d18f9a93cdff176ee6469c67a8b11cb528 Mon Sep 17 00:00:00 2001 +From 0bbb0e593c104ca6db38519b0f2e01d0a565288d Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:21 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: convert to PHY_INTF_SEL_xxx diff --git a/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch b/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch index 3546e04959..16f424bc0b 100644 --- a/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch +++ b/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch @@ -1,4 +1,4 @@ -From cc8ade8e3e83180c2b2c2458f61161c29f310f53 Mon Sep 17 00:00:00 2001 +From 9115a394b543402831d6296170c8473755216a9b Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:26 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use FIELD_PREP()/FIELD_GET() diff --git a/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch index 133ab7846d..3b77c41813 100644 --- a/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch +++ b/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch @@ -1,4 +1,4 @@ -From c242a53cab013ff50b42785236d0b703b63c9e37 Mon Sep 17 00:00:00 2001 +From a3036bb05f0f0ba49141f757e8a9c682124b897f Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:31 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use diff --git a/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch b/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch index cc5171568d..2755d3b7f6 100644 --- a/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch +++ b/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch @@ -1,4 +1,4 @@ -From 38044c901de858463843f7c8cfab808a34627f56 Mon Sep 17 00:00:00 2001 +From 316608f6a973202aecff9d544c0c8df73b28974f Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:36 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: simplify set_intf_mode() diff --git a/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch b/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch index 7f2c908494..eb07230bdb 100644 --- a/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch +++ b/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch @@ -1,4 +1,4 @@ -From 3c89184f3302aafeabc618409bf916aa970f4f16 Mon Sep 17 00:00:00 2001 +From 7c1bcafe332511c19de7c7ac676bb3858d39410c Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:41 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: cleanup arguments for diff --git a/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch index 20bb16df38..24dab4413e 100644 --- a/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch +++ b/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch @@ -1,4 +1,4 @@ -From e0a6c2e873b5d2ba2e3a62461407c4523f488812 Mon Sep 17 00:00:00 2001 +From 1eabcd14c3a8ae06847f6a7af868db90fdd417d2 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:46 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use ->set_phy_intf_sel() diff --git a/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch b/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch index f73e1f62b4..b6df6f8e72 100644 --- a/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch +++ b/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch @@ -1,4 +1,4 @@ -From d219e86b2ba446033884ed9b3f3cb9d0edcd98ef Mon Sep 17 00:00:00 2001 +From eadf535b70265b367eb6619033594dad637807b2 Mon Sep 17 00:00:00 2001 From: Nilay Shroff Date: Fri, 20 Feb 2026 12:32:27 +0530 Subject: [RUYI PATCH] UPSTREAM: powerpc/pci: Initialize msi_addr_mask for diff --git a/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch b/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch index e75eecbde3..a3aa543955 100644 --- a/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch +++ b/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch @@ -1,4 +1,4 @@ -From 9e9a5cb4c3cd15b6b321a0ec71d41d8318cfd254 Mon Sep 17 00:00:00 2001 +From 2b9cdafd6924c78f840a81079b9b3460ca015f62 Mon Sep 17 00:00:00 2001 From: Nilay Shroff Date: Fri, 20 Feb 2026 12:32:28 +0530 Subject: [RUYI PATCH] UPSTREAM: sparc/PCI: Initialize msi_addr_mask for diff --git a/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch b/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch index 9f8cb3b4b0..b7814169fb 100644 --- a/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch +++ b/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch @@ -1,4 +1,4 @@ -From 94993ae18a9db8b1a6f5939a8bfc465712f0e760 Mon Sep 17 00:00:00 2001 +From a2a523e92eddce6fd85a0553540d59423a4b779d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 29 Oct 2025 17:33:30 +0100 Subject: [RUYI PATCH] UPSTREAM: syscore: Pass context data to callbacks @@ -700,7 +700,7 @@ index 6f63b90f9e1a..e7807356dfab 100644 spin_lock(&rac_lock); reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c -index 46036d98da75..8b2fcb3fb874 100644 +index 5d6a60294fb2..24f947e4b219 100644 --- a/arch/loongarch/kernel/smp.c +++ b/arch/loongarch/kernel/smp.c @@ -535,28 +535,32 @@ int hibernate_resume_nonboot_cpu_disable(void) @@ -2903,7 +2903,7 @@ index b19bc60cc627..3372e1f90561 100644 static void psci_idle_init_cpuhp(void) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c -index 441ba95b38cf..647b6f4861b7 100644 +index dbdf0f41b6bb..12f11a6c9665 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -675,7 +675,7 @@ static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { @@ -3034,10 +3034,10 @@ index 7f6a62f5d1ee..1938ffa2f4f3 100644 } diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c -index 3ab62277b6be..7000e2a5511f 100644 +index 137cf82e2292..40646ddaf3fe 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c -@@ -2861,7 +2861,7 @@ static void hv_crash_handler(struct pt_regs *regs) +@@ -2907,7 +2907,7 @@ static void hv_crash_handler(struct pt_regs *regs) hv_synic_disable_regs(cpu); }; @@ -3046,7 +3046,7 @@ index 3ab62277b6be..7000e2a5511f 100644 { /* * When we reach here, all the non-boot CPUs have been offlined. -@@ -2888,7 +2888,7 @@ static int hv_synic_suspend(void) +@@ -2934,7 +2934,7 @@ static int hv_synic_suspend(void) return 0; } @@ -3055,7 +3055,7 @@ index 3ab62277b6be..7000e2a5511f 100644 { hv_synic_enable_regs(0); -@@ -2900,11 +2900,15 @@ static void hv_synic_resume(void) +@@ -2946,11 +2946,15 @@ static void hv_synic_resume(void) } /* The callbacks run only on CPU0, with irqs_disabled. */ @@ -3072,7 +3072,7 @@ index 3ab62277b6be..7000e2a5511f 100644 static int __init hv_acpi_init(void) { int ret; -@@ -2947,7 +2951,7 @@ static int __init hv_acpi_init(void) +@@ -2993,7 +2997,7 @@ static int __init hv_acpi_init(void) hv_setup_kexec_handler(hv_kexec_handler); hv_setup_crash_handler(hv_crash_handler); @@ -3081,7 +3081,7 @@ index 3ab62277b6be..7000e2a5511f 100644 return 0; -@@ -2961,7 +2965,7 @@ static void __exit vmbus_exit(void) +@@ -3007,7 +3011,7 @@ static void __exit vmbus_exit(void) { int cpu; @@ -4839,10 +4839,10 @@ index c7dcccc5f3d6..c07e562ee4c1 100644 } device_initcall(timekeeping_init_ops); diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c -index 46581554abfb..3ec22d034e73 100644 +index 8d55bbc6f34a..c75fea0c9bad 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c -@@ -5629,7 +5629,7 @@ static int kvm_offline_cpu(unsigned int cpu) +@@ -5630,7 +5630,7 @@ static int kvm_offline_cpu(unsigned int cpu) return 0; } @@ -4851,7 +4851,7 @@ index 46581554abfb..3ec22d034e73 100644 { /* * Disable hardware virtualization and set kvm_rebooting to indicate -@@ -5647,7 +5647,7 @@ static void kvm_shutdown(void) +@@ -5648,7 +5648,7 @@ static void kvm_shutdown(void) on_each_cpu(kvm_disable_virtualization_cpu, NULL, 1); } @@ -4860,7 +4860,7 @@ index 46581554abfb..3ec22d034e73 100644 { /* * Secondary CPUs and CPU hotplug are disabled across the suspend/resume -@@ -5664,7 +5664,7 @@ static int kvm_suspend(void) +@@ -5665,7 +5665,7 @@ static int kvm_suspend(void) return 0; } @@ -4869,7 +4869,7 @@ index 46581554abfb..3ec22d034e73 100644 { lockdep_assert_not_held(&kvm_usage_lock); lockdep_assert_irqs_disabled(); -@@ -5672,12 +5672,16 @@ static void kvm_resume(void) +@@ -5673,12 +5673,16 @@ static void kvm_resume(void) WARN_ON_ONCE(kvm_enable_virtualization_cpu()); } @@ -4887,7 +4887,7 @@ index 46581554abfb..3ec22d034e73 100644 int kvm_enable_virtualization(void) { int r; -@@ -5694,7 +5698,7 @@ int kvm_enable_virtualization(void) +@@ -5695,7 +5699,7 @@ int kvm_enable_virtualization(void) if (r) goto err_cpuhp; @@ -4896,7 +4896,7 @@ index 46581554abfb..3ec22d034e73 100644 /* * Undo virtualization enabling and bail if the system is going down. -@@ -5716,7 +5720,7 @@ int kvm_enable_virtualization(void) +@@ -5717,7 +5721,7 @@ int kvm_enable_virtualization(void) return 0; err_rebooting: @@ -4905,7 +4905,7 @@ index 46581554abfb..3ec22d034e73 100644 cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); err_cpuhp: kvm_arch_disable_virtualization(); -@@ -5732,7 +5736,7 @@ void kvm_disable_virtualization(void) +@@ -5733,7 +5737,7 @@ void kvm_disable_virtualization(void) if (--kvm_usage_count) return; diff --git a/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch b/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch index 778297758c..204163fd5e 100644 --- a/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch +++ b/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch @@ -1,4 +1,4 @@ -From dc079d2d3ef26e7fc9ba38e7af9c67873ed5fc55 Mon Sep 17 00:00:00 2001 +From 6dc6cd1f8b082a07a30cb10ffb8a1403350e506b Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Tue, 2 Dec 2025 14:07:41 +0800 Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Preserve APLIC states diff --git a/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch b/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch index 9ede52445f..c7285fc313 100644 --- a/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch +++ b/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch @@ -1,4 +1,4 @@ -From 9030f2dc70b9b4bd8e20de88dcbbd8afa905d20e Mon Sep 17 00:00:00 2001 +From b767d9568f3b66f92d69207f325a2b16a652c531 Mon Sep 17 00:00:00 2001 From: Jessica Liu Date: Tue, 10 Mar 2026 14:16:00 +0800 Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Do not clear ACPI diff --git a/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch b/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch index 7e5c262b22..85281a4886 100644 --- a/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch +++ b/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch @@ -1,4 +1,4 @@ -From f0f6537007b57483923b71a9da409d7811b4a6a1 Mon Sep 17 00:00:00 2001 +From 85a95040d75c291fbc93e0e561d3568b14954b13 Mon Sep 17 00:00:00 2001 From: Jessica Liu Date: Tue, 10 Mar 2026 14:17:31 +0800 Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Register syscore diff --git a/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch b/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch index edf918ccc1..53005c0618 100644 --- a/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch +++ b/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch @@ -1,4 +1,4 @@ -From 362bcba652bd4b28531fbf93691ef6fba9a852a7 Mon Sep 17 00:00:00 2001 +From a6f845b2f096257348eb1751bb207a536f04a311 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Sep 2025 10:24:14 -0400 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: add missed compatible string diff --git a/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch b/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch index 3f06b45545..2d0aad73f6 100644 --- a/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch +++ b/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch @@ -1,4 +1,4 @@ -From 95da822dbecb61c821f0748e19304ec198992377 Mon Sep 17 00:00:00 2001 +From 17845b8b81cac4442af465cdf6758b45d6d8560d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Sep 2025 10:24:15 -0400 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add software-managed properties for diff --git a/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch b/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch index 0ff5ac0f10..14eb37d81f 100644 --- a/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch +++ b/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch @@ -1,4 +1,4 @@ -From 336f616b6d4b4f53eb9ffdf8822f067ff0820efa Mon Sep 17 00:00:00 2001 +From 237f1c42bc214c3cb3a624c24de08b613706e2f0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Sep 2025 10:24:16 -0400 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: Add layerscape diff --git a/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch b/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch index 85f93bef67..e612d006cb 100644 --- a/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch +++ b/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch @@ -1,4 +1,4 @@ -From 4b1c4f9c84bda4bcf482c0efe496c3a6648372ca Mon Sep 17 00:00:00 2001 +From 0b176d28630308e769098ac5e29e0edf51a0b398 Mon Sep 17 00:00:00 2001 From: Hang Cao Date: Wed, 12 Nov 2025 13:53:21 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add ESWIN EIC7700 USB diff --git a/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch b/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch index c664c16a80..d17829474c 100644 --- a/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch +++ b/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch @@ -1,4 +1,4 @@ -From a2ce6ee9f23da731a7f30c0869f5b48c66d727e1 Mon Sep 17 00:00:00 2001 +From f9fb0523e8826c570898c56b50bf9779f894ce26 Mon Sep 17 00:00:00 2001 From: Hang Cao Date: Wed, 12 Nov 2025 13:53:45 +0800 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: eic7700: Add EIC7700 USB driver diff --git a/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch b/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch index 0830c4cd17..c3a4eb335d 100644 --- a/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch +++ b/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch @@ -1,4 +1,4 @@ -From 9acac5b146b312ddb8525d13c2ba273dff6508a0 Mon Sep 17 00:00:00 2001 +From e2c5643e1715c990fc07ce560139625f2edd5827 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 16 Feb 2026 23:26:53 +0800 Subject: [RUYI PATCH] UPSTREAM: phy: k1-usb: add disconnect function support diff --git a/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch b/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch index f563981345..174cd8a8f1 100644 --- a/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch +++ b/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch @@ -1,4 +1,4 @@ -From 8aba9c8ffd6f7bf33950abcc2bb276254f6749cf Mon Sep 17 00:00:00 2001 +From c6a6a28a720c061231c7672505fe6b1692dc0c55 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Wed, 17 Dec 2025 07:45:28 -0800 Subject: [RUYI PATCH] UPSTREAM: PCI: Add ASPEED vendor ID to pci_ids.h diff --git a/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch b/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch index dba743541d..fbb2b87937 100644 --- a/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch +++ b/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch @@ -1,4 +1,4 @@ -From ebc23bfadb5fbe0d0f28b65fd9c6837238e6e941 Mon Sep 17 00:00:00 2001 +From a642f8bcf0cf62d7cf1642f8f24b2fbcfe80fc37 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Wed, 17 Dec 2025 07:45:29 -0800 Subject: [RUYI PATCH] UPSTREAM: PCI: Add PCI_BRIDGE_NO_ALIAS quirk for ASPEED diff --git a/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch b/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch index b717a1f71f..0e1b88fcc9 100644 --- a/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch +++ b/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch @@ -1,4 +1,4 @@ -From 9b54a8b4866b22ba764ced5eadb4df836758c46b Mon Sep 17 00:00:00 2001 +From e3d9fb3bd8c7d99e6f808702d5335a99df089451 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 23 Mar 2026 17:43:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: patch: Avoid early phys_to_page() diff --git a/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch b/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch index 7274ae6b1a..123c56b68d 100644 --- a/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch +++ b/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch @@ -1,4 +1,4 @@ -From 6727a0a8b7add2ff9543cd2e8e0f4e29a5a9b89a Mon Sep 17 00:00:00 2001 +From ee641316ba28b407fa3c0e2e30ff68676b24911c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 20 Jan 2026 23:17:44 +0530 Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Fail dw_pcie_host_init() if diff --git a/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch b/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch index 1cc4f9a6b9..58fb655677 100644 --- a/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch +++ b/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch @@ -1,4 +1,4 @@ -From a21ca9741cdf655d806097dd0285fc759b7550dd Mon Sep 17 00:00:00 2001 +From 50e513b530f9e8ff4e5efaa0d2a9c1ddf0ed96fe Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 11:06:17 +0000 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: k3: Decouple composite reset diff --git a/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch index f22e81a3cb..b9680b0e9a 100644 --- a/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch +++ b/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch @@ -1,4 +1,4 @@ -From 36c2fd3cabf5ec62efb4f91282e7b4afd1034963 Mon Sep 17 00:00:00 2001 +From b177ff56efc790143fcad8774a0fa6295390e2c9 Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:25 +0000 Subject: [RUYI PATCH] UPSTREAM: rust: clk: implement Send and Sync diff --git a/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch index de7554e891..5f4ad88656 100644 --- a/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch +++ b/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch @@ -1,4 +1,4 @@ -From 83865522aaf93ce13b4bf32daff035cc0ffb1875 Mon Sep 17 00:00:00 2001 +From 656a7926c150505d9e7116c44047cb98b9b144ac Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:26 +0000 Subject: [RUYI PATCH] UPSTREAM: tyr: remove impl Send/Sync for TyrData diff --git a/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch b/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch index 96d1a40105..14ac0db488 100644 --- a/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch +++ b/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch @@ -1,4 +1,4 @@ -From 196de3c6b4e75a74ef0157f0c59ca867711beb1f Mon Sep 17 00:00:00 2001 +From c8b2cc93f304e121425f8ab08537d10ae2a5110a Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 21 Jan 2026 19:37:19 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: fix `CLIPPY=1` warning diff --git a/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch index bfdd63b39b..e20e980eb2 100644 --- a/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch +++ b/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch @@ -1,4 +1,4 @@ -From b521133241a4f965f50ccf4af99769c36904d779 Mon Sep 17 00:00:00 2001 +From 1c00f5d8f76d51936665551442e935339855075a Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:27 +0000 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: remove impl Send/Sync for diff --git a/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch index 3373671d06..4cf0c7a3ce 100644 --- a/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch +++ b/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch @@ -1,4 +1,4 @@ -From 32264ffa5210859b00dbce09fa640779874438f7 Mon Sep 17 00:00:00 2001 +From 6b739d775a13c509e838c68cb864879eb5035a21 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 5 Mar 2026 15:00:29 +0800 Subject: [RUYI PATCH] UPSTREAM: net: spacemit: Remove unused buff_addr fields diff --git a/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch index 9f38d216be..81a0a8d8e7 100644 --- a/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch +++ b/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch @@ -1,4 +1,4 @@ -From c446f352ebab05c2cef0a9835bd9224e19c24ccb Mon Sep 17 00:00:00 2001 +From da2e9a8963b952986b932b293479350fe4dbebc0 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:37 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: Add support for Spacemit K3 diff --git a/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch index e0e422ae4b..4d058142e7 100644 --- a/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch +++ b/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch @@ -1,4 +1,4 @@ -From 415d3b3b2a8fe07f5d9c84225c47c6f3be8fd827 Mon Sep 17 00:00:00 2001 +From 2587e7c305cdac8ba52da0a37169d1b9c8064588 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:38 +0800 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a IP diff --git a/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch index e3ca4ecc6c..a953c62cbe 100644 --- a/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch +++ b/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch @@ -1,4 +1,4 @@ -From 945ce43958e6a4b22a3bf632d66514c6e279d2e9 Mon Sep 17 00:00:00 2001 +From 8877fbd548452797ddc8b8ea1e278fe120e4ed3e Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:39 +0800 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 diff --git a/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch index be1102a0eb..b43ad2ba8c 100644 --- a/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch +++ b/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch @@ -1,4 +1,4 @@ -From eaea87333b8ad51ffef8e8e2939c8aedc0c6f5f5 Mon Sep 17 00:00:00 2001 +From 89f93eb859e29528753f46b119d8e592d8df98b4 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Fri, 6 Feb 2026 16:02:12 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve handling of unknown diff --git a/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch index d0de8aa1e5..bf83516e20 100644 --- a/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch +++ b/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch @@ -1,4 +1,4 @@ -From 74c17747b1c536e207645c2cd6bd1399b9d2ec05 Mon Sep 17 00:00:00 2001 +From d3c0e1ed28ef36b7a478ab1e5a1d43b177252681 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Fri, 6 Feb 2026 16:02:13 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Mark FWCCB_CMD_UPDATE_STATS diff --git a/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch index 50ffd104f5..2b791ebf69 100644 --- a/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch +++ b/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch @@ -1,4 +1,4 @@ -From 913bf005c8fcc762460c945ae4c4b99a3b30e116 Mon Sep 17 00:00:00 2001 +From 38fc4d550a8ceafb242fc13b315cf8978c21de80 Mon Sep 17 00:00:00 2001 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:24 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve firmware power off diff --git a/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch index 30928dca28..a80553db97 100644 --- a/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch +++ b/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch @@ -1,4 +1,4 @@ -From 1c4786d466085bd7d5e793bc432f8d9d77048fb9 Mon Sep 17 00:00:00 2001 +From 3c81b0118a1dae65d34dd8ccfcc3c139756498ab Mon Sep 17 00:00:00 2001 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:25 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip 2nd thread DM diff --git a/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch index 74f768a3dd..1000a5b0eb 100644 --- a/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch +++ b/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch @@ -1,4 +1,4 @@ -From 2af0a8e17c8cfcbee59a2a2f6315c394a0342dc5 Mon Sep 17 00:00:00 2001 +From 90791ed1e854870177f6c1d1b77e2676feac639f Mon Sep 17 00:00:00 2001 From: Alexandru Dadu Date: Mon, 23 Mar 2026 20:31:28 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Add missing rogue context diff --git a/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch index 0b560df8fc..1b0b881b05 100644 --- a/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch +++ b/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch @@ -1,4 +1,4 @@ -From 3ea351d649da005c14bb7563aff7c5a258116a18 Mon Sep 17 00:00:00 2001 +From 401d51c0efd933cbb72ce194feb019d8ec7119d1 Mon Sep 17 00:00:00 2001 From: Alexandru Dadu Date: Mon, 23 Mar 2026 20:31:30 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Implement handling of context diff --git a/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch index f7d478ada1..eed39f4394 100644 --- a/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch +++ b/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch @@ -1,4 +1,4 @@ -From e88d780551651b13977fcb9a0fc500f0edc4ec8d Mon Sep 17 00:00:00 2001 +From 17ffbb0f5a1fccd445f675bb3c6c05253578a74a Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:15 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: add verisilicon diff --git a/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch index 3ab06308e6..b530b8d352 100644 --- a/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch +++ b/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch @@ -1,4 +1,4 @@ -From 0097108abfd8e7e0526f283feef46f9ff85d3019 Mon Sep 17 00:00:00 2001 +From cc17be16d91b62778ed9f985371b1e03411d8938 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:16 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display: add verisilicon,dc diff --git a/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch index f6b7875e3a..1bcbd0654a 100644 --- a/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch +++ b/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch @@ -1,4 +1,4 @@ -From 6b2f35b64e7c0486c46921e2bae819b08dc83a72 Mon Sep 17 00:00:00 2001 +From 232492bd64c5a453597b4bc3bfd8d0c1e4c1be57 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:17 +0800 Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add a driver for Verisilicon diff --git a/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch index 641e31a30d..6982aad95b 100644 --- a/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch +++ b/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch @@ -1,4 +1,4 @@ -From f3c9d099748a9f334530dc8d3b829667282a09e2 Mon Sep 17 00:00:00 2001 +From 6274472f0a7aacec6bf75732549eb8801ce79364 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:18 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display/bridge: add binding for diff --git a/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch index cf9d00a163..98cacc3de7 100644 --- a/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch +++ b/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch @@ -1,4 +1,4 @@ -From 58ad5626c4911a37f2e711c60ae825d55251511b Mon Sep 17 00:00:00 2001 +From b4768d8979f02ad4d17b11a4bd4a0c97b33d5fbc Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:19 +0800 Subject: [RUYI PATCH] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 diff --git a/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch index 6f796d9cbc..bb1851b7f9 100644 --- a/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch +++ b/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch @@ -1,4 +1,4 @@ -From ea4a0e0935587b36a14380693c67c8cd0a9b30f1 Mon Sep 17 00:00:00 2001 +From 95eff11a4892693dbe633e1582a8e9359fcd79f7 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:02 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add individual diff --git a/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch index c1c7ac83ec..9fc6e8dfd3 100644 --- a/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch +++ b/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch @@ -1,4 +1,4 @@ -From 42b7ba3e5273fbdc3ca27c1fb551be6f0eccab97 Mon Sep 17 00:00:00 2001 +From b190e35d2b5d27e768e7b1ab0e227d0a768a2159 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:03 +0800 Subject: [RUYI PATCH] UPSTREAM: regulator: spacemit-p1: Update supply names diff --git a/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch index 7a0dd9d20a..391aba0e06 100644 --- a/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch +++ b/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch @@ -1,4 +1,4 @@ -From a16a762a96646468762203524a13847057523875 Mon Sep 17 00:00:00 2001 +From dd2cc43099815a13549008e14bc55ac63e84a1c7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 23 Dec 2025 10:24:50 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add reset support diff --git a/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch index 271bd70fc5..b268f7565b 100644 --- a/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch +++ b/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch @@ -1,4 +1,4 @@ -From 3661bb1bda184323b7f27ca11c4f6aa2453a891b Mon Sep 17 00:00:00 2001 +From 34f466edac754bd7fcecd9a421744a5f4ad5280a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 22 Jan 2026 17:37:30 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add support diff --git a/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch index 067922ab83..b3e8c6be5f 100644 --- a/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch +++ b/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch @@ -1,4 +1,4 @@ -From aef7fb87d55efc5bff2a628b6196c36b7eaf3e12 Mon Sep 17 00:00:00 2001 +From ab33d441a051812b365999d837b8afaa448e3da7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 22 Jan 2026 17:37:31 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for K3 diff --git a/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch b/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch index bd29a279bd..71b4897e14 100644 --- a/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch +++ b/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch @@ -1,4 +1,4 @@ -From 71fc35504a003f43684f36757050f5c7e1ca7c23 Mon Sep 17 00:00:00 2001 +From f96f9ecbf2aa737fe00a69a78cc04b4004e5a254 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Sun, 5 Apr 2026 15:41:53 +0000 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add flags for disabling ASPM diff --git a/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch b/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch index 863472668a..d36042d2d2 100644 --- a/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch +++ b/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch @@ -1,4 +1,4 @@ -From b79c6a8e8737f691e21ed1f9492ed9784de03550 Mon Sep 17 00:00:00 2001 +From 7634a34dc15383e81523eec67c157edc7f6267d5 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Sun, 5 Apr 2026 15:41:54 +0000 Subject: [RUYI PATCH] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 diff --git a/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch index 45d9a8f9de..2c9e5a12a7 100644 --- a/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch +++ b/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch @@ -1,4 +1,4 @@ -From e8797e3dcfc25acbd3f8c8b268ec9d8bd1c28295 Mon Sep 17 00:00:00 2001 +From e7eda2ad9f7e602ec3c79a20c05dbcb621c6ac76 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Mar 2026 00:24:56 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt diff --git a/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch b/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch index 3011e77bd5..800736102b 100644 --- a/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch +++ b/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch @@ -1,4 +1,4 @@ -From 42218f60a7def59ca6f9513365c5aed9fb77a124 Mon Sep 17 00:00:00 2001 +From 71420ca546d63613ee47267fdcfcb0a761bf330f Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Tue, 10 Mar 2026 11:41:12 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Disable interrupts before diff --git a/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch index 97daa0a8b0..ffe40672f2 100644 --- a/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch +++ b/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch @@ -1,4 +1,4 @@ -From 9714f16b48717549d0332bbcd37661290bf0a765 Mon Sep 17 00:00:00 2001 +From 890f73d1b5c1319a9308842d0a118a23799701a6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:20 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add DPU and HDMI device diff --git a/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch index df92d3aeea..81f79d6d5b 100644 --- a/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch +++ b/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch @@ -1,4 +1,4 @@ -From 4633a7a2c68426c3f3fc28382fd6cba7df6134d8 Mon Sep 17 00:00:00 2001 +From 81676c69d6cf6b645944ad1e96c72e35e483f069 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:21 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable HDMI diff --git a/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch index dfee292fb6..7e8edfaeb8 100644 --- a/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch +++ b/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch @@ -1,4 +1,4 @@ -From 00020f3b46c3943b6ce714ac17de5fd1573b399b Mon Sep 17 00:00:00 2001 +From 8e3494bc849eb33a26b0fc1e3c0662ecc6cbdaba Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Mar 2026 00:24:57 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: th1520: add coefficients to diff --git a/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch index 03da857375..7ab4fffc43 100644 --- a/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch +++ b/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch @@ -1,4 +1,4 @@ -From 1cce6a25c0cf7aab271eb21e6d8b9ed58ed13b84 Mon Sep 17 00:00:00 2001 +From dceaa01db9088494f93a2bc9dd7fd5887f44e60e Mon Sep 17 00:00:00 2001 From: Robert Mazur Date: Wed, 25 Mar 2026 09:18:59 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable HDMI diff --git a/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch index 0128ba9bc1..f42029e4e2 100644 --- a/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch +++ b/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch @@ -1,4 +1,4 @@ -From d2ce0203a4d1455b03013278280f7ac698fce115 Mon Sep 17 00:00:00 2001 +From 383020d47e926f8e6e10db7f404c0f22f4ac37b7 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Sat, 7 Feb 2026 23:08:21 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() diff --git a/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch index 34101370a3..e5c199eec8 100644 --- a/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch +++ b/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch @@ -1,4 +1,4 @@ -From 4fa4815280ddada7e960eb90a9ccccd015916c00 Mon Sep 17 00:00:00 2001 +From 85a82954acd965a8e7f06acf2b98533ffe944b92 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Sat, 7 Feb 2026 23:08:22 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: introduce pio for k1 diff --git a/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch index d01da0caa4..a0402db174 100644 --- a/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch +++ b/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch @@ -1,4 +1,4 @@ -From 55a3d0c1bf77d828f3581b3c07e12d8a25775e1c Mon Sep 17 00:00:00 2001 +From 189d71e00b28cf84bdef8a3368c473675599b5a4 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:42 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for diff --git a/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch index 5b07efea54..330746bdaa 100644 --- a/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch +++ b/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch @@ -1,4 +1,4 @@ -From 698e2cf6a0e40c6a445aeefa403bb4ac1b28919a Mon Sep 17 00:00:00 2001 +From 4588a083d35aa5e2e2c1c4ad364eb4de88d6a7ad Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:43 +0800 Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Add set_config callback diff --git a/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch b/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch index e3ff5c7bb8..64650bb229 100644 --- a/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch +++ b/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch @@ -1,4 +1,4 @@ -From 8572451bc96b2e6e3f43ce554e3806a5b1c7778c Mon Sep 17 00:00:00 2001 +From 3972df874b39a17accecea4ef294937b0b4db42d Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 08:17:55 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pcie: fix missing power diff --git a/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch index c1a03ad44a..e598325fe2 100644 --- a/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch +++ b/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch @@ -1,4 +1,4 @@ -From d591170d2ed25e8716eb3db09e686e859c5c318b Mon Sep 17 00:00:00 2001 +From c74eeb3e1afb91310fa36cfdf25bd8dccaf5dc72 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:04 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Update PMIC supply diff --git a/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch index 2dce8101f3..53c8565593 100644 --- a/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch +++ b/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch @@ -1,4 +1,4 @@ -From d068a8147daedba4965fc79a896ad7dcaa91b9e4 Mon Sep 17 00:00:00 2001 +From 706c6c7d0a2819ecb157351bcb6b9d3c85c72f8a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 09:35:00 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: adapt regulator node diff --git a/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch index dd31af6364..8e8e77d707 100644 --- a/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch +++ b/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch @@ -1,4 +1,4 @@ -From 3c942f15e5112f8554b39f1c889cb52184bd3e90 Mon Sep 17 00:00:00 2001 +From b1b9cbb75e922569afad4faecf4626e8bde3e7d7 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 9 Mar 2026 11:00:00 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add 'linux,pci-domain' diff --git a/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch index 1a6351971a..565fb8abda 100644 --- a/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch +++ b/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch @@ -1,4 +1,4 @@ -From e6fddcb8065f3568285549e732cda7618b1e5065 Mon Sep 17 00:00:00 2001 +From 88d533f1c6bfb3181035649386387a8d59f75318 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:19:39 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix clock diff --git a/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch index d84cac3c6d..80b8be71a3 100644 --- a/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch +++ b/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch @@ -1,4 +1,4 @@ -From d685ab6d599ba502610b5f425c35683c2c838c0a Mon Sep 17 00:00:00 2001 +From 60519a3245f5c93f0bbe6ec9f8502c9031994419 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:42 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add clock tree diff --git a/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch index 43081756d0..12c9c99597 100644 --- a/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch +++ b/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch @@ -1,4 +1,4 @@ -From 26584036220607376da285b0c0cf42306e1dc824 Mon Sep 17 00:00:00 2001 +From 6cefb7d0dcc59b4d29c4b66e52d86a7e80d4db06 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:43 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl support diff --git a/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch index dae1e8f109..a2207de4f1 100644 --- a/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch +++ b/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch @@ -1,4 +1,4 @@ -From d0197dc9c7ce0b6d04f508db631f06668553d958 Mon Sep 17 00:00:00 2001 +From 67a9dfd22c5cefa5860160d30c1b5bce5719c5a6 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:44 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support diff --git a/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch index 581044da67..e7737fa5c7 100644 --- a/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch +++ b/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch @@ -1,4 +1,4 @@ -From 186d384a785aeb3b664585647bd06ee2009145dd Mon Sep 17 00:00:00 2001 +From 44eedf0908b4e6c2893a89cb94053d973411abab Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:45 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add full resource to diff --git a/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch index a15e56ca61..dfeb6a4a3f 100644 --- a/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch +++ b/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch @@ -1,4 +1,4 @@ -From 8ded8df1d9dccc63760629834a87ae2c8615e042 Mon Sep 17 00:00:00 2001 +From bae97e71f9ca4558461de9dd135102ef2c5a4f0b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 07:15:37 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add support diff --git a/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch index 45a1cbb328..90eb42bbb1 100644 --- a/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch +++ b/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch @@ -1,4 +1,4 @@ -From 27133a501e88e5b271c1a5c98f2013d1f8dc931a Mon Sep 17 00:00:00 2001 +From 7d4a17760463805b041533b09751e181e870e5e4 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 07:15:38 +0000 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add diff --git a/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch index e9139f8f74..f6606cf138 100644 --- a/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch +++ b/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch @@ -1,4 +1,4 @@ -From ec33bc462214da036d45ea0a3822c34e9f3d422b Mon Sep 17 00:00:00 2001 +From 395f6faa5c6eaee1206ab83d69d671da8d8bf5e3 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 26 Mar 2026 18:00:10 +0800 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add optional VBUS regulator support diff --git a/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch index 4c498e66d6..29c7c2bea5 100644 --- a/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch +++ b/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch @@ -1,4 +1,4 @@ -From feb6ae05030bda7ec7a43a8384cfdffc80d33e30 Mon Sep 17 00:00:00 2001 +From 8ad8078b131f6aea0fde2e411f43212dbb92b54b Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 18 Mar 2026 18:00:00 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for K1 diff --git a/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch b/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch index 7d60f42287..4198effb46 100644 --- a/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch +++ b/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch @@ -1,4 +1,4 @@ -From 9c90526d6c53498c2b0fce296ea54822274f4e03 Mon Sep 17 00:00:00 2001 +From cc73195bc241ce392226f27e718ad6bb23c7dc33 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 22 Mar 2026 21:25:01 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: drop incorrect pinctrl diff --git a/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch index daa6d30ac8..0ebc98616d 100644 --- a/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch +++ b/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch @@ -1,4 +1,4 @@ -From f1fd9849a3a86e6e7567394bcfbd7e80314e1925 Mon Sep 17 00:00:00 2001 +From 8199942289fa74a51c30bec529cab134501ee2be Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 26 Mar 2026 09:46:17 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add ethernet device for diff --git a/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch index 0ef10a2c37..7651ca9ac9 100644 --- a/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch +++ b/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch @@ -1,4 +1,4 @@ -From 22e068c1b0db347abe57240b5f4e6aea284b400a Mon Sep 17 00:00:00 2001 +From 9350d479493c039562a167931c2a148bb2257368 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:29 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V diff --git a/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch index d1757910da..78c7581d06 100644 --- a/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch +++ b/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch @@ -1,4 +1,4 @@ -From fd0cc30ddc8df5ecd44ae759b0d7ba0d8b5140c5 Mon Sep 17 00:00:00 2001 +From a28cfbc8b3633e1c31dc2dd1b607c515e3d9473a Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:30 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on diff --git a/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch index d6371cd157..199d048656 100644 --- a/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch +++ b/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch @@ -1,4 +1,4 @@ -From 82fab0710b5af85d582db37f1628e0efe0783003 Mon Sep 17 00:00:00 2001 +From d33a5a7d922d3c7562e7169a9c50caf7b81d39dd Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:31 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on diff --git a/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch index 7da7a14692..6f72accab4 100644 --- a/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch +++ b/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch @@ -1,4 +1,4 @@ -From 8cd168c0e1c6761c9dc36dba489883961c115b69 Mon Sep 17 00:00:00 2001 +From 7bf7522c2f3ea687882aebaef45a23db49a253a6 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:32 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI and add SPI diff --git a/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch index ab6defa852..53bcae1cda 100644 --- a/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch +++ b/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch @@ -1,4 +1,4 @@ -From 7c97859e0dc8e3a13976fbd8fa3512d2a6469e32 Mon Sep 17 00:00:00 2001 +From 16315cf1d62e428f4ffd7477fe748a579e08c767 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:33 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on diff --git a/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch index 37c7e74275..bfdf3f0566 100644 --- a/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch +++ b/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch @@ -1,4 +1,4 @@ -From a6af60e5b4b61218cbfe45507b2a9c0740b13741 Mon Sep 17 00:00:00 2001 +From 008e9161472e33b735cabb897a883483eb1d62ce Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:34 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on diff --git a/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch index 636cc98729..2105efb33b 100644 --- a/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch +++ b/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch @@ -1,4 +1,4 @@ -From ffb258a6f70ad79ca6c7b0a4c04cd38fbdd33471 Mon Sep 17 00:00:00 2001 +From eaf94de0b17a7f2c6c983d703f6f3bd8dbd4db38 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 25 Mar 2026 09:49:24 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add compatible diff --git a/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch index 4fa6b0eb20..692dc582f5 100644 --- a/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch +++ b/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch @@ -1,4 +1,4 @@ -From 2e5ff84331e9d469cf732e06694632b4d7f0a64e Mon Sep 17 00:00:00 2001 +From dc51053b1e9c63bf238c7324e2bfb06cacd96efd Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:40:40 +0000 Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes diff --git a/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch index fec47cecd6..69f27b1739 100644 --- a/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch +++ b/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch @@ -1,4 +1,4 @@ -From 7602638398631706b3b851eeb82562691d9fbf20 Mon Sep 17 00:00:00 2001 +From 5eadd54b1f4d67bed0234caa109dfa0bce785c40 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:51:18 +0000 Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC diff --git a/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch index dc246bac07..1dda4ae65f 100644 --- a/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch +++ b/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch @@ -1,4 +1,4 @@ -From e2f15b90c20c9acc8b6524640ad61e8dd279261b Mon Sep 17 00:00:00 2001 +From 852e5e193c12e0e5eb26b24e0eb9517eaeaf46b9 Mon Sep 17 00:00:00 2001 From: Chen Pei Date: Tue, 17 Mar 2026 11:48:47 +0800 Subject: [RUYI PATCH] UPSTREAM: perf symbol: Add RISCV case in get_plt_sizes diff --git a/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch index 4135dc8422..cd178c2295 100644 --- a/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch +++ b/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch @@ -1,4 +1,4 @@ -From 88b461165ff138a8bc16b7a3d1540a19c8a3710e Mon Sep 17 00:00:00 2001 +From 90646c816a8e1bb5cf43743f706066bc525133ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 4 Apr 2026 18:42:40 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE diff --git a/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch index c12445faca..ac47ff42ee 100644 --- a/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch +++ b/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch @@ -1,4 +1,4 @@ -From f64acae7865de9be5e3490b46bc253b9e0d8464e Mon Sep 17 00:00:00 2001 +From a3b19f0358177e3a9a105a429a45332a53464e30 Mon Sep 17 00:00:00 2001 From: Austin Kim Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to diff --git a/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch index 53eb710553..558694da38 100644 --- a/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch +++ b/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch @@ -1,4 +1,4 @@ -From 50da2d0c20ed5daeac5e56fc3b173a315118dc29 Mon Sep 17 00:00:00 2001 +From 55bd39f8dbbb10df72d54d5154629679a7c26d5b Mon Sep 17 00:00:00 2001 From: Yufeng Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: acpi: update FADT revision check to 6.6 diff --git a/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch index 03b0b8232a..1717b0a8f0 100644 --- a/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch +++ b/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch @@ -1,4 +1,4 @@ -From 527bf47071201cafeeb74ad89ac94e5d61eb3691 Mon Sep 17 00:00:00 2001 +From c96326e9beaa6d43dee68a3d895b432c6d47151c Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in diff --git a/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch index d8e8ef3623..039119e151 100644 --- a/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch +++ b/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch @@ -1,4 +1,4 @@ -From 21223e48716232b52be9719f8d4361bc9f82af59 Mon Sep 17 00:00:00 2001 +From bf80711365ff96f172a52b4e8ccac4322a7a3b48 Mon Sep 17 00:00:00 2001 From: Yufeng Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT diff --git a/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch b/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch index 1647db78f8..b5da7e906d 100644 --- a/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch +++ b/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch @@ -1,4 +1,4 @@ -From 94b2dc80662df98e75c5893573a98c832aa7b104 Mon Sep 17 00:00:00 2001 +From 2192890eb62375ada4534f4dca4d8fc75d8e97d4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 12 Nov 2025 14:55:30 +0100 Subject: [RUYI PATCH] UPSTREAM: string: provide strends() diff --git a/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index 98ac349bfa..46309a18d1 100644 --- a/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,4 +1,4 @@ -From 79e2cd89898e36fdb3d1714bbd7988fb286c84c7 Mon Sep 17 00:00:00 2001 +From 7ae2a067cd00b1c714466b1d1f02b9b411af5d76 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for diff --git a/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index cf2e77deb8..306e922690 100644 --- a/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,4 +1,4 @@ -From 902bdb8bb0a0f55816f458cf513b52da08e503fb Mon Sep 17 00:00:00 2001 +From 1dd18b43a3cfbc4596a549638d881be3fb39fe5f Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for diff --git a/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index b303a23ddc..3fe7266d90 100644 --- a/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,4 +1,4 @@ -From a35e09fa31b7cc0d163e681b2acef99edf7f626b Mon Sep 17 00:00:00 2001 +From 6b47c4d6992b0b42614e5c42cd68a690c32a445c Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for diff --git a/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch index 8ed6b57c83..4216e5a9b8 100644 --- a/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch +++ b/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch @@ -1,4 +1,4 @@ -From 3157c725cd7a5774a6e772aee7c537b7bc65a90e Mon Sep 17 00:00:00 2001 +From d032a3bac6de0685705b92695173bf82d6eeb886 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add performance benchmark diff --git a/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch index 8a4b47a942..2012c69aaf 100644 --- a/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch +++ b/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch @@ -1,4 +1,4 @@ -From d4f3b19d0ba9850b6052f6adfda81bdd61650371 Mon Sep 17 00:00:00 2001 +From 11b6137f31389cecbf4ac42f2cd0da5955d5509e Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: extend benchmarks to diff --git a/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch index da2b0c30de..115899af46 100644 --- a/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch +++ b/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch @@ -1,4 +1,4 @@ -From d7fce76a1ce208fab598335c38ae8071bb4d893d Mon Sep 17 00:00:00 2001 +From 1a8b9de36cf32d4946ac90848ae0f16b4436b71d Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strnlen() implementation diff --git a/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch index 82e732ebcb..681090539c 100644 --- a/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch +++ b/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch @@ -1,4 +1,4 @@ -From 2f4c1bb28db6a3485cd348d5484cabeee5afb672 Mon Sep 17 00:00:00 2001 +From 5720372e6ff0e8dc4f75e5d70b798c3dd898d8e6 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strchr() implementation diff --git a/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch index 4a1a619b26..d3723941b6 100644 --- a/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch +++ b/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch @@ -1,4 +1,4 @@ -From 7a1bef3a9306a7c4cd45d233b4965356c86f23d4 Mon Sep 17 00:00:00 2001 +From c9a314cc16c1422c4922b0a902f8f01ef17ad06f Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strrchr() implementation diff --git a/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch b/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch index a11233ee84..e40c8137ae 100644 --- a/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch +++ b/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch @@ -1,4 +1,4 @@ -From 0bd7f056d6569dc61e0cc65e7eaab3c9d9d1e879 Mon Sep 17 00:00:00 2001 +From 51dd8eef5e0f89c2b72fd1f0b6c6bc8177438545 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 21 Nov 2025 17:49:18 +0100 Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Add register and bitfield diff --git a/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch index 9b9454daa8..a9c3f4d779 100644 --- a/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch +++ b/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch @@ -1,4 +1,4 @@ -From 22c3a93bf61eb47e3b47fd1cbfb9bed064b5de81 Mon Sep 17 00:00:00 2001 +From 5f7beedf8c1e1cf4cc2d8915cd12d47296a9f445 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 09:38:47 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: move hw constraints from diff --git a/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch index a235db3255..42acd706e3 100644 --- a/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch +++ b/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch @@ -1,4 +1,4 @@ -From b81d7e8285e49c07fa31cdb599fdeedddec0fb3c Mon Sep 17 00:00:00 2001 +From 0b445558d4400c7c06a9225f92fc58434d9c4d63 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 09:38:48 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: adjust FIFO trigger threshold diff --git a/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch b/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch index dbc1d4ed46..61f13b52f2 100644 --- a/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch +++ b/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch @@ -1,4 +1,4 @@ -From 42cd6879691919aaf3200276ed71a8c7f081bf8f Mon Sep 17 00:00:00 2001 +From 0dee3c150e4f31a42ee5358c2fb16cedbad43f79 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:28 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Remove diff --git a/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch b/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch index 20d4cb4ce7..9a271b21cf 100644 --- a/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch +++ b/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch @@ -1,4 +1,4 @@ -From 729fb80f40c116319af3f00f273cb56718995e42 Mon Sep 17 00:00:00 2001 +From 0a037ecaecd5d3d6451db6da957486d31735aa89 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:29 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Add diff --git a/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch b/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch index 46e0cf3948..c1f80c30ab 100644 --- a/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch +++ b/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch @@ -1,4 +1,4 @@ -From 822ec8590fdd9c6e8152814eca6d64a56660f962 Mon Sep 17 00:00:00 2001 +From b7535d42730ac17d83ccbadc8307100224b35705 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:30 +0000 Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Prepare for supporting multiple diff --git a/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch b/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch index 7a6c0e9f96..16798fa2d1 100644 --- a/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch +++ b/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch @@ -1,4 +1,4 @@ -From 34aaa4adc6171c1a972e81edbb9861406d7dfa83 Mon Sep 17 00:00:00 2001 +From faec33d63e5af3e07a519daa81a8d9e953889eaf Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:31 +0000 Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Support reset controllers in diff --git a/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch b/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch index 0509d7a26d..7b5917de8c 100644 --- a/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch +++ b/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch @@ -1,4 +1,4 @@ -From 9edafc5f3980e8fcb1a7a18a54466898f1279c14 Mon Sep 17 00:00:00 2001 +From 990eca59b3d00bfc3fd84a349b32be602ef7eeb9 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:32 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add reset controllers of diff --git a/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch index 983dd64913..f40121b1d7 100644 --- a/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch +++ b/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch @@ -1,4 +1,4 @@ -From 5f50d2a328f7b2daa106bafdb1d4a794f52fbdb4 Mon Sep 17 00:00:00 2001 +From 9a05689ddb515469b8dd3b3c86c6e461cb930936 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 24 Apr 2026 16:20:32 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: mark top_dclk as diff --git a/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch index b11d06885a..fb64bb8356 100644 --- a/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch +++ b/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch @@ -1,4 +1,4 @@ -From a7739f1ea5fb20b796b4b1d3758fd44635a40ea9 Mon Sep 17 00:00:00 2001 +From ceac6c799226bf0a55e750f8dfda4457a57c8b30 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 17:00:50 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: fix RX DMA params not set when diff --git a/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch b/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch index 23a5e1bf51..99abbd9388 100644 --- a/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch +++ b/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch @@ -1,4 +1,4 @@ -From 2c946683705fc6706119c588fd5499c0c91b2369 Mon Sep 17 00:00:00 2001 +From 6d414cc0992e8a50a71176942000ae8b501050ec Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 26 Dec 2025 16:31:59 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: drop useless spaces diff --git a/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch b/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch index dbb5d3dfe0..41e1d30f6d 100644 --- a/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch +++ b/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch @@ -1,4 +1,4 @@ -From fa80698856016bcd983f8ac31a38e4f108170879 Mon Sep 17 00:00:00 2001 +From 0889d1b742e0a98a0d7f090055580115acf747e6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:49 +0100 Subject: [RUYI PATCH] UPSTREAM: clk: at91: pmc: #undef field_{get,prep}() diff --git a/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch b/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch index 28c2c8a5db..cd542378fa 100644 --- a/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch +++ b/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch @@ -1,4 +1,4 @@ -From 0443b117c46d5530b02f66cefa36882031ef8c7f Mon Sep 17 00:00:00 2001 +From b493426d9cce7da21f2865b6e67975ecb05db09f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:50 +0100 Subject: [RUYI PATCH] UPSTREAM: crypto: qat - #undef field_get() before local diff --git a/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch b/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch index 5bd7f8e544..c21ab5a1c2 100644 --- a/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch +++ b/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch @@ -1,4 +1,4 @@ -From 8d1903d76c78fd4c3f54ccb47a84b23de8c65c5a Mon Sep 17 00:00:00 2001 +From 55c96fbd859895ac18ef19bf2cb66a79be5a441b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:51 +0100 Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: #undef field_get() before local diff --git a/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch b/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch index 8d05fa846c..d8f64a7fc9 100644 --- a/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch +++ b/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch @@ -1,4 +1,4 @@ -From 8490549e86aef53fa8416d6accaa31283186c10b Mon Sep 17 00:00:00 2001 +From 737621e196c8ba0b53475a9010406b9314bac718 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:52 +0100 Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: #undef field_{get,prep}() before diff --git a/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch b/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch index 7595552488..c5ec822ba4 100644 --- a/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch +++ b/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch @@ -1,4 +1,4 @@ -From 2fda7cbf1f4289cbb26b12faf98ad22cbbf1c6b6 Mon Sep 17 00:00:00 2001 +From 200aa85cc99066caf1bfe42bc48afde3f5f165de Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:53 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: dac: ad3530r: #undef field_prep() before @@ -20,7 +20,7 @@ Signed-off-by: Han Gao 1 file changed, 1 insertion(+) diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 6134613777b8..5684d11137f2 100644 +index a0625fc7ad48..84ce89dd76a4 100644 --- a/drivers/iio/dac/ad3530r.c +++ b/drivers/iio/dac/ad3530r.c @@ -54,6 +54,7 @@ diff --git a/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch index 9deec2c78e..b4200b44f7 100644 --- a/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch +++ b/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch @@ -1,4 +1,4 @@ -From a31ca7ca552212b34bea5cb3fcf52759dc2a28a0 Mon Sep 17 00:00:00 2001 +From 56a0c498eb7202b1712b5d25176fd0f45ba6ab53 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:54 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: #undef field_{get,prep}() diff --git a/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch index 747d0f1115..74d6b8ea5f 100644 --- a/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch +++ b/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch @@ -1,4 +1,4 @@ -From 92ba8033d4f60d619ebeb8f1f465e68d66004e81 Mon Sep 17 00:00:00 2001 +From 9d7dbecad1fa5819d037808617b077ceccfaf798 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:55 +0100 Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: #undef field_{get,prep}() diff --git a/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch b/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch index a8085f2c11..716a908a6d 100644 --- a/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch +++ b/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch @@ -1,4 +1,4 @@ -From f43d3afeb48fc78d1fa9aec7aaaefdf6964e4b6c Mon Sep 17 00:00:00 2001 +From 3de69d18d8eb1ecf72128605e7f0f320f0504078 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:56 +0100 Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: #undef field_get() diff --git a/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch b/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch index ae69b76f2a..857453db7c 100644 --- a/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch +++ b/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch @@ -1,4 +1,4 @@ -From a743678cdf95c66206f1cefd74ad8f2e3157f680 Mon Sep 17 00:00:00 2001 +From dd326795b66465f04d08f11807c402dc08b8e615 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:57 +0100 Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: #undef field_{get,prep}() diff --git a/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch b/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch index 9a78322adf..4554119461 100644 --- a/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch +++ b/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch @@ -1,4 +1,4 @@ -From c59127e75e8cf8ce74f12bd0fe0bb2574674fbe4 Mon Sep 17 00:00:00 2001 +From 7d48e0ac649a9c8f4b760a91b4eb1e76fa1ec967 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:00 +0100 Subject: [RUYI PATCH] UPSTREAM: bitfield: Add less-checking diff --git a/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch b/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch index 68212a5dda..851db8f7ac 100644 --- a/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch +++ b/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch @@ -1,4 +1,4 @@ -From 9508a0e99753a0d15b30509ead3b2314fe5d2572 Mon Sep 17 00:00:00 2001 +From 29093ed6a42705c11d9aad5ea6ad64a74dc62910 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:01 +0100 Subject: [RUYI PATCH] UPSTREAM: bitfield: Add non-constant field_{prep,get}() diff --git a/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch b/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch index 5f249092c8..a587b97492 100644 --- a/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch +++ b/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch @@ -1,4 +1,4 @@ -From 7ab27d3da88e00fd0367baf7b18fb5484ac4fd65 Mon Sep 17 00:00:00 2001 +From 8096ab2dd7593c509f2914244c681f02c9b33108 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:02 +0100 Subject: [RUYI PATCH] UPSTREAM: clk: at91: Convert to common diff --git a/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch b/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch index ad7e2a30bc..2e3e3e992e 100644 --- a/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch +++ b/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch @@ -1,4 +1,4 @@ -From e7cc1307805b330990170342cd2e17a4790cae37 Mon Sep 17 00:00:00 2001 +From 9434386120d19e42a43e97baa0574d3919723bda Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:03 +0100 Subject: [RUYI PATCH] UPSTREAM: crypto: qat - convert to common field_get() diff --git a/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch b/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch index 15800bac47..316ceb06f1 100644 --- a/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch +++ b/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch @@ -1,4 +1,4 @@ -From 435c6fcc72eff501ecd29fabd2fedec939c67aa6 Mon Sep 17 00:00:00 2001 +From 01de375c11e96785ae483780df945db623280b95 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:04 +0100 Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: Convert to common field_get() diff --git a/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch b/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch index 8bbf1a93ec..62a1d60f9d 100644 --- a/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch +++ b/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch @@ -1,4 +1,4 @@ -From d812b182981498ab3054a3c64531710d096f4e8a Mon Sep 17 00:00:00 2001 +From 99f9fe7759f561b8b37477c015e1186da1e3b182 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:05 +0100 Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: Convert to common diff --git a/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch b/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch index 0c7f9de5cc..5247b913ab 100644 --- a/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch +++ b/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch @@ -1,4 +1,4 @@ -From 8c762e56b97e2dfa47081feffdf43f03d3f977e5 Mon Sep 17 00:00:00 2001 +From f9bc08e080dccd44f22a6dcd7d0cb5ee72455eb5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:06 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: dac: Convert to common field_prep() @@ -17,7 +17,7 @@ Signed-off-by: Han Gao 1 file changed, 4 deletions(-) diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 5684d11137f2..b97b46090d80 100644 +index 84ce89dd76a4..d9db3226ecd6 100644 --- a/drivers/iio/dac/ad3530r.c +++ b/drivers/iio/dac/ad3530r.c @@ -53,10 +53,6 @@ diff --git a/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch index 5dec21e9bb..f037318cef 100644 --- a/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch +++ b/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch @@ -1,4 +1,4 @@ -From c7ea1c7ee160166a1ed64ca27681872c97335904 Mon Sep 17 00:00:00 2001 +From 4b5147a1b6e7c57b1d67fd4d34f4d245d368401e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:07 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: Convert to common diff --git a/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch index d757b43507..fd71abcfbc 100644 --- a/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch +++ b/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch @@ -1,4 +1,4 @@ -From 2cbda24297eace09de563cb06455c5936a00088e Mon Sep 17 00:00:00 2001 +From 02ff752ecdd8f77567b57dd2fe015f4b52f0173c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:08 +0100 Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: Convert to common diff --git a/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch b/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch index f9d9f0c492..7022d54f29 100644 --- a/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch +++ b/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch @@ -1,4 +1,4 @@ -From 8833c4b417190dce1a91dbf31da82221a266f133 Mon Sep 17 00:00:00 2001 +From 9d7b112b2c4bd1ec0fa4fefeb7dd17be7100c322 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:09 +0100 Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: Convert to common diff --git a/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch b/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch index 9e36e61789..d504a4d562 100644 --- a/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch +++ b/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch @@ -1,4 +1,4 @@ -From d565f3b6ace21a51f62812c86add16af8553952d Mon Sep 17 00:00:00 2001 +From 1e575c7526236eca8a9557805ef5a712cc7c3062 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:10 +0100 Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: Convert to common diff --git a/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch index 383627c806..e2898f65d6 100644 --- a/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch +++ b/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch @@ -1,4 +1,4 @@ -From 019a7bd0c854f0ec67ae6e379c46f05ccf4be4dd Mon Sep 17 00:00:00 2001 +From fbba92fc24439fb25b3afc63b3bc7576193ba10f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:13 +0100 Subject: [RUYI PATCH] UPSTREAM: clk: renesas: Use bitfield helpers diff --git a/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch index 4685894400..a8bc5a6f32 100644 --- a/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch +++ b/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch @@ -1,4 +1,4 @@ -From 23fef80ff6550ef4d1ece307b5c601d37a1fe71c Mon Sep 17 00:00:00 2001 +From faddb8617190ce6db91b8957ad5a6e3a98024931 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:14 +0100 Subject: [RUYI PATCH] UPSTREAM: soc: renesas: Use bitfield helpers diff --git a/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch index 45f824af71..604dfc454f 100644 --- a/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch +++ b/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch @@ -1,4 +1,4 @@ -From 56a298b59d7189961a4e6a04e449718ff2944c21 Mon Sep 17 00:00:00 2001 +From 55eb935ad6a55992f79be588fa21fc97cc4a0368 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 19 Mar 2026 07:51:03 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add support for Terminus diff --git a/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch index d9fcc7fdbd..9b5d33a19d 100644 --- a/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch +++ b/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch @@ -1,4 +1,4 @@ -From 7cc16fe69696bb942fb6f1b9a227fd74082707ae Mon Sep 17 00:00:00 2001 +From 08f28ce8702a79a701c3eac1b17da588327be574 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 19 Mar 2026 07:51:04 +0000 Subject: [RUYI PATCH] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus diff --git a/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch index 366e334f76..dc42ff010a 100644 --- a/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch +++ b/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch @@ -1,4 +1,4 @@ -From 3df7916fd6c198c8e58d6d4914ab06ebca3918bc Mon Sep 17 00:00:00 2001 +From 827c515038d43e1143d418d94d84f5e524f379aa Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 29 Apr 2026 20:38:17 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: Define diff --git a/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch index 74474ab04e..7f1f3d4585 100644 --- a/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ b/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -1,4 +1,4 @@ -From 2eae98ea7476677c8119a80ff9bf50c8a3600315 Mon Sep 17 00:00:00 2001 +From b950709b055b0574ff76824bfdb674410a09112d Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Thu, 21 May 2026 22:44:45 +0800 Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT diff --git a/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch index cee092d499..4042da2a5e 100644 --- a/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch +++ b/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch @@ -1,4 +1,4 @@ -From 4f4bff270953588decae0547de96ac02939beaad Mon Sep 17 00:00:00 2001 +From b7da1d402e48e261c72ea3f0b3cd368e88cd0731 Mon Sep 17 00:00:00 2001 From: Jiakai Xu Date: Sun, 17 May 2026 12:44:14 +0000 Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference in diff --git a/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch b/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch index e7deac9aea..931abf6629 100644 --- a/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch +++ b/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch @@ -1,4 +1,4 @@ -From bb40d8362ee33eb3d7341201cc0193113631e03c Mon Sep 17 00:00:00 2001 +From 6c7ef4de721d3b9e0965553bfc8242f28e0f350b Mon Sep 17 00:00:00 2001 From: Huan He Date: Sun, 19 Oct 2025 19:52:38 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin diff --git a/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch b/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch index ca470143dd..f219d49ad8 100644 --- a/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch +++ b/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch @@ -1,4 +1,4 @@ -From 09f0d19162ff660efb7b93fd764ae93f6d004129 Mon Sep 17 00:00:00 2001 +From 4ec2ef8d7b9dde2c8f044bead5b65d4e39e3fd8c Mon Sep 17 00:00:00 2001 From: Huan He Date: Sun, 19 Oct 2025 19:53:16 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Add support for Eswin diff --git a/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch b/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch index 8991fa572e..e30b7d99e8 100644 --- a/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch +++ b/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch @@ -1,4 +1,4 @@ -From eec5a961f5c9f3a5b4a99624544700e30ae02323 Mon Sep 17 00:00:00 2001 +From 956564167124dc4f8549d22339a980eaf7730bf0 Mon Sep 17 00:00:00 2001 From: Huan He Date: Wed, 14 Jan 2026 20:21:41 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix init for AXI clock diff --git a/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch b/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch index 25b1fd7b47..861a6640bb 100644 --- a/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch +++ b/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch @@ -1,4 +1,4 @@ -From 3cd03e009502a385f88e1102cb0517e2f25f455c Mon Sep 17 00:00:00 2001 +From b96b065a3520d9551fc5a976f91c53ad36374536 Mon Sep 17 00:00:00 2001 From: Huan He Date: Wed, 14 Jan 2026 20:22:56 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix DMA 128MB boundary diff --git a/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch b/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch deleted file mode 100644 index c72f779250..0000000000 --- a/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 07935065ada83928cfb96ceab6a5ec204787eed5 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:36 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Count paired job fence as - dependency in prepare_job() - -The DRM scheduler's prepare_job() callback counts the remaining -non-signaled native dependencies for a job, preventing job submission -until those (plus job data and fence update) can fit in the job queue's -CCCB. - -This means checking which dependencies can be waited upon in the -firmware, i.e. whether they are backed by a UFO object, i.e. whether -their drm_sched_fence::parent has been assigned to a -pvr_queue_fence::base fence. That happens when the job owning the fence -is submitted to the firmware. - -Paired geometry and fragment jobs are submitted at the same time, which -means the dependency between them can't be checked this way before -submission. - -Update job_count_remaining_native_deps() to take into account the -dependency between paired jobs. - -This fixes cases where prepare_job() underestimated the space left in -an almost full fragment CCCB, wrongly unblocking run_job(), which then -returned early without writing the full sequence of commands to the -CCCB. - -The above lead to kernel warnings such as the following and potentially -job timeouts (depending on waiters on the missing commands): - - [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 - [ 375.703160] Modules linked in: - [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT - [ 375.703613] Tainted: [W]=WARN - [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) - [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] - [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) - [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] - [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] - [ 375.703921] sp : ffff800084a97650 - [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 - [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 - [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 - [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 - [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 - [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 - [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 - [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 - [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 - [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f - [ 375.704317] Call trace: - [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) - [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] - [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] - [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] - [ 375.704623] process_one_work+0x520/0x1288 - [ 375.704658] worker_thread+0x3f0/0xb3c - [ 375.704680] kthread+0x334/0x3d8 - [ 375.704706] ret_from_fork+0x10/0x20 - [ 375.704736] ---[ end trace 0000000000000000 ]--- - -Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") -Cc: stable@vger.kernel.org -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 9cd74f935306cd857f46686975c43383e1d95f94 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 27 +++++++++++++++++++++---- - 1 file changed, 23 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index fc415dd0d7a7..8829c65747b6 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -179,7 +179,7 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { - - /** - * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is -- * backed by a UFO. -+ * already backed by a UFO. - * @f: The dma_fence to turn into a pvr_queue_fence. - * - * Return: -@@ -356,6 +356,15 @@ static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) - pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); - } - -+static bool -+is_paired_job_fence(struct dma_fence *fence, struct pvr_job *job) -+{ -+ /* This assumes "fence" is one of "job"'s drm_sched_job::dependencies */ -+ return job->type == DRM_PVR_JOB_TYPE_FRAGMENT && -+ job->paired_job && -+ &job->paired_job->base.s_fence->scheduled == fence; -+} -+ - /** - * job_count_remaining_native_deps() - Count the number of non-signaled native dependencies. - * @job: Job to operate on. -@@ -371,6 +380,17 @@ static unsigned long job_count_remaining_native_deps(struct pvr_job *job) - xa_for_each(&job->base.dependencies, index, fence) { - struct pvr_queue_fence *jfence; - -+ if (is_paired_job_fence(fence, job)) { -+ /* -+ * A fence between paired jobs won't resolve to a pvr_queue_fence (i.e. -+ * be backed by a UFO) until the jobs have been submitted, together. -+ * The submitting code will insert a partial render fence command for this. -+ */ -+ WARN_ON(dma_fence_is_signaled(fence)); -+ remaining_count++; -+ continue; -+ } -+ - jfence = to_pvr_queue_job_fence(fence); - if (!jfence) - continue; -@@ -630,9 +650,8 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -- /* Skip the partial render fence, we will place it at the end. */ -- if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job && -- &job->paired_job->base.s_fence->scheduled == fence) -+ /* This fence will be placed last, as partial render fence. */ -+ if (is_paired_job_fence(fence, job)) - continue; - - if (dma_fence_is_signaled(&jfence->base)) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0292-UPSTREAM-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux-lts-kmhv2/0292-UPSTREAM-riscv-Fix-fast_unaligned_access_speed_key-n.patch new file mode 100644 index 0000000000..bc05c34f71 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0292-UPSTREAM-riscv-Fix-fast_unaligned_access_speed_key-n.patch @@ -0,0 +1,68 @@ +From 6e571fa8e67dbd674e29f78d81c3ac573c603e38 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Tue, 7 Apr 2026 14:06:39 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: Fix fast_unaligned_access_speed_key not + getting initialized + +The static key fast_unaligned_access_speed_key is supposed to be +initialized after check_unaligned_access_all_cpus() has been completed. + +However, check_unaligned_access_all_cpus() has been moved to late_initcall +while setting fast_unaligned_access_speed_key still happens at +arch_initcall_sync, thus the static key does not get properly initialized. + +fast_unaligned_access_speed_key can still be initialized in CPU hotplug +events, but that cannot be relied on. + +Move fast_unaligned_access_speed_key's initialization into +check_unaligned_access_all_cpus() to fix this issue. This also prevent +someone from moving one initcall while forgetting the other in the future. + +Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") +Reported-by: Michael Neuling +Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ +Signed-off-by: Nam Cao +Link: https://patch.msgid.link/20260407120639.4006031-1-namcao@linutronix.de +Signed-off-by: Paul Walmsley +(cherry picked from commit aad60bdd0b5a6dfa40454ab03ce658408eaf4615) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/unaligned_access_speed.c | 15 ++++----------- + 1 file changed, 4 insertions(+), 11 deletions(-) + +diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c +index 70b5e6927620..5e224cc48c62 100644 +--- a/arch/riscv/kernel/unaligned_access_speed.c ++++ b/arch/riscv/kernel/unaligned_access_speed.c +@@ -223,17 +223,6 @@ static void set_unaligned_access_static_branches(void) + modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); + } + +-static int __init lock_and_set_unaligned_access_static_branch(void) +-{ +- cpus_read_lock(); +- set_unaligned_access_static_branches(); +- cpus_read_unlock(); +- +- return 0; +-} +- +-arch_initcall_sync(lock_and_set_unaligned_access_static_branch); +- + static int riscv_online_cpu(unsigned int cpu) + { + int ret = cpu_online_unaligned_access_init(cpu); +@@ -491,6 +480,10 @@ static int __init check_unaligned_access_all_cpus(void) + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu_vec, NULL); + ++ cpus_read_lock(); ++ set_unaligned_access_static_branches(); ++ cpus_read_unlock(); ++ + return 0; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch b/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch deleted file mode 100644 index 26a9e98208..0000000000 --- a/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch +++ /dev/null @@ -1,161 +0,0 @@ -From cc7e1eff70086b94e4cc0442c78e493d14ea2a91 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:37 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Fit paired fragment job in the - correct CCCB - -For geometry jobs with a paired fragment job, at the moment, the -DRM scheduler's prepare_job() callback: - -- checks for internal (driver) dependencies for the geometry job; -- calls into pvr_queue_get_paired_frag_job_dep() to check for external - dependencies for the fragment job (the two jobs are submitted together - but the common scheduler code doesn't know about it, so this needs to - be done at this point in time); -- calls into the prepare_job() callback again, but for the fragment job, - to check its internal dependencies as well, passing the fragment job's - drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. - -The problem with the last step is that pvr_queue_prepare_job() doesn't -always take the mismatched fragment job and geometry queue into account, -in particular when checking whether there is space for the fragment -command to be submitted, so the code ends up checking for space in the -geometry (i.e. wrong) CCCB. -The rest of the nested prepare_job() callback happens to work fine at -the moment as the other internal dependencies are not relevant for a -paired fragment job. - -Move the initialisation of a paired fragment job's done fence and CCCB -fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct -queue from the fragment job itself. - -This fixes cases where prepare_job() wrongly assumed that there was -enough space for a paired fragment job in its own CCCB, unblocking -run_job(), which then returned early without writing the full sequence -of commands to the CCCB. - -The above lead to kernel warnings such as the following and potentially -job timeouts (depending on waiters on the missing commands): - - [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 - [ 552.421230] Modules linked in: - [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT - [ 552.421625] Tainted: [W]=WARN - [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) - [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] - [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) - [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] - [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] - [ 552.421923] sp : ffff800084c47650 - [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 - [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 - [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 - [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 - [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 - [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 - [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 - [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 - [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 - [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f - [ 552.422316] Call trace: - [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) - [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] - [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] - [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] - [ 552.422623] process_one_work+0x520/0x1288 - [ 552.422657] worker_thread+0x3f0/0xb3c - [ 552.422679] kthread+0x334/0x3d8 - [ 552.422706] ret_from_fork+0x10/0x20 - -Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") -Cc: stable@vger.kernel.org -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 4baf9e70cb756d78dd56419f8baee2978a72d0c3 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 32 +++++++++++-------------- - 1 file changed, 14 insertions(+), 18 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 8829c65747b6..7d0d09026b82 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -488,10 +488,11 @@ pvr_queue_get_job_kccb_fence(struct pvr_queue *queue, struct pvr_job *job) - } - - static struct dma_fence * --pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) -+pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) - { - struct pvr_job *frag_job = job->type == DRM_PVR_JOB_TYPE_GEOMETRY ? - job->paired_job : NULL; -+ struct pvr_queue *frag_queue = frag_job ? frag_job->ctx->queues.fragment : NULL; - struct dma_fence *f; - unsigned long index; - -@@ -510,7 +511,10 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) - return dma_fence_get(f); - } - -- return frag_job->base.sched->ops->prepare_job(&frag_job->base, &queue->entity); -+ /* Initialize the paired fragment job's done_fence, so we can signal it. */ -+ pvr_queue_job_fence_init(frag_job->done_fence, frag_queue); -+ -+ return pvr_queue_get_job_cccb_fence(frag_queue, frag_job); - } - - /** -@@ -529,11 +533,6 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - struct pvr_queue *queue = container_of(s_entity, struct pvr_queue, entity); - struct dma_fence *internal_dep = NULL; - -- /* -- * Initialize the done_fence, so we can signal it. This must be done -- * here because otherwise by the time of run_job() the job will end up -- * in the pending list without a valid fence. -- */ - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { - /* - * This will be called on a paired fragment job after being -@@ -543,18 +542,15 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - */ - if (job->paired_job->has_pm_ref) - return NULL; -- -- /* -- * In this case we need to use the job's own ctx to initialise -- * the done_fence. The other steps are done in the ctx of the -- * paired geometry job. -- */ -- pvr_queue_job_fence_init(job->done_fence, -- job->ctx->queues.fragment); -- } else { -- pvr_queue_job_fence_init(job->done_fence, queue); - } - -+ /* -+ * Initialize the done_fence, so we can signal it. This must be done -+ * here because otherwise by the time of run_job() the job will end up -+ * in the pending list without a valid fence. -+ */ -+ pvr_queue_job_fence_init(job->done_fence, queue); -+ - /* CCCB fence is used to make sure we have enough space in the CCCB to - * submit our commands. - */ -@@ -575,7 +571,7 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - - /* The paired job fence should come last, when everything else is ready. */ - if (!internal_dep) -- internal_dep = pvr_queue_get_paired_frag_job_dep(queue, job); -+ internal_dep = pvr_queue_get_paired_frag_job_dep(job); - - return internal_dep; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0293-UPSTREAM-checkpatch-Suggest-kmalloc_obj-family-for-s.patch b/SPECS/linux-lts-kmhv2/0293-UPSTREAM-checkpatch-Suggest-kmalloc_obj-family-for-s.patch new file mode 100644 index 0000000000..bb7d00253d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0293-UPSTREAM-checkpatch-Suggest-kmalloc_obj-family-for-s.patch @@ -0,0 +1,84 @@ +From 0f2c5d969282094ed883fc5f1c347726659aad3d Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 3 Dec 2025 15:30:32 -0800 +Subject: [RUYI PATCH] UPSTREAM: checkpatch: Suggest kmalloc_obj family for + sizeof allocations + +To support shifting away from sized allocation towards typed +allocations, suggest the kmalloc_obj family of macros when a sizeof() is +present in the argument lists. + +Link: https://patch.msgid.link/20251203233036.3212363-2-kees@kernel.org +Signed-off-by: Kees Cook +(cherry picked from commit 070580b0b1740a4b930f367d21fdb5b253a8b3fb) +Signed-off-by: Han Gao +--- + scripts/checkpatch.pl | 39 +++++++++++++++++++++++++++++++++------ + 1 file changed, 33 insertions(+), 6 deletions(-) + +diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl +index 9979bf9f87bc..d85a5891e741 100755 +--- a/scripts/checkpatch.pl ++++ b/scripts/checkpatch.pl +@@ -7257,17 +7257,42 @@ sub process { + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +-# check for (kv|k)[mz]alloc with multiplies that could be kmalloc_array/kvmalloc_array/kvcalloc/kcalloc ++# check for (kv|k)[mz]alloc that could be kmalloc_obj/kvmalloc_obj/kzalloc_obj/kvzalloc_obj ++ if ($perl_version_ok && ++ defined $stat && ++ $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*,/) { ++ my $oldfunc = $3; ++ my $a1 = $4; ++ my $newfunc = "kmalloc_obj"; ++ $newfunc = "kvmalloc_obj" if ($oldfunc eq "kvmalloc"); ++ $newfunc = "kvzalloc_obj" if ($oldfunc eq "kvzalloc"); ++ $newfunc = "kzalloc_obj" if ($oldfunc eq "kzalloc"); ++ ++ if ($a1 =~ s/^sizeof\s*\S\(?([^\)]*)\)?$/$1/) { ++ my $cnt = statement_rawlines($stat); ++ my $herectx = get_stat_here($linenr, $cnt, $here); ++ ++ if (WARN("ALLOC_WITH_SIZEOF", ++ "Prefer $newfunc over $oldfunc with sizeof\n" . $herectx) && ++ $cnt == 1 && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*,/$1 = $newfunc($a1,/; ++ } ++ } ++ } ++ ++ ++# check for (kv|k)[mz]alloc with multiplies that could be kmalloc_objs/kvmalloc_objs/kzalloc_objs/kvzalloc_objs + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) { + my $oldfunc = $3; + my $a1 = $4; + my $a2 = $10; +- my $newfunc = "kmalloc_array"; +- $newfunc = "kvmalloc_array" if ($oldfunc eq "kvmalloc"); +- $newfunc = "kvcalloc" if ($oldfunc eq "kvzalloc"); +- $newfunc = "kcalloc" if ($oldfunc eq "kzalloc"); ++ my $newfunc = "kmalloc_objs"; ++ $newfunc = "kvmalloc_objs" if ($oldfunc eq "kvmalloc"); ++ $newfunc = "kvzalloc_objs" if ($oldfunc eq "kvzalloc"); ++ $newfunc = "kzalloc_objs" if ($oldfunc eq "kzalloc"); + my $r1 = $a1; + my $r2 = $a2; + if ($a1 =~ /^sizeof\s*\S/) { +@@ -7283,7 +7308,9 @@ sub process { + "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) && + $cnt == 1 && + $fix) { +- $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e; ++ my $sized = trim($r2); ++ $sized =~ s/^sizeof\s*\S\(?([^\)]*)\)?$/$1/; ++ $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . $sized . ', ' . trim($r1)/e; + } + } + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch b/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch deleted file mode 100644 index ef8b49eec6..0000000000 --- a/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch +++ /dev/null @@ -1,58 +0,0 @@ -From a64a810c6fa9b9f608d345c1c8fddcb487bf750a Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:38 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Skip check on paired job fence - during job submission - -While submitting a paired fragment job, there is no need to manually -look for, and skip, the paired job fence, as the existing logic to -resolve dependencies to pvr_queue_fence objects will have failed to -resolve it already and continued with the next one. - -Point this out where the fence is actually accessed and drop the related -check. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 18998b3cb7595850b8b2da55adb3fdc7aef8bc22 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 7d0d09026b82..6fdf74a1b73c 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -646,10 +646,6 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -- /* This fence will be placed last, as partial render fence. */ -- if (is_paired_job_fence(fence, job)) -- continue; -- - if (dma_fence_is_signaled(&jfence->base)) - continue; - -@@ -664,8 +660,13 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - } - } - -- /* Partial render fence goes last. */ - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { -+ /* -+ * The loop above will only process dependencies backed by a UFO i.e. with -+ * a valid parent fence assigned, but the paired job dependency won't have -+ * one until both jobs have been submitted. Access the parent fence directly -+ * here instead, submitting it last as partial render fence. -+ */ - jfence = to_pvr_queue_job_fence(job->paired_job->done_fence); - if (!WARN_ON(!jfence)) { - pvr_fw_object_get_fw_addr(jfence->queue->timeline_ufo.fw_obj, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0294-UPSTREAM-compiler_types-Introduce-__flex_counter-and.patch b/SPECS/linux-lts-kmhv2/0294-UPSTREAM-compiler_types-Introduce-__flex_counter-and.patch new file mode 100644 index 0000000000..905c983507 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0294-UPSTREAM-compiler_types-Introduce-__flex_counter-and.patch @@ -0,0 +1,145 @@ +From bb0199964817fab2ed25a40ae6a8b6f1df4e3bb9 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 3 Dec 2025 15:30:33 -0800 +Subject: [RUYI PATCH] UPSTREAM: compiler_types: Introduce __flex_counter() and + family + +Introduce __flex_counter() which wraps __builtin_counted_by_ref(), +as newly introduced by GCC[1] and Clang[2]. Use of __flex_counter() +allows access to the counter member of a struct's flexible array member +when it has been annotated with __counted_by(). + +Introduce typeof_flex_counter(), overflows_flex_counter_type(), and +__set_flex_counter() to provide the needed _Generic() wrappers to get +sane results out of __flex_counter(). + +For example, with: + + struct foo { + int counter; + short array[] __counted_by(counter); + } *p; + +__flex_counter(p->array) will resolve to: &p->counter + +typeof_flex_counter(p->array) will resolve to "int". (If p->array was not +annotated, it would resolve to "size_t".) + +overflows_flex_counter_type(typeof(*p), array, COUNT) is the same as: + + COUNT <= type_max(p->counter) && COUNT >= type_min(p->counter) + +(If p->array was not annotated it would return true since everything +fits in size_t.) + +__set_flex_counter(p->array, COUNT) is the same as: + + p->counter = COUNT; + +(It is a no-op if p->array is not annotated with __counted_by().) + +Link: https://patch.msgid.link/20251203233036.3212363-3-kees@kernel.org +Signed-off-by: Kees Cook +(cherry picked from commit 81cee9166a9073b4da28e970e75d7f89c98ed966) +Signed-off-by: Han Gao +--- + include/linux/compiler_types.h | 31 +++++++++++++++++++++++++ + include/linux/overflow.h | 42 ++++++++++++++++++++++++++++++++++ + 2 files changed, 73 insertions(+) + +diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h +index 2f18b8a01afe..1da5ab00193d 100644 +--- a/include/linux/compiler_types.h ++++ b/include/linux/compiler_types.h +@@ -529,6 +529,37 @@ struct ftrace_likely_data { + #define __annotated(var, attr) __builtin_has_attribute(var, attr) + #endif + ++/* ++ * Optional: only supported since gcc >= 15, clang >= 19 ++ * ++ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#index-_005f_005fbuiltin_005fcounted_005fby_005fref ++ * clang: https://clang.llvm.org/docs/LanguageExtensions.html#builtin-counted-by-ref ++ */ ++#if __has_builtin(__builtin_counted_by_ref) ++/** ++ * __flex_counter() - Get pointer to counter member for the given ++ * flexible array, if it was annotated with __counted_by() ++ * @FAM: Pointer to flexible array member of an addressable struct instance ++ * ++ * For example, with: ++ * ++ * struct foo { ++ * int counter; ++ * short array[] __counted_by(counter); ++ * } *p; ++ * ++ * __flex_counter(p->array) will resolve to &p->counter. ++ * ++ * Note that Clang may not allow this to be assigned to a separate ++ * variable; it must be used directly. ++ * ++ * If p->array is unannotated, this returns (void *)NULL. ++ */ ++#define __flex_counter(FAM) __builtin_counted_by_ref(FAM) ++#else ++#define __flex_counter(FAM) ((void *)NULL) ++#endif ++ + /* + * Some versions of gcc do not mark 'asm goto' volatile: + * +diff --git a/include/linux/overflow.h b/include/linux/overflow.h +index 725f95f7e416..f362e155a7ec 100644 +--- a/include/linux/overflow.h ++++ b/include/linux/overflow.h +@@ -540,4 +540,46 @@ static inline size_t __must_check size_sub(size_t minuend, size_t subtrahend) + (__member_size((name)->array) / sizeof(*(name)->array) + \ + __must_be_array((name)->array)) + ++/** ++ * typeof_flex_counter() - Return the type of the counter variable of a given ++ * flexible array member annotated by __counted_by(). ++ * @FAM: Instance of flexible array member within a given struct. ++ * ++ * Returns: "size_t" if no annotation exists. ++ */ ++#define typeof_flex_counter(FAM) \ ++ typeof(_Generic(__flex_counter(FAM), \ ++ void *: (size_t)0, \ ++ default: *__flex_counter(FAM))) ++ ++/** ++ * overflows_flex_counter_type() - Check if the counter associated with the ++ * given flexible array member can represent ++ * a value. ++ * @TYPE: Type of the struct that contains the @FAM. ++ * @FAM: Member name of the FAM within @TYPE. ++ * @COUNT: Value to check against the __counted_by annotated @FAM's counter. ++ * ++ * Returns: true if @COUNT can be represented in the @FAM's counter. When ++ * @FAM is not annotated with __counted_by(), always returns true. ++ */ ++#define overflows_flex_counter_type(TYPE, FAM, COUNT) \ ++ (!overflows_type(COUNT, typeof_flex_counter(((TYPE *)NULL)->FAM))) ++ ++/** ++ * __set_flex_counter() - Set the counter associated with the given flexible ++ * array member that has been annoated by __counted_by(). ++ * @FAM: Instance of flexible array member within a given struct. ++ * @COUNT: Value to store to the __counted_by annotated @FAM_PTR's counter. ++ * ++ * This is a no-op if no annotation exists. Count needs to be checked with ++ * overflows_flex_counter_type() before using this function. ++ */ ++#define __set_flex_counter(FAM, COUNT) \ ++({ \ ++ *_Generic(__flex_counter(FAM), \ ++ void *: &(size_t){ 0 }, \ ++ default: __flex_counter(FAM)) = (COUNT); \ ++}) ++ + #endif /* __LINUX_OVERFLOW_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch b/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch deleted file mode 100644 index 9cc27fddc4..0000000000 --- a/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 37bce3dfda3d6bfd8120dd4ca4ce59da566ffd8c Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:39 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename - pvr_queue_fence_is_ufo_backed() to reflect usage - -This function is only used by the synchronization code to figure out if -a fence belongs to this driver. -Rename it to pvr_queue_fence_is_native() and update its documentation to -reflect its current purpose. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit c162e655092de8de2e0f7776d72919dd5e3b84f2 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 14 +++++++------- - drivers/gpu/drm/imagination/pvr_queue.h | 2 +- - drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- - 3 files changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 6fdf74a1b73c..609ba457a619 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -898,16 +898,16 @@ static const struct drm_sched_backend_ops pvr_queue_sched_ops = { - }; - - /** -- * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO object -+ * pvr_queue_fence_is_native() - Check if a dma_fence is native to this driver. - * @f: Fence to test. - * -- * A UFO-backed fence is a fence that can be signaled or waited upon FW-side. -- * pvr_job::done_fence objects are backed by the timeline UFO attached to the queue -- * they are pushed to, but those fences are not directly exposed to the outside -- * world, so we also need to check if the fence we're being passed is a -- * drm_sched_fence that was coming from our driver. -+ * Check if the fence we're being passed is a drm_sched_fence that is coming from this driver. -+ * -+ * It may be a UFO-backed fence i.e. a fence that can be signaled or waited upon FW-side, -+ * such as pvr_job::done_fence objects that are backed by the timeline UFO attached to the queue -+ * they are pushed to. - */ --bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f) -+bool pvr_queue_fence_is_native(struct dma_fence *f) - { - struct drm_sched_fence *sched_fence = f ? to_drm_sched_fence(f) : NULL; - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.h b/drivers/gpu/drm/imagination/pvr_queue.h -index fc1986d73fc8..4aa72665ce25 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.h -+++ b/drivers/gpu/drm/imagination/pvr_queue.h -@@ -141,7 +141,7 @@ struct pvr_queue { - u64 callstack_addr; - }; - --bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f); -+bool pvr_queue_fence_is_native(struct dma_fence *f); - - int pvr_queue_job_init(struct pvr_job *job, u64 drm_client_id); - -diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c -index 129f646d14ba..d627c36e262f 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.c -+++ b/drivers/gpu/drm/imagination/pvr_sync.c -@@ -211,7 +211,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) - int err = 0; - - dma_fence_unwrap_for_each(uf, &iter, f) { -- if (pvr_queue_fence_is_ufo_backed(uf)) -+ if (pvr_queue_fence_is_native(uf)) - native_fence_count++; - } - -@@ -227,7 +227,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) - if (err) - continue; - -- if (pvr_queue_fence_is_ufo_backed(uf)) { -+ if (pvr_queue_fence_is_native(uf)) { - struct drm_sched_fence *s_fence = to_drm_sched_fence(uf); - - /* If this is a native dependency, we wait for the scheduled fence, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0295-UPSTREAM-slab-Introduce-kmalloc_flex-and-family.patch b/SPECS/linux-lts-kmhv2/0295-UPSTREAM-slab-Introduce-kmalloc_flex-and-family.patch new file mode 100644 index 0000000000..769e87b11d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0295-UPSTREAM-slab-Introduce-kmalloc_flex-and-family.patch @@ -0,0 +1,175 @@ +From d9fa1d68d8b36823ee40a365f0eab558c675d8f9 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 3 Dec 2025 15:30:34 -0800 +Subject: [RUYI PATCH] UPSTREAM: slab: Introduce kmalloc_flex() and family + +As done for kmalloc_obj*(), introduce a type-aware allocator for flexible +arrays, which may also have "counted_by" annotations: + + ptr = kmalloc(struct_size(ptr, flex_member, count), gfp); + +becomes: + + ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + +The internal use of __flex_counter() allows for automatically setting +the counter member of a struct's flexible array member when it has +been annotated with __counted_by(), avoiding any missed early size +initializations while __counted_by() annotations are added to the +kernel. Additionally, this also checks for "too large" allocations based +on the type size of the counter variable. For example: + + if (count > type_max(ptr->flex_counter)) + fail...; + size = struct_size(ptr, flex_member, count); + ptr = kmalloc(size, gfp); + if (!ptr) + fail...; + ptr->flex_counter = count; + +becomes (n.b. unchanged from earlier example): + + ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + if (!ptr) + fail...; + ptr->flex_counter = count; + +Note that manual initialization of the flexible array counter is still +required (at some point) after allocation as not all compiler versions +support the __counted_by annotation yet. But doing it internally makes +sure they cannot be missed when __counted_by _is_ available, meaning +that the bounds checker will not trip due to the lack of "early enough" +initializations that used to work before enabling the stricter bounds +checking. For example: + + ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + fill(ptr->flex, count); + ptr->flex_count = count; + +This works correctly before adding a __counted_by annotation (since +nothing is checking ptr->flex accesses against ptr->flex_count). After +adding the annotation, the bounds sanitizer would trip during fill() +because ptr->flex_count wasn't set yet. But with kmalloc_flex() setting +ptr->flex_count internally at allocation time, the existing code works +without needing to move the ptr->flex_count assignment before the call +to fill(). (This has been a stumbling block for __counted_by adoption.) + +Link: https://patch.msgid.link/20251203233036.3212363-4-kees@kernel.org +Acked-by: Vlastimil Babka +Signed-off-by: Kees Cook +(cherry picked from commit e4c8b46b924eb8de66c6f0accc9cdd0c2e8fa23b) +Signed-off-by: Han Gao +--- + Documentation/process/deprecated.rst | 7 ++++ + include/linux/slab.h | 48 ++++++++++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/Documentation/process/deprecated.rst b/Documentation/process/deprecated.rst +index 91c628fa2d59..fed56864d036 100644 +--- a/Documentation/process/deprecated.rst ++++ b/Documentation/process/deprecated.rst +@@ -387,6 +387,7 @@ allocations. For example, these open coded assignments:: + ptr = kzalloc(sizeof(*ptr), gfp); + ptr = kmalloc_array(count, sizeof(*ptr), gfp); + ptr = kcalloc(count, sizeof(*ptr), gfp); ++ ptr = kmalloc(struct_size(ptr, flex_member, count), gfp); + ptr = kmalloc(sizeof(struct foo, gfp); + + become, respectively:: +@@ -395,4 +396,10 @@ become, respectively:: + ptr = kzalloc_obj(*ptr, gfp); + ptr = kmalloc_objs(*ptr, count, gfp); + ptr = kzalloc_objs(*ptr, count, gfp); ++ ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + __auto_type ptr = kmalloc_obj(struct foo, gfp); ++ ++If `ptr->flex_member` is annotated with __counted_by(), the allocation ++will automatically fail if `count` is larger than the maximum ++representable value that can be stored in the counter member associated ++with `flex_member`. +diff --git a/include/linux/slab.h b/include/linux/slab.h +index cbb64a2698f5..7701b38cedec 100644 +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -982,6 +982,33 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + (TYPE *)KMALLOC(__obj_size, GFP); \ + }) + ++/** ++ * __alloc_flex - Allocate an object that has a trailing flexible array ++ * @KMALLOC: kmalloc wrapper function to use for allocation. ++ * @GFP: GFP flags for the allocation. ++ * @TYPE: type of structure to allocate space for. ++ * @FAM: The name of the flexible array member of @TYPE structure. ++ * @COUNT: how many @FAM elements to allocate space for. ++ * ++ * Returns: Newly allocated pointer to @TYPE with @COUNT-many trailing ++ * @FAM elements, or NULL on failure or if @COUNT cannot be represented ++ * by the member of @TYPE that counts the @FAM elements (annotated via ++ * __counted_by()). ++ */ ++#define __alloc_flex(KMALLOC, GFP, TYPE, FAM, COUNT) \ ++({ \ ++ const size_t __count = (COUNT); \ ++ const size_t __obj_size = struct_size_t(TYPE, FAM, __count); \ ++ TYPE *__obj_ptr; \ ++ if (WARN_ON_ONCE(overflows_flex_counter_type(TYPE, FAM, __count))) \ ++ __obj_ptr = NULL; \ ++ else \ ++ __obj_ptr = KMALLOC(__obj_size, GFP); \ ++ if (__obj_ptr) \ ++ __set_flex_counter(__obj_ptr->FAM, __count); \ ++ __obj_ptr; \ ++}) ++ + /** + * kmalloc_obj - Allocate a single instance of the given type + * @VAR_OR_TYPE: Variable or type to allocate. +@@ -1005,23 +1032,44 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + #define kmalloc_objs(VAR_OR_TYPE, COUNT, GFP) \ + __alloc_objs(kmalloc, GFP, typeof(VAR_OR_TYPE), COUNT) + ++/** ++ * kmalloc_flex - Allocate a single instance of the given flexible structure ++ * @VAR_OR_TYPE: Variable or type to allocate (with its flex array). ++ * @FAM: The name of the flexible array member of the structure. ++ * @COUNT: How many flexible array member elements are desired. ++ * @GFP: GFP flags for the allocation. ++ * ++ * Returns: newly allocated pointer to @VAR_OR_TYPE on success, NULL on ++ * failure. If @FAM has been annotated with __counted_by(), the allocation ++ * will immediately fail if @COUNT is larger than what the type of the ++ * struct's counter variable can represent. ++ */ ++#define kmalloc_flex(VAR_OR_TYPE, FAM, COUNT, GFP) \ ++ __alloc_flex(kmalloc, GFP, typeof(VAR_OR_TYPE), FAM, COUNT) ++ + /* All kzalloc aliases for kmalloc_(obj|objs|flex). */ + #define kzalloc_obj(P, GFP) \ + __alloc_objs(kzalloc, GFP, typeof(P), 1) + #define kzalloc_objs(P, COUNT, GFP) \ + __alloc_objs(kzalloc, GFP, typeof(P), COUNT) ++#define kzalloc_flex(P, FAM, COUNT, GFP) \ ++ __alloc_flex(kzalloc, GFP, typeof(P), FAM, COUNT) + + /* All kvmalloc aliases for kmalloc_(obj|objs|flex). */ + #define kvmalloc_obj(P, GFP) \ + __alloc_objs(kvmalloc, GFP, typeof(P), 1) + #define kvmalloc_objs(P, COUNT, GFP) \ + __alloc_objs(kvmalloc, GFP, typeof(P), COUNT) ++#define kvmalloc_flex(P, FAM, COUNT, GFP) \ ++ __alloc_flex(kvmalloc, GFP, typeof(P), FAM, COUNT) + + /* All kvzalloc aliases for kmalloc_(obj|objs|flex). */ + #define kvzalloc_obj(P, GFP) \ + __alloc_objs(kvzalloc, GFP, typeof(P), 1) + #define kvzalloc_objs(P, COUNT, GFP) \ + __alloc_objs(kvzalloc, GFP, typeof(P), COUNT) ++#define kvzalloc_flex(P, FAM, COUNT, GFP) \ ++ __alloc_flex(kvzalloc, GFP, typeof(P), FAM, COUNT) + + #define kmem_buckets_alloc(_b, _size, _flags) \ + alloc_hooks(__kmalloc_node_noprof(PASS_BUCKET_PARAMS(_size, _b), _flags, NUMA_NO_NODE)) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch b/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch deleted file mode 100644 index 726a6e00f1..0000000000 --- a/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 1b5c97a61b1f397f31c97959e50a7bafe4997757 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:40 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename fence returned by - pvr_queue_job_arm() - -Rename from done_fence to finished_fence, both because the function -returns a drm_sched_fence's finished fence, and to avoid confusion with -the job fence, which is called the same but has a different purpose. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 5dae1a21f1e7128a19c68212422383f700699d01 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_job.c | 8 ++++---- - drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- - drivers/gpu/drm/imagination/pvr_sync.h | 2 +- - 3 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c -index 7564b0f21b42..2da61083ab3e 100644 ---- a/drivers/gpu/drm/imagination/pvr_job.c -+++ b/drivers/gpu/drm/imagination/pvr_job.c -@@ -326,7 +326,7 @@ prepare_job_syncs(struct pvr_file *pvr_file, - struct pvr_job_data *job_data, - struct xarray *signal_array) - { -- struct dma_fence *done_fence; -+ struct dma_fence *finished_fence; - int err = pvr_sync_signal_array_collect_ops(signal_array, - from_pvr_file(pvr_file), - job_data->sync_op_count, -@@ -359,13 +359,13 @@ prepare_job_syncs(struct pvr_file *pvr_file, - return err; - } - -- /* We need to arm the job to get the job done fence. */ -- done_fence = pvr_queue_job_arm(job_data->job); -+ /* We need to arm the job to get the job finished fence. */ -+ finished_fence = pvr_queue_job_arm(job_data->job); - - err = pvr_sync_signal_array_update_fences(signal_array, - job_data->sync_op_count, - job_data->sync_ops, -- done_fence); -+ finished_fence); - return err; - } - -diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c -index d627c36e262f..45ac7a0aff65 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.c -+++ b/drivers/gpu/drm/imagination/pvr_sync.c -@@ -160,7 +160,7 @@ int - pvr_sync_signal_array_update_fences(struct xarray *array, - u32 sync_op_count, - const struct drm_pvr_sync_op *sync_ops, -- struct dma_fence *done_fence) -+ struct dma_fence *finished_fence) - { - for (u32 i = 0; i < sync_op_count; i++) { - struct dma_fence *old_fence; -@@ -175,7 +175,7 @@ pvr_sync_signal_array_update_fences(struct xarray *array, - return -EINVAL; - - old_fence = sig_sync->fence; -- sig_sync->fence = dma_fence_get(done_fence); -+ sig_sync->fence = dma_fence_get(finished_fence); - dma_fence_put(old_fence); - - if (WARN_ON(!sig_sync->fence)) -diff --git a/drivers/gpu/drm/imagination/pvr_sync.h b/drivers/gpu/drm/imagination/pvr_sync.h -index db6ccfda104a..48501ad27794 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.h -+++ b/drivers/gpu/drm/imagination/pvr_sync.h -@@ -70,7 +70,7 @@ int - pvr_sync_signal_array_update_fences(struct xarray *array, - u32 sync_op_count, - const struct drm_pvr_sync_op *sync_ops, -- struct dma_fence *done_fence); -+ struct dma_fence *finished_fence); - - void - pvr_sync_signal_array_push_fences(struct xarray *array); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0296-UPSTREAM-slab.h-disable-completely-broken-overflow-h.patch b/SPECS/linux-lts-kmhv2/0296-UPSTREAM-slab.h-disable-completely-broken-overflow-h.patch new file mode 100644 index 0000000000..4eb6820d4d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0296-UPSTREAM-slab.h-disable-completely-broken-overflow-h.patch @@ -0,0 +1,70 @@ +From e163512ed18c577583d18b04cc24da6dfff50e4d Mon Sep 17 00:00:00 2001 +From: Linus Torvalds +Date: Sat, 21 Feb 2026 15:12:09 -0800 +Subject: [RUYI PATCH] UPSTREAM: slab.h: disable completely broken overflow + handling in flex allocations + +Commit 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for +non-scalar types") started using the new allocation helpers, and in the +process showed that they were completely non-working. + +The overflow logic in overflows_flex_counter_type() is completely the +wrong way around, and that broke __alloc_flex() completely. By chance, +the resulting code was then such a mess that clang generated +sufficiently garbage code that objtool warned about it all. Which made +it somewhat quicker to narrow things down. + +While fixing overflows_flex_counter_type() would presumably fix this +all, I'm excising the whole broken overflow logic from __alloc_flex(), +because we don't want that kind of code in basic allocation functions +anyway. + +That (no longer) broken overflows_flex_counter_type() thing needs to be +inserted into the actual __set_flex_counter() logic in the unlikely case +that we ever want this at all. And made conditional. + +Fixes: 81cee9166a90 ("compiler_types: Introduce __flex_counter() and family") +Fixes: 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for non-scalar types") +Cc: Kees Cook +Link: https://lore.kernel.org/all/CAHk-=whEd020BYzGTzYrENjD9Z5_82xx6h8HsQvH5xDSnv0=Hw@mail.gmail.com/ +Signed-off-by: Linus Torvalds +(cherry picked from commit fa5c82f4d2bbde10e9fd3a32aecacfe3813919ba) +Signed-off-by: Han Gao +--- + include/linux/overflow.h | 2 +- + include/linux/slab.h | 6 +----- + 2 files changed, 2 insertions(+), 6 deletions(-) + +diff --git a/include/linux/overflow.h b/include/linux/overflow.h +index f362e155a7ec..7b2e5b1d30ed 100644 +--- a/include/linux/overflow.h ++++ b/include/linux/overflow.h +@@ -564,7 +564,7 @@ static inline size_t __must_check size_sub(size_t minuend, size_t subtrahend) + * @FAM is not annotated with __counted_by(), always returns true. + */ + #define overflows_flex_counter_type(TYPE, FAM, COUNT) \ +- (!overflows_type(COUNT, typeof_flex_counter(((TYPE *)NULL)->FAM))) ++ (overflows_type(COUNT, typeof_flex_counter(((TYPE *)NULL)->FAM))) + + /** + * __set_flex_counter() - Set the counter associated with the given flexible +diff --git a/include/linux/slab.h b/include/linux/slab.h +index 7701b38cedec..4e9119d8bd4c 100644 +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -999,11 +999,7 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + ({ \ + const size_t __count = (COUNT); \ + const size_t __obj_size = struct_size_t(TYPE, FAM, __count); \ +- TYPE *__obj_ptr; \ +- if (WARN_ON_ONCE(overflows_flex_counter_type(TYPE, FAM, __count))) \ +- __obj_ptr = NULL; \ +- else \ +- __obj_ptr = KMALLOC(__obj_size, GFP); \ ++ TYPE *__obj_ptr = KMALLOC(__obj_size, GFP); \ + if (__obj_ptr) \ + __set_flex_counter(__obj_ptr->FAM, __count); \ + __obj_ptr; \ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch b/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch deleted file mode 100644 index aaa07dc5cb..0000000000 --- a/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 03aa10e9329f54737669ec56c2b2ab66eac2f987 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:41 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Move repeated job fence check - to its own function - -This should make the code slightly clearer. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 402562e60c6c1b15ee359ba7ffed907baa886a99 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 25 ++++++++++++++++++++----- - 1 file changed, 20 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 609ba457a619..2a26b87d146d 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -177,6 +177,24 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { - .release = pvr_queue_fence_release, - }; - -+/** -+ * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO. -+ * @f: The dma_fence to check. -+ * -+ * Return: -+ * * true if the dma_fence is backed by a UFO, or -+ * * false otherwise. -+ */ -+static inline bool -+pvr_queue_fence_is_ufo_backed(struct dma_fence *f) -+{ -+ /* -+ * Currently the only dma_fence backed by a UFO object is the job fence, -+ * e.g. pvr_job::done_fence, wrapped by a pvr_queue_fence object. -+ */ -+ return f && f->ops == &pvr_queue_job_fence_ops; -+} -+ - /** - * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is - * already backed by a UFO. -@@ -194,7 +212,7 @@ to_pvr_queue_job_fence(struct dma_fence *f) - if (sched_fence) - f = sched_fence->parent; - -- if (f && f->ops == &pvr_queue_job_fence_ops) -+ if (pvr_queue_fence_is_ufo_backed(f)) - return container_of(f, struct pvr_queue_fence, base); - - return NULL; -@@ -915,10 +933,7 @@ bool pvr_queue_fence_is_native(struct dma_fence *f) - sched_fence->sched->ops == &pvr_queue_sched_ops) - return true; - -- if (f && f->ops == &pvr_queue_job_fence_ops) -- return true; -- -- return false; -+ return pvr_queue_fence_is_ufo_backed(f); - } - - /** --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0297-UPSTREAM-add-default_gfp-helper-macro-and-use-it-in-.patch b/SPECS/linux-lts-kmhv2/0297-UPSTREAM-add-default_gfp-helper-macro-and-use-it-in-.patch new file mode 100644 index 0000000000..40dd16ac19 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0297-UPSTREAM-add-default_gfp-helper-macro-and-use-it-in-.patch @@ -0,0 +1,135 @@ +From 6d5529550ccb5aa91a302877ba0554fc515ace92 Mon Sep 17 00:00:00 2001 +From: Linus Torvalds +Date: Sat, 21 Feb 2026 16:14:11 -0800 +Subject: [RUYI PATCH] UPSTREAM: add default_gfp() helper macro and use it in + the new *alloc_obj() helpers + +Most simple allocations use GFP_KERNEL, and with the new allocation +helpers being introduced, let's just take advantage of that to simplify +that default case. + +It's a numbers game: + + git grep 'alloc_obj(' | + sed 's/.*\(GFP_[_A-Z]*\).*/\1/' | + sort | uniq -c | sort -n | tail + +shows that about 90% of all those new allocator instances just use that +standard GFP_KERNEL. + +Those helpers are already macros, and we can easily just make it be the +default case when the gfp argument is missing. + +And yes, we could do that for all the legacy interfaces too, but let's +keep it to just the new ones at least for now, since those all got +converted recently anyway, so this is not any "extra" noise outside of +that limited conversion. + +And, in fact, I want to do this before doing the -rc1 release, exactly +so that we don't get extra merge conflicts. + +Signed-off-by: Linus Torvalds +(cherry picked from commit e19e1b480ac73c3e62ffebbca1174f0f511f43e7) +Signed-off-by: Han Gao +--- + include/linux/gfp.h | 4 ++++ + include/linux/slab.h | 48 ++++++++++++++++++++++---------------------- + 2 files changed, 28 insertions(+), 24 deletions(-) + +diff --git a/include/linux/gfp.h b/include/linux/gfp.h +index b155929af5b1..09559f7126ac 100644 +--- a/include/linux/gfp.h ++++ b/include/linux/gfp.h +@@ -13,6 +13,10 @@ + struct vm_area_struct; + struct mempolicy; + ++/* Helper macro to avoid gfp flags if they are the default one */ ++#define __default_gfp(a,...) a ++#define default_gfp(...) __default_gfp(__VA_ARGS__ __VA_OPT__(,) GFP_KERNEL) ++ + /* Convert GFP flags to their corresponding migrate type */ + #define GFP_MOVABLE_MASK (__GFP_RECLAIMABLE|__GFP_MOVABLE) + #define GFP_MOVABLE_SHIFT 3 +diff --git a/include/linux/slab.h b/include/linux/slab.h +index 4e9119d8bd4c..8f3c7f4948eb 100644 +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -1013,8 +1013,8 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + * Returns: newly allocated pointer to a @VAR_OR_TYPE on success, or NULL + * on failure. + */ +-#define kmalloc_obj(VAR_OR_TYPE, GFP) \ +- __alloc_objs(kmalloc, GFP, typeof(VAR_OR_TYPE), 1) ++#define kmalloc_obj(VAR_OR_TYPE, ...) \ ++ __alloc_objs(kmalloc, default_gfp(__VA_ARGS__), typeof(VAR_OR_TYPE), 1) + + /** + * kmalloc_objs - Allocate an array of the given type +@@ -1025,8 +1025,8 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + * Returns: newly allocated pointer to array of @VAR_OR_TYPE on success, + * or NULL on failure. + */ +-#define kmalloc_objs(VAR_OR_TYPE, COUNT, GFP) \ +- __alloc_objs(kmalloc, GFP, typeof(VAR_OR_TYPE), COUNT) ++#define kmalloc_objs(VAR_OR_TYPE, COUNT, ...) \ ++ __alloc_objs(kmalloc, default_gfp(__VA_ARGS__), typeof(VAR_OR_TYPE), COUNT) + + /** + * kmalloc_flex - Allocate a single instance of the given flexible structure +@@ -1040,32 +1040,32 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + * will immediately fail if @COUNT is larger than what the type of the + * struct's counter variable can represent. + */ +-#define kmalloc_flex(VAR_OR_TYPE, FAM, COUNT, GFP) \ +- __alloc_flex(kmalloc, GFP, typeof(VAR_OR_TYPE), FAM, COUNT) ++#define kmalloc_flex(VAR_OR_TYPE, FAM, COUNT, ...) \ ++ __alloc_flex(kmalloc, default_gfp(__VA_ARGS__), typeof(VAR_OR_TYPE), FAM, COUNT) + + /* All kzalloc aliases for kmalloc_(obj|objs|flex). */ +-#define kzalloc_obj(P, GFP) \ +- __alloc_objs(kzalloc, GFP, typeof(P), 1) +-#define kzalloc_objs(P, COUNT, GFP) \ +- __alloc_objs(kzalloc, GFP, typeof(P), COUNT) +-#define kzalloc_flex(P, FAM, COUNT, GFP) \ +- __alloc_flex(kzalloc, GFP, typeof(P), FAM, COUNT) ++#define kzalloc_obj(P, ...) \ ++ __alloc_objs(kzalloc, default_gfp(__VA_ARGS__), typeof(P), 1) ++#define kzalloc_objs(P, COUNT, ...) \ ++ __alloc_objs(kzalloc, default_gfp(__VA_ARGS__), typeof(P), COUNT) ++#define kzalloc_flex(P, FAM, COUNT, ...) \ ++ __alloc_flex(kzalloc, default_gfp(__VA_ARGS__), typeof(P), FAM, COUNT) + + /* All kvmalloc aliases for kmalloc_(obj|objs|flex). */ +-#define kvmalloc_obj(P, GFP) \ +- __alloc_objs(kvmalloc, GFP, typeof(P), 1) +-#define kvmalloc_objs(P, COUNT, GFP) \ +- __alloc_objs(kvmalloc, GFP, typeof(P), COUNT) +-#define kvmalloc_flex(P, FAM, COUNT, GFP) \ +- __alloc_flex(kvmalloc, GFP, typeof(P), FAM, COUNT) ++#define kvmalloc_obj(P, ...) \ ++ __alloc_objs(kvmalloc, default_gfp(__VA_ARGS__), typeof(P), 1) ++#define kvmalloc_objs(P, COUNT, ...) \ ++ __alloc_objs(kvmalloc, default_gfp(__VA_ARGS__), typeof(P), COUNT) ++#define kvmalloc_flex(P, FAM, COUNT, ...) \ ++ __alloc_flex(kvmalloc, default_gfp(__VA_ARGS__), typeof(P), FAM, COUNT) + + /* All kvzalloc aliases for kmalloc_(obj|objs|flex). */ +-#define kvzalloc_obj(P, GFP) \ +- __alloc_objs(kvzalloc, GFP, typeof(P), 1) +-#define kvzalloc_objs(P, COUNT, GFP) \ +- __alloc_objs(kvzalloc, GFP, typeof(P), COUNT) +-#define kvzalloc_flex(P, FAM, COUNT, GFP) \ +- __alloc_flex(kvzalloc, GFP, typeof(P), FAM, COUNT) ++#define kvzalloc_obj(P, ...) \ ++ __alloc_objs(kvzalloc, default_gfp(__VA_ARGS__), typeof(P), 1) ++#define kvzalloc_objs(P, COUNT, ...) \ ++ __alloc_objs(kvzalloc, default_gfp(__VA_ARGS__), typeof(P), COUNT) ++#define kvzalloc_flex(P, FAM, COUNT, ...) \ ++ __alloc_flex(kvzalloc, default_gfp(__VA_ARGS__), typeof(P), FAM, COUNT) + + #define kmem_buckets_alloc(_b, _size, _flags) \ + alloc_hooks(__kmalloc_node_noprof(PASS_BUCKET_PARAMS(_size, _b), _flags, NUMA_NO_NODE)) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch b/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch deleted file mode 100644 index c27054fa2d..0000000000 --- a/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch +++ /dev/null @@ -1,49 +0,0 @@ -From de6096b77f0bf0bf39ff10bd616f13c5e0945d58 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:42 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Update check to skip - prepare_job() for fragment jobs - -By the time prepare_job() is called on a paired fragment job, the paired -geometry job might already be finished and its PM reference dropped. - -Check the fragment job's PM reference instead which is a bit more likely -to be still set. This is a very minor optimization. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 5c81eb2970133ad073214eb1e5b0c34a1ae793eb - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 2a26b87d146d..00cc0dd4ca2b 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -553,12 +553,13 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { - /* -- * This will be called on a paired fragment job after being -- * submitted to firmware. We can tell if this is the case and -- * bail early from whether run_job() has been called on the -- * geometry job, which would issue a pm ref. -+ * This will be called on a paired fragment job after being submitted -+ * to the firmware as part of the paired geometry job's submission. -+ * We can tell if this is the case and bail early from whether run_job() -+ * has been called on the geometry job, which would issue a pm ref on -+ * this job as well. - */ -- if (job->paired_job->has_pm_ref) -+ if (job->has_pm_ref) - return NULL; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0298-UPSTREAM-of-Add-wrappers-to-match-root-node-with-OF-.patch b/SPECS/linux-lts-kmhv2/0298-UPSTREAM-of-Add-wrappers-to-match-root-node-with-OF-.patch new file mode 100644 index 0000000000..7288fce455 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0298-UPSTREAM-of-Add-wrappers-to-match-root-node-with-OF-.patch @@ -0,0 +1,125 @@ +From fe8a4dbdb43b413a60322ec8219c7316b5bf8125 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Wed, 12 Nov 2025 11:28:46 +0100 +Subject: [RUYI PATCH] UPSTREAM: of: Add wrappers to match root node with OF + device ID tables + +Several drivers duplicate same code for getting reference to the root +node, matching it against 'struct of_device_id' table and getting out +the match data from the table entry. + +There is a of_machine_compatible_match() wrapper but it takes array of +strings, which is not suitable for many drivers since they want the +driver data associated with each compatible. + +Add two wrappers, similar to existing of_device_get_match_data(): +1. of_machine_device_match() doing only matching against 'struct + of_device_id' and returning bool. +2. of_machine_get_match_data() doing the matching and returning + associated driver data for found compatible. + +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Lukasz Luba +Tested-by: AngeloGioacchino Del Regno +Link: https://patch.msgid.link/20251112-b4-of-match-matchine-data-v2-1-d46b72003fd6@linaro.org +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 4a93adcbd201aad5ba607810cfe1b19d44e5d171) +Signed-off-by: Han Gao +--- + drivers/of/base.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++ + include/linux/of.h | 13 +++++++++++++ + 2 files changed, 60 insertions(+) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index 6620bf07b79b..8d1972e18161 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -434,6 +434,53 @@ bool of_machine_compatible_match(const char *const *compats) + } + EXPORT_SYMBOL(of_machine_compatible_match); + ++/** ++ * of_machine_device_match - Test root of device tree against a of_device_id array ++ * @matches: NULL terminated array of of_device_id match structures to search in ++ * ++ * Returns true if the root node has any of the given compatible values in its ++ * compatible property. ++ */ ++bool of_machine_device_match(const struct of_device_id *matches) ++{ ++ struct device_node *root; ++ const struct of_device_id *match = NULL; ++ ++ root = of_find_node_by_path("/"); ++ if (root) { ++ match = of_match_node(matches, root); ++ of_node_put(root); ++ } ++ ++ return match != NULL; ++} ++EXPORT_SYMBOL(of_machine_device_match); ++ ++/** ++ * of_machine_get_match_data - Tell if root of device tree has a matching of_match structure ++ * @matches: NULL terminated array of of_device_id match structures to search in ++ * ++ * Returns data associated with matched entry or NULL ++ */ ++const void *of_machine_get_match_data(const struct of_device_id *matches) ++{ ++ const struct of_device_id *match; ++ struct device_node *root; ++ ++ root = of_find_node_by_path("/"); ++ if (!root) ++ return NULL; ++ ++ match = of_match_node(matches, root); ++ of_node_put(root); ++ ++ if (!match) ++ return NULL; ++ ++ return match->data; ++} ++EXPORT_SYMBOL(of_machine_get_match_data); ++ + static bool __of_device_is_status(const struct device_node *device, + const char * const*strings) + { +diff --git a/include/linux/of.h b/include/linux/of.h +index 121a288ca92d..01bb3affcd49 100644 +--- a/include/linux/of.h ++++ b/include/linux/of.h +@@ -407,6 +407,8 @@ extern int of_alias_get_id(const struct device_node *np, const char *stem); + extern int of_alias_get_highest_id(const char *stem); + + bool of_machine_compatible_match(const char *const *compats); ++bool of_machine_device_match(const struct of_device_id *matches); ++const void *of_machine_get_match_data(const struct of_device_id *matches); + + /** + * of_machine_is_compatible - Test root of device tree for a given compatible value +@@ -855,6 +857,17 @@ static inline bool of_machine_compatible_match(const char *const *compats) + return false; + } + ++static inline bool of_machine_device_match(const struct of_device_id *matches) ++{ ++ return false; ++} ++ ++static inline const void * ++of_machine_get_match_data(const struct of_device_id *matches) ++{ ++ return NULL; ++} ++ + static inline bool of_console_check(const struct device_node *dn, const char *name, int index) + { + return false; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch b/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch deleted file mode 100644 index e093399458..0000000000 --- a/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch +++ /dev/null @@ -1,141 +0,0 @@ -From fea5671abc67fb18ac13ed5ac838464e6ac1d034 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:43 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Minor improvements to job - submission code documentation - -Mixed list of clarifications and typo fixes. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-8-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 62a36c2da774800bef893bc4bf8922fb9c07c1d0 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 38 ++++++++++++------- - .../drm/imagination/pvr_rogue_fwif_shared.h | 10 +---- - 2 files changed, 26 insertions(+), 22 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 00cc0dd4ca2b..21803d3cfbb4 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -200,6 +200,13 @@ pvr_queue_fence_is_ufo_backed(struct dma_fence *f) - * already backed by a UFO. - * @f: The dma_fence to turn into a pvr_queue_fence. - * -+ * This could be called on: -+ * - a job fence directly, in which case it simply returns the containing pvr_queue_fence; -+ * - a drm_sched_fence's scheduled or finished fence, in which case it will first try to follow -+ * the parent pointer to find the job fence (note that the parent pointer is initialized -+ * only after the run_job() callback is called on the drm_sched_fence's owning job); -+ * - any other dma_fence, in which case it will return NULL. -+ * - * Return: - * * A non-NULL pvr_queue_fence object if the dma_fence is backed by a UFO, or - * * NULL otherwise. -@@ -367,11 +374,14 @@ static u32 ufo_cmds_size(u32 elem_count) - - static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) - { -- /* One UFO cmd for the fence signaling, one UFO cmd per native fence native, -- * and a command for the job itself. -+ /* -+ * One UFO command per native fence this job will be waiting on (unless any are -+ * signaled by the time the job is submitted), plus a command for the job itself, -+ * plus one UFO command for the fence signaling. - */ -- return ufo_cmds_size(1) + ufo_cmds_size(ufo_wait_count) + -- pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); -+ return ufo_cmds_size(ufo_wait_count) + -+ pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len) + -+ ufo_cmds_size(1); - } - - static bool -@@ -517,12 +527,16 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) - if (!frag_job) - return NULL; - -+ /* Have the geometry job wait on the paired fragment job's dependencies as well. */ - xa_for_each(&frag_job->base.dependencies, index, f) { - /* Skip already signaled fences. */ - if (dma_fence_is_signaled(f)) - continue; - -- /* Skip our own fence. */ -+ /* -+ * The paired job fence won't be signaled until both jobs have -+ * been submitted, so we can't wait on it to schedule them. -+ */ - if (f == &job->base.s_fence->scheduled) - continue; - -@@ -665,6 +679,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -+ /* Some dependencies might have been signaled since prepare_job() */ - if (dma_fence_is_signaled(&jfence->base)) - continue; - -@@ -714,7 +729,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - pvr_cccb_write_command_with_header(cccb, job->fw_ccb_cmd_type, job->cmd_len, job->cmd, - job->id, job->id); - -- /* Signal the job fence. */ -+ /* Update command to signal the job fence. */ - pvr_fw_object_get_fw_addr(queue->timeline_ufo.fw_obj, &ufos[0].addr); - ufos[0].value = job->done_fence->seqno; - pvr_cccb_write_command_with_header(cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE, -@@ -744,10 +759,8 @@ static struct dma_fence *pvr_queue_run_job(struct drm_sched_job *sched_job) - } - - /* The only kind of jobs that can be paired are geometry and fragment, and -- * we bail out early if we see a fragment job that's paired with a geomtry -- * job. -- * Paired jobs must also target the same context and point to the same -- * HWRT. -+ * we bail out early if we see a fragment job that's paired with a geometry job. -+ * Paired jobs must also target the same context and point to the same HWRT. - */ - if (WARN_ON(job->paired_job && - (job->type != DRM_PVR_JOB_TYPE_GEOMETRY || -@@ -966,9 +979,8 @@ pvr_queue_signal_done_fences(struct pvr_queue *queue) - } - - /** -- * pvr_queue_check_job_waiting_for_cccb_space() - Check if the job waiting for CCCB space -- * can be unblocked -- * pushed to the CCCB -+ * pvr_queue_check_job_waiting_for_cccb_space() - Check if a job waiting for CCCB space -+ * can be unblocked and pushed to the CCCB. - * @queue: Queue to check - * - * If we have a job waiting for CCCB, and this job now fits in the CCCB, we signal -diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -index 869d904e3649..fe54c1cad7a9 100644 ---- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -@@ -14,15 +14,7 @@ - - #define ROGUE_NUM_GEOM_CORES_SIZE 2U - --/* -- * Maximum number of UFOs in a CCB command. -- * The number is based on having 32 sync prims (as originally), plus 32 sync -- * checkpoints. -- * Once the use of sync prims is no longer supported, we will retain -- * the same total (64) as the number of sync checkpoints which may be -- * supporting a fence is not visible to the client driver and has to -- * allow for the number of different timelines involved in fence merges. -- */ -+/* Maximum number of UFOs in a CCB command. */ - #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) - - /* --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0299-UPSTREAM-cpufreq-qcom-nvmem-add-compatible-fallback-.patch b/SPECS/linux-lts-kmhv2/0299-UPSTREAM-cpufreq-qcom-nvmem-add-compatible-fallback-.patch new file mode 100644 index 0000000000..9e4db2f1b7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0299-UPSTREAM-cpufreq-qcom-nvmem-add-compatible-fallback-.patch @@ -0,0 +1,88 @@ +From 6855c96e22f6f0a72a729f84c4bc445490ba7569 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 5 Nov 2025 12:21:34 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: qcom-nvmem: add compatible fallback + for ipq806x for no SMEM + +On some IPQ806x SoC SMEM might be not initialized by SBL. This is the +case for some Google devices (the OnHub family) that can't make use of +SMEM to detect the SoC ID (and socinfo can't be used either as it does +depends on SMEM presence). + +To handle these specific case, check if the SMEM is not initialized (by +checking if the qcom_smem_get_soc_id returns -ENODEV) and fallback to +OF machine compatible checking to identify the SoC variant. + +Suggested-by: Dmitry Baryshkov +Reviewed-by: Konrad Dybcio +Signed-off-by: Christian Marangi +Signed-off-by: Viresh Kumar +(cherry picked from commit 58f5d39d5ed8f2e43f230389ea0d59791afdcd55) +Signed-off-by: Han Gao +--- + drivers/cpufreq/qcom-cpufreq-nvmem.c | 35 ++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c +index 765a5bb81829..d5af74bf71c6 100644 +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -256,13 +256,22 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, + return ret; + } + ++static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] = { ++ { .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 }, ++ { .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 }, ++ { .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 }, ++ { .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 }, ++ { .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 }, ++ { .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 }, ++}; ++ + static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) + { ++ int msm_id = -1, ret = 0; + int speed = 0, pvs = 0; +- int msm_id, ret = 0; + u8 *speedbin; + size_t len; + +@@ -279,8 +288,30 @@ static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + ret = qcom_smem_get_soc_id(&msm_id); +- if (ret) ++ if (ret == -ENODEV) { ++ const struct of_device_id *match; ++ struct device_node *root; ++ ++ root = of_find_node_by_path("/"); ++ if (!root) { ++ ret = -ENODEV; ++ goto exit; ++ } ++ ++ /* Fallback to compatible match with no SMEM initialized */ ++ match = of_match_node(qcom_cpufreq_ipq806x_match_list, root); ++ of_node_put(root); ++ if (!match) { ++ ret = -ENODEV; ++ goto exit; ++ } ++ ++ /* We found a matching device, get the msm_id from the data entry */ ++ msm_id = (int)(uintptr_t)match->data; ++ ret = 0; ++ } else if (ret) { + goto exit; ++ } + + switch (msm_id) { + case QCOM_ID_IPQ8062: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch b/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch deleted file mode 100644 index ed087c87c3..0000000000 --- a/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From d6e9674d63435e685b8f714dd05c6d76d0cd3383 Mon Sep 17 00:00:00 2001 -From: Li Guan -Date: Thu, 14 May 2026 02:07:21 +0800 -Subject: [RUYI PATCH] FROMGIT: perf riscv: Fix discarded const qualifier in - _get_field() - -The assignment of strrchr() return values to non-const char * variables -triggers a -Werror=discarded-qualifiers warning when building with GCC -14. - -This happens because in newer glibc versions, strrchr() returns a 'const -char *' if the input string is const. - -Properly declare 'line2' and 'nl' as const char * to match the glibc -function signature and ensure type safety. This avoids the need for -explicit type casting and aligns with the design pattern of not -modifying read-only memory in the perf tool. - -Reviewed-by: Ian Rogers -Signed-off-by: Li Guan -Cc: Adrian Hunter -Cc: Namhyung Kim -Cc: Palmer Dabbelt -Cc: Paul Walmsley -Signed-off-by: Arnaldo Carvalho de Melo -(cherry picked from commit 7378b6656aa46fda56f2743d5a7c1f619c2f6f9b - https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git perf-tools-next) -Signed-off-by: Han Gao ---- - tools/perf/arch/riscv/util/header.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c -index 4b839203d4a5..891984e909bd 100644 ---- a/tools/perf/arch/riscv/util/header.c -+++ b/tools/perf/arch/riscv/util/header.c -@@ -19,7 +19,7 @@ - - static char *_get_field(const char *line) - { -- char *line2, *nl; -+ const char *line2, *nl; - - line2 = strrchr(line, ' '); - if (!line2) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0300-UPSTREAM-of-Add-of_machine_get_match-helper.patch b/SPECS/linux-lts-kmhv2/0300-UPSTREAM-of-Add-of_machine_get_match-helper.patch new file mode 100644 index 0000000000..d7d13d10c7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0300-UPSTREAM-of-Add-of_machine_get_match-helper.patch @@ -0,0 +1,103 @@ +From 148e741934cb1a6081d7f61769f15d4b34bdebcc Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:05 +0100 +Subject: [RUYI PATCH] UPSTREAM: of: Add of_machine_get_match() helper + +Currently, there are two helpers to match the root compatible value +against an of_device_id array: + - of_machine_device_match() returns true if a match is found, + - of_machine_get_match_data() returns the match data if a match is + found. +However, there is no helper that returns the actual of_device_id +structure corresponding to the match, leading to code duplication in +various drivers. + +Fix this by reworking of_machine_device_match() to return the actual +match structure, and renaming it to of_machine_get_match(). +Retain the old of_machine_device_match() functionality using a cheap +static inline wrapper around the new of_machine_get_match() helper. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/14e1c03d443b1a5f210609ec3a1ebbaeab8fb3d9.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 82b6c1b542ea0530318c6f2a880d884eb4dce49f) +Signed-off-by: Han Gao +--- + drivers/of/base.c | 11 +++++------ + include/linux/of.h | 11 ++++++++--- + 2 files changed, 13 insertions(+), 9 deletions(-) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index 8d1972e18161..aca156128e3e 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -435,13 +435,12 @@ bool of_machine_compatible_match(const char *const *compats) + EXPORT_SYMBOL(of_machine_compatible_match); + + /** +- * of_machine_device_match - Test root of device tree against a of_device_id array ++ * of_machine_get_match - Test root of device tree against an of_device_id array + * @matches: NULL terminated array of of_device_id match structures to search in + * +- * Returns true if the root node has any of the given compatible values in its +- * compatible property. ++ * Returns matched entry or NULL + */ +-bool of_machine_device_match(const struct of_device_id *matches) ++const struct of_device_id *of_machine_get_match(const struct of_device_id *matches) + { + struct device_node *root; + const struct of_device_id *match = NULL; +@@ -452,9 +451,9 @@ bool of_machine_device_match(const struct of_device_id *matches) + of_node_put(root); + } + +- return match != NULL; ++ return match; + } +-EXPORT_SYMBOL(of_machine_device_match); ++EXPORT_SYMBOL(of_machine_get_match); + + /** + * of_machine_get_match_data - Tell if root of device tree has a matching of_match structure +diff --git a/include/linux/of.h b/include/linux/of.h +index 01bb3affcd49..698f42670c51 100644 +--- a/include/linux/of.h ++++ b/include/linux/of.h +@@ -407,7 +407,7 @@ extern int of_alias_get_id(const struct device_node *np, const char *stem); + extern int of_alias_get_highest_id(const char *stem); + + bool of_machine_compatible_match(const char *const *compats); +-bool of_machine_device_match(const struct of_device_id *matches); ++const struct of_device_id *of_machine_get_match(const struct of_device_id *matches); + const void *of_machine_get_match_data(const struct of_device_id *matches); + + /** +@@ -857,9 +857,9 @@ static inline bool of_machine_compatible_match(const char *const *compats) + return false; + } + +-static inline bool of_machine_device_match(const struct of_device_id *matches) ++static inline const struct of_device_id *of_machine_get_match(const struct of_device_id *matches) + { +- return false; ++ return NULL; + } + + static inline const void * +@@ -967,6 +967,11 @@ static inline int of_numa_init(void) + } + #endif + ++static inline bool of_machine_device_match(const struct of_device_id *matches) ++{ ++ return of_machine_get_match(matches) != NULL; ++} ++ + static inline struct device_node *of_find_matching_node( + struct device_node *from, + const struct of_device_id *matches) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch deleted file mode 100644 index df45fcf2dc..0000000000 --- a/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 9312f5952083473da163ade5c4b5f0cd1170caf2 Mon Sep 17 00:00:00 2001 -From: "Guo Ren (Alibaba DAMO Academy)" -Date: Tue, 21 Apr 2026 10:31:40 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE - fixup - -The early version of XuanTie C910 core has a store merge buffer -delay problem. The store merge buffer could improve the store queue -performance by merging multi-store requests, but when there are not -continued store requests, the prior single store request would be -waiting in the store queue for a long time. That would cause -significant problems for communication between multi-cores. This -problem was found on sg2042 & th1520 platforms with the qspinlock -lock torture test. - -So appending a fence w.o could immediately flush the store merge -buffer and let other cores see the write result. - -This will apply the WRITE_ONCE errata to handle the non-standard -behavior via appending a fence w.o instruction for WRITE_ONCE(). - -This problem is only observed on the sg2042 hardware platform by -running the lock_torture test program for half an hour. The problem -was not found in the user space application, because interrupt can -break the livelock. - -Acked-by: Arnd Bergmann -Reviewed-by: Alexandre Ghiti -Reviewed-by: Leonardo Bras -Reviewed-by: Inochi Amaoto -Tested-by: Han Gao -Tested-by: Yao Zi -Cc: Chen Wang -Cc: Xiaoguang Xing -Cc: Paul Walmsley -Signed-off-by: Guo Ren (Alibaba DAMO Academy) -Link: https://lore.kernel.org/r/20260421143154.1590156-1-guoren@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig.errata | 17 ++++++++++ - arch/riscv/errata/thead/errata.c | 20 ++++++++++++ - arch/riscv/include/asm/errata_list_vendors.h | 3 +- - arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ - include/asm-generic/rwonce.h | 2 ++ - 5 files changed, 75 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/include/asm/rwonce.h - -diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata -index aca9b0cfcfec..ac64123433e7 100644 ---- a/arch/riscv/Kconfig.errata -+++ b/arch/riscv/Kconfig.errata -@@ -153,4 +153,21 @@ config ERRATA_THEAD_GHOSTWRITE - - If you don't know what to do here, say "Y". - -+config ERRATA_THEAD_WRITE_ONCE -+ bool "Apply T-Head WRITE_ONCE errata" -+ depends on ERRATA_THEAD -+ default y -+ help -+ The early version of T-Head C9xx cores of sg2042 & th1520 have a store -+ merge buffer delay problem. The store merge buffer could improve the -+ store queue performance by merging multi-store requests, but when there -+ are no continued store requests, the prior single store request would be -+ waiting in the store queue for a long time. That would cause signifi- -+ cant problems for communication between multi-cores. Appending a -+ fence w.o could immediately flush the store merge buffer and let other -+ cores see the write result. -+ -+ This will apply the WRITE_ONCE errata to handle the non-standard beh- -+ avior via appending a fence w.o instruction for WRITE_ONCE(). -+ - endmenu # "CPU errata selection" -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index 0b942183f708..fbe46f2fa8fb 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, - return true; - } - -+static bool errata_probe_write_once(unsigned int stage, -+ unsigned long arch_id, unsigned long impid) -+{ -+ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) -+ return false; -+ -+ /* target-c9xx cores report arch_id and impid as 0 */ -+ if (arch_id != 0 || impid != 0) -+ return false; -+ -+ if (stage == RISCV_ALTERNATIVES_BOOT || -+ stage == RISCV_ALTERNATIVES_MODULE) -+ return true; -+ -+ return false; -+} -+ - static u32 thead_errata_probe(unsigned int stage, - unsigned long archid, unsigned long impid) - { -@@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, - - errata_probe_ghostwrite(stage, archid, impid); - -+ if (errata_probe_write_once(stage, archid, impid)) -+ cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); -+ - return cpu_req_errata; - } - -diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h -index ec7eba373437..8fd7c36307e2 100644 ---- a/arch/riscv/include/asm/errata_list_vendors.h -+++ b/arch/riscv/include/asm/errata_list_vendors.h -@@ -18,7 +18,8 @@ - #define ERRATA_THEAD_MAE 0 - #define ERRATA_THEAD_PMU 1 - #define ERRATA_THEAD_GHOSTWRITE 2 --#define ERRATA_THEAD_NUMBER 3 -+#define ERRATA_THEAD_WRITE_ONCE 3 -+#define ERRATA_THEAD_NUMBER 4 - #endif - - #ifdef CONFIG_ERRATA_MIPS -diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h -new file mode 100644 -index 000000000000..081793d4d772 ---- /dev/null -+++ b/arch/riscv/include/asm/rwonce.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __ASM_RWONCE_H -+#define __ASM_RWONCE_H -+ -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) -+ -+#define write_once_fence() \ -+do { \ -+ asm volatile(ALTERNATIVE( \ -+ "nop", \ -+ "fence w, o", \ -+ THEAD_VENDOR_ID, \ -+ ERRATA_THEAD_WRITE_ONCE, \ -+ CONFIG_ERRATA_THEAD_WRITE_ONCE) \ -+ : : : "memory"); \ -+} while (0) -+ -+#define __WRITE_ONCE(x, val) \ -+do { \ -+ *(volatile typeof(x) *)&(x) = (val); \ -+ write_once_fence(); \ -+} while (0) -+ -+#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ -+ -+#include -+ -+#endif /* __ASM_RWONCE_H */ -diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h -index 52b969c7cef9..4e2d941f15a1 100644 ---- a/include/asm-generic/rwonce.h -+++ b/include/asm-generic/rwonce.h -@@ -50,10 +50,12 @@ - __READ_ONCE(x); \ - }) - -+#ifndef __WRITE_ONCE - #define __WRITE_ONCE(x, val) \ - do { \ - *(volatile typeof(x) *)&(x) = (val); \ - } while (0) -+#endif - - #define WRITE_ONCE(x, val) \ - do { \ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0301-UPSTREAM-of-Convert-to-of_machine_get_match.patch b/SPECS/linux-lts-kmhv2/0301-UPSTREAM-of-Convert-to-of_machine_get_match.patch new file mode 100644 index 0000000000..017a7b3d0c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0301-UPSTREAM-of-Convert-to-of_machine_get_match.patch @@ -0,0 +1,42 @@ +From 17fc1a4886108c056f9d0729bbd97965fcb74e37 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:06 +0100 +Subject: [RUYI PATCH] UPSTREAM: of: Convert to of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/83ed49314b94dab7781e1d74236af72dd5c349c6.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 57814f2e0cd7960fc8bbe097c05fdf2c3f8c67e4) +Signed-off-by: Han Gao +--- + drivers/of/base.c | 9 +-------- + 1 file changed, 1 insertion(+), 8 deletions(-) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index aca156128e3e..ff142b650732 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -464,15 +464,8 @@ EXPORT_SYMBOL(of_machine_get_match); + const void *of_machine_get_match_data(const struct of_device_id *matches) + { + const struct of_device_id *match; +- struct device_node *root; +- +- root = of_find_node_by_path("/"); +- if (!root) +- return NULL; +- +- match = of_match_node(matches, root); +- of_node_put(root); + ++ match = of_machine_get_match(matches); + if (!match) + return NULL; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch deleted file mode 100644 index 747ee38919..0000000000 --- a/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 4c835b4cf54a8879850b5743cbe7d75d2b218c9c Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:56:57 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native - PCIe port services - -Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe -port service driver from probing specific devices. This provides a -per-device equivalent of the global pcie_ports=compat kernel parameter. - -Some platforms have PCIe root ports that break MSI delivery to downstream -devices when native port services (AER, PME, bwctrl, etc.) are active. -The existing pci_host_bridge native_* flags do not cover all services -(notably bwctrl), so a mechanism to skip port driver probing entirely -on a per-device basis is needed. - -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331175658.1015829-2-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pci/pcie/portdrv.c | 3 +++ - include/linux/pci.h | 2 ++ - 2 files changed, 5 insertions(+) - -diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c -index a0991da48213..315a8d9cb440 100644 ---- a/drivers/pci/pcie/portdrv.c -+++ b/drivers/pci/pcie/portdrv.c -@@ -684,6 +684,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { - static int pcie_portdrv_probe(struct pci_dev *dev, - const struct pci_device_id *id) - { -+ if (dev->dev_flags & PCI_DEV_FLAGS_NO_PORT_SERVICES) -+ return -ENODEV; -+ - int type = pci_pcie_type(dev); - int status; - -diff --git a/include/linux/pci.h b/include/linux/pci.h -index cdf67f5aa239..daf7f2363658 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -253,6 +253,8 @@ enum pci_dev_flags { - * integrated with the downstream devices and doesn't use real PCI. - */ - PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), -+ /* Do not use native PCIe port services (equivalent to pcie_ports=compat) */ -+ PCI_DEV_FLAGS_NO_PORT_SERVICES = (__force pci_dev_flags_t) (1 << 15), - }; - - enum pci_irq_reroute_variant { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0302-UPSTREAM-cpufreq-airoha-Convert-to-of_machine_get_ma.patch b/SPECS/linux-lts-kmhv2/0302-UPSTREAM-cpufreq-airoha-Convert-to-of_machine_get_ma.patch new file mode 100644 index 0000000000..dbb7d59334 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0302-UPSTREAM-cpufreq-airoha-Convert-to-of_machine_get_ma.patch @@ -0,0 +1,43 @@ +From 0fee0e576719e3ba3b9977be709f64a2e4dd6957 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:07 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: airoha: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/cc76137755d93af982bf255095adafc7d523692c.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 1838e0924e508eb30e140ad8f037863ee53be3c6) +Signed-off-by: Han Gao +--- + drivers/cpufreq/airoha-cpufreq.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/cpufreq/airoha-cpufreq.c b/drivers/cpufreq/airoha-cpufreq.c +index b6b1cdc4d11d..3e7770860d13 100644 +--- a/drivers/cpufreq/airoha-cpufreq.c ++++ b/drivers/cpufreq/airoha-cpufreq.c +@@ -115,15 +115,10 @@ MODULE_DEVICE_TABLE(of, airoha_cpufreq_match_list); + + static int __init airoha_cpufreq_init(void) + { +- struct device_node *np = of_find_node_by_path("/"); + const struct of_device_id *match; + int ret; + +- if (!np) +- return -ENODEV; +- +- match = of_match_node(airoha_cpufreq_match_list, np); +- of_node_put(np); ++ match = of_machine_get_match(airoha_cpufreq_match_list); + if (!match) + return -ENODEV; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch deleted file mode 100644 index 58cd59ae0c..0000000000 --- a/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch +++ /dev/null @@ -1,60 +0,0 @@ -From cfb56bdda1f734ba778e001d5436e62217a69a3c Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:56:58 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services - on Sophgo SG2042 - -SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to -downstream devices when native port services are enabled. Devices under -an affected root port receive zero interrupts despite successful vector -allocation, causing driver timeouts (e.g. amdgpu fence fallback timer -expired on all rings). - -Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the -port service driver from probing, restoring correct MSI delivery. - -Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 12 ++++++++++++ - include/linux/pci_ids.h | 2 ++ - 2 files changed, 14 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 481e4186a5c1..28d23f8dfd60 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -6388,3 +6388,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); - #endif -+ -+/* -+ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to -+ * downstream devices when native PCIe port services are enabled. All -+ * services including bwctrl must be disabled, equivalent to pcie_ports=compat. -+ */ -+static void quirk_sg2042_no_port_services(struct pci_dev *dev) -+{ -+ pci_info(dev, "SG2042: disabling native PCIe port services\n"); -+ dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 2b6692a5005f..7c01548a6ddb 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2633,6 +2633,8 @@ - - #define PCI_VENDOR_ID_CXL 0x1e98 - -+#define PCI_VENDOR_ID_SOPHGO 0x1f1c -+ - #define PCI_VENDOR_ID_TEHUTI 0x1fc9 - #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 - #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0303-UPSTREAM-cpufreq-qcom-nvmem-Convert-to-of_machine_ge.patch b/SPECS/linux-lts-kmhv2/0303-UPSTREAM-cpufreq-qcom-nvmem-Convert-to-of_machine_ge.patch new file mode 100644 index 0000000000..37ca1acf10 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0303-UPSTREAM-cpufreq-qcom-nvmem-Convert-to-of_machine_ge.patch @@ -0,0 +1,61 @@ +From eaadc023345ed1e272a0f77cdd4cc7f503116a3d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:08 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: qcom-nvmem: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/886a603a7a1de6c8cb14ee0783ee0bceea4d914a.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 8cd94ead5184c5bdde74dc0afc316c6f3c41fdd7) +Signed-off-by: Han Gao +--- + drivers/cpufreq/qcom-cpufreq-nvmem.c | 16 ++-------------- + 1 file changed, 2 insertions(+), 14 deletions(-) + +diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c +index d5af74bf71c6..be06a4762e35 100644 +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -290,17 +290,9 @@ static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + ret = qcom_smem_get_soc_id(&msm_id); + if (ret == -ENODEV) { + const struct of_device_id *match; +- struct device_node *root; +- +- root = of_find_node_by_path("/"); +- if (!root) { +- ret = -ENODEV; +- goto exit; +- } + + /* Fallback to compatible match with no SMEM initialized */ +- match = of_match_node(qcom_cpufreq_ipq806x_match_list, root); +- of_node_put(root); ++ match = of_machine_get_match(qcom_cpufreq_ipq806x_match_list); + if (!match) { + ret = -ENODEV; + goto exit; +@@ -646,14 +638,10 @@ MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); + */ + static int __init qcom_cpufreq_init(void) + { +- struct device_node *np __free(device_node) = of_find_node_by_path("/"); + const struct of_device_id *match; + int ret; + +- if (!np) +- return -ENODEV; +- +- match = of_match_node(qcom_cpufreq_match_list, np); ++ match = of_machine_get_match(qcom_cpufreq_match_list); + if (!match) + return -ENODEV; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch deleted file mode 100644 index 92052a71a6..0000000000 --- a/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch +++ /dev/null @@ -1,83 +0,0 @@ -From ef760574ea2b96b482691e4b76ea4544d2b04231 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= -Date: Thu, 18 Sep 2025 13:58:56 -0700 -Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to - allow GPU BAR resize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Resizing BAR to a larger size has to release upstream bridge windows in -order make the bridge windows larger as well (and to potential relocate -them into a larger free block within iomem space). Some GPUs have an -integrated PCI switch that has BAR0. The resource allocation assigns -space for that BAR0 as it does for any resource. - -An extra resource on a bridge will pin its upstream bridge window in -place which prevents BAR resize for anything beneath that bridge. - -Nothing in the pcieport driver provided by PCI core, which typically is -the driver bound to these bridges, requires that BAR0. Because of that, -releasing the extra BAR does not seem to have notable downsides but -comes with a clear upside. - -Therefore, release BAR0 of such switches using a quirk and clear its -flags to prevent any new invocation of the resource assignment -algorithm from assigning the resource again. - -Due to other siblings within the PCI hierarchy of all the devices -integrated into the GPU, some other devices may still have to be -manually removed before the resize is free of any bridge window pins. -Such siblings can be released through sysfs to unpin windows while -leaving access to GPU's sysfs entries required for initiating the -resize operation, whereas removing the topmost bridge this quirk -targets would result in removing the GPU device as well so no manual -workaround for this problem exists. - -Reported-by: Lucas De Marchi -Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ -Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ -Signed-off-by: Ilpo Järvinen -Cc: stable@vger.kernel.org # v6.12+ -Signed-off-by: Lucas De Marchi -Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com -Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 28d23f8dfd60..f0cd6c2a7827 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -6400,3 +6400,26 @@ static void quirk_sg2042_no_port_services(struct pci_dev *dev) - dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; - } - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); -+ -+/* -+ * PCI switches integrated into Intel Arc GPUs have BAR0 that prevents -+ * resizing the BARs of the GPU device due to that bridge BAR0 pinning the -+ * bridge window it's under in place. Nothing in pcieport requires that -+ * BAR0. -+ * -+ * Release and disable BAR0 permanently by clearing its flags to prevent -+ * anything from assigning it again. -+ */ -+static void pci_release_bar0(struct pci_dev *pdev) -+{ -+ struct resource *res = pci_resource_n(pdev, 0); -+ -+ if (!res->parent) -+ return; -+ -+ pci_release_resource(pdev, 0); -+ res->flags = 0; -+} -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa0, pci_release_bar0); -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa1, pci_release_bar0); -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0xe2ff, pci_release_bar0); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0304-UPSTREAM-cpufreq-ti-cpufreq-Convert-to-of_machine_ge.patch b/SPECS/linux-lts-kmhv2/0304-UPSTREAM-cpufreq-ti-cpufreq-Convert-to-of_machine_ge.patch new file mode 100644 index 0000000000..9c60d5bb9c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0304-UPSTREAM-cpufreq-ti-cpufreq-Convert-to-of_machine_ge.patch @@ -0,0 +1,52 @@ +From 9cd245b383317da14e142085b8c2bc2e39f8874e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:09 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: ti-cpufreq: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/bba0631aea78b6db7d453a9f9e98ea16b7e2c269.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 951318c4651a646f4835ae33abe7c4cb232e7c6e) +Signed-off-by: Han Gao +--- + drivers/cpufreq/ti-cpufreq.c | 12 +----------- + 1 file changed, 1 insertion(+), 11 deletions(-) + +diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c +index 6ee76f5fe9c5..0c27c89b7853 100644 +--- a/drivers/cpufreq/ti-cpufreq.c ++++ b/drivers/cpufreq/ti-cpufreq.c +@@ -470,16 +470,6 @@ static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = { + {}, + }; + +-static const struct of_device_id *ti_cpufreq_match_node(void) +-{ +- struct device_node *np __free(device_node) = of_find_node_by_path("/"); +- const struct of_device_id *match; +- +- match = of_match_node(ti_cpufreq_of_match, np); +- +- return match; +-} +- + static int ti_cpufreq_probe(struct platform_device *pdev) + { + u32 version[VERSION_COUNT]; +@@ -564,7 +554,7 @@ static int __init ti_cpufreq_init(void) + const struct of_device_id *match; + + /* Check to ensure we are on a compatible platform */ +- match = ti_cpufreq_match_node(); ++ match = of_machine_get_match(ti_cpufreq_of_match); + if (match) + platform_device_register_data(NULL, "ti-cpufreq", -1, match, + sizeof(*match)); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch deleted file mode 100644 index 826058c0bf..0000000000 --- a/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 1f52ff4a8952f2dcd39f984b094e0d3ba4227bcd Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sat, 29 Jun 2024 13:22:46 +0800 -Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA - coherency status in ttm_device - -Currently TTM utilizes cached memory regardless of whether the device -have full DMA coherency (can snoop CPU cache). - -Save the device's DMA coherency status in struct ttm_device, to allow -further support of devices w/o snooping capability (the capability -missing on at least one part of the transmission between the CPU and the -device). - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20240629052247.2653363-2-uwu@icenowy.me -[ Han Gao: add conditional compilation for dma_coherent ] -Signed-off-by: Han Gao ---- - drivers/gpu/drm/ttm/ttm_device.c | 6 ++++++ - include/drm/ttm/ttm_device.h | 9 +++++++++ - 2 files changed, 15 insertions(+) - -diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c -index c3e2fcbdd2cc..1758d94b3d44 100644 ---- a/drivers/gpu/drm/ttm/ttm_device.c -+++ b/drivers/gpu/drm/ttm/ttm_device.c -@@ -246,6 +246,12 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func - list_add_tail(&bdev->device_list, &glob->device_list); - mutex_unlock(&ttm_global_mutex); - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ bdev->dma_coherent = dev->dma_coherent; -+#endif -+ - return 0; - } - EXPORT_SYMBOL(ttm_device_init); -diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h -index 592b5f802859..c2e61312a43a 100644 ---- a/include/drm/ttm/ttm_device.h -+++ b/include/drm/ttm/ttm_device.h -@@ -225,6 +225,15 @@ struct ttm_device { - */ - const struct ttm_device_funcs *funcs; - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /** -+ * @dma_coherent: if the device backed is dma-coherent. -+ */ -+ bool dma_coherent; -+#endif -+ - /** - * @sysman: Resource manager for the system domain. - * Access via ttm_manager_type. --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0305-UPSTREAM-soc-qcom-pd-mapper-Convert-to-of_machine_ge.patch b/SPECS/linux-lts-kmhv2/0305-UPSTREAM-soc-qcom-pd-mapper-Convert-to-of_machine_ge.patch new file mode 100644 index 0000000000..7550a0c61e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0305-UPSTREAM-soc-qcom-pd-mapper-Convert-to-of_machine_ge.patch @@ -0,0 +1,44 @@ +From e2e5cd5b291fd8acdb66195ec90de58a96638242 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:10 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: qcom: pd-mapper: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Konrad Dybcio +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/0d23a449e62ac85f04ff07bc2758efbaa709c9d1.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 3ee3d8a44976ac7e39584637ee4c840d70ab2ad1) +Signed-off-by: Han Gao +--- + drivers/soc/qcom/qcom_pd_mapper.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c +index 6384f271953d..56d2377fb8b1 100644 +--- a/drivers/soc/qcom/qcom_pd_mapper.c ++++ b/drivers/soc/qcom/qcom_pd_mapper.c +@@ -605,15 +605,9 @@ static struct qcom_pdm_data *qcom_pdm_start(void) + const struct qcom_pdm_domain_data * const *domains; + const struct of_device_id *match; + struct qcom_pdm_data *data; +- struct device_node *root; + int ret, i; + +- root = of_find_node_by_path("/"); +- if (!root) +- return ERR_PTR(-ENODEV); +- +- match = of_match_node(qcom_pdm_domains, root); +- of_node_put(root); ++ match = of_machine_get_match(qcom_pdm_domains); + if (!match) { + pr_notice("PDM: no support for the platform, userspace daemon might be required.\n"); + return ERR_PTR(-ENODEV); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch deleted file mode 100644 index bb46fa248c..0000000000 --- a/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 555ac6aeaf274981371546928300e152ff7ac153 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sat, 29 Jun 2024 13:22:47 +0800 -Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to - write_combined when snooping not available - -As we can now acquire the presence of the full DMA coherency (snooping -capability) from ttm_device, we can now map the CPU side memory as -write-combined when cached is requested and snooping is not avilable. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20240629052247.2653363-3-uwu@icenowy.me -[ Han Gao: add conditional compilation for dma coherent operations ] -[ Icenowy: omit single page ttm_cached optimization when non-coherent and handle linear io iter ] -Signed-off-by: Han Gao ---- - drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +++++++++++++ - drivers/gpu/drm/ttm/ttm_resource.c | 13 +++++++++++-- - drivers/gpu/drm/ttm/ttm_tt.c | 8 ++++++++ - include/drm/ttm/ttm_caching.h | 3 ++- - 4 files changed, 34 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c -index acbbca9d5c92..2a8777d1f2b8 100644 ---- a/drivers/gpu/drm/ttm/ttm_bo_util.c -+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c -@@ -307,6 +307,14 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res, - caching = res->bus.caching; - } - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bo->bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - return ttm_prot_from_caching(caching, tmp); - } - EXPORT_SYMBOL(ttm_io_prot); -@@ -360,6 +368,11 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, - return ret; - - if (num_pages == 1 && ttm->caching == ttm_cached && -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ bo->bdev->dma_coherent && -+#endif - !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { - /* - * We're mapping a single page, and the desired -diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c -index 2a05fbd07546..4f18a9a98f11 100644 ---- a/drivers/gpu/drm/ttm/ttm_resource.c -+++ b/drivers/gpu/drm/ttm/ttm_resource.c -@@ -830,8 +830,17 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, - struct ttm_device *bdev, - struct ttm_resource *mem) - { -+ enum ttm_caching caching = mem->bus.caching; - int ret; - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - ret = ttm_mem_io_reserve(bdev, mem); - if (ret) - goto out_err; -@@ -846,11 +855,11 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, - } else { - iter_io->needs_unmap = true; - memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); -- if (mem->bus.caching == ttm_write_combined) -+ if (caching == ttm_write_combined) - iosys_map_set_vaddr_iomem(&iter_io->dmap, - ioremap_wc(mem->bus.offset, - mem->size)); -- else if (mem->bus.caching == ttm_cached) -+ else if (caching == ttm_cached) - iosys_map_set_vaddr(&iter_io->dmap, - memremap(mem->bus.offset, mem->size, - MEMREMAP_WB | -diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c -index 506e257dfba8..8338deb3330f 100644 ---- a/drivers/gpu/drm/ttm/ttm_tt.c -+++ b/drivers/gpu/drm/ttm/ttm_tt.c -@@ -154,6 +154,14 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, - enum ttm_caching caching, - unsigned long extra_pages) - { -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bo->bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; - ttm->page_flags = page_flags; - ttm->dma_address = NULL; -diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h -index a18f43e93aba..f92d7911f50e 100644 ---- a/include/drm/ttm/ttm_caching.h -+++ b/include/drm/ttm/ttm_caching.h -@@ -47,7 +47,8 @@ enum ttm_caching { - - /** - * @ttm_cached: Fully cached like normal system memory, requires that -- * devices snoop the CPU cache on accesses. -+ * devices snoop the CPU cache on accesses. Downgraded to -+ * ttm_write_combined when the snooping capaiblity is missing. - */ - ttm_cached - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0306-UPSTREAM-init-deduplicate-cc-can-link.sh-invocations.patch b/SPECS/linux-lts-kmhv2/0306-UPSTREAM-init-deduplicate-cc-can-link.sh-invocations.patch new file mode 100644 index 0000000000..d9ac5cc345 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0306-UPSTREAM-init-deduplicate-cc-can-link.sh-invocations.patch @@ -0,0 +1,57 @@ +From 47f12485bbbdd57fa80c7323c7c2e70e379985f1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Fri, 14 Nov 2025 14:43:57 +0100 +Subject: [RUYI PATCH] UPSTREAM: init: deduplicate cc-can-link.sh invocations +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The command to invoke scripts/cc-can-link.sh is very long and new usages +are about to be added. + +Add a helper variable to make the code easier to read and maintain. + +Signed-off-by: Thomas Weißschuh +Reviewed-by: Nicolas Schier +Reviewed-by: Nathan Chancellor +Link: https://patch.msgid.link/20251114-kbuild-userprogs-bits-v3-2-4dee0d74d439@linutronix.de +Signed-off-by: Nicolas Schier +(cherry picked from commit 80623f2c83d7de5c289d4240b8f4cef4103c51fc) +Signed-off-by: Han Gao +--- + init/Kconfig | 4 ++-- + scripts/Kconfig.include | 3 +++ + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/init/Kconfig b/init/Kconfig +index cab3ad28ca49..7b722e714d5c 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -84,8 +84,8 @@ config RUSTC_LLVM_VERSION + + config CC_CAN_LINK + bool +- default $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(m64-flag)) if 64BIT +- default $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(m32-flag)) ++ default $(cc_can_link_user,$(m64-flag)) if 64BIT ++ default $(cc_can_link_user,$(m32-flag)) + + # Fixed in GCC 14, 13.3, 12.4 and 11.5 + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113921 +diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include +index 33193ca6e803..d42042b6c9e2 100644 +--- a/scripts/Kconfig.include ++++ b/scripts/Kconfig.include +@@ -65,6 +65,9 @@ cc-option-bit = $(if-success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null,$ + m32-flag := $(cc-option-bit,-m32) + m64-flag := $(cc-option-bit,-m64) + ++# Test whether the compiler can link userspace applications ++cc_can_link_user = $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(1)) ++ + rustc-version := $(shell,$(srctree)/scripts/rustc-version.sh $(RUSTC)) + rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch deleted file mode 100644 index 58e516d738..0000000000 --- a/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 5911aa5fe93310aba068d9a4361bc5827ce35b62 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:16 +0000 -Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP - table for TH1520 - -Add operating point table for CPU cores, and wire up clocks for CPU -nodes. - -This patch isn't intended for upstreaming but only for testing purpose, -since the PMIC driver for scaling CPU voltage isn't ready yet. Only -operating points whose voltage is satisified by Lichee Module 4A's PMIC -default, i.e. <= 1.5GHz, are enabled. - -Signed-off-by: Yao Zi -Link: https://lore.kernel.org/r/20251120131416.26236-8-ziyao@disroot.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 35 +++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 5e91dc1d2b9b..2910249e1f0c 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -38,6 +38,8 @@ c910_0: cpu@0 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -65,6 +67,8 @@ c910_1: cpu@1 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -92,6 +96,8 @@ c910_2: cpu@2 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -119,6 +125,8 @@ c910_3: cpu@3 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -137,6 +145,33 @@ l2_cache: l2-cache { - }; - }; - -+ cpu_opp: opp-table-cpu { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <600000>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <700000>; -+ }; -+ -+ opp-1500000000 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <800000>; -+ }; -+ -+/* -+ opp-1848000000 { -+ opp-hz = /bits/ 64 <1848000000>; -+ opp-microvolt = <1000000>; -+ }; -+ */ -+ }; -+ - pmu { - compatible = "riscv,pmu"; - riscv,event-to-mhpmcounters = --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0307-UPSTREAM-kbuild-allow-architectures-to-override-CC_C.patch b/SPECS/linux-lts-kmhv2/0307-UPSTREAM-kbuild-allow-architectures-to-override-CC_C.patch new file mode 100644 index 0000000000..8fe2478493 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0307-UPSTREAM-kbuild-allow-architectures-to-override-CC_C.patch @@ -0,0 +1,76 @@ +From 5145724870f7f6189dd6daa9500771e4c3184a29 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Fri, 14 Nov 2025 14:43:58 +0100 +Subject: [RUYI PATCH] UPSTREAM: kbuild: allow architectures to override + CC_CAN_LINK +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The generic test for CC_CAN_LINK assumes that all architectures use -m32 +and -m64 to switch between 32-bit and 64-bit compilation. This is overly +simplistic. Architectures may use other flags (-mabi, -m31, etc.) or may +also require byte order handling (-mlittle-endian, -EL). Expressing all +of the different possibilities will be very complicated and brittle. +Instead allow architectures to supply their own logic which will be +easy to understand and evolve. + +Both the boolean ARCH_HAS_CC_CAN_LINK and the string ARCH_USERFLAGS need +to be implemented as kconfig does not allow the reuse of string options. + +Signed-off-by: Thomas Weißschuh +Reviewed-by: Nicolas Schier +Reviewed-by: Nathan Chancellor +Link: https://patch.msgid.link/20251114-kbuild-userprogs-bits-v3-3-4dee0d74d439@linutronix.de +Signed-off-by: Nicolas Schier +(cherry picked from commit deab487e0f9b39ae4603e22d7d00908ebfc9753c) +Signed-off-by: Han Gao +--- + Makefile | 13 +++++++++++-- + init/Kconfig | 4 ++++ + 2 files changed, 15 insertions(+), 2 deletions(-) + +diff --git a/Makefile b/Makefile +index 7ee3beedceca..8ae52cf42da5 100644 +--- a/Makefile ++++ b/Makefile +@@ -1156,8 +1156,17 @@ ifneq ($(CONFIG_ARCH_VMLINUX_NEEDS_RELOCS),) + LDFLAGS_vmlinux += --emit-relocs --discard-none + endif + +-# Align the bit size of userspace programs with the kernel +-USERFLAGS_FROM_KERNEL := -m32 -m64 --target=% ++# Align the architecture of userspace programs with the kernel ++USERFLAGS_FROM_KERNEL := --target=% ++ ++ifdef CONFIG_ARCH_USERFLAGS ++KBUILD_USERCFLAGS += $(CONFIG_ARCH_USERFLAGS) ++KBUILD_USERLDFLAGS += $(CONFIG_ARCH_USERFLAGS) ++else ++# If not overridden also inherit the bit size ++USERFLAGS_FROM_KERNEL += -m32 -m64 ++endif ++ + KBUILD_USERCFLAGS += $(filter $(USERFLAGS_FROM_KERNEL), $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS)) + KBUILD_USERLDFLAGS += $(filter $(USERFLAGS_FROM_KERNEL), $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS)) + +diff --git a/init/Kconfig b/init/Kconfig +index 7b722e714d5c..4a2ae3cfbf26 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -82,8 +82,12 @@ config RUSTC_LLVM_VERSION + int + default $(rustc-llvm-version) + ++config ARCH_HAS_CC_CAN_LINK ++ bool ++ + config CC_CAN_LINK + bool ++ default ARCH_CC_CAN_LINK if ARCH_HAS_CC_CAN_LINK + default $(cc_can_link_user,$(m64-flag)) if 64BIT + default $(cc_can_link_user,$(m32-flag)) + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch deleted file mode 100644 index 207ec24976..0000000000 --- a/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 1331a7f7caf771503583f18f7576c01b13e887ec Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:54 +0100 -Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate - Makefile - -A subsequent commit will add a new function `bindgen-option` to -`scripts/Kconfig.include`. The bindgen backend requires the `--target` -option for cross compiling, but variable `BINDGEN_TARGET` in -`rust/Makefile` cannot be exported to `scripts/Kconfig.include`. - -Therefore, move this variable to a separate new `Makefile.rust` file and -include it from `scripts/Makefile` to make the exported variable -available for use in Kconfig. Place the include in the `need-compiler` -branch to avoid including it in irrelevant make targets. - -Since the new file name is `Makefile.rust`, it matches an existing -MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS -file is needed. - -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-1-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - Makefile | 3 ++- - rust/Makefile | 8 -------- - scripts/Makefile.rust | 9 +++++++++ - 3 files changed, 11 insertions(+), 9 deletions(-) - create mode 100644 scripts/Makefile.rust - -diff --git a/Makefile b/Makefile -index 5087bd6183dd..e5901ed88254 100644 ---- a/Makefile -+++ b/Makefile -@@ -724,9 +724,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) - include $(srctree)/scripts/Makefile.clang - endif - -+ifdef need-compiler -+include $(srctree)/scripts/Makefile.rust - # Include this also for config targets because some architectures need - # cc-cross-prefix to determine CROSS_COMPILE. --ifdef need-compiler - include $(srctree)/scripts/Makefile.compiler - endif - -diff --git a/rust/Makefile b/rust/Makefile -index d4618f646b05..c311d16e7e74 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -300,14 +300,6 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fzero-init-padding-bits=% -mno-fdpic \ - --param=% --param asan-% -fno-isolate-erroneous-paths-dereference - --# Derived from `scripts/Makefile.clang`. --BINDGEN_TARGET_x86 := x86_64-linux-gnu --BINDGEN_TARGET_arm64 := aarch64-linux-gnu --BINDGEN_TARGET_arm := arm-linux-gnueabi --BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf --BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) --BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) -- - # All warnings are inhibited since GCC builds are very experimental, - # many GCC warnings are not supported by Clang, they may only appear in - # some configurations, with new GCC versions, etc. -diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust -new file mode 100644 -index 000000000000..5c12b4b8c8b6 ---- /dev/null -+++ b/scripts/Makefile.rust -@@ -0,0 +1,9 @@ -+# Derived from `scripts/Makefile.clang`. -+BINDGEN_TARGET_x86 := x86_64-linux-gnu -+BINDGEN_TARGET_arm64 := aarch64-linux-gnu -+BINDGEN_TARGET_arm := arm-linux-gnueabi -+BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf -+BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) -+BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) -+ -+export BINDGEN_TARGET --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0308-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux-lts-kmhv2/0308-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch new file mode 100644 index 0000000000..6e1d1080ec --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0308-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch @@ -0,0 +1,44 @@ +From cf338d06de5e4ef58b84b81bbc067c2c24163a24 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add reset + support + +The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus +which shared by all controllers, while another one connect to individual +controller separately. + +Signed-off-by: Yixun Lan +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Ulf Hansson +(cherry picked from commit 4231325cfb87f712fcbe1fcbeea4186d18c78513) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 383841369fb2..9a055d963a7f 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -34,6 +34,16 @@ properties: + - const: core + - const: io + ++ resets: ++ items: ++ - description: axi reset, connect to AXI bus, shared by all controllers ++ - description: sdh reset, connect to individual controller separately ++ ++ reset-names: ++ items: ++ - const: axi ++ - const: sdh ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch deleted file mode 100644 index 99ff4e9cc0..0000000000 --- a/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 22c8be25d1ed7a76f36d5f1d30f0c61faa68b951 Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:55 +0100 -Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET - is undefined - -Generate a friendly fatal error if the target triplet is undefined for -bindgen, rather than having the compiler generate obscure error messages -during the build stage. - -`BINDGEN_TARGET` is actually defined in `scripts/Makefile.rust`, but the -file is included regardless of whether Rust is enabled, so perform this -check in `rust/Makefile` to avoid breaking targets that do not yet -support Rust builds. - -This piece of code is copied from `scripts/Makefile.clang`. - -Before this commit, error messages might look like: - -error: unknown argument: '-mno-riscv-attribute' -error: unsupported argument 'medany' to option '-mcmodel=' for target -'unknown' -error: unsupported option '-march=' for target '' -error: unsupported option '-mno-save-restore' for target '' -error: unknown target triple 'unknown' -panicked at bindgen/ir/context.rs:562:15: -libclang error; possible causes include: -- Invalid flag syntax -- Unrecognized flags -- Invalid flag arguments -- File I/O errors -- Host vs. target architecture mismatch - -Acked-by: Miguel Ojeda -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-2-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - rust/Makefile | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/rust/Makefile b/rust/Makefile -index c311d16e7e74..6d2d542a55e8 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -300,6 +300,12 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fzero-init-padding-bits=% -mno-fdpic \ - --param=% --param asan-% -fno-isolate-erroneous-paths-dereference - -+# Because scripts/Makefile.rust is included regardless of whether Rust is enabled, -+# we perform this check here to avoid breaking targets that do not yet support Rust builds. -+ifeq ($(BINDGEN_TARGET),) -+$(error add '--target=' option to scripts/Makefile.rust) -+endif -+ - # All warnings are inhibited since GCC builds are very experimental, - # many GCC warnings are not supported by Clang, they may only appear in - # some configurations, with new GCC versions, etc. --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0309-UPSTREAM-drm-imagination-Count-paired-job-fence-as-d.patch b/SPECS/linux-lts-kmhv2/0309-UPSTREAM-drm-imagination-Count-paired-job-fence-as-d.patch new file mode 100644 index 0000000000..077a474e9a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0309-UPSTREAM-drm-imagination-Count-paired-job-fence-as-d.patch @@ -0,0 +1,137 @@ +From b3bf69fd4a4d2738496929312af9b0b7f59e8ca3 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:36 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Count paired job fence as + dependency in prepare_job() + +The DRM scheduler's prepare_job() callback counts the remaining +non-signaled native dependencies for a job, preventing job submission +until those (plus job data and fence update) can fit in the job queue's +CCCB. + +This means checking which dependencies can be waited upon in the +firmware, i.e. whether they are backed by a UFO object, i.e. whether +their drm_sched_fence::parent has been assigned to a +pvr_queue_fence::base fence. That happens when the job owning the fence +is submitted to the firmware. + +Paired geometry and fragment jobs are submitted at the same time, which +means the dependency between them can't be checked this way before +submission. + +Update job_count_remaining_native_deps() to take into account the +dependency between paired jobs. + +This fixes cases where prepare_job() underestimated the space left in +an almost full fragment CCCB, wrongly unblocking run_job(), which then +returned early without writing the full sequence of commands to the +CCCB. + +The above lead to kernel warnings such as the following and potentially +job timeouts (depending on waiters on the missing commands): + + [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 + [ 375.703160] Modules linked in: + [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT + [ 375.703613] Tainted: [W]=WARN + [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) + [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] + [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] + [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] + [ 375.703921] sp : ffff800084a97650 + [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 + [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 + [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 + [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 + [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 + [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 + [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 + [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 + [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 + [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f + [ 375.704317] Call trace: + [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) + [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] + [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] + [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] + [ 375.704623] process_one_work+0x520/0x1288 + [ 375.704658] worker_thread+0x3f0/0xb3c + [ 375.704680] kthread+0x334/0x3d8 + [ 375.704706] ret_from_fork+0x10/0x20 + [ 375.704736] ---[ end trace 0000000000000000 ]--- + +Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") +Cc: stable@vger.kernel.org +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 9cd74f935306cd857f46686975c43383e1d95f94) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 27 +++++++++++++++++++++---- + 1 file changed, 23 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index fc415dd0d7a7..8829c65747b6 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -179,7 +179,7 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { + + /** + * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is +- * backed by a UFO. ++ * already backed by a UFO. + * @f: The dma_fence to turn into a pvr_queue_fence. + * + * Return: +@@ -356,6 +356,15 @@ static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) + pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); + } + ++static bool ++is_paired_job_fence(struct dma_fence *fence, struct pvr_job *job) ++{ ++ /* This assumes "fence" is one of "job"'s drm_sched_job::dependencies */ ++ return job->type == DRM_PVR_JOB_TYPE_FRAGMENT && ++ job->paired_job && ++ &job->paired_job->base.s_fence->scheduled == fence; ++} ++ + /** + * job_count_remaining_native_deps() - Count the number of non-signaled native dependencies. + * @job: Job to operate on. +@@ -371,6 +380,17 @@ static unsigned long job_count_remaining_native_deps(struct pvr_job *job) + xa_for_each(&job->base.dependencies, index, fence) { + struct pvr_queue_fence *jfence; + ++ if (is_paired_job_fence(fence, job)) { ++ /* ++ * A fence between paired jobs won't resolve to a pvr_queue_fence (i.e. ++ * be backed by a UFO) until the jobs have been submitted, together. ++ * The submitting code will insert a partial render fence command for this. ++ */ ++ WARN_ON(dma_fence_is_signaled(fence)); ++ remaining_count++; ++ continue; ++ } ++ + jfence = to_pvr_queue_job_fence(fence); + if (!jfence) + continue; +@@ -630,9 +650,8 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + +- /* Skip the partial render fence, we will place it at the end. */ +- if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job && +- &job->paired_job->base.s_fence->scheduled == fence) ++ /* This fence will be placed last, as partial render fence. */ ++ if (is_paired_job_fence(fence, job)) + continue; + + if (dma_fence_is_signaled(&jfence->base)) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch deleted file mode 100644 index f14c7c2ccd..0000000000 --- a/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0bae0d06c2aca802becde0cd7d5cb153390dcd4d Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:56 +0100 -Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for - support of bindgen options - -Add a new `bindgen-backend-option` Kconfig function to test whether the -bindgen backend supports a given flag. - -A subsequent commit will use this function to test for RISC-V extension -flags. - -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-3-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - scripts/Kconfig.include | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include -index 33193ca6e803..c7360e1e59ab 100644 ---- a/scripts/Kconfig.include -+++ b/scripts/Kconfig.include -@@ -75,3 +75,8 @@ rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) - # If you are testing for unstable features, consider testing RUSTC_VERSION - # instead, as features may have different completeness while available. - rustc-option = $(success,trap "rm -rf .tmp_$$" EXIT; mkdir .tmp_$$; $(RUSTC) $(1) --crate-type=rlib /dev/null --out-dir=.tmp_$$ -o .tmp_$$/tmp.rlib) -+ -+# $(bindgen-backend-option,) -+# Return y if bindgen backend supports , n otherwise -+# For now, the backend refers only to libclang, so more specifically, this function tests whether the given flag is recognized by the libclang used by bindgen. -+bindgen-backend-option = $(success,$(BINDGEN) /dev/null -- -x c --target=$(BINDGEN_TARGET) $(1)) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0310-UPSTREAM-drm-imagination-Fit-paired-fragment-job-in-.patch b/SPECS/linux-lts-kmhv2/0310-UPSTREAM-drm-imagination-Fit-paired-fragment-job-in-.patch new file mode 100644 index 0000000000..25983da88f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0310-UPSTREAM-drm-imagination-Fit-paired-fragment-job-in-.patch @@ -0,0 +1,160 @@ +From 6dcaba0f69bca88b0f2f3aaebc2164b16f142bcc Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:37 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Fit paired fragment job in + the correct CCCB + +For geometry jobs with a paired fragment job, at the moment, the +DRM scheduler's prepare_job() callback: + +- checks for internal (driver) dependencies for the geometry job; +- calls into pvr_queue_get_paired_frag_job_dep() to check for external + dependencies for the fragment job (the two jobs are submitted together + but the common scheduler code doesn't know about it, so this needs to + be done at this point in time); +- calls into the prepare_job() callback again, but for the fragment job, + to check its internal dependencies as well, passing the fragment job's + drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. + +The problem with the last step is that pvr_queue_prepare_job() doesn't +always take the mismatched fragment job and geometry queue into account, +in particular when checking whether there is space for the fragment +command to be submitted, so the code ends up checking for space in the +geometry (i.e. wrong) CCCB. +The rest of the nested prepare_job() callback happens to work fine at +the moment as the other internal dependencies are not relevant for a +paired fragment job. + +Move the initialisation of a paired fragment job's done fence and CCCB +fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct +queue from the fragment job itself. + +This fixes cases where prepare_job() wrongly assumed that there was +enough space for a paired fragment job in its own CCCB, unblocking +run_job(), which then returned early without writing the full sequence +of commands to the CCCB. + +The above lead to kernel warnings such as the following and potentially +job timeouts (depending on waiters on the missing commands): + + [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 + [ 552.421230] Modules linked in: + [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT + [ 552.421625] Tainted: [W]=WARN + [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) + [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] + [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] + [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] + [ 552.421923] sp : ffff800084c47650 + [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 + [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 + [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 + [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 + [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 + [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 + [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 + [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 + [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 + [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f + [ 552.422316] Call trace: + [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) + [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] + [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] + [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] + [ 552.422623] process_one_work+0x520/0x1288 + [ 552.422657] worker_thread+0x3f0/0xb3c + [ 552.422679] kthread+0x334/0x3d8 + [ 552.422706] ret_from_fork+0x10/0x20 + +Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") +Cc: stable@vger.kernel.org +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 4baf9e70cb756d78dd56419f8baee2978a72d0c3) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 32 +++++++++++-------------- + 1 file changed, 14 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 8829c65747b6..7d0d09026b82 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -488,10 +488,11 @@ pvr_queue_get_job_kccb_fence(struct pvr_queue *queue, struct pvr_job *job) + } + + static struct dma_fence * +-pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) ++pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) + { + struct pvr_job *frag_job = job->type == DRM_PVR_JOB_TYPE_GEOMETRY ? + job->paired_job : NULL; ++ struct pvr_queue *frag_queue = frag_job ? frag_job->ctx->queues.fragment : NULL; + struct dma_fence *f; + unsigned long index; + +@@ -510,7 +511,10 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) + return dma_fence_get(f); + } + +- return frag_job->base.sched->ops->prepare_job(&frag_job->base, &queue->entity); ++ /* Initialize the paired fragment job's done_fence, so we can signal it. */ ++ pvr_queue_job_fence_init(frag_job->done_fence, frag_queue); ++ ++ return pvr_queue_get_job_cccb_fence(frag_queue, frag_job); + } + + /** +@@ -529,11 +533,6 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + struct pvr_queue *queue = container_of(s_entity, struct pvr_queue, entity); + struct dma_fence *internal_dep = NULL; + +- /* +- * Initialize the done_fence, so we can signal it. This must be done +- * here because otherwise by the time of run_job() the job will end up +- * in the pending list without a valid fence. +- */ + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { + /* + * This will be called on a paired fragment job after being +@@ -543,18 +542,15 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + */ + if (job->paired_job->has_pm_ref) + return NULL; +- +- /* +- * In this case we need to use the job's own ctx to initialise +- * the done_fence. The other steps are done in the ctx of the +- * paired geometry job. +- */ +- pvr_queue_job_fence_init(job->done_fence, +- job->ctx->queues.fragment); +- } else { +- pvr_queue_job_fence_init(job->done_fence, queue); + } + ++ /* ++ * Initialize the done_fence, so we can signal it. This must be done ++ * here because otherwise by the time of run_job() the job will end up ++ * in the pending list without a valid fence. ++ */ ++ pvr_queue_job_fence_init(job->done_fence, queue); ++ + /* CCCB fence is used to make sure we have enough space in the CCCB to + * submit our commands. + */ +@@ -575,7 +571,7 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + + /* The paired job fence should come last, when everything else is ready. */ + if (!internal_dep) +- internal_dep = pvr_queue_get_paired_frag_job_dep(queue, job); ++ internal_dep = pvr_queue_get_paired_frag_job_dep(job); + + return internal_dep; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch deleted file mode 100644 index 22dad26c59..0000000000 --- a/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch +++ /dev/null @@ -1,183 +0,0 @@ -From bdb364df3673e4e729a0e33788d91c7ace67e22e Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:57 +0100 -Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, - re-enable gcc + rust builds - -Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC -+ Rust builds for RISC-V due to differences in extension handling -compared to LLVM. This commit enables GCC + Rust builds again. - -Add `bindgen-option` conditions for the availability of libclang to the -RISC-V extension Kconfig symbols that depend on the `cc-option` -function. - -For Zicsr/Zifencei special handling, since LLVM/Clang always enables -these two extensions, either don't pass them to `-march`, or pass them -explicitly and Rust bindgen libclang must recognize them. - -Clang does not support `-mno-riscv-attribute` flag, filter it out to -resolve error: unknown argument: '-mno-riscv-attribute'. - -Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen -libclang for RISC-V to resolve error: unsupported argument 'medany' to -option '-mcmodel=' for target 'unknown'. - -Update the documentation, GCC + Rust builds for RISC-V are now -maintained. - -Acked-by: Miguel Ojeda -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - Documentation/rust/arch-support.rst | 2 +- - arch/riscv/Kconfig | 35 ++++++++++++++++++++++++++++- - rust/Makefile | 3 ++- - scripts/Makefile.rust | 1 + - 4 files changed, 38 insertions(+), 3 deletions(-) - -diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst -index 6e6a515d0899..5282e0e174e8 100644 ---- a/Documentation/rust/arch-support.rst -+++ b/Documentation/rust/arch-support.rst -@@ -18,7 +18,7 @@ Architecture Level of support Constraints - ``arm`` Maintained ARMv7 Little Endian only. - ``arm64`` Maintained Little Endian only. - ``loongarch`` Maintained \- --``riscv`` Maintained ``riscv64`` and LLVM/Clang only. -+``riscv`` Maintained ``riscv64`` only. - ``um`` Maintained \- - ``x86`` Maintained ``x86_64`` only. - ============= ================ ============================================== -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 9c43346fabcd..1aa7fec41c09 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -194,7 +194,7 @@ config RISCV - select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_RETHOOK if !XIP_KERNEL - select HAVE_RSEQ -- select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG -+ select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI - select HAVE_SAMPLE_FTRACE_DIRECT - select HAVE_SAMPLE_FTRACE_DIRECT_MULTI - select HAVE_STACKPROTECTOR -@@ -618,6 +618,8 @@ config TOOLCHAIN_HAS_V - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv) - depends on LD_IS_LLD || LD_VERSION >= 23800 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64imv) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32imv) - - config RISCV_ISA_V - bool "Vector extension support" -@@ -682,6 +684,8 @@ config TOOLCHAIN_HAS_ZABHA - depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha) - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha) - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zabha) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zabha) - - config RISCV_ISA_ZABHA - bool "Zabha extension support for atomic byte/halfword operations" -@@ -700,6 +704,8 @@ config TOOLCHAIN_HAS_ZACAS - depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas) - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas) - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zacas) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zacas) - - config RISCV_ISA_ZACAS - bool "Zacas extension support for atomic CAS" -@@ -718,6 +724,8 @@ config TOOLCHAIN_HAS_ZBB - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbb) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbb) - - # This symbol indicates that the toolchain supports all v1.0 vector crypto - # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once. -@@ -733,6 +741,8 @@ config TOOLCHAIN_HAS_ZBA - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zba) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zba) - - config RISCV_ISA_ZBA - bool "Zba extension support for bit manipulation instructions" -@@ -768,6 +778,8 @@ config TOOLCHAIN_HAS_ZBC - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbc) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbc) - - config RISCV_ISA_ZBC - bool "Zbc extension support for carry-less multiplication instructions" -@@ -791,6 +803,8 @@ config TOOLCHAIN_HAS_ZBKB - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbkb) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbkb) - - config RISCV_ISA_ZBKB - bool "Zbkb extension support for bit manipulation instructions" -@@ -878,6 +892,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC - versions of clang and GCC to be passed to GAS, which has the same result - as passing zicsr and zifencei to -march. - -+config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI -+ def_bool y -+ depends on !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zicsr_zifencei) -+ depends on !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zicsr_zifencei) -+ -+config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI -+ def_bool y -+ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 -+ depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI -+ help -+ LLVM/Clang >= 17.0.0 starts recognizing Zicsr/Zifencei in -march, passing -+ them to -march doesn't generate an error anymore, and passing them or not -+ doesn't have any real difference, it still follows ISA before version -+ 20190608 - Zicsr/Zifencei are included in base ISA. -+ -+ The current latest version of LLVM/Clang still does not require explicit -+ Zicsr/Zifencei to enable these two extensions, Clang just accepts them in -+ -march and then silently ignores them. -+ - config FPU - bool "FPU support" - default y -diff --git a/rust/Makefile b/rust/Makefile -index 6d2d542a55e8..046492426017 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -298,7 +298,8 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fno-inline-functions-called-once -fsanitize=bounds-strict \ - -fstrict-flex-arrays=% -fmin-function-alignment=% \ - -fzero-init-padding-bits=% -mno-fdpic \ -- --param=% --param asan-% -fno-isolate-erroneous-paths-dereference -+ --param=% --param asan-% -fno-isolate-erroneous-paths-dereference \ -+ -mno-riscv-attribute - - # Because scripts/Makefile.rust is included regardless of whether Rust is enabled, - # we perform this check here to avoid breaking targets that do not yet support Rust builds. -diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust -index 5c12b4b8c8b6..bfdad4a0a3ce 100644 ---- a/scripts/Makefile.rust -+++ b/scripts/Makefile.rust -@@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 := x86_64-linux-gnu - BINDGEN_TARGET_arm64 := aarch64-linux-gnu - BINDGEN_TARGET_arm := arm-linux-gnueabi - BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf -+BINDGEN_TARGET_riscv := riscv64-linux-gnu - BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) - BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0311-UPSTREAM-drm-imagination-Skip-check-on-paired-job-fe.patch b/SPECS/linux-lts-kmhv2/0311-UPSTREAM-drm-imagination-Skip-check-on-paired-job-fe.patch new file mode 100644 index 0000000000..1b153151ce --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0311-UPSTREAM-drm-imagination-Skip-check-on-paired-job-fe.patch @@ -0,0 +1,57 @@ +From f167ab31c2dd0055541129478ef3ea0991a79898 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:38 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip check on paired job + fence during job submission + +While submitting a paired fragment job, there is no need to manually +look for, and skip, the paired job fence, as the existing logic to +resolve dependencies to pvr_queue_fence objects will have failed to +resolve it already and continued with the next one. + +Point this out where the fence is actually accessed and drop the related +check. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 18998b3cb7595850b8b2da55adb3fdc7aef8bc22) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 7d0d09026b82..6fdf74a1b73c 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -646,10 +646,6 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + +- /* This fence will be placed last, as partial render fence. */ +- if (is_paired_job_fence(fence, job)) +- continue; +- + if (dma_fence_is_signaled(&jfence->base)) + continue; + +@@ -664,8 +660,13 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + } + } + +- /* Partial render fence goes last. */ + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { ++ /* ++ * The loop above will only process dependencies backed by a UFO i.e. with ++ * a valid parent fence assigned, but the paired job dependency won't have ++ * one until both jobs have been submitted. Access the parent fence directly ++ * here instead, submitting it last as partial render fence. ++ */ + jfence = to_pvr_queue_job_fence(job->paired_job->done_fence); + if (!WARN_ON(!jfence)) { + pvr_fw_object_get_fw_addr(jfence->queue->timeline_ufo.fw_obj, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch deleted file mode 100644 index cde256c3dd..0000000000 --- a/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 6b99e40ab4ea69deb0bef324e4a5160a020862f2 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sun, 21 Dec 2025 16:20:26 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset - support - -The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus -which shared by all controllers, while another one connect to individual -controller separately. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20251221-07-k1-sdhci-reset-v1-1-6780af7fa6e7@gentoo.org -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 383841369fb2..1081ea687702 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -34,12 +34,24 @@ properties: - - const: core - - const: io - -+ resets: -+ items: -+ - description: axi reset, connect to AXI bus, shared by all controllers -+ - description: sdh reset, connect to individual controller separately -+ -+ reset-names: -+ items: -+ - const: axi -+ - const: sdh -+ - required: - - compatible - - reg - - interrupts - - clocks - - clock-names -+ - resets -+ - reset-names - - unevaluatedProperties: false - -@@ -52,4 +64,6 @@ examples: - interrupt-parent = <&plic>; - clocks = <&clk_apmu 10>, <&clk_apmu 13>; - clock-names = "core", "io"; -+ resets = <&syscon_apmu 2>, <&syscon_apmu 5>; -+ reset-names = "axi", "sdh"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0312-UPSTREAM-drm-imagination-Rename-pvr_queue_fence_is_u.patch b/SPECS/linux-lts-kmhv2/0312-UPSTREAM-drm-imagination-Rename-pvr_queue_fence_is_u.patch new file mode 100644 index 0000000000..2eda8c732e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0312-UPSTREAM-drm-imagination-Rename-pvr_queue_fence_is_u.patch @@ -0,0 +1,89 @@ +From 351437995884f517e697b735ff5f09abc94f598c Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:39 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Rename + pvr_queue_fence_is_ufo_backed() to reflect usage + +This function is only used by the synchronization code to figure out if +a fence belongs to this driver. +Rename it to pvr_queue_fence_is_native() and update its documentation to +reflect its current purpose. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit c162e655092de8de2e0f7776d72919dd5e3b84f2) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 14 +++++++------- + drivers/gpu/drm/imagination/pvr_queue.h | 2 +- + drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- + 3 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 6fdf74a1b73c..609ba457a619 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -898,16 +898,16 @@ static const struct drm_sched_backend_ops pvr_queue_sched_ops = { + }; + + /** +- * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO object ++ * pvr_queue_fence_is_native() - Check if a dma_fence is native to this driver. + * @f: Fence to test. + * +- * A UFO-backed fence is a fence that can be signaled or waited upon FW-side. +- * pvr_job::done_fence objects are backed by the timeline UFO attached to the queue +- * they are pushed to, but those fences are not directly exposed to the outside +- * world, so we also need to check if the fence we're being passed is a +- * drm_sched_fence that was coming from our driver. ++ * Check if the fence we're being passed is a drm_sched_fence that is coming from this driver. ++ * ++ * It may be a UFO-backed fence i.e. a fence that can be signaled or waited upon FW-side, ++ * such as pvr_job::done_fence objects that are backed by the timeline UFO attached to the queue ++ * they are pushed to. + */ +-bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f) ++bool pvr_queue_fence_is_native(struct dma_fence *f) + { + struct drm_sched_fence *sched_fence = f ? to_drm_sched_fence(f) : NULL; + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.h b/drivers/gpu/drm/imagination/pvr_queue.h +index fc1986d73fc8..4aa72665ce25 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.h ++++ b/drivers/gpu/drm/imagination/pvr_queue.h +@@ -141,7 +141,7 @@ struct pvr_queue { + u64 callstack_addr; + }; + +-bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f); ++bool pvr_queue_fence_is_native(struct dma_fence *f); + + int pvr_queue_job_init(struct pvr_job *job, u64 drm_client_id); + +diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c +index 129f646d14ba..d627c36e262f 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.c ++++ b/drivers/gpu/drm/imagination/pvr_sync.c +@@ -211,7 +211,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) + int err = 0; + + dma_fence_unwrap_for_each(uf, &iter, f) { +- if (pvr_queue_fence_is_ufo_backed(uf)) ++ if (pvr_queue_fence_is_native(uf)) + native_fence_count++; + } + +@@ -227,7 +227,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) + if (err) + continue; + +- if (pvr_queue_fence_is_ufo_backed(uf)) { ++ if (pvr_queue_fence_is_native(uf)) { + struct drm_sched_fence *s_fence = to_drm_sched_fence(uf); + + /* If this is a native dependency, we wait for the scheduled fence, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch b/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch deleted file mode 100644 index 27e125777e..0000000000 --- a/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch +++ /dev/null @@ -1,31 +0,0 @@ -From e4c3413f71ca577a9344235a8e76978b9df6b41d Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Mon, 3 Nov 2025 00:02:00 +0100 -Subject: [RUYI PATCH] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for the - SpacemiT P1 chip - -Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20251102230352.914421-3-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - drivers/mfd/simple-mfd-i2c.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c -index 9f911afafc25..c4166e8aeb9d 100644 ---- a/drivers/mfd/simple-mfd-i2c.c -+++ b/drivers/mfd/simple-mfd-i2c.c -@@ -99,6 +99,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { - }; - - static const struct mfd_cell spacemit_p1_cells[] = { -+ { .name = "spacemit-p1-reboot", }, - { .name = "spacemit-p1-regulator", }, - { .name = "spacemit-p1-rtc", }, - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0313-UPSTREAM-drm-imagination-Rename-fence-returned-by-pv.patch b/SPECS/linux-lts-kmhv2/0313-UPSTREAM-drm-imagination-Rename-fence-returned-by-pv.patch new file mode 100644 index 0000000000..f75151b8b4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0313-UPSTREAM-drm-imagination-Rename-fence-returned-by-pv.patch @@ -0,0 +1,90 @@ +From b6f87f4ccf25cada139114a10bc4d9c644d91f5e Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:40 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Rename fence returned by + pvr_queue_job_arm() + +Rename from done_fence to finished_fence, both because the function +returns a drm_sched_fence's finished fence, and to avoid confusion with +the job fence, which is called the same but has a different purpose. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 5dae1a21f1e7128a19c68212422383f700699d01) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_job.c | 8 ++++---- + drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- + drivers/gpu/drm/imagination/pvr_sync.h | 2 +- + 3 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c +index 7564b0f21b42..2da61083ab3e 100644 +--- a/drivers/gpu/drm/imagination/pvr_job.c ++++ b/drivers/gpu/drm/imagination/pvr_job.c +@@ -326,7 +326,7 @@ prepare_job_syncs(struct pvr_file *pvr_file, + struct pvr_job_data *job_data, + struct xarray *signal_array) + { +- struct dma_fence *done_fence; ++ struct dma_fence *finished_fence; + int err = pvr_sync_signal_array_collect_ops(signal_array, + from_pvr_file(pvr_file), + job_data->sync_op_count, +@@ -359,13 +359,13 @@ prepare_job_syncs(struct pvr_file *pvr_file, + return err; + } + +- /* We need to arm the job to get the job done fence. */ +- done_fence = pvr_queue_job_arm(job_data->job); ++ /* We need to arm the job to get the job finished fence. */ ++ finished_fence = pvr_queue_job_arm(job_data->job); + + err = pvr_sync_signal_array_update_fences(signal_array, + job_data->sync_op_count, + job_data->sync_ops, +- done_fence); ++ finished_fence); + return err; + } + +diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c +index d627c36e262f..45ac7a0aff65 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.c ++++ b/drivers/gpu/drm/imagination/pvr_sync.c +@@ -160,7 +160,7 @@ int + pvr_sync_signal_array_update_fences(struct xarray *array, + u32 sync_op_count, + const struct drm_pvr_sync_op *sync_ops, +- struct dma_fence *done_fence) ++ struct dma_fence *finished_fence) + { + for (u32 i = 0; i < sync_op_count; i++) { + struct dma_fence *old_fence; +@@ -175,7 +175,7 @@ pvr_sync_signal_array_update_fences(struct xarray *array, + return -EINVAL; + + old_fence = sig_sync->fence; +- sig_sync->fence = dma_fence_get(done_fence); ++ sig_sync->fence = dma_fence_get(finished_fence); + dma_fence_put(old_fence); + + if (WARN_ON(!sig_sync->fence)) +diff --git a/drivers/gpu/drm/imagination/pvr_sync.h b/drivers/gpu/drm/imagination/pvr_sync.h +index db6ccfda104a..48501ad27794 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.h ++++ b/drivers/gpu/drm/imagination/pvr_sync.h +@@ -70,7 +70,7 @@ int + pvr_sync_signal_array_update_fences(struct xarray *array, + u32 sync_op_count, + const struct drm_pvr_sync_op *sync_ops, +- struct dma_fence *done_fence); ++ struct dma_fence *finished_fence); + + void + pvr_sync_signal_array_push_fences(struct xarray *array); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch deleted file mode 100644 index 2e6395db50..0000000000 --- a/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 976f3a509c35b7b5a88d9f5f44f15301bbfef945 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 16:38:54 +0800 -Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as - dependencies - -REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on -MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' -does not always respect the parent's dependencies, so 'depends on' -is the safer and more correct choice. - -Since MFD_SPACEMIT_P1 already depends on I2C_K1, the dependency -in REGULATOR_SPACEMIT_P1 is now redundant. - -Additionally, the default value depends on MFD_SPACEMIT_P1 rather -than ARCH_SPACEMIT. - -Acked-by: Mark Brown -Acked-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-1-6fe19f460269@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/regulator/Kconfig | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index d84f3d054c59..3701d0fe3e06 100644 ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1455,9 +1455,8 @@ config REGULATOR_SLG51000 - config REGULATOR_SPACEMIT_P1 - tristate "SpacemiT P1 regulators" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on I2C -- select MFD_SPACEMIT_P1 -- default ARCH_SPACEMIT -+ depends on MFD_SPACEMIT_P1 -+ default m if MFD_SPACEMIT_P1 - help - Enable support for regulators implemented by the SpacemiT P1 - power controller. The P1 implements 6 high-efficiency buck --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0314-UPSTREAM-drm-imagination-Move-repeated-job-fence-che.patch b/SPECS/linux-lts-kmhv2/0314-UPSTREAM-drm-imagination-Move-repeated-job-fence-che.patch new file mode 100644 index 0000000000..a3106f6d7d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0314-UPSTREAM-drm-imagination-Move-repeated-job-fence-che.patch @@ -0,0 +1,71 @@ +From c00d4f006162665ea56fcd25375f61e34fa161a4 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:41 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Move repeated job fence check + to its own function + +This should make the code slightly clearer. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 402562e60c6c1b15ee359ba7ffed907baa886a99) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 25 ++++++++++++++++++++----- + 1 file changed, 20 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 609ba457a619..2a26b87d146d 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -177,6 +177,24 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { + .release = pvr_queue_fence_release, + }; + ++/** ++ * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO. ++ * @f: The dma_fence to check. ++ * ++ * Return: ++ * * true if the dma_fence is backed by a UFO, or ++ * * false otherwise. ++ */ ++static inline bool ++pvr_queue_fence_is_ufo_backed(struct dma_fence *f) ++{ ++ /* ++ * Currently the only dma_fence backed by a UFO object is the job fence, ++ * e.g. pvr_job::done_fence, wrapped by a pvr_queue_fence object. ++ */ ++ return f && f->ops == &pvr_queue_job_fence_ops; ++} ++ + /** + * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is + * already backed by a UFO. +@@ -194,7 +212,7 @@ to_pvr_queue_job_fence(struct dma_fence *f) + if (sched_fence) + f = sched_fence->parent; + +- if (f && f->ops == &pvr_queue_job_fence_ops) ++ if (pvr_queue_fence_is_ufo_backed(f)) + return container_of(f, struct pvr_queue_fence, base); + + return NULL; +@@ -915,10 +933,7 @@ bool pvr_queue_fence_is_native(struct dma_fence *f) + sched_fence->sched->ops == &pvr_queue_sched_ops) + return true; + +- if (f && f->ops == &pvr_queue_job_fence_ops) +- return true; +- +- return false; ++ return pvr_queue_fence_is_ufo_backed(f); + } + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch deleted file mode 100644 index a28f57c29e..0000000000 --- a/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch +++ /dev/null @@ -1,37 +0,0 @@ -From f7a63859a84191dd8619e6a34c9bf4d6664dcf23 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 16:38:56 +0800 -Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when - MFD_SPACEMIT_P1 is enabled - -The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which -caused it to be built-in automatically whenever the PMIC support was -set to y. - -This is not always desirable, as the RTC function is not required on -all platforms using the SpacemiT P1 PMIC. - -Acked-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-3-6fe19f460269@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/rtc/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig -index b392e6d096ed..4fc77f6b8a72 100644 ---- a/drivers/rtc/Kconfig -+++ b/drivers/rtc/Kconfig -@@ -410,7 +410,7 @@ config RTC_DRV_SPACEMIT_P1 - tristate "SpacemiT P1 RTC" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on MFD_SPACEMIT_P1 -- default MFD_SPACEMIT_P1 -+ default m if MFD_SPACEMIT_P1 - help - Enable support for the RTC function in the SpacemiT P1 PMIC. - This driver can also be built as a module, which will be called --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0315-UPSTREAM-drm-imagination-Update-check-to-skip-prepar.patch b/SPECS/linux-lts-kmhv2/0315-UPSTREAM-drm-imagination-Update-check-to-skip-prepar.patch new file mode 100644 index 0000000000..1e50d28b34 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0315-UPSTREAM-drm-imagination-Update-check-to-skip-prepar.patch @@ -0,0 +1,48 @@ +From 03c76855dc91a9dc6f7676155ff8621b7585106d Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:42 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Update check to skip + prepare_job() for fragment jobs + +By the time prepare_job() is called on a paired fragment job, the paired +geometry job might already be finished and its PM reference dropped. + +Check the fragment job's PM reference instead which is a bit more likely +to be still set. This is a very minor optimization. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 5c81eb2970133ad073214eb1e5b0c34a1ae793eb) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 2a26b87d146d..00cc0dd4ca2b 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -553,12 +553,13 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { + /* +- * This will be called on a paired fragment job after being +- * submitted to firmware. We can tell if this is the case and +- * bail early from whether run_job() has been called on the +- * geometry job, which would issue a pm ref. ++ * This will be called on a paired fragment job after being submitted ++ * to the firmware as part of the paired geometry job's submission. ++ * We can tell if this is the case and bail early from whether run_job() ++ * has been called on the geometry job, which would issue a pm ref on ++ * this job as well. + */ +- if (job->paired_job->has_pm_ref) ++ if (job->has_pm_ref) + return NULL; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch deleted file mode 100644 index 6981bb7c1e..0000000000 --- a/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 2a9661946f61c576e2b7534403eae881deb90a82 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:51 -0400 -Subject: [RUYI PATCH] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI support - -Add support for the SPI controller implemented by the SpacemiT K1 SoC. - -Acked-by: Conor Dooley -Acked-by: Troy Mitchell -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - .../bindings/spi/spacemit,k1-spi.yaml | 84 +++++++++++++++++++ - 1 file changed, 84 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml - -diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml -new file mode 100644 -index 000000000000..e82c7f8d0b98 ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml -@@ -0,0 +1,84 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) -+ -+maintainers: -+ - Alex Elder -+ -+description: -+ The SpacemiT K1 SoC implements a SPI controller that has two 32-entry -+ FIFOs, for transmit and receive. Details are currently available in -+ section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone -+ K1 Documentation[1]. The controller transfers words using PIO. DMA -+ transfers are supported as well, if both TX and RX DMA channels are -+ specified, -+ -+ [1] https://developer.spacemit.com/documentation -+ -+allOf: -+ - $ref: /schemas/spi/spi-controller.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k1-spi -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Core clock -+ - description: Bus clock -+ -+ clock-names: -+ items: -+ - const: core -+ - const: bus -+ -+ resets: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ dmas: -+ items: -+ - description: RX DMA channel -+ - description: TX DMA channel -+ -+ dma-names: -+ items: -+ - const: rx -+ - const: tx -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - interrupts -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ -+ #include -+ spi@d401c000 { -+ compatible = "spacemit,k1-spi"; -+ reg = <0xd401c000 0x30>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&syscon_apbc CLK_SSP3>, -+ <&syscon_apbc CLK_SSP3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_SSP3>; -+ interrupts = <55>; -+ dmas = <&pdma 20>, <&pdma 19>; -+ dma-names = "rx", "tx"; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0316-UPSTREAM-drm-imagination-Minor-improvements-to-job-s.patch b/SPECS/linux-lts-kmhv2/0316-UPSTREAM-drm-imagination-Minor-improvements-to-job-s.patch new file mode 100644 index 0000000000..4bb8046782 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0316-UPSTREAM-drm-imagination-Minor-improvements-to-job-s.patch @@ -0,0 +1,140 @@ +From 0ff6dd4a04aca768dcdcdc8a5eb44ce7095a4c92 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:43 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Minor improvements to job + submission code documentation + +Mixed list of clarifications and typo fixes. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-8-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 62a36c2da774800bef893bc4bf8922fb9c07c1d0) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 38 ++++++++++++------- + .../drm/imagination/pvr_rogue_fwif_shared.h | 10 +---- + 2 files changed, 26 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 00cc0dd4ca2b..21803d3cfbb4 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -200,6 +200,13 @@ pvr_queue_fence_is_ufo_backed(struct dma_fence *f) + * already backed by a UFO. + * @f: The dma_fence to turn into a pvr_queue_fence. + * ++ * This could be called on: ++ * - a job fence directly, in which case it simply returns the containing pvr_queue_fence; ++ * - a drm_sched_fence's scheduled or finished fence, in which case it will first try to follow ++ * the parent pointer to find the job fence (note that the parent pointer is initialized ++ * only after the run_job() callback is called on the drm_sched_fence's owning job); ++ * - any other dma_fence, in which case it will return NULL. ++ * + * Return: + * * A non-NULL pvr_queue_fence object if the dma_fence is backed by a UFO, or + * * NULL otherwise. +@@ -367,11 +374,14 @@ static u32 ufo_cmds_size(u32 elem_count) + + static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) + { +- /* One UFO cmd for the fence signaling, one UFO cmd per native fence native, +- * and a command for the job itself. ++ /* ++ * One UFO command per native fence this job will be waiting on (unless any are ++ * signaled by the time the job is submitted), plus a command for the job itself, ++ * plus one UFO command for the fence signaling. + */ +- return ufo_cmds_size(1) + ufo_cmds_size(ufo_wait_count) + +- pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); ++ return ufo_cmds_size(ufo_wait_count) + ++ pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len) + ++ ufo_cmds_size(1); + } + + static bool +@@ -517,12 +527,16 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) + if (!frag_job) + return NULL; + ++ /* Have the geometry job wait on the paired fragment job's dependencies as well. */ + xa_for_each(&frag_job->base.dependencies, index, f) { + /* Skip already signaled fences. */ + if (dma_fence_is_signaled(f)) + continue; + +- /* Skip our own fence. */ ++ /* ++ * The paired job fence won't be signaled until both jobs have ++ * been submitted, so we can't wait on it to schedule them. ++ */ + if (f == &job->base.s_fence->scheduled) + continue; + +@@ -665,6 +679,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + ++ /* Some dependencies might have been signaled since prepare_job() */ + if (dma_fence_is_signaled(&jfence->base)) + continue; + +@@ -714,7 +729,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + pvr_cccb_write_command_with_header(cccb, job->fw_ccb_cmd_type, job->cmd_len, job->cmd, + job->id, job->id); + +- /* Signal the job fence. */ ++ /* Update command to signal the job fence. */ + pvr_fw_object_get_fw_addr(queue->timeline_ufo.fw_obj, &ufos[0].addr); + ufos[0].value = job->done_fence->seqno; + pvr_cccb_write_command_with_header(cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE, +@@ -744,10 +759,8 @@ static struct dma_fence *pvr_queue_run_job(struct drm_sched_job *sched_job) + } + + /* The only kind of jobs that can be paired are geometry and fragment, and +- * we bail out early if we see a fragment job that's paired with a geomtry +- * job. +- * Paired jobs must also target the same context and point to the same +- * HWRT. ++ * we bail out early if we see a fragment job that's paired with a geometry job. ++ * Paired jobs must also target the same context and point to the same HWRT. + */ + if (WARN_ON(job->paired_job && + (job->type != DRM_PVR_JOB_TYPE_GEOMETRY || +@@ -966,9 +979,8 @@ pvr_queue_signal_done_fences(struct pvr_queue *queue) + } + + /** +- * pvr_queue_check_job_waiting_for_cccb_space() - Check if the job waiting for CCCB space +- * can be unblocked +- * pushed to the CCCB ++ * pvr_queue_check_job_waiting_for_cccb_space() - Check if a job waiting for CCCB space ++ * can be unblocked and pushed to the CCCB. + * @queue: Queue to check + * + * If we have a job waiting for CCCB, and this job now fits in the CCCB, we signal +diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +index 869d904e3649..fe54c1cad7a9 100644 +--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h ++++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +@@ -14,15 +14,7 @@ + + #define ROGUE_NUM_GEOM_CORES_SIZE 2U + +-/* +- * Maximum number of UFOs in a CCB command. +- * The number is based on having 32 sync prims (as originally), plus 32 sync +- * checkpoints. +- * Once the use of sync prims is no longer supported, we will retain +- * the same total (64) as the number of sync checkpoints which may be +- * supporting a fence is not visible to the client driver and has to +- * allow for the number of different timelines involved in fence merges. +- */ ++/* Maximum number of UFOs in a CCB command. */ + #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) + + /* +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch deleted file mode 100644 index 0ee0c336df..0000000000 --- a/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch +++ /dev/null @@ -1,852 +0,0 @@ -From 36ae899198d9231685aaf77e1dbcd6d51b0c9a76 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:52 -0400 -Subject: [RUYI PATCH] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI - controller driver - -This patch introduces the driver for the SPI controller found in the -SpacemiT K1 SoC. Currently the driver supports master mode only. -The SPI hardware implements RX and TX FIFOs, 32 entries each, and -supports both PIO and DMA mode transfers. - -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - drivers/spi/Kconfig | 9 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-spacemit-k1.c | 789 ++++++++++++++++++++++++++++++++++ - 3 files changed, 799 insertions(+) - create mode 100644 drivers/spi/spi-spacemit-k1.c - -diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index a63fb0a40be5..7cc04b5a1444 100644 ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -1073,6 +1073,15 @@ config SPI_SG2044_NOR - also supporting 3Byte address devices and 4Byte address - devices. - -+config SPI_SPACEMIT_K1 -+ tristate "K1 SPI Controller" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on OF -+ imply MMP_PDMA if ARCH_SPACEMIT -+ default m if ARCH_SPACEMIT -+ help -+ Enable support for the SpacemiT K1 SPI controller. -+ - config SPI_SPRD - tristate "Spreadtrum SPI controller" - depends on ARCH_SPRD || COMPILE_TEST -diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 1f7c06a3091d..f2beb2eb8b48 100644 ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -140,6 +140,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o - obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o - obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o - obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o -+obj-$(CONFIG_SPI_SPACEMIT_K1) += spi-spacemit-k1.o - obj-$(CONFIG_SPI_SPRD) += spi-sprd.o - obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o - obj-$(CONFIG_SPI_STM32) += spi-stm32.o -diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c -new file mode 100644 -index 000000000000..99db429db0b2 ---- /dev/null -+++ b/drivers/spi/spi-spacemit-k1.c -@@ -0,0 +1,789 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// SpacemiT K1 SPI controller driver -+// -+// Copyright (C) 2026, RISCstar Solutions Corporation -+// Copyright (C) 2023, SpacemiT Corporation -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "internals.h" -+ -+/* This is the range of transfer rates supported by the K1 SoC */ -+#define K1_SPI_MIN_SPEED_HZ 6250 -+#define K1_SPI_MAX_SPEED_HZ 51200000 -+ -+/* DMA constraints */ -+#define K1_SPI_DMA_ALIGNMENT 64 -+#define K1_SPI_MAX_DMA_LEN SZ_512K -+ -+/* SSP Top Control Register */ -+#define SSP_TOP_CTRL 0x00 -+#define TOP_SSE BIT(0) /* Enable port */ -+#define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ -+#define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ -+#define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ -+#define TOP_SPO BIT(10) /* Polarity: 0=low */ -+#define TOP_SPH BIT(11) /* Half-cycle phase */ -+#define TOP_LBM BIT(12) /* Loopback mode */ -+#define TOP_TRAIL BIT(13) /* Trailing bytes */ -+#define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ -+ -+/* SSP FIFO Control Register */ -+#define SSP_FIFO_CTRL 0x04 -+#define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ -+#define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ -+#define FIFO_TSRE BIT(10) /* TX service request */ -+#define FIFO_RSRE BIT(11) /* RX service request */ -+ -+/* SSP Interrupt Enable Register */ -+#define SSP_INT_EN 0x08 -+#define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ -+#define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ -+#define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ -+#define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ -+#define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ -+#define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ -+ -+/* TX interrupts, RX interrupts, and error interrupts */ -+#define SSP_INT_EN_TX SSP_INT_EN_TIE -+#define SSP_INT_EN_RX \ -+ (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) -+#define SSP_INT_EN_ERROR \ -+ (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) -+ -+/* SSP Time Out Register */ -+#define SSP_TIMEOUT 0x0c -+#define SSP_TIMEOUT_MASK GENMASK(23, 0) -+ -+/* SSP Data Register */ -+#define SSP_DATAR 0x10 -+ -+/* SSP Status Register */ -+#define SSP_STATUS 0x14 -+#define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ -+#define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ -+#define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ -+#define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ -+#define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ -+#define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ -+#define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ -+#define SSP_STATUS_BCE BIT(21) /* Bit count error */ -+ -+/* Error status mask */ -+#define SSP_STATUS_ERROR \ -+ (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) -+ -+/* The FIFO sizes and thresholds are the same for RX and TX */ -+#define K1_SPI_FIFO_SIZE 32 -+#define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) -+ -+struct k1_spi_driver_data { -+ struct spi_controller *host; -+ void __iomem *base; -+ phys_addr_t base_addr; -+ unsigned long bus_rate; -+ struct clk *clk; -+ unsigned long rate; -+ int irq; -+ -+ /* Current transfer information; not valid if message is null */ -+ u32 bytes; /* Bytes used for bits_per_word */ -+ unsigned int rx_resid; /* RX bytes left in transfer */ -+ unsigned int tx_resid; /* TX bytes left in transfer */ -+ struct spi_transfer *transfer; /* Current transfer */ -+ -+ bool dma_enabled; -+}; -+ -+/* Set our registers to a known initial state */ -+static void -+k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) -+{ -+ u32 val = 0; -+ -+ writel(0, drv_data->base + SSP_TOP_CTRL); -+ -+ if (initial) { -+ /* -+ * The TX and RX FIFO thresholds are the same no matter -+ * what the speed or bits per word, so we can just set -+ * them once. The thresholds are one more than the values -+ * in the register. -+ */ -+ val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); -+ val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); -+ } -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ writel(0, drv_data->base + SSP_INT_EN); -+ writel(0, drv_data->base + SSP_TIMEOUT); -+ -+ /* Clear any pending interrupt conditions */ -+ writel(~0, drv_data->base + SSP_STATUS); -+} -+ -+/* -+ * The client can call the setup function multiple times, and each call -+ * can specify a different SPI mode (and transfer speed). Each transfer -+ * can specify its own speed though, and the core code ensures each -+ * transfer's speed is set to something nonzero and supported by both -+ * the controller and the device. We just set the speed for each transfer. -+ */ -+static int k1_spi_setup(struct spi_device *spi) -+{ -+ struct k1_spi_driver_data *drv_data; -+ u32 val; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ -+ /* -+ * Configure the message format for this device. We only -+ * support Motorola SPI format in master mode. -+ */ -+ val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); -+ -+ /* Translate the mode into the value used to program the hardware. */ -+ if (spi->mode & SPI_CPHA) -+ val |= TOP_SPH; /* 1/2 cycle */ -+ if (spi->mode & SPI_CPOL) -+ val |= TOP_SPO; /* active low */ -+ if (spi->mode & SPI_LOOP) -+ val |= TOP_LBM; /* enable loopback */ -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ return 0; -+} -+ -+static void k1_spi_cleanup(struct spi_device *spi) -+{ -+ struct k1_spi_driver_data *drv_data; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ k1_spi_register_reset(drv_data, false); -+} -+ -+static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 burst_size; -+ -+ if (!drv_data->dma_enabled) -+ return false; -+ -+ if (transfer->len > SZ_2K) -+ return false; -+ -+ /* Don't bother with DMA if we can't do even a single burst */ -+ burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); -+ -+ return transfer->len >= burst_size; -+} -+ -+static void k1_spi_dma_callback(void *param) -+{ -+ struct k1_spi_driver_data *drv_data = param; -+ u32 val; -+ -+ val = readl(drv_data->base + SSP_FIFO_CTRL); -+ val &= ~(FIFO_TSRE | FIFO_RSRE); -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val &= ~TOP_TRAIL; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ /* Check for any error conditions */ -+ val = readl(drv_data->base + SSP_STATUS); -+ if (val & SSP_STATUS_ERROR) -+ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; -+ -+ /* Disable the port */ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val &= ~TOP_SSE; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ drv_data->transfer = NULL; -+ -+ spi_finalize_current_transfer(drv_data->host); -+} -+ -+/* Prepare a descriptor for TX or RX DMA */ -+static struct dma_async_tx_descriptor * -+k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, -+ struct spi_transfer *transfer, bool tx) -+{ -+ phys_addr_t addr = drv_data->base_addr + SSP_DATAR; -+ u32 burst_size = K1_SPI_THRESH * drv_data->bytes; -+ struct dma_slave_config cfg = { }; -+ enum dma_transfer_direction dir; -+ enum dma_slave_buswidth width; -+ struct dma_chan *chan; -+ struct sg_table *sgt; -+ -+ switch (drv_data->bytes) { -+ case 1: -+ width = DMA_SLAVE_BUSWIDTH_1_BYTE; -+ break; -+ case 2: -+ width = DMA_SLAVE_BUSWIDTH_2_BYTES; -+ break; -+ default: /* bytes == 4 */ -+ width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ break; -+ } -+ -+ if (tx) { -+ chan = drv_data->host->dma_tx; -+ sgt = &transfer->tx_sg; -+ dir = DMA_MEM_TO_DEV; -+ -+ cfg.dst_addr = addr; -+ cfg.dst_addr_width = width; -+ cfg.dst_maxburst = burst_size; -+ } else { -+ chan = drv_data->host->dma_rx; -+ sgt = &transfer->rx_sg; -+ dir = DMA_DEV_TO_MEM; -+ -+ cfg.src_addr = addr; -+ cfg.src_addr_width = width; -+ cfg.src_maxburst = burst_size; -+ } -+ cfg.direction = dir; -+ -+ if (dmaengine_slave_config(chan, &cfg)) -+ return NULL; -+ -+ return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); -+ -+} -+ -+static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ struct dma_async_tx_descriptor *desc; -+ u32 val; -+ -+ /* Prepare the TX descriptor and submit it */ -+ desc = k1_spi_dma_prep(drv_data, transfer, true); -+ if (!desc) -+ goto fallback; -+ dmaengine_submit(desc); -+ -+ /* Prepare the RX descriptor and submit it */ -+ desc = k1_spi_dma_prep(drv_data, transfer, false); -+ if (!desc) -+ goto fallback; -+ -+ /* When RX is complete we also know TX has completed */ -+ desc->callback = k1_spi_dma_callback; -+ desc->callback_param = drv_data; -+ -+ dmaengine_submit(desc); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ val = readl(drv_data->base + SSP_FIFO_CTRL); -+ val |= FIFO_TSRE | FIFO_RSRE; -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ /* Start RX first so we're ready the instant we start transmitting */ -+ dma_async_issue_pending(host->dma_rx); -+ dma_async_issue_pending(host->dma_tx); -+ -+ return 1; -+fallback: -+ transfer->error |= SPI_TRANS_FAIL_NO_START; -+ -+ return -EAGAIN; -+} -+ -+/* Flush the RX FIFO of any leftover data before processing a message */ -+static int k1_spi_prepare_message(struct spi_controller *host, -+ struct spi_message *message) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 val = readl(drv_data->base + SSP_STATUS); -+ u32 count; -+ -+ /* If there's nothing in the FIFO, we're done */ -+ if (!(val & SSP_STATUS_RNE)) -+ return 0; -+ -+ /* Read and discard what's there (one more than what the field says) */ -+ count = FIELD_GET(SSP_STATUS_RFL, val) + 1; -+ do -+ (void)readl(drv_data->base + SSP_DATAR); -+ while (--count); -+ -+ return 0; -+} -+ -+/* Set logic level of chip select line (high=true means CS deasserted) */ -+static void k1_spi_set_cs(struct spi_device *spi, bool high) -+{ -+ struct k1_spi_driver_data *drv_data; -+ u32 val; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ if (high) -+ val &= ~TOP_HOLD_FRAME_LOW; -+ else -+ val |= TOP_HOLD_FRAME_LOW; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+} -+ -+/* Set the transfer speed; the SPI core code ensures it is supported */ -+static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, -+ struct spi_transfer *transfer) -+{ -+ struct clk *clk = drv_data->clk; -+ u64 nsec_per_word; -+ u64 bus_ticks; -+ u32 timeout; -+ u32 val; -+ int ret; -+ -+ ret = clk_set_rate(clk, transfer->speed_hz); -+ if (ret) -+ return ret; -+ -+ drv_data->rate = clk_get_rate(clk); -+ -+ /* No need for RX FIFO timeout if we're not receiving anything */ -+ if (!transfer->rx_buf) -+ return 0; -+ -+ /* -+ * Compute the RX FIFO inactivity timeout value that should be used. -+ * The inactivity timer restarts with each word that lands in the -+ * FIFO. If several "word transfer times" pass without any new data -+ * in the RX FIFO, we might as well read what's there. -+ * -+ * The rate at which words land in the FIFO is determined by the -+ * word size and the transfer rate. One bit is transferred per -+ * clock tick, and 8 (or 16 or 32) bits are transferred per word. -+ * -+ * So we can get word transfer time (in nanoseconds) from: -+ * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; -+ * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; -+ * We do the divide last for better accuracy. -+ */ -+ nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; -+ nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); -+ -+ /* -+ * The timeout (which we'll set to three word transfer times) is -+ * expressed as a number of APB clock ticks. -+ * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) -+ */ -+ bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; -+ timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); -+ -+ /* Set the RX timeout period (required for both DMA and PIO) */ -+ val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); -+ writel(val, drv_data->base + SSP_TIMEOUT); -+ -+ return 0; -+} -+ -+static int k1_spi_transfer_one(struct spi_controller *host, -+ struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 ctrl; -+ u32 val; -+ int ret; -+ -+ /* Bits per word can change on a per-transfer basis */ -+ drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); -+ -+ /* Each transfer can also specify a different rate */ -+ ret = k1_spi_set_speed(drv_data, transfer); -+ if (ret) { -+ dev_err(&host->dev, -+ "failed to set transfer speed: %d\n", ret); -+ return ret; -+ } -+ -+ drv_data->rx_resid = transfer->len; -+ drv_data->tx_resid = transfer->len; -+ -+ drv_data->transfer = transfer; -+ -+ /* Clear any existing interrupt conditions */ -+ writel(~0, drv_data->base + SSP_STATUS); -+ -+ /* Set the data (word) size, and enable the port */ -+ ctrl = readl(drv_data->base + SSP_TOP_CTRL); -+ ctrl &= ~TOP_DSS_MASK; -+ ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); -+ ctrl |= TOP_SSE; -+ writel(ctrl, drv_data->base + SSP_TOP_CTRL); -+ -+ if (spi_xfer_is_dma_mapped(host, spi, transfer)) -+ return k1_spi_dma_one(host, spi, transfer); -+ -+ /* An interrupt will initiate the transfer */ -+ val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; -+ writel(val, drv_data->base + SSP_INT_EN); -+ -+ return 1; /* We will call spi_finalize_current_transfer() */ -+} -+ -+static void -+k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ -+ if (drv_data->dma_enabled) { -+ dmaengine_terminate_sync(host->dma_rx); -+ dmaengine_terminate_sync(host->dma_tx); -+ } -+} -+ -+static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) -+{ -+ struct spi_transfer *transfer = drv_data->transfer; -+ u32 bytes = drv_data->bytes; -+ u32 val; -+ -+ if (transfer->tx_buf) { -+ const void *buf; -+ -+ buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); -+ if (bytes == 1) -+ val = *(u8 *)buf; -+ else if (bytes == 2) -+ val = *(u16 *)buf; -+ else /* bytes == 4 */ -+ val = *(u32 *)buf; -+ } else { -+ val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ -+ } -+ /* Fill the next TX FIFO entry */ -+ writel(val, drv_data->base + SSP_DATAR); -+ -+ drv_data->tx_resid -= bytes; -+} -+ -+/* The last-read status value is provided; we know SSP_STATUS_TNF is set */ -+static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) -+{ -+ unsigned int count; -+ -+ /* Get the number of open slots in the FIFO; zero means all */ -+ count = FIELD_GET(SSP_STATUS_TFL, val) ? : K1_SPI_FIFO_SIZE; -+ -+ /* -+ * Limit how much we try to send at a time, to reduce the -+ * chance the other side can overrun our RX FIFO. -+ */ -+ count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); -+ do -+ k1_spi_write_word(drv_data); -+ while (--count); -+ -+ return !drv_data->tx_resid; -+} -+ -+static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) -+{ -+ struct spi_transfer *transfer = drv_data->transfer; -+ u32 bytes = drv_data->bytes; -+ u32 val; -+ -+ /* Consume the next RX FIFO entry */ -+ val = readl(drv_data->base + SSP_DATAR); -+ if (transfer->rx_buf) { -+ void *buf; -+ -+ buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); -+ -+ if (bytes == 1) -+ *(u8 *)buf = val; -+ else if (bytes == 2) -+ *(u16 *)buf = val; -+ else /* bytes == 4 */ -+ *(u32 *)buf = val; -+ } /* Otherwise null reader: discard the data */ -+ -+ drv_data->rx_resid -= bytes; -+} -+ -+/* The last-read status value is provided; we know SSP_STATUS_RNE is set */ -+static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) -+{ -+ do { -+ unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; -+ -+ /* Only read what we need */ -+ count = min(count, drv_data->rx_resid / drv_data->bytes); -+ do -+ k1_spi_read_word(drv_data); -+ while (--count); -+ -+ /* If there's no more to read, we're done */ -+ if (!drv_data->rx_resid) -+ return true; -+ -+ /* Check again in case more became available to read */ -+ val = readl(drv_data->base + SSP_STATUS); -+ if (val & SSP_STATUS_RNE) -+ writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); -+ else -+ return false; -+ } while (true); -+} -+ -+static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) -+{ -+ struct k1_spi_driver_data *drv_data = dev_id; -+ u32 status; -+ u32 top_ctrl; -+ -+ /* Get status and clear pending interrupts */ -+ status = readl(drv_data->base + SSP_STATUS); -+ writel(status, drv_data->base + SSP_STATUS); -+ -+ /* If no actionable status bits are set, this is not our interrupt */ -+ if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) -+ return IRQ_NONE; -+ -+ /* Check for any error conditions first */ -+ if (status & SSP_STATUS_ERROR) { -+ if (drv_data->transfer) -+ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; -+ goto done; -+ } -+ -+ /* -+ * For SPI, bytes are transferred in both directions equally, and -+ * RX always follows TX. Start by writing if there is anything to -+ * write, then read. Once there's no more to read, we're done. -+ */ -+ if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { -+ /* If we finish writing, disable TX interrupts */ -+ if (k1_spi_write(drv_data, status)) -+ writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, -+ drv_data->base + SSP_INT_EN); -+ } -+ -+ /* We're not done unless we've read all that was requested */ -+ if (drv_data->rx_resid) { -+ /* Read more if the FIFO is not empty */ -+ if (status & SSP_STATUS_RNE) -+ if (k1_spi_read(drv_data, status)) -+ goto done; -+ -+ return IRQ_HANDLED; -+ } -+done: -+ /* Disable the port */ -+ top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); -+ top_ctrl &= ~TOP_SSE; -+ writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); -+ -+ /* Disable all interrupts */ -+ writel(0, drv_data->base + SSP_INT_EN); -+ -+ if (drv_data->transfer) { -+ drv_data->transfer = NULL; -+ spi_finalize_current_transfer(drv_data->host); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int -+k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) -+{ -+ struct spi_controller *host = drv_data->host; -+ struct dma_chan *chan; -+ -+ chan = dma_request_chan(dev, "tx"); -+ if (IS_ERR(chan)) -+ return PTR_ERR(chan); -+ host->dma_tx = chan; -+ -+ chan = dma_request_chan(dev, "rx"); -+ if (IS_ERR(chan)) { -+ dma_release_channel(host->dma_tx); -+ host->dma_tx = NULL; -+ return PTR_ERR(chan); -+ } -+ host->dma_rx = chan; -+ -+ drv_data->dma_enabled = true; -+ -+ return 0; -+} -+ -+static void k1_spi_dma_cleanup(struct device *dev, void *res) -+{ -+ struct k1_spi_driver_data **ptr = res; -+ struct k1_spi_driver_data *drv_data = *ptr; -+ struct spi_controller *host = drv_data->host; -+ -+ if (!drv_data->dma_enabled) -+ return; -+ -+ drv_data->dma_enabled = false; -+ -+ dma_release_channel(host->dma_rx); -+ host->dma_rx = NULL; -+ dma_release_channel(host->dma_tx); -+ host->dma_tx = NULL; -+} -+ -+static int -+devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) -+{ -+ struct k1_spi_driver_data **ptr; -+ int ret; -+ -+ if (!IS_ENABLED(CONFIG_MMP_PDMA)) { -+ dev_info(dev, "DMA not available; using PIO\n"); -+ return 0; -+ } -+ -+ ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); -+ if (!ptr) -+ return -ENOMEM; -+ -+ ret = k1_spi_dma_setup(drv_data, dev); -+ if (ret) { -+ devres_free(ptr); -+ return ret; -+ } -+ -+ *ptr = drv_data; -+ devres_add(dev, ptr); -+ -+ return 0; -+} -+ -+static int k1_spi_probe(struct platform_device *pdev) -+{ -+ struct k1_spi_driver_data *drv_data; -+ struct device *dev = &pdev->dev; -+ struct reset_control *reset; -+ struct spi_controller *host; -+ struct resource *iores; -+ struct clk *clk_bus; -+ int ret; -+ -+ host = devm_spi_alloc_host(dev, sizeof(*drv_data)); -+ if (!host) -+ return -ENOMEM; -+ drv_data = spi_controller_get_devdata(host); -+ drv_data->host = host; -+ platform_set_drvdata(pdev, drv_data); -+ -+ ret = devm_k1_spi_dma_setup(drv_data, dev); -+ if (ret == -EPROBE_DEFER) -+ return ret; -+ if (ret) -+ dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); -+ -+ drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, -+ &iores); -+ if (IS_ERR(drv_data->base)) -+ return dev_err_probe(dev, PTR_ERR(drv_data->base), -+ "error mapping memory\n"); -+ drv_data->base_addr = iores->start; -+ -+ clk_bus = devm_clk_get_enabled(dev, "bus"); -+ if (IS_ERR(clk_bus)) -+ return dev_err_probe(dev, PTR_ERR(clk_bus), -+ "error getting/enabling bus clock\n"); -+ drv_data->bus_rate = clk_get_rate(clk_bus); -+ -+ drv_data->clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(drv_data->clk)) -+ return dev_err_probe(dev, PTR_ERR(drv_data->clk), -+ "error getting/enabling core clock\n"); -+ -+ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(reset)) -+ return dev_err_probe(dev, PTR_ERR(reset), -+ "error getting/deasserting reset\n"); -+ -+ k1_spi_register_reset(drv_data, true); -+ -+ drv_data->irq = platform_get_irq(pdev, 0); -+ if (drv_data->irq < 0) -+ return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); -+ -+ ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, -+ IRQF_SHARED, dev_name(dev), drv_data); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "error requesting IRQ\n"); -+ -+ /* Initialize the host structure, then register it */ -+ host->dev.of_node = dev_of_node(dev); -+ host->dev.parent = dev; -+ host->num_chipselect = 1; -+ if (drv_data->dma_enabled) -+ host->dma_alignment = K1_SPI_DMA_ALIGNMENT; -+ host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; -+ host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); -+ host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; -+ host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; -+ host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; -+ host->max_dma_len = K1_SPI_MAX_DMA_LEN; -+ -+ host->setup = k1_spi_setup; -+ host->cleanup = k1_spi_cleanup; -+ host->can_dma = k1_spi_can_dma; -+ host->prepare_message = k1_spi_prepare_message; -+ host->set_cs = k1_spi_set_cs; -+ host->transfer_one = k1_spi_transfer_one; -+ host->handle_err = k1_spi_handle_err; -+ -+ ret = devm_spi_register_controller(dev, host); -+ if (ret) -+ dev_err(dev, "error registering controller\n"); -+ -+ return ret; -+} -+ -+static const struct of_device_id k1_spi_dt_ids[] = { -+ { .compatible = "spacemit,k1-spi", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); -+ -+static struct platform_driver k1_spi_driver = { -+ .probe = k1_spi_probe, -+ .driver = { -+ .name = "k1-spi", -+ .of_match_table = k1_spi_dt_ids, -+ }, -+}; -+module_platform_driver(k1_spi_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0317-UPSTREAM-perf-riscv-Fix-discarded-const-qualifier-in.patch b/SPECS/linux-lts-kmhv2/0317-UPSTREAM-perf-riscv-Fix-discarded-const-qualifier-in.patch new file mode 100644 index 0000000000..3c33130788 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0317-UPSTREAM-perf-riscv-Fix-discarded-const-qualifier-in.patch @@ -0,0 +1,47 @@ +From cd1e45b5876eb3ddcb7d82dbb6af6141b27e83b1 Mon Sep 17 00:00:00 2001 +From: Li Guan +Date: Thu, 14 May 2026 02:07:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: perf riscv: Fix discarded const qualifier in + _get_field() + +The assignment of strrchr() return values to non-const char * variables +triggers a -Werror=discarded-qualifiers warning when building with GCC +14. + +This happens because in newer glibc versions, strrchr() returns a 'const +char *' if the input string is const. + +Properly declare 'line2' and 'nl' as const char * to match the glibc +function signature and ensure type safety. This avoids the need for +explicit type casting and aligns with the design pattern of not +modifying read-only memory in the perf tool. + +Reviewed-by: Ian Rogers +Signed-off-by: Li Guan +Cc: Adrian Hunter +Cc: Namhyung Kim +Cc: Palmer Dabbelt +Cc: Paul Walmsley +Signed-off-by: Arnaldo Carvalho de Melo +(cherry picked from commit 7378b6656aa46fda56f2743d5a7c1f619c2f6f9b) +Signed-off-by: Han Gao +--- + tools/perf/arch/riscv/util/header.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c +index 4b839203d4a5..891984e909bd 100644 +--- a/tools/perf/arch/riscv/util/header.c ++++ b/tools/perf/arch/riscv/util/header.c +@@ -19,7 +19,7 @@ + + static char *_get_field(const char *line) + { +- char *line2, *nl; ++ const char *line2, *nl; + + line2 = strrchr(line, ' '); + if (!line2) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch deleted file mode 100644 index e4a7aa5c83..0000000000 --- a/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch +++ /dev/null @@ -1,114 +0,0 @@ -From e61e5b8803d80c43b4959f8e4b6e863d1730fe51 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:53 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: define a SPI controller - node - -Define a node for the fourth SoC SPI controller (number 3) on the -SpacemiT K1 SoC. - -Enable it on the Banana Pi BPI-F3 board, which exposes this feature -via its GPIO block: - GPIO PIN 19: MOSI - GPIO PIN 21: MISO - GPIO PIN 23: SCLK - GPIO PIN 24: SS (inverted) - -Define pincontrol configurations for the pins as used on that board. - -(This was tested using a GigaDevice GD25Q64E SPI NOR chip.) - -Reviewed-by: Yixun Lan -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ - 3 files changed, 42 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 5790d927b93d..9429189354d6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -14,6 +14,7 @@ aliases { - ethernet0 = ð0; - ethernet1 = ð1; - serial0 = &uart0; -+ spi3 = &spi3; - i2c2 = &i2c2; - i2c8 = &i2c8; - }; -@@ -335,6 +336,12 @@ &pcie2 { - status = "okay"; - }; - -+&spi3 { -+ pinctrl-0 = <&ssp3_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index b13dcb10f4d6..34d88334e95e 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -570,4 +570,24 @@ pwm14-1-pins { - drive-strength = <32>; - }; - }; -+ -+ ssp3_0_cfg: ssp3-0-cfg { -+ ssp3-0-pins { -+ pinmux = , /* SCLK */ -+ , /* MOSI */ -+ ; /* MISO */ -+ -+ bias-disable; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ -+ ssp3-0-frm-pins { -+ pinmux = ; /* FRM (frame) */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index f0bad6855c97..f8747190d2e1 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -983,6 +983,21 @@ qspi: spi@d420c000 { - status = "disabled"; - }; - -+ spi3: spi@d401c000 { -+ compatible = "spacemit,k1-spi"; -+ reg = <0x0 0xd401c000 0x0 0x30>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&syscon_apbc CLK_SSP3>, -+ <&syscon_apbc CLK_SSP3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_SSP3>; -+ interrupts = <55>; -+ dmas = <&pdma 20>, <&pdma 19>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ - /* sec_uart1: 0xf0612000, not available from Linux */ - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0318-UPSTREAM-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-th.patch b/SPECS/linux-lts-kmhv2/0318-UPSTREAM-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-th.patch new file mode 100644 index 0000000000..87fa2e5dd5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0318-UPSTREAM-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-th.patch @@ -0,0 +1,34 @@ +From 0918127a4ec2839945f0afb57e86f0c0efe7f856 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Mon, 3 Nov 2025 00:02:00 +0100 +Subject: [RUYI PATCH] UPSTREAM: mfd: simple-mfd-i2c: Add a reboot cell for the + SpacemiT P1 chip + +Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll # OrangePi-RV2 +Link: https://patch.msgid.link/20251102230352.914421-3-aurelien@aurel32.net +Signed-off-by: Lee Jones +(cherry picked from commit 25c80f08e54ef5298eb68866f755f35b59a26d2b) +Signed-off-by: Han Gao +--- + drivers/mfd/simple-mfd-i2c.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c +index 9f911afafc25..c4166e8aeb9d 100644 +--- a/drivers/mfd/simple-mfd-i2c.c ++++ b/drivers/mfd/simple-mfd-i2c.c +@@ -99,6 +99,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { + }; + + static const struct mfd_cell spacemit_p1_cells[] = { ++ { .name = "spacemit-p1-reboot", }, + { .name = "spacemit-p1-regulator", }, + { .name = "spacemit-p1-rtc", }, + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch deleted file mode 100644 index 7bd9ac4c2d..0000000000 --- a/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 7769d31e702d0f09a02488efb2a7b55c42255417 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:15 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 thermal - sensor - -Document the SpacemiT K1 Thermal Sensor, which supports -monitoring temperatures for five zones: soc, package, gpu, cluster0, -and cluster1. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-1-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - .../bindings/thermal/spacemit,k1-tsensor.yaml | 76 +++++++++++++++++++ - 1 file changed, 76 insertions(+) - create mode 100644 Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml - -diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml -new file mode 100644 -index 000000000000..6dad76a7dd36 ---- /dev/null -+++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml -@@ -0,0 +1,76 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 Thermal Sensor -+ -+description: -+ The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC -+ using multiple internal sensors (e.g., soc, package, gpu, clusters). -+ -+maintainers: -+ - Shuwei Wu -+ -+$ref: thermal-sensor.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k1-tsensor -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Core clock for thermal sensor -+ - description: Bus clock for thermal sensor -+ -+ clock-names: -+ items: -+ - const: core -+ - const: bus -+ -+ interrupts: -+ maxItems: 1 -+ -+ resets: -+ items: -+ - description: Reset for the thermal sensor -+ -+ "#thermal-sensor-cells": -+ const: 1 -+ description: -+ The first cell indicates the sensor ID. -+ 0 = soc -+ 1 = package -+ 2 = gpu -+ 3 = cluster0 -+ 4 = cluster1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - resets -+ - "#thermal-sensor-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ thermal@d4018000 { -+ compatible = "spacemit,k1-tsensor"; -+ reg = <0xd4018000 0x100>; -+ clocks = <&syscon_apbc CLK_TSEN>, -+ <&syscon_apbc CLK_TSEN_BUS>; -+ clock-names = "core", "bus"; -+ interrupts = <61>; -+ resets = <&syscon_apbc RESET_TSEN>; -+ #thermal-sensor-cells = <1>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0319-UPSTREAM-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux-lts-kmhv2/0319-UPSTREAM-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch new file mode 100644 index 0000000000..97cb2590ec --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0319-UPSTREAM-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch @@ -0,0 +1,114 @@ +From c9de083b123ef9d664fb29c8f853770804df02fb Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:51 -0400 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: add SpacemiT K1 SPI support + +Add support for the SPI controller implemented by the SpacemiT K1 SoC. + +Acked-by: Conor Dooley +Acked-by: Troy Mitchell +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit b610d5333c4b93389240b62d1b6299e7e2ee2e65) +Signed-off-by: Han Gao +--- + .../bindings/spi/spacemit,k1-spi.yaml | 84 +++++++++++++++++++ + 1 file changed, 84 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml + +diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml +new file mode 100644 +index 000000000000..e82c7f8d0b98 +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml +@@ -0,0 +1,84 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) ++ ++maintainers: ++ - Alex Elder ++ ++description: ++ The SpacemiT K1 SoC implements a SPI controller that has two 32-entry ++ FIFOs, for transmit and receive. Details are currently available in ++ section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone ++ K1 Documentation[1]. The controller transfers words using PIO. DMA ++ transfers are supported as well, if both TX and RX DMA channels are ++ specified, ++ ++ [1] https://developer.spacemit.com/documentation ++ ++allOf: ++ - $ref: /schemas/spi/spi-controller.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k1-spi ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Core clock ++ - description: Bus clock ++ ++ clock-names: ++ items: ++ - const: core ++ - const: bus ++ ++ resets: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ dmas: ++ items: ++ - description: RX DMA channel ++ - description: TX DMA channel ++ ++ dma-names: ++ items: ++ - const: rx ++ - const: tx ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - interrupts ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ ++ #include ++ spi@d401c000 { ++ compatible = "spacemit,k1-spi"; ++ reg = <0xd401c000 0x30>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_SSP3>, ++ <&syscon_apbc CLK_SSP3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_SSP3>; ++ interrupts = <55>; ++ dmas = <&pdma 20>, <&pdma 19>; ++ dma-names = "rx", "tx"; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch b/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch deleted file mode 100644 index 0a1aad818b..0000000000 --- a/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch +++ /dev/null @@ -1,380 +0,0 @@ -From e87ee0243fcb7c4480eb9766f9800d4905e11b24 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:16 +0800 -Subject: [RUYI PATCH] FROMLIST: thermal: spacemit: k1: Add thermal sensor - support - -The thermal sensor on K1 supports monitoring five temperature zones. -The driver registers these sensors with the thermal framework -and supports standard operations: -- Reading temperature (millidegree Celsius) -- Setting high/low thresholds for interrupts - -Reviewed-by: Anand Moon -Tested-by: Anand Moon -Reviewed-by: Troy Mitchell -Reviewed-by: Yao Zi -Tested-by: Vincent Legoll # OrangePi-RV2 -Tested-by: Gong Shuai -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-2-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - drivers/thermal/Kconfig | 2 + - drivers/thermal/Makefile | 1 + - drivers/thermal/spacemit/Kconfig | 19 ++ - drivers/thermal/spacemit/Makefile | 3 + - drivers/thermal/spacemit/k1_tsensor.c | 280 ++++++++++++++++++++++++++ - 5 files changed, 305 insertions(+) - create mode 100644 drivers/thermal/spacemit/Kconfig - create mode 100644 drivers/thermal/spacemit/Makefile - create mode 100644 drivers/thermal/spacemit/k1_tsensor.c - -diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index a09c188b9ad1..a96e2d045d97 100644 ---- a/drivers/thermal/Kconfig -+++ b/drivers/thermal/Kconfig -@@ -462,6 +462,8 @@ endmenu - - source "drivers/thermal/renesas/Kconfig" - -+source "drivers/thermal/spacemit/Kconfig" -+ - source "drivers/thermal/tegra/Kconfig" - - config GENERIC_ADC_THERMAL -diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index d7718978db24..64cbed51d4fb 100644 ---- a/drivers/thermal/Makefile -+++ b/drivers/thermal/Makefile -@@ -64,6 +64,7 @@ obj-y += mediatek/ - obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o - obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o - obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o -+obj-y += spacemit/ - obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o - obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o - obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o -diff --git a/drivers/thermal/spacemit/Kconfig b/drivers/thermal/spacemit/Kconfig -new file mode 100644 -index 000000000000..de7b5ece5af2 ---- /dev/null -+++ b/drivers/thermal/spacemit/Kconfig -@@ -0,0 +1,19 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+menu "SpacemiT thermal drivers" -+depends on ARCH_SPACEMIT || COMPILE_TEST -+ -+config SPACEMIT_K1_TSENSOR -+ tristate "SpacemiT K1 thermal sensor driver" -+ depends on THERMAL_OF -+ help -+ This driver provides support for the thermal sensor -+ integrated in the SpacemiT K1 SoC. -+ -+ The thermal sensor monitors temperatures for five thermal zones: -+ soc, package, gpu, cluster0, and cluster1. It supports reporting -+ temperature values and handling high/low threshold interrupts. -+ -+ Say Y here if you want to enable thermal monitoring on SpacemiT K1. -+ If compiled as a module, it will be called k1_tsensor. -+ -+endmenu -diff --git a/drivers/thermal/spacemit/Makefile b/drivers/thermal/spacemit/Makefile -new file mode 100644 -index 000000000000..82b30741e4ec ---- /dev/null -+++ b/drivers/thermal/spacemit/Makefile -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_SPACEMIT_K1_TSENSOR) += k1_tsensor.o -diff --git a/drivers/thermal/spacemit/k1_tsensor.c b/drivers/thermal/spacemit/k1_tsensor.c -new file mode 100644 -index 000000000000..79222d233129 ---- /dev/null -+++ b/drivers/thermal/spacemit/k1_tsensor.c -@@ -0,0 +1,280 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Thermal sensor driver for SpacemiT K1 SoC -+ * -+ * Copyright (C) 2026 Shuwei Wu -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../thermal_hwmon.h" -+ -+#define K1_TSENSOR_PCTRL_REG 0x00 -+#define K1_TSENSOR_PCTRL_ENABLE BIT(0) -+#define K1_TSENSOR_PCTRL_TEMP_MODE BIT(3) -+#define K1_TSENSOR_PCTRL_RAW_SEL BIT(7) -+ -+#define K1_TSENSOR_PCTRL_CTUNE GENMASK(11, 8) -+#define K1_TSENSOR_PCTRL_SW_CTRL GENMASK(21, 18) -+#define K1_TSENSOR_PCTRL_HW_AUTO_MODE BIT(23) -+ -+#define K1_TSENSOR_EN_REG 0x08 -+#define K1_TSENSOR_EN_ALL GENMASK(MAX_SENSOR_NUMBER - 1, 0) -+ -+#define K1_TSENSOR_TIME_REG 0x0C -+#define K1_TSENSOR_TIME_WAIT_REF_CNT GENMASK(3, 0) -+#define K1_TSENSOR_TIME_ADC_CNT_RST GENMASK(7, 4) -+#define K1_TSENSOR_TIME_FILTER_PERIOD GENMASK(21, 20) -+#define K1_TSENSOR_TIME_MASK GENMASK(23, 0) -+ -+#define K1_TSENSOR_INT_CLR_REG 0x10 -+#define K1_TSENSOR_INT_EN_REG 0x14 -+#define K1_TSENSOR_INT_STA_REG 0x18 -+ -+#define K1_TSENSOR_INT_EN_MASK BIT(0) -+#define K1_TSENSOR_INT_MASK(x) (GENMASK(2, 1) << ((x) * 2)) -+ -+#define K1_TSENSOR_DATA_BASE_REG 0x20 -+#define K1_TSENSOR_DATA_REG(x) (K1_TSENSOR_DATA_BASE_REG + ((x) / 2) * 4) -+#define K1_TSENSOR_DATA_LOW_MASK GENMASK(15, 0) -+#define K1_TSENSOR_DATA_HIGH_MASK GENMASK(31, 16) -+ -+#define K1_TSENSOR_THRSH_BASE_REG 0x40 -+#define K1_TSENSOR_THRSH_REG(x) (K1_TSENSOR_THRSH_BASE_REG + ((x) * 4)) -+#define K1_TSENSOR_THRSH_LOW_MASK GENMASK(15, 0) -+#define K1_TSENSOR_THRSH_HIGH_MASK GENMASK(31, 16) -+ -+#define MAX_SENSOR_NUMBER 5 -+ -+/* Hardware offset value required for temperature calculation */ -+#define TEMPERATURE_OFFSET 278 -+ -+struct k1_tsensor_channel { -+ struct k1_tsensor *ts; -+ struct thermal_zone_device *tzd; -+ int id; -+}; -+ -+struct k1_tsensor { -+ void __iomem *base; -+ struct k1_tsensor_channel ch[MAX_SENSOR_NUMBER]; -+}; -+ -+static void k1_tsensor_init(struct k1_tsensor *ts) -+{ -+ u32 val; -+ -+ /* Disable all the interrupts */ -+ writel(0xffffffff, ts->base + K1_TSENSOR_INT_EN_REG); -+ -+ /* Configure ADC sampling time and filter period */ -+ val = readl(ts->base + K1_TSENSOR_TIME_REG); -+ val &= ~K1_TSENSOR_TIME_MASK; -+ val |= K1_TSENSOR_TIME_FILTER_PERIOD | -+ K1_TSENSOR_TIME_ADC_CNT_RST | -+ K1_TSENSOR_TIME_WAIT_REF_CNT; -+ writel(val, ts->base + K1_TSENSOR_TIME_REG); -+ -+ /* -+ * Enable all sensors' auto mode, enable dither control, -+ * consecutive mode, and power up sensor. -+ */ -+ val = readl(ts->base + K1_TSENSOR_PCTRL_REG); -+ val &= ~K1_TSENSOR_PCTRL_SW_CTRL; -+ val &= ~K1_TSENSOR_PCTRL_CTUNE; -+ val |= K1_TSENSOR_PCTRL_RAW_SEL | -+ K1_TSENSOR_PCTRL_TEMP_MODE | -+ K1_TSENSOR_PCTRL_HW_AUTO_MODE | -+ K1_TSENSOR_PCTRL_ENABLE; -+ writel(val, ts->base + K1_TSENSOR_PCTRL_REG); -+ -+ /* Enable each sensor */ -+ val = readl(ts->base + K1_TSENSOR_EN_REG); -+ val |= K1_TSENSOR_EN_ALL; -+ writel(val, ts->base + K1_TSENSOR_EN_REG); -+} -+ -+static void k1_tsensor_enable_irq(struct k1_tsensor_channel *ch) -+{ -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ val = readl(ts->base + K1_TSENSOR_INT_CLR_REG); -+ val |= K1_TSENSOR_INT_MASK(ch->id); -+ writel(val, ts->base + K1_TSENSOR_INT_CLR_REG); -+ -+ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); -+ val &= ~K1_TSENSOR_INT_MASK(ch->id); -+ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); -+ -+ /* Enable thermal interrupt */ -+ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); -+ val |= K1_TSENSOR_INT_EN_MASK; -+ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); -+} -+ -+/* -+ * The conversion formula used is: -+ * T(m°C) = (((raw_value & mask) >> shift) - TEMPERATURE_OFFSET) * 1000 -+ */ -+static int k1_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) -+{ -+ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ val = readl(ts->base + K1_TSENSOR_DATA_REG(ch->id)); -+ if (ch->id % 2) -+ *temp = FIELD_GET(K1_TSENSOR_DATA_HIGH_MASK, val); -+ else -+ *temp = FIELD_GET(K1_TSENSOR_DATA_LOW_MASK, val); -+ -+ *temp -= TEMPERATURE_OFFSET; -+ *temp *= 1000; -+ -+ return 0; -+} -+ -+/* -+ * For each sensor, the hardware threshold register is 32 bits: -+ * - Lower 16 bits [15:0] configure the low threshold temperature. -+ * - Upper 16 bits [31:16] configure the high threshold temperature. -+ */ -+static int k1_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) -+{ -+ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ if (low >= high) -+ return -EINVAL; -+ -+ low = clamp_val(low / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, -+ FIELD_MAX(K1_TSENSOR_THRSH_LOW_MASK)); -+ high = clamp_val(high / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, -+ FIELD_MAX(K1_TSENSOR_THRSH_HIGH_MASK)); -+ -+ val = readl(ts->base + K1_TSENSOR_THRSH_REG(ch->id)); -+ -+ val &= ~(K1_TSENSOR_THRSH_LOW_MASK | K1_TSENSOR_THRSH_HIGH_MASK); -+ val |= FIELD_PREP(K1_TSENSOR_THRSH_LOW_MASK, low); -+ val |= FIELD_PREP(K1_TSENSOR_THRSH_HIGH_MASK, high); -+ -+ writel(val, ts->base + K1_TSENSOR_THRSH_REG(ch->id)); -+ -+ return 0; -+} -+ -+static const struct thermal_zone_device_ops k1_tsensor_ops = { -+ .get_temp = k1_tsensor_get_temp, -+ .set_trips = k1_tsensor_set_trips, -+}; -+ -+static irqreturn_t k1_tsensor_irq_thread(int irq, void *data) -+{ -+ struct k1_tsensor *ts = (struct k1_tsensor *)data; -+ int mask, status, i; -+ -+ status = readl(ts->base + K1_TSENSOR_INT_STA_REG); -+ -+ for (i = 0; i < MAX_SENSOR_NUMBER; i++) { -+ if (status & K1_TSENSOR_INT_MASK(i)) { -+ mask = readl(ts->base + K1_TSENSOR_INT_CLR_REG); -+ mask |= K1_TSENSOR_INT_MASK(i); -+ writel(mask, ts->base + K1_TSENSOR_INT_CLR_REG); -+ thermal_zone_device_update(ts->ch[i].tzd, THERMAL_EVENT_UNSPECIFIED); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int k1_tsensor_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct k1_tsensor *ts; -+ struct reset_control *reset; -+ struct clk *clk; -+ int i, irq, ret; -+ -+ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); -+ if (!ts) -+ return -ENOMEM; -+ -+ ts->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ts->base)) -+ return dev_err_probe(dev, PTR_ERR(ts->base), "Failed to get reg\n"); -+ -+ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(reset)) -+ return dev_err_probe(dev, PTR_ERR(reset), "Failed to get/deassert reset control\n"); -+ -+ clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(clk)) -+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get core clock\n"); -+ -+ clk = devm_clk_get_enabled(dev, "bus"); -+ if (IS_ERR(clk)) -+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get bus clock\n"); -+ -+ k1_tsensor_init(ts); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = devm_request_threaded_irq(dev, irq, NULL, -+ k1_tsensor_irq_thread, -+ IRQF_ONESHOT, "k1_tsensor", ts); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 0; i < MAX_SENSOR_NUMBER; ++i) { -+ ts->ch[i].id = i; -+ ts->ch[i].ts = ts; -+ ts->ch[i].tzd = devm_thermal_of_zone_register(dev, i, ts->ch + i, &k1_tsensor_ops); -+ if (IS_ERR(ts->ch[i].tzd)) -+ return PTR_ERR(ts->ch[i].tzd); -+ -+ /* Attach sysfs hwmon attributes for userspace monitoring */ -+ ret = devm_thermal_add_hwmon_sysfs(dev, ts->ch[i].tzd); -+ if (ret) -+ dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); -+ -+ k1_tsensor_enable_irq(ts->ch + i); -+ } -+ -+ platform_set_drvdata(pdev, ts); -+ -+ return 0; -+} -+ -+static const struct of_device_id k1_tsensor_dt_ids[] = { -+ { .compatible = "spacemit,k1-tsensor" }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, k1_tsensor_dt_ids); -+ -+static struct platform_driver k1_tsensor_driver = { -+ .driver = { -+ .name = "k1_tsensor", -+ .of_match_table = k1_tsensor_dt_ids, -+ }, -+ .probe = k1_tsensor_probe, -+}; -+module_platform_driver(k1_tsensor_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 Thermal Sensor Driver"); -+MODULE_AUTHOR("Shuwei Wu "); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0320-UPSTREAM-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux-lts-kmhv2/0320-UPSTREAM-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch new file mode 100644 index 0000000000..a7a050e1c1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0320-UPSTREAM-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch @@ -0,0 +1,854 @@ +From 55568d74ff1ea521fbf5f33880177c367a364577 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:52 -0400 +Subject: [RUYI PATCH] UPSTREAM: spi: spacemit: introduce SpacemiT K1 SPI + controller driver + +This patch introduces the driver for the SPI controller found in the +SpacemiT K1 SoC. Currently the driver supports master mode only. +The SPI hardware implements RX and TX FIFOs, 32 entries each, and +supports both PIO and DMA mode transfers. + +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit efcd8b9d111177d48c841d09beca43b15d5b9e5f) +Signed-off-by: Han Gao +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-spacemit-k1.c | 789 ++++++++++++++++++++++++++++++++++ + 3 files changed, 799 insertions(+) + create mode 100644 drivers/spi/spi-spacemit-k1.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index a63fb0a40be5..7cc04b5a1444 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -1073,6 +1073,15 @@ config SPI_SG2044_NOR + also supporting 3Byte address devices and 4Byte address + devices. + ++config SPI_SPACEMIT_K1 ++ tristate "K1 SPI Controller" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on OF ++ imply MMP_PDMA if ARCH_SPACEMIT ++ default m if ARCH_SPACEMIT ++ help ++ Enable support for the SpacemiT K1 SPI controller. ++ + config SPI_SPRD + tristate "Spreadtrum SPI controller" + depends on ARCH_SPRD || COMPILE_TEST +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 1f7c06a3091d..f2beb2eb8b48 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -140,6 +140,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o + obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o + obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o + obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o ++obj-$(CONFIG_SPI_SPACEMIT_K1) += spi-spacemit-k1.o + obj-$(CONFIG_SPI_SPRD) += spi-sprd.o + obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o + obj-$(CONFIG_SPI_STM32) += spi-stm32.o +diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c +new file mode 100644 +index 000000000000..99db429db0b2 +--- /dev/null ++++ b/drivers/spi/spi-spacemit-k1.c +@@ -0,0 +1,789 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// SpacemiT K1 SPI controller driver ++// ++// Copyright (C) 2026, RISCstar Solutions Corporation ++// Copyright (C) 2023, SpacemiT Corporation ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "internals.h" ++ ++/* This is the range of transfer rates supported by the K1 SoC */ ++#define K1_SPI_MIN_SPEED_HZ 6250 ++#define K1_SPI_MAX_SPEED_HZ 51200000 ++ ++/* DMA constraints */ ++#define K1_SPI_DMA_ALIGNMENT 64 ++#define K1_SPI_MAX_DMA_LEN SZ_512K ++ ++/* SSP Top Control Register */ ++#define SSP_TOP_CTRL 0x00 ++#define TOP_SSE BIT(0) /* Enable port */ ++#define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ ++#define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ ++#define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ ++#define TOP_SPO BIT(10) /* Polarity: 0=low */ ++#define TOP_SPH BIT(11) /* Half-cycle phase */ ++#define TOP_LBM BIT(12) /* Loopback mode */ ++#define TOP_TRAIL BIT(13) /* Trailing bytes */ ++#define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ ++ ++/* SSP FIFO Control Register */ ++#define SSP_FIFO_CTRL 0x04 ++#define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ ++#define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ ++#define FIFO_TSRE BIT(10) /* TX service request */ ++#define FIFO_RSRE BIT(11) /* RX service request */ ++ ++/* SSP Interrupt Enable Register */ ++#define SSP_INT_EN 0x08 ++#define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ ++#define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ ++#define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ ++#define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ ++#define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ ++#define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ ++ ++/* TX interrupts, RX interrupts, and error interrupts */ ++#define SSP_INT_EN_TX SSP_INT_EN_TIE ++#define SSP_INT_EN_RX \ ++ (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) ++#define SSP_INT_EN_ERROR \ ++ (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) ++ ++/* SSP Time Out Register */ ++#define SSP_TIMEOUT 0x0c ++#define SSP_TIMEOUT_MASK GENMASK(23, 0) ++ ++/* SSP Data Register */ ++#define SSP_DATAR 0x10 ++ ++/* SSP Status Register */ ++#define SSP_STATUS 0x14 ++#define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ ++#define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ ++#define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ ++#define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ ++#define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ ++#define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ ++#define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ ++#define SSP_STATUS_BCE BIT(21) /* Bit count error */ ++ ++/* Error status mask */ ++#define SSP_STATUS_ERROR \ ++ (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) ++ ++/* The FIFO sizes and thresholds are the same for RX and TX */ ++#define K1_SPI_FIFO_SIZE 32 ++#define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) ++ ++struct k1_spi_driver_data { ++ struct spi_controller *host; ++ void __iomem *base; ++ phys_addr_t base_addr; ++ unsigned long bus_rate; ++ struct clk *clk; ++ unsigned long rate; ++ int irq; ++ ++ /* Current transfer information; not valid if message is null */ ++ u32 bytes; /* Bytes used for bits_per_word */ ++ unsigned int rx_resid; /* RX bytes left in transfer */ ++ unsigned int tx_resid; /* TX bytes left in transfer */ ++ struct spi_transfer *transfer; /* Current transfer */ ++ ++ bool dma_enabled; ++}; ++ ++/* Set our registers to a known initial state */ ++static void ++k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) ++{ ++ u32 val = 0; ++ ++ writel(0, drv_data->base + SSP_TOP_CTRL); ++ ++ if (initial) { ++ /* ++ * The TX and RX FIFO thresholds are the same no matter ++ * what the speed or bits per word, so we can just set ++ * them once. The thresholds are one more than the values ++ * in the register. ++ */ ++ val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); ++ val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); ++ } ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ writel(0, drv_data->base + SSP_INT_EN); ++ writel(0, drv_data->base + SSP_TIMEOUT); ++ ++ /* Clear any pending interrupt conditions */ ++ writel(~0, drv_data->base + SSP_STATUS); ++} ++ ++/* ++ * The client can call the setup function multiple times, and each call ++ * can specify a different SPI mode (and transfer speed). Each transfer ++ * can specify its own speed though, and the core code ensures each ++ * transfer's speed is set to something nonzero and supported by both ++ * the controller and the device. We just set the speed for each transfer. ++ */ ++static int k1_spi_setup(struct spi_device *spi) ++{ ++ struct k1_spi_driver_data *drv_data; ++ u32 val; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ ++ /* ++ * Configure the message format for this device. We only ++ * support Motorola SPI format in master mode. ++ */ ++ val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); ++ ++ /* Translate the mode into the value used to program the hardware. */ ++ if (spi->mode & SPI_CPHA) ++ val |= TOP_SPH; /* 1/2 cycle */ ++ if (spi->mode & SPI_CPOL) ++ val |= TOP_SPO; /* active low */ ++ if (spi->mode & SPI_LOOP) ++ val |= TOP_LBM; /* enable loopback */ ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ return 0; ++} ++ ++static void k1_spi_cleanup(struct spi_device *spi) ++{ ++ struct k1_spi_driver_data *drv_data; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ k1_spi_register_reset(drv_data, false); ++} ++ ++static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 burst_size; ++ ++ if (!drv_data->dma_enabled) ++ return false; ++ ++ if (transfer->len > SZ_2K) ++ return false; ++ ++ /* Don't bother with DMA if we can't do even a single burst */ ++ burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); ++ ++ return transfer->len >= burst_size; ++} ++ ++static void k1_spi_dma_callback(void *param) ++{ ++ struct k1_spi_driver_data *drv_data = param; ++ u32 val; ++ ++ val = readl(drv_data->base + SSP_FIFO_CTRL); ++ val &= ~(FIFO_TSRE | FIFO_RSRE); ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val &= ~TOP_TRAIL; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ /* Check for any error conditions */ ++ val = readl(drv_data->base + SSP_STATUS); ++ if (val & SSP_STATUS_ERROR) ++ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; ++ ++ /* Disable the port */ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val &= ~TOP_SSE; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ drv_data->transfer = NULL; ++ ++ spi_finalize_current_transfer(drv_data->host); ++} ++ ++/* Prepare a descriptor for TX or RX DMA */ ++static struct dma_async_tx_descriptor * ++k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, ++ struct spi_transfer *transfer, bool tx) ++{ ++ phys_addr_t addr = drv_data->base_addr + SSP_DATAR; ++ u32 burst_size = K1_SPI_THRESH * drv_data->bytes; ++ struct dma_slave_config cfg = { }; ++ enum dma_transfer_direction dir; ++ enum dma_slave_buswidth width; ++ struct dma_chan *chan; ++ struct sg_table *sgt; ++ ++ switch (drv_data->bytes) { ++ case 1: ++ width = DMA_SLAVE_BUSWIDTH_1_BYTE; ++ break; ++ case 2: ++ width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ default: /* bytes == 4 */ ++ width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ } ++ ++ if (tx) { ++ chan = drv_data->host->dma_tx; ++ sgt = &transfer->tx_sg; ++ dir = DMA_MEM_TO_DEV; ++ ++ cfg.dst_addr = addr; ++ cfg.dst_addr_width = width; ++ cfg.dst_maxburst = burst_size; ++ } else { ++ chan = drv_data->host->dma_rx; ++ sgt = &transfer->rx_sg; ++ dir = DMA_DEV_TO_MEM; ++ ++ cfg.src_addr = addr; ++ cfg.src_addr_width = width; ++ cfg.src_maxburst = burst_size; ++ } ++ cfg.direction = dir; ++ ++ if (dmaengine_slave_config(chan, &cfg)) ++ return NULL; ++ ++ return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ ++} ++ ++static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ struct dma_async_tx_descriptor *desc; ++ u32 val; ++ ++ /* Prepare the TX descriptor and submit it */ ++ desc = k1_spi_dma_prep(drv_data, transfer, true); ++ if (!desc) ++ goto fallback; ++ dmaengine_submit(desc); ++ ++ /* Prepare the RX descriptor and submit it */ ++ desc = k1_spi_dma_prep(drv_data, transfer, false); ++ if (!desc) ++ goto fallback; ++ ++ /* When RX is complete we also know TX has completed */ ++ desc->callback = k1_spi_dma_callback; ++ desc->callback_param = drv_data; ++ ++ dmaengine_submit(desc); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ val = readl(drv_data->base + SSP_FIFO_CTRL); ++ val |= FIFO_TSRE | FIFO_RSRE; ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ /* Start RX first so we're ready the instant we start transmitting */ ++ dma_async_issue_pending(host->dma_rx); ++ dma_async_issue_pending(host->dma_tx); ++ ++ return 1; ++fallback: ++ transfer->error |= SPI_TRANS_FAIL_NO_START; ++ ++ return -EAGAIN; ++} ++ ++/* Flush the RX FIFO of any leftover data before processing a message */ ++static int k1_spi_prepare_message(struct spi_controller *host, ++ struct spi_message *message) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 val = readl(drv_data->base + SSP_STATUS); ++ u32 count; ++ ++ /* If there's nothing in the FIFO, we're done */ ++ if (!(val & SSP_STATUS_RNE)) ++ return 0; ++ ++ /* Read and discard what's there (one more than what the field says) */ ++ count = FIELD_GET(SSP_STATUS_RFL, val) + 1; ++ do ++ (void)readl(drv_data->base + SSP_DATAR); ++ while (--count); ++ ++ return 0; ++} ++ ++/* Set logic level of chip select line (high=true means CS deasserted) */ ++static void k1_spi_set_cs(struct spi_device *spi, bool high) ++{ ++ struct k1_spi_driver_data *drv_data; ++ u32 val; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ if (high) ++ val &= ~TOP_HOLD_FRAME_LOW; ++ else ++ val |= TOP_HOLD_FRAME_LOW; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++} ++ ++/* Set the transfer speed; the SPI core code ensures it is supported */ ++static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, ++ struct spi_transfer *transfer) ++{ ++ struct clk *clk = drv_data->clk; ++ u64 nsec_per_word; ++ u64 bus_ticks; ++ u32 timeout; ++ u32 val; ++ int ret; ++ ++ ret = clk_set_rate(clk, transfer->speed_hz); ++ if (ret) ++ return ret; ++ ++ drv_data->rate = clk_get_rate(clk); ++ ++ /* No need for RX FIFO timeout if we're not receiving anything */ ++ if (!transfer->rx_buf) ++ return 0; ++ ++ /* ++ * Compute the RX FIFO inactivity timeout value that should be used. ++ * The inactivity timer restarts with each word that lands in the ++ * FIFO. If several "word transfer times" pass without any new data ++ * in the RX FIFO, we might as well read what's there. ++ * ++ * The rate at which words land in the FIFO is determined by the ++ * word size and the transfer rate. One bit is transferred per ++ * clock tick, and 8 (or 16 or 32) bits are transferred per word. ++ * ++ * So we can get word transfer time (in nanoseconds) from: ++ * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; ++ * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; ++ * We do the divide last for better accuracy. ++ */ ++ nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; ++ nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); ++ ++ /* ++ * The timeout (which we'll set to three word transfer times) is ++ * expressed as a number of APB clock ticks. ++ * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) ++ */ ++ bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; ++ timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); ++ ++ /* Set the RX timeout period (required for both DMA and PIO) */ ++ val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); ++ writel(val, drv_data->base + SSP_TIMEOUT); ++ ++ return 0; ++} ++ ++static int k1_spi_transfer_one(struct spi_controller *host, ++ struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 ctrl; ++ u32 val; ++ int ret; ++ ++ /* Bits per word can change on a per-transfer basis */ ++ drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); ++ ++ /* Each transfer can also specify a different rate */ ++ ret = k1_spi_set_speed(drv_data, transfer); ++ if (ret) { ++ dev_err(&host->dev, ++ "failed to set transfer speed: %d\n", ret); ++ return ret; ++ } ++ ++ drv_data->rx_resid = transfer->len; ++ drv_data->tx_resid = transfer->len; ++ ++ drv_data->transfer = transfer; ++ ++ /* Clear any existing interrupt conditions */ ++ writel(~0, drv_data->base + SSP_STATUS); ++ ++ /* Set the data (word) size, and enable the port */ ++ ctrl = readl(drv_data->base + SSP_TOP_CTRL); ++ ctrl &= ~TOP_DSS_MASK; ++ ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); ++ ctrl |= TOP_SSE; ++ writel(ctrl, drv_data->base + SSP_TOP_CTRL); ++ ++ if (spi_xfer_is_dma_mapped(host, spi, transfer)) ++ return k1_spi_dma_one(host, spi, transfer); ++ ++ /* An interrupt will initiate the transfer */ ++ val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; ++ writel(val, drv_data->base + SSP_INT_EN); ++ ++ return 1; /* We will call spi_finalize_current_transfer() */ ++} ++ ++static void ++k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ ++ if (drv_data->dma_enabled) { ++ dmaengine_terminate_sync(host->dma_rx); ++ dmaengine_terminate_sync(host->dma_tx); ++ } ++} ++ ++static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) ++{ ++ struct spi_transfer *transfer = drv_data->transfer; ++ u32 bytes = drv_data->bytes; ++ u32 val; ++ ++ if (transfer->tx_buf) { ++ const void *buf; ++ ++ buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); ++ if (bytes == 1) ++ val = *(u8 *)buf; ++ else if (bytes == 2) ++ val = *(u16 *)buf; ++ else /* bytes == 4 */ ++ val = *(u32 *)buf; ++ } else { ++ val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ ++ } ++ /* Fill the next TX FIFO entry */ ++ writel(val, drv_data->base + SSP_DATAR); ++ ++ drv_data->tx_resid -= bytes; ++} ++ ++/* The last-read status value is provided; we know SSP_STATUS_TNF is set */ ++static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) ++{ ++ unsigned int count; ++ ++ /* Get the number of open slots in the FIFO; zero means all */ ++ count = FIELD_GET(SSP_STATUS_TFL, val) ? : K1_SPI_FIFO_SIZE; ++ ++ /* ++ * Limit how much we try to send at a time, to reduce the ++ * chance the other side can overrun our RX FIFO. ++ */ ++ count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); ++ do ++ k1_spi_write_word(drv_data); ++ while (--count); ++ ++ return !drv_data->tx_resid; ++} ++ ++static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) ++{ ++ struct spi_transfer *transfer = drv_data->transfer; ++ u32 bytes = drv_data->bytes; ++ u32 val; ++ ++ /* Consume the next RX FIFO entry */ ++ val = readl(drv_data->base + SSP_DATAR); ++ if (transfer->rx_buf) { ++ void *buf; ++ ++ buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); ++ ++ if (bytes == 1) ++ *(u8 *)buf = val; ++ else if (bytes == 2) ++ *(u16 *)buf = val; ++ else /* bytes == 4 */ ++ *(u32 *)buf = val; ++ } /* Otherwise null reader: discard the data */ ++ ++ drv_data->rx_resid -= bytes; ++} ++ ++/* The last-read status value is provided; we know SSP_STATUS_RNE is set */ ++static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) ++{ ++ do { ++ unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; ++ ++ /* Only read what we need */ ++ count = min(count, drv_data->rx_resid / drv_data->bytes); ++ do ++ k1_spi_read_word(drv_data); ++ while (--count); ++ ++ /* If there's no more to read, we're done */ ++ if (!drv_data->rx_resid) ++ return true; ++ ++ /* Check again in case more became available to read */ ++ val = readl(drv_data->base + SSP_STATUS); ++ if (val & SSP_STATUS_RNE) ++ writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); ++ else ++ return false; ++ } while (true); ++} ++ ++static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) ++{ ++ struct k1_spi_driver_data *drv_data = dev_id; ++ u32 status; ++ u32 top_ctrl; ++ ++ /* Get status and clear pending interrupts */ ++ status = readl(drv_data->base + SSP_STATUS); ++ writel(status, drv_data->base + SSP_STATUS); ++ ++ /* If no actionable status bits are set, this is not our interrupt */ ++ if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) ++ return IRQ_NONE; ++ ++ /* Check for any error conditions first */ ++ if (status & SSP_STATUS_ERROR) { ++ if (drv_data->transfer) ++ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; ++ goto done; ++ } ++ ++ /* ++ * For SPI, bytes are transferred in both directions equally, and ++ * RX always follows TX. Start by writing if there is anything to ++ * write, then read. Once there's no more to read, we're done. ++ */ ++ if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { ++ /* If we finish writing, disable TX interrupts */ ++ if (k1_spi_write(drv_data, status)) ++ writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, ++ drv_data->base + SSP_INT_EN); ++ } ++ ++ /* We're not done unless we've read all that was requested */ ++ if (drv_data->rx_resid) { ++ /* Read more if the FIFO is not empty */ ++ if (status & SSP_STATUS_RNE) ++ if (k1_spi_read(drv_data, status)) ++ goto done; ++ ++ return IRQ_HANDLED; ++ } ++done: ++ /* Disable the port */ ++ top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); ++ top_ctrl &= ~TOP_SSE; ++ writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); ++ ++ /* Disable all interrupts */ ++ writel(0, drv_data->base + SSP_INT_EN); ++ ++ if (drv_data->transfer) { ++ drv_data->transfer = NULL; ++ spi_finalize_current_transfer(drv_data->host); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) ++{ ++ struct spi_controller *host = drv_data->host; ++ struct dma_chan *chan; ++ ++ chan = dma_request_chan(dev, "tx"); ++ if (IS_ERR(chan)) ++ return PTR_ERR(chan); ++ host->dma_tx = chan; ++ ++ chan = dma_request_chan(dev, "rx"); ++ if (IS_ERR(chan)) { ++ dma_release_channel(host->dma_tx); ++ host->dma_tx = NULL; ++ return PTR_ERR(chan); ++ } ++ host->dma_rx = chan; ++ ++ drv_data->dma_enabled = true; ++ ++ return 0; ++} ++ ++static void k1_spi_dma_cleanup(struct device *dev, void *res) ++{ ++ struct k1_spi_driver_data **ptr = res; ++ struct k1_spi_driver_data *drv_data = *ptr; ++ struct spi_controller *host = drv_data->host; ++ ++ if (!drv_data->dma_enabled) ++ return; ++ ++ drv_data->dma_enabled = false; ++ ++ dma_release_channel(host->dma_rx); ++ host->dma_rx = NULL; ++ dma_release_channel(host->dma_tx); ++ host->dma_tx = NULL; ++} ++ ++static int ++devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) ++{ ++ struct k1_spi_driver_data **ptr; ++ int ret; ++ ++ if (!IS_ENABLED(CONFIG_MMP_PDMA)) { ++ dev_info(dev, "DMA not available; using PIO\n"); ++ return 0; ++ } ++ ++ ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); ++ if (!ptr) ++ return -ENOMEM; ++ ++ ret = k1_spi_dma_setup(drv_data, dev); ++ if (ret) { ++ devres_free(ptr); ++ return ret; ++ } ++ ++ *ptr = drv_data; ++ devres_add(dev, ptr); ++ ++ return 0; ++} ++ ++static int k1_spi_probe(struct platform_device *pdev) ++{ ++ struct k1_spi_driver_data *drv_data; ++ struct device *dev = &pdev->dev; ++ struct reset_control *reset; ++ struct spi_controller *host; ++ struct resource *iores; ++ struct clk *clk_bus; ++ int ret; ++ ++ host = devm_spi_alloc_host(dev, sizeof(*drv_data)); ++ if (!host) ++ return -ENOMEM; ++ drv_data = spi_controller_get_devdata(host); ++ drv_data->host = host; ++ platform_set_drvdata(pdev, drv_data); ++ ++ ret = devm_k1_spi_dma_setup(drv_data, dev); ++ if (ret == -EPROBE_DEFER) ++ return ret; ++ if (ret) ++ dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); ++ ++ drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, ++ &iores); ++ if (IS_ERR(drv_data->base)) ++ return dev_err_probe(dev, PTR_ERR(drv_data->base), ++ "error mapping memory\n"); ++ drv_data->base_addr = iores->start; ++ ++ clk_bus = devm_clk_get_enabled(dev, "bus"); ++ if (IS_ERR(clk_bus)) ++ return dev_err_probe(dev, PTR_ERR(clk_bus), ++ "error getting/enabling bus clock\n"); ++ drv_data->bus_rate = clk_get_rate(clk_bus); ++ ++ drv_data->clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(drv_data->clk)) ++ return dev_err_probe(dev, PTR_ERR(drv_data->clk), ++ "error getting/enabling core clock\n"); ++ ++ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(reset)) ++ return dev_err_probe(dev, PTR_ERR(reset), ++ "error getting/deasserting reset\n"); ++ ++ k1_spi_register_reset(drv_data, true); ++ ++ drv_data->irq = platform_get_irq(pdev, 0); ++ if (drv_data->irq < 0) ++ return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); ++ ++ ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, ++ IRQF_SHARED, dev_name(dev), drv_data); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "error requesting IRQ\n"); ++ ++ /* Initialize the host structure, then register it */ ++ host->dev.of_node = dev_of_node(dev); ++ host->dev.parent = dev; ++ host->num_chipselect = 1; ++ if (drv_data->dma_enabled) ++ host->dma_alignment = K1_SPI_DMA_ALIGNMENT; ++ host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; ++ host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); ++ host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; ++ host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; ++ host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; ++ host->max_dma_len = K1_SPI_MAX_DMA_LEN; ++ ++ host->setup = k1_spi_setup; ++ host->cleanup = k1_spi_cleanup; ++ host->can_dma = k1_spi_can_dma; ++ host->prepare_message = k1_spi_prepare_message; ++ host->set_cs = k1_spi_set_cs; ++ host->transfer_one = k1_spi_transfer_one; ++ host->handle_err = k1_spi_handle_err; ++ ++ ret = devm_spi_register_controller(dev, host); ++ if (ret) ++ dev_err(dev, "error registering controller\n"); ++ ++ return ret; ++} ++ ++static const struct of_device_id k1_spi_dt_ids[] = { ++ { .compatible = "spacemit,k1-spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); ++ ++static struct platform_driver k1_spi_driver = { ++ .probe = k1_spi_probe, ++ .driver = { ++ .name = "k1-spi", ++ .of_match_table = k1_spi_dt_ids, ++ }, ++}; ++module_platform_driver(k1_spi_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch deleted file mode 100644 index 6ad93704d4..0000000000 --- a/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch +++ /dev/null @@ -1,142 +0,0 @@ -From 99bf7248cb67723d749134575afb9fcb3425bccd Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:17 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add thermal sensor for - K1 SoC - -Include the Thermal Sensor node in the SpacemiT K1 dtsi -with definitions for registers, clocks, and interrupts. -Additionally, configure thermal zones for the soc, package, gpu, and -clusters to enable temperature monitoring via the thermal framework. - -Tested-by: Vincent Legoll # OrangePi-RV2 -Tested-by: Gong Shuai -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ - 1 file changed, 101 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index f8747190d2e1..2ed5cc24e505 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -339,6 +339,96 @@ osc_32k: clock-32k { - }; - }; - -+ thermal-zones { -+ soc-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 0>; -+ -+ trips { -+ soc-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ package-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 1>; -+ -+ trips { -+ package-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 2>; -+ -+ trips { -+ gpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ gpu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cluster0-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 3>; -+ -+ trips { -+ cluster0-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cluster0-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cluster1-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 4>; -+ -+ trips { -+ cluster1-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cluster1-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; -@@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { - #reset-cells = <1>; - }; - -+ thermal: thermal@d4018000 { -+ compatible = "spacemit,k1-tsensor"; -+ reg = <0x0 0xd4018000 0x0 0x100>; -+ clocks = <&syscon_apbc CLK_TSEN>, -+ <&syscon_apbc CLK_TSEN_BUS>; -+ clock-names = "core", "bus"; -+ interrupts = <61>; -+ resets = <&syscon_apbc RESET_TSEN>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - i2c6: i2c@d4018800 { - compatible = "spacemit,k1-i2c"; - reg = <0x0 0xd4018800 0x0 0x38>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0321-UPSTREAM-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux-lts-kmhv2/0321-UPSTREAM-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch new file mode 100644 index 0000000000..28f651871d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0321-UPSTREAM-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch @@ -0,0 +1,43 @@ +From aa4a2c86728cf32921d3fbe11265934fd65f4792 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 5 May 2026 09:53:34 -0400 +Subject: [RUYI PATCH] UPSTREAM: spi: spacemit: add u64 cast to NSEC_PER_SEC to + avoid 32-bit overflow + +NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * +BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures +before the result reaches the u64 nsec_per_word. + +Promote the multiplication to u64 by casting the first operand, which is +NSEC_PER_SEC. + +Fixes: efcd8b9d1111 ("spi: spacemit: introduce SpacemiT K1 SPI controller driver") +Suggested-by: Alex Elder +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202605050437.RS6mmV2b-lkp@intel.com/ +Closes: https://lore.kernel.org/oe-kbuild-all/202605050317.Tf9j487w-lkp@intel.com/ +Signed-off-by: Guodong Xu +Link: https://patch.msgid.link/20260505-spi-spacemit-k1-fix-overflow-v1-1-77564c2e4e86@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit 00cef7eb08c8b9af0978f667c77c6a30b71b7e22) +Signed-off-by: Han Gao +--- + drivers/spi/spi-spacemit-k1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c +index 99db429db0b2..215fe66d27b4 100644 +--- a/drivers/spi/spi-spacemit-k1.c ++++ b/drivers/spi/spi-spacemit-k1.c +@@ -390,7 +390,7 @@ static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, + * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; + * We do the divide last for better accuracy. + */ +- nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; ++ nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; + nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); + + /* +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch deleted file mode 100644 index 560b162481..0000000000 --- a/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 83a04d13a39350e2059289ae74da6a837187c63e Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 17:24:21 +0800 -Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after - unmapping DMA - -In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA -before calling kfree() to deallocate the memory, instead of the other -way around. - -Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-4-0ab0122fdd14@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index 359b409f8203..48c80c075fdf 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -463,12 +463,12 @@ static void emac_free_tx_resources(struct emac_priv *priv) - - emac_clean_tx_desc_ring(priv); - -- kfree(tr->tx_desc_buf); -- tr->tx_desc_buf = NULL; -- - dma_free_coherent(dev, tr->total_size, tr->desc_addr, - tr->desc_dma_addr); - tr->desc_addr = NULL; -+ -+ kfree(tr->tx_desc_buf); -+ tr->tx_desc_buf = NULL; - } - - static void emac_free_rx_resources(struct emac_priv *priv) -@@ -478,12 +478,12 @@ static void emac_free_rx_resources(struct emac_priv *priv) - - emac_clean_rx_desc_ring(priv); - -- kfree(rr->rx_desc_buf); -- rr->rx_desc_buf = NULL; -- - dma_free_coherent(dev, rr->total_size, rr->desc_addr, - rr->desc_dma_addr); - rr->desc_addr = NULL; -+ -+ kfree(rr->rx_desc_buf); -+ rr->rx_desc_buf = NULL; - } - - static int emac_tx_clean_desc(struct emac_priv *priv) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0322-UPSTREAM-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux-lts-kmhv2/0322-UPSTREAM-riscv-dts-spacemit-define-a-SPI-controller-.patch new file mode 100644 index 0000000000..c4fb36efd0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0322-UPSTREAM-riscv-dts-spacemit-define-a-SPI-controller-.patch @@ -0,0 +1,116 @@ +From 2e4e61ca226d44b5ce1e7e2f945827d19bd181ce Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:53 -0400 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define a SPI controller + node + +Define a node for the fourth SoC SPI controller (number 3) on the +SpacemiT K1 SoC. + +Enable it on the Banana Pi BPI-F3 board, which exposes this feature +via its GPIO block: + GPIO PIN 19: MOSI + GPIO PIN 21: MISO + GPIO PIN 23: SCLK + GPIO PIN 24: SS (inverted) + +Define pincontrol configurations for the pins as used on that board. + +(This was tested using a GigaDevice GD25Q64E SPI NOR chip.) + +Reviewed-by: Yixun Lan +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit c580774185426ea316396b1dc3f1737a3ad3800a) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ + 3 files changed, 42 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 5790d927b93d..9429189354d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -14,6 +14,7 @@ aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; ++ spi3 = &spi3; + i2c2 = &i2c2; + i2c8 = &i2c8; + }; +@@ -335,6 +336,12 @@ &pcie2 { + status = "okay"; + }; + ++&spi3 { ++ pinctrl-0 = <&ssp3_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index b13dcb10f4d6..34d88334e95e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -570,4 +570,24 @@ pwm14-1-pins { + drive-strength = <32>; + }; + }; ++ ++ ssp3_0_cfg: ssp3-0-cfg { ++ ssp3-0-pins { ++ pinmux = , /* SCLK */ ++ , /* MOSI */ ++ ; /* MISO */ ++ ++ bias-disable; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ ssp3-0-frm-pins { ++ pinmux = ; /* FRM (frame) */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index f0bad6855c97..f8747190d2e1 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -983,6 +983,21 @@ qspi: spi@d420c000 { + status = "disabled"; + }; + ++ spi3: spi@d401c000 { ++ compatible = "spacemit,k1-spi"; ++ reg = <0x0 0xd401c000 0x0 0x30>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_SSP3>, ++ <&syscon_apbc CLK_SSP3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_SSP3>; ++ interrupts = <55>; ++ dmas = <&pdma 20>, <&pdma 19>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + /* sec_uart1: 0xf0612000, not available from Linux */ + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch b/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch deleted file mode 100644 index 5a383caca0..0000000000 --- a/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 0615284b82b82ee1dc7ccbc7146e31afa8bbbc9f Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:45 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Extract helper mark_new_valid_map() - -In preparation of a future patch using the same mechanism for -non-vmalloc addresses, extract the mark_new_valid_map() helper from -flush_cache_vmap(). - -No functional change intended. - -Cc: stable@vger.kernel.org -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-1-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 25 ++++++++++++++----------- - 1 file changed, 14 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index 0092513c3376..b1a2ac665792 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -43,20 +43,23 @@ do { \ - #ifdef CONFIG_64BIT - extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; - extern char _end[]; -+static inline void mark_new_valid_map(void) -+{ -+ int i; -+ -+ /* -+ * We don't care if concurrently a cpu resets this value since -+ * the only place this can happen is in handle_exception() where -+ * an sfence.vma is emitted. -+ */ -+ for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -+ new_vmalloc[i] = -1ULL; -+} - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) - { -- if (is_vmalloc_or_module_addr((void *)start)) { -- int i; -- -- /* -- * We don't care if concurrently a cpu resets this value since -- * the only place this can happen is in handle_exception() where -- * an sfence.vma is emitted. -- */ -- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -- new_vmalloc[i] = -1ULL; -- } -+ if (is_vmalloc_or_module_addr((void *)start)) -+ mark_new_valid_map(); - } - #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0323-UPSTREAM-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux-lts-kmhv2/0323-UPSTREAM-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch new file mode 100644 index 0000000000..2a22e408af --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0323-UPSTREAM-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch @@ -0,0 +1,106 @@ +From a1ad9185aadd589ed707c4b1e557eb8013447fde Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: thermal: Add SpacemiT K1 thermal + sensor + +Document the SpacemiT K1 Thermal Sensor, which supports +monitoring temperatures for five zones: soc, package, gpu, cluster0, +and cluster1. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Shuwei Wu +Signed-off-by: Daniel Lezcano +Link: https://patch.msgid.link/20260427-k1-thermal-v5-1-df39187480ed@mailbox.org +(cherry picked from commit 0309075e080306ad2e3b3148a3495b10dd252ef2) +Signed-off-by: Han Gao +--- + .../bindings/thermal/spacemit,k1-tsensor.yaml | 76 +++++++++++++++++++ + 1 file changed, 76 insertions(+) + create mode 100644 Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml + +diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml +new file mode 100644 +index 000000000000..6dad76a7dd36 +--- /dev/null ++++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml +@@ -0,0 +1,76 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 Thermal Sensor ++ ++description: ++ The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC ++ using multiple internal sensors (e.g., soc, package, gpu, clusters). ++ ++maintainers: ++ - Shuwei Wu ++ ++$ref: thermal-sensor.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k1-tsensor ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Core clock for thermal sensor ++ - description: Bus clock for thermal sensor ++ ++ clock-names: ++ items: ++ - const: core ++ - const: bus ++ ++ interrupts: ++ maxItems: 1 ++ ++ resets: ++ items: ++ - description: Reset for the thermal sensor ++ ++ "#thermal-sensor-cells": ++ const: 1 ++ description: ++ The first cell indicates the sensor ID. ++ 0 = soc ++ 1 = package ++ 2 = gpu ++ 3 = cluster0 ++ 4 = cluster1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - resets ++ - "#thermal-sensor-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ thermal@d4018000 { ++ compatible = "spacemit,k1-tsensor"; ++ reg = <0xd4018000 0x100>; ++ clocks = <&syscon_apbc CLK_TSEN>, ++ <&syscon_apbc CLK_TSEN_BUS>; ++ clock-names = "core", "bus"; ++ interrupts = <61>; ++ resets = <&syscon_apbc RESET_TSEN>; ++ #thermal-sensor-cells = <1>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch b/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch deleted file mode 100644 index 24cfe28e1b..0000000000 --- a/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch +++ /dev/null @@ -1,80 +0,0 @@ -From a6ee02e2ad7a759a5906206b87b7525c1ac580e4 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:46 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: kfence: Call mark_new_valid_map() for - kfence_unprotect() - -In kfence_protect_page(), which kfence_unprotect() calls, we cannot send -IPIs to other CPUs to ask them to flush TLB. This may lead to those CPUs -spuriously faulting on a recently allocated kfence object despite it -being valid, leading to false positive use-after-free reports. - -Fix this by calling mark_new_valid_map() so that the page fault handling -code path notices the spurious fault and flushes TLB then retries the -access. - -Update the comment in handle_exception to indicate that -new_valid_map_cpus_check also handles kfence_unprotect() spurious -faults. - -Note that kfence_protect() has the same stale TLB entries problem, but -that leads to false negatives, which is fine with kfence. - -Cc: stable@vger.kernel.org -Reported-by: Yanko Kaneti -Fixes: b3431a8bb336 ("riscv: Fix IPIs usage in kfence_protect_page()") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-2-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/kfence.h | 7 +++++-- - arch/riscv/kernel/entry.S | 6 ++++-- - 2 files changed, 9 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/include/asm/kfence.h b/arch/riscv/include/asm/kfence.h -index d08bf7fb3aee..29cb3a6ee113 100644 ---- a/arch/riscv/include/asm/kfence.h -+++ b/arch/riscv/include/asm/kfence.h -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - - static inline bool arch_kfence_init_pool(void) -@@ -17,10 +18,12 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect) - { - pte_t *pte = virt_to_kpte(addr); - -- if (protect) -+ if (protect) { - set_pte(pte, __pte(pte_val(ptep_get(pte)) & ~_PAGE_PRESENT)); -- else -+ } else { - set_pte(pte, __pte(pte_val(ptep_get(pte)) | _PAGE_PRESENT)); -+ mark_new_valid_map(); -+ } - - preempt_disable(); - local_flush_tlb_kernel_range(addr, addr + PAGE_SIZE); -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index 9b9dec6893b8..e7bd03a9ced5 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -107,8 +107,10 @@ SYM_CODE_START(handle_exception) - - #ifdef CONFIG_64BIT - /* -- * The RISC-V kernel does not eagerly emit a sfence.vma after each -- * new vmalloc mapping, which may result in exceptions: -+ * The RISC-V kernel does not flush TLBs on all CPUS after each new -+ * vmalloc mapping or kfence_unprotect(), which may result in -+ * exceptions: -+ * - * - if the uarch caches invalid entries, the new mapping would not be - * observed by the page table walker and an invalidation is needed. - * - if the uarch does not cache invalid entries, a reordered access --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0324-UPSTREAM-thermal-drivers-spacemit-k1-Add-thermal-sen.patch b/SPECS/linux-lts-kmhv2/0324-UPSTREAM-thermal-drivers-spacemit-k1-Add-thermal-sen.patch new file mode 100644 index 0000000000..2ace22f808 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0324-UPSTREAM-thermal-drivers-spacemit-k1-Add-thermal-sen.patch @@ -0,0 +1,382 @@ +From 71b21b20b4bdeada625862067165bb41c7e15671 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: thermal/drivers/spacemit/k1: Add thermal + sensor support + +The thermal sensor on K1 supports monitoring five temperature zones. +The driver registers these sensors with the thermal framework +and supports standard operations: +- Reading temperature (millidegree Celsius) +- Setting high/low thresholds for interrupts + +Signed-off-by: Shuwei Wu +Signed-off-by: Daniel Lezcano +Reviewed-by: Anand Moon +Reviewed-by: Troy Mitchell +Reviewed-by: Yao Zi +Tested-by: Anand Moon +Tested-by: Vincent Legoll # OrangePi-RV2 +Tested-by: Gong Shuai +Link: https://patch.msgid.link/20260427-k1-thermal-v5-2-df39187480ed@mailbox.org +(cherry picked from commit 296a977f2bac45759a427dc57a21edb628f5c86c) +Signed-off-by: Han Gao +--- + drivers/thermal/Kconfig | 2 + + drivers/thermal/Makefile | 1 + + drivers/thermal/spacemit/Kconfig | 19 ++ + drivers/thermal/spacemit/Makefile | 3 + + drivers/thermal/spacemit/k1_tsensor.c | 280 ++++++++++++++++++++++++++ + 5 files changed, 305 insertions(+) + create mode 100644 drivers/thermal/spacemit/Kconfig + create mode 100644 drivers/thermal/spacemit/Makefile + create mode 100644 drivers/thermal/spacemit/k1_tsensor.c + +diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig +index a09c188b9ad1..a96e2d045d97 100644 +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -462,6 +462,8 @@ endmenu + + source "drivers/thermal/renesas/Kconfig" + ++source "drivers/thermal/spacemit/Kconfig" ++ + source "drivers/thermal/tegra/Kconfig" + + config GENERIC_ADC_THERMAL +diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile +index d7718978db24..64cbed51d4fb 100644 +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -64,6 +64,7 @@ obj-y += mediatek/ + obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o + obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o + obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o ++obj-y += spacemit/ + obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o + obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o + obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o +diff --git a/drivers/thermal/spacemit/Kconfig b/drivers/thermal/spacemit/Kconfig +new file mode 100644 +index 000000000000..de7b5ece5af2 +--- /dev/null ++++ b/drivers/thermal/spacemit/Kconfig +@@ -0,0 +1,19 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++menu "SpacemiT thermal drivers" ++depends on ARCH_SPACEMIT || COMPILE_TEST ++ ++config SPACEMIT_K1_TSENSOR ++ tristate "SpacemiT K1 thermal sensor driver" ++ depends on THERMAL_OF ++ help ++ This driver provides support for the thermal sensor ++ integrated in the SpacemiT K1 SoC. ++ ++ The thermal sensor monitors temperatures for five thermal zones: ++ soc, package, gpu, cluster0, and cluster1. It supports reporting ++ temperature values and handling high/low threshold interrupts. ++ ++ Say Y here if you want to enable thermal monitoring on SpacemiT K1. ++ If compiled as a module, it will be called k1_tsensor. ++ ++endmenu +diff --git a/drivers/thermal/spacemit/Makefile b/drivers/thermal/spacemit/Makefile +new file mode 100644 +index 000000000000..82b30741e4ec +--- /dev/null ++++ b/drivers/thermal/spacemit/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_SPACEMIT_K1_TSENSOR) += k1_tsensor.o +diff --git a/drivers/thermal/spacemit/k1_tsensor.c b/drivers/thermal/spacemit/k1_tsensor.c +new file mode 100644 +index 000000000000..79222d233129 +--- /dev/null ++++ b/drivers/thermal/spacemit/k1_tsensor.c +@@ -0,0 +1,280 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Thermal sensor driver for SpacemiT K1 SoC ++ * ++ * Copyright (C) 2026 Shuwei Wu ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../thermal_hwmon.h" ++ ++#define K1_TSENSOR_PCTRL_REG 0x00 ++#define K1_TSENSOR_PCTRL_ENABLE BIT(0) ++#define K1_TSENSOR_PCTRL_TEMP_MODE BIT(3) ++#define K1_TSENSOR_PCTRL_RAW_SEL BIT(7) ++ ++#define K1_TSENSOR_PCTRL_CTUNE GENMASK(11, 8) ++#define K1_TSENSOR_PCTRL_SW_CTRL GENMASK(21, 18) ++#define K1_TSENSOR_PCTRL_HW_AUTO_MODE BIT(23) ++ ++#define K1_TSENSOR_EN_REG 0x08 ++#define K1_TSENSOR_EN_ALL GENMASK(MAX_SENSOR_NUMBER - 1, 0) ++ ++#define K1_TSENSOR_TIME_REG 0x0C ++#define K1_TSENSOR_TIME_WAIT_REF_CNT GENMASK(3, 0) ++#define K1_TSENSOR_TIME_ADC_CNT_RST GENMASK(7, 4) ++#define K1_TSENSOR_TIME_FILTER_PERIOD GENMASK(21, 20) ++#define K1_TSENSOR_TIME_MASK GENMASK(23, 0) ++ ++#define K1_TSENSOR_INT_CLR_REG 0x10 ++#define K1_TSENSOR_INT_EN_REG 0x14 ++#define K1_TSENSOR_INT_STA_REG 0x18 ++ ++#define K1_TSENSOR_INT_EN_MASK BIT(0) ++#define K1_TSENSOR_INT_MASK(x) (GENMASK(2, 1) << ((x) * 2)) ++ ++#define K1_TSENSOR_DATA_BASE_REG 0x20 ++#define K1_TSENSOR_DATA_REG(x) (K1_TSENSOR_DATA_BASE_REG + ((x) / 2) * 4) ++#define K1_TSENSOR_DATA_LOW_MASK GENMASK(15, 0) ++#define K1_TSENSOR_DATA_HIGH_MASK GENMASK(31, 16) ++ ++#define K1_TSENSOR_THRSH_BASE_REG 0x40 ++#define K1_TSENSOR_THRSH_REG(x) (K1_TSENSOR_THRSH_BASE_REG + ((x) * 4)) ++#define K1_TSENSOR_THRSH_LOW_MASK GENMASK(15, 0) ++#define K1_TSENSOR_THRSH_HIGH_MASK GENMASK(31, 16) ++ ++#define MAX_SENSOR_NUMBER 5 ++ ++/* Hardware offset value required for temperature calculation */ ++#define TEMPERATURE_OFFSET 278 ++ ++struct k1_tsensor_channel { ++ struct k1_tsensor *ts; ++ struct thermal_zone_device *tzd; ++ int id; ++}; ++ ++struct k1_tsensor { ++ void __iomem *base; ++ struct k1_tsensor_channel ch[MAX_SENSOR_NUMBER]; ++}; ++ ++static void k1_tsensor_init(struct k1_tsensor *ts) ++{ ++ u32 val; ++ ++ /* Disable all the interrupts */ ++ writel(0xffffffff, ts->base + K1_TSENSOR_INT_EN_REG); ++ ++ /* Configure ADC sampling time and filter period */ ++ val = readl(ts->base + K1_TSENSOR_TIME_REG); ++ val &= ~K1_TSENSOR_TIME_MASK; ++ val |= K1_TSENSOR_TIME_FILTER_PERIOD | ++ K1_TSENSOR_TIME_ADC_CNT_RST | ++ K1_TSENSOR_TIME_WAIT_REF_CNT; ++ writel(val, ts->base + K1_TSENSOR_TIME_REG); ++ ++ /* ++ * Enable all sensors' auto mode, enable dither control, ++ * consecutive mode, and power up sensor. ++ */ ++ val = readl(ts->base + K1_TSENSOR_PCTRL_REG); ++ val &= ~K1_TSENSOR_PCTRL_SW_CTRL; ++ val &= ~K1_TSENSOR_PCTRL_CTUNE; ++ val |= K1_TSENSOR_PCTRL_RAW_SEL | ++ K1_TSENSOR_PCTRL_TEMP_MODE | ++ K1_TSENSOR_PCTRL_HW_AUTO_MODE | ++ K1_TSENSOR_PCTRL_ENABLE; ++ writel(val, ts->base + K1_TSENSOR_PCTRL_REG); ++ ++ /* Enable each sensor */ ++ val = readl(ts->base + K1_TSENSOR_EN_REG); ++ val |= K1_TSENSOR_EN_ALL; ++ writel(val, ts->base + K1_TSENSOR_EN_REG); ++} ++ ++static void k1_tsensor_enable_irq(struct k1_tsensor_channel *ch) ++{ ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ val = readl(ts->base + K1_TSENSOR_INT_CLR_REG); ++ val |= K1_TSENSOR_INT_MASK(ch->id); ++ writel(val, ts->base + K1_TSENSOR_INT_CLR_REG); ++ ++ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); ++ val &= ~K1_TSENSOR_INT_MASK(ch->id); ++ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); ++ ++ /* Enable thermal interrupt */ ++ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); ++ val |= K1_TSENSOR_INT_EN_MASK; ++ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); ++} ++ ++/* ++ * The conversion formula used is: ++ * T(m°C) = (((raw_value & mask) >> shift) - TEMPERATURE_OFFSET) * 1000 ++ */ ++static int k1_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) ++{ ++ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ val = readl(ts->base + K1_TSENSOR_DATA_REG(ch->id)); ++ if (ch->id % 2) ++ *temp = FIELD_GET(K1_TSENSOR_DATA_HIGH_MASK, val); ++ else ++ *temp = FIELD_GET(K1_TSENSOR_DATA_LOW_MASK, val); ++ ++ *temp -= TEMPERATURE_OFFSET; ++ *temp *= 1000; ++ ++ return 0; ++} ++ ++/* ++ * For each sensor, the hardware threshold register is 32 bits: ++ * - Lower 16 bits [15:0] configure the low threshold temperature. ++ * - Upper 16 bits [31:16] configure the high threshold temperature. ++ */ ++static int k1_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) ++{ ++ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ if (low >= high) ++ return -EINVAL; ++ ++ low = clamp_val(low / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, ++ FIELD_MAX(K1_TSENSOR_THRSH_LOW_MASK)); ++ high = clamp_val(high / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, ++ FIELD_MAX(K1_TSENSOR_THRSH_HIGH_MASK)); ++ ++ val = readl(ts->base + K1_TSENSOR_THRSH_REG(ch->id)); ++ ++ val &= ~(K1_TSENSOR_THRSH_LOW_MASK | K1_TSENSOR_THRSH_HIGH_MASK); ++ val |= FIELD_PREP(K1_TSENSOR_THRSH_LOW_MASK, low); ++ val |= FIELD_PREP(K1_TSENSOR_THRSH_HIGH_MASK, high); ++ ++ writel(val, ts->base + K1_TSENSOR_THRSH_REG(ch->id)); ++ ++ return 0; ++} ++ ++static const struct thermal_zone_device_ops k1_tsensor_ops = { ++ .get_temp = k1_tsensor_get_temp, ++ .set_trips = k1_tsensor_set_trips, ++}; ++ ++static irqreturn_t k1_tsensor_irq_thread(int irq, void *data) ++{ ++ struct k1_tsensor *ts = (struct k1_tsensor *)data; ++ int mask, status, i; ++ ++ status = readl(ts->base + K1_TSENSOR_INT_STA_REG); ++ ++ for (i = 0; i < MAX_SENSOR_NUMBER; i++) { ++ if (status & K1_TSENSOR_INT_MASK(i)) { ++ mask = readl(ts->base + K1_TSENSOR_INT_CLR_REG); ++ mask |= K1_TSENSOR_INT_MASK(i); ++ writel(mask, ts->base + K1_TSENSOR_INT_CLR_REG); ++ thermal_zone_device_update(ts->ch[i].tzd, THERMAL_EVENT_UNSPECIFIED); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int k1_tsensor_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct k1_tsensor *ts; ++ struct reset_control *reset; ++ struct clk *clk; ++ int i, irq, ret; ++ ++ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); ++ if (!ts) ++ return -ENOMEM; ++ ++ ts->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ts->base)) ++ return dev_err_probe(dev, PTR_ERR(ts->base), "Failed to get reg\n"); ++ ++ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(reset)) ++ return dev_err_probe(dev, PTR_ERR(reset), "Failed to get/deassert reset control\n"); ++ ++ clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get core clock\n"); ++ ++ clk = devm_clk_get_enabled(dev, "bus"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get bus clock\n"); ++ ++ k1_tsensor_init(ts); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = devm_request_threaded_irq(dev, irq, NULL, ++ k1_tsensor_irq_thread, ++ IRQF_ONESHOT, "k1_tsensor", ts); ++ if (ret < 0) ++ return ret; ++ ++ for (i = 0; i < MAX_SENSOR_NUMBER; ++i) { ++ ts->ch[i].id = i; ++ ts->ch[i].ts = ts; ++ ts->ch[i].tzd = devm_thermal_of_zone_register(dev, i, ts->ch + i, &k1_tsensor_ops); ++ if (IS_ERR(ts->ch[i].tzd)) ++ return PTR_ERR(ts->ch[i].tzd); ++ ++ /* Attach sysfs hwmon attributes for userspace monitoring */ ++ ret = devm_thermal_add_hwmon_sysfs(dev, ts->ch[i].tzd); ++ if (ret) ++ dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); ++ ++ k1_tsensor_enable_irq(ts->ch + i); ++ } ++ ++ platform_set_drvdata(pdev, ts); ++ ++ return 0; ++} ++ ++static const struct of_device_id k1_tsensor_dt_ids[] = { ++ { .compatible = "spacemit,k1-tsensor" }, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, k1_tsensor_dt_ids); ++ ++static struct platform_driver k1_tsensor_driver = { ++ .driver = { ++ .name = "k1_tsensor", ++ .of_match_table = k1_tsensor_dt_ids, ++ }, ++ .probe = k1_tsensor_probe, ++}; ++module_platform_driver(k1_tsensor_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 Thermal Sensor Driver"); ++MODULE_AUTHOR("Shuwei Wu "); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch deleted file mode 100644 index a75c6a24b4..0000000000 --- a/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch +++ /dev/null @@ -1,162 +0,0 @@ -From 0ff2687ed24d31a6e1dcee2c1fd287112688dabe Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:47 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Rename new_vmalloc into - new_valid_map_cpus - -Since this mechanism is now used for the kfence pool, which comes from -the linear mapping and not vmalloc, rename new_vmalloc into -new_valid_map_cpus to avoid misleading readers. - -No functional change intended. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-3-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 6 ++--- - arch/riscv/kernel/entry.S | 38 ++++++++++++++--------------- - arch/riscv/mm/init.c | 2 +- - 3 files changed, 23 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index b1a2ac665792..8c7a0ef2635a 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -41,7 +41,7 @@ do { \ - } while (0) - - #ifdef CONFIG_64BIT --extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; -+extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; - extern char _end[]; - static inline void mark_new_valid_map(void) - { -@@ -52,8 +52,8 @@ static inline void mark_new_valid_map(void) - * the only place this can happen is in handle_exception() where - * an sfence.vma is emitted. - */ -- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -- new_vmalloc[i] = -1ULL; -+ for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) -+ new_valid_map_cpus[i] = -1ULL; - } - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index e7bd03a9ced5..4f88d3353b00 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -20,44 +20,44 @@ - - .section .irqentry.text, "ax" - --.macro new_vmalloc_check -+.macro new_valid_map_cpus_check - REG_S a0, TASK_TI_A0(tp) - csrr a0, CSR_CAUSE - /* Exclude IRQs */ -- blt a0, zero, .Lnew_vmalloc_restore_context_a0 -+ blt a0, zero, .Lnew_valid_map_cpus_restore_context_a0 - - REG_S a1, TASK_TI_A1(tp) -- /* Only check new_vmalloc if we are in page/protection fault */ -+ /* Only check new_valid_map_cpus if we are in page/protection fault */ - li a1, EXC_LOAD_PAGE_FAULT -- beq a0, a1, .Lnew_vmalloc_kernel_address -+ beq a0, a1, .Lnew_valid_map_cpus_kernel_address - li a1, EXC_STORE_PAGE_FAULT -- beq a0, a1, .Lnew_vmalloc_kernel_address -+ beq a0, a1, .Lnew_valid_map_cpus_kernel_address - li a1, EXC_INST_PAGE_FAULT -- bne a0, a1, .Lnew_vmalloc_restore_context_a1 -+ bne a0, a1, .Lnew_valid_map_cpus_restore_context_a1 - --.Lnew_vmalloc_kernel_address: -+.Lnew_valid_map_cpus_kernel_address: - /* Is it a kernel address? */ - csrr a0, CSR_TVAL -- bge a0, zero, .Lnew_vmalloc_restore_context_a1 -+ bge a0, zero, .Lnew_valid_map_cpus_restore_context_a1 - - /* Check if a new vmalloc mapping appeared that could explain the trap */ - REG_S a2, TASK_TI_A2(tp) - /* - * Computes: -- * a0 = &new_vmalloc[BIT_WORD(cpu)] -+ * a0 = &new_valid_map_cpus[BIT_WORD(cpu)] - * a1 = BIT_MASK(cpu) - */ - lw a2, TASK_TI_CPU(tp) - /* -- * Compute the new_vmalloc element position: -+ * Compute the new_valid_map_cpus element position: - * (cpu / 64) * 8 = (cpu >> 6) << 3 - */ - srli a1, a2, 6 - slli a1, a1, 3 -- la a0, new_vmalloc -+ la a0, new_valid_map_cpus - add a0, a0, a1 - /* -- * Compute the bit position in the new_vmalloc element: -+ * Compute the bit position in the new_valid_map_cpus element: - * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6 - * = cpu - ((cpu >> 6) << 3) << 3 - */ -@@ -67,12 +67,12 @@ - li a2, 1 - sll a1, a2, a1 - -- /* Check the value of new_vmalloc for this cpu */ -+ /* Check the value of new_valid_map_cpus for this cpu */ - REG_L a2, 0(a0) - and a2, a2, a1 -- beq a2, zero, .Lnew_vmalloc_restore_context -+ beq a2, zero, .Lnew_valid_map_cpus_restore_context - -- /* Atomically reset the current cpu bit in new_vmalloc */ -+ /* Atomically reset the current cpu bit in new_valid_map_cpus */ - amoxor.d a0, a1, (a0) - - /* Only emit a sfence.vma if the uarch caches invalid entries */ -@@ -84,11 +84,11 @@ - csrw CSR_SCRATCH, x0 - sret - --.Lnew_vmalloc_restore_context: -+.Lnew_valid_map_cpus_restore_context: - REG_L a2, TASK_TI_A2(tp) --.Lnew_vmalloc_restore_context_a1: -+.Lnew_valid_map_cpus_restore_context_a1: - REG_L a1, TASK_TI_A1(tp) --.Lnew_vmalloc_restore_context_a0: -+.Lnew_valid_map_cpus_restore_context_a0: - REG_L a0, TASK_TI_A0(tp) - .endm - -@@ -117,7 +117,7 @@ SYM_CODE_START(handle_exception) - * could "miss" the new mapping and traps: in that case, we only need - * to retry the access, no sfence.vma is required. - */ -- new_vmalloc_check -+ new_valid_map_cpus_check - #endif - - REG_S sp, TASK_TI_KERNEL_SP(tp) -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 8f4e7e505906..750d3356683a 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -37,7 +37,7 @@ - - #include "../kernel/head.h" - --u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; -+u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; - - struct kernel_mapping kernel_map __ro_after_init; - EXPORT_SYMBOL(kernel_map); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0325-UPSTREAM-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux-lts-kmhv2/0325-UPSTREAM-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch new file mode 100644 index 0000000000..43d7a4322d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0325-UPSTREAM-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch @@ -0,0 +1,145 @@ +From 0a392c75073727b0d88a59c8552d6d1b8cc59aea Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add thermal sensor for + K1 SoC + +Include the Thermal Sensor node in the SpacemiT K1 dtsi +with definitions for registers, clocks, and interrupts. +Additionally, configure thermal zones for the soc, package, gpu, and +clusters to enable temperature monitoring via the thermal framework. + +Tested-by: Vincent Legoll # OrangePi-RV2 +Tested-by: Gong Shuai +Signed-off-by: Shuwei Wu +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org +Signed-off-by: Yixun Lan +(cherry picked from commit 247c77ff5806bcd6a5ff802718de1f0aa2bcba6c) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ + 1 file changed, 101 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index f8747190d2e1..2ed5cc24e505 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -339,6 +339,96 @@ osc_32k: clock-32k { + }; + }; + ++ thermal-zones { ++ soc-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 0>; ++ ++ trips { ++ soc-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ package-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 1>; ++ ++ trips { ++ package-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 2>; ++ ++ trips { ++ gpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ gpu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cluster0-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 3>; ++ ++ trips { ++ cluster0-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cluster0-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cluster1-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 4>; ++ ++ trips { ++ cluster1-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cluster1-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; +@@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { + #reset-cells = <1>; + }; + ++ thermal: thermal@d4018000 { ++ compatible = "spacemit,k1-tsensor"; ++ reg = <0x0 0xd4018000 0x0 0x100>; ++ clocks = <&syscon_apbc CLK_TSEN>, ++ <&syscon_apbc CLK_TSEN_BUS>; ++ clock-names = "core", "bus"; ++ interrupts = <61>; ++ resets = <&syscon_apbc RESET_TSEN>; ++ #thermal-sensor-cells = <1>; ++ }; ++ + i2c6: i2c@d4018800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4018800 0x0 0x38>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch deleted file mode 100644 index 6e8c075234..0000000000 --- a/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch +++ /dev/null @@ -1,61 +0,0 @@ -From e7c9b52a88814781a9b973a8bc5d43cb3655f869 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:48 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Use the bitmap API for - new_valid_map_cpus - -The bitmap was defined with incorrect size. Fix it by using the proper -bitmap API in C code. The corresponding assembly code is still okay and -remains unchanged. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-4-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 8 +++----- - arch/riscv/mm/init.c | 2 +- - 2 files changed, 4 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index 8c7a0ef2635a..8cfe59483a8f 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -41,19 +41,17 @@ do { \ - } while (0) - - #ifdef CONFIG_64BIT --extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; -+/* This is accessed in assembly code. cpumask_var_t would be too complex. */ -+extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); - extern char _end[]; - static inline void mark_new_valid_map(void) - { -- int i; -- - /* - * We don't care if concurrently a cpu resets this value since - * the only place this can happen is in handle_exception() where - * an sfence.vma is emitted. - */ -- for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) -- new_valid_map_cpus[i] = -1ULL; -+ bitmap_fill(new_valid_map_cpus, NR_CPUS); - } - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 750d3356683a..6533cc17825a 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -37,7 +37,7 @@ - - #include "../kernel/head.h" - --u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; -+DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); - - struct kernel_mapping kernel_map __ro_after_init; - EXPORT_SYMBOL(kernel_map); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0326-UPSTREAM-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux-lts-kmhv2/0326-UPSTREAM-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch new file mode 100644 index 0000000000..aba60f1573 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0326-UPSTREAM-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch @@ -0,0 +1,164 @@ +From e8af905f2845703432550c425161b23d3eef9770 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Rename new_vmalloc into + new_valid_map_cpus + +Since this mechanism is now used for the kfence pool, which comes from +the linear mapping and not vmalloc, rename new_vmalloc into +new_valid_map_cpus to avoid misleading readers. + +No functional change intended. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-3-f80d8354d79d@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit a50940adfb8f390337d6ef9afe15b66ec498aceb) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 6 ++--- + arch/riscv/kernel/entry.S | 38 ++++++++++++++--------------- + arch/riscv/mm/init.c | 2 +- + 3 files changed, 23 insertions(+), 23 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index b1a2ac665792..8c7a0ef2635a 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -41,7 +41,7 @@ do { \ + } while (0) + + #ifdef CONFIG_64BIT +-extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; ++extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; + extern char _end[]; + static inline void mark_new_valid_map(void) + { +@@ -52,8 +52,8 @@ static inline void mark_new_valid_map(void) + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. + */ +- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) +- new_vmalloc[i] = -1ULL; ++ for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) ++ new_valid_map_cpus[i] = -1ULL; + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index e7bd03a9ced5..4f88d3353b00 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -20,44 +20,44 @@ + + .section .irqentry.text, "ax" + +-.macro new_vmalloc_check ++.macro new_valid_map_cpus_check + REG_S a0, TASK_TI_A0(tp) + csrr a0, CSR_CAUSE + /* Exclude IRQs */ +- blt a0, zero, .Lnew_vmalloc_restore_context_a0 ++ blt a0, zero, .Lnew_valid_map_cpus_restore_context_a0 + + REG_S a1, TASK_TI_A1(tp) +- /* Only check new_vmalloc if we are in page/protection fault */ ++ /* Only check new_valid_map_cpus if we are in page/protection fault */ + li a1, EXC_LOAD_PAGE_FAULT +- beq a0, a1, .Lnew_vmalloc_kernel_address ++ beq a0, a1, .Lnew_valid_map_cpus_kernel_address + li a1, EXC_STORE_PAGE_FAULT +- beq a0, a1, .Lnew_vmalloc_kernel_address ++ beq a0, a1, .Lnew_valid_map_cpus_kernel_address + li a1, EXC_INST_PAGE_FAULT +- bne a0, a1, .Lnew_vmalloc_restore_context_a1 ++ bne a0, a1, .Lnew_valid_map_cpus_restore_context_a1 + +-.Lnew_vmalloc_kernel_address: ++.Lnew_valid_map_cpus_kernel_address: + /* Is it a kernel address? */ + csrr a0, CSR_TVAL +- bge a0, zero, .Lnew_vmalloc_restore_context_a1 ++ bge a0, zero, .Lnew_valid_map_cpus_restore_context_a1 + + /* Check if a new vmalloc mapping appeared that could explain the trap */ + REG_S a2, TASK_TI_A2(tp) + /* + * Computes: +- * a0 = &new_vmalloc[BIT_WORD(cpu)] ++ * a0 = &new_valid_map_cpus[BIT_WORD(cpu)] + * a1 = BIT_MASK(cpu) + */ + lw a2, TASK_TI_CPU(tp) + /* +- * Compute the new_vmalloc element position: ++ * Compute the new_valid_map_cpus element position: + * (cpu / 64) * 8 = (cpu >> 6) << 3 + */ + srli a1, a2, 6 + slli a1, a1, 3 +- la a0, new_vmalloc ++ la a0, new_valid_map_cpus + add a0, a0, a1 + /* +- * Compute the bit position in the new_vmalloc element: ++ * Compute the bit position in the new_valid_map_cpus element: + * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6 + * = cpu - ((cpu >> 6) << 3) << 3 + */ +@@ -67,12 +67,12 @@ + li a2, 1 + sll a1, a2, a1 + +- /* Check the value of new_vmalloc for this cpu */ ++ /* Check the value of new_valid_map_cpus for this cpu */ + REG_L a2, 0(a0) + and a2, a2, a1 +- beq a2, zero, .Lnew_vmalloc_restore_context ++ beq a2, zero, .Lnew_valid_map_cpus_restore_context + +- /* Atomically reset the current cpu bit in new_vmalloc */ ++ /* Atomically reset the current cpu bit in new_valid_map_cpus */ + amoxor.d a0, a1, (a0) + + /* Only emit a sfence.vma if the uarch caches invalid entries */ +@@ -84,11 +84,11 @@ + csrw CSR_SCRATCH, x0 + sret + +-.Lnew_vmalloc_restore_context: ++.Lnew_valid_map_cpus_restore_context: + REG_L a2, TASK_TI_A2(tp) +-.Lnew_vmalloc_restore_context_a1: ++.Lnew_valid_map_cpus_restore_context_a1: + REG_L a1, TASK_TI_A1(tp) +-.Lnew_vmalloc_restore_context_a0: ++.Lnew_valid_map_cpus_restore_context_a0: + REG_L a0, TASK_TI_A0(tp) + .endm + +@@ -117,7 +117,7 @@ SYM_CODE_START(handle_exception) + * could "miss" the new mapping and traps: in that case, we only need + * to retry the access, no sfence.vma is required. + */ +- new_vmalloc_check ++ new_valid_map_cpus_check + #endif + + REG_S sp, TASK_TI_KERNEL_SP(tp) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 8f4e7e505906..750d3356683a 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,7 @@ + + #include "../kernel/head.h" + +-u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; ++u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch deleted file mode 100644 index 9d00d9a51f..0000000000 --- a/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0236a57f077395bd67012bf4e9d33ba23ecdedd5 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:49 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Unconditionally sfence.vma for - spurious fault - -Svvptc does not guarantee that it's safe to just return here. Since we -have already cleared our bit, if, theoretically, the bounded timeframe -for the accessed page to become valid still hasn't happened after sret, -we could fault again and actually crash. - -Hopefully, these spurious faults should be rare enough that this is an -acceptable slowdown. - -Cc: stable@vger.kernel.org -Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/kernel/entry.S | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index 4f88d3353b00..5639031d1437 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -75,8 +75,11 @@ - /* Atomically reset the current cpu bit in new_valid_map_cpus */ - amoxor.d a0, a1, (a0) - -- /* Only emit a sfence.vma if the uarch caches invalid entries */ -- ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) -+ /* -+ * A sfence.vma is required here. Even if we had Svvptc, there's no -+ * guarantee that after returning we wouldn't just fault again. -+ */ -+ sfence.vma - - REG_L a0, TASK_TI_A0(tp) - REG_L a1, TASK_TI_A1(tp) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0327-UPSTREAM-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux-lts-kmhv2/0327-UPSTREAM-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch new file mode 100644 index 0000000000..9237c38792 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0327-UPSTREAM-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch @@ -0,0 +1,63 @@ +From a587720a8231fc15d1bdddc06c3a527a6bb31177 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Use the bitmap API for + new_valid_map_cpus + +The bitmap was defined with incorrect size. Fix it by using the proper +bitmap API in C code. The corresponding assembly code is still okay and +remains unchanged. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-4-f80d8354d79d@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 26c171fc48539ac88d3697792b1fde9334af836c) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 8 +++----- + arch/riscv/mm/init.c | 2 +- + 2 files changed, 4 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 8c7a0ef2635a..8cfe59483a8f 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -41,19 +41,17 @@ do { \ + } while (0) + + #ifdef CONFIG_64BIT +-extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; ++/* This is accessed in assembly code. cpumask_var_t would be too complex. */ ++extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; + static inline void mark_new_valid_map(void) + { +- int i; +- + /* + * We don't care if concurrently a cpu resets this value since + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. + */ +- for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) +- new_valid_map_cpus[i] = -1ULL; ++ bitmap_fill(new_valid_map_cpus, NR_CPUS); + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 750d3356683a..6533cc17825a 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,7 @@ + + #include "../kernel/head.h" + +-u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; ++DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch deleted file mode 100644 index 113e960802..0000000000 --- a/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1bee6d3eac2cd34b39a8ce2c3e590aaf2f4f38f1 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 5 Mar 2026 01:00:51 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 PHY - support - -Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP -of USB2 PHY mostly shares the same functionalities with K1 SoC, while has -some register layout changes. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org -Signed-off-by: Han Gao ---- - .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -index 43eaca90d88c..18025e5f60d6 100644 ---- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -@@ -4,14 +4,16 @@ - $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 SoC USB 2.0 PHY -+title: SpacemiT K1/K3 SoC USB 2.0 PHY - - maintainers: - - Ze Huang - - properties: - compatible: -- const: spacemit,k1-usb2-phy -+ enum: -+ - spacemit,k1-usb2-phy -+ - spacemit,k3-usb2-phy - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0328-UPSTREAM-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux-lts-kmhv2/0328-UPSTREAM-riscv-mm-Unconditionally-sfence.vma-for-spu.patch new file mode 100644 index 0000000000..5292c92a0e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0328-UPSTREAM-riscv-mm-Unconditionally-sfence.vma-for-spu.patch @@ -0,0 +1,46 @@ +From ace153ba8b01ae0c26eebe767cf283497f23a6c4 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Unconditionally sfence.vma for + spurious fault + +Svvptc does not guarantee that it's safe to just return here. Since we +have already cleared our bit, if, theoretically, the bounded timeframe +for the accessed page to become valid still hasn't happened after sret, +we could fault again and actually crash. + +Hopefully, these spurious faults should be rare enough that this is an +acceptable slowdown. + +Cc: stable@vger.kernel.org +Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 1b2c6b56a9fa0dcbef461039937de22b1cbecc7d) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/entry.S | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 4f88d3353b00..5639031d1437 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -75,8 +75,11 @@ + /* Atomically reset the current cpu bit in new_valid_map_cpus */ + amoxor.d a0, a1, (a0) + +- /* Only emit a sfence.vma if the uarch caches invalid entries */ +- ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) ++ /* ++ * A sfence.vma is required here. Even if we had Svvptc, there's no ++ * guarantee that after returning we wouldn't just fault again. ++ */ ++ sfence.vma + + REG_L a0, TASK_TI_A0(tp) + REG_L a1, TASK_TI_A1(tp) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch deleted file mode 100644 index 309f8ea1b2..0000000000 --- a/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch +++ /dev/null @@ -1,109 +0,0 @@ -From e42b13b733fe6bf35801da4dd939e98421377976 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 5 Mar 2026 01:00:52 +0000 -Subject: [RUYI PATCH] FROMLIST: phy: k1-usb: k3: add USB2 PHY support - -Add USB2 PHY support for SpacemiT K3 SoC. - -Register layout of handling USB disconnect operation has been changed, -So introducing a platform data to distinguish the different SoCs. - -Reviewed-by: Yao Zi -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-2-15554fb933bc@kernel.org -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++----- - 1 file changed, 29 insertions(+), 5 deletions(-) - -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -index 9215d0b223b2..87b943d9111f 100644 ---- a/drivers/phy/spacemit/phy-k1-usb2.c -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -51,6 +51,9 @@ - #define PHY_K1_HS_HOST_DISC 0x40 - #define PHY_K1_HS_HOST_DISC_CLR BIT(0) - -+#define PHY_K3_HS_HOST_DISC 0x20 -+#define PHY_K3_HS_HOST_DISC_CLR BIT(8) -+ - #define PHY_PLL_DIV_CFG 0x98 - #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) - #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -@@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy) - return 0; - } - --static int spacemit_usb2phy_disconnect(struct phy *phy, int port) -+static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port) - { - struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); - -@@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port) - return 0; - } - --static const struct phy_ops spacemit_usb2phy_ops = { -+static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC, -+ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR); -+ -+ return 0; -+} -+ -+static const struct phy_ops spacemit_k1_usb2phy_ops = { - .init = spacemit_usb2phy_init, - .exit = spacemit_usb2phy_exit, -- .disconnect = spacemit_usb2phy_disconnect, -+ .disconnect = spacemit_k1_usb2phy_disconnect, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct phy_ops spacemit_k3_usb2phy_ops = { -+ .init = spacemit_usb2phy_init, -+ .exit = spacemit_usb2phy_exit, -+ .disconnect = spacemit_k3_usb2phy_disconnect, - .owner = THIS_MODULE, - }; - -@@ -167,12 +187,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct spacemit_usb2phy *sphy; -+ const struct phy_ops *ops; - void __iomem *base; - - sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); - if (!sphy) - return -ENOMEM; - -+ ops = device_get_match_data(dev); -+ - sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); - if (IS_ERR(sphy->clk)) - return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); -@@ -185,7 +208,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - if (IS_ERR(sphy->regmap_base)) - return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); - -- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); -+ sphy->phy = devm_phy_create(dev, NULL, ops); - if (IS_ERR(sphy->phy)) - return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); - -@@ -196,7 +219,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - } - - static const struct of_device_id spacemit_usb2phy_dt_match[] = { -- { .compatible = "spacemit,k1-usb2-phy", }, -+ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops }, -+ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0329-UPSTREAM-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux-lts-kmhv2/0329-UPSTREAM-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch new file mode 100644 index 0000000000..09ed31d943 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0329-UPSTREAM-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch @@ -0,0 +1,49 @@ +From 1c431753b9cfbc8886977e0bc6e1a1f1031cd8ca Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Sat, 6 Jun 2026 20:17:54 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Define DIRECT_MAP_PHYSMEM_END + +On RISC-V, the actual mappable range of physical address space is +dependent on the current MMU mode i.e. satp_mode (See +Documentation/arch/riscv/vm-layout.rst). + +Define the DIRECT_MAP_PHYSMEM_END macro based on the existing virtual +address space layout macros to expose this information to +get_free_mem_region(). Otherwise, it returns a region that couldn't be +mapped, which breaks ZONE_DEVICE. + +Cc: stable@vger.kernel.org # v6.13+ +Tested-by: Han Gao # SG2044 +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260309-riscv-sparsemem-vmemmap-limits-v1-2-f40efe18e3cd@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit f3336b48cf9d3f2d1fc78e3289c0ded2f00876ee) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/pgtable.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 30d1ea93dde3..9b2e967c9fe0 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -93,6 +93,16 @@ + */ + #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) + ++/* Needed to limit get_free_mem_region() */ ++#if defined(CONFIG_FLATMEM) ++#define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) ++#elif defined(CONFIG_SPARSEMEM_VMEMMAP) ++#define DIRECT_MAP_PHYSMEM_END \ ++ ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) ++#elif defined(CONFIG_SPARSEMEM) ++/* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ ++#endif ++ + #define PCI_IO_SIZE SZ_16M + #define PCI_IO_END VMEMMAP_START + #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch deleted file mode 100644 index f84dd26276..0000000000 --- a/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 313a26d3fa86f65c2c9bcfdaa1d325594d4d3960 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Fri, 10 Apr 2026 15:58:22 +0800 -Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to - the allowlist - -The SpacemiT K1 SoC uses standard device tree based CPU frequency -scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. - -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-1-4e16b8c0f60e@mailbox.org -Signed-off-by: Han Gao ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c -index 47dd76acd31e..5c048d7351be 100644 ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = { - { .have_governor_per_policy = true, }, - }, - -+ { .compatible = "spacemit,k1", }, - { .compatible = "st-ericsson,u8500", }, - { .compatible = "st-ericsson,u8540", }, - { .compatible = "st-ericsson,u9500", }, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0330-UPSTREAM-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux-lts-kmhv2/0330-UPSTREAM-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch new file mode 100644 index 0000000000..15d1e94f44 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0330-UPSTREAM-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch @@ -0,0 +1,48 @@ +From 5b5b7926b1acc7efd8184d408f7f48ac6348b55c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 5 Mar 2026 01:00:51 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: k3: add USB2 PHY + support + +Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP +of USB2 PHY mostly shares the same functionalities with K1 SoC, while has +some register layout changes. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=c05cf9d274daf72dc7e433480cf2e0e888f6bd89 [1] +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=00b4fe5be06aecd6426930de86b7cffc2330f4b8 [2] +Link: https://patch.msgid.link/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit ad8fdebd40fd25e86331886f4fc6951531691319) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +index 43eaca90d88c..18025e5f60d6 100644 +--- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +@@ -4,14 +4,16 @@ + $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 SoC USB 2.0 PHY ++title: SpacemiT K1/K3 SoC USB 2.0 PHY + + maintainers: + - Ze Huang + + properties: + compatible: +- const: spacemit,k1-usb2-phy ++ enum: ++ - spacemit,k1-usb2-phy ++ - spacemit,k3-usb2-phy + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch deleted file mode 100644 index ab37eecf22..0000000000 --- a/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch +++ /dev/null @@ -1,264 +0,0 @@ -From 76023519e9da3b79768d23f7ffe1a08e230674bd Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Fri, 10 Apr 2026 15:58:23 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 - SoC - -Add Operating Performance Points (OPP) tables and CPU clock properties -for the two clusters in the SpacemiT K1 SoC. - -Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 -board to fully enable CPU DVFS. - -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- - arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ - 3 files changed, 147 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 9429189354d6..2a0caecd9a41 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -5,6 +5,7 @@ - - #include "k1.dtsi" - #include "k1-pinctrl.dtsi" -+#include "k1-opp.dtsi" - - / { - model = "Banana Pi BPI-F3"; -@@ -85,6 +86,38 @@ &combo_phy { - status = "okay"; - }; - -+&cpu_0 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_1 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_2 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_3 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_4 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_5 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_6 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_7 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ - &emmc { - bus-width = <8>; - mmc-hs400-1_8v; -@@ -200,7 +233,7 @@ pmic@41 { - dldoin2-supply = <&buck5>; - - regulators { -- buck1 { -+ buck1_3v45: buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi -new file mode 100644 -index 000000000000..768ae390686d ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi -@@ -0,0 +1,105 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/ { -+ cluster0_opp_table: opp-table-cluster0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-614400000 { -+ opp-hz = /bits/ 64 <614400000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-819000000 { -+ opp-hz = /bits/ 64 <819000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1228800000 { -+ opp-hz = /bits/ 64 <1228800000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <1050000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+ -+ cluster1_opp_table: opp-table-cluster1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-614400000 { -+ opp-hz = /bits/ 64 <614400000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-819000000 { -+ opp-hz = /bits/ 64 <819000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1228800000 { -+ opp-hz = /bits/ 64 <1228800000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <1050000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+}; -+ -+&cpu_0 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_1 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_2 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_3 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_4 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_5 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_6 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_7 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 2ed5cc24e505..aefdbbadc9ef 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -54,6 +54,7 @@ cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -84,6 +85,7 @@ cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -114,6 +116,7 @@ cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -144,6 +147,7 @@ cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -174,6 +178,7 @@ cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -204,6 +209,7 @@ cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -234,6 +240,7 @@ cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -264,6 +271,7 @@ cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0331-UPSTREAM-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux-lts-kmhv2/0331-UPSTREAM-phy-k1-usb-k3-add-USB2-PHY-support.patch new file mode 100644 index 0000000000..1706c58128 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0331-UPSTREAM-phy-k1-usb-k3-add-USB2-PHY-support.patch @@ -0,0 +1,114 @@ +From 7847fff353ab57df19db9c9f4b4610ae46dff156 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 5 Mar 2026 01:00:52 +0000 +Subject: [RUYI PATCH] UPSTREAM: phy: k1-usb: k3: add USB2 PHY support + +Add USB2 PHY support for SpacemiT K3 SoC. + +Register layout of handling USB disconnect operation has been changed, +So introducing a platform data to distinguish the different SoCs. + +Reviewed-by: Yao Zi +Signed-off-by: Yixun Lan +Reviewed-by: Neil Armstrong +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=c05cf9d274daf72dc7e433480cf2e0e888f6bd89 [1] +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=00b4fe5be06aecd6426930de86b7cffc2330f4b8 [2] +Link: https://patch.msgid.link/20260305-11-k3-usb2-phy-v4-2-15554fb933bc@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit 056ee8b37bc91e3230afa11ec1018fa898b983b8) +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++----- + 1 file changed, 29 insertions(+), 5 deletions(-) + +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +index 9215d0b223b2..87b943d9111f 100644 +--- a/drivers/phy/spacemit/phy-k1-usb2.c ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -51,6 +51,9 @@ + #define PHY_K1_HS_HOST_DISC 0x40 + #define PHY_K1_HS_HOST_DISC_CLR BIT(0) + ++#define PHY_K3_HS_HOST_DISC 0x20 ++#define PHY_K3_HS_HOST_DISC_CLR BIT(8) ++ + #define PHY_PLL_DIV_CFG 0x98 + #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) + #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) +@@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy) + return 0; + } + +-static int spacemit_usb2phy_disconnect(struct phy *phy, int port) ++static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port) + { + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + +@@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port) + return 0; + } + +-static const struct phy_ops spacemit_usb2phy_ops = { ++static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC, ++ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR); ++ ++ return 0; ++} ++ ++static const struct phy_ops spacemit_k1_usb2phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, +- .disconnect = spacemit_usb2phy_disconnect, ++ .disconnect = spacemit_k1_usb2phy_disconnect, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops spacemit_k3_usb2phy_ops = { ++ .init = spacemit_usb2phy_init, ++ .exit = spacemit_usb2phy_exit, ++ .disconnect = spacemit_k3_usb2phy_disconnect, + .owner = THIS_MODULE, + }; + +@@ -167,12 +187,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct spacemit_usb2phy *sphy; ++ const struct phy_ops *ops; + void __iomem *base; + + sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); + if (!sphy) + return -ENOMEM; + ++ ops = device_get_match_data(dev); ++ + sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); + if (IS_ERR(sphy->clk)) + return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); +@@ -185,7 +208,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + if (IS_ERR(sphy->regmap_base)) + return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); + +- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); ++ sphy->phy = devm_phy_create(dev, NULL, ops); + if (IS_ERR(sphy->phy)) + return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); + +@@ -196,7 +219,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + } + + static const struct of_device_id spacemit_usb2phy_dt_match[] = { +- { .compatible = "spacemit,k1-usb2-phy", }, ++ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops }, ++ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch deleted file mode 100644 index a5d6058fa5..0000000000 --- a/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch +++ /dev/null @@ -1,47 +0,0 @@ -From b71c8252ef37bceafb077b1ac8b79eb81f094356 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 9 Mar 2026 19:09:38 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END - -On RISC-V, the actual mappable range of physical address space is -dependent on the current MMU mode i.e. satp_mode (See -Documentation/arch/riscv/vm-layout.rst). - -Define the DIRECT_MAP_PHYSMEM_END macro based on the existing virtual -address space layout macros to expose this information to -get_free_mem_region(). Otherwise, it returns a region that couldn't be -mapped, which breaks ZONE_DEVICE. - -Cc: stable@vger.kernel.org # v6.13+ -Tested-by: Han Gao # SG2044 -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260309-riscv-sparsemem-vmemmap-limits-v1-2-f40efe18e3cd@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/pgtable.h | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h -index 30d1ea93dde3..9b2e967c9fe0 100644 ---- a/arch/riscv/include/asm/pgtable.h -+++ b/arch/riscv/include/asm/pgtable.h -@@ -93,6 +93,16 @@ - */ - #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) - -+/* Needed to limit get_free_mem_region() */ -+#if defined(CONFIG_FLATMEM) -+#define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) -+#elif defined(CONFIG_SPARSEMEM_VMEMMAP) -+#define DIRECT_MAP_PHYSMEM_END \ -+ ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) -+#elif defined(CONFIG_SPARSEMEM) -+/* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ -+#endif -+ - #define PCI_IO_SIZE SZ_16M - #define PCI_IO_END VMEMMAP_START - #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0332-UPSTREAM-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux-lts-kmhv2/0332-UPSTREAM-drm-verisilicon-add-max-cursor-size-to-HWDB.patch new file mode 100644 index 0000000000..d96de5f89a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0332-UPSTREAM-drm-verisilicon-add-max-cursor-size-to-HWDB.patch @@ -0,0 +1,79 @@ +From 74b04b4bce07d610a797bf8a9e01aa04cc395d49 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 01:56:09 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add max cursor size to HWDB + +Different display controller variants support different maximum cursor +size. All known DC8200 variants support both 32x32 and 64x64, but some +DC8000 variants support either only 32x32 or up to 256x256. + +The minimum size is fixed at 32 and only PoT square sizes are supported. + +Add the max cursor size field to HWDB and fill all entries with 64. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Thomas Zimmermann +Reviewed-by: Dmitry Baryshkov +Link: https://patch.msgid.link/20260506175610.2542888-2-zhengxingda@iscas.ac.cn +(cherry picked from commit 9637867d78a7bc5e76b17fe6cb0be5e054fce973) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 ++++ + drivers/gpu/drm/verisilicon/vs_hwdb.h | 5 +++++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c +index 09336af0900a..2a0f7c59afa3 100644 +--- a/drivers/gpu/drm/verisilicon/vs_hwdb.c ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c +@@ -95,6 +95,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = ~0U, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + { +@@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x30B, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + { +@@ -111,6 +113,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x310, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_with_yuv444, + }, + { +@@ -119,6 +122,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x311, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + }; +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h +index 92192e4fa086..2065ecb73043 100644 +--- a/drivers/gpu/drm/verisilicon/vs_hwdb.h ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h +@@ -20,6 +20,11 @@ struct vs_chip_identity { + u32 customer_id; + + u32 display_count; ++ /* ++ * The hardware only supports square cursor planes, so this field ++ * is both the maximum width and height in pixels. ++ */ ++ int32_t max_cursor_size; + const struct vs_formats *formats; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch deleted file mode 100644 index 3cac36fd67..0000000000 --- a/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 3d54bf791cf5017cc96bc5222094dc98fb50e585 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 01:56:09 +0800 -Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add max cursor size to HWDB - -Different display controller variants support different maximum cursor -size. All known DC8200 variants support both 32x32 and 64x64, but some -DC8000 variants support either only 32x32 or up to 256x256. - -The minimum size is fixed at 32 and only PoT square sizes are supported. - -Add the max cursor size field to HWDB and fill all entries with 64. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Thomas Zimmermann -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20260506175610.2542888-2-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 ++++ - drivers/gpu/drm/verisilicon/vs_hwdb.h | 5 +++++ - 2 files changed, 9 insertions(+) - -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c -index 09336af0900a..2a0f7c59afa3 100644 ---- a/drivers/gpu/drm/verisilicon/vs_hwdb.c -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c -@@ -95,6 +95,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = ~0U, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - { -@@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x30B, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - { -@@ -111,6 +113,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x310, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_with_yuv444, - }, - { -@@ -119,6 +122,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x311, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - }; -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h -index 92192e4fa086..2065ecb73043 100644 ---- a/drivers/gpu/drm/verisilicon/vs_hwdb.h -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h -@@ -20,6 +20,11 @@ struct vs_chip_identity { - u32 customer_id; - - u32 display_count; -+ /* -+ * The hardware only supports square cursor planes, so this field -+ * is both the maximum width and height in pixels. -+ */ -+ int32_t max_cursor_size; - const struct vs_formats *formats; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0333-UPSTREAM-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux-lts-kmhv2/0333-UPSTREAM-drm-verisilicon-add-support-for-cursor-plan.patch new file mode 100644 index 0000000000..1bfbc1c42d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0333-UPSTREAM-drm-verisilicon-add-support-for-cursor-plan.patch @@ -0,0 +1,412 @@ +From 36a43bb417a3853fa8c3f3571cedd82e1b464bc6 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 01:56:10 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add support for cursor + planes + +Verisilicon display controllers support hardware cursors per output +port. + +Add support for them as cursor planes. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Thomas Zimmermann +Reviewed-by: Dmitry Baryshkov +Link: https://patch.msgid.link/20260506175610.2542888-3-zhengxingda@iscas.ac.cn +(cherry picked from commit 8c4ae218912554ef427440293cdb97319d17ca5d) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/verisilicon/Makefile | 3 +- + drivers/gpu/drm/verisilicon/vs_crtc.c | 11 +- + drivers/gpu/drm/verisilicon/vs_cursor_plane.c | 272 ++++++++++++++++++ + .../drm/verisilicon/vs_cursor_plane_regs.h | 44 +++ + drivers/gpu/drm/verisilicon/vs_plane.h | 1 + + 5 files changed, 328 insertions(+), 3 deletions(-) + create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index fd8d805fbcde..426f4bcaa834 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o ++verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ ++ vs_plane.o vs_primary_plane.o vs_cursor_plane.o + + obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c +index f49401713000..5c9714a3e69a 100644 +--- a/drivers/gpu/drm/verisilicon/vs_crtc.c ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.c +@@ -159,7 +159,7 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + unsigned int output) + { + struct vs_crtc *vcrtc; +- struct drm_plane *primary; ++ struct drm_plane *primary, *cursor; + int ret; + + vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); +@@ -175,9 +175,16 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + return ERR_PTR(PTR_ERR(primary)); + } + ++ /* Create our cursor plane */ ++ cursor = vs_cursor_plane_init(drm_dev, dc); ++ if (IS_ERR(cursor)) { ++ drm_err(drm_dev, "Couldn't create the cursor plane\n"); ++ return ERR_CAST(cursor); ++ } ++ + ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, + primary, +- NULL, ++ cursor, + &vs_crtc_funcs, + NULL); + if (ret) { +diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane.c b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c +new file mode 100644 +index 000000000000..acb9854fa67e +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c +@@ -0,0 +1,272 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) ++ * ++ * Authors: ++ * Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_plane.h" ++#include "vs_dc.h" ++#include "vs_hwdb.h" ++#include "vs_cursor_plane_regs.h" ++ ++#define VSDC_MIN_CURSOR_SIZE 32 ++#define VSDC_MAX_CURSOR_SIZE 256 ++ ++#define VSDC_CURSOR_LOCATION_MAX_POSITIVE BIT_MASK(15) ++#define VSDC_CURSOR_LOCATION_MAX_NEGATIVE BIT_MASK(5) ++ ++static bool vs_cursor_plane_check_coord(int32_t coord) ++{ ++ if (coord >= 0) ++ return coord <= VSDC_CURSOR_LOCATION_MAX_POSITIVE; ++ else ++ return (-coord) <= VSDC_CURSOR_LOCATION_MAX_NEGATIVE; ++} ++ ++static int vs_cursor_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct drm_framebuffer *fb = new_plane_state->fb; ++ struct drm_crtc_state *crtc_state = NULL; ++ struct vs_crtc *vcrtc; ++ struct vs_dc *dc; ++ int ret; ++ ++ if (crtc) ++ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); ++ ++ ret = drm_atomic_helper_check_plane_state(new_plane_state, ++ crtc_state, ++ DRM_PLANE_NO_SCALING, ++ DRM_PLANE_NO_SCALING, ++ true, true); ++ if (ret) ++ return ret; ++ ++ if (!new_plane_state->visible) ++ return 0; /* Skip validity check */ ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ dc = vcrtc->dc; ++ ++ /* Only certain PoT square sizes is supported. */ ++ if (!is_power_of_2(new_plane_state->crtc_w) || ++ new_plane_state->crtc_w < VSDC_MIN_CURSOR_SIZE || ++ new_plane_state->crtc_w > dc->identity.max_cursor_size) ++ return -EINVAL; ++ ++ if (new_plane_state->crtc_w != new_plane_state->crtc_h) ++ return -EINVAL; ++ ++ /* Check if the cursor is inside the register fields' range */ ++ if (!vs_cursor_plane_check_coord(new_plane_state->crtc_x) || ++ !vs_cursor_plane_check_coord(new_plane_state->crtc_y)) ++ return -EINVAL; ++ ++ /* Extra line padding isn't supported */ ++ if (fb->pitches[0] != ++ drm_format_info_min_pitch(fb->format, 0, new_plane_state->crtc_w)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) ++{ ++ regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_COMMIT | ++ VSDC_CURSOR_CONFIG_IMG_UPDATE); ++} ++ ++static void vs_cursor_plane_atomic_enable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_FMT_MASK, ++ VSDC_CURSOR_CONFIG_FMT_ARGB8888); ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static void vs_cursor_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_FMT_MASK, ++ VSDC_CURSOR_CONFIG_FMT_OFF); ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static void vs_cursor_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_framebuffer *fb = state->fb; ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_dc *dc; ++ struct vs_crtc *vcrtc; ++ unsigned int output; ++ dma_addr_t dma_addr; ++ ++ if (!state->visible) { ++ vs_cursor_plane_atomic_disable(plane, atomic_state); ++ return; ++ } ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ output = vcrtc->id; ++ dc = vcrtc->dc; ++ ++ /* Other sizes should be rejected by atomic_check */ ++ switch (state->crtc_w) { ++ case 32: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_32); ++ break; ++ case 64: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_64); ++ break; ++ case 128: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_128); ++ break; ++ case 256: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_256); ++ break; ++ } ++ ++ dma_addr = vs_fb_get_dma_addr(fb, &state->src); ++ ++ regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output), ++ lower_32_bits(dma_addr)); ++ ++ /* ++ * The X_OFF and Y_OFF fields define which point does the LOCATION ++ * register represent in the cursor image, and LOCATION register ++ * values are unsigned. To for positive left-top coordinates the ++ * offset is set to 0 and the location is set to the coordinate, for ++ * negative coordinates the location is set to 0 and the offset ++ * is set to the opposite number of the coordinate to offset the ++ * cursor image partly off-screen. ++ */ ++ if (state->crtc_x >= 0) { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_X_OFF_MASK, 0); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_X_MASK, ++ VSDC_CURSOR_LOCATION_X(state->crtc_x)); ++ } else { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_X_OFF_MASK, ++ -state->crtc_x); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_X_MASK, 0); ++ } ++ ++ if (state->crtc_y >= 0) { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_Y_OFF_MASK, 0); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_Y_MASK, ++ VSDC_CURSOR_LOCATION_Y(state->crtc_y)); ++ } else { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_Y_OFF_MASK, ++ -state->crtc_y); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_Y_MASK, 0); ++ } ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static const struct drm_plane_helper_funcs vs_cursor_plane_helper_funcs = { ++ .atomic_check = vs_cursor_plane_atomic_check, ++ .atomic_update = vs_cursor_plane_atomic_update, ++ .atomic_enable = vs_cursor_plane_atomic_enable, ++ .atomic_disable = vs_cursor_plane_atomic_disable, ++}; ++ ++static const struct drm_plane_funcs vs_cursor_plane_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .reset = drm_atomic_helper_plane_reset, ++ .update_plane = drm_atomic_helper_update_plane, ++}; ++ ++static const u32 vs_cursor_plane_formats[] = { ++ DRM_FORMAT_ARGB8888, ++}; ++ ++static const u64 vs_cursor_plane_modifiers[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ DRM_FORMAT_MOD_INVALID, /* sentinel */ ++}; ++ ++struct drm_plane *vs_cursor_plane_init(struct drm_device *drm_dev, ++ struct vs_dc *dc) ++{ ++ int32_t max_cursor_size = dc->identity.max_cursor_size; ++ struct drm_plane *plane; ++ ++ if (drm_WARN_ON_ONCE(drm_dev, max_cursor_size < VSDC_MIN_CURSOR_SIZE || ++ max_cursor_size > VSDC_MAX_CURSOR_SIZE)) ++ return ERR_PTR(-EINVAL); ++ ++ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, ++ &vs_cursor_plane_funcs, ++ vs_cursor_plane_formats, ++ ARRAY_SIZE(vs_cursor_plane_formats), ++ vs_cursor_plane_modifiers, ++ DRM_PLANE_TYPE_CURSOR, ++ NULL); ++ ++ if (IS_ERR(plane)) ++ return plane; ++ ++ drm_plane_helper_add(plane, &vs_cursor_plane_helper_funcs); ++ ++ return plane; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h +new file mode 100644 +index 000000000000..99693f2c95b9 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h +@@ -0,0 +1,44 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_CURSOR_PLANE_REGS_H_ ++#define _VS_CURSOR_PLANE_REGS_H_ ++ ++#include ++ ++#define VSDC_CURSOR_CONFIG(n) (0x1468 + 0x1080 * (n)) ++#define VSDC_CURSOR_CONFIG_FMT_MASK GENMASK(1, 0) ++#define VSDC_CURSOR_CONFIG_FMT_ARGB8888 (0x2 << 0) ++#define VSDC_CURSOR_CONFIG_FMT_OFF (0x0 << 0) ++#define VSDC_CURSOR_CONFIG_IMG_UPDATE BIT(2) ++#define VSDC_CURSOR_CONFIG_COMMIT BIT(3) ++#define VSDC_CURSOR_CONFIG_SIZE_MASK GENMASK(7, 5) ++#define VSDC_CURSOR_CONFIG_SIZE_32 (0x0 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_64 (0x1 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_128 (0x2 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_256 (0x3 << 5) ++#define VSDC_CURSOR_CONFIG_Y_OFF_MASK GENMASK(12, 8) ++#define VSDC_CURSOR_CONFIG_Y_OFF(v) ((v) << 8) ++#define VSDC_CURSOR_CONFIG_X_OFF_MASK GENMASK(20, 16) ++#define VSDC_CURSOR_CONFIG_X_OFF(v) ((v) << 16) ++ ++#define VSDC_CURSOR_ADDRESS(n) (0x146C + 0x1080 * (n)) ++ ++#define VSDC_CURSOR_LOCATION(n) (0x1470 + 0x1080 * (n)) ++#define VSDC_CURSOR_LOCATION_X_MASK GENMASK(14, 0) ++#define VSDC_CURSOR_LOCATION_X(v) ((v) << 0) ++#define VSDC_CURSOR_LOCATION_Y_MASK GENMASK(30, 16) ++#define VSDC_CURSOR_LOCATION_Y(v) ((v) << 16) ++ ++#define VSDC_CURSOR_BACKGROUND(n) (0x1474 + 0x1080 * (n)) ++#define VSDC_CURSOR_BACKGRUOND_DEFAULT 0x00FFFFFF ++ ++#define VSDC_CURSOR_FOREGROUND(n) (0x1478 + 0x1080 * (n)) ++#define VSDC_CURSOR_FOREGRUOND_DEFAULT 0x00AAAAAA ++ ++#endif /* _VS_CURSOR_PLANE_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h +index 41875ea3d66a..60b5b3a1bc22 100644 +--- a/drivers/gpu/drm/verisilicon/vs_plane.h ++++ b/drivers/gpu/drm/verisilicon/vs_plane.h +@@ -68,5 +68,6 @@ dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, + const struct drm_rect *src_rect); + + struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); ++struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc); + + #endif /* _VS_PLANE_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch deleted file mode 100644 index 0430f73844..0000000000 --- a/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch +++ /dev/null @@ -1,411 +0,0 @@ -From 5b2cb452135b05fe65a5440fa7f2e39d9b28d5f3 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 01:56:10 +0800 -Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add support for cursor - planes - -Verisilicon display controllers support hardware cursors per output -port. - -Add support for them as cursor planes. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Thomas Zimmermann -Link: https://lore.kernel.org/r/20260506175610.2542888-3-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/gpu/drm/verisilicon/Makefile | 3 +- - drivers/gpu/drm/verisilicon/vs_crtc.c | 11 +- - drivers/gpu/drm/verisilicon/vs_cursor_plane.c | 272 ++++++++++++++++++ - .../drm/verisilicon/vs_cursor_plane_regs.h | 44 +++ - drivers/gpu/drm/verisilicon/vs_plane.h | 1 + - 5 files changed, 328 insertions(+), 3 deletions(-) - create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h - -diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile -index fd8d805fbcde..426f4bcaa834 100644 ---- a/drivers/gpu/drm/verisilicon/Makefile -+++ b/drivers/gpu/drm/verisilicon/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0-only - --verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o -+verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ -+ vs_plane.o vs_primary_plane.o vs_cursor_plane.o - - obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c -index f49401713000..5c9714a3e69a 100644 ---- a/drivers/gpu/drm/verisilicon/vs_crtc.c -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.c -@@ -159,7 +159,7 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, - unsigned int output) - { - struct vs_crtc *vcrtc; -- struct drm_plane *primary; -+ struct drm_plane *primary, *cursor; - int ret; - - vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); -@@ -175,9 +175,16 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, - return ERR_PTR(PTR_ERR(primary)); - } - -+ /* Create our cursor plane */ -+ cursor = vs_cursor_plane_init(drm_dev, dc); -+ if (IS_ERR(cursor)) { -+ drm_err(drm_dev, "Couldn't create the cursor plane\n"); -+ return ERR_CAST(cursor); -+ } -+ - ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, - primary, -- NULL, -+ cursor, - &vs_crtc_funcs, - NULL); - if (ret) { -diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane.c b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c -new file mode 100644 -index 000000000000..acb9854fa67e ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c -@@ -0,0 +1,272 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) -+ * -+ * Authors: -+ * Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_plane.h" -+#include "vs_dc.h" -+#include "vs_hwdb.h" -+#include "vs_cursor_plane_regs.h" -+ -+#define VSDC_MIN_CURSOR_SIZE 32 -+#define VSDC_MAX_CURSOR_SIZE 256 -+ -+#define VSDC_CURSOR_LOCATION_MAX_POSITIVE BIT_MASK(15) -+#define VSDC_CURSOR_LOCATION_MAX_NEGATIVE BIT_MASK(5) -+ -+static bool vs_cursor_plane_check_coord(int32_t coord) -+{ -+ if (coord >= 0) -+ return coord <= VSDC_CURSOR_LOCATION_MAX_POSITIVE; -+ else -+ return (-coord) <= VSDC_CURSOR_LOCATION_MAX_NEGATIVE; -+} -+ -+static int vs_cursor_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc *crtc = new_plane_state->crtc; -+ struct drm_framebuffer *fb = new_plane_state->fb; -+ struct drm_crtc_state *crtc_state = NULL; -+ struct vs_crtc *vcrtc; -+ struct vs_dc *dc; -+ int ret; -+ -+ if (crtc) -+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ -+ ret = drm_atomic_helper_check_plane_state(new_plane_state, -+ crtc_state, -+ DRM_PLANE_NO_SCALING, -+ DRM_PLANE_NO_SCALING, -+ true, true); -+ if (ret) -+ return ret; -+ -+ if (!new_plane_state->visible) -+ return 0; /* Skip validity check */ -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ dc = vcrtc->dc; -+ -+ /* Only certain PoT square sizes is supported. */ -+ if (!is_power_of_2(new_plane_state->crtc_w) || -+ new_plane_state->crtc_w < VSDC_MIN_CURSOR_SIZE || -+ new_plane_state->crtc_w > dc->identity.max_cursor_size) -+ return -EINVAL; -+ -+ if (new_plane_state->crtc_w != new_plane_state->crtc_h) -+ return -EINVAL; -+ -+ /* Check if the cursor is inside the register fields' range */ -+ if (!vs_cursor_plane_check_coord(new_plane_state->crtc_x) || -+ !vs_cursor_plane_check_coord(new_plane_state->crtc_y)) -+ return -EINVAL; -+ -+ /* Extra line padding isn't supported */ -+ if (fb->pitches[0] != -+ drm_format_info_min_pitch(fb->format, 0, new_plane_state->crtc_w)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) -+{ -+ regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_COMMIT | -+ VSDC_CURSOR_CONFIG_IMG_UPDATE); -+} -+ -+static void vs_cursor_plane_atomic_enable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_FMT_MASK, -+ VSDC_CURSOR_CONFIG_FMT_ARGB8888); -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static void vs_cursor_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_FMT_MASK, -+ VSDC_CURSOR_CONFIG_FMT_OFF); -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static void vs_cursor_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_framebuffer *fb = state->fb; -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_dc *dc; -+ struct vs_crtc *vcrtc; -+ unsigned int output; -+ dma_addr_t dma_addr; -+ -+ if (!state->visible) { -+ vs_cursor_plane_atomic_disable(plane, atomic_state); -+ return; -+ } -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ output = vcrtc->id; -+ dc = vcrtc->dc; -+ -+ /* Other sizes should be rejected by atomic_check */ -+ switch (state->crtc_w) { -+ case 32: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_32); -+ break; -+ case 64: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_64); -+ break; -+ case 128: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_128); -+ break; -+ case 256: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_256); -+ break; -+ } -+ -+ dma_addr = vs_fb_get_dma_addr(fb, &state->src); -+ -+ regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output), -+ lower_32_bits(dma_addr)); -+ -+ /* -+ * The X_OFF and Y_OFF fields define which point does the LOCATION -+ * register represent in the cursor image, and LOCATION register -+ * values are unsigned. To for positive left-top coordinates the -+ * offset is set to 0 and the location is set to the coordinate, for -+ * negative coordinates the location is set to 0 and the offset -+ * is set to the opposite number of the coordinate to offset the -+ * cursor image partly off-screen. -+ */ -+ if (state->crtc_x >= 0) { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_X_OFF_MASK, 0); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_X_MASK, -+ VSDC_CURSOR_LOCATION_X(state->crtc_x)); -+ } else { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_X_OFF_MASK, -+ -state->crtc_x); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_X_MASK, 0); -+ } -+ -+ if (state->crtc_y >= 0) { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_Y_OFF_MASK, 0); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_Y_MASK, -+ VSDC_CURSOR_LOCATION_Y(state->crtc_y)); -+ } else { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_Y_OFF_MASK, -+ -state->crtc_y); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_Y_MASK, 0); -+ } -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static const struct drm_plane_helper_funcs vs_cursor_plane_helper_funcs = { -+ .atomic_check = vs_cursor_plane_atomic_check, -+ .atomic_update = vs_cursor_plane_atomic_update, -+ .atomic_enable = vs_cursor_plane_atomic_enable, -+ .atomic_disable = vs_cursor_plane_atomic_disable, -+}; -+ -+static const struct drm_plane_funcs vs_cursor_plane_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .reset = drm_atomic_helper_plane_reset, -+ .update_plane = drm_atomic_helper_update_plane, -+}; -+ -+static const u32 vs_cursor_plane_formats[] = { -+ DRM_FORMAT_ARGB8888, -+}; -+ -+static const u64 vs_cursor_plane_modifiers[] = { -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID, /* sentinel */ -+}; -+ -+struct drm_plane *vs_cursor_plane_init(struct drm_device *drm_dev, -+ struct vs_dc *dc) -+{ -+ int32_t max_cursor_size = dc->identity.max_cursor_size; -+ struct drm_plane *plane; -+ -+ if (drm_WARN_ON_ONCE(drm_dev, max_cursor_size < VSDC_MIN_CURSOR_SIZE || -+ max_cursor_size > VSDC_MAX_CURSOR_SIZE)) -+ return ERR_PTR(-EINVAL); -+ -+ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, -+ &vs_cursor_plane_funcs, -+ vs_cursor_plane_formats, -+ ARRAY_SIZE(vs_cursor_plane_formats), -+ vs_cursor_plane_modifiers, -+ DRM_PLANE_TYPE_CURSOR, -+ NULL); -+ -+ if (IS_ERR(plane)) -+ return plane; -+ -+ drm_plane_helper_add(plane, &vs_cursor_plane_helper_funcs); -+ -+ return plane; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h -new file mode 100644 -index 000000000000..99693f2c95b9 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_CURSOR_PLANE_REGS_H_ -+#define _VS_CURSOR_PLANE_REGS_H_ -+ -+#include -+ -+#define VSDC_CURSOR_CONFIG(n) (0x1468 + 0x1080 * (n)) -+#define VSDC_CURSOR_CONFIG_FMT_MASK GENMASK(1, 0) -+#define VSDC_CURSOR_CONFIG_FMT_ARGB8888 (0x2 << 0) -+#define VSDC_CURSOR_CONFIG_FMT_OFF (0x0 << 0) -+#define VSDC_CURSOR_CONFIG_IMG_UPDATE BIT(2) -+#define VSDC_CURSOR_CONFIG_COMMIT BIT(3) -+#define VSDC_CURSOR_CONFIG_SIZE_MASK GENMASK(7, 5) -+#define VSDC_CURSOR_CONFIG_SIZE_32 (0x0 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_64 (0x1 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_128 (0x2 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_256 (0x3 << 5) -+#define VSDC_CURSOR_CONFIG_Y_OFF_MASK GENMASK(12, 8) -+#define VSDC_CURSOR_CONFIG_Y_OFF(v) ((v) << 8) -+#define VSDC_CURSOR_CONFIG_X_OFF_MASK GENMASK(20, 16) -+#define VSDC_CURSOR_CONFIG_X_OFF(v) ((v) << 16) -+ -+#define VSDC_CURSOR_ADDRESS(n) (0x146C + 0x1080 * (n)) -+ -+#define VSDC_CURSOR_LOCATION(n) (0x1470 + 0x1080 * (n)) -+#define VSDC_CURSOR_LOCATION_X_MASK GENMASK(14, 0) -+#define VSDC_CURSOR_LOCATION_X(v) ((v) << 0) -+#define VSDC_CURSOR_LOCATION_Y_MASK GENMASK(30, 16) -+#define VSDC_CURSOR_LOCATION_Y(v) ((v) << 16) -+ -+#define VSDC_CURSOR_BACKGROUND(n) (0x1474 + 0x1080 * (n)) -+#define VSDC_CURSOR_BACKGRUOND_DEFAULT 0x00FFFFFF -+ -+#define VSDC_CURSOR_FOREGROUND(n) (0x1478 + 0x1080 * (n)) -+#define VSDC_CURSOR_FOREGRUOND_DEFAULT 0x00AAAAAA -+ -+#endif /* _VS_CURSOR_PLANE_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h -index 41875ea3d66a..60b5b3a1bc22 100644 ---- a/drivers/gpu/drm/verisilicon/vs_plane.h -+++ b/drivers/gpu/drm/verisilicon/vs_plane.h -@@ -68,5 +68,6 @@ dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, - const struct drm_rect *src_rect); - - struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); -+struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc); - - #endif /* _VS_PLANE_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0334-UPSTREAM-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux-lts-kmhv2/0334-UPSTREAM-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch new file mode 100644 index 0000000000..577d5107c8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0334-UPSTREAM-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch @@ -0,0 +1,123 @@ +From f4c857da03891f845d2a43cc281ced8a1b20550c Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 27 Apr 2026 09:32:11 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: PCI: Add UltraRISC DP1000 PCIe + controller + +Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. + +Signed-off-by: Jia Wang +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: squash MAINTAINERS to driver commit update to touch only once] +Signed-off-by: Bjorn Helgaas +Reviewed-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com +(cherry picked from commit d9ff07f459552eabd04f8831bcaa76d761dfe264) +Signed-off-by: Han Gao +--- + .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++++++++++ + 1 file changed, 93 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +new file mode 100644 +index 000000000000..512b935bf5d1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +@@ -0,0 +1,93 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: UltraRISC DP1000 PCIe Host Controller ++ ++description: ++ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. ++ ++maintainers: ++ - Xincheng Zhang ++ - Jia Wang ++ ++allOf: ++ - $ref: /schemas/pci/snps,dw-pcie.yaml# ++ ++properties: ++ compatible: ++ const: ultrarisc,dp1000-pcie ++ ++ reg: ++ items: ++ - description: Data Bus Interface (DBI) registers. ++ - description: PCIe configuration space region. ++ ++ reg-names: ++ items: ++ - const: dbi ++ - const: config ++ ++ num-lanes: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [4, 16] ++ description: Number of lanes to use. ++ ++ interrupts: ++ items: ++ - description: MSI interrupt ++ - description: Legacy INTA interrupt ++ - description: Legacy INTB interrupt ++ - description: Legacy INTC interrupt ++ - description: Legacy INTD interrupt ++ ++ interrupt-names: ++ items: ++ - const: msi ++ - const: inta ++ - const: intb ++ - const: intc ++ - const: intd ++ ++required: ++ - compatible ++ - reg ++ - reg-names ++ - interrupts ++ - interrupt-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie@21000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x21000000 0x0 0x01000000>, ++ <0x0 0x4fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch deleted file mode 100644 index 6d1f390fdf..0000000000 --- a/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 7670121cc9020d50b0705929db01a06e18578be0 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 27 Apr 2026 09:32:10 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: add UltraRISC SoC family Kconfig - support - -The first SoC in the UltraRISC series is UR-DP1000, containing octa -UltraRISC CP100 cores. - -Signed-off-by: Jia Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig.socs | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs -index 848e7149e443..98c70e2ae958 100644 ---- a/arch/riscv/Kconfig.socs -+++ b/arch/riscv/Kconfig.socs -@@ -71,6 +71,12 @@ config ARCH_THEAD - help - This enables support for the RISC-V based T-HEAD SoCs. - -+config ARCH_ULTRARISC -+ bool "UltraRISC RISC-V SoCs" -+ help -+ This enables support for UltraRISC SoC platform hardware, -+ including boards based on the UR-DP1000. -+ - config ARCH_VIRT - bool "QEMU Virt Machine" - select POWER_RESET --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0335-UPSTREAM-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux-lts-kmhv2/0335-UPSTREAM-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch new file mode 100644 index 0000000000..cdd26c8e81 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0335-UPSTREAM-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch @@ -0,0 +1,307 @@ +From c76fc49d8b4f1f718bd742fe3ede9b1c0a88bdd2 Mon Sep 17 00:00:00 2001 +From: Xincheng Zhang +Date: Mon, 27 Apr 2026 09:32:12 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root + Complex driver + +Add DP1000 SoC PCIe Root Complex driver. + +The controller only supports 32-bit aligned configuration space accesses. + +Signed-off-by: Xincheng Zhang +Signed-off-by: Jia Wang +[mani: changed to builtin_platform_driver() to prevent irqchip removal] +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: squash MAINTAINERS update here] +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com +(cherry picked from commit 5fc35740c3b32d2c820c97d041282e7bca4ad0bf) +Signed-off-by: Han Gao +--- + MAINTAINERS | 8 + + drivers/pci/controller/dwc/Kconfig | 13 ++ + drivers/pci/controller/dwc/Makefile | 1 + + drivers/pci/controller/dwc/pcie-designware.h | 24 +++ + drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++ + 5 files changed, 221 insertions(+) + create mode 100644 drivers/pci/controller/dwc/pcie-ultrarisc.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 1509fa6ab229..996aa3d41e95 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -20076,6 +20076,14 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + F: drivers/pci/controller/plda/pcie-starfive.c + ++PCIE DRIVER FOR ULTRARISC DP1000 ++M: Xincheng Zhang ++M: Jia Wang ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml ++F: drivers/pci/controller/dwc/pcie-ultrarisc.c ++ + PCIE ENDPOINT DRIVER FOR QUALCOMM + M: Manivannan Sadhasivam + L: linux-pci@vger.kernel.org +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index 718bb54e943f..af024a18621d 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -531,4 +531,17 @@ config PCIE_VISCONTI_HOST + Say Y here if you want PCIe controller support on Toshiba Visconti SoC. + This driver supports TMPV7708 SoC. + ++config PCIE_ULTRARISC ++ tristate "UltraRISC PCIe host controller" ++ depends on ARCH_ULTRARISC || COMPILE_TEST ++ select PCIE_DW_HOST ++ select PCI_MSI ++ default y if ARCH_ULTRARISC ++ help ++ Enables support for the PCIe controller in the UltraRISC SoC. ++ This driver supports UR-DP1000 SoC. ++ ++ By default, this symbol is enabled when ARCH_ULTRARISC is active, ++ requiring no further configuration on that platform. ++ + endmenu +diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile +index 662b0a219ddc..39087e7a06d5 100644 +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -34,6 +34,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o + obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o + obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o + obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o ++obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o + + # The following drivers are for devices that use the generic ACPI + # pci_root.c driver but don't support standard ECAM config access. +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index 295e113189b7..535964be5ac3 100644 +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -71,6 +71,8 @@ + + /* Synopsys-specific PCIe configuration registers */ + #define PCIE_PORT_FORCE 0x708 ++/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ ++#define PORT_LINK_NUM_MASK GENMASK(7, 0) + #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) + + #define PCIE_PORT_AFR 0x70C +@@ -98,6 +100,28 @@ + #define PCIE_PORT_LANE_SKEW 0x714 + #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) + ++/* ++ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number ++ * Register. ++ * ++ * This register holds the ack frequency, latency, replay, fast link ++ * scaling timers, and max function number values. ++ * ++ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. ++ * 0x0 (SF_1024): Scaling Factor is 1024 (1ms is 1us). ++ * When the LTSSM is in Config or L12 Entry State, 1ms ++ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. ++ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) ++ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) ++ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) ++ */ ++#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 ++#define PORT_FLT_SF_MASK GENMASK(30, 29) ++#define PORT_FLT_SF_VAL_1024 0x0 ++#define PORT_FLT_SF_VAL_256 0x1 ++#define PORT_FLT_SF_VAL_64 0x2 ++#define PORT_FLT_SF_VAL_16 0x3 ++ + #define PCIE_PORT_DEBUG0 0x728 + #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f + #define PORT_LOGIC_LTSSM_STATE_L0 0x11 +diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c +new file mode 100644 +index 000000000000..6ee661ceff67 +--- /dev/null ++++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c +@@ -0,0 +1,175 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * DWC PCIe RC driver for UltraRISC SoCs ++ * ++ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#define PCIE_CUS_CORE 0x400000 ++ ++#define LTSSM_ENABLE BIT(7) ++#define FAST_LINK_MODE BIT(12) ++#define HOLD_PHY_RST BIT(14) ++#define L1SUB_DISABLE BIT(15) ++ ++#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 ++ ++static struct pci_ops ultrarisc_pci_ops = { ++ .map_bus = dw_pcie_own_conf_map_bus, ++ .read = pci_generic_config_read32, ++ .write = pci_generic_config_write32, ++}; ++ ++static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct pci_host_bridge *bridge = pp->bridge; ++ u8 cap_exp; ++ u32 val; ++ ++ bridge->ops = &ultrarisc_pci_ops; ++ ++ if (dw_pcie_link_up(pci)) ++ return 0; ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val &= ~FAST_LINK_MODE; ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); ++ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); ++ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); ++ ++ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); ++ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); ++ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); ++ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); ++ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); ++ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); ++ ++ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); ++ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, ++ ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); ++ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ return 0; ++} ++ ++static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) ++{ ++ /* ++ * DP1000 does not support sending PME_Turn_Off from the RC. ++ * Keep this callback empty to skip the generic MSG TLP path. ++ */ ++} ++ ++static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { ++ .init = ultrarisc_pcie_host_init, ++ .pme_turn_off = ultrarisc_pcie_pme_turn_off, ++}; ++ ++static int ultrarisc_pcie_start_link(struct dw_pcie *pci) ++{ ++ u32 val; ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val |= LTSSM_ENABLE; ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ return 0; ++} ++ ++static const struct dw_pcie_ops dw_pcie_ops = { ++ .start_link = ultrarisc_pcie_start_link, ++}; ++ ++static int ultrarisc_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct dw_pcie_rp *pp; ++ struct dw_pcie *pci; ++ int ret; ++ ++ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); ++ if (!pci) ++ return -ENOMEM; ++ ++ pci->dev = dev; ++ pci->ops = &dw_pcie_ops; ++ ++ /* Set a default value suitable for at most 16 in and 16 out windows */ ++ pci->atu_size = SZ_8K; ++ ++ pp = &pci->pp; ++ ++ platform_set_drvdata(pdev, pci); ++ ++ pp->num_vectors = MAX_MSI_IRQS; ++ /* No L2/L3 Ready indication is available on this platform */ ++ pp->skip_l23_ready = true; ++ pp->ops = &ultrarisc_pcie_host_ops; ++ ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(dev, "Failed to initialize host\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ultrarisc_pcie_suspend_noirq(struct device *dev) ++{ ++ struct dw_pcie *pci = dev_get_drvdata(dev); ++ ++ return dw_pcie_suspend_noirq(pci); ++} ++ ++static int ultrarisc_pcie_resume_noirq(struct device *dev) ++{ ++ struct dw_pcie *pci = dev_get_drvdata(dev); ++ ++ return dw_pcie_resume_noirq(pci); ++} ++ ++static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { ++ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, ++ ultrarisc_pcie_resume_noirq) ++}; ++ ++static const struct of_device_id ultrarisc_pcie_of_match[] = { ++ { ++ .compatible = "ultrarisc,dp1000-pcie", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); ++ ++static struct platform_driver ultrarisc_pcie_driver = { ++ .driver = { ++ .name = "ultrarisc-pcie", ++ .of_match_table = ultrarisc_pcie_of_match, ++ .suppress_bind_attrs = true, ++ .pm = &ultrarisc_pcie_pm_ops, ++ }, ++ .probe = ultrarisc_pcie_probe, ++}; ++builtin_platform_driver(ultrarisc_pcie_driver); ++ ++MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch deleted file mode 100644 index e2d8d4c7b2..0000000000 --- a/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 7bdcfb039d0ab0b746a0ee44a449149463a7b94e Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 27 Apr 2026 09:32:11 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe - controller - -Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. - -Signed-off-by: Jia Wang -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++++++++++ - MAINTAINERS | 7 ++ - 2 files changed, 100 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml - -diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -new file mode 100644 -index 000000000000..512b935bf5d1 ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: UltraRISC DP1000 PCIe Host Controller -+ -+description: -+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. -+ -+maintainers: -+ - Xincheng Zhang -+ - Jia Wang -+ -+allOf: -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ -+properties: -+ compatible: -+ const: ultrarisc,dp1000-pcie -+ -+ reg: -+ items: -+ - description: Data Bus Interface (DBI) registers. -+ - description: PCIe configuration space region. -+ -+ reg-names: -+ items: -+ - const: dbi -+ - const: config -+ -+ num-lanes: -+ $ref: /schemas/types.yaml#/definitions/uint32 -+ enum: [4, 16] -+ description: Number of lanes to use. -+ -+ interrupts: -+ items: -+ - description: MSI interrupt -+ - description: Legacy INTA interrupt -+ - description: Legacy INTB interrupt -+ - description: Legacy INTC interrupt -+ - description: Legacy INTD interrupt -+ -+ interrupt-names: -+ items: -+ - const: msi -+ - const: inta -+ - const: intb -+ - const: intc -+ - const: intd -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - interrupts -+ - interrupt-names -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@21000000 { -+ compatible = "ultrarisc,dp1000-pcie"; -+ reg = <0x0 0x21000000 0x0 0x01000000>, -+ <0x0 0x4fff0000 0x0 0x00010000>; -+ reg-names = "dbi", "config"; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ }; -diff --git a/MAINTAINERS b/MAINTAINERS -index 1509fa6ab229..a6cbce2ebe1d 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -20076,6 +20076,13 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml - F: drivers/pci/controller/plda/pcie-starfive.c - -+PCIE DRIVER FOR ULTRARISC DP1000 -+M: Xincheng Zhang -+M: Jia Wang -+L: linux-pci@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -+ - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam - L: linux-pci@vger.kernel.org --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0336-UPSTREAM-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux-lts-kmhv2/0336-UPSTREAM-serial-8250_dwlib-move-DesignWare-register-.patch new file mode 100644 index 0000000000..8736009541 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0336-UPSTREAM-serial-8250_dwlib-move-DesignWare-register-.patch @@ -0,0 +1,205 @@ +From 6bc115431a74f3706c15ac3326e475eba1056f47 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:25 +0800 +Subject: [RUYI PATCH] UPSTREAM: serial: 8250_dwlib: move DesignWare register + definitions to header +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move the DW_UART_* register offsets and CPR bit/field definitions from +8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and +8250_dwlib users. + +Add an include guard for 8250_dwlib.h. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Reviewed-by: Ilpo Järvinen +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-1-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 6d7f4890bbb6fc8b70f618aa0407043b32bc738a) +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 11 ----- + drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------- + drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++ + 3 files changed, 67 insertions(+), 60 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 7a0008363543..c5ad459eef01 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -34,22 +34,11 @@ + + #include "8250_dwlib.h" + +-/* Offsets for the DesignWare specific registers */ +-#define DW_UART_USR 0x1f /* UART Status Register */ +-#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ +- + #define OCTEON_UART_USR 0x27 /* UART Status Register */ + + #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ + #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ + +-/* DesignWare specific register fields */ +-#define DW_UART_IIR_IID GENMASK(3, 0) +- +-#define DW_UART_MCR_SIRE BIT(6) +- +-#define DW_UART_USR_BUSY BIT(0) +- + /* Renesas specific register fields */ + #define RZN1_UART_xDMACR_DMA_EN BIT(0) + #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) +diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c +index b055d89cfb39..8859e66d2d71 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.c ++++ b/drivers/tty/serial/8250/8250_dwlib.c +@@ -13,55 +13,6 @@ + + #include "8250_dwlib.h" + +-/* Offsets for the DesignWare specific registers */ +-#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ +-#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ +-#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ +-#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ +-#define DW_UART_RAR 0xc4 /* Receive Address Register */ +-#define DW_UART_TAR 0xc8 /* Transmit Address Register */ +-#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ +-#define DW_UART_CPR 0xf4 /* Component Parameter Register */ +-#define DW_UART_UCV 0xf8 /* UART Component Version */ +- +-/* Receive / Transmit Address Register bits */ +-#define DW_UART_ADDR_MASK GENMASK(7, 0) +- +-/* Line Status Register bits */ +-#define DW_UART_LSR_ADDR_RCVD BIT(8) +- +-/* Transceiver Control Register bits */ +-#define DW_UART_TCR_RS485_EN BIT(0) +-#define DW_UART_TCR_RE_POL BIT(1) +-#define DW_UART_TCR_DE_POL BIT(2) +-#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) +-#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) +-#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) +-#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) +- +-/* Line Extended Control Register bits */ +-#define DW_UART_LCR_EXT_DLS_E BIT(0) +-#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) +-#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) +-#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) +- +-/* Component Parameter Register bits */ +-#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) +-#define DW_UART_CPR_AFCE_MODE BIT(4) +-#define DW_UART_CPR_THRE_MODE BIT(5) +-#define DW_UART_CPR_SIR_MODE BIT(6) +-#define DW_UART_CPR_SIR_LP_MODE BIT(7) +-#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) +-#define DW_UART_CPR_FIFO_ACCESS BIT(9) +-#define DW_UART_CPR_FIFO_STAT BIT(10) +-#define DW_UART_CPR_SHADOW BIT(11) +-#define DW_UART_CPR_ENCODED_PARMS BIT(12) +-#define DW_UART_CPR_DMA_EXTRA BIT(13) +-#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) +- +-/* Helper for FIFO size calculation */ +-#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) +- + /* + * divisor = div(I) + div(F) + * "I" means integer, "F" means fractional +diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h +index 7dd2a8e7b780..2f26f9ecacbe 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.h ++++ b/drivers/tty/serial/8250/8250_dwlib.h +@@ -1,11 +1,76 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* Synopsys DesignWare 8250 library header file. */ + ++#ifndef _SERIAL_8250_DWLIB_H_ ++#define _SERIAL_8250_DWLIB_H_ ++ ++#include ++#include + #include + #include + + #include "8250.h" + ++/* Offsets for the DesignWare specific registers */ ++#define DW_UART_USR 0x1f /* UART Status Register */ ++#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ ++#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ ++#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ ++#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ ++#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ ++#define DW_UART_RAR 0xc4 /* Receive Address Register */ ++#define DW_UART_TAR 0xc8 /* Transmit Address Register */ ++#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ ++#define DW_UART_CPR 0xf4 /* Component Parameter Register */ ++#define DW_UART_UCV 0xf8 /* UART Component Version */ ++ ++/* Interrupt ID Register bits */ ++#define DW_UART_IIR_IID GENMASK(3, 0) ++ ++/* Modem Control Register bits */ ++#define DW_UART_MCR_SIRE BIT(6) ++ ++/* Line Status Register bits */ ++#define DW_UART_LSR_ADDR_RCVD BIT(8) ++ ++/* UART Status Register bits */ ++#define DW_UART_USR_BUSY BIT(0) ++ ++/* Transceiver Control Register bits */ ++#define DW_UART_TCR_RS485_EN BIT(0) ++#define DW_UART_TCR_RE_POL BIT(1) ++#define DW_UART_TCR_DE_POL BIT(2) ++#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) ++#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) ++#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) ++#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) ++ ++/* Receive / Transmit Address Register bits */ ++#define DW_UART_ADDR_MASK GENMASK(7, 0) ++ ++/* Line Extended Control Register bits */ ++#define DW_UART_LCR_EXT_DLS_E BIT(0) ++#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) ++#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) ++#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) ++ ++/* Component Parameter Register bits */ ++#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) ++#define DW_UART_CPR_AFCE_MODE BIT(4) ++#define DW_UART_CPR_THRE_MODE BIT(5) ++#define DW_UART_CPR_SIR_MODE BIT(6) ++#define DW_UART_CPR_SIR_LP_MODE BIT(7) ++#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) ++#define DW_UART_CPR_FIFO_ACCESS BIT(9) ++#define DW_UART_CPR_FIFO_STAT BIT(10) ++#define DW_UART_CPR_SHADOW BIT(11) ++#define DW_UART_CPR_ENCODED_PARMS BIT(12) ++#define DW_UART_CPR_DMA_EXTRA BIT(13) ++#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) ++ ++/* Helper for FIFO size calculation */ ++#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) ++ + struct dw8250_port_data { + /* Port properties */ + int line; +@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) + else + writel(reg, p->membase + offset); + } ++ ++#endif /* _SERIAL_8250_DWLIB_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch deleted file mode 100644 index 520f243b8f..0000000000 --- a/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch +++ /dev/null @@ -1,292 +0,0 @@ -From 4263860bea4eb50e8c9cce4769c096e144fd0400 Mon Sep 17 00:00:00 2001 -From: Xincheng Zhang -Date: Mon, 27 Apr 2026 09:32:12 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root - Complex driver - -Add DP1000 SoC PCIe Root Complex driver. - -The controller only supports 32-bit aligned configuration space accesses. - -Signed-off-by: Xincheng Zhang -Signed-off-by: Jia Wang -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - MAINTAINERS | 1 + - drivers/pci/controller/dwc/Kconfig | 12 ++ - drivers/pci/controller/dwc/Makefile | 1 + - drivers/pci/controller/dwc/pcie-designware.h | 22 +++ - drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++ - 5 files changed, 211 insertions(+) - create mode 100644 drivers/pci/controller/dwc/pcie-ultrarisc.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index a6cbce2ebe1d..996aa3d41e95 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -20082,6 +20082,7 @@ M: Jia Wang - L: linux-pci@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -+F: drivers/pci/controller/dwc/pcie-ultrarisc.c - - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam -diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig -index 718bb54e943f..5e0656eea718 100644 ---- a/drivers/pci/controller/dwc/Kconfig -+++ b/drivers/pci/controller/dwc/Kconfig -@@ -531,4 +531,16 @@ config PCIE_VISCONTI_HOST - Say Y here if you want PCIe controller support on Toshiba Visconti SoC. - This driver supports TMPV7708 SoC. - -+config PCIE_ULTRARISC -+ tristate "UltraRISC PCIe host controller" -+ depends on ARCH_ULTRARISC || COMPILE_TEST -+ select PCIE_DW_HOST -+ select PCI_MSI -+ default y if ARCH_ULTRARISC -+ help -+ Enables support for the PCIe controller in the UltraRISC SoC. -+ This driver supports UR-DP1000 SoC. -+ By default, this symbol is enabled when ARCH_ULTRARISC is active, -+ requiring no further configuration on that platform. -+ - endmenu -diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile -index 662b0a219ddc..39087e7a06d5 100644 ---- a/drivers/pci/controller/dwc/Makefile -+++ b/drivers/pci/controller/dwc/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o - obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o - obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o - obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o -+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o - - # The following drivers are for devices that use the generic ACPI - # pci_root.c driver but don't support standard ECAM config access. -diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h -index 295e113189b7..bd3d35354758 100644 ---- a/drivers/pci/controller/dwc/pcie-designware.h -+++ b/drivers/pci/controller/dwc/pcie-designware.h -@@ -71,6 +71,8 @@ - - /* Synopsys-specific PCIe configuration registers */ - #define PCIE_PORT_FORCE 0x708 -+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ -+#define PORT_LINK_NUM_MASK GENMASK(7, 0) - #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) - - #define PCIE_PORT_AFR 0x70C -@@ -98,6 +100,26 @@ - #define PCIE_PORT_LANE_SKEW 0x714 - #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) - -+/* -+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number -+ * Register. -+ * This register holds the ack frequency, latency, replay, fast link -+ * scaling timers, and max function number values. -+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. -+ * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). -+ * When the LTSSM is in Config or L12 Entry State, 1ms -+ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. -+ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) -+ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) -+ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) -+ */ -+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 -+#define PORT_FLT_SF_MASK GENMASK(30, 29) -+#define PORT_FLT_SF_VAL_1024 0x0 -+#define PORT_FLT_SF_VAL_256 0x1 -+#define PORT_FLT_SF_VAL_64 0x2 -+#define PORT_FLT_SF_VAL_16 0x3 -+ - #define PCIE_PORT_DEBUG0 0x728 - #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f - #define PORT_LOGIC_LTSSM_STATE_L0 0x11 -diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c -new file mode 100644 -index 000000000000..7326bd446590 ---- /dev/null -+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c -@@ -0,0 +1,175 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * DWC PCIe RC driver for UltraRISC SoCs -+ * -+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-designware.h" -+ -+#define PCIE_CUS_CORE 0x400000 -+ -+#define LTSSM_ENABLE BIT(7) -+#define FAST_LINK_MODE BIT(12) -+#define HOLD_PHY_RST BIT(14) -+#define L1SUB_DISABLE BIT(15) -+ -+#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 -+ -+static struct pci_ops ultrarisc_pci_ops = { -+ .map_bus = dw_pcie_own_conf_map_bus, -+ .read = pci_generic_config_read32, -+ .write = pci_generic_config_write32, -+}; -+ -+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ struct pci_host_bridge *bridge = pp->bridge; -+ u8 cap_exp; -+ u32 val; -+ -+ bridge->ops = &ultrarisc_pci_ops; -+ -+ if (dw_pcie_link_up(pci)) -+ return 0; -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val &= ~FAST_LINK_MODE; -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); -+ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); -+ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); -+ -+ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); -+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); -+ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); -+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); -+ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); -+ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); -+ -+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); -+ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, -+ ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); -+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ return 0; -+} -+ -+static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) -+{ -+ /* -+ * DP1000 does not support sending PME_Turn_Off from the RC. -+ * Keep this callback empty to skip the generic MSG TLP path. -+ */ -+} -+ -+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { -+ .init = ultrarisc_pcie_host_init, -+ .pme_turn_off = ultrarisc_pcie_pme_turn_off, -+}; -+ -+static int ultrarisc_pcie_start_link(struct dw_pcie *pci) -+{ -+ u32 val; -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val |= LTSSM_ENABLE; -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ return 0; -+} -+ -+static const struct dw_pcie_ops dw_pcie_ops = { -+ .start_link = ultrarisc_pcie_start_link, -+}; -+ -+static int ultrarisc_pcie_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct dw_pcie_rp *pp; -+ struct dw_pcie *pci; -+ int ret; -+ -+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); -+ if (!pci) -+ return -ENOMEM; -+ -+ pci->dev = dev; -+ pci->ops = &dw_pcie_ops; -+ -+ /* Set a default value suitable for at most 16 in and 16 out windows */ -+ pci->atu_size = SZ_8K; -+ -+ pp = &pci->pp; -+ -+ platform_set_drvdata(pdev, pci); -+ -+ pp->num_vectors = MAX_MSI_IRQS; -+ /* No L2/L3 Ready indication is available on this platform. */ -+ pp->skip_l23_ready = true; -+ pp->ops = &ultrarisc_pcie_host_ops; -+ -+ ret = dw_pcie_host_init(pp); -+ if (ret) { -+ dev_err(dev, "Failed to initialize host\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int ultrarisc_pcie_suspend_noirq(struct device *dev) -+{ -+ struct dw_pcie *pci = dev_get_drvdata(dev); -+ -+ return dw_pcie_suspend_noirq(pci); -+} -+ -+static int ultrarisc_pcie_resume_noirq(struct device *dev) -+{ -+ struct dw_pcie *pci = dev_get_drvdata(dev); -+ -+ return dw_pcie_resume_noirq(pci); -+} -+ -+static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { -+ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, -+ ultrarisc_pcie_resume_noirq) -+}; -+ -+static const struct of_device_id ultrarisc_pcie_of_match[] = { -+ { -+ .compatible = "ultrarisc,dp1000-pcie", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); -+ -+static struct platform_driver ultrarisc_pcie_driver = { -+ .driver = { -+ .name = "ultrarisc-pcie", -+ .of_match_table = ultrarisc_pcie_of_match, -+ .suppress_bind_attrs = true, -+ .pm = &ultrarisc_pcie_pm_ops, -+ }, -+ .probe = ultrarisc_pcie_probe, -+}; -+module_platform_driver(ultrarisc_pcie_driver); -+ -+MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0337-UPSTREAM-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux-lts-kmhv2/0337-UPSTREAM-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch new file mode 100644 index 0000000000..2de45c6c4d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0337-UPSTREAM-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch @@ -0,0 +1,79 @@ +From 8d0349194b40df1005bf8dbe9fc1d88c0c8cd873 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:26 +0800 +Subject: [RUYI PATCH] UPSTREAM: serial: 8250_dw: build Renesas RZN1 CPR value + from DW_UART_CPR_* definitions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace the magic CPR value for Renesas RZ/N1 with a composition using +DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). + +Introduce a helper macro to convert a FIFO size (bytes) into the CPR +FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and +bounds. Use it to replace the literal FIFO_MODE values in the RZN1. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Reviewed-by: Ilpo Järvinen +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-2-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 07bb8459c443b840c55293cee1c726431dd749cf) +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 10 +++++++++- + drivers/tty/serial/8250/8250_dwlib.h | 8 +++++++- + 2 files changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index c5ad459eef01..81848f2696cd 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -937,7 +937,15 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { + + static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { + .usr_reg = DW_UART_USR, +- .cpr_value = 0x00012f32, ++ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | ++ DW_UART_CPR_AFCE_MODE | ++ DW_UART_CPR_THRE_MODE | ++ DW_UART_CPR_ADDITIONAL_FEATURES | ++ DW_UART_CPR_FIFO_ACCESS | ++ DW_UART_CPR_FIFO_STAT | ++ DW_UART_CPR_SHADOW | ++ DW_UART_CPR_DMA_EXTRA | ++ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16), + .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, + }; + +diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h +index 2f26f9ecacbe..1fe52332e774 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.h ++++ b/drivers/tty/serial/8250/8250_dwlib.h +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + #include + +@@ -68,8 +69,13 @@ + #define DW_UART_CPR_DMA_EXTRA BIT(13) + #define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) + +-/* Helper for FIFO size calculation */ ++/* Helpers for FIFO size calculation */ + #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) ++#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \ ++ (FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, \ ++ BUILD_BUG_ON_ZERO((size) > 2048) + \ ++ BUILD_BUG_ON_ZERO((size) % 16) + \ ++ ((size) / 16))) + + struct dw8250_port_data { + /* Port properties */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch deleted file mode 100644 index 43fcf3979b..0000000000 --- a/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch +++ /dev/null @@ -1,199 +0,0 @@ -From 7215c59bd1680f8f694982585919d6ec01c2e009 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:26 +0800 -Subject: [RUYI PATCH] FROMLIST: serial: 8250_dwlib: move DesignWare register - definitions to header - -Move the DW_UART_* register offsets and CPR bit/field definitions from -8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and -8250_dwlib users. - -Add an include guard for 8250_dwlib.h. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-1-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 ----- - drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------- - drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++ - 3 files changed, 67 insertions(+), 60 deletions(-) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index b1f0303aceab..552455b6f51e 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -34,22 +34,11 @@ - - #include "8250_dwlib.h" - --/* Offsets for the DesignWare specific registers */ --#define DW_UART_USR 0x1f /* UART Status Register */ --#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ -- - #define OCTEON_UART_USR 0x27 /* UART Status Register */ - - #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ - #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ - --/* DesignWare specific register fields */ --#define DW_UART_IIR_IID GENMASK(3, 0) -- --#define DW_UART_MCR_SIRE BIT(6) -- --#define DW_UART_USR_BUSY BIT(0) -- - /* Renesas specific register fields */ - #define RZN1_UART_xDMACR_DMA_EN BIT(0) - #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) -diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c -index b055d89cfb39..8859e66d2d71 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.c -+++ b/drivers/tty/serial/8250/8250_dwlib.c -@@ -13,55 +13,6 @@ - - #include "8250_dwlib.h" - --/* Offsets for the DesignWare specific registers */ --#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ --#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ --#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ --#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ --#define DW_UART_RAR 0xc4 /* Receive Address Register */ --#define DW_UART_TAR 0xc8 /* Transmit Address Register */ --#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ --#define DW_UART_CPR 0xf4 /* Component Parameter Register */ --#define DW_UART_UCV 0xf8 /* UART Component Version */ -- --/* Receive / Transmit Address Register bits */ --#define DW_UART_ADDR_MASK GENMASK(7, 0) -- --/* Line Status Register bits */ --#define DW_UART_LSR_ADDR_RCVD BIT(8) -- --/* Transceiver Control Register bits */ --#define DW_UART_TCR_RS485_EN BIT(0) --#define DW_UART_TCR_RE_POL BIT(1) --#define DW_UART_TCR_DE_POL BIT(2) --#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) --#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) --#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) --#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) -- --/* Line Extended Control Register bits */ --#define DW_UART_LCR_EXT_DLS_E BIT(0) --#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) --#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) --#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) -- --/* Component Parameter Register bits */ --#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) --#define DW_UART_CPR_AFCE_MODE BIT(4) --#define DW_UART_CPR_THRE_MODE BIT(5) --#define DW_UART_CPR_SIR_MODE BIT(6) --#define DW_UART_CPR_SIR_LP_MODE BIT(7) --#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) --#define DW_UART_CPR_FIFO_ACCESS BIT(9) --#define DW_UART_CPR_FIFO_STAT BIT(10) --#define DW_UART_CPR_SHADOW BIT(11) --#define DW_UART_CPR_ENCODED_PARMS BIT(12) --#define DW_UART_CPR_DMA_EXTRA BIT(13) --#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) -- --/* Helper for FIFO size calculation */ --#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -- - /* - * divisor = div(I) + div(F) - * "I" means integer, "F" means fractional -diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h -index 7dd2a8e7b780..2f26f9ecacbe 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.h -+++ b/drivers/tty/serial/8250/8250_dwlib.h -@@ -1,11 +1,76 @@ - /* SPDX-License-Identifier: GPL-2.0+ */ - /* Synopsys DesignWare 8250 library header file. */ - -+#ifndef _SERIAL_8250_DWLIB_H_ -+#define _SERIAL_8250_DWLIB_H_ -+ -+#include -+#include - #include - #include - - #include "8250.h" - -+/* Offsets for the DesignWare specific registers */ -+#define DW_UART_USR 0x1f /* UART Status Register */ -+#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ -+#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ -+#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ -+#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ -+#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ -+#define DW_UART_RAR 0xc4 /* Receive Address Register */ -+#define DW_UART_TAR 0xc8 /* Transmit Address Register */ -+#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ -+#define DW_UART_CPR 0xf4 /* Component Parameter Register */ -+#define DW_UART_UCV 0xf8 /* UART Component Version */ -+ -+/* Interrupt ID Register bits */ -+#define DW_UART_IIR_IID GENMASK(3, 0) -+ -+/* Modem Control Register bits */ -+#define DW_UART_MCR_SIRE BIT(6) -+ -+/* Line Status Register bits */ -+#define DW_UART_LSR_ADDR_RCVD BIT(8) -+ -+/* UART Status Register bits */ -+#define DW_UART_USR_BUSY BIT(0) -+ -+/* Transceiver Control Register bits */ -+#define DW_UART_TCR_RS485_EN BIT(0) -+#define DW_UART_TCR_RE_POL BIT(1) -+#define DW_UART_TCR_DE_POL BIT(2) -+#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) -+#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) -+#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) -+#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) -+ -+/* Receive / Transmit Address Register bits */ -+#define DW_UART_ADDR_MASK GENMASK(7, 0) -+ -+/* Line Extended Control Register bits */ -+#define DW_UART_LCR_EXT_DLS_E BIT(0) -+#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) -+#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) -+#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) -+ -+/* Component Parameter Register bits */ -+#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) -+#define DW_UART_CPR_AFCE_MODE BIT(4) -+#define DW_UART_CPR_THRE_MODE BIT(5) -+#define DW_UART_CPR_SIR_MODE BIT(6) -+#define DW_UART_CPR_SIR_LP_MODE BIT(7) -+#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) -+#define DW_UART_CPR_FIFO_ACCESS BIT(9) -+#define DW_UART_CPR_FIFO_STAT BIT(10) -+#define DW_UART_CPR_SHADOW BIT(11) -+#define DW_UART_CPR_ENCODED_PARMS BIT(12) -+#define DW_UART_CPR_DMA_EXTRA BIT(13) -+#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) -+ -+/* Helper for FIFO size calculation */ -+#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -+ - struct dw8250_port_data { - /* Port properties */ - int line; -@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) - else - writel(reg, p->membase + offset); - } -+ -+#endif /* _SERIAL_8250_DWLIB_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0338-UPSTREAM-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux-lts-kmhv2/0338-UPSTREAM-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch new file mode 100644 index 0000000000..96e947321d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0338-UPSTREAM-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch @@ -0,0 +1,35 @@ +From 964cdf57a956fa7a689e12f1066079b71ed7e916 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:27 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: snps-dw-apb-uart: Add + UltraRISC DP1000 UART + +UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does +not provide the standard CPR and UCV registers. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Reviewed-by: Andy Shevchenko +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit d22d2e54f660eeb64e06f2cb6db068dac66a5733) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +index cb9da6c97afc..4ed637df0186 100644 +--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml ++++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +@@ -75,6 +75,7 @@ properties: + - starfive,jh7100-hsuart + - starfive,jh7100-uart + - starfive,jh7110-uart ++ - ultrarisc,dp1000-uart + - const: snps,dw-apb-uart + - const: snps,dw-apb-uart + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch deleted file mode 100644 index 361bfc6547..0000000000 --- a/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 6180d1c44da7f8a61ffe42b1aa5f7fed0db947c5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:27 +0800 -Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR value - from DW_UART_CPR_* definitions - -Replace the magic CPR value for Renesas RZ/N1 with a composition using -DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). - -Introduce a helper macro to convert a FIFO size (bytes) into the CPR -FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and -bounds. Use it to replace the literal FIFO_MODE values in the RZN1. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-2-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 ++++++++++- - drivers/tty/serial/8250/8250_dwlib.h | 7 +++++++ - 2 files changed, 17 insertions(+), 1 deletion(-) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 552455b6f51e..57c037f19951 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -935,7 +935,16 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { - - static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { - .usr_reg = DW_UART_USR, -- .cpr_value = 0x00012f32, -+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | -+ DW_UART_CPR_AFCE_MODE | -+ DW_UART_CPR_THRE_MODE | -+ DW_UART_CPR_ADDITIONAL_FEATURES | -+ DW_UART_CPR_FIFO_ACCESS | -+ DW_UART_CPR_FIFO_STAT | -+ DW_UART_CPR_SHADOW | -+ DW_UART_CPR_DMA_EXTRA | -+ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, -+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16)), - .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, - }; - -diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h -index 2f26f9ecacbe..c1f87cd42ecc 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.h -+++ b/drivers/tty/serial/8250/8250_dwlib.h -@@ -6,6 +6,8 @@ - - #include - #include -+#include -+#include - #include - #include - -@@ -70,6 +72,11 @@ - - /* Helper for FIFO size calculation */ - #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -+#define DW_UART_CPR_FIFO_MODE_MAX 0x80 -+#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \ -+ (BUILD_BUG_ON_ZERO(!IS_ALIGNED((size), 16)) + \ -+ BUILD_BUG_ON_ZERO(((size) / 16) > DW_UART_CPR_FIFO_MODE_MAX) + \ -+ ((size) / 16)) - - struct dw8250_port_data { - /* Port properties */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0339-UPSTREAM-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux-lts-kmhv2/0339-UPSTREAM-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch new file mode 100644 index 0000000000..313bdf66bb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0339-UPSTREAM-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch @@ -0,0 +1,57 @@ +From c3ece7b6088ef015d4826bd725453df7480e087a Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:28 +0800 +Subject: [RUYI PATCH] UPSTREAM: serial: 8250_dw: Use a fixed CPR value for + UltraRISC DP1000 UART +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The UltraRISC DP1000 UART does not provide the standard CPR register used +by 8250_dw to discover port capabilities. + +Provide a fixed CPR value for the DP1000-specific compatible so the +driver can configure the port correctly. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Reviewed-by: Ilpo Järvinen +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-4-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 4a9a0b1a82a8b23eb68032dd19b120e82cd67004) +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 81848f2696cd..9c1ff564e09d 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -959,6 +959,15 @@ static const struct dw8250_platform_data dw8250_intc10ee = { + .quirks = DW_UART_QUIRK_IER_KICK, + }; + ++static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { ++ .usr_reg = DW_UART_USR, ++ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | ++ DW_UART_CPR_THRE_MODE | ++ DW_UART_CPR_DMA_EXTRA | ++ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32), ++ .quirks = DW_UART_QUIRK_CPR_VALUE, ++}; ++ + static const struct of_device_id dw8250_of_match[] = { + { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, + { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, +@@ -966,6 +975,7 @@ static const struct of_device_id dw8250_of_match[] = { + { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, + { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, ++ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, + { /* Sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dw8250_of_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch deleted file mode 100644 index 2d2f322fc8..0000000000 --- a/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0b0183bf49240d8f6c2d66b6eaff2fe17c541d19 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:28 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add - UltraRISC DP1000 UART - -UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does -not provide the standard CPR and UCV registers. - -Signed-off-by: Jia Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-3-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -index cb9da6c97afc..4ed637df0186 100644 ---- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -@@ -75,6 +75,7 @@ properties: - - starfive,jh7100-hsuart - - starfive,jh7100-uart - - starfive,jh7110-uart -+ - ultrarisc,dp1000-uart - - const: snps,dw-apb-uart - - const: snps,dw-apb-uart - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0340-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts-kmhv2/0340-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch new file mode 100644 index 0000000000..f6b4b4f799 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0340-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -0,0 +1,39 @@ +From 1bcfb5adfc0e60be3c2f53a6fd1886e7d18d9968 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:14 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter for + OrangePi RV2 + +The adapter is used to access the SpacemiT P1 PMIC present in this board. + +Tested-by: Vincent Legoll # OrangePi-RV2 +Signed-off-by: Han Gao +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Yixun Lan +(cherry picked from commit ece83d42785e12ab7690c0c13b416baf46a74063) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 7b7331cb3c72..57ec1cc32b03 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -87,6 +87,12 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch deleted file mode 100644 index 710885bf79..0000000000 --- a/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 07e647f6d38a2395768391b1126d6af257685679 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:29 +0800 -Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: Use a fixed CPR value for - UltraRISC DP1000 UART - -The UltraRISC DP1000 UART does not provide the standard CPR register used -by 8250_dw to discover port capabilities. - -Provide a fixed CPR value for the DP1000-specific compatible so the -driver can configure the port correctly. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-4-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 57c037f19951..a13fde96efd9 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -958,6 +958,16 @@ static const struct dw8250_platform_data dw8250_intc10ee = { - .quirks = DW_UART_QUIRK_IER_KICK, - }; - -+static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { -+ .usr_reg = DW_UART_USR, -+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | -+ DW_UART_CPR_THRE_MODE | -+ DW_UART_CPR_DMA_EXTRA | -+ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, -+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32)), -+ .quirks = DW_UART_QUIRK_CPR_VALUE, -+}; -+ - static const struct of_device_id dw8250_of_match[] = { - { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, - { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, -@@ -965,6 +975,7 @@ static const struct of_device_id dw8250_of_match[] = { - { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, - { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, - { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, -+ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, - { /* Sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dw8250_of_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0341-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts-kmhv2/0341-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch new file mode 100644 index 0000000000..2bf6e157aa --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0341-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -0,0 +1,175 @@ +From 38d4eec31f7970169c13d50f1af3d12ce1ef7ee3 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC + regulators for OrangePi RV2 + +Define the DC power input and the 4v power as fixed regulator supplies. + +Define the SpacemiT P1 PMIC voltage regulators and their constraints. + +Co-developed-by: Chukun Pan +Signed-off-by: Chukun Pan +Tested-by: Vincent Legoll # OrangePi-RV2 +Signed-off-by: Han Gao +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Yixun Lan +(cherry picked from commit c02c047b925c0ed101ec6834e1c07a53a45f98d4) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ + 1 file changed, 131 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 57ec1cc32b03..f7a1dadaa95f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -23,6 +23,25 @@ chosen { + stdout-path = "serial0"; + }; + ++ vcc_5v0: regulator-vcc-5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_5v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc4v0: regulator-vcc4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -91,6 +110,118 @@ &i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <&vcc4v0>; ++ vin2-supply = <&vcc4v0>; ++ vin3-supply = <&vcc4v0>; ++ vin4-supply = <&vcc4v0>; ++ vin5-supply = <&vcc4v0>; ++ vin6-supply = <&vcc4v0>; ++ aldoin-supply = <&vcc4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ /* not connected */ ++ }; ++ ++ aldo3 { ++ /* not connected */ ++ }; ++ ++ aldo4 { ++ /* not connected */ ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ /* not connected */ ++ }; ++ ++ dldo3 { ++ /* not connected */ ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ /* not connected */ ++ }; ++ }; ++ }; + }; + + &uart0 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch deleted file mode 100644 index e964c8cfd5..0000000000 --- a/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 53a9a6f9561ecf77c64e14e718b3c6677e450356 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Tue, 17 Mar 2026 16:48:06 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other - CPUs before reboot/shutdown - -Currently, the RISC-V implementation of machine_restart(), machine_halt(), -and machine_power_off() invokes the kernel teardown chains (e.g., -do_kernel_restart()) with local interrupts enabled and other CPUs still -running. - -This implementation fails to provide a deterministic execution environment -for registered handlers in the restart or power-off notifier chains. These -chains are intended to be executed in a strict atomic and single-threaded -context. - -Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increment -the preempt_count. If local interrupts remain enabled, the environment -is not guaranteed to be atomic. This can lead to a context misidentification -within generic kernel teardown code, causing it to incorrectly enter -non-atomic paths (such as attempting to acquire sleeping locks), which -results in fatal "scheduling while atomic" splats or system hangs. - -Additionally, stopping other CPUs ensures the primary CPU has exclusive -access to the hardware state during the final teardown phase, preventing -unpredictable interference from other active cores. - -Align RISC-V with other major architectures by disabling local interrupts -and stopping other CPUs at the beginning of the shutdown sequences. This -guarantees the architectural expectations of the kernel's restart and -power-off handlers are met. - -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Link: https://lore.kernel.org/all/abEP80FoCn4S4-WG@aurel32.net/ [1] -Link: https://lore.kernel.org/r/20260317-v7-0-rc1-rv-dis-int-before-restart-v2-1-0ecc85fbb7ff@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/reset.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c -index 912288572226..8c48466c50e9 100644 ---- a/arch/riscv/kernel/reset.c -+++ b/arch/riscv/kernel/reset.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - - static void default_power_off(void) - { -@@ -17,18 +18,27 @@ EXPORT_SYMBOL(pm_power_off); - - void machine_restart(char *cmd) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_restart(cmd); - while (1); - } - - void machine_halt(void) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_power_off(); - default_power_off(); - } - - void machine_power_off(void) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_power_off(); - default_power_off(); - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0342-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux-lts-kmhv2/0342-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch new file mode 100644 index 0000000000..43acbe1d5e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0342-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch @@ -0,0 +1,144 @@ +From 4636f951d781851a6b27a746ff2dbd8fbe8f560c Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable USB3.0/PCIe on + OrangePi RV2 + +Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the +OrangePi RV2 board. + +The board utilizes a Genesys Logic GL3523 USB3.0 hub. + +Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and +PHY-related Device Tree nodes for the OrangePi RV2. + +Co-developed-by: Chukun Pan +Signed-off-by: Chukun Pan +Tested-by: Vincent Legoll # OrangePi-RV2 +Signed-off-by: Han Gao +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Yixun Lan +(cherry picked from commit e3e433dd9aa04448f8f98d59359cab1340d994a3) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ + 1 file changed, 80 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index f7a1dadaa95f..3a829e3c9cbc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -23,6 +23,16 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; +@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { + vin-supply = <&vcc_5v0>; + }; + ++ vcc5v0_usb30: regulator-vcc5v0-usb30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc5v0_usb30"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -54,6 +74,10 @@ led1 { + }; + }; + ++&combo_phy { ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -224,8 +248,64 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ vbus-supply = <&vcc5v0_usb30>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb5e3,610"; ++ reg = <0x1>; ++ peer-hub = <&hub_3_0>; ++ vdd-supply = <&vcc_5v0>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb5e3,620"; ++ reg = <0x2>; ++ peer-hub = <&hub_2_0>; ++ vdd-supply = <&vcc_5v0>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch deleted file mode 100644 index baf487668c..0000000000 --- a/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch +++ /dev/null @@ -1,39 +0,0 @@ -From c3dbfd57b9930def2f6e386d4a107127d798a89e Mon Sep 17 00:00:00 2001 -From: Felix Gu -Date: Sat, 21 Mar 2026 03:12:10 +0800 -Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on - dw_hdmi_probe() return value - -The error check after calling dw_hdmi_probe() was incorrectly checking -the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. - -Fix this by checking the correct variable. - -Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") -Signed-off-by: Felix Gu -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260321-th1520-v1-1-ec877197770d@gmail.com -Signed-off-by: Han Gao ---- - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -index 389eead5f1c4..c9968ec1823c 100644 ---- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -136,8 +136,8 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) - plat_data->priv_data = hdmi; - - hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); -- if (IS_ERR(hdmi)) -- return PTR_ERR(hdmi); -+ if (IS_ERR(hdmi->dw_hdmi)) -+ return PTR_ERR(hdmi->dw_hdmi); - - platform_set_drvdata(pdev, hdmi); - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0343-UPSTREAM-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux-lts-kmhv2/0343-UPSTREAM-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch new file mode 100644 index 0000000000..2dcb9913c0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0343-UPSTREAM-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch @@ -0,0 +1,42 @@ +From fa38bd5eff505e05e5dbc55b313c820b0bc332ed Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: dmaengine: Add SpacemiT K3 DMA + compatible string + +Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. + +While the K3 PDMA IP reuses most of the design found on the earlier +K1 SoC, a new compatible string is required because the DRCMR +(DMA Request/Command Register) base address for extended DMA request +numbers (>= 64) differs from the K1 implementation. + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Vinod Koul +(cherry picked from commit 55620b11186c81757b05fb8e2df9ddc7127d6fd2) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +index ec06235baf5c..62ce6d81526b 100644 +--- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml ++++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +@@ -14,7 +14,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-pdma ++ enum: ++ - spacemit,k1-pdma ++ - spacemit,k3-pdma + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch deleted file mode 100644 index 107fa9a940..0000000000 --- a/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch +++ /dev/null @@ -1,43 +0,0 @@ -From e4498bef7d35202c1d4fff03e1f738c01c63141b Mon Sep 17 00:00:00 2001 -From: Felix Gu -Date: Sat, 21 Mar 2026 03:12:11 +0800 -Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() - callback - -This driver stores struct th1520_hdmi * in platform drvdata, but -th1520_dw_hdmi_remove() was reading it back as struct dw_hdmi * -and passing it to dw_hdmi_remove(), so teardown runs on the wrong -pointer. - -Retrieve struct th1520_hdmi * from platform drvdata and pass -hdmi->dw_hdmi to dw_hdmi_remove(). - -Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") -Signed-off-by: Felix Gu -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260321-th1520-v1-2-ec877197770d@gmail.com -Signed-off-by: Han Gao ---- - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -index c9968ec1823c..6ec9003a8f3f 100644 ---- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -146,9 +146,9 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) - - static void th1520_dw_hdmi_remove(struct platform_device *pdev) - { -- struct dw_hdmi *hdmi = platform_get_drvdata(pdev); -+ struct th1520_hdmi *hdmi = platform_get_drvdata(pdev); - -- dw_hdmi_remove(hdmi); -+ dw_hdmi_remove(hdmi->dw_hdmi); - } - - static const struct of_device_id th1520_dw_hdmi_of_table[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0344-UPSTREAM-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux-lts-kmhv2/0344-UPSTREAM-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch new file mode 100644 index 0000000000..cd6a75207e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0344-UPSTREAM-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch @@ -0,0 +1,102 @@ +From 18cd7af49f8e0c1a02283d85c51d3eafbb445e5c Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: dmaengine: mmp_pdma: refactor DRCMR access + with helper function + +Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() +to support variable extended DRCMR base addresses across different PDMA +implementations, such as SpacemiT K3. + +Signed-off-by: Guodong Xu +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Vinod Koul +(cherry picked from commit f46b47623e70dea8b03794a5420ffba060425e85) +Signed-off-by: Han Gao +--- + drivers/dma/mmp_pdma.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c +index d12e729ee12c..6112369006ee 100644 +--- a/drivers/dma/mmp_pdma.c ++++ b/drivers/dma/mmp_pdma.c +@@ -51,7 +51,9 @@ + #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ + #define DCSR_EORINTR BIT(9) /* The end of Receive */ + +-#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) ++#define DRCMR_BASE 0x0100 ++#define DRCMR_EXT_BASE_DEFAULT 0x1100 ++#define DRCMR_REQ_LIMIT 64 + #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ + #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ + +@@ -154,6 +156,7 @@ struct mmp_pdma_phy { + * @run_bits: Control bits in DCSR register for channel start/stop + * @dma_width: DMA addressing width in bits (32 or 64). Determines the + * DMA mask capability of the controller hardware. ++ * @drcmr_ext_base: Base DRCMR address for extended requests + */ + struct mmp_pdma_ops { + /* Hardware Register Operations */ +@@ -174,6 +177,7 @@ struct mmp_pdma_ops { + /* Controller Configuration */ + u32 run_bits; + u32 dma_width; ++ u32 drcmr_ext_base; + }; + + struct mmp_pdma_device { +@@ -195,6 +199,13 @@ struct mmp_pdma_device { + #define to_mmp_pdma_dev(dmadev) \ + container_of(dmadev, struct mmp_pdma_device, device) + ++static u32 mmp_pdma_get_drcmr(struct mmp_pdma_device *pdev, u32 drcmr) ++{ ++ if (drcmr < DRCMR_REQ_LIMIT) ++ return DRCMR_BASE + (drcmr << 2); ++ return pdev->ops->drcmr_ext_base + ((drcmr - DRCMR_REQ_LIMIT) << 2); ++} ++ + /* For 32-bit PDMA */ + static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) + { +@@ -301,7 +312,7 @@ static void enable_chan(struct mmp_pdma_phy *phy) + + pdev = to_mmp_pdma_dev(phy->vchan->chan.device); + +- reg = DRCMR(phy->vchan->drcmr); ++ reg = mmp_pdma_get_drcmr(pdev, phy->vchan->drcmr); + writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); + + dalgn = readl(phy->base + DALGN); +@@ -437,7 +448,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) + return; + + /* clear the channel mapping in DRCMR */ +- reg = DRCMR(pchan->drcmr); ++ reg = mmp_pdma_get_drcmr(pdev, pchan->drcmr); + writel(0, pchan->phy->base + reg); + + spin_lock_irqsave(&pdev->phy_lock, flags); +@@ -1179,6 +1190,7 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = { + .get_desc_dst_addr = get_desc_dst_addr_32, + .run_bits = (DCSR_RUN), + .dma_width = 32, ++ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + + static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { +@@ -1192,6 +1204,7 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { + .get_desc_dst_addr = get_desc_dst_addr_64, + .run_bits = (DCSR_RUN | DCSR_LPAEEN), + .dma_width = 64, ++ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + + static const struct of_device_id mmp_pdma_dt_ids[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch deleted file mode 100644 index f320d51fd9..0000000000 --- a/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From b6fedd583f0486d6ff23a73e611445adac11b2b7 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:14 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter for - OrangePi RV2 - -The adapter is used to access the SpacemiT P1 PMIC present in this board. - -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 7b7331cb3c72..57ec1cc32b03 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -87,6 +87,12 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0345-UPSTREAM-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux-lts-kmhv2/0345-UPSTREAM-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch new file mode 100644 index 0000000000..b9220ead09 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0345-UPSTREAM-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch @@ -0,0 +1,65 @@ +From 6708ff1446d61d3031a99d79e08375f9bafa58b8 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: dmaengine: mmp_pdma: add SpacemiT K3 support + +SpacemiT K3 reuses most of the PDMA IP design found on K1, with one +difference being the extended DRCMR base address. Add "spacemit,k3-pdma" +compatible string and define a new mmp_pdma_ops for K3 PDMA. + +Signed-off-by: Guodong Xu +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Vinod Koul +(cherry picked from commit 6587b8661a0b61c2f4b260bfc9f0e9ef9de0ea2e) +Signed-off-by: Han Gao +--- + drivers/dma/mmp_pdma.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c +index 6112369006ee..386e85cd4882 100644 +--- a/drivers/dma/mmp_pdma.c ++++ b/drivers/dma/mmp_pdma.c +@@ -52,6 +52,7 @@ + #define DCSR_EORINTR BIT(9) /* The end of Receive */ + + #define DRCMR_BASE 0x0100 ++#define DRCMR_EXT_BASE_K3 0x1000 + #define DRCMR_EXT_BASE_DEFAULT 0x1100 + #define DRCMR_REQ_LIMIT 64 + #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ +@@ -1207,6 +1208,20 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { + .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + ++static const struct mmp_pdma_ops spacemit_k3_pdma_ops = { ++ .write_next_addr = write_next_addr_64, ++ .read_src_addr = read_src_addr_64, ++ .read_dst_addr = read_dst_addr_64, ++ .set_desc_next_addr = set_desc_next_addr_64, ++ .set_desc_src_addr = set_desc_src_addr_64, ++ .set_desc_dst_addr = set_desc_dst_addr_64, ++ .get_desc_src_addr = get_desc_src_addr_64, ++ .get_desc_dst_addr = get_desc_dst_addr_64, ++ .run_bits = (DCSR_RUN | DCSR_LPAEEN | DCSR_EORIRQEN | DCSR_EORSTOPEN), ++ .dma_width = 64, ++ .drcmr_ext_base = DRCMR_EXT_BASE_K3, ++}; ++ + static const struct of_device_id mmp_pdma_dt_ids[] = { + { + .compatible = "marvell,pdma-1.0", +@@ -1214,6 +1229,9 @@ static const struct of_device_id mmp_pdma_dt_ids[] = { + }, { + .compatible = "spacemit,k1-pdma", + .data = &spacemit_k1_pdma_ops ++ }, { ++ .compatible = "spacemit,k3-pdma", ++ .data = &spacemit_k3_pdma_ops + }, { + /* sentinel */ + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch deleted file mode 100644 index d8cc2b7e7f..0000000000 --- a/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ /dev/null @@ -1,171 +0,0 @@ -From 8a8b83695e5206dc768419823d357d36066dcc1a Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:15 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC - regulators for OrangePi RV2 - -Define the DC power input and the 4v power as fixed regulator supplies. - -Define the SpacemiT P1 PMIC voltage regulators and their constraints. - -Co-developed-by: Chukun Pan -Signed-off-by: Chukun Pan -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ - 1 file changed, 131 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 57ec1cc32b03..f7a1dadaa95f 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -23,6 +23,25 @@ chosen { - stdout-path = "serial0"; - }; - -+ vcc_5v0: regulator-vcc-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc4v0: regulator-vcc4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -91,6 +110,118 @@ &i2c8 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_cfg>; - status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <&vcc4v0>; -+ vin2-supply = <&vcc4v0>; -+ vin3-supply = <&vcc4v0>; -+ vin4-supply = <&vcc4v0>; -+ vin5-supply = <&vcc4v0>; -+ vin6-supply = <&vcc4v0>; -+ aldoin-supply = <&vcc4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4_3v3: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ /* not connected */ -+ }; -+ -+ aldo3 { -+ /* not connected */ -+ }; -+ -+ aldo4 { -+ /* not connected */ -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ /* not connected */ -+ }; -+ -+ dldo3 { -+ /* not connected */ -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ /* not connected */ -+ }; -+ }; -+ }; - }; - - &uart0 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0346-UPSTREAM-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux-lts-kmhv2/0346-UPSTREAM-riscv-dts-spacemit-Add-PDMA-controller-node.patch new file mode 100644 index 0000000000..8a11de676f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0346-UPSTREAM-riscv-dts-spacemit-Add-PDMA-controller-node.patch @@ -0,0 +1,50 @@ +From 3f07b7f3337da5b321d0c0c16c56aad0a3d46f7e Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Mon, 18 May 2026 11:32:44 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add PDMA controller node + for K3 SoC + +Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. +The PDMA controller provides general-purpose DMA capabilities for various +peripheral devices across the system to offload CPU data transfers. + +Unlike the previous K1 SoC, where some DMA masters had memory addressing +limitations (e.g. restricted to the 0-4GB space) requiring a dedicated +dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters +have full memory addressing capabilities. Therefore, the PDMA node is now +instantiated directly under the main soc bus. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Yixun Lan +(cherry picked from commit 3f47ca8bb3c3f4a71688451a0cb7350d3e1e1059) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 815debd16409..01124ff429a2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -555,6 +555,17 @@ gmac2_axi_setup: stmmac-axi-config { + }; + }; + ++ pdma: dma-controller@d4000000 { ++ compatible = "spacemit,k3-pdma"; ++ reg = <0x0 0xd4000000 0x0 0x4000>; ++ clocks = <&syscon_apmu CLK_APMU_DMA>; ++ resets = <&syscon_apmu RESET_APMU_DMA>; ++ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; ++ dma-channels = <16>; ++ #dma-cells = <1>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@d4010800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch deleted file mode 100644 index 2eece049ed..0000000000 --- a/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch +++ /dev/null @@ -1,140 +0,0 @@ -From be6360dcda59815d23e91c2273c7af8ee688b197 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:16 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on - OrangePi RV2 - -Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the -OrangePi RV2 board. - -The board utilizes a Genesys Logic GL3523 USB3.0 hub. - -Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and -PHY-related Device Tree nodes for the OrangePi RV2. - -Co-developed-by: Chukun Pan -Signed-off-by: Chukun Pan -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ - 1 file changed, 80 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index f7a1dadaa95f..3a829e3c9cbc 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -23,6 +23,16 @@ chosen { - stdout-path = "serial0"; - }; - -+ pcie_vcc3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - vcc_5v0: regulator-vcc-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; -@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { - vin-supply = <&vcc_5v0>; - }; - -+ vcc5v0_usb30: regulator-vcc5v0-usb30 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb30"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -54,6 +74,10 @@ led1 { - }; - }; - -+&combo_phy { -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; -@@ -224,8 +248,64 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie2 { -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vbus-supply = <&vcc5v0_usb30>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb5e3,610"; -+ reg = <0x1>; -+ peer-hub = <&hub_3_0>; -+ vdd-supply = <&vcc_5v0>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb5e3,620"; -+ reg = <0x2>; -+ peer-hub = <&hub_2_0>; -+ vdd-supply = <&vcc_5v0>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0347-UPSTREAM-dt-bindings-PCI-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux-lts-kmhv2/0347-UPSTREAM-dt-bindings-PCI-sophgo-Add-dma-coherent-pro.patch new file mode 100644 index 0000000000..d19a362af1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0347-UPSTREAM-dt-bindings-PCI-sophgo-Add-dma-coherent-pro.patch @@ -0,0 +1,43 @@ +From 1040b342d286dc0a6a7e0ae1d58ba8702ed96d32 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:12:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: PCI: sophgo: Add dma-coherent + property for SG2042 + +Add dma-coherent as an allowed property in the SG2042 PCIe host controller +binding. SG2042's PCIe Root Complexes are cache-coherent with the CPU. + +Signed-off-by: Han Gao +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Acked-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260331171248.973014-2-gaohan@iscas.ac.cn +(cherry picked from commit c6d51515ee0b79a52b7e532b6b20067fa0cec96f) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +index f8b7ca57fff1..ab482488b047 100644 +--- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml ++++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +@@ -30,6 +30,8 @@ properties: + device-id: + const: 0x2042 + ++ dma-coherent: true ++ + msi-parent: true + + allOf: +@@ -60,5 +62,6 @@ examples: + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch deleted file mode 100644 index ec194d2c76..0000000000 --- a/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 35352343154bd3b77a7ce708b33610ead4fa645b Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:41 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA - compatible string - -Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. - -While the K3 PDMA IP reuses most of the design found on the earlier -K1 SoC, a new compatible string is required because the DRCMR -(DMA Request/Command Register) base address for extended DMA request -numbers (>= 64) differs from the K1 implementation. - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -index ec06235baf5c..62ce6d81526b 100644 ---- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -+++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -@@ -14,7 +14,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-pdma -+ enum: -+ - spacemit,k1-pdma -+ - spacemit,k3-pdma - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0348-UPSTREAM-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux-lts-kmhv2/0348-UPSTREAM-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch new file mode 100644 index 0000000000..4c4b3c944b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0348-UPSTREAM-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch @@ -0,0 +1,61 @@ +From 051562e4456c9fc4ee03ac5d0f4cbfd785d943c0 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:12:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Add dma-coherent to SG2042 + PCIe controllers + +SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all +four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent +so the kernel uses coherent DMA mappings instead of non-coherent bounce +buffering. + +Cc: stable@vger.kernel.org +Signed-off-by: Han Gao +Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit 2647eabde8de748ee2c9a2816615d4af3bd4bf9d) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index 9fddf3f0b3b9..3af770549742 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch deleted file mode 100644 index 2671371cc9..0000000000 --- a/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 086a8550aad82551854f105777656e655e68512f Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:42 +0800 -Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access - with helper function - -Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() -to support variable extended DRCMR base addresses across different PDMA -implementations, such as SpacemiT K3. - -Signed-off-by: Guodong Xu -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/dma/mmp_pdma.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - -diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c -index d12e729ee12c..6112369006ee 100644 ---- a/drivers/dma/mmp_pdma.c -+++ b/drivers/dma/mmp_pdma.c -@@ -51,7 +51,9 @@ - #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ - #define DCSR_EORINTR BIT(9) /* The end of Receive */ - --#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) -+#define DRCMR_BASE 0x0100 -+#define DRCMR_EXT_BASE_DEFAULT 0x1100 -+#define DRCMR_REQ_LIMIT 64 - #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ - #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ - -@@ -154,6 +156,7 @@ struct mmp_pdma_phy { - * @run_bits: Control bits in DCSR register for channel start/stop - * @dma_width: DMA addressing width in bits (32 or 64). Determines the - * DMA mask capability of the controller hardware. -+ * @drcmr_ext_base: Base DRCMR address for extended requests - */ - struct mmp_pdma_ops { - /* Hardware Register Operations */ -@@ -174,6 +177,7 @@ struct mmp_pdma_ops { - /* Controller Configuration */ - u32 run_bits; - u32 dma_width; -+ u32 drcmr_ext_base; - }; - - struct mmp_pdma_device { -@@ -195,6 +199,13 @@ struct mmp_pdma_device { - #define to_mmp_pdma_dev(dmadev) \ - container_of(dmadev, struct mmp_pdma_device, device) - -+static u32 mmp_pdma_get_drcmr(struct mmp_pdma_device *pdev, u32 drcmr) -+{ -+ if (drcmr < DRCMR_REQ_LIMIT) -+ return DRCMR_BASE + (drcmr << 2); -+ return pdev->ops->drcmr_ext_base + ((drcmr - DRCMR_REQ_LIMIT) << 2); -+} -+ - /* For 32-bit PDMA */ - static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) - { -@@ -301,7 +312,7 @@ static void enable_chan(struct mmp_pdma_phy *phy) - - pdev = to_mmp_pdma_dev(phy->vchan->chan.device); - -- reg = DRCMR(phy->vchan->drcmr); -+ reg = mmp_pdma_get_drcmr(pdev, phy->vchan->drcmr); - writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); - - dalgn = readl(phy->base + DALGN); -@@ -437,7 +448,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) - return; - - /* clear the channel mapping in DRCMR */ -- reg = DRCMR(pchan->drcmr); -+ reg = mmp_pdma_get_drcmr(pdev, pchan->drcmr); - writel(0, pchan->phy->base + reg); - - spin_lock_irqsave(&pdev->phy_lock, flags); -@@ -1179,6 +1190,7 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = { - .get_desc_dst_addr = get_desc_dst_addr_32, - .run_bits = (DCSR_RUN), - .dma_width = 32, -+ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - - static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { -@@ -1192,6 +1204,7 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { - .get_desc_dst_addr = get_desc_dst_addr_64, - .run_bits = (DCSR_RUN | DCSR_LPAEEN), - .dma_width = 64, -+ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - - static const struct of_device_id mmp_pdma_dt_ids[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0349-UPSTREAM-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux-lts-kmhv2/0349-UPSTREAM-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch new file mode 100644 index 0000000000..0e96eb7e06 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0349-UPSTREAM-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch @@ -0,0 +1,771 @@ +From e77a20759db98180b55de00bfcfdcc48f79fcbf2 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 26 Apr 2026 09:34:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2044: use hex for CPU + unit address + +Previous the CPU unit address cpu of sg2044 use decimal, it is +not following the general convention for unit addresses of the +OF. Convent the unit address to hex to resolve this problem. + +The introduces a small change for the CPU node name, but it should +nothing since there is no direct full-path reference to these +CPU nodes. + +Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") +Reviewed-by: Chen Wang +Reviewed-by: Guo Ren +Link: https://patch.msgid.link/20260426013449.694435-2-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit 207cbc477406a72952e27ace2eadbae55164f129) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- + 1 file changed, 118 insertions(+), 118 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +index 3135409c2149..f66a382c95bd 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +@@ -14,7 +14,7 @@ cpus { + + cpu0: cpu@0 { + compatible = "thead,c920", "riscv"; +- reg = <0>; ++ reg = <0x0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { + + cpu1: cpu@1 { + compatible = "thead,c920", "riscv"; +- reg = <1>; ++ reg = <0x1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { + + cpu2: cpu@2 { + compatible = "thead,c920", "riscv"; +- reg = <2>; ++ reg = <0x2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { + + cpu3: cpu@3 { + compatible = "thead,c920", "riscv"; +- reg = <3>; ++ reg = <0x3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { + + cpu4: cpu@4 { + compatible = "thead,c920", "riscv"; +- reg = <4>; ++ reg = <0x4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { + + cpu5: cpu@5 { + compatible = "thead,c920", "riscv"; +- reg = <5>; ++ reg = <0x5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { + + cpu6: cpu@6 { + compatible = "thead,c920", "riscv"; +- reg = <6>; ++ reg = <0x6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { + + cpu7: cpu@7 { + compatible = "thead,c920", "riscv"; +- reg = <7>; ++ reg = <0x7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { + + cpu8: cpu@8 { + compatible = "thead,c920", "riscv"; +- reg = <8>; ++ reg = <0x8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { + + cpu9: cpu@9 { + compatible = "thead,c920", "riscv"; +- reg = <9>; ++ reg = <0x9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { + }; + }; + +- cpu10: cpu@10 { ++ cpu10: cpu@a { + compatible = "thead,c920", "riscv"; +- reg = <10>; ++ reg = <0xa>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { + }; + }; + +- cpu11: cpu@11 { ++ cpu11: cpu@b { + compatible = "thead,c920", "riscv"; +- reg = <11>; ++ reg = <0xb>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { + }; + }; + +- cpu12: cpu@12 { ++ cpu12: cpu@c { + compatible = "thead,c920", "riscv"; +- reg = <12>; ++ reg = <0xc>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { + }; + }; + +- cpu13: cpu@13 { ++ cpu13: cpu@d { + compatible = "thead,c920", "riscv"; +- reg = <13>; ++ reg = <0xd>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { + }; + }; + +- cpu14: cpu@14 { ++ cpu14: cpu@e { + compatible = "thead,c920", "riscv"; +- reg = <14>; ++ reg = <0xe>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { + }; + }; + +- cpu15: cpu@15 { ++ cpu15: cpu@f { + compatible = "thead,c920", "riscv"; +- reg = <15>; ++ reg = <0xf>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { + }; + }; + +- cpu16: cpu@16 { ++ cpu16: cpu@10 { + compatible = "thead,c920", "riscv"; +- reg = <16>; ++ reg = <0x10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { + }; + }; + +- cpu17: cpu@17 { ++ cpu17: cpu@11 { + compatible = "thead,c920", "riscv"; +- reg = <17>; ++ reg = <0x11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { + }; + }; + +- cpu18: cpu@18 { ++ cpu18: cpu@12 { + compatible = "thead,c920", "riscv"; +- reg = <18>; ++ reg = <0x12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { + }; + }; + +- cpu19: cpu@19 { ++ cpu19: cpu@13 { + compatible = "thead,c920", "riscv"; +- reg = <19>; ++ reg = <0x13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { + }; + }; + +- cpu20: cpu@20 { ++ cpu20: cpu@14 { + compatible = "thead,c920", "riscv"; +- reg = <20>; ++ reg = <0x14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { + }; + }; + +- cpu21: cpu@21 { ++ cpu21: cpu@15 { + compatible = "thead,c920", "riscv"; +- reg = <21>; ++ reg = <0x15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { + }; + }; + +- cpu22: cpu@22 { ++ cpu22: cpu@16 { + compatible = "thead,c920", "riscv"; +- reg = <22>; ++ reg = <0x16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { + }; + }; + +- cpu23: cpu@23 { ++ cpu23: cpu@17 { + compatible = "thead,c920", "riscv"; +- reg = <23>; ++ reg = <0x17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { + }; + }; + +- cpu24: cpu@24 { ++ cpu24: cpu@18 { + compatible = "thead,c920", "riscv"; +- reg = <24>; ++ reg = <0x18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { + }; + }; + +- cpu25: cpu@25 { ++ cpu25: cpu@19 { + compatible = "thead,c920", "riscv"; +- reg = <25>; ++ reg = <0x19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { + }; + }; + +- cpu26: cpu@26 { ++ cpu26: cpu@1a { + compatible = "thead,c920", "riscv"; +- reg = <26>; ++ reg = <0x1a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { + }; + }; + +- cpu27: cpu@27 { ++ cpu27: cpu@1b { + compatible = "thead,c920", "riscv"; +- reg = <27>; ++ reg = <0x1b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { + }; + }; + +- cpu28: cpu@28 { ++ cpu28: cpu@1c { + compatible = "thead,c920", "riscv"; +- reg = <28>; ++ reg = <0x1c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { + }; + }; + +- cpu29: cpu@29 { ++ cpu29: cpu@1d { + compatible = "thead,c920", "riscv"; +- reg = <29>; ++ reg = <0x1d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { + }; + }; + +- cpu30: cpu@30 { ++ cpu30: cpu@1e { + compatible = "thead,c920", "riscv"; +- reg = <30>; ++ reg = <0x1e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { + }; + }; + +- cpu31: cpu@31 { ++ cpu31: cpu@1f { + compatible = "thead,c920", "riscv"; +- reg = <31>; ++ reg = <0x1f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { + }; + }; + +- cpu32: cpu@32 { ++ cpu32: cpu@20 { + compatible = "thead,c920", "riscv"; +- reg = <32>; ++ reg = <0x20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { + }; + }; + +- cpu33: cpu@33 { ++ cpu33: cpu@21 { + compatible = "thead,c920", "riscv"; +- reg = <33>; ++ reg = <0x21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { + }; + }; + +- cpu34: cpu@34 { ++ cpu34: cpu@22 { + compatible = "thead,c920", "riscv"; +- reg = <34>; ++ reg = <0x22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { + }; + }; + +- cpu35: cpu@35 { ++ cpu35: cpu@23 { + compatible = "thead,c920", "riscv"; +- reg = <35>; ++ reg = <0x23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { + }; + }; + +- cpu36: cpu@36 { ++ cpu36: cpu@24 { + compatible = "thead,c920", "riscv"; +- reg = <36>; ++ reg = <0x24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { + }; + }; + +- cpu37: cpu@37 { ++ cpu37: cpu@25 { + compatible = "thead,c920", "riscv"; +- reg = <37>; ++ reg = <0x25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { + }; + }; + +- cpu38: cpu@38 { ++ cpu38: cpu@26 { + compatible = "thead,c920", "riscv"; +- reg = <38>; ++ reg = <0x26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { + }; + }; + +- cpu39: cpu@39 { ++ cpu39: cpu@27 { + compatible = "thead,c920", "riscv"; +- reg = <39>; ++ reg = <0x27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { + }; + }; + +- cpu40: cpu@40 { ++ cpu40: cpu@28 { + compatible = "thead,c920", "riscv"; +- reg = <40>; ++ reg = <0x28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { + }; + }; + +- cpu41: cpu@41 { ++ cpu41: cpu@29 { + compatible = "thead,c920", "riscv"; +- reg = <41>; ++ reg = <0x29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { + }; + }; + +- cpu42: cpu@42 { ++ cpu42: cpu@2a { + compatible = "thead,c920", "riscv"; +- reg = <42>; ++ reg = <0x2a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { + }; + }; + +- cpu43: cpu@43 { ++ cpu43: cpu@2b { + compatible = "thead,c920", "riscv"; +- reg = <43>; ++ reg = <0x2b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { + }; + }; + +- cpu44: cpu@44 { ++ cpu44: cpu@2c { + compatible = "thead,c920", "riscv"; +- reg = <44>; ++ reg = <0x2c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { + }; + }; + +- cpu45: cpu@45 { ++ cpu45: cpu@2d { + compatible = "thead,c920", "riscv"; +- reg = <45>; ++ reg = <0x2d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { + }; + }; + +- cpu46: cpu@46 { ++ cpu46: cpu@2e { + compatible = "thead,c920", "riscv"; +- reg = <46>; ++ reg = <0x2e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { + }; + }; + +- cpu47: cpu@47 { ++ cpu47: cpu@2f { + compatible = "thead,c920", "riscv"; +- reg = <47>; ++ reg = <0x2f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { + }; + }; + +- cpu48: cpu@48 { ++ cpu48: cpu@30 { + compatible = "thead,c920", "riscv"; +- reg = <48>; ++ reg = <0x30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { + }; + }; + +- cpu49: cpu@49 { ++ cpu49: cpu@31 { + compatible = "thead,c920", "riscv"; +- reg = <49>; ++ reg = <0x31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { + }; + }; + +- cpu50: cpu@50 { ++ cpu50: cpu@32 { + compatible = "thead,c920", "riscv"; +- reg = <50>; ++ reg = <0x32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { + }; + }; + +- cpu51: cpu@51 { ++ cpu51: cpu@33 { + compatible = "thead,c920", "riscv"; +- reg = <51>; ++ reg = <0x33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { + }; + }; + +- cpu52: cpu@52 { ++ cpu52: cpu@34 { + compatible = "thead,c920", "riscv"; +- reg = <52>; ++ reg = <0x34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { + }; + }; + +- cpu53: cpu@53 { ++ cpu53: cpu@35 { + compatible = "thead,c920", "riscv"; +- reg = <53>; ++ reg = <0x35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { + }; + }; + +- cpu54: cpu@54 { ++ cpu54: cpu@36 { + compatible = "thead,c920", "riscv"; +- reg = <54>; ++ reg = <0x36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { + }; + }; + +- cpu55: cpu@55 { ++ cpu55: cpu@37 { + compatible = "thead,c920", "riscv"; +- reg = <55>; ++ reg = <0x37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { + }; + }; + +- cpu56: cpu@56 { ++ cpu56: cpu@38 { + compatible = "thead,c920", "riscv"; +- reg = <56>; ++ reg = <0x38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { + }; + }; + +- cpu57: cpu@57 { ++ cpu57: cpu@39 { + compatible = "thead,c920", "riscv"; +- reg = <57>; ++ reg = <0x39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { + }; + }; + +- cpu58: cpu@58 { ++ cpu58: cpu@3a { + compatible = "thead,c920", "riscv"; +- reg = <58>; ++ reg = <0x3a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { + }; + }; + +- cpu59: cpu@59 { ++ cpu59: cpu@3b { + compatible = "thead,c920", "riscv"; +- reg = <59>; ++ reg = <0x3b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { + }; + }; + +- cpu60: cpu@60 { ++ cpu60: cpu@3c { + compatible = "thead,c920", "riscv"; +- reg = <60>; ++ reg = <0x3c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { + }; + }; + +- cpu61: cpu@61 { ++ cpu61: cpu@3d { + compatible = "thead,c920", "riscv"; +- reg = <61>; ++ reg = <0x3d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { + }; + }; + +- cpu62: cpu@62 { ++ cpu62: cpu@3e { + compatible = "thead,c920", "riscv"; +- reg = <62>; ++ reg = <0x3e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { + }; + }; + +- cpu63: cpu@63 { ++ cpu63: cpu@3f { + compatible = "thead,c920", "riscv"; +- reg = <63>; ++ reg = <0x3f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch deleted file mode 100644 index db3d534951..0000000000 --- a/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch +++ /dev/null @@ -1,63 +0,0 @@ -From e077c02ed73be7f8782ceacc9a2f7dd9396857b0 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:43 +0800 -Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 support - -SpacemiT K3 reuses most of the PDMA IP design found on K1, with one -difference being the extended DRCMR base address. Add "spacemit,k3-pdma" -compatible string and define a new mmp_pdma_ops for K3 PDMA. - -Signed-off-by: Guodong Xu -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/dma/mmp_pdma.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c -index 6112369006ee..386e85cd4882 100644 ---- a/drivers/dma/mmp_pdma.c -+++ b/drivers/dma/mmp_pdma.c -@@ -52,6 +52,7 @@ - #define DCSR_EORINTR BIT(9) /* The end of Receive */ - - #define DRCMR_BASE 0x0100 -+#define DRCMR_EXT_BASE_K3 0x1000 - #define DRCMR_EXT_BASE_DEFAULT 0x1100 - #define DRCMR_REQ_LIMIT 64 - #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ -@@ -1207,6 +1208,20 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { - .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - -+static const struct mmp_pdma_ops spacemit_k3_pdma_ops = { -+ .write_next_addr = write_next_addr_64, -+ .read_src_addr = read_src_addr_64, -+ .read_dst_addr = read_dst_addr_64, -+ .set_desc_next_addr = set_desc_next_addr_64, -+ .set_desc_src_addr = set_desc_src_addr_64, -+ .set_desc_dst_addr = set_desc_dst_addr_64, -+ .get_desc_src_addr = get_desc_src_addr_64, -+ .get_desc_dst_addr = get_desc_dst_addr_64, -+ .run_bits = (DCSR_RUN | DCSR_LPAEEN | DCSR_EORIRQEN | DCSR_EORSTOPEN), -+ .dma_width = 64, -+ .drcmr_ext_base = DRCMR_EXT_BASE_K3, -+}; -+ - static const struct of_device_id mmp_pdma_dt_ids[] = { - { - .compatible = "marvell,pdma-1.0", -@@ -1214,6 +1229,9 @@ static const struct of_device_id mmp_pdma_dt_ids[] = { - }, { - .compatible = "spacemit,k1-pdma", - .data = &spacemit_k1_pdma_ops -+ }, { -+ .compatible = "spacemit,k3-pdma", -+ .data = &spacemit_k3_pdma_ops - }, { - /* sentinel */ - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0350-UPSTREAM-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux-lts-kmhv2/0350-UPSTREAM-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch new file mode 100644 index 0000000000..6484dee47a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0350-UPSTREAM-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch @@ -0,0 +1,1098 @@ +From a2a2a77e5257e95499bd89302751e6e9b3edec32 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 26 Apr 2026 09:34:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2042: use hex for CPU + unit address + +Previous the CPU unit address cpu of sg2042 use decimal, it is +not following the general convention for unit addresses of the +OF. Convent the unit address to hex to resolve this problem. + +The introduces a small change for the CPU node name, but it should +affect nothing since there is no direct full-path reference to +these CPU nodes. + +Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") +Tested-by: Chen Wang # Pioneerbox. +Reviewed-by: Guo Ren +Reviewed-by: Chen Wang +Acked-by: Conor Dooley +Tested-by: Chen Wang on Pioneerbox. +Link: https://patch.msgid.link/20260426013449.694435-3-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit a7e658907686528fe06a11828b04a3e42df9ef18) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- + 1 file changed, 118 insertions(+), 118 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +index 509488eee432..fd8906b313d2 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +@@ -263,7 +263,7 @@ cpu0: cpu@0 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <0>; ++ reg = <0x0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -291,7 +291,7 @@ cpu1: cpu@1 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <1>; ++ reg = <0x1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -319,7 +319,7 @@ cpu2: cpu@2 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <2>; ++ reg = <0x2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -347,7 +347,7 @@ cpu3: cpu@3 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <3>; ++ reg = <0x3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -375,7 +375,7 @@ cpu4: cpu@4 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <4>; ++ reg = <0x4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -403,7 +403,7 @@ cpu5: cpu@5 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <5>; ++ reg = <0x5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -431,7 +431,7 @@ cpu6: cpu@6 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <6>; ++ reg = <0x6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -459,7 +459,7 @@ cpu7: cpu@7 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <7>; ++ reg = <0x7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -487,7 +487,7 @@ cpu8: cpu@8 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <8>; ++ reg = <0x8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -515,7 +515,7 @@ cpu9: cpu@9 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <9>; ++ reg = <0x9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { + }; + }; + +- cpu10: cpu@10 { ++ cpu10: cpu@a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -543,7 +543,7 @@ cpu10: cpu@10 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <10>; ++ reg = <0xa>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { + }; + }; + +- cpu11: cpu@11 { ++ cpu11: cpu@b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -571,7 +571,7 @@ cpu11: cpu@11 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <11>; ++ reg = <0xb>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { + }; + }; + +- cpu12: cpu@12 { ++ cpu12: cpu@c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -599,7 +599,7 @@ cpu12: cpu@12 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <12>; ++ reg = <0xc>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { + }; + }; + +- cpu13: cpu@13 { ++ cpu13: cpu@d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -627,7 +627,7 @@ cpu13: cpu@13 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <13>; ++ reg = <0xd>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { + }; + }; + +- cpu14: cpu@14 { ++ cpu14: cpu@e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -655,7 +655,7 @@ cpu14: cpu@14 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <14>; ++ reg = <0xe>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { + }; + }; + +- cpu15: cpu@15 { ++ cpu15: cpu@f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -683,7 +683,7 @@ cpu15: cpu@15 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <15>; ++ reg = <0xf>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { + }; + }; + +- cpu16: cpu@16 { ++ cpu16: cpu@10 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -711,7 +711,7 @@ cpu16: cpu@16 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <16>; ++ reg = <0x10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { + }; + }; + +- cpu17: cpu@17 { ++ cpu17: cpu@11 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -739,7 +739,7 @@ cpu17: cpu@17 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <17>; ++ reg = <0x11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { + }; + }; + +- cpu18: cpu@18 { ++ cpu18: cpu@12 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -767,7 +767,7 @@ cpu18: cpu@18 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <18>; ++ reg = <0x12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { + }; + }; + +- cpu19: cpu@19 { ++ cpu19: cpu@13 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -795,7 +795,7 @@ cpu19: cpu@19 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <19>; ++ reg = <0x13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { + }; + }; + +- cpu20: cpu@20 { ++ cpu20: cpu@14 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -823,7 +823,7 @@ cpu20: cpu@20 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <20>; ++ reg = <0x14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { + }; + }; + +- cpu21: cpu@21 { ++ cpu21: cpu@15 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -851,7 +851,7 @@ cpu21: cpu@21 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <21>; ++ reg = <0x15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { + }; + }; + +- cpu22: cpu@22 { ++ cpu22: cpu@16 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -879,7 +879,7 @@ cpu22: cpu@22 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <22>; ++ reg = <0x16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { + }; + }; + +- cpu23: cpu@23 { ++ cpu23: cpu@17 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -907,7 +907,7 @@ cpu23: cpu@23 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <23>; ++ reg = <0x17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { + }; + }; + +- cpu24: cpu@24 { ++ cpu24: cpu@18 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -935,7 +935,7 @@ cpu24: cpu@24 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <24>; ++ reg = <0x18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { + }; + }; + +- cpu25: cpu@25 { ++ cpu25: cpu@19 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -963,7 +963,7 @@ cpu25: cpu@25 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <25>; ++ reg = <0x19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { + }; + }; + +- cpu26: cpu@26 { ++ cpu26: cpu@1a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -991,7 +991,7 @@ cpu26: cpu@26 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <26>; ++ reg = <0x1a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { + }; + }; + +- cpu27: cpu@27 { ++ cpu27: cpu@1b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1019,7 +1019,7 @@ cpu27: cpu@27 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <27>; ++ reg = <0x1b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { + }; + }; + +- cpu28: cpu@28 { ++ cpu28: cpu@1c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1047,7 +1047,7 @@ cpu28: cpu@28 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <28>; ++ reg = <0x1c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { + }; + }; + +- cpu29: cpu@29 { ++ cpu29: cpu@1d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1075,7 +1075,7 @@ cpu29: cpu@29 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <29>; ++ reg = <0x1d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { + }; + }; + +- cpu30: cpu@30 { ++ cpu30: cpu@1e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1103,7 +1103,7 @@ cpu30: cpu@30 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <30>; ++ reg = <0x1e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { + }; + }; + +- cpu31: cpu@31 { ++ cpu31: cpu@1f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1131,7 +1131,7 @@ cpu31: cpu@31 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <31>; ++ reg = <0x1f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { + }; + }; + +- cpu32: cpu@32 { ++ cpu32: cpu@20 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1159,7 +1159,7 @@ cpu32: cpu@32 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <32>; ++ reg = <0x20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { + }; + }; + +- cpu33: cpu@33 { ++ cpu33: cpu@21 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1187,7 +1187,7 @@ cpu33: cpu@33 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <33>; ++ reg = <0x21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { + }; + }; + +- cpu34: cpu@34 { ++ cpu34: cpu@22 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1215,7 +1215,7 @@ cpu34: cpu@34 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <34>; ++ reg = <0x22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { + }; + }; + +- cpu35: cpu@35 { ++ cpu35: cpu@23 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1243,7 +1243,7 @@ cpu35: cpu@35 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <35>; ++ reg = <0x23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { + }; + }; + +- cpu36: cpu@36 { ++ cpu36: cpu@24 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1271,7 +1271,7 @@ cpu36: cpu@36 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <36>; ++ reg = <0x24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { + }; + }; + +- cpu37: cpu@37 { ++ cpu37: cpu@25 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1299,7 +1299,7 @@ cpu37: cpu@37 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <37>; ++ reg = <0x25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { + }; + }; + +- cpu38: cpu@38 { ++ cpu38: cpu@26 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1327,7 +1327,7 @@ cpu38: cpu@38 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <38>; ++ reg = <0x26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { + }; + }; + +- cpu39: cpu@39 { ++ cpu39: cpu@27 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1355,7 +1355,7 @@ cpu39: cpu@39 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <39>; ++ reg = <0x27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { + }; + }; + +- cpu40: cpu@40 { ++ cpu40: cpu@28 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1383,7 +1383,7 @@ cpu40: cpu@40 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <40>; ++ reg = <0x28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { + }; + }; + +- cpu41: cpu@41 { ++ cpu41: cpu@29 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1411,7 +1411,7 @@ cpu41: cpu@41 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <41>; ++ reg = <0x29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { + }; + }; + +- cpu42: cpu@42 { ++ cpu42: cpu@2a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1439,7 +1439,7 @@ cpu42: cpu@42 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <42>; ++ reg = <0x2a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { + }; + }; + +- cpu43: cpu@43 { ++ cpu43: cpu@2b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1467,7 +1467,7 @@ cpu43: cpu@43 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <43>; ++ reg = <0x2b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { + }; + }; + +- cpu44: cpu@44 { ++ cpu44: cpu@2c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1495,7 +1495,7 @@ cpu44: cpu@44 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <44>; ++ reg = <0x2c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { + }; + }; + +- cpu45: cpu@45 { ++ cpu45: cpu@2d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1523,7 +1523,7 @@ cpu45: cpu@45 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <45>; ++ reg = <0x2d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { + }; + }; + +- cpu46: cpu@46 { ++ cpu46: cpu@2e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1551,7 +1551,7 @@ cpu46: cpu@46 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <46>; ++ reg = <0x2e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { + }; + }; + +- cpu47: cpu@47 { ++ cpu47: cpu@2f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1579,7 +1579,7 @@ cpu47: cpu@47 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <47>; ++ reg = <0x2f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { + }; + }; + +- cpu48: cpu@48 { ++ cpu48: cpu@30 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1607,7 +1607,7 @@ cpu48: cpu@48 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <48>; ++ reg = <0x30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { + }; + }; + +- cpu49: cpu@49 { ++ cpu49: cpu@31 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1635,7 +1635,7 @@ cpu49: cpu@49 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <49>; ++ reg = <0x31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { + }; + }; + +- cpu50: cpu@50 { ++ cpu50: cpu@32 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1663,7 +1663,7 @@ cpu50: cpu@50 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <50>; ++ reg = <0x32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { + }; + }; + +- cpu51: cpu@51 { ++ cpu51: cpu@33 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1691,7 +1691,7 @@ cpu51: cpu@51 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <51>; ++ reg = <0x33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { + }; + }; + +- cpu52: cpu@52 { ++ cpu52: cpu@34 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1719,7 +1719,7 @@ cpu52: cpu@52 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <52>; ++ reg = <0x34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { + }; + }; + +- cpu53: cpu@53 { ++ cpu53: cpu@35 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1747,7 +1747,7 @@ cpu53: cpu@53 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <53>; ++ reg = <0x35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { + }; + }; + +- cpu54: cpu@54 { ++ cpu54: cpu@36 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1775,7 +1775,7 @@ cpu54: cpu@54 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <54>; ++ reg = <0x36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { + }; + }; + +- cpu55: cpu@55 { ++ cpu55: cpu@37 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1803,7 +1803,7 @@ cpu55: cpu@55 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <55>; ++ reg = <0x37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { + }; + }; + +- cpu56: cpu@56 { ++ cpu56: cpu@38 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1831,7 +1831,7 @@ cpu56: cpu@56 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <56>; ++ reg = <0x38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { + }; + }; + +- cpu57: cpu@57 { ++ cpu57: cpu@39 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1859,7 +1859,7 @@ cpu57: cpu@57 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <57>; ++ reg = <0x39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { + }; + }; + +- cpu58: cpu@58 { ++ cpu58: cpu@3a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1887,7 +1887,7 @@ cpu58: cpu@58 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <58>; ++ reg = <0x3a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { + }; + }; + +- cpu59: cpu@59 { ++ cpu59: cpu@3b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1915,7 +1915,7 @@ cpu59: cpu@59 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <59>; ++ reg = <0x3b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { + }; + }; + +- cpu60: cpu@60 { ++ cpu60: cpu@3c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1943,7 +1943,7 @@ cpu60: cpu@60 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <60>; ++ reg = <0x3c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { + }; + }; + +- cpu61: cpu@61 { ++ cpu61: cpu@3d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1971,7 +1971,7 @@ cpu61: cpu@61 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <61>; ++ reg = <0x3d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { + }; + }; + +- cpu62: cpu@62 { ++ cpu62: cpu@3e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1999,7 +1999,7 @@ cpu62: cpu@62 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <62>; ++ reg = <0x3e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { + }; + }; + +- cpu63: cpu@63 { ++ cpu63: cpu@3f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -2027,7 +2027,7 @@ cpu63: cpu@63 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <63>; ++ reg = <0x3f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch deleted file mode 100644 index 3b955dda90..0000000000 --- a/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 21b7895de7539f827659bef3d905b99563ac4277 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Mon, 18 May 2026 11:32:44 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add PDMA controller node - for K3 SoC - -Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. -The PDMA controller provides general-purpose DMA capabilities for various -peripheral devices across the system to offload CPU data transfers. - -Unlike the previous K1 SoC, where some DMA masters had memory addressing -limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus -with dma-ranges to restrict memory allocations, the K3 DMA masters have -full memory addressing capabilities. Therefore, the PDMA node is now -instantiated directly under the main soc bus. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 815debd16409..81ad575f16a5 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -625,6 +625,18 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ -+ pdma: dma-controller@d4000000 { -+ compatible = "spacemit,k3-pdma"; -+ reg = <0x0 0xd4000000 0x0 0x4000>; -+ clocks = <&syscon_apmu CLK_APMU_DMA>; -+ resets = <&syscon_apmu RESET_APMU_DMA>; -+ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; -+ dma-channels = <16>; -+ #dma-cells = <1>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0351-UPSTREAM-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux-lts-kmhv2/0351-UPSTREAM-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch new file mode 100644 index 0000000000..c929d41c5d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0351-UPSTREAM-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch @@ -0,0 +1,43 @@ +From 59a46abf3b3bc582bb600ebdf795d8e31927ff02 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 8 Apr 2026 00:01:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: reduce SG2042 MSI count to + 16 + +The SG2042 MSI controller has one 32-bit doorbell register, and each bit +corresponds to an interrupt. At a glance, it seems that the MSI +controller can support 32 interrupts; however the PCI MSI capability +only supports 16-bit messages, which makes the high 16 interrupts +unusable in such way. + +Reduce the MSI count to 16 to prevent producing MSI message values that +cannot fit 16-bit integers. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Chen Wang +Tested-by: Chen Wang on Pioneerbox. +Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit 903a9364e40563faf4730dc63ad7446246f494ff) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index 3af770549742..7eab0655f150 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { + reg-names = "clr", "doorbell"; + msi-controller; + #msi-cells = <0>; +- msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; ++ msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; + }; + + rpgate: clock-controller@7030010368 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch deleted file mode 100644 index 505c1fcf8b..0000000000 --- a/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch +++ /dev/null @@ -1,39 +0,0 @@ -From e45053fa3fb846fee16140a46bfca3810a696d3a Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:12:47 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent - property for SG2042 - -Add dma-coherent as an allowed property in the SG2042 PCIe host -controller binding. SG2042's PCIe root complexes are cache-coherent -with the CPU. - -Link: https://lore.kernel.org/r/20260331171248.973014-2-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -index f8b7ca57fff1..ab482488b047 100644 ---- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -@@ -30,6 +30,8 @@ properties: - device-id: - const: 0x2042 - -+ dma-coherent: true -+ - msi-parent: true - - allOf: -@@ -60,5 +62,6 @@ examples: - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0352-UPSTREAM-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux-lts-kmhv2/0352-UPSTREAM-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch new file mode 100644 index 0000000000..0f3e351bc2 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0352-UPSTREAM-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch @@ -0,0 +1,99 @@ +From a69ba2041927a2833c0f219d0d7c201b106b9096 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:46:50 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pwm: marvell,pxa-pwm: Add + SpacemiT K3 PWM support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 +generation, while the difference is that one additional bus clock is +added. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org +Signed-off-by: Uwe Kleine-König +(cherry picked from commit e7abbff5e8b2924a53b583e6d57804c6cad0ab81) +Signed-off-by: Han Gao +--- + .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- + 1 file changed, 38 insertions(+), 3 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +index 8df327e52810..f1422a401b6b 100644 +--- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml ++++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +@@ -15,7 +15,9 @@ allOf: + properties: + compatible: + contains: +- const: spacemit,k1-pwm ++ enum: ++ - spacemit,k1-pwm ++ - spacemit,k3-pwm + then: + properties: + "#pwm-cells": +@@ -26,6 +28,26 @@ allOf: + const: 1 + description: | + Used for specifying the period length in nanoseconds. ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - spacemit,k3-pwm ++ then: ++ required: ++ - clock-names ++ properties: ++ clocks: ++ minItems: 2 ++ clock-names: ++ minItems: 2 ++ else: ++ properties: ++ clocks: ++ maxItems: 1 ++ clock-names: ++ maxItems: 1 + + properties: + compatible: +@@ -36,7 +58,9 @@ properties: + - marvell,pxa168-pwm + - marvell,pxa910-pwm + - items: +- - const: spacemit,k1-pwm ++ - enum: ++ - spacemit,k1-pwm ++ - spacemit,k3-pwm + - const: marvell,pxa910-pwm + + reg: +@@ -47,7 +71,18 @@ properties: + description: Number of cells in a pwm specifier. + + clocks: +- maxItems: 1 ++ minItems: 1 ++ items: ++ - description: The function clock ++ - description: An optional bus clock ++ ++ clock-names: ++ minItems: 1 ++ maxItems: 2 ++ oneOf: ++ - items: ++ - const: func ++ - const: bus + + resets: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch deleted file mode 100644 index 59e22401d2..0000000000 --- a/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 4edb2b9deb6868de278295f9df339eb66e2dc5e6 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:12:48 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: Add dma-coherent to SG2042 - PCIe controllers - -SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all -four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent -so the kernel uses coherent DMA mappings instead of non-coherent bounce -buffering. - -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331171248.973014-3-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index 9fddf3f0b3b9..3af770549742 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0353-UPSTREAM-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux-lts-kmhv2/0353-UPSTREAM-pwm-pxa-Add-optional-bus-clock.patch new file mode 100644 index 0000000000..0b8d768f93 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0353-UPSTREAM-pwm-pxa-Add-optional-bus-clock.patch @@ -0,0 +1,52 @@ +From 3d75a58d454b0668263795bbfdaccf0587a36d08 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:46:51 +0000 +Subject: [RUYI PATCH] UPSTREAM: pwm: pxa: Add optional bus clock +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add one secondary optional bus clock for the PWM PXA driver, also keep it +compatible with old single clock. + +The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and +enable it during probe phase. + +Signed-off-by: Yixun Lan +Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org +Signed-off-by: Uwe Kleine-König +(cherry picked from commit 74bca0f2d37f5fd9a4bd5378d9f9579e72038556) +Signed-off-by: Han Gao +--- + drivers/pwm/pwm-pxa.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c +index 0f5bdb0e395e..80d2fa10919f 100644 +--- a/drivers/pwm/pwm-pxa.c ++++ b/drivers/pwm/pwm-pxa.c +@@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) + const struct platform_device_id *id = platform_get_device_id(pdev); + struct pwm_chip *chip; + struct pxa_pwm_chip *pc; ++ struct clk *bus_clk; + struct device *dev = &pdev->dev; + struct reset_control *rst; + int ret = 0; +@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) + return PTR_ERR(chip); + pc = to_pxa_pwm_chip(chip); + +- pc->clk = devm_clk_get(dev, NULL); ++ bus_clk = devm_clk_get_optional_enabled(dev, "bus"); ++ if (IS_ERR(bus_clk)) ++ return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); ++ ++ /* Get named func clk if bus clock is valid */ ++ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); + if (IS_ERR(pc->clk)) + return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch deleted file mode 100644 index 54ce584981..0000000000 --- a/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 4d5cd4b1f6fe26dc668fffd055e5d01af826c026 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Tue, 31 Mar 2026 15:37:22 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for - systems with DRAM above 4GB - -On RISC-V platforms where the entire physical memory (DRAM) resides -above the 32-bit address space (i.e., above dma32_phys_limit), the -current SWIOTLB initialization logic fails. - -This patch addresses two interconnected issues on such platforms: - -1. Incorrect 32-bit DMA bounce assumption: -The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes -that a 32-bit DMA bounce buffer is required simply because the maximum -PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, -no memory exists below the limit to satisfy this allocation. Fix -this by adding a check to ensure `memblock_start_of_DRAM()` is actually -below the 32-bit limit before enforcing 32-bit SWIOTLB. - -2. kmalloc() bounce buffer allocation failure on non-coherent systems: -For non-coherent hardware, a bounce buffer is still mandatory for -cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. -Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating -from low memory, which fails completely when DRAM only exists in high -memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is -permitted to allocate this alignment buffer from high memory. - -With this patch, systems with non-coherent DMA and DRAM entirely above -4GB can successfully map the software IO TLB in high memory and boot -normally. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260331-fix-riscv-swiotlb-v1-1-74dd5e6be0f1@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 6533cc17825a..ac5bece70736 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -172,7 +172,9 @@ static void print_vm_layout(void) { } - - void __init arch_mm_preinit(void) - { -- bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit); -+ bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) && -+ memblock_start_of_DRAM() < dma32_phys_limit; -+ unsigned int swiotlb_flags = SWIOTLB_VERBOSE; - #ifdef CONFIG_FLATMEM - BUG_ON(!mem_map); - #endif /* CONFIG_FLATMEM */ -@@ -180,17 +182,21 @@ void __init arch_mm_preinit(void) - if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb && - dma_cache_alignment != 1) { - /* -- * If no bouncing needed for ZONE_DMA, allocate 1MB swiotlb -- * buffer per 1GB of RAM for kmalloc() bouncing on -- * non-coherent platforms. -+ * No 32-bit DMA bouncing needed (either all DRAM is within -+ * the 32-bit limit, or it all starts above it), but -+ * non-coherent hardware still requires cache-line-aligned -+ * bounce buffers for kmalloc(). Use SWIOTLB_ANY so that the -+ * buffer can be allocated from high memory when DRAM starts -+ * above dma32_phys_limit. Allocate ~1 MB per 1 GB of RAM. - */ - unsigned long size = - DIV_ROUND_UP(memblock_phys_mem_size(), 1024); - swiotlb_adjust_size(min(swiotlb_size_or_default(), size)); - swiotlb = true; -+ swiotlb_flags |= SWIOTLB_ANY; - } - -- swiotlb_init(swiotlb, SWIOTLB_VERBOSE); -+ swiotlb_init(swiotlb, swiotlb_flags); - - print_vm_layout(); - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0354-UPSTREAM-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux-lts-kmhv2/0354-UPSTREAM-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch new file mode 100644 index 0000000000..3042a262ab --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0354-UPSTREAM-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch @@ -0,0 +1,48 @@ +From 8681df6aff6818f9e842a3a9ba4757f0cb4acdf1 Mon Sep 17 00:00:00 2001 +From: Chen Pei +Date: Sat, 6 Jun 2026 20:17:53 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: ftrace: select + HAVE_BUILDTIME_MCOUNT_SORT + +RISC-V already satisfies all prerequisites for build-time mcount sorting: +the sorttable host tool handles EM_RISCV in its machine-type dispatch, and +the __mcount_loc section entries are stored as direct virtual addresses in +the final vmlinux binary, so no relocation processing is required during +the sort step. + +Select HAVE_BUILDTIME_MCOUNT_SORT so that BUILDTIME_MCOUNT_SORT is +automatically enabled when DYNAMIC_FTRACE is configured. This allows +sorttable to sort the __mcount_loc section at link time, making the +run-time ftrace initialisation path skip the software sort and reducing +kernel startup overhead. + +Verified with CONFIG_FTRACE_SORT_STARTUP_TEST=y, which confirms that +the section produced by the build is already in ascending order: + + [ 0.000000] ftrace section at ffffffff81015a60 sorted properly + +Signed-off-by: Chen Pei +Tested-by: Guo Ren +Link: https://patch.msgid.link/20260409114736.907-1-cp0613@linux.alibaba.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 9fd44698b11dbdf4d29fdef0f0da25f320c13854) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 9c43346fabcd..4946ac7b6db1 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -150,6 +150,7 @@ config RISCV + select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD + select HAVE_ARCH_VMAP_STACK if MMU && 64BIT + select HAVE_ASM_MODVERSIONS ++ select HAVE_BUILDTIME_MCOUNT_SORT + select HAVE_CONTEXT_TRACKING_USER + select HAVE_DEBUG_KMEMLEAK + select HAVE_DMA_CONTIGUOUS if MMU +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch deleted file mode 100644 index 223d5a699f..0000000000 --- a/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 1e089bd4441c081e557a84db781ccfe5f79b5601 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:08 +0530 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add - vcc5v0_sys regulator for Banana Pi F3 - -Define the system 5V fixed regulator (vcc5v0_sys) supplied by the -DC input. As per the schematics, vcc5v0_sys is the input power source -for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators -to correctly reference vcc5v0_sys as their parent (vin-supply). - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-2-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 2a0caecd9a41..341d86a8f7ae 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -52,6 +52,16 @@ reg_dc_in: regulator-dc-in-12v { - regulator-always-on; - }; - -+ reg_vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ - reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; -@@ -68,6 +78,7 @@ regulator-usb3-vbus-5v { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; -+ vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -@@ -77,6 +88,7 @@ usb3_hub_5v: regulator-usb3-hub-5v { - regulator-name = "USB30_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0355-UPSTREAM-dts-spacemit-set-console-baud-rate-on-bpif3.patch b/SPECS/linux-lts-kmhv2/0355-UPSTREAM-dts-spacemit-set-console-baud-rate-on-bpif3.patch new file mode 100644 index 0000000000..efeea3b0be --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0355-UPSTREAM-dts-spacemit-set-console-baud-rate-on-bpif3.patch @@ -0,0 +1,37 @@ +From 9f9a29f7d2c0237960ad9bac7e73e25fd16c64ec Mon Sep 17 00:00:00 2001 +From: Conor Dooley +Date: Thu, 30 Apr 2026 19:52:12 +0100 +Subject: [RUYI PATCH] UPSTREAM: dts: spacemit: set console baud rate on bpif3 + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +Suggested-by: Vivian Wang +Fixes: d60d57ab6b2a8 ("riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree") +Signed-off-by: Conor Dooley +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260430-reword-overstep-3be08b7eab25@spud +Signed-off-by: Yixun Lan +(cherry picked from commit 24c12ca43b12c104389d9a159207d0b25779d0af) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 9429189354d6..e20daa50a152 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -20,7 +20,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch deleted file mode 100644 index 5fda255af1..0000000000 --- a/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 9927a583ce5c19e8befcb7ed40a6238c53f79b35 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:09 +0530 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update - USB regulator on onboard usb and lable - -Update the USB regulator labels to align with the board schematics and -power hierarchy. This change renames the regulator to reg_5v_vbus and -its name to 5V_VBUS. Additionally, it fixes the vdd-supply references -for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point -to the 5V_VBUS input source as per the board schematics. - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-3-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 341d86a8f7ae..6c2a2e713121 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -72,9 +72,9 @@ reg_vcc_4v: regulator-vcc-4v { - vin-supply = <®_dc_in>; - }; - -- regulator-usb3-vbus-5v { -+ reg_5v_vbus: regulator-usb3-vbus-5v { - compatible = "regulator-fixed"; -- regulator-name = "USB30_VBUS"; -+ regulator-name = "5V_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; -@@ -406,7 +406,7 @@ &usb_dwc3 { - hub_2_0: hub@1 { - compatible = "usb2109,2817"; - reg = <0x1>; -- vdd-supply = <&usb3_hub_5v>; -+ vdd-supply = <®_5v_vbus>; - peer-hub = <&hub_3_0>; - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; -@@ -414,7 +414,7 @@ hub_2_0: hub@1 { - hub_3_0: hub@2 { - compatible = "usb2109,817"; - reg = <0x2>; -- vdd-supply = <&usb3_hub_5v>; -+ vdd-supply = <®_5v_vbus>; - peer-hub = <&hub_2_0>; - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0356-UPSTREAM-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0356-UPSTREAM-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch new file mode 100644 index 0000000000..3ca90c180d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0356-UPSTREAM-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch @@ -0,0 +1,61 @@ +From 19ef70b8381d25c5d9091e65c6960a6d6f7fbd81 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 18 May 2026 18:00:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB3 on OrangePi + R2S + +Enable the DWC3 USB3.0 controller and its associated PHY on the +OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 +ports, but the USB2 ports are handled by a separate controller. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260518100030.2354606-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit c5ad6737df88bd3c3e83145edb25737cb19f9a1f) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index de75f6aac740..1ecc40749e5a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -21,6 +21,19 @@ aliases { + chosen { + stdout-path = "serial0"; + }; ++ ++ vcc5v0_usb: regulator-vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combo_phy { ++ status = "okay"; + }; + + &emmc { +@@ -90,3 +103,13 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ vbus-supply = <&vcc5v0_usb>; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch deleted file mode 100644 index a3dbb529e4..0000000000 --- a/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch +++ /dev/null @@ -1,52 +0,0 @@ -From c3e497dbbb78a87638bd90cab0bd7540fd683d89 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:10 +0530 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct - USB hub power hierarchy -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to -ensure the USB 3.0 stack is properly powered as per the schematics. -In addition, align the USB hub regulator with the board schematics -by renaming it to VCC5V0_HUB and marking it as regulator-always-on -to maintain power stability. - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-4-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 6c2a2e713121..b48a485f954b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -85,9 +85,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v { - - usb3_hub_5v: regulator-usb3-hub-5v { - compatible = "regulator-fixed"; -- regulator-name = "USB30_HUB"; -+ regulator-name = "VCC5V0_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ regulator-always-on; - vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; - enable-active-high; -@@ -401,6 +402,7 @@ &usb_dwc3 { - dr_mode = "host"; - #address-cells = <1>; - #size-cells = <0>; -+ vbus-supply = <&usb3_hub_5v>; - status = "okay"; - - hub_2_0: hub@1 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0357-UPSTREAM-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux-lts-kmhv2/0357-UPSTREAM-dts-riscv-spacemit-correct-32k-clock-freque.patch new file mode 100644 index 0000000000..8bcc27f67e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0357-UPSTREAM-dts-riscv-spacemit-correct-32k-clock-freque.patch @@ -0,0 +1,48 @@ +From 9d04d67bbe15d5b1dda5eac0ba8ec11c26b4ec0d Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:57:29 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: correct 32k clock + frequency + +The 32k oscillator's clock frequency is actually 32768Hz, so correct it. + +Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") +Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") +Link: https://patch.msgid.link/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3c350f6284d8ea5e7a9648241b2e9604f2262d42) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- + arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 2ed5cc24e505..cba160c5edc5 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -333,7 +333,7 @@ vctcxo_3m: clock-3m { + + osc_32k: clock-32k { + compatible = "fixed-clock"; +- clock-frequency = <32000>; ++ clock-frequency = <32768>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 01124ff429a2..9e3c005f7bdf 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { + + osc_32k: clock-32k { + compatible = "fixed-clock"; +- clock-frequency = <32000>; ++ clock-frequency = <32768>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch deleted file mode 100644 index 39245052d3..0000000000 --- a/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch +++ /dev/null @@ -1,769 +0,0 @@ -From a19f30eaeebdca312c928a1bd82a354ba9ce2e8e Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 26 Apr 2026 09:34:48 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU - unit address - -Previous the CPU unit address cpu of sg2044 use decimal, it is -not following the general convention for unit addresses of the -OF. Convent the unit address to hex to resolve this problem. - -The introduces a small change for the CPU node name, but it should -nothing since there is no direct full-path reference to these -CPU nodes. - -Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") -Signed-off-by: Inochi Amaoto -Reviewed-by: Chen Wang -Reviewed-by: Guo Ren -Link: https://lore.kernel.org/r/20260426013449.694435-2-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- - 1 file changed, 118 insertions(+), 118 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -index 3135409c2149..f66a382c95bd 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -@@ -14,7 +14,7 @@ cpus { - - cpu0: cpu@0 { - compatible = "thead,c920", "riscv"; -- reg = <0>; -+ reg = <0x0>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { - - cpu1: cpu@1 { - compatible = "thead,c920", "riscv"; -- reg = <1>; -+ reg = <0x1>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { - - cpu2: cpu@2 { - compatible = "thead,c920", "riscv"; -- reg = <2>; -+ reg = <0x2>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { - - cpu3: cpu@3 { - compatible = "thead,c920", "riscv"; -- reg = <3>; -+ reg = <0x3>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { - - cpu4: cpu@4 { - compatible = "thead,c920", "riscv"; -- reg = <4>; -+ reg = <0x4>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { - - cpu5: cpu@5 { - compatible = "thead,c920", "riscv"; -- reg = <5>; -+ reg = <0x5>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { - - cpu6: cpu@6 { - compatible = "thead,c920", "riscv"; -- reg = <6>; -+ reg = <0x6>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { - - cpu7: cpu@7 { - compatible = "thead,c920", "riscv"; -- reg = <7>; -+ reg = <0x7>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { - - cpu8: cpu@8 { - compatible = "thead,c920", "riscv"; -- reg = <8>; -+ reg = <0x8>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { - - cpu9: cpu@9 { - compatible = "thead,c920", "riscv"; -- reg = <9>; -+ reg = <0x9>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { - }; - }; - -- cpu10: cpu@10 { -+ cpu10: cpu@a { - compatible = "thead,c920", "riscv"; -- reg = <10>; -+ reg = <0xa>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { - }; - }; - -- cpu11: cpu@11 { -+ cpu11: cpu@b { - compatible = "thead,c920", "riscv"; -- reg = <11>; -+ reg = <0xb>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { - }; - }; - -- cpu12: cpu@12 { -+ cpu12: cpu@c { - compatible = "thead,c920", "riscv"; -- reg = <12>; -+ reg = <0xc>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { - }; - }; - -- cpu13: cpu@13 { -+ cpu13: cpu@d { - compatible = "thead,c920", "riscv"; -- reg = <13>; -+ reg = <0xd>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { - }; - }; - -- cpu14: cpu@14 { -+ cpu14: cpu@e { - compatible = "thead,c920", "riscv"; -- reg = <14>; -+ reg = <0xe>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { - }; - }; - -- cpu15: cpu@15 { -+ cpu15: cpu@f { - compatible = "thead,c920", "riscv"; -- reg = <15>; -+ reg = <0xf>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { - }; - }; - -- cpu16: cpu@16 { -+ cpu16: cpu@10 { - compatible = "thead,c920", "riscv"; -- reg = <16>; -+ reg = <0x10>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { - }; - }; - -- cpu17: cpu@17 { -+ cpu17: cpu@11 { - compatible = "thead,c920", "riscv"; -- reg = <17>; -+ reg = <0x11>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { - }; - }; - -- cpu18: cpu@18 { -+ cpu18: cpu@12 { - compatible = "thead,c920", "riscv"; -- reg = <18>; -+ reg = <0x12>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { - }; - }; - -- cpu19: cpu@19 { -+ cpu19: cpu@13 { - compatible = "thead,c920", "riscv"; -- reg = <19>; -+ reg = <0x13>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { - }; - }; - -- cpu20: cpu@20 { -+ cpu20: cpu@14 { - compatible = "thead,c920", "riscv"; -- reg = <20>; -+ reg = <0x14>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { - }; - }; - -- cpu21: cpu@21 { -+ cpu21: cpu@15 { - compatible = "thead,c920", "riscv"; -- reg = <21>; -+ reg = <0x15>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { - }; - }; - -- cpu22: cpu@22 { -+ cpu22: cpu@16 { - compatible = "thead,c920", "riscv"; -- reg = <22>; -+ reg = <0x16>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { - }; - }; - -- cpu23: cpu@23 { -+ cpu23: cpu@17 { - compatible = "thead,c920", "riscv"; -- reg = <23>; -+ reg = <0x17>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { - }; - }; - -- cpu24: cpu@24 { -+ cpu24: cpu@18 { - compatible = "thead,c920", "riscv"; -- reg = <24>; -+ reg = <0x18>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { - }; - }; - -- cpu25: cpu@25 { -+ cpu25: cpu@19 { - compatible = "thead,c920", "riscv"; -- reg = <25>; -+ reg = <0x19>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { - }; - }; - -- cpu26: cpu@26 { -+ cpu26: cpu@1a { - compatible = "thead,c920", "riscv"; -- reg = <26>; -+ reg = <0x1a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { - }; - }; - -- cpu27: cpu@27 { -+ cpu27: cpu@1b { - compatible = "thead,c920", "riscv"; -- reg = <27>; -+ reg = <0x1b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { - }; - }; - -- cpu28: cpu@28 { -+ cpu28: cpu@1c { - compatible = "thead,c920", "riscv"; -- reg = <28>; -+ reg = <0x1c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { - }; - }; - -- cpu29: cpu@29 { -+ cpu29: cpu@1d { - compatible = "thead,c920", "riscv"; -- reg = <29>; -+ reg = <0x1d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { - }; - }; - -- cpu30: cpu@30 { -+ cpu30: cpu@1e { - compatible = "thead,c920", "riscv"; -- reg = <30>; -+ reg = <0x1e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { - }; - }; - -- cpu31: cpu@31 { -+ cpu31: cpu@1f { - compatible = "thead,c920", "riscv"; -- reg = <31>; -+ reg = <0x1f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { - }; - }; - -- cpu32: cpu@32 { -+ cpu32: cpu@20 { - compatible = "thead,c920", "riscv"; -- reg = <32>; -+ reg = <0x20>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { - }; - }; - -- cpu33: cpu@33 { -+ cpu33: cpu@21 { - compatible = "thead,c920", "riscv"; -- reg = <33>; -+ reg = <0x21>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { - }; - }; - -- cpu34: cpu@34 { -+ cpu34: cpu@22 { - compatible = "thead,c920", "riscv"; -- reg = <34>; -+ reg = <0x22>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { - }; - }; - -- cpu35: cpu@35 { -+ cpu35: cpu@23 { - compatible = "thead,c920", "riscv"; -- reg = <35>; -+ reg = <0x23>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { - }; - }; - -- cpu36: cpu@36 { -+ cpu36: cpu@24 { - compatible = "thead,c920", "riscv"; -- reg = <36>; -+ reg = <0x24>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { - }; - }; - -- cpu37: cpu@37 { -+ cpu37: cpu@25 { - compatible = "thead,c920", "riscv"; -- reg = <37>; -+ reg = <0x25>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { - }; - }; - -- cpu38: cpu@38 { -+ cpu38: cpu@26 { - compatible = "thead,c920", "riscv"; -- reg = <38>; -+ reg = <0x26>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { - }; - }; - -- cpu39: cpu@39 { -+ cpu39: cpu@27 { - compatible = "thead,c920", "riscv"; -- reg = <39>; -+ reg = <0x27>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { - }; - }; - -- cpu40: cpu@40 { -+ cpu40: cpu@28 { - compatible = "thead,c920", "riscv"; -- reg = <40>; -+ reg = <0x28>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { - }; - }; - -- cpu41: cpu@41 { -+ cpu41: cpu@29 { - compatible = "thead,c920", "riscv"; -- reg = <41>; -+ reg = <0x29>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { - }; - }; - -- cpu42: cpu@42 { -+ cpu42: cpu@2a { - compatible = "thead,c920", "riscv"; -- reg = <42>; -+ reg = <0x2a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { - }; - }; - -- cpu43: cpu@43 { -+ cpu43: cpu@2b { - compatible = "thead,c920", "riscv"; -- reg = <43>; -+ reg = <0x2b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { - }; - }; - -- cpu44: cpu@44 { -+ cpu44: cpu@2c { - compatible = "thead,c920", "riscv"; -- reg = <44>; -+ reg = <0x2c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { - }; - }; - -- cpu45: cpu@45 { -+ cpu45: cpu@2d { - compatible = "thead,c920", "riscv"; -- reg = <45>; -+ reg = <0x2d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { - }; - }; - -- cpu46: cpu@46 { -+ cpu46: cpu@2e { - compatible = "thead,c920", "riscv"; -- reg = <46>; -+ reg = <0x2e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { - }; - }; - -- cpu47: cpu@47 { -+ cpu47: cpu@2f { - compatible = "thead,c920", "riscv"; -- reg = <47>; -+ reg = <0x2f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { - }; - }; - -- cpu48: cpu@48 { -+ cpu48: cpu@30 { - compatible = "thead,c920", "riscv"; -- reg = <48>; -+ reg = <0x30>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { - }; - }; - -- cpu49: cpu@49 { -+ cpu49: cpu@31 { - compatible = "thead,c920", "riscv"; -- reg = <49>; -+ reg = <0x31>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { - }; - }; - -- cpu50: cpu@50 { -+ cpu50: cpu@32 { - compatible = "thead,c920", "riscv"; -- reg = <50>; -+ reg = <0x32>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { - }; - }; - -- cpu51: cpu@51 { -+ cpu51: cpu@33 { - compatible = "thead,c920", "riscv"; -- reg = <51>; -+ reg = <0x33>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { - }; - }; - -- cpu52: cpu@52 { -+ cpu52: cpu@34 { - compatible = "thead,c920", "riscv"; -- reg = <52>; -+ reg = <0x34>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { - }; - }; - -- cpu53: cpu@53 { -+ cpu53: cpu@35 { - compatible = "thead,c920", "riscv"; -- reg = <53>; -+ reg = <0x35>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { - }; - }; - -- cpu54: cpu@54 { -+ cpu54: cpu@36 { - compatible = "thead,c920", "riscv"; -- reg = <54>; -+ reg = <0x36>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { - }; - }; - -- cpu55: cpu@55 { -+ cpu55: cpu@37 { - compatible = "thead,c920", "riscv"; -- reg = <55>; -+ reg = <0x37>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { - }; - }; - -- cpu56: cpu@56 { -+ cpu56: cpu@38 { - compatible = "thead,c920", "riscv"; -- reg = <56>; -+ reg = <0x38>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { - }; - }; - -- cpu57: cpu@57 { -+ cpu57: cpu@39 { - compatible = "thead,c920", "riscv"; -- reg = <57>; -+ reg = <0x39>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { - }; - }; - -- cpu58: cpu@58 { -+ cpu58: cpu@3a { - compatible = "thead,c920", "riscv"; -- reg = <58>; -+ reg = <0x3a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { - }; - }; - -- cpu59: cpu@59 { -+ cpu59: cpu@3b { - compatible = "thead,c920", "riscv"; -- reg = <59>; -+ reg = <0x3b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { - }; - }; - -- cpu60: cpu@60 { -+ cpu60: cpu@3c { - compatible = "thead,c920", "riscv"; -- reg = <60>; -+ reg = <0x3c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { - }; - }; - -- cpu61: cpu@61 { -+ cpu61: cpu@3d { - compatible = "thead,c920", "riscv"; -- reg = <61>; -+ reg = <0x3d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { - }; - }; - -- cpu62: cpu@62 { -+ cpu62: cpu@3e { - compatible = "thead,c920", "riscv"; -- reg = <62>; -+ reg = <0x3e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { - }; - }; - -- cpu63: cpu@63 { -+ cpu63: cpu@3f { - compatible = "thead,c920", "riscv"; -- reg = <63>; -+ reg = <0x3f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0358-UPSTREAM-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux-lts-kmhv2/0358-UPSTREAM-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch new file mode 100644 index 0000000000..6a9f6f6270 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0358-UPSTREAM-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch @@ -0,0 +1,93 @@ +From 5a9239b601536fb198a2c13be9e6741d874df8fb Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:12:14 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: dt-bindings: add SpacemiT K3 SoC + compatible + +Add the spacemit,k3-i2s compatible string for the K3 SoC I2S +controller. The K3 I2S IP is the same as K1 but requires additional +clocks: a dedicated sysclk_div clock, along with common_sysclk and +common_bclk which are shared across multiple I2S controllers on K3. + +Acked-by: Rob Herring (Arm) +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-k3-i2s-v3-1-08e3eb811d93@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 6bc6b28c031484092ce1f829f59e4768e12b268e) +Signed-off-by: Han Gao +--- + .../bindings/sound/spacemit,k1-i2s.yaml | 31 +++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +index 55bd0b307d22..240d90402e4f 100644 +--- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml ++++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +@@ -4,7 +4,7 @@ + $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: K1 I2S controller ++title: SpacemiT K1/K3 I2S controller + + description: + The I2S bus (Inter-IC sound bus) is a serial link for digital +@@ -15,27 +15,54 @@ maintainers: + + allOf: + - $ref: dai-common.yaml# ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k3-i2s ++ then: ++ properties: ++ clocks: ++ minItems: 7 ++ clock-names: ++ minItems: 7 ++ else: ++ properties: ++ clocks: ++ maxItems: 4 ++ clock-names: ++ maxItems: 4 + + properties: + compatible: +- const: spacemit,k1-i2s ++ enum: ++ - spacemit,k1-i2s ++ - spacemit,k3-i2s + + reg: + maxItems: 1 + + clocks: ++ minItems: 4 + items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller ++ - description: clock for I2S sysclk divider ++ - description: clock for I2S common sysclk ++ - description: clock for I2S common bclk + + clock-names: ++ minItems: 4 + items: + - const: sysclk + - const: bclk + - const: bus + - const: func ++ - const: sysclk_div ++ - const: c_sysclk ++ - const: c_bclk + + dmas: + minItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch deleted file mode 100644 index 56f743e220..0000000000 --- a/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch +++ /dev/null @@ -1,1095 +0,0 @@ -From 1e554a628178f25ce798d80c22f6e32c9013f918 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 26 Apr 2026 09:34:49 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU - unit address - -Previous the CPU unit address cpu of sg2042 use decimal, it is -not following the general convention for unit addresses of the -OF. Convent the unit address to hex to resolve this problem. - -The introduces a small change for the CPU node name, but it should -affect nothing since there is no direct full-path reference to -these CPU nodes. - -Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") -Signed-off-by: Inochi Amaoto -Tested-by: Chen Wang # Pioneerbox. -Reviewed-by: Guo Ren -Reviewed-by: Chen Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260426013449.694435-3-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- - 1 file changed, 118 insertions(+), 118 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -index 509488eee432..fd8906b313d2 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -@@ -263,7 +263,7 @@ cpu0: cpu@0 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <0>; -+ reg = <0x0>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -291,7 +291,7 @@ cpu1: cpu@1 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <1>; -+ reg = <0x1>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -319,7 +319,7 @@ cpu2: cpu@2 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <2>; -+ reg = <0x2>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -347,7 +347,7 @@ cpu3: cpu@3 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <3>; -+ reg = <0x3>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -375,7 +375,7 @@ cpu4: cpu@4 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <4>; -+ reg = <0x4>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -403,7 +403,7 @@ cpu5: cpu@5 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <5>; -+ reg = <0x5>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -431,7 +431,7 @@ cpu6: cpu@6 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <6>; -+ reg = <0x6>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -459,7 +459,7 @@ cpu7: cpu@7 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <7>; -+ reg = <0x7>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -487,7 +487,7 @@ cpu8: cpu@8 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <8>; -+ reg = <0x8>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -515,7 +515,7 @@ cpu9: cpu@9 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <9>; -+ reg = <0x9>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { - }; - }; - -- cpu10: cpu@10 { -+ cpu10: cpu@a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -543,7 +543,7 @@ cpu10: cpu@10 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <10>; -+ reg = <0xa>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { - }; - }; - -- cpu11: cpu@11 { -+ cpu11: cpu@b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -571,7 +571,7 @@ cpu11: cpu@11 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <11>; -+ reg = <0xb>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { - }; - }; - -- cpu12: cpu@12 { -+ cpu12: cpu@c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -599,7 +599,7 @@ cpu12: cpu@12 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <12>; -+ reg = <0xc>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { - }; - }; - -- cpu13: cpu@13 { -+ cpu13: cpu@d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -627,7 +627,7 @@ cpu13: cpu@13 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <13>; -+ reg = <0xd>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { - }; - }; - -- cpu14: cpu@14 { -+ cpu14: cpu@e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -655,7 +655,7 @@ cpu14: cpu@14 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <14>; -+ reg = <0xe>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { - }; - }; - -- cpu15: cpu@15 { -+ cpu15: cpu@f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -683,7 +683,7 @@ cpu15: cpu@15 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <15>; -+ reg = <0xf>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { - }; - }; - -- cpu16: cpu@16 { -+ cpu16: cpu@10 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -711,7 +711,7 @@ cpu16: cpu@16 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <16>; -+ reg = <0x10>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { - }; - }; - -- cpu17: cpu@17 { -+ cpu17: cpu@11 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -739,7 +739,7 @@ cpu17: cpu@17 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <17>; -+ reg = <0x11>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { - }; - }; - -- cpu18: cpu@18 { -+ cpu18: cpu@12 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -767,7 +767,7 @@ cpu18: cpu@18 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <18>; -+ reg = <0x12>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { - }; - }; - -- cpu19: cpu@19 { -+ cpu19: cpu@13 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -795,7 +795,7 @@ cpu19: cpu@19 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <19>; -+ reg = <0x13>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { - }; - }; - -- cpu20: cpu@20 { -+ cpu20: cpu@14 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -823,7 +823,7 @@ cpu20: cpu@20 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <20>; -+ reg = <0x14>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { - }; - }; - -- cpu21: cpu@21 { -+ cpu21: cpu@15 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -851,7 +851,7 @@ cpu21: cpu@21 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <21>; -+ reg = <0x15>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { - }; - }; - -- cpu22: cpu@22 { -+ cpu22: cpu@16 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -879,7 +879,7 @@ cpu22: cpu@22 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <22>; -+ reg = <0x16>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { - }; - }; - -- cpu23: cpu@23 { -+ cpu23: cpu@17 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -907,7 +907,7 @@ cpu23: cpu@23 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <23>; -+ reg = <0x17>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { - }; - }; - -- cpu24: cpu@24 { -+ cpu24: cpu@18 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -935,7 +935,7 @@ cpu24: cpu@24 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <24>; -+ reg = <0x18>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { - }; - }; - -- cpu25: cpu@25 { -+ cpu25: cpu@19 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -963,7 +963,7 @@ cpu25: cpu@25 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <25>; -+ reg = <0x19>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { - }; - }; - -- cpu26: cpu@26 { -+ cpu26: cpu@1a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -991,7 +991,7 @@ cpu26: cpu@26 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <26>; -+ reg = <0x1a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { - }; - }; - -- cpu27: cpu@27 { -+ cpu27: cpu@1b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1019,7 +1019,7 @@ cpu27: cpu@27 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <27>; -+ reg = <0x1b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { - }; - }; - -- cpu28: cpu@28 { -+ cpu28: cpu@1c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1047,7 +1047,7 @@ cpu28: cpu@28 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <28>; -+ reg = <0x1c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { - }; - }; - -- cpu29: cpu@29 { -+ cpu29: cpu@1d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1075,7 +1075,7 @@ cpu29: cpu@29 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <29>; -+ reg = <0x1d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { - }; - }; - -- cpu30: cpu@30 { -+ cpu30: cpu@1e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1103,7 +1103,7 @@ cpu30: cpu@30 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <30>; -+ reg = <0x1e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { - }; - }; - -- cpu31: cpu@31 { -+ cpu31: cpu@1f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1131,7 +1131,7 @@ cpu31: cpu@31 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <31>; -+ reg = <0x1f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { - }; - }; - -- cpu32: cpu@32 { -+ cpu32: cpu@20 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1159,7 +1159,7 @@ cpu32: cpu@32 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <32>; -+ reg = <0x20>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { - }; - }; - -- cpu33: cpu@33 { -+ cpu33: cpu@21 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1187,7 +1187,7 @@ cpu33: cpu@33 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <33>; -+ reg = <0x21>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { - }; - }; - -- cpu34: cpu@34 { -+ cpu34: cpu@22 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1215,7 +1215,7 @@ cpu34: cpu@34 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <34>; -+ reg = <0x22>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { - }; - }; - -- cpu35: cpu@35 { -+ cpu35: cpu@23 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1243,7 +1243,7 @@ cpu35: cpu@35 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <35>; -+ reg = <0x23>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { - }; - }; - -- cpu36: cpu@36 { -+ cpu36: cpu@24 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1271,7 +1271,7 @@ cpu36: cpu@36 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <36>; -+ reg = <0x24>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { - }; - }; - -- cpu37: cpu@37 { -+ cpu37: cpu@25 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1299,7 +1299,7 @@ cpu37: cpu@37 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <37>; -+ reg = <0x25>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { - }; - }; - -- cpu38: cpu@38 { -+ cpu38: cpu@26 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1327,7 +1327,7 @@ cpu38: cpu@38 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <38>; -+ reg = <0x26>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { - }; - }; - -- cpu39: cpu@39 { -+ cpu39: cpu@27 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1355,7 +1355,7 @@ cpu39: cpu@39 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <39>; -+ reg = <0x27>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { - }; - }; - -- cpu40: cpu@40 { -+ cpu40: cpu@28 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1383,7 +1383,7 @@ cpu40: cpu@40 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <40>; -+ reg = <0x28>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { - }; - }; - -- cpu41: cpu@41 { -+ cpu41: cpu@29 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1411,7 +1411,7 @@ cpu41: cpu@41 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <41>; -+ reg = <0x29>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { - }; - }; - -- cpu42: cpu@42 { -+ cpu42: cpu@2a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1439,7 +1439,7 @@ cpu42: cpu@42 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <42>; -+ reg = <0x2a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { - }; - }; - -- cpu43: cpu@43 { -+ cpu43: cpu@2b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1467,7 +1467,7 @@ cpu43: cpu@43 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <43>; -+ reg = <0x2b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { - }; - }; - -- cpu44: cpu@44 { -+ cpu44: cpu@2c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1495,7 +1495,7 @@ cpu44: cpu@44 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <44>; -+ reg = <0x2c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { - }; - }; - -- cpu45: cpu@45 { -+ cpu45: cpu@2d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1523,7 +1523,7 @@ cpu45: cpu@45 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <45>; -+ reg = <0x2d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { - }; - }; - -- cpu46: cpu@46 { -+ cpu46: cpu@2e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1551,7 +1551,7 @@ cpu46: cpu@46 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <46>; -+ reg = <0x2e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { - }; - }; - -- cpu47: cpu@47 { -+ cpu47: cpu@2f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1579,7 +1579,7 @@ cpu47: cpu@47 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <47>; -+ reg = <0x2f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { - }; - }; - -- cpu48: cpu@48 { -+ cpu48: cpu@30 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1607,7 +1607,7 @@ cpu48: cpu@48 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <48>; -+ reg = <0x30>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { - }; - }; - -- cpu49: cpu@49 { -+ cpu49: cpu@31 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1635,7 +1635,7 @@ cpu49: cpu@49 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <49>; -+ reg = <0x31>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { - }; - }; - -- cpu50: cpu@50 { -+ cpu50: cpu@32 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1663,7 +1663,7 @@ cpu50: cpu@50 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <50>; -+ reg = <0x32>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { - }; - }; - -- cpu51: cpu@51 { -+ cpu51: cpu@33 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1691,7 +1691,7 @@ cpu51: cpu@51 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <51>; -+ reg = <0x33>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { - }; - }; - -- cpu52: cpu@52 { -+ cpu52: cpu@34 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1719,7 +1719,7 @@ cpu52: cpu@52 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <52>; -+ reg = <0x34>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { - }; - }; - -- cpu53: cpu@53 { -+ cpu53: cpu@35 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1747,7 +1747,7 @@ cpu53: cpu@53 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <53>; -+ reg = <0x35>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { - }; - }; - -- cpu54: cpu@54 { -+ cpu54: cpu@36 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1775,7 +1775,7 @@ cpu54: cpu@54 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <54>; -+ reg = <0x36>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { - }; - }; - -- cpu55: cpu@55 { -+ cpu55: cpu@37 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1803,7 +1803,7 @@ cpu55: cpu@55 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <55>; -+ reg = <0x37>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { - }; - }; - -- cpu56: cpu@56 { -+ cpu56: cpu@38 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1831,7 +1831,7 @@ cpu56: cpu@56 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <56>; -+ reg = <0x38>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { - }; - }; - -- cpu57: cpu@57 { -+ cpu57: cpu@39 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1859,7 +1859,7 @@ cpu57: cpu@57 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <57>; -+ reg = <0x39>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { - }; - }; - -- cpu58: cpu@58 { -+ cpu58: cpu@3a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1887,7 +1887,7 @@ cpu58: cpu@58 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <58>; -+ reg = <0x3a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { - }; - }; - -- cpu59: cpu@59 { -+ cpu59: cpu@3b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1915,7 +1915,7 @@ cpu59: cpu@59 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <59>; -+ reg = <0x3b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { - }; - }; - -- cpu60: cpu@60 { -+ cpu60: cpu@3c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1943,7 +1943,7 @@ cpu60: cpu@60 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <60>; -+ reg = <0x3c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { - }; - }; - -- cpu61: cpu@61 { -+ cpu61: cpu@3d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1971,7 +1971,7 @@ cpu61: cpu@61 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <61>; -+ reg = <0x3d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { - }; - }; - -- cpu62: cpu@62 { -+ cpu62: cpu@3e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1999,7 +1999,7 @@ cpu62: cpu@62 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <62>; -+ reg = <0x3e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { - }; - }; - -- cpu63: cpu@63 { -+ cpu63: cpu@3f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -2027,7 +2027,7 @@ cpu63: cpu@63 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <63>; -+ reg = <0x3f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0359-UPSTREAM-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux-lts-kmhv2/0359-UPSTREAM-ASoC-spacemit-add-K3-SoC-support-with-addit.patch new file mode 100644 index 0000000000..17706c3876 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0359-UPSTREAM-ASoC-spacemit-add-K3-SoC-support-with-addit.patch @@ -0,0 +1,114 @@ +From e8e01a1507354c98f3a65db6a5bbf170677c3d57 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:12:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: add K3 SoC support with + additional clocks + +Add support for the SpacemiT K3 SoC I2S controller, which shares the +same IP as K1 but requires additional clocks: sysclk_div, c_sysclk, +and c_bclk. These clocks only exist on K3 and are not present on K1. +The sysclk_div clock is present on most K3 I2S controllers except I2S1. +The c_sysclk and c_bclk clocks are shared across multiple I2S +controllers on K3. + +Use devm_clk_get_optional_enabled() to acquire these clocks so that +the driver works on both K1 (where they are absent) and K3 without +needing SoC-specific match data. For K3, the sysclk_div rate is set +before sysclk in set_sysclk, and the common clock rates are configured +in hw_params based on the sample rate. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-k3-i2s-v3-2-08e3eb811d93@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 1c6ca2ca5c1bdc97912cf3f9b4a1e186919a6a98) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 36 +++++++++++++++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 03cca5d84503..3df94b4ca5a5 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -53,6 +53,9 @@ struct spacemit_i2s_dev { + struct clk *sysclk; + struct clk *bclk; + struct clk *sspa_clk; ++ struct clk *sysclk_div; ++ struct clk *c_sysclk; ++ struct clk *c_bclk; + + struct snd_dmaengine_dai_dma_data capture_dma_data; + struct snd_dmaengine_dai_dma_data playback_dma_data; +@@ -206,6 +209,14 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + params_rate(params) * + data_bits; + ++ ret = clk_set_rate(i2s->c_sysclk, bclk_rate * 2); ++ if (ret) ++ return ret; ++ ++ ret = clk_set_rate(i2s->c_bclk, bclk_rate); ++ if (ret) ++ return ret; ++ + ret = clk_set_rate(i2s->bclk, bclk_rate); + if (ret) + return ret; +@@ -217,10 +228,17 @@ static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, + unsigned int freq, int dir) + { + struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev); ++ int ret; + + if (freq == 0) + return 0; + ++ if (i2s->sysclk_div) { ++ ret = clk_set_rate(i2s->sysclk_div, freq); ++ if (ret) ++ return ret; ++ } ++ + return clk_set_rate(i2s->sysclk, freq); + } + +@@ -435,6 +453,21 @@ static int spacemit_i2s_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(i2s->dev, PTR_ERR(clk), "failed to enable sspa clock\n"); + ++ i2s->sysclk_div = devm_clk_get_optional_enabled(i2s->dev, "sysclk_div"); ++ if (IS_ERR(i2s->sysclk_div)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk_div), ++ "failed to enable sysclk_div clock\n"); ++ ++ i2s->c_sysclk = devm_clk_get_optional_enabled(i2s->dev, "c_sysclk"); ++ if (IS_ERR(i2s->c_sysclk)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_sysclk), ++ "failed to enable c_sysclk clock\n"); ++ ++ i2s->c_bclk = devm_clk_get_optional_enabled(i2s->dev, "c_bclk"); ++ if (IS_ERR(i2s->c_bclk)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_bclk), ++ "failed to enable c_bclk clock\n"); ++ + i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(i2s->base)) + return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n"); +@@ -459,6 +492,7 @@ static int spacemit_i2s_probe(struct platform_device *pdev) + + static const struct of_device_id spacemit_i2s_of_match[] = { + { .compatible = "spacemit,k1-i2s", }, ++ { .compatible = "spacemit,k3-i2s", }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match); +@@ -473,4 +507,4 @@ static struct platform_driver spacemit_i2s_driver = { + module_platform_driver(spacemit_i2s_driver); + + MODULE_LICENSE("GPL"); +-MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1/K3 SoC"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch deleted file mode 100644 index 3978b9eca3..0000000000 --- a/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 344151a10b042115f283ccb3ceb2241243f4f16a Mon Sep 17 00:00:00 2001 -From: Nam Cao -Date: Tue, 7 Apr 2026 14:06:39 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: Fix fast_unaligned_access_speed_key not - getting initialized - -The static key fast_unaligned_access_speed_key is supposed to be -initialized after check_unaligned_access_all_cpus() has been completed. - -However, check_unaligned_access_all_cpus() has been moved to late_initcall -while setting fast_unaligned_access_speed_key still happens at -arch_initcall_sync, thus the static key does not get properly initialized. - -fast_unaligned_access_speed_key can still be initialized in CPU hotplug -events, but that cannot be relied on. - -Move fast_unaligned_access_speed_key's initialization into -check_unaligned_access_all_cpus() to fix this issue. This also prevent -someone from moving one initcall while forgetting the other in the future. - -Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") -Reported-by: Michael Neuling -Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ -Signed-off-by: Nam Cao -Link: https://lore.kernel.org/r/20260407120639.4006031-1-namcao@linutronix.de -Signed-off-by: Han Gao ---- - arch/riscv/kernel/unaligned_access_speed.c | 15 ++++----------- - 1 file changed, 4 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c -index 70b5e6927620..5e224cc48c62 100644 ---- a/arch/riscv/kernel/unaligned_access_speed.c -+++ b/arch/riscv/kernel/unaligned_access_speed.c -@@ -223,17 +223,6 @@ static void set_unaligned_access_static_branches(void) - modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); - } - --static int __init lock_and_set_unaligned_access_static_branch(void) --{ -- cpus_read_lock(); -- set_unaligned_access_static_branches(); -- cpus_read_unlock(); -- -- return 0; --} -- --arch_initcall_sync(lock_and_set_unaligned_access_static_branch); -- - static int riscv_online_cpu(unsigned int cpu) - { - int ret = cpu_online_unaligned_access_init(cpu); -@@ -491,6 +480,10 @@ static int __init check_unaligned_access_all_cpus(void) - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu_vec, NULL); - -+ cpus_read_lock(); -+ set_unaligned_access_static_branches(); -+ cpus_read_unlock(); -+ - return 0; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0360-UPSTREAM-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux-lts-kmhv2/0360-UPSTREAM-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch new file mode 100644 index 0000000000..4cf0690bef --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0360-UPSTREAM-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch @@ -0,0 +1,98 @@ +From 50fa7e06cba360d45ba4e526225eaf114699b5eb Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:33:57 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: soc-dai: add shared BCLK clock for + cross-DAI rate constraints + +Add a bclk field to struct snd_soc_dai and a helper function +snd_soc_dai_set_bclk_clk() that platform drivers can use to declare +which clock is their BCLK. + +Also cache the bclk_ratio in snd_soc_dai_set_bclk_ratio() so that +the framework can use it later in hw_rule evaluation for TDM +configurations where BCLK = rate * slots * slot_width. + +When multiple DAIs on the same card share the same physical BCLK +(detected via clk_is_match()), the ASoC core can automatically +constrain their hw_params so that the resulting BCLK rates are +compatible. This commit adds the data structure support; the actual +constraint logic follows in the next patch. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-i2s-same-blk-v4-1-a71a86faaa20@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 94bdfad3a665da68731deb56b0fe80f00a3e6da8) +Signed-off-by: Han Gao +--- + include/sound/soc-dai.h | 7 +++++++ + sound/soc/soc-dai.c | 18 ++++++++++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h +index 224396927aef..6d3a0ce02fd8 100644 +--- a/include/sound/soc-dai.h ++++ b/include/sound/soc-dai.h +@@ -17,6 +17,7 @@ + struct snd_pcm_substream; + struct snd_soc_dapm_widget; + struct snd_compr_stream; ++struct clk; + + /* + * DAI hardware audio formats. +@@ -173,6 +174,8 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, + + int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); + ++void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); ++ + /* Digital Audio interface formatting */ + int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); + u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); +@@ -451,6 +454,10 @@ struct snd_soc_dai { + unsigned int symmetric_channels; + unsigned int symmetric_sample_bits; + ++ /* shared BCLK clock for cross-DAI rate constraints */ ++ struct clk *bclk; ++ unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ ++ + /* parent platform/codec */ + struct snd_soc_component *component; + +diff --git a/sound/soc/soc-dai.c b/sound/soc/soc-dai.c +index f231b4174b5f..a32501d017f6 100644 +--- a/sound/soc/soc-dai.c ++++ b/sound/soc/soc-dai.c +@@ -116,10 +116,28 @@ int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) + dai->driver->ops->set_bclk_ratio) + ret = dai->driver->ops->set_bclk_ratio(dai, ratio); + ++ if (!ret) ++ dai->bclk_ratio = ratio; ++ + return soc_dai_ret(dai, ret); + } + EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio); + ++/** ++ * snd_soc_dai_set_bclk_clk - set the BCLK clock for shared clock detection ++ * @dai: DAI ++ * @bclk: BCLK clock pointer (or NULL to clear) ++ * ++ * When multiple DAIs share the same physical BCLK (detected via ++ * clk_is_match()), the ASoC core will automatically constrain their ++ * hw_params so that the resulting BCLK rates are compatible. ++ */ ++void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk) ++{ ++ dai->bclk = bclk; ++} ++EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_clk); ++ + int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd) + { + struct snd_soc_dai *dai; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch deleted file mode 100644 index 4ca22126b9..0000000000 --- a/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6f609eb72f740d3d3be5b596fca48b7d76f3a181 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 8 Apr 2026 00:01:43 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count to - 16 - -The SG2042 MSI controller has one 32-bit doorbell register, and each bit -corresponds to an interrupt. At a glance, it seems that the MSI -controller can support 32 interrupts; however the PCI MSI capability -only supports 16-bit messages, which makes the high 16 interrupts -unusable in such way. - -Reduce the MSI count to 16 to prevent producing MSI message values that -cannot fit 16-bit integers. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260407160143.1182430-1-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index 3af770549742..7eab0655f150 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { - reg-names = "clr", "doorbell"; - msi-controller; - #msi-cells = <0>; -- msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; -+ msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; - }; - - rpgate: clock-controller@7030010368 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0361-UPSTREAM-ASoC-soc-pcm-add-DEFINE_GUARD-for-snd_soc_c.patch b/SPECS/linux-lts-kmhv2/0361-UPSTREAM-ASoC-soc-pcm-add-DEFINE_GUARD-for-snd_soc_c.patch new file mode 100644 index 0000000000..20a1ebbdbd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0361-UPSTREAM-ASoC-soc-pcm-add-DEFINE_GUARD-for-snd_soc_c.patch @@ -0,0 +1,36 @@ +From 97c539645d73a837bfe7f50f9eccec5474f2e8d4 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:33:58 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: soc-pcm: add DEFINE_GUARD for + snd_soc_card_mutex + +Define a guard class wrapping snd_soc_card_mutex_lock() and +snd_soc_card_mutex_unlock() so that scope-based locking can be used +while still picking up the SND_SOC_CARD_CLASS_RUNTIME lockdep subclass. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-i2s-same-blk-v4-2-a71a86faaa20@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 2555c62275a10bb7dfb4476ebe73d48df11f3112) +Signed-off-by: Han Gao +--- + sound/soc/soc-pcm.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c +index 99299364c9ba..f83d06b753b0 100644 +--- a/sound/soc/soc-pcm.c ++++ b/sound/soc/soc-pcm.c +@@ -26,6 +26,9 @@ + #include + #include + ++ ++DEFINE_GUARD(snd_soc_card_mutex, struct snd_soc_card *, ++ snd_soc_card_mutex_lock(_T), snd_soc_card_mutex_unlock(_T)) + #define soc_pcm_ret(rtd, ret) _soc_pcm_ret(rtd, __func__, ret) + static inline int _soc_pcm_ret(struct snd_soc_pcm_runtime *rtd, + const char *func, int ret) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch deleted file mode 100644 index fe8f74bcb4..0000000000 --- a/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch +++ /dev/null @@ -1,93 +0,0 @@ -From a42a4931c6355f9aec78b37eacf4e7f01afaa772 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:46:50 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add - SpacemiT K3 PWM support - -The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 -generation, while the difference is that one additional bus clock is -added. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org -Signed-off-by: Han Gao ---- - .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- - 1 file changed, 38 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -index 8df327e52810..f1422a401b6b 100644 ---- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -+++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -@@ -15,7 +15,9 @@ allOf: - properties: - compatible: - contains: -- const: spacemit,k1-pwm -+ enum: -+ - spacemit,k1-pwm -+ - spacemit,k3-pwm - then: - properties: - "#pwm-cells": -@@ -26,6 +28,26 @@ allOf: - const: 1 - description: | - Used for specifying the period length in nanoseconds. -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - spacemit,k3-pwm -+ then: -+ required: -+ - clock-names -+ properties: -+ clocks: -+ minItems: 2 -+ clock-names: -+ minItems: 2 -+ else: -+ properties: -+ clocks: -+ maxItems: 1 -+ clock-names: -+ maxItems: 1 - - properties: - compatible: -@@ -36,7 +58,9 @@ properties: - - marvell,pxa168-pwm - - marvell,pxa910-pwm - - items: -- - const: spacemit,k1-pwm -+ - enum: -+ - spacemit,k1-pwm -+ - spacemit,k3-pwm - - const: marvell,pxa910-pwm - - reg: -@@ -47,7 +71,18 @@ properties: - description: Number of cells in a pwm specifier. - - clocks: -- maxItems: 1 -+ minItems: 1 -+ items: -+ - description: The function clock -+ - description: An optional bus clock -+ -+ clock-names: -+ minItems: 1 -+ maxItems: 2 -+ oneOf: -+ - items: -+ - const: func -+ - const: bus - - resets: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0362-UPSTREAM-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux-lts-kmhv2/0362-UPSTREAM-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch new file mode 100644 index 0000000000..474ad453d7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0362-UPSTREAM-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch @@ -0,0 +1,183 @@ +From b7ac20b9e9a352e22f9cfa322714fd27dd30d1bd Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:33:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: soc-pcm: constrain hw_params when DAIs + share the same BCLK + +When multiple CPU DAIs on the same sound card share the same physical +BCLK, add a hw_rule during PCM open that constrains the sample rate so +the resulting BCLK rate stays consistent across all sharing DAIs. + +The rule callback scans all DAIs on the card at hw_refine time, looking +for an active peer that shares the same physical BCLK (via +clk_is_match()) and has already completed hw_params (checked via +dai->symmetric_rate != 0). This ensures the constraint uses the real +BCLK rate established by the peer's clk_set_rate() in hw_params, not a +stale boot-time default. + +The first DAI to complete hw_params is unconstrained (no active peer +yet); subsequent DAIs are constrained to match. + +The rule supports two modes: +- If the DAI has an explicit bclk_ratio set (e.g. for TDM where + BCLK = rate * slots * slot_width), the rate is constrained to + active_bclk_rate / bclk_ratio. +- Otherwise, the default formula BCLK = rate * channels * sample_bits + is used to derive the valid rate range. + +The constraint is purely additive: DAIs that do not set a bclk clock +pointer are completely unaffected. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-i2s-same-blk-v4-3-a71a86faaa20@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit c8c2ffd722a6e497b9c6bb9961a7afb6ee5e2c28) +Signed-off-by: Han Gao +--- + sound/soc/soc-pcm.c | 116 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 116 insertions(+) + +diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c +index f83d06b753b0..e09f262fb827 100644 +--- a/sound/soc/soc-pcm.c ++++ b/sound/soc/soc-pcm.c +@@ -12,6 +12,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -470,6 +471,114 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream, + return 0; + } + ++/* ++ * Shared BCLK constraint: when multiple DAIs share the same physical BCLK, ++ * constrain hw_params so that the BCLK rate (rate * channels * sample_bits, ++ * or rate * slots * slot_width for TDM) remains consistent. ++ */ ++ ++static int soc_pcm_shared_bclk_rule_rate(struct snd_pcm_hw_params *params, ++ struct snd_pcm_hw_rule *rule) ++{ ++ struct snd_soc_dai *dai = rule->private; ++ struct snd_soc_card *card = dai->component->card; ++ struct snd_soc_pcm_runtime *rtd; ++ struct snd_soc_dai *other_dai; ++ unsigned long active_bclk_rate = 0; ++ struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); ++ struct snd_interval constraint = { .empty = 1 }; ++ unsigned int target_rate; ++ int i; ++ ++ /* Protect the rtd list traversal with the ASoC card mutex helper. */ ++ guard(snd_soc_card_mutex)(card); ++ ++ /* Scan all DAIs on the card for an active peer sharing the same BCLK */ ++ for_each_card_rtds(card, rtd) { ++ for_each_rtd_cpu_dais(rtd, i, other_dai) { ++ if (other_dai == dai) ++ continue; ++ if (!other_dai->bclk) ++ continue; ++ if (!snd_soc_dai_active(other_dai)) ++ continue; ++ /* ++ * Skip peers whose hw_params hasn't run yet. ++ * symmetric_rate is set by soc_pcm_set_dai_params() ++ * after snd_soc_dai_hw_params(), so non-zero means ++ * the DAI's clk_set_rate() has already executed. ++ */ ++ if (!other_dai->symmetric_rate) ++ continue; ++ if (!clk_is_match(dai->bclk, other_dai->bclk)) ++ continue; ++ ++ active_bclk_rate = clk_get_rate(other_dai->bclk); ++ if (active_bclk_rate) ++ goto found; ++ } ++ } ++ ++ return 0; ++ ++found: ++ if (dai->bclk_ratio) { ++ /* ++ * Driver has set an explicit BCLK ratio (e.g. for TDM where ++ * BCLK = rate * slots * slot_width). The only valid rate is ++ * active_bclk_rate / bclk_ratio. ++ */ ++ target_rate = active_bclk_rate / dai->bclk_ratio; ++ ++ constraint.min = target_rate; ++ constraint.max = target_rate; ++ } else { ++ struct snd_interval *channels = hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_CHANNELS); ++ struct snd_interval *sample_bits = hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_SAMPLE_BITS); ++ ++ /* ++ * Default: BCLK = rate * channels * sample_bits. ++ * Calculate the range of valid rates given the current ++ * channel and sample_bits intervals. ++ */ ++ if (!channels->min || !sample_bits->min) ++ return 0; ++ ++ constraint.max = active_bclk_rate / ++ ((unsigned long)channels->min * sample_bits->min); ++ ++ if (channels->max && sample_bits->max) ++ constraint.min = active_bclk_rate / ++ ((unsigned long)channels->max * sample_bits->max); ++ else ++ constraint.min = constraint.max; ++ } ++ ++ constraint.integer = 1; ++ constraint.empty = 0; ++ ++ return snd_interval_refine(rate, &constraint); ++} ++ ++static int soc_pcm_apply_shared_bclk(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ if (!dai->bclk) ++ return 0; ++ ++ dev_dbg(dai->dev, ++ "ASoC: registering shared BCLK rate constraint\n"); ++ ++ return snd_pcm_hw_rule_add(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ soc_pcm_shared_bclk_rule_rate, dai, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ SNDRV_PCM_HW_PARAM_SAMPLE_BITS, ++ -1); ++} ++ + static int soc_pcm_params_symmetry(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) + { +@@ -894,6 +1003,13 @@ static int __soc_pcm_open(struct snd_soc_pcm_runtime *rtd, + if (ret != 0) + goto err; + } ++ ++ /* Shared BCLK constraint across DAIs on the same card */ ++ for_each_rtd_cpu_dais(rtd, i, dai) { ++ ret = soc_pcm_apply_shared_bclk(substream, dai); ++ if (ret != 0) ++ goto err; ++ } + dynamic: + snd_soc_runtime_activate(rtd, substream->stream); + ret = 0; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch deleted file mode 100644 index 8346eff059..0000000000 --- a/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 2173dcb3b9c7cd083216f7561ca2c80cc779e6c3 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:46:51 +0000 -Subject: [RUYI PATCH] FROMLIST: pwm: pxa: Add optional bus clock - -Add one secondary optional bus clock for the PWM PXA driver, also keep it -compatible with old single clock. - -The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and -enable it during probe phase. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org -Signed-off-by: Han Gao ---- - drivers/pwm/pwm-pxa.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c -index 0f5bdb0e395e..80d2fa10919f 100644 ---- a/drivers/pwm/pwm-pxa.c -+++ b/drivers/pwm/pwm-pxa.c -@@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) - const struct platform_device_id *id = platform_get_device_id(pdev); - struct pwm_chip *chip; - struct pxa_pwm_chip *pc; -+ struct clk *bus_clk; - struct device *dev = &pdev->dev; - struct reset_control *rst; - int ret = 0; -@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) - return PTR_ERR(chip); - pc = to_pxa_pwm_chip(chip); - -- pc->clk = devm_clk_get(dev, NULL); -+ bus_clk = devm_clk_get_optional_enabled(dev, "bus"); -+ if (IS_ERR(bus_clk)) -+ return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); -+ -+ /* Get named func clk if bus clock is valid */ -+ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); - if (IS_ERR(pc->clk)) - return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0363-UPSTREAM-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux-lts-kmhv2/0363-UPSTREAM-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch new file mode 100644 index 0000000000..ab2203fd1b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0363-UPSTREAM-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch @@ -0,0 +1,44 @@ +From 77d0825c6e1782e7a2f5484d9433738ef80b6f6d Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:05 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: gpio: dwapb: allow GPIO hogs + +GPIO hogs are described in the gpio.txt binding as automatic default +GPIO configuration items. + +Allow them for GPIO ports in DesignWare APB GPIO controller nodes. + +Cc: Hoan Tran +Cc: Linus Walleij +Cc: Bartosz Golaszewski +Cc: Serge Semin +Signed-off-by: Icenowy Zheng +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260507081710.4090814-8-zhengxingda@iscas.ac.cn +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit f76c8be440e53465a306c95a7d50ca8675252f82) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +index ab2afc0e4153..79679a14a02f 100644 +--- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml ++++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +@@ -95,6 +95,12 @@ patternProperties: + '#interrupt-cells': + const: 2 + ++ patternProperties: ++ "^.+-hog(-[0-9]+)?$": ++ type: object ++ required: ++ - gpio-hog ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch deleted file mode 100644 index 169b4e07b6..0000000000 --- a/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch +++ /dev/null @@ -1,45 +0,0 @@ -From a9afe33a20c57d9588e3a723da69fe92572f5726 Mon Sep 17 00:00:00 2001 -From: Chen Pei -Date: Thu, 9 Apr 2026 19:47:36 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: select - HAVE_BUILDTIME_MCOUNT_SORT - -RISC-V already satisfies all prerequisites for build-time mcount sorting: -the sorttable host tool handles EM_RISCV in its machine-type dispatch, and -the __mcount_loc section entries are stored as direct virtual addresses in -the final vmlinux binary, so no relocation processing is required during -the sort step. - -Select HAVE_BUILDTIME_MCOUNT_SORT so that BUILDTIME_MCOUNT_SORT is -automatically enabled when DYNAMIC_FTRACE is configured. This allows -sorttable to sort the __mcount_loc section at link time, making the -run-time ftrace initialisation path skip the software sort and reducing -kernel startup overhead. - -Verified with CONFIG_FTRACE_SORT_STARTUP_TEST=y, which confirms that -the section produced by the build is already in ascending order: - - [ 0.000000] ftrace section at ffffffff81015a60 sorted properly - -Signed-off-by: Chen Pei -Link: https://lore.kernel.org/r/20260409114736.907-1-cp0613@linux.alibaba.com -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 1aa7fec41c09..5cc386e56d13 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -150,6 +150,7 @@ config RISCV - select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD - select HAVE_ARCH_VMAP_STACK if MMU && 64BIT - select HAVE_ASM_MODVERSIONS -+ select HAVE_BUILDTIME_MCOUNT_SORT - select HAVE_CONTEXT_TRACKING_USER - select HAVE_DEBUG_KMEMLEAK - select HAVE_DMA_CONTIGUOUS if MMU --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0364-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux-lts-kmhv2/0364-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch new file mode 100644 index 0000000000..a5df66a978 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0364-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch @@ -0,0 +1,181 @@ +From ee545472effccb2aca0af0209c8fede99d5a4ed5 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:49 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: add PMIC + and power infrastructure + +Enable i2c8 and add the connected SpacemiT P1 PMIC with its related +regulators for the board's power infrastructure and voltage regulation +support. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-2-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit e2dac7c7a3a8970feeeb758f782ce86b89625ebd) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 134 ++++++++++++++++++ + 1 file changed, 134 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 29e333b670cf..653e5a1bf41b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -17,6 +17,7 @@ / { + aliases { + ethernet0 = ð0; + serial0 = &uart0; ++ i2c8 = &i2c8; + }; + + chosen { +@@ -33,6 +34,15 @@ led1 { + default-state = "on"; + }; + }; ++ ++ reg_vcc_4v: regulator-vcc-4v { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC4V0"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + &emmc { +@@ -72,6 +82,130 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-0 = <&i2c8_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch deleted file mode 100644 index 63660577e2..0000000000 --- a/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 62c0719d1e7faf6136869e6f6da6b1f069f63523 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 18 May 2026 18:00:30 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable USB3 on OrangePi - R2S - -Enable the DWC3 USB3.0 controller and its associated PHY on the -OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 -ports, but the USB2 ports are handled by a separate controller. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260518100030.2354606-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index de75f6aac740..1ecc40749e5a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -21,6 +21,19 @@ aliases { - chosen { - stdout-path = "serial0"; - }; -+ -+ vcc5v0_usb: regulator-vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combo_phy { -+ status = "okay"; - }; - - &emmc { -@@ -90,3 +103,13 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ vbus-supply = <&vcc5v0_usb>; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0365-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-24c02-.patch b/SPECS/linux-lts-kmhv2/0365-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-24c02-.patch new file mode 100644 index 0000000000..35ab70a8b8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0365-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-24c02-.patch @@ -0,0 +1,90 @@ +From e2f8a478f91b32fb059faf0d944707eb7c2b360d Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:50 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: add 24c02 + eeprom + +Enable i2c2 and add the connected GT24C02B EEPROM. + +It contains an ONIE TLV table: +=> tlv_eeprom +TLV: 0 +[ 12.162] TlvInfo Header: +[ 12.162] Id String: TlvInfo +[ 12.165] Version: 1 +[ 12.168] Total Length: 58 +[ 12.171] TLV Name Code Len Value +[ 12.175] -------------------- ---- --- ----- +[ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro +[ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX +[ 12.189] Unknown 0x41 1 0x02 +[ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX +[ 12.199] MAC Addresses 0x2A 2 2 +[ 12.203] CRC-32 0xFE 4 0x395ECD34 +[ 12.207] Checksum is valid. + +(With 0x41 as TLV_CODE_DDR_CSNUM) + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-3-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 6bc75cfa56e885c2eab80e215f0a610075505846) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 33 +++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 653e5a1bf41b..b8e73eed8e62 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -17,6 +17,7 @@ / { + aliases { + ethernet0 = ð0; + serial0 = &uart0; ++ i2c2 = &i2c2; + i2c8 = &i2c8; + }; + +@@ -82,6 +83,38 @@ &pdma { + status = "okay"; + }; + ++&i2c2 { ++ pinctrl-0 = <&i2c2_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ ++ pagesize = <8>; ++ read-only; ++ size = <256>; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ product-name { ++ }; ++ ++ serial-number { ++ }; ++ ++ mac-address { ++ #nvmem-cell-cells = <1>; ++ }; ++ ++ num-macs { ++ }; ++ }; ++ }; ++}; ++ + &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch deleted file mode 100644 index 84486826fc..0000000000 --- a/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5d9676891cd5d6a9735391e8b346e75d7f6559c9 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:57:29 +0000 -Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: correct 32k clock - frequency - -The 32k oscillator's clock frequency is actually 32768Hz, so correct it. - -Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") -Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- - arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index aefdbbadc9ef..8774a00a854b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -341,7 +341,7 @@ vctcxo_3m: clock-3m { - - osc_32k: clock-32k { - compatible = "fixed-clock"; -- clock-frequency = <32000>; -+ clock-frequency = <32768>; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 81ad575f16a5..0408929f7949 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { - - osc_32k: clock-32k { - compatible = "fixed-clock"; -- clock-frequency = <32000>; -+ clock-frequency = <32768>; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0366-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux-lts-kmhv2/0366-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch new file mode 100644 index 0000000000..081b65364f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0366-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch @@ -0,0 +1,91 @@ +From ec1239c7ad79bc3f3381acb33cbbc01de935cfd8 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:51 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: enable + QSPI and add SPI NOR + +Add the QSPI controller node and describe the attached SPI NOR flash +(Winbond W25Q64FWSSAQ). + +Add a corresponding vendor flash partition layout. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-4-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 735b1b205d07bf7bfa55b1f50f5485b9cc42a251) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index b8e73eed8e62..74841cffd5f5 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -44,6 +44,15 @@ reg_vcc_4v: regulator-vcc-4v { + regulator-boot-on; + regulator-always-on; + }; ++ ++ reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { ++ compatible = "regulator-fixed"; ++ regulator-name = "QSPI_VCC1833"; ++ regulator-min-microvolt = <1833000>; ++ regulator-max-microvolt = <1833000>; ++ regulator-always-on; ++ vin-supply = <&buck4_3v3>; ++ }; + }; + + &emmc { +@@ -239,6 +248,47 @@ dldo7 { + }; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <®_qspi_vcc1v833>; ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x10000>; ++ }; ++ private@10000 { ++ reg = <0x10000 0x10000>; ++ }; ++ fsbl@20000 { ++ reg = <0x20000 0x40000>; ++ }; ++ env@60000 { ++ reg = <0x60000 0x10000>; ++ }; ++ opensbi@70000 { ++ reg = <0x70000 0x30000>; ++ }; ++ uboot@a0000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch deleted file mode 100644 index ae80025a53..0000000000 --- a/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 50c5274eb867073ad2b53bef51e6d9d19aa9ac2a Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 15:33:09 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC - compatible - -Add the spacemit,k3-i2s compatible string for the K3 SoC I2S -controller. The K3 I2S IP is the same as K1 but requires additional -clocks: a dedicated sysclk_div clock, along with common_sysclk and -common_bclk which are shared across multiple I2S controllers on K3. - -Acked-by: Rob Herring (Arm) -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-1-9cdbf95b7533@linux.spacemit.com -Signed-off-by: Han Gao ---- - .../bindings/sound/spacemit,k1-i2s.yaml | 31 +++++++++++++++++-- - 1 file changed, 29 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -index 55bd0b307d22..240d90402e4f 100644 ---- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -+++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -@@ -4,7 +4,7 @@ - $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: K1 I2S controller -+title: SpacemiT K1/K3 I2S controller - - description: - The I2S bus (Inter-IC sound bus) is a serial link for digital -@@ -15,27 +15,54 @@ maintainers: - - allOf: - - $ref: dai-common.yaml# -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: spacemit,k3-i2s -+ then: -+ properties: -+ clocks: -+ minItems: 7 -+ clock-names: -+ minItems: 7 -+ else: -+ properties: -+ clocks: -+ maxItems: 4 -+ clock-names: -+ maxItems: 4 - - properties: - compatible: -- const: spacemit,k1-i2s -+ enum: -+ - spacemit,k1-i2s -+ - spacemit,k3-i2s - - reg: - maxItems: 1 - - clocks: -+ minItems: 4 - items: - - description: clock for I2S sysclk - - description: clock for I2S bclk - - description: clock for I2S bus - - description: clock for I2S controller -+ - description: clock for I2S sysclk divider -+ - description: clock for I2S common sysclk -+ - description: clock for I2S common bclk - - clock-names: -+ minItems: 4 - items: - - const: sysclk - - const: bclk - - const: bus - - const: func -+ - const: sysclk_div -+ - const: c_sysclk -+ - const: c_bclk - - dmas: - minItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0367-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux-lts-kmhv2/0367-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch new file mode 100644 index 0000000000..cadb0c3aba --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0367-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch @@ -0,0 +1,97 @@ +From f74e19d0b02f487933837056c19f7c73e05a26f3 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:52 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: enable + USB 3 ports + +Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) +and usbphy2 (USB 2 PHY) on the MusePi Pro board. + +The board uses a VLI VL817 hub, providing four ports. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-5-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 83c658c7a82304a2bc944cdd4a5b4f98d19322f0) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 52 +++++++++++++++++++ + 1 file changed, 52 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 74841cffd5f5..b284bf416880 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -53,6 +53,26 @@ reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { + regulator-always-on; + vin-supply = <&buck4_3v3>; + }; ++ ++ reg_5v_vbus: regulator-5v-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "5V_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ ++ enable-active-high; ++ }; ++ ++ reg_vcc5v_hub: regulator-vcc5v-hub { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V0_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ ++ enable-active-high; ++ }; + }; + + &emmc { +@@ -65,6 +85,10 @@ &emmc { + status = "okay"; + }; + ++&combo_phy { ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -294,3 +318,31 @@ &uart0 { + pinctrl-names = "default"; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ vbus-supply = <®_5v_vbus>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <®_vcc5v_hub>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <®_vcc5v_hub>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch deleted file mode 100644 index f0c06195d2..0000000000 --- a/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch +++ /dev/null @@ -1,112 +0,0 @@ -From ff69086b4bd33d60ba9c418d37ac92992aae8876 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 15:33:10 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: add K3 SoC support with - additional clocks - -Add support for the SpacemiT K3 SoC I2S controller, which shares the -same IP as K1 but requires additional clocks: sysclk_div, c_sysclk, -and c_bclk. These clocks only exist on K3 and are not present on K1. -The sysclk_div clock is present on most K3 I2S controllers except I2S1. -The c_sysclk and c_bclk clocks are shared across multiple I2S -controllers on K3. - -Use devm_clk_get_optional_enabled() to acquire these clocks so that -the driver works on both K1 (where they are absent) and K3 without -needing SoC-specific match data. For K3, the sysclk_div rate is set -before sysclk in set_sysclk, and the common clock rates are configured -in hw_params based on the sample rate. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-2-9cdbf95b7533@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 36 +++++++++++++++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 03cca5d84503..3df94b4ca5a5 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -53,6 +53,9 @@ struct spacemit_i2s_dev { - struct clk *sysclk; - struct clk *bclk; - struct clk *sspa_clk; -+ struct clk *sysclk_div; -+ struct clk *c_sysclk; -+ struct clk *c_bclk; - - struct snd_dmaengine_dai_dma_data capture_dma_data; - struct snd_dmaengine_dai_dma_data playback_dma_data; -@@ -206,6 +209,14 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - params_rate(params) * - data_bits; - -+ ret = clk_set_rate(i2s->c_sysclk, bclk_rate * 2); -+ if (ret) -+ return ret; -+ -+ ret = clk_set_rate(i2s->c_bclk, bclk_rate); -+ if (ret) -+ return ret; -+ - ret = clk_set_rate(i2s->bclk, bclk_rate); - if (ret) - return ret; -@@ -217,10 +228,17 @@ static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, - unsigned int freq, int dir) - { - struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev); -+ int ret; - - if (freq == 0) - return 0; - -+ if (i2s->sysclk_div) { -+ ret = clk_set_rate(i2s->sysclk_div, freq); -+ if (ret) -+ return ret; -+ } -+ - return clk_set_rate(i2s->sysclk, freq); - } - -@@ -435,6 +453,21 @@ static int spacemit_i2s_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(i2s->dev, PTR_ERR(clk), "failed to enable sspa clock\n"); - -+ i2s->sysclk_div = devm_clk_get_optional_enabled(i2s->dev, "sysclk_div"); -+ if (IS_ERR(i2s->sysclk_div)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk_div), -+ "failed to enable sysclk_div clock\n"); -+ -+ i2s->c_sysclk = devm_clk_get_optional_enabled(i2s->dev, "c_sysclk"); -+ if (IS_ERR(i2s->c_sysclk)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_sysclk), -+ "failed to enable c_sysclk clock\n"); -+ -+ i2s->c_bclk = devm_clk_get_optional_enabled(i2s->dev, "c_bclk"); -+ if (IS_ERR(i2s->c_bclk)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_bclk), -+ "failed to enable c_bclk clock\n"); -+ - i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(i2s->base)) - return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n"); -@@ -459,6 +492,7 @@ static int spacemit_i2s_probe(struct platform_device *pdev) - - static const struct of_device_id spacemit_i2s_of_match[] = { - { .compatible = "spacemit,k1-i2s", }, -+ { .compatible = "spacemit,k3-i2s", }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match); -@@ -473,4 +507,4 @@ static struct platform_driver spacemit_i2s_driver = { - module_platform_driver(spacemit_i2s_driver); - - MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1/K3 SoC"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0368-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux-lts-kmhv2/0368-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch new file mode 100644 index 0000000000..8a6cb446cf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0368-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch @@ -0,0 +1,77 @@ +From 557a84f989292b858f0edca6c24633d20aa1b406 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:53 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: enable + PCIe ports + +Enable the two PCIe controllers along with their associated PHYs. They +are routed to the M.2 M-key connector and to the PCIe slot. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-6-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit d9ab0a855ba13f1db3ae16539348714c74010a22) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index b284bf416880..898b537ba0bc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -36,6 +36,14 @@ led1 { + }; + }; + ++ reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PCIE_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "VCC4V0"; +@@ -272,6 +280,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <®_pcie_vcc_3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <®_pcie_vcc_3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch deleted file mode 100644 index 7eaa0d4690..0000000000 --- a/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 0151c24b6a7cffec1479bc57a27443328f1d2fef Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:42 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: soc-dai: add shared BCLK clock for - cross-DAI rate constraints - -Add a bclk field to struct snd_soc_dai and a helper function -snd_soc_dai_set_bclk_clk() that platform drivers can use to declare -which clock is their BCLK. - -Also cache the bclk_ratio in snd_soc_dai_set_bclk_ratio() so that -the framework can use it later in hw_rule evaluation for TDM -configurations where BCLK = rate * slots * slot_width. - -When multiple DAIs on the same card share the same physical BCLK -(detected via clk_is_match()), the ASoC core can automatically -constrain their hw_params so that the resulting BCLK rates are -compatible. This commit adds the data structure support; the actual -constraint logic follows in the next patch. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-1-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - include/sound/soc-dai.h | 7 +++++++ - sound/soc/soc-dai.c | 18 ++++++++++++++++++ - 2 files changed, 25 insertions(+) - -diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h -index 224396927aef..6d3a0ce02fd8 100644 ---- a/include/sound/soc-dai.h -+++ b/include/sound/soc-dai.h -@@ -17,6 +17,7 @@ - struct snd_pcm_substream; - struct snd_soc_dapm_widget; - struct snd_compr_stream; -+struct clk; - - /* - * DAI hardware audio formats. -@@ -173,6 +174,8 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, - - int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); - -+void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); -+ - /* Digital Audio interface formatting */ - int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); - u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); -@@ -451,6 +454,10 @@ struct snd_soc_dai { - unsigned int symmetric_channels; - unsigned int symmetric_sample_bits; - -+ /* shared BCLK clock for cross-DAI rate constraints */ -+ struct clk *bclk; -+ unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ -+ - /* parent platform/codec */ - struct snd_soc_component *component; - -diff --git a/sound/soc/soc-dai.c b/sound/soc/soc-dai.c -index f231b4174b5f..a32501d017f6 100644 ---- a/sound/soc/soc-dai.c -+++ b/sound/soc/soc-dai.c -@@ -116,10 +116,28 @@ int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) - dai->driver->ops->set_bclk_ratio) - ret = dai->driver->ops->set_bclk_ratio(dai, ratio); - -+ if (!ret) -+ dai->bclk_ratio = ratio; -+ - return soc_dai_ret(dai, ret); - } - EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio); - -+/** -+ * snd_soc_dai_set_bclk_clk - set the BCLK clock for shared clock detection -+ * @dai: DAI -+ * @bclk: BCLK clock pointer (or NULL to clear) -+ * -+ * When multiple DAIs share the same physical BCLK (detected via -+ * clk_is_match()), the ASoC core will automatically constrain their -+ * hw_params so that the resulting BCLK rates are compatible. -+ */ -+void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk) -+{ -+ dai->bclk = bclk; -+} -+EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_clk); -+ - int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd) - { - struct snd_soc_dai *dai; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0369-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux-lts-kmhv2/0369-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch new file mode 100644 index 0000000000..5854217cb5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0369-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch @@ -0,0 +1,35 @@ +From 207accf16e500677ac7c9b1005d049a90ed0cba5 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:54 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: set + default console baud rate + +Allow serial output with the same uboot/opensbi settings so the +console works without providing a cmdline. + +Signed-off-by: Andre Heider +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260513071958.29574-7-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit f125c6085fd775f09a316f61cc89a0ae86826895) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 898b537ba0bc..4aef287353ca 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -22,7 +22,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch deleted file mode 100644 index b2112c73cc..0000000000 --- a/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch +++ /dev/null @@ -1,186 +0,0 @@ -From 811d7e0186f2cec4b5ebbd7506439ef84e15a0ff Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:43 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: soc-pcm: constrain hw_params when DAIs - share the same BCLK - -When multiple CPU DAIs on the same sound card share the same physical -BCLK, add a hw_rule during PCM open that constrains the sample rate so -the resulting BCLK rate stays consistent across all sharing DAIs. - -The hw_rule is registered unconditionally for every DAI that has a bclk -clock pointer set. The actual peer scanning happens inside the rule -callback at hw_refine time: it walks all DAIs on the card, looking for -an active peer that shares the same physical BCLK (via clk_is_match()) -and has already completed hw_params (checked via dai->symmetric_rate -!= 0). This ensures the constraint uses the real BCLK rate established -by the peer's clk_set_rate() in hw_params, not a stale boot-time -default. - -The first DAI to complete hw_params is unconstrained (no active peer -yet); subsequent DAIs are constrained to match. - -The rule supports two modes: -- If the DAI has an explicit bclk_ratio set (e.g. for TDM where - BCLK = rate * slots * slot_width), the rate is constrained to - active_bclk_rate / bclk_ratio. -- Otherwise, the default formula BCLK = rate * channels * sample_bits - is used to derive the valid rate range. - -The constraint is purely additive: DAIs that do not set a bclk clock -pointer are completely unaffected. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-2-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/soc-pcm.c | 119 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 119 insertions(+) - -diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c -index 99299364c9ba..c6b01f802b10 100644 ---- a/sound/soc/soc-pcm.c -+++ b/sound/soc/soc-pcm.c -@@ -12,6 +12,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -467,6 +468,117 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream, - return 0; - } - -+/* -+ * Shared BCLK constraint: when multiple DAIs share the same physical BCLK, -+ * constrain hw_params so that the BCLK rate (rate * channels * sample_bits, -+ * or rate * slots * slot_width for TDM) remains consistent. -+ */ -+ -+static int soc_pcm_shared_bclk_rule_rate(struct snd_pcm_hw_params *params, -+ struct snd_pcm_hw_rule *rule) -+{ -+ struct snd_soc_dai *dai = rule->private; -+ struct snd_soc_card *card = dai->component->card; -+ struct snd_soc_pcm_runtime *rtd; -+ struct snd_soc_dai *other_dai; -+ unsigned long active_bclk_rate = 0; -+ struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); -+ struct snd_interval constraint = { .empty = 1 }; -+ unsigned int target_rate; -+ int i; -+ -+ /* -+ * Protect the rtd list traversal. No nesting: this callback runs -+ * from snd_pcm_hw_refine() which does not hold card->mutex. -+ */ -+ guard(mutex)(&card->mutex); -+ -+ /* Scan all DAIs on the card for an active peer sharing the same BCLK */ -+ for_each_card_rtds(card, rtd) { -+ for_each_rtd_cpu_dais(rtd, i, other_dai) { -+ if (other_dai == dai) -+ continue; -+ if (!other_dai->bclk) -+ continue; -+ if (!snd_soc_dai_active(other_dai)) -+ continue; -+ /* -+ * Skip peers whose hw_params hasn't run yet. -+ * symmetric_rate is set by soc_pcm_set_dai_params() -+ * after snd_soc_dai_hw_params(), so non-zero means -+ * the DAI's clk_set_rate() has already executed. -+ */ -+ if (!other_dai->symmetric_rate) -+ continue; -+ if (!clk_is_match(dai->bclk, other_dai->bclk)) -+ continue; -+ -+ active_bclk_rate = clk_get_rate(other_dai->bclk); -+ if (active_bclk_rate) -+ goto found; -+ } -+ } -+ -+ return 0; -+ -+found: -+ if (dai->bclk_ratio) { -+ /* -+ * Driver has set an explicit BCLK ratio (e.g. for TDM where -+ * BCLK = rate * slots * slot_width). The only valid rate is -+ * active_bclk_rate / bclk_ratio. -+ */ -+ target_rate = active_bclk_rate / dai->bclk_ratio; -+ -+ constraint.min = target_rate; -+ constraint.max = target_rate; -+ } else { -+ struct snd_interval *channels = hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_CHANNELS); -+ struct snd_interval *sample_bits = hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS); -+ -+ /* -+ * Default: BCLK = rate * channels * sample_bits. -+ * Calculate the range of valid rates given the current -+ * channel and sample_bits intervals. -+ */ -+ if (!channels->min || !sample_bits->min) -+ return 0; -+ -+ constraint.max = active_bclk_rate / -+ ((unsigned long)channels->min * sample_bits->min); -+ -+ if (channels->max && sample_bits->max) -+ constraint.min = active_bclk_rate / -+ ((unsigned long)channels->max * sample_bits->max); -+ else -+ constraint.min = constraint.max; -+ } -+ -+ constraint.integer = 1; -+ constraint.empty = 0; -+ -+ return snd_interval_refine(rate, &constraint); -+} -+ -+static int soc_pcm_apply_shared_bclk(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ if (!dai->bclk) -+ return 0; -+ -+ dev_dbg(dai->dev, -+ "ASoC: registering shared BCLK rate constraint\n"); -+ -+ return snd_pcm_hw_rule_add(substream->runtime, 0, -+ SNDRV_PCM_HW_PARAM_RATE, -+ soc_pcm_shared_bclk_rule_rate, dai, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS, -+ -1); -+} -+ - static int soc_pcm_params_symmetry(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) - { -@@ -891,6 +1003,13 @@ static int __soc_pcm_open(struct snd_soc_pcm_runtime *rtd, - if (ret != 0) - goto err; - } -+ -+ /* Shared BCLK constraint across DAIs on the same card */ -+ for_each_rtd_cpu_dais(rtd, i, dai) { -+ ret = soc_pcm_apply_shared_bclk(substream, dai); -+ if (ret != 0) -+ goto err; -+ } - dynamic: - snd_soc_runtime_activate(rtd, substream->stream); - ret = 0; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0370-UPSTREAM-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux-lts-kmhv2/0370-UPSTREAM-riscv-dts-spacemit-k3-Add-pwm-support.patch new file mode 100644 index 0000000000..ee40fb24cd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0370-UPSTREAM-riscv-dts-spacemit-k3-Add-pwm-support.patch @@ -0,0 +1,852 @@ +From fd6e40bc55165f03bde310bec4c7dfe51c8ef371 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 21 May 2026 00:24:41 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Add pwm support + +Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents +the pinctrl info which would easily help to enable them in future. + +Link: https://patch.msgid.link/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 844c29197366e25ad361cf725d80acb4f10e3e19) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ + 2 files changed, 810 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 23899d3f308a..252c64af76fe 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -56,6 +56,596 @@ i2c8-pins { + }; + }; + ++ /omit-if-no-ref/ ++ pwm0_0_cfg: pwm0-0-cfg { ++ pwm0-0-pins { ++ pinmux = ; /* pwm0 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0_1_cfg: pwm0-1-cfg { ++ pwm0-1-pins { ++ pinmux = ; /* pwm0 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_0_cfg: pwm1-0-cfg { ++ pwm1-0-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_1_cfg: pwm1-1-cfg { ++ pwm1-1-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_2_cfg: pwm1-2-cfg { ++ pwm1-2-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_0_cfg: pwm2-0-cfg { ++ pwm2-0-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_1_cfg: pwm2-1-cfg { ++ pwm2-1-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_2_cfg: pwm2-2-cfg { ++ pwm2-2-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_3_cfg: pwm2-3-cfg { ++ pwm2-3-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_0_cfg: pwm3-0-cfg { ++ pwm3-0-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_1_cfg: pwm3-1-cfg { ++ pwm3-1-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_2_cfg: pwm3-2-cfg { ++ pwm3-2-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_3_cfg: pwm3-3-cfg { ++ pwm3-3-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_0_cfg: pwm4-0-cfg { ++ pwm4-0-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_1_cfg: pwm4-1-cfg { ++ pwm4-1-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_2_cfg: pwm4-2-cfg { ++ pwm4-2-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_0_cfg: pwm5-0-cfg { ++ pwm5-0-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_1_cfg: pwm5-1-cfg { ++ pwm5-1-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_2_cfg: pwm5-2-cfg { ++ pwm5-2-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_0_cfg: pwm6-0-cfg { ++ pwm6-0-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_1_cfg: pwm6-1-cfg { ++ pwm6-1-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_2_cfg: pwm6-2-cfg { ++ pwm6-2-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_0_cfg: pwm7-0-cfg { ++ pwm7-0-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_1_cfg: pwm7-1-cfg { ++ pwm7-1-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_2_cfg: pwm7-2-cfg { ++ pwm7-2-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_0_cfg: pwm8-0-cfg { ++ pwm8-0-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_1_cfg: pwm8-1-cfg { ++ pwm8-1-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_2_cfg: pwm8-2-cfg { ++ pwm8-2-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_0_cfg: pwm9-0-cfg { ++ pwm9-0-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_1_cfg: pwm9-1-cfg { ++ pwm9-1-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_2_cfg: pwm9-2-cfg { ++ pwm9-2-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_0_cfg: pwm10-0-cfg { ++ pwm10-0-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_1_cfg: pwm10-1-cfg { ++ pwm10-1-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_2_cfg: pwm10-2-cfg { ++ pwm10-2-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11_0_cfg: pwm11-0-cfg { ++ pwm11-0-pins { ++ pinmux = ; /* pwm11 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11_1_cfg: pwm11-1-cfg { ++ pwm11-1-pins { ++ pinmux = ; /* pwm11 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12_0_cfg: pwm12-0-cfg { ++ pwm12-0-pins { ++ pinmux = ; /* pwm12 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12_1_cfg: pwm12-1-cfg { ++ pwm12-1-pins { ++ pinmux = ; /* pwm12 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_0_cfg: pwm13-0-cfg { ++ pwm13-0-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_1_cfg: pwm13-1-cfg { ++ pwm13-1-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_2_cfg: pwm13-2-cfg { ++ pwm13-2-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_0_cfg: pwm14-0-cfg { ++ pwm14-0-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_1_cfg: pwm14-1-cfg { ++ pwm14-1-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_2_cfg: pwm14-2-cfg { ++ pwm14-2-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_0_cfg: pwm15-0-cfg { ++ pwm15-0-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_1_cfg: pwm15-1-cfg { ++ pwm15-1-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_2_cfg: pwm15-2-cfg { ++ pwm15-2-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_0_cfg: pwm16-0-cfg { ++ pwm16-0-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_1_cfg: pwm16-1-cfg { ++ pwm16-1-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_2_cfg: pwm16-2-cfg { ++ pwm16-2-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_0_cfg: pwm17-0-cfg { ++ pwm17-0-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_1_cfg: pwm17-1-cfg { ++ pwm17-1-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_2_cfg: pwm17-2-cfg { ++ pwm17-2-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_0_cfg: pwm18-0-cfg { ++ pwm18-0-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_1_cfg: pwm18-1-cfg { ++ pwm18-1-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_2_cfg: pwm18-2-cfg { ++ pwm18-2-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_0_cfg: pwm19-0-cfg { ++ pwm19-0-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_1_cfg: pwm19-1-cfg { ++ pwm19-1-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_2_cfg: pwm19-2-cfg { ++ pwm19-2-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 9e3c005f7bdf..97cc9e2dd554 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -808,6 +808,226 @@ i2c8: i2c@d401d800 { + status = "disabled"; + }; + ++ pwm0: pwm@d401a000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM0>, ++ <&syscon_apbc CLK_APBC_PWM0_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM0>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@d401a400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM1>, ++ <&syscon_apbc CLK_APBC_PWM1_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM1>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@d401a800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM2>, ++ <&syscon_apbc CLK_APBC_PWM2_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM2>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@d401ac00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401ac00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM3>, ++ <&syscon_apbc CLK_APBC_PWM3_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM3>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@d401b000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM4>, ++ <&syscon_apbc CLK_APBC_PWM4_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM4>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@d401b400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM5>, ++ <&syscon_apbc CLK_APBC_PWM5_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM5>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@d401b800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM6>, ++ <&syscon_apbc CLK_APBC_PWM6_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM6>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@d401bc00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401bc00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM7>, ++ <&syscon_apbc CLK_APBC_PWM7_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM7>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@d4020000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM8>, ++ <&syscon_apbc CLK_APBC_PWM8_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM8>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@d4020400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM9>, ++ <&syscon_apbc CLK_APBC_PWM9_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM9>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@d4020800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM10>, ++ <&syscon_apbc CLK_APBC_PWM10_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM10>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@d4020c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM11>, ++ <&syscon_apbc CLK_APBC_PWM11_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM11>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@d4021000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM12>, ++ <&syscon_apbc CLK_APBC_PWM12_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM12>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@d4021400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM13>, ++ <&syscon_apbc CLK_APBC_PWM13_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM13>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@d4021800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM14>, ++ <&syscon_apbc CLK_APBC_PWM14_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM14>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@d4021c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM15>, ++ <&syscon_apbc CLK_APBC_PWM15_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM15>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm16: pwm@d4022000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM16>, ++ <&syscon_apbc CLK_APBC_PWM16_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM16>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm17: pwm@d4022400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM17>, ++ <&syscon_apbc CLK_APBC_PWM17_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM17>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm18: pwm@d4022800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM18>, ++ <&syscon_apbc CLK_APBC_PWM18_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM18>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm19: pwm@d4022c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM19>, ++ <&syscon_apbc CLK_APBC_PWM19_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM19>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch deleted file mode 100644 index ff936b2c7c..0000000000 --- a/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch +++ /dev/null @@ -1,37 +0,0 @@ -From ab006e609e125b2253d6016108a7ac52e642a192 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:44 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for - cross-DAI rate constraint - -On SpacemiT K3, multiple I2S controllers share the same physical BCLK -(c_bclk). Declare this clock via snd_soc_dai_set_bclk_clk() so the -ASoC core can automatically constrain hw_params when one controller is -already streaming. - -For K1, c_bclk is NULL (obtained via devm_clk_get_optional_enabled), -so this call is a no-op and behavior is unchanged. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-3-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 3df94b4ca5a5..1a02d7fcc7e1 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -323,6 +323,8 @@ static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai) - - spacemit_i2s_init(i2s); - -+ snd_soc_dai_set_bclk_clk(dai, i2s->c_bclk); -+ - return 0; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0371-UPSTREAM-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux-lts-kmhv2/0371-UPSTREAM-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch new file mode 100644 index 0000000000..8ac8b11460 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0371-UPSTREAM-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch @@ -0,0 +1,58 @@ +From 8fa4a6e89eabd9eeee5bce6b7db92337c1c77302 Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Sat, 6 Jun 2026 20:17:52 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: use sysfs_emit in cpu_show_ghostwrite + +Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is +preferred for formatting sysfs output because it provides safer bounds +checking. + +While the current code only emits fixed strings that fit easily within +PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. + +Signed-off-by: Thorsten Blum +Link: https://patch.msgid.link/20260510165420.109453-3-thorsten.blum@linux.dev +Signed-off-by: Paul Walmsley +(cherry picked from commit 7d0dec57e52c7b5e14ba4ab6f86e9c17b850f1ec) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/bugs.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c +index 3655fe7d678c..e5758e3f1c7e 100644 +--- a/arch/riscv/kernel/bugs.c ++++ b/arch/riscv/kernel/bugs.c +@@ -5,7 +5,7 @@ + + #include + #include +-#include ++#include + + #include + #include +@@ -46,15 +46,15 @@ ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *attr, c + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { + switch (ghostwrite_state) { + case UNAFFECTED: +- return sprintf(buf, "Not affected\n"); ++ return sysfs_emit(buf, "Not affected\n"); + case MITIGATED: +- return sprintf(buf, "Mitigation: xtheadvector disabled\n"); ++ return sysfs_emit(buf, "Mitigation: xtheadvector disabled\n"); + case VULNERABLE: + fallthrough; + default: +- return sprintf(buf, "Vulnerable\n"); ++ return sysfs_emit(buf, "Vulnerable\n"); + } +- } else { +- return sprintf(buf, "Not affected\n"); + } ++ ++ return sysfs_emit(buf, "Not affected\n"); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch deleted file mode 100644 index 26e3e584c6..0000000000 --- a/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fd1098639a4174a54cfc40a6fe40bbcb9569aee6 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 5 May 2026 09:53:34 -0400 -Subject: [RUYI PATCH] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC to - avoid 32-bit overflow - -NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * -BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures -before the result reaches the u64 nsec_per_word. - -Promote the multiplication to u64 by casting the first operand, which is -NSEC_PER_SEC. - -Fixes: efcd8b9d1111 ("spi: spacemit: introduce SpacemiT K1 SPI controller driver") -Suggested-by: Alex Elder -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202605050437.RS6mmV2b-lkp@intel.com/ -Closes: https://lore.kernel.org/oe-kbuild-all/202605050317.Tf9j487w-lkp@intel.com/ -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260505-spi-spacemit-k1-fix-overflow-v1-1-77564c2e4e86@riscstar.com -Signed-off-by: Han Gao ---- - drivers/spi/spi-spacemit-k1.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c -index 99db429db0b2..215fe66d27b4 100644 ---- a/drivers/spi/spi-spacemit-k1.c -+++ b/drivers/spi/spi-spacemit-k1.c -@@ -390,7 +390,7 @@ static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, - * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; - * We do the divide last for better accuracy. - */ -- nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; -+ nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; - nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); - - /* --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0372-UPSTREAM-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux-lts-kmhv2/0372-UPSTREAM-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch new file mode 100644 index 0000000000..ddab01031a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0372-UPSTREAM-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch @@ -0,0 +1,52 @@ +From a93178e11905ffbe2651c6f1c30c59732b11a4ba Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:09 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: Switch to pll2_d6 as parent + for PCIe clock + +According to SpacemiT updated docs, the PCIe master and slave clock's +parent is the pll2_d6 clock, so fix it. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit d8a4cef90b1a4ae9196a5bfba683eb9a0c75acdc) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index bb8b75bdbdb3..1a53b14739fe 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents[] = { + }; + CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); + +-CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); +-CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); +-CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); +-CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); +-CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); +-CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); +-CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); +-CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); +-CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); +-CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); ++CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); ++CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); ++CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); ++CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); ++CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); + + static const struct clk_parent_data emac_1588_parents[] = { + CCU_PARENT_NAME(vctcxo_24m), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch deleted file mode 100644 index 1ec5840379..0000000000 --- a/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 70157c501907a5cde732fdf89f3f458d3aba2959 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:16:59 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC - subsys clock controller - -TH1520 has a subsystem clock controller called MISC_SUBSYS in its -manual, mainly controlling clocks for USB and MMC/SD in non-TEE -environment. - -Add device tree binding for it. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-2-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- - include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ - 2 files changed, 13 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -index 9d058c00ab3d..d46d13597466 100644 ---- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -@@ -23,6 +23,7 @@ properties: - compatible: - enum: - - thead,th1520-clk-ap -+ - thead,th1520-clk-misc - - thead,th1520-clk-vo - - reg: -@@ -32,8 +33,8 @@ properties: - items: - - description: | - One input clock: -- - For "thead,th1520-clk-ap": the clock input must be the 24 MHz -- main oscillator. -+ - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clock -+ input must be the 24 MHz main oscillator. - - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, - which is configured by the AP clock controller. According to the - TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL -diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h -index 68b35cc61204..642c2a69a579 100644 ---- a/include/dt-bindings/clock/thead,th1520-clk-ap.h -+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h -@@ -128,4 +128,14 @@ - #define CLK_MIPIDSI1_PIXCLK 29 - #define CLK_HDMI_PIXCLK 30 - -+/* MISC clocks */ -+#define CLK_MISCSYS_ACLK 0 -+#define CLK_USB 1 -+#define CLK_USB_CTL_REF 2 -+#define CLK_USB_PHY_REF 3 -+#define CLK_USB_SUSPEND 4 -+#define CLK_EMMC 5 -+#define CLK_SDIO0 6 -+#define CLK_SDIO1 7 -+ - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0373-UPSTREAM-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux-lts-kmhv2/0373-UPSTREAM-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch new file mode 100644 index 0000000000..3fcf131ac8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0373-UPSTREAM-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch @@ -0,0 +1,37 @@ +From 53b13f1ef4c5ee060d5fc719b83e18200029aac8 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:10 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: Fix PCIe clock register + offset + +The offset of PCIe Clock CTRL register for port B and C controller was +wrongly swapped, correct it here. + +Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 2f20c859a82a291483a8b3f01cbfbb1642782a14) +Signed-off-by: Han Gao +--- + include/soc/spacemit/k3-syscon.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +index 0299bea065a0..a68255dd641f 100644 +--- a/include/soc/spacemit/k3-syscon.h ++++ b/include/soc/spacemit/k3-syscon.h +@@ -168,8 +168,8 @@ + #define APMU_CPU_C2_CLK_CTRL 0x394 + #define APMU_CPU_C3_CLK_CTRL 0x208 + #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 +-#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 +-#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 + #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 + #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 + #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch deleted file mode 100644 index 4e7272cafb..0000000000 --- a/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch +++ /dev/null @@ -1,124 +0,0 @@ -From ff7baa8d99b3acfa161a96f9d572688e8fbfb14f Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:00 +0800 -Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC - subsys clocks - -The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows -controlling of USB related clocks and MMC/SD controller AHB bus clocks. - -Add support for this clock controller, in order to enable USB support. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-3-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ - 1 file changed, 64 insertions(+) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index 3a6847f1c950..24f785f0b329 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", - static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, - 0x4, 0, 0); - -+static struct clk_fixed_factor usb_suspend_div_clk = { -+ .div = 24, -+ .mult = 1, -+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", -+ osc_24m_clk, -+ &clk_fixed_factor_ops, -+ 0), -+}; -+ -+static const struct clk_parent_data usb_suspend_parents[] = { -+ { .hw = &usb_suspend_div_clk.hw }, -+}; -+ -+static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_pd, -+ 0x0, 0, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data miscsys_aclk_pd[] = { -+ { .hw = &miscsys_aclk.gate.hw }, -+}; -+ -+static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, -+ CLK_IS_CRITICAL); -+static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_clk, -+ 0x4, 1, 0); -+static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_clk, -+ 0x4, 2, 0); -+static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", -+ usb_suspend_parents, 0x4, 3, 0); -+static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, -+ 0); -+static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, -+ 0); -+static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, 0, -+ 0); -+ - static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", - &gmac_pll_clk.common.hw, 10, 1, 0); - -@@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] = { - &hdmi_pixclk - }; - -+static struct ccu_gate *th1520_misc_gate_clks[] = { -+ &miscsys_aclk, -+ &usb_clk, -+ &usb_ctl_ref_clk, -+ &usb_phy_ref_clk, -+ &usb_suspend_clk, -+ &emmc_clk, -+ &sdio0_clk, -+ &sdio1_clk -+}; -+ - static const struct regmap_config th1520_clk_regmap_config = { - .reg_bits = 32, - .val_bits = 32, -@@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platdata = { - .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), - }; - -+static const struct th1520_plat_data th1520_misc_platdata = { -+ .th1520_gate_clks = th1520_misc_gate_clks, -+ -+ .nr_clks = CLK_SDIO1 + 1, -+ -+ .nr_gate_clks = ARRAY_SIZE(th1520_misc_gate_clks), -+}; -+ - /* - * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) - * when its parent, c910_clk, changes the rate. -@@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *pdev) - return ret; - } - -+ if (plat_data == &th1520_ap_platdata) { -+ ret = devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); -+ if (ret) -+ return ret; -+ } -+ - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); - if (ret) - return ret; -@@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = { - .compatible = "thead,th1520-clk-vo", - .data = &th1520_vo_platdata, - }, -+ { -+ .compatible = "thead,th1520-clk-misc", -+ .data = &th1520_misc_platdata, -+ }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, th1520_clk_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0374-UPSTREAM-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux-lts-kmhv2/0374-UPSTREAM-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch new file mode 100644 index 0000000000..70f651133b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0374-UPSTREAM-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch @@ -0,0 +1,36 @@ +From 8f46d831880adb7e2d1fd0f12e3decdfb1481f54 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:11 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: k3: Add PCIe DBI + clock IDs + +Add clock IDs of PCIe DBI (Data Bus Interface) clock. + +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 7a2db70a3196717bfb01415b6dde1f90d4291ab1) +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index b22336f3ae40..dfae52547cda 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -380,6 +380,11 @@ + #define CLK_APMU_ISIM_VCLK1 86 + #define CLK_APMU_ISIM_VCLK2 87 + #define CLK_APMU_ISIM_VCLK3 88 ++#define CLK_APMU_PCIE_PORTA_DBI 89 ++#define CLK_APMU_PCIE_PORTB_DBI 90 ++#define CLK_APMU_PCIE_PORTC_DBI 91 ++#define CLK_APMU_PCIE_PORTD_DBI 92 ++#define CLK_APMU_PCIE_PORTE_DBI 93 + + /* DCIU clocks */ + #define CLK_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch deleted file mode 100644 index 5712f59936..0000000000 --- a/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 25858e77df3fb64d1db8a210aa513630aa172761 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:01 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for - MISC clock controller - -The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller -mainly controlling USB-related clocks (which isn't utilized yet) and -MMC/SD controllers' AHB bus clocks. - -Add the device tree node for it along with the missing bus clock -references for MMC/SD controllers. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-4-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 2910249e1f0c..4d1e71227339 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -401,8 +401,8 @@ emmc: mmc@ffe7080000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -410,8 +410,8 @@ sdio0: mmc@ffe7090000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -419,8 +419,8 @@ sdio1: mmc@ffe70a0000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -568,6 +568,13 @@ rst_misc: reset-controller@ffec02c000 { - #reset-cells = <1>; - }; - -+ clk_misc: clock-controller@ffec02c100 { -+ compatible = "thead,th1520-clk-misc"; -+ reg = <0xff 0xec02c100 0x0 0x100>; -+ clocks = <&osc>; -+ #clock-cells = <1>; -+ }; -+ - rst_vp: reset-controller@ffecc30000 { - compatible = "thead,th1520-reset-vp"; - reg = <0xff 0xecc30000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0375-UPSTREAM-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux-lts-kmhv2/0375-UPSTREAM-clk-spacemit-k3-Add-PCIe-DBI-clock.patch new file mode 100644 index 0000000000..4f2a5c9ce1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0375-UPSTREAM-clk-spacemit-k3-Add-PCIe-DBI-clock.patch @@ -0,0 +1,64 @@ +From 081afca5f2f91c2228a833a5801c4728a834dd88 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: Add PCIe DBI clock + +Add PCIe DBI (Data Bus Interface) clock which was missing, This will +support PCIe driver to explicitly request and enable all clocks that +needed. + +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit a37c75d7b5bb7f3344b0e639b313ac5ace6244ff) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 1a53b14739fe..cb0c4277f72a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT + + CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); + CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0); + CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); + CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0); + CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); + CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0); + CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); + CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0); + CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); + CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0); + + static const struct clk_parent_data emac_1588_parents[] = { + CCU_PARENT_NAME(vctcxo_24m), +@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { + [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, + [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw, + [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, + [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, + [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch deleted file mode 100644 index d6fc48cce2..0000000000 --- a/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch +++ /dev/null @@ -1,102 +0,0 @@ -From bf1bce6b58599f811e5d960528b05a56606c6198 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:02 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head - TH1520 USB PHY - -The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom -glue logic configuring PHY parameters. - -Add a binding for it. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-5-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ - 1 file changed, 74 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml -new file mode 100644 -index 000000000000..37f5cfb95bad ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml -@@ -0,0 +1,74 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: T-Head TH1520 USB PHY -+ -+description: | -+ The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some -+ custom logic to configure PHY parameters. -+ -+maintainers: -+ - Icenowy Zheng -+ - Wei Fu -+ - Drew Fustini -+ -+properties: -+ compatible: -+ const: thead,th1520-usb-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 0 -+ -+ clocks: -+ items: -+ - description: PHY bus clock -+ - description: PHY reference clock -+ -+ clock-names: -+ items: -+ - const: bus -+ - const: ref -+ -+ resets: -+ items: -+ - description: PHY bus reset -+ - description: PHY reset -+ -+ reset-names: -+ items: -+ - const: bus -+ - const: phy -+ -+ avdd33-usb3-supply: -+ description: | -+ 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. -+ -+required: -+ - compatible -+ - "#phy-cells" -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - avdd33-usb3-supply -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@ec030000 { -+ compatible = "thead,th1520-usb-phy"; -+ reg = <0xec030000 0x10000>; -+ #phy-cells = <0>; -+ clocks = <&clk_misc 1>, <&clk_misc 3>; -+ clock-names = "bus", "ref"; -+ resets = <&rst_misc 6>, <&rst_misc 7>; -+ reset-names = "bus", "phy"; -+ avdd33-usb3-supply = <&avdd33_usb3>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0376-UPSTREAM-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux-lts-kmhv2/0376-UPSTREAM-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch new file mode 100644 index 0000000000..72d5f97116 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0376-UPSTREAM-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch @@ -0,0 +1,43 @@ +From 872ef7cb6e8323840b32a1d5db9356728075bcd0 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 9 May 2026 18:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable eMMC for OrangePi + RV2 + +The OrangePi RV2 board has one eMMC slot, so enable eMMC. +Tested using a 16 GiB AJTD4R eMMC module. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260509100000.3315109-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit f068b204555ad62d6a841a49feb4ea8c4f45b25c) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 3a829e3c9cbc..c95ca38e3d4a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -78,6 +78,16 @@ &combo_phy { + status = "okay"; + }; + ++&emmc { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ no-sd; ++ no-sdio; ++ non-removable; ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch deleted file mode 100644 index f37bec7b80..0000000000 --- a/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 6836defb3d09054866bd4165ee60f3bcd6135b07 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:03 +0800 -Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY - -The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with -some PHY parameters exported as another system controller along with it. - -As a few PHY parameters' default value isn't ready to work, add a driver -configuring them before letting the PHY run, in addition to -clock/reset/regulator management. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-6-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - drivers/phy/Makefile | 1 + - drivers/phy/thead/Kconfig | 12 ++ - drivers/phy/thead/Makefile | 2 + - drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ - 5 files changed, 213 insertions(+) - create mode 100644 drivers/phy/thead/Kconfig - create mode 100644 drivers/phy/thead/Makefile - create mode 100644 drivers/phy/thead/phy-th1520-usb.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 88ea9af445b1..75c4af62f92a 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -140,6 +140,7 @@ source "drivers/phy/st/Kconfig" - source "drivers/phy/starfive/Kconfig" - source "drivers/phy/sunplus/Kconfig" - source "drivers/phy/tegra/Kconfig" -+source "drivers/phy/thead/Kconfig" - source "drivers/phy/ti/Kconfig" - source "drivers/phy/intel/Kconfig" - source "drivers/phy/xilinx/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index 950dd4f14372..5dffb5fcef3d 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -42,5 +42,6 @@ obj-y += allwinner/ \ - starfive/ \ - sunplus/ \ - tegra/ \ -+ thead/ \ - ti/ \ - xilinx/ -diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig -new file mode 100644 -index 000000000000..14012db5973c ---- /dev/null -+++ b/drivers/phy/thead/Kconfig -@@ -0,0 +1,12 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config PHY_TH1520_USB -+ tristate "USB PHY driver for T-Head TH1520 SoC" -+ depends on ARCH_THEAD || COMPILE_TEST -+ depends on COMMON_CLK -+ depends on HAS_IOMEM -+ depends on OF -+ depends on RESET_CONTROLLER -+ select GENERIC_PHY -+ default ARCH_THEAD -+ help -+ Enable support for the USB PHY on the T-Head TH1520 SoC. -diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile -new file mode 100644 -index 000000000000..5b459bc7004b ---- /dev/null -+++ b/drivers/phy/thead/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_TH1520_USB) += phy-th1520-usb.o -diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1520-usb.c -new file mode 100644 -index 000000000000..c87bd779bbb7 ---- /dev/null -+++ b/drivers/phy/thead/phy-th1520-usb.c -@@ -0,0 +1,197 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) -+ * -+ * Authors: -+ * Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define USB_SYSCON_OFFSET 0xf000 -+ -+/* All the below registers are in the USB syscon region */ -+#define USB_CLK_GATE_STS 0x0 -+#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 -+#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 -+#define USB_GPIO 0xc -+#define USB_DEBUG_STS0 0x10 -+#define USB_DEBUG_STS1 0x14 -+#define USB_DEBUG_STS2 0x18 -+#define USBCTL_CLK_CTRL0 0x1c -+#define USBPHY_CLK_CTRL1 0x20 -+#define USBPHY_TEST_CTRL0 0x24 -+#define USBPHY_TEST_CTRL1 0x28 -+#define USBPHY_TEST_CTRL2 0x2c -+#define USBPHY_TEST_CTRL3 0x30 -+#define USB_SSP_EN 0x34 -+#define USB_HADDR_SEL 0x38 -+#define USB_SYS 0x3c -+#define USB_HOST_STATUS 0x40 -+#define USB_HOST_CTRL 0x44 -+#define USBPHY_HOST_CTRL 0x48 -+#define USBPHY_HOST_STATUS 0x4c -+#define USB_TEST_REG0 0x50 -+#define USB_TEST_REG1 0x54 -+#define USB_TEST_REG2 0x58 -+#define USB_TEST_REG3 0x5c -+ -+#define USB_SYS_COMMONONN BIT(0) -+ -+#define USB_SSP_EN_REF_SSP_EN BIT(0) -+ -+struct th1520_usb_phy { -+ struct platform_device *pdev; -+ struct phy *phy; -+ struct regmap *regmap; -+ struct clk *ref_clk; -+ struct reset_control *phy_reset; -+}; -+ -+static int th1520_usb_phy_init(struct phy *phy) -+{ -+ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = clk_prepare_enable(th1520_phy->ref_clk); -+ if (ret) -+ return ret; -+ -+ ret = reset_control_assert(th1520_phy->phy_reset); -+ if (ret) -+ goto err_disable_clk; -+ -+ /* -+ * Do some initial PHY setup: -+ * - Set COMMONONN to allow the PHY to automatically power down. -+ * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed -+ * PHY clock PLL. -+ */ -+ regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); -+ regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); -+ -+ ret = reset_control_deassert(th1520_phy->phy_reset); -+ if (ret) -+ goto err_disable_clk; -+ -+ udelay(10); -+ -+ return 0; -+ -+err_disable_clk: -+ clk_disable_unprepare(th1520_phy->ref_clk); -+ return ret; -+} -+ -+static int th1520_usb_phy_exit(struct phy *phy) -+{ -+ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = reset_control_assert(th1520_phy->phy_reset); -+ if (ret) -+ return ret; -+ -+ clk_disable_unprepare(th1520_phy->ref_clk); -+ -+ return 0; -+} -+ -+static const struct phy_ops th1520_usb_phy_ops = { -+ .init = th1520_usb_phy_init, -+ .exit = th1520_usb_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct regmap_config phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = USB_TEST_REG3, -+}; -+ -+static int th1520_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct th1520_usb_phy *th1520_phy; -+ struct reset_control *bus_reset; -+ void __iomem *base; -+ int ret; -+ -+ th1520_phy = devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); -+ if (!th1520_phy) -+ return -ENOMEM; -+ -+ th1520_phy->pdev = pdev; -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ th1520_phy->ref_clk = devm_clk_get(dev, "ref"); -+ if (IS_ERR(th1520_phy->ref_clk)) -+ return PTR_ERR(th1520_phy->ref_clk); -+ -+ /* De-assert the bus reset and leave it that way */ -+ bus_reset = devm_reset_control_get_exclusive_deasserted(dev, "bus"); -+ if (IS_ERR(bus_reset)) -+ return PTR_ERR(bus_reset); -+ -+ th1520_phy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); -+ if (IS_ERR(th1520_phy->phy_reset)) -+ return PTR_ERR(th1520_phy->phy_reset); -+ -+ /* -+ * Schematics of several boards (Lichee Module 4A/Milk-V Meles) -+ * describe this power rail as always-on. -+ */ -+ ret = devm_regulator_get_enable(dev, "avdd33-usb3"); -+ if (ret) -+ return ret; -+ -+ th1520_phy->regmap = devm_regmap_init_mmio_clk(dev, "bus", -+ base + USB_SYSCON_OFFSET, -+ &phy_regmap_config); -+ if (IS_ERR(th1520_phy->regmap)) -+ return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), -+ "Failed to init regmap\n"); -+ -+ th1520_phy->phy = devm_phy_create(dev, dev->of_node, &th1520_usb_phy_ops); -+ if (IS_ERR(th1520_phy->phy)) { -+ dev_err(dev, "failed to create PHY\n"); -+ return PTR_ERR(th1520_phy->phy); -+ } -+ -+ phy_set_drvdata(th1520_phy->phy, th1520_phy); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id th1520_usb_phy_of_table[] = { -+ { .compatible = "thead,th1520-usb-phy" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); -+ -+static struct platform_driver th1520_usb_phy_driver = { -+ .driver = { -+ .name = "th1520-usb-phy", -+ .of_match_table = th1520_usb_phy_of_table, -+ }, -+ .probe = th1520_usb_phy_probe, -+}; -+ -+module_platform_driver(th1520_usb_phy_driver); -+ -+MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0377-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux-lts-kmhv2/0377-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch new file mode 100644 index 0000000000..0a425df319 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0377-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch @@ -0,0 +1,60 @@ +From 19b475e9164d312914d231c056b3ef86feca6701 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:56 +0200 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add pinctrl + support for voltage switching + +Document pinctrl properties to support voltage-dependent pin +configuration switching for UHS-I SD card modes. + +Add optional pinctrl-names property with two states: +- "default": For 3.3V operation with standard drive strength +- "state_uhs": For 1.8V operation with optimized drive strength + +These pinctrl states allow the SDHCI driver to coordinate voltage +switching with pin configuration changes, ensuring proper signal +integrity during UHS-I mode transitions. + +Acked-by: Conor Dooley +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit 04a8ddc39e5cfebffb06f383350a6ee393ba89a6) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 9a055d963a7f..34d202af909f 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -44,6 +44,18 @@ properties: + - const: axi + - const: sdh + ++ pinctrl-names: ++ minItems: 1 ++ items: ++ - const: default ++ - const: uhs ++ ++ pinctrl-0: ++ description: Default pinctrl state for 3.3V operation ++ ++ pinctrl-1: ++ description: Optional pinctrl state for 1.8V UHS operation with "uhs" name ++ + required: + - compatible + - reg +@@ -62,4 +74,7 @@ examples: + interrupt-parent = <&plic>; + clocks = <&clk_apmu 10>, <&clk_apmu 13>; + clock-names = "core", "io"; ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&sdhci_default_cfg>; ++ pinctrl-1 = <&sdhci_uhs_cfg>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch deleted file mode 100644 index 01b5e27c73..0000000000 --- a/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 2be6de531146e3cb05e762c17c5d087a15b3ad2d Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:04 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB - -The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 -Dual Role Device controller in addition to a USB2+USB3 combo PHY based -on Synopsys USB3.0 FemtoPHY. - -Add device tree nodes for them. The USB controller is quite generic, new -and properly configured during silicon design, but the PHY is a little -quirky. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-7-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 4d1e71227339..f1746b5fcd40 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -351,6 +351,20 @@ uart0: serial@ffe7014000 { - status = "disabled"; - }; - -+ usb: usb@ffe7040000 { -+ compatible = "snps,dwc3"; -+ reg = <0xff 0xe7040000 0x0 0x10000>; -+ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_misc CLK_USB>, -+ <&clk_misc CLK_USB_CTL_REF>, -+ <&clk_misc CLK_USB_SUSPEND>; -+ clock-names = "bus_early", "ref", "suspend"; -+ resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>; -+ phys = <&usb_phy>; -+ phy-names = "usb3-phy"; -+ status = "disabled"; -+ }; -+ - gmac1: ethernet@ffe7060000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; -@@ -575,6 +589,19 @@ clk_misc: clock-controller@ffec02c100 { - #clock-cells = <1>; - }; - -+ usb_phy: phy@ffec030000 { -+ compatible = "thead,th1520-usb-phy"; -+ reg = <0xff 0xec030000 0x0 0x10000>; -+ clocks = <&clk_misc CLK_USB>, -+ <&clk_misc CLK_USB_PHY_REF>; -+ clock-names = "bus", "ref"; -+ resets = <&rst_misc TH1520_RESET_ID_USB3_APB>, -+ <&rst_misc TH1520_RESET_ID_USB3_PHY>; -+ reset-names = "bus", "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - rst_vp: reset-controller@ffecc30000 { - compatible = "thead,th1520-reset-vp"; - reg = <0xff 0xecc30000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0378-UPSTREAM-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux-lts-kmhv2/0378-UPSTREAM-mmc-sdhci-of-k1-enable-essential-clock-infr.patch new file mode 100644 index 0000000000..5abba2823e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0378-UPSTREAM-mmc-sdhci-of-k1-enable-essential-clock-infr.patch @@ -0,0 +1,66 @@ +From 512992b87de645b36c37feea9f28f4c99659e543 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:57 +0200 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: enable essential clock + infrastructure for SD operation + +Ensure SD card pins receive clock signals by enabling pad clock +generation and overriding automatic clock gating. Required for all SD +operation modes. + +The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD +and eMMC operation as both protocols use the same physical MMC interface +pins and require proper clock signal generation at the hardware level +for signal integrity and timing. + +Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and +SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only +controllers to handle removable card scenarios. + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit f87b273e4b6dfe57dcd63c24cbe3764d1f6954ae) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 455656f9842d..0dd06fc19b85 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -21,6 +21,13 @@ + #include "sdhci.h" + #include "sdhci-pltfm.h" + ++#define SPACEMIT_SDHC_OP_EXT_REG 0x108 ++#define SDHC_OVRRD_CLK_OEN BIT(11) ++#define SDHC_FORCE_CLK_ON BIT(12) ++ ++#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C ++#define SDHC_GEN_PAD_CLK_ON BIT(6) ++ + #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 + #define SDHC_MISC_INT_EN BIT(1) + #define SDHC_MISC_INT BIT(2) +@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + + if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) + spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); ++ ++ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) ++ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, ++ SPACEMIT_SDHC_OP_EXT_REG); + } + + static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch deleted file mode 100644 index bd9aea764d..0000000000 --- a/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b2708e5bb25843313bbb63f5c6417d756f0ce5e0 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:05 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs - -GPIO hogs are described in the gpio.txt binding as automatic default -GPIO configuration items. - -Allow them for GPIO ports in DesignWare APB GPIO controller nodes. - -Cc: Hoan Tran -Cc: Linus Walleij -Cc: Bartosz Golaszewski -Cc: Serge Semin -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-8-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -index ab2afc0e4153..79679a14a02f 100644 ---- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -+++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -@@ -95,6 +95,12 @@ patternProperties: - '#interrupt-cells': - const: 2 - -+ patternProperties: -+ "^.+-hog(-[0-9]+)?$": -+ type: object -+ required: -+ - gpio-hog -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0379-UPSTREAM-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux-lts-kmhv2/0379-UPSTREAM-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch new file mode 100644 index 0000000000..b4b1be4746 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0379-UPSTREAM-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch @@ -0,0 +1,145 @@ +From 736364c56c6d5f971133c00a40d564d6771ce992 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:58 +0200 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add regulator and pinctrl + voltage switching support + +Add voltage switching infrastructure for UHS-I modes by integrating both +regulator framework (for supply voltage control) and pinctrl state +switching (for pin drive strength optimization). + +- Add regulator supply parsing and voltage switching callback +- Add optional pinctrl state switching between "default" (3.3V) and + "state_uhs" (1.8V) configurations +- Enable coordinated voltage and pin configuration changes for UHS modes + +This provides complete voltage switching support while maintaining +backward compatibility when pinctrl states are not defined. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Acked-by: Adrian Hunter +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit 00a97fc57c09ff1cf71107753d9b5629caeb8c8a) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ + 1 file changed, 72 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 0dd06fc19b85..d9144537032a 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -71,6 +72,9 @@ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pinctrl_default; ++ struct pinctrl_state *pinctrl_uhs; + }; + + /* All helper functions will update clr/set while preserve rest bits */ +@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) + SPACEMIT_SDHC_PHY_CTRL_REG); + } + ++static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, ++ struct mmc_ios *ios) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ struct pinctrl_state *state; ++ int ret; ++ ++ ret = sdhci_start_signal_voltage_switch(mmc, ios); ++ if (ret) ++ return ret; ++ ++ if (!sdhst->pinctrl) ++ return 0; ++ ++ /* Select appropriate pinctrl state based on signal voltage */ ++ switch (ios->signal_voltage) { ++ case MMC_SIGNAL_VOLTAGE_330: ++ state = sdhst->pinctrl_default; ++ break; ++ case MMC_SIGNAL_VOLTAGE_180: ++ state = sdhst->pinctrl_uhs; ++ break; ++ default: ++ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); ++ return 0; ++ } ++ ++ ret = pinctrl_select_state(sdhst->pinctrl, state); ++ if (ret) { ++ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); ++ return 0; ++ } ++ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", ++ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); ++ ++ return 0; ++} ++ + static inline int spacemit_sdhci_get_clocks(struct device *dev, + struct sdhci_pltfm_host *pltfm_host) + { +@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) + return 0; + } + ++static inline void spacemit_sdhci_get_pins(struct device *dev, ++ struct sdhci_pltfm_host *pltfm_host) ++{ ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ ++ sdhst->pinctrl = devm_pinctrl_get(dev); ++ if (IS_ERR(sdhst->pinctrl)) { ++ sdhst->pinctrl = NULL; ++ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); ++ return; ++ } ++ ++ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); ++ if (IS_ERR(sdhst->pinctrl_default)) ++ sdhst->pinctrl_default = NULL; ++ ++ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); ++ if (IS_ERR(sdhst->pinctrl_uhs)) ++ sdhst->pinctrl_uhs = NULL; ++ ++ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", ++ sdhst->pinctrl_default, sdhst->pinctrl_uhs); ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -324,6 +392,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + + host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; + ++ spacemit_sdhci_get_pins(dev, pltfm_host); ++ ++ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; ++ + ret = spacemit_sdhci_get_clocks(dev, pltfm_host); + if (ret) + goto err_pltfm; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch deleted file mode 100644 index 00f4949ecd..0000000000 --- a/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch +++ /dev/null @@ -1,48 +0,0 @@ -From d114c66e2f27fb7d5c538f14399ab98ce4960f83 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:06 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports - property - -As a USB hub device, VL817 can surely be connected to external USB -connectors. The binding for such connectors connection is already -described in the generic usb-hub.yaml binding with ports subnode, but -it's not yet allowed in the VL817 binding. - -Switch the reference binding from usb-device.yaml to usb-hub.yaml (which -recursively references usb-device.yaml and contains definition for ports -subnode) and allow ports subnode in VL817 binding. - -Cc: Anand Moon -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-9-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -index c815010ba9c2..7387f4fae54d 100644 ---- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -+++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -@@ -10,7 +10,7 @@ maintainers: - - Anand Moon - - allOf: -- - $ref: usb-device.yaml# -+ - $ref: usb-hub.yaml# - - properties: - compatible: -@@ -34,6 +34,8 @@ properties: - description: - phandle to the peer hub on the controller. - -+ ports: true -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0380-UPSTREAM-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux-lts-kmhv2/0380-UPSTREAM-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch new file mode 100644 index 0000000000..0f282ac34c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0380-UPSTREAM-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch @@ -0,0 +1,242 @@ +From 3cb51db0e02a736385051491bd5cb3dca2a67ec3 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:59 +0200 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add comprehensive SDR tuning + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Implement software tuning algorithm to enable UHS-I SDR modes for SD +card operation and HS200 mode for eMMC. This adds both TX and RX delay +line tuning based on the SpacemiT K1 controller capabilities. + +Algorithm features: +- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) +- Conditional tuning: only for high-speed modes (≥100MHz) +- TX tuning: configure transmit delay line with optimal values + (dline_reg=0, delaycode=127) to ensure optimal signal output timing +- RX tuning: single-pass window detection algorithm testing full + delay range (0-255) to find optimal receive timing window +- Retry mechanism: multiple fallback delays within optimal window + for improved reliability + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit e9cb83c10071808aa7db4582e007a650aa6aa183) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ + 1 file changed, 172 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index d9144537032a..37b0911e7cf2 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -69,6 +69,28 @@ + #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) + #define SDHC_RX_BIAS_CTRL BIT(5) + ++#define SPACEMIT_SDHC_RX_CFG_REG 0x118 ++#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) ++#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) ++#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) ++ ++#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 ++#define SDHC_DLINE_PU BIT(0) ++#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) ++#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) ++ ++#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 ++#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) ++#define SDHC_RX_DLINE_GAIN BIT(8) ++#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) ++ ++#define SPACEMIT_RX_DLINE_REG 9 ++#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 ++#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF ++ ++#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 ++#define SPACEMIT_TX_TUNING_DELAYCODE 127 ++ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; +@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u + sdhci_writel(host, val, reg); + } + ++static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++} ++ ++static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) ++{ ++ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++} ++ ++static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, ++ SPACEMIT_SDHC_RX_CFG_REG); ++ ++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) ++ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); ++} ++ + static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + { + sdhci_reset(host, mask); +@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) + return clk_get_rate(pltfm_host->clk); + } + ++static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ int current_len = 0, current_start = 0; ++ int max_pass_len = 0, max_pass_start = 0; ++ struct mmc_host *mmc = host->mmc; ++ struct mmc_ios ios = mmc->ios; ++ u8 final_delay; ++ int ret = 0; ++ int i; ++ ++ /* ++ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and ++ * if clock frequency is greater than 100MHz in these modes. ++ */ ++ if (host->clock < 100 * 1000 * 1000 || ++ !(ios.timing == MMC_TIMING_MMC_HS200 || ++ ios.timing == MMC_TIMING_UHS_SDR50 || ++ ios.timing == MMC_TIMING_UHS_SDR104)) ++ return 0; ++ ++ if (mmc->caps2 & MMC_CAP2_NO_MMC) { ++ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); ++ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); ++ spacemit_sdhci_tx_tuning_prepare(host); ++ ++ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", ++ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); ++ } ++ ++ spacemit_sdhci_prepare_tuning(host); ++ ++ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { ++ spacemit_sdhci_set_rx_delay(host, i); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ ++ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", ++ i, ret == 0 ? "pass" : "fail"); ++ ++ if (ret == 0) { ++ /* Test passed - extend current window */ ++ if (current_len == 0) ++ current_start = i; ++ current_len++; ++ } else { ++ /* Test failed - check if current window is best so far */ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ current_len = 0; ++ } ++ } ++ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ ++ if (max_pass_len < 3) { ++ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); ++ return -EIO; ++ } ++ ++ final_delay = max_pass_start + max_pass_len / 2; ++ spacemit_sdhci_set_rx_delay(host, final_delay); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (ret) { ++ u8 retry_delays[] = { ++ max_pass_start + max_pass_len / 4, ++ max_pass_start + (3 * max_pass_len) / 4, ++ max_pass_start, ++ max_pass_start + max_pass_len - 1 ++ }; ++ int retry_count = ARRAY_SIZE(retry_delays); ++ ++ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", ++ final_delay); ++ ++ for (i = 0; i < retry_count; i++) { ++ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && ++ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { ++ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (!ret) { ++ final_delay = retry_delays[i]; ++ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", ++ final_delay); ++ break; ++ } ++ } ++ } ++ ++ if (ret) { ++ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); ++ return -EIO; ++ } ++ } ++ ++ dev_dbg(mmc_dev(host->mmc), ++ "Tuning successful: window %d-%d, using delay %d\n", ++ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); ++ ++ return 0; ++} ++ + static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) + { + struct sdhci_host *host = mmc_priv(mmc); +@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { + .set_bus_width = sdhci_set_bus_width, + .set_clock = spacemit_sdhci_set_clock, + .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, ++ .platform_execute_tuning = spacemit_sdhci_execute_tuning, + }; + + static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch deleted file mode 100644 index 16cdfd9cbf..0000000000 --- a/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch +++ /dev/null @@ -1,66 +0,0 @@ -From f92fde63364be52d61f1457466f5b1697b0e9b09 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:07 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes - -Although "D" and "H" are earlier in the alphabet than "P", the DPU and -HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. - -Sort the nodes in this device tree. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-10-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 7cb7d28683bc..4198dbf953f0 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -96,6 +96,20 @@ fan: pwm-fan { - - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &padctrl0_apsys { - fan_pins: fan-0 { - pwm1-pins { -@@ -132,20 +146,6 @@ rx-pins { - }; - }; - --&dpu { -- status = "okay"; --}; -- --&hdmi { -- status = "okay"; --}; -- --&hdmi_out_port { -- hdmi_out_con: endpoint { -- remote-endpoint = <&hdmi_con_in>; -- }; --}; -- - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0381-UPSTREAM-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux-lts-kmhv2/0381-UPSTREAM-riscv-dts-spacemit-k1-add-SD-card-controlle.patch new file mode 100644 index 0000000000..cae679141d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0381-UPSTREAM-riscv-dts-spacemit-k1-add-SD-card-controlle.patch @@ -0,0 +1,107 @@ +From 50411cf3e9ec53259b4850193c45b0cf08da771d Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:48:59 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1: add SD card + controller and pinctrl support + +Add SD card controller infrastructure for SpacemiT K1 SoC with complete +pinctrl support for both standard and UHS modes. + +- Add sdhci0 controller definition with clocks, resets and interrupts +- Add mmc1_cfg pinctrl for 3.3V standard SD operation +- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation +- Configure appropriate drive strength and power-source properties + +This provides complete SD card infrastructure that K1-based boards can +enable. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Reviewed-by: Troy Mitchell +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 2d77e577109967ef65f269c1fc1d6a659d4260fb) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ + 2 files changed, 53 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index 34d88334e95e..4e9a62d0e85b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -590,4 +590,44 @@ ssp3-0-frm-pins { + power-source = <3300>; + }; + }; ++ ++ mmc1_cfg: mmc1-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ mmc1_uhs_cfg: mmc1-uhs-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index cba160c5edc5..08a0f28d011f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1315,6 +1315,19 @@ usb_dwc3: usb@c0a00000 { + status = "disabled"; + }; + ++ sdhci0: mmc@d4280000 { ++ compatible = "spacemit,k1-sdhci"; ++ reg = <0x0 0xd4280000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH0>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH0>; ++ reset-names = "axi", "sdh"; ++ interrupts = <99>; ++ status = "disabled"; ++ }; ++ + emmc: mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch b/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch deleted file mode 100644 index e70fcfd352..0000000000 --- a/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 235225ebc673fe3cf62d79eb1936fb0ef9b3aa52 Mon Sep 17 00:00:00 2001 -From: Thomas Bonnefille -Date: Thu, 7 May 2026 16:17:08 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes - -Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. - -Signed-off-by: Thomas Bonnefille -Reviewed-by: Drew Fustini -[Icenowy: rebase on top of v7.1-rc2] -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-11-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 60 +++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f1746b5fcd40..e44010810c07 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -460,6 +460,36 @@ uart3: serial@ffe7f04000 { - status = "disabled"; - }; - -+ i2c0: i2c@ffe7f20000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f20000 0x0 0x4000>; -+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@ffe7f24000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f24000 0x0 0x4000>; -+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@ffe7f28000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f28000 0x0 0x4000>; -+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; -@@ -558,6 +588,16 @@ padctrl0_apsys: pinctrl@ffec007000 { - thead,pad-group = <3>; - }; - -+ i2c2: i2c@ffec00c000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xec00c000 0x0 0x4000>; -+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - uart2: serial@ffec010000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; -@@ -569,6 +609,16 @@ uart2: serial@ffec010000 { - status = "disabled"; - }; - -+ i2c3: i2c@ffec014000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xec014000 0x0 0x4000>; -+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C3>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - pwm: pwm@ffec01c000 { - compatible = "thead,th1520-pwm"; - reg = <0xff 0xec01c000 0x0 0x4000>; -@@ -794,6 +844,16 @@ uart5: serial@fff7f0c000 { - status = "disabled"; - }; - -+ i2c5: i2c@fff7f2c000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xf7f2c000 0x0 0x4000>; -+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C5>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0382-UPSTREAM-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux-lts-kmhv2/0382-UPSTREAM-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch new file mode 100644 index 0000000000..8538a0ef57 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0382-UPSTREAM-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch @@ -0,0 +1,79 @@ +From 0822961c114acb5124ccf9f66e9d9ea96114be1d Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:00 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-orangepi-rv2: add SD + card support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW logic +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Michael Opdenacker +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 2585c60ce2f977b13f14a67d1e3ed9c73fd7f381) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- + 1 file changed, 21 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index c95ca38e3d4a..bd40bc9011e2 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -17,6 +17,8 @@ aliases { + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -202,7 +204,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -319,3 +321,21 @@ hub_3_0: hub@2 { + vdd-supply = <&vcc_5v0>; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch b/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch deleted file mode 100644 index 6905dfac60..0000000000 --- a/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch +++ /dev/null @@ -1,166 +0,0 @@ -From e7621614a1d93b84b3994cc4e147e2f5f24e8b8c Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Thu, 7 May 2026 16:17:09 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO - expansions - -Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the -I2C0/1/3 busses. - -Add device tree nodes for them. - -Signed-off-by: Emil Renner Berthing -[Icenowy: added commit description] -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-12-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 111 ++++++++++++++++++ - 1 file changed, 111 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 4198dbf953f0..354f3893aa8c 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -16,6 +16,9 @@ aliases { - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &aogpio; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; -@@ -110,6 +113,76 @@ hdmi_out_con: endpoint { - }; - }; - -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp1: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "cam0_dvdd12", -+ "cam0_avdd28", -+ "cam0_dovdd18"; -+ }; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp2: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "", -+ "cam0_reset", -+ "cam1_reset", -+ "cam2_reset", -+ "wl_host_wake", -+ "bt_resetn", -+ "", -+ "bt_host_wake"; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp3: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "tp0_rst", -+ "", -+ "", -+ "vcc5v_usb", -+ "vdd28_tp0", -+ "vdd33_lcd0", -+ "vdd18_lcd0", -+ "lcd0_reset"; -+ }; -+}; -+ - &padctrl0_apsys { - fan_pins: fan-0 { - pwm1-pins { -@@ -123,6 +196,18 @@ pwm1-pins { - }; - }; - -+ i2c3_pins: i2c3-0 { -+ i2c-pins { -+ pins = "I2C3_SCL", "I2C3_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ - uart0_pins: uart0-0 { - tx-pins { - pins = "UART0_TXD"; -@@ -146,6 +231,32 @@ rx-pins { - }; - }; - -+&padctrl1_apsys { -+ i2c0_pins: i2c0-0 { -+ i2c-pins { -+ pins = "I2C0_SCL", "I2C0_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-0 { -+ i2c-pins { -+ pins = "I2C1_SCL", "I2C1_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0383-UPSTREAM-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux-lts-kmhv2/0383-UPSTREAM-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch new file mode 100644 index 0000000000..4eed21973c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0383-UPSTREAM-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch @@ -0,0 +1,90 @@ +From 1ce95de9f1cfb7d46a05fb2252438dd0c5cbab2c Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:01 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-bananapi-f3: add SD + card support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up + support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Suggested-by: Anand Moon +Tested-by: Anand Moon +Tested-by: Margherita Milani +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit c76e2f058cbcab84e4a703f26857a58bdf6a0042) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- + 1 file changed, 22 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index e20daa50a152..72f77e9edd63 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -17,6 +17,8 @@ aliases { + spi3 = &spi3; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -221,7 +223,7 @@ buck3_1v8: buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -242,7 +244,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -374,3 +376,21 @@ hub_3_0: hub@2 { + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch deleted file mode 100644 index f1e49e1290..0000000000 --- a/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch +++ /dev/null @@ -1,306 +0,0 @@ -From 0b1e399727d5ebc0f998864161be37205403f479 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:10 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee - Pi 4A - -The Lichee Pi 4A board features an onboard VIA VL817 hub connected to -the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as -downstream. - -Enable SoC USB3 and the hub on Lichee Pi 4A. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-13-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 231 ++++++++++++++++++ - 2 files changed, 246 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -index 8e76b63e0100..bfda5a6b56b8 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -@@ -20,6 +20,16 @@ memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - }; -+ -+ /* TODO: Switch to AON regulator when it's available. */ -+ avdd33_usb3: regulator-avdd33-usb3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AVDD33_USB3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ /* Marked as always on on the schematics */ -+ regulator-always-on; -+ }; - }; - - &osc { -@@ -202,3 +212,8 @@ &sdio0 { - max-frequency = <198000000>; - status = "okay"; - }; -+ -+&usb_phy { -+ avdd33-usb3-supply = <&avdd33_usb3>; -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 354f3893aa8c..de38f1f457e6 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -4,6 +4,7 @@ - */ - - #include "th1520-lichee-module-4a.dtsi" -+#include - - / { - model = "Sipeed Lichee Pi 4A"; -@@ -97,6 +98,141 @@ fan: pwm-fan { - cooling-levels = <0 66 196 255>; - }; - -+ hub_5v: regulator-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "HUB_5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&ioexp3 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ vcc5v_usb: regulator-vcc5v-usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC5V_USB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ /* -+ * Workaround for Linux currently being not able to power on -+ * Vbus for USB Type-A connectors. -+ */ -+ regulator-always-on; -+ }; -+ -+ connector-usb-a-1 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_1_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port1_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_1_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port1_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-2 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_2_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port2_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_2_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port2_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-3 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_3_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port3_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_3_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port3_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-4 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_4_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port4_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_4_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port4_ep>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&aogpio { -+ /* Route USB2 to the onboard hub for normal operation */ -+ sel-usb-hub-hog { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; - }; - - &dpu { -@@ -262,3 +398,98 @@ &uart0 { - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; -+ -+&usb { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_hs: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <1>; -+ peer-hub = <&hub_ss>; -+ vdd-supply = <&hub_5v>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ -+ hub_hs_port1_ep: endpoint { -+ remote-endpoint = <&usb_a_1_hs_ep>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ hub_hs_port2_ep: endpoint { -+ remote-endpoint = <&usb_a_2_hs_ep>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ -+ hub_hs_port3_ep: endpoint { -+ remote-endpoint = <&usb_a_3_hs_ep>; -+ }; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ -+ hub_hs_port4_ep: endpoint { -+ remote-endpoint = <&usb_a_4_hs_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ hub_ss: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <2>; -+ peer-hub = <&hub_hs>; -+ vdd-supply = <&hub_5v>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ -+ hub_ss_port1_ep: endpoint { -+ remote-endpoint = <&usb_a_1_ss_ep>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ hub_ss_port2_ep: endpoint { -+ remote-endpoint = <&usb_a_2_ss_ep>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ -+ hub_ss_port3_ep: endpoint { -+ remote-endpoint = <&usb_a_3_ss_ep>; -+ }; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ -+ hub_ss_port4_ep: endpoint { -+ remote-endpoint = <&usb_a_4_ss_ep>; -+ }; -+ }; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0384-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux-lts-kmhv2/0384-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch new file mode 100644 index 0000000000..ebd66256d7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0384-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch @@ -0,0 +1,79 @@ +From 465fb1c6ace1b648650a742ed279f82514c2c7b9 Mon Sep 17 00:00:00 2001 +From: Trevor Gamblin +Date: Wed, 20 May 2026 15:06:23 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: add SD + card support with UHS modes + +Update the Muse Pi Pro devicetree with SD card support to match what +was done for the OrangePi RV2 in [1]. More precisely: + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with internal pull-up support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +[1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# + +Tested-by: Andre Heider +Signed-off-by: Trevor Gamblin +Signed-off-by: Iker Pedrosa +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# +Link: https://patch.msgid.link/20260520130624.1763487-1-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 85e4c5733cd7efa39f10d7200095c016ce4a2815) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 22 ++++++++++++++++++- + 1 file changed, 21 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 4aef287353ca..0d809e4ad3b1 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -19,6 +19,8 @@ aliases { + serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -218,7 +220,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -384,3 +386,21 @@ hub_3_0: hub@2 { + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch deleted file mode 100644 index 9a32cb3ce3..0000000000 --- a/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 52e6648f05a98b5daa57d14ffbc7a8f17e0a2e70 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:08 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add PMIC - and power infrastructure - -Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators -for the board's power infrastructure and voltage regulation support. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-2-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 144 ++++++++++++++++++ - 1 file changed, 144 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 29e333b670cf..88c35ad1ef2a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -17,6 +17,7 @@ / { - aliases { - ethernet0 = ð0; - serial0 = &uart0; -+ i2c8 = &i2c8; - }; - - chosen { -@@ -33,6 +34,25 @@ led1 { - default-state = "on"; - }; - }; -+ -+ reg_usb_vbus: regulator-usb-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "USBVBUS"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_vcc_4v0: regulator-vcc-40v { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC4V0"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; - }; - - &emmc { -@@ -72,6 +92,130 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-0 = <&i2c8_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <®_vcc_4v0>; -+ vin2-supply = <®_vcc_4v0>; -+ vin3-supply = <®_vcc_4v0>; -+ vin4-supply = <®_vcc_4v0>; -+ vin5-supply = <®_vcc_4v0>; -+ vin6-supply = <®_vcc_4v0>; -+ aldoin-supply = <®_vcc_4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0385-UPSTREAM-riscv-dts-thead-Add-TH1520-I2C1-controller.patch b/SPECS/linux-lts-kmhv2/0385-UPSTREAM-riscv-dts-thead-Add-TH1520-I2C1-controller.patch new file mode 100644 index 0000000000..603c6fe38b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0385-UPSTREAM-riscv-dts-thead-Add-TH1520-I2C1-controller.patch @@ -0,0 +1,44 @@ +From 53070d9fa8472939cc7affc019fbd0a753bd55fe Mon Sep 17 00:00:00 2001 +From: MoeLeak +Date: Fri, 8 May 2026 19:44:13 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add TH1520 I2C1 controller + +Describe the TH1520 I2C1 controller so boards can enable devices attached +to that bus. + +The controller is disabled by default because pinmuxing and connected +peripherals are board-specific. + +Signed-off-by: MoeLeak +Signed-off-by: Drew Fustini +(cherry picked from commit 2f60e351633044dee88b63fb1600e284d2476e9c) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 5e91dc1d2b9b..94932c51b7e3 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -411,6 +411,17 @@ uart3: serial@ffe7f04000 { + status = "disabled"; + }; + ++ i2c1: i2c@ffe7f24000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f24000 0x0 0x4000>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ref", "pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch b/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch deleted file mode 100644 index 27c61ac393..0000000000 --- a/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 766c66afb264021498a9385a2332b05c2ab32653 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:09 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add 24c04 - eeprom - -Enable i2c2 and add the connected 24c04 EEPROM. - -It contains an ONIE TLV table: -=> tlv_eeprom -TLV: 0 -[ 12.162] TlvInfo Header: -[ 12.162] Id String: TlvInfo -[ 12.165] Version: 1 -[ 12.168] Total Length: 58 -[ 12.171] TLV Name Code Len Value -[ 12.175] -------------------- ---- --- ----- -[ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro -[ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX -[ 12.189] Unknown 0x41 1 0x02 -[ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX -[ 12.199] MAC Addresses 0x2A 2 2 -[ 12.203] CRC-32 0xFE 4 0x395ECD34 -[ 12.207] Checksum is valid. - -(With 0x41 as TLV_CODE_DDR_CSNUM) - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-3-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- - 1 file changed, 34 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 88c35ad1ef2a..79415d760f16 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -17,6 +17,7 @@ / { - aliases { - ethernet0 = ð0; - serial0 = &uart0; -+ i2c2 = &i2c2; - i2c8 = &i2c8; - }; - -@@ -92,6 +93,38 @@ &pdma { - status = "okay"; - }; - -+&i2c2 { -+ pinctrl-0 = <&i2c2_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ -+ pagesize = <8>; -+ read-only; -+ size = <256>; -+ -+ nvmem-layout { -+ compatible = "onie,tlv-layout"; -+ -+ product-name { -+ }; -+ -+ serial-number { -+ }; -+ -+ mac-address { -+ #nvmem-cell-cells = <1>; -+ }; -+ -+ num-macs { -+ }; -+ }; -+ }; -+}; -+ - &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; -@@ -126,7 +159,7 @@ buck2 { - regulator-always-on; - }; - -- buck3 { -+ buck3_1v8: buck3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <5000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0386-UPSTREAM-riscv-dts-thead-Enable-WiFi-on-Lichee-Pi-4A.patch b/SPECS/linux-lts-kmhv2/0386-UPSTREAM-riscv-dts-thead-Enable-WiFi-on-Lichee-Pi-4A.patch new file mode 100644 index 0000000000..38b2170b73 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0386-UPSTREAM-riscv-dts-thead-Enable-WiFi-on-Lichee-Pi-4A.patch @@ -0,0 +1,103 @@ +From 5961ecdee2d1f4769af808a73715baaafdd5d854 Mon Sep 17 00:00:00 2001 +From: MoeLeak +Date: Fri, 8 May 2026 19:44:14 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Enable WiFi on Lichee Pi 4A + +The Lichee Pi 4A has an RTL8723DS WiFi module connected to the TH1520 +SDIO1 controller. The module reset line is driven through a PCA9557 GPIO +expander on the I2C1 bus. + +Enable I2C1 for the GPIO expander and configure SDIO1 as a non-removable +4-bit SDIO bus using an mmc-pwrseq-simple reset sequence so the WiFi +device can be powered and enumerated. + +Signed-off-by: MoeLeak +Signed-off-by: Drew Fustini +(cherry picked from commit a20241c08385c875c4d0deb6c8ffc15f13f5b388) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 47 +++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 7cb7d28683bc..af6f25ebbf60 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -4,6 +4,7 @@ + */ + + #include "th1520-lichee-module-4a.dtsi" ++#include + + / { + model = "Sipeed Lichee Pi 4A"; +@@ -40,6 +41,12 @@ hdmi_con_in: endpoint { + }; + }; + ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&ioexp2 4 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <200>; ++ }; ++ + thermal-zones { + cpu-thermal { + polling-delay = <1000>; +@@ -96,6 +103,20 @@ fan: pwm-fan { + + }; + ++&padctrl1_apsys { ++ i2c1_pins: i2c1-0 { ++ i2c-pins { ++ pins = "I2C1_SCL", "I2C1_SDA"; ++ function = "i2c"; ++ bias-pull-up = <2100>; ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -132,6 +153,32 @@ rx-pins { + }; + }; + ++&i2c1 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ ++ ioexp2: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++}; ++ ++&sdio1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus-width = <4>; ++ max-frequency = <198000000>; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ non-removable; ++ status = "okay"; ++}; ++ + &dpu { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch deleted file mode 100644 index bb1a850bdd..0000000000 --- a/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch +++ /dev/null @@ -1,82 +0,0 @@ -From c117a7fcd7c10d4f8235ca033fe3b09674838cc2 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:10 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - QSPI and add SPI NOR - -Add the QSPI controller node and describe the attached SPI NOR flash -(Winbond W25Q64FWSSAQ). - -Add a corresponding vendor flash partition layout. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-4-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 43 ++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 79415d760f16..7ebace0e46ed 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -166,7 +166,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4_3v3: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -249,6 +249,47 @@ dldo7 { - }; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x10000>; -+ }; -+ private@10000 { -+ reg = <0x10000 0x10000>; -+ }; -+ fsbl@20000 { -+ reg = <0x20000 0x40000>; -+ }; -+ env@60000 { -+ reg = <0x60000 0x10000>; -+ }; -+ opensbi@70000 { -+ reg = <0x70000 0x30000>; -+ }; -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0387-UPSTREAM-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux-lts-kmhv2/0387-UPSTREAM-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch new file mode 100644 index 0000000000..ebb958dcff --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0387-UPSTREAM-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch @@ -0,0 +1,97 @@ +From 9ac45a8228e9832ca354e2ab4a6dbdc805d6f151 Mon Sep 17 00:00:00 2001 +From: Thomas Gerner +Date: Thu, 14 May 2026 20:32:01 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Enable wifi on the + BeagleV-Ahead + +The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology +Inc. connected to SDIO1. The chip is compatible to the broadcom wireless +driver. + +The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and +Bluetooth 5.4 module. Bluetooth is not enabled by this patch. + +Signed-off-by: Thomas Gerner +Signed-off-by: Drew Fustini +(cherry picked from commit 3a5791956edbfa84d7256224167941931cbc46e7) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +index 91f3f9b987bc..e16484a47653 100644 +--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts ++++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +@@ -86,6 +86,11 @@ hdmi_con_in: endpoint { + }; + }; + }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ ++ }; + }; + + &osc { +@@ -239,6 +244,28 @@ rx-pins { + slew-rate = <0>; + }; + }; ++ ++ wifi_pins: wifi-0 { ++ host-wake-pins { ++ pins = "GPIO2_25"; ++ function = "gpio"; ++ bias-disable; ++ drive-strength = <1>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ reg-on-pins { ++ pins = "GPIO2_31"; ++ function = "gpio"; ++ bias-disable; ++ drive-strength = <3>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; + }; + + &sdio0 { +@@ -247,6 +274,27 @@ &sdio0 { + status = "okay"; + }; + ++&sdio1 { ++ bus-width = <4>; ++ max-frequency = <198000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ non-removable; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ status = "okay"; ++ ++ wifi@1 { ++ compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <25 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ + &dpu { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch deleted file mode 100644 index e2dbb68dfc..0000000000 --- a/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch +++ /dev/null @@ -1,97 +0,0 @@ -From a94156daa45213f4dfc1d6f6cc6a3f25b4e635c1 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:11 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - USB 3 ports - -Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) -and usbphy2 (USB 2 PHY) on the MusePi Pro board. - -The board uses a VLI VL817 hub, providing four ports. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-5-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 54 +++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 7ebace0e46ed..9c90c2817ecb 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -54,6 +54,28 @@ reg_vcc_4v0: regulator-vcc-40v { - regulator-always-on; - vin-supply = <®_usb_vbus>; - }; -+ -+ reg_5v_vbus: regulator-5v-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "5V_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ -+ enable-active-high; -+ }; -+ -+ reg_vcc5v_hub: regulator-vcc5v-hub { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC5V0_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ -+ enable-active-high; -+ }; - }; - - &emmc { -@@ -66,6 +88,10 @@ &emmc { - status = "okay"; - }; - -+&combo_phy { -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; -@@ -295,3 +321,31 @@ &uart0 { - pinctrl-names = "default"; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vbus-supply = <®_5v_vbus>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <®_vcc5v_hub>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <®_vcc5v_hub>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0388-UPSTREAM-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux-lts-kmhv2/0388-UPSTREAM-riscv-module-Use-generic-cmp_int-instead-of.patch new file mode 100644 index 0000000000..454b1a615f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0388-UPSTREAM-riscv-module-Use-generic-cmp_int-instead-of.patch @@ -0,0 +1,49 @@ +From baa25175c1992324a927b6aaecffa5bc1aa01a37 Mon Sep 17 00:00:00 2001 +From: Florian Schmaus +Date: Sat, 6 Jun 2026 20:17:53 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: module: Use generic cmp_int() instead + of custom cmp_3way() + +The module-sections.c file defines a custom cmp_3way() macro to perform +3-way comparisons during relocation sorting. + +Instead of maintaining our own implementation, use the generic +cmp_int() macro provided by the already included . This +removes redundant code and relies on standard kernel interfaces. + +Signed-off-by: Florian Schmaus +Link: https://patch.msgid.link/20260512063231.708256-1-florian.schmaus@codasip.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 3e17a4b443bbaecc723a2d51faeaa1a0097e43e9) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/module-sections.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module-sections.c +index 1675cbad8619..33750a51f157 100644 +--- a/arch/riscv/kernel/module-sections.c ++++ b/arch/riscv/kernel/module-sections.c +@@ -56,17 +56,15 @@ unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) + return (unsigned long)&plt[i]; + } + +-#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) +- + static int cmp_rela(const void *a, const void *b) + { + const Elf_Rela *x = a, *y = b; + int i; + + /* sort by type, symbol index and addend */ +- i = cmp_3way(x->r_info, y->r_info); ++ i = cmp_int(x->r_info, y->r_info); + if (i == 0) +- i = cmp_3way(x->r_addend, y->r_addend); ++ i = cmp_int(x->r_addend, y->r_addend); + return i; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch deleted file mode 100644 index 23832d06b8..0000000000 --- a/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 349e55f2df85d45315a64261930482121af299e5 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:12 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - PCIe ports - -Enable the two PCIe controller along with and their associated PHYs. They -are routed to the M.2 M-key connector and to the PCIe slot. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-6-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ - 1 file changed, 50 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 9c90c2817ecb..2d3e30f0bd80 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -36,6 +36,24 @@ led1 { - }; - }; - -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "PCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; -+ -+ mpcie_vcc_3v3: regulator-mpcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "MPCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; -+ - reg_usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "USBVBUS"; -@@ -275,6 +293,38 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&mpcie_vcc_3v3>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&mpcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0389-UPSTREAM-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux-lts-kmhv2/0389-UPSTREAM-riscv-propagate-insert_resource-result-from.patch new file mode 100644 index 0000000000..468b5bf2f3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0389-UPSTREAM-riscv-propagate-insert_resource-result-from.patch @@ -0,0 +1,50 @@ +From a5535ff7504eb1609517707e87e8036a64835533 Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Sat, 6 Jun 2026 20:17:52 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: propagate insert_resource result from + add_resource + +Currently, add_resource() returns 1 on success, even though its callers +only check for negative values. Instead, propagate the insert_resource() +result from add_resource() to align with standard kernel return-value +conventions (0 on success, negative errno on failure). + +Use %pR to print the full resource range while at it. + +Signed-off-by: Thorsten Blum +Link: https://patch.msgid.link/20260512172034.328405-4-thorsten.blum@linux.dev +Signed-off-by: Paul Walmsley +(cherry picked from commit 13fe217f64a7ee71aa58d871c6021a721a5a0c6f) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/setup.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c +index b5bc5fc65cea..13b27a078912 100644 +--- a/arch/riscv/kernel/setup.c ++++ b/arch/riscv/kernel/setup.c +@@ -75,16 +75,13 @@ static struct resource *standard_resources; + static int __init add_resource(struct resource *parent, + struct resource *res) + { +- int ret = 0; ++ int ret; + + ret = insert_resource(parent, res); +- if (ret < 0) { +- pr_err("Failed to add a %s resource at %llx\n", +- res->name, (unsigned long long) res->start); +- return ret; +- } ++ if (ret < 0) ++ pr_err("Failed to add resource %s %pR\n", res->name, res); + +- return 1; ++ return ret; + } + + static int __init add_kernel_resources(void) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch deleted file mode 100644 index 2a721e03c5..0000000000 --- a/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9a43c78660975e06c30cbaf943e981dd50feee99 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:13 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set - default console baud rate - -Allow serial output with the same uboot/opensbi settings so the -console works without providing a cmdline. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-7-a.heider@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 2d3e30f0bd80..c8bf776511c9 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -22,7 +22,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - leds { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0390-UPSTREAM-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux-lts-kmhv2/0390-UPSTREAM-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch new file mode 100644 index 0000000000..82871b55b8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0390-UPSTREAM-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch @@ -0,0 +1,78 @@ +From 61eba02b59eba26f274780eb63e84e3b66145380 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 16 May 2026 16:00:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI for OrangePi + RV2 + +Enable the QSPI controller and the XM25QU128C SPI NOR flash on the +OrangePi RV2 board. Add a flash partition layout from vendor UBoot. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260516080030.1736836-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit e2518e8cb1dde64af2d1bb246639bb7ef7523f7a) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index bd40bc9011e2..7c49bce427f3 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -290,6 +290,51 @@ &pcie2 { + status = "okay"; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&buck3_1v8>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x00000 0x010000>; ++ }; ++ ++ private@10000 { ++ reg = <0x10000 0x010000>; ++ }; ++ ++ fsbl@20000 { ++ reg = <0x20000 0x040000>; ++ }; ++ ++ env@60000 { ++ reg = <0x60000 0x010000>; ++ }; ++ ++ opensbi@70000 { ++ reg = <0x70000 0x030000>; ++ }; ++ ++ uboot@a0000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch deleted file mode 100644 index e480697ecf..0000000000 --- a/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch +++ /dev/null @@ -1,851 +0,0 @@ -From 19e0459a70fb9e1c62f2eb097e72e73136997ccd Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 21 May 2026 00:24:41 +0000 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add pwm support - -Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents -the pinctrl info which would easily help to enable them in future. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ - 2 files changed, 810 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 23899d3f308a..252c64af76fe 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -56,6 +56,596 @@ i2c8-pins { - }; - }; - -+ /omit-if-no-ref/ -+ pwm0_0_cfg: pwm0-0-cfg { -+ pwm0-0-pins { -+ pinmux = ; /* pwm0 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm0_1_cfg: pwm0-1-cfg { -+ pwm0-1-pins { -+ pinmux = ; /* pwm0 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_0_cfg: pwm1-0-cfg { -+ pwm1-0-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_1_cfg: pwm1-1-cfg { -+ pwm1-1-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_2_cfg: pwm1-2-cfg { -+ pwm1-2-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_0_cfg: pwm2-0-cfg { -+ pwm2-0-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_1_cfg: pwm2-1-cfg { -+ pwm2-1-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_2_cfg: pwm2-2-cfg { -+ pwm2-2-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_3_cfg: pwm2-3-cfg { -+ pwm2-3-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_0_cfg: pwm3-0-cfg { -+ pwm3-0-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_1_cfg: pwm3-1-cfg { -+ pwm3-1-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_2_cfg: pwm3-2-cfg { -+ pwm3-2-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_3_cfg: pwm3-3-cfg { -+ pwm3-3-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_0_cfg: pwm4-0-cfg { -+ pwm4-0-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_1_cfg: pwm4-1-cfg { -+ pwm4-1-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_2_cfg: pwm4-2-cfg { -+ pwm4-2-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_0_cfg: pwm5-0-cfg { -+ pwm5-0-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_1_cfg: pwm5-1-cfg { -+ pwm5-1-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_2_cfg: pwm5-2-cfg { -+ pwm5-2-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_0_cfg: pwm6-0-cfg { -+ pwm6-0-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_1_cfg: pwm6-1-cfg { -+ pwm6-1-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_2_cfg: pwm6-2-cfg { -+ pwm6-2-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_0_cfg: pwm7-0-cfg { -+ pwm7-0-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_1_cfg: pwm7-1-cfg { -+ pwm7-1-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_2_cfg: pwm7-2-cfg { -+ pwm7-2-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_0_cfg: pwm8-0-cfg { -+ pwm8-0-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_1_cfg: pwm8-1-cfg { -+ pwm8-1-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_2_cfg: pwm8-2-cfg { -+ pwm8-2-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_0_cfg: pwm9-0-cfg { -+ pwm9-0-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_1_cfg: pwm9-1-cfg { -+ pwm9-1-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_2_cfg: pwm9-2-cfg { -+ pwm9-2-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_0_cfg: pwm10-0-cfg { -+ pwm10-0-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_1_cfg: pwm10-1-cfg { -+ pwm10-1-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_2_cfg: pwm10-2-cfg { -+ pwm10-2-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11_0_cfg: pwm11-0-cfg { -+ pwm11-0-pins { -+ pinmux = ; /* pwm11 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11_1_cfg: pwm11-1-cfg { -+ pwm11-1-pins { -+ pinmux = ; /* pwm11 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12_0_cfg: pwm12-0-cfg { -+ pwm12-0-pins { -+ pinmux = ; /* pwm12 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12_1_cfg: pwm12-1-cfg { -+ pwm12-1-pins { -+ pinmux = ; /* pwm12 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_0_cfg: pwm13-0-cfg { -+ pwm13-0-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_1_cfg: pwm13-1-cfg { -+ pwm13-1-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_2_cfg: pwm13-2-cfg { -+ pwm13-2-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_0_cfg: pwm14-0-cfg { -+ pwm14-0-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_1_cfg: pwm14-1-cfg { -+ pwm14-1-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_2_cfg: pwm14-2-cfg { -+ pwm14-2-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_0_cfg: pwm15-0-cfg { -+ pwm15-0-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_1_cfg: pwm15-1-cfg { -+ pwm15-1-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_2_cfg: pwm15-2-cfg { -+ pwm15-2-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_0_cfg: pwm16-0-cfg { -+ pwm16-0-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_1_cfg: pwm16-1-cfg { -+ pwm16-1-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_2_cfg: pwm16-2-cfg { -+ pwm16-2-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_0_cfg: pwm17-0-cfg { -+ pwm17-0-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_1_cfg: pwm17-1-cfg { -+ pwm17-1-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_2_cfg: pwm17-2-cfg { -+ pwm17-2-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_0_cfg: pwm18-0-cfg { -+ pwm18-0-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_1_cfg: pwm18-1-cfg { -+ pwm18-1-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_2_cfg: pwm18-2-cfg { -+ pwm18-2-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_0_cfg: pwm19-0-cfg { -+ pwm19-0-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_1_cfg: pwm19-1-cfg { -+ pwm19-1-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_2_cfg: pwm19-2-cfg { -+ pwm19-2-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 0408929f7949..a336de5f3d94 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -809,6 +809,226 @@ i2c8: i2c@d401d800 { - status = "disabled"; - }; - -+ pwm0: pwm@d401a000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM0>, -+ <&syscon_apbc CLK_APBC_PWM0_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM0>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@d401a400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM1>, -+ <&syscon_apbc CLK_APBC_PWM1_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM1>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@d401a800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM2>, -+ <&syscon_apbc CLK_APBC_PWM2_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM2>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@d401ac00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401ac00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM3>, -+ <&syscon_apbc CLK_APBC_PWM3_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM3>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@d401b000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM4>, -+ <&syscon_apbc CLK_APBC_PWM4_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM4>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm5: pwm@d401b400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM5>, -+ <&syscon_apbc CLK_APBC_PWM5_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM5>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm6: pwm@d401b800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM6>, -+ <&syscon_apbc CLK_APBC_PWM6_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM6>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm7: pwm@d401bc00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401bc00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM7>, -+ <&syscon_apbc CLK_APBC_PWM7_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM7>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm8: pwm@d4020000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM8>, -+ <&syscon_apbc CLK_APBC_PWM8_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM8>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm9: pwm@d4020400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM9>, -+ <&syscon_apbc CLK_APBC_PWM9_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM9>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm10: pwm@d4020800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM10>, -+ <&syscon_apbc CLK_APBC_PWM10_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM10>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm11: pwm@d4020c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM11>, -+ <&syscon_apbc CLK_APBC_PWM11_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM11>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm12: pwm@d4021000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM12>, -+ <&syscon_apbc CLK_APBC_PWM12_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM12>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm13: pwm@d4021400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM13>, -+ <&syscon_apbc CLK_APBC_PWM13_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM13>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm14: pwm@d4021800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM14>, -+ <&syscon_apbc CLK_APBC_PWM14_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM14>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm15: pwm@d4021c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM15>, -+ <&syscon_apbc CLK_APBC_PWM15_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM15>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm16: pwm@d4022000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM16>, -+ <&syscon_apbc CLK_APBC_PWM16_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM16>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm17: pwm@d4022400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM17>, -+ <&syscon_apbc CLK_APBC_PWM17_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM17>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm18: pwm@d4022800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM18>, -+ <&syscon_apbc CLK_APBC_PWM18_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM18>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm19: pwm@d4022c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM19>, -+ <&syscon_apbc CLK_APBC_PWM19_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM19>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0391-UPSTREAM-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux-lts-kmhv2/0391-UPSTREAM-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch new file mode 100644 index 0000000000..09077f3893 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0391-UPSTREAM-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch @@ -0,0 +1,38 @@ +From 480eafda6c00000e59013a52c8ac92b0a0340d2d Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 20:58:16 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Fix I/O power + settings + +SpacemiT K3 SoC support dual-voltage I/O power domain, while initially +configure to 3.3v, and need to access register from APBC space to switch +to 1.8v domain. + +Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken +ethernet driver. + +Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") +Reported-by: Han Gao +Link: https://patch.msgid.link/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3ea695eb111fc5a7ffddd21d5c3fee6d82560413) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 97cc9e2dd554..7e3cdd42ab8e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1034,6 +1034,7 @@ pinctrl: pinctrl@d401e000 { + clocks = <&syscon_apbc CLK_APBC_AIB>, + <&syscon_apbc CLK_APBC_AIB_BUS>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + }; + + uart10: serial@d401f000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch deleted file mode 100644 index dfea8b63a1..0000000000 --- a/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 990e07e7b25d9ad6863585a17875fd32e9b194ed Mon Sep 17 00:00:00 2001 -From: Thorsten Blum -Date: Sun, 10 May 2026 18:54:21 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: use sysfs_emit in cpu_show_ghostwrite - -Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is -preferred for formatting sysfs output because it provides safer bounds -checking. - -While the current code only emits fixed strings that fit easily within -PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. - -Signed-off-by: Thorsten Blum -Link: https://lore.kernel.org/r/20260510165420.109453-3-thorsten.blum@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/bugs.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c -index 3655fe7d678c..e5758e3f1c7e 100644 ---- a/arch/riscv/kernel/bugs.c -+++ b/arch/riscv/kernel/bugs.c -@@ -5,7 +5,7 @@ - - #include - #include --#include -+#include - - #include - #include -@@ -46,15 +46,15 @@ ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *attr, c - if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { - switch (ghostwrite_state) { - case UNAFFECTED: -- return sprintf(buf, "Not affected\n"); -+ return sysfs_emit(buf, "Not affected\n"); - case MITIGATED: -- return sprintf(buf, "Mitigation: xtheadvector disabled\n"); -+ return sysfs_emit(buf, "Mitigation: xtheadvector disabled\n"); - case VULNERABLE: - fallthrough; - default: -- return sprintf(buf, "Vulnerable\n"); -+ return sysfs_emit(buf, "Vulnerable\n"); - } -- } else { -- return sprintf(buf, "Not affected\n"); - } -+ -+ return sysfs_emit(buf, "Not affected\n"); - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0392-UPSTREAM-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0392-UPSTREAM-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..d0a0a0e895 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0392-UPSTREAM-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,38 @@ +From 4d7d02c5011f52e058f5468879b54e8994f61173 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:35 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: set console baud rate on + Milk-V Jupiter + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") +Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-2-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 4f97acb4f744f516bbe976da8282c0fe213216ff) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index afaad59e6bce..db98dbfadf00 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -20,7 +20,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch deleted file mode 100644 index 61c699fb6b..0000000000 --- a/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 5feeaceeac1d83b0bc4b52a476972edb0633b9b1 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:09 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as parent - for PCIe clock - -According to SpacemiT updated docs, the PCIe master and slave clock's -parent is the pll2_d6 clock, so fix it. - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index bb8b75bdbdb3..1a53b14739fe 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents[] = { - }; - CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); - --CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); --CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); --CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); --CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); --CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); --CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); --CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); --CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); --CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); --CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); -+CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); -+CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); -+CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); -+CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); -+CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); - - static const struct clk_parent_data emac_1588_parents[] = { - CCU_PARENT_NAME(vctcxo_24m), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0393-UPSTREAM-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux-lts-kmhv2/0393-UPSTREAM-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch new file mode 100644 index 0000000000..fe18fb722e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0393-UPSTREAM-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch @@ -0,0 +1,36 @@ +From 76ae3c142243ad74a38a0048541e4e56bcb2be29 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:36 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: sort aliases on Milk-V + Jupiter + +Before adding more aliases, just sort them. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-3-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 9cdeba29d65b10e7bdb1491167141ff2df238ab8) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index db98dbfadf00..fbba33992347 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -14,9 +14,9 @@ / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; +- serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ serial0 = &uart0; + }; + + chosen { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch deleted file mode 100644 index cec142274b..0000000000 --- a/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch +++ /dev/null @@ -1,35 +0,0 @@ -From e7889702a01dfeefc13f75527701150067033d27 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:10 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Fix PCIe clock register - offset - -The offset of PCIe Clock CTRL register for port B and C controller was -wrongly swapped, correct it here. - -Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - include/soc/spacemit/k3-syscon.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h -index 0299bea065a0..a68255dd641f 100644 ---- a/include/soc/spacemit/k3-syscon.h -+++ b/include/soc/spacemit/k3-syscon.h -@@ -168,8 +168,8 @@ - #define APMU_CPU_C2_CLK_CTRL 0x394 - #define APMU_CPU_C3_CLK_CTRL 0x208 - #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 --#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 --#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 - #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 - #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 - #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0394-UPSTREAM-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux-lts-kmhv2/0394-UPSTREAM-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch new file mode 100644 index 0000000000..d2b113a2d9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0394-UPSTREAM-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch @@ -0,0 +1,59 @@ +From 1de348d68788e830d0de3ba1151f1f90cfe31c17 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:37 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable eMMC on Milk-V + Jupiter + +The Milk-V Jupiter board has a connector for an eMMC module. Add an +entry for it in the device tree and alias it mmc0. + +Mark the device as non-removable as eMMC modules have no CD pin and are +not supposed to be inserted or removed while the system is running. On +systems without an eMMC module installed, the kernel emits the following +informational message during boot: + +mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA +mmc0: Failed to initialize a non-removable card + +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-4-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 4bc9f44d581be66718cf7cf6e649fb92b3c2e6c6) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index fbba33992347..1a833e716cb6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -16,6 +16,7 @@ aliases { + ethernet1 = ð1; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; + serial0 = &uart0; + }; + +@@ -105,6 +106,16 @@ &combo_phy { + status = "okay"; + }; + ++&emmc { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch deleted file mode 100644 index 8c7de819c6..0000000000 --- a/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 81e7dee63c57fbbbf525e3b3e475ac4463f4be56 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:11 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe DBI - clock IDs - -Add clock IDs of PCIe DBI (Data Bus Interface) clock. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h -index b22336f3ae40..dfae52547cda 100644 ---- a/include/dt-bindings/clock/spacemit,k3-clocks.h -+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h -@@ -380,6 +380,11 @@ - #define CLK_APMU_ISIM_VCLK1 86 - #define CLK_APMU_ISIM_VCLK2 87 - #define CLK_APMU_ISIM_VCLK3 88 -+#define CLK_APMU_PCIE_PORTA_DBI 89 -+#define CLK_APMU_PCIE_PORTB_DBI 90 -+#define CLK_APMU_PCIE_PORTC_DBI 91 -+#define CLK_APMU_PCIE_PORTD_DBI 92 -+#define CLK_APMU_PCIE_PORTE_DBI 93 - - /* DCIU clocks */ - #define CLK_DCIU_HDMA 0 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0395-UPSTREAM-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux-lts-kmhv2/0395-UPSTREAM-riscv-dts-spacemit-enable-SD-card-support-o.patch new file mode 100644 index 0000000000..8ec4e6bda9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0395-UPSTREAM-riscv-dts-spacemit-enable-SD-card-support-o.patch @@ -0,0 +1,75 @@ +From ce615bc00efde31f8b47b06b7273fc6d405e2c74 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:38 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable SD card support + on Milk-V Jupiter + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with pull-up +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Alias it as mmc1 + +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-5-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 60b5e027c8c8cab69ad9cc7cab71ee795963e7b1) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 1a833e716cb6..beebf804197e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -17,6 +17,7 @@ aliases { + i2c2 = &i2c2; + i2c8 = &i2c8; + mmc0 = &emmc; ++ mmc1 = &sdhci0; + serial0 = &uart0; + }; + +@@ -250,7 +251,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -385,6 +386,24 @@ uboot@a00000 { + }; + }; + ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch deleted file mode 100644 index b1757a1b9e..0000000000 --- a/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 2e07351b454e444fdff46836d26d0ca8f0f1d241 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:12 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock - -Add PCIe DBI (Data Bus Interface) clock which was missing, This will -support PCIe driver to explicitly request and enable all clocks that -needed. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 1a53b14739fe..cb0c4277f72a 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT - - CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); - CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0); - CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); - CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0); - CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); - CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0); - CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); - CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0); - CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); - CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0); - - static const struct clk_parent_data emac_1588_parents[] = { - CCU_PARENT_NAME(vctcxo_24m), -@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { - [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, - [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw, - [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, - [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, - [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0396-UPSTREAM-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux-lts-kmhv2/0396-UPSTREAM-riscv-dts-spacemit-fix-uboot-partition-offs.patch new file mode 100644 index 0000000000..911b308320 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0396-UPSTREAM-riscv-dts-spacemit-fix-uboot-partition-offs.patch @@ -0,0 +1,35 @@ +From 7fde181808d2a610e81bd057e2cac6f82768e559 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:39 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: fix uboot partition + offset on Milk-V Jupiter + +Correct the uboot partition node name to match its actual offset. + +Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-6-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 6edd9a0d32e1ef81133b8cb5b3bb3157a44da4d1) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index beebf804197e..2fc8d6533786 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -379,7 +379,7 @@ env@60000 { + opensbi@70000 { + reg = <0x70000 0x30000>; + }; +- uboot@a00000 { ++ uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch deleted file mode 100644 index 3c8f831c46..0000000000 --- a/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 1e42639469619e69ed0fe533281513ebbf8fb45f Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 9 May 2026 18:00:00 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC for OrangePi - RV2 - -The OrangePi RV2 board has one eMMC slot, so enable eMMC. -Tested using a 16 GiB AJTD4R eMMC module. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260509100000.3315109-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 3a829e3c9cbc..c95ca38e3d4a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -78,6 +78,16 @@ &combo_phy { - status = "okay"; - }; - -+&emmc { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0397-UPSTREAM-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux-lts-kmhv2/0397-UPSTREAM-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch new file mode 100644 index 0000000000..dccdeeade1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0397-UPSTREAM-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch @@ -0,0 +1,53 @@ +From 0306f8c5802acf2fda8055b82fccbbb1396754cd Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 00:40:07 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: fix NULL check in + spacemit_pin_set_config + +spacemit_pin_set_config() looks up the per-pin descriptor with +spacemit_get_pin() then checks the wrong variable for failure: + + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + ... + if (!pin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); + +pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a +valid pin, so rejecting it here drops the PAD config write for the first +pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as +its first entry, so its drive-strength / bias configuration was silently +ignored. + +The intended guard is against spacemit_get_pin() returning NULL when the +pin id isn't in the SoC's pin table. Check spin instead, which both +restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. + +Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") +Signed-off-by: Han Gao +Reviewed-by: Troy Mitchell +Reviewed-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 09c816e5c4d3a8d6d6e4b7537433e5e98505d934) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index f3c754f78074..f71091254382 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -795,7 +795,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, + void __iomem *reg; + unsigned int mux; + +- if (!pin) ++ if (!spin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch deleted file mode 100644 index f786ba93a4..0000000000 --- a/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch +++ /dev/null @@ -1,318 +0,0 @@ -From 952ad4c278b4a099d4fbcabc3b23304339f3277a Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 8 May 2026 15:25:24 +0800 -Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for - accurate SCL frequency - -The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for -master mode operations is determined by the ILCR (I2C Load Count Register). -Previously, the driver relied on the hardware's reset default -values for this register. - -The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL -frequencies lower than intended. For example, with the default -31.5 MHz input clock, these default settings result in an SCL -frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, -and approximately 338 kHz (fast mode) when targeting 400 kHz. -These frequencies are below the 100 kHz/400 kHz nominal speeds. - -This patch integrates the SCL frequency management into -the Common Clock Framework (CCF). Specifically, the ILCR register, -which acts as a frequency divider for the SCL clock, is now registered -as a managed clock (scl_clk) within the CCF. - -The actual hardware timing formulas are: -- standard mode: SCL = FCLK / (2 * SLV + 8) -- fast mode: SCL = FCLK / (2 * FLV + 10) - -These formulas are only valid when the IWCR (Wait Count Register) is -programmed to 0x142A, a value specified by the I2C IP designer. The -driver now initializes IWCR to this value during controller init. - -Reviewed-by: Yixun Lan -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/i2c/busses/Kconfig | 2 +- - drivers/i2c/busses/i2c-k1.c | 174 ++++++++++++++++++++++++++++++++++-- - 2 files changed, 167 insertions(+), 9 deletions(-) - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 4515ded4338c..e53b9487341d 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -798,7 +798,7 @@ config I2C_JZ4780 - config I2C_K1 - tristate "SpacemiT K1 I2C adapter" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on OF -+ depends on OF && COMMON_CLK - help - This option enables support for the I2C interface on the SpacemiT K1 - platform. -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 9152cf436bea..c6fe2052e479 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -4,7 +4,9 @@ - */ - - #include -+#include - #include -+#include - #include - #include - #include -@@ -17,6 +19,8 @@ - #define SPACEMIT_ISR 0x4 /* Status register */ - #define SPACEMIT_IDBR 0xc /* Data buffer register */ - #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ -+#define SPACEMIT_ILCR 0x10 /* Load Count Register */ -+#define SPACEMIT_IWCR 0x14 /* Wait Count Register */ - #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ - - /* SPACEMIT_ICR register fields */ -@@ -88,6 +92,19 @@ - #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ - #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ - -+#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0) -+#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9) -+ -+/* SPACEMIT_IWCR register fields */ -+#define SPACEMIT_WCR_COUNT GENMASK(4, 0) -+#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5) -+#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10) -+ -+/* Required by I2C IP for correct SCL timing */ -+#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \ -+ FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \ -+ FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5)) -+ - /* i2c bus recover timeout: us */ - #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 - -@@ -109,11 +126,20 @@ enum spacemit_i2c_state { - SPACEMIT_STATE_WRITE, - }; - -+enum spacemit_i2c_mode { -+ SPACEMIT_MODE_STANDARD, -+ SPACEMIT_MODE_FAST -+}; -+ - /* i2c-spacemit driver's main struct */ - struct spacemit_i2c_dev { - struct device *dev; - struct i2c_adapter adapt; - -+ struct clk_hw scl_clk_hw; -+ struct clk *scl_clk; -+ enum spacemit_i2c_mode mode; -+ - /* hardware resources */ - void __iomem *base; - int irq; -@@ -135,6 +161,85 @@ struct spacemit_i2c_dev { - u32 status; - }; - -+static void spacemit_i2c_scl_clk_disable_unprepare(void *data) -+{ -+ clk_disable_unprepare(data); -+} -+ -+/* -+ * Calculate the ILCR divider value (lv) from the target SCL rate. -+ * -+ * Hardware timing formulas: -+ * - standard mode: SCL = FCLK / (2 * SLV + 8) -+ * - fast mode: SCL = FCLK / (2 * FLV + 10) -+ */ -+static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c, -+ unsigned long parent_rate, -+ unsigned long target_rate) -+{ -+ u32 offset, denom; -+ -+ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; -+ denom = DIV_ROUND_CLOSEST(parent_rate, target_rate); -+ -+ return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2); -+} -+ -+static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lv, lcr, mask; -+ -+ lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate); -+ -+ mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ? -+ SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK; -+ -+ lcr = readl(i2c->base + SPACEMIT_ILCR); -+ lcr &= ~mask; -+ lcr |= field_prep(mask, lv); -+ writel(lcr, i2c->base + SPACEMIT_ILCR); -+ -+ return 0; -+} -+ -+static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lv, offset; -+ -+ lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate); -+ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; -+ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset); -+ -+ return 0; -+} -+ -+static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lcr, lv = 0; -+ -+ lcr = readl(i2c->base + SPACEMIT_ILCR); -+ -+ if (i2c->mode == SPACEMIT_MODE_STANDARD) { -+ lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr); -+ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8); -+ } -+ -+ lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr); -+ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10); -+} -+ -+static const struct clk_ops spacemit_i2c_clk_ops = { -+ .set_rate = spacemit_i2c_clk_set_rate, -+ .determine_rate = spacemit_i2c_clk_determine_rate, -+ .recalc_rate = spacemit_i2c_clk_recalc_rate, -+}; -+ - static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) - { - u32 val; -@@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_ICR); - } - -+static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c) -+{ -+ struct clk_init_data init = {}; -+ char name[64]; -+ int ret; -+ -+ ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev)); -+ if (ret >= ARRAY_SIZE(name)) -+ dev_warn(i2c->dev, "scl clock name truncated"); -+ -+ init.name = name; -+ init.ops = &spacemit_i2c_clk_ops; -+ init.parent_data = (struct clk_parent_data[]) { -+ { .fw_name = "func" }, -+ }; -+ init.num_parents = 1; -+ -+ i2c->scl_clk_hw.init = &init; -+ -+ return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw); -+} -+ - static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) - { - writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); -@@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - val |= SPACEMIT_CR_MSDIE; - } - -- if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) -+ if (i2c->mode == SPACEMIT_MODE_FAST) - val |= SPACEMIT_CR_MODE_FAST; - - /* disable response to general call */ -@@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_IRCR); - - spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); -+ -+ /* -+ * Initialize IWCR to the value specified by the I2C IP designer. -+ * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard -+ * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when -+ * IWCR contains this specific value. -+ */ -+ writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR); - } - - static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) -@@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); - - /* For now, this driver doesn't support high-speed. */ -- if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { -- dev_warn(dev, "unsupported clock frequency %u; using %u\n", -- i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); -+ if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && -+ i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { -+ i2c->mode = SPACEMIT_MODE_FAST; -+ } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { -+ i2c->mode = SPACEMIT_MODE_STANDARD; -+ } else { -+ dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); -+ i2c->mode = SPACEMIT_MODE_FAST; - i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; -- } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { -- dev_warn(dev, "unsupported clock frequency %u; using %u\n", -- i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); -- i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; - } - - i2c->dev = &pdev->dev; -@@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); - -+ ret = spacemit_i2c_register_scl_clk(i2c); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register scl clock\n"); -+ -+ i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl"); -+ if (IS_ERR(i2c->scl_clk)) -+ return dev_err_probe(dev, PTR_ERR(i2c->scl_clk), -+ "failed to get scl clock\n"); -+ - clk = devm_clk_get_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); -@@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - return dev_err_probe(dev, PTR_ERR(rst), - "failed to acquire deasserted reset\n"); - -+ ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to set rate for SCL clock"); -+ -+ ret = clk_prepare_enable(i2c->scl_clk); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to prepare and enable clock"); -+ -+ ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare, -+ i2c->scl_clk); -+ if (ret) -+ return ret; -+ - spacemit_i2c_reset(i2c); - - i2c_set_adapdata(&i2c->adapt, i2c); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0398-UPSTREAM-riscv-also-select-ARCH_KEEP_MEMBLOCK-if-kex.patch b/SPECS/linux-lts-kmhv2/0398-UPSTREAM-riscv-also-select-ARCH_KEEP_MEMBLOCK-if-kex.patch new file mode 100644 index 0000000000..d946566608 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0398-UPSTREAM-riscv-also-select-ARCH_KEEP_MEMBLOCK-if-kex.patch @@ -0,0 +1,38 @@ +From ffdcc545657a81c173eccf702463e8e760627d50 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 00:55:46 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: also select ARCH_KEEP_MEMBLOCK if kexec + is selected + +On RISC-V, also select ARCH_KEEP_MEMBLOCK if kexec is selected, not +only if ACPI is selected. This is because kexec requires the memblock +areas to be kept after boot to initialize the secondary kernel. This +is needed for both Device Tree and ACPI platforms. + +Signed-off-by: Han Gao +Link: https://patch.msgid.link/20260519165546.123105-1-gaohan@iscas.ac.cn +[pjw@kernel.org: change to add the dependency on kexec, rather than making it unconditional; + rewrite the patch description accordingly] +Signed-off-by: Paul Walmsley +(cherry picked from commit bce35135fecc7a73c60aaa9d2ec699ead1e32661) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 4946ac7b6db1..5a3e88128ee0 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -56,7 +56,7 @@ config RISCV + select ARCH_HAS_UBSAN + select ARCH_HAS_VDSO_ARCH_DATA if HAVE_GENERIC_VDSO + select ARCH_HAVE_NMI_SAFE_CMPXCHG +- select ARCH_KEEP_MEMBLOCK if ACPI ++ select ARCH_KEEP_MEMBLOCK if ACPI || KEXEC + select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU + select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX + select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch deleted file mode 100644 index 7e3a638bb7..0000000000 --- a/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 362a9bc03d8080d38e5ea64ba2c39884e945e945 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 8 May 2026 15:25:25 +0800 -Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when - clock-frequency property is absent - -The clock-frequency property is optional according to the DT binding. -Do not emit a warning when the property is missing and fall back to the -default frequency instead. - -Reviewed-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index c6fe2052e479..7cf5c05a20d2 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -833,9 +833,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (!i2c) - return -ENOMEM; - -- ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); -- if (ret && ret != -EINVAL) -- dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); -+ of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); - - /* For now, this driver doesn't support high-speed. */ - if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && -@@ -844,7 +842,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { - i2c->mode = SPACEMIT_MODE_STANDARD; - } else { -- dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); -+ dev_info(dev, "clock-frequency not set or out of range, using fast mode\n"); - i2c->mode = SPACEMIT_MODE_FAST; - i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0399-UPSTREAM-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux-lts-kmhv2/0399-UPSTREAM-riscv-kexec_file-Constrain-segment-placemen.patch new file mode 100644 index 0000000000..7f4b0dceed --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0399-UPSTREAM-riscv-kexec_file-Constrain-segment-placemen.patch @@ -0,0 +1,54 @@ +From c6c0627d65fe33069ebb3a211a784b8f5722c21b Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sat, 6 Jun 2026 20:17:58 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: kexec_file: Constrain segment placement + to direct map + +When kexec_file_load places segments with buf_max=ULONG_MAX and +top_down=true, they land at the highest available physical addresses. +On RISC-V the size of the linear mapping is determined by the active +VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 +extend the range substantially further. When the installed physical +memory exceeds the direct map size of the active mode, top-down +placement puts DTB/initrd at physical addresses outside the linearly +mapped region. The kexec'd kernel cannot reach them during early +boot, triggering a page fault at memcmp in start_kernel. + +Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects +the runtime direct map boundary for the active VM mode (SV39/SV48/ +SV57). This keeps all kexec segments within the linearly mapped +region while preserving the upstream top_down allocation strategy. + +Signed-off-by: Han Gao +Link: https://patch.msgid.link/20260519170641.123517-1-gaohan@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit b67a1ee0db0094c6cc158b087be6c334ad881a41) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/machine_kexec_file.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c +index dd9d92a96517..b5fe17238df2 100644 +--- a/arch/riscv/kernel/machine_kexec_file.c ++++ b/arch/riscv/kernel/machine_kexec_file.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -266,7 +267,7 @@ int load_extra_segments(struct kimage *image, unsigned long kernel_start, + + kbuf.image = image; + kbuf.buf_min = kernel_start + kernel_len; +- kbuf.buf_max = ULONG_MAX; ++ kbuf.buf_max = PFN_PHYS(max_low_pfn); + + #ifdef CONFIG_CRASH_DUMP + /* Add elfcorehdr */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch deleted file mode 100644 index 837fc9207b..0000000000 --- a/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 56ba1d8c335d661163b9d3b1d870a9e07dd575cc Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:56 +0200 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add pinctrl - support for voltage switching - -Document pinctrl properties to support voltage-dependent pin -configuration switching for UHS-I SD card modes. - -Add optional pinctrl-names property with two states: -- "default": For 3.3V operation with standard drive strength -- "state_uhs": For 1.8V operation with optimized drive strength - -These pinctrl states allow the SDHCI driver to coordinate voltage -switching with pin configuration changes, ensuring proper signal -integrity during UHS-I mode transitions. - -Acked-by: Conor Dooley -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-1-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 1081ea687702..e5534c781c19 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -44,6 +44,18 @@ properties: - - const: axi - - const: sdh - -+ pinctrl-names: -+ minItems: 1 -+ items: -+ - const: default -+ - const: uhs -+ -+ pinctrl-0: -+ description: Default pinctrl state for 3.3V operation -+ -+ pinctrl-1: -+ description: Optional pinctrl state for 1.8V UHS operation with "uhs" name -+ - required: - - compatible - - reg -@@ -66,4 +78,7 @@ examples: - clock-names = "core", "io"; - resets = <&syscon_apmu 2>, <&syscon_apmu 5>; - reset-names = "axi", "sdh"; -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&sdhci_default_cfg>; -+ pinctrl-1 = <&sdhci_uhs_cfg>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0400-UPSTREAM-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0400-UPSTREAM-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch new file mode 100644 index 0000000000..8257476d7a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0400-UPSTREAM-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch @@ -0,0 +1,181 @@ +From 18e50b0e446a995f40df70e3c2285bdac6c0fcd5 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Wed, 20 May 2026 18:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PMIC on OrangePi + R2S + +Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and +its associated regulators to support voltage regulation on the board. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun lan +Link: https://patch.msgid.link/20260520100000.575719-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit 793cc54475b49b5b558902b5c13e4bfe66530a50) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ + 1 file changed, 134 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index 1ecc40749e5a..b13a8d6a2670 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -13,6 +13,7 @@ / { + compatible = "xunlong,orangepi-r2s", "spacemit,k1"; + + aliases { ++ i2c8 = &i2c8; + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; +@@ -22,6 +23,15 @@ chosen { + stdout-path = "serial0"; + }; + ++ vcc4v0: regulator-vcc4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ }; ++ + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; +@@ -94,6 +104,130 @@ rgmii1: phy@1 { + }; + }; + ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <&vcc4v0>; ++ vin2-supply = <&vcc4v0>; ++ vin3-supply = <&vcc4v0>; ++ vin4-supply = <&vcc4v0>; ++ vin5-supply = <&vcc4v0>; ++ vin6-supply = <&vcc4v0>; ++ aldoin-supply = <&vcc4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1_3v3: aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch deleted file mode 100644 index 5583dc6077..0000000000 --- a/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch +++ /dev/null @@ -1,65 +0,0 @@ -From a164c67f524d96eea999938772b0e7664cf8432d Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:57 +0200 -Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: enable essential clock - infrastructure for SD operation - -Ensure SD card pins receive clock signals by enabling pad clock -generation and overriding automatic clock gating. Required for all SD -operation modes. - -The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD -and eMMC operation as both protocols use the same physical MMC interface -pins and require proper clock signal generation at the hardware level -for signal integrity and timing. - -Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and -SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only -controllers to handle removable card scenarios. - -Tested-by: Anand Moon -Acked-by: Adrian Hunter -Tested-by: Trevor Gamblin -Reviewed-by: Troy Mitchell -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-2-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 455656f9842d..0dd06fc19b85 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -21,6 +21,13 @@ - #include "sdhci.h" - #include "sdhci-pltfm.h" - -+#define SPACEMIT_SDHC_OP_EXT_REG 0x108 -+#define SDHC_OVRRD_CLK_OEN BIT(11) -+#define SDHC_FORCE_CLK_ON BIT(12) -+ -+#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C -+#define SDHC_GEN_PAD_CLK_ON BIT(6) -+ - #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 - #define SDHC_MISC_INT_EN BIT(1) - #define SDHC_MISC_INT BIT(2) -@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) - - if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) - spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); -+ -+ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); -+ -+ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) -+ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, -+ SPACEMIT_SDHC_OP_EXT_REG); - } - - static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0401-UPSTREAM-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux-lts-kmhv2/0401-UPSTREAM-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch new file mode 100644 index 0000000000..e8f37c6f38 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0401-UPSTREAM-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch @@ -0,0 +1,102 @@ +From b888c1af17bb7d9698d667fe697cf2ce716998fe Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 26 May 2026 15:22:58 -0400 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Add Ziccrse + extension for X100 cores + +Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse +provides a forward progress guarantee on LR/SC sequences in main +memory regions with cacheability and coherence PMAs. + +The SpacemiT X100 core supports it per the SpacemiT K3 hardware +specification. + +Signed-off-by: Guodong Xu +Reviewed-by: Yixun lan +Link: https://patch.msgid.link/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit b4a789799d4c2be03a2c9a4e06f3ea817bb04416) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 7e3cdd42ab8e..0b5c6c741ba1 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -36,7 +36,7 @@ cpu_0: cpu@0 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -77,7 +77,7 @@ cpu_1: cpu@1 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -118,7 +118,7 @@ cpu_2: cpu@2 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -159,7 +159,7 @@ cpu_3: cpu@3 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -200,7 +200,7 @@ cpu_4: cpu@4 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -241,7 +241,7 @@ cpu_5: cpu@5 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -282,7 +282,7 @@ cpu_6: cpu@6 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -323,7 +323,7 @@ cpu_7: cpu@7 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch deleted file mode 100644 index d77d4b7d8e..0000000000 --- a/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 7104b26621a3b8b7a0f213f846d4e94f40cbd6ef Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:58 +0200 -Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl - voltage switching support - -Add voltage switching infrastructure for UHS-I modes by integrating both -regulator framework (for supply voltage control) and pinctrl state -switching (for pin drive strength optimization). - -- Add regulator supply parsing and voltage switching callback -- Add optional pinctrl state switching between "default" (3.3V) and - "state_uhs" (1.8V) configurations -- Enable coordinated voltage and pin configuration changes for UHS modes - -This provides complete voltage switching support while maintaining -backward compatibility when pinctrl states are not defined. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Acked-by: Adrian Hunter -Reviewed-by: Troy Mitchell -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-3-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ - 1 file changed, 72 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 0dd06fc19b85..d9144537032a 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - - #include "sdhci.h" -@@ -71,6 +72,9 @@ - struct spacemit_sdhci_host { - struct clk *clk_core; - struct clk *clk_io; -+ struct pinctrl *pinctrl; -+ struct pinctrl_state *pinctrl_default; -+ struct pinctrl_state *pinctrl_uhs; - }; - - /* All helper functions will update clr/set while preserve rest bits */ -@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) - SPACEMIT_SDHC_PHY_CTRL_REG); - } - -+static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, -+ struct mmc_ios *ios) -+{ -+ struct sdhci_host *host = mmc_priv(mmc); -+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); -+ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); -+ struct pinctrl_state *state; -+ int ret; -+ -+ ret = sdhci_start_signal_voltage_switch(mmc, ios); -+ if (ret) -+ return ret; -+ -+ if (!sdhst->pinctrl) -+ return 0; -+ -+ /* Select appropriate pinctrl state based on signal voltage */ -+ switch (ios->signal_voltage) { -+ case MMC_SIGNAL_VOLTAGE_330: -+ state = sdhst->pinctrl_default; -+ break; -+ case MMC_SIGNAL_VOLTAGE_180: -+ state = sdhst->pinctrl_uhs; -+ break; -+ default: -+ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); -+ return 0; -+ } -+ -+ ret = pinctrl_select_state(sdhst->pinctrl, state); -+ if (ret) { -+ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); -+ return 0; -+ } -+ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", -+ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); -+ -+ return 0; -+} -+ - static inline int spacemit_sdhci_get_clocks(struct device *dev, - struct sdhci_pltfm_host *pltfm_host) - { -@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) - return 0; - } - -+static inline void spacemit_sdhci_get_pins(struct device *dev, -+ struct sdhci_pltfm_host *pltfm_host) -+{ -+ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); -+ -+ sdhst->pinctrl = devm_pinctrl_get(dev); -+ if (IS_ERR(sdhst->pinctrl)) { -+ sdhst->pinctrl = NULL; -+ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); -+ return; -+ } -+ -+ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); -+ if (IS_ERR(sdhst->pinctrl_default)) -+ sdhst->pinctrl_default = NULL; -+ -+ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); -+ if (IS_ERR(sdhst->pinctrl_uhs)) -+ sdhst->pinctrl_uhs = NULL; -+ -+ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", -+ sdhst->pinctrl_default, sdhst->pinctrl_uhs); -+} -+ - static const struct sdhci_ops spacemit_sdhci_ops = { - .get_max_clock = spacemit_sdhci_clk_get_max_clock, - .reset = spacemit_sdhci_reset, -@@ -324,6 +392,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - - host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; - -+ spacemit_sdhci_get_pins(dev, pltfm_host); -+ -+ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; -+ - ret = spacemit_sdhci_get_clocks(dev, pltfm_host); - if (ret) - goto err_pltfm; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0402-UPSTREAM-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux-lts-kmhv2/0402-UPSTREAM-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch new file mode 100644 index 0000000000..2ac544628f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0402-UPSTREAM-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch @@ -0,0 +1,55 @@ +From 4ab83cd1c5eede7457f1f446a59bbaa8a8f3d768 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 28 May 2026 19:38:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Enhance the logging check for mmu + mapping + +When enabling dirty ring, the dirty bitmap is disable, and the logging +check is always false as the RISC-V architecture does not select +"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded +since the write path already trying to add the dirty log, the logic for +logging check is broken and some side effect will occurs. + +Enhance the logging check for mmu mapping so it can check both the dirty +ring and the dirty bitmap. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Anup Patel +Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com +Signed-off-by: Anup Patel +(cherry picked from commit 851334760330dafa68ab8f371e804ea6ad56ff9a) +Signed-off-by: Han Gao +--- + arch/riscv/kvm/mmu.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c +index 58f5f3536ffd..a0d9c113258e 100644 +--- a/arch/riscv/kvm/mmu.c ++++ b/arch/riscv/kvm/mmu.c +@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, + enum kvm_mr_change change) + { + /* +- * At this point memslot has been committed and there is an +- * allocated dirty_bitmap[], dirty pages will be tracked while +- * the memory slot is write protected. ++ * At this point memslot has been committed and dirty pages will be ++ * tracked while the memory slot is write protected. + */ + if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) + mmu_wp_memory_region(kvm, new->id); +@@ -314,8 +313,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, + struct vm_area_struct *vma; + struct kvm *kvm = vcpu->kvm; + struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; +- bool logging = (memslot->dirty_bitmap && +- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; ++ bool logging = kvm_slot_dirty_track_enabled(memslot) && ++ !(memslot->flags & KVM_MEM_READONLY); + unsigned long vma_pagesize, mmu_seq; + struct kvm_gstage gstage; + struct page *page; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch deleted file mode 100644 index a431dd69fd..0000000000 --- a/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 88c16045a194f9da4ac3d1e41104c2bc67bef52f Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:59 +0200 -Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR tuning - support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Implement software tuning algorithm to enable UHS-I SDR modes for SD -card operation and HS200 mode for eMMC. This adds both TX and RX delay -line tuning based on the SpacemiT K1 controller capabilities. - -Algorithm features: -- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) -- Conditional tuning: only for high-speed modes (≥100MHz) -- TX tuning: configure transmit delay line with optimal values - (dline_reg=0, delaycode=127) to ensure optimal signal output timing -- RX tuning: single-pass window detection algorithm testing full - delay range (0-255) to find optimal receive timing window -- Retry mechanism: multiple fallback delays within optimal window - for improved reliability - -Tested-by: Anand Moon -Acked-by: Adrian Hunter -Tested-by: Trevor Gamblin -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-4-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ - 1 file changed, 172 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index d9144537032a..37b0911e7cf2 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -69,6 +69,28 @@ - #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) - #define SDHC_RX_BIAS_CTRL BIT(5) - -+#define SPACEMIT_SDHC_RX_CFG_REG 0x118 -+#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) -+#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) -+#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) -+ -+#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 -+#define SDHC_DLINE_PU BIT(0) -+#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) -+#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) -+ -+#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 -+#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) -+#define SDHC_RX_DLINE_GAIN BIT(8) -+#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) -+ -+#define SPACEMIT_RX_DLINE_REG 9 -+#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 -+#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF -+ -+#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 -+#define SPACEMIT_TX_TUNING_DELAYCODE 127 -+ - struct spacemit_sdhci_host { - struct clk *clk_core; - struct clk *clk_io; -@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u - sdhci_writel(host, val, reg); - } - -+static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, -+ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), -+ SPACEMIT_SDHC_DLINE_CTRL_REG); -+} -+ -+static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, -+ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), -+ SPACEMIT_SDHC_DLINE_CTRL_REG); -+} -+ -+static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, -+ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), -+ SPACEMIT_SDHC_DLINE_CFG_REG); -+} -+ -+static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) -+{ -+ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); -+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); -+ udelay(5); -+} -+ -+static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, -+ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), -+ SPACEMIT_SDHC_DLINE_CFG_REG); -+ -+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); -+ udelay(5); -+ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, -+ SPACEMIT_SDHC_RX_CFG_REG); -+ -+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) -+ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); -+} -+ - static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) - { - sdhci_reset(host, mask); -@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) - return clk_get_rate(pltfm_host->clk); - } - -+static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) -+{ -+ int current_len = 0, current_start = 0; -+ int max_pass_len = 0, max_pass_start = 0; -+ struct mmc_host *mmc = host->mmc; -+ struct mmc_ios ios = mmc->ios; -+ u8 final_delay; -+ int ret = 0; -+ int i; -+ -+ /* -+ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and -+ * if clock frequency is greater than 100MHz in these modes. -+ */ -+ if (host->clock < 100 * 1000 * 1000 || -+ !(ios.timing == MMC_TIMING_MMC_HS200 || -+ ios.timing == MMC_TIMING_UHS_SDR50 || -+ ios.timing == MMC_TIMING_UHS_SDR104)) -+ return 0; -+ -+ if (mmc->caps2 & MMC_CAP2_NO_MMC) { -+ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); -+ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); -+ spacemit_sdhci_tx_tuning_prepare(host); -+ -+ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", -+ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); -+ } -+ -+ spacemit_sdhci_prepare_tuning(host); -+ -+ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { -+ spacemit_sdhci_set_rx_delay(host, i); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ -+ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", -+ i, ret == 0 ? "pass" : "fail"); -+ -+ if (ret == 0) { -+ /* Test passed - extend current window */ -+ if (current_len == 0) -+ current_start = i; -+ current_len++; -+ } else { -+ /* Test failed - check if current window is best so far */ -+ if (current_len > max_pass_len) { -+ max_pass_len = current_len; -+ max_pass_start = current_start; -+ } -+ current_len = 0; -+ } -+ } -+ -+ if (current_len > max_pass_len) { -+ max_pass_len = current_len; -+ max_pass_start = current_start; -+ } -+ -+ if (max_pass_len < 3) { -+ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); -+ return -EIO; -+ } -+ -+ final_delay = max_pass_start + max_pass_len / 2; -+ spacemit_sdhci_set_rx_delay(host, final_delay); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ if (ret) { -+ u8 retry_delays[] = { -+ max_pass_start + max_pass_len / 4, -+ max_pass_start + (3 * max_pass_len) / 4, -+ max_pass_start, -+ max_pass_start + max_pass_len - 1 -+ }; -+ int retry_count = ARRAY_SIZE(retry_delays); -+ -+ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", -+ final_delay); -+ -+ for (i = 0; i < retry_count; i++) { -+ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && -+ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { -+ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ if (!ret) { -+ final_delay = retry_delays[i]; -+ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", -+ final_delay); -+ break; -+ } -+ } -+ } -+ -+ if (ret) { -+ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); -+ return -EIO; -+ } -+ } -+ -+ dev_dbg(mmc_dev(host->mmc), -+ "Tuning successful: window %d-%d, using delay %d\n", -+ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); -+ -+ return 0; -+} -+ - static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) - { - struct sdhci_host *host = mmc_priv(mmc); -@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { - .set_bus_width = sdhci_set_bus_width, - .set_clock = spacemit_sdhci_set_clock, - .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, -+ .platform_execute_tuning = spacemit_sdhci_execute_tuning, - }; - - static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0403-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-phy-int.patch b/SPECS/linux-lts-kmhv2/0403-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-phy-int.patch new file mode 100644 index 0000000000..38bb88c006 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0403-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-phy-int.patch @@ -0,0 +1,59 @@ +From 27323eb8136e33d506d96efa5b34658c0fe05a8c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 23 Jun 2026 15:46:34 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: dwmac-spacemit: Fix wrong phy + interface definition + +The current MII interface register definition from the vendor is wrong, +use the right number for the macro. Also, correct the interface mask +in spacemit_set_phy_intf_sel() so it can update the register with the +right number + +Fixes: 30f0ba420ed3 ("net: stmmac: Add glue layer for Spacemit K3 SoC") +Signed-off-by: Inochi Amaoto +Reviewed-by: Maxime Chevallier +Link: https://patch.msgid.link/20260623074637.503864-2-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit d1e3a4c3b24d4430d9987a3f349c6c2a959a389a) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +index 223754cc5c79..3bfb6d49be6c 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +@@ -18,8 +18,10 @@ + #include "stmmac_platform.h" + + /* ctrl register bits */ +-#define CTRL_PHY_INTF_RGMII BIT(3) +-#define CTRL_PHY_INTF_MII BIT(4) ++#define CTRL_PHY_INTF_MODE GENMASK(4, 3) ++#define CTRL_PHY_INTF_RMII FIELD_PREP(CTRL_PHY_INTF_MODE, 0) ++#define CTRL_PHY_INTF_RGMII FIELD_PREP(CTRL_PHY_INTF_MODE, 1) ++#define CTRL_PHY_INTF_MII FIELD_PREP(CTRL_PHY_INTF_MODE, 3) + #define CTRL_WAKE_IRQ_EN BIT(9) + #define CTRL_PHY_IRQ_EN BIT(12) + +@@ -118,7 +120,7 @@ static void spacemit_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, + + static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) + { +- unsigned int mask = CTRL_PHY_INTF_MII | CTRL_PHY_INTF_RGMII; ++ unsigned int mask = CTRL_PHY_INTF_MODE; + struct spacmit_dwmac *dwmac = bsp_priv; + unsigned int val = 0; + +@@ -128,6 +130,7 @@ static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) + break; + + case PHY_INTF_SEL_RMII: ++ val = CTRL_PHY_INTF_RMII; + break; + + case PHY_INTF_SEL_RGMII: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch deleted file mode 100644 index acee11c137..0000000000 --- a/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch +++ /dev/null @@ -1,105 +0,0 @@ -From c7ea3695cea289291e871b1d5ee24585b4b969ad Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:48:59 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1: add SD card - controller and pinctrl support - -Add SD card controller infrastructure for SpacemiT K1 SoC with complete -pinctrl support for both standard and UHS modes. - -- Add sdhci0 controller definition with clocks, resets and interrupts -- Add mmc1_cfg pinctrl for 3.3V standard SD operation -- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation -- Configure appropriate drive strength and power-source properties - -This provides complete SD card infrastructure that K1-based boards can -enable. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Tested-by: Vincent Legoll -Reviewed-by: Troy Mitchell -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ - 2 files changed, 53 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index 34d88334e95e..4e9a62d0e85b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -590,4 +590,44 @@ ssp3-0-frm-pins { - power-source = <3300>; - }; - }; -+ -+ mmc1_cfg: mmc1-cfg { -+ mmc1-data-cmd-pins { -+ pinmux = , /* mmc1_d3 */ -+ , /* mmc1_d2 */ -+ , /* mmc1_d1 */ -+ , /* mmc1_d0 */ -+ ; /* mmc1_cmd */ -+ bias-pull-up = <1>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ -+ mmc1-clk-pins { -+ pinmux = ; /* mmc1_clk */ -+ bias-pull-down = <1>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ mmc1_uhs_cfg: mmc1-uhs-cfg { -+ mmc1-data-cmd-pins { -+ pinmux = , /* mmc1_d3 */ -+ , /* mmc1_d2 */ -+ , /* mmc1_d1 */ -+ , /* mmc1_d0 */ -+ ; /* mmc1_cmd */ -+ bias-pull-up = <1>; -+ drive-strength = <42>; -+ power-source = <1800>; -+ }; -+ -+ mmc1-clk-pins { -+ pinmux = ; /* mmc1_clk */ -+ bias-pull-down = <1>; -+ drive-strength = <42>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 8774a00a854b..4a359190f633 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1323,6 +1323,19 @@ usb_dwc3: usb@c0a00000 { - status = "disabled"; - }; - -+ sdhci0: mmc@d4280000 { -+ compatible = "spacemit,k1-sdhci"; -+ reg = <0x0 0xd4280000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_SDH_AXI>, -+ <&syscon_apmu CLK_SDH0>; -+ clock-names = "core", "io"; -+ resets = <&syscon_apmu RESET_SDH_AXI>, -+ <&syscon_apmu RESET_SDH0>; -+ reset-names = "axi", "sdh"; -+ interrupts = <99>; -+ status = "disabled"; -+ }; -+ - emmc: mmc@d4281000 { - compatible = "spacemit,k1-sdhci"; - reg = <0x0 0xd4281000 0x0 0x200>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0404-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-irq-def.patch b/SPECS/linux-lts-kmhv2/0404-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-irq-def.patch new file mode 100644 index 0000000000..d814720d53 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0404-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-irq-def.patch @@ -0,0 +1,38 @@ +From 407faee624342cf52e173a9481305cc6eb8e456a Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 23 Jun 2026 15:46:35 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: dwmac-spacemit: Fix wrong irq + definition + +The current irq definition of the wake irq and the lpi irq +is wrong, replace them with the right number and name. + +Fixes: 30f0ba420ed3 ("net: stmmac: Add glue layer for Spacemit K3 SoC") +Signed-off-by: Inochi Amaoto +Reviewed-by: Maxime Chevallier +Link: https://patch.msgid.link/20260623074637.503864-3-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit bf5cd5d4ca423d348e01b3bbcdccd0e02b1b408b) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +index 3bfb6d49be6c..322bdf167a4a 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +@@ -22,8 +22,8 @@ + #define CTRL_PHY_INTF_RMII FIELD_PREP(CTRL_PHY_INTF_MODE, 0) + #define CTRL_PHY_INTF_RGMII FIELD_PREP(CTRL_PHY_INTF_MODE, 1) + #define CTRL_PHY_INTF_MII FIELD_PREP(CTRL_PHY_INTF_MODE, 3) +-#define CTRL_WAKE_IRQ_EN BIT(9) +-#define CTRL_PHY_IRQ_EN BIT(12) ++#define CTRL_LPI_IRQ_EN BIT(9) ++#define CTRL_WAKE_IRQ_EN BIT(12) + + /* dline register bits */ + #define RGMII_RX_DLINE_EN BIT(0) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch deleted file mode 100644 index ba6141397e..0000000000 --- a/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 43968e62edda768281d634a038212b96befc49e5 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:49:00 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add SD - card support with UHS modes - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with GPIO_ACTIVE_LOW logic -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) - -This enables full SD card functionality including high-speed UHS modes -for improved performance. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Tested-by: Michael Opdenacker -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- - 1 file changed, 21 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index c95ca38e3d4a..bd40bc9011e2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -17,6 +17,8 @@ aliases { - serial0 = &uart0; - ethernet0 = ð0; - ethernet1 = ð1; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - - chosen { -@@ -202,7 +204,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -319,3 +321,21 @@ hub_3_0: hub@2 { - vdd-supply = <&vcc_5v0>; - }; - }; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4_3v3>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0405-UPSTREAM-dt-bindings-riscv-spacemit-add-deepcomputin.patch b/SPECS/linux-lts-kmhv2/0405-UPSTREAM-dt-bindings-riscv-spacemit-add-deepcomputin.patch new file mode 100644 index 0000000000..073007da3e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0405-UPSTREAM-dt-bindings-riscv-spacemit-add-deepcomputin.patch @@ -0,0 +1,37 @@ +From 539b63af7f1e72efe62cb18355b5ffa9e2ea3a9f Mon Sep 17 00:00:00 2001 +From: Sandie Cao +Date: Tue, 21 Apr 2026 14:42:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: add + deepcomputing,fml13v05 + +Document the compatible string for the Deepcomputing fml13v05. +It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework +Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. + +Acked-by: Conor Dooley +Signed-off-by: Sandie Cao +Reviewed-by: Troy Mitchell +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260421064200.1582367-1-sandie.cao@deepcomputing.io +Signed-off-by: Yixun Lan +(cherry picked from commit a17be027dc5ccd51b99b5bc7b487ba9fbdc554e8) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index eca403a8e49e..5fa5080e1f61 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -27,6 +27,7 @@ properties: + - const: spacemit,k1 + - items: + - enum: ++ - deepcomputing,fml13v05 + - spacemit,k3-pico-itx + - const: spacemit,k3 + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch deleted file mode 100644 index 5173364a60..0000000000 --- a/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 139e0716fdfe2ce733d52f88221f1b6727235cf7 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:49:01 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add SD - card support with UHS modes - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up - support -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) - -This enables full SD card functionality including high-speed UHS modes -for improved performance. - -Suggested-by: Anand Moon -Tested-by: Anand Moon -Tested-by: Margherita Milani -Tested-by: Aurelien Jarno -Reviewed-by: Aurelien Jarno -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- - 1 file changed, 22 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index b48a485f954b..b15f4c36e622 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -18,6 +18,8 @@ aliases { - spi3 = &spi3; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - - chosen { -@@ -267,7 +269,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -288,7 +290,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -421,3 +423,21 @@ hub_3_0: hub@2 { - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; - }; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0406-UPSTREAM-riscv-dts-spacemit-add-DeepComputing-FML13V.patch b/SPECS/linux-lts-kmhv2/0406-UPSTREAM-riscv-dts-spacemit-add-DeepComputing-FML13V.patch new file mode 100644 index 0000000000..f8991d0349 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0406-UPSTREAM-riscv-dts-spacemit-add-DeepComputing-FML13V.patch @@ -0,0 +1,89 @@ +From 5bb2f1fa80f4d0c23b08ab1736164985cf0ee1df Mon Sep 17 00:00:00 2001 +From: Sandie Cao +Date: Tue, 21 Apr 2026 14:43:06 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add DeepComputing + FML13V05 board device tree + +The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V +SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, +which has (Framework) SKU FRANHQ0001. + +The FML13V05 board features: +- SpacemiT K3 RISC-V SoC +- LPDDR5 16GB or 32GB +- eMMC 32GB ~128GB (Optional) +- UFS 3.1 256G (Optional) +- QSPI Flash +- MicroSD Slot +- PCIe-based Wi-Fi +- 4 USB-C Ports + - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1 + - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz) + - Port 3 & 4: USB 3.2 Gen 1 + +This minimal device tree enables booting into a serial console with UART +output. + +Signed-off-by: Sandie Cao +Reviewed-by: Troy Mitchell +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260421064306.1583888-1-sandie.cao@deepcomputing.io +Signed-off-by: Yixun Lan +(cherry picked from commit 448fedd56cdfa68c2e661b16a8dfc8f3c40a1bcf) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + .../spacemit/k3-deepcomputing-fml13v05.dts | 31 +++++++++++++++++++ + 2 files changed, 32 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index 7e2b87702571..acb993c452ba 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +new file mode 100644 +index 000000000000..b5d5112de358 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2026 DeepComputing (HK) Limited ++ */ ++ ++#include "k3.dtsi" ++#include "k3-pinctrl.dtsi" ++ ++/ { ++ model = "DeepComputing FML13V05"; ++ compatible = "deepcomputing,fml13v05", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch deleted file mode 100644 index fc44499a76..0000000000 --- a/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 25997e10bcbb4842cd8f7f69db1754a807b4515b Mon Sep 17 00:00:00 2001 -From: Trevor Gamblin -Date: Fri, 15 May 2026 12:49:02 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD - card support with UHS modes - -Update the Muse Pi Pro devicetree with SD card support to match what -was done for the OrangePi RV2 in [1]. More precisely: - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with internal pull-up support -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) -- Update PMIC configuration to use per-regulator supply properties - -[1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# - -Tested-by: Andre Heider -Signed-off-by: Trevor Gamblin -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-4-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 60 +++++++++++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index c8bf776511c9..9952014701f7 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -19,8 +19,20 @@ aliases { - serial0 = &uart0; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - -+ reg_vcc_4v: vcc-4v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_4v"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ - chosen { - stdout-path = "serial0:115200n8"; - }; -@@ -399,3 +411,51 @@ hub_3_0: hub@2 { - reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ - }; - }; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin4-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ -+ regulators { -+ buck4: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0407-UPSTREAM-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux-lts-kmhv2/0407-UPSTREAM-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch new file mode 100644 index 0000000000..27d9ebfe94 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0407-UPSTREAM-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch @@ -0,0 +1,49 @@ +From b2ab39df317dc237462f72052e611ab59e6d80a6 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 20 May 2026 23:45:27 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: Add K3 + CoM260-IFX board +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module +with a reference carrier board. + +The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD +card slot and includes interfaces such as dual MIPI CSI-2 connectors, +M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin +expansion header. + +The carrier board is intended as a general-purpose development platform +for CoM260 module and exposes interfaces for all of storage, display, +networking, and camera connectivity. + +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3abf3f5c84fd32a95132a403e0209c8010b227f8) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index 5fa5080e1f61..9f1a6e65c7c8 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -30,6 +30,11 @@ properties: + - deepcomputing,fml13v05 + - spacemit,k3-pico-itx + - const: spacemit,k3 ++ - items: ++ - enum: ++ - spacemit,k3-com260-ifx ++ - const: spacemit,k3-com260 ++ - const: spacemit,k3 + + additionalProperties: true + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch deleted file mode 100644 index 5f154ddf37..0000000000 --- a/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 30f59c0f689a00390e4183a7b58ec3108d1d55a8 Mon Sep 17 00:00:00 2001 -From: Thomas Gerner -Date: Thu, 14 May 2026 20:32:01 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Enable wifi on the - BeagleV-Ahead - -The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology -Inc. connected to SDIO1. The chip is compatible to the broadcom wireless -driver. - -The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and -Bluetooth 5.4 module. Bluetooth is not enabled by this patch. - -Signed-off-by: Thomas Gerner -Link: https://lore.kernel.org/r/20260514183510.234063-1-thomas.gerner@muenchen-mail.de -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -index 91f3f9b987bc..e16484a47653 100644 ---- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -@@ -86,6 +86,11 @@ hdmi_con_in: endpoint { - }; - }; - }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ -+ }; - }; - - &osc { -@@ -239,6 +244,28 @@ rx-pins { - slew-rate = <0>; - }; - }; -+ -+ wifi_pins: wifi-0 { -+ host-wake-pins { -+ pins = "GPIO2_25"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <1>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ reg-on-pins { -+ pins = "GPIO2_31"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <3>; -+ input-disable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ }; - }; - - &sdio0 { -@@ -247,6 +274,27 @@ &sdio0 { - status = "okay"; - }; - -+&sdio1 { -+ bus-width = <4>; -+ max-frequency = <198000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ non-removable; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ status = "okay"; -+ -+ wifi@1 { -+ compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <25 IRQ_TYPE_EDGE_RISING>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &dpu { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0408-UPSTREAM-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux-lts-kmhv2/0408-UPSTREAM-riscv-dts-spacemit-k3-Initial-support-for-C.patch new file mode 100644 index 0000000000..3a96620ed0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0408-UPSTREAM-riscv-dts-spacemit-k3-Initial-support-for-C.patch @@ -0,0 +1,308 @@ +From 9bcfedccd2cec21b6492289885ac684deeca84e0 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 20 May 2026 23:45:28 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Initial support for + CoM260-IFX board + +The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer +module with a carrier board. The module integrates the K3 SoC, LPDDR5, +UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers +a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, +DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. + +Add initial support for enabling Serial UART and ethernet. + +Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit cfe5c91cb73c87f9021e446ec9d323c483851c46) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ + arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ + 4 files changed, 245 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts + create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index acb993c452ba..28ec9e1e0a62 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +new file mode 100644 +index 000000000000..238bb03d0e9e +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Yixun Lan ++ */ ++ ++#include "k3-com260.dtsi" ++ ++/ { ++ model = "SpacemiT K3 CoM260 IFX"; ++ compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = ð1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +new file mode 100644 +index 000000000000..a38d7b738258 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +@@ -0,0 +1,190 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Yixun Lan ++ */ ++#include ++ ++#include "k3.dtsi" ++#include "k3-pinctrl.dtsi" ++ ++/ { ++ model = "SpacemiT K3 CoM260 Module"; ++ compatible = "spacemit,k3-com260", "spacemit,k3"; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++ ++ reg_5v_sys: regulator-5v-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "P5V0_SYS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; ++ vin1-supply = <®_5v_sys>; ++ vin2-supply = <®_5v_sys>; ++ vin3-supply = <®_5v_sys>; ++ vin4-supply = <®_5v_sys>; ++ vin5-supply = <®_5v_sys>; ++ vin6-supply = <®_5v_sys>; ++ aldoin-supply = <®_5v_sys>; ++ dldoin1-supply = <&buck4>; ++ dldoin2-supply = <&buck4>; ++ ++ regulators { ++ buck1: buck1 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2: buck2 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3: buck3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4: buck4 { ++ regulator-min-microvolt = <2100000>; ++ regulator-max-microvolt = <2100000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6: buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <500000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1: aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo2: aldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo3: aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4: aldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo1: dldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo2: dldo2 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo3: dldo3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo4: dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ }; ++ ++ dldo5: dldo5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo6: dldo6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo7: dldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; ++}; ++ ++ð1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy1>; ++ status = "okay"; ++ ++ mdio { ++ phy1: phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <10000>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 252c64af76fe..3ee1471f3798 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -45,6 +45,39 @@ gmac0-phy-0-pins { + }; + }; + ++ gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { ++ gmac1-rgmii-0-pins { ++ pinmux = , /* gmac1_rxdv */ ++ , /* gmac1 rx d0 */ ++ , /* gmac1 rx d1 */ ++ , /* gmac1 rx_clk */ ++ , /* gmac1 rx d2 */ ++ , /* gmac1 rx d3 */ ++ , /* gmac1 tx d0 */ ++ , /* gmac1 tx d1 */ ++ , /* gmac1 tx clk */ ++ , /* gmac1 tx d2 */ ++ , /* gmac1 tx d3 */ ++ , /* gmac1 tx_en */ ++ , /* gmac1 mdc */ ++ ; /* gmac1 mdio */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ gmac1_phy_0_cfg: gmac1-phy-0-cfg { ++ gmac1-phy-0-pins { ++ pinmux = ; /* gmac1 int */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch deleted file mode 100644 index d8e8c34faf..0000000000 --- a/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch +++ /dev/null @@ -1,47 +0,0 @@ -From d02e702da21996ccb557b91e5cb594f6c76e0025 Mon Sep 17 00:00:00 2001 -From: Florian Schmaus -Date: Tue, 12 May 2026 08:32:31 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: module: Use generic cmp_int() instead - of custom cmp_3way() - -The module-sections.c file defines a custom cmp_3way() macro to perform -3-way comparisons during relocation sorting. - -Instead of maintaining our own implementation, use the generic -cmp_int() macro provided by the already included . This -removes redundant code and relies on standard kernel interfaces. - -Signed-off-by: Florian Schmaus -Link: https://lore.kernel.org/r/20260512063231.708256-1-florian.schmaus@codasip.com -Signed-off-by: Han Gao ---- - arch/riscv/kernel/module-sections.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module-sections.c -index 1675cbad8619..33750a51f157 100644 ---- a/arch/riscv/kernel/module-sections.c -+++ b/arch/riscv/kernel/module-sections.c -@@ -56,17 +56,15 @@ unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) - return (unsigned long)&plt[i]; - } - --#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) -- - static int cmp_rela(const void *a, const void *b) - { - const Elf_Rela *x = a, *y = b; - int i; - - /* sort by type, symbol index and addend */ -- i = cmp_3way(x->r_info, y->r_info); -+ i = cmp_int(x->r_info, y->r_info); - if (i == 0) -- i = cmp_3way(x->r_addend, y->r_addend); -+ i = cmp_int(x->r_addend, y->r_addend); - return i; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0409-UPSTREAM-riscv-Implement-ARCH_HAS_CC_CAN_LINK.patch b/SPECS/linux-lts-kmhv2/0409-UPSTREAM-riscv-Implement-ARCH_HAS_CC_CAN_LINK.patch new file mode 100644 index 0000000000..17f5734c7e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0409-UPSTREAM-riscv-Implement-ARCH_HAS_CC_CAN_LINK.patch @@ -0,0 +1,61 @@ +From eb84757dd5d3bdd86b9d2416592634a065006323 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Sat, 6 Jun 2026 20:17:52 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: Implement ARCH_HAS_CC_CAN_LINK +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The generic CC_CAN_LINK detection relies on -m32/-m64 compiler flags. +These are not supported by riscv compilers. + +Use architecture-specific logic using -mabi instead. + +Prefer the 'd' ABI variant when possible as todays toolchains are most +likely to provide a libc for that one. + +Signed-off-by: Thomas Weißschuh +Link: https://patch.msgid.link/20260316-cc-can-link-riscv-v4-1-64c072b456dd@linutronix.de +Signed-off-by: Paul Walmsley +(cherry picked from commit 84894ceb3c2ef5c5404359efd4edc6c438aa6d0c) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 5a3e88128ee0..12bebdbaaf9f 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -25,6 +25,7 @@ config RISCV + select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 + select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE + select ARCH_HAS_BINFMT_FLAT ++ select ARCH_HAS_CC_CAN_LINK + select ARCH_HAS_CURRENT_STACK_POINTER + select ARCH_HAS_DEBUG_VIRTUAL if MMU + select ARCH_HAS_DEBUG_VM_PGTABLE +@@ -1337,6 +1338,20 @@ config PORTABLE + config ARCH_PROC_KCORE_TEXT + def_bool y + ++config ARCH_CC_CAN_LINK ++ bool ++ default $(cc_can_link_user,-march=rv64g -mabi=lp64d) if 64BIT && FPU ++ default $(cc_can_link_user,-march=rv64g -mabi=lp64) if 64BIT ++ default $(cc_can_link_user,-march=rv32g -mabi=ilp32d) if FPU ++ default $(cc_can_link_user,-march=rv32g -mabi=ilp32) ++ ++config ARCH_USERFLAGS ++ string ++ default "-march=rv64g -mabi=lp64d" if 64BIT && FPU ++ default "-march=rv64g -mabi=lp64" if 64BIT ++ default "-march=rv32g -mabi=ilp32d" if FPU ++ default "-march=rv32g -mabi=ilp32" ++ + menu "Power management options" + + source "kernel/power/Kconfig" +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch deleted file mode 100644 index 616724be18..0000000000 --- a/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 41705cbe35101c7de961fb93f3c0d01b4f424bd3 Mon Sep 17 00:00:00 2001 -From: Thorsten Blum -Date: Tue, 12 May 2026 19:20:35 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: propagate insert_resource result from - add_resource - -Currently, add_resource() returns 1 on success, even though its callers -only check for negative values. Instead, propagate the insert_resource() -result from add_resource() to align with standard kernel return-value -conventions (0 on success, negative errno on failure). - -Use %pR to print the full resource range while at it. - -Signed-off-by: Thorsten Blum -Link: https://lore.kernel.org/r/20260512172034.328405-4-thorsten.blum@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/setup.c | 11 ++++------- - 1 file changed, 4 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c -index b5bc5fc65cea..13b27a078912 100644 ---- a/arch/riscv/kernel/setup.c -+++ b/arch/riscv/kernel/setup.c -@@ -75,16 +75,13 @@ static struct resource *standard_resources; - static int __init add_resource(struct resource *parent, - struct resource *res) - { -- int ret = 0; -+ int ret; - - ret = insert_resource(parent, res); -- if (ret < 0) { -- pr_err("Failed to add a %s resource at %llx\n", -- res->name, (unsigned long long) res->start); -- return ret; -- } -+ if (ret < 0) -+ pr_err("Failed to add resource %s %pR\n", res->name, res); - -- return 1; -+ return ret; - } - - static int __init add_kernel_resources(void) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0410-UPSTREAM-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts-kmhv2/0410-UPSTREAM-riscv-dts-spacemit-k3-Add-USB2.0-support.patch new file mode 100644 index 0000000000..f14ee7c204 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0410-UPSTREAM-riscv-dts-spacemit-k3-Add-USB2.0-support.patch @@ -0,0 +1,104 @@ +From 35e5453fa87c5e5d93a992e15b4581f6940f1037 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 30 Mar 2026 22:15:21 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Add USB2.0 support + +There is one USB2.0 host in K3 SoC which use DWC3 IP but only provide +USB2.0 functionality, and with only one USB2 PHY connected. + +The USB2.0 controller on Pico-ITX board connects to a Terminus FE1.1 Hub +which fully USB2.0 protocol compliant and provides 4 ports. + +Link: https://patch.msgid.link/20260330-02-k3-usb20-dts-v2-1-46af262fb4a9@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit d3bd58f3060f28ecd30df51925a9b1f62e5e8c9b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 4486dc1fe114..b89c1521e664 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -26,6 +26,14 @@ memory@100000000 { + reg = <0x1 0x00000000 0x4 0x00000000>; + }; + ++ reg_aux_vcc3v3: regulator-aux-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + reg_aux_vcc5v: regulator-aux-vcc5v { + compatible = "regulator-fixed"; + regulator-name = "AUX_VCC5V"; +@@ -197,3 +205,19 @@ &uart0 { + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; ++ ++&usb2_host { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ vdd-supply = <®_aux_vcc3v3>; ++ }; ++}; ++ ++&usb2_phy { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 0b5c6c741ba1..19fc9b49668e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -438,6 +438,37 @@ soc: soc { + dma-noncoherent; + ranges; + ++ usb2_host: usb@c0a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, ++ <&syscon_apmu RESET_APMU_USB2_VCC>, ++ <&syscon_apmu RESET_APMU_USB2_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ phys = <&usb2_phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ dr_mode = "host"; ++ maximum-speed = "high-speed"; ++ status = "disabled"; ++ }; ++ ++ usb2_phy: phy@c0a20000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0xc0a20000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + eth0: ethernet@cac80000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac80000 0x0 0x2000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch deleted file mode 100644 index d8ae0df53d..0000000000 --- a/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch +++ /dev/null @@ -1,91 +0,0 @@ -From a380dc5ba876575445cbffdd6abae226725a9fce Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:36 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support - -To reuse the K1 PCIe driver logic for K3 PCIe controller, add device -data to handle the K1 specific logic and make room for the incoming -logic for K3. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-2-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 25 ++++++++++++++++--- - 1 file changed, 21 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index be20a520255b..1b519d49dcc0 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -57,6 +57,12 @@ struct k1_pcie { - u32 pmu_off; - }; - -+struct k1_pcie_device_data { -+ const struct dw_pcie_host_ops *host_ops; -+ const struct dw_pcie_ops *ops; -+ int (*parse_port)(struct k1_pcie *k1); -+}; -+ - #define to_k1_pcie(dw_pcie) \ - platform_get_drvdata(to_platform_device((dw_pcie)->dev)) - -@@ -278,10 +284,15 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) - - static int k1_pcie_probe(struct platform_device *pdev) - { -+ const struct k1_pcie_device_data *data; - struct device *dev = &pdev->dev; - struct k1_pcie *k1; - int ret; - -+ data = device_get_match_data(dev); -+ if (!data) -+ return -ENODEV; -+ - k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); - if (!k1) - return -ENOMEM; -@@ -299,11 +310,11 @@ static int k1_pcie_probe(struct platform_device *pdev) - "failed to map \"link\" registers\n"); - - k1->pci.dev = dev; -- k1->pci.ops = &k1_pcie_ops; -+ k1->pci.ops = data->ops; - k1->pci.pp.num_vectors = MAX_MSI_IRQS; - dw_pcie_cap_set(&k1->pci, REQ_RES); - -- k1->pci.pp.ops = &k1_pcie_host_ops; -+ k1->pci.pp.ops = data->host_ops; - - /* Hold the PHY in reset until we start the link */ - regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, -@@ -320,7 +331,7 @@ static int k1_pcie_probe(struct platform_device *pdev) - - platform_set_drvdata(pdev, k1); - -- ret = k1_pcie_parse_port(k1); -+ ret = data->parse_port(k1); - if (ret) - return dev_err_probe(dev, ret, "failed to parse root port\n"); - -@@ -338,8 +349,14 @@ static void k1_pcie_remove(struct platform_device *pdev) - dw_pcie_host_deinit(&k1->pci.pp); - } - -+static const struct k1_pcie_device_data k1_pcie_device_data = { -+ .host_ops = &k1_pcie_host_ops, -+ .ops = &k1_pcie_ops, -+ .parse_port = k1_pcie_parse_port, -+}; -+ - static const struct of_device_id k1_pcie_of_match_table[] = { -- { .compatible = "spacemit,k1-pcie", }, -+ { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, - { } - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0411-UPSTREAM-i2c-busses-make-K1-driver-default-for-Space.patch b/SPECS/linux-lts-kmhv2/0411-UPSTREAM-i2c-busses-make-K1-driver-default-for-Space.patch new file mode 100644 index 0000000000..688e56d13d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0411-UPSTREAM-i2c-busses-make-K1-driver-default-for-Space.patch @@ -0,0 +1,40 @@ +From dd7106a9bf1dc7aa4b0aef4b1974a592d0d194c4 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Tue, 26 May 2026 16:36:57 +0200 +Subject: [RUYI PATCH] UPSTREAM: i2c: busses: make K1 driver default for + SpacemiT platforms + +Enable I2C_K1 by default when ARCH_SPACEMIT is configured to ensure SD +card functionality works out-of-the-box. + +SpacemiT K1 boards use I2C-controlled PMICs (like the P1 chip) to +provide SD card power supplies. Without the I2C_K1 driver enabled, +regulators cannot be controlled and SD card detection/operation fails. + +Suggested-by: Margherita Milani +Suggested-by: Yixun Lan +Signed-off-by: Iker Pedrosa +Reviewed-by: Yixun Lan +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20260526-orangepi-sd-card-i2c-v1-1-b92268bfd467@gmail.com +(cherry picked from commit d38e710fba1806974051972d69fbbd6c69b55734) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 4515ded4338c..e60faac4e337 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -799,6 +799,7 @@ config I2C_K1 + tristate "SpacemiT K1 I2C adapter" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF ++ default ARCH_SPACEMIT + help + This option enables support for the I2C interface on the SpacemiT K1 + platform. +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch deleted file mode 100644 index b4cf2fd137..0000000000 --- a/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 291d83131cb1a80661bf10272be1b0aab99fb39d Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:37 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles - support - -The PCIe controller on Spacemit K3 may use multiple PHYs at the -same time. The feature is not support by the current driver. -So extend the PHY definition to support multiple PHY handles. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-3-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 16 ++++++++++++---- - 1 file changed, 12 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index 1b519d49dcc0..7f6f1df31cd8 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -51,7 +51,8 @@ - - struct k1_pcie { - struct dw_pcie pci; -- struct phy *phy; -+ struct phy **phy; -+ int phy_count; - void __iomem *link; - struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ - u32 pmu_off; -@@ -171,7 +172,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) - */ - regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); - -- ret = phy_init(k1->phy); -+ ret = phy_init(k1->phy[0]); - if (ret) { - k1_pcie_disable_resources(k1); - -@@ -191,12 +192,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct k1_pcie *k1 = to_k1_pcie(pci); -+ int i; - - /* Assert fundamental reset (drive PERST# low) */ - regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, - PCIE_RC_PERST); - -- phy_exit(k1->phy); -+ for (i = 0; i < k1->phy_count; i++) -+ phy_exit(k1->phy[i]); - - k1_pcie_disable_resources(k1); - } -@@ -277,7 +280,12 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) - if (IS_ERR(phy)) - return PTR_ERR(phy); - -- k1->phy = phy; -+ k1->phy = devm_kmalloc_array(dev, 1, sizeof(*k1->phy), GFP_KERNEL); -+ if (!k1->phy) -+ return -ENOMEM; -+ -+ k1->phy[0] = phy; -+ k1->phy_count = 1; - - return 0; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0412-UPSTREAM-riscv-Add-build-salt-to-the-vDSO.patch b/SPECS/linux-lts-kmhv2/0412-UPSTREAM-riscv-Add-build-salt-to-the-vDSO.patch new file mode 100644 index 0000000000..5bca6d4e2a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0412-UPSTREAM-riscv-Add-build-salt-to-the-vDSO.patch @@ -0,0 +1,38 @@ +From bcf4bd53a95abd61e8023377edf74cada143466b Mon Sep 17 00:00:00 2001 +From: Bastian Blank +Date: Thu, 18 Jun 2026 18:12:30 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: Add build salt to the vDSO + +The vDSO needs to have a unique build id in a similar manner +to the kernel and modules. Use the build salt macro. + +Signed-off-by: Bastian Blank +Reviewed-by: Nam Cao +Link: https://patch.msgid.link/ajQY7n0an0YwQ--j@steamhammer.waldi.eu.org +Signed-off-by: Paul Walmsley +(cherry picked from commit c8c5a7835f5c9e34c8a15190519a2cc9ecb9b5b5) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/vdso/note.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/kernel/vdso/note.S b/arch/riscv/kernel/vdso/note.S +index 2a956c942211..f42c7ad4f564 100644 +--- a/arch/riscv/kernel/vdso/note.S ++++ b/arch/riscv/kernel/vdso/note.S +@@ -4,9 +4,12 @@ + * Here we can supply some information useful to userland. + */ + ++#include + #include + #include + + ELFNOTE_START(Linux, 0, "a") + .long LINUX_VERSION_CODE + ELFNOTE_END ++ ++BUILD_SALT +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch deleted file mode 100644 index d0085e05ec..0000000000 --- a/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e1caa735029246df2abdcf416ccc274ca3ff53d5 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:38 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent - for MSI handle check - -The IMSIC device on RISC-V based system does not require ID -remapping for MSI. So this device only needs "msi-parent" -property for IMSIC-based SoC, and the "msi-map" is not a -necessary property. - -Add new condition for MSI handling on IMSIC based SoC. - -Signed-off-by: Inochi Amaoto -Acked-by: Rob Herring (Arm) -Link: https://lore.kernel.org/r/20260517014841.254085-4-inochiama@gmail.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -index b3216141881c..91bbbc8924f6 100644 ---- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -@@ -27,8 +27,11 @@ allOf: - - $ref: /schemas/pci/snps,dw-pcie-common.yaml# - - if: - not: -- required: -- - msi-map -+ anyOf: -+ - required: -+ - msi-map -+ - required: -+ - msi-parent - then: - properties: - interrupt-names: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0413-UPSTREAM-riscv-probes-save-original-sp-in-rethook-tr.patch b/SPECS/linux-lts-kmhv2/0413-UPSTREAM-riscv-probes-save-original-sp-in-rethook-tr.patch new file mode 100644 index 0000000000..cc9841a9c2 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0413-UPSTREAM-riscv-probes-save-original-sp-in-rethook-tr.patch @@ -0,0 +1,62 @@ +From 27f7ea28b3ba5ec4ea6a6cdbf6e2919bc10f0279 Mon Sep 17 00:00:00 2001 +From: Martin Kaiser +Date: Tue, 30 Jun 2026 21:40:03 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: probes: save original sp in rethook + trampoline + +Reading a word from the stack in a kretprobe crashes a risc-v kernel. + +$ cd /sys/kernel/tracing/ +$ echo 'r n_tty_write $stack0' > dynamic_events +$ echo 1 > events/kprobes/enable +Unable to handle kernel paging request at virtual address 0000000200000128 +... +[] regs_get_kernel_stack_nth+0x26/0x38 +[] process_fetch_insn+0x3ee/0x760 +[] kretprobe_trace_func+0x116/0x1f0 +[] kretprobe_dispatcher+0x4a/0x58 +[] kretprobe_rethook_handler+0x5e/0x90 +[] rethook_trampoline_handler+0x70/0x108 +[] arch_rethook_trampoline_callback+0x12/0x1c +[] arch_rethook_trampoline+0x48/0x94 +[] tty_write+0x1a/0x30 + +In regs_get_kernel_stack_nth, regs->sp contains an arbitrary value. + +arch_rethook_trampoline saves the registers from the probed function in a +struct pt_regs. sp is not saved. Instead, sp is decremented for +arch_rethook_trampoline's local stack. + +Fix this crash and save the original sp along with the other registers. +Use a0 as a temporary register, it is overwritten anyway. + +Cc: stable@vger.kernel.org +Fixes: c22b0bcb1dd02 ("riscv: Add kprobes supported") +Signed-off-by: Martin Kaiser +Acked-by: Masami Hiramatsu (Google) +Link: https://patch.msgid.link/20260630194010.1824039-1-martin@kaiser.cx +[pjw@kernel.org: added Fixes tag; cc'ed stable] +Signed-off-by: Paul Walmsley +(cherry picked from commit bc7b086a45521a986a49045907f017e3e46c763e) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/probes/rethook_trampoline.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/kernel/probes/rethook_trampoline.S b/arch/riscv/kernel/probes/rethook_trampoline.S +index f2cd83d9b0f0..c3aa8d8cf5af 100644 +--- a/arch/riscv/kernel/probes/rethook_trampoline.S ++++ b/arch/riscv/kernel/probes/rethook_trampoline.S +@@ -41,6 +41,9 @@ + REG_S x29, PT_T4(sp) + REG_S x30, PT_T5(sp) + REG_S x31, PT_T6(sp) ++ /* save original sp */ ++ addi a0, sp, PT_SIZE_ON_STACK ++ REG_S a0, PT_SP(sp) + .endm + + .macro restore_all_base_regs +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch deleted file mode 100644 index ce7568b3bb..0000000000 --- a/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch +++ /dev/null @@ -1,162 +0,0 @@ -From f9aab33c4cd724380b176901c11e9b2d5dbe7b6f Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:39 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit - K3 PCIe host controller - -Add binding support for the PCIe controller on the SpacemiT K3 SoC. -This controller is almost a standard Synopsys DesignWare PCIe IP, -with some extra link and reset state control. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-5-inochiama@gmail.com -Signed-off-by: Han Gao ---- - .../bindings/pci/spacemit,k3-pcie-host.yaml | 135 ++++++++++++++++++ - 1 file changed, 135 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml - -diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml -new file mode 100644 -index 000000000000..46147a37a9ce ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml -@@ -0,0 +1,135 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K3 PCI Express Host Controller -+ -+maintainers: -+ - Inochi Amaoto -+ -+description: -+ The SpacemiT K3 SoC PCIe host controller is based on the Synopsys -+ DesignWare PCIe IP. The controller uses the external MSI interrupt -+ controller. -+ -+allOf: -+ - $ref: /schemas/pci/pci-host-bridge.yaml# -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k3-pcie -+ -+ reg: -+ items: -+ - description: DesignWare PCIe registers -+ - description: Data Bus Interface (DBI) shadow registers -+ - description: ATU address space -+ - description: PCIe configuration space -+ - description: Link control registers -+ -+ reg-names: -+ items: -+ - const: dbi -+ - const: dbi2 -+ - const: atu -+ - const: config -+ - const: link -+ -+ clocks: -+ items: -+ - description: DWC PCIe Data Bus Interface (DBI) clock -+ - description: DWC PCIe application AXI-bus master interface clock -+ - description: DWC PCIe application AXI-bus slave interface clock -+ -+ clock-names: -+ items: -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ resets: -+ items: -+ - description: DWC PCIe Data Bus Interface (DBI) reset -+ - description: DWC PCIe application AXI-bus master interface reset -+ - description: DWC PCIe application AXI-bus slave interface reset -+ -+ reset-names: -+ items: -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ msi-parent: true -+ -+ phys: -+ description: -+ PHY phandle from the Combo PHY, the lane number does not depends -+ on this, since the number of lanes provided by Combo PHY can be -+ 1 or 2. -+ minItems: 1 -+ maxItems: 6 -+ -+ phy-names: -+ minItems: 1 -+ maxItems: 6 -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ description: -+ A phandle that refers to the APMU system controller, whose regmap is -+ used in managing resets and link state, along with and offset of its -+ reset control register. -+ items: -+ - items: -+ - description: phandle to APMU system controller -+ - description: register offset -+ -+required: -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - msi-parent -+ - spacemit,apmu -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu 89>, -+ <&syscon_apmu 56>, -+ <&syscon_apmu 57>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu 76>, -+ <&syscon_apmu 78>, -+ <&syscon_apmu 77>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ }; -+ }; -+ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0414-UPSTREAM-ACPI-RIMT-Only-defer-the-IOMMU-configuratio.patch b/SPECS/linux-lts-kmhv2/0414-UPSTREAM-ACPI-RIMT-Only-defer-the-IOMMU-configuratio.patch new file mode 100644 index 0000000000..cb693a734d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0414-UPSTREAM-ACPI-RIMT-Only-defer-the-IOMMU-configuratio.patch @@ -0,0 +1,54 @@ +From 0cec38fef3db4241a48d39e7b155ef7372fb168a Mon Sep 17 00:00:00 2001 +From: Yicong Yang +Date: Thu, 25 Jun 2026 17:47:02 +0800 +Subject: [RUYI PATCH] UPSTREAM: ACPI: RIMT: Only defer the IOMMU configuration + in init stage + +The IOMMU configuration will be deferred if the IOMMU driver +isn't probed by the time. Make this deferral only in the +initialization stage with driver_deferred_probe_check_state(). +Otherwise the devices depends on IOMMU will be deferred forever +in case the IOMMU device probe failed or it doesn't appear in +the ACPI namespace. + +Fixes: 8f7729552582 ("ACPI: RISC-V: Add support for RIMT") +Signed-off-by: Yicong Yang +Link: https://patch.msgid.link/20260625094702.11558-1-yang.yicong@picoheart.com +[pjw@kernel.org: added Fixes line] +Signed-off-by: Paul Walmsley +(cherry picked from commit b8f62414fa05144924257db283c5c35f74d21121) +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/rimt.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c +index 8eaa8731bddd..4c0962e68c94 100644 +--- a/drivers/acpi/riscv/rimt.c ++++ b/drivers/acpi/riscv/rimt.c +@@ -9,6 +9,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -257,11 +258,11 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 + rimt_fwnode = rimt_get_fwnode(node); + + /* +- * The IOMMU drivers may not be probed yet. +- * Defer the IOMMU configuration ++ * The IOMMU drivers may not be probed yet. Defer the IOMMU ++ * configuration if it's still in initialization stage. + */ + if (!rimt_fwnode) +- return -EPROBE_DEFER; ++ return driver_deferred_probe_check_state(dev); + + /* + * EPROBE_DEFER ensures IOMMU is probed before the devices that +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch deleted file mode 100644 index 66e63181b2..0000000000 --- a/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch +++ /dev/null @@ -1,258 +0,0 @@ -From 28a3c6b229dbe4b76f568ab83a3d0405809c7f1b Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:40 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host - controller support - -The PCIe controller on Spacemit K3 is almost a standard Synopsys -DesignWare PCIe IP with extra link and reset control. Unlike -the PCIe controller on K1, this controller supports external MSI -interrupt controller and can use multiple PHYs at the same time. - -Add driver to support PCIe controller on Spacemit K3 PCIe. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-6-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/Kconfig | 4 +- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 169 ++++++++++++++++++ - 2 files changed, 171 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig -index 5e0656eea718..bb3c32e64c98 100644 ---- a/drivers/pci/controller/dwc/Kconfig -+++ b/drivers/pci/controller/dwc/Kconfig -@@ -417,7 +417,7 @@ config PCIE_SOPHGO_DW - Sophgo SoCs. - - config PCIE_SPACEMIT_K1 -- tristate "SpacemiT K1 PCIe controller (host mode)" -+ tristate "SpacemiT K1/K3 PCIe controller (host mode)" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on HAS_IOMEM - select PCIE_DW_HOST -@@ -425,7 +425,7 @@ config PCIE_SPACEMIT_K1 - default ARCH_SPACEMIT - help - Enables support for the DesignWare based PCIe controller in -- the SpacemiT K1 SoC operating in host mode. Three controllers -+ the SpacemiT K1/K3 SoC operating in host mode. Three controllers - are available on the K1 SoC; the first of these shares a PHY - with a USB 3.0 host controller (one or the other can be used). - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index 7f6f1df31cd8..7854d26220a9 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -23,6 +23,7 @@ - - #define PCI_VENDOR_ID_SPACEMIT 0x201f - #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 - - /* Offsets and field definitions for link management registers */ - #define K1_PHY_AHB_IRQ_EN 0x0000 -@@ -32,8 +33,20 @@ - #define SMLH_LINK_UP BIT(1) - #define RDLH_LINK_UP BIT(12) - -+#define INTR_STATUS 0x0010 -+ - #define INTR_ENABLE 0x0014 - #define MSI_CTRL_INT BIT(11) -+#define RDLH_LINK_UP_INT BIT(20) -+ -+#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 -+ -+#define K3_ADDR_INTR_STATUS1 0x0018 -+ -+#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) -+#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf -+ -+#define K3_MAX_PHY_NUMBER 6 - - /* Some controls require APMU regmap access */ - #define SYSCON_APMU "spacemit,apmu" -@@ -48,6 +61,9 @@ - - #define PCIE_CONTROL_LOGIC 0x0004 - #define PCIE_SOFT_RESET BIT(0) -+#define PCIE_PERSTN_OE BIT(24) -+#define PCIE_PERSTN_OUT BIT(25) -+#define PCIE_IGNORE_PERSTN BIT(31) - - struct k1_pcie { - struct dw_pcie pci; -@@ -262,6 +278,152 @@ static const struct dw_pcie_ops k1_pcie_ops = { - .stop_link = k1_pcie_stop_link, - }; - -+static int k3_pcie_enable_phy(struct k1_pcie *pcie) -+{ -+ int i, ret; -+ -+ for (i = 0; i < pcie->phy_count; i++) { -+ ret = phy_init(pcie->phy[i]); -+ if (ret) -+ goto err_phy; -+ } -+ -+ return 0; -+ -+err_phy: -+ while (--i >= 0) -+ phy_exit(pcie->phy[i]); -+ -+ return ret; -+} -+ -+static int k3_pcie_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ struct k1_pcie *k1 = to_k1_pcie(pci); -+ u32 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; -+ u32 val; -+ int ret; -+ -+ regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); -+ -+ k1_pcie_toggle_soft_reset(k1); -+ -+ ret = k1_pcie_enable_resources(k1); -+ if (ret) -+ return ret; -+ -+ regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); -+ regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); -+ -+ ret = k3_pcie_enable_phy(k1); -+ if (ret) { -+ k1_pcie_disable_resources(k1); -+ return ret; -+ } -+ -+ /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ -+ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, -+ PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); -+ usleep_range(1000, 2000); -+ regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); -+ -+ msleep(PCIE_T_PVPERL_MS); -+ -+ /* -+ * Put the controller in root complex mode, and indicate that -+ * Vaux (3.3v) is present. -+ */ -+ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, -+ PCIE_PERSTN_OUT | PCIE_PERSTN_OE); -+ -+ val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); -+ val = u32_replace_bits(val, GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE, -+ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); -+ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); -+ -+ dw_pcie_dbi_ro_wr_en(pci); -+ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); -+ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K3); -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ /* Finally, as a workaround, disable ASPM L1 */ -+ k1_pcie_disable_aspm_l1(k1); -+ -+ return 0; -+} -+ -+static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ u32 val; -+ -+ dw_pcie_dbi_ro_wr_en(pci); -+ -+ val = dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); -+ val |= u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, -+ K3_CACHE_MSTR_AWCACHE_MODE); -+ dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); -+ -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ return 0; -+} -+ -+static const struct dw_pcie_host_ops k3_pcie_host_ops = { -+ .init = k3_pcie_init, -+ .deinit = k1_pcie_deinit, -+ .msi_init = k3_pcie_msi_host_init, -+}; -+ -+static const struct dw_pcie_ops k3_pcie_ops = { -+ .link_up = k1_pcie_link_up, -+ .start_link = k1_pcie_start_link, -+ .stop_link = k1_pcie_stop_link, -+}; -+ -+static void k3_pcie_clear_irq_status(struct k1_pcie *k1, -+ u32 *status0, u32 *status1, u32 *status2) -+{ -+ *status0 = readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); -+ *status1 = readl_relaxed(k1->link + INTR_STATUS); -+ *status2 = readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); -+ -+ writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); -+ writel_relaxed(*status1, k1->link + INTR_STATUS); -+ writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); -+} -+ -+static int k3_pcie_parse_port(struct k1_pcie *k1) -+{ -+ struct device *dev = k1->pci.dev; -+ u32 status0, status1, status2; -+ int i; -+ -+ k1->phy = devm_kmalloc_array(dev, K3_MAX_PHY_NUMBER, sizeof(*k1->phy), -+ GFP_KERNEL); -+ if (!k1->phy) -+ return -ENOMEM; -+ -+ for (i = 0; i < K3_MAX_PHY_NUMBER; i++) { -+ k1->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); -+ if (IS_ERR(k1->phy[i])) { -+ if (PTR_ERR(k1->phy[i]) == -ENODEV) -+ break; -+ -+ return PTR_ERR(k1->phy[i]); -+ } -+ } -+ -+ k1->phy_count = i; -+ if (k1->phy_count == 0) -+ return -EINVAL; -+ -+ k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); -+ -+ return 0; -+} -+ - static int k1_pcie_parse_port(struct k1_pcie *k1) - { - struct device *dev = k1->pci.dev; -@@ -363,8 +525,15 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { - .parse_port = k1_pcie_parse_port, - }; - -+static const struct k1_pcie_device_data k3_pcie_device_data = { -+ .host_ops = &k3_pcie_host_ops, -+ .ops = &k3_pcie_ops, -+ .parse_port = k3_pcie_parse_port, -+}; -+ - static const struct of_device_id k1_pcie_of_match_table[] = { - { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, -+ { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, - { } - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0415-UPSTREAM-phy-move-spacemit-pcie-driver-to-its-subfol.patch b/SPECS/linux-lts-kmhv2/0415-UPSTREAM-phy-move-spacemit-pcie-driver-to-its-subfol.patch new file mode 100644 index 0000000000..43da71f843 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0415-UPSTREAM-phy-move-spacemit-pcie-driver-to-its-subfol.patch @@ -0,0 +1,100 @@ +From 96b3e72a2b88678a06248bfb352a95baaa87b976 Mon Sep 17 00:00:00 2001 +From: Vinod Koul +Date: Mon, 23 Feb 2026 12:12:39 +0530 +Subject: [RUYI PATCH] UPSTREAM: phy: move spacemit pcie driver to its + subfolder + +Commit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller") +created spacemit subfolder with usb driver while commit 57e920b92724 +("phy: spacemit: Introduce PCIe/combo PHY") added pcie driver in phy +folder. Move latter into spacemit subfolder and rename file to +phy-k1-pcie.c + +Reviewed-by: Alex Elder +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260223064240.386617-1-vkoul@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit 75fb1a33f9ac4c9730e61bb19aaaab02023a99b2) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 12 ------------ + drivers/phy/Makefile | 1 - + drivers/phy/spacemit/Kconfig | 12 ++++++++++++ + drivers/phy/spacemit/Makefile | 1 + + .../phy-k1-pcie.c} | 0 + 5 files changed, 13 insertions(+), 13 deletions(-) + rename drivers/phy/{phy-spacemit-k1-pcie.c => spacemit/phy-k1-pcie.c} (100%) + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 88ea9af445b1..c39b40876177 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -101,18 +101,6 @@ config PHY_NXP_PTN3222 + schemes. It supports all three USB 2.0 data rates: Low Speed, Full + Speed and High Speed. + +-config PHY_SPACEMIT_K1_PCIE +- tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" +- depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on COMMON_CLK +- depends on HAS_IOMEM +- depends on OF +- select GENERIC_PHY +- default ARCH_SPACEMIT +- help +- Enable support for the PCIe and USB 3 combo PHY and two +- PCIe-only PHYs used in the SpacemiT K1 SoC. +- + source "drivers/phy/allwinner/Kconfig" + source "drivers/phy/amlogic/Kconfig" + source "drivers/phy/broadcom/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index 950dd4f14372..e1aea28dbf6b 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -13,7 +13,6 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o + obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o + obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o + obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o +-obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o + obj-y += allwinner/ \ + amlogic/ \ + broadcom/ \ +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 0136aee2e8a2..50b0005acf66 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -2,6 +2,18 @@ + # + # Phy drivers for SpacemiT platforms + # ++config PHY_SPACEMIT_K1_PCIE ++ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on COMMON_CLK ++ depends on HAS_IOMEM ++ depends on OF ++ select GENERIC_PHY ++ default ARCH_SPACEMIT ++ help ++ Enable support for the PCIe and USB 3 combo PHY and two ++ PCIe-only PHYs used in the SpacemiT K1 SoC. ++ + config PHY_SPACEMIT_K1_USB2 + tristate "SpacemiT K1 USB 2.0 PHY support" + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index fec0b425a948..a821a21d6142 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o +diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/spacemit/phy-k1-pcie.c +similarity index 100% +rename from drivers/phy/phy-spacemit-k1-pcie.c +rename to drivers/phy/spacemit/phy-k1-pcie.c +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch deleted file mode 100644 index 80bd621ef2..0000000000 --- a/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch +++ /dev/null @@ -1,76 +0,0 @@ -From e933fb1426b50978196a70b05655d5cb7a3bcb76 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 16 May 2026 16:00:30 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable QSPI for OrangePi - RV2 - -Enable the QSPI controller and the XM25QU128C SPI NOR flash on the -OrangePi RV2 board. Add a flash partition layout from vendor UBoot. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260516080030.1736836-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ - 1 file changed, 45 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index bd40bc9011e2..0b4d4d1418e2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -290,6 +290,51 @@ &pcie2 { - status = "okay"; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck3_1v8>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x00000 0x010000>; -+ }; -+ -+ private@10000 { -+ reg = <0x10000 0x010000>; -+ }; -+ -+ fsbl@20000 { -+ reg = <0x20000 0x040000>; -+ }; -+ -+ env@60000 { -+ reg = <0x60000 0x010000>; -+ }; -+ -+ opensbi@70000 { -+ reg = <0x70000 0x030000>; -+ }; -+ -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0416-UPSTREAM-scsi-ufs-dt-bindings-amd-versal2-Add-UFS-Ho.patch b/SPECS/linux-lts-kmhv2/0416-UPSTREAM-scsi-ufs-dt-bindings-amd-versal2-Add-UFS-Ho.patch new file mode 100644 index 0000000000..1de9e1fc38 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0416-UPSTREAM-scsi-ufs-dt-bindings-amd-versal2-Add-UFS-Ho.patch @@ -0,0 +1,93 @@ +From 717427296655d4abcf6d70e8ca8c7a7403bb684d Mon Sep 17 00:00:00 2001 +From: Sai Krishna Potthuri +Date: Tue, 21 Oct 2025 17:00:00 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: dt-bindings: amd-versal2: Add UFS + Host Controller for AMD Versal Gen 2 SoC + +Add devicetree document for UFS Host Controller on AMD Versal Gen 2 SoC. +This includes clocks and clock-names as mandated by UFS common bindings. + +Signed-off-by: Sai Krishna Potthuri +Co-developed-by: Ajay Neeli +Signed-off-by: Ajay Neeli +Reviewed-by: Conor Dooley +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-2-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 754c6f539effa8ad332e305e34665849638fa40f) +Signed-off-by: Han Gao +--- + .../bindings/ufs/amd,versal2-ufs.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml + +diff --git a/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml +new file mode 100644 +index 000000000000..c00ec342d574 +--- /dev/null ++++ b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/ufs/amd,versal2-ufs.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: AMD Versal Gen 2 UFS Host Controller ++ ++maintainers: ++ - Sai Krishna Potthuri ++ ++allOf: ++ - $ref: ufs-common.yaml ++ ++properties: ++ compatible: ++ const: amd,versal2-ufs ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ clock-names: ++ items: ++ - const: core ++ ++ power-domains: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 2 ++ ++ reset-names: ++ items: ++ - const: host ++ - const: phy ++ ++required: ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ufs@f10b0000 { ++ compatible = "amd,versal2-ufs"; ++ reg = <0xf10b0000 0x1000>; ++ clocks = <&ufs_core_clk>; ++ clock-names = "core"; ++ resets = <&scmi_reset 4>, <&scmi_reset 35>; ++ reset-names = "host", "phy"; ++ interrupts = ; ++ freq-table-hz = <0 0>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch deleted file mode 100644 index 7ce6604711..0000000000 --- a/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 9ffbd34c853c426d82f3daf0bb7512fc1b08d611 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 02:58:36 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock - -According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus -clock enable bit was wrongly swapped, the correct one should be: - -Register : APMU_USB_CLK_RES_CTRL -bit[1] : usb2_port_bus_clk_en -bit[0] : usb2_port_ahb_rstn - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Reported-by: Junzhong Pan -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index cb0c4277f72a..03de04144963 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -777,7 +777,7 @@ static const struct clk_parent_data sdh2_parents[] = { - CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, - BIT(11), 5, 3, BIT(4), 0); - --CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); - CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); - CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); - CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0417-UPSTREAM-scsi-firmware-xilinx-Add-support-for-secure.patch b/SPECS/linux-lts-kmhv2/0417-UPSTREAM-scsi-firmware-xilinx-Add-support-for-secure.patch new file mode 100644 index 0000000000..379e89467c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0417-UPSTREAM-scsi-firmware-xilinx-Add-support-for-secure.patch @@ -0,0 +1,137 @@ +From 37ad30b40e9c272af82adac50f530c09b367a610 Mon Sep 17 00:00:00 2001 +From: Izhar Ameer Shaikh +Date: Tue, 21 Oct 2025 17:00:01 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: firmware: xilinx: Add support for secure + read/write ioctl interface + +Add support for a generic ioctl read/write interface using which users +can request firmware to perform read/write operations on a protected and +secure address space. + +The functionality is introduced through the means of two new IOCTL IDs +which extend the existing PM_IOCTL EEMI API: + + - IOCTL_READ_REG + - IOCTL_MASK_WRITE_REG + +The caller only passes the node id of the given device and an offset. +The base address is not exposed to the caller and internally retrieved +by the firmware. Firmware will enforce an access policy on the incoming +read/write request. + +Signed-off-by: Izhar Ameer Shaikh +Reviewed-by: Tanmay Shah +Signed-off-by: Radhey Shyam Pandey +Signed-off-by: Ajay Neeli +Acked-by: Senthil Nathan Thangaraj +Acked-by: Michal Simek +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-3-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 00b3e8480be7a49203594bd1fdb4fd46f3b69d59) +Signed-off-by: Han Gao +--- + drivers/firmware/xilinx/zynqmp.c | 46 ++++++++++++++++++++++++++++ + include/linux/firmware/xlnx-zynqmp.h | 15 +++++++++ + 2 files changed, 61 insertions(+) + +diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c +index 02da3e48bc8f..b7cd0eca9eaa 100644 +--- a/drivers/firmware/xilinx/zynqmp.c ++++ b/drivers/firmware/xilinx/zynqmp.c +@@ -1616,6 +1616,52 @@ int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, + return zynqmp_pm_invoke_fn(PM_IOCTL, payload, 3, 0, IOCTL_GET_FEATURE_CONFIG, id); + } + ++/** ++ * zynqmp_pm_sec_read_reg - PM call to securely read from given offset ++ * of the node ++ * @node_id: Node Id of the device ++ * @offset: Offset to be used (20-bit) ++ * @ret_value: Output data read from the given offset after ++ * firmware access policy is successfully enforced ++ * ++ * Return: Returns 0 on success or error value on failure ++ */ ++int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value) ++{ ++ u32 ret_payload[PAYLOAD_ARG_CNT]; ++ u32 count = 1; ++ int ret; ++ ++ if (!ret_value) ++ return -EINVAL; ++ ++ ret = zynqmp_pm_invoke_fn(PM_IOCTL, ret_payload, 4, node_id, IOCTL_READ_REG, ++ offset, count); ++ ++ *ret_value = ret_payload[1]; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_sec_read_reg); ++ ++/** ++ * zynqmp_pm_sec_mask_write_reg - PM call to securely write to given offset ++ * of the node ++ * @node_id: Node Id of the device ++ * @offset: Offset to be used (20-bit) ++ * @mask: Mask to be used ++ * @value: Value to be written ++ * ++ * Return: Returns 0 on success or error value on failure ++ */ ++int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, u32 mask, ++ u32 value) ++{ ++ return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 5, node_id, IOCTL_MASK_WRITE_REG, ++ offset, mask, value); ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_sec_mask_write_reg); ++ + /** + * zynqmp_pm_set_sd_config - PM call to set value of SD config registers + * @node: SD node ID +diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h +index ae48d619c4e0..b161f37de5cc 100644 +--- a/include/linux/firmware/xlnx-zynqmp.h ++++ b/include/linux/firmware/xlnx-zynqmp.h +@@ -241,6 +241,7 @@ enum pm_ioctl_id { + IOCTL_GET_FEATURE_CONFIG = 27, + /* IOCTL for Secure Read/Write Interface */ + IOCTL_READ_REG = 28, ++ IOCTL_MASK_WRITE_REG = 29, + /* Dynamic SD/GEM configuration */ + IOCTL_SET_SD_CONFIG = 30, + IOCTL_SET_GEM_CONFIG = 31, +@@ -619,6 +620,9 @@ int zynqmp_pm_feature(const u32 api_id); + int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); + int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); + int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); ++int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value); ++int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, ++ u32 mask, u32 value); + int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); + int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack); +@@ -916,6 +920,17 @@ static inline int zynqmp_pm_request_wake(const u32 node, + return -ENODEV; + } + ++static inline int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, ++ u32 mask, u32 value) ++{ ++ return -ENODEV; ++} ++ + static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) + { + return -ENODEV; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch deleted file mode 100644 index ef6c5cfcb2..0000000000 --- a/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d420aa127fcbe63635453a4103d4d013e9027703 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 02:58:37 +0000 -Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset - -According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus -clock enable bit was wrongly swapped, the correct one should be: - -Register : APMU_USB_CLK_RES_CTRL -bit[1] : usb2_port_bus_clk_en -bit[0] : usb2_port_ahb_rstn - -Fixes: a0e0c2f8c5f3 ("reset: spacemit: k3: Decouple composite reset lines") -Reported-by: Junzhong Pan -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/reset-spacemit-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -index 9841f5e057b2..2e87f320cf11 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k3.c -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -- [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), - [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), - [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0418-UPSTREAM-scsi-firmware-xilinx-Add-APIs-for-UFS-PHY-i.patch b/SPECS/linux-lts-kmhv2/0418-UPSTREAM-scsi-firmware-xilinx-Add-APIs-for-UFS-PHY-i.patch new file mode 100644 index 0000000000..660e27b701 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0418-UPSTREAM-scsi-firmware-xilinx-Add-APIs-for-UFS-PHY-i.patch @@ -0,0 +1,225 @@ +From 84a63c91f60633a8bea67f024d5cf7fe363b5346 Mon Sep 17 00:00:00 2001 +From: Ajay Neeli +Date: Tue, 21 Oct 2025 17:00:02 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: firmware: xilinx: Add APIs for UFS PHY + initialization + + - Add APIs for UFS PHY initialization. + + - Verify M-PHY TX-RX configuration readiness. + + - Confirm SRAM initialization and Set SRAM bypass. + + - Retrieve UFS calibration values. + +Signed-off-by: Ajay Neeli +Acked-by: Senthil Nathan Thangaraj +Acked-by: Michal Simek +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-4-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 0e4d26f79a74bc633846a27a9a20d52217c108dc) +Signed-off-by: Han Gao +--- + drivers/firmware/xilinx/Makefile | 2 +- + drivers/firmware/xilinx/zynqmp-ufs.c | 118 +++++++++++++++++++++++ + include/linux/firmware/xlnx-zynqmp-ufs.h | 38 ++++++++ + include/linux/firmware/xlnx-zynqmp.h | 1 + + 4 files changed, 158 insertions(+), 1 deletion(-) + create mode 100644 drivers/firmware/xilinx/zynqmp-ufs.c + create mode 100644 include/linux/firmware/xlnx-zynqmp-ufs.h + +diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile +index 875a53703c82..70f8f02f14a3 100644 +--- a/drivers/firmware/xilinx/Makefile ++++ b/drivers/firmware/xilinx/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + # Makefile for Xilinx firmwares + +-obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o ++obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-ufs.o + obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o +diff --git a/drivers/firmware/xilinx/zynqmp-ufs.c b/drivers/firmware/xilinx/zynqmp-ufs.c +new file mode 100644 +index 000000000000..85da8a822f3a +--- /dev/null ++++ b/drivers/firmware/xilinx/zynqmp-ufs.c +@@ -0,0 +1,118 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Firmware Layer for UFS APIs ++ * ++ * Copyright (C) 2025 Advanced Micro Devices, Inc. ++ */ ++ ++#include ++#include ++ ++/* Register Node IDs */ ++#define PM_REGNODE_PMC_IOU_SLCR 0x30000002 /* PMC IOU SLCR */ ++#define PM_REGNODE_EFUSE_CACHE 0x30000003 /* EFUSE Cache */ ++ ++/* Register Offsets for PMC IOU SLCR */ ++#define SRAM_CSR_OFFSET 0x104C /* SRAM Control and Status */ ++#define TXRX_CFGRDY_OFFSET 0x1054 /* M-PHY TX-RX Config ready */ ++ ++/* Masks for SRAM Control and Status Register */ ++#define SRAM_CSR_INIT_DONE_MASK BIT(0) /* SRAM initialization done */ ++#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) /* SRAM External load done */ ++#define SRAM_CSR_BYPASS_MASK BIT(2) /* Bypass SRAM interface */ ++ ++/* Mask to check M-PHY TX-RX configuration readiness */ ++#define TX_RX_CFG_RDY_MASK GENMASK(3, 0) ++ ++/* Register Offsets for EFUSE Cache */ ++#define UFS_CAL_1_OFFSET 0xBE8 /* UFS Calibration Value */ ++ ++/** ++ * zynqmp_pm_is_mphy_tx_rx_config_ready - check M-PHY TX-RX config readiness ++ * @is_ready: Store output status (true/false) ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) ++{ ++ u32 regval; ++ int ret; ++ ++ if (!is_ready) ++ return -EINVAL; ++ ++ ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, TXRX_CFGRDY_OFFSET, ®val); ++ if (ret) ++ return ret; ++ ++ regval &= TX_RX_CFG_RDY_MASK; ++ if (regval) ++ *is_ready = true; ++ else ++ *is_ready = false; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready); ++ ++/** ++ * zynqmp_pm_is_sram_init_done - check SRAM initialization ++ * @is_done: Store output status (true/false) ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_is_sram_init_done(bool *is_done) ++{ ++ u32 regval; ++ int ret; ++ ++ if (!is_done) ++ return -EINVAL; ++ ++ ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, ®val); ++ if (ret) ++ return ret; ++ ++ regval &= SRAM_CSR_INIT_DONE_MASK; ++ if (regval) ++ *is_done = true; ++ else ++ *is_done = false; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_is_sram_init_done); ++ ++/** ++ * zynqmp_pm_set_sram_bypass - Set SRAM bypass Control ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_set_sram_bypass(void) ++{ ++ u32 sram_csr; ++ int ret; ++ ++ ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, &sram_csr); ++ if (ret) ++ return ret; ++ ++ sram_csr &= ~SRAM_CSR_EXT_LD_DONE_MASK; ++ sram_csr |= SRAM_CSR_BYPASS_MASK; ++ ++ return zynqmp_pm_sec_mask_write_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, ++ GENMASK(2, 1), sram_csr); ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_set_sram_bypass); ++ ++/** ++ * zynqmp_pm_get_ufs_calibration_values - Read UFS calibration values ++ * @val: Store the calibration value ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_get_ufs_calibration_values(u32 *val) ++{ ++ return zynqmp_pm_sec_read_reg(PM_REGNODE_EFUSE_CACHE, UFS_CAL_1_OFFSET, val); ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_get_ufs_calibration_values); +diff --git a/include/linux/firmware/xlnx-zynqmp-ufs.h b/include/linux/firmware/xlnx-zynqmp-ufs.h +new file mode 100644 +index 000000000000..d3538dd5822a +--- /dev/null ++++ b/include/linux/firmware/xlnx-zynqmp-ufs.h +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Firmware layer for UFS APIs. ++ * ++ * Copyright (c) 2025 Advanced Micro Devices, Inc. ++ */ ++ ++#ifndef __FIRMWARE_XLNX_ZYNQMP_UFS_H__ ++#define __FIRMWARE_XLNX_ZYNQMP_UFS_H__ ++ ++#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) ++int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready); ++int zynqmp_pm_is_sram_init_done(bool *is_done); ++int zynqmp_pm_set_sram_bypass(void); ++int zynqmp_pm_get_ufs_calibration_values(u32 *val); ++#else ++static inline int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_is_sram_init_done(bool *is_done) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_set_sram_bypass(void) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_get_ufs_calibration_values(u32 *val) ++{ ++ return -ENODEV; ++} ++#endif ++ ++#endif /* __FIRMWARE_XLNX_ZYNQMP_UFS_H__ */ +diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h +index b161f37de5cc..784d5920b4cd 100644 +--- a/include/linux/firmware/xlnx-zynqmp.h ++++ b/include/linux/firmware/xlnx-zynqmp.h +@@ -16,6 +16,7 @@ + #include + + #include ++#include + + #define ZYNQMP_PM_VERSION_MAJOR 1 + #define ZYNQMP_PM_VERSION_MINOR 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch deleted file mode 100644 index 05b9ee6eb7..0000000000 --- a/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch +++ /dev/null @@ -1,37 +0,0 @@ -From cf3c64c0e469dac06db3606b299ff2b6be12345c Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 20:58:16 +0000 -Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power - settings - -SpacemiT K3 SoC support dual-voltage I/O power domain, while initially -configure to 3.3v, and need to access register from APBC space to switch -to 1.8v domain. - -Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken -ethernet driver. - -Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") -Reported-by: Han Gao -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index a336de5f3d94..809067d6383c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -1035,6 +1035,7 @@ pinctrl: pinctrl@d401e000 { - clocks = <&syscon_apbc CLK_APBC_AIB>, - <&syscon_apbc CLK_APBC_AIB_BUS>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - }; - - uart10: serial@d401f000 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0419-UPSTREAM-scsi-ufs-amd-versal2-Add-UFS-support-for-AM.patch b/SPECS/linux-lts-kmhv2/0419-UPSTREAM-scsi-ufs-amd-versal2-Add-UFS-support-for-AM.patch new file mode 100644 index 0000000000..df1c511cd8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0419-UPSTREAM-scsi-ufs-amd-versal2-Add-UFS-support-for-AM.patch @@ -0,0 +1,719 @@ +From 52e01c14272ec6eb93bb1f9b435f00c1918c7043 Mon Sep 17 00:00:00 2001 +From: Sai Krishna Potthuri +Date: Tue, 21 Oct 2025 17:00:03 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: amd-versal2: Add UFS support for + AMD Versal Gen 2 SoC + +Add support for the UFS host controller on the AMD Versal Gen 2 SoC, +built on the Synopsys DWC UFS architecture, using the UFSHCD DWC and +UFSHCD platform driver. This controller requires specific configurations +like M-PHY/RMMI/UniPro and vendor specific registers programming before +doing the UIC_LINKSTARTUP. + +Signed-off-by: Sai Krishna Potthuri +Signed-off-by: Ajay Neeli +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-5-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 769b8b2ffded4cd880669edd83e2952efeeb27f7) +Signed-off-by: Han Gao +--- + MAINTAINERS | 7 + + drivers/ufs/host/Kconfig | 13 + + drivers/ufs/host/Makefile | 1 + + drivers/ufs/host/ufs-amd-versal2.c | 564 +++++++++++++++++++++++++++++ + drivers/ufs/host/ufshcd-dwc.h | 46 +++ + include/ufs/unipro.h | 1 + + 6 files changed, 632 insertions(+) + create mode 100644 drivers/ufs/host/ufs-amd-versal2.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 996aa3d41e95..a3bc23926943 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -26403,6 +26403,13 @@ F: Documentation/devicetree/bindings/ufs/ + F: Documentation/scsi/ufs.rst + F: drivers/ufs/core/ + ++UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER AMD VERSAL2 ++M: Sai Krishna Potthuri ++M: Ajay Neeli ++S: Maintained ++F: Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml ++F: drivers/ufs/host/ufs-amd-versal2.c ++ + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER DWC HOOKS + M: Pedro Sousa + L: linux-scsi@vger.kernel.org +diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig +index 48ee7e9b665e..964ae70e7390 100644 +--- a/drivers/ufs/host/Kconfig ++++ b/drivers/ufs/host/Kconfig +@@ -155,3 +155,16 @@ config SCSI_UFS_ROCKCHIP + + Select this if you have UFS controller on Rockchip chipset. + If unsure, say N. ++ ++config SCSI_UFS_AMD_VERSAL2 ++ tristate "AMD Versal Gen 2 UFS controller platform driver" ++ depends on SCSI_UFSHCD_PLATFORM && (ARCH_ZYNQMP || COMPILE_TEST) ++ help ++ This selects the AMD Versal Gen 2 specific additions on top of ++ the UFSHCD DWC and UFSHCD platform driver. UFS host on AMD ++ Versal Gen 2 needs some vendor specific configurations like PHY ++ and vendor specific register accesses before accessing the ++ hardware. ++ ++ Select this if you have UFS controller on AMD Versal Gen 2 SoC. ++ If unsure, say N. +diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile +index 2f97feb5db3f..65d8bb23ab7b 100644 +--- a/drivers/ufs/host/Makefile ++++ b/drivers/ufs/host/Makefile +@@ -13,3 +13,4 @@ obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o + obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o + obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o + obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o ++obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o +diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c +new file mode 100644 +index 000000000000..40543db621a1 +--- /dev/null ++++ b/drivers/ufs/host/ufs-amd-versal2.c +@@ -0,0 +1,564 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 Advanced Micro Devices, Inc. ++ * ++ * Authors: Sai Krishna Potthuri ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ufshcd-dwc.h" ++#include "ufshcd-pltfrm.h" ++#include "ufshci-dwc.h" ++ ++/* PHY modes */ ++#define UFSHCD_DWC_PHY_MODE_ROM 0 ++ ++#define MPHY_FAST_RX_AFE_CAL BIT(2) ++#define MPHY_FW_CALIB_CFG_VAL BIT(8) ++ ++#define MPHY_RX_OVRD_EN BIT(3) ++#define MPHY_RX_OVRD_VAL BIT(2) ++#define MPHY_RX_ACK_MASK BIT(0) ++ ++#define TIMEOUT_MICROSEC 1000000 ++ ++struct ufs_versal2_host { ++ struct ufs_hba *hba; ++ struct reset_control *rstc; ++ struct reset_control *rstphy; ++ u32 phy_mode; ++ unsigned long host_clk; ++ u8 attcompval0; ++ u8 attcompval1; ++ u8 ctlecompval0; ++ u8 ctlecompval1; ++}; ++ ++static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) ++{ ++ static struct ufshcd_dme_attr_val phy_write_attrs[] = { ++ { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, ++ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } ++ }; ++ ++ phy_write_attrs[0].mib_val = (u8)addr; ++ phy_write_attrs[1].mib_val = (u8)(addr >> 8); ++ phy_write_attrs[2].mib_val = (u8)val; ++ phy_write_attrs[3].mib_val = (u8)(val >> 8); ++ ++ return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); ++} ++ ++static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) ++{ ++ u32 mib_val; ++ int ret; ++ static struct ufshcd_dme_attr_val phy_read_attrs[] = { ++ { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } ++ }; ++ ++ phy_read_attrs[0].mib_val = (u8)addr; ++ phy_read_attrs[1].mib_val = (u8)(addr >> 8); ++ ++ ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); ++ if (ret) ++ return ret; ++ ++ *val = mib_val; ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); ++ if (ret) ++ return ret; ++ ++ *val |= (mib_val << 8); ++ ++ return 0; ++} ++ ++static int ufs_versal2_enable_phy(struct ufs_hba *hba) ++{ ++ u32 offset, reg; ++ int ret; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); ++ if (ret) ++ return ret; ++ ++ /* Check Tx/Rx FSM states */ ++ for (offset = 0; offset < 2; offset++) { ++ u32 time_left, mibsel; ++ ++ time_left = TIMEOUT_MICROSEC; ++ mibsel = UIC_ARG_MIB_SEL(MTX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset)); ++ do { ++ ret = ufshcd_dme_get(hba, mibsel, ®); ++ if (ret) ++ return ret; ++ ++ if (reg == TX_STATE_HIBERN8 || reg == TX_STATE_SLEEP || ++ reg == TX_STATE_LSBURST) ++ break; ++ ++ time_left--; ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Invalid Tx FSM state.\n"); ++ return -ETIMEDOUT; ++ } ++ ++ time_left = TIMEOUT_MICROSEC; ++ mibsel = UIC_ARG_MIB_SEL(MRX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset)); ++ do { ++ ret = ufshcd_dme_get(hba, mibsel, ®); ++ if (ret) ++ return ret; ++ ++ if (reg == RX_STATE_HIBERN8 || reg == RX_STATE_SLEEP || ++ reg == RX_STATE_LSBURST) ++ break; ++ ++ time_left--; ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Invalid Rx FSM state.\n"); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return 0; ++} ++ ++static int ufs_versal2_setup_phy(struct ufs_hba *hba) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ int ret; ++ u32 reg; ++ ++ /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ ++ ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FAST_RX_AFE_CAL; ++ ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FAST_RX_AFE_CAL; ++ ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); ++ if (ret) ++ return ret; ++ ++ /* Program ATT and CTLE compensation values */ ++ if (host->attcompval0) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0); ++ if (ret) ++ return ret; ++ } ++ ++ if (host->attcompval1) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1); ++ if (ret) ++ return ret; ++ } ++ ++ if (host->ctlecompval0) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0); ++ if (ret) ++ return ret; ++ } ++ ++ if (host->ctlecompval1) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1); ++ if (ret) ++ return ret; ++ } ++ ++ ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FW_CALIB_CFG_VAL; ++ ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FW_CALIB_CFG_VAL; ++ return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); ++} ++ ++static int ufs_versal2_phy_init(struct ufs_hba *hba) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ u32 time_left; ++ bool is_ready; ++ int ret; ++ static const struct ufshcd_dme_attr_val rmmi_attrs[] = { ++ { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCRCTRL), 1, DME_LOCAL }, ++ { UIC_ARG_MIB(CBC10DIRECTCONF2), 1, DME_LOCAL }, ++ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } ++ }; ++ ++ /* Wait for Tx/Rx config_rdy */ ++ time_left = TIMEOUT_MICROSEC; ++ do { ++ time_left--; ++ ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready); ++ if (ret) ++ return ret; ++ ++ if (!is_ready) ++ break; ++ ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Tx/Rx configuration signal busy.\n"); ++ return -ETIMEDOUT; ++ } ++ ++ ret = ufshcd_dwc_dme_set_attrs(hba, rmmi_attrs, ARRAY_SIZE(rmmi_attrs)); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_deassert(host->rstphy); ++ if (ret) { ++ dev_err(hba->dev, "ufsphy reset deassert failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ /* Wait for SRAM init done */ ++ time_left = TIMEOUT_MICROSEC; ++ do { ++ time_left--; ++ ret = zynqmp_pm_is_sram_init_done(&is_ready); ++ if (ret) ++ return ret; ++ ++ if (is_ready) ++ break; ++ ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "SRAM initialization failed.\n"); ++ return -ETIMEDOUT; ++ } ++ ++ ret = ufs_versal2_setup_phy(hba); ++ if (ret) ++ return ret; ++ ++ return ufs_versal2_enable_phy(hba); ++} ++ ++static int ufs_versal2_init(struct ufs_hba *hba) ++{ ++ struct ufs_versal2_host *host; ++ struct device *dev = hba->dev; ++ struct ufs_clk_info *clki; ++ int ret; ++ u32 cal; ++ ++ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ host->hba = hba; ++ ufshcd_set_variant(hba, host); ++ ++ host->phy_mode = UFSHCD_DWC_PHY_MODE_ROM; ++ ++ list_for_each_entry(clki, &hba->clk_list_head, list) { ++ if (!strcmp(clki->name, "core")) ++ host->host_clk = clk_get_rate(clki->clk); ++ } ++ ++ host->rstc = devm_reset_control_get_exclusive(dev, "host"); ++ if (IS_ERR(host->rstc)) { ++ dev_err(dev, "failed to get reset ctrl: host\n"); ++ return PTR_ERR(host->rstc); ++ } ++ ++ host->rstphy = devm_reset_control_get_exclusive(dev, "phy"); ++ if (IS_ERR(host->rstphy)) { ++ dev_err(dev, "failed to get reset ctrl: phy\n"); ++ return PTR_ERR(host->rstphy); ++ } ++ ++ ret = reset_control_assert(host->rstc); ++ if (ret) { ++ dev_err(hba->dev, "host reset assert failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_control_assert(host->rstphy); ++ if (ret) { ++ dev_err(hba->dev, "phy reset assert failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ ret = zynqmp_pm_set_sram_bypass(); ++ if (ret) { ++ dev_err(dev, "Bypass SRAM interface failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_control_deassert(host->rstc); ++ if (ret) ++ dev_err(hba->dev, "host reset deassert failed, err = %d\n", ret); ++ ++ ret = zynqmp_pm_get_ufs_calibration_values(&cal); ++ if (ret) { ++ dev_err(dev, "failed to read calibration values\n"); ++ return ret; ++ } ++ ++ host->attcompval0 = (u8)cal; ++ host->attcompval1 = (u8)(cal >> 8); ++ host->ctlecompval0 = (u8)(cal >> 16); ++ host->ctlecompval1 = (u8)(cal >> 24); ++ ++ hba->quirks |= UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING; ++ ++ return 0; ++} ++ ++static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ int ret = 0; ++ ++ if (status == PRE_CHANGE) { ++ ret = ufs_versal2_phy_init(hba); ++ if (ret) ++ dev_err(hba->dev, "Phy init failed (%d)\n", ret); ++ } ++ ++ return ret; ++} ++ ++static int ufs_versal2_link_startup_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ int ret = 0; ++ ++ switch (status) { ++ case PRE_CHANGE: ++ if (host->host_clk) ++ ufshcd_writel(hba, host->host_clk / 1000000, DWC_UFS_REG_HCLKDIV); ++ ++ break; ++ case POST_CHANGE: ++ ret = ufshcd_dwc_link_startup_notify(hba, status); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_req) ++{ ++ u32 time_left, reg, lane; ++ int ret; ++ ++ for (lane = 0; lane < activelanes; lane++) { ++ time_left = TIMEOUT_MICROSEC; ++ ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_RX_OVRD_EN; ++ if (rx_req) ++ reg |= MPHY_RX_OVRD_VAL; ++ else ++ reg &= ~MPHY_RX_OVRD_VAL; ++ ++ ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); ++ if (ret) ++ return ret; ++ ++ do { ++ ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); ++ if (ret) ++ return ret; ++ ++ reg &= MPHY_RX_ACK_MASK; ++ if (reg == rx_req) ++ break; ++ ++ time_left--; ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Invalid Rx Ack value.\n"); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return 0; ++} ++ ++static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ u32 lane, reg, rate = 0; ++ int ret = 0; ++ ++ if (status == PRE_CHANGE) { ++ memcpy(dev_req_params, dev_max_params, sizeof(struct ufs_pa_layer_attr)); ++ ++ /* If it is not a calibrated part, switch PWRMODE to SLOW_MODE */ ++ if (!host->attcompval0 && !host->attcompval1 && !host->ctlecompval0 && ++ !host->ctlecompval1) { ++ dev_req_params->pwr_rx = SLOW_MODE; ++ dev_req_params->pwr_tx = SLOW_MODE; ++ return 0; ++ } ++ ++ if (dev_req_params->pwr_rx == SLOW_MODE || dev_req_params->pwr_rx == SLOWAUTO_MODE) ++ return 0; ++ ++ if (dev_req_params->hs_rate == PA_HS_MODE_B) ++ rate = 1; ++ ++ /* Select the rate */ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), rate); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 1); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 0); ++ if (ret) ++ return ret; ++ ++ /* Remove rx_req override */ ++ for (lane = 0; lane < dev_req_params->lane_tx; lane++) { ++ ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); ++ if (ret) ++ return ret; ++ ++ reg &= ~MPHY_RX_OVRD_EN; ++ ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); ++ if (ret) ++ return ret; ++ } ++ ++ if (dev_req_params->lane_tx == UFS_LANE_2 && dev_req_params->lane_rx == UFS_LANE_2) ++ ret = ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, ++ PA_INITIAL_ADAPT); ++ } ++ ++ return ret; ++} ++ ++static struct ufs_hba_variant_ops ufs_versal2_hba_vops = { ++ .name = "ufs-versal2-pltfm", ++ .init = ufs_versal2_init, ++ .link_startup_notify = ufs_versal2_link_startup_notify, ++ .hce_enable_notify = ufs_versal2_hce_enable_notify, ++ .pwr_change_notify = ufs_versal2_pwr_change_notify, ++}; ++ ++static const struct of_device_id ufs_versal2_pltfm_match[] = { ++ { ++ .compatible = "amd,versal2-ufs", ++ .data = &ufs_versal2_hba_vops, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, ufs_versal2_pltfm_match); ++ ++static int ufs_versal2_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ /* Perform generic probe */ ++ ret = ufshcd_pltfrm_init(pdev, &ufs_versal2_hba_vops); ++ if (ret) ++ dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", ret); ++ ++ return ret; ++} ++ ++static void ufs_versal2_remove(struct platform_device *pdev) ++{ ++ struct ufs_hba *hba = platform_get_drvdata(pdev); ++ ++ pm_runtime_get_sync(&(pdev)->dev); ++ ufshcd_remove(hba); ++} ++ ++static const struct dev_pm_ops ufs_versal2_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) ++ SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) ++}; ++ ++static struct platform_driver ufs_versal2_pltfm = { ++ .probe = ufs_versal2_probe, ++ .remove = ufs_versal2_remove, ++ .driver = { ++ .name = "ufshcd-versal2", ++ .pm = &ufs_versal2_pm_ops, ++ .of_match_table = of_match_ptr(ufs_versal2_pltfm_match), ++ }, ++}; ++ ++module_platform_driver(ufs_versal2_pltfm); ++ ++MODULE_AUTHOR("Sai Krishna Potthuri "); ++MODULE_DESCRIPTION("AMD Versal Gen 2 UFS Host Controller driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h +index ad91ea56662c..c618bb914904 100644 +--- a/drivers/ufs/host/ufshcd-dwc.h ++++ b/drivers/ufs/host/ufshcd-dwc.h +@@ -12,6 +12,52 @@ + + #include + ++/* RMMI Attributes */ ++#define CBREFCLKCTRL2 0x8132 ++#define CBCRCTRL 0x811F ++#define CBC10DIRECTCONF2 0x810E ++#define CBRATESEL 0x8114 ++#define CBCREGADDRLSB 0x8116 ++#define CBCREGADDRMSB 0x8117 ++#define CBCREGWRLSB 0x8118 ++#define CBCREGWRMSB 0x8119 ++#define CBCREGRDLSB 0x811A ++#define CBCREGRDMSB 0x811B ++#define CBCREGRDWRSEL 0x811C ++ ++#define CBREFREFCLK_GATE_OVR_EN BIT(7) ++ ++/* M-PHY Attributes */ ++#define MTX_FSM_STATE 0x41 ++#define MRX_FSM_STATE 0xC1 ++ ++/* M-PHY registers */ ++#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100)) ++#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100)) ++#define FAST_FLAGS(n) (0x401C + ((n) * 0x100)) ++#define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100)) ++#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100)) ++#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100)) ++ ++/* Tx/Rx FSM state */ ++enum rx_fsm_state { ++ RX_STATE_DISABLED = 0, ++ RX_STATE_HIBERN8 = 1, ++ RX_STATE_SLEEP = 2, ++ RX_STATE_STALL = 3, ++ RX_STATE_LSBURST = 4, ++ RX_STATE_HSBURST = 5, ++}; ++ ++enum tx_fsm_state { ++ TX_STATE_DISABLED = 0, ++ TX_STATE_HIBERN8 = 1, ++ TX_STATE_SLEEP = 2, ++ TX_STATE_STALL = 3, ++ TX_STATE_LSBURST = 4, ++ TX_STATE_HSBURST = 5, ++}; ++ + struct ufshcd_dme_attr_val { + u32 attr_sel; + u32 mib_val; +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 360e1245fb40..faf1c471ad30 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -174,6 +174,7 @@ + #define VS_POWERSTATE 0xD083 + #define VS_MPHYCFGUPDT 0xD085 + #define VS_DEBUGOMC 0xD09E ++#define VS_MPHYDISABLE 0xD0C1 + + #define PA_GRANULARITY_MIN_VAL 1 + #define PA_GRANULARITY_MAX_VAL 6 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch deleted file mode 100644 index 5640477b61..0000000000 --- a/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 24e92b2f714ec09b1217533e18d18a7a1416d52f Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:35 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on - Milk-V Jupiter - -Because the default console's baud rate is not set, defconfig kernels do -not have any serial output on this platform. Set the baud rate to -115200, matching what is used by U-Boot etc on this platform. - -See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") -Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-2-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index afaad59e6bce..db98dbfadf00 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -20,7 +20,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - leds { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0420-UPSTREAM-scsi-ufs-amd-versal2-Fix-PHY-initialization.patch b/SPECS/linux-lts-kmhv2/0420-UPSTREAM-scsi-ufs-amd-versal2-Fix-PHY-initialization.patch new file mode 100644 index 0000000000..7a26cf2da7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0420-UPSTREAM-scsi-ufs-amd-versal2-Fix-PHY-initialization.patch @@ -0,0 +1,42 @@ +From fde75cf0667176b48c80b52592112e61f8335ade Mon Sep 17 00:00:00 2001 +From: Ajay Neeli +Date: Wed, 24 Dec 2025 11:09:50 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: amd-versal2: Fix PHY initialization + in HCE enable notify + +Move the PHY initialization from PRE_CHANGE to POST_CHANGE in the +ufs_versal2_hce_enable_notify() callback. This ensures that the PHY is +initialized after the host controller enable sequence is complete, rather +than before it starts. + +The PHY initialization requires the UFS host controller to be in a stable +enabled state to properly configure the MPHY registers. Moving this to +POST_CHANGE aligns with the expected initialization order and prevents +potential timing issues during controller startup. + +Fixes: 769b8b2ffded ("scsi: ufs: amd-versal2: Add UFS support for AMD Versal Gen 2 SoC") +Signed-off-by: Ajay Neeli +Link: https://patch.msgid.link/20251224053950.54213-1-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 0444568edbf87c1da76b61c798ce0f1c1e478467) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-amd-versal2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c +index 40543db621a1..6c454ae8a9c8 100644 +--- a/drivers/ufs/host/ufs-amd-versal2.c ++++ b/drivers/ufs/host/ufs-amd-versal2.c +@@ -367,7 +367,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, + { + int ret = 0; + +- if (status == PRE_CHANGE) { ++ if (status == POST_CHANGE) { + ret = ufs_versal2_phy_init(hba); + if (ret) + dev_err(hba->dev, "Phy init failed (%d)\n", ret); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch deleted file mode 100644 index f35dbf7a0b..0000000000 --- a/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8422624a96d6035950f1902cc537f1e7d2a4c281 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:36 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: sort aliases on Milk-V - Jupiter - -Before adding more aliases, just sort them. - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-3-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index db98dbfadf00..fbba33992347 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -14,9 +14,9 @@ / { - aliases { - ethernet0 = ð0; - ethernet1 = ð1; -- serial0 = &uart0; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ serial0 = &uart0; - }; - - chosen { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0421-UPSTREAM-scsi-ufs-core-Convert-string-descriptor-for.patch b/SPECS/linux-lts-kmhv2/0421-UPSTREAM-scsi-ufs-core-Convert-string-descriptor-for.patch new file mode 100644 index 0000000000..3756dee1bd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0421-UPSTREAM-scsi-ufs-core-Convert-string-descriptor-for.patch @@ -0,0 +1,103 @@ +From d6fa6c137f923ae7d7f34fa69ba2c2568d901363 Mon Sep 17 00:00:00 2001 +From: Bean Huo +Date: Sat, 8 Nov 2025 00:05:16 +0100 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Convert string descriptor + format macros to enum + +Convert SD_ASCII_STD and SD_RAW from boolean macros to enum values for +improved code readability. This makes ufshcd_read_string_desc() calls +self-documenting by using explicit enum values instead of true/false. + +Move the ufshcd_read_string_desc() declaration from include/ufs/ufshcd.h +to drivers/ufs/core/ufshcd-priv.h since this function is not exported. + +Co-developed-by: Bart Van Assche +Signed-off-by: Bart Van Assche +Suggested-by: Avri Altman +Signed-off-by: Bean Huo +Link: https://patch.msgid.link/20251107230518.4060231-2-beanhuo@iokpp.de +Signed-off-by: Martin K. Petersen +(cherry picked from commit 0d9a7085ec24983b5b8a4971c0eb6c756c75f1bf) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd-priv.h | 14 ++++++++++---- + drivers/ufs/core/ufshcd.c | 8 +++----- + include/ufs/ufshcd.h | 4 ---- + 3 files changed, 13 insertions(+), 13 deletions(-) + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 1f0d38aa37f9..f3eeaf45cfdb 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -80,11 +80,17 @@ int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag); + void ufshcd_release_scsi_cmd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp); + +-#define SD_ASCII_STD true +-#define SD_RAW false +-int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, +- u8 **buf, bool ascii); ++/** ++ * enum ufs_descr_fmt - UFS string descriptor format ++ * @SD_RAW: Raw UTF-16 format ++ * @SD_ASCII_STD: Convert to null-terminated ASCII string ++ */ ++enum ufs_descr_fmt { ++ SD_RAW = 0, ++ SD_ASCII_STD = 1, ++}; + ++int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, u8 **buf, enum ufs_descr_fmt fmt); + int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); + int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); + +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 5371f173e28b..eaced632623f 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -3773,16 +3773,14 @@ static inline char ufshcd_remove_non_printable(u8 ch) + * @desc_index: descriptor index + * @buf: pointer to buffer where descriptor would be read, + * the caller should free the memory. +- * @ascii: if true convert from unicode to ascii characters +- * null terminated string. ++ * @fmt: if %SD_ASCII_STD, convert from UTF-16 to ASCII + * + * Return: + * * string size on success. + * * -ENOMEM: on allocation failure + * * -EINVAL: on a wrong parameter + */ +-int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, +- u8 **buf, bool ascii) ++int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, u8 **buf, enum ufs_descr_fmt fmt) + { + struct uc_string_id *uc_str; + u8 *str; +@@ -3811,7 +3809,7 @@ int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, + goto out; + } + +- if (ascii) { ++ if (fmt == SD_ASCII_STD) { + ssize_t ascii_len; + int i; + /* remove header and divide by 2 to move from UTF16 to UTF8 */ +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 17fe07dac6a7..a829db551080 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1433,10 +1433,6 @@ static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) + void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); + void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, + const struct ufs_dev_quirk *fixups); +-#define SD_ASCII_STD true +-#define SD_RAW false +-int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, +- u8 **buf, bool ascii); + + void ufshcd_hold(struct ufs_hba *hba); + void ufshcd_release(struct ufs_hba *hba); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch deleted file mode 100644 index ebf0663617..0000000000 --- a/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 72311926929a84047a95c07cdcaf0f7211764d88 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:37 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V - Jupiter - -The Milk-V Jupiter board has a connector for an eMMC module. Add an -entry for it in the device tree and alias it mmc0. - -Mark the device as non-removable as eMMC modules have no CD pin and are -not supposed to be inserted or removed while the system is running. On -systems without an eMMC module installed, the kernel emits the following -informational message during boot: - -mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA -mmc0: Failed to initialize a non-removable card - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-4-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index fbba33992347..1a833e716cb6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -16,6 +16,7 @@ aliases { - ethernet1 = ð1; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; - serial0 = &uart0; - }; - -@@ -105,6 +106,16 @@ &combo_phy { - status = "okay"; - }; - -+&emmc { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0422-UPSTREAM-scsi-ufs-core-Add-OP-TEE-based-RPMB-driver-.patch b/SPECS/linux-lts-kmhv2/0422-UPSTREAM-scsi-ufs-core-Add-OP-TEE-based-RPMB-driver-.patch new file mode 100644 index 0000000000..41feb06ad3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0422-UPSTREAM-scsi-ufs-core-Add-OP-TEE-based-RPMB-driver-.patch @@ -0,0 +1,562 @@ +From e5be2897e232f2c9cf7bfd60fc7f251f27659db4 Mon Sep 17 00:00:00 2001 +From: Bean Huo +Date: Sat, 8 Nov 2025 00:05:18 +0100 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add OP-TEE based RPMB driver + for UFS devices + +Add OP-TEE based RPMB support for UFS devices. This enables secure RPMB +operations on UFS devices through OP-TEE, providing the same +functionality available for eMMC devices and extending kernel-based +secure storage support to UFS-based systems. + +Benefits of OP-TEE based RPMB implementation: + + - Eliminates dependency on userspace supplicant for RPMB access + + - Enables early boot secure storage access (e.g., fTPM, secure UEFI + variables) + + - Provides kernel-level RPMB access as soon as UFS driver is + initialized + + - Removes complex initramfs dependencies and boot ordering requirements + + - Ensures reliable and deterministic secure storage operations + + - Supports both built-in and modular fTPM configurations + +[mkp: make this build as a module] + +Co-developed-by: Can Guo +Signed-off-by: Can Guo +Reviewed-by: Avri Altman +Reviewed-by: Bart Van Assche +Signed-off-by: Bean Huo +Link: https://patch.msgid.link/20251107230518.4060231-4-beanhuo@iokpp.de +Signed-off-by: Martin K. Petersen +(cherry picked from commit b06b8c421485e0e96d7fd6aa614fb0b6f2778a03) +Signed-off-by: Han Gao +--- + drivers/misc/Kconfig | 2 +- + drivers/ufs/core/Makefile | 1 + + drivers/ufs/core/ufs-rpmb.c | 254 +++++++++++++++++++++++++++++++++ + drivers/ufs/core/ufshcd-priv.h | 13 ++ + drivers/ufs/core/ufshcd.c | 86 ++++++++++- + include/ufs/ufs.h | 5 + + include/ufs/ufshcd.h | 7 +- + 7 files changed, 361 insertions(+), 7 deletions(-) + create mode 100644 drivers/ufs/core/ufs-rpmb.c + +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index b9c11f67315f..9d1de68dee27 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -106,7 +106,7 @@ config PHANTOM + + config RPMB + tristate "RPMB partition interface" +- depends on MMC ++ depends on MMC || SCSI_UFSHCD + help + Unified RPMB unit interface for RPMB capable devices such as eMMC and + UFS. Provides interface for in-kernel security controllers to access +diff --git a/drivers/ufs/core/Makefile b/drivers/ufs/core/Makefile +index cf820fa09a04..51e1867e524e 100644 +--- a/drivers/ufs/core/Makefile ++++ b/drivers/ufs/core/Makefile +@@ -2,6 +2,7 @@ + + obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o + ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ++ufshcd-core-$(CONFIG_RPMB) += ufs-rpmb.o + ufshcd-core-$(CONFIG_DEBUG_FS) += ufs-debugfs.o + ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o + ufshcd-core-$(CONFIG_SCSI_UFS_CRYPTO) += ufshcd-crypto.o +diff --git a/drivers/ufs/core/ufs-rpmb.c b/drivers/ufs/core/ufs-rpmb.c +new file mode 100644 +index 000000000000..ffad049872b9 +--- /dev/null ++++ b/drivers/ufs/core/ufs-rpmb.c +@@ -0,0 +1,254 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * UFS OP-TEE based RPMB Driver ++ * ++ * Copyright (C) 2025 Micron Technology, Inc. ++ * Copyright (C) 2025 Qualcomm Technologies, Inc. ++ * ++ * Authors: ++ * Bean Huo ++ * Can Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ufshcd-priv.h" ++ ++#define UFS_RPMB_SEC_PROTOCOL 0xEC /* JEDEC UFS application */ ++#define UFS_RPMB_SEC_PROTOCOL_ID 0x01 /* JEDEC UFS RPMB protocol ID, CDB byte3 */ ++ ++static const struct bus_type ufs_rpmb_bus_type = { ++ .name = "ufs_rpmb", ++}; ++ ++/* UFS RPMB device structure */ ++struct ufs_rpmb_dev { ++ u8 region_id; ++ struct device dev; ++ struct rpmb_dev *rdev; ++ struct ufs_hba *hba; ++ struct list_head node; ++}; ++ ++static int ufs_sec_submit(struct ufs_hba *hba, u16 spsp, void *buffer, size_t len, bool send) ++{ ++ struct scsi_device *sdev = hba->ufs_rpmb_wlun; ++ u8 cdb[12] = { }; ++ ++ cdb[0] = send ? SECURITY_PROTOCOL_OUT : SECURITY_PROTOCOL_IN; ++ cdb[1] = UFS_RPMB_SEC_PROTOCOL; ++ put_unaligned_be16(spsp, &cdb[2]); ++ put_unaligned_be32(len, &cdb[6]); ++ ++ return scsi_execute_cmd(sdev, cdb, send ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN, ++ buffer, len, /*timeout=*/30 * HZ, 0, NULL); ++} ++ ++/* UFS RPMB route frames implementation */ ++static int ufs_rpmb_route_frames(struct device *dev, u8 *req, unsigned int req_len, u8 *resp, ++ unsigned int resp_len) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb = dev_get_drvdata(dev); ++ struct rpmb_frame *frm_out = (struct rpmb_frame *)req; ++ bool need_result_read = true; ++ u16 req_type, protocol_id; ++ struct ufs_hba *hba; ++ int ret; ++ ++ if (!ufs_rpmb) { ++ dev_err(dev, "Missing driver data\n"); ++ return -ENODEV; ++ } ++ ++ hba = ufs_rpmb->hba; ++ ++ req_type = be16_to_cpu(frm_out->req_resp); ++ ++ switch (req_type) { ++ case RPMB_PROGRAM_KEY: ++ if (req_len != sizeof(struct rpmb_frame) || resp_len != sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ break; ++ case RPMB_GET_WRITE_COUNTER: ++ if (req_len != sizeof(struct rpmb_frame) || resp_len != sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ need_result_read = false; ++ break; ++ case RPMB_WRITE_DATA: ++ if (req_len % sizeof(struct rpmb_frame) || resp_len != sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ break; ++ case RPMB_READ_DATA: ++ if (req_len != sizeof(struct rpmb_frame) || resp_len % sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ need_result_read = false; ++ break; ++ default: ++ dev_err(dev, "Unknown request type=0x%04x\n", req_type); ++ return -EINVAL; ++ } ++ ++ protocol_id = ufs_rpmb->region_id << 8 | UFS_RPMB_SEC_PROTOCOL_ID; ++ ++ ret = ufs_sec_submit(hba, protocol_id, req, req_len, true); ++ if (ret) { ++ dev_err(dev, "Command failed with ret=%d\n", ret); ++ return ret; ++ } ++ ++ if (need_result_read) { ++ struct rpmb_frame *frm_resp = (struct rpmb_frame *)resp; ++ ++ memset(frm_resp, 0, sizeof(*frm_resp)); ++ frm_resp->req_resp = cpu_to_be16(RPMB_RESULT_READ); ++ ret = ufs_sec_submit(hba, protocol_id, resp, resp_len, true); ++ if (ret) { ++ dev_err(dev, "Result read request failed with ret=%d\n", ret); ++ return ret; ++ } ++ } ++ ++ if (!ret) { ++ ret = ufs_sec_submit(hba, protocol_id, resp, resp_len, false); ++ if (ret) ++ dev_err(dev, "Response read failed with ret=%d\n", ret); ++ } ++ ++ return ret; ++} ++ ++static void ufs_rpmb_device_release(struct device *dev) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb = dev_get_drvdata(dev); ++ ++ rpmb_dev_unregister(ufs_rpmb->rdev); ++} ++ ++/* UFS RPMB device registration */ ++int ufs_rpmb_probe(struct ufs_hba *hba) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb, *it, *tmp; ++ struct rpmb_dev *rdev; ++ char *cid = NULL; ++ int region; ++ u32 cap; ++ int ret; ++ ++ if (!hba->ufs_rpmb_wlun || hba->dev_info.b_advanced_rpmb_en) { ++ dev_info(hba->dev, "Skip OP-TEE RPMB registration\n"); ++ return -ENODEV; ++ } ++ ++ /* Check if device_id is available */ ++ if (!hba->dev_info.device_id) { ++ dev_err(hba->dev, "UFS Device ID not available\n"); ++ return -EINVAL; ++ } ++ ++ INIT_LIST_HEAD(&hba->rpmbs); ++ ++ struct rpmb_descr descr = { ++ .type = RPMB_TYPE_UFS, ++ .route_frames = ufs_rpmb_route_frames, ++ .reliable_wr_count = hba->dev_info.rpmb_io_size, ++ }; ++ ++ for (region = 0; region < ARRAY_SIZE(hba->dev_info.rpmb_region_size); region++) { ++ cap = hba->dev_info.rpmb_region_size[region]; ++ if (!cap) ++ continue; ++ ++ ufs_rpmb = devm_kzalloc(hba->dev, sizeof(*ufs_rpmb), GFP_KERNEL); ++ if (!ufs_rpmb) { ++ ret = -ENOMEM; ++ goto err_out; ++ } ++ ++ ufs_rpmb->hba = hba; ++ ufs_rpmb->dev.parent = &hba->ufs_rpmb_wlun->sdev_gendev; ++ ufs_rpmb->dev.bus = &ufs_rpmb_bus_type; ++ ufs_rpmb->dev.release = ufs_rpmb_device_release; ++ dev_set_name(&ufs_rpmb->dev, "ufs_rpmb%d", region); ++ ++ /* Set driver data BEFORE device_register */ ++ dev_set_drvdata(&ufs_rpmb->dev, ufs_rpmb); ++ ++ ret = device_register(&ufs_rpmb->dev); ++ if (ret) { ++ dev_err(hba->dev, "Failed to register UFS RPMB device %d\n", region); ++ put_device(&ufs_rpmb->dev); ++ goto err_out; ++ } ++ ++ /* Create unique ID by appending region number to device_id */ ++ cid = kasprintf(GFP_KERNEL, "%s-R%d", hba->dev_info.device_id, region); ++ if (!cid) { ++ device_unregister(&ufs_rpmb->dev); ++ ret = -ENOMEM; ++ goto err_out; ++ } ++ ++ descr.dev_id = cid; ++ descr.dev_id_len = strlen(cid); ++ descr.capacity = cap; ++ ++ /* Register RPMB device */ ++ rdev = rpmb_dev_register(&ufs_rpmb->dev, &descr); ++ if (IS_ERR(rdev)) { ++ dev_err(hba->dev, "Failed to register UFS RPMB device.\n"); ++ device_unregister(&ufs_rpmb->dev); ++ ret = PTR_ERR(rdev); ++ goto err_out; ++ } ++ ++ kfree(cid); ++ cid = NULL; ++ ++ ufs_rpmb->rdev = rdev; ++ ufs_rpmb->region_id = region; ++ ++ list_add_tail(&ufs_rpmb->node, &hba->rpmbs); ++ ++ dev_info(hba->dev, "UFS RPMB region %d registered (capacity=%u)\n", region, cap); ++ } ++ ++ return 0; ++err_out: ++ kfree(cid); ++ list_for_each_entry_safe(it, tmp, &hba->rpmbs, node) { ++ list_del(&it->node); ++ device_unregister(&it->dev); ++ } ++ ++ return ret; ++} ++ ++/* UFS RPMB remove handler */ ++void ufs_rpmb_remove(struct ufs_hba *hba) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb, *tmp; ++ ++ if (list_empty(&hba->rpmbs)) ++ return; ++ ++ /* Remove all registered RPMB devices */ ++ list_for_each_entry_safe(ufs_rpmb, tmp, &hba->rpmbs, node) { ++ dev_info(hba->dev, "Removing UFS RPMB region %d\n", ufs_rpmb->region_id); ++ /* Remove from list first */ ++ list_del(&ufs_rpmb->node); ++ /* Unregister device */ ++ device_unregister(&ufs_rpmb->dev); ++ } ++ ++ dev_info(hba->dev, "All UFS RPMB devices unregistered\n"); ++} ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("OP-TEE UFS RPMB driver"); +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index f3eeaf45cfdb..3ccbbdb18a24 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -419,4 +419,17 @@ static inline u32 ufshcd_mcq_get_sq_head_slot(struct ufs_hw_queue *q) + return val / sizeof(struct utp_transfer_req_desc); + } + ++#if IS_ENABLED(CONFIG_RPMB) ++int ufs_rpmb_probe(struct ufs_hba *hba); ++void ufs_rpmb_remove(struct ufs_hba *hba); ++#else ++static inline int ufs_rpmb_probe(struct ufs_hba *hba) ++{ ++ return 0; ++} ++static inline void ufs_rpmb_remove(struct ufs_hba *hba) ++{ ++} ++#endif ++ + #endif /* _UFSHCD_PRIV_H_ */ +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index eaced632623f..707f3243dda3 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -5243,10 +5243,15 @@ static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) + desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) + hba->dev_info.is_lu_power_on_wp = true; + +- /* In case of RPMB LU, check if advanced RPMB mode is enabled */ +- if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && +- desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) +- hba->dev_info.b_advanced_rpmb_en = true; ++ /* In case of RPMB LU, check if advanced RPMB mode is enabled, and get region size */ ++ if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN) { ++ if (desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) ++ hba->dev_info.b_advanced_rpmb_en = true; ++ hba->dev_info.rpmb_region_size[0] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION0_SIZE]; ++ hba->dev_info.rpmb_region_size[1] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION1_SIZE]; ++ hba->dev_info.rpmb_region_size[2] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION2_SIZE]; ++ hba->dev_info.rpmb_region_size[3] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION3_SIZE]; ++ } + + + kfree(desc_buf); +@@ -8206,8 +8211,11 @@ static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) + ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); + if (IS_ERR(sdev_rpmb)) { + ret = PTR_ERR(sdev_rpmb); ++ hba->ufs_rpmb_wlun = NULL; ++ dev_err(hba->dev, "%s: RPMB WLUN not found\n", __func__); + goto remove_ufs_device_wlun; + } ++ hba->ufs_rpmb_wlun = sdev_rpmb; + ufshcd_blk_pm_runtime_init(sdev_rpmb); + scsi_device_put(sdev_rpmb); + +@@ -8475,6 +8483,67 @@ static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) + dev_info->rtc_update_period = 0; + } + ++/** ++ * ufshcd_create_device_id - Generate unique device identifier string ++ * @hba: per-adapter instance ++ * @desc_buf: device descriptor buffer ++ * ++ * Creates a unique device ID string combining manufacturer ID, spec version, ++ * model name, serial number (as hex), device version, and manufacture date. ++ * ++ * Returns: Allocated device ID string on success, NULL on failure ++ */ ++static char *ufshcd_create_device_id(struct ufs_hba *hba, u8 *desc_buf) ++{ ++ struct ufs_dev_info *dev_info = &hba->dev_info; ++ u16 manufacture_date; ++ u16 device_version; ++ u8 *serial_number; ++ char *serial_hex; ++ char *device_id; ++ u8 serial_index; ++ int serial_len; ++ int ret; ++ ++ serial_index = desc_buf[DEVICE_DESC_PARAM_SN]; ++ ++ ret = ufshcd_read_string_desc(hba, serial_index, &serial_number, SD_RAW); ++ if (ret < 0) { ++ dev_err(hba->dev, "Failed reading Serial Number. err = %d\n", ret); ++ return NULL; ++ } ++ ++ device_version = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_DEV_VER]); ++ manufacture_date = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_MANF_DATE]); ++ ++ serial_len = ret; ++ /* Allocate buffer for hex string: 2 chars per byte + null terminator */ ++ serial_hex = kzalloc(serial_len * 2 + 1, GFP_KERNEL); ++ if (!serial_hex) { ++ kfree(serial_number); ++ return NULL; ++ } ++ ++ bin2hex(serial_hex, serial_number, serial_len); ++ ++ /* ++ * Device ID format is ABI with secure world - do not change without firmware ++ * coordination. ++ */ ++ device_id = kasprintf(GFP_KERNEL, "%04X-%04X-%s-%s-%04X-%04X", ++ dev_info->wmanufacturerid, dev_info->wspecversion, ++ dev_info->model, serial_hex, device_version, ++ manufacture_date); ++ ++ kfree(serial_hex); ++ kfree(serial_number); ++ ++ if (!device_id) ++ dev_warn(hba->dev, "Failed to allocate unique device ID\n"); ++ ++ return device_id; ++} ++ + static int ufs_get_device_desc(struct ufs_hba *hba) + { + int err; +@@ -8524,6 +8593,9 @@ static int ufs_get_device_desc(struct ufs_hba *hba) + goto out; + } + ++ /* Generate unique device ID */ ++ dev_info->device_id = ufshcd_create_device_id(hba, desc_buf); ++ + hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + + desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; + +@@ -8559,6 +8631,8 @@ static void ufs_put_device_desc(struct ufs_hba *hba) + + kfree(dev_info->model); + dev_info->model = NULL; ++ kfree(dev_info->device_id); ++ dev_info->device_id = NULL; + } + + /** +@@ -8702,6 +8776,8 @@ static int ufshcd_device_geo_params_init(struct ufs_hba *hba) + else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) + hba->dev_info.max_lu_supported = 8; + ++ hba->dev_info.rpmb_io_size = desc_buf[GEOMETRY_DESC_PARAM_RPMB_RW_SIZE]; ++ + out: + kfree(desc_buf); + return err; +@@ -8888,6 +8964,7 @@ static int ufshcd_add_lus(struct ufs_hba *hba) + + ufs_bsg_probe(hba); + scsi_scan_host(hba->host); ++ ufs_rpmb_probe(hba); + + out: + return ret; +@@ -10455,6 +10532,7 @@ void ufshcd_remove(struct ufs_hba *hba) + ufshcd_rpm_get_sync(hba); + ufs_hwmon_remove(hba); + ufs_bsg_remove(hba); ++ ufs_rpmb_remove(hba); + ufs_sysfs_remove_nodes(hba->dev); + cancel_delayed_work_sync(&hba->ufs_rtc_update_work); + blk_mq_destroy_queue(hba->tmf_queue); +diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h +index 245a6a829ce9..ab8f6c07b5a2 100644 +--- a/include/ufs/ufs.h ++++ b/include/ufs/ufs.h +@@ -651,6 +651,11 @@ struct ufs_dev_info { + u8 rtt_cap; /* bDeviceRTTCap */ + + bool hid_sup; ++ ++ /* Unique device ID string (manufacturer+model+serial+version+date) */ ++ char *device_id; ++ u8 rpmb_io_size; ++ u8 rpmb_region_size[4]; + }; + + #endif /* End of Header */ +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index a829db551080..e59e37753ad7 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -833,6 +833,7 @@ enum ufshcd_mcq_opr { + * @host: Scsi_Host instance of the driver + * @dev: device handle + * @ufs_device_wlun: WLUN that controls the entire UFS device. ++ * @ufs_rpmb_wlun: RPMB WLUN SCSI device + * @hwmon_device: device instance registered with the hwmon core. + * @curr_dev_pwr_mode: active UFS device power mode. + * @uic_link_state: active state of the link to the UFS device. +@@ -948,8 +949,8 @@ enum ufshcd_mcq_opr { + * @pm_qos_mutex: synchronizes PM QoS request and status updates + * @critical_health_count: count of critical health exceptions + * @dev_lvl_exception_count: count of device level exceptions since last reset +- * @dev_lvl_exception_id: vendor specific information about the +- * device level exception event. ++ * @dev_lvl_exception_id: vendor specific information about the device level exception event. ++ * @rpmbs: list of OP-TEE RPMB devices (one per RPMB region) + */ + struct ufs_hba { + void __iomem *mmio_base; +@@ -967,6 +968,7 @@ struct ufs_hba { + struct Scsi_Host *host; + struct device *dev; + struct scsi_device *ufs_device_wlun; ++ struct scsi_device *ufs_rpmb_wlun; + + #ifdef CONFIG_SCSI_UFS_HWMON + struct device *hwmon_device; +@@ -1124,6 +1126,7 @@ struct ufs_hba { + int critical_health_count; + atomic_t dev_lvl_exception_count; + u64 dev_lvl_exception_id; ++ struct list_head rpmbs; + }; + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch deleted file mode 100644 index 7b0fee89d3..0000000000 --- a/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 629f9f3c4e0f9cca344b52a02ceedd2e91ab9756 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:38 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable SD card support - on Milk-V Jupiter - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with pull-up -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Alias it as mmc1 - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-5-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 1a833e716cb6..beebf804197e 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -17,6 +17,7 @@ aliases { - i2c2 = &i2c2; - i2c8 = &i2c8; - mmc0 = &emmc; -+ mmc1 = &sdhci0; - serial0 = &uart0; - }; - -@@ -250,7 +251,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -385,6 +386,24 @@ uboot@a00000 { - }; - }; - -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4_3v3>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0423-UPSTREAM-scsi-ufs-host-mediatek-Correct-clock-scalin.patch b/SPECS/linux-lts-kmhv2/0423-UPSTREAM-scsi-ufs-host-mediatek-Correct-clock-scalin.patch new file mode 100644 index 0000000000..7d13bd32e1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0423-UPSTREAM-scsi-ufs-host-mediatek-Correct-clock-scalin.patch @@ -0,0 +1,101 @@ +From ef9429eda550c8a92b95a1a698364f2bf497f3bc Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:23 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Correct clock + scaling with PM QoS flow + +Correct clock scaling with PM QoS during suspend and resume. Ensure PM +QoS is released during suspend if scaling up and re-applied after +resume. This prevents performance issues and maintains proper power +management. + +Signed-off-by: Peter Wang +Reviewed-by: Bart Van Assche +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-2-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 7162536410768ec6b219524c36d3a871ff97adf8) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd.c | 3 ++- + drivers/ufs/host/ufs-mediatek.c | 10 ++++++++++ + include/ufs/ufshcd.h | 1 + + 3 files changed, 13 insertions(+), 1 deletion(-) + +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 707f3243dda3..80c504e270b6 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -1076,7 +1076,7 @@ void ufshcd_pm_qos_exit(struct ufs_hba *hba) + * @hba: per adapter instance + * @on: If True, vote for perf PM QoS mode otherwise power save mode + */ +-static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) ++void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) + { + guard(mutex)(&hba->pm_qos_mutex); + +@@ -1085,6 +1085,7 @@ static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) + + cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); + } ++EXPORT_SYMBOL_GPL(ufshcd_pm_qos_update); + + /** + * ufshcd_set_clk_freq - set UFS controller clock frequencies +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 3c63adca561d..27418ea618ed 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1744,6 +1744,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + { + int err; + struct arm_smccc_res res; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + if (status == PRE_CHANGE) { + if (ufshcd_is_auto_hibern8_supported(hba)) +@@ -1773,6 +1774,10 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + + ufs_mtk_sram_pwr_ctrl(false, res); + ++ /* Release pm_qos if in scale-up mode during suspend */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ ufshcd_pm_qos_update(hba, false); ++ + return 0; + fail: + /* +@@ -1788,6 +1793,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + { + int err; + struct arm_smccc_res res; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) + ufs_mtk_dev_vreg_set_lpm(hba, false); +@@ -1798,6 +1804,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + if (err) + goto fail; + ++ /* Request pm_qos if in scale-up mode after resume */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ ufshcd_pm_qos_update(hba, true); ++ + if (ufshcd_is_link_hibern8(hba)) { + err = ufs_mtk_link_set_hpm(hba); + if (err) +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index e59e37753ad7..9f2160829d80 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1488,5 +1488,6 @@ int ufshcd_write_ee_control(struct ufs_hba *hba); + int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, + const u16 *other_mask, u16 set, u16 clr); + void ufshcd_force_error_recovery(struct ufs_hba *hba); ++void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on); + + #endif /* End of Header */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch deleted file mode 100644 index c52a677920..0000000000 --- a/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 396d9a81ca85057f4a8bc7ad711b684dcffafb06 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:39 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: fix uboot partition - offset on Milk-V Jupiter - -Correct the uboot partition node name to match its actual offset. - -Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-6-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index beebf804197e..2fc8d6533786 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -379,7 +379,7 @@ env@60000 { - opensbi@70000 { - reg = <0x70000 0x30000>; - }; -- uboot@a00000 { -+ uboot@a0000 { - reg = <0xa0000 0x760000>; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0424-UPSTREAM-scsi-ufs-host-mediatek-Adjust-clock-scaling.patch b/SPECS/linux-lts-kmhv2/0424-UPSTREAM-scsi-ufs-host-mediatek-Adjust-clock-scaling.patch new file mode 100644 index 0000000000..9a66fd41c1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0424-UPSTREAM-scsi-ufs-host-mediatek-Adjust-clock-scaling.patch @@ -0,0 +1,56 @@ +From f1d17b7a4f696ff2e0d459ce22f402103a434cde Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:24 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Adjust clock + scaling for PM flow + +Adjust clock scaling during suspend and resume in the UFS Mediatek +driver. Ensure that the clock scales down during suspend if it was +scaled up, and scales up again after resume. This adjustment maintains +proper power management. + +Signed-off-by: Peter Wang +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-3-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 55ce691dc75a356e4b7c552505ce0a427c72f3af) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 27418ea618ed..c25ca23a84cc 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1774,9 +1774,11 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + + ufs_mtk_sram_pwr_ctrl(false, res); + +- /* Release pm_qos if in scale-up mode during suspend */ +- if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ /* Release pm_qos/clk if in scale-up mode during suspend */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, false); ++ _ufs_mtk_clk_scale(hba, false); ++ } + + return 0; + fail: +@@ -1804,9 +1806,11 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + if (err) + goto fail; + +- /* Request pm_qos if in scale-up mode after resume */ +- if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ /* Request pm_qos/clk if in scale-up mode after resume */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, true); ++ _ufs_mtk_clk_scale(hba, true); ++ } + + if (ufshcd_is_link_hibern8(hba)) { + err = ufs_mtk_link_set_hpm(hba); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch b/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch deleted file mode 100644 index 3cee4760cd..0000000000 --- a/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 98c6ddea13512cec403705f0e1898daa262466b1 Mon Sep 17 00:00:00 2001 -From: Zhengyu He -Date: Thu, 21 May 2026 22:44:46 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add QSPI support for K3 - Pico-ITX - -Add K3 QSPI controller node into k3.dtsi, and add related pinmux -configuration. - -Enable QSPI on Pico-ITX board, and describe the NOR flash which wires -to it. - -Signed-off-by: Cody Kang -Signed-off-by: Zhengyu He -Link: https://lore.kernel.org/r/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-2-52bce26e5fd8@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 58 ++++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 +++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ - 3 files changed, 96 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 4486dc1fe114..61cbf924830b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -192,6 +192,64 @@ phy0: phy@1 { - }; - }; - -+&pinctrl { -+ qspi-cfg { -+ qspi-pins { -+ power-source = <1800>; -+ }; -+ -+ qspi-cs0-pins { -+ power-source = <1800>; -+ }; -+ }; -+}; -+ -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x20000>; -+ }; -+ -+ fsbl@20000 { -+ reg = <0x20000 0x80000>; -+ }; -+ -+ env@a0000 { -+ reg = <0xa0000 0x10000>; -+ }; -+ -+ esos@b0000 { -+ reg = <0xb0000 0x100000>; -+ }; -+ -+ opensbi@1b0000 { -+ reg = <0x1b0000 0x60000>; -+ }; -+ -+ uboot@210000 { -+ reg = <0x210000 0x5f0000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 252c64af76fe..dffa4d583bb2 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -646,6 +646,27 @@ pwm19-2-pins { - }; - }; - -+ /omit-if-no-ref/ -+ qspi_cfg: qspi-cfg { -+ qspi-pins { -+ pinmux = , /* qspi dat0 */ -+ , /* qspi dat1 */ -+ , /* qspi dat2 */ -+ , /* qspi dat3 */ -+ ; /* qspi clk */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ }; -+ -+ qspi-cs0-pins { -+ pinmux = ; /* qspi cs0 */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 809067d6383c..5b17612fe58e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -1069,6 +1069,23 @@ pll: clock-controller@d4090000 { - #clock-cells = <1>; - }; - -+ qspi: spi@d420c000 { -+ compatible = "spacemit,k3-qspi", -+ "spacemit,k1-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0xd420c000 0x0 0x1000>, -+ <0x0 0xb8000000 0x0 0xc00000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, -+ <&syscon_apmu CLK_APMU_QSPI>; -+ clock-names = "qspi_en", "qspi"; -+ resets = <&syscon_apmu RESET_APMU_QSPI>, -+ <&syscon_apmu RESET_APMU_QSPI_BUS>; -+ interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ - syscon_apmu: system-controller@d4282800 { - compatible = "spacemit,k3-syscon-apmu"; - reg = <0x0 0xd4282800 0x0 0x400>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0425-UPSTREAM-scsi-ufs-host-mediatek-Handle-clock-scaling.patch b/SPECS/linux-lts-kmhv2/0425-UPSTREAM-scsi-ufs-host-mediatek-Handle-clock-scaling.patch new file mode 100644 index 0000000000..55c43cebb7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0425-UPSTREAM-scsi-ufs-host-mediatek-Handle-clock-scaling.patch @@ -0,0 +1,48 @@ +From e6b93ad394a4fa2295a2087afc9a956837475724 Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:25 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Handle clock + scaling for high gear in PM flow + +Add clock scaling down for power management flow in the UFS Mediatek +driver. If clock scaling is disabled and fixed in high gear, ensure the +clock scales down during suspend and scales up again after resume to +support high gear. This adjustment maintains proper power management. + +Signed-off-by: Peter Wang +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-4-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 16b42c4281ae536a6ceda97303d9820ac5741293) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index c25ca23a84cc..b8ef8eefa1cc 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1778,6 +1778,9 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, false); + _ufs_mtk_clk_scale(hba, false); ++ } else if ((!ufshcd_is_clkscaling_supported(hba) && ++ hba->pwr_info.gear_rx >= UFS_HS_G5)) { ++ _ufs_mtk_clk_scale(hba, false); + } + + return 0; +@@ -1810,6 +1813,9 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, true); + _ufs_mtk_clk_scale(hba, true); ++ } else if ((!ufshcd_is_clkscaling_supported(hba) && ++ hba->pwr_info.gear_rx >= UFS_HS_G5)) { ++ _ufs_mtk_clk_scale(hba, true); + } + + if (ufshcd_is_link_hibern8(hba)) { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch deleted file mode 100644 index 2df47fbbeb..0000000000 --- a/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 4188a3bf42259d212c5d61101e694a2dc05e3dd4 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 00:40:07 +0800 -Subject: [RUYI PATCH] FROMLIST: pinctrl: spacemit: fix NULL check in - spacemit_pin_set_config - -spacemit_pin_set_config() looks up the per-pin descriptor with -spacemit_get_pin() then checks the wrong variable for failure: - - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - ... - if (!pin) - return -EINVAL; - - reg = spacemit_pin_to_reg(pctrl, spin->pin); - -pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a -valid pin, so rejecting it here drops the PAD config write for the first -pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as -its first entry, so its drive-strength / bias configuration was silently -ignored. - -The intended guard is against spacemit_get_pin() returning NULL when the -pin id isn't in the SoC's pin table. Check spin instead, which both -restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. - -Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") -Link: https://lore.kernel.org/r/20260519164007.122574-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index f3c754f78074..f71091254382 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -795,7 +795,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, - void __iomem *reg; - unsigned int mux; - -- if (!pin) -+ if (!spin) - return -EINVAL; - - reg = spacemit_pin_to_reg(pctrl, spin->pin); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0426-UPSTREAM-scsi-ufs-host-mediatek-Adjust-sync-length-f.patch b/SPECS/linux-lts-kmhv2/0426-UPSTREAM-scsi-ufs-host-mediatek-Adjust-sync-length-f.patch new file mode 100644 index 0000000000..d4e763ff16 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0426-UPSTREAM-scsi-ufs-host-mediatek-Adjust-sync-length-f.patch @@ -0,0 +1,100 @@ +From a52aba3f7189c05d469edd5ef59d86ede64eacdb Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:26 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Adjust sync length + for FASTAUTO mode + +Set the sync length for FASTAUTO G1 mode in the UFS Mediatek +driver. This ensures the sync length meets minimum values for high-speed +gears, improving stability during power mode changes. + +Signed-off-by: Peter Wang +Reviewed-by: Bart Van Assche +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-5-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 1fd05367d5b1a5edd3d14c966a5f510e5b8a0c5e) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 32 ++++++++++++++++++++++++++++++++ + include/ufs/unipro.h | 7 ++++++- + 2 files changed, 38 insertions(+), 1 deletion(-) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index b8ef8eefa1cc..0f261c3afc34 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1332,6 +1332,36 @@ static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba, + return true; + } + ++static void ufs_mtk_adjust_sync_length(struct ufs_hba *hba) ++{ ++ int i; ++ u32 value; ++ u32 cnt, att, min; ++ struct attr_min { ++ u32 attr; ++ u32 min_value; ++ } pa_min_sync_length[] = { ++ {PA_TXHSG1SYNCLENGTH, 0x48}, ++ {PA_TXHSG2SYNCLENGTH, 0x48}, ++ {PA_TXHSG3SYNCLENGTH, 0x48}, ++ {PA_TXHSG4SYNCLENGTH, 0x48}, ++ {PA_TXHSG5SYNCLENGTH, 0x48} ++ }; ++ ++ cnt = sizeof(pa_min_sync_length) / sizeof(struct attr_min); ++ for (i = 0; i < cnt; i++) { ++ att = pa_min_sync_length[i].attr; ++ min = pa_min_sync_length[i].min_value; ++ ufshcd_dme_get(hba, UIC_ARG_MIB(att), &value); ++ if (value < min) ++ ufshcd_dme_set(hba, UIC_ARG_MIB(att), min); ++ ++ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(att), &value); ++ if (value < min) ++ ufshcd_dme_peer_set(hba, UIC_ARG_MIB(att), min); ++ } ++} ++ + static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, + const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) +@@ -1355,6 +1385,8 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, + } + + if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) { ++ ufs_mtk_adjust_sync_length(hba); ++ + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1); + +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index faf1c471ad30..59de737490ca 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -111,6 +111,9 @@ + #define PA_TXLINKSTARTUPHS 0x1544 + #define PA_AVAILRXDATALANES 0x1540 + #define PA_MINRXTRAILINGCLOCKS 0x1543 ++#define PA_TXHSG1SYNCLENGTH 0x1552 ++#define PA_TXHSG2SYNCLENGTH 0x1554 ++#define PA_TXHSG3SYNCLENGTH 0x1556 + #define PA_LOCAL_TX_LCC_ENABLE 0x155E + #define PA_ACTIVETXDATALANES 0x1560 + #define PA_CONNECTEDTXDATALANES 0x1561 +@@ -160,7 +163,9 @@ + #define PA_PACPFRAMECOUNT 0x15C0 + #define PA_PACPERRORCOUNT 0x15C1 + #define PA_PHYTESTCONTROL 0x15C2 +-#define PA_TXHSADAPTTYPE 0x15D4 ++#define PA_TXHSG4SYNCLENGTH 0x15D0 ++#define PA_TXHSADAPTTYPE 0x15D4 ++#define PA_TXHSG5SYNCLENGTH 0x15D6 + + /* Adpat type for PA_TXHSADAPTTYPE attribute */ + #define PA_REFRESH_ADAPT 0x00 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch b/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch deleted file mode 100644 index 950680a506..0000000000 --- a/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 2e0cced73e82d39a2fd99776f4972c20778cd27b Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 00:55:46 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: unconditionally select - ARCH_KEEP_MEMBLOCK - -Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock -to be kept after boot to initialize the secondary kernel. Device -Tree platforms also need this for kexec support. - -Link: https://lore.kernel.org/r/20260519165546.123105-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 5cc386e56d13..68faa6cf6ee0 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -56,7 +56,7 @@ config RISCV - select ARCH_HAS_UBSAN - select ARCH_HAS_VDSO_ARCH_DATA if HAVE_GENERIC_VDSO - select ARCH_HAVE_NMI_SAFE_CMPXCHG -- select ARCH_KEEP_MEMBLOCK if ACPI -+ select ARCH_KEEP_MEMBLOCK - select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU - select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX - select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0427-UPSTREAM-scsi-ufs-host-mediatek-Remove-duplicate-fun.patch b/SPECS/linux-lts-kmhv2/0427-UPSTREAM-scsi-ufs-host-mediatek-Remove-duplicate-fun.patch new file mode 100644 index 0000000000..99520b36e0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0427-UPSTREAM-scsi-ufs-host-mediatek-Remove-duplicate-fun.patch @@ -0,0 +1,91 @@ +From 46733bb6b387ba043d987355eb2bb7fef4083ad1 Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:28 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Remove duplicate + function + +Remove the duplicate ufs_mtk_us_to_ahit() function in the UFS Mediatek +driver and export the existing ufshcd_us_to_ahit() function for shared +use. This change reduces redundancy and maintains consistency across the +codebase. + +Signed-off-by: Peter Wang +Reviewed-by: Bart Van Assche +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-7-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 9b2b03b36168bcda298546b121d6ecc530d01d25) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-sysfs.c | 3 ++- + drivers/ufs/host/ufs-mediatek.c | 14 +------------- + include/ufs/ufshcd.h | 1 + + 3 files changed, 4 insertions(+), 14 deletions(-) + +diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c +index 0086816b27cd..b33f8656edb5 100644 +--- a/drivers/ufs/core/ufs-sysfs.c ++++ b/drivers/ufs/core/ufs-sysfs.c +@@ -235,7 +235,7 @@ static int ufshcd_ahit_to_us(u32 ahit) + } + + /* Convert microseconds to Auto-Hibernate Idle Timer register value */ +-static u32 ufshcd_us_to_ahit(unsigned int timer) ++u32 ufshcd_us_to_ahit(unsigned int timer) + { + unsigned int scale; + +@@ -245,6 +245,7 @@ static u32 ufshcd_us_to_ahit(unsigned int timer) + return FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, timer) | + FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, scale); + } ++EXPORT_SYMBOL_GPL(ufshcd_us_to_ahit); + + static int ufshcd_read_hci_reg(struct ufs_hba *hba, u32 *val, unsigned int reg) + { +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 0f261c3afc34..be89cd01d920 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1109,18 +1109,6 @@ static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) + } + } + +-/* Convert microseconds to Auto-Hibernate Idle Timer register value */ +-static u32 ufs_mtk_us_to_ahit(unsigned int timer) +-{ +- unsigned int scale; +- +- for (scale = 0; timer > UFSHCI_AHIBERN8_TIMER_MASK; ++scale) +- timer /= UFSHCI_AHIBERN8_SCALE_FACTOR; +- +- return FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, timer) | +- FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, scale); +-} +- + static void ufs_mtk_fix_ahit(struct ufs_hba *hba) + { + unsigned int us; +@@ -1143,7 +1131,7 @@ static void ufs_mtk_fix_ahit(struct ufs_hba *hba) + break; + } + +- hba->ahit = ufs_mtk_us_to_ahit(us); ++ hba->ahit = ufshcd_us_to_ahit(us); + } + + ufs_mtk_setup_clk_gating(hba); +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 9f2160829d80..775a66f334a3 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1489,5 +1489,6 @@ int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, + const u16 *other_mask, u16 set, u16 clr); + void ufshcd_force_error_recovery(struct ufs_hba *hba); + void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on); ++u32 ufshcd_us_to_ahit(unsigned int timer); + + #endif /* End of Header */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch deleted file mode 100644 index c4ff341f5d..0000000000 --- a/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 3c28d26c50aa548e866a1681ca068993386a91c3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 01:06:41 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: kexec_file: Constrain segment placement - to direct map - -When kexec_file_load places segments with buf_max=ULONG_MAX and -top_down=true, they land at the highest available physical addresses. -On RISC-V the size of the linear mapping is determined by the active -VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 -extend the range substantially further. When the installed physical -memory exceeds the direct map size of the active mode, top-down -placement puts DTB/initrd at physical addresses outside the linearly -mapped region. The kexec'd kernel cannot reach them during early -boot, triggering a page fault at memcmp in start_kernel. - -Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects -the runtime direct map boundary for the active VM mode (SV39/SV48/ -SV57). This keeps all kexec segments within the linearly mapped -region while preserving the upstream top_down allocation strategy. - -Link: https://lore.kernel.org/r/20260519170641.123517-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/kernel/machine_kexec_file.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c -index dd9d92a96517..b5fe17238df2 100644 ---- a/arch/riscv/kernel/machine_kexec_file.c -+++ b/arch/riscv/kernel/machine_kexec_file.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -266,7 +267,7 @@ int load_extra_segments(struct kimage *image, unsigned long kernel_start, - - kbuf.image = image; - kbuf.buf_min = kernel_start + kernel_len; -- kbuf.buf_max = ULONG_MAX; -+ kbuf.buf_max = PFN_PHYS(max_low_pfn); - - #ifdef CONFIG_CRASH_DUMP - /* Add elfcorehdr */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0428-UPSTREAM-scsi-ufs-host-mediatek-Add-support-for-new-.patch b/SPECS/linux-lts-kmhv2/0428-UPSTREAM-scsi-ufs-host-mediatek-Add-support-for-new-.patch new file mode 100644 index 0000000000..163393188f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0428-UPSTREAM-scsi-ufs-host-mediatek-Add-support-for-new-.patch @@ -0,0 +1,142 @@ +From bf61c88d6f9960d674232aef5b2e3003d6b62dd0 Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:29 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Add support for new + platform with MMIO_OTSD_CTR + +Introduce support for a new UFS Mediatek platform by adding the +REG_UFS_UFS_MMIO_OTSD_CTRL register. This update includes checks for +legacy platforms and uses the new register to replace debug selection +and handle specific operations. The changes ensure compatibility across +different hardware versions and prevent potential issues with debug +usage on newer platforms. + +Additional updates include error logging improvements during link setup +for newer and legacy platforms, ensuring proper event logging and +debugging. + +Signed-off-by: Peter Wang +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-8-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 4fb4c835a92b6dfa3a461102ba0943b416ae7e55) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 42 +++++++++++++++++++++++++++------ + drivers/ufs/host/ufs-mediatek.h | 1 + + 2 files changed, 36 insertions(+), 7 deletions(-) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index be89cd01d920..074c988c4e3f 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -280,6 +280,9 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, + ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, + REG_UFS_XOUFS_CTRL); + ++ if (host->legacy_ip_ver) ++ return 0; ++ + /* DDR_EN setting */ + if (host->ip_ver >= IP_VER_MT6989) { + ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8), +@@ -405,7 +408,7 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba) + { + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + +- if (((host->ip_ver >> 16) & 0xFF) >= 0x36) { ++ if (!host->legacy_ip_ver && host->ip_ver >= IP_VER_MT6983) { + ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL); + ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0); + ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1); +@@ -422,6 +425,7 @@ static int ufs_mtk_wait_idle_state(struct ufs_hba *hba, + u64 timeout, time_checked; + u32 val, sm; + bool wait_idle; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + /* cannot use plain ktime_get() in suspend */ + timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL; +@@ -432,8 +436,13 @@ static int ufs_mtk_wait_idle_state(struct ufs_hba *hba, + + do { + time_checked = ktime_get_mono_fast_ns(); +- ufs_mtk_dbg_sel(hba); +- val = ufshcd_readl(hba, REG_UFS_PROBE); ++ if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { ++ ufs_mtk_dbg_sel(hba); ++ val = ufshcd_readl(hba, REG_UFS_PROBE); ++ } else { ++ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); ++ val = val >> 16; ++ } + + sm = val & 0x1f; + +@@ -465,13 +474,20 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, + { + ktime_t timeout, time_checked; + u32 val; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + timeout = ktime_add_ms(ktime_get(), max_wait_ms); + do { + time_checked = ktime_get(); +- ufs_mtk_dbg_sel(hba); +- val = ufshcd_readl(hba, REG_UFS_PROBE); +- val = val >> 28; ++ ++ if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { ++ ufs_mtk_dbg_sel(hba); ++ val = ufshcd_readl(hba, REG_UFS_PROBE); ++ val = val >> 28; ++ } else { ++ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); ++ val = val >> 24; ++ } + + if (val == state) + return 0; +@@ -1639,14 +1655,26 @@ static int ufs_mtk_device_reset(struct ufs_hba *hba) + static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) + { + int err; ++ u32 val; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + err = ufshcd_hba_enable(hba); + if (err) + return err; + + err = ufs_mtk_unipro_set_lpm(hba, false); +- if (err) ++ if (err) { ++ if (host->ip_ver < IP_VER_MT6899) { ++ ufs_mtk_dbg_sel(hba); ++ val = ufshcd_readl(hba, REG_UFS_PROBE); ++ } else { ++ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); ++ } ++ ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val); ++ val = ufshcd_readl(hba, REG_INTERRUPT_STATUS); ++ ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val); + return err; ++ } + + err = ufshcd_uic_hibern8_exit(hba); + if (err) +diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h +index dfbf78bd8664..f96fd032371d 100644 +--- a/drivers/ufs/host/ufs-mediatek.h ++++ b/drivers/ufs/host/ufs-mediatek.h +@@ -28,6 +28,7 @@ + */ + #define REG_UFS_XOUFS_CTRL 0x140 + #define REG_UFS_REFCLK_CTRL 0x144 ++#define REG_UFS_UFS_MMIO_OTSD_CTRL 0x14C + #define REG_UFS_MMIO_OPT_CTRL_0 0x160 + #define REG_UFS_EXTREG 0x2100 + #define REG_UFS_MPHYCTRL 0x2200 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch deleted file mode 100644 index 35f6ab7227..0000000000 --- a/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 66203a4e0eefa5812e80d8953dd2e958bbeaa89b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 20 May 2026 23:45:27 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: spacemit: Add K3 - CoM260-IFX board -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module -with a reference carrier board. - -The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD -card slot and includes interfaces such as dual MIPI CSI-2 connectors, -M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin -expansion header. - -The carrier board is intended as a general-purpose development platform -for CoM260 module and exposes interfaces for all of storage, display, -networking, and camera connectivity. - -Acked-by: Conor Dooley -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml -index eca403a8e49e..5273d5bdfc4e 100644 ---- a/Documentation/devicetree/bindings/riscv/spacemit.yaml -+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml -@@ -29,6 +29,11 @@ properties: - - enum: - - spacemit,k3-pico-itx - - const: spacemit,k3 -+ - items: -+ - enum: -+ - spacemit,k3-com260-ifx -+ - const: spacemit,k3-com260 -+ - const: spacemit,k3 - - additionalProperties: true - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0429-UPSTREAM-scsi-ufs-host-mediatek-Support-new-features.patch b/SPECS/linux-lts-kmhv2/0429-UPSTREAM-scsi-ufs-host-mediatek-Support-new-features.patch new file mode 100644 index 0000000000..cf6f271c0b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0429-UPSTREAM-scsi-ufs-host-mediatek-Support-new-features.patch @@ -0,0 +1,61 @@ +From ed665f9af9b48c83b5432971d4b31aa92b19d18d Mon Sep 17 00:00:00 2001 +From: Naomi Chu +Date: Wed, 24 Sep 2025 17:43:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Support new + features for MT6991 + +Add support for the MT6991 platform by enabling MRTT settings and random +performance improvements. These enhancements aim to optimize performance +and efficiency on the MT6991 hardware. + +Enable multi-Round Trip Time (MRTT) for improved data handling. Enable +random performance improvement features to boost overall system +responsiveness. + +Signed-off-by: Naomi Chu +Reviewed-by: Peter Wang +Acked-by: Chun-Hung Wu +Signed-off-by: Peter Wang +Link: https://patch.msgid.link/20250924094527.2992256-9-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 9ce37e94c30090d26df26b1bbb2fa9c51ede7651) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 6 ++++++ + drivers/ufs/host/ufs-mediatek.h | 3 +++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 074c988c4e3f..a0de39274036 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -289,6 +289,12 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, + 0x453000, REG_UFS_MMIO_OPT_CTRL_0); + } + ++ if (host->ip_ver >= IP_VER_MT6991_A0) { ++ /* Enable multi-rtt */ ++ ufshcd_rmwl(hba, MRTT_EN, MRTT_EN, REG_UFS_MMIO_OPT_CTRL_0); ++ /* Enable random performance improvement */ ++ ufshcd_rmwl(hba, RDN_PFM_IMPV_DIS, 0, REG_UFS_MMIO_OPT_CTRL_0); ++ } + } + + return 0; +diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h +index f96fd032371d..9747277f11e8 100644 +--- a/drivers/ufs/host/ufs-mediatek.h ++++ b/drivers/ufs/host/ufs-mediatek.h +@@ -20,6 +20,9 @@ + #define MCQ_MULTI_INTR_EN BIT(2) + #define MCQ_CMB_INTR_EN BIT(3) + #define MCQ_AH8 BIT(4) ++#define MON_EN BIT(5) ++#define MRTT_EN BIT(25) ++#define RDN_PFM_IMPV_DIS BIT(28) + + #define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN) + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch deleted file mode 100644 index 30fcfb32cb..0000000000 --- a/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch +++ /dev/null @@ -1,306 +0,0 @@ -From 204ddf86a80e19378811ebf324fd4e8474fa0834 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 20 May 2026 23:45:28 +0000 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Initial support for - CoM260-IFX board - -The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer -module with a carrier board. The module integrates the K3 SoC, LPDDR5, -UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers -a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, -DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. - -Add initial support for enabling Serial UART and ethernet. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/Makefile | 1 + - .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ - arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ - 4 files changed, 245 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts - create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile -index 7e2b87702571..bf233ec0683b 100644 ---- a/arch/riscv/boot/dts/spacemit/Makefile -+++ b/arch/riscv/boot/dts/spacemit/Makefile -@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb -+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb -diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts -new file mode 100644 -index 000000000000..238bb03d0e9e ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Yixun Lan -+ */ -+ -+#include "k3-com260.dtsi" -+ -+/ { -+ model = "SpacemiT K3 CoM260 IFX"; -+ compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = ð1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi -new file mode 100644 -index 000000000000..a38d7b738258 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi -@@ -0,0 +1,190 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Yixun Lan -+ */ -+#include -+ -+#include "k3.dtsi" -+#include "k3-pinctrl.dtsi" -+ -+/ { -+ model = "SpacemiT K3 CoM260 Module"; -+ compatible = "spacemit,k3-com260", "spacemit,k3"; -+ -+ memory@100000000 { -+ device_type = "memory"; -+ reg = <0x1 0x00000000 0x4 0x00000000>; -+ }; -+ -+ reg_5v_sys: regulator-5v-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "P5V0_SYS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -+ vin1-supply = <®_5v_sys>; -+ vin2-supply = <®_5v_sys>; -+ vin3-supply = <®_5v_sys>; -+ vin4-supply = <®_5v_sys>; -+ vin5-supply = <®_5v_sys>; -+ vin6-supply = <®_5v_sys>; -+ aldoin-supply = <®_5v_sys>; -+ dldoin1-supply = <&buck4>; -+ dldoin2-supply = <&buck4>; -+ -+ regulators { -+ buck1: buck1 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2: buck2 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3: buck3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4: buck4 { -+ regulator-min-microvolt = <2100000>; -+ regulator-max-microvolt = <2100000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6: buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <500000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo2: aldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo3: aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4: aldo4 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo1: dldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo2: dldo2 { -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo3: dldo3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo4: dldo4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ dldo5: dldo5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo6: dldo6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo7: dldo7 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+}; -+ -+ð1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy1>; -+ status = "okay"; -+ -+ mdio { -+ phy1: phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <10000>; -+ }; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_0_cfg>; -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index dffa4d583bb2..846d5e8cc783 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -45,6 +45,39 @@ gmac0-phy-0-pins { - }; - }; - -+ gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { -+ gmac1-rgmii-0-pins { -+ pinmux = , /* gmac1_rxdv */ -+ , /* gmac1 rx d0 */ -+ , /* gmac1 rx d1 */ -+ , /* gmac1 rx_clk */ -+ , /* gmac1 rx d2 */ -+ , /* gmac1 rx d3 */ -+ , /* gmac1 tx d0 */ -+ , /* gmac1 tx d1 */ -+ , /* gmac1 tx clk */ -+ , /* gmac1 tx d2 */ -+ , /* gmac1 tx d3 */ -+ , /* gmac1 tx_en */ -+ , /* gmac1 mdc */ -+ ; /* gmac1 mdio */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ gmac1_phy_0_cfg: gmac1-phy-0-cfg { -+ gmac1-phy-0-pins { -+ pinmux = ; /* gmac1 int */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ - /omit-if-no-ref/ - i2c8_cfg: i2c8-cfg { - i2c8-pins { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0430-UPSTREAM-scsi-ufs-core-Introduce-a-new-ufshcd-vops-n.patch b/SPECS/linux-lts-kmhv2/0430-UPSTREAM-scsi-ufs-core-Introduce-a-new-ufshcd-vops-n.patch new file mode 100644 index 0000000000..a9ddcdf9eb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0430-UPSTREAM-scsi-ufs-core-Introduce-a-new-ufshcd-vops-n.patch @@ -0,0 +1,583 @@ +From d68daa72d4d5317e8a3494174341147459848a9f Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:43 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Introduce a new ufshcd vops + negotiate_pwr_mode() + +Most vendor specific implemenations of vops pwr_change_notify(PRE_CHANGE) +are fulfilling two things at once: + + - Vendor specific target power mode negotiation + + - Vendor specific power mode change preparation + +When TX Equalization is added into consideration, before power mode change +to a target power mode, TX Equalization Training (EQTR) needs be done for +that target power mode. In addition, UFSHCI spec requires to start TX EQTR +from HS-G1 (the most reliable High Speed Gear). + +Adding TX EQTR before pwr_change_notify(PRE_CHANGE) is not applicable +because we don't know the negotiated power mode yet. + +Adding TX EQTR post pwr_change_notify(PRE_CHANGE) is inappropriate because +pwr_change_notify(PRE_CHANGE) has finished preparation for a power mode +change to negotiated power mode, yet we are changing power mode to HS-G1 +for TX EQTR. + +Add a new vops negotiate_pwr_mode() so that vendor specific power mode +negotiation can be fulfilled in its vendor specific implementations. Later +on, TX EQTR can be added post vops negotiate_pwr_mode() and before vops +pwr_change_notify(PRE_CHANGE). + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-2-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit d3eba21c71708746672587f1de2cc33e6a10d61a) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd-priv.h | 14 +++++- + drivers/ufs/core/ufshcd.c | 70 ++++++++++++++++++++++++------ + drivers/ufs/host/ufs-amd-versal2.c | 3 -- + drivers/ufs/host/ufs-exynos.c | 34 +++++++-------- + drivers/ufs/host/ufs-hisi.c | 23 +++++----- + drivers/ufs/host/ufs-mediatek.c | 40 ++++++++--------- + drivers/ufs/host/ufs-qcom.c | 24 +++++----- + drivers/ufs/host/ufs-sprd.c | 3 -- + drivers/ufs/host/ufshcd-pci.c | 6 +-- + include/ufs/ufshcd.h | 17 +++++--- + 10 files changed, 143 insertions(+), 91 deletions(-) + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 3ccbbdb18a24..087ebf43b09d 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -168,14 +168,24 @@ static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, + return 0; + } + ++static inline int ufshcd_vops_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ if (hba->vops && hba->vops->negotiate_pwr_mode) ++ return hba->vops->negotiate_pwr_mode(hba, dev_max_params, ++ dev_req_params); ++ ++ return -ENOTSUPP; ++} ++ + static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + if (hba->vops && hba->vops->pwr_change_notify) + return hba->vops->pwr_change_notify(hba, status, +- dev_max_params, dev_req_params); ++ dev_req_params); + + return -ENOTSUPP; + } +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 80c504e270b6..5c7b48664147 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -333,8 +333,6 @@ static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); + static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, + bool scale_up); + static irqreturn_t ufshcd_intr(int irq, void *__hba); +-static int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode); + static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); + static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); + static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, +@@ -4666,8 +4664,26 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) + return 0; + } + +-static int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++/** ++ * ufshcd_dme_change_power_mode() - UniPro DME Power Mode change sequence ++ * @hba: per-adapter instance ++ * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * ++ * This function handles the low-level DME (Device Management Entity) ++ * configuration required to transition the UFS link to a new power mode. It ++ * performs the following steps: ++ * 1. Checks if the requested mode matches the current state. ++ * 2. Sets M-PHY and UniPro attributes including Gear (PA_RXGEAR/TXGEAR), ++ * Lanes, Termination, and HS Series (PA_HSSERIES). ++ * 3. Configures default UniPro timeout values (DL_FC0, etc.) unless ++ * explicitly skipped via quirks. ++ * 4. Triggers the actual hardware mode change via ufshcd_uic_change_pwr_mode(). ++ * 5. Updates the HBA's cached power information on success. ++ * ++ * Return: 0 on success, non-zero error code on failure. ++ */ ++static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) + { + int ret; + +@@ -4751,6 +4767,34 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba, + return ret; + } + ++/** ++ * ufshcd_change_power_mode() - Change UFS Link Power Mode ++ * @hba: per-adapter instance ++ * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * ++ * This function handles the high-level sequence for changing the UFS link ++ * power mode. It triggers vendor-specific pre-change notification, ++ * executes the DME (Device Management Entity) power mode change sequence, ++ * and, upon success, triggers vendor-specific post-change notification. ++ * ++ * Return: 0 on success, non-zero error code on failure. ++ */ ++int ufshcd_change_power_mode(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ int ret; ++ ++ ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, pwr_mode); ++ ++ ret = ufshcd_dme_change_power_mode(hba, pwr_mode); ++ ++ if (!ret) ++ ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, pwr_mode); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ufshcd_change_power_mode); ++ + /** + * ufshcd_config_pwr_mode - configure a new power mode + * @hba: per-adapter instance +@@ -4764,19 +4808,17 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr final_params = { 0 }; + int ret; + +- ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, +- desired_pwr_mode, &final_params); ++ ret = ufshcd_vops_negotiate_pwr_mode(hba, desired_pwr_mode, ++ &final_params); ++ if (ret) { ++ if (ret != -ENOTSUPP) ++ dev_err(hba->dev, "Failed to negotiate power mode: %d, use desired as is\n", ++ ret); + +- if (ret) + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); ++ } + +- ret = ufshcd_change_power_mode(hba, &final_params); +- +- if (!ret) +- ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, +- &final_params); +- +- return ret; ++ return ufshcd_change_power_mode(hba, &final_params); + } + EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); + +diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c +index 6c454ae8a9c8..2154d6286817 100644 +--- a/drivers/ufs/host/ufs-amd-versal2.c ++++ b/drivers/ufs/host/ufs-amd-versal2.c +@@ -443,7 +443,6 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_ + } + + static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_versal2_host *host = ufshcd_get_variant(hba); +@@ -451,8 +450,6 @@ static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_ch + int ret = 0; + + if (status == PRE_CHANGE) { +- memcpy(dev_req_params, dev_max_params, sizeof(struct ufs_pa_layer_attr)); +- + /* If it is not a calibrated part, switch PWRMODE to SLOW_MODE */ + if (!host->attcompval0 && !host->attcompval1 && !host->ctlecompval0 && + !host->ctlecompval1) { +diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c +index 70d195179eba..3230c8ffff0b 100644 +--- a/drivers/ufs/host/ufs-exynos.c ++++ b/drivers/ufs/host/ufs-exynos.c +@@ -818,12 +818,10 @@ static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba) + } + + static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct exynos_ufs *ufs = ufshcd_get_variant(hba); + struct phy *generic_phy = ufs->phy; +- struct ufs_host_params host_params; + int ret; + + if (!dev_req_params) { +@@ -832,18 +830,6 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, + goto out; + } + +- ufshcd_init_host_params(&host_params); +- +- /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ +- host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); +- host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); +- +- ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); +- if (ret) { +- pr_err("%s: failed to determine capabilities\n", __func__); +- goto out; +- } +- + if (ufs->drv_data->pre_pwr_change) + ufs->drv_data->pre_pwr_change(ufs, dev_req_params); + +@@ -1667,17 +1653,30 @@ static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, + return ret; + } + ++static int exynos_ufs_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ ++ ufshcd_init_host_params(&host_params); ++ ++ /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ ++ host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); ++ host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); ++ ++ return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); ++} ++ + static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + int ret = 0; + + switch (status) { + case PRE_CHANGE: +- ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, +- dev_req_params); ++ ret = exynos_ufs_pre_pwr_mode(hba, dev_req_params); + break; + case POST_CHANGE: + ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); +@@ -2005,6 +2004,7 @@ static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = { + .exit = exynos_ufs_exit, + .hce_enable_notify = exynos_ufs_hce_enable_notify, + .link_startup_notify = exynos_ufs_link_startup_notify, ++ .negotiate_pwr_mode = exynos_ufs_negotiate_pwr_mode, + .pwr_change_notify = exynos_ufs_pwr_change_notify, + .setup_clocks = exynos_ufs_setup_clocks, + .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req, +diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c +index 6f2e6bf31225..993e20ac211d 100644 +--- a/drivers/ufs/host/ufs-hisi.c ++++ b/drivers/ufs/host/ufs-hisi.c +@@ -298,6 +298,17 @@ static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params) + ufshcd_init_host_params(host_params); + } + ++static int ufs_hisi_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ ++ ufs_hisi_set_dev_cap(&host_params); ++ ++ return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); ++} ++ + static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) + { + struct ufs_hisi_host *host = ufshcd_get_variant(hba); +@@ -362,10 +373,8 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) + + static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { +- struct ufs_host_params host_params; + int ret = 0; + + if (!dev_req_params) { +@@ -377,14 +386,6 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + + switch (status) { + case PRE_CHANGE: +- ufs_hisi_set_dev_cap(&host_params); +- ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); +- if (ret) { +- dev_err(hba->dev, +- "%s: failed to determine capabilities\n", __func__); +- goto out; +- } +- + ufs_hisi_pwr_change_pre_change(hba); + break; + case POST_CHANGE: +@@ -543,6 +544,7 @@ static const struct ufs_hba_variant_ops ufs_hba_hi3660_vops = { + .name = "hi3660", + .init = ufs_hi3660_init, + .link_startup_notify = ufs_hisi_link_startup_notify, ++ .negotiate_pwr_mode = ufs_hisi_negotiate_pwr_mode, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +@@ -552,6 +554,7 @@ static const struct ufs_hba_variant_ops ufs_hba_hi3670_vops = { + .name = "hi3670", + .init = ufs_hi3670_init, + .link_startup_notify = ufs_hisi_link_startup_notify, ++ .negotiate_pwr_mode = ufs_hisi_negotiate_pwr_mode, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index a0de39274036..49a83e074926 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1318,6 +1318,23 @@ static int ufs_mtk_init(struct ufs_hba *hba) + return err; + } + ++static int ufs_mtk_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ ++ ufshcd_init_host_params(&host_params); ++ host_params.hs_rx_gear = UFS_HS_G5; ++ host_params.hs_tx_gear = UFS_HS_G5; ++ ++ if (dev_max_params->pwr_rx == SLOW_MODE || ++ dev_max_params->pwr_tx == SLOW_MODE) ++ host_params.desired_working_mode = UFS_PWM_MODE; ++ ++ return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); ++} ++ + static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba, + struct ufs_pa_layer_attr *dev_req_params) + { +@@ -1373,26 +1390,10 @@ static void ufs_mtk_adjust_sync_length(struct ufs_hba *hba) + } + + static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_mtk_host *host = ufshcd_get_variant(hba); +- struct ufs_host_params host_params; +- int ret; +- +- ufshcd_init_host_params(&host_params); +- host_params.hs_rx_gear = UFS_HS_G5; +- host_params.hs_tx_gear = UFS_HS_G5; +- +- if (dev_max_params->pwr_rx == SLOW_MODE || +- dev_max_params->pwr_tx == SLOW_MODE) +- host_params.desired_working_mode = UFS_PWM_MODE; +- +- ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); +- if (ret) { +- pr_info("%s: failed to determine capabilities\n", +- __func__); +- } ++ int ret = 0; + + if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) { + ufs_mtk_adjust_sync_length(hba); +@@ -1504,7 +1505,6 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba) + + static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status stage, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + int ret = 0; +@@ -1516,8 +1516,7 @@ static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba, + reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + ufs_mtk_auto_hibern8_disable(hba); + } +- ret = ufs_mtk_pre_pwr_change(hba, dev_max_params, +- dev_req_params); ++ ret = ufs_mtk_pre_pwr_change(hba, dev_req_params); + break; + case POST_CHANGE: + if (ufshcd_is_auto_hibern8_supported(hba)) +@@ -2321,6 +2320,7 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = { + .setup_clocks = ufs_mtk_setup_clocks, + .hce_enable_notify = ufs_mtk_hce_enable_notify, + .link_startup_notify = ufs_mtk_link_startup_notify, ++ .negotiate_pwr_mode = ufs_mtk_negotiate_pwr_mode, + .pwr_change_notify = ufs_mtk_pwr_change_notify, + .apply_dev_quirks = ufs_mtk_apply_dev_quirks, + .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks, +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index eba0e6617483..fec0ecad6be1 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -917,13 +917,21 @@ static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_l + } + } + +-static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, +- enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, +- struct ufs_pa_layer_attr *dev_req_params) ++static int ufs_qcom_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_host_params *host_params = &host->host_params; ++ ++ return ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); ++} ++ ++static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int ret = 0; + + if (!dev_req_params) { +@@ -933,13 +941,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, + + switch (status) { + case PRE_CHANGE: +- ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); +- if (ret) { +- dev_err(hba->dev, "%s: failed to determine capabilities\n", +- __func__); +- return ret; +- } +- + /* + * During UFS driver probe, always update the PHY gear to match the negotiated + * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, +@@ -2218,6 +2219,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .setup_clocks = ufs_qcom_setup_clocks, + .hce_enable_notify = ufs_qcom_hce_enable_notify, + .link_startup_notify = ufs_qcom_link_startup_notify, ++ .negotiate_pwr_mode = ufs_qcom_negotiate_pwr_mode, + .pwr_change_notify = ufs_qcom_pwr_change_notify, + .apply_dev_quirks = ufs_qcom_apply_dev_quirks, + .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, +diff --git a/drivers/ufs/host/ufs-sprd.c b/drivers/ufs/host/ufs-sprd.c +index 65bd8fb96b99..a5e8c591bead 100644 +--- a/drivers/ufs/host/ufs-sprd.c ++++ b/drivers/ufs/host/ufs-sprd.c +@@ -161,14 +161,11 @@ static int ufs_sprd_common_init(struct ufs_hba *hba) + + static int sprd_ufs_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_sprd_host *host = ufshcd_get_variant(hba); + + if (status == PRE_CHANGE) { +- memcpy(dev_req_params, dev_max_params, +- sizeof(struct ufs_pa_layer_attr)); + if (host->unipro_ver >= UFS_UNIPRO_VER_1_8) + ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, + PA_INITIAL_ADAPT); +diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c +index 5f65dfad1a71..8a4f2381a32e 100644 +--- a/drivers/ufs/host/ufshcd-pci.c ++++ b/drivers/ufs/host/ufshcd-pci.c +@@ -145,7 +145,7 @@ static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) + + pwr_info.lane_rx = lanes; + pwr_info.lane_tx = lanes; +- ret = ufshcd_config_pwr_mode(hba, &pwr_info); ++ ret = ufshcd_change_power_mode(hba, &pwr_info); + if (ret) + dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n", + __func__, lanes, ret); +@@ -154,17 +154,15 @@ static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) + + static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + int err = 0; + + switch (status) { + case PRE_CHANGE: +- if (ufshcd_is_hs_mode(dev_max_params) && ++ if (ufshcd_is_hs_mode(dev_req_params) && + (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2)) + ufs_intel_set_lanes(hba, 2); +- memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params)); + break; + case POST_CHANGE: + if (ufshcd_is_hs_mode(dev_req_params)) { +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 775a66f334a3..eb6e8e9b6433 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -307,11 +307,10 @@ struct ufs_pwr_mode_info { + * variant specific Uni-Pro initialization. + * @link_startup_notify: called before and after Link startup is carried out + * to allow variant specific Uni-Pro initialization. ++ * @negotiate_pwr_mode: called to negotiate power mode. + * @pwr_change_notify: called before and after a power mode change + * is carried out to allow vendor spesific capabilities +- * to be set. PRE_CHANGE can modify final_params based +- * on desired_pwr_mode, but POST_CHANGE must not alter +- * the final_params parameter ++ * to be set. + * @setup_xfer_req: called before any transfer request is issued + * to set some things + * @setup_task_mgmt: called before any task management request is issued +@@ -352,10 +351,12 @@ struct ufs_hba_variant_ops { + enum ufs_notify_change_status); + int (*link_startup_notify)(struct ufs_hba *, + enum ufs_notify_change_status); +- int (*pwr_change_notify)(struct ufs_hba *, +- enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *desired_pwr_mode, +- struct ufs_pa_layer_attr *final_params); ++ int (*negotiate_pwr_mode)(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *desired_pwr_mode, ++ struct ufs_pa_layer_attr *final_params); ++ int (*pwr_change_notify)(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *final_params); + void (*setup_xfer_req)(struct ufs_hba *hba, int tag, + bool is_scsi_cmd); + void (*setup_task_mgmt)(struct ufs_hba *, int, u8); +@@ -1370,6 +1371,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, + u8 attr_set, u32 mib_val, u8 peer); + extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer); ++extern int ufshcd_change_power_mode(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode); + extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *desired_pwr_mode); + extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch deleted file mode 100644 index 70f7cc89e9..0000000000 --- a/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 78d249e0f67dafbf778883d6990fcb4c34638969 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Wed, 20 May 2026 18:00:00 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PMIC on OrangePi - R2S - -Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and -its associated regulators to support voltage regulation on the board. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260520100000.575719-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ - 1 file changed, 134 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index 1ecc40749e5a..b13a8d6a2670 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -13,6 +13,7 @@ / { - compatible = "xunlong,orangepi-r2s", "spacemit,k1"; - - aliases { -+ i2c8 = &i2c8; - serial0 = &uart0; - ethernet0 = ð0; - ethernet1 = ð1; -@@ -22,6 +23,15 @@ chosen { - stdout-path = "serial0"; - }; - -+ vcc4v0: regulator-vcc4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ }; -+ - vcc5v0_usb: regulator-vcc5v0-usb { - compatible = "regulator-fixed"; - enable-active-high; -@@ -94,6 +104,130 @@ rgmii1: phy@1 { - }; - }; - -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <&vcc4v0>; -+ vin2-supply = <&vcc4v0>; -+ vin3-supply = <&vcc4v0>; -+ vin4-supply = <&vcc4v0>; -+ vin5-supply = <&vcc4v0>; -+ vin6-supply = <&vcc4v0>; -+ aldoin-supply = <&vcc4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4_3v3: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1_3v3: aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; -+}; -+ - &pdma { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0431-UPSTREAM-scsi-ufs-core-Pass-force_pmc-to-ufshcd_conf.patch b/SPECS/linux-lts-kmhv2/0431-UPSTREAM-scsi-ufs-core-Pass-force_pmc-to-ufshcd_conf.patch new file mode 100644 index 0000000000..b1da5ed091 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0431-UPSTREAM-scsi-ufs-core-Pass-force_pmc-to-ufshcd_conf.patch @@ -0,0 +1,228 @@ +From 64b849ace44e88370c33ba1e12ad636feaa2a9c8 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:44 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Pass force_pmc to + ufshcd_config_pwr_mode() as a parameter + +Currently, callers must manually toggle hba->force_pmc before and after +calling ufshcd_config_pwr_mode() to force a Power Mode change. Introduce +enum ufshcd_pmc_policy and refactor ufshcd_config_pwr_mode() to accept +pmc_policy as a parameter to force a Power Mode change. + +Reviewed-by: Bart Van Assche +Reviewed-by: Bean Huo +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-3-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit c91c83671642d6140b703e999e2aff2d7ad57c74) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd.c | 35 ++++++++++++++++++++++------------- + drivers/ufs/host/ufshcd-pci.c | 3 ++- + include/ufs/ufshcd.h | 19 +++++++++++++++---- + 3 files changed, 39 insertions(+), 18 deletions(-) + +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 5c7b48664147..25ff3629df99 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -1406,7 +1406,8 @@ static int ufshcd_scale_gear(struct ufs_hba *hba, u32 target_gear, bool scale_up + + config_pwr_mode: + /* check if the power mode needs to be changed or not? */ +- ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); ++ ret = ufshcd_config_pwr_mode(hba, &new_pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) + dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", + __func__, ret, +@@ -4260,7 +4261,8 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + pwr_mode_change = true; + } + if (pwr_mode_change) { +- ret = ufshcd_change_power_mode(hba, &temp_pwr_info); ++ ret = ufshcd_change_power_mode(hba, &temp_pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) + goto out; + } +@@ -4284,7 +4286,8 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + + if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) + && pwr_mode_change) +- ufshcd_change_power_mode(hba, &orig_pwr_info); ++ ufshcd_change_power_mode(hba, &orig_pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + out: + return ret; + } +@@ -4668,6 +4671,7 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) + * ufshcd_dme_change_power_mode() - UniPro DME Power Mode change sequence + * @hba: per-adapter instance + * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * @pmc_policy: Power Mode change policy + * + * This function handles the low-level DME (Device Management Entity) + * configuration required to transition the UFS link to a new power mode. It +@@ -4683,12 +4687,13 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) + * Return: 0 on success, non-zero error code on failure. + */ + static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++ struct ufs_pa_layer_attr *pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy) + { + int ret; + + /* if already configured to the requested pwr_mode */ +- if (!hba->force_pmc && ++ if (pmc_policy == UFSHCD_PMC_POLICY_DONT_FORCE && + pwr_mode->gear_rx == hba->pwr_info.gear_rx && + pwr_mode->gear_tx == hba->pwr_info.gear_tx && + pwr_mode->lane_rx == hba->pwr_info.lane_rx && +@@ -4771,6 +4776,7 @@ static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, + * ufshcd_change_power_mode() - Change UFS Link Power Mode + * @hba: per-adapter instance + * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * @pmc_policy: Power Mode change policy + * + * This function handles the high-level sequence for changing the UFS link + * power mode. It triggers vendor-specific pre-change notification, +@@ -4780,13 +4786,14 @@ static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, + * Return: 0 on success, non-zero error code on failure. + */ + int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++ struct ufs_pa_layer_attr *pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy) + { + int ret; + + ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, pwr_mode); + +- ret = ufshcd_dme_change_power_mode(hba, pwr_mode); ++ ret = ufshcd_dme_change_power_mode(hba, pwr_mode, pmc_policy); + + if (!ret) + ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, pwr_mode); +@@ -4799,11 +4806,13 @@ EXPORT_SYMBOL_GPL(ufshcd_change_power_mode); + * ufshcd_config_pwr_mode - configure a new power mode + * @hba: per-adapter instance + * @desired_pwr_mode: desired power configuration ++ * @pmc_policy: Power Mode change policy + * + * Return: 0 upon success; < 0 upon failure. + */ + int ufshcd_config_pwr_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *desired_pwr_mode) ++ struct ufs_pa_layer_attr *desired_pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy) + { + struct ufs_pa_layer_attr final_params = { 0 }; + int ret; +@@ -4818,7 +4827,7 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); + } + +- return ufshcd_change_power_mode(hba, &final_params); ++ return ufshcd_change_power_mode(hba, &final_params, pmc_policy); + } + EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); + +@@ -6857,14 +6866,13 @@ static void ufshcd_err_handler(struct work_struct *work) + * are sent via bsg and/or sysfs. + */ + down_write(&hba->clk_scaling_lock); +- hba->force_pmc = true; +- pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); ++ pmc_err = ufshcd_config_pwr_mode(hba, &hba->pwr_info, ++ UFSHCD_PMC_POLICY_FORCE); + if (pmc_err) { + needs_reset = true; + dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", + __func__, pmc_err); + } +- hba->force_pmc = false; + ufshcd_print_pwr_info(hba); + up_write(&hba->clk_scaling_lock); + spin_lock_irqsave(hba->host->host_lock, flags); +@@ -9107,7 +9115,8 @@ static int ufshcd_post_device_init(struct ufs_hba *hba) + if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) + ufshcd_set_dev_ref_clk(hba); + /* Gear up to HS gear. */ +- ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); ++ ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) { + dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", + __func__, ret); +diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c +index 8a4f2381a32e..38d458711c99 100644 +--- a/drivers/ufs/host/ufshcd-pci.c ++++ b/drivers/ufs/host/ufshcd-pci.c +@@ -145,7 +145,8 @@ static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) + + pwr_info.lane_rx = lanes; + pwr_info.lane_tx = lanes; +- ret = ufshcd_change_power_mode(hba, &pwr_info); ++ ret = ufshcd_change_power_mode(hba, &pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) + dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n", + __func__, lanes, ret); +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index eb6e8e9b6433..c33060f24dfd 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -534,6 +534,17 @@ enum ufshcd_state { + UFSHCD_STATE_ERROR, + }; + ++/** ++ * enum ufshcd_pmc_policy - Power Mode change policy ++ * @UFSHCD_PMC_POLICY_DONT_FORCE: Do not force a Power Mode change. ++ * @UFSHCD_PMC_POLICY_FORCE: Force a Power Mode change even if current Power ++ * Mode is same as target Power Mode. ++ */ ++enum ufshcd_pmc_policy { ++ UFSHCD_PMC_POLICY_DONT_FORCE, ++ UFSHCD_PMC_POLICY_FORCE, ++}; ++ + enum ufshcd_quirks { + /* Interrupt aggregation support is broken */ + UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, +@@ -888,7 +899,6 @@ enum ufshcd_mcq_opr { + * @saved_uic_err: sticky UIC error mask + * @ufs_stats: various error counters + * @force_reset: flag to force eh_work perform a full reset +- * @force_pmc: flag to force a power mode change + * @silence_err_logs: flag to silence error logs + * @dev_cmd: ufs device management command information + * @last_dme_cmd_tstamp: time stamp of the last completed DME command +@@ -1045,7 +1055,6 @@ struct ufs_hba { + u32 saved_uic_err; + struct ufs_stats ufs_stats; + bool force_reset; +- bool force_pmc; + bool silence_err_logs; + + /* Device management request data */ +@@ -1372,9 +1381,11 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, + extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer); + extern int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode); ++ struct ufs_pa_layer_attr *pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy); + extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *desired_pwr_mode); ++ struct ufs_pa_layer_attr *desired_pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy); + extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); + + /* UIC command interfaces for DME primitives */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch deleted file mode 100644 index 5e9e4db788..0000000000 --- a/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 6aa02cc299f6c36d323e193ab8c1f6118e33d3f9 Mon Sep 17 00:00:00 2001 -From: Jennifer Berringer -Date: Wed, 20 May 2026 07:11:50 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on - OrangePi RV2 - -Set the baud rate to 115200, matching what is used by U-Boot on this -platform so that the console is usable even when console options are not -specified in cmdline. - -Fixes: bab8dea259100 ("riscv: dts: spacemit: Add OrangePi RV2 board device tree") -Signed-off-by: Jennifer Berringer -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520111150.3300707-1-jberring@redhat.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 0b4d4d1418e2..131062325e08 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -22,7 +22,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - pcie_vcc3v3: regulator-pcie-vcc3v3 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0432-UPSTREAM-scsi-ufs-core-Add-UFS_HS_G6-and-UFS_HS_GEAR.patch b/SPECS/linux-lts-kmhv2/0432-UPSTREAM-scsi-ufs-core-Add-UFS_HS_G6-and-UFS_HS_GEAR.patch new file mode 100644 index 0000000000..234f301265 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0432-UPSTREAM-scsi-ufs-core-Add-UFS_HS_G6-and-UFS_HS_GEAR.patch @@ -0,0 +1,39 @@ +From 2fc2775dc1e08879e18a10daa482189df2a84adc Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:45 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add UFS_HS_G6 and + UFS_HS_GEAR_MAX to enum ufs_hs_gear_tag + +Add UFS_HS_G6 to enum ufs_hs_gear_tag. In addition, add UFS_HS_GEAR_MAX to +enum ufs_hs_gear_tag to facilitate iteration over valid High Speed Gears. + +Reviewed-by: Bart Van Assche +Reviewed-by: Bean Huo +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-4-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 6669ab18c2238299a685ada1acea1c7d4f1da1d5) +Signed-off-by: Han Gao +--- + include/ufs/unipro.h | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 59de737490ca..71a5f643400c 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -233,7 +233,9 @@ enum ufs_hs_gear_tag { + UFS_HS_G2, /* HS Gear 2 */ + UFS_HS_G3, /* HS Gear 3 */ + UFS_HS_G4, /* HS Gear 4 */ +- UFS_HS_G5 /* HS Gear 5 */ ++ UFS_HS_G5, /* HS Gear 5 */ ++ UFS_HS_G6, /* HS Gear 6 */ ++ UFS_HS_GEAR_MAX = UFS_HS_G6, + }; + + enum ufs_lanes { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch b/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch deleted file mode 100644 index cd9e99e6c3..0000000000 --- a/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 82b7ff76828e1cb4e0a7b4cf12583f33f99e37bc Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 25 May 2026 12:23:29 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Call mark_new_valid_map() after - hotplugging vmemmap - -section_activate() creates new mappings in the vmemmap range without -flushing TLB, which may cause faults on some RISC-V implementations that -cache non-present PTEs and crashes. - -This seems to be most easily reproduced with DEBUG_VM=y and -PAGE_POISONING=y, which causes these newly mapped struct pages to be -poisoned i.e. written to immediately after mapping. - -Add a hook vmemmap_populate_finalize() in __populate_section_memmap(), -and implement it as calling mark_new_valid_map() on RISC-V, which -arranges for the exception handler to deal with these faults if they -happen. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260525-mark-after-vmemmap-populate-v1-1-e698d859ba16@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 6 ++++++ - include/linux/mm.h | 1 + - mm/sparse-vmemmap.c | 6 ++++++ - 3 files changed, 13 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index ac5bece70736..4f39ba717d59 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -1502,6 +1502,12 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, - */ - return vmemmap_populate_hugepages(start, end, node, altmap); - } -+ -+void __meminit vmemmap_populate_finalize(void) -+{ -+ /* Avoid faults on cached non-present TLB entries. */ -+ mark_new_valid_map(); -+} - #endif - - #if defined(CONFIG_MMU) && defined(CONFIG_64BIT) -diff --git a/include/linux/mm.h b/include/linux/mm.h -index 1e74eb7267ac..f75348d9364b 100644 ---- a/include/linux/mm.h -+++ b/include/linux/mm.h -@@ -3995,6 +3995,7 @@ int vmemmap_populate_hugepages(unsigned long start, unsigned long end, - int node, struct vmem_altmap *altmap); - int vmemmap_populate(unsigned long start, unsigned long end, int node, - struct vmem_altmap *altmap); -+void vmemmap_populate_finalize(void); - int vmemmap_populate_hvo(unsigned long start, unsigned long end, int node, - unsigned long headsize); - int vmemmap_undo_hvo(unsigned long start, unsigned long end, int node, -diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c -index 37522d6cb398..3fa299ce0938 100644 ---- a/mm/sparse-vmemmap.c -+++ b/mm/sparse-vmemmap.c -@@ -558,6 +558,10 @@ static int __meminit vmemmap_populate_compound_pages(unsigned long start_pfn, - - #endif - -+void __weak __meminit vmemmap_populate_finalize(void) -+{ -+} -+ - struct page * __meminit __populate_section_memmap(unsigned long pfn, - unsigned long nr_pages, int nid, struct vmem_altmap *altmap, - struct dev_pagemap *pgmap) -@@ -575,6 +579,8 @@ struct page * __meminit __populate_section_memmap(unsigned long pfn, - else - r = vmemmap_populate(start, end, nid, altmap); - -+ vmemmap_populate_finalize(); -+ - if (r < 0) - return NULL; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0433-UPSTREAM-scsi-ufs-core-Add-support-for-TX-Equalizati.patch b/SPECS/linux-lts-kmhv2/0433-UPSTREAM-scsi-ufs-core-Add-support-for-TX-Equalizati.patch new file mode 100644 index 0000000000..517d920365 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0433-UPSTREAM-scsi-ufs-core-Add-support-for-TX-Equalizati.patch @@ -0,0 +1,1798 @@ +From 08a695c27dd58d49d7657805c5ea6471716a23ca Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:46 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add support for TX + Equalization + +MIPI Unipro3.0 introduced PA_TxEQGnSetting and PA_PreCodeEn attributes for +TX Equalization and Pre-Coding. It is Host Software's responsibility to +configure these attributes for both host and device before initiating Power +Mode Change to High-Speed Gears. + +MIPI Unipro3.0 also introduced TX Equalization Training (EQTR) to identify +optimal TX Equalization settings for use by both Host's and Device's +UniPro. TX EQTR shall be initiated from the most reliable High-Speed Gear +(HS-G1) targeting High-Speed Gears (HS-G4 to HS-G6). + +Implement TX Equalization configuration and TX EQTR procedure as defined +in UFSHCI v5.0 specification. The TX EQTR procedure determines the optimal +TX Equalization settings by iterating through all possible PreShoot and +DeEmphasis combinations and selecting the best combinations for both Host +and Device based on Figure of Merit (FOM) evaluation. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-5-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 03e5d38e2f985d8d0b0a60508c0b422f664808e3) +Signed-off-by: Han Gao +--- + drivers/ufs/core/Makefile | 2 +- + drivers/ufs/core/ufs-txeq.c | 1186 ++++++++++++++++++++++++++++++++ + drivers/ufs/core/ufshcd-priv.h | 38 + + drivers/ufs/core/ufshcd.c | 50 +- + include/ufs/ufshcd.h | 135 ++++ + include/ufs/unipro.h | 114 ++- + 6 files changed, 1516 insertions(+), 9 deletions(-) + create mode 100644 drivers/ufs/core/ufs-txeq.c + +diff --git a/drivers/ufs/core/Makefile b/drivers/ufs/core/Makefile +index 51e1867e524e..ce7d16d2cf35 100644 +--- a/drivers/ufs/core/Makefile ++++ b/drivers/ufs/core/Makefile +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + + obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o +-ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ++ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ufs-txeq.o + ufshcd-core-$(CONFIG_RPMB) += ufs-rpmb.o + ufshcd-core-$(CONFIG_DEBUG_FS) += ufs-debugfs.o + ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +new file mode 100644 +index 000000000000..04f9f1ffa43e +--- /dev/null ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -0,0 +1,1186 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Qualcomm Technologies, Inc. ++ * ++ * Author: ++ * Can Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ufshcd-priv.h" ++ ++static bool use_adaptive_txeq; ++module_param(use_adaptive_txeq, bool, 0644); ++MODULE_PARM_DESC(use_adaptive_txeq, "Find and apply optimal TX Equalization settings before changing Power Mode (default: false)"); ++ ++static int txeq_gear_set(const char *val, const struct kernel_param *kp) ++{ ++ return param_set_uint_minmax(val, kp, UFS_HS_G1, UFS_HS_GEAR_MAX); ++} ++ ++static const struct kernel_param_ops txeq_gear_ops = { ++ .set = txeq_gear_set, ++ .get = param_get_uint, ++}; ++ ++static unsigned int adaptive_txeq_gear = UFS_HS_G6; ++module_param_cb(adaptive_txeq_gear, &txeq_gear_ops, &adaptive_txeq_gear, 0644); ++MODULE_PARM_DESC(adaptive_txeq_gear, "For HS-Gear[n] and above, adaptive txeq shall be used"); ++ ++static bool use_txeq_presets; ++module_param(use_txeq_presets, bool, 0644); ++MODULE_PARM_DESC(use_txeq_presets, "Use only the 8 TX Equalization Presets (pre-defined Pre-Shoot & De-Emphasis combinations) for TX EQTR (default: false)"); ++ ++static bool txeq_presets_selected[UFS_TX_EQ_PRESET_MAX] = {[0 ... (UFS_TX_EQ_PRESET_MAX - 1)] = 1}; ++module_param_array(txeq_presets_selected, bool, NULL, 0644); ++MODULE_PARM_DESC(txeq_presets_selected, "Use only the selected Presets out of the 8 TX Equalization Presets for TX EQTR"); ++ ++/* ++ * ufs_tx_eq_preset - Table of minimum required list of presets. ++ * ++ * A HS-G6 capable M-TX shall support the presets defined in M-PHY v6.0 spec. ++ * Preset Pre-Shoot(dB) De-Emphasis(dB) ++ * P0 0.0 0.0 ++ * P1 0.0 0.8 ++ * P2 0.0 1.6 ++ * P3 0.8 0.0 ++ * P4 1.6 0.0 ++ * P5 0.8 0.8 ++ * P6 0.8 1.6 ++ * P7 1.6 0.8 ++ */ ++static const struct __ufs_tx_eq_preset { ++ u8 preshoot; ++ u8 deemphasis; ++} ufs_tx_eq_preset[UFS_TX_EQ_PRESET_MAX] = { ++ [UFS_TX_EQ_PRESET_P0] = {UFS_TX_HS_PRESHOOT_DB_0P0, UFS_TX_HS_DEEMPHASIS_DB_0P0}, ++ [UFS_TX_EQ_PRESET_P1] = {UFS_TX_HS_PRESHOOT_DB_0P0, UFS_TX_HS_DEEMPHASIS_DB_0P8}, ++ [UFS_TX_EQ_PRESET_P2] = {UFS_TX_HS_PRESHOOT_DB_0P0, UFS_TX_HS_DEEMPHASIS_DB_1P6}, ++ [UFS_TX_EQ_PRESET_P3] = {UFS_TX_HS_PRESHOOT_DB_0P8, UFS_TX_HS_DEEMPHASIS_DB_0P0}, ++ [UFS_TX_EQ_PRESET_P4] = {UFS_TX_HS_PRESHOOT_DB_1P6, UFS_TX_HS_DEEMPHASIS_DB_0P0}, ++ [UFS_TX_EQ_PRESET_P5] = {UFS_TX_HS_PRESHOOT_DB_0P8, UFS_TX_HS_DEEMPHASIS_DB_0P8}, ++ [UFS_TX_EQ_PRESET_P6] = {UFS_TX_HS_PRESHOOT_DB_0P8, UFS_TX_HS_DEEMPHASIS_DB_1P6}, ++ [UFS_TX_EQ_PRESET_P7] = {UFS_TX_HS_PRESHOOT_DB_1P6, UFS_TX_HS_DEEMPHASIS_DB_0P8}, ++}; ++ ++/* ++ * pa_peer_rx_adapt_initial - Table of UniPro PA_PeerRxHSGnAdaptInitial ++ * attribute IDs for High Speed (HS) Gears. ++ * ++ * This table maps HS Gears to their respective UniPro PA_PeerRxHSGnAdaptInitial ++ * attribute IDs. Entries for Gears 1-3 are 0 (unsupported). ++ */ ++static const u32 pa_peer_rx_adapt_initial[UFS_HS_GEAR_MAX] = { ++ 0, ++ 0, ++ 0, ++ PA_PEERRXHSG4ADAPTINITIAL, ++ PA_PEERRXHSG5ADAPTINITIAL, ++ PA_PEERRXHSG6ADAPTINITIALL0L3 ++}; ++ ++/* ++ * rx_adapt_initial_cap - Table of M-PHY RX_HS_Gn_ADAPT_INITIAL_Capability ++ * attribute IDs for High Speed (HS) Gears. ++ * ++ * This table maps HS Gears to their respective M-PHY ++ * RX_HS_Gn_ADAPT_INITIAL_Capability attribute IDs. Entries for Gears 1-3 are 0 ++ * (unsupported). ++ */ ++static const u32 rx_adapt_initial_cap[UFS_HS_GEAR_MAX] = { ++ 0, ++ 0, ++ 0, ++ RX_HS_G4_ADAPT_INITIAL_CAP, ++ RX_HS_G5_ADAPT_INITIAL_CAP, ++ RX_HS_G6_ADAPT_INITIAL_CAP ++}; ++ ++/* ++ * pa_tx_eq_setting - Table of UniPro PA_TxEQGnSetting attribute IDs for High ++ * Speed (HS) Gears. ++ * ++ * This table maps HS Gears to their respective UniPro PA_TxEQGnSetting ++ * attribute IDs. ++ */ ++static const u32 pa_tx_eq_setting[UFS_HS_GEAR_MAX] = { ++ PA_TXEQG1SETTING, ++ PA_TXEQG2SETTING, ++ PA_TXEQG3SETTING, ++ PA_TXEQG4SETTING, ++ PA_TXEQG5SETTING, ++ PA_TXEQG6SETTING ++}; ++ ++/** ++ * ufshcd_configure_precoding - Configure Pre-Coding for all active lanes ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * ++ * Bit[7] in RX_FOM indicates that the receiver needs to enable Pre-Coding when ++ * set. Pre-Coding must be enabled on both the transmitter and receiver to ++ * ensure proper operation. ++ * ++ * Returns 0 on success, non-zero error code otherwise ++ */ ++static int ufshcd_configure_precoding(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params) ++{ ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ u32 local_precode_en = 0; ++ u32 peer_precode_en = 0; ++ int lane, ret; ++ ++ /* Enable Pre-Coding for Host's TX & Device's RX pair */ ++ for (lane = 0; lane < pwr_info->lane_tx; lane++) { ++ if (params->host[lane].precode_en) { ++ local_precode_en |= PRECODEEN_TX_BIT(lane); ++ peer_precode_en |= PRECODEEN_RX_BIT(lane); ++ } ++ } ++ ++ /* Enable Pre-Coding for Device's TX & Host's RX pair */ ++ for (lane = 0; lane < pwr_info->lane_rx; lane++) { ++ if (params->device[lane].precode_en) { ++ peer_precode_en |= PRECODEEN_TX_BIT(lane); ++ local_precode_en |= PRECODEEN_RX_BIT(lane); ++ } ++ } ++ ++ if (!local_precode_en && !peer_precode_en) { ++ dev_dbg(hba->dev, "Pre-Coding is not required for Host and Device\n"); ++ return 0; ++ } ++ ++ /* Set local PA_PreCodeEn */ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PRECODEEN), local_precode_en); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set local PA_PreCodeEn: %d\n", ret); ++ return ret; ++ } ++ ++ /* Set peer PA_PreCodeEn */ ++ ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_PRECODEEN), peer_precode_en); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set peer PA_PreCodeEn: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hba->dev, "Local PA_PreCodeEn: 0x%02x, Peer PA_PreCodeEn: 0x%02x\n", ++ local_precode_en, peer_precode_en); ++ ++ return 0; ++} ++ ++void ufshcd_print_tx_eq_params(struct ufs_hba *hba) ++{ ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ struct ufshcd_tx_eq_params *params; ++ u32 gear = hba->pwr_info.gear_tx; ++ int lane; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) ++ return; ++ ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid || !params->is_applied) ++ return; ++ ++ for (lane = 0; lane < pwr_info->lane_tx; lane++) ++ dev_dbg(hba->dev, "Host TX Lane %d: PreShoot %u, DeEmphasis %u, FOM %u, PreCodeEn %d\n", ++ lane, params->host[lane].preshoot, ++ params->host[lane].deemphasis, ++ params->host[lane].fom_val, ++ params->host[lane].precode_en); ++ ++ for (lane = 0; lane < pwr_info->lane_rx; lane++) ++ dev_dbg(hba->dev, "Device TX Lane %d: PreShoot %u, DeEmphasis %u, FOM %u, PreCodeEn %d\n", ++ lane, params->device[lane].preshoot, ++ params->device[lane].deemphasis, ++ params->device[lane].fom_val, ++ params->device[lane].precode_en); ++} ++ ++static inline u32 ++ufshcd_compose_tx_eq_setting(struct ufshcd_tx_eq_settings *settings, ++ int num_lanes) ++{ ++ u32 setting = 0; ++ int lane; ++ ++ for (lane = 0; lane < num_lanes; lane++, settings++) { ++ setting |= TX_HS_PRESHOOT_BITS(lane, settings->preshoot); ++ setting |= TX_HS_DEEMPHASIS_BITS(lane, settings->deemphasis); ++ } ++ ++ return setting; ++} ++ ++/** ++ * ufshcd_apply_tx_eq_settings - Apply TX Equalization settings for target gear ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * @gear: target gear ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ u32 gear) ++{ ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ u32 setting; ++ int ret; ++ ++ /* Compose settings for Host's TX Lanes */ ++ setting = ufshcd_compose_tx_eq_setting(params->host, pwr_info->lane_tx); ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(pa_tx_eq_setting[gear - 1]), setting); ++ if (ret) ++ return ret; ++ ++ /* Compose settings for Device's TX Lanes */ ++ setting = ufshcd_compose_tx_eq_setting(params->device, pwr_info->lane_rx); ++ ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(pa_tx_eq_setting[gear - 1]), setting); ++ if (ret) ++ return ret; ++ ++ /* Configure Pre-Coding */ ++ if (gear >= UFS_HS_G6) { ++ ret = ufshcd_configure_precoding(hba, params); ++ if (ret) { ++ dev_err(hba->dev, "Failed to configure pre-coding: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * ufshcd_evaluate_tx_eqtr_fom - Evaluate TX EQTR FOM results ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * @eqtr_data: TX EQTR data structure ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * Evaluate TX EQTR FOM results, update host and device TX EQTR data accordingy ++ * if FOM have been improved compared to previous iteration, and record TX EQTR ++ * FOM results. ++ */ ++static void ufshcd_evaluate_tx_eqtr_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct ufshcd_tx_eqtr_data *eqtr_data, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ u8 preshoot, deemphasis, fom_value; ++ bool precode_en; ++ int lane; ++ ++ for (lane = 0; h_iter->is_updated && lane < pwr_mode->lane_tx; lane++) { ++ preshoot = h_iter->preshoot; ++ deemphasis = h_iter->deemphasis; ++ fom_value = h_iter->fom[lane] & RX_FOM_VALUE_MASK; ++ precode_en = h_iter->fom[lane] & RX_FOM_PRECODING_EN_BIT; ++ ++ /* Record host TX EQTR FOM */ ++ eqtr_data->host_fom[lane][preshoot][deemphasis] = h_iter->fom[lane]; ++ ++ /* Check if FOM has been improved for host's TX Lanes */ ++ if (fom_value > eqtr_data->host[lane].fom_val) { ++ eqtr_data->host[lane].preshoot = preshoot; ++ eqtr_data->host[lane].deemphasis = deemphasis; ++ eqtr_data->host[lane].fom_val = fom_value; ++ eqtr_data->host[lane].precode_en = precode_en; ++ } ++ ++ dev_dbg(hba->dev, "TX EQTR: Host TX Lane %d: PreShoot %u, DeEmphasis %u, FOM value %u, PreCodeEn %d\n", ++ lane, preshoot, deemphasis, fom_value, precode_en); ++ } ++ ++ for (lane = 0; d_iter->is_updated && lane < pwr_mode->lane_rx; lane++) { ++ preshoot = d_iter->preshoot; ++ deemphasis = d_iter->deemphasis; ++ fom_value = d_iter->fom[lane] & RX_FOM_VALUE_MASK; ++ precode_en = d_iter->fom[lane] & RX_FOM_PRECODING_EN_BIT; ++ ++ /* Record device TX EQTR FOM */ ++ eqtr_data->device_fom[lane][preshoot][deemphasis] = d_iter->fom[lane]; ++ ++ /* Check if FOM has been improved for Device's TX Lanes */ ++ if (fom_value > eqtr_data->device[lane].fom_val) { ++ eqtr_data->device[lane].preshoot = preshoot; ++ eqtr_data->device[lane].deemphasis = deemphasis; ++ eqtr_data->device[lane].fom_val = fom_value; ++ eqtr_data->device[lane].precode_en = precode_en; ++ } ++ ++ dev_dbg(hba->dev, "TX EQTR: Device TX Lane %d: PreShoot %u, DeEmphasis %u, FOM value %u, PreCodeEn %d\n", ++ lane, preshoot, deemphasis, fom_value, precode_en); ++ } ++} ++ ++/** ++ * ufshcd_get_rx_fom - Get Figure of Merit (FOM) for both sides ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_get_rx_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ int lane, ret; ++ u32 fom; ++ ++ /* Get FOM of host's TX lanes from device's RX_FOM. */ ++ for (lane = 0; lane < pwr_mode->lane_tx; lane++) { ++ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB_SEL(RX_FOM, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &fom); ++ if (ret) ++ return ret; ++ ++ h_iter->fom[lane] = (u8)fom; ++ } ++ ++ /* Get FOM of device's TX lanes from host's RX_FOM. */ ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_FOM, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &fom); ++ if (ret) ++ return ret; ++ ++ d_iter->fom[lane] = (u8)fom; ++ } ++ ++ ret = ufshcd_vops_get_rx_fom(hba, pwr_mode, h_iter, d_iter); ++ if (ret) ++ dev_err(hba->dev, "Failed to get FOM via vops: %d\n", ret); ++ ++ return ret; ++} ++ ++static bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis) ++{ ++ int i; ++ ++ for (i = 0; i < UFS_TX_EQ_PRESET_MAX; i++) { ++ if (!txeq_presets_selected[i]) ++ continue; ++ ++ if (preshoot == ufs_tx_eq_preset[i].preshoot && ++ deemphasis == ufs_tx_eq_preset[i].deemphasis) ++ return true; ++ } ++ ++ return false; ++} ++ ++/** ++ * tx_eqtr_iter_try_update - Try to update a TX EQTR iterator ++ * @iter: TX EQTR iterator data structure ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * ++ * This function validates whether the provided PreShoot and DeEmphasis ++ * combination can be used or not. If yes, it updates the TX EQTR iterator with ++ * the provided PreShoot and DeEmphasis, it also sets the is_updated flag ++ * to indicate the iterator has been updated. ++ */ ++static void tx_eqtr_iter_try_update(struct tx_eqtr_iter *iter, ++ u8 preshoot, u8 deemphasis) ++{ ++ if (!test_bit(preshoot, &iter->preshoot_bitmap) || ++ !test_bit(deemphasis, &iter->deemphasis_bitmap) || ++ (use_txeq_presets && !ufshcd_is_txeq_preset_selected(preshoot, deemphasis))) { ++ iter->is_updated = false; ++ return; ++ } ++ ++ iter->preshoot = preshoot; ++ iter->deemphasis = deemphasis; ++ iter->is_updated = true; ++} ++ ++/** ++ * tx_eqtr_iter_update() - Update host and deviceTX EQTR iterators ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * @h_iter: Host TX EQTR iterator data structure ++ * @d_iter: Device TX EQTR iterator data structure ++ * ++ * Updates host and device TX Equalization training iterators with the ++ * provided PreShoot and DeEmphasis. ++ * ++ * Return: true if host and/or device TX Equalization training iterator has ++ * been updated to the provided PreShoot and DeEmphasis, false otherwise. ++ */ ++static bool tx_eqtr_iter_update(u8 preshoot, u8 deemphasis, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ tx_eqtr_iter_try_update(h_iter, preshoot, deemphasis); ++ tx_eqtr_iter_try_update(d_iter, preshoot, deemphasis); ++ ++ return h_iter->is_updated || d_iter->is_updated; ++} ++ ++/** ++ * ufshcd_tx_eqtr_iter_init - Initialize host and device TX EQTR iterators ++ * @hba: per adapter instance ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * This function initializes the TX EQTR iterator structures for both host and ++ * device by reading their TX equalization capabilities. The capabilities are ++ * cached in the hba structure to avoid redundant DME operations in subsequent ++ * calls. In the TX EQTR procedure, the iterator structures are updated by ++ * tx_eqtr_iter_update() to systematically iterate through supported TX ++ * Equalization setting combinations. ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_tx_eqtr_iter_init(struct ufs_hba *hba, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ u32 cap; ++ int ret; ++ ++ if (!hba->host_preshoot_cap) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(TX_HS_PRESHOOT_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->host_preshoot_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ if (!hba->host_deemphasis_cap) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(TX_HS_DEEMPHASIS_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->host_deemphasis_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ if (!hba->device_preshoot_cap) { ++ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(TX_HS_PRESHOOT_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->device_preshoot_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ if (!hba->device_deemphasis_cap) { ++ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(TX_HS_DEEMPHASIS_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->device_deemphasis_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ /* ++ * Support PreShoot & DeEmphasis of value 0 is mandatory, hence they are ++ * not reflected in PreShoot/DeEmphasis capabilities. Left shift the ++ * capability bitmap by 1 and set bit[0] to reflect value 0 is ++ * supported, such that test_bit() can be used later for convenience. ++ */ ++ h_iter->preshoot_bitmap = (hba->host_preshoot_cap << 0x1) | 0x1; ++ h_iter->deemphasis_bitmap = (hba->host_deemphasis_cap << 0x1) | 0x1; ++ d_iter->preshoot_bitmap = (hba->device_preshoot_cap << 0x1) | 0x1; ++ d_iter->deemphasis_bitmap = (hba->device_deemphasis_cap << 0x1) | 0x1; ++ ++ return 0; ++} ++ ++/** ++ * adapt_cap_to_t_adapt - Calculate TAdapt from adapt capability ++ * @adapt_cap: Adapt capability ++ * ++ * For NRZ: ++ * IF (ADAPT_range = FINE) ++ * TADAPT = 650 x (ADAPT_length + 1) ++ * ELSE (IF ADAPT_range = COARSE) ++ * TADAPT = 650 x 2^ADAPT_length ++ * ++ * Returns calculated TAdapt value in term of Unit Intervals (UI) ++ */ ++static inline u64 adapt_cap_to_t_adapt(u32 adapt_cap) ++{ ++ u64 tadapt; ++ u8 adapt_length = adapt_cap & ADAPT_LENGTH_MASK; ++ ++ if (!IS_ADAPT_RANGE_COARSE(adapt_cap)) ++ tadapt = TADAPT_FACTOR * (adapt_length + 1); ++ else ++ tadapt = TADAPT_FACTOR * (1 << adapt_length); ++ ++ return tadapt; ++} ++ ++/** ++ * adapt_cap_to_t_adapt_l0l3 - Calculate TAdapt_L0_L3 from adapt capability ++ * @adapt_cap: Adapt capability ++ * ++ * For PAM-4: ++ * IF (ADAPT_range = FINE) ++ * TADAPT_L0_L3 = 2^9 x ADAPT_length ++ * ELSE IF (ADAPT_range = COARSE) ++ * TADAPT_L0_L3 = 2^9 x (2^ADAPT_length) ++ * ++ * Returns calculated TAdapt value in term of Unit Intervals (UI) ++ */ ++static inline u64 adapt_cap_to_t_adapt_l0l3(u32 adapt_cap) ++{ ++ u64 tadapt; ++ u8 adapt_length = adapt_cap & ADAPT_LENGTH_MASK; ++ ++ if (!IS_ADAPT_RANGE_COARSE(adapt_cap)) ++ tadapt = TADAPT_L0L3_FACTOR * adapt_length; ++ else ++ tadapt = TADAPT_L0L3_FACTOR * (1 << adapt_length); ++ ++ return tadapt; ++} ++ ++/** ++ * adapt_cap_to_t_adapt_l0l1l2l3 - Calculate TAdapt_L0_L1_L2_L3 from adapt capability ++ * @adapt_cap: Adapt capability ++ * ++ * For PAM-4: ++ * IF (ADAPT_range_L0_L1_L2_L3 = FINE) ++ * TADAPT_L0_L1_L2_L3 = 2^15 x (ADAPT_length_L0_L1_L2_L3 + 1) ++ * ELSE IF (ADAPT_range_L0_L1_L2_L3 = COARSE) ++ * TADAPT_L0_L1_L2_L3 = 2^15 x 2^ADAPT_length_L0_L1_L2_L3 ++ * ++ * Returns calculated TAdapt value in term of Unit Intervals (UI) ++ */ ++static inline u64 adapt_cap_to_t_adapt_l0l1l2l3(u32 adapt_cap) ++{ ++ u64 tadapt; ++ u8 adapt_length = adapt_cap & ADAPT_LENGTH_MASK; ++ ++ if (!IS_ADAPT_RANGE_COARSE(adapt_cap)) ++ tadapt = TADAPT_L0L1L2L3_FACTOR * (adapt_length + 1); ++ else ++ tadapt = TADAPT_L0L1L2L3_FACTOR * (1 << adapt_length); ++ ++ return tadapt; ++} ++ ++/** ++ * ufshcd_setup_tx_eqtr_adapt_length - Setup TX adapt length for EQTR ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * @gear: target gear for EQTR ++ * ++ * This function determines and configures the proper TX adapt length (TAdapt) ++ * for the TX EQTR procedure based on the target gear and RX adapt capabilities ++ * of both host and device. ++ * ++ * Guidelines from MIPI UniPro v3.0 spec - select the minimum Adapt Length for ++ * the Equalization Training procedure based on the following conditions: ++ * ++ * If the target High-Speed Gear n is HS-G4 or HS-G5: ++ * PA_TxAdaptLength_EQTR[7:0] >= Max (10us, RX_HS_Gn_ADAPT_INITIAL_Capability, ++ * PA_PeerRxHsGnAdaptInitial) ++ * PA_TxAdaptLength_EQTR[7:0] shall be shorter than PACP_REQUEST_TIMER (10ms) ++ * PA_TxAdaptLength_EQTR[15:8] is not relevant for HS-G4 and HS-G5. This field ++ * is set to 255 (reserved value). ++ * ++ * If the target High-Speed Gear n is HS-G6: ++ * PA_TxAdapthLength_EQTR >= 10us ++ * PA_TxAdapthLength_EQTR[7:0] >= Max (RX_HS_G6_ADAPT_INITIAL_Capability, ++ * PA_PeerRxHsG6AdaptInitialL0L3) ++ * PA_TxAdapthLength_EQTR[15:8] >= Max (RX_HS_G6_ADAPT_INITIAL_L0_L1_L2_L3_Capability, ++ * PA_PeerRxHsG6AdaptInitialL0L1L2L3) ++ * PA_TxAdaptLength_EQTR shall be shorter than PACP_REQUEST_TIMER value of 10ms. ++ * ++ * Since adapt capabilities encode both range (fine/coarse) and length values, ++ * direct comparison is not possible. This function converts adapt capabilities ++ * to actual time durations in Unit Intervals (UI) using the Adapt time ++ * calculation formular in M-PHY v6.0 spec (Table 8), then selects the maximum ++ * to ensure both host and device use adequate TX adapt length. ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_setup_tx_eqtr_adapt_length(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ u32 gear) ++{ ++ u32 adapt_eqtr; ++ int ret; ++ ++ if (gear == UFS_HS_G4 || gear == UFS_HS_G5) { ++ u64 t_adapt, t_adapt_local, t_adapt_peer; ++ u32 adapt_cap_local, adapt_cap_peer, adapt_length; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(rx_adapt_initial_cap[gear - 1], ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &adapt_cap_local); ++ if (ret) ++ return ret; ++ ++ if (adapt_cap_local > ADAPT_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_cap_local); ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(pa_peer_rx_adapt_initial[gear - 1]), ++ &adapt_cap_peer); ++ if (ret) ++ return ret; ++ ++ if (adapt_cap_peer > ADAPT_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_cap_peer); ++ return -EINVAL; ++ } ++ ++ t_adapt_local = adapt_cap_to_t_adapt(adapt_cap_local); ++ t_adapt_peer = adapt_cap_to_t_adapt(adapt_cap_peer); ++ t_adapt = max(t_adapt_local, t_adapt_peer); ++ ++ dev_dbg(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_cap_local); ++ dev_dbg(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_cap_peer); ++ dev_dbg(hba->dev, "t_adapt_local = %llu UI, t_adapt_peer = %llu UI\n", ++ t_adapt_local, t_adapt_peer); ++ dev_dbg(hba->dev, "TAdapt %llu UI selected for TX EQTR\n", ++ t_adapt); ++ ++ adapt_length = (t_adapt_local >= t_adapt_peer) ? ++ adapt_cap_local : adapt_cap_peer; ++ ++ if (gear == UFS_HS_G4 && t_adapt < TX_EQTR_HS_G4_MIN_T_ADAPT) { ++ dev_dbg(hba->dev, "TAdapt %llu UI is too short for TX EQTR for HS-G%u, use default Adapt 0x%x\n", ++ t_adapt, gear, TX_EQTR_HS_G4_ADAPT_DEFAULT); ++ adapt_length = TX_EQTR_HS_G4_ADAPT_DEFAULT; ++ } else if (gear == UFS_HS_G5 && t_adapt < TX_EQTR_HS_G5_MIN_T_ADAPT) { ++ dev_dbg(hba->dev, "TAdapt %llu UI is too short for TX EQTR for HS-G%u, use default Adapt 0x%x\n", ++ t_adapt, gear, TX_EQTR_HS_G5_ADAPT_DEFAULT); ++ adapt_length = TX_EQTR_HS_G5_ADAPT_DEFAULT; ++ } ++ ++ adapt_eqtr = adapt_length | ++ (TX_EQTR_ADAPT_RESERVED << TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT); ++ } else if (gear == UFS_HS_G6) { ++ u64 t_adapt, t_adapt_l0l3, t_adapt_l0l3_local, t_adapt_l0l3_peer; ++ u64 t_adapt_l0l1l2l3, t_adapt_l0l1l2l3_local, t_adapt_l0l1l2l3_peer; ++ u32 adapt_l0l3_cap_local, adapt_l0l3_cap_peer, adapt_length_l0l3; ++ u32 adapt_l0l1l2l3_cap_local, adapt_l0l1l2l3_cap_peer, adapt_length_l0l1l2l3; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(rx_adapt_initial_cap[gear - 1], ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &adapt_l0l3_cap_local); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l3_cap_local > ADAPT_L0L3_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l3_cap_local); ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(pa_peer_rx_adapt_initial[gear - 1]), ++ &adapt_l0l3_cap_peer); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l3_cap_peer > ADAPT_L0L3_LENGTH_MAX) { ++ dev_err(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l3_cap_peer); ++ return -EINVAL; ++ } ++ ++ t_adapt_l0l3_local = adapt_cap_to_t_adapt_l0l3(adapt_l0l3_cap_local); ++ t_adapt_l0l3_peer = adapt_cap_to_t_adapt_l0l3(adapt_l0l3_cap_peer); ++ ++ dev_dbg(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_l0l3_cap_local); ++ dev_dbg(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_l0l3_cap_peer); ++ dev_dbg(hba->dev, "t_adapt_l0l3_local = %llu UI, t_adapt_l0l3_peer = %llu UI\n", ++ t_adapt_l0l3_local, t_adapt_l0l3_peer); ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &adapt_l0l1l2l3_cap_local); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l1l2l3_cap_local > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l1l2l3_cap_local); ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), ++ &adapt_l0l1l2l3_cap_peer); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l1l2l3_cap_peer > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l1l2l3_cap_peer); ++ return -EINVAL; ++ } ++ ++ t_adapt_l0l1l2l3_local = adapt_cap_to_t_adapt_l0l1l2l3(adapt_l0l1l2l3_cap_local); ++ t_adapt_l0l1l2l3_peer = adapt_cap_to_t_adapt_l0l1l2l3(adapt_l0l1l2l3_cap_peer); ++ ++ dev_dbg(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP = 0x%x\n", ++ gear, adapt_l0l1l2l3_cap_local); ++ dev_dbg(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP = 0x%x\n", ++ gear, adapt_l0l1l2l3_cap_peer); ++ dev_dbg(hba->dev, "t_adapt_l0l1l2l3_local = %llu UI, t_adapt_l0l1l2l3_peer = %llu UI\n", ++ t_adapt_l0l1l2l3_local, t_adapt_l0l1l2l3_peer); ++ ++ t_adapt_l0l1l2l3 = max(t_adapt_l0l1l2l3_local, t_adapt_l0l1l2l3_peer); ++ t_adapt_l0l3 = max(t_adapt_l0l3_local, t_adapt_l0l3_peer); ++ t_adapt = t_adapt_l0l3 + t_adapt_l0l1l2l3; ++ ++ dev_dbg(hba->dev, "TAdapt %llu PAM-4 UI selected for TX EQTR\n", ++ t_adapt); ++ ++ adapt_length_l0l3 = (t_adapt_l0l3_local >= t_adapt_l0l3_peer) ? ++ adapt_l0l3_cap_local : adapt_l0l3_cap_peer; ++ adapt_length_l0l1l2l3 = (t_adapt_l0l1l2l3_local >= t_adapt_l0l1l2l3_peer) ? ++ adapt_l0l1l2l3_cap_local : adapt_l0l1l2l3_cap_peer; ++ ++ if (t_adapt < TX_EQTR_HS_G6_MIN_T_ADAPT) { ++ dev_dbg(hba->dev, "TAdapt %llu UI is too short for TX EQTR for HS-G%u, use default Adapt 0x%x\n", ++ t_adapt, gear, TX_EQTR_HS_G6_ADAPT_DEFAULT); ++ adapt_length_l0l3 = TX_EQTR_HS_G6_ADAPT_DEFAULT; ++ } ++ ++ adapt_eqtr = adapt_length_l0l3 | ++ (adapt_length_l0l1l2l3 << TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT); ++ } else { ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXADAPTLENGTH_EQTR), adapt_eqtr); ++ if (ret) ++ dev_err(hba->dev, "Failed to set adapt length for TX EQTR: %d\n", ret); ++ else ++ dev_dbg(hba->dev, "PA_TXADAPTLENGTH_EQTR configured to 0x%08x\n", adapt_eqtr); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_compose_tx_eqtr_setting - Compose TX EQTR setting ++ * @iter: TX EQTR iterator data structure ++ * @num_lanes: number of active lanes ++ * ++ * Returns composed TX EQTR setting, same setting is used for all active lanes ++ */ ++static inline u32 ufshcd_compose_tx_eqtr_setting(struct tx_eqtr_iter *iter, ++ int num_lanes) ++{ ++ u32 setting = 0; ++ int lane; ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ setting |= TX_HS_PRESHOOT_BITS(lane, iter->preshoot); ++ setting |= TX_HS_DEEMPHASIS_BITS(lane, iter->deemphasis); ++ } ++ ++ return setting; ++} ++ ++/** ++ * ufshcd_apply_tx_eqtr_settings - Apply TX EQTR setting ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_apply_tx_eqtr_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ u32 setting; ++ int ret; ++ ++ setting = ufshcd_compose_tx_eqtr_setting(h_iter, pwr_mode->lane_tx); ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQTRSETTING), setting); ++ if (ret) ++ return ret; ++ ++ setting = ufshcd_compose_tx_eqtr_setting(d_iter, pwr_mode->lane_rx); ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERTXEQTRSETTING), setting); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_vops_apply_tx_eqtr_settings(hba, pwr_mode, h_iter, d_iter); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_update_tx_eq_params - Update TX Equalization params ++ * @params: TX EQ parameters data structure ++ * @eqtr_data: TX EQTR data structure ++ * ++ * Update TX Equalization params using results from TX EQTR data. ++ */ ++static inline void ++ufshcd_update_tx_eq_params(struct ufshcd_tx_eq_params *params, ++ struct ufshcd_tx_eqtr_data *eqtr_data) ++{ ++ struct ufshcd_tx_eqtr_record *rec = params->eqtr_record; ++ ++ memcpy(params->host, eqtr_data->host, sizeof(params->host)); ++ memcpy(params->device, eqtr_data->device, sizeof(params->device)); ++ ++ if (!rec) ++ return; ++ ++ memcpy(rec->host_fom, eqtr_data->host_fom, sizeof(rec->host_fom)); ++ memcpy(rec->device_fom, eqtr_data->device_fom, sizeof(rec->device_fom)); ++ rec->last_record_ts = ktime_get(); ++ rec->last_record_index++; ++} ++ ++/** ++ * __ufshcd_tx_eqtr - TX Equalization Training (EQTR) procedure ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * @pwr_mode: target power mode containing gear and rate information ++ * ++ * This function implements the complete TX EQTR procedure as defined in UFSHCI ++ * v5.0 specification. It iterates through all possible combinations of PreShoot ++ * and DeEmphasis settings to find the optimal TX Equalization settings for all ++ * active lanes. ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int __ufshcd_tx_eqtr(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufshcd_tx_eqtr_data *eqtr_data __free(kfree) = ++ kzalloc(sizeof(*eqtr_data), GFP_KERNEL); ++ struct tx_eqtr_iter h_iter = {}; ++ struct tx_eqtr_iter d_iter = {}; ++ u32 gear = pwr_mode->gear_tx; ++ u8 preshoot, deemphasis; ++ ktime_t start; ++ int ret; ++ ++ if (!eqtr_data) ++ return -ENOMEM; ++ ++ dev_info(hba->dev, "Start TX EQTR procedure for HS-G%u, Rate-%s, RX Lanes: %u, TX Lanes: %u\n", ++ gear, ufs_hs_rate_to_str(pwr_mode->hs_rate), ++ pwr_mode->lane_rx, pwr_mode->lane_tx); ++ ++ start = ktime_get(); ++ ++ /* Step 1 - Determine the TX Adapt Length for EQTR */ ++ ret = ufshcd_setup_tx_eqtr_adapt_length(hba, params, gear); ++ if (ret) { ++ dev_err(hba->dev, "Failed to setup TX EQTR Adaptation length: %d\n", ret); ++ return ret; ++ } ++ ++ /* Step 2 - Determine TX Equalization setting capabilities */ ++ ret = ufshcd_tx_eqtr_iter_init(hba, &h_iter, &d_iter); ++ if (ret) { ++ dev_err(hba->dev, "Failed to init TX EQTR data: %d\n", ret); ++ return ret; ++ } ++ ++ /* TX EQTR main loop */ ++ for (preshoot = 0; preshoot < TX_HS_NUM_PRESHOOT; preshoot++) { ++ for (deemphasis = 0; deemphasis < TX_HS_NUM_DEEMPHASIS; deemphasis++) { ++ if (!tx_eqtr_iter_update(preshoot, deemphasis, &h_iter, &d_iter)) ++ continue; ++ ++ /* Step 3 - Apply TX EQTR settings */ ++ ret = ufshcd_apply_tx_eqtr_settings(hba, pwr_mode, &h_iter, &d_iter); ++ if (ret) { ++ dev_err(hba->dev, "Failed to apply TX EQTR settings (PreShoot %u, DeEmphasis %u): %d\n", ++ preshoot, deemphasis, ret); ++ return ret; ++ } ++ ++ /* Step 4 - Trigger UIC TX EQTR */ ++ ret = ufshcd_uic_tx_eqtr(hba, gear); ++ if (ret) { ++ dev_err(hba->dev, "Failed to trigger UIC TX EQTR for target gear %u: %d\n", ++ gear, ret); ++ return ret; ++ } ++ ++ /* Step 5 - Get FOM */ ++ ret = ufshcd_get_rx_fom(hba, pwr_mode, &h_iter, &d_iter); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get RX_FOM: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ufshcd_evaluate_tx_eqtr_fom(hba, pwr_mode, eqtr_data, &h_iter, &d_iter); ++ } ++ } ++ ++ dev_info(hba->dev, "TX EQTR procedure completed! Time elapsed: %llu ms\n", ++ ktime_to_ms(ktime_sub(ktime_get(), start))); ++ ++ ufshcd_update_tx_eq_params(params, eqtr_data); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_tx_eqtr_prepare - Prepare UFS link for TX EQTR procedure ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate ++ * ++ * This function prepares the UFS link for TX Equalization Training (EQTR) by ++ * establishing the proper initial conditions required by the EQTR procedure. ++ * It ensures that EQTR starts from the most reliable Power Mode (HS-G1) with ++ * all connected lanes activated and sets host TX HS Adapt Type to INITIAL. ++ * ++ * Returns 0 on successful preparation, negative error code on failure ++ */ ++static int ufshcd_tx_eqtr_prepare(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufs_pa_layer_attr pwr_mode_hs_g1 = { ++ /* TX EQTR shall be initiated from the most reliable HS-G1 */ ++ .gear_rx = UFS_HS_G1, ++ .gear_tx = UFS_HS_G1, ++ .lane_rx = pwr_mode->lane_rx, ++ .lane_tx = pwr_mode->lane_tx, ++ .pwr_rx = FAST_MODE, ++ .pwr_tx = FAST_MODE, ++ /* Use the target power mode's HS rate */ ++ .hs_rate = pwr_mode->hs_rate, ++ }; ++ u32 rate = pwr_mode->hs_rate; ++ int ret; ++ ++ /* Change power mode to HS-G1, activate all connected lanes. */ ++ ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (ret) { ++ dev_err(hba->dev, "TX EQTR: Failed to change power mode to HS-G1, Rate-%s: %d\n", ++ ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), ++ PA_INITIAL_ADAPT); ++ if (ret) ++ dev_err(hba->dev, "TX EQTR: Failed to set Host Adapt type to INITIAL: %d\n", ++ ret); ++ ++ return ret; ++} ++ ++static void ufshcd_tx_eqtr_unprepare(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ int err; ++ ++ if (pwr_mode->pwr_rx == SLOWAUTO_MODE || pwr_mode->hs_rate == 0) ++ return; ++ ++ err = ufshcd_change_power_mode(hba, pwr_mode, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (err) ++ dev_err(hba->dev, "%s: Failed to restore Power Mode: %d\n", ++ __func__, err); ++} ++ ++/** ++ * ufshcd_tx_eqtr - Perform TX EQTR procedures with vops callbacks ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure to populate ++ * @pwr_mode: target power mode containing gear and rate information ++ * ++ * This is the main entry point for performing TX Equalization Training (EQTR) ++ * procedure as defined in UFSCHI v5.0 specification. It serves as a wrapper ++ * around __ufshcd_tx_eqtr() to provide vops support through the variant ++ * operations framework. ++ * ++ * Returns 0 on success, negative error code on failure ++ */ ++static int ufshcd_tx_eqtr(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufs_pa_layer_attr old_pwr_info; ++ int ret; ++ ++ if (!params->eqtr_record) { ++ params->eqtr_record = devm_kzalloc(hba->dev, ++ sizeof(*params->eqtr_record), ++ GFP_KERNEL); ++ if (!params->eqtr_record) ++ return -ENOMEM; ++ } ++ ++ memcpy(&old_pwr_info, &hba->pwr_info, sizeof(struct ufs_pa_layer_attr)); ++ ++ ret = ufshcd_tx_eqtr_prepare(hba, pwr_mode); ++ if (ret) { ++ dev_err(hba->dev, "Failed to prepare TX EQTR: %d\n", ret); ++ goto out; ++ } ++ ++ ret = ufshcd_vops_tx_eqtr_notify(hba, PRE_CHANGE, pwr_mode); ++ if (ret) ++ goto out; ++ ++ ret = __ufshcd_tx_eqtr(hba, params, pwr_mode); ++ if (ret) ++ goto out; ++ ++ ret = ufshcd_vops_tx_eqtr_notify(hba, POST_CHANGE, pwr_mode); ++ ++out: ++ if (ret) ++ ufshcd_tx_eqtr_unprepare(hba, &old_pwr_info); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_config_tx_eq_settings - Configure TX Equalization settings ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * ++ * This function finds and sets the TX Equalization settings for the given ++ * target power mode. ++ * ++ * Returns 0 on success, error code otherwise ++ */ ++int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufshcd_tx_eq_params *params; ++ u32 gear, rate; ++ ++ if (!ufshcd_is_tx_eq_supported(hba) || !use_adaptive_txeq) ++ return 0; ++ ++ if (!hba->max_pwr_info.is_valid) { ++ dev_err(hba->dev, "Max power info is invalid\n"); ++ return -EINVAL; ++ } ++ ++ if (!pwr_mode) { ++ dev_err(hba->dev, "Target power mode is NULL\n"); ++ return -EINVAL; ++ } ++ ++ gear = pwr_mode->gear_tx; ++ rate = pwr_mode->hs_rate; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) { ++ dev_err(hba->dev, "Invalid HS-Gear (%u) for TX Equalization\n", ++ gear); ++ return -EINVAL; ++ } else if (gear < max_t(u32, adaptive_txeq_gear, UFS_HS_G4)) { ++ /* TX EQTR is supported for HS-G4 and higher Gears */ ++ return 0; ++ } ++ ++ if (rate != PA_HS_MODE_A && rate != PA_HS_MODE_B) { ++ dev_err(hba->dev, "Invalid HS-Rate (%u) for TX Equalization\n", ++ rate); ++ return -EINVAL; ++ } ++ ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid) { ++ int ret; ++ ++ ret = ufshcd_tx_eqtr(hba, params, pwr_mode); ++ if (ret) { ++ dev_err(hba->dev, "Failed to train TX Equalization for HS-G%u, Rate-%s: %d\n", ++ gear, ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ /* Mark TX Equalization settings as valid */ ++ params->is_valid = true; ++ params->is_applied = false; ++ } ++ ++ if (params->is_valid && !params->is_applied) { ++ int ret; ++ ++ ret = ufshcd_apply_tx_eq_settings(hba, params, gear); ++ if (ret) { ++ dev_err(hba->dev, "Failed to apply TX Equalization settings for HS-G%u, Rate-%s: %d\n", ++ gear, ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ params->is_applied = true; ++ } ++ ++ return 0; ++} ++ ++/** ++ * ufshcd_apply_valid_tx_eq_settings - Apply valid TX Equalization settings ++ * @hba: per-adapter instance ++ * ++ * This function iterates through all supported High-Speed (HS) gears and ++ * applies valid TX Equalization settings to both Host and Device. ++ */ ++void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba) ++{ ++ struct ufshcd_tx_eq_params *params; ++ int gear, err; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return; ++ ++ if (!hba->max_pwr_info.is_valid) { ++ dev_err(hba->dev, "Max power info is invalid, cannot apply TX Equalization settings\n"); ++ return; ++ } ++ ++ for (gear = UFS_HS_G1; gear <= UFS_HS_GEAR_MAX; gear++) { ++ params = &hba->tx_eq_params[gear - 1]; ++ ++ if (params->is_valid) { ++ err = ufshcd_apply_tx_eq_settings(hba, params, gear); ++ if (err) { ++ params->is_applied = false; ++ dev_err(hba->dev, "Failed to apply TX Equalization settings for HS-G%u: %d\n", ++ gear, err); ++ } else { ++ params->is_applied = true; ++ } ++ } ++ } ++} +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 087ebf43b09d..fbcea20c8991 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -104,6 +104,12 @@ int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, + int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); + int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id); + ++int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear); ++void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba); ++int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode); ++void ufshcd_print_tx_eq_params(struct ufs_hba *hba); ++ + /* Wrapper functions for safely calling variant operations */ + static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) + { +@@ -298,6 +304,38 @@ static inline u32 ufshcd_vops_freq_to_gear_speed(struct ufs_hba *hba, unsigned l + return 0; + } + ++static inline int ufshcd_vops_get_rx_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ if (hba->vops && hba->vops->get_rx_fom) ++ return hba->vops->get_rx_fom(hba, pwr_mode, h_iter, d_iter); ++ ++ return 0; ++} ++ ++static inline int ufshcd_vops_apply_tx_eqtr_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ if (hba->vops && hba->vops->apply_tx_eqtr_settings) ++ return hba->vops->apply_tx_eqtr_settings(hba, pwr_mode, h_iter, d_iter); ++ ++ return 0; ++} ++ ++static inline int ufshcd_vops_tx_eqtr_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ if (hba->vops && hba->vops->tx_eqtr_notify) ++ return hba->vops->tx_eqtr_notify(hba, status, pwr_mode); ++ ++ return 0; ++} ++ + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; + + /** +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 25ff3629df99..51e431a04ee4 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -4354,16 +4354,18 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) + ret = __ufshcd_send_uic_cmd(hba, cmd); + if (ret) { + dev_err(hba->dev, +- "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", +- cmd->command, cmd->argument3, ret); ++ "pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) uic error %d\n", ++ cmd->command, UIC_GET_ATTR_ID(cmd->argument1), ++ cmd->argument3, ret); + goto out; + } + + if (!wait_for_completion_timeout(hba->uic_async_done, + msecs_to_jiffies(uic_cmd_timeout))) { + dev_err(hba->dev, +- "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", +- cmd->command, cmd->argument3); ++ "pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) completion timeout\n", ++ cmd->command, UIC_GET_ATTR_ID(cmd->argument1), ++ cmd->argument3); + + if (!cmd->cmd_active) { + dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", +@@ -4379,14 +4381,16 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) + status = ufshcd_get_upmcrs(hba); + if (status != PWR_LOCAL) { + dev_err(hba->dev, +- "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", +- cmd->command, status); ++ "pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) failed, host upmcrs:0x%x\n", ++ cmd->command, UIC_GET_ATTR_ID(cmd->argument1), ++ cmd->argument3, status); + ret = (status != PWR_OK) ? status : -1; + } + out: + if (ret) { + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + ufshcd_print_evt_hist(hba); + } + +@@ -4404,6 +4408,29 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) + return ret; + } + ++/** ++ * ufshcd_uic_tx_eqtr - Perform UIC TX Equalization Training ++ * @hba: per adapter instance ++ * @gear: target gear for EQTR ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear) ++{ ++ struct uic_command uic_cmd = { ++ .command = UIC_CMD_DME_SET, ++ .argument1 = UIC_ARG_MIB(PA_EQTR_GEAR), ++ .argument3 = gear, ++ }; ++ int ret; ++ ++ ufshcd_hold(hba); ++ ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); ++ ufshcd_release(hba); ++ ++ return ret; ++} ++ + /** + * ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result + * @hba: per adapter instance +@@ -4827,6 +4854,12 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); + } + ++ ret = ufshcd_config_tx_eq_settings(hba, &final_params); ++ if (ret) ++ dev_warn(hba->dev, "Failed to configure TX Equalization for HS-G%u, Rate-%s: %d\n", ++ final_params.gear_tx, ++ ufs_hs_rate_to_str(final_params.hs_rate), ret); ++ + return ufshcd_change_power_mode(hba, &final_params, pmc_policy); + } + EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); +@@ -6808,6 +6841,7 @@ static void ufshcd_err_handler(struct work_struct *work) + spin_unlock_irqrestore(hba->host->host_lock, flags); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + ufshcd_print_evt_hist(hba); + ufshcd_print_tmrs(hba, hba->outstanding_tasks); + ufshcd_print_trs_all(hba, pr_prdt); +@@ -7071,6 +7105,7 @@ static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) + ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, + "host_regs: "); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + } + ufshcd_schedule_eh_work(hba); + retval |= IRQ_HANDLED; +@@ -7833,6 +7868,7 @@ static int ufshcd_abort(struct scsi_cmnd *cmd) + ufshcd_print_evt_hist(hba); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + ufshcd_print_tr(hba, tag, true); + } else { + ufshcd_print_tr(hba, tag, false); +@@ -8794,6 +8830,8 @@ static void ufshcd_tune_unipro_params(struct ufs_hba *hba) + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_HIBER8TIME) + ufshcd_quirk_override_pa_h8time(hba); ++ ++ ufshcd_apply_valid_tx_eq_settings(hba); + } + + static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index c33060f24dfd..77634e07cbb3 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -292,6 +292,84 @@ struct ufs_pwr_mode_info { + struct ufs_pa_layer_attr info; + }; + ++#define UFS_MAX_LANES 2 ++ ++/** ++ * struct tx_eqtr_iter - TX Equalization Training iterator ++ * @preshoot_bitmap: PreShoot bitmap ++ * @deemphasis_bitmap: DeEmphasis bitmap ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * @fom: Figure-of-Merit read out from RX_FOM ++ * @is_updated: Flag to indicate if updated since previous iteration ++ */ ++struct tx_eqtr_iter { ++ unsigned long preshoot_bitmap; ++ unsigned long deemphasis_bitmap; ++ u8 preshoot; ++ u8 deemphasis; ++ u8 fom[UFS_MAX_LANES]; ++ bool is_updated; ++}; ++ ++/** ++ * struct ufshcd_tx_eq_settings - TX Equalization settings ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * @fom_val: Figure-of-Merit value read out from RX_FOM (Bit[6:0]) ++ * @precode_en: Flag to indicate whether need to enable pre-coding ++ */ ++struct ufshcd_tx_eq_settings { ++ u8 preshoot; ++ u8 deemphasis; ++ u8 fom_val; ++ bool precode_en; ++}; ++ ++/** ++ * struct ufshcd_tx_eqtr_data - Data used during TX Equalization Training procedure ++ * @host: Optimal TX EQ settings identified for host TX Lanes during TX EQTR ++ * @device: Optimal TX EQ settings identified for device TX Lanes during TX EQTR ++ * @host_fom: Host TX EQTR FOM record ++ * @device_fom: Device TX EQTR FOM record ++ */ ++struct ufshcd_tx_eqtr_data { ++ struct ufshcd_tx_eq_settings host[UFS_MAX_LANES]; ++ struct ufshcd_tx_eq_settings device[UFS_MAX_LANES]; ++ u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++}; ++ ++/** ++ * struct ufshcd_tx_eqtr_record - TX Equalization Training record ++ * @host_fom: Host TX EQTR FOM record ++ * @device_fom: Device TX EQTR FOM record ++ * @last_record_ts: Timestamp of the most recent TX EQTR record ++ * @last_record_index: Index of the most recent TX EQTR record ++ */ ++struct ufshcd_tx_eqtr_record { ++ u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ ktime_t last_record_ts; ++ u16 last_record_index; ++}; ++ ++/** ++ * struct ufshcd_tx_eq_params - TX Equalization parameters structure ++ * @host: TX EQ settings for host TX Lanes ++ * @device: TX EQ settings for device TX Lanes ++ * @eqtr_record: Pointer to TX EQTR record ++ * @is_valid: True if parameter contains valid TX Equalization settings ++ * @is_applied: True if settings have been applied to UniPro of both sides ++ */ ++struct ufshcd_tx_eq_params { ++ struct ufshcd_tx_eq_settings host[UFS_MAX_LANES]; ++ struct ufshcd_tx_eq_settings device[UFS_MAX_LANES]; ++ struct ufshcd_tx_eqtr_record *eqtr_record; ++ bool is_valid; ++ bool is_applied; ++}; ++ + /** + * struct ufs_hba_variant_ops - variant specific callbacks + * @name: variant name +@@ -335,6 +413,11 @@ struct ufs_pwr_mode_info { + * @config_esi: called to config Event Specific Interrupt + * @config_scsi_dev: called to configure SCSI device parameters + * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed ++ * @apply_tx_eqtr_settings: called to apply settings for TX Equalization ++ * Training settings. ++ * @get_rx_fom: called to get Figure of Merit (FOM) value. ++ * @tx_eqtr_notify: called before and after TX Equalization Training procedure ++ * to allow platform vendor specific configs to take place. + */ + struct ufs_hba_variant_ops { + const char *name; +@@ -386,6 +469,17 @@ struct ufs_hba_variant_ops { + int (*config_esi)(struct ufs_hba *hba); + void (*config_scsi_dev)(struct scsi_device *sdev); + u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq); ++ int (*get_rx_fom)(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter); ++ int (*apply_tx_eqtr_settings)(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter); ++ int (*tx_eqtr_notify)(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *pwr_mode); + }; + + /* clock gating state */ +@@ -784,6 +878,13 @@ enum ufshcd_caps { + * WriteBooster when scaling the clock down. + */ + UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, ++ ++ /* ++ * This capability allows the host controller driver to apply TX ++ * Equalization settings discovered from UFS attributes, variant ++ * specific operations and TX Equaliztion Training procedure. ++ */ ++ UFSHCD_CAP_TX_EQUALIZATION = 1 << 13, + }; + + struct ufs_hba_variant_params { +@@ -962,6 +1063,15 @@ enum ufshcd_mcq_opr { + * @dev_lvl_exception_count: count of device level exceptions since last reset + * @dev_lvl_exception_id: vendor specific information about the device level exception event. + * @rpmbs: list of OP-TEE RPMB devices (one per RPMB region) ++ * @host_preshoot_cap: a bitfield to indicate supported PreShoot dBs of host's TX lanes, cache of ++ * host M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15) ++ * @host_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of host's TX lanes, cache ++ * of host M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12) ++ * @device_preshoot_cap: a bitfield to indicate supported PreShoot dBs of device's TX lanes, cache ++ * of device M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15) ++ * @device_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of device's TX lanes, ++ * cache of device M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12) ++ * @tx_eq_params: TX Equalization settings + */ + struct ufs_hba { + void __iomem *mmio_base; +@@ -1137,6 +1247,12 @@ struct ufs_hba { + atomic_t dev_lvl_exception_count; + u64 dev_lvl_exception_id; + struct list_head rpmbs; ++ ++ u8 host_preshoot_cap; ++ u8 host_deemphasis_cap; ++ u8 device_preshoot_cap; ++ u8 device_deemphasis_cap; ++ struct ufshcd_tx_eq_params tx_eq_params[UFS_HS_GEAR_MAX]; + }; + + /** +@@ -1281,6 +1397,13 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) + return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; + } + ++static inline bool ufshcd_is_tx_eq_supported(struct ufs_hba *hba) ++{ ++ return hba->caps & UFSHCD_CAP_TX_EQUALIZATION && ++ hba->ufs_version >= ufshci_version(5, 0) && ++ hba->dev_info.wspecversion >= 0x500; ++} ++ + #define ufsmcq_writel(hba, val, reg) \ + writel((val), (hba)->mcq_base + (reg)) + #define ufsmcq_readl(hba, reg) \ +@@ -1296,6 +1419,18 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) + #define ufshcd_readl(hba, reg) \ + readl((hba)->mmio_base + (reg)) + ++static inline const char *ufs_hs_rate_to_str(enum ufs_hs_gear_rate rate) ++{ ++ switch (rate) { ++ case PA_HS_MODE_A: ++ return "A"; ++ case PA_HS_MODE_B: ++ return "B"; ++ default: ++ return "Unknown"; ++ } ++} ++ + /** + * ufshcd_rmwl - perform read/modify/write for a controller register + * @hba: per adapter instance +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 71a5f643400c..4aa592130b4e 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -10,6 +10,8 @@ + * M-TX Configuration Attributes + */ + #define TX_HIBERN8TIME_CAPABILITY 0x000F ++#define TX_HS_DEEMPHASIS_SETTING_CAP 0x0012 ++#define TX_HS_PRESHOOT_SETTING_CAP 0x0015 + #define TX_MODE 0x0021 + #define TX_HSRATE_SERIES 0x0022 + #define TX_HSGEAR 0x0023 +@@ -38,6 +40,9 @@ + /* + * M-RX Configuration Attributes + */ ++#define RX_HS_G5_ADAPT_INITIAL_CAP 0x0074 ++#define RX_HS_G6_ADAPT_INITIAL_CAP 0x007B ++#define RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP 0x007D + #define RX_HS_G1_SYNC_LENGTH_CAP 0x008B + #define RX_HS_G1_PREP_LENGTH_CAP 0x008C + #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F +@@ -50,6 +55,7 @@ + #define RX_HIBERN8TIME_CAP 0x0092 + #define RX_ADV_HIBERN8TIME_CAP 0x0099 + #define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A ++#define RX_HS_G4_ADAPT_INITIAL_CAP 0x009F + #define RX_MODE 0x00A1 + #define RX_HSRATE_SERIES 0x00A2 + #define RX_HSGEAR 0x00A3 +@@ -64,6 +70,7 @@ + #define CFGRXCDR8 0x00BA + #define CFGRXOVR8 0x00BD + #define CFGRXOVR6 0x00BF ++#define RX_FOM 0x00C2 + #define RXDIRECTCTRL2 0x00C7 + #define CFGRXOVR4 0x00E9 + #define RX_REFCLKFREQ 0x00EB +@@ -73,7 +80,6 @@ + #define ENARXDIRECTCFG3 0x00F3 + #define ENARXDIRECTCFG2 0x00F4 + +- + #define is_mphy_tx_attr(attr) (attr < RX_MODE) + #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) + #define SYNC_LEN_FINE(x) ((x) & 0x3F) +@@ -99,6 +105,18 @@ + + #define UNIPRO_CB_OFFSET(x) (0x8000 | x) + ++#define ADAPT_LENGTH_MASK 0x7F ++#define ADAPT_RANGE_BIT BIT(7) ++#define IS_ADAPT_RANGE_COARSE(x) ((x) & ADAPT_RANGE_BIT) ++ ++/* Adapt definitions */ ++#define ADAPT_LENGTH_MAX 0x91 ++#define ADAPT_L0L3_LENGTH_MAX 0x90 ++#define ADAPT_L0L1L2L3_LENGTH_MAX 0x8C ++#define TADAPT_FACTOR 650 ++#define TADAPT_L0L3_FACTOR (1 << 9) ++#define TADAPT_L0L1L2L3_FACTOR (1 << 15) ++ + /* + * PHY Adapter attributes + */ +@@ -164,10 +182,26 @@ + #define PA_PACPERRORCOUNT 0x15C1 + #define PA_PHYTESTCONTROL 0x15C2 + #define PA_TXHSG4SYNCLENGTH 0x15D0 ++#define PA_PEERRXHSG4ADAPTINITIAL 0x15D3 + #define PA_TXHSADAPTTYPE 0x15D4 + #define PA_TXHSG5SYNCLENGTH 0x15D6 ++#define PA_PEERRXHSG5ADAPTINITIAL 0x15D9 ++#define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3 0x15DE ++#define PA_PEERRXHSG6ADAPTINITIALL0L3 0x15DF ++#define PA_PEERRXHSG6ADAPTINITIALL0L1L2L3 0x15E0 ++#define PA_TXEQG1SETTING 0x15E1 ++#define PA_TXEQG2SETTING 0x15E2 ++#define PA_TXEQG3SETTING 0x15E3 ++#define PA_TXEQG4SETTING 0x15E4 ++#define PA_TXEQG5SETTING 0x15E5 ++#define PA_TXEQG6SETTING 0x15E6 ++#define PA_TXEQTRSETTING 0x15E7 ++#define PA_PEERTXEQTRSETTING 0x15E8 ++#define PA_PRECODEEN 0x15E9 ++#define PA_EQTR_GEAR 0x15EA ++#define PA_TXADAPTLENGTH_EQTR 0x15EB + +-/* Adpat type for PA_TXHSADAPTTYPE attribute */ ++/* Adapt type for PA_TXHSADAPTTYPE attribute */ + #define PA_REFRESH_ADAPT 0x00 + #define PA_INITIAL_ADAPT 0x01 + #define PA_NO_ADAPT 0x03 +@@ -187,6 +221,82 @@ + /* PHY Adapter Protocol Constants */ + #define PA_MAXDATALANES 4 + ++/* ++ * TX EQTR's minimum TAdapt should not be less than 10us. ++ * This value is rounded up into the nearest Unit Intervals (UI) ++ */ ++#define TX_EQTR_HS_G4_MIN_T_ADAPT 166400 ++#define TX_EQTR_HS_G5_MIN_T_ADAPT 332800 ++#define TX_EQTR_HS_G6_MIN_T_ADAPT 262144 ++ ++#define TX_EQTR_HS_G4_ADAPT_DEFAULT 0x88 ++#define TX_EQTR_HS_G5_ADAPT_DEFAULT 0x89 ++#define TX_EQTR_HS_G6_ADAPT_DEFAULT 0x89 ++ ++#define TX_EQTR_CAP_MASK 0x7F ++ ++#define TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT 8 ++#define TX_EQTR_ADAPT_RESERVED 0xFF ++ ++#define TX_HS_NUM_PRESHOOT 8 ++#define TX_HS_NUM_DEEMPHASIS 8 ++#define TX_HS_PRESHOOT_SHIFT 4 ++#define TX_HS_DEEMPHASIS_SHIFT 4 ++#define TX_HS_PRESHOOT_OFFSET 0 ++#define TX_HS_DEEMPHASIS_OFFSET 16 ++ ++#define TX_HS_PRESHOOT_LANE_SHIFT(lane) \ ++ (TX_HS_PRESHOOT_OFFSET + (lane) * TX_HS_PRESHOOT_SHIFT) ++#define TX_HS_DEEMPHASIS_LANE_SHIFT(lane) \ ++ (TX_HS_DEEMPHASIS_OFFSET + (lane) * TX_HS_DEEMPHASIS_SHIFT) ++ ++#define TX_HS_PRESHOOT_BITS(lane, val) \ ++ ((val) << TX_HS_PRESHOOT_LANE_SHIFT(lane)) ++#define TX_HS_DEEMPHASIS_BITS(lane, val) \ ++ ((val) << TX_HS_DEEMPHASIS_LANE_SHIFT(lane)) ++ ++#define RX_FOM_VALUE_MASK 0x7F ++#define RX_FOM_PRECODING_EN_BIT BIT(7) ++ ++#define PRECODEEN_TX_OFFSET 0 ++#define PRECODEEN_RX_OFFSET 4 ++#define PRECODEEN_TX_BIT(lane) (1 << (PRECODEEN_TX_OFFSET + (lane))) ++#define PRECODEEN_RX_BIT(lane) (1 << (PRECODEEN_RX_OFFSET + (lane))) ++ ++enum ufs_tx_eq_preset { ++ UFS_TX_EQ_PRESET_P0, ++ UFS_TX_EQ_PRESET_P1, ++ UFS_TX_EQ_PRESET_P2, ++ UFS_TX_EQ_PRESET_P3, ++ UFS_TX_EQ_PRESET_P4, ++ UFS_TX_EQ_PRESET_P5, ++ UFS_TX_EQ_PRESET_P6, ++ UFS_TX_EQ_PRESET_P7, ++ UFS_TX_EQ_PRESET_MAX, ++}; ++ ++enum ufs_tx_hs_preshoot { ++ UFS_TX_HS_PRESHOOT_DB_0P0, ++ UFS_TX_HS_PRESHOOT_DB_0P4, ++ UFS_TX_HS_PRESHOOT_DB_0P8, ++ UFS_TX_HS_PRESHOOT_DB_1P2, ++ UFS_TX_HS_PRESHOOT_DB_1P6, ++ UFS_TX_HS_PRESHOOT_DB_2P5, ++ UFS_TX_HS_PRESHOOT_DB_3P5, ++ UFS_TX_HS_PRESHOOT_DB_4P7, ++}; ++ ++enum ufs_tx_hs_deemphasis { ++ UFS_TX_HS_DEEMPHASIS_DB_0P0, ++ UFS_TX_HS_DEEMPHASIS_DB_0P8, ++ UFS_TX_HS_DEEMPHASIS_DB_1P6, ++ UFS_TX_HS_DEEMPHASIS_DB_2P5, ++ UFS_TX_HS_DEEMPHASIS_DB_3P5, ++ UFS_TX_HS_DEEMPHASIS_DB_4P7, ++ UFS_TX_HS_DEEMPHASIS_DB_6P0, ++ UFS_TX_HS_DEEMPHASIS_DB_7P6, ++}; ++ + #define DL_FC0ProtectionTimeOutVal_Default 8191 + #define DL_TC0ReplayTimeOutVal_Default 65535 + #define DL_AFC0ReqTimeOutVal_Default 32767 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux-lts-kmhv2/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch deleted file mode 100644 index de078902a8..0000000000 --- a/SPECS/linux-lts-kmhv2/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 39f4f9ff2f7384331b347a162c95587733dbc042 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 26 May 2026 15:22:58 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add Ziccrse - extension for X100 cores - -Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse -provides a forward progress guarantee on LR/SC sequences in main -memory regions with cacheability and coherence PMAs. - -The SpacemiT X100 core supports it per the SpacemiT K3 hardware -specification. - -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5b17612fe58e..ed046714a7ac 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -36,7 +36,7 @@ cpu_0: cpu@0 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -77,7 +77,7 @@ cpu_1: cpu@1 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -118,7 +118,7 @@ cpu_2: cpu@2 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -159,7 +159,7 @@ cpu_3: cpu@3 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -200,7 +200,7 @@ cpu_4: cpu@4 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -241,7 +241,7 @@ cpu_5: cpu@5 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -282,7 +282,7 @@ cpu_6: cpu@6 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -323,7 +323,7 @@ cpu_7: cpu@7 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0434-UPSTREAM-scsi-ufs-core-Add-debugfs-entries-for-TX-Eq.patch b/SPECS/linux-lts-kmhv2/0434-UPSTREAM-scsi-ufs-core-Add-debugfs-entries-for-TX-Eq.patch new file mode 100644 index 0000000000..f6dafbba18 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0434-UPSTREAM-scsi-ufs-core-Add-debugfs-entries-for-TX-Eq.patch @@ -0,0 +1,327 @@ +From 924b391d3abc1f92cc8dc08f5ed3c8976b083223 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:47 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add debugfs entries for TX + Equalization params + +Add debugfs support for UFS TX Equalization and UFS TX Equalization +Training (EQTR) to facilitate runtime inspection of link quality. These +entries allow developers to monitor and optimize TX Equalization parameters +and EQTR records during live operation. + +The debugfs entries are organized on a per-gear basis under the HBA's +debugfs root. Since TX EQTR is only defined for High Speed Gear 4 (HS-G4) +and above, EQTR-related entries are explicitly excluded for HS-G1 through +HS-G3 to avoid exposing unsupported attributes. + +The ufshcd's debugfs folder structure will look like below: + + /sys/kernel/debug/ufshcd/*ufs*/ + |--tx_eq_hs_gear1/ + | |--device_tx_eq_params + | |--host_tx_eq_params + |--tx_eq_hs_gear2/ + |--tx_eq_hs_gear3/ + |--tx_eq_hs_gear4/ + |--tx_eq_hs_gear5/ + |--tx_eq_hs_gear6/ + |--device_tx_eq_params + |--device_tx_eqtr_record + |--host_tx_eq_params + |--host_tx_eqtr_record + +Reviewed-by: Bart Van Assche +Reviewed-by: Bean Huo +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-6-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 10c40143f369a601cc54dd39777843e000b730a6) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-debugfs.c | 229 +++++++++++++++++++++++++++++++++ + drivers/ufs/core/ufs-txeq.c | 7 +- + drivers/ufs/core/ufshcd-priv.h | 2 + + 3 files changed, 237 insertions(+), 1 deletion(-) + +diff --git a/drivers/ufs/core/ufs-debugfs.c b/drivers/ufs/core/ufs-debugfs.c +index e3baed6c70bd..831758b45163 100644 +--- a/drivers/ufs/core/ufs-debugfs.c ++++ b/drivers/ufs/core/ufs-debugfs.c +@@ -209,6 +209,204 @@ static const struct ufs_debugfs_attr ufs_attrs[] = { + { } + }; + ++static int ufs_tx_eq_params_show(struct seq_file *s, void *data) ++{ ++ const char *file_name = s->file->f_path.dentry->d_name.name; ++ u32 gear = (u32)(uintptr_t)s->file->f_inode->i_private; ++ struct ufs_hba *hba = hba_from_file(s->file); ++ struct ufshcd_tx_eq_settings *settings; ++ struct ufs_pa_layer_attr *pwr_info; ++ struct ufshcd_tx_eq_params *params; ++ u32 rate = hba->pwr_info.hs_rate; ++ u32 num_lanes; ++ int lane; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return -EOPNOTSUPP; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) { ++ seq_printf(s, "Invalid gear selected: %u\n", gear); ++ return 0; ++ } ++ ++ if (!hba->max_pwr_info.is_valid) { ++ seq_puts(s, "Max power info is invalid\n"); ++ return 0; ++ } ++ ++ pwr_info = &hba->max_pwr_info.info; ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid) { ++ seq_printf(s, "TX EQ params are invalid for HS-G%u, Rate-%s\n", ++ gear, ufs_hs_rate_to_str(rate)); ++ return 0; ++ } ++ ++ if (strcmp(file_name, "host_tx_eq_params") == 0) { ++ settings = params->host; ++ num_lanes = pwr_info->lane_tx; ++ seq_printf(s, "Host TX EQ PreShoot Cap: 0x%02x, DeEmphasis Cap: 0x%02x\n", ++ hba->host_preshoot_cap, hba->host_deemphasis_cap); ++ } else if (strcmp(file_name, "device_tx_eq_params") == 0) { ++ settings = params->device; ++ num_lanes = pwr_info->lane_rx; ++ seq_printf(s, "Device TX EQ PreShoot Cap: 0x%02x, DeEmphasis Cap: 0x%02x\n", ++ hba->device_preshoot_cap, hba->device_deemphasis_cap); ++ } else { ++ return -ENOENT; ++ } ++ ++ seq_printf(s, "TX EQ setting for HS-G%u, Rate-%s:\n", gear, ++ ufs_hs_rate_to_str(rate)); ++ for (lane = 0; lane < num_lanes; lane++) ++ seq_printf(s, "TX Lane %d - PreShoot: %d, DeEmphasis: %d, Pre-Coding %senabled\n", ++ lane, settings[lane].preshoot, ++ settings[lane].deemphasis, ++ settings[lane].precode_en ? "" : "not "); ++ ++ return 0; ++} ++ ++static int ufs_tx_eq_params_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ufs_tx_eq_params_show, inode->i_private); ++} ++ ++static const struct file_operations ufs_tx_eq_params_fops = { ++ .owner = THIS_MODULE, ++ .open = ufs_tx_eq_params_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct ufs_debugfs_attr ufs_tx_eq_attrs[] = { ++ { "host_tx_eq_params", 0400, &ufs_tx_eq_params_fops }, ++ { "device_tx_eq_params", 0400, &ufs_tx_eq_params_fops }, ++ { } ++}; ++ ++static int ufs_tx_eqtr_record_show(struct seq_file *s, void *data) ++{ ++ const char *file_name = s->file->f_path.dentry->d_name.name; ++ u8 (*fom_array)[TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ u32 gear = (u32)(uintptr_t)s->file->f_inode->i_private; ++ unsigned long preshoot_bitmap, deemphasis_bitmap; ++ struct ufs_hba *hba = hba_from_file(s->file); ++ struct ufs_pa_layer_attr *pwr_info; ++ struct ufshcd_tx_eq_params *params; ++ struct ufshcd_tx_eqtr_record *rec; ++ u32 rate = hba->pwr_info.hs_rate; ++ u8 preshoot, deemphasis; ++ u32 num_lanes; ++ char name[32]; ++ int lane; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return -EOPNOTSUPP; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) { ++ seq_printf(s, "Invalid gear selected: %u\n", gear); ++ return 0; ++ } ++ ++ if (!hba->max_pwr_info.is_valid) { ++ seq_puts(s, "Max power info is invalid\n"); ++ return 0; ++ } ++ ++ pwr_info = &hba->max_pwr_info.info; ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid) { ++ seq_printf(s, "TX EQ params are invalid for HS-G%u, Rate-%s\n", ++ gear, ufs_hs_rate_to_str(rate)); ++ return 0; ++ } ++ ++ rec = params->eqtr_record; ++ if (!rec || !rec->last_record_index) { ++ seq_printf(s, "No TX EQTR records found for HS-G%u, Rate-%s.\n", ++ gear, ufs_hs_rate_to_str(rate)); ++ return 0; ++ } ++ ++ if (strcmp(file_name, "host_tx_eqtr_record") == 0) { ++ preshoot_bitmap = (hba->host_preshoot_cap << 0x1) | 0x1; ++ deemphasis_bitmap = (hba->host_deemphasis_cap << 0x1) | 0x1; ++ num_lanes = pwr_info->lane_tx; ++ fom_array = rec->host_fom; ++ snprintf(name, sizeof(name), "%s", "Host"); ++ } else if (strcmp(file_name, "device_tx_eqtr_record") == 0) { ++ preshoot_bitmap = (hba->device_preshoot_cap << 0x1) | 0x1; ++ deemphasis_bitmap = (hba->device_deemphasis_cap << 0x1) | 0x1; ++ num_lanes = pwr_info->lane_rx; ++ fom_array = rec->device_fom; ++ snprintf(name, sizeof(name), "%s", "Device"); ++ } else { ++ return -ENOENT; ++ } ++ ++ seq_printf(s, "%s TX EQTR record summary -\n", name); ++ seq_printf(s, "Target Power Mode: HS-G%u, Rate-%s\n", gear, ++ ufs_hs_rate_to_str(rate)); ++ seq_printf(s, "Most recent record index: %d\n", ++ rec->last_record_index); ++ seq_printf(s, "Most recent record timestamp: %llu us\n", ++ ktime_to_us(rec->last_record_ts)); ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ seq_printf(s, "\nTX Lane %d FOM - %s\n", lane, "PreShoot\\DeEmphasis"); ++ seq_puts(s, "\\"); ++ /* Print DeEmphasis header as X-axis. */ ++ for (deemphasis = 0; deemphasis < TX_HS_NUM_DEEMPHASIS; deemphasis++) ++ seq_printf(s, "%8d%s", deemphasis, " "); ++ seq_puts(s, "\n"); ++ /* Print matrix rows with PreShoot as Y-axis. */ ++ for (preshoot = 0; preshoot < TX_HS_NUM_PRESHOOT; preshoot++) { ++ seq_printf(s, "%d", preshoot); ++ for (deemphasis = 0; deemphasis < TX_HS_NUM_DEEMPHASIS; deemphasis++) { ++ if (test_bit(preshoot, &preshoot_bitmap) && ++ test_bit(deemphasis, &deemphasis_bitmap)) { ++ u8 fom = fom_array[lane][preshoot][deemphasis]; ++ u8 fom_val = fom & RX_FOM_VALUE_MASK; ++ bool precode_en = fom & RX_FOM_PRECODING_EN_BIT; ++ ++ if (ufshcd_is_txeq_presets_used(hba) && ++ !ufshcd_is_txeq_preset_selected(preshoot, deemphasis)) ++ seq_printf(s, "%8s%s", "-", " "); ++ else ++ seq_printf(s, "%8u%s", fom_val, ++ precode_en ? "*" : " "); ++ } else { ++ seq_printf(s, "%8s%s", "x", " "); ++ } ++ } ++ seq_puts(s, "\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int ufs_tx_eqtr_record_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ufs_tx_eqtr_record_show, inode->i_private); ++} ++ ++static const struct file_operations ufs_tx_eqtr_record_fops = { ++ .owner = THIS_MODULE, ++ .open = ufs_tx_eqtr_record_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct ufs_debugfs_attr ufs_tx_eqtr_attrs[] = { ++ { "host_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, ++ { "device_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, ++ { } ++}; ++ + void ufs_debugfs_hba_init(struct ufs_hba *hba) + { + const struct ufs_debugfs_attr *attr; +@@ -230,6 +428,37 @@ void ufs_debugfs_hba_init(struct ufs_hba *hba) + hba, &ee_usr_mask_fops); + debugfs_create_u32("exception_event_rate_limit_ms", 0600, hba->debugfs_root, + &hba->debugfs_ee_rate_limit_ms); ++ ++ if (!(hba->caps & UFSHCD_CAP_TX_EQUALIZATION)) ++ return; ++ ++ for (u32 gear = UFS_HS_G1; gear <= UFS_HS_GEAR_MAX; gear++) { ++ struct dentry *txeq_dir; ++ char name[32]; ++ ++ snprintf(name, sizeof(name), "tx_eq_hs_gear%d", gear); ++ txeq_dir = debugfs_create_dir(name, hba->debugfs_root); ++ if (IS_ERR_OR_NULL(txeq_dir)) ++ return; ++ ++ d_inode(txeq_dir)->i_private = hba; ++ ++ /* Create files for TX Equalization parameters */ ++ for (attr = ufs_tx_eq_attrs; attr->name; attr++) ++ debugfs_create_file(attr->name, attr->mode, txeq_dir, ++ (void *)(uintptr_t)gear, ++ attr->fops); ++ ++ /* TX EQTR is supported for HS-G4 and higher Gears */ ++ if (gear < UFS_HS_G4) ++ continue; ++ ++ /* Create files for TX EQTR related attributes */ ++ for (attr = ufs_tx_eqtr_attrs; attr->name; attr++) ++ debugfs_create_file(attr->name, attr->mode, txeq_dir, ++ (void *)(uintptr_t)gear, ++ attr->fops); ++ } + } + + void ufs_debugfs_hba_exit(struct ufs_hba *hba) +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +index 04f9f1ffa43e..b68a7af78290 100644 +--- a/drivers/ufs/core/ufs-txeq.c ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -375,7 +375,12 @@ static int ufshcd_get_rx_fom(struct ufs_hba *hba, + return ret; + } + +-static bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis) ++bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba) ++{ ++ return use_txeq_presets; ++} ++ ++bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis) + { + int i; + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index fbcea20c8991..671f33d153b0 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -109,6 +109,8 @@ void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba); + int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, + struct ufs_pa_layer_attr *pwr_mode); + void ufshcd_print_tx_eq_params(struct ufs_hba *hba); ++bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba); ++bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis); + + /* Wrapper functions for safely calling variant operations */ + static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux-lts-kmhv2/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch deleted file mode 100644 index 3c0a31840b..0000000000 --- a/SPECS/linux-lts-kmhv2/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 5bf0a7bd6d1da26628096529743d98bfd1be37e1 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 28 May 2026 19:38:39 +0800 -Subject: [RUYI PATCH] FROMLIST: RISC-V: KVM: Enhance the logging check for mmu - mapping - -When enabling dirty ring, the dirty bitmap is disable, and the logging -check is always false as the RISC-V architecture does not select -"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded -since the write path already trying to add the dirty log, the logic for -logging check is broken and some side effect will occurs. - -Enhance the logging check for mmu mapping so it can check both the dirty -ring and the dirty bitmap. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/kvm/mmu.c | 9 ++++----- - 1 file changed, 4 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c -index 58f5f3536ffd..a0d9c113258e 100644 ---- a/arch/riscv/kvm/mmu.c -+++ b/arch/riscv/kvm/mmu.c -@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, - enum kvm_mr_change change) - { - /* -- * At this point memslot has been committed and there is an -- * allocated dirty_bitmap[], dirty pages will be tracked while -- * the memory slot is write protected. -+ * At this point memslot has been committed and dirty pages will be -+ * tracked while the memory slot is write protected. - */ - if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) - mmu_wp_memory_region(kvm, new->id); -@@ -314,8 +313,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, - struct vm_area_struct *vma; - struct kvm *kvm = vcpu->kvm; - struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; -- bool logging = (memslot->dirty_bitmap && -- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; -+ bool logging = kvm_slot_dirty_track_enabled(memslot) && -+ !(memslot->flags & KVM_MEM_READONLY); - unsigned long vma_pagesize, mmu_seq; - struct kvm_gstage gstage; - struct page *page; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0435-UPSTREAM-scsi-ufs-core-Add-helpers-to-pause-and-resu.patch b/SPECS/linux-lts-kmhv2/0435-UPSTREAM-scsi-ufs-core-Add-helpers-to-pause-and-resu.patch new file mode 100644 index 0000000000..2694528bdd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0435-UPSTREAM-scsi-ufs-core-Add-helpers-to-pause-and-resu.patch @@ -0,0 +1,99 @@ +From b7110bcf92d44cdc75ad9e168c735756d83d118d Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:48 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add helpers to pause and + resume command processing + +In preparation for supporting TX Equalization refreshing, introduce helper +functions to safely pause and resume command processing. + +ufshcd_pause_command_processing() ensures the host is in a quiescent state +by stopping the block layer tagset, acquiring the necessary locks +(scan_mutex and clk_scaling_lock), and waiting for any in-flight commands +to complete within a specified timeout. + +ufshcd_resume_command_processing() restores the host to its previous +operational state by reversing these steps in the correct order. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-7-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit dc5dcac5327832bffc1971b1445553823bdebc08) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd-priv.h | 2 ++ + drivers/ufs/core/ufshcd.c | 42 ++++++++++++++++++++++++++++++++++ + 2 files changed, 44 insertions(+) + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 671f33d153b0..6ff4badba0f2 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -79,6 +79,8 @@ int ufshcd_mcq_abort(struct scsi_cmnd *cmd); + int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag); + void ufshcd_release_scsi_cmd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp); ++int ufshcd_pause_command_processing(struct ufs_hba *hba, u64 timeout_us); ++void ufshcd_resume_command_processing(struct ufs_hba *hba); + + /** + * enum ufs_descr_fmt - UFS string descriptor format +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 51e431a04ee4..5f75f95957a4 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -1361,6 +1361,48 @@ static int ufshcd_wait_for_pending_cmds(struct ufs_hba *hba, + return ret; + } + ++/** ++ * ufshcd_pause_command_processing - Pause command processing ++ * @hba: per-adapter instance ++ * @timeout_us: timeout in microseconds to wait for pending commands to finish ++ * ++ * This function stops new command submissions and waits for existing commands ++ * to complete. ++ * ++ * Return: 0 on success, %-EBUSY if commands did not finish within @timeout_us. ++ * On failure, all acquired locks are released and the tagset is unquiesced. ++ */ ++int ufshcd_pause_command_processing(struct ufs_hba *hba, u64 timeout_us) ++{ ++ int ret = 0; ++ ++ mutex_lock(&hba->host->scan_mutex); ++ blk_mq_quiesce_tagset(&hba->host->tag_set); ++ down_write(&hba->clk_scaling_lock); ++ ++ if (ufshcd_wait_for_pending_cmds(hba, timeout_us)) { ++ ret = -EBUSY; ++ up_write(&hba->clk_scaling_lock); ++ blk_mq_unquiesce_tagset(&hba->host->tag_set); ++ mutex_unlock(&hba->host->scan_mutex); ++ } ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_resume_command_processing - Resume command processing ++ * @hba: per-adapter instance ++ * ++ * This function resumes command submissions. ++ */ ++void ufshcd_resume_command_processing(struct ufs_hba *hba) ++{ ++ up_write(&hba->clk_scaling_lock); ++ blk_mq_unquiesce_tagset(&hba->host->tag_set); ++ mutex_unlock(&hba->host->scan_mutex); ++} ++ + /** + * ufshcd_scale_gear - scale up/down UFS gear + * @hba: per adapter instance +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch deleted file mode 100644 index 3af359443c..0000000000 --- a/SPECS/linux-lts-kmhv2/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 1089052df50a4781f12e65e68f2cfeb75dca9d84 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 2 Jun 2026 18:00:00 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi - R2S - -Enable the two RTL8125 network controllers and corresponding -PHYs connected via the PCIe controllers on the OrangePi R2S. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ - 1 file changed, 38 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index b13a8d6a2670..919e5b451109 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -23,6 +23,14 @@ chosen { - stdout-path = "serial0"; - }; - -+ pcie_vcc3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - vcc4v0: regulator-vcc4v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc4v0"; -@@ -228,6 +236,36 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie2 { -+ status = "okay"; -+}; -+ - &pdma { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0436-UPSTREAM-scsi-ufs-core-Add-support-to-retrain-TX-Equ.patch b/SPECS/linux-lts-kmhv2/0436-UPSTREAM-scsi-ufs-core-Add-support-to-retrain-TX-Equ.patch new file mode 100644 index 0000000000..27e31c0520 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0436-UPSTREAM-scsi-ufs-core-Add-support-to-retrain-TX-Equ.patch @@ -0,0 +1,390 @@ +From fbdcf3ab4ffed53e1826cd4abfb673fb3b5288f7 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:49 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add support to retrain TX + Equalization via debugfs + +Drastic environmental changes, such as significant temperature shifts, can +impact link signal integrity. In such cases, retraining TX Equalization is +necessary to compensate for these environmental changes. + +Add a debugfs entry, 'tx_eq_ctrl', to allow userspace to manually trigger +the TX Equalization training (EQTR) procedure and apply the identified +optimal settings on the fly. These entries are created on a per-gear basis +for High Speed Gear 4 (HS-G4) and above, as TX EQTR is not supported for +lower gears. + +The 'tx_eq_ctrl' entry currently accepts the 'retrain' command to initiate +the procedure. The interface is designed to be scalable to support +additional commands in the future. + +Reading the 'tx_eq_ctrl' entry provides a usage hint to the user, ensuring +the interface is self-documenting. + +The ufshcd's debugfs folder structure will look like below: + + /sys/kernel/debug/ufshcd/*ufs*/ + |--tx_eq_hs_gear1/ + | |--device_tx_eq_params + | |--host_tx_eq_params + |--tx_eq_hs_gear2/ + |--tx_eq_hs_gear3/ + |--tx_eq_hs_gear4/ + |--tx_eq_hs_gear5/ + |--tx_eq_hs_gear6/ + |--device_tx_eq_params + |--device_tx_eqtr_record + |--host_tx_eq_params + |--host_tx_eqtr_record + |--tx_eq_ctrl + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-8-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit adbabdcf0db0f929e642f95d7528dce0f6bd3a11) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-debugfs.c | 61 ++++++++++++++++++ + drivers/ufs/core/ufs-txeq.c | 110 +++++++++++++++++++++++++++++++-- + drivers/ufs/core/ufshcd-priv.h | 5 +- + drivers/ufs/core/ufshcd.c | 7 +-- + include/ufs/ufshcd.h | 2 + + 5 files changed, 175 insertions(+), 10 deletions(-) + +diff --git a/drivers/ufs/core/ufs-debugfs.c b/drivers/ufs/core/ufs-debugfs.c +index 831758b45163..e3dd81d6fe82 100644 +--- a/drivers/ufs/core/ufs-debugfs.c ++++ b/drivers/ufs/core/ufs-debugfs.c +@@ -401,9 +401,70 @@ static const struct file_operations ufs_tx_eqtr_record_fops = { + .release = single_release, + }; + ++static ssize_t ufs_tx_eq_ctrl_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ u32 gear = (u32)(uintptr_t)file->f_inode->i_private; ++ struct ufs_hba *hba = hba_from_file(file); ++ char kbuf[32]; ++ int ret; ++ ++ if (count >= sizeof(kbuf)) ++ return -EINVAL; ++ ++ if (copy_from_user(kbuf, buf, count)) ++ return -EFAULT; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return -EOPNOTSUPP; ++ ++ if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || ++ !hba->max_pwr_info.is_valid) ++ return -EBUSY; ++ ++ if (!hba->ufs_device_wlun) ++ return -ENODEV; ++ ++ kbuf[count] = '\0'; ++ ++ if (sysfs_streq(kbuf, "retrain")) { ++ ret = ufs_debugfs_get_user_access(hba); ++ if (ret) ++ return ret; ++ ret = ufshcd_retrain_tx_eq(hba, gear); ++ ufs_debugfs_put_user_access(hba); ++ } else { ++ /* Unknown operation */ ++ return -EINVAL; ++ } ++ ++ return ret ? ret : count; ++} ++ ++static int ufs_tx_eq_ctrl_show(struct seq_file *s, void *data) ++{ ++ seq_puts(s, "write 'retrain' to retrain TX Equalization settings\n"); ++ return 0; ++} ++ ++static int ufs_tx_eq_ctrl_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ufs_tx_eq_ctrl_show, inode->i_private); ++} ++ ++static const struct file_operations ufs_tx_eq_ctrl_fops = { ++ .owner = THIS_MODULE, ++ .open = ufs_tx_eq_ctrl_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = ufs_tx_eq_ctrl_write, ++ .release = single_release, ++}; ++ + static const struct ufs_debugfs_attr ufs_tx_eqtr_attrs[] = { + { "host_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, + { "device_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, ++ { "tx_eq_ctrl", 0600, &ufs_tx_eq_ctrl_fops }, + { } + }; + +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +index b68a7af78290..3a879c644faa 100644 +--- a/drivers/ufs/core/ufs-txeq.c ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -628,9 +628,15 @@ static int ufshcd_setup_tx_eqtr_adapt_length(struct ufs_hba *hba, + struct ufshcd_tx_eq_params *params, + u32 gear) + { ++ struct ufshcd_tx_eqtr_record *rec = params->eqtr_record; + u32 adapt_eqtr; + int ret; + ++ if (rec && rec->saved_adapt_eqtr) { ++ adapt_eqtr = rec->saved_adapt_eqtr; ++ goto set_adapt_eqtr; ++ } ++ + if (gear == UFS_HS_G4 || gear == UFS_HS_G5) { + u64 t_adapt, t_adapt_local, t_adapt_peer; + u32 adapt_cap_local, adapt_cap_peer, adapt_length; +@@ -782,6 +788,10 @@ static int ufshcd_setup_tx_eqtr_adapt_length(struct ufs_hba *hba, + return -EINVAL; + } + ++ if (rec) ++ rec->saved_adapt_eqtr = (u16)adapt_eqtr; ++ ++set_adapt_eqtr: + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXADAPTLENGTH_EQTR), adapt_eqtr); + if (ret) + dev_err(hba->dev, "Failed to set adapt length for TX EQTR: %d\n", ret); +@@ -847,16 +857,33 @@ static int ufshcd_apply_tx_eqtr_settings(struct ufs_hba *hba, + /** + * ufshcd_update_tx_eq_params - Update TX Equalization params + * @params: TX EQ parameters data structure ++ * @pwr_mode: target power mode containing gear and rate + * @eqtr_data: TX EQTR data structure + * +- * Update TX Equalization params using results from TX EQTR data. ++ * Update TX Equalization params using results from TX EQTR data. Check also ++ * the TX EQTR FOM value for each TX lane in the TX EQTR data. If a TX lane got ++ * a FOM value of 0, restore the TX Equalization settings from the last known ++ * valid TX Equalization params for that specific TX lane. + */ + static inline void + ufshcd_update_tx_eq_params(struct ufshcd_tx_eq_params *params, ++ struct ufs_pa_layer_attr *pwr_mode, + struct ufshcd_tx_eqtr_data *eqtr_data) + { + struct ufshcd_tx_eqtr_record *rec = params->eqtr_record; + ++ if (params->is_valid) { ++ int lane; ++ ++ for (lane = 0; lane < pwr_mode->lane_tx; lane++) ++ if (eqtr_data->host[lane].fom_val == 0) ++ eqtr_data->host[lane] = params->host[lane]; ++ ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) ++ if (eqtr_data->device[lane].fom_val == 0) ++ eqtr_data->device[lane] = params->device[lane]; ++ } ++ + memcpy(params->host, eqtr_data->host, sizeof(params->host)); + memcpy(params->device, eqtr_data->device, sizeof(params->device)); + +@@ -955,7 +982,7 @@ static int __ufshcd_tx_eqtr(struct ufs_hba *hba, + dev_info(hba->dev, "TX EQTR procedure completed! Time elapsed: %llu ms\n", + ktime_to_ms(ktime_sub(ktime_get(), start))); + +- ufshcd_update_tx_eq_params(params, eqtr_data); ++ ufshcd_update_tx_eq_params(params, pwr_mode, eqtr_data); + + return ret; + } +@@ -1079,6 +1106,7 @@ static int ufshcd_tx_eqtr(struct ufs_hba *hba, + * ufshcd_config_tx_eq_settings - Configure TX Equalization settings + * @hba: per adapter instance + * @pwr_mode: target power mode containing gear and rate information ++ * @force_tx_eqtr: execute the TX EQTR procedure + * + * This function finds and sets the TX Equalization settings for the given + * target power mode. +@@ -1086,7 +1114,8 @@ static int ufshcd_tx_eqtr(struct ufs_hba *hba, + * Returns 0 on success, error code otherwise + */ + int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++ struct ufs_pa_layer_attr *pwr_mode, ++ bool force_tx_eqtr) + { + struct ufshcd_tx_eq_params *params; + u32 gear, rate; +@@ -1123,7 +1152,7 @@ int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, + } + + params = &hba->tx_eq_params[gear - 1]; +- if (!params->is_valid) { ++ if (!params->is_valid || force_tx_eqtr) { + int ret; + + ret = ufshcd_tx_eqtr(hba, params, pwr_mode); +@@ -1189,3 +1218,76 @@ void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba) + } + } + } ++ ++/** ++ * ufshcd_retrain_tx_eq - Retrain TX Equalization and apply new settings ++ * @hba: per-adapter instance ++ * @gear: target High-Speed (HS) gear for retraining ++ * ++ * This function initiates a refresh of the TX Equalization settings for a ++ * specific HS gear. It scales the clocks to maximum frequency, negotiates the ++ * power mode with the device, retrains TX EQ and applies new TX EQ settings ++ * by conducting a Power Mode change. ++ * ++ * Returns 0 on success, non-zero error code otherwise ++ */ ++int ufshcd_retrain_tx_eq(struct ufs_hba *hba, u32 gear) ++{ ++ struct ufs_pa_layer_attr new_pwr_info, final_params = {}; ++ int ret; ++ ++ if (!ufshcd_is_tx_eq_supported(hba) || !use_adaptive_txeq) ++ return -EOPNOTSUPP; ++ ++ if (gear < adaptive_txeq_gear) ++ return -ERANGE; ++ ++ ufshcd_hold(hba); ++ ++ ret = ufshcd_pause_command_processing(hba, 1 * USEC_PER_SEC); ++ if (ret) { ++ ufshcd_release(hba); ++ return ret; ++ } ++ ++ /* scale up clocks to max frequency before TX EQTR */ ++ if (ufshcd_is_clkscaling_supported(hba)) ++ ufshcd_scale_clks(hba, ULONG_MAX, true); ++ ++ new_pwr_info = hba->pwr_info; ++ new_pwr_info.gear_tx = gear; ++ new_pwr_info.gear_rx = gear; ++ ++ ret = ufshcd_vops_negotiate_pwr_mode(hba, &new_pwr_info, &final_params); ++ if (ret) ++ memcpy(&final_params, &new_pwr_info, sizeof(final_params)); ++ ++ if (final_params.gear_tx != gear) { ++ dev_err(hba->dev, "Negotiated Gear (%u) does not match target Gear (%u)\n", ++ final_params.gear_tx, gear); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = ufshcd_config_tx_eq_settings(hba, &final_params, true); ++ if (ret) { ++ dev_err(hba->dev, "Failed to config TX Equalization for HS-G%u, Rate-%s: %d\n", ++ final_params.gear_tx, ++ ufs_hs_rate_to_str(final_params.hs_rate), ret); ++ goto out; ++ } ++ ++ /* Change Power Mode to apply the new TX EQ settings */ ++ ret = ufshcd_change_power_mode(hba, &final_params, ++ UFSHCD_PMC_POLICY_FORCE); ++ if (ret) ++ dev_err(hba->dev, "%s: Failed to change Power Mode to HS-G%u, Rate-%s: %d\n", ++ __func__, final_params.gear_tx, ++ ufs_hs_rate_to_str(final_params.hs_rate), ret); ++ ++out: ++ ufshcd_resume_command_processing(hba); ++ ufshcd_release(hba); ++ ++ return ret; ++} +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 6ff4badba0f2..dcff75f75dac 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -81,6 +81,7 @@ void ufshcd_release_scsi_cmd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp); + int ufshcd_pause_command_processing(struct ufs_hba *hba, u64 timeout_us); + void ufshcd_resume_command_processing(struct ufs_hba *hba); ++int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, bool scale_up); + + /** + * enum ufs_descr_fmt - UFS string descriptor format +@@ -109,10 +110,12 @@ int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id); + int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear); + void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba); + int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode); ++ struct ufs_pa_layer_attr *pwr_mode, ++ bool force_tx_eqtr); + void ufshcd_print_tx_eq_params(struct ufs_hba *hba); + bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba); + bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis); ++int ufshcd_retrain_tx_eq(struct ufs_hba *hba, u32 gear); + + /* Wrapper functions for safely calling variant operations */ + static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 5f75f95957a4..1686bb5630d4 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -330,8 +330,6 @@ static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); + static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); + static void ufshcd_resume_clkscaling(struct ufs_hba *hba); + static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); +-static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, +- bool scale_up); + static irqreturn_t ufshcd_intr(int irq, void *__hba); + static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); + static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); +@@ -1207,8 +1205,7 @@ static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) + * + * Return: 0 if successful; < 0 upon failure. + */ +-static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, +- bool scale_up) ++int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, bool scale_up) + { + int ret = 0; + ktime_t start = ktime_get(); +@@ -4896,7 +4893,7 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); + } + +- ret = ufshcd_config_tx_eq_settings(hba, &final_params); ++ ret = ufshcd_config_tx_eq_settings(hba, &final_params, false); + if (ret) + dev_warn(hba->dev, "Failed to configure TX Equalization for HS-G%u, Rate-%s: %d\n", + final_params.gear_tx, +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 77634e07cbb3..8bb279c0e992 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -346,12 +346,14 @@ struct ufshcd_tx_eqtr_data { + * @device_fom: Device TX EQTR FOM record + * @last_record_ts: Timestamp of the most recent TX EQTR record + * @last_record_index: Index of the most recent TX EQTR record ++ * @saved_adapt_eqtr: Saved Adaptation length setting for TX EQTR + */ + struct ufshcd_tx_eqtr_record { + u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; + u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; + ktime_t last_record_ts; + u16 last_record_index; ++ u16 saved_adapt_eqtr; + }; + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch b/SPECS/linux-lts-kmhv2/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch deleted file mode 100644 index 0150c1e446..0000000000 --- a/SPECS/linux-lts-kmhv2/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 63031abd1c4c52dfc3b406612721eff99c69ed49 Mon Sep 17 00:00:00 2001 -From: Wang Yechao -Date: Thu, 4 Jun 2026 14:55:10 +0800 -Subject: [RUYI PATCH] FROMLIST: iommu/riscv: Add dependency between iommu and - devices - -Commit 9156585280f1 ("ACPI: RIMT: Add dependency between iommu and -devices") adds the dependency between iommu and devices on ACPI -systems. On devicetree systems, the incorrect removal order also -occurs. - -It can be reproduced on the QEMU RISC-V machine if the kernel enables -IOMMU_DMA: - -[ 635.081530] e1000e: EEE TX LPI TIMER: 00000000 -[ 656.100306] rcu: INFO: rcu_sched self-detected stall on CPU -[ 656.101374] rcu: 5-....: (5250 ticks this GP) idle=d774/1/0x4000000000000000 softirq=5173/5185 fqs=2625 -[ 656.102237] rcu: (t=5251 jiffies g=36825 q=101 ncpus=16) -[ 656.103801] CPU: 5 UID: 0 PID: 1958 Comm: reboot Tainted: G W 7.1.0-rc5 #31 PREEMPTLAZY -[ 656.104127] Tainted: [W]=WARN -[ 656.104182] Hardware name: QEMU QEMU Virtual Machine, BIOS 2.7 02/02/2022 -[ 656.104339] epc : riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 -[ 656.105352] ra : riscv_iommu_cmd_sync.constprop.0+0xa8/0x148 -[ 656.105433] epc : ffffffff807ca980 ra : ffffffff807ca970 sp : ff60000085dbf960 -[ 656.105475] gp : ffffffff81e0d798 tp : ff60000084b58e00 t0 : ffffffff80021048 -[ 656.105514] t1 : ff60000081b18400 t2 : 45203a6530303031 s0 : ff60000085dbf9c0 -[ 656.105554] s1 : 00000098c92a567c a0 : 00000098c03986f0 a1 : ff60000085dbf970 -[ 656.105594] a2 : 000024bb5cac6aee a3 : ff200000004f1000 a4 : ff6000008140a040 -[ 656.105632] a5 : 0000000000000669 a6 : 0000000000000000 a7 : 00000000ffffa000 -[ 656.105669] s2 : 0000000000000000 s3 : 00000098c0398308 s4 : 000000000000066a -[ 656.105706] s5 : 0000000008f0d180 s6 : 000000a8d08b8de9 s7 : 0000000000001fff -[ 656.105743] s8 : ff6000008140a040 s9 : ff6000008484cb00 s10: ff200000005cc000 -[ 656.105781] s11: ff600000814652a0 t3 : 000000f000000000 t4 : 0000000000000000 -[ 656.105845] t5 : 0000000000000003 t6 : ff600000841666b0 ssp : 0000000000000000 -[ 656.105883] status: 0000000200000120 badaddr: 0000000000000000 cause: 8000000000000005 -[ 656.106072] riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 -[ 656.106321] riscv_iommu_iotlb_inval+0x120/0x160 -[ 656.106373] riscv_iommu_iotlb_sync+0x48/0x60 -[ 656.106422] __iommu_dma_unmap+0xca/0xf8 -[ 656.106470] iommu_dma_unmap_phys+0x58/0xc8 -[ 656.106517] dma_unmap_phys+0x15c/0x248 -[ 656.106564] dma_unmap_page_attrs+0x1e/0x30 -[ 656.106915] e1000_clean_rx_ring+0x1d2/0x200 [e1000e] -[ 656.107668] e1000e_down+0x168/0x1c8 [e1000e] -[ 656.107995] e1000e_pm_freeze+0x94/0x128 [e1000e] -[ 656.108328] e1000_shutdown+0x28/0x48 [e1000e] -[ 656.108652] pci_device_shutdown+0x34/0x48 -[ 656.108706] device_shutdown+0x104/0x1e8 -[ 656.108752] kernel_restart+0x46/0xb8 -[ 656.108797] __do_sys_reboot+0xc0/0x1c8 -[ 656.108840] __riscv_sys_reboot+0x22/0x38 -[ 656.108882] do_trap_ecall_u+0x236/0x3f8 -[ 656.108947] handle_exception+0x15a/0x166 - -So move the device link into the iommu driver to fix both ACPI and -devicetree systems. - -Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") -Signed-off-by: Wang Yechao -Link: https://lore.kernel.org/r/20260604145510898G2kTwM2Pr25QE5H8T4Wh6@zte.com.cn -Signed-off-by: Han Gao ---- - drivers/acpi/riscv/rimt.c | 7 ------- - drivers/iommu/riscv/iommu.c | 7 +++++++ - 2 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c -index 8eaa8731bddd..7f423405e5ef 100644 ---- a/drivers/acpi/riscv/rimt.c -+++ b/drivers/acpi/riscv/rimt.c -@@ -263,13 +263,6 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 - if (!rimt_fwnode) - return -EPROBE_DEFER; - -- /* -- * EPROBE_DEFER ensures IOMMU is probed before the devices that -- * depend on them. During shutdown, however, the IOMMU may be removed -- * first, leading to issues. To avoid this, a device link is added -- * which enforces the correct removal order. -- */ -- device_link_add(dev, rimt_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); - return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode); - } - -diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c -index de286563bd44..07ae3c4ec38e 100644 ---- a/drivers/iommu/riscv/iommu.c -+++ b/drivers/iommu/riscv/iommu.c -@@ -1598,6 +1598,13 @@ static struct iommu_device *riscv_iommu_probe_device(struct device *dev) - - dev_iommu_priv_set(dev, info); - -+ /* -+ * During shutdown, however, the IOMMU may be removed first, leading -+ * to issues. To avoid this, a device link is added which enforces -+ * the correct removal order. -+ */ -+ device_link_add(dev, fwspec->iommu_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); -+ - return &iommu->iommu; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0437-UPSTREAM-scsi-ufs-ufs-qcom-Fixup-PAM-4-TX-L0_L1_L2_L.patch b/SPECS/linux-lts-kmhv2/0437-UPSTREAM-scsi-ufs-ufs-qcom-Fixup-PAM-4-TX-L0_L1_L2_L.patch new file mode 100644 index 0000000000..cb35bed61c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0437-UPSTREAM-scsi-ufs-ufs-qcom-Fixup-PAM-4-TX-L0_L1_L2_L.patch @@ -0,0 +1,235 @@ +From d1c820cddd79d0e3c2a54ce0cb201d451088a0bf Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:50 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Fixup PAM-4 TX + L0_L1_L2_L3 adaptation pattern length + +If HS-G6 Power Mode change handshake is successful and outbound data Lanes +are expected to transmit ADAPT, M-TX Lanes shall be configured as + + if (Adapt Type == REFRESH) + TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 = PA_PeerRxHsG6AdaptRefreshL0L1L2L3. + else if (Adapt Type == INITIAL) + TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 = PA_PeerRxHsG6AdaptInitialL0L1L2L3. + +On some platforms, the ADAPT_L0_L1_L2_L3 duration on Host TX Lanes is only +a half of theoretical ADAPT_L0_L1_L2_L3 duration TADAPT_L0_L1_L2_L3 (in +PAM-4 UI) calculated from TX_HS_ADAPT_LENGTH_L0_L1_L2_L3. + +For such platforms, the workaround is to double the ADAPT_L0_L1_L2_L3 +duration by uplifting TX_HS_ADAPT_LENGTH_L0_L1_L2_L3. UniPro initializes +TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 during HS-G6 Power Mode change handshake, it +would be too late for SW to update TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 post +HS-G6 Power Mode change. Update PA_PeerRxHsG6AdaptRefreshL0L1L2L3 and +PA_PeerRxHsG6AdaptInitialL0L1L2L3 post Link Startup and before HS-G6 Power +Mode change, so that the UniPro would use the updated value during HS-G6 +Power Mode change handshake. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-9-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 53c94067efa252e20f813c6eb714dc1cddf06aaa) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 178 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 178 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index fec0ecad6be1..f6ba37e1a931 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -1020,10 +1020,188 @@ static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) + dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); + } + ++/** ++ * ufs_qcom_double_t_adapt_l0l1l2l3 - Create a new adapt that doubles the ++ * adaptation duration TADAPT_L0_L1_L2_L3 derived from the old adapt. ++ * ++ * @old_adapt: Original ADAPT_L0_L1_L2_L3 capability ++ * ++ * ADAPT_length_L0_L1_L2_L3 formula from M-PHY spec: ++ * if (ADAPT_range_L0_L1_L2_L3 == COARSE) { ++ * ADAPT_length_L0_L1_L2_L3 = [0, 12] ++ * ADAPT_L0_L1_L2_L3 = 215 x 2^ADAPT_length_L0_L1_L2_L3 ++ * } else if (ADAPT_range_L0_L1_L2_L3 == FINE) { ++ * ADAPT_length_L0_L1_L2_L3 = [0, 127] ++ * TADAPT_L0_L1_L2_L3 = 215 x (ADAPT_length_L0_L1_L2_L3 + 1) ++ * } ++ * ++ * To double the adaptation duration TADAPT_L0_L1_L2_L3: ++ * 1. If adapt range is COARSE (1'b1), new adapt = old adapt + 1. ++ * 2. If adapt range is FINE (1'b0): ++ * a) If old adapt length is < 64, (new adapt + 1) = 2 * (old adapt + 1). ++ * b) If old adapt length is >= 64, set new adapt to 0x88 using COARSE ++ * range, because new adapt get from equation in a) shall exceed 127. ++ * ++ * Examples: ++ * ADAPT_range_L0_L1_L2_L3 | ADAPT_length_L0_L1_L2_L3 | TADAPT_L0_L1_L2_L3 (PAM-4 UI) ++ * 0 3 131072 ++ * 0 7 262144 ++ * 0 63 2097152 ++ * 0 64 2129920 ++ * 0 127 4194304 ++ * 1 8 8388608 ++ * 1 9 16777216 ++ * 1 10 33554432 ++ * 1 11 67108864 ++ * 1 12 134217728 ++ * ++ * Return: new adapt. ++ */ ++static u32 ufs_qcom_double_t_adapt_l0l1l2l3(u32 old_adapt) ++{ ++ u32 adapt_length = old_adapt & ADAPT_LENGTH_MASK; ++ u32 new_adapt; ++ ++ if (IS_ADAPT_RANGE_COARSE(old_adapt)) { ++ new_adapt = (adapt_length + 1) | ADAPT_RANGE_BIT; ++ } else { ++ if (adapt_length < 64) ++ new_adapt = (adapt_length << 1) + 1; ++ else ++ /* ++ * 0x88 is the very coarse Adapt value which is two ++ * times of the largest fine Adapt value (0x7F) ++ */ ++ new_adapt = 0x88; ++ } ++ ++ return new_adapt; ++} ++ ++static void ufs_qcom_limit_max_gear(struct ufs_hba *hba, ++ enum ufs_hs_gear_tag gear) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ struct ufs_host_params *host_params = &host->host_params; ++ ++ host_params->hs_tx_gear = gear; ++ host_params->hs_rx_gear = gear; ++ pwr_info->gear_tx = gear; ++ pwr_info->gear_rx = gear; ++ ++ dev_warn(hba->dev, "Limited max gear of host and device to HS-G%d\n", gear); ++} ++ ++static void ufs_qcom_fixup_tx_adapt_l0l1l2l3(struct ufs_hba *hba) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ struct ufs_host_params *host_params = &host->host_params; ++ u32 old_adapt, new_adapt, actual_adapt; ++ bool limit_speed = false; ++ int err; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 || ++ host_params->hs_tx_gear <= UFS_HS_G5 || ++ pwr_info->gear_tx <= UFS_HS_G5) ++ return; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), &old_adapt); ++ if (err) ++ goto out; ++ ++ if (old_adapt > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "PA_PeerRxHsG6AdaptInitialL0L1L2L3 value (0x%x) exceeds MAX\n", ++ old_adapt); ++ err = -ERANGE; ++ goto out; ++ } ++ ++ new_adapt = ufs_qcom_double_t_adapt_l0l1l2l3(old_adapt); ++ dev_dbg(hba->dev, "Original PA_PeerRxHsG6AdaptInitialL0L1L2L3 = 0x%x, new value = 0x%x\n", ++ old_adapt, new_adapt); ++ ++ /* ++ * 0x8C is the max possible value allowed by UniPro v3.0 spec, some HWs ++ * can accept 0x8D but some cannot. ++ */ ++ if (new_adapt <= ADAPT_L0L1L2L3_LENGTH_MAX || ++ (new_adapt == ADAPT_L0L1L2L3_LENGTH_MAX + 1 && host->hw_ver.minor == 0x1)) { ++ err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), ++ new_adapt); ++ if (err) ++ goto out; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), ++ &actual_adapt); ++ if (err) ++ goto out; ++ ++ if (actual_adapt != new_adapt) { ++ limit_speed = true; ++ dev_warn(hba->dev, "PA_PeerRxHsG6AdaptInitialL0L1L2L3 0x%x, expect 0x%x\n", ++ actual_adapt, new_adapt); ++ } ++ } else { ++ limit_speed = true; ++ dev_warn(hba->dev, "New PA_PeerRxHsG6AdaptInitialL0L1L2L3 (0x%x) is too large!\n", ++ new_adapt); ++ } ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), &old_adapt); ++ if (err) ++ goto out; ++ ++ if (old_adapt > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "PA_PeerRxHsG6AdaptRefreshL0L1L2L3 value (0x%x) exceeds MAX\n", ++ old_adapt); ++ err = -ERANGE; ++ goto out; ++ } ++ ++ new_adapt = ufs_qcom_double_t_adapt_l0l1l2l3(old_adapt); ++ dev_dbg(hba->dev, "Original PA_PeerRxHsG6AdaptRefreshL0L1L2L3 = 0x%x, new value = 0x%x\n", ++ old_adapt, new_adapt); ++ ++ /* ++ * 0x8C is the max possible value allowed by UniPro v3.0 spec, some HWs ++ * can accept 0x8D but some cannot. ++ */ ++ if (new_adapt <= ADAPT_L0L1L2L3_LENGTH_MAX || ++ (new_adapt == ADAPT_L0L1L2L3_LENGTH_MAX + 1 && host->hw_ver.minor == 0x1)) { ++ err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), ++ new_adapt); ++ if (err) ++ goto out; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), ++ &actual_adapt); ++ if (err) ++ goto out; ++ ++ if (actual_adapt != new_adapt) { ++ limit_speed = true; ++ dev_warn(hba->dev, "PA_PeerRxHsG6AdaptRefreshL0L1L2L3 0x%x, expect 0x%x\n", ++ new_adapt, actual_adapt); ++ } ++ } else { ++ limit_speed = true; ++ dev_warn(hba->dev, "New PA_PeerRxHsG6AdaptRefreshL0L1L2L3 (0x%x) is too large!\n", ++ new_adapt); ++ } ++ ++out: ++ if (limit_speed || err) ++ ufs_qcom_limit_max_gear(hba, UFS_HS_G5); ++} ++ + static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) + { + int err = 0; + ++ ufs_qcom_fixup_tx_adapt_l0l1l2l3(hba); ++ + if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) + err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0438-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-tx_eqtr_no.patch b/SPECS/linux-lts-kmhv2/0438-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-tx_eqtr_no.patch new file mode 100644 index 0000000000..a99ee8451f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0438-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-tx_eqtr_no.patch @@ -0,0 +1,87 @@ +From 7386d5488c789d7d66d43d537816f45eaf515f71 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:51 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Implement vops + tx_eqtr_notify() + +On some platforms, HW does not support triggering TX EQTR from the most +reliable High-Speed (HS) Gear (HS Gear1), but only allows to trigger TX +EQTR for the target HS Gear from the same HS Gear. To work around the HW +limitation, implement vops tx_eqtr_notify() to change Power Mode to the +target TX EQTR HS Gear prior to TX EQTR procedure and change Power Mode +back to HS Gear1 (the most reliable gear) post TX EQTR procedure. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-10-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 385b95893e799885ec54a4ec2e240b1d814205be) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 41 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index f6ba37e1a931..57171f69b12a 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -2382,6 +2382,46 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) + return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); + } + ++static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr pwr_mode_hs_g1 = { ++ .gear_rx = UFS_HS_G1, ++ .gear_tx = UFS_HS_G1, ++ .lane_rx = pwr_mode->lane_rx, ++ .lane_tx = pwr_mode->lane_tx, ++ .pwr_rx = FAST_MODE, ++ .pwr_tx = FAST_MODE, ++ .hs_rate = pwr_mode->hs_rate, ++ }; ++ u32 gear = pwr_mode->gear_tx; ++ u32 rate = pwr_mode->hs_rate; ++ int ret; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) ++ return 0; ++ ++ if (status == PRE_CHANGE) { ++ /* PMC to target HS Gear. */ ++ ret = ufshcd_change_power_mode(hba, pwr_mode, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (ret) ++ dev_err(hba->dev, "%s: Failed to PMC to target HS-G%u, Rate-%s: %d\n", ++ __func__, gear, ufs_hs_rate_to_str(rate), ret); ++ } else { ++ /* PMC back to HS-G1. */ ++ ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (ret) ++ dev_err(hba->dev, "%s: Failed to PMC to HS-G1, Rate-%s: %d\n", ++ __func__, ufs_hs_rate_to_str(rate), ret); ++ } ++ ++ return ret; ++} ++ + /* + * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations + * +@@ -2412,6 +2452,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, + .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, ++ .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, + }; + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts-kmhv2/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch deleted file mode 100644 index 19a9ca6539..0000000000 --- a/SPECS/linux-lts-kmhv2/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 202c07f948325a5c584ae346de90b289bd86b125 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 24 Nov 2025 20:38:44 +0800 -Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support - -From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/Makefile | 1 + - .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ - 2 files changed, 19 insertions(+) - create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts - -diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile -index b55a17127c2b..281849e71ccb 100644 ---- a/arch/riscv/boot/dts/thead/Makefile -+++ b/arch/riscv/boot/dts/thead/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb -+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -new file mode 100644 -index 000000000000..a3a991baf716 ---- /dev/null -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 Han Gao -+ */ -+ -+/dts-v1/; -+ -+#include "th1520-lichee-pi-4a.dts" -+ -+/ { -+ model = "Sipeed Lichee Pi 4A 16G"; -+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x00000000 0x4 0x00000000>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts-kmhv2/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch deleted file mode 100644 index 1c294c8a28..0000000000 --- a/SPECS/linux-lts-kmhv2/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 7b0831ac6fa2e8db34c9c89d4e02bf2aa105fab3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:16:15 +0800 -Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie - -Signed-off-by: Han Gao -[Icenowy: preserve the original compatible to allow Linux to match] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index e44010810c07..f85d93227170 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { - }; - - aon: aon { -- compatible = "thead,th1520-aon"; -+ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; - mboxes = <&mbox_910t 1>; - mbox-names = "aon"; - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0439-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-get_rx_fom.patch b/SPECS/linux-lts-kmhv2/0439-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-get_rx_fom.patch new file mode 100644 index 0000000000..b786e7c773 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0439-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-get_rx_fom.patch @@ -0,0 +1,504 @@ +From 0ab479b135f8e3355ebce39e841852acda1edc62 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:52 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Implement vops + get_rx_fom() + +On some platforms, host's M-PHY RX_FOM Attribute always reads 0, meaning SW +cannot rely on Figure of Merit (FOM) to identify the optimal TX +Equalization settings for device's TX Lanes. Implement the vops +ufs_qcom_get_rx_fom() such that SW can utilize the UFS Eye Opening Monitor +(EOM) to evaluate the TX Equalization settings for device's TX Lanes. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-11-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 26605db7604deb18cf004cf3ad51e72e5d9b7add) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-txeq.c | 6 +- + drivers/ufs/host/ufs-qcom.c | 312 ++++++++++++++++++++++++++++++++++++ + drivers/ufs/host/ufs-qcom.h | 40 +++++ + include/ufs/ufshcd.h | 3 + + include/ufs/unipro.h | 25 +++ + 5 files changed, 383 insertions(+), 3 deletions(-) + +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +index 3a879c644faa..b2dc89124353 100644 +--- a/drivers/ufs/core/ufs-txeq.c ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -232,9 +232,8 @@ ufshcd_compose_tx_eq_setting(struct ufshcd_tx_eq_settings *settings, + * + * Returns 0 on success, negative error code otherwise + */ +-static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, +- struct ufshcd_tx_eq_params *params, +- u32 gear) ++int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, u32 gear) + { + struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; + u32 setting; +@@ -263,6 +262,7 @@ static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, + + return 0; + } ++EXPORT_SYMBOL_GPL(ufshcd_apply_tx_eq_settings); + + /** + * ufshcd_evaluate_tx_eqtr_fom - Evaluate TX EQTR FOM results +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index 57171f69b12a..b5e95c7385d1 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -2382,6 +2382,317 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) + return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); + } + ++static int ufs_qcom_host_eom_config(struct ufs_hba *hba, int lane, ++ const struct ufs_eom_coord *eom_coord, ++ u32 target_test_count) ++{ ++ enum ufs_eom_eye_mask eye_mask = eom_coord->eye_mask; ++ int v_step = eom_coord->v_step; ++ int t_step = eom_coord->t_step; ++ u32 volt_step, timing_step; ++ int ret; ++ ++ if (abs(v_step) > UFS_QCOM_EOM_VOLTAGE_STEPS_MAX) { ++ dev_err(hba->dev, "Invalid EOM Voltage Step: %d\n", v_step); ++ return -ERANGE; ++ } ++ ++ if (abs(t_step) > UFS_QCOM_EOM_TIMING_STEPS_MAX) { ++ dev_err(hba->dev, "Invalid EOM Timing Step: %d\n", t_step); ++ return -ERANGE; ++ } ++ ++ if (v_step < 0) ++ volt_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-v_step); ++ else ++ volt_step = (u32)v_step; ++ ++ if (t_step < 0) ++ timing_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-t_step); ++ else ++ timing_step = (u32)t_step; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ BIT(eye_mask) | RX_EYEMON_EXTENDED_VRANGE_BIT); ++ if (ret) { ++ dev_err(hba->dev, "Failed to enable Host EOM on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TIMING_STEPS, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ timing_step); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set Host EOM timing step on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_VOLTAGE_STEPS, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ volt_step); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set Host EOM voltage step on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TARGET_TEST_COUNT, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ target_test_count); ++ if (ret) ++ dev_err(hba->dev, "Failed to set Host EOM target test count on Lane %d: %d\n", ++ lane, ret); ++ ++ return ret; ++} ++ ++static int ufs_qcom_host_eom_may_stop(struct ufs_hba *hba, int lane, ++ u32 target_test_count, u32 *err_count) ++{ ++ u32 start, tested_count, error_count; ++ int ret; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_START, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &start); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get Host EOM start status on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ if (start & 0x1) ++ return -EAGAIN; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TESTED_COUNT, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &tested_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get Host EOM tested count on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ERROR_COUNT, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &error_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get Host EOM error count on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ /* EOM can stop */ ++ if ((tested_count >= target_test_count - 3) || error_count > 0) { ++ *err_count = error_count; ++ ++ /* Disable EOM */ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ 0x0); ++ if (ret) { ++ dev_err(hba->dev, "Failed to disable Host EOM on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ } else { ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++static int ufs_qcom_host_eom_scan(struct ufs_hba *hba, int num_lanes, ++ const struct ufs_eom_coord *eom_coord, ++ u32 target_test_count, u32 *err_count) ++{ ++ bool eom_stopped[PA_MAXDATALANES] = { 0 }; ++ int lane, ret; ++ u32 setting; ++ ++ if (!err_count || !eom_coord) ++ return -EINVAL; ++ ++ if (target_test_count < UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN) { ++ dev_err(hba->dev, "Target test count (%u) too small for Host EOM\n", ++ target_test_count); ++ return -ERANGE; ++ } ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ ret = ufs_qcom_host_eom_config(hba, lane, eom_coord, ++ target_test_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to config Host RX EOM: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ /* ++ * Trigger a PACP_PWR_req to kick start EOM, but not to really change ++ * the Power Mode. ++ */ ++ ret = ufshcd_uic_change_pwr_mode(hba, FAST_MODE << 4 | FAST_MODE); ++ if (ret) { ++ dev_err(hba->dev, "Failed to change power mode to kick start Host EOM: %d\n", ++ ret); ++ return ret; ++ } ++ ++more_burst: ++ /* Create burst on Host RX Lane. */ ++ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &setting); ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ if (eom_stopped[lane]) ++ continue; ++ ++ ret = ufs_qcom_host_eom_may_stop(hba, lane, target_test_count, ++ &err_count[lane]); ++ if (!ret) { ++ eom_stopped[lane] = true; ++ } else if (ret == -EAGAIN) { ++ /* Need more burst to excercise EOM */ ++ goto more_burst; ++ } else { ++ dev_err(hba->dev, "Failed to stop Host EOM: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hba->dev, "Host RX Lane %d EOM, v_step %d, t_step %d, error count %u\n", ++ lane, eom_coord->v_step, eom_coord->t_step, ++ err_count[lane]); ++ } ++ ++ return 0; ++} ++ ++static int ufs_qcom_host_sw_rx_fom(struct ufs_hba *hba, int num_lanes, u32 *fom) ++{ ++ const struct ufs_eom_coord *eom_coord = sw_rx_fom_eom_coords_g6; ++ u32 eom_err_count[PA_MAXDATALANES] = { 0 }; ++ u32 curr_ahit; ++ int lane, i, ret; ++ ++ if (!fom) ++ return -EINVAL; ++ ++ /* Stop the auto hibernate idle timer */ ++ curr_ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); ++ if (curr_ahit) ++ ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), PA_NO_ADAPT); ++ if (ret) { ++ dev_err(hba->dev, "Failed to select NO_ADAPT before starting Host EOM: %d\n", ret); ++ goto out; ++ } ++ ++ for (i = 0; i < SW_RX_FOM_EOM_COORDS; i++, eom_coord++) { ++ ret = ufs_qcom_host_eom_scan(hba, num_lanes, eom_coord, ++ UFS_QCOM_EOM_TARGET_TEST_COUNT_G6, ++ eom_err_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to run Host EOM scan: %d\n", ret); ++ break; ++ } ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ /* Bad coordinates have no weights */ ++ if (eom_err_count[lane]) ++ continue; ++ fom[lane] += SW_RX_FOM_EOM_COORDS_WEIGHT; ++ } ++ } ++ ++out: ++ /* Restore the auto hibernate idle timer */ ++ if (curr_ahit) ++ ufshcd_writel(hba, curr_ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); ++ ++ return ret; ++} ++ ++static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ struct ufshcd_tx_eq_params *params __free(kfree) = ++ kzalloc(sizeof(*params), GFP_KERNEL); ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr old_pwr_info; ++ u32 fom[PA_MAXDATALANES] = { 0 }; ++ u32 gear = pwr_mode->gear_tx; ++ u32 rate = pwr_mode->hs_rate; ++ int lane, ret; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 || ++ gear <= UFS_HS_G5 || !d_iter || !d_iter->is_updated) ++ return 0; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) ++ return -ERANGE; ++ ++ if (!params) ++ return -ENOMEM; ++ ++ memcpy(&old_pwr_info, &hba->pwr_info, sizeof(struct ufs_pa_layer_attr)); ++ ++ memcpy(params, &hba->tx_eq_params[gear - 1], sizeof(struct ufshcd_tx_eq_params)); ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) { ++ params->device[lane].preshoot = d_iter->preshoot; ++ params->device[lane].deemphasis = d_iter->deemphasis; ++ } ++ ++ /* Use TX EQTR settings as Device's TX Equalization settings. */ ++ ret = ufshcd_apply_tx_eq_settings(hba, params, gear); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n", ++ __func__, gear, ret); ++ return ret; ++ } ++ ++ /* Force PMC to target HS Gear to use new TX Equalization settings. */ ++ ret = ufshcd_change_power_mode(hba, pwr_mode, UFSHCD_PMC_POLICY_FORCE); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to change power mode to HS-G%u, Rate-%s: %d\n", ++ __func__, gear, ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ ret = ufs_qcom_host_sw_rx_fom(hba, pwr_mode->lane_rx, fom); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get SW FOM of TX (PreShoot: %u, DeEmphasis: %u): %d\n", ++ d_iter->preshoot, d_iter->deemphasis, ret); ++ return ret; ++ } ++ ++ /* Restore Device's TX Equalization settings. */ ++ ret = ufshcd_apply_tx_eq_settings(hba, &hba->tx_eq_params[gear - 1], gear); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n", ++ __func__, gear, ret); ++ return ret; ++ } ++ ++ /* Restore Power Mode. */ ++ ret = ufshcd_change_power_mode(hba, &old_pwr_info, UFSHCD_PMC_POLICY_FORCE); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to retore power mode to HS-G%u: %d\n", ++ __func__, old_pwr_info.gear_tx, ret); ++ return ret; ++ } ++ ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) ++ d_iter->fom[lane] = fom[lane]; ++ ++ return 0; ++} ++ + static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *pwr_mode) +@@ -2452,6 +2763,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, + .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, ++ .get_rx_fom = ufs_qcom_get_rx_fom, + .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, + }; + +diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h +index 380d02333d38..d38bc0c4fc58 100644 +--- a/drivers/ufs/host/ufs-qcom.h ++++ b/drivers/ufs/host/ufs-qcom.h +@@ -33,6 +33,46 @@ + #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) + #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) + ++#define UFS_QCOM_EOM_VOLTAGE_STEPS_MAX 127 ++#define UFS_QCOM_EOM_TIMING_STEPS_MAX 63 ++#define UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN 8 ++#define UFS_QCOM_EOM_TARGET_TEST_COUNT_G6 0x3F ++ ++#define SW_RX_FOM_EOM_COORDS 23 ++#define SW_RX_FOM_EOM_COORDS_WEIGHT (127 / SW_RX_FOM_EOM_COORDS) ++ ++struct ufs_eom_coord { ++ int t_step; ++ int v_step; ++ u8 eye_mask; ++}; ++ ++static const struct ufs_eom_coord sw_rx_fom_eom_coords_g6[SW_RX_FOM_EOM_COORDS] = { ++ [0] = { -2, -15, UFS_EOM_EYE_MASK_M }, ++ [1] = { 0, -15, UFS_EOM_EYE_MASK_M }, ++ [2] = { 2, -15, UFS_EOM_EYE_MASK_M }, ++ [3] = { -4, -10, UFS_EOM_EYE_MASK_M }, ++ [4] = { -2, -10, UFS_EOM_EYE_MASK_M }, ++ [5] = { 0, -10, UFS_EOM_EYE_MASK_M }, ++ [6] = { 2, -10, UFS_EOM_EYE_MASK_M }, ++ [7] = { 4, -10, UFS_EOM_EYE_MASK_M }, ++ [8] = { -6, 0, UFS_EOM_EYE_MASK_M }, ++ [9] = { -4, 0, UFS_EOM_EYE_MASK_M }, ++ [10] = { -2, 0, UFS_EOM_EYE_MASK_M }, ++ [11] = { 0, 0, UFS_EOM_EYE_MASK_M }, ++ [12] = { 2, 0, UFS_EOM_EYE_MASK_M }, ++ [13] = { 4, 0, UFS_EOM_EYE_MASK_M }, ++ [14] = { 6, 0, UFS_EOM_EYE_MASK_M }, ++ [15] = { -4, 10, UFS_EOM_EYE_MASK_M }, ++ [16] = { -2, 10, UFS_EOM_EYE_MASK_M }, ++ [17] = { 0, 10, UFS_EOM_EYE_MASK_M }, ++ [18] = { 2, 10, UFS_EOM_EYE_MASK_M }, ++ [19] = { 4, 10, UFS_EOM_EYE_MASK_M }, ++ [20] = { -2, 15, UFS_EOM_EYE_MASK_M }, ++ [21] = { 0, 15, UFS_EOM_EYE_MASK_M }, ++ [22] = { 2, 15, UFS_EOM_EYE_MASK_M }, ++}; ++ + /* Qualcomm MCQ Configuration */ + #define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */ + #define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* 0x1C000 */ +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 8bb279c0e992..8ce8208445e7 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1524,6 +1524,9 @@ extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *desired_pwr_mode, + enum ufshcd_pmc_policy pmc_policy); + extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); ++extern int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ u32 gear); + + /* UIC command interfaces for DME primitives */ + #define DME_LOCAL 0 +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 4aa592130b4e..f849a2a101ae 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -32,6 +32,8 @@ + #define TX_LCC_SEQUENCER 0x0032 + #define TX_MIN_ACTIVATETIME 0x0033 + #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 ++#define TX_HS_DEEMPHASIS_SETTING 0x0037 ++#define TX_HS_PRESHOOT_SETTING 0x003B + #define TX_REFCLKFREQ 0x00EB + #define TX_CFGCLKFREQVAL 0x00EC + #define CFGEXTRATTR 0x00F0 +@@ -76,10 +78,27 @@ + #define RX_REFCLKFREQ 0x00EB + #define RX_CFGCLKFREQVAL 0x00EC + #define CFGWIDEINLN 0x00F0 ++#define RX_EYEMON_CAP 0x00F1 ++#define RX_EYEMON_TIMING_MAX_STEPS_CAP 0x00F2 ++#define RX_EYEMON_TIMING_MAX_OFFSET_CAP 0x00F3 ++#define RX_EYEMON_VOLTAGE_MAX_STEPS_CAP 0x00F4 ++#define RX_EYEMON_VOLTAGE_MAX_OFFSET_CAP 0x00F5 ++#define RX_EYEMON_ENABLE 0x00F6 ++#define RX_EYEMON_TIMING_STEPS 0x00F7 ++#define RX_EYEMON_VOLTAGE_STEPS 0x00F8 ++#define RX_EYEMON_TARGET_TEST_COUNT 0x00F9 ++#define RX_EYEMON_TESTED_COUNT 0x00FA ++#define RX_EYEMON_ERROR_COUNT 0x00FB ++#define RX_EYEMON_START 0x00FC ++#define RX_EYEMON_EXTENDED_ERROR_COUNT 0x00FD ++ + #define ENARXDIRECTCFG4 0x00F2 + #define ENARXDIRECTCFG3 0x00F3 + #define ENARXDIRECTCFG2 0x00F4 + ++#define RX_EYEMON_NEGATIVE_STEP_BIT BIT(6) ++#define RX_EYEMON_EXTENDED_VRANGE_BIT BIT(6) ++ + #define is_mphy_tx_attr(attr) (attr < RX_MODE) + #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) + #define SYNC_LEN_FINE(x) ((x) & 0x3F) +@@ -297,6 +316,12 @@ enum ufs_tx_hs_deemphasis { + UFS_TX_HS_DEEMPHASIS_DB_7P6, + }; + ++enum ufs_eom_eye_mask { ++ UFS_EOM_EYE_MASK_M, ++ UFS_EOM_EYE_MASK_L, ++ UFS_EOM_EYE_MASK_U, ++}; ++ + #define DL_FC0ProtectionTimeOutVal_Default 8191 + #define DL_TC0ReplayTimeOutVal_Default 65535 + #define DL_AFC0ReqTimeOutVal_Default 32767 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts-kmhv2/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch deleted file mode 100644 index 757ee92472..0000000000 --- a/SPECS/linux-lts-kmhv2/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1fa033781168266e279c276df269822336f8d946 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:27:18 +0800 -Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r - -Signed-off-by: Han Gao -[Icenowy: remove the interrupt-controller property] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f85d93227170..ab681cf850d1 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -292,6 +292,24 @@ aon: aon { - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; - reset-names = "gpu-clkgen"; - #power-domain-cells = <1>; -+ opensbi-mboxes = <&mbox_910r>; -+ status = "okay"; -+ }; -+ -+ mbox_910r: mbox@ffefc53000 { -+ compatible = "xuantie,th1520-mbox-r"; -+ reg = <0xff 0xefc53000 0x0 0x4000>, -+ <0xff 0xefc3f000 0x0 0x1000>, -+ <0xff 0xefc47000 0x0 0x1000>, -+ <0xff 0xefc4f000 0x0 0x1000>; -+ reg-names = "local_base", -+ "remote_icu0", -+ "remote_icu1", -+ "remote_icu2"; -+ clocks = <&clk CLK_PERI_APB_PCLK>; -+ clock-names = "ipg"; -+ icu_cpu_id = <3>; -+ #mbox-cells = <2>; - }; - - soc { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0440-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-apply_tx_e.patch b/SPECS/linux-lts-kmhv2/0440-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-apply_tx_e.patch new file mode 100644 index 0000000000..42a1c7874b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0440-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-apply_tx_e.patch @@ -0,0 +1,104 @@ +From 0623b509b86e77bdd30f561590bf76fcd9a798e2 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:53 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Implement vops + apply_tx_eqtr_settings() + +On some platforms, when Host Software triggers TX Equalization Training, HW +does not take TX EQTR settings programmed in PA_TxEQTRSetting, instead HW +takes TX EQTR settings from PA_TxEQG1Setting. Implement vops +apply_tx_eqtr_setting() to work around it by programming TX EQTR settings +to PA_TxEQG1Setting during TX EQTR procedure. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-12-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 16cbdc8308776270d76340cd52ac63ac4fbf9968) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 31 +++++++++++++++++++++++++++++++ + drivers/ufs/host/ufs-qcom.h | 2 ++ + 2 files changed, 33 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index b5e95c7385d1..c0112ad1db53 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -2693,6 +2693,26 @@ static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, + return 0; + } + ++static int ufs_qcom_apply_tx_eqtr_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ u32 setting = 0; ++ int lane; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) ++ return 0; ++ ++ for (lane = 0; lane < pwr_mode->lane_tx; lane++) { ++ setting |= TX_HS_PRESHOOT_BITS(lane, h_iter->preshoot); ++ setting |= TX_HS_DEEMPHASIS_BITS(lane, h_iter->deemphasis); ++ } ++ ++ return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), setting); ++} ++ + static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *pwr_mode) +@@ -2715,6 +2735,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + return 0; + + if (status == PRE_CHANGE) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), ++ &host->saved_tx_eq_g1_setting); ++ if (ret) ++ return ret; ++ + /* PMC to target HS Gear. */ + ret = ufshcd_change_power_mode(hba, pwr_mode, + UFSHCD_PMC_POLICY_DONT_FORCE); +@@ -2722,6 +2747,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + dev_err(hba->dev, "%s: Failed to PMC to target HS-G%u, Rate-%s: %d\n", + __func__, gear, ufs_hs_rate_to_str(rate), ret); + } else { ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), ++ host->saved_tx_eq_g1_setting); ++ if (ret) ++ return ret; ++ + /* PMC back to HS-G1. */ + ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, + UFSHCD_PMC_POLICY_DONT_FORCE); +@@ -2764,6 +2794,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, + .get_rx_fom = ufs_qcom_get_rx_fom, ++ .apply_tx_eqtr_settings = ufs_qcom_apply_tx_eqtr_settings, + .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, + }; + +diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h +index d38bc0c4fc58..5f979daabd53 100644 +--- a/drivers/ufs/host/ufs-qcom.h ++++ b/drivers/ufs/host/ufs-qcom.h +@@ -348,6 +348,8 @@ struct ufs_qcom_host { + u32 phy_gear; + + bool esi_enabled; ++ ++ u32 saved_tx_eq_g1_setting; + }; + + struct ufs_qcom_drvdata { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts-kmhv2/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch deleted file mode 100644 index 79f21e68df..0000000000 --- a/SPECS/linux-lts-kmhv2/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 40d9d7d4261e84ef42987558481248dd8a8a89b0 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:31 +0800 -Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller - -Sophgo SG2044 uses eFuses used to store factory-programmed data -such as ROM patch, public keys and other factory information. - -Signed-off-by: Inochi Amaoto ---- - .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml - -diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -new file mode 100644 -index 000000000000..d4bffe2724ac ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -@@ -0,0 +1,61 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo SoC eFuse-based NVMEM -+ -+description: -+ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, -+ public key and other factory information. -+ -+maintainers: -+ - Inochi Amaoto -+ -+allOf: -+ - $ref: nvmem.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - sophgo,sg2044-efuse -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ items: -+ - description: Core clock -+ - description: APB clock -+ -+ clock-names: -+ minItems: 1 -+ items: -+ - const: core -+ - const: apb -+ -+ resets: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ efuse@40000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x40000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk 0>, -+ <&clk 1>; -+ clock-names = "core", "apb"; -+ }; -+ -+... --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0441-UPSTREAM-scsi-ufs-ufs-qcom-Enable-TX-Equalization.patch b/SPECS/linux-lts-kmhv2/0441-UPSTREAM-scsi-ufs-ufs-qcom-Enable-TX-Equalization.patch new file mode 100644 index 0000000000..bf5e5b2a6d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0441-UPSTREAM-scsi-ufs-ufs-qcom-Enable-TX-Equalization.patch @@ -0,0 +1,45 @@ +From 7d50836efe2ea050d9fc54df1cd274bdb7883a2b Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:54 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Enable TX Equalization + +Enable TX Equalization for hosts with HW version 0x7 and onwards. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-13-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 57b7943fd87f086a3497ecbecc502b7418ed4ab8) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index c0112ad1db53..9f9c0e5adc2a 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -1338,6 +1338,8 @@ static void ufs_qcom_set_host_caps(struct ufs_hba *hba) + + static void ufs_qcom_set_caps(struct ufs_hba *hba) + { ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ + hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; + hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; +@@ -1345,6 +1347,9 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) + hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; + hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; + ++ if (host->hw_ver.major >= 0x7) ++ hba->caps |= UFSHCD_CAP_TX_EQUALIZATION; ++ + ufs_qcom_set_host_caps(hba); + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts-kmhv2/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch deleted file mode 100644 index 2ebd4453f3..0000000000 --- a/SPECS/linux-lts-kmhv2/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch +++ /dev/null @@ -1,241 +0,0 @@ -From e96eabf82535fd6f2fc338f3f5af2fb50721a459 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:32 +0800 -Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver - -Sophgo SoCs such as SG2044 contain eFuses used to store -factory-programmed data. - -As for SG2044, HW automatically loads the eFuse content -into shadow registers which are organized as 32bit values -exposed as MMIO. - -Signed-off-by: Inochi Amaoto ---- - drivers/nvmem/Kconfig | 12 +++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ - 3 files changed, 190 insertions(+) - create mode 100644 drivers/nvmem/sophgo-efuse.c - -diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig -index 11b098705ec6..42f46eb0462a 100644 ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - -+config NVMEM_SOPHGO_EFUSE -+ tristate "Sophgo eFuse support" -+ depends on ARCH_SOPHGO || COMPILE_TEST -+ default ARCH_SOPHGO -+ help -+ Say y here to enable support for reading eFuses on Sophgo SoCs -+ such as the CV1800B. These are e.g. used to store factory programmed -+ calibration data required for the builtin ethernet PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-sophgo-efuse. -+ - config NVMEM_SPMI_SDAM - tristate "SPMI SDAM Support" - depends on SPMI -diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile -index 70a4464dcb1e..6cc324aaa757 100644 ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o - nvmem-sc27xx-efuse-y := sc27xx-efuse.o - obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o - nvmem_snvs_lpgpr-y := snvs_lpgpr.o -+obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o -+nvmem-sophgo-efuse-y := sophgo-efuse.o - obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o - nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o - obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o -diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c -new file mode 100644 -index 000000000000..5f90adaf8e4f ---- /dev/null -+++ b/drivers/nvmem/sophgo-efuse.c -@@ -0,0 +1,176 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Sophgo SoC eFuse driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SG2044_EFUSE_CONTENT_SIZE 0x400 -+ -+#define SG2044_EFUSE_MD 0x000 -+#define SG2044_EFUSE_ADR 0x004 -+#define SG2044_EFUSE_RD_DATA 0x00c -+ -+#define SG2044_EFUSE_MODE GENMASK(1, 0) -+#define SG2044_EFUSE_MODE_READ 2 -+ -+#define SG2044_EFUSE_BOOT_DONE BIT(7) -+#define SG2044_BOOT_TIMEOUT 10000 -+ -+#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) -+ -+#define SG2044_EFUSE_ALIGN 4 -+ -+struct sophgo_efuses { -+ void __iomem *base; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct mutex mutex; -+}; -+ -+static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) -+{ -+ u32 value; -+ -+ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, -+ 1, SG2044_BOOT_TIMEOUT); -+} -+ -+static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) -+{ -+ u32 val = readl(efuse->base + SG2044_EFUSE_MD); -+ -+ val &= ~SG2044_EFUSE_MODE; -+ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); -+ -+ writel(val, efuse->base + SG2044_EFUSE_MD); -+ -+ return sg2044_efuse_wait_mode(efuse); -+} -+ -+static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, -+ unsigned int offset, u32 *strip) -+{ -+ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); -+ int ret; -+ -+ guard(mutex)(&efuse->mutex); -+ -+ writel(val, efuse->base + SG2044_EFUSE_ADR); -+ -+ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); -+ if (ret < 0) -+ return ret; -+ -+ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); -+ -+ return 0; -+} -+ -+static int sg2044_efuses_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct sophgo_efuses *efuse = context; -+ unsigned int start, start_offset, end, i; -+ u32 value; -+ u8 *buf; -+ int ret; -+ -+ start = rounddown(offset, SG2044_EFUSE_ALIGN); -+ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); -+ start_offset = offset - start; -+ -+ start /= SG2044_EFUSE_ALIGN; -+ end /= SG2044_EFUSE_ALIGN; -+ -+ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ (value & SG2044_EFUSE_BOOT_DONE), -+ 1, SG2044_BOOT_TIMEOUT); -+ if (ret < 0) -+ return ret; -+ -+ buf = kzalloc(end - start, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ for (i = start; i < end; i++) { -+ ret = sg2044_efuses_read_strip(efuse, i, &value); -+ if (ret) -+ goto failed; -+ -+ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); -+ } -+ -+ memcpy(val, buf + start_offset, bytes); -+ -+failed: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int sophgo_efuses_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct sophgo_efuses *efuse; -+ struct nvmem_config config = { -+ .dev = &pdev->dev, -+ .add_legacy_fixed_of_cells = true, -+ .read_only = true, -+ .reg_read = sg2044_efuses_read, -+ .stride = 1, -+ .word_size = 1, -+ .name = "sophgo-efuse", -+ .id = NVMEM_DEVID_AUTO, -+ .root_only = true, -+ }; -+ -+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); -+ if (!efuse) -+ return -ENOMEM; -+ -+ efuse->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(efuse->base)) -+ return PTR_ERR(efuse->base); -+ -+ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); -+ if (efuse->num_clks < 0) -+ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); -+ -+ config.priv = efuse; -+ config.size = SG2044_EFUSE_CONTENT_SIZE; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); -+} -+ -+static const struct of_device_id sophgo_efuses_of_match[] = { -+ { .compatible = "sophgo,sg2044-efuse", }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); -+ -+static struct platform_driver sophgo_efuses_driver = { -+ .driver = { -+ .name = "sophgo_efuse", -+ .of_match_table = sophgo_efuses_of_match, -+ }, -+ .probe = sophgo_efuses_probe, -+}; -+ -+module_platform_driver(sophgo_efuses_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Sophgo efuse driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0442-UPSTREAM-riscv-Prevent-NULL-pointer-dereference-in-m.patch b/SPECS/linux-lts-kmhv2/0442-UPSTREAM-riscv-Prevent-NULL-pointer-dereference-in-m.patch new file mode 100644 index 0000000000..59961d2bb0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0442-UPSTREAM-riscv-Prevent-NULL-pointer-dereference-in-m.patch @@ -0,0 +1,56 @@ +From 96011511aea891b691cd12a4580f687531e8c92c Mon Sep 17 00:00:00 2001 +From: Tao Liu +Date: Mon, 6 Jul 2026 11:27:07 +1200 +Subject: [RUYI PATCH] UPSTREAM: riscv: Prevent NULL pointer dereference in + machine_kexec_prepare() + +A NULL pointer dereference issue is noticed in riscv's +machine_kexec_prepare(), where image->segment[i].buf might be NULL and +copied unchecked. + +The NULL buf comes from ima_add_kexec_buffer(), where kbuf is added by +kexec_add_buffer(), but kbuf.buffer is NULL, then it is copied without +a check in machine_kexec_prepare(): + + kexec_file_load + -> kimage_file_alloc_init() + -> kimage_file_prepare_segments() + -> ima_add_kexec_buffer() + -> kexec_add_buffer() + -> machine_kexec_prepare() + -> memcpy() + +Address this by adding a check before the data copy attempt. + +Fixes: b7fb4d78a6ad ("RISC-V: use memcpy for kexec_file mode") +Cc: stable@vger.kernel.org +Closes: https://lore.kernel.org/kexec/CAO7dBbVftLUhd2qrh7hmijTB3PEPfZAhykCGqEfrPoOcSrrj-w@mail.gmail.com/ +Acked-by: Baoquan He +Acked-by: Pratyush Yadav +Reviewed-by: Nutty Liu +Signed-off-by: Tao Liu +Link: https://patch.msgid.link/20260705232706.30265-2-ltao@redhat.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 81bbcff0c053c4f5c711c31a9b72fc492bd96c3f) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/machine_kexec.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c +index 2306ce3e5f22..738df176ff6f 100644 +--- a/arch/riscv/kernel/machine_kexec.c ++++ b/arch/riscv/kernel/machine_kexec.c +@@ -41,6 +41,9 @@ machine_kexec_prepare(struct kimage *image) + if (image->segment[i].memsz <= sizeof(fdt)) + continue; + ++ if (!image->segment[i].buf) ++ continue; ++ + if (image->file_mode) + memcpy(&fdt, image->segment[i].buf, sizeof(fdt)); + else if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt))) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts-kmhv2/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch deleted file mode 100644 index ca1a921e5d..0000000000 --- a/SPECS/linux-lts-kmhv2/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 973bb367e07f78196b1e441326cbdef6c366955f Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 5 Dec 2024 13:24:13 +0800 -Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device - -Add eFUSE controller node for SG2044. - -Signed-off-by: Inochi Amaoto ---- - arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -index fed3d9a384a0..1b506972d465 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -@@ -36,6 +36,10 @@ &emmc { - status = "okay"; - }; - -+&efuse0 { -+ status = "okay"; -+}; -+ - &gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 320c4d1d08e6..9577aae08f7f 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -408,6 +408,18 @@ sd: mmc@703000b000 { - status = "disabled"; - }; - -+ efuse0: efuse@7040000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x70 0x40000000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk CLK_GATE_EFUSE>, -+ <&clk CLK_GATE_APB_EFUSE>; -+ clock-names = "core", "apb"; -+ resets = <&rst RST_EFUSE0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@7040005000 { - compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; - reg = <0x70 0x40005000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0443-UPSTREAM-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux-lts-kmhv2/0443-UPSTREAM-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch new file mode 100644 index 0000000000..1a102f5c13 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0443-UPSTREAM-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch @@ -0,0 +1,39 @@ +From 1a061ac4b941f7d99ba753e6f208194662f45fd3 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 27 Apr 2026 09:32:10 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: add UltraRISC SoC family Kconfig + support + +The first SoC in the UltraRISC series is UR-DP1000, containing octa +UltraRISC CP100 cores. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com +Signed-off-by: Paul Walmsley +(cherry picked from commit a3320469e3c8a58c808a090f3e1b5bfccb4c59c6) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig.socs | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs +index 848e7149e443..98c70e2ae958 100644 +--- a/arch/riscv/Kconfig.socs ++++ b/arch/riscv/Kconfig.socs +@@ -71,6 +71,12 @@ config ARCH_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + ++config ARCH_ULTRARISC ++ bool "UltraRISC RISC-V SoCs" ++ help ++ This enables support for UltraRISC SoC platform hardware, ++ including boards based on the UR-DP1000. ++ + config ARCH_VIRT + bool "QEMU Virt Machine" + select POWER_RESET +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts-kmhv2/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch deleted file mode 100644 index 7551151403..0000000000 --- a/SPECS/linux-lts-kmhv2/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch +++ /dev/null @@ -1,102 +0,0 @@ -From e2ed9e487c648247b91a25cef6515dc2a54aba85 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 28 Dec 2025 23:02:15 +0800 -Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address - -FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 9577aae08f7f..f1377ee8e149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x00000000 0x0 0x00001000>, - <0x6c 0x00300000 0x0 0x00004000>, -- <0x48 0x00000000 0x0 0x00001000>, -+ <0x50 0x00000000 0x0 0x00001000>, - <0x6c 0x000c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, - <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc0: interrupt-controller { -@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { - ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, - <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc1: interrupt-controller { -@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04000000 0x0 0x00001000>, - <0x6c 0x04300000 0x0 0x00004000>, -- <0x58 0x00000000 0x0 0x00001000>, -+ <0x7c 0x00000000 0x0 0x00001000>, - <0x6c 0x040c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, - <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, -- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc2: interrupt-controller { -@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04400000 0x0 0x00001000>, - <0x6c 0x04700000 0x0 0x00004000>, -- <0x50 0x00000000 0x0 0x00001000>, -+ <0x78 0x00000000 0x0 0x00001000>, - <0x6c 0x04780000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, - <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, -- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, -- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc3: interrupt-controller { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0444-UPSTREAM-riscv-defconfig-enable-ARCH_ULTRARISC.patch b/SPECS/linux-lts-kmhv2/0444-UPSTREAM-riscv-defconfig-enable-ARCH_ULTRARISC.patch new file mode 100644 index 0000000000..35e652c411 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0444-UPSTREAM-riscv-defconfig-enable-ARCH_ULTRARISC.patch @@ -0,0 +1,31 @@ +From e28418b1445fd81ea0360d13cd0c8a2a794cd7f6 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:05 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: defconfig: enable ARCH_ULTRARISC + +Enable `ARCH_ULTRARISC` in the default RISC-V defconfig. + +Signed-off-by: Jia Wang +Link: https://patch.msgid.link/20260515-ultrarisc-pinctrl-v1-9-bf559589ea8a@ultrarisc.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 3fb29495b486b1ec61708248cb388745fc607278) +Signed-off-by: Han Gao +--- + arch/riscv/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig +index fc2725cbca18..140c12d4ab15 100644 +--- a/arch/riscv/configs/defconfig ++++ b/arch/riscv/configs/defconfig +@@ -30,6 +30,7 @@ CONFIG_ARCH_SPACEMIT=y + CONFIG_SOC_STARFIVE=y + CONFIG_ARCH_SUNXI=y + CONFIG_ARCH_THEAD=y ++CONFIG_ARCH_ULTRARISC=y + CONFIG_ARCH_VIRT=y + CONFIG_ARCH_CANAAN=y + CONFIG_SMP=y +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts-kmhv2/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch deleted file mode 100644 index 8f80489e78..0000000000 --- a/SPECS/linux-lts-kmhv2/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 90bc96384294bf251a26f5f518765309821b8cd2 Mon Sep 17 00:00:00 2001 -From: Xiaoguang Xing -Date: Mon, 22 Jan 2024 10:31:30 +0800 -Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean - with flush - -FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 - -Signed-off-by: Xiaoguang Xing -Signed-off-by: Han Gao ---- - arch/riscv/errata/thead/errata.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index fbe46f2fa8fb..9be8c45f4531 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, - * 0000000 11001 00000 000 00000 0001011 - */ - #define THEAD_INVAL_A0 ".long 0x02a5000b" --#define THEAD_CLEAN_A0 ".long 0x0295000b" -+#define THEAD_CLEAN_A0 ".long 0x02b5000b" - #define THEAD_FLUSH_A0 ".long 0x02b5000b" - #define THEAD_SYNC_S ".long 0x0190000b" - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0445-UPSTREAM-selftests-rseq-Fix-a-building-error-for-ris.patch b/SPECS/linux-lts-kmhv2/0445-UPSTREAM-selftests-rseq-Fix-a-building-error-for-ris.patch new file mode 100644 index 0000000000..49f1f4693c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0445-UPSTREAM-selftests-rseq-Fix-a-building-error-for-ris.patch @@ -0,0 +1,51 @@ +From 2a5a5569ecca5b121c27b2e52e2167399ac07557 Mon Sep 17 00:00:00 2001 +From: Hui Wang +Date: Tue, 7 Jul 2026 16:23:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: selftests/rseq: Fix a building error for riscv + arch + +RISC-V rseq selftests include asm/fence.h from tools/arch/riscv, +but the rseq Makefile only adds tools/include in the CFLAGS, this +results in the building failure both for native and cross build: + + In file included from rseq.h:131, + from rseq.c:37: + rseq-riscv.h:11:10: fatal error: asm/fence.h: No such file or directory + +To fix it, add the matching tools/arch/$(ARCH)/include path in the +CFLAGS and derive ARCH from SUBARCH for standalone native builds where +ARCH is not set. + +Fixes: c92786e179e0 ("KVM: riscv: selftests: Use the existing RISCV_FENCE macro in `rseq-riscv.h`") +Cc: stable@vger.kernel.org +Signed-off-by: Hui Wang +Link: https://patch.msgid.link/20260707082348.36896-1-hui.wang@canonical.com +Signed-off-by: Paul Walmsley +(cherry picked from commit a2ac823d8a228e392bc6a79ea63b550ab84a55b2) +Signed-off-by: Han Gao +--- + tools/testing/selftests/rseq/Makefile | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/tools/testing/selftests/rseq/Makefile b/tools/testing/selftests/rseq/Makefile +index 0d0a5fae5954..ee4325874bae 100644 +--- a/tools/testing/selftests/rseq/Makefile ++++ b/tools/testing/selftests/rseq/Makefile +@@ -5,9 +5,13 @@ CLANG_FLAGS += -no-integrated-as + endif + + top_srcdir = ../../../.. ++include $(top_srcdir)/scripts/subarch.include ++ARCH ?= $(SUBARCH) ++LINUX_TOOL_ARCH_INCLUDE = $(top_srcdir)/tools/arch/$(ARCH)/include + + CFLAGS += -O2 -Wall -g -I./ $(KHDR_INCLUDES) -L$(OUTPUT) -Wl,-rpath=./ \ +- $(CLANG_FLAGS) -I$(top_srcdir)/tools/include ++ $(CLANG_FLAGS) -I$(top_srcdir)/tools/include \ ++ -I$(LINUX_TOOL_ARCH_INCLUDE) + LDLIBS += -lpthread -ldl + + # Own dependencies because we only want to build against 1st prerequisite, but +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0446-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux-lts-kmhv2/0446-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch new file mode 100644 index 0000000000..c168ebac21 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0446-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch @@ -0,0 +1,185 @@ +From dacfb03effe0f9ff79f2e310a9529323830e037e Mon Sep 17 00:00:00 2001 +From: "Guo Ren (Alibaba DAMO Academy)" +Date: Tue, 21 Apr 2026 10:31:40 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE + fixup + +The early version of XuanTie C910 core has a store merge buffer +delay problem. The store merge buffer could improve the store queue +performance by merging multi-store requests, but when there are not +continued store requests, the prior single store request would be +waiting in the store queue for a long time. That would cause +significant problems for communication between multi-cores. This +problem was found on sg2042 & th1520 platforms with the qspinlock +lock torture test. + +So appending a fence w.o could immediately flush the store merge +buffer and let other cores see the write result. + +This will apply the WRITE_ONCE errata to handle the non-standard +behavior via appending a fence w.o instruction for WRITE_ONCE(). + +This problem is only observed on the sg2042 hardware platform by +running the lock_torture test program for half an hour. The problem +was not found in the user space application, because interrupt can +break the livelock. + +Acked-by: Arnd Bergmann +Reviewed-by: Alexandre Ghiti +Reviewed-by: Leonardo Bras +Reviewed-by: Inochi Amaoto +Tested-by: Han Gao +Tested-by: Yao Zi +Cc: Chen Wang +Cc: Xiaoguang Xing +Cc: Paul Walmsley +Signed-off-by: Guo Ren (Alibaba DAMO Academy) +Link: https://lore.kernel.org/r/20260421143154.1590156-1-guoren@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig.errata | 17 ++++++++++ + arch/riscv/errata/thead/errata.c | 20 ++++++++++++ + arch/riscv/include/asm/errata_list_vendors.h | 3 +- + arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ + include/asm-generic/rwonce.h | 2 ++ + 5 files changed, 75 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/include/asm/rwonce.h + +diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata +index aca9b0cfcfec..ac64123433e7 100644 +--- a/arch/riscv/Kconfig.errata ++++ b/arch/riscv/Kconfig.errata +@@ -153,4 +153,21 @@ config ERRATA_THEAD_GHOSTWRITE + + If you don't know what to do here, say "Y". + ++config ERRATA_THEAD_WRITE_ONCE ++ bool "Apply T-Head WRITE_ONCE errata" ++ depends on ERRATA_THEAD ++ default y ++ help ++ The early version of T-Head C9xx cores of sg2042 & th1520 have a store ++ merge buffer delay problem. The store merge buffer could improve the ++ store queue performance by merging multi-store requests, but when there ++ are no continued store requests, the prior single store request would be ++ waiting in the store queue for a long time. That would cause signifi- ++ cant problems for communication between multi-cores. Appending a ++ fence w.o could immediately flush the store merge buffer and let other ++ cores see the write result. ++ ++ This will apply the WRITE_ONCE errata to handle the non-standard beh- ++ avior via appending a fence w.o instruction for WRITE_ONCE(). ++ + endmenu # "CPU errata selection" +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index 0b942183f708..fbe46f2fa8fb 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, + return true; + } + ++static bool errata_probe_write_once(unsigned int stage, ++ unsigned long arch_id, unsigned long impid) ++{ ++ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) ++ return false; ++ ++ /* target-c9xx cores report arch_id and impid as 0 */ ++ if (arch_id != 0 || impid != 0) ++ return false; ++ ++ if (stage == RISCV_ALTERNATIVES_BOOT || ++ stage == RISCV_ALTERNATIVES_MODULE) ++ return true; ++ ++ return false; ++} ++ + static u32 thead_errata_probe(unsigned int stage, + unsigned long archid, unsigned long impid) + { +@@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, + + errata_probe_ghostwrite(stage, archid, impid); + ++ if (errata_probe_write_once(stage, archid, impid)) ++ cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); ++ + return cpu_req_errata; + } + +diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h +index ec7eba373437..8fd7c36307e2 100644 +--- a/arch/riscv/include/asm/errata_list_vendors.h ++++ b/arch/riscv/include/asm/errata_list_vendors.h +@@ -18,7 +18,8 @@ + #define ERRATA_THEAD_MAE 0 + #define ERRATA_THEAD_PMU 1 + #define ERRATA_THEAD_GHOSTWRITE 2 +-#define ERRATA_THEAD_NUMBER 3 ++#define ERRATA_THEAD_WRITE_ONCE 3 ++#define ERRATA_THEAD_NUMBER 4 + #endif + + #ifdef CONFIG_ERRATA_MIPS +diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h +new file mode 100644 +index 000000000000..081793d4d772 +--- /dev/null ++++ b/arch/riscv/include/asm/rwonce.h +@@ -0,0 +1,34 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef __ASM_RWONCE_H ++#define __ASM_RWONCE_H ++ ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) ++ ++#define write_once_fence() \ ++do { \ ++ asm volatile(ALTERNATIVE( \ ++ "nop", \ ++ "fence w, o", \ ++ THEAD_VENDOR_ID, \ ++ ERRATA_THEAD_WRITE_ONCE, \ ++ CONFIG_ERRATA_THEAD_WRITE_ONCE) \ ++ : : : "memory"); \ ++} while (0) ++ ++#define __WRITE_ONCE(x, val) \ ++do { \ ++ *(volatile typeof(x) *)&(x) = (val); \ ++ write_once_fence(); \ ++} while (0) ++ ++#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ ++ ++#include ++ ++#endif /* __ASM_RWONCE_H */ +diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h +index 52b969c7cef9..4e2d941f15a1 100644 +--- a/include/asm-generic/rwonce.h ++++ b/include/asm-generic/rwonce.h +@@ -50,10 +50,12 @@ + __READ_ONCE(x); \ + }) + ++#ifndef __WRITE_ONCE + #define __WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) = (val); \ + } while (0) ++#endif + + #define WRITE_ONCE(x, val) \ + do { \ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux-lts-kmhv2/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch deleted file mode 100644 index 5ca806b352..0000000000 --- a/SPECS/linux-lts-kmhv2/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 283120c06a7de7f2b98715726a766cbef2459707 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 15:59:17 +0800 -Subject: [RUYI PATCH] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add - support for Ultrarisc DP1000 GMAC - -The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC -(version 5.10a). - -Add necessary compatible string for this device. - -Signed-off-by: Han Gao -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 1 + - .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ - 2 files changed, 90 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index eb36cb36a57a..a8a45b844335 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -113,6 +113,7 @@ properties: - - starfive,jh7110-dwmac - - tesla,fsd-ethqos - - thead,th1520-gmac -+ - ultrarisc,dp1000-gmac - - reg: - minItems: 1 -diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -new file mode 100644 -index 000000000000..ace5c4058cc9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Ultrarisc dp1000 glue layer -+ -+maintainers: -+ - Han Gao -+ -+select: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - ultrarisc,dp1000-gmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - const: ultrarisc,dp1000-gmac -+ - const: snps,dwmac-5.10a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC main clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ -+ dma-noncoherent: true -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0447-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux-lts-kmhv2/0447-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch new file mode 100644 index 0000000000..e00c8ebfe4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0447-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch @@ -0,0 +1,54 @@ +From 20b11bd8885b81bc6e9498cecffb7048b7ecca08 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:56:57 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native + PCIe port services + +Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe +port service driver from probing specific devices. This provides a +per-device equivalent of the global pcie_ports=compat kernel parameter. + +Some platforms have PCIe root ports that break MSI delivery to downstream +devices when native port services (AER, PME, bwctrl, etc.) are active. +The existing pci_host_bridge native_* flags do not cover all services +(notably bwctrl), so a mechanism to skip port driver probing entirely +on a per-device basis is needed. + +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331175658.1015829-2-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/pcie/portdrv.c | 3 +++ + include/linux/pci.h | 2 ++ + 2 files changed, 5 insertions(+) + +diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c +index a0991da48213..315a8d9cb440 100644 +--- a/drivers/pci/pcie/portdrv.c ++++ b/drivers/pci/pcie/portdrv.c +@@ -684,6 +684,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { + static int pcie_portdrv_probe(struct pci_dev *dev, + const struct pci_device_id *id) + { ++ if (dev->dev_flags & PCI_DEV_FLAGS_NO_PORT_SERVICES) ++ return -ENODEV; ++ + int type = pci_pcie_type(dev); + int status; + +diff --git a/include/linux/pci.h b/include/linux/pci.h +index cdf67f5aa239..daf7f2363658 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -253,6 +253,8 @@ enum pci_dev_flags { + * integrated with the downstream devices and doesn't use real PCI. + */ + PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), ++ /* Do not use native PCIe port services (equivalent to pcie_ports=compat) */ ++ PCI_DEV_FLAGS_NO_PORT_SERVICES = (__force pci_dev_flags_t) (1 << 15), + }; + + enum pci_irq_reroute_variant { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux-lts-kmhv2/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch deleted file mode 100644 index 271d5db9ac..0000000000 --- a/SPECS/linux-lts-kmhv2/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 10d617cd5ad42153be1aa390de90e0cdd8376340 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 17:00:37 +0800 -Subject: [RUYI PATCH] REVYSR: net: stmmac: add support for dwmac 5.10a - -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -index b9218c07eb6b..a27b2bc177af 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { - { .compatible = "snps,dwmac-3.72a"}, - { .compatible = "snps,dwmac-4.00"}, - { .compatible = "snps,dwmac-4.10a"}, -+ { .compatible = "snps,dwmac-5.10a"}, - { .compatible = "snps,dwmac"}, - { .compatible = "snps,dwxgmac-2.10"}, - { .compatible = "snps,dwxgmac"}, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0448-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux-lts-kmhv2/0448-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch new file mode 100644 index 0000000000..6eaf9b9ecd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0448-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch @@ -0,0 +1,60 @@ +From e0f84e027e0c4bfad18d1f9f85e526228473219a Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:56:58 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services + on Sophgo SG2042 + +SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to +downstream devices when native port services are enabled. Devices under +an affected root port receive zero interrupts despite successful vector +allocation, causing driver timeouts (e.g. amdgpu fence fallback timer +expired on all rings). + +Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the +port service driver from probing, restoring correct MSI delivery. + +Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 12 ++++++++++++ + include/linux/pci_ids.h | 2 ++ + 2 files changed, 14 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 481e4186a5c1..28d23f8dfd60 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -6388,3 +6388,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); + #endif ++ ++/* ++ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to ++ * downstream devices when native PCIe port services are enabled. All ++ * services including bwctrl must be disabled, equivalent to pcie_ports=compat. ++ */ ++static void quirk_sg2042_no_port_services(struct pci_dev *dev) ++{ ++ pci_info(dev, "SG2042: disabling native PCIe port services\n"); ++ dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 2b6692a5005f..7c01548a6ddb 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2633,6 +2633,8 @@ + + #define PCI_VENDOR_ID_CXL 0x1e98 + ++#define PCI_VENDOR_ID_SOPHGO 0x1f1c ++ + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 + #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 + #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch deleted file mode 100644 index 9de39c75e0..0000000000 --- a/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch +++ /dev/null @@ -1,578 +0,0 @@ -From 99ea7fd4bd1ccf2910170d8c84c997b33c948537 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 16 May 2025 11:12:26 +0800 -Subject: [RUYI PATCH] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 SoC - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/Makefile | 1 + - arch/riscv/boot/dts/ultrarisc/Makefile | 2 + - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ - 3 files changed, 539 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts - -diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile -index 3763d199c70a..297b30243037 100644 ---- a/arch/riscv/boot/dts/Makefile -+++ b/arch/riscv/boot/dts/Makefile -@@ -10,3 +10,4 @@ subdir-y += sophgo - subdir-y += spacemit - subdir-y += starfive - subdir-y += thead -+subdir-y += ultrarisc -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -new file mode 100644 -index 000000000000..c27f490e2b99 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-y += dp1000.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -new file mode 100644 -index 000000000000..3eb811f73aa8 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -0,0 +1,536 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "ultrarisc,dp1000"; -+ model = "ultrarisc,dp1000"; -+ -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+ -+ cpus { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ timebase-frequency = <10000000>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ reg = <0x00>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu0_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ reg = <0x1>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu1_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ reg = <0x2>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu2_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ reg = <0x3>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu3_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu4: cpu@4 { -+ device_type = "cpu"; -+ reg = <0x10>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu4_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu5: cpu@5 { -+ device_type = "cpu"; -+ reg = <0x11>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu5_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu6: cpu@6 { -+ device_type = "cpu"; -+ reg = <0x12>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ -+ clock-frequency = <2000000000>; -+ -+ cpu6_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu7: cpu@7 { -+ device_type = "cpu"; -+ reg = <0x13>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu7_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00 0x80000000 0x4 0x00000000>; -+ }; -+ -+ soc { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "simple-bus"; -+ ranges; -+ -+ clocks { -+ compatible = "simple-bus"; -+ u-boot,dm-pre-reloc; -+ device_clk: device_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <62500000>; -+ #clock-cells = <0>; -+ }; -+ csr_clk: csr_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <250000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ clint: clint@8000000 { -+ compatible = "riscv,clint0"; -+ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ reg = <0x00 0x8000000 0x00 0x100000>; -+ }; -+ -+ plic: plic@9000000 { -+ #interrupt-cells = <1>; -+ #address-cells = <0>; -+ phandle = <0x01>; -+ compatible = "ultrarisc,dp1000-plic"; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ reg = <0x00 0x9000000 0x00 0x4000000>; -+ riscv,max-priority = <0x07>; -+ riscv,ndev = <160>; -+ }; -+ -+ uart0: serial@20300000 { -+ interrupt-parent = <0x01>; -+ interrupts = <17>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20300000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart1: serial@20310000 { -+ interrupt-parent = <0x01>; -+ interrupts = <18>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20310000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart2: serial@20400000 { -+ interrupt-parent = <0x01>; -+ interrupts = <25>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20400000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart3: serial@20410000 { -+ interrupt-parent = <0x01>; -+ interrupts = <26>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20410000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ spi0: spi@20320000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20320000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <19>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; -+ }; -+ -+ spi1: spi@20420000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20420000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <27>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ }; -+ -+ i2c0: i2c@20330000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20330000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <20>; -+ }; -+ -+ i2c1: i2c@20340000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20340000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <21>; -+ }; -+ -+ i2c2: i2c@20430000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20430000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <28>; -+ }; -+ -+ i2c3: i2c@20440000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20440000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <29>; -+ }; -+ -+ wdt0: watchdog@20210000 { -+ compatible = "snps,dw-wdt"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20210000 0x0 0x100>; -+ interrupt-parent = <0x01>; -+ interrupts = <33>; -+ clocks = <&device_clk>; -+ }; -+ -+ timer0: timer@20220000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20220000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <35>; -+ status = "okay"; -+ }; -+ -+ timer1: timer@20230000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20230000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <36>; -+ status = "okay"; -+ }; -+ -+ gpio: gpio@20200000 { -+ compatible = "snps,dw-apb-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20200000 0x0 0x1000>; -+ clocks = <&csr_clk>, <&device_clk>; -+ clock-names = "bus", "db"; -+ status = "okay"; -+ -+ porta: gpio-port@0 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <16>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <0x01>; -+ interrupts = <34>; -+ }; -+ -+ portb: gpio-port@1 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portc: gpio-port@2 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portd: gpio-port@3 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <3>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ }; -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ phandle = <0x04>; -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ dmac: dma-controller@39000000 { -+ compatible = "snps,axi-dma-1.01a"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x39000000 0x0 0x400>; -+ clocks = <&device_clk>, <&device_clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <0x01>; -+ interrupts = <152>; -+ #dma-cells = <1>; -+ dma-channels = <8>; -+ snps,dma-masters = <1>; -+ snps,data-width = <4>; -+ snps,block-size = <512 512 512 512 512 512 512 512>; -+ snps,priority = <0 1 2 3 4 5 6 7>; -+ snps,axi-max-burst-len = <256>; -+ }; -+ -+ pcie_x16: pcie@21000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ -+ pcie_x4a: pcie@23000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, -+ <0x0 0x0 0x0 0x2 &plic 65>, -+ <0x0 0x0 0x0 0x3 &plic 66>, -+ <0x0 0x0 0x0 0x4 &plic 67>; -+ }; -+ -+ pcie_x4b: pcie@24000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, -+ <0x0 0x0 0x0 0x2 &plic 75>, -+ <0x0 0x0 0x0 0x3 &plic 76>, -+ <0x0 0x0 0x0 0x4 &plic 77>; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0449-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux-lts-kmhv2/0449-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch new file mode 100644 index 0000000000..5de83f4a30 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0449-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch @@ -0,0 +1,83 @@ +From 3b6fe729fdaddb25e1dd2b72d088b126141b2cfa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= +Date: Thu, 18 Sep 2025 13:58:56 -0700 +Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to + allow GPU BAR resize +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Resizing BAR to a larger size has to release upstream bridge windows in +order make the bridge windows larger as well (and to potential relocate +them into a larger free block within iomem space). Some GPUs have an +integrated PCI switch that has BAR0. The resource allocation assigns +space for that BAR0 as it does for any resource. + +An extra resource on a bridge will pin its upstream bridge window in +place which prevents BAR resize for anything beneath that bridge. + +Nothing in the pcieport driver provided by PCI core, which typically is +the driver bound to these bridges, requires that BAR0. Because of that, +releasing the extra BAR does not seem to have notable downsides but +comes with a clear upside. + +Therefore, release BAR0 of such switches using a quirk and clear its +flags to prevent any new invocation of the resource assignment +algorithm from assigning the resource again. + +Due to other siblings within the PCI hierarchy of all the devices +integrated into the GPU, some other devices may still have to be +manually removed before the resize is free of any bridge window pins. +Such siblings can be released through sysfs to unpin windows while +leaving access to GPU's sysfs entries required for initiating the +resize operation, whereas removing the topmost bridge this quirk +targets would result in removing the GPU device as well so no manual +workaround for this problem exists. + +Reported-by: Lucas De Marchi +Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ +Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ +Signed-off-by: Ilpo Järvinen +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Lucas De Marchi +Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com +Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 28d23f8dfd60..f0cd6c2a7827 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -6400,3 +6400,26 @@ static void quirk_sg2042_no_port_services(struct pci_dev *dev) + dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; + } + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); ++ ++/* ++ * PCI switches integrated into Intel Arc GPUs have BAR0 that prevents ++ * resizing the BARs of the GPU device due to that bridge BAR0 pinning the ++ * bridge window it's under in place. Nothing in pcieport requires that ++ * BAR0. ++ * ++ * Release and disable BAR0 permanently by clearing its flags to prevent ++ * anything from assigning it again. ++ */ ++static void pci_release_bar0(struct pci_dev *pdev) ++{ ++ struct resource *res = pci_resource_n(pdev, 0); ++ ++ if (!res->parent) ++ return; ++ ++ pci_release_resource(pdev, 0); ++ res->flags = 0; ++} ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa0, pci_release_bar0); ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa1, pci_release_bar0); ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0xe2ff, pci_release_bar0); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux-lts-kmhv2/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch deleted file mode 100644 index fad0cc8ffd..0000000000 --- a/SPECS/linux-lts-kmhv2/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,880 +0,0 @@ -From 709a5329d0c5e869292d0fb40e080d1e280adb51 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 17 Jan 2025 19:34:48 +0800 -Subject: [RUYI PATCH] RVCK: pinctrl: add pinctrl dirver for UltraRisc DP1000 - -support pinmux and pinconf for UltraRisc DP1000 SoC - -Signed-off-by: Jia Wang -Signed-off-by: Yanteng Si -FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade -Signed-off-by: Han Gao ---- - drivers/pinctrl/Kconfig | 1 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/ultrarisc/Kconfig | 20 + - drivers/pinctrl/ultrarisc/Makefile | 4 + - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ - .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ - 8 files changed, 794 insertions(+) - create mode 100644 drivers/pinctrl/ultrarisc/Kconfig - create mode 100644 drivers/pinctrl/ultrarisc/Makefile - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h - create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h - -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index 4f8507ebbdac..b4ba4fb72f10 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -712,5 +712,6 @@ source "drivers/pinctrl/ti/Kconfig" - source "drivers/pinctrl/uniphier/Kconfig" - source "drivers/pinctrl/visconti/Kconfig" - source "drivers/pinctrl/vt8500/Kconfig" -+source "drivers/pinctrl/ultrarisc/Kconfig" - - endif -diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index e0cfb9b7c99b..32f0d988e505 100644 ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -95,3 +95,4 @@ obj-y += ti/ - obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ - obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ - obj-$(CONFIG_ARCH_VT8500) += vt8500/ -+obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ -diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig -new file mode 100644 -index 000000000000..e4db80843bea ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Kconfig -@@ -0,0 +1,20 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config PINCTRL_ULTRARISC -+ bool -+ depends on OF -+ select PINMUX -+ select GENERIC_PINCTRL_GROUPS -+ select GENERIC_PINCONF -+ select GENERIC_PINMUX_FUNCTIONS -+ select GPIOLIB -+ select IRQ_DOMAIN_HIERARCHY -+ select MFD_SYSCON -+ -+config PINCTRL_ULTRARISC_DP1000 -+ tristate "Pinctrl driver of UltraRisc DP1000" -+ select PINCTRL_ULTRARISC -+ depends on OF && HAS_IOMEM -+ help -+ This driver configures the UltraRisc DP1000 SoC's pinctrl -+ subsystem. -diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile -new file mode 100644 -index 000000000000..5bf3f449d59b ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o -+obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o -\ No newline at end of file -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -new file mode 100644 -index 000000000000..217f671fe63a ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static const struct pinctrl_pin_desc ur_dp1000_pins[] = { -+ // PA -+ PINCTRL_PIN(0, "PA0"), -+ PINCTRL_PIN(1, "PA1"), -+ PINCTRL_PIN(2, "PA2"), -+ PINCTRL_PIN(3, "PA3"), -+ PINCTRL_PIN(4, "PA4"), -+ PINCTRL_PIN(5, "PA5"), -+ PINCTRL_PIN(6, "PA6"), -+ PINCTRL_PIN(7, "PA7"), -+ PINCTRL_PIN(8, "PA8"), -+ PINCTRL_PIN(9, "PA9"), -+ PINCTRL_PIN(10, "PA10"), -+ PINCTRL_PIN(11, "PA11"), -+ PINCTRL_PIN(12, "PA12"), -+ PINCTRL_PIN(13, "PA13"), -+ PINCTRL_PIN(14, "PA14"), -+ PINCTRL_PIN(15, "PA15"), -+ // PB -+ PINCTRL_PIN(16, "PB0"), -+ PINCTRL_PIN(17, "PB1"), -+ PINCTRL_PIN(18, "PB2"), -+ PINCTRL_PIN(19, "PB3"), -+ PINCTRL_PIN(20, "PB4"), -+ PINCTRL_PIN(21, "PB5"), -+ PINCTRL_PIN(22, "PB6"), -+ PINCTRL_PIN(23, "PB7"), -+ // PC -+ PINCTRL_PIN(24, "PC0"), -+ PINCTRL_PIN(25, "PC1"), -+ PINCTRL_PIN(26, "PC2"), -+ PINCTRL_PIN(27, "PC3"), -+ PINCTRL_PIN(28, "PC4"), -+ PINCTRL_PIN(29, "PC5"), -+ PINCTRL_PIN(30, "PC6"), -+ PINCTRL_PIN(31, "PC7"), -+ // PD -+ PINCTRL_PIN(32, "PD0"), -+ PINCTRL_PIN(33, "PD1"), -+ PINCTRL_PIN(34, "PD2"), -+ PINCTRL_PIN(35, "PD3"), -+ PINCTRL_PIN(36, "PD4"), -+ PINCTRL_PIN(37, "PD5"), -+ PINCTRL_PIN(38, "PD6"), -+ PINCTRL_PIN(39, "PD7"), -+ // LPC -+ PINCTRL_PIN(40, "LPC0"), -+ PINCTRL_PIN(41, "LPC1"), -+ PINCTRL_PIN(42, "LPC2"), -+ PINCTRL_PIN(43, "LPC3"), -+ PINCTRL_PIN(44, "LPC4"), -+ PINCTRL_PIN(45, "LPC5"), -+ PINCTRL_PIN(46, "LPC6"), -+ PINCTRL_PIN(47, "LPC7"), -+ PINCTRL_PIN(48, "LPC8"), -+ PINCTRL_PIN(49, "LPC9"), -+ PINCTRL_PIN(50, "LPC10"), -+ PINCTRL_PIN(51, "LPC11"), -+ PINCTRL_PIN(52, "LPC12"), -+}; -+ -+static struct ur_pinctrl_match_data ur_dp1000_match_data = { -+ .pins = ur_dp1000_pins, -+ .npins = ARRAY_SIZE(ur_dp1000_pins), -+ .offset = 0x2c0, -+ .ports = { -+ {"A", 16, 0x2c0, 0x310}, -+ {"B", 8, 0x2c4, 0x318}, -+ {"C", 8, 0x2c8, 0x31c}, -+ {"D", 8, 0x2cc, 0x320}, -+ {"LPC", 13, 0x2d0, 0x324}, -+ }, -+}; -+ -+enum ur_dp1000_port_list { -+ PORT_A = 0, -+ PORT_B, -+ PORT_C, -+ PORT_D, -+ PORT_LPC -+}; -+ -+ -+static const struct of_device_id ur_pinctrl_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); -+ -+static struct platform_driver ur_pinctrl_driver = { -+ .driver = { -+ .name = "ultrarisc-pinctrl-dp1000", -+ .of_match_table = ur_pinctrl_of_match, -+ }, -+ .probe = ur_pinctrl_probe, -+ .remove = ur_pinctrl_remove, -+}; -+ -+module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -new file mode 100644 -index 000000000000..667d59e0ac6e ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -0,0 +1,503 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) -+{ -+ int index = 0; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; -+ -+ for (int i = 0; i < pin_val->port; i++) -+ index += ur_match_data->ports[i].npins; -+ index += pin_val->pin; -+ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); -+ return index; -+} -+ -+static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, -+ const char *name, -+ enum pinctrl_map_type type, -+ struct device_node *np, -+ int **pins, -+ struct ur_pin_val **pin_val, -+ int *pin_num) -+{ -+ struct ur_pin_val *pin_vals; -+ int rows; -+ int ret = -EINVAL; -+ int *group_pins; -+ const char **pgnames; -+ -+ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); -+ rows = pinctrl_count_index_with_args(np, name); -+ if (rows < 0) { -+ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); -+ return rows; -+ } -+ -+ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); -+ if (!pin_vals) { -+ return -ENOMEM; -+ } -+ -+ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); -+ if (!group_pins) { -+ ret = -ENOMEM; -+ goto free_pin_vals; -+ } -+ -+ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); -+ if (!pgnames) { -+ ret = -ENOMEM; -+ goto free_pins; -+ } -+ -+ for (int i = 0; i < rows; i++) { -+ struct of_phandle_args pin_args; -+ -+ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); -+ if (ret) { -+ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); -+ goto free_pgnames; -+ } -+ -+ if (pin_args.args_count < 3) { -+ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", -+ pin_args.args_count, name, i, rows); -+ ret = -EINVAL; -+ goto free_pgnames; -+ } -+ pin_vals[i].port = pin_args.args[0]; -+ pin_vals[i].pin = pin_args.args[1]; -+ pin_vals[i].mode = pin_args.args[2]; -+ -+ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", -+ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); -+ -+ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); -+ -+ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add group %s failed\n", np->name); -+ goto free_pgnames; -+ } -+ -+ *pgnames = np->name; -+ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add function %s failed\n", np->name); -+ goto free_group; -+ } -+ -+ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); -+ -+ *pins = group_pins; -+ *pin_val = pin_vals; -+ *pin_num = rows; -+ -+ return 0; -+ -+free_group: -+ pinctrl_generic_remove_group(pctldev, ret); -+free_pgnames: -+ devm_kfree(pctldev->dev, pgnames); -+free_pins: -+ devm_kfree(pctldev->dev, group_pins); -+free_pin_vals: -+ devm_kfree(pctldev->dev, pin_vals); -+ return ret; -+} -+ -+static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin_vals; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, -+ np, &pins, &pin_vals, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); -+ return ret; -+ } -+ -+ map->type = PIN_MAP_TYPE_MUX_GROUP; -+ map->data.mux.group = np->name; -+ map->data.mux.function = np->name; -+ -+ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", -+ map->type, map->data.mux.group, map->data.mux.function); -+ -+ return 0; -+} -+ -+static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, -+ np, &pins, &pin, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); -+ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; -+ map->data.configs.group_or_pin = np->name; -+ map->data.configs.configs = (unsigned long *)pin; -+ map->data.configs.num_configs = pin_num; -+ -+ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", -+ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); -+ -+ return 0; -+} -+ -+static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map **map, -+ unsigned int *num_maps) -+{ -+ int ret; -+ bool mux_present = false, conf_present = false; -+ struct pinctrl_map *new_map; -+ unsigned int map_num = 0, prop_count = 0; -+ -+ //device_get_named_child_node(pctldev->dev, np->name); -+ if (of_property_present(np, PINMUX_PROP_NAME)) { -+ mux_present = true; -+ prop_count++; -+ } -+ if (of_property_present(np, PINCONF_PROP_NAME)) { -+ conf_present = true; -+ prop_count++; -+ } -+ -+ if (!prop_count) { -+ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); -+ return -EINVAL; -+ } -+ -+ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); -+ if (!new_map) -+ return -ENOMEM; -+ -+ *map = new_map; -+ if (mux_present) { -+ ret = ur_pinmux_to_map(pctldev, np, new_map); -+ if (!ret) { -+ new_map++; -+ map_num++; -+ } -+ } -+ if (conf_present) { -+ ret = ur_pinconf_to_map(pctldev, np, new_map); -+ if (!ret) -+ map_num++; -+ } -+ -+ if (!map_num) { -+ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); -+ goto free_map; -+ } -+ *num_maps = map_num; -+ -+ return 0; -+ -+free_map: -+ devm_kfree(pctldev->dev, new_map); -+ return ret; -+} -+ -+static void ur_dt_free_map(struct pinctrl_dev *pctldev, -+ struct pinctrl_map *map, unsigned int num_maps) -+{ -+ if (map) -+ devm_kfree(pctldev->dev, map); -+} -+ -+static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, -+ struct seq_file *s, unsigned int offset) -+{ -+ seq_printf(s, "%s", dev_name(pctldev->dev)); -+} -+ -+static const struct pinctrl_ops ur_pinctrl_ops = { -+ .get_groups_count = pinctrl_generic_get_group_count, -+ .get_group_name = pinctrl_generic_get_group_name, -+ .get_group_pins = pinctrl_generic_get_group_pins, -+ .dt_node_to_map = ur_dt_node_to_map, -+ .dt_free_map = ur_dt_free_map, -+ .pin_dbg_show = ur_pin_dbg_show, -+}; -+ -+static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ unsigned long flag; -+ //bool clear_mode = false; -+ void __iomem *reg; -+ u32 val; -+ const struct ur_port_desc *port; -+ -+ port = &pin_ctrl->match_data->ports[pin_vals->port]; -+ -+ reg = pin_ctrl->base + port->func_offset; -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); -+ val |= (pin_vals->mode << pin_vals->pin); -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ -+ return 0; -+} -+ -+static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, -+ unsigned int group_selector) -+{ -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_vals; -+ -+ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", -+ func_selector, group_selector); -+ ur_group = pinctrl_generic_get_group(pctldev, group_selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "get group %d failed\n", group_selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); -+ pin_vals = ur_group->data; -+ if (!pin_vals) { -+ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); -+ return -EINVAL; -+ } -+ -+ for (int i = 0; i < ur_group->grp.npins; i++) -+ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); -+ -+ return 0; -+} -+ -+static const struct pinmux_ops ur_pinmux_ops = { -+ .get_functions_count = pinmux_generic_get_function_count, -+ .get_function_name = pinmux_generic_get_function_name, -+ .get_function_groups = pinmux_generic_get_function_groups, -+ .set_mux = ur_set_mux, -+ .strict = true, -+}; -+ -+#define UR_CONF_BIT_PER_PIN (4) -+#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ const struct ur_port_desc *port_desc; -+ unsigned long flag; -+ void __iomem *reg; -+ u32 val, conf; -+ -+ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ reg = pin_ctrl->base + port_desc->conf_offset; -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; -+ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); -+ -+ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); -+ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); -+ val |= conf; -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); -+ -+ return 0; -+} -+ -+static int ur_pin_config_get(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); -+ // TODO: this is call by pinconf-generic -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_set(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -+ __func__, __LINE__, pin, num_configs); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", -+ __func__, __LINE__, selector, *config); -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", -+ __func__, __LINE__, selector, num_configs); -+ ur_group = pinctrl_generic_get_group(pctldev, selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static const struct pinconf_ops ur_pinconf_ops = { -+ .pin_config_get = ur_pin_config_get, -+ .pin_config_set = ur_pin_config_set, -+ .pin_config_group_get = ur_pin_config_group_get, -+ .pin_config_group_set = ur_pin_config_group_set, -+#ifdef CONFIG_GENERIC_PINCONF -+ .is_generic = true, -+#endif -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct pinctrl_desc *ur_pinctrl_desc; -+ const struct ur_pinctrl_match_data *pins_data; -+ struct ur_pinctrl *ur_pinctrl; -+ int ret; -+ -+ pins_data = of_device_get_match_data(&pdev->dev); -+ if (!pins_data) -+ return -ENODEV; -+ -+ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); -+ if (!ur_pinctrl_desc) { -+ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); -+ if (!ur_pinctrl) { -+ dev_err(&pdev->dev, "pinctrl alloc failed\n"); -+ ret = -ENOMEM; -+ goto free_pinctrl_desc; -+ } -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); -+ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ur_pinctrl->base)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pinctrl_desc; -+ } -+ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); -+ ur_pinctrl_desc->name = dev_name(&pdev->dev); -+ ur_pinctrl_desc->owner = THIS_MODULE; -+ ur_pinctrl_desc->pins = pins_data->pins; -+ ur_pinctrl_desc->npins = pins_data->npins; -+ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; -+ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; -+ ur_pinctrl_desc->confops = &ur_pinconf_ops; -+ -+ ur_pinctrl->dev = &pdev->dev; -+ ur_pinctrl->match_data = pins_data; -+ ur_pinctrl->pctl_desc = ur_pinctrl_desc; -+ raw_spin_lock_init(&ur_pinctrl->lock); -+ mutex_init(&ur_pinctrl->mutex); -+ -+ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, -+ ur_pinctrl, &ur_pinctrl->pctl_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "pinctrl register failed\n"); -+ goto free_pinctrl; -+ } -+ -+ platform_set_drvdata(pdev, ur_pinctrl); -+ -+ return pinctrl_enable(ur_pinctrl->pctl_dev); -+ -+free_pinctrl: -+ devm_kfree(&pdev->dev, ur_pinctrl); -+free_pinctrl_desc: -+ devm_kfree(&pdev->dev, ur_pinctrl_desc); -+ return ret; -+} -+ -+ -+void ur_pinctrl_remove(struct platform_device *pdev) -+{ -+ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -+ -+ if (ur_pinctrl->pctl_dev) -+ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); -+} -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -new file mode 100644 -index 000000000000..eec621bf8b05 ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __PINCTRL_ULTRARISC_H__ -+#define __PINCTRL_ULTRARISC_H__ -+ -+#include -+#include -+ -+#define PINMUX_PROP_NAME "pinctrl-pins" -+#define PINCONF_PROP_NAME "pinconf-pins" -+ -+struct ur_pin_conf { -+ u16 pull; -+ u16 drive; -+}; -+ -+struct ur_pin_val { -+ u32 port; -+ u32 pin; -+ union { -+ u32 mode; -+ u32 conf; -+ }; -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+#define UR_BIAS_MASK 0x0000000F -+#define UR_PULL_MASK 0x0C -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+#define UR_DRIVE_MASK 0x03 -+}; -+ -+struct ur_port_desc { -+ char *name; -+ u32 npins; -+ u32 func_offset; -+ u32 conf_offset; -+}; -+ -+struct ur_pinctrl_match_data { -+ const struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 offset; -+ //u32 conf_offset[]; -+ struct ur_port_desc ports[]; -+}; -+ -+ -+struct ur_pinctrl { -+ struct device *dev; -+ struct pinctrl_dev *pctl_dev; -+ struct pinctrl_desc *pctl_desc; -+ void __iomem *base; -+ unsigned int ngroups; -+ const char **grp_names; -+ unsigned int nbanks; -+ const struct ur_pinctrl_match_data *match_data; -+ struct regmap *regmap; -+ raw_spinlock_t lock; -+ struct mutex mutex; -+ struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 pkg; -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev); -+void ur_pinctrl_remove(struct platform_device *pdev); -+ -+#endif -diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -new file mode 100644 -index 000000000000..5bec446e2411 ---- /dev/null -+++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl header -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __UR_DP1000_PINCTRL_H__ -+#define __UR_DP1000_PINCTRL_H__ -+ -+#define UR_DP1000_IOMUX_A 0x0 -+#define UR_DP1000_IOMUX_B 0x1 -+#define UR_DP1000_IOMUX_C 0x2 -+#define UR_DP1000_IOMUX_D 0x3 -+#define UR_DP1000_IOMUX_LPC 0x4 -+ -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+/** -+ * port: 'A' 'B' 'C' -+ * Pin in the port -+ * pin: -+ * PA: 0 - 15 -+ * PB-PD: 0 - 7 -+ * func: -+ * UR_FUNC_DEF: default -+ * UR_FUNC0: func0 -+ * UR_FUNC1: func1 -+ */ -+#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) -+ -+/** -+ * Configure pull up/down resistor of the IO pin -+ * UR_PULL_DIS: disable pull-up and pull-down -+ * UR_PULL_UP: enable pull-up -+ * UR_PULL_DOWN: enable pull-down -+ */ -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+/** -+ * Configure drive strength of the IO pin -+ * UR_DRIVE_DEF: default value, reset value is 2 -+ * UR_DRIVE_0: 20mA -+ * UR_DRIVE_1: 27mA -+ * UR_DIRVE_2: 33mA -+ * UR_DRIVE_3: 40mA -+ */ -+#define UR_DRIVE_DEF 2 -+#define UR_DRIVE_0 0 -+#define UR_DRIVE_1 1 -+#define UR_DRIVE_2 2 -+#define UR_DRIVE_3 3 -+ -+/** -+ * Combine the pull-up/down resistor and drive strength -+ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN -+ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 -+ */ -+#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0450-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux-lts-kmhv2/0450-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch new file mode 100644 index 0000000000..5d8d7c38cb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0450-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch @@ -0,0 +1,63 @@ +From 5bedd31673a02d21556a205f46115eaa2aadc42f Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sat, 29 Jun 2024 13:22:46 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA + coherency status in ttm_device + +Currently TTM utilizes cached memory regardless of whether the device +have full DMA coherency (can snoop CPU cache). + +Save the device's DMA coherency status in struct ttm_device, to allow +further support of devices w/o snooping capability (the capability +missing on at least one part of the transmission between the CPU and the +device). + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20240629052247.2653363-2-uwu@icenowy.me +[ Han Gao: add conditional compilation for dma_coherent ] +Signed-off-by: Han Gao +--- + drivers/gpu/drm/ttm/ttm_device.c | 6 ++++++ + include/drm/ttm/ttm_device.h | 9 +++++++++ + 2 files changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c +index c3e2fcbdd2cc..1758d94b3d44 100644 +--- a/drivers/gpu/drm/ttm/ttm_device.c ++++ b/drivers/gpu/drm/ttm/ttm_device.c +@@ -246,6 +246,12 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func + list_add_tail(&bdev->device_list, &glob->device_list); + mutex_unlock(&ttm_global_mutex); + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ bdev->dma_coherent = dev->dma_coherent; ++#endif ++ + return 0; + } + EXPORT_SYMBOL(ttm_device_init); +diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h +index 592b5f802859..c2e61312a43a 100644 +--- a/include/drm/ttm/ttm_device.h ++++ b/include/drm/ttm/ttm_device.h +@@ -225,6 +225,15 @@ struct ttm_device { + */ + const struct ttm_device_funcs *funcs; + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /** ++ * @dma_coherent: if the device backed is dma-coherent. ++ */ ++ bool dma_coherent; ++#endif ++ + /** + * @sysman: Resource manager for the system domain. + * Access via ttm_manager_type. +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux-lts-kmhv2/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch deleted file mode 100644 index 935589d38c..0000000000 --- a/SPECS/linux-lts-kmhv2/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,237 +0,0 @@ -From c3b99eaa70d3c031fe29c503b85abb31e02d50a4 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 16 Jun 2025 10:25:31 +0800 -Subject: [RUYI PATCH] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 - -The newly added dtsi/dts is used to describe the pinctrl -configuration of the UltraRisc DP1000-EVB mainboard. - -Do not involve functional changes. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ - 3 files changed, 194 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index c27f490e2b99..ef70e28e0b65 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,2 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb -+dtb-y += dp1000.dtb dp1000-evb-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -new file mode 100644 -index 000000000000..be898b6df6fb ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -0,0 +1,141 @@ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -new file mode 100644 -index 000000000000..5ec9a39e8c34 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -0,0 +1,52 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+#include "dp1000.dts" -+#include "dp1000-evb-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0451-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux-lts-kmhv2/0451-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch new file mode 100644 index 0000000000..8f765e4abb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0451-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch @@ -0,0 +1,125 @@ +From 1500e6d66b9678818ba5df1e067507906ddabc8c Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sat, 29 Jun 2024 13:22:47 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to + write_combined when snooping not available + +As we can now acquire the presence of the full DMA coherency (snooping +capability) from ttm_device, we can now map the CPU side memory as +write-combined when cached is requested and snooping is not avilable. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20240629052247.2653363-3-uwu@icenowy.me +[ Han Gao: add conditional compilation for dma coherent operations ] +[ Icenowy: omit single page ttm_cached optimization when non-coherent and handle linear io iter ] +Signed-off-by: Han Gao +--- + drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +++++++++++++ + drivers/gpu/drm/ttm/ttm_resource.c | 13 +++++++++++-- + drivers/gpu/drm/ttm/ttm_tt.c | 8 ++++++++ + include/drm/ttm/ttm_caching.h | 3 ++- + 4 files changed, 34 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c +index acbbca9d5c92..2a8777d1f2b8 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo_util.c ++++ b/drivers/gpu/drm/ttm/ttm_bo_util.c +@@ -307,6 +307,14 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res, + caching = res->bus.caching; + } + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bo->bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + return ttm_prot_from_caching(caching, tmp); + } + EXPORT_SYMBOL(ttm_io_prot); +@@ -360,6 +368,11 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, + return ret; + + if (num_pages == 1 && ttm->caching == ttm_cached && ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ bo->bdev->dma_coherent && ++#endif + !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { + /* + * We're mapping a single page, and the desired +diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c +index 2a05fbd07546..4f18a9a98f11 100644 +--- a/drivers/gpu/drm/ttm/ttm_resource.c ++++ b/drivers/gpu/drm/ttm/ttm_resource.c +@@ -830,8 +830,17 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, + struct ttm_device *bdev, + struct ttm_resource *mem) + { ++ enum ttm_caching caching = mem->bus.caching; + int ret; + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + ret = ttm_mem_io_reserve(bdev, mem); + if (ret) + goto out_err; +@@ -846,11 +855,11 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, + } else { + iter_io->needs_unmap = true; + memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); +- if (mem->bus.caching == ttm_write_combined) ++ if (caching == ttm_write_combined) + iosys_map_set_vaddr_iomem(&iter_io->dmap, + ioremap_wc(mem->bus.offset, + mem->size)); +- else if (mem->bus.caching == ttm_cached) ++ else if (caching == ttm_cached) + iosys_map_set_vaddr(&iter_io->dmap, + memremap(mem->bus.offset, mem->size, + MEMREMAP_WB | +diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c +index 506e257dfba8..8338deb3330f 100644 +--- a/drivers/gpu/drm/ttm/ttm_tt.c ++++ b/drivers/gpu/drm/ttm/ttm_tt.c +@@ -154,6 +154,14 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, + enum ttm_caching caching, + unsigned long extra_pages) + { ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bo->bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; + ttm->page_flags = page_flags; + ttm->dma_address = NULL; +diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h +index a18f43e93aba..f92d7911f50e 100644 +--- a/include/drm/ttm/ttm_caching.h ++++ b/include/drm/ttm/ttm_caching.h +@@ -47,7 +47,8 @@ enum ttm_caching { + + /** + * @ttm_cached: Fully cached like normal system memory, requires that +- * devices snoop the CPU cache on accesses. ++ * devices snoop the CPU cache on accesses. Downgraded to ++ * ttm_write_combined when the snooping capaiblity is missing. + */ + ttm_cached + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux-lts-kmhv2/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch deleted file mode 100644 index dfeb639386..0000000000 --- a/SPECS/linux-lts-kmhv2/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 6e08f5227680fcb9eef599c73c6a48dbba8d8f66 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 4 Sep 2025 16:31:30 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: add the dts of UltraRISC - dp1000-mo-v1 board - -adds the necessary device tree files for the UltraRISC -dp1000-mo-v1 board. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ - 3 files changed, 209 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index ef70e28e0b65..9eac56549340 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -new file mode 100644 -index 000000000000..e82fcf2901ab ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -new file mode 100644 -index 000000000000..a74714629566 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000.dts" -+#include "dp1000-mo-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@32 { -+ compatible = "whwave,sd3078"; -+ reg = <0x32>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0452-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux-lts-kmhv2/0452-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch new file mode 100644 index 0000000000..aa8d8fd112 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0452-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch @@ -0,0 +1,98 @@ +From 5c63322d4ad772fbd9ac2df51769aa8e554b790e Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:16 +0000 +Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP + table for TH1520 + +Add operating point table for CPU cores, and wire up clocks for CPU +nodes. + +This patch isn't intended for upstreaming but only for testing purpose, +since the PMIC driver for scaling CPU voltage isn't ready yet. Only +operating points whose voltage is satisified by Lichee Module 4A's PMIC +default, i.e. <= 1.5GHz, are enabled. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20251120131416.26236-8-ziyao@disroot.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 35 +++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 94932c51b7e3..f2abc6338458 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -38,6 +38,8 @@ c910_0: cpu@0 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -65,6 +67,8 @@ c910_1: cpu@1 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -92,6 +96,8 @@ c910_2: cpu@2 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -119,6 +125,8 @@ c910_3: cpu@3 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -137,6 +145,33 @@ l2_cache: l2-cache { + }; + }; + ++ cpu_opp: opp-table-cpu { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <600000>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <700000>; ++ }; ++ ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <800000>; ++ }; ++ ++/* ++ opp-1848000000 { ++ opp-hz = /bits/ 64 <1848000000>; ++ opp-microvolt = <1000000>; ++ }; ++ */ ++ }; ++ + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch deleted file mode 100644 index ee76518537..0000000000 --- a/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch +++ /dev/null @@ -1,111 +0,0 @@ -From b9ce7c71ab1aae741d95ad74bd380256a79a7de3 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 9 Sep 2025 15:45:52 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to - board DTS - -The mmc0 node (mmc-spi-slot) is a board-level peripheral -specific to the UltraRISC DP1000 EVB V1.0, not part of the -base SoC. Move it from the SoC-level dp1000.dts to the -board-specific dp1000-evb-v1.dts to maintain proper device -tree hierarchy between SoC core and board-specific components. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 -Signed-off-by: Han Gao ---- - .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ - 3 files changed, 21 insertions(+), 19 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index be898b6df6fb..e82fcf2901ab 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -1,3 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ - #include - - / { -@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) - - uart0_pins: uart0_pins { - pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) - >; - - pinconf-pins = < -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 5ec9a39e8c34..34622a33e63b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - #include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" -@@ -27,6 +25,14 @@ &i2c3 { - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -+ -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; - }; - - &spi1 { -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 3eb811f73aa8..23a983d6a4c8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - /dts-v1/; - -@@ -261,13 +259,6 @@ spi0: spi@20320000 { - clock-names = "device_clk"; - num-cs = <3>; - spi-max-frequency = <62500000>; -- mmc0: mmc@0 { -- compatible = "mmc-spi-slot"; -- spi-max-frequency = <15625000>; -- reg = <0x00>; -- voltage-ranges = <3300 3300>; -- disable-wp; -- }; - }; - - spi1: spi@20420000 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0453-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux-lts-kmhv2/0453-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch new file mode 100644 index 0000000000..5d15847c7d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0453-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch @@ -0,0 +1,83 @@ +From d7a807a6da111df9d1768cea86661423eb39f79d Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:54 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate + Makefile + +A subsequent commit will add a new function `bindgen-option` to +`scripts/Kconfig.include`. The bindgen backend requires the `--target` +option for cross compiling, but variable `BINDGEN_TARGET` in +`rust/Makefile` cannot be exported to `scripts/Kconfig.include`. + +Therefore, move this variable to a separate new `Makefile.rust` file and +include it from `scripts/Makefile` to make the exported variable +available for use in Kconfig. Place the include in the `need-compiler` +branch to avoid including it in irrelevant make targets. + +Since the new file name is `Makefile.rust`, it matches an existing +MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS +file is needed. + +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-1-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + Makefile | 3 ++- + rust/Makefile | 8 -------- + scripts/Makefile.rust | 9 +++++++++ + 3 files changed, 11 insertions(+), 9 deletions(-) + create mode 100644 scripts/Makefile.rust + +diff --git a/Makefile b/Makefile +index 8ae52cf42da5..45c25959a2b1 100644 +--- a/Makefile ++++ b/Makefile +@@ -725,9 +725,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) + include $(srctree)/scripts/Makefile.clang + endif + ++ifdef need-compiler ++include $(srctree)/scripts/Makefile.rust + # Include this also for config targets because some architectures need + # cc-cross-prefix to determine CROSS_COMPILE. +-ifdef need-compiler + include $(srctree)/scripts/Makefile.compiler + endif + +diff --git a/rust/Makefile b/rust/Makefile +index d4618f646b05..c311d16e7e74 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -300,14 +300,6 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fzero-init-padding-bits=% -mno-fdpic \ + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference + +-# Derived from `scripts/Makefile.clang`. +-BINDGEN_TARGET_x86 := x86_64-linux-gnu +-BINDGEN_TARGET_arm64 := aarch64-linux-gnu +-BINDGEN_TARGET_arm := arm-linux-gnueabi +-BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf +-BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) +-BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) +- + # All warnings are inhibited since GCC builds are very experimental, + # many GCC warnings are not supported by Clang, they may only appear in + # some configurations, with new GCC versions, etc. +diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust +new file mode 100644 +index 000000000000..5c12b4b8c8b6 +--- /dev/null ++++ b/scripts/Makefile.rust +@@ -0,0 +1,9 @@ ++# Derived from `scripts/Makefile.clang`. ++BINDGEN_TARGET_x86 := x86_64-linux-gnu ++BINDGEN_TARGET_arm64 := aarch64-linux-gnu ++BINDGEN_TARGET_arm := arm-linux-gnueabi ++BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf ++BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) ++BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) ++ ++export BINDGEN_TARGET +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch deleted file mode 100644 index 2e0d7ad5ce..0000000000 --- a/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 2e69e921113ca412333654bea99e8cde384f3780 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 18 Sep 2025 10:44:01 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: plic: add plic early init supports - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - -------------------------------------------------- - -Add PLIC early init supports and remove invalid -timer nodes in dp1000.dts. - -Signed-off-by: Jia Wang -From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- - drivers/irqchip/irq-sifive-plic.c | 1 + - 2 files changed, 3 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 23a983d6a4c8..4a2dae602693 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -164,6 +164,7 @@ device_clk: device_clk { - clock-frequency = <62500000>; - #clock-cells = <0>; - }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { - interrupts = <33>; - clocks = <&device_clk>; - }; -- -- timer0: timer@20220000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20220000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <35>; -- status = "okay"; -- }; -- -- timer1: timer@20230000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20230000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <36>; -- status = "okay"; -- }; -- -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 70058871d2fb..007a4668f9e5 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, - } - - IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); -+IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0454-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux-lts-kmhv2/0454-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch new file mode 100644 index 0000000000..930937fa4d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0454-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch @@ -0,0 +1,61 @@ +From 0fb94e0dedf55feb6037f53cc79738321746b27c Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:55 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET + is undefined + +Generate a friendly fatal error if the target triplet is undefined for +bindgen, rather than having the compiler generate obscure error messages +during the build stage. + +`BINDGEN_TARGET` is actually defined in `scripts/Makefile.rust`, but the +file is included regardless of whether Rust is enabled, so perform this +check in `rust/Makefile` to avoid breaking targets that do not yet +support Rust builds. + +This piece of code is copied from `scripts/Makefile.clang`. + +Before this commit, error messages might look like: + +error: unknown argument: '-mno-riscv-attribute' +error: unsupported argument 'medany' to option '-mcmodel=' for target +'unknown' +error: unsupported option '-march=' for target '' +error: unsupported option '-mno-save-restore' for target '' +error: unknown target triple 'unknown' +panicked at bindgen/ir/context.rs:562:15: +libclang error; possible causes include: +- Invalid flag syntax +- Unrecognized flags +- Invalid flag arguments +- File I/O errors +- Host vs. target architecture mismatch + +Acked-by: Miguel Ojeda +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-2-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + rust/Makefile | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/rust/Makefile b/rust/Makefile +index c311d16e7e74..6d2d542a55e8 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -300,6 +300,12 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fzero-init-padding-bits=% -mno-fdpic \ + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference + ++# Because scripts/Makefile.rust is included regardless of whether Rust is enabled, ++# we perform this check here to avoid breaking targets that do not yet support Rust builds. ++ifeq ($(BINDGEN_TARGET),) ++$(error add '--target=' option to scripts/Makefile.rust) ++endif ++ + # All warnings are inhibited since GCC builds are very experimental, + # many GCC warnings are not supported by Clang, they may only appear in + # some configurations, with new GCC versions, etc. +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux-lts-kmhv2/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch deleted file mode 100644 index 87e90bc15e..0000000000 --- a/SPECS/linux-lts-kmhv2/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch +++ /dev/null @@ -1,85 +0,0 @@ -From c95a87c3fe519649f8470396461cd19be68bb138 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 10 Nov 2025 16:11:12 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move chosen node from common - to board-specific DTS - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -This commit moves the chosen node configuration from the -common dp1000.dts file to the respective board-specific -DTS files. - -This change allows each board to specify its own console -configuration while keeping the common SoC definitions clean. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ - 3 files changed, 15 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34622a33e63b..34d024a083fc 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-evb-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index a74714629566..8c532e5b71a3 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-mo-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 4a2dae602693..128293c0af1f 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -10,12 +10,7 @@ / { - #size-cells = <0x02>; - compatible = "ultrarisc,dp1000"; - model = "ultrarisc,dp1000"; -- -- chosen { -- bootargs = "earlycon=sbi console=ttyS1,115200"; -- stdout-path = &uart1; -- }; -- -+ - cpus { - #address-cells = <0x01>; - #size-cells = <0x00>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0455-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux-lts-kmhv2/0455-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch new file mode 100644 index 0000000000..bf57eb698d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0455-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch @@ -0,0 +1,35 @@ +From 0a7fb712936e3739ca0aec162a654b3554e8de8d Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:56 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for + support of bindgen options + +Add a new `bindgen-backend-option` Kconfig function to test whether the +bindgen backend supports a given flag. + +A subsequent commit will use this function to test for RISC-V extension +flags. + +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-3-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + scripts/Kconfig.include | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include +index d42042b6c9e2..9954b8093fab 100644 +--- a/scripts/Kconfig.include ++++ b/scripts/Kconfig.include +@@ -78,3 +78,8 @@ rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) + # If you are testing for unstable features, consider testing RUSTC_VERSION + # instead, as features may have different completeness while available. + rustc-option = $(success,trap "rm -rf .tmp_$$" EXIT; mkdir .tmp_$$; $(RUSTC) $(1) --crate-type=rlib /dev/null --out-dir=.tmp_$$ -o .tmp_$$/tmp.rlib) ++ ++# $(bindgen-backend-option,) ++# Return y if bindgen backend supports , n otherwise ++# For now, the backend refers only to libclang, so more specifically, this function tests whether the given flag is recognized by the libclang used by bindgen. ++bindgen-backend-option = $(success,$(BINDGEN) /dev/null -- -x c --target=$(BINDGEN_TARGET) $(1)) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux-lts-kmhv2/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch deleted file mode 100644 index 47458b4dd9..0000000000 --- a/SPECS/linux-lts-kmhv2/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch +++ /dev/null @@ -1,677 +0,0 @@ -From efed87f8a357dd6937ae5011627de96daf2e7029 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 11 Nov 2025 17:03:37 +0800 -Subject: [RUYI PATCH] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device tree - files - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add gpio-ranges property to all gpio/portX nodes. -This property maps GPIO lines to pin controller pins, -ensuring proper GPIO pin allocation and management. - -Convert dp1000.dts to a common include file (dp1000.dtsi) and update -the board-specific DTS files to include it. This refactoring allows -for better code reuse across different DP1000-based boards (EVB, MO, -and Titan variants) while maintaining board-specific configurations. - -The changes include: -- Renaming dp1000.dts to dp1000.dtsi -- Updating board-specific DTS files to include the common .dtsi -- Adjusting Makefile to reflect these changes -- Updating pinctrl files for all board variants - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 - - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - - .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + - 6 files changed, 263 insertions(+), 277 deletions(-) - rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 9eac56549340..22c03b44b2f8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,4 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index e82fcf2901ab..e2c09d5bdb20 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34d024a083fc..46fe457b5f52 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -index e82fcf2901ab..85b013f66bbd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index 8c532e5b71a3..dc057cbaf59b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-mo-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -similarity index 96% -rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts -rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 128293c0af1f..a25e87e15553 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { - clocks = <&device_clk>; - }; - -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ }; -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -@@ -349,6 +360,7 @@ porta: gpio-port@0 { - #interrupt-cells = <2>; - interrupt-parent = <0x01>; - interrupts = <34>; -+ gpio-ranges = <&pmx0 0 0 16>; - }; - - portb: gpio-port@1 { -@@ -357,6 +369,7 @@ portb: gpio-port@1 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 16 0 8>; - }; - - portc: gpio-port@2 { -@@ -365,6 +378,7 @@ portc: gpio-port@2 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 24 0 8>; - }; - - portd: gpio-port@3 { -@@ -373,6 +387,7 @@ portd: gpio-port@3 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 32 0 8>; - }; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0456-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux-lts-kmhv2/0456-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch new file mode 100644 index 0000000000..5116c4be0a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0456-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch @@ -0,0 +1,183 @@ +From be97e5642f9d000785f845323dce45e5fc583bf8 Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:57 +0100 +Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, + re-enable gcc + rust builds + +Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC ++ Rust builds for RISC-V due to differences in extension handling +compared to LLVM. This commit enables GCC + Rust builds again. + +Add `bindgen-option` conditions for the availability of libclang to the +RISC-V extension Kconfig symbols that depend on the `cc-option` +function. + +For Zicsr/Zifencei special handling, since LLVM/Clang always enables +these two extensions, either don't pass them to `-march`, or pass them +explicitly and Rust bindgen libclang must recognize them. + +Clang does not support `-mno-riscv-attribute` flag, filter it out to +resolve error: unknown argument: '-mno-riscv-attribute'. + +Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen +libclang for RISC-V to resolve error: unsupported argument 'medany' to +option '-mcmodel=' for target 'unknown'. + +Update the documentation, GCC + Rust builds for RISC-V are now +maintained. + +Acked-by: Miguel Ojeda +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + Documentation/rust/arch-support.rst | 2 +- + arch/riscv/Kconfig | 35 ++++++++++++++++++++++++++++- + rust/Makefile | 3 ++- + scripts/Makefile.rust | 1 + + 4 files changed, 38 insertions(+), 3 deletions(-) + +diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst +index 6e6a515d0899..5282e0e174e8 100644 +--- a/Documentation/rust/arch-support.rst ++++ b/Documentation/rust/arch-support.rst +@@ -18,7 +18,7 @@ Architecture Level of support Constraints + ``arm`` Maintained ARMv7 Little Endian only. + ``arm64`` Maintained Little Endian only. + ``loongarch`` Maintained \- +-``riscv`` Maintained ``riscv64`` and LLVM/Clang only. ++``riscv`` Maintained ``riscv64`` only. + ``um`` Maintained \- + ``x86`` Maintained ``x86_64`` only. + ============= ================ ============================================== +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 12bebdbaaf9f..36112b662884 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -196,7 +196,7 @@ config RISCV + select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_RETHOOK if !XIP_KERNEL + select HAVE_RSEQ +- select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG ++ select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI + select HAVE_SAMPLE_FTRACE_DIRECT + select HAVE_SAMPLE_FTRACE_DIRECT_MULTI + select HAVE_STACKPROTECTOR +@@ -620,6 +620,8 @@ config TOOLCHAIN_HAS_V + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv) + depends on LD_IS_LLD || LD_VERSION >= 23800 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64imv) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32imv) + + config RISCV_ISA_V + bool "Vector extension support" +@@ -684,6 +686,8 @@ config TOOLCHAIN_HAS_ZABHA + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha) + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zabha) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zabha) + + config RISCV_ISA_ZABHA + bool "Zabha extension support for atomic byte/halfword operations" +@@ -702,6 +706,8 @@ config TOOLCHAIN_HAS_ZACAS + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas) + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zacas) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zacas) + + config RISCV_ISA_ZACAS + bool "Zacas extension support for atomic CAS" +@@ -720,6 +726,8 @@ config TOOLCHAIN_HAS_ZBB + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbb) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbb) + + # This symbol indicates that the toolchain supports all v1.0 vector crypto + # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once. +@@ -735,6 +743,8 @@ config TOOLCHAIN_HAS_ZBA + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zba) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zba) + + config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" +@@ -770,6 +780,8 @@ config TOOLCHAIN_HAS_ZBC + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbc) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbc) + + config RISCV_ISA_ZBC + bool "Zbc extension support for carry-less multiplication instructions" +@@ -793,6 +805,8 @@ config TOOLCHAIN_HAS_ZBKB + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbkb) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbkb) + + config RISCV_ISA_ZBKB + bool "Zbkb extension support for bit manipulation instructions" +@@ -880,6 +894,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC + versions of clang and GCC to be passed to GAS, which has the same result + as passing zicsr and zifencei to -march. + ++config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI ++ def_bool y ++ depends on !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zicsr_zifencei) ++ depends on !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zicsr_zifencei) ++ ++config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI ++ def_bool y ++ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 ++ depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI ++ help ++ LLVM/Clang >= 17.0.0 starts recognizing Zicsr/Zifencei in -march, passing ++ them to -march doesn't generate an error anymore, and passing them or not ++ doesn't have any real difference, it still follows ISA before version ++ 20190608 - Zicsr/Zifencei are included in base ISA. ++ ++ The current latest version of LLVM/Clang still does not require explicit ++ Zicsr/Zifencei to enable these two extensions, Clang just accepts them in ++ -march and then silently ignores them. ++ + config FPU + bool "FPU support" + default y +diff --git a/rust/Makefile b/rust/Makefile +index 6d2d542a55e8..046492426017 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -298,7 +298,8 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fno-inline-functions-called-once -fsanitize=bounds-strict \ + -fstrict-flex-arrays=% -fmin-function-alignment=% \ + -fzero-init-padding-bits=% -mno-fdpic \ +- --param=% --param asan-% -fno-isolate-erroneous-paths-dereference ++ --param=% --param asan-% -fno-isolate-erroneous-paths-dereference \ ++ -mno-riscv-attribute + + # Because scripts/Makefile.rust is included regardless of whether Rust is enabled, + # we perform this check here to avoid breaking targets that do not yet support Rust builds. +diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust +index 5c12b4b8c8b6..bfdad4a0a3ce 100644 +--- a/scripts/Makefile.rust ++++ b/scripts/Makefile.rust +@@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 := x86_64-linux-gnu + BINDGEN_TARGET_arm64 := aarch64-linux-gnu + BINDGEN_TARGET_arm := arm-linux-gnueabi + BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf ++BINDGEN_TARGET_riscv := riscv64-linux-gnu + BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) + BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux-lts-kmhv2/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch deleted file mode 100644 index ebf2263e4c..0000000000 --- a/SPECS/linux-lts-kmhv2/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch +++ /dev/null @@ -1,166 +0,0 @@ -From bae8242b84b2c9409608fced96e355aa782dfcd8 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Wed, 12 Nov 2025 15:43:27 +0800 -Subject: [RUYI PATCH] RVCK: riscv: pinctrl: ultrarisc: Implement pin - configuration support - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Update ur_pin_config_set() to use the new configuration handling logic. -This allows the driver to properly handle standard Linux kernel pin -configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, -PIN_CONFIG_BIAS_PULL_DOWN, etc. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- - 3 files changed, 77 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 217f671fe63a..6a7496a465d8 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { - .pins = ur_dp1000_pins, - .npins = ARRAY_SIZE(ur_dp1000_pins), - .offset = 0x2c0, -+ .num_ports = 5, - .ports = { - {"A", 16, 0x2c0, 0x310}, - {"B", 8, 0x2c4, 0x318}, -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index 667d59e0ac6e..edaeca881af7 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { - - #define UR_CONF_BIT_PER_PIN (4) - #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+ -+static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, -+ struct ur_pin_val *pin_val, u32 pin_num) -+{ -+ const struct ur_port_desc *port_desc; -+ -+ for (int i = 0; i < match_data->num_ports; i++) { -+ port_desc = &match_data->ports[i]; -+ if (pin_num < port_desc->npins) { -+ pin_val->port = i; -+ pin_val->pin = pin_num; -+ pin_val->conf = 0; -+ return 0; -+ } -+ pin_num -= port_desc->npins; -+ } -+ return -EINVAL; -+} -+ -+static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, -+ struct ur_pin_val *pin_vals, -+ unsigned long *config) -+{ -+ enum pin_config_param param = pinconf_to_config_param(*config); -+ u32 arg = pinconf_to_config_argument(*config); -+ -+ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", -+ __func__, __LINE__, param, arg); -+ -+ switch (param) { -+ case PIN_CONFIG_BIAS_DISABLE: -+ pin_vals->conf &= ~UR_BIAS_MASK; -+ break; -+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: -+ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); -+ break; -+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: -+ case PIN_CONFIG_BIAS_PULL_DOWN: -+ pin_vals->conf |= UR_PULL_DOWN; -+ break; -+ case PIN_CONFIG_BIAS_PULL_UP: -+ pin_vals->conf |= UR_PULL_UP; -+ break; -+ case PIN_CONFIG_DRIVE_PUSH_PULL: -+ case PIN_CONFIG_PERSIST_STATE: -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ return 0; -+} -+ - static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) - { - const struct ur_port_desc *port_desc; -@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v - u32 val, conf; - - port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", -+ pin_vals->port, pin_vals->pin, pin_vals->conf); - reg = pin_ctrl->base + port_desc->conf_offset; -- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", -+ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); - reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; - dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); - -@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, - unsigned long *configs, - unsigned int num_configs) - { -- struct ur_pin_val *pin_conf; -+ struct ur_pin_val pin_val; - struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ int ret; -+ -+ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid pin number %d\n", pin); -+ return ret; -+ } -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", -+ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); - -- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -- __func__, __LINE__, pin, num_configs); -- pin_conf = (struct ur_pin_val *)configs; - for (int i = 0; i < num_configs; i++) { -- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", -+ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_val); - } - return 0; - } -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -index eec621bf8b05..728b2111def0 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - u32 npins; - u32 offset; -- //u32 conf_offset[]; -+ u32 num_ports; - struct ur_port_desc ports[]; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0457-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux-lts-kmhv2/0457-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch new file mode 100644 index 0000000000..3f84a1dedd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0457-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch @@ -0,0 +1,45 @@ +From 9d4f7807566149c7cd345ebd0bf77f93a630d667 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 16:38:54 +0800 +Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as + dependencies + +REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on +MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' +does not always respect the parent's dependencies, so 'depends on' +is the safer and more correct choice. + +Since MFD_SPACEMIT_P1 already depends on I2C_K1, the dependency +in REGULATOR_SPACEMIT_P1 is now redundant. + +Additionally, the default value depends on MFD_SPACEMIT_P1 rather +than ARCH_SPACEMIT. + +Acked-by: Mark Brown +Acked-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-1-6fe19f460269@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/regulator/Kconfig | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig +index d84f3d054c59..3701d0fe3e06 100644 +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1455,9 +1455,8 @@ config REGULATOR_SLG51000 + config REGULATOR_SPACEMIT_P1 + tristate "SpacemiT P1 regulators" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on I2C +- select MFD_SPACEMIT_P1 +- default ARCH_SPACEMIT ++ depends on MFD_SPACEMIT_P1 ++ default m if MFD_SPACEMIT_P1 + help + Enable support for regulators implemented by the SpacemiT P1 + power controller. The P1 implements 6 high-efficiency buck +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux-lts-kmhv2/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch deleted file mode 100644 index ca0081cabf..0000000000 --- a/SPECS/linux-lts-kmhv2/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch +++ /dev/null @@ -1,364 +0,0 @@ -From 90a72c61206582a7f4df5b88119e6602cbafc201 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 18 Nov 2025 13:48:49 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V Titan - board based on UltraRISC DP1000 SoC - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan -board. The Titan board is designed by Milk-V and is based on the UltraRISC -DP1000 SoC. These device tree files provide the initial support for the -board, including pinctrl and basic peripheral configuration. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 + - .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ - 3 files changed, 313 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 22c03b44b2f8..df8efe1a3ed7 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -new file mode 100644 -index 000000000000..35429e539832 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart3_pins: uart3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 6 UR_FUNC0 -+ UR_DP1000_IOMUX_C 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ UR_DP1000_IOMUX_A 4 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ gpios_pin: gpios_pin { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF -+ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -new file mode 100644 -index 000000000000..2cbdfa2ad813 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000-titan-pinctrl.dtsi" -+#include -+#include -+#include -+#include -+ -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&portb 0 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "power-off"; -+ status = "okay"; -+ }; -+ -+ gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&portb 1 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "reset-system"; -+ status = "okay"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ key-wakeup { -+ label = "Wake-Up"; -+ gpios = <&porta 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ linux,input-type = ; -+ debounce-interval = <10>; -+ wakeup-source; -+ wakeup-event-action = ; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@68 { -+ compatible = "st,m41t11"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+}; -+ -+&porta { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpios_pin>; -+ -+ i2c1-mux-hog { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ /* LOW: DCDC(U6) connect MCU(EC) -+ * HIGH: DCDC(U6) connect CPU -+ */ -+ output-low; -+ line-name = "gpio-mux-dcdc"; -+ }; -+ -+ i2c3-mux-hog { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_LOW>; -+ /* LOW: CPU i2c3 connect nvme -+ * HIGH: CPU i2c3 connect pciex16 -+ */ -+ output-low; -+ line-name = "gpio-mux-i2c3"; -+ }; -+ -+ uart0-mux-hog { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ /* LOW: uart_debug connect BMC -+ * HIGH: uart_debug connect CPU -+ */ -+ output-high; -+ line-name = "gpio-mux-debug"; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0458-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux-lts-kmhv2/0458-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch new file mode 100644 index 0000000000..559cbb12bc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0458-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch @@ -0,0 +1,37 @@ +From 51a4c9295dc51a46adb40ccb9cdbc7934f3ae495 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 16:38:56 +0800 +Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when + MFD_SPACEMIT_P1 is enabled + +The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which +caused it to be built-in automatically whenever the PMIC support was +set to y. + +This is not always desirable, as the RTC function is not required on +all platforms using the SpacemiT P1 PMIC. + +Acked-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-3-6fe19f460269@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/rtc/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index b392e6d096ed..4fc77f6b8a72 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -410,7 +410,7 @@ config RTC_DRV_SPACEMIT_P1 + tristate "SpacemiT P1 RTC" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on MFD_SPACEMIT_P1 +- default MFD_SPACEMIT_P1 ++ default m if MFD_SPACEMIT_P1 + help + Enable support for the RTC function in the SpacemiT P1 PMIC. + This driver can also be built as a module, which will be called +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux-lts-kmhv2/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch deleted file mode 100644 index 7b6568d84b..0000000000 --- a/SPECS/linux-lts-kmhv2/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch +++ /dev/null @@ -1,77 +0,0 @@ -From ad2ca89827235515c3cfea8822ac22544a6f79f1 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 23 Feb 2026 14:35:29 +0800 -Subject: [RUYI PATCH] REVYSR: pinctrl: ultrarisc: cleanup probe&remove - -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- - 2 files changed, 3 insertions(+), 20 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 6a7496a465d8..0ead138c9d1f 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { - .of_match_table = ur_pinctrl_of_match, - }, - .probe = ur_pinctrl_probe, -- .remove = ur_pinctrl_remove, - }; - - module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index edaeca881af7..cdd7160f3183 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); - if (!ur_pinctrl) { - dev_err(&pdev->dev, "pinctrl alloc failed\n"); -- ret = -ENOMEM; -- goto free_pinctrl_desc; -+ return -ENOMEM; - } - struct resource *res; - -@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ur_pinctrl->base)) { - dev_err(&pdev->dev, "get ioremap resource failed\n"); -- ret = -EINVAL; -- goto free_pinctrl_desc; -+ return -EINVAL; - } - dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); - ur_pinctrl_desc->name = dev_name(&pdev->dev); -@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl, &ur_pinctrl->pctl_dev); - if (ret) { - dev_err(&pdev->dev, "pinctrl register failed\n"); -- goto free_pinctrl; -+ return ret; - } - - platform_set_drvdata(pdev, ur_pinctrl); - - return pinctrl_enable(ur_pinctrl->pctl_dev); -- --free_pinctrl: -- devm_kfree(&pdev->dev, ur_pinctrl); --free_pinctrl_desc: -- devm_kfree(&pdev->dev, ur_pinctrl_desc); -- return ret; - } - -- --void ur_pinctrl_remove(struct platform_device *pdev) --{ -- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -- -- if (ur_pinctrl->pctl_dev) -- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); --} --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0459-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux-lts-kmhv2/0459-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch new file mode 100644 index 0000000000..e92cce8ec3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0459-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch @@ -0,0 +1,57 @@ +From fe76dddf31c17cfb0bcb998537c23161cc793091 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 17:24:21 +0800 +Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after + unmapping DMA + +In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA +before calling kfree() to deallocate the memory, instead of the other +way around. + +Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC") +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-4-0ab0122fdd14@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index 359b409f8203..48c80c075fdf 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -463,12 +463,12 @@ static void emac_free_tx_resources(struct emac_priv *priv) + + emac_clean_tx_desc_ring(priv); + +- kfree(tr->tx_desc_buf); +- tr->tx_desc_buf = NULL; +- + dma_free_coherent(dev, tr->total_size, tr->desc_addr, + tr->desc_dma_addr); + tr->desc_addr = NULL; ++ ++ kfree(tr->tx_desc_buf); ++ tr->tx_desc_buf = NULL; + } + + static void emac_free_rx_resources(struct emac_priv *priv) +@@ -478,12 +478,12 @@ static void emac_free_rx_resources(struct emac_priv *priv) + + emac_clean_rx_desc_ring(priv); + +- kfree(rr->rx_desc_buf); +- rr->rx_desc_buf = NULL; +- + dma_free_coherent(dev, rr->total_size, rr->desc_addr, + rr->desc_dma_addr); + rr->desc_addr = NULL; ++ ++ kfree(rr->rx_desc_buf); ++ rr->rx_desc_buf = NULL; + } + + static int emac_tx_clean_desc(struct emac_priv *priv) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux-lts-kmhv2/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch deleted file mode 100644 index 3ab0a8fab6..0000000000 --- a/SPECS/linux-lts-kmhv2/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 3a0ec292f418c3f0ec2630531aeab29eea263f22 Mon Sep 17 00:00:00 2001 -From: U2FsdGVkX1 -Date: Sun, 29 Mar 2026 15:31:14 +0000 -Subject: [RUYI PATCH] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie - for PCIe nodes - -Signed-off-by: U2FsdGVkX1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index a25e87e15553..78e0cda1fcb9 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { - }; - - pcie_x16: pcie@21000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { - }; - - pcie_x4a: pcie@23000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { - }; - - pcie_x4b: pcie@24000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0460-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux-lts-kmhv2/0460-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch new file mode 100644 index 0000000000..ed21dc9f9a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0460-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch @@ -0,0 +1,33 @@ +From 489d0a8540aa197ecba524f862ae9a022e756ad2 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Fri, 26 Jun 2026 16:10:23 +0800 +Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to + the allowlist + +Add the compatible string for supporting the generic +cpufreq driver on the SpacemiT K1 SoC. + +Signed-off-by: Shuwei Wu +Tested-by: Gong Shuai # OrangePi-RV2 +Link: https://lore.kernel.org/r/20260626-shadow-deps-v4-1-bba9831f2f1d@mailbox.org +Signed-off-by: Han Gao +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index 47dd76acd31e..8d37426273df 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -81,6 +81,8 @@ static const struct of_device_id allowlist[] __initconst = { + { .have_governor_per_policy = true, }, + }, + ++ { .compatible = "spacemit,k1", }, ++ + { .compatible = "st-ericsson,u8500", }, + { .compatible = "st-ericsson,u8540", }, + { .compatible = "st-ericsson,u9500", }, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux-lts-kmhv2/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch deleted file mode 100644 index 732de29759..0000000000 --- a/SPECS/linux-lts-kmhv2/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch +++ /dev/null @@ -1,450 +0,0 @@ -From 3091a1fa3451d492041d5cc22aeb46f67edaf469 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 13 Feb 2025 15:50:12 +0800 -Subject: [RUYI PATCH] ULTRARISC: hwmon: add corepvt driver of UltraRISC DP1000 - -From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 - -UltraRISC Corepvt driver supports cluster voltage -and core temperature detection - -Signed-off-by: Jia Wang -Signed-off-by: Han Gao ---- - drivers/hwmon/Kconfig | 9 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ - 3 files changed, 400 insertions(+) - create mode 100644 drivers/hwmon/corepvt-ultrarisc.c - -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 2a71b6e834b0..2a44030c7796 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 - To compile this driver as a module, choose M here: the module - will be called chipcap2. - -+config SENSORS_COREPVT_ULTRARISC -+ tristate "UltraRISC Core Voltage, Temperature sensor driver" -+ help -+ If you say yes here you get support for UltraRISC Core PVT sensor -+ embedded into the SoC. -+ -+ This driver can also be built as a module. If so, the module will be -+ called corepvt-ultrarisc. -+ - config SENSORS_CORSAIR_CPRO - tristate "Corsair Commander Pro controller" - depends on HID -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 73b2abdcc6dd..6cf5fac80b7b 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o - obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o - obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o - obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o -+obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o - obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o - obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o - obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o -diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c -new file mode 100644 -index 000000000000..3674eedefbda ---- /dev/null -+++ b/drivers/hwmon/corepvt-ultrarisc.c -@@ -0,0 +1,390 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Driver for UltraRISC Core PVT -+ * -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define COREPVT_CHL_OFFSET 0x1000 -+#define COREPVT_REG_CIR 0x0 -+#define COREPVT_REG_PSCR 0x04 -+#define COREPVT_REG_CFDR 0x08 -+#define COREPVT_REG_DOR 0x0C -+#define COREPVT_REG_ICR 0x10 -+#define COREPVT_REG_IER 0x14 -+#define COREPVT_REG_IMSR 0x18 -+#define COREPVT_REG_IRSR 0x1C -+ -+#define PVT_MAX_CHANNEL 64 -+#define PVT_TRIM_DEFAULT 0x7 -+ -+struct corepvt_channel_config { -+ const char *label; -+ u32 trim; -+}; -+ -+struct corepvt_cal_data { -+ u32 val_offset; -+ u32 val_lsb; -+}; -+ -+struct corepvt_data { -+ const struct hwmon_chip_info *chip_info; -+ u64 temp_chl_mask; -+ u64 vol_chl_mask; -+}; -+ -+struct corepvt_hwmon { -+ struct device *dev; -+ struct device *hwmon; -+ -+ void __iomem *regs; -+ int irq; -+ int clk_freq; -+ int channels; -+ const struct hwmon_chip_info *chip_info; -+ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; -+ const struct corepvt_data *pvt_data; -+ raw_spinlock_t lock; -+}; -+ -+#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ -+#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ -+#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ -+#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ -+ -+static int corepvt_read_vol(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the voltage channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; -+ -+ return 0; -+} -+ -+static int corepvt_read_temp(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the temperature channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; -+ -+ return 0; -+} -+ -+static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct corepvt_hwmon *pvt = drvdata; -+ -+ if (channel >= pvt->channels) -+ return 0; -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ case hwmon_in_label: -+ return 0444; -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_type: -+ case hwmon_temp_label: -+ return 0444; -+ } -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ return corepvt_read_vol(pvt, channel, val); -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_type: -+ *val = 1; -+ return 0; -+ case hwmon_temp_input: -+ return corepvt_read_temp(pvt, channel, val); -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return -ENODATA; -+} -+ -+static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, const char **str) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ u32 chl_offset = 0; -+ -+ switch (type) { -+ case hwmon_in: -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ break; -+ case hwmon_temp: -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ break; -+ default: -+ return -ENODATA; -+ break; -+ } -+ -+ *str = pvt->config[channel + chl_offset].label; -+ -+ return 0; -+} -+ -+/* -+ * corepvt init process: -+ * 1. config SETUP time, should be 10us, set PSCR register -+ * 2. config CLKIN, should be 4MHz, set CFDR register -+ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR -+ * 4. config TRIM and enable PVT, set CIR -+ */ -+static int corepvt_init(struct corepvt_hwmon *pvt) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ /* -+ * SETUP time 10us = 100KHz -+ * PSCR = CLK_FREQ / 100KHz -+ */ -+ u32 pscr_val = pvt->clk_freq / 100000; -+ /* -+ * CFDR = CLK_FREQ / 4MHz / 2 -+ */ -+ u32 cfdr_val = pvt->clk_freq / 8000000; -+ /* -+ * CIR: -+ * bit[0]: PU_VTDC, set 1 to enable pvt -+ * bit[5:2]: TRIM -+ */ -+ u32 cir_val; -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ for (int i = 0; i < pvt->channels; i++) { -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; -+ cir_val = (pvt->config[i].trim << 2) | 0x01; -+ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); -+ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); -+ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); -+ } -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ return 0; -+} -+ -+static const struct hwmon_ops corepvt_hwmon_ops = { -+ .is_visible = corepvt_is_visible, -+ .read = corepvt_read, -+ .read_string = corepvt_read_string, -+}; -+ -+static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) -+{ -+ struct device_node *child; -+ int ret; -+ u32 channel; -+ const char *label; -+ u32 trim; -+ -+ for_each_child_of_node(pdev->dev.of_node, child) { -+ if (!of_node_name_eq(child, "channel")) -+ continue; -+ -+ ret = of_property_read_u32(child, "reg", &channel); -+ if (ret) -+ goto node_put; -+ -+ ret = of_property_read_string(child, "label", &label); -+ if (ret) -+ goto node_put; -+ -+ if (of_property_present(child, "trim")) -+ of_property_read_u32(child, "trim", &trim); -+ else -+ trim = PVT_TRIM_DEFAULT; -+ -+ pvt->config[channel].label = label; -+ pvt->config[channel].trim = trim; -+ } -+ -+ return 0; -+ -+node_put: -+ of_node_put(child); -+ return ret; -+} -+ -+static int corepvt_probe(struct platform_device *pdev) -+{ -+ struct corepvt_hwmon *pvt; -+ const struct corepvt_data *pvt_data; -+ int ret; -+ -+ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); -+ if (!pvt) -+ return -ENOMEM; -+ -+ pvt->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(pvt->regs)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ if (device_property_present(&pdev->dev, "interrupts")) -+ pvt->irq = platform_get_irq(pdev, 0); -+ -+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); -+ if (ret) { -+ dev_err(&pdev->dev, "get clock-frequency failed\n"); -+ goto free_pvt; -+ } -+ -+ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); -+ if (ret) { -+ dev_err(&pdev->dev, "get channels failed\n"); -+ goto free_pvt; -+ } -+ -+ pvt_data = device_get_match_data(&pdev->dev); -+ if (!pvt_data) { -+ dev_err(&pdev->dev, "No chip info found\n"); -+ ret = -ENODATA; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ pvt->chip_info = pvt_data->chip_info; -+ pvt->pvt_data = pvt_data; -+ -+ if (pdev->dev.of_node) { -+ ret = corepvt_probe_channel_from_dt(pdev, pvt); -+ if (ret) -+ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); -+ } -+ -+ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", -+ pvt, pvt->chip_info, -+ NULL); -+ if (IS_ERR(pvt->hwmon)) { -+ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ raw_spin_lock_init(&pvt->lock); -+ -+ // Config and enable corepvt -+ corepvt_init(pvt); -+ -+ return 0; -+ -+free_pvt: -+ devm_kfree(&pdev->dev, pvt); -+ return ret; -+} -+ -+static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL), -+ HWMON_CHANNEL_INFO(in, -+ HWMON_I_INPUT | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_LABEL), -+ NULL -+}; -+ -+static const struct hwmon_chip_info ur_dp1000_chip_info = { -+ .ops = &corepvt_hwmon_ops, -+ .info = ur_dp1000_channel_info, -+}; -+ -+static struct corepvt_data ur_dp1000_pvt_data = { -+ .chip_info = &ur_dp1000_chip_info, -+ .temp_chl_mask = GENMASK_ULL(10, 0), -+ .vol_chl_mask = GENMASK_ULL(12, 11) -+}; -+ -+static const struct of_device_id corepvt_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, corepvt_of_match); -+ -+static struct platform_driver corepvt_driver = { -+ .probe = corepvt_probe, -+ .driver = { -+ .name = "corepvt-ultrarisc", -+ .of_match_table = corepvt_of_match -+ } -+}; -+module_platform_driver(corepvt_driver); -+ -+MODULE_AUTHOR("Jia Wang "); -+MODULE_DESCRIPTION("corepvt-ultrarisc driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0461-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux-lts-kmhv2/0461-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch new file mode 100644 index 0000000000..11317035e7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0461-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch @@ -0,0 +1,267 @@ +From a6cef789e1aadc2510ae9cb9c4417da34582a866 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Fri, 26 Jun 2026 16:10:24 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 + SoC + +Add CPU clock properties and OPP tables for the two CPU clusters in the +SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU +supply is shared by both clusters. + +Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and +wiring the CPU nodes to the CPU regulator supply. + +Signed-off-by: Shuwei Wu +Tested-by: Andre Heider # k1-musepi-pro +Tested-by: Gong Shuai # OrangePi-RV2 +Link: https://lore.kernel.org/r/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- + arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ + 3 files changed, 147 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 72f77e9edd63..307a7e4a8943 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -4,6 +4,7 @@ + */ + + #include "k1.dtsi" ++#include "k1-opp.dtsi" + #include "k1-pinctrl.dtsi" + + / { +@@ -87,6 +88,38 @@ &combo_phy { + status = "okay"; + }; + ++&cpu_0 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_1 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_2 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_3 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_4 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_5 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_6 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_7 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ + &emmc { + bus-width = <8>; + mmc-hs400-1_8v; +@@ -202,7 +235,7 @@ pmic@41 { + dldoin2-supply = <&buck5>; + + regulators { +- buck1 { ++ buck1_0v9: buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi +new file mode 100644 +index 000000000000..4cebfcd87485 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/ { ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-614400000 { ++ opp-hz = /bits/ 64 <614400000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-819000000 { ++ opp-hz = /bits/ 64 <819000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1228800000 { ++ opp-hz = /bits/ 64 <1228800000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1600000000 { ++ opp-hz = /bits/ 64 <1600000000>; ++ opp-microvolt = <1050000 1050000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-614400000 { ++ opp-hz = /bits/ 64 <614400000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-819000000 { ++ opp-hz = /bits/ 64 <819000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1228800000 { ++ opp-hz = /bits/ 64 <1228800000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1600000000 { ++ opp-hz = /bits/ 64 <1600000000>; ++ opp-microvolt = <1050000 1050000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++}; ++ ++&cpu_0 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_1 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_2 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_3 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_4 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_5 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_6 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_7 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 08a0f28d011f..4a359190f633 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -54,6 +54,7 @@ cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -84,6 +85,7 @@ cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -114,6 +116,7 @@ cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -144,6 +147,7 @@ cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -174,6 +178,7 @@ cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -204,6 +209,7 @@ cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -234,6 +240,7 @@ cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -264,6 +271,7 @@ cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux-lts-kmhv2/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch deleted file mode 100644 index 0582b1d016..0000000000 --- a/SPECS/linux-lts-kmhv2/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +++ /dev/null @@ -1,732 +0,0 @@ -From 817a4331068207be97f31dbe87e3512e92b549de Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 12 Apr 2026 02:50:03 +0800 -Subject: [RUYI PATCH] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi - -FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- - 1 file changed, 489 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 78e0cda1fcb9..7b7016618dcd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -22,121 +22,491 @@ cpu0: cpu@0 { - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache0>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu0_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache0: l2-cache0 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu1: cpu@1 { - device_type = "cpu"; - reg = <0x1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache1>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu1_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache1: l2-cache1 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu2: cpu@2 { - device_type = "cpu"; - reg = <0x2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache2>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu2_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache2: l2-cache2 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu3: cpu@3 { - device_type = "cpu"; - reg = <0x3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache3>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu3_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache3: l2-cache3 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu4: cpu@4 { - device_type = "cpu"; - reg = <0x10>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache4>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu4_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache4: l2-cache4 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu5: cpu@5 { - device_type = "cpu"; - reg = <0x11>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache5>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu5_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache5: l2-cache5 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu6: cpu@6 { - device_type = "cpu"; - reg = <0x12>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; -- - clock-frequency = <2000000000>; -- -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache6>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu6_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache6: l2-cache6 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu7: cpu@7 { - device_type = "cpu"; - reg = <0x13>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache7>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu7_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache7: l2-cache7 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; -+ }; -+ -+ cpu-map { -+ cluster0: cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ core2 { -+ cpu = <&cpu2>; -+ }; -+ core3 { -+ cpu = <&cpu3>; -+ }; -+ -+ cluster0_l3: l3-cache0 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; -+ -+ cluster1: cluster1 { -+ core0 { -+ cpu = <&cpu4>; -+ }; -+ core1 { -+ cpu = <&cpu5>; -+ }; -+ core2 { -+ cpu = <&cpu6>; -+ }; -+ core3 { -+ cpu = <&cpu7>; -+ }; -+ cluster1_l3: l3-cache1 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; - }; - }; - -@@ -150,6 +520,20 @@ soc { - #size-cells = <0x02>; - compatible = "simple-bus"; - ranges; -+ -+ l4_cache: l4-cache { -+ /* L4 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 16MB -+ * shared by the SoC. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <4>; -+ cache-size = <0x1000000>; -+ cache-sets = <0x4000>; -+ cache-unified; -+ }; - - clocks { - compatible = "simple-bus"; -@@ -160,6 +544,12 @@ device_clk: device_clk { - #clock-cells = <0>; - }; - -+ timer_clk: timer_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+ #clock-cells = <0>; -+ }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -170,35 +560,102 @@ csr_clk: csr_clk { - clint: clint@8000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; - reg = <0x00 0x8000000 0x00 0x100000>; - }; -- -+ - plic: plic@9000000 { - #interrupt-cells = <1>; - #address-cells = <0>; -- phandle = <0x01>; -- compatible = "ultrarisc,dp1000-plic"; -+ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; - interrupt-controller; - interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; - reg = <0x00 0x9000000 0x00 0x4000000>; - riscv,max-priority = <0x07>; - riscv,ndev = <160>; - }; -- -+ -+ core_pvt: pvt@110D0000 { -+ compatible = "ultrarisc,dp1000-pvt"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00 0x110D0000 0x00 0x0000D000>; -+ clock-frequency = <250000000>; -+ channels = <13>; -+ -+ #thermal-sensor-cells = <1>; -+ channel@0 { -+ label = "Core temp0"; -+ reg = <0>; -+ }; -+ -+ channel@1 { -+ label = "Core temp1"; -+ reg = <1>; -+ }; -+ -+ channel@2 { -+ label = "Core temp2"; -+ reg = <2>; -+ }; -+ -+ channel@3 { -+ label = "Core temp3"; -+ reg = <3>; -+ }; -+ -+ channel@4 { -+ label = "Core temp4"; -+ reg = <4>; -+ }; -+ -+ channel@5 { -+ label = "Core temp5"; -+ reg = <5>; -+ }; -+ channel@6 { -+ label = "Core temp6"; -+ reg = <6>; -+ }; -+ channel@7 { -+ label = "Core temp7"; -+ reg = <7>; -+ }; -+ channel@8 { -+ label = "Core temp8"; -+ reg = <8>; -+ }; -+ channel@9 { -+ label = "Core temp9"; -+ reg = <9>; -+ }; -+ channel@10 { -+ label = "Core temp10"; -+ reg = <10>; -+ }; -+ channel@11 { -+ label = "Cluster0 voltage"; -+ reg = <11>; -+ }; -+ channel@12 { -+ label = "Cluster1 voltage"; -+ reg = <12>; -+ }; -+ }; -+ - uart0: serial@20300000 { - interrupt-parent = <0x01>; - interrupts = <17>; -@@ -244,7 +701,7 @@ uart3: serial@20410000 { - }; - - spi0: spi@20320000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -258,7 +715,7 @@ spi0: spi@20320000 { - }; - - spi1: spi@20420000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { - num-lanes = <16>; - ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -- max-link-speed = <4>; -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <16>; - interrupt-parent = <&plic>; -- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, - <0x0 0x0 0x0 0x2 &plic 45>, -@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <63>, <64>, <65>, <66>, <67>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, - <0x0 0x0 0x0 0x2 &plic 65>, -@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <73>, <74>, <75>, <76>, <77>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, - <0x0 0x0 0x0 0x2 &plic 75>, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0462-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux-lts-kmhv2/0462-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch new file mode 100644 index 0000000000..2c733ae413 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0462-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch @@ -0,0 +1,84 @@ +From 4108a2c32f1c17beab2e4fef0cc9a3c8837300e7 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Tue, 17 Mar 2026 16:48:06 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other + CPUs before reboot/shutdown + +Currently, the RISC-V implementation of machine_restart(), machine_halt(), +and machine_power_off() invokes the kernel teardown chains (e.g., +do_kernel_restart()) with local interrupts enabled and other CPUs still +running. + +This implementation fails to provide a deterministic execution environment +for registered handlers in the restart or power-off notifier chains. These +chains are intended to be executed in a strict atomic and single-threaded +context. + +Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increment +the preempt_count. If local interrupts remain enabled, the environment +is not guaranteed to be atomic. This can lead to a context misidentification +within generic kernel teardown code, causing it to incorrectly enter +non-atomic paths (such as attempting to acquire sleeping locks), which +results in fatal "scheduling while atomic" splats or system hangs. + +Additionally, stopping other CPUs ensures the primary CPU has exclusive +access to the hardware state during the final teardown phase, preventing +unpredictable interference from other active cores. + +Align RISC-V with other major architectures by disabling local interrupts +and stopping other CPUs at the beginning of the shutdown sequences. This +guarantees the architectural expectations of the kernel's restart and +power-off handlers are met. + +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Link: https://lore.kernel.org/all/abEP80FoCn4S4-WG@aurel32.net/ [1] +Link: https://lore.kernel.org/r/20260317-v7-0-rc1-rv-dis-int-before-restart-v2-1-0ecc85fbb7ff@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/kernel/reset.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c +index 912288572226..8c48466c50e9 100644 +--- a/arch/riscv/kernel/reset.c ++++ b/arch/riscv/kernel/reset.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + + static void default_power_off(void) + { +@@ -17,18 +18,27 @@ EXPORT_SYMBOL(pm_power_off); + + void machine_restart(char *cmd) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_restart(cmd); + while (1); + } + + void machine_halt(void) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_power_off(); + default_power_off(); + } + + void machine_power_off(void) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_power_off(); + default_power_off(); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch deleted file mode 100644 index f7231a5dd3..0000000000 --- a/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 360a4acac1e14c683370c4ffa8f3e85733ca0207 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 24 Jan 2026 08:48:53 +0800 -Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support - -FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 - -The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub -which fully USB2.0 protocol compliant and provides 4 ports. - -Signed-off-by: Yixun Lan -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ - 2 files changed, 56 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 61cbf924830b..ac965ec83f2c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ aux_vcc3v3: regulator-aux-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - }; - - &i2c8 { -@@ -255,3 +264,19 @@ &uart0 { - pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -+ -+&usb2_host { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ vdd-supply = <&aux_vcc3v3>; -+ }; -+}; -+ -+&usb2_phy { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index ed046714a7ac..1b86c872accb 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb2_host: usb@c0a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, -+ <&syscon_apmu RESET_APMU_USB2_VCC>, -+ <&syscon_apmu RESET_APMU_USB2_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ dr_mode = "host"; -+ maximum-speed = "high-speed"; -+ status = "disabled"; -+ }; -+ -+ usb2_phy: phy@c0a20000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0xc0a20000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0463-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux-lts-kmhv2/0463-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch new file mode 100644 index 0000000000..6d5912b805 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0463-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch @@ -0,0 +1,39 @@ +From 7d7f234e12191d9c9ec0b097efa23976191b35d9 Mon Sep 17 00:00:00 2001 +From: Felix Gu +Date: Sat, 21 Mar 2026 03:12:10 +0800 +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on + dw_hdmi_probe() return value + +The error check after calling dw_hdmi_probe() was incorrectly checking +the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. + +Fix this by checking the correct variable. + +Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") +Signed-off-by: Felix Gu +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260321-th1520-v1-1-ec877197770d@gmail.com +Signed-off-by: Han Gao +--- + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +index 389eead5f1c4..c9968ec1823c 100644 +--- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -136,8 +136,8 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) + plat_data->priv_data = hdmi; + + hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); +- if (IS_ERR(hdmi)) +- return PTR_ERR(hdmi); ++ if (IS_ERR(hdmi->dw_hdmi)) ++ return PTR_ERR(hdmi->dw_hdmi); + + platform_set_drvdata(pdev, hdmi); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts-kmhv2/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch deleted file mode 100644 index 7871de10b3..0000000000 --- a/SPECS/linux-lts-kmhv2/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 8b65d5e0ae467754eccf77dddcd58ae11ea35cdd Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Mon, 5 Jan 2026 20:05:04 +0800 -Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is - not cacheable - -FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f - -Change-Id: I040d597ee246777767f7be747fa9202154524538 -[ Vivian: Rebase and move check into enter_vector_usercopy ] -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/uaccess.h | 5 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/riscv_v_helpers.c | 5 +++ - arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ - 4 files changed, 76 insertions(+) - create mode 100644 arch/riscv/lib/uaccess_cache_check.c - -diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h -index 6aef591a6bfc..b028208b05ec 100644 ---- a/arch/riscv/include/asm/uaccess.h -+++ b/arch/riscv/include/asm/uaccess.h -@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } - if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ - goto label; - -+/* Memory cacheability check for vector uaccess optimization */ -+#ifdef CONFIG_RISCV_ISA_V -+int is_cacheable_safe(const void *addr); -+#endif -+ - #else /* CONFIG_MMU */ - #include - #endif /* CONFIG_MMU */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 735d0b665536..43fe69db9803 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -14,6 +14,7 @@ endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) - lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o -+lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o - endif - lib-$(CONFIG_MMU) += uaccess.o - lib-$(CONFIG_64BIT) += tishift.o -diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c -index 7bbdfc6d4552..7ab2cea280f8 100644 ---- a/arch/riscv/lib/riscv_v_helpers.c -+++ b/arch/riscv/lib/riscv_v_helpers.c -@@ -8,6 +8,7 @@ - - #include - #include -+#include - - #ifdef CONFIG_MMU - #include -@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, - if (!may_use_simd()) - goto fallback; - -+ /* HACK */ -+ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) -+ goto fallback; -+ - kernel_vector_begin(); - remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : - __asm_vector_usercopy_sum_enabled(dst, src, n); -diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c -new file mode 100644 -index 000000000000..0b0996fa2d37 ---- /dev/null -+++ b/arch/riscv/lib/uaccess_cache_check.c -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Memory cacheability check for RISC-V uaccess optimization -+ * -+ * This file provides a C function that can be called from assembly -+ * to determine if a buffer is cacheable before using vector instructions. -+ */ -+ -+#include -+#include -+#include -+ -+/** -+ * is_cacheable_safe - Check if memory buffer is cacheable -+ * @addr: Virtual address to check (kernel or user space) -+ * -+ * Returns: 1 if cacheable, 0 if non-cacheable -+ * -+ * This function is designed to be called from assembly code in uaccess.S -+ * to determine if vector instructions are safe to use for memory copy. -+ * -+ * Non-cacheable memory (device IO, DMA coherent buffers) should not use -+ * vector instructions as they may cause cache coherency issues. -+ * -+ * Handles both kernel and user space addresses safely: -+ * - Kernel direct mapping: Always cacheable -+ * - Kernel vmalloc: Check VM flags -+ * - User space: Check page table (most are cacheable) -+ * - ioremap/DMA: Non-cacheable -+ */ -+int is_cacheable_safe(const void *addr) -+{ -+ unsigned long vaddr = (unsigned long)addr; -+ -+ /* Kernel direct mapped memory - always cacheable */ -+ if (virt_addr_valid(addr)) -+ return 1; -+ -+ if (vaddr < TASK_SIZE) { -+ /* -+ * User space address, Determine it as a cacheable buffer, -+ * maybe not safe!! -+ */ -+ return 1; -+ } -+ -+ /* Check if it's a vmalloc region (kernel virtual address) */ -+ if (is_vmalloc_addr(addr)) { -+ struct vm_struct *vm; -+ -+ vm = find_vm_area(addr); -+ if (!vm) -+ return 0; -+ -+ /* Exclude ioremap and DMA coherent buffers */ -+ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) -+ return 0; -+ -+ /* Normal vmalloc - cacheable */ -+ return 1; -+ } -+ -+ /* Unknown kernel region - assume non-cacheable for safety */ -+ return 0; -+} --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0464-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux-lts-kmhv2/0464-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch new file mode 100644 index 0000000000..d11395b288 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0464-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch @@ -0,0 +1,43 @@ +From b3a415a826bf0b3679416bd4c7dd0547fafe05df Mon Sep 17 00:00:00 2001 +From: Felix Gu +Date: Sat, 21 Mar 2026 03:12:11 +0800 +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() + callback + +This driver stores struct th1520_hdmi * in platform drvdata, but +th1520_dw_hdmi_remove() was reading it back as struct dw_hdmi * +and passing it to dw_hdmi_remove(), so teardown runs on the wrong +pointer. + +Retrieve struct th1520_hdmi * from platform drvdata and pass +hdmi->dw_hdmi to dw_hdmi_remove(). + +Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") +Signed-off-by: Felix Gu +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260321-th1520-v1-2-ec877197770d@gmail.com +Signed-off-by: Han Gao +--- + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +index c9968ec1823c..6ec9003a8f3f 100644 +--- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -146,9 +146,9 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) + + static void th1520_dw_hdmi_remove(struct platform_device *pdev) + { +- struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ struct th1520_hdmi *hdmi = platform_get_drvdata(pdev); + +- dw_hdmi_remove(hdmi); ++ dw_hdmi_remove(hdmi->dw_hdmi); + } + + static const struct of_device_id th1520_dw_hdmi_of_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux-lts-kmhv2/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch deleted file mode 100644 index 2a03ed4e12..0000000000 --- a/SPECS/linux-lts-kmhv2/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 675808049c603e6935816557a160a1d7f6eb5495 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:01:58 +0800 -Subject: [RUYI PATCH] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb - phy support - -The USB3/PCIe comb PHY on the K3 is a complex PHY group that -can provide multiple phy for both PCIe and USB controller. -Its mux configuration is controlled by the APMU syscon device. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -new file mode 100644 -index 000000000000..eafc753b7e9b ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 PCIE/USB3 Comb PHY -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ const: spacemit,k3-combo-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 2 -+ description: -+ The first one is phy id, the second one is phy type. -+ -+ spacemit,apb-spare: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Phandle to APB SPARE system controller interface, used for -+ PHY calibration. -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle of APMU syscon -+ - description: configuration of the PHY lanes -+ description: | -+ Phandle to control PHY mux configuration. The configuration -+ is described as follows: -+ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode -+ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode -+ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode -+ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode -+ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode -+ -+ The bit[3:0] is only valid when bit 4 is 1. -+ -+required: -+ - compatible -+ - reg -+ - "#phy-cells" -+ - spacemit,apb-spare -+ - spacemit,apmu -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x81d00000 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&apb_spare>; -+ spacemit,apmu = <&apmu 0x00>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0465-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux-lts-kmhv2/0465-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch new file mode 100644 index 0000000000..7178b45152 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0465-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch @@ -0,0 +1,83 @@ +From 71f06799692814cdd5d371b34e71bb4ad361c7bb Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Tue, 31 Mar 2026 15:37:22 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for + systems with DRAM above 4GB + +On RISC-V platforms where the entire physical memory (DRAM) resides +above the 32-bit address space (i.e., above dma32_phys_limit), the +current SWIOTLB initialization logic fails. + +This patch addresses two interconnected issues on such platforms: + +1. Incorrect 32-bit DMA bounce assumption: +The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes +that a 32-bit DMA bounce buffer is required simply because the maximum +PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, +no memory exists below the limit to satisfy this allocation. Fix +this by adding a check to ensure `memblock_start_of_DRAM()` is actually +below the 32-bit limit before enforcing 32-bit SWIOTLB. + +2. kmalloc() bounce buffer allocation failure on non-coherent systems: +For non-coherent hardware, a bounce buffer is still mandatory for +cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. +Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating +from low memory, which fails completely when DRAM only exists in high +memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is +permitted to allocate this alignment buffer from high memory. + +With this patch, systems with non-coherent DMA and DRAM entirely above +4GB can successfully map the software IO TLB in high memory and boot +normally. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260331-fix-riscv-swiotlb-v1-1-74dd5e6be0f1@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 6533cc17825a..ac5bece70736 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -172,7 +172,9 @@ static void print_vm_layout(void) { } + + void __init arch_mm_preinit(void) + { +- bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit); ++ bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) && ++ memblock_start_of_DRAM() < dma32_phys_limit; ++ unsigned int swiotlb_flags = SWIOTLB_VERBOSE; + #ifdef CONFIG_FLATMEM + BUG_ON(!mem_map); + #endif /* CONFIG_FLATMEM */ +@@ -180,17 +182,21 @@ void __init arch_mm_preinit(void) + if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb && + dma_cache_alignment != 1) { + /* +- * If no bouncing needed for ZONE_DMA, allocate 1MB swiotlb +- * buffer per 1GB of RAM for kmalloc() bouncing on +- * non-coherent platforms. ++ * No 32-bit DMA bouncing needed (either all DRAM is within ++ * the 32-bit limit, or it all starts above it), but ++ * non-coherent hardware still requires cache-line-aligned ++ * bounce buffers for kmalloc(). Use SWIOTLB_ANY so that the ++ * buffer can be allocated from high memory when DRAM starts ++ * above dma32_phys_limit. Allocate ~1 MB per 1 GB of RAM. + */ + unsigned long size = + DIV_ROUND_UP(memblock_phys_mem_size(), 1024); + swiotlb_adjust_size(min(swiotlb_size_or_default(), size)); + swiotlb = true; ++ swiotlb_flags |= SWIOTLB_ANY; + } + +- swiotlb_init(swiotlb, SWIOTLB_VERBOSE); ++ swiotlb_init(swiotlb, swiotlb_flags); + + print_vm_layout(); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux-lts-kmhv2/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch deleted file mode 100644 index 4c1686add5..0000000000 --- a/SPECS/linux-lts-kmhv2/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +++ /dev/null @@ -1,730 +0,0 @@ -From 4ee622c1f03b3a5e9d6df7f54f612202f9462d8c Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:09:58 +0800 -Subject: [RUYI PATCH] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver for - Spacemit K3 - -The comb PHY on K3 requires to configure a syscon device for the -right mux configuration. And it requires calibration before any -usage. - -Add USB3/PCIe comb PHY driver for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/Kconfig | 16 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.h | 27 ++ - 5 files changed, 669 insertions(+) - create mode 100644 drivers/phy/spacemit/phy-k3-combo.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.h - -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -index 0136aee2e8a2..9a1e25592f25 100644 ---- a/drivers/phy/spacemit/Kconfig -+++ b/drivers/phy/spacemit/Kconfig -@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 - help - Enable this to support K1 USB 2.0 PHY driver. This driver takes care of - enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -+ -+config PHY_SPACEMIT_K3_COMMON_OPS -+ tristate -+ select MFD_SYSCON -+ select GENERIC_PHY -+ -+config PHY_SPACEMIT_K3_COMBO_PHY -+ tristate "SpacemiT K3 USB3/PCIe PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ select PHY_SPACEMIT_K3_COMMON_OPS -+ help -+ Enable this to support K3 USB3/PCIe combo PHY driver. This -+ driver takes care of enabling and clock setup and will be used -+ by K3 dwc3 driver. -+ If unsure, say N. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -index fec0b425a948..df9b609d066f 100644 ---- a/drivers/phy/spacemit/Makefile -+++ b/drivers/phy/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o -diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c -new file mode 100644 -index 000000000000..abd0aad18893 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-combo.c -@@ -0,0 +1,252 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver -+ * -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* -+ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs -+ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. -+ * -+ * PMUA_PCIE_SUBSYS_MGMT[4:0] -+ * -+ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A -+ * 1 : PHY lanes shared between PCIe or USB according to [3:0] -+ * -+ * All PHY matrix combinations according to [4:0]: -+ * -+ * 0x0X : PCIe-A X8 -+ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) -+ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) -+ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) -+ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) -+ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) -+ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) -+ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * -+ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. -+ */ -+#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 -+#define PU_MATRIX_CONF_MASK GENMASK(4, 0) -+ -+#define COMBPHY_MAX_SUBPHYS 6 -+ -+struct k3_combo_phy { -+ struct device *dev; -+ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; -+ void __iomem *base; -+ struct regmap *apb_spare; -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x0, 0x400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x100000, 0x100400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { -+ .lanes = 1, -+ .config = 0x14, -+ .mask = 0x14, -+ .offsets = { -+ 0x200000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { -+ .lanes = 1, -+ .config = 0x12, -+ .mask = 0x12, -+ .offsets = { -+ 0x300000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { -+ .lanes = 1, -+ .config = 0x11, -+ .mask = 0x11, -+ .offsets = { -+ 0x400000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { -+ .lanes = 1, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x500000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { -+ &k3_combphy_lane_group0, -+ &k3_combphy_lane_group1, -+ &k3_combphy_lane_group2, -+ &k3_combphy_lane_group3, -+ &k3_combphy_lane_group4, -+ &k3_combphy_lane_group5, -+}; -+ -+static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { -+ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; -+ struct k3_lane_group *lg = &phy->groups[i]; -+ const struct phy_ops *ops; -+ bool is_usb; -+ -+ is_usb = (data->mask & config) == data->config; -+ if (is_usb) -+ ops = &k3_usb3_phy_ops; -+ else -+ ops = &k3_pcie_phy_ops; -+ -+ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); -+ -+ lg->phy = devm_phy_create(phy->dev, NULL, ops); -+ if (IS_ERR(lg->phy)) -+ return PTR_ERR(lg->phy); -+ -+ lg->is_pcie = !is_usb; -+ lg->data = data; -+ lg->base = phy->base; -+ phy_set_drvdata(lg->phy, lg); -+ } -+ -+ return 0; -+} -+ -+static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) -+{ -+ if (config & ~PU_MATRIX_CONF_MASK) -+ return -EINVAL; -+ -+ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); -+} -+ -+static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k3_combo_phy *phy = dev_get_drvdata(dev); -+ struct k3_lane_group *lg; -+ -+ if (args->args_count != 2) { -+ dev_err(dev, "Invalid number of arguments\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { -+ dev_err(dev, "Invalid PHY id\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ lg = &phy->groups[args->args[0]]; -+ -+ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || -+ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { -+ dev_err(dev, "Invalid PHY mode\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return lg->phy; -+} -+ -+static int k3_combo_phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct phy_provider *provider; -+ struct k3_combo_phy *phy; -+ struct regmap *apmu; -+ u32 config = 0; -+ int ret; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(phy->base)) -+ return PTR_ERR(phy->base); -+ -+ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); -+ if (IS_ERR(phy->apb_spare)) -+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), -+ "Failed to fine APB SPARE syscon"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to find APMU syscon"); -+ -+ ret = k3_combo_phy_update_config(apmu, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to set lane configuration"); -+ -+ phy->dev = dev; -+ platform_set_drvdata(pdev, phy); -+ -+ ret = k3_phy_calibrate(phy->apb_spare); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to calibrate phy"); -+ -+ ret = k3_combo_phy_init_lanes(phy, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to init lanes"); -+ -+ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "Failed to register provider\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id k3_combo_phy_of_match[] = { -+ { .compatible = "spacemit,k3-combo-phy" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); -+ -+static struct platform_driver k3_combo_phy_driver = { -+ .probe = k3_combo_phy_probe, -+ .driver = { -+ .name = "spacemit,k3-combo-phy", -+ .of_match_table = k3_combo_phy_of_match, -+ }, -+}; -+module_platform_driver(k3_combo_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c -new file mode 100644 -index 000000000000..840524cbe533 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.c -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* PHY Registers */ -+#define PHY_VERSION 0x0 -+ -+#define PHY_RESET_CFG 0x04 -+ -+#define PHY_RESET_RXBUF_RST BIT(0) -+#define PHY_RESET_SOFT_RST_PCS BIT(1) -+#define PHY_RESET_SOFT_RST_AHB BIT(2) -+#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) -+ -+#define PHY_CLK_CFG 0x08 -+ -+#define PHY_CLK_PLL_READY BIT(0) -+#define PHY_CLK_TXCLK_INV BIT(2) -+#define PHY_CLK_RXCLK_EN BIT(3) -+#define PHY_CLK_TXCLK_EN BIT(4) -+#define PHY_CLK_PCLK_EN BIT(5) -+#define PHY_CLK_PIPE_PCLK_EN BIT(6) -+#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) -+#define PHY_CLK_REFCLK_24M 2 -+#define PHY_CLK_SW_INIT_DONE BIT(11) -+#define PHY_CLK_PU_SSC_OUT BIT(23) -+ -+#define PHY_MODE_CFG 0x0C -+ -+#define PHY_MODE_PCIE_INT_EN BIT(0) -+#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) -+#define PHY_MODE_LFPS_TPERIOD_USB 3 -+ -+#define PHY_PU_SEL 0x40 -+ -+#define PHY_PU_CFG_STATUS BIT(9) -+#define PHY_PU_OVRD_STATUS BIT(10) -+ -+#define PHY_PU_CK_REG 0x54 -+ -+#define PHY_PU_REFCLK_100 BIT(25) -+ -+#define PHY_PLL_REG1 0x58 -+ -+#define PHY_PLL_FREF_SEL GENMASK(15, 13) -+#define PHY_PLL_FREF_24M 0x1 -+#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) -+#define PHY_PLL_SSC_5000PPM 0xa -+#define PHY_PLL_SSC_MODE GENMASK(29, 28) -+#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 -+#define PHY_PLL_SSC_MODE_UP_SPREAD 1 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 -+ -+#define PHY_PLL_REG2 0x5c -+ -+#define PHY_PLL_SEL_REF100 BIT(21) -+ -+/* PHY RX Register Definitions */ -+#define PHY_RX_REG_A 0x60 -+ -+#define PHY_RX_REG0_RLOAD BIT(4) -+#define PHY_RX_REG1_RTERM GENMASK(11, 8) -+#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) -+#define PHY_RX_REG2_CSEL GENMASK(19, 16) -+#define PHY_RX_REG2_FORCE_CSEL BIT(20) -+#define PHY_RX_REG2_PSEL GENMASK(23, 21) -+#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) -+#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) -+#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) -+#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) -+ -+#define PHY_RX_REG_B 0x64 -+ -+#define PHY_RX_REGB_MASK GENMASK(23, 0) -+ -+#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) -+#define PHY_RX_REG4_ENVOS BIT(4) -+#define PHY_RX_REG4_RTERM_SEL BIT(5) -+#define PHY_RX_REG4_MANUAL_CFG BIT(7) -+#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) -+#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) -+#define PHY_RX_REG6_H1_REG GENMASK(19, 16) -+#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) -+#define PHY_RX_REG6_BYPASS_ADPT BIT(22) -+ -+#define PHY_ADPT_CFG0 0x140 -+#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) -+#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) -+ -+#define PHY_RXEQ_TIME 0xb4 -+#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) -+#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) -+#define PHY_RXEQ_TIME_AMP_SOC_650M 0 -+#define PHY_RXEQ_TIME_AMP_SOC_800M 1 -+#define PHY_RXEQ_TIME_AMP_SOC_870M 2 -+#define PHY_RXEQ_TIME_AMP_SOC_900M 3 -+#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) -+ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PHY_CLK_PLL_READY BIT(0) -+#define PCIE_INITAL_TIMER GENMASK(6, 3) -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define CFG_SW_PHY_INIT_DONE BIT(11) -+ -+/* Lane RX/TX configuration (per‑lane, at lane_base) */ -+#define PCIE_RX_REG1 0x050 -+#define PCIE_TX_REG1 0x064 -+ -+#define PCIE_PLL_TIMEOUT 500000 -+#define PCIE_POLL_DELAY 500 -+ -+static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) -+{ -+ struct phy *phy = lg->phy; -+ u32 val, tmp; -+ int ret; -+ -+ /* Do not wait CDR lock before sampling data */ -+ val = readl(base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); -+ writel(val, base + PHY_RESET_CFG); -+ -+ /* Power down 100MHz refclk buffer */ -+ val = readl(base + PHY_PU_CK_REG); -+ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); -+ writel(val, base + PHY_PU_CK_REG); -+ -+ /* Program PLL REG1 configure the SSC */ -+ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | -+ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | -+ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); -+ writel(val, base + PHY_PLL_REG1); -+ -+ /* Un-select 100MHz PLL reference */ -+ val = readl(base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); -+ writel(val, base + PHY_PLL_REG2); -+ -+ /* USB LFPS period configuration */ -+ val = readl(base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); -+ writel(val, base + PHY_MODE_CFG); -+ -+ /* Force AFE adaptation reset */ -+ val = readl(base + PHY_ADPT_CFG0); -+ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; -+ writel(val, base + PHY_ADPT_CFG0); -+ -+ /* Override driver amplitude value to 900m */ -+ val = readl(base + PHY_RXEQ_TIME); -+ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; -+ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); -+ writel(val, base + PHY_RXEQ_TIME); -+ -+ /* Configure RX parameters */ -+ val = PHY_RX_REG0_RLOAD | -+ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | -+ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | -+ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | -+ PHY_RX_REG2_FORCE_CSEL | -+ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | -+ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | -+ PHY_RX_REG3_SEL_CBOOST_CODE | -+ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | -+ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); -+ writel(val, base + PHY_RX_REG_A); -+ -+ val = readl(base + PHY_RX_REG_B); -+ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | -+ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | -+ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | -+ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); -+ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); -+ writel(val, base + PHY_RX_REG_B); -+ -+ /* -+ * Inform PHY that all PLL-related configuration is done. -+ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. -+ */ -+ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | -+ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | -+ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | -+ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; -+ writel(val, base + PHY_CLK_CFG); -+ -+ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), -+ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&phy->dev, "PHY PLL polling timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int k3_usb3phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ int ret, i; -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_usb3_phy_ops = { -+ .init = k3_usb3phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); -+ -+static int k3_pcie_phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ void __iomem *phy_base = lg->base + lg->data->offsets[0]; -+ u32 val; -+ int ret; -+ int i; -+ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, BIT(21)); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ val = readl(lane_base + PCIE_RX_REG1); -+ val = u32_replace_bits(val, 0, 0x3); -+ writel(val, lane_base + PCIE_RX_REG1); -+ } -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val |= BIT(20); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ writel(0x00006505, phy_base + PCIE_RX_REG1); -+ -+ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0, GENMASK(27, 24)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ -+ val = readl(lane_base + PHY_PU_SEL); -+ val = u32_replace_bits(val, 1, BIT(13)); -+ writel(val, lane_base + PHY_PU_SEL); -+ -+ /* disable en_sample_data_after_cdr_locked */ -+ val = readl(lane_base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, BIT(6)); -+ writel(val, lane_base + PHY_RESET_CFG); -+ -+ /* Dynamic Lock */ -+ val = readl(lane_base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, 1, BIT(2)); -+ writel(val, lane_base + PHY_MODE_CFG); -+ -+ val = FIELD_PREP(GENMASK(7, 0), 0x10) | -+ FIELD_PREP(GENMASK(15, 8), 0x78) | -+ FIELD_PREP(GENMASK(23, 16), 0x98) | -+ FIELD_PREP(GENMASK(31, 24), 0xdf); -+ writel(val, lane_base + PHY_RX_REG_A); -+ -+ val = readl(lane_base + PHY_RX_REG_B); -+ val &= ~PHY_RX_REGB_MASK; -+ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | -+ FIELD_PREP(GENMASK(15, 8), 0x88) | -+ FIELD_PREP(GENMASK(23, 16), 0x28); -+ writel(val, lane_base + PHY_RX_REG_B); -+ -+ /* Set init done */ -+ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); -+ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); -+ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); -+ } -+ -+ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, -+ PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_pcie_phy_ops = { -+ .init = k3_pcie_phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); -+ -+/* PHY rcal init requires APB_SPARE regmap access */ -+ -+#define APB_SPARE_PU_CAL 0x178 -+#define PU_CAL BIT(17) -+ -+#define APB_SPARE_RCAL_HSIO 0x17c -+#define APB_SPARE_PU_CAL_DONE BIT(8) -+#define RCAL_OVRD_PTRIM GENMASK(23, 20) -+#define RCAL_OVRD_NTRIM GENMASK(27, 24) -+#define RCAL_OVRD_PTRIM_EN BIT(28) -+#define RCAL_OVRD_NTRIM_EN BIT(29) -+#define RCAL_OVRD_STABLE_VAL BIT(30) -+#define RCAL_OVRD_STABLE_EN BIT(31) -+ -+#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) -+#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) -+ -+#define PU_CAL_TIMEOUT 2000000 -+ -+static DEFINE_MUTEX(calibrate_lock); -+ -+int k3_phy_calibrate(struct regmap *apb_spare) -+{ -+ unsigned int val = 0; -+ int ret; -+ -+ guard(mutex)(&calibrate_lock); -+ -+ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); -+ if (val & APB_SPARE_PU_CAL_DONE) -+ return 0; -+ -+ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, -+ PU_CAL); -+ -+ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, -+ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, -+ PU_CAL_TIMEOUT); -+ -+ if (ret) -+ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | -+ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | -+ RCAL_OVRD_STABLE_EN); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(k3_phy_calibrate); -+ -+MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h -new file mode 100644 -index 000000000000..49009c3c313a ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _PHY_K3_COMMON_H -+#define _PHY_K3_COMMON_H -+ -+#include -+ -+struct k3_phy_lane_group_data { -+ u32 lanes; -+ u8 config; -+ u8 mask; -+ u32 offsets[] __counted_by(lanes); -+}; -+ -+struct k3_lane_group { -+ const struct k3_phy_lane_group_data *data; -+ void __iomem *base; -+ struct phy *phy; -+ bool is_pcie; -+}; -+ -+extern const struct phy_ops k3_pcie_phy_ops; -+extern const struct phy_ops k3_usb3_phy_ops; -+ -+int k3_phy_calibrate(struct regmap *apb_spare); -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0466-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux-lts-kmhv2/0466-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch new file mode 100644 index 0000000000..9e78580517 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0466-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch @@ -0,0 +1,61 @@ +From e6e34cc6749f4fd4a9f8f59f3cbed84a538bb564 Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:08 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add + vcc5v0_sys regulator for Banana Pi F3 + +Define the system 5V fixed regulator (vcc5v0_sys) supplied by the +DC input. As per the schematics, vcc5v0_sys is the input power source +for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators +to correctly reference vcc5v0_sys as their parent (vin-supply). + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-2-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 307a7e4a8943..fbb4ff5e169f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -54,6 +54,16 @@ reg_dc_in: regulator-dc-in-12v { + regulator-always-on; + }; + ++ reg_vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; +@@ -70,6 +80,7 @@ regulator-usb3-vbus-5v { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; ++ vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +@@ -79,6 +90,7 @@ usb3_hub_5v: regulator-usb3-hub-5v { + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux-lts-kmhv2/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch deleted file mode 100644 index ce8ce857a9..0000000000 --- a/SPECS/linux-lts-kmhv2/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 448b7e9c38ae27c10f2aa343886ce7c2b8243f8d Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 27 Feb 2026 09:46:06 +0800 -Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: add USB controller and - USB phy support - -Add all USB device node to the Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ - 2 files changed, 55 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index ac965ec83f2c..acfbb5029c15 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -183,6 +183,11 @@ dldo7: dldo7 { - }; - }; - -+&combophy { -+ spacemit,apmu = <&syscon_apmu 0x11>; -+ status = "okay"; -+}; -+ - ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -@@ -280,3 +285,11 @@ hub@1 { - &usb2_phy { - status = "okay"; - }; -+ -+&usb3d_u2phy { -+ status = "okay"; -+}; -+ -+&usb3d { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 1b86c872accb..e73e6838f6b0 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - /dts-v1/; - -@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb3d: usb@81a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0x81a00000 0x0 0x10000>; -+ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, -+ <&syscon_apmu RESET_APMU_USB3_D_VCC>, -+ <&syscon_apmu RESET_APMU_USB3_D_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ phys = <&usb3d_u2phy>, -+ <&combophy 4 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,parkmode-disable-ss-quirk; -+ dr_mode = "host"; -+ status = "disabled"; -+ }; -+ -+ usb3d_u2phy: phy@81b00000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0x81b00000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combophy: phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x0 0x81d00000 0x0 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&pll>; -+ status = "disabled"; -+ }; -+ - usb2_host: usb@c0a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0xc0a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0467-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux-lts-kmhv2/0467-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch new file mode 100644 index 0000000000..983640a3a3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0467-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch @@ -0,0 +1,59 @@ +From e520c42b3ece2562b8301a3c122559e0a95ad7ba Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:09 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update + USB regulator on onboard usb and lable + +Update the USB regulator labels to align with the board schematics and +power hierarchy. This change renames the regulator to reg_5v_vbus and +its name to 5V_VBUS. Additionally, it fixes the vdd-supply references +for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point +to the 5V_VBUS input source as per the board schematics. + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-3-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index fbb4ff5e169f..e97519a9a55e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -74,9 +74,9 @@ reg_vcc_4v: regulator-vcc-4v { + vin-supply = <®_dc_in>; + }; + +- regulator-usb3-vbus-5v { ++ reg_5v_vbus: regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; +- regulator-name = "USB30_VBUS"; ++ regulator-name = "5V_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; +@@ -408,7 +408,7 @@ &usb_dwc3 { + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; +- vdd-supply = <&usb3_hub_5v>; ++ vdd-supply = <®_5v_vbus>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +@@ -416,7 +416,7 @@ hub_2_0: hub@1 { + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; +- vdd-supply = <&usb3_hub_5v>; ++ vdd-supply = <®_5v_vbus>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts-kmhv2/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch deleted file mode 100644 index 76aa9565cc..0000000000 --- a/SPECS/linux-lts-kmhv2/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +++ /dev/null @@ -1,261 +0,0 @@ -From 3e1379ca2b2ca099c8a0a6900f9be381e48213c6 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 24 Mar 2026 11:06:24 +0800 -Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add PCIe device node - -Add all PCIe device node for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ - 3 files changed, 212 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index acfbb5029c15..f24ada15f182 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -264,6 +264,35 @@ uboot@210000 { - }; - }; - -+&pcie0_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_0_cfg>; -+ phys = <&combophy 0 PHY_TYPE_PCIE>, -+ <&combophy 1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pcie2_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_cfg>; -+ phys = <&combophy 2 PHY_TYPE_PCIE>, -+ <&combophy 3 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <2>; -+ status = "okay"; -+}; -+ -+&pcie4_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie4_0_cfg>; -+ phys = <&combophy 5 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ num-lanes = <1>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 846d5e8cc783..5a817610101b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -710,4 +710,37 @@ uart0-0-pins { - drive-strength = <25>; - }; - }; -+ -+ pcie0_0_cfg: pcie0-0-cfg { -+ pcie0-0-pins { -+ pinmux = , /* pcie0 perst */ -+ ; /* pcie0 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ pcie2_0_cfg: pcie2-0-cfg { -+ pcie2-0-pins { -+ pinmux = , /* pcie2 perst */ -+ ; /* pcie2 clkreq */ -+ -+ drive-strength = <38>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ pcie4_0_cfg: pcie4-0-cfg { -+ pcie4-0-pins { -+ pinmux = , /* pcie4 perst */ -+ , /* pcie4 wake */ -+ ; /* pcie4 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index e73e6838f6b0..9552089c7c73 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ pcie0_rc: pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ status = "disabled"; -+ }; -+ -+ pcie1_rc: pcie@80400000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80400000 0x0 0x00001000>, -+ <0x0 0x80500000 0x0 0x00001000>, -+ <0x0 0x80700000 0x0 0x00003f20>, -+ <0x11 0x80000000 0x0 0x00010000>, -+ <0x0 0x82c00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, -+ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <1>; -+ spacemit,apmu = <&syscon_apmu 0x1d0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_rc: pcie@80800000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80800000 0x0 0x00001000>, -+ <0x0 0x80900000 0x0 0x00001000>, -+ <0x0 0x80b00000 0x0 0x00003f20>, -+ <0x12 0x00000000 0x0 0x00010000>, -+ <0x0 0x82d00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <2>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1c8>; -+ status = "disabled"; -+ }; -+ -+ pcie3_rc: pcie@80c00000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80c00000 0x0 0x00001000>, -+ <0x0 0x80d00000 0x0 0x00001000>, -+ <0x0 0x80f00000 0x0 0x00003f20>, -+ <0x12 0x80000000 0x0 0x00010000>, -+ <0x0 0x82a00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, -+ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, -+ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <3>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e0>; -+ status = "disabled"; -+ }; -+ -+ pcie4_rc: pcie@81000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x81000000 0x0 0x00001000>, -+ <0x0 0x81100000 0x0 0x00001000>, -+ <0x0 0x81300000 0x0 0x00003f20>, -+ <0x12 0xc0000000 0x0 0x00010000>, -+ <0x0 0x82b00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, -+ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, -+ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <4>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e8>; -+ status = "disabled"; -+ }; -+ - usb3d: usb@81a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0x81a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0468-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux-lts-kmhv2/0468-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch new file mode 100644 index 0000000000..7e2a884509 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0468-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch @@ -0,0 +1,52 @@ +From f02035a00fee5f965789e1fbb4d5ee0f8a71b08b Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:10 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct + USB hub power hierarchy +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to +ensure the USB 3.0 stack is properly powered as per the schematics. +In addition, align the USB hub regulator with the board schematics +by renaming it to VCC5V0_HUB and marking it as regulator-always-on +to maintain power stability. + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-4-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index e97519a9a55e..8d2c161f5b35 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -87,9 +87,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v { + + usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; +- regulator-name = "USB30_HUB"; ++ regulator-name = "VCC5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ regulator-always-on; + vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; +@@ -403,6 +404,7 @@ &usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; ++ vbus-supply = <&usb3_hub_5v>; + status = "okay"; + + hub_2_0: hub@1 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux-lts-kmhv2/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch deleted file mode 100644 index 9a9326a3e9..0000000000 --- a/SPECS/linux-lts-kmhv2/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 88fa19733f8dc09f9c51bf41ded9c4d68c722b88 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:28:15 +0800 -Subject: [RUYI PATCH] RUYI: PCI: add SpacemiT vendor id and its K3 device id - to pci_ids - -The SpacemiT K3 chip's root complex needs to be listed in the allowlist -of rtw89 driver to allow 36-bit DMA. - -Add the vendor and device IDs to pci_ids.h header file. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - include/linux/pci_ids.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 7c01548a6ddb..e5a5700f7c8c 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2643,6 +2643,9 @@ - #define PCI_VENDOR_ID_SUNIX 0x1fd4 - #define PCI_DEVICE_ID_SUNIX_1999 0x1999 - -+#define PCI_VENDOR_ID_SPACEMIT 0x201f -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 -+ - #define PCI_VENDOR_ID_HINT 0x3388 - #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0469-FROMLIST-riscv-mm-Do-not-probe-satp-mode-limit-if-kn.patch b/SPECS/linux-lts-kmhv2/0469-FROMLIST-riscv-mm-Do-not-probe-satp-mode-limit-if-kn.patch new file mode 100644 index 0000000000..7a4d943883 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0469-FROMLIST-riscv-mm-Do-not-probe-satp-mode-limit-if-kn.patch @@ -0,0 +1,72 @@ +From e308a4d17d13dd8bd7022a103861970e8276e363 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 24 Apr 2026 11:03:26 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Do not probe satp mode limit if + known in FDT + +Some systems may only have memory at such a high address that an +identity mapping cannot be made in Sv48, or even Sv57. To avoid crashing +while probing satp mode support, trust the mmu-type property from FDT +and avoid probing if it is set. + +For example, if a CPU supports (up to) Sv57 but the SoC it is on only +has memory starting at 128 TiB, an identity mapping cannot be made in +Sv48. If the user specifies "no5lvl" on the command line, +set_satp_mode() will attempt to test Sv48 support and crash, since the +virtual address is too high. Instead, given the correct FDT CPU node +property mmu-type = "riscv,sv57", set_satp_mode() can pick the maximum +allowed mode from command line and FDT, namely Sv48, without probing. + +Handling of mmu-type "riscv,sv57" in set_satp_mode_from_fdt() is added +since it is now needed. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260424-riscv-mm-trust-fdt-mmu-type-v1-1-57f3313275d2@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/kernel/pi/fdt_early.c | 2 ++ + arch/riscv/mm/init.c | 7 ++++++- + 2 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/pi/fdt_early.c b/arch/riscv/kernel/pi/fdt_early.c +index a12ff8090f19..702253287560 100644 +--- a/arch/riscv/kernel/pi/fdt_early.c ++++ b/arch/riscv/kernel/pi/fdt_early.c +@@ -218,6 +218,8 @@ u64 set_satp_mode_from_fdt(uintptr_t dtb_pa) + return SATP_MODE_39; + else if (!strcmp(mmu_type, "riscv,sv48")) + return SATP_MODE_48; ++ else if (!strcmp(mmu_type, "riscv,sv57")) ++ return SATP_MODE_57; + break; + } + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index ac5bece70736..f10c37999f23 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -892,8 +892,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) + { + u64 identity_satp, hw_satp; + uintptr_t set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; ++ u64 satp_mode_limit_fdt = __pi_set_satp_mode_from_fdt(dtb_pa); + u64 satp_mode_limit = min_not_zero(__pi_set_satp_mode_from_cmdline(dtb_pa), +- __pi_set_satp_mode_from_fdt(dtb_pa)); ++ satp_mode_limit_fdt); + + kernel_map.page_offset = PAGE_OFFSET_L5; + +@@ -905,6 +906,10 @@ static __init void set_satp_mode(uintptr_t dtb_pa) + return; + } + ++ /* Skip probing if max SATP mode known from FDT */ ++ if (satp_mode_limit_fdt) ++ return; ++ + create_p4d_mapping(early_p4d, + set_satp_mode_pmd, (uintptr_t)early_pud, + P4D_SIZE, PAGE_TABLE); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux-lts-kmhv2/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch deleted file mode 100644 index e0b9eb8766..0000000000 --- a/SPECS/linux-lts-kmhv2/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e57bb71611315a5153d479c9e82b806ab76de1fb Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:29:46 +0800 -Subject: [RUYI PATCH] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA - allowlist - -The SpacemiT K3 platform has no system memory in the 32-bit address -space, and it's verified that the chip works well with 36-bit DMA of -RTL8852BE. - -Add it to the 36-bit DMA allowlist of rtw89_pci. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c -index 6be1849b0c4d..5058ebadb604 100644 ---- a/drivers/net/wireless/realtek/rtw89/pci.c -+++ b/drivers/net/wireless/realtek/rtw89/pci.c -@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) - if (bridge->device == 0x2806) - return true; - break; -+ case PCI_VENDOR_ID_SPACEMIT: -+ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) -+ return true; -+ break; - } - - return false; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0470-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux-lts-kmhv2/0470-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch new file mode 100644 index 0000000000..18cf83a357 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0470-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch @@ -0,0 +1,37 @@ +From ae4f71186edf3edcdff7559238bfbf06bf69cd51 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 18:31:44 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for + cross-DAI rate constraint + +On SpacemiT K3, multiple I2S controllers share the same physical BCLK +(c_bclk). Declare this clock via snd_soc_dai_set_bclk_clk() so the +ASoC core can automatically constrain hw_params when one controller is +already streaming. + +For K1, c_bclk is NULL (obtained via devm_clk_get_optional_enabled), +so this call is a no-op and behavior is unchanged. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-3-ede05a22f732@linux.spacemit.com +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 3df94b4ca5a5..1a02d7fcc7e1 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -323,6 +323,8 @@ static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai) + + spacemit_i2s_init(i2s); + ++ snd_soc_dai_set_bclk_clk(dai, i2s->c_bclk); ++ + return 0; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts-kmhv2/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch deleted file mode 100644 index 00daab299c..0000000000 --- a/SPECS/linux-lts-kmhv2/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 50eb8f06ed16e79d0840e5c58220ae05cac7dbb1 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 19 May 2026 19:57:52 +0800 -Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on - SpacemiT K3 - -The dynamic speed switch functionality seems to be broken on SpacemiT -K3, and leads to frequent GPU crashes at least with Polaris GPUs. - -Disable dynamic speed switch on this platform. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index c22aea46efcd..b54f7cdd0ce8 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) - */ - static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) - { -+ struct pci_dev *parent = adev->pdev; -+ static const struct pci_device_id broken_devids[] = { -+ /* SpacemiT K3 */ -+ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, -+ PCI_DEVICE_ID_SPACEMIT_K3) }, -+ {} -+ }; -+ - #if IS_ENABLED(CONFIG_X86) - struct cpuinfo_x86 *c = &cpu_data(0); - -@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device - if (c->x86_vendor == X86_VENDOR_INTEL) - return false; - #endif -+ /* skip upstream/downstream switches internal to dGPU */ -+ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { -+ parent = pci_upstream_bridge(parent); -+ } -+ -+ if (!parent) -+ return true; -+ -+ if (pci_match_id(broken_devids, parent)) -+ return false; -+ - return true; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0471-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux-lts-kmhv2/0471-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch new file mode 100644 index 0000000000..7eeffa199a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0471-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch @@ -0,0 +1,65 @@ +From 1e205e57bed060dde731ccfde50d6a73f757ee3a Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:16:59 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC + subsys clock controller + +TH1520 has a subsystem clock controller called MISC_SUBSYS in its +manual, mainly controlling clocks for USB and MMC/SD in non-TEE +environment. + +Add device tree binding for it. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-2-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- + include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ + 2 files changed, 13 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +index 9d058c00ab3d..d46d13597466 100644 +--- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml ++++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +@@ -23,6 +23,7 @@ properties: + compatible: + enum: + - thead,th1520-clk-ap ++ - thead,th1520-clk-misc + - thead,th1520-clk-vo + + reg: +@@ -32,8 +33,8 @@ properties: + items: + - description: | + One input clock: +- - For "thead,th1520-clk-ap": the clock input must be the 24 MHz +- main oscillator. ++ - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clock ++ input must be the 24 MHz main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL +diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h +index 68b35cc61204..642c2a69a579 100644 +--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h ++++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h +@@ -128,4 +128,14 @@ + #define CLK_MIPIDSI1_PIXCLK 29 + #define CLK_HDMI_PIXCLK 30 + ++/* MISC clocks */ ++#define CLK_MISCSYS_ACLK 0 ++#define CLK_USB 1 ++#define CLK_USB_CTL_REF 2 ++#define CLK_USB_PHY_REF 3 ++#define CLK_USB_SUSPEND 4 ++#define CLK_EMMC 5 ++#define CLK_SDIO0 6 ++#define CLK_SDIO1 7 ++ + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux-lts-kmhv2/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch deleted file mode 100644 index daa05c9c8d..0000000000 --- a/SPECS/linux-lts-kmhv2/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +++ /dev/null @@ -1,50 +0,0 @@ -From c0f35dd9ad2ce894ee2fef94f5ac86216d03ef46 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Wed, 4 Feb 2026 08:54:40 +0800 -Subject: [RUYI PATCH] RVCK: driver: clk: k3: keep some system based clock - always on - -FROM: https://github.com/RVCK-Project/rvck/pull/213 - -community inclusion -category: bugfix -bugzilla: https://github.com/RVCK-Project/rvck/issues/212 - --------------------------------- - -The hdma clk is used by some component of CCI bus, it should -be keep always on, regardless of whether hdma enabled. - -The rcpu clk should be always on because it is running backround. - -Signed-off-by: Zhang Meng -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 03de04144963..6acde3b76b7b 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { - CCU_PARENT_HW(pll1_d6_409p6), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -- 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); - - static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { - CCU_PARENT_HW(pll1_d48_51p2_ap), -@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT - /* APMU clocks end */ - - /* DCIU clocks start */ --CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); - CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); - CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); - CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0472-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux-lts-kmhv2/0472-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch new file mode 100644 index 0000000000..f407d873df --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0472-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch @@ -0,0 +1,124 @@ +From 1ea3a9e11199d508a404f6f72d8b455e39d612e1 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:00 +0800 +Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC + subsys clocks + +The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows +controlling of USB related clocks and MMC/SD controller AHB bus clocks. + +Add support for this clock controller, in order to enable USB support. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-3-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ + 1 file changed, 64 insertions(+) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index 3a6847f1c950..24f785f0b329 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", + static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, + 0x4, 0, 0); + ++static struct clk_fixed_factor usb_suspend_div_clk = { ++ .div = 24, ++ .mult = 1, ++ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", ++ osc_24m_clk, ++ &clk_fixed_factor_ops, ++ 0), ++}; ++ ++static const struct clk_parent_data usb_suspend_parents[] = { ++ { .hw = &usb_suspend_div_clk.hw }, ++}; ++ ++static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_pd, ++ 0x0, 0, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data miscsys_aclk_pd[] = { ++ { .hw = &miscsys_aclk.gate.hw }, ++}; ++ ++static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, ++ CLK_IS_CRITICAL); ++static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_clk, ++ 0x4, 1, 0); ++static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_clk, ++ 0x4, 2, 0); ++static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", ++ usb_suspend_parents, 0x4, 3, 0); ++static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, ++ 0); ++static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, ++ 0); ++static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, 0, ++ 0); ++ + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", + &gmac_pll_clk.common.hw, 10, 1, 0); + +@@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] = { + &hdmi_pixclk + }; + ++static struct ccu_gate *th1520_misc_gate_clks[] = { ++ &miscsys_aclk, ++ &usb_clk, ++ &usb_ctl_ref_clk, ++ &usb_phy_ref_clk, ++ &usb_suspend_clk, ++ &emmc_clk, ++ &sdio0_clk, ++ &sdio1_clk ++}; ++ + static const struct regmap_config th1520_clk_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +@@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platdata = { + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), + }; + ++static const struct th1520_plat_data th1520_misc_platdata = { ++ .th1520_gate_clks = th1520_misc_gate_clks, ++ ++ .nr_clks = CLK_SDIO1 + 1, ++ ++ .nr_gate_clks = ARRAY_SIZE(th1520_misc_gate_clks), ++}; ++ + /* + * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) + * when its parent, c910_clk, changes the rate. +@@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *pdev) + return ret; + } + ++ if (plat_data == &th1520_ap_platdata) { ++ ret = devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); ++ if (ret) ++ return ret; ++ } ++ + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); + if (ret) + return ret; +@@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = { + .compatible = "thead,th1520-clk-vo", + .data = &th1520_vo_platdata, + }, ++ { ++ .compatible = "thead,th1520-clk-misc", ++ .data = &th1520_misc_platdata, ++ }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, th1520_clk_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts-kmhv2/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch deleted file mode 100644 index 5c6f644043..0000000000 --- a/SPECS/linux-lts-kmhv2/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch +++ /dev/null @@ -1,65 +0,0 @@ -From af2e3f98ce75fe961163f67f323465d95ce082d9 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 28 May 2026 14:18:23 +0800 -Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA - variant - -Add support for a testing variant of the SG2042 SDHCI controller without -PHY reset and without the "timer" clock. - -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c -index 90aa146a1be3..292940d9c45b 100644 ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -1664,6 +1664,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { - .platform_execute_tuning = th1520_execute_tuning, - }; - -+static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { -+ .set_clock = sdhci_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .set_uhs_signaling = dwcmshc_set_uhs_signaling, -+ .get_max_clock = dwcmshc_get_max_clock, -+ .reset = sdhci_reset, -+ .adma_write_desc = dwcmshc_adma_write_desc, -+ .platform_execute_tuning = th1520_execute_tuning, -+}; -+ - static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { - .set_clock = sdhci_eic7700_set_clock, - .get_max_clock = sdhci_pltfm_clk_get_max_clock, -@@ -1746,6 +1756,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { - .init = sg2042_init, - }; - -+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { -+ .pdata = { -+ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, -+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+ }, -+}; -+ - static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { - .pdata = { - .ops = &sdhci_dwcmshc_eic7700_ops, -@@ -1857,6 +1875,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { - .compatible = "sophgo,sg2042-dwcmshc", - .data = &sdhci_dwcmshc_sg2042_pdata, - }, -+ { -+ .compatible = "sophgo,sg2042-fpga-dwcmshc", -+ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, -+ }, - { - .compatible = "eswin,eic7700-dwcmshc", - .data = &sdhci_dwcmshc_eic7700_pdata, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0473-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux-lts-kmhv2/0473-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch new file mode 100644 index 0000000000..35188c6953 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0473-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch @@ -0,0 +1,74 @@ +From f975aa1c287cee3e6227d7bd60a2ff64c4fc607f Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:01 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for + MISC clock controller + +The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller +mainly controlling USB-related clocks (which isn't utilized yet) and +MMC/SD controllers' AHB bus clocks. + +Add the device tree node for it along with the missing bus clock +references for MMC/SD controllers. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-4-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ + 1 file changed, 13 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f2abc6338458..f54329861496 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -401,8 +401,8 @@ emmc: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -410,8 +410,8 @@ sdio0: mmc@ffe7090000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -419,8 +419,8 @@ sdio1: mmc@ffe70a0000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe70a0000 0x0 0x10000>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -579,6 +579,13 @@ rst_misc: reset-controller@ffec02c000 { + #reset-cells = <1>; + }; + ++ clk_misc: clock-controller@ffec02c100 { ++ compatible = "thead,th1520-clk-misc"; ++ reg = <0xff 0xec02c100 0x0 0x100>; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; ++ + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0474-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux-lts-kmhv2/0474-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch new file mode 100644 index 0000000000..ac2e734a54 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0474-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch @@ -0,0 +1,102 @@ +From 66f85ff8fbb353a1dfcb16a6755a232ccc2ba2f2 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:02 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head + TH1520 USB PHY + +The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom +glue logic configuring PHY parameters. + +Add a binding for it. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-5-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ + 1 file changed, 74 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml +new file mode 100644 +index 000000000000..37f5cfb95bad +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml +@@ -0,0 +1,74 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: T-Head TH1520 USB PHY ++ ++description: | ++ The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some ++ custom logic to configure PHY parameters. ++ ++maintainers: ++ - Icenowy Zheng ++ - Wei Fu ++ - Drew Fustini ++ ++properties: ++ compatible: ++ const: thead,th1520-usb-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ clocks: ++ items: ++ - description: PHY bus clock ++ - description: PHY reference clock ++ ++ clock-names: ++ items: ++ - const: bus ++ - const: ref ++ ++ resets: ++ items: ++ - description: PHY bus reset ++ - description: PHY reset ++ ++ reset-names: ++ items: ++ - const: bus ++ - const: phy ++ ++ avdd33-usb3-supply: ++ description: | ++ 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. ++ ++required: ++ - compatible ++ - "#phy-cells" ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - avdd33-usb3-supply ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@ec030000 { ++ compatible = "thead,th1520-usb-phy"; ++ reg = <0xec030000 0x10000>; ++ #phy-cells = <0>; ++ clocks = <&clk_misc 1>, <&clk_misc 3>; ++ clock-names = "bus", "ref"; ++ resets = <&rst_misc 6>, <&rst_misc 7>; ++ reset-names = "bus", "phy"; ++ avdd33-usb3-supply = <&avdd33_usb3>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0475-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux-lts-kmhv2/0475-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch new file mode 100644 index 0000000000..df0e716d5e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0475-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch @@ -0,0 +1,281 @@ +From 3fd89dbf05c5808ca796f284fdfa9e52b806e90e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:03 +0800 +Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY + +The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with +some PHY parameters exported as another system controller along with it. + +As a few PHY parameters' default value isn't ready to work, add a driver +configuring them before letting the PHY run, in addition to +clock/reset/regulator management. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-6-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/thead/Kconfig | 12 ++ + drivers/phy/thead/Makefile | 2 + + drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ + 5 files changed, 213 insertions(+) + create mode 100644 drivers/phy/thead/Kconfig + create mode 100644 drivers/phy/thead/Makefile + create mode 100644 drivers/phy/thead/phy-th1520-usb.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index c39b40876177..d775ac20fafd 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -128,6 +128,7 @@ source "drivers/phy/st/Kconfig" + source "drivers/phy/starfive/Kconfig" + source "drivers/phy/sunplus/Kconfig" + source "drivers/phy/tegra/Kconfig" ++source "drivers/phy/thead/Kconfig" + source "drivers/phy/ti/Kconfig" + source "drivers/phy/intel/Kconfig" + source "drivers/phy/xilinx/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index e1aea28dbf6b..2577882c9647 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -41,5 +41,6 @@ obj-y += allwinner/ \ + starfive/ \ + sunplus/ \ + tegra/ \ ++ thead/ \ + ti/ \ + xilinx/ +diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig +new file mode 100644 +index 000000000000..14012db5973c +--- /dev/null ++++ b/drivers/phy/thead/Kconfig +@@ -0,0 +1,12 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config PHY_TH1520_USB ++ tristate "USB PHY driver for T-Head TH1520 SoC" ++ depends on ARCH_THEAD || COMPILE_TEST ++ depends on COMMON_CLK ++ depends on HAS_IOMEM ++ depends on OF ++ depends on RESET_CONTROLLER ++ select GENERIC_PHY ++ default ARCH_THEAD ++ help ++ Enable support for the USB PHY on the T-Head TH1520 SoC. +diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile +new file mode 100644 +index 000000000000..5b459bc7004b +--- /dev/null ++++ b/drivers/phy/thead/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_TH1520_USB) += phy-th1520-usb.o +diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1520-usb.c +new file mode 100644 +index 000000000000..c87bd779bbb7 +--- /dev/null ++++ b/drivers/phy/thead/phy-th1520-usb.c +@@ -0,0 +1,197 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) ++ * ++ * Authors: ++ * Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define USB_SYSCON_OFFSET 0xf000 ++ ++/* All the below registers are in the USB syscon region */ ++#define USB_CLK_GATE_STS 0x0 ++#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 ++#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 ++#define USB_GPIO 0xc ++#define USB_DEBUG_STS0 0x10 ++#define USB_DEBUG_STS1 0x14 ++#define USB_DEBUG_STS2 0x18 ++#define USBCTL_CLK_CTRL0 0x1c ++#define USBPHY_CLK_CTRL1 0x20 ++#define USBPHY_TEST_CTRL0 0x24 ++#define USBPHY_TEST_CTRL1 0x28 ++#define USBPHY_TEST_CTRL2 0x2c ++#define USBPHY_TEST_CTRL3 0x30 ++#define USB_SSP_EN 0x34 ++#define USB_HADDR_SEL 0x38 ++#define USB_SYS 0x3c ++#define USB_HOST_STATUS 0x40 ++#define USB_HOST_CTRL 0x44 ++#define USBPHY_HOST_CTRL 0x48 ++#define USBPHY_HOST_STATUS 0x4c ++#define USB_TEST_REG0 0x50 ++#define USB_TEST_REG1 0x54 ++#define USB_TEST_REG2 0x58 ++#define USB_TEST_REG3 0x5c ++ ++#define USB_SYS_COMMONONN BIT(0) ++ ++#define USB_SSP_EN_REF_SSP_EN BIT(0) ++ ++struct th1520_usb_phy { ++ struct platform_device *pdev; ++ struct phy *phy; ++ struct regmap *regmap; ++ struct clk *ref_clk; ++ struct reset_control *phy_reset; ++}; ++ ++static int th1520_usb_phy_init(struct phy *phy) ++{ ++ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = clk_prepare_enable(th1520_phy->ref_clk); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_assert(th1520_phy->phy_reset); ++ if (ret) ++ goto err_disable_clk; ++ ++ /* ++ * Do some initial PHY setup: ++ * - Set COMMONONN to allow the PHY to automatically power down. ++ * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed ++ * PHY clock PLL. ++ */ ++ regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); ++ regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); ++ ++ ret = reset_control_deassert(th1520_phy->phy_reset); ++ if (ret) ++ goto err_disable_clk; ++ ++ udelay(10); ++ ++ return 0; ++ ++err_disable_clk: ++ clk_disable_unprepare(th1520_phy->ref_clk); ++ return ret; ++} ++ ++static int th1520_usb_phy_exit(struct phy *phy) ++{ ++ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = reset_control_assert(th1520_phy->phy_reset); ++ if (ret) ++ return ret; ++ ++ clk_disable_unprepare(th1520_phy->ref_clk); ++ ++ return 0; ++} ++ ++static const struct phy_ops th1520_usb_phy_ops = { ++ .init = th1520_usb_phy_init, ++ .exit = th1520_usb_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct regmap_config phy_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = USB_TEST_REG3, ++}; ++ ++static int th1520_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct th1520_usb_phy *th1520_phy; ++ struct reset_control *bus_reset; ++ void __iomem *base; ++ int ret; ++ ++ th1520_phy = devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); ++ if (!th1520_phy) ++ return -ENOMEM; ++ ++ th1520_phy->pdev = pdev; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ th1520_phy->ref_clk = devm_clk_get(dev, "ref"); ++ if (IS_ERR(th1520_phy->ref_clk)) ++ return PTR_ERR(th1520_phy->ref_clk); ++ ++ /* De-assert the bus reset and leave it that way */ ++ bus_reset = devm_reset_control_get_exclusive_deasserted(dev, "bus"); ++ if (IS_ERR(bus_reset)) ++ return PTR_ERR(bus_reset); ++ ++ th1520_phy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); ++ if (IS_ERR(th1520_phy->phy_reset)) ++ return PTR_ERR(th1520_phy->phy_reset); ++ ++ /* ++ * Schematics of several boards (Lichee Module 4A/Milk-V Meles) ++ * describe this power rail as always-on. ++ */ ++ ret = devm_regulator_get_enable(dev, "avdd33-usb3"); ++ if (ret) ++ return ret; ++ ++ th1520_phy->regmap = devm_regmap_init_mmio_clk(dev, "bus", ++ base + USB_SYSCON_OFFSET, ++ &phy_regmap_config); ++ if (IS_ERR(th1520_phy->regmap)) ++ return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), ++ "Failed to init regmap\n"); ++ ++ th1520_phy->phy = devm_phy_create(dev, dev->of_node, &th1520_usb_phy_ops); ++ if (IS_ERR(th1520_phy->phy)) { ++ dev_err(dev, "failed to create PHY\n"); ++ return PTR_ERR(th1520_phy->phy); ++ } ++ ++ phy_set_drvdata(th1520_phy->phy, th1520_phy); ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id th1520_usb_phy_of_table[] = { ++ { .compatible = "thead,th1520-usb-phy" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); ++ ++static struct platform_driver th1520_usb_phy_driver = { ++ .driver = { ++ .name = "th1520-usb-phy", ++ .of_match_table = th1520_usb_phy_of_table, ++ }, ++ .probe = th1520_usb_phy_probe, ++}; ++ ++module_platform_driver(th1520_usb_phy_driver); ++ ++MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0476-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux-lts-kmhv2/0476-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch new file mode 100644 index 0000000000..5639deb1e0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0476-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch @@ -0,0 +1,68 @@ +From a909ed185ec695980b1d7077fcc0a623041b5e71 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:04 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB + +The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 +Dual Role Device controller in addition to a USB2+USB3 combo PHY based +on Synopsys USB3.0 FemtoPHY. + +Add device tree nodes for them. The USB controller is quite generic, new +and properly configured during silicon design, but the PHY is a little +quirky. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-7-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f54329861496..f6049dadc3d3 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -351,6 +351,20 @@ uart0: serial@ffe7014000 { + status = "disabled"; + }; + ++ usb: usb@ffe7040000 { ++ compatible = "snps,dwc3"; ++ reg = <0xff 0xe7040000 0x0 0x10000>; ++ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_misc CLK_USB>, ++ <&clk_misc CLK_USB_CTL_REF>, ++ <&clk_misc CLK_USB_SUSPEND>; ++ clock-names = "bus_early", "ref", "suspend"; ++ resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>; ++ phys = <&usb_phy>; ++ phy-names = "usb3-phy"; ++ status = "disabled"; ++ }; ++ + gmac1: ethernet@ffe7060000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; +@@ -586,6 +600,19 @@ clk_misc: clock-controller@ffec02c100 { + #clock-cells = <1>; + }; + ++ usb_phy: phy@ffec030000 { ++ compatible = "thead,th1520-usb-phy"; ++ reg = <0xff 0xec030000 0x0 0x10000>; ++ clocks = <&clk_misc CLK_USB>, ++ <&clk_misc CLK_USB_PHY_REF>; ++ clock-names = "bus", "ref"; ++ resets = <&rst_misc TH1520_RESET_ID_USB3_APB>, ++ <&rst_misc TH1520_RESET_ID_USB3_PHY>; ++ reset-names = "bus", "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0477-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux-lts-kmhv2/0477-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch new file mode 100644 index 0000000000..50054349a0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0477-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch @@ -0,0 +1,48 @@ +From df0426871c47577b198bcc8cff14405a4b5a2e4e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:06 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports + property + +As a USB hub device, VL817 can surely be connected to external USB +connectors. The binding for such connectors connection is already +described in the generic usb-hub.yaml binding with ports subnode, but +it's not yet allowed in the VL817 binding. + +Switch the reference binding from usb-device.yaml to usb-hub.yaml (which +recursively references usb-device.yaml and contains definition for ports +subnode) and allow ports subnode in VL817 binding. + +Cc: Anand Moon +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-9-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +index c815010ba9c2..7387f4fae54d 100644 +--- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml ++++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +@@ -10,7 +10,7 @@ maintainers: + - Anand Moon + + allOf: +- - $ref: usb-device.yaml# ++ - $ref: usb-hub.yaml# + + properties: + compatible: +@@ -34,6 +34,8 @@ properties: + description: + phandle to the peer hub on the controller. + ++ ports: true ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0478-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux-lts-kmhv2/0478-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch new file mode 100644 index 0000000000..3d307a7d12 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0478-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch @@ -0,0 +1,66 @@ +From 1462dae45364f55b5bd2abc1fe3843cd79e6d08e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:07 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes + +Although "D" and "H" are earlier in the alphabet than "P", the DPU and +HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. + +Sort the nodes in this device tree. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-10-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index af6f25ebbf60..834ee72a77ee 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -117,6 +117,20 @@ i2c-pins { + }; + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -179,20 +193,6 @@ &sdio1 { + status = "okay"; + }; + +-&dpu { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out_port { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0479-BACKPORT-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nod.patch b/SPECS/linux-lts-kmhv2/0479-BACKPORT-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nod.patch new file mode 100644 index 0000000000..08c762a841 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0479-BACKPORT-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nod.patch @@ -0,0 +1,111 @@ +From 999615d8e829b7e54b7f592523530f707b09a765 Mon Sep 17 00:00:00 2001 +From: Thomas Bonnefille +Date: Thu, 7 May 2026 16:17:08 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: riscv: dts: thead: Add TH1520 I2C + nodes + +Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. + +Signed-off-by: Thomas Bonnefille +Reviewed-by: Drew Fustini +[Icenowy: rebase on top of v7.1-rc2] +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-11-zhengxingda@iscas.ac.cn +[Han Gao: i2c1 node has been merged, so drop it from origin patch] +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f6049dadc3d3..aa757ddd6046 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -460,6 +460,16 @@ uart3: serial@ffe7f04000 { + status = "disabled"; + }; + ++ i2c0: i2c@ffe7f20000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f20000 0x0 0x4000>; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2c1: i2c@ffe7f24000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; +@@ -471,6 +481,16 @@ i2c1: i2c@ffe7f24000 { + status = "disabled"; + }; + ++ i2c4: i2c@ffe7f28000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f28000 0x0 0x4000>; ++ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C4>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; +@@ -569,6 +589,16 @@ padctrl0_apsys: pinctrl@ffec007000 { + thead,pad-group = <3>; + }; + ++ i2c2: i2c@ffec00c000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xec00c000 0x0 0x4000>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; +@@ -580,6 +610,16 @@ uart2: serial@ffec010000 { + status = "disabled"; + }; + ++ i2c3: i2c@ffec014000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xec014000 0x0 0x4000>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C3>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + pwm: pwm@ffec01c000 { + compatible = "thead,th1520-pwm"; + reg = <0xff 0xec01c000 0x0 0x4000>; +@@ -805,6 +845,16 @@ uart5: serial@fff7f0c000 { + status = "disabled"; + }; + ++ i2c5: i2c@fff7f2c000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xf7f2c000 0x0 0x4000>; ++ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C5>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0480-BACKPORT-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-I.patch b/SPECS/linux-lts-kmhv2/0480-BACKPORT-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-I.patch new file mode 100644 index 0000000000..d1f85614e9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0480-BACKPORT-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-I.patch @@ -0,0 +1,189 @@ +From 7d0c40ab6d9603c045e3ec1c534a923b54c228af Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Thu, 7 May 2026 16:17:09 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: riscv: dts: thead: Add Lichee Pi 4A + IO expansions + +Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the +I2C0/1/3 busses. + +Add device tree nodes for them. + +Signed-off-by: Emil Renner Berthing +[Icenowy: added commit description] +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-12-zhengxingda@iscas.ac.cn +[Han Gao: Remove the upstream i2c1 node + and set the i2c1 clock frequency to the mainline value. ] +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 125 ++++++++++++++++-- + 1 file changed, 111 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 834ee72a77ee..76c211ffdbf9 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -17,6 +17,9 @@ aliases { + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &aogpio; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; +@@ -131,6 +134,76 @@ hdmi_out_con: endpoint { + }; + }; + ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp1: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "cam0_dvdd12", ++ "cam0_avdd28", ++ "cam0_dovdd18"; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <400000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp2: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "", ++ "cam0_reset", ++ "cam1_reset", ++ "cam2_reset", ++ "wl_host_wake", ++ "bt_resetn", ++ "", ++ "bt_host_wake"; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp3: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "tp0_rst", ++ "", ++ "", ++ "vcc5v_usb", ++ "vdd28_tp0", ++ "vdd33_lcd0", ++ "vdd18_lcd0", ++ "lcd0_reset"; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -144,6 +217,18 @@ pwm1-pins { + }; + }; + ++ i2c3_pins: i2c3-0 { ++ i2c-pins { ++ pins = "I2C3_SCL", "I2C3_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++ + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; +@@ -167,20 +252,6 @@ rx-pins { + }; + }; + +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- +- ioexp2: gpio@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- + &sdio1 { + #address-cells = <1>; + #size-cells = <0>; +@@ -193,6 +264,32 @@ &sdio1 { + status = "okay"; + }; + ++&padctrl1_apsys { ++ i2c0_pins: i2c0-0 { ++ i2c-pins { ++ pins = "I2C0_SCL", "I2C0_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-0 { ++ i2c-pins { ++ pins = "I2C1_SCL", "I2C1_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0481-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux-lts-kmhv2/0481-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch new file mode 100644 index 0000000000..5fa7f15e44 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0481-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch @@ -0,0 +1,298 @@ +From fc84999cabbda71a6f64d0b05b52714597ab9717 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:10 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee + Pi 4A + +The Lichee Pi 4A board features an onboard VIA VL817 hub connected to +the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as +downstream. + +Enable SoC USB3 and the hub on Lichee Pi 4A. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-13-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 230 ++++++++++++++++++ + 2 files changed, 245 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +index 8e76b63e0100..bfda5a6b56b8 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +@@ -20,6 +20,16 @@ memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; ++ ++ /* TODO: Switch to AON regulator when it's available. */ ++ avdd33_usb3: regulator-avdd33-usb3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AVDD33_USB3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ /* Marked as always on on the schematics */ ++ regulator-always-on; ++ }; + }; + + &osc { +@@ -202,3 +212,8 @@ &sdio0 { + max-frequency = <198000000>; + status = "okay"; + }; ++ ++&usb_phy { ++ avdd33-usb3-supply = <&avdd33_usb3>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 76c211ffdbf9..da3425a44f63 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -104,6 +104,141 @@ fan: pwm-fan { + cooling-levels = <0 66 196 255>; + }; + ++ hub_5v: regulator-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "HUB_5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&ioexp3 3 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc5v_usb: regulator-vcc5v-usb { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V_USB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* ++ * Workaround for Linux currently being not able to power on ++ * Vbus for USB Type-A connectors. ++ */ ++ regulator-always-on; ++ }; ++ ++ connector-usb-a-1 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_1_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port1_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_1_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port1_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-2 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_2_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port2_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_2_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port2_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-3 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_3_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port3_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_3_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port3_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-4 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_4_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port4_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_4_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port4_ep>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&aogpio { ++ /* Route USB2 to the onboard hub for normal operation */ ++ sel-usb-hub-hog { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; + }; + + &padctrl1_apsys { +@@ -295,3 +430,98 @@ &uart0 { + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&usb { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_hs: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <1>; ++ peer-hub = <&hub_ss>; ++ vdd-supply = <&hub_5v>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ hub_hs_port1_ep: endpoint { ++ remote-endpoint = <&usb_a_1_hs_ep>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ hub_hs_port2_ep: endpoint { ++ remote-endpoint = <&usb_a_2_hs_ep>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ hub_hs_port3_ep: endpoint { ++ remote-endpoint = <&usb_a_3_hs_ep>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ hub_hs_port4_ep: endpoint { ++ remote-endpoint = <&usb_a_4_hs_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ hub_ss: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <2>; ++ peer-hub = <&hub_hs>; ++ vdd-supply = <&hub_5v>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ hub_ss_port1_ep: endpoint { ++ remote-endpoint = <&usb_a_1_ss_ep>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ hub_ss_port2_ep: endpoint { ++ remote-endpoint = <&usb_a_2_ss_ep>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ hub_ss_port3_ep: endpoint { ++ remote-endpoint = <&usb_a_3_ss_ep>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ hub_ss_port4_ep: endpoint { ++ remote-endpoint = <&usb_a_4_ss_ep>; ++ }; ++ }; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0482-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux-lts-kmhv2/0482-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch new file mode 100644 index 0000000000..3c624e3928 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0482-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch @@ -0,0 +1,318 @@ +From 5da3180c2d8a66742b63158bf1717c6352af5d7c Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 8 May 2026 15:25:24 +0800 +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for + accurate SCL frequency + +The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for +master mode operations is determined by the ILCR (I2C Load Count Register). +Previously, the driver relied on the hardware's reset default +values for this register. + +The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL +frequencies lower than intended. For example, with the default +31.5 MHz input clock, these default settings result in an SCL +frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, +and approximately 338 kHz (fast mode) when targeting 400 kHz. +These frequencies are below the 100 kHz/400 kHz nominal speeds. + +This patch integrates the SCL frequency management into +the Common Clock Framework (CCF). Specifically, the ILCR register, +which acts as a frequency divider for the SCL clock, is now registered +as a managed clock (scl_clk) within the CCF. + +The actual hardware timing formulas are: +- standard mode: SCL = FCLK / (2 * SLV + 8) +- fast mode: SCL = FCLK / (2 * FLV + 10) + +These formulas are only valid when the IWCR (Wait Count Register) is +programmed to 0x142A, a value specified by the I2C IP designer. The +driver now initializes IWCR to this value during controller init. + +Reviewed-by: Yixun Lan +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/i2c/busses/Kconfig | 2 +- + drivers/i2c/busses/i2c-k1.c | 174 ++++++++++++++++++++++++++++++++++-- + 2 files changed, 167 insertions(+), 9 deletions(-) + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index e60faac4e337..456cced004b2 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -798,7 +798,7 @@ config I2C_JZ4780 + config I2C_K1 + tristate "SpacemiT K1 I2C adapter" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on OF ++ depends on OF && COMMON_CLK + default ARCH_SPACEMIT + help + This option enables support for the I2C interface on the SpacemiT K1 +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 9152cf436bea..c6fe2052e479 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -4,7 +4,9 @@ + */ + + #include ++#include + #include ++#include + #include + #include + #include +@@ -17,6 +19,8 @@ + #define SPACEMIT_ISR 0x4 /* Status register */ + #define SPACEMIT_IDBR 0xc /* Data buffer register */ + #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ ++#define SPACEMIT_ILCR 0x10 /* Load Count Register */ ++#define SPACEMIT_IWCR 0x14 /* Wait Count Register */ + #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ + + /* SPACEMIT_ICR register fields */ +@@ -88,6 +92,19 @@ + #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ + #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ + ++#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0) ++#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9) ++ ++/* SPACEMIT_IWCR register fields */ ++#define SPACEMIT_WCR_COUNT GENMASK(4, 0) ++#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5) ++#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10) ++ ++/* Required by I2C IP for correct SCL timing */ ++#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \ ++ FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \ ++ FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5)) ++ + /* i2c bus recover timeout: us */ + #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 + +@@ -109,11 +126,20 @@ enum spacemit_i2c_state { + SPACEMIT_STATE_WRITE, + }; + ++enum spacemit_i2c_mode { ++ SPACEMIT_MODE_STANDARD, ++ SPACEMIT_MODE_FAST ++}; ++ + /* i2c-spacemit driver's main struct */ + struct spacemit_i2c_dev { + struct device *dev; + struct i2c_adapter adapt; + ++ struct clk_hw scl_clk_hw; ++ struct clk *scl_clk; ++ enum spacemit_i2c_mode mode; ++ + /* hardware resources */ + void __iomem *base; + int irq; +@@ -135,6 +161,85 @@ struct spacemit_i2c_dev { + u32 status; + }; + ++static void spacemit_i2c_scl_clk_disable_unprepare(void *data) ++{ ++ clk_disable_unprepare(data); ++} ++ ++/* ++ * Calculate the ILCR divider value (lv) from the target SCL rate. ++ * ++ * Hardware timing formulas: ++ * - standard mode: SCL = FCLK / (2 * SLV + 8) ++ * - fast mode: SCL = FCLK / (2 * FLV + 10) ++ */ ++static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c, ++ unsigned long parent_rate, ++ unsigned long target_rate) ++{ ++ u32 offset, denom; ++ ++ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; ++ denom = DIV_ROUND_CLOSEST(parent_rate, target_rate); ++ ++ return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2); ++} ++ ++static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lv, lcr, mask; ++ ++ lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate); ++ ++ mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ? ++ SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK; ++ ++ lcr = readl(i2c->base + SPACEMIT_ILCR); ++ lcr &= ~mask; ++ lcr |= field_prep(mask, lv); ++ writel(lcr, i2c->base + SPACEMIT_ILCR); ++ ++ return 0; ++} ++ ++static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lv, offset; ++ ++ lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate); ++ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; ++ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset); ++ ++ return 0; ++} ++ ++static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lcr, lv = 0; ++ ++ lcr = readl(i2c->base + SPACEMIT_ILCR); ++ ++ if (i2c->mode == SPACEMIT_MODE_STANDARD) { ++ lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr); ++ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8); ++ } ++ ++ lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr); ++ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10); ++} ++ ++static const struct clk_ops spacemit_i2c_clk_ops = { ++ .set_rate = spacemit_i2c_clk_set_rate, ++ .determine_rate = spacemit_i2c_clk_determine_rate, ++ .recalc_rate = spacemit_i2c_clk_recalc_rate, ++}; ++ + static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) + { + u32 val; +@@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_ICR); + } + ++static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c) ++{ ++ struct clk_init_data init = {}; ++ char name[64]; ++ int ret; ++ ++ ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev)); ++ if (ret >= ARRAY_SIZE(name)) ++ dev_warn(i2c->dev, "scl clock name truncated"); ++ ++ init.name = name; ++ init.ops = &spacemit_i2c_clk_ops; ++ init.parent_data = (struct clk_parent_data[]) { ++ { .fw_name = "func" }, ++ }; ++ init.num_parents = 1; ++ ++ i2c->scl_clk_hw.init = &init; ++ ++ return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw); ++} ++ + static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) + { + writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); +@@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + val |= SPACEMIT_CR_MSDIE; + } + +- if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) ++ if (i2c->mode == SPACEMIT_MODE_FAST) + val |= SPACEMIT_CR_MODE_FAST; + + /* disable response to general call */ +@@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_IRCR); + + spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); ++ ++ /* ++ * Initialize IWCR to the value specified by the I2C IP designer. ++ * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard ++ * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when ++ * IWCR contains this specific value. ++ */ ++ writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR); + } + + static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) +@@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); + + /* For now, this driver doesn't support high-speed. */ +- if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { +- dev_warn(dev, "unsupported clock frequency %u; using %u\n", +- i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); ++ if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && ++ i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { ++ i2c->mode = SPACEMIT_MODE_FAST; ++ } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { ++ i2c->mode = SPACEMIT_MODE_STANDARD; ++ } else { ++ dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); ++ i2c->mode = SPACEMIT_MODE_FAST; + i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; +- } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { +- dev_warn(dev, "unsupported clock frequency %u; using %u\n", +- i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); +- i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; + } + + i2c->dev = &pdev->dev; +@@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); + ++ ret = spacemit_i2c_register_scl_clk(i2c); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register scl clock\n"); ++ ++ i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl"); ++ if (IS_ERR(i2c->scl_clk)) ++ return dev_err_probe(dev, PTR_ERR(i2c->scl_clk), ++ "failed to get scl clock\n"); ++ + clk = devm_clk_get_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); +@@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + return dev_err_probe(dev, PTR_ERR(rst), + "failed to acquire deasserted reset\n"); + ++ ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to set rate for SCL clock"); ++ ++ ret = clk_prepare_enable(i2c->scl_clk); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to prepare and enable clock"); ++ ++ ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare, ++ i2c->scl_clk); ++ if (ret) ++ return ret; ++ + spacemit_i2c_reset(i2c); + + i2c_set_adapdata(&i2c->adapt, i2c); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0483-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux-lts-kmhv2/0483-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch new file mode 100644 index 0000000000..497fbf65d0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0483-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch @@ -0,0 +1,45 @@ +From f68f6e52d9807e19c5662a3a3a157ddcee8d1098 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 8 May 2026 15:25:25 +0800 +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when + clock-frequency property is absent + +The clock-frequency property is optional according to the DT binding. +Do not emit a warning when the property is missing and fall back to the +default frequency instead. + +Reviewed-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index c6fe2052e479..7cf5c05a20d2 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -833,9 +833,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (!i2c) + return -ENOMEM; + +- ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); +- if (ret && ret != -EINVAL) +- dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); ++ of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); + + /* For now, this driver doesn't support high-speed. */ + if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && +@@ -844,7 +842,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { + i2c->mode = SPACEMIT_MODE_STANDARD; + } else { +- dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); ++ dev_info(dev, "clock-frequency not set or out of range, using fast mode\n"); + i2c->mode = SPACEMIT_MODE_FAST; + i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0484-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux-lts-kmhv2/0484-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch new file mode 100644 index 0000000000..b4ce439eb6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0484-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch @@ -0,0 +1,102 @@ +From fd0b7e4ebbd77c9d9180ee860c936e95844e4a2c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:21 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support + +To reuse the K1 PCIe driver logic for K3 PCIe controller, add device +data to handle the K1 specific logic and make room for the incoming +logic for K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 30 ++++++++++++++++--- + 1 file changed, 26 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index be20a520255b..f6ae8ff3589a 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -49,8 +49,17 @@ + #define PCIE_CONTROL_LOGIC 0x0004 + #define PCIE_SOFT_RESET BIT(0) + ++struct k1_pcie; ++ ++struct k1_pcie_device_data { ++ const struct dw_pcie_host_ops *host_ops; ++ const struct dw_pcie_ops *ops; ++ int (*parse_port)(struct k1_pcie *k1); ++}; ++ + struct k1_pcie { + struct dw_pcie pci; ++ const struct k1_pcie_device_data *data; + struct phy *phy; + void __iomem *link; + struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ +@@ -278,14 +287,21 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + + static int k1_pcie_probe(struct platform_device *pdev) + { ++ const struct k1_pcie_device_data *data; + struct device *dev = &pdev->dev; + struct k1_pcie *k1; + int ret; + ++ data = device_get_match_data(dev); ++ if (!data) ++ return -ENODEV; ++ + k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); + if (!k1) + return -ENOMEM; + ++ k1->data = data; ++ + k1->pmu = syscon_regmap_lookup_by_phandle_args(dev_of_node(dev), + SYSCON_APMU, 1, + &k1->pmu_off); +@@ -299,11 +315,11 @@ static int k1_pcie_probe(struct platform_device *pdev) + "failed to map \"link\" registers\n"); + + k1->pci.dev = dev; +- k1->pci.ops = &k1_pcie_ops; ++ k1->pci.ops = data->ops; + k1->pci.pp.num_vectors = MAX_MSI_IRQS; + dw_pcie_cap_set(&k1->pci, REQ_RES); + +- k1->pci.pp.ops = &k1_pcie_host_ops; ++ k1->pci.pp.ops = data->host_ops; + + /* Hold the PHY in reset until we start the link */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, +@@ -320,7 +336,7 @@ static int k1_pcie_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, k1); + +- ret = k1_pcie_parse_port(k1); ++ ret = data->parse_port(k1); + if (ret) + return dev_err_probe(dev, ret, "failed to parse root port\n"); + +@@ -338,8 +354,14 @@ static void k1_pcie_remove(struct platform_device *pdev) + dw_pcie_host_deinit(&k1->pci.pp); + } + ++static const struct k1_pcie_device_data k1_pcie_device_data = { ++ .host_ops = &k1_pcie_host_ops, ++ .ops = &k1_pcie_ops, ++ .parse_port = k1_pcie_parse_port, ++}; ++ + static const struct of_device_id k1_pcie_of_match_table[] = { +- { .compatible = "spacemit,k1-pcie", }, ++ { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, + { } + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0485-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux-lts-kmhv2/0485-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch new file mode 100644 index 0000000000..9583f0fd23 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0485-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch @@ -0,0 +1,155 @@ +From 7851cfa52f4968dd95e9c120403957785bd51bac Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:22 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles + support + +The PCIe controller on Spacemit K3 may use multiple PHYs at the +same time. The feature is not support by the current driver. +So extend the PHY definition to support multiple PHY handles. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 70 ++++++++++++++++--- + 1 file changed, 59 insertions(+), 11 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index f6ae8ff3589a..e22ecbd09579 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -55,12 +55,14 @@ struct k1_pcie_device_data { + const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ops *ops; + int (*parse_port)(struct k1_pcie *k1); ++ unsigned int max_phy_count; + }; + + struct k1_pcie { + struct dw_pcie pci; + const struct k1_pcie_device_data *data; +- struct phy *phy; ++ struct phy **phy; ++ unsigned int phy_count; + void __iomem *link; + struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ + u32 pmu_off; +@@ -119,6 +121,54 @@ static void k1_pcie_disable_resources(struct k1_pcie *k1) + clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); + } + ++static int k1_pcie_get_phy_handle(struct k1_pcie *k1, struct device_node *node) ++{ ++ const struct k1_pcie_device_data *data = k1->data; ++ struct device *dev = k1->pci.dev; ++ unsigned int i; ++ ++ k1->phy = devm_kmalloc_array(dev, data->max_phy_count, ++ sizeof(*k1->phy), GFP_KERNEL); ++ if (!k1->phy) ++ return -ENOMEM; ++ ++ for (i = 0; i < data->max_phy_count; i++) { ++ k1->phy[i] = devm_of_phy_get_by_index(dev, node, i); ++ if (IS_ERR(k1->phy[i])) { ++ if (PTR_ERR(k1->phy[i]) == -ENODEV) ++ break; ++ ++ return PTR_ERR(k1->phy[i]); ++ } ++ } ++ ++ k1->phy_count = i; ++ if (k1->phy_count == 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int k1_pcie_enable_phy(struct k1_pcie *k1) ++{ ++ unsigned int i; ++ int ret; ++ ++ for (i = 0; i < k1->phy_count; i++) { ++ ret = phy_init(k1->phy[i]); ++ if (ret) ++ goto err_phy; ++ } ++ ++ return 0; ++ ++err_phy: ++ while (i--) ++ phy_exit(k1->phy[i]); ++ ++ return ret; ++} ++ + /* FIXME: Disable ASPM L1 to avoid errors reported on some NVMe drives */ + static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) + { +@@ -174,7 +224,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) + */ + regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); + +- ret = phy_init(k1->phy); ++ ret = k1_pcie_enable_phy(k1); + if (ret) { + k1_pcie_disable_resources(k1); + +@@ -194,12 +244,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct k1_pcie *k1 = to_k1_pcie(pci); ++ int i; + + /* Assert fundamental reset (drive PERST# low) */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + PCIE_RC_PERST); + +- phy_exit(k1->phy); ++ for (i = 0; i < k1->phy_count; i++) ++ phy_exit(k1->phy[i]); + + k1_pcie_disable_resources(k1); + } +@@ -266,23 +318,18 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + { + struct device *dev = k1->pci.dev; + struct device_node *root_port; +- struct phy *phy; ++ int ret; + + /* We assume only one root port */ + root_port = of_get_next_available_child(dev_of_node(dev), NULL); + if (!root_port) + return -EINVAL; + +- phy = devm_of_phy_get(dev, root_port, NULL); ++ ret = k1_pcie_get_phy_handle(k1, root_port); + + of_node_put(root_port); + +- if (IS_ERR(phy)) +- return PTR_ERR(phy); +- +- k1->phy = phy; +- +- return 0; ++ return ret; + } + + static int k1_pcie_probe(struct platform_device *pdev) +@@ -358,6 +405,7 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .host_ops = &k1_pcie_host_ops, + .ops = &k1_pcie_ops, + .parse_port = k1_pcie_parse_port, ++ .max_phy_count = 1, + }; + + static const struct of_device_id k1_pcie_of_match_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0486-FROMLIST-PCI-spacemit-k1-Add-device-id-update-helper.patch b/SPECS/linux-lts-kmhv2/0486-FROMLIST-PCI-spacemit-k1-Add-device-id-update-helper.patch new file mode 100644 index 0000000000..0b8258558c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0486-FROMLIST-PCI-spacemit-k1-Add-device-id-update-helper.patch @@ -0,0 +1,67 @@ +From 1ceddcb346dade0ca601ead0c65044ffd409b988 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:23 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device id update helper + +Both K1 and K3 needs to set vendor id and device id, add a helper function +to simplify this. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-4-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index e22ecbd09579..31aac056b68e 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -56,6 +56,7 @@ struct k1_pcie_device_data { + const struct dw_pcie_ops *ops; + int (*parse_port)(struct k1_pcie *k1); + unsigned int max_phy_count; ++ unsigned int device_id; + }; + + struct k1_pcie { +@@ -186,6 +187,16 @@ static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) + dw_pcie_dbi_ro_wr_dis(pci); + } + ++static void k1_pcie_set_device_id(struct k1_pcie *k1) ++{ ++ struct dw_pcie *pci = &k1->pci; ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); ++ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, k1->data->device_id); ++ dw_pcie_dbi_ro_wr_dis(pci); ++} ++ + static int k1_pcie_init(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +@@ -201,10 +212,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) + return ret; + + /* Set the PCI vendor and device ID */ +- dw_pcie_dbi_ro_wr_en(pci); +- dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); +- dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K1); +- dw_pcie_dbi_ro_wr_dis(pci); ++ k1_pcie_set_device_id(k1); + + /* + * Start by asserting fundamental reset (drive PERST# low). The +@@ -406,6 +414,7 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .ops = &k1_pcie_ops, + .parse_port = k1_pcie_parse_port, + .max_phy_count = 1, ++ .device_id = PCI_DEVICE_ID_SPACEMIT_K1, + }; + + static const struct of_device_id k1_pcie_of_match_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0487-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux-lts-kmhv2/0487-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch new file mode 100644 index 0000000000..d2a3059f97 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0487-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch @@ -0,0 +1,42 @@ +From a9276d0da521588ea063c1d7e3e66f14c971fd73 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:24 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent + for MSI handle check + +The IMSIC device on RISC-V based system does not require ID +remapping for MSI. So this device only needs "msi-parent" +property for IMSIC-based SoC, and the "msi-map" is not a +necessary property. + +Add new condition for MSI handling on IMSIC based SoC. + +Signed-off-by: Inochi Amaoto +Acked-by: Rob Herring (Arm) +Link: https://lore.kernel.org/r/20260709040027.958400-5-inochiama@gmail.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +index b3216141881c..91bbbc8924f6 100644 +--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml ++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +@@ -27,8 +27,11 @@ allOf: + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + - if: + not: +- required: +- - msi-map ++ anyOf: ++ - required: ++ - msi-map ++ - required: ++ - msi-parent + then: + properties: + interrupt-names: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0488-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux-lts-kmhv2/0488-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch new file mode 100644 index 0000000000..4276f26d42 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0488-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch @@ -0,0 +1,123 @@ +From 12732c2c8ac64d1c18abbee127dd9dca49efd4a2 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:25 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit + K3 PCIe host controller + +Add binding support for the PCIe controller on the SpacemiT K3 SoC. +This controller is almost a standard Synopsys DesignWare PCIe IP, +with some extra link and reset state control. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-6-inochiama@gmail.com +Signed-off-by: Han Gao +--- + .../bindings/pci/spacemit,k1-pcie-host.yaml | 50 ++++++++++++++++--- + 1 file changed, 43 insertions(+), 7 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml +index c4c00b5fcdc0..54817d6fd9af 100644 +--- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml ++++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml +@@ -14,26 +14,29 @@ description: > + PCIe IP. The controller uses the DesignWare built-in MSI interrupt + controller, and supports 256 MSIs. + +-allOf: +- - $ref: /schemas/pci/snps,dw-pcie.yaml# +- + properties: + compatible: +- const: spacemit,k1-pcie ++ enum: ++ - spacemit,k1-pcie ++ - spacemit,k3-pcie + + reg: ++ minItems: 4 + items: + - description: DesignWare PCIe registers + - description: ATU address space + - description: PCIe configuration space + - description: Link control registers ++ - description: Data Bus Interface (DBI) shadow registers. + + reg-names: ++ minItems: 4 + items: + - const: dbi + - const: atu + - const: config + - const: link ++ - const: dbi2 + + clocks: + items: +@@ -66,6 +69,8 @@ properties: + interrupt-names: + const: msi + ++ msi-parent: true ++ + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: +@@ -84,7 +89,8 @@ patternProperties: + + properties: + phys: +- maxItems: 1 ++ minItems: 1 ++ maxItems: 6 + + vpcie3v3-supply: + description: +@@ -96,13 +102,43 @@ patternProperties: + + unevaluatedProperties: false + ++allOf: ++ - $ref: /schemas/pci/snps,dw-pcie.yaml# ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k1-pcie ++ then: ++ properties: ++ reg: ++ maxItems: 4 ++ ++ reg-names: ++ maxItems: 4 ++ ++ patternProperties: ++ '^pcie@': ++ properties: ++ phys: ++ maxItems: 1 ++ ++ required: ++ - interrupts ++ - interrupt-names ++ else: ++ properties: ++ reg: ++ minItems: 5 ++ ++ reg-names: ++ minItems: 5 ++ + required: + - clocks + - clock-names + - resets + - reset-names +- - interrupts +- - interrupt-names + - spacemit,apmu + + unevaluatedProperties: false +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0489-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux-lts-kmhv2/0489-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch new file mode 100644 index 0000000000..89e72f0baf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0489-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch @@ -0,0 +1,215 @@ +From 2a6036e000e9f2ba727072be0a8d992a502938ec Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:26 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host + controller support + +The PCIe controller on Spacemit K3 is almost a standard Synopsys +DesignWare PCIe IP with extra link and reset control. Unlike +the PCIe controller on K1, this controller supports external MSI +interrupt controller and can use multiple PHYs at the same time. + +Add driver to support PCIe controller on Spacemit K3 PCIe. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-7-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/Kconfig | 4 +- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 126 ++++++++++++++++++ + 2 files changed, 128 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index af024a18621d..a1d7192e705f 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -417,7 +417,7 @@ config PCIE_SOPHGO_DW + Sophgo SoCs. + + config PCIE_SPACEMIT_K1 +- tristate "SpacemiT K1 PCIe controller (host mode)" ++ tristate "SpacemiT PCIe controller (host mode)" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on HAS_IOMEM + select PCIE_DW_HOST +@@ -425,7 +425,7 @@ config PCIE_SPACEMIT_K1 + default ARCH_SPACEMIT + help + Enables support for the DesignWare based PCIe controller in +- the SpacemiT K1 SoC operating in host mode. Three controllers ++ the SpacemiT SoC operating in host mode. Three controllers + are available on the K1 SoC; the first of these shares a PHY + with a USB 3.0 host controller (one or the other can be used). + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 31aac056b68e..680acc93f539 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -23,6 +23,7 @@ + + #define PCI_VENDOR_ID_SPACEMIT 0x201f + #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 + + /* Offsets and field definitions for link management registers */ + #define K1_PHY_AHB_IRQ_EN 0x0000 +@@ -32,8 +33,18 @@ + #define SMLH_LINK_UP BIT(1) + #define RDLH_LINK_UP BIT(12) + ++#define INTR_STATUS 0x0010 ++ + #define INTR_ENABLE 0x0014 + #define MSI_CTRL_INT BIT(11) ++#define RDLH_LINK_UP_INT BIT(20) ++ ++#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 ++ ++#define K3_ADDR_INTR_STATUS1 0x0018 ++ ++#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) ++#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf + + /* Some controls require APMU regmap access */ + #define SYSCON_APMU "spacemit,apmu" +@@ -48,6 +59,9 @@ + + #define PCIE_CONTROL_LOGIC 0x0004 + #define PCIE_SOFT_RESET BIT(0) ++#define PCIE_PERSTN_OE BIT(24) ++#define PCIE_PERSTN_OUT BIT(25) ++#define PCIE_IGNORE_PERSTN BIT(31) + + struct k1_pcie; + +@@ -340,6 +354,109 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + return ret; + } + ++static int k3_pcie_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct k1_pcie *k1 = to_k1_pcie(pci); ++ u32 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; ++ u32 val; ++ int ret; ++ ++ regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); ++ ++ k1_pcie_toggle_soft_reset(k1); ++ ++ ret = k1_pcie_enable_resources(k1); ++ if (ret) ++ return ret; ++ ++ regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); ++ regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); ++ ++ ret = k1_pcie_enable_phy(k1); ++ if (ret) { ++ k1_pcie_disable_resources(k1); ++ return ret; ++ } ++ ++ /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ ++ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, ++ PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); ++ usleep_range(1000, 2000); ++ regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); ++ ++ msleep(PCIE_T_PVPERL_MS); ++ ++ /* ++ * Put the controller in root complex mode, and indicate that ++ * Vaux (3.3v) is present. ++ */ ++ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, ++ PCIE_PERSTN_OUT | PCIE_PERSTN_OE); ++ ++ val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); ++ val = u32_replace_bits(val, BIT(7), ++ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); ++ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); ++ ++ k1_pcie_set_device_id(k1); ++ ++ /* Finally, as a workaround, disable ASPM L1 */ ++ k1_pcie_disable_aspm_l1(k1); ++ ++ return 0; ++} ++ ++static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ u32 val; ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ ++ val = dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); ++ val = u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, ++ K3_CACHE_MSTR_AWCACHE_MODE); ++ dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); ++ ++ dw_pcie_dbi_ro_wr_dis(pci); ++ ++ return 0; ++} ++ ++static const struct dw_pcie_host_ops k3_pcie_host_ops = { ++ .init = k3_pcie_init, ++ .deinit = k1_pcie_deinit, ++ .msi_init = k3_pcie_msi_host_init, ++}; ++ ++static const struct dw_pcie_ops k3_pcie_ops = { ++ .link_up = k1_pcie_link_up, ++ .start_link = k1_pcie_start_link, ++ .stop_link = k1_pcie_stop_link, ++}; ++ ++static void k3_pcie_clear_irq_status(struct k1_pcie *k1, ++ u32 *status0, u32 *status1, u32 *status2) ++{ ++ *status0 = readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); ++ *status1 = readl_relaxed(k1->link + INTR_STATUS); ++ *status2 = readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); ++ ++ writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); ++ writel_relaxed(*status1, k1->link + INTR_STATUS); ++ writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); ++} ++ ++static int k3_pcie_parse_port(struct k1_pcie *k1) ++{ ++ u32 status0, status1, status2; ++ ++ k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); ++ ++ return k1_pcie_parse_port(k1); ++} ++ + static int k1_pcie_probe(struct platform_device *pdev) + { + const struct k1_pcie_device_data *data; +@@ -417,8 +534,17 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .device_id = PCI_DEVICE_ID_SPACEMIT_K1, + }; + ++static const struct k1_pcie_device_data k3_pcie_device_data = { ++ .host_ops = &k3_pcie_host_ops, ++ .ops = &k3_pcie_ops, ++ .parse_port = k3_pcie_parse_port, ++ .max_phy_count = 6, ++ .device_id = PCI_DEVICE_ID_SPACEMIT_K3, ++}; ++ + static const struct of_device_id k1_pcie_of_match_table[] = { + { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, ++ { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, + { } + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0490-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux-lts-kmhv2/0490-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch new file mode 100644 index 0000000000..11295a44f1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0490-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch @@ -0,0 +1,37 @@ +From 3748a5c47c8c95ff1013a6db12e90030fea6d4bf Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 02:58:36 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock + +According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus +clock enable bit was wrongly swapped, the correct one should be: + +Register : APMU_USB_CLK_RES_CTRL +bit[1] : usb2_port_bus_clk_en +bit[0] : usb2_port_ahb_rstn + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Junzhong Pan +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index cb0c4277f72a..03de04144963 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -777,7 +777,7 @@ static const struct clk_parent_data sdh2_parents[] = { + CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, + BIT(11), 5, 3, BIT(4), 0); + +-CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); + CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); + CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); + CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0491-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux-lts-kmhv2/0491-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch new file mode 100644 index 0000000000..23a19eb2ae --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0491-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch @@ -0,0 +1,37 @@ +From 22ec86aedc922b5afebd7f4c23b120545a563e69 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 02:58:37 +0000 +Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset + +According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus +clock enable bit was wrongly swapped, the correct one should be: + +Register : APMU_USB_CLK_RES_CTRL +bit[1] : usb2_port_bus_clk_en +bit[0] : usb2_port_ahb_rstn + +Fixes: a0e0c2f8c5f3 ("reset: spacemit: k3: Decouple composite reset lines") +Reported-by: Junzhong Pan +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/reset-spacemit-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +index 9841f5e057b2..2e87f320cf11 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k3.c ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), +- [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), + [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), + [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0492-FROMLIST-riscv-dts-spacemit-k3-Add-QSPI-support-for-.patch b/SPECS/linux-lts-kmhv2/0492-FROMLIST-riscv-dts-spacemit-k3-Add-QSPI-support-for-.patch new file mode 100644 index 0000000000..791c58d538 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0492-FROMLIST-riscv-dts-spacemit-k3-Add-QSPI-support-for-.patch @@ -0,0 +1,152 @@ +From 73238d89a2b005bcbf2fa0eef726acd61a0962cd Mon Sep 17 00:00:00 2001 +From: Zhengyu He +Date: Sat, 11 Jul 2026 09:38:52 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add QSPI support for + Pico-ITX board + +Enable QSPI with proper pinmux on the Pico-ITX board, and describe the +NOR flash wired to it. + +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Cody Kang +Signed-off-by: Zhengyu He +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 56 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 ++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ + 3 files changed, 94 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index b89c1521e664..fd2b154f275a 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -200,6 +200,62 @@ phy0: phy@1 { + }; + }; + ++&qspi_cfg { ++ qspi-pins { ++ power-source = <1800>; ++ }; ++ ++ qspi-cs0-pins { ++ power-source = <1800>; ++ }; ++}; ++ ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x20000>; ++ }; ++ ++ fsbl@20000 { ++ reg = <0x20000 0x80000>; ++ }; ++ ++ env@a0000 { ++ reg = <0xa0000 0x10000>; ++ }; ++ ++ esos@b0000 { ++ reg = <0xb0000 0x100000>; ++ }; ++ ++ opensbi@1b0000 { ++ reg = <0x1b0000 0x60000>; ++ }; ++ ++ uboot@210000 { ++ reg = <0x210000 0x5f0000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 3ee1471f3798..846d5e8cc783 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -679,6 +679,27 @@ pwm19-2-pins { + }; + }; + ++ /omit-if-no-ref/ ++ qspi_cfg: qspi-cfg { ++ qspi-pins { ++ pinmux = , /* qspi dat0 */ ++ , /* qspi dat1 */ ++ , /* qspi dat2 */ ++ , /* qspi dat3 */ ++ ; /* qspi clk */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ }; ++ ++ qspi-cs0-pins { ++ pinmux = ; /* qspi cs0 */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 19fc9b49668e..9a49dd8032bf 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1099,6 +1099,23 @@ pll: clock-controller@d4090000 { + #clock-cells = <1>; + }; + ++ qspi: spi@d420c000 { ++ compatible = "spacemit,k3-qspi", ++ "spacemit,k1-qspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0xd420c000 0x0 0x1000>, ++ <0x0 0xb8000000 0x0 0xc00000>; ++ reg-names = "QuadSPI", "QuadSPI-memory"; ++ clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, ++ <&syscon_apmu CLK_APMU_QSPI>; ++ clock-names = "qspi_en", "qspi"; ++ resets = <&syscon_apmu RESET_APMU_QSPI>, ++ <&syscon_apmu RESET_APMU_QSPI_BUS>; ++ interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0493-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0493-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..4a4aae87e2 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0493-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,35 @@ +From 507ebca60d2727433d5db92f854fa3e28688b729 Mon Sep 17 00:00:00 2001 +From: Jennifer Berringer +Date: Wed, 20 May 2026 07:11:50 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + OrangePi RV2 + +Set the baud rate to 115200, matching what is used by U-Boot on this +platform so that the console is usable even when console options are not +specified in cmdline. + +Fixes: bab8dea259100 ("riscv: dts: spacemit: Add OrangePi RV2 board device tree") +Signed-off-by: Jennifer Berringer +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260520111150.3300707-1-jberring@redhat.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 7c49bce427f3..07dbd292eee3 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -22,7 +22,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + pcie_vcc3v3: regulator-pcie-vcc3v3 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0494-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0494-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch new file mode 100644 index 0000000000..55e80852a8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0494-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch @@ -0,0 +1,75 @@ +From e89f6522eb0ab0e4bab06940c306db21bd715065 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 2 Jun 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi + R2S + +Enable the two RTL8125 network controllers and corresponding +PHYs connected via the PCIe controllers on the OrangePi R2S. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index b13a8d6a2670..919e5b451109 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -23,6 +23,14 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; +@@ -228,6 +236,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0495-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-cpu-sc.patch b/SPECS/linux-lts-kmhv2/0495-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-cpu-sc.patch new file mode 100644 index 0000000000..361f3f6f13 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0495-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-cpu-sc.patch @@ -0,0 +1,79 @@ +From 87828fa45efba06d39fec25170189b42e8678691 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Sun, 14 Jun 2026 14:28:11 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add cpu + scaling + +Enable CPU DVFS by including the OPP table and wiring the CPU nodes to the +CPU regulator supply. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260614122812.2287506-1-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 0d809e4ad3b1..1b425011f123 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -9,6 +9,7 @@ + + #include "k1.dtsi" + #include "k1-pinctrl.dtsi" ++#include "k1-opp.dtsi" + + / { + model = "SpacemiT MusePi Pro"; +@@ -99,6 +100,38 @@ &combo_phy { + status = "okay"; + }; + ++&cpu_0 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_1 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_2 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_3 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_4 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_5 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_6 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_7 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -178,7 +211,7 @@ pmic@41 { + dldoin2-supply = <&buck5>; + + regulators { +- buck1 { ++ buck1_0v9: buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0496-FROMLIST-riscv-dts-spacemit-k3-Enable-SD-card-suppor.patch b/SPECS/linux-lts-kmhv2/0496-FROMLIST-riscv-dts-spacemit-k3-Enable-SD-card-suppor.patch new file mode 100644 index 0000000000..68ec8b1206 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0496-FROMLIST-riscv-dts-spacemit-k3-Enable-SD-card-suppor.patch @@ -0,0 +1,126 @@ +From 0e224d82edfb1ad6ef17f3f40dd9946fe77817dc Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 10 Jun 2026 12:34:32 +0000 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Enable SD card + support + +Add the device tree node of SDHCI-0 controller which found on CoM260-IFX +board, it's currenty used for Micro SD card slot, and one GPIO pin is +configured as card insertion/removal detection pin, the slot use 4-bit +data bus, and up support to SDR104 speed mode. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260610-07-k3-enable-sd-v1-1-196ae29bd091@kernel.org +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 18 ++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 44 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 13 ++++++ + 3 files changed, 75 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +index 238bb03d0e9e..e7f76cd24b90 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -19,3 +19,21 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default","uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K3_GPIO(4) GPIO_ACTIVE_HIGH>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&aldo4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 846d5e8cc783..ee53ab2e7267 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -710,4 +710,48 @@ uart0-0-pins { + drive-strength = <25>; + }; + }; ++ ++ mmc1_cfg: mmc1-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1 dat3 */ ++ , /* mmc1 dat2 */ ++ , /* mmc1 dat1 */ ++ , /* mmc1 dat0 */ ++ ; /* mmc1 cmd */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ power-source = <3300>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1 clk */ ++ ++ bias-pull-down; ++ drive-strength = <25>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ mmc1_uhs_cfg: mmc1-uhs-cfg { ++ mmc1-uhs-data-cmd-pins { ++ pinmux = , /* mmc1 dat3 */ ++ , /* mmc1 dat2 */ ++ , /* mmc1 dat1 */ ++ , /* mmc1 dat0 */ ++ ; /* mmc1 cmd */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ power-source = <1800>; ++ }; ++ ++ mmc1-uhs-clk-pins { ++ pinmux = ; /* mmc1 clk */ ++ ++ bias-pull-down; ++ drive-strength = <21>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 9a49dd8032bf..fc46e34465e4 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1116,6 +1116,19 @@ qspi: spi@d420c000 { + status = "disabled"; + }; + ++ sdhci0: mmc@d4280000 { ++ compatible = "spacemit,k3-sdhci"; ++ reg = <0x0 0xd4280000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_SDH_AXI>, ++ <&syscon_apmu CLK_APMU_SDH0>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_APMU_SDH_AXI>, ++ <&syscon_apmu RESET_APMU_SDH0>; ++ reset-names = "axi", "sdh"; ++ interrupts = <99 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0497-FROMLIST-ACPI-tables-Add-missing-include-asm-fixmap..patch b/SPECS/linux-lts-kmhv2/0497-FROMLIST-ACPI-tables-Add-missing-include-asm-fixmap..patch new file mode 100644 index 0000000000..63da94638c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0497-FROMLIST-ACPI-tables-Add-missing-include-asm-fixmap..patch @@ -0,0 +1,33 @@ +From ecc87e849e81a2541048869d3c89f519e46ebe40 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 16 Jun 2026 21:51:31 +0800 +Subject: [RUYI PATCH] FROMLIST: ACPI: tables: Add missing #include + + +drivers/acpi/tables.c uses NR_FIX_BTMAPS without including +. This isn't a problem for existing archs, but would be +when ARCH_HAS_ACPI_TABLE_UPGRADE is enabled for RISC-V. Add the missing +include. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260616-riscv-acpi-table-upgrade-v1-1-45902d2dedf9@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/acpi/tables.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c +index 57fc8bc56166..c127da7fa32a 100644 +--- a/drivers/acpi/tables.c ++++ b/drivers/acpi/tables.c +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + #include "internal.h" + + #ifdef CONFIG_ACPI_CUSTOM_DSDT +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0498-FROMLIST-riscv-acpi-Enable-ARCH_HAS_ACPI_TABLE_UPGRA.patch b/SPECS/linux-lts-kmhv2/0498-FROMLIST-riscv-acpi-Enable-ARCH_HAS_ACPI_TABLE_UPGRA.patch new file mode 100644 index 0000000000..2a443a53d1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0498-FROMLIST-riscv-acpi-Enable-ARCH_HAS_ACPI_TABLE_UPGRA.patch @@ -0,0 +1,75 @@ +From 8b2fd77b8c90c505e59b00a3437419a7b0a81dd2 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 16 Jun 2026 21:51:32 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: acpi: Enable + ARCH_HAS_ACPI_TABLE_UPGRADE + +Implement the various required hooks and enable +ARCH_HAS_ACPI_TABLE_UPGRADE to allow use for ACPI_TABLE_UPGRADE, which +is useful for debugging ACPI table problems. + +The implementation is based on arm64's of the same feature due to the +similarities of the requirements of the two platforms. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260616-riscv-acpi-table-upgrade-v1-2-45902d2dedf9@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 1 + + arch/riscv/include/asm/acpi.h | 2 ++ + arch/riscv/kernel/acpi.c | 5 +++++ + arch/riscv/kernel/setup.c | 2 ++ + 4 files changed, 10 insertions(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 36112b662884..afdd6f6a05f6 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -24,6 +24,7 @@ config RISCV + select ARCH_ENABLE_MEMORY_HOTREMOVE if MEMORY_HOTPLUG + select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 + select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE ++ select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI + select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CC_CAN_LINK + select ARCH_HAS_CURRENT_STACK_POINTER +diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h +index 6e13695120bc..b0c1f2669335 100644 +--- a/arch/riscv/include/asm/acpi.h ++++ b/arch/riscv/include/asm/acpi.h +@@ -96,4 +96,6 @@ void acpi_map_cpus_to_nodes(void); + static inline void acpi_map_cpus_to_nodes(void) { } + #endif /* CONFIG_ACPI_NUMA */ + ++#define ACPI_TABLE_UPGRADE_MAX_PHYS MEMBLOCK_ALLOC_ACCESSIBLE ++ + #endif /*_ASM_ACPI_H*/ +diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c +index ff681db9f4f1..a9b1d50b0bdd 100644 +--- a/arch/riscv/kernel/acpi.c ++++ b/arch/riscv/kernel/acpi.c +@@ -337,3 +337,8 @@ int raw_pci_write(unsigned int domain, unsigned int bus, + } + + #endif /* CONFIG_PCI */ ++ ++void __init arch_reserve_mem_area(acpi_physical_address addr, size_t size) ++{ ++ memblock_mark_nomap(addr, size); ++} +diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c +index 13b27a078912..36812b984395 100644 +--- a/arch/riscv/kernel/setup.c ++++ b/arch/riscv/kernel/setup.c +@@ -325,6 +325,8 @@ void __init setup_arch(char **cmdline_p) + efi_init(); + paging_init(); + ++ acpi_table_upgrade(); ++ + /* Parse the ACPI tables for possible boot-time configuration */ + acpi_boot_table_init(); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0499-FROMLIST-RISC-V-Add-common-csr_read_num-and-csr_writ.patch b/SPECS/linux-lts-kmhv2/0499-FROMLIST-RISC-V-Add-common-csr_read_num-and-csr_writ.patch new file mode 100644 index 0000000000..78ed4b6bb2 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0499-FROMLIST-RISC-V-Add-common-csr_read_num-and-csr_writ.patch @@ -0,0 +1,349 @@ +From 86bb04caa022348523df07728b024482dc38554e Mon Sep 17 00:00:00 2001 +From: Anup Patel +Date: Wed, 4 Feb 2026 21:23:09 +0530 +Subject: [RUYI PATCH] FROMLIST: RISC-V: Add common csr_read_num() and + csr_write_num() functions + +In RISC-V, there is no CSR read/write instruction which takes CSR +number via register so add common csr_read_num() and csr_write_num() +functions which allow accessing certain CSRs by passing CSR number +as parameter. These common functions will be first used by the +ACPI CPPC driver and RISC-V PMU driver. + +Also, the RISC-V ACPI FFH specification allows arbitrary CSR number +as CPPC register and the RISC-V SBI specification allows arbitrary +CSR number as PMU hardware counter. This means ACPI CPPC driver and +RISC-V PMU driver no longer need to do sanity checks on CSR number +which are now done by the common csr_read_num() and csr_write_num() +functions. + +Signed-off-by: Anup Patel +Reviewed-by: Sunil V L +Reviewed-by: Andrew Jones +Reviewed-by: Atish Patra +Reviewed-by: Nutty Liu +Link: https://lore.kernel.org/r/20260204155309.763597-2-anup.patel@oss.qualcomm.com +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/csr.h | 3 + + arch/riscv/kernel/Makefile | 1 + + arch/riscv/kernel/csr.c | 165 +++++++++++++++++++++++++++++++++++ + drivers/acpi/riscv/cppc.c | 17 ++-- + drivers/perf/riscv_pmu.c | 54 ++---------- + 5 files changed, 184 insertions(+), 56 deletions(-) + create mode 100644 arch/riscv/kernel/csr.c + +diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h +index 4a37a98398ad..543a3364f11d 100644 +--- a/arch/riscv/include/asm/csr.h ++++ b/arch/riscv/include/asm/csr.h +@@ -575,6 +575,9 @@ + : "memory"); \ + }) + ++unsigned long csr_read_num(unsigned long csr_num, int *out_err); ++void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err); ++ + #endif /* __ASSEMBLER__ */ + + #endif /* _ASM_RISCV_CSR_H */ +diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile +index a01f6439d62b..0b9008a6f4e0 100644 +--- a/arch/riscv/kernel/Makefile ++++ b/arch/riscv/kernel/Makefile +@@ -51,6 +51,7 @@ obj-y += soc.o + obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o + obj-y += cpu.o + obj-y += cpufeature.o ++obj-y += csr.o + obj-y += entry.o + obj-y += irq.o + obj-y += process.o +diff --git a/arch/riscv/kernel/csr.c b/arch/riscv/kernel/csr.c +new file mode 100644 +index 000000000000..e96b129c1a99 +--- /dev/null ++++ b/arch/riscv/kernel/csr.c +@@ -0,0 +1,165 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2025 Ventana Micro Systems Inc. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define CSR_CUSTOM0_U_RW_BASE 0x800 ++#define CSR_CUSTOM0_U_RW_COUNT 0x100 ++ ++#define CSR_CUSTOM1_U_RO_BASE 0xCC0 ++#define CSR_CUSTOM1_U_RO_COUNT 0x040 ++ ++#define CSR_CUSTOM2_S_RW_BASE 0x5C0 ++#define CSR_CUSTOM2_S_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM3_S_RW_BASE 0x9C0 ++#define CSR_CUSTOM3_S_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM4_S_RO_BASE 0xDC0 ++#define CSR_CUSTOM4_S_RO_COUNT 0x040 ++ ++#define CSR_CUSTOM5_HS_RW_BASE 0x6C0 ++#define CSR_CUSTOM5_HS_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM6_HS_RW_BASE 0xAC0 ++#define CSR_CUSTOM6_HS_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM7_HS_RO_BASE 0xEC0 ++#define CSR_CUSTOM7_HS_RO_COUNT 0x040 ++ ++#define CSR_CUSTOM8_M_RW_BASE 0x7C0 ++#define CSR_CUSTOM8_M_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM9_M_RW_BASE 0xBC0 ++#define CSR_CUSTOM9_M_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM10_M_RO_BASE 0xFC0 ++#define CSR_CUSTOM10_M_RO_COUNT 0x040 ++ ++unsigned long csr_read_num(unsigned long csr_num, int *out_err) ++{ ++#define switchcase_csr_read(__csr_num) \ ++ case (__csr_num): \ ++ return csr_read(__csr_num) ++#define switchcase_csr_read_2(__csr_num) \ ++ switchcase_csr_read(__csr_num + 0); \ ++ switchcase_csr_read(__csr_num + 1) ++#define switchcase_csr_read_4(__csr_num) \ ++ switchcase_csr_read_2(__csr_num + 0); \ ++ switchcase_csr_read_2(__csr_num + 2) ++#define switchcase_csr_read_8(__csr_num) \ ++ switchcase_csr_read_4(__csr_num + 0); \ ++ switchcase_csr_read_4(__csr_num + 4) ++#define switchcase_csr_read_16(__csr_num) \ ++ switchcase_csr_read_8(__csr_num + 0); \ ++ switchcase_csr_read_8(__csr_num + 8) ++#define switchcase_csr_read_32(__csr_num) \ ++ switchcase_csr_read_16(__csr_num + 0); \ ++ switchcase_csr_read_16(__csr_num + 16) ++#define switchcase_csr_read_64(__csr_num) \ ++ switchcase_csr_read_32(__csr_num + 0); \ ++ switchcase_csr_read_32(__csr_num + 32) ++#define switchcase_csr_read_128(__csr_num) \ ++ switchcase_csr_read_64(__csr_num + 0); \ ++ switchcase_csr_read_64(__csr_num + 64) ++#define switchcase_csr_read_256(__csr_num) \ ++ switchcase_csr_read_128(__csr_num + 0); \ ++ switchcase_csr_read_128(__csr_num + 128) ++ ++ *out_err = 0; ++ switch (csr_num) { ++ switchcase_csr_read_32(CSR_CYCLE); ++ switchcase_csr_read_32(CSR_CYCLEH); ++ switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE); ++#ifdef CONFIG_RISCV_M_MODE ++ switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE); ++#endif ++ default: ++ *out_err = -EINVAL; ++ break; ++ } ++ ++ return 0; ++#undef switchcase_csr_read_256 ++#undef switchcase_csr_read_128 ++#undef switchcase_csr_read_64 ++#undef switchcase_csr_read_32 ++#undef switchcase_csr_read_16 ++#undef switchcase_csr_read_8 ++#undef switchcase_csr_read_4 ++#undef switchcase_csr_read_2 ++#undef switchcase_csr_read ++} ++EXPORT_SYMBOL_GPL(csr_read_num); ++ ++void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err) ++{ ++#define switchcase_csr_write(__csr_num, __val) \ ++ case (__csr_num): \ ++ csr_write(__csr_num, __val); \ ++ break ++#define switchcase_csr_write_2(__csr_num, __val) \ ++ switchcase_csr_write(__csr_num + 0, __val); \ ++ switchcase_csr_write(__csr_num + 1, __val) ++#define switchcase_csr_write_4(__csr_num, __val) \ ++ switchcase_csr_write_2(__csr_num + 0, __val); \ ++ switchcase_csr_write_2(__csr_num + 2, __val) ++#define switchcase_csr_write_8(__csr_num, __val) \ ++ switchcase_csr_write_4(__csr_num + 0, __val); \ ++ switchcase_csr_write_4(__csr_num + 4, __val) ++#define switchcase_csr_write_16(__csr_num, __val) \ ++ switchcase_csr_write_8(__csr_num + 0, __val); \ ++ switchcase_csr_write_8(__csr_num + 8, __val) ++#define switchcase_csr_write_32(__csr_num, __val) \ ++ switchcase_csr_write_16(__csr_num + 0, __val); \ ++ switchcase_csr_write_16(__csr_num + 16, __val) ++#define switchcase_csr_write_64(__csr_num, __val) \ ++ switchcase_csr_write_32(__csr_num + 0, __val); \ ++ switchcase_csr_write_32(__csr_num + 32, __val) ++#define switchcase_csr_write_128(__csr_num, __val) \ ++ switchcase_csr_write_64(__csr_num + 0, __val); \ ++ switchcase_csr_write_64(__csr_num + 64, __val) ++#define switchcase_csr_write_256(__csr_num, __val) \ ++ switchcase_csr_write_128(__csr_num + 0, __val); \ ++ switchcase_csr_write_128(__csr_num + 128, __val) ++ ++ *out_err = 0; ++ switch (csr_num) { ++ switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val); ++#ifdef CONFIG_RISCV_M_MODE ++ switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val); ++#endif ++ default: ++ *out_err = -EINVAL; ++ break; ++ } ++#undef switchcase_csr_write_256 ++#undef switchcase_csr_write_128 ++#undef switchcase_csr_write_64 ++#undef switchcase_csr_write_32 ++#undef switchcase_csr_write_16 ++#undef switchcase_csr_write_8 ++#undef switchcase_csr_write_4 ++#undef switchcase_csr_write_2 ++#undef switchcase_csr_write ++} ++EXPORT_SYMBOL_GPL(csr_write_num); +diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c +index 42c1a9052470..fe491937ed25 100644 +--- a/drivers/acpi/riscv/cppc.c ++++ b/drivers/acpi/riscv/cppc.c +@@ -65,24 +65,19 @@ static void sbi_cppc_write(void *write_data) + static void cppc_ffh_csr_read(void *read_data) + { + struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data; ++ int err; + +- switch (data->reg) { +- /* Support only TIME CSR for now */ +- case CSR_TIME: +- data->ret.value = csr_read(CSR_TIME); +- data->ret.error = 0; +- break; +- default: +- data->ret.error = -EINVAL; +- break; +- } ++ data->ret.value = csr_read_num(data->reg, &err); ++ data->ret.error = err; + } + + static void cppc_ffh_csr_write(void *write_data) + { + struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data; ++ int err; + +- data->ret.error = -EINVAL; ++ csr_write_num(data->reg, data->val, &err); ++ data->ret.error = err; + } + + /* +diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c +index 7644147d50b4..b41f353ba964 100644 +--- a/drivers/perf/riscv_pmu.c ++++ b/drivers/perf/riscv_pmu.c +@@ -16,6 +16,7 @@ + #include + #include + ++#include + #include + + static bool riscv_perf_user_access(struct perf_event *event) +@@ -88,58 +89,21 @@ void arch_perf_update_userpage(struct perf_event *event, + userpg->cap_user_time_short = 1; + } + +-static unsigned long csr_read_num(int csr_num) +-{ +-#define switchcase_csr_read(__csr_num, __val) {\ +- case __csr_num: \ +- __val = csr_read(__csr_num); \ +- break; } +-#define switchcase_csr_read_2(__csr_num, __val) {\ +- switchcase_csr_read(__csr_num + 0, __val) \ +- switchcase_csr_read(__csr_num + 1, __val)} +-#define switchcase_csr_read_4(__csr_num, __val) {\ +- switchcase_csr_read_2(__csr_num + 0, __val) \ +- switchcase_csr_read_2(__csr_num + 2, __val)} +-#define switchcase_csr_read_8(__csr_num, __val) {\ +- switchcase_csr_read_4(__csr_num + 0, __val) \ +- switchcase_csr_read_4(__csr_num + 4, __val)} +-#define switchcase_csr_read_16(__csr_num, __val) {\ +- switchcase_csr_read_8(__csr_num + 0, __val) \ +- switchcase_csr_read_8(__csr_num + 8, __val)} +-#define switchcase_csr_read_32(__csr_num, __val) {\ +- switchcase_csr_read_16(__csr_num + 0, __val) \ +- switchcase_csr_read_16(__csr_num + 16, __val)} +- +- unsigned long ret = 0; +- +- switch (csr_num) { +- switchcase_csr_read_32(CSR_CYCLE, ret) +- switchcase_csr_read_32(CSR_CYCLEH, ret) +- default : +- break; +- } +- +- return ret; +-#undef switchcase_csr_read_32 +-#undef switchcase_csr_read_16 +-#undef switchcase_csr_read_8 +-#undef switchcase_csr_read_4 +-#undef switchcase_csr_read_2 +-#undef switchcase_csr_read +-} +- + /* + * Read the CSR of a corresponding counter. + */ + unsigned long riscv_pmu_ctr_read_csr(unsigned long csr) + { +- if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H || +- (csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) { +- pr_err("Invalid performance counter csr %lx\n", csr); +- return -EINVAL; ++ unsigned long val; ++ int rc; ++ ++ val = csr_read_num(csr, &rc); ++ if (rc) { ++ pr_err("Failed to read performance counter csr %lx (error %d)\n", csr, rc); ++ return rc; + } + +- return csr_read_num(csr); ++ return val; + } + + u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0500-FROMLIST-ACPI-RISC-V-Fix-false-warning-in-cppc_read_.patch b/SPECS/linux-lts-kmhv2/0500-FROMLIST-ACPI-RISC-V-Fix-false-warning-in-cppc_read_.patch new file mode 100644 index 0000000000..3e85fd102d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0500-FROMLIST-ACPI-RISC-V-Fix-false-warning-in-cppc_read_.patch @@ -0,0 +1,70 @@ +From be85392e7c5d19687473ddf28227aa6780bec969 Mon Sep 17 00:00:00 2001 +From: Wang Yechao +Date: Tue, 9 Jun 2026 19:28:56 +0800 +Subject: [RUYI PATCH] FROMLIST: ACPI: RISC-V: Fix false warning in + cppc_read_ffh() for same-CPU reads + +Commit 997c021abc6e ("cpufreq: CPPC: Update FIE arch_freq_scale in +ticks for non-PCC regs") changed the CPPC Frequency Invariance Engine +to read AMU counters directly from the scheduler tick for non-PCC +register spaces (like FFH), instead of deferring to a kthread. This +means cppc_read_ffh() is now called with IRQs disabled from the tick +handler, triggering the warning. + +This is the same fix as commit df6e4ab654dc ("arm64: topology: Fix +false warning in counters_read_on_cpu() for same-CPU reads"). + +Fixes: 997c021abc6e ("cpufreq: CPPC: Update FIE arch_freq_scale in ticks for non-PCC regs") +Signed-off-by: Wang Yechao +Link: https://lore.kernel.org/r/20260609192856874Y8AaPpKL5TnmbgiWI8DI3@zte.com.cn +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/cppc.c | 19 ++++++++++++++----- + 1 file changed, 14 insertions(+), 5 deletions(-) + +diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c +index fe491937ed25..41c23db0223a 100644 +--- a/drivers/acpi/riscv/cppc.c ++++ b/drivers/acpi/riscv/cppc.c +@@ -93,16 +93,19 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val) + { + struct sbi_cppc_data data; + +- if (WARN_ON_ONCE(irqs_disabled())) +- return -EPERM; +- + if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) { + if (!cppc_ext_present) + return -EINVAL; + + data.reg = FFH_CPPC_SBI_REG(reg->address); + +- smp_call_function_single(cpu, sbi_cppc_read, &data, 1); ++ if (irqs_disabled()) { ++ if (WARN_ON_ONCE(cpu != smp_processor_id())) ++ return -EPERM; ++ sbi_cppc_read(&data); ++ } else { ++ smp_call_function_single(cpu, sbi_cppc_read, &data, 1); ++ } + + *val = data.ret.value; + +@@ -110,7 +113,13 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val) + } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) { + data.reg = FFH_CPPC_CSR_NUM(reg->address); + +- smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1); ++ if (irqs_disabled()) { ++ if (WARN_ON_ONCE(cpu != smp_processor_id())) ++ return -EPERM; ++ cppc_ffh_csr_read(&data); ++ } else { ++ smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1); ++ } + + *val = data.ret.value; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0501-FROMLIST-riscv-unaligned-stop-using-kthread-for-chec.patch b/SPECS/linux-lts-kmhv2/0501-FROMLIST-riscv-unaligned-stop-using-kthread-for-chec.patch new file mode 100644 index 0000000000..4d90c36fc8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0501-FROMLIST-riscv-unaligned-stop-using-kthread-for-chec.patch @@ -0,0 +1,95 @@ +From b97a141de17eb9d0d6e48338e2f159e1556ac301 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Wed, 17 Jun 2026 05:38:24 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: unaligned: stop using kthread for + check_vector_unaligned_access() + +A kthread is used to run check_vector_unaligned_access() to optimize boot +time, allowing the kernel to continue booting without waiting for the +unaligned vector speed probe to finish. + +However, this asynchronous approach introduces several complications. +First, the kthread may not complete before a user reads vDSO data, +resulting in incorrect values. This was previously addressed by +commit 5d15d2ad36b0 ("riscv: hwprobe: Fix stale vDSO data for +late-initialized keys at boot"), which added complex synchronization +between the kthread and vDSO reads. + +Second, it was discovered that the kthread may not finish before +vec_check_unaligned_access_speed_all_cpus() (marked with __init) is freed, +triggering a page fault. + +These issues raise the question of whether the kthread is worth the added +complexity. A past boot time regression report was actually unrelated to +synchronous probing; it was caused by the probe running serially. Since +switching to a parallel probe, no further complaints have been made. +Furthermore, the unaligned scalar access speed probe takes the same amount +of time, runs synchronously, and has caused no issues. + +Testing shows no noticeable boot time slowdown when running the vector +probe synchronously (0.464474s with kthread vs. 0.457991s without). + +Remove the kthread usage and run the probe synchronously. This simplifies +the boot flow and allows for the revert of commit 5d15d2ad36b0 ("riscv: +hwprobe: Fix stale vDSO data for late-initialized keys at boot") + +Reported-by: Anirudh Srinivasan +Closes: https://lore.kernel.org/linux-riscv/20260612-vec_unaligned_drop_init-v1-1-df969210ae34@oss.tenstorrent.com/ +Fixes: a00e022be531 ("riscv: Annotate unaligned access init functions") +Cc: stable@vger.kernel.org +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/1c378963f27c5960e8a57c50b8b444d30954cb54.1781666867.git.namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/kernel/unaligned_access_speed.c | 19 ++----------------- + 1 file changed, 2 insertions(+), 17 deletions(-) + +diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c +index 5e224cc48c62..e779fd703730 100644 +--- a/arch/riscv/kernel/unaligned_access_speed.c ++++ b/arch/riscv/kernel/unaligned_access_speed.c +@@ -6,7 +6,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -364,18 +363,9 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus + __free_pages(page, MISALIGNED_BUFFER_ORDER); + } + +-/* Measure unaligned access speed on all CPUs present at boot in parallel. */ +-static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +-{ +- schedule_on_each_cpu(check_vector_unaligned_access); +- riscv_hwprobe_complete_async_probe(); +- +- return 0; +-} + #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ +-static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) ++static void check_vector_unaligned_access(struct work_struct *work __always_unused) + { +- return 0; + } + #endif + +@@ -463,12 +453,7 @@ static int __init check_unaligned_access_all_cpus(void) + per_cpu(vector_misaligned_access, cpu) = unaligned_vector_speed_param; + } else if (!check_vector_unaligned_access_emulated_all_cpus() && + IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { +- riscv_hwprobe_register_async_probe(); +- if (IS_ERR(kthread_run(vec_check_unaligned_access_speed_all_cpus, +- NULL, "vec_check_unaligned_access_speed_all_cpus"))) { +- pr_warn("Failed to create vec_unalign_check kthread\n"); +- riscv_hwprobe_complete_async_probe(); +- } ++ schedule_on_each_cpu(check_vector_unaligned_access); + } + + /* +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0502-FROMLIST-Revert-riscv-hwprobe-Fix-stale-vDSO-data-fo.patch b/SPECS/linux-lts-kmhv2/0502-FROMLIST-Revert-riscv-hwprobe-Fix-stale-vDSO-data-fo.patch new file mode 100644 index 0000000000..ec92abed56 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0502-FROMLIST-Revert-riscv-hwprobe-Fix-stale-vDSO-data-fo.patch @@ -0,0 +1,182 @@ +From e4de9fc60f2d44feef3bf2f2e15fda93f6da4ab7 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Wed, 17 Jun 2026 05:38:25 +0200 +Subject: [RUYI PATCH] FROMLIST: Revert "riscv: hwprobe: Fix stale vDSO data + for late-initialized keys at boot" + +This reverts commit 5d15d2ad36b0 ("riscv: hwprobe: Fix stale vDSO data for +late-initialized keys at boot"). The commit ensures synchronization between +the unaligned vector access speed probe kthread and vDSO data read. But now +that the kthread has been removed, this commit can be reverted. + +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/50ca78a649faf53f8941bc94c9cf8268b3644d38.1781666867.git.namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/hwprobe.h | 7 --- + arch/riscv/include/asm/vdso/arch_data.h | 6 --- + arch/riscv/kernel/sys_hwprobe.c | 70 +++++-------------------- + arch/riscv/kernel/vdso/hwprobe.c | 2 +- + 4 files changed, 13 insertions(+), 72 deletions(-) + +diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h +index 58f8dda73259..948d2b34e94e 100644 +--- a/arch/riscv/include/asm/hwprobe.h ++++ b/arch/riscv/include/asm/hwprobe.h +@@ -42,11 +42,4 @@ static inline bool riscv_hwprobe_pair_cmp(struct riscv_hwprobe *pair, + return pair->value == other_pair->value; + } + +-#ifdef CONFIG_MMU +-void riscv_hwprobe_register_async_probe(void); +-void riscv_hwprobe_complete_async_probe(void); +-#else +-static inline void riscv_hwprobe_register_async_probe(void) {} +-static inline void riscv_hwprobe_complete_async_probe(void) {} +-#endif + #endif +diff --git a/arch/riscv/include/asm/vdso/arch_data.h b/arch/riscv/include/asm/vdso/arch_data.h +index 88b37af55175..da57a3786f7a 100644 +--- a/arch/riscv/include/asm/vdso/arch_data.h ++++ b/arch/riscv/include/asm/vdso/arch_data.h +@@ -12,12 +12,6 @@ struct vdso_arch_data { + + /* Boolean indicating all CPUs have the same static hwprobe values. */ + __u8 homogeneous_cpus; +- +- /* +- * A gate to check and see if the hwprobe data is actually ready, as +- * probing is deferred to avoid boot slowdowns. +- */ +- __u8 ready; + }; + + #endif /* __RISCV_ASM_VDSO_ARCH_DATA_H */ +diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c +index 199d13f86f31..ded80da10678 100644 +--- a/arch/riscv/kernel/sys_hwprobe.c ++++ b/arch/riscv/kernel/sys_hwprobe.c +@@ -5,9 +5,6 @@ + * more details. + */ + #include +-#include +-#include +-#include + #include + #include + #include +@@ -463,32 +460,28 @@ static int hwprobe_get_cpus(struct riscv_hwprobe __user *pairs, + return 0; + } + +-#ifdef CONFIG_MMU +- +-static DECLARE_COMPLETION(boot_probes_done); +-static atomic_t pending_boot_probes = ATOMIC_INIT(1); +- +-void riscv_hwprobe_register_async_probe(void) ++static int do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, ++ size_t pair_count, size_t cpusetsize, ++ unsigned long __user *cpus_user, ++ unsigned int flags) + { +- atomic_inc(&pending_boot_probes); +-} ++ if (flags & RISCV_HWPROBE_WHICH_CPUS) ++ return hwprobe_get_cpus(pairs, pair_count, cpusetsize, ++ cpus_user, flags); + +-void riscv_hwprobe_complete_async_probe(void) +-{ +- if (atomic_dec_and_test(&pending_boot_probes)) +- complete(&boot_probes_done); ++ return hwprobe_get_values(pairs, pair_count, cpusetsize, ++ cpus_user, flags); + } + +-static int complete_hwprobe_vdso_data(void) ++#ifdef CONFIG_MMU ++ ++static int __init init_hwprobe_vdso_data(void) + { + struct vdso_arch_data *avd = vdso_k_arch_data; + u64 id_bitsmash = 0; + struct riscv_hwprobe pair; + int key; + +- if (unlikely(!atomic_dec_and_test(&pending_boot_probes))) +- wait_for_completion(&boot_probes_done); +- + /* + * Initialize vDSO data with the answers for the "all CPUs" case, to + * save a syscall in the common case. +@@ -516,52 +509,13 @@ static int complete_hwprobe_vdso_data(void) + * vDSO should defer to the kernel for exotic cpu masks. + */ + avd->homogeneous_cpus = id_bitsmash != 0 && id_bitsmash != -1; +- +- /* +- * Make sure all the VDSO values are visible before we look at them. +- * This pairs with the implicit "no speculativly visible accesses" +- * barrier in the VDSO hwprobe code. +- */ +- smp_wmb(); +- avd->ready = true; +- return 0; +-} +- +-static int __init init_hwprobe_vdso_data(void) +-{ +- struct vdso_arch_data *avd = vdso_k_arch_data; +- +- /* +- * Prevent the vDSO cached values from being used, as they're not ready +- * yet. +- */ +- avd->ready = false; + return 0; + } + + arch_initcall_sync(init_hwprobe_vdso_data); + +-#else +- +-static int complete_hwprobe_vdso_data(void) { return 0; } +- + #endif /* CONFIG_MMU */ + +-static int do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, +- size_t pair_count, size_t cpusetsize, +- unsigned long __user *cpus_user, +- unsigned int flags) +-{ +- DO_ONCE_SLEEPABLE(complete_hwprobe_vdso_data); +- +- if (flags & RISCV_HWPROBE_WHICH_CPUS) +- return hwprobe_get_cpus(pairs, pair_count, cpusetsize, +- cpus_user, flags); +- +- return hwprobe_get_values(pairs, pair_count, cpusetsize, +- cpus_user, flags); +-} +- + SYSCALL_DEFINE5(riscv_hwprobe, struct riscv_hwprobe __user *, pairs, + size_t, pair_count, size_t, cpusetsize, unsigned long __user *, + cpus, unsigned int, flags) +diff --git a/arch/riscv/kernel/vdso/hwprobe.c b/arch/riscv/kernel/vdso/hwprobe.c +index 8f45500d0a6e..2ddeba6c68dd 100644 +--- a/arch/riscv/kernel/vdso/hwprobe.c ++++ b/arch/riscv/kernel/vdso/hwprobe.c +@@ -27,7 +27,7 @@ static int riscv_vdso_get_values(struct riscv_hwprobe *pairs, size_t pair_count, + * homogeneous, then this function can handle requests for arbitrary + * masks. + */ +- if (flags != 0 || (!all_cpus && !avd->homogeneous_cpus) || unlikely(!avd->ready)) ++ if ((flags != 0) || (!all_cpus && !avd->homogeneous_cpus)) + return riscv_hwprobe(pairs, pair_count, cpusetsize, cpus, flags); + + /* This is something we can handle, fill out the pairs. */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0503-FROMLIST-riscv-uaccess-Add-a-fast-path-for-small-ali.patch b/SPECS/linux-lts-kmhv2/0503-FROMLIST-riscv-uaccess-Add-a-fast-path-for-small-ali.patch new file mode 100644 index 0000000000..623bca7113 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0503-FROMLIST-riscv-uaccess-Add-a-fast-path-for-small-ali.patch @@ -0,0 +1,79 @@ +From e7d6a964039535c0d255b5f04106a0146360db63 Mon Sep 17 00:00:00 2001 +From: Yunhui Cui +Date: Tue, 23 Jun 2026 16:35:51 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: uaccess: Add a fast path for small + aligned copies + +The scalar user copy routine currently enters the word-copy path only +for copies of at least 9 * SZREG - 1 bytes. On RV64 this is 71 bytes, +so common 32-byte and 64-byte aligned user/kernel copies fall back to +byte-by-byte copying. + +Add a small-copy word path for copies below that threshold when both +source and destination are SZREG-aligned. Unaligned and sub-word copies +keep using the existing byte-copy path, and larger copies keep using the +existing large-copy paths. + +This is a generic usercopy improvement. One common case is Linux AIO: +io_getevents() copies 32-byte struct io_event objects to userspace, and +io_submit() copies 64-byte struct iocb objects from userspace. + +fio libaio randrw three-run averages improved: + + baseline: read 560k IOPS, write 240k IOPS, sys 68.60% + this patch: read 593k IOPS, write 254k IOPS, sys 69.03% + +This is about +5.8% read IOPS and +5.5% write IOPS. + +lmbench bw_pipe with small messages was also improved: + + bw_pipe -m -M 16m -W 1 -N 5 + + size baseline MB/s this patch MB/s change + 32 62.52 74.54 +19.2% + 64 122.57 155.31 +26.7% + +Signed-off-by: Yunhui Cui +Link: https://lore.kernel.org/r/20260623083551.86021-1-cuiyunhui@bytedance.com +Signed-off-by: Han Gao +--- + arch/riscv/lib/uaccess.S | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S +index 4efea1b3326c..2d78007f10d0 100644 +--- a/arch/riscv/lib/uaccess.S ++++ b/arch/riscv/lib/uaccess.S +@@ -70,12 +70,27 @@ SYM_FUNC_START(fallback_scalar_usercopy_sum_enabled) + add t0, a0, a2 + + /* +- * Use byte copy only if too small. +- * SZREG holds 4 for RV32 and 8 for RV64 ++ * For small copies below the large-copy threshold, use word-copy if ++ * both src and dst are naturally aligned. Unaligned or sub-word copies ++ * are left to the byte-copy tail. + */ + li a3, 9*SZREG-1 /* size must >= (word_copy stride + SZREG-1) */ ++ bgeu a2, a3, .Llarge_copy_user ++ li a3, SZREG + bltu a2, a3, .Lbyte_copy_tail ++ or a3, a0, a1 ++ andi a3, a3, SZREG-1 ++ bnez a3, .Lbyte_copy_tail ++ andi t1, t0, ~(SZREG-1) ++5: ++ fixup REG_L a5, 0(a1), 10f ++ addi a1, a1, SZREG ++ fixup REG_S a5, 0(a0), 10f ++ addi a0, a0, SZREG ++ bltu a0, t1, 5b ++ j .Lbyte_copy_tail + ++.Llarge_copy_user: + /* + * Copy first bytes until dst is aligned to word boundary. + * a0 - start of dst +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0504-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0504-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..82dfdd5e6e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0504-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,35 @@ +From 10909b4ca532268892e712654aa65d5c1a32d141 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:45 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + K3 Pico-ITX board + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +Fixes: 7a6131804986 ("riscv: dts: spacemit: add K3 Pico-ITX board support") +Signed-off-by: Aurelien Jarno +Reviewed-by: Guodong Xu +Link: https://lore.kernel.org/r/20260623204431.498700-2-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index fd2b154f275a..7f2236104490 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -18,7 +18,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + memory@100000000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0505-FROMLIST-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch b/SPECS/linux-lts-kmhv2/0505-FROMLIST-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch new file mode 100644 index 0000000000..9f96a9df66 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0505-FROMLIST-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch @@ -0,0 +1,59 @@ +From 56ea79d330bdf3403632db83e4d2c9e97502472b Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:46 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable the i2c2 adapter + on K3 Pico-ITX board + +Define I2C2 pinctrl properties, and enable it on the K3 Pico-ITX board. +It will be used by the 24c02 eeprom. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-3-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 6 ++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 +++++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 7f2236104490..20848a5d2f9c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -43,6 +43,12 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + }; + }; + ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_1_cfg>; ++ status = "okay"; ++}; ++ + &i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index ee53ab2e7267..5b9045e01434 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -78,6 +78,17 @@ gmac1-phy-0-pins { + }; + }; + ++ /omit-if-no-ref/ ++ i2c2_1_cfg: i2c2-1-cfg { ++ i2c2-1-pins { ++ pinmux = , /* i2c2 scl */ ++ ; /* i2c2 sda */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0506-FROMLIST-riscv-dts-spacemit-add-24c02-eeprom-on-K3-P.patch b/SPECS/linux-lts-kmhv2/0506-FROMLIST-riscv-dts-spacemit-add-24c02-eeprom-on-K3-P.patch new file mode 100644 index 0000000000..2e935a2df0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0506-FROMLIST-riscv-dts-spacemit-add-24c02-eeprom-on-K3-P.patch @@ -0,0 +1,65 @@ +From af4a9c8c6fd1ae4bd0153f3136b839aa54e274d5 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:47 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add 24c02 eeprom on K3 + Pico-ITX board + +The K3 Pico-ITX board includes a 24c02 eeprom, that stores the product +name, the part name, the MAC address of the network interfaces and the +board's serial number. These values are also exposed via an +onie,tlv-layout nvmem layout. + +The eeprom is marked as read-only since its contents are not supposed to +be modified. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-4-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 30 ++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 20848a5d2f9c..85dd87a4381e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -47,6 +47,36 @@ &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_cfg>; + status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <8>; ++ read-only; ++ size = <256>; ++ status = "okay"; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ mac-address { ++ #nvmem-cell-cells = <1>; ++ }; ++ ++ num-macs { ++ }; ++ ++ part-number { ++ }; ++ ++ product-name { ++ }; ++ ++ serial-number { ++ }; ++ ++ }; ++ }; + }; + + &i2c8 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0507-FROMLIST-riscv-dts-spacemit-add-i2c-aliases-on-K3-Pi.patch b/SPECS/linux-lts-kmhv2/0507-FROMLIST-riscv-dts-spacemit-add-i2c-aliases-on-K3-Pi.patch new file mode 100644 index 0000000000..f004f94324 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0507-FROMLIST-riscv-dts-spacemit-add-i2c-aliases-on-K3-Pi.patch @@ -0,0 +1,33 @@ +From 843267f7efa94a4497127b96b58f4b4b7460a459 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:48 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add i2c aliases on K3 + Pico-ITX board + +Add i2c aliases for i2c2 and i2c8 on K3 Pico-ITX board. This is useful +to keep a stable number for the /dev entries after loading the i2c-dev +module. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-5-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 85dd87a4381e..a07db9853ad8 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -14,6 +14,8 @@ / { + + aliases { + ethernet0 = ð0; ++ i2c2 = &i2c2; ++ i2c8 = &i2c8; + serial0 = &uart0; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0508-FROMLIST-riscv-dts-spacemit-improve-RTL8211F-PHY-con.patch b/SPECS/linux-lts-kmhv2/0508-FROMLIST-riscv-dts-spacemit-improve-RTL8211F-PHY-con.patch new file mode 100644 index 0000000000..045ad597bc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0508-FROMLIST-riscv-dts-spacemit-improve-RTL8211F-PHY-con.patch @@ -0,0 +1,36 @@ +From 6019cef4db7227082c278bbf6663364aa65fb0e4 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:49 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: improve RTL8211F PHY + configuration on K3 Pico-ITX board + +Vendor kernel enabled ALDPS (Advanced Link Down Power Saving) on the +RTL8211F PHY to save power when link down. + +Vendor kernel also disabled the 125MHz clkout clock signal, and indeed +the schematics confirms that it only goes to a test point (TP14), so +let's do the same. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-6-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index a07db9853ad8..8b2a120b02d1 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -234,6 +234,8 @@ phy0: phy@1 { + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; ++ realtek,aldps-enable; ++ realtek,clkout-disable; + }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0509-FROMLIST-arch-riscv-vdso-remove-CFI-landing-pad-from.patch b/SPECS/linux-lts-kmhv2/0509-FROMLIST-arch-riscv-vdso-remove-CFI-landing-pad-from.patch new file mode 100644 index 0000000000..be88a3c33d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0509-FROMLIST-arch-riscv-vdso-remove-CFI-landing-pad-from.patch @@ -0,0 +1,52 @@ +From 60703b7dd0916fb50ad7c9a9a07ca3a4738c1741 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:40:57 +0200 +Subject: [RUYI PATCH] FROMLIST: arch/riscv: vdso: remove CFI landing pad from + rt_sigreturn + +When CONFIG_RISCV_USER_CFI is enabled, the CFI version of the vDSO, has +a CFI landing pad instruction at the start of __vdso_rt_sigreturn. This +breaks libgcc's unwinding code which matches on the first two +instructions. Other unwinders that rely on similar instruction matching +may also be affected. + +Since __vdso_rt_sigreturn is reached as part of signal-return handling +rather than via an indirect call/jump from userspace, it does not need a +CFI landing pad. Remove it and restore the instruction sequence expected +by existing unwinding code. + +This matches what was done on arm64 in commit 9a964285572b ("arm64: +vdso: Don't prefix sigreturn trampoline with a BTI C instruction") for a +similar issue. + +Fixes: 37f57bd3faea ("arch/riscv: compile vdso with landing pad and shadow stack note") +Co-authored-by: Joel Stanley +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204058.498120-1-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/kernel/vdso/rt_sigreturn.S | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/kernel/vdso/rt_sigreturn.S b/arch/riscv/kernel/vdso/rt_sigreturn.S +index 3dc022aa8931..43e0c1607271 100644 +--- a/arch/riscv/kernel/vdso/rt_sigreturn.S ++++ b/arch/riscv/kernel/vdso/rt_sigreturn.S +@@ -6,6 +6,14 @@ + #include + #include + ++/* WARNING: Do NOT add a CFI landing pad at the start of this function. ++ * Unwinders such as libgcc identify the sigreturn trampoline by matching the ++ * instruction sequence. Adding a landing pad here would break unwinding from ++ * signal handlers. ++ * ++ * This trampoline is used only for signal return and not via an indirect ++ * call/jump from userspace, so adding CFI landing pad is unnecessary. ++ */ + .text + SYM_FUNC_START(__vdso_rt_sigreturn) + .cfi_startproc +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0510-FROMLIST-dt-bindings-vendor-prefixes-add-Rongda.patch b/SPECS/linux-lts-kmhv2/0510-FROMLIST-dt-bindings-vendor-prefixes-add-Rongda.patch new file mode 100644 index 0000000000..b46bdc466e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0510-FROMLIST-dt-bindings-vendor-prefixes-add-Rongda.patch @@ -0,0 +1,33 @@ +From d6a4700e9c8a801dd4c9c247fa9416bf6bdc2ca4 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:17:57 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: vendor-prefixes: add Rongda + +Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. + +Link: http://www.shenrongda.com/ + +Signed-off-by: Jia Wang +Link: http://www.shenrongda.com/ +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-1-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index d03f700d178e..4ba63daade2d 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -1355,6 +1355,8 @@ patternProperties: + description: Rockchip Electronics Co., Ltd. + "^rocktech,.*": + description: ROCKTECH DISPLAYS LIMITED ++ "^rongda,.*": ++ description: Shenzhen Rongda Computer Co., Ltd. + "^rohm,.*": + description: ROHM Semiconductor Co., Ltd + "^ronbo,.*": +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0511-FROMLIST-dt-bindings-riscv-cpus-Add-UltraRISC-CP100-.patch b/SPECS/linux-lts-kmhv2/0511-FROMLIST-dt-bindings-riscv-cpus-Add-UltraRISC-CP100-.patch new file mode 100644 index 0000000000..1c4d5dbc91 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0511-FROMLIST-dt-bindings-riscv-cpus-Add-UltraRISC-CP100-.patch @@ -0,0 +1,33 @@ +From e1f510725851ec21d732d9546f8faa3e98c53bce Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:17:58 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: cpus: Add UltraRISC CP100 + compatible + +Update Documentation for supporting UltraRISC CP100 based CPU. + +CP100 is used in UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-2-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml +index a86819565394..3fdd3571436d 100644 +--- a/Documentation/devicetree/bindings/riscv/cpus.yaml ++++ b/Documentation/devicetree/bindings/riscv/cpus.yaml +@@ -66,6 +66,7 @@ properties: + - thead,c908 + - thead,c910 + - thead,c920 ++ - ultrarisc,cp100 + - const: riscv + - items: + - enum: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0512-FROMLIST-dt-bindings-riscv-Add-UltraRISC-DP1000-bind.patch b/SPECS/linux-lts-kmhv2/0512-FROMLIST-dt-bindings-riscv-Add-UltraRISC-DP1000-bind.patch new file mode 100644 index 0000000000..f1bb7708cb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0512-FROMLIST-dt-bindings-riscv-Add-UltraRISC-DP1000-bind.patch @@ -0,0 +1,70 @@ +From 8edb9581c7e088b0f3cbf5fa05c58a74f2c5ca6c Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:17:59 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: Add UltraRISC DP1000 + bindings + +Add DT binding documentation for the UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-3-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/ultrarisc.yaml | 27 +++++++++++++++++++ + MAINTAINERS | 6 +++++ + 2 files changed, 33 insertions(+) + create mode 100644 Documentation/devicetree/bindings/riscv/ultrarisc.yaml + +diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml +new file mode 100644 +index 000000000000..d4421c2ef945 +--- /dev/null ++++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml +@@ -0,0 +1,27 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: UltraRISC SoC-based boards ++ ++maintainers: ++ - Jia Wang ++ ++description: ++ UltraRISC DP1000 SoC-based boards ++ ++properties: ++ $nodename: ++ const: '/' ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - rongda,m0 ++ - milkv,titan ++ - const: ultrarisc,dp1000 ++ ++additionalProperties: true ++... +diff --git a/MAINTAINERS b/MAINTAINERS +index a3bc23926943..968133ea82e8 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -22249,6 +22249,12 @@ F: include/dt-bindings/power/thead,th1520-power.h + F: include/dt-bindings/reset/thead,th1520-reset.h + F: include/linux/firmware/thead/thead,th1520-aon.h + ++RISC-V ULTRARISC SoC SUPPORT ++M: Jia Wang ++L: linux-riscv@lists.infradead.org ++S: Maintained ++F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml ++ + RNBD BLOCK DRIVERS + M: Md. Haris Iqbal + M: Jack Wang +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0513-FROMLIST-riscv-dts-ultrarisc-Add-initial-device-tree.patch b/SPECS/linux-lts-kmhv2/0513-FROMLIST-riscv-dts-ultrarisc-Add-initial-device-tree.patch new file mode 100644 index 0000000000..de08316483 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0513-FROMLIST-riscv-dts-ultrarisc-Add-initial-device-tree.patch @@ -0,0 +1,900 @@ +From 8b23e4334dc19b856bff57963fb1a51a19141823 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:01 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: ultrarisc: Add initial device tree + for UltraRISC DP1000 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add the base device tree for the UltraRISC DP1000 SoC. It describes the +8×CP100 CPU cores and essential SoC peripherals including the interrupt +controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC and the DMA +controller. + +Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/ +Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/ + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/ +Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/ +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-5-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + MAINTAINERS | 1 + + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 851 ++++++++++++++++++++++ + 2 files changed, 852 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dtsi + +diff --git a/MAINTAINERS b/MAINTAINERS +index 968133ea82e8..d774f0f29f70 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -22254,6 +22254,7 @@ M: Jia Wang + L: linux-riscv@lists.infradead.org + S: Maintained + F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml ++F: arch/riscv/boot/dts/ultrarisc/ + + RNBD BLOCK DRIVERS + M: Md. Haris Iqbal +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +new file mode 100644 +index 000000000000..1aae53fc1a2b +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -0,0 +1,851 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ compatible = "ultrarisc,dp1000"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <10000000>; ++ ++ cpu0: cpu@0 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x0>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache0>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache0: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu1: cpu@1 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x1>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache1>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu1_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache1: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu2: cpu@2 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x2>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache2>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu2_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache2: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu3: cpu@3 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x3>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache3>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu3_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache3: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu4: cpu@4 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x10>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache4>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu4_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache4: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ cpu5: cpu@5 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x11>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache5>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu5_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache5: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ cpu6: cpu@6 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x12>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache6>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu6_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache6: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu7: cpu@7 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x13>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache7>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu7_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache7: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0: cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ }; ++ ++ cluster1: cluster1 { ++ core0 { ++ cpu = <&cpu4>; ++ }; ++ ++ core1 { ++ cpu = <&cpu5>; ++ }; ++ ++ core2 { ++ cpu = <&cpu6>; ++ }; ++ ++ core3 { ++ cpu = <&cpu7>; ++ }; ++ }; ++ }; ++ ++ cluster0_l3: l3-cache0 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ ++ cluster1_l3: l3-cache1 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; ++ ++ clocks { ++ device_clk: device_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <62500000>; ++ #clock-cells = <0>; ++ }; ++ ++ timer_clk: timer_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ #clock-cells = <0>; ++ }; ++ ++ csr_clk: csr_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <250000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ l4_cache: l4-cache { ++ /* L4 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 16MB ++ * shared by the SoC. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <4>; ++ cache-size = <0x1000000>; ++ cache-sets = <0x4000>; ++ cache-unified; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x00 0x80000000 0x4 0x00000000>; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ ranges; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ++ clint: clint@8000000 { ++ compatible = "sifive,clint0", "riscv,clint0"; ++ reg = <0x00 0x8000000 0x00 0x100000>; ++ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ }; ++ ++ plic: plic@9000000 { ++ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; ++ reg = <0x00 0x9000000 0x00 0x4000000>; ++ #interrupt-cells = <1>; ++ #address-cells = <0>; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ riscv,ndev = <160>; ++ }; ++ ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #pinctrl-cells = <2>; ++ }; ++ ++ gpio: gpio@20200000 { ++ compatible = "snps,dw-apb-gpio"; ++ reg = <0x0 0x20200000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-names = "bus", "db"; ++ clocks = <&csr_clk>, <&device_clk>; ++ ++ gpio_a: gpio-port@0 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <16>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <&plic>; ++ interrupts = <34>; ++ gpio-ranges = <&pmx0 0 0 16>; ++ }; ++ ++ gpio_b: gpio-port@1 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <1>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 16 0 8>; ++ }; ++ ++ gpio_c: gpio-port@2 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 24 0 8>; ++ }; ++ ++ gpio_d: gpio-port@3 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <3>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 32 0 8>; ++ }; ++ }; ++ ++ uart0: serial@20300000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20300000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <17>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart1: serial@20310000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20310000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <18>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart2: serial@20400000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20400000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <25>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart3: serial@20410000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20410000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <26>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ spi0: spi@20320000 { ++ compatible = "snps,dw-apb-ssi"; ++ reg = <0x0 0x20320000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <19>; ++ num-cs = <3>; ++ }; ++ ++ spi1: spi@20420000 { ++ compatible = "snps,dw-apb-ssi"; ++ reg = <0x0 0x20420000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <27>; ++ num-cs = <3>; ++ }; ++ ++ i2c0: i2c@20330000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20330000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <20>; ++ }; ++ ++ i2c1: i2c@20340000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20340000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <21>; ++ }; ++ ++ i2c2: i2c@20430000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20430000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <28>; ++ }; ++ ++ i2c3: i2c@20440000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20440000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <29>; ++ }; ++ ++ pcie_x16: pcie@21000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x21000000 0x0 0x01000000>, ++ <0x0 0x4fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ ++ pcie_x4a: pcie@23000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x23000000 0x0 0x01000000>, ++ <0x0 0x6fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <63>, <64>, <65>, <66>, <67>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, ++ <0x0 0x0 0x0 0x2 &plic 65>, ++ <0x0 0x0 0x0 0x3 &plic 66>, ++ <0x0 0x0 0x0 0x4 &plic 67>; ++ }; ++ ++ pcie_x4b: pcie@24000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x24000000 0x0 0x01000000>, ++ <0x0 0x7fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <73>, <74>, <75>, <76>, <77>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, ++ <0x0 0x0 0x0 0x2 &plic 75>, ++ <0x0 0x0 0x0 0x3 &plic 76>, ++ <0x0 0x0 0x0 0x4 &plic 77>; ++ }; ++ ++ ethernet: ethernet@38000000 { ++ compatible = "snps,dwmac", "snps,dwmac-5.10a"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ interrupt-parent = <&plic>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ local-mac-address = [ff ff ff ff ff ff]; ++ max-speed = <1000>; ++ phy-mode = "rgmii-id"; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ }; ++ ++ dmac: dma-controller@39000000 { ++ compatible = "snps,axi-dma-1.01a"; ++ reg = <0x0 0x39000000 0x0 0x400>; ++ clocks = <&device_clk>, <&device_clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ #dma-cells = <1>; ++ dma-channels = <8>; ++ interrupt-parent = <&plic>; ++ interrupts = <152>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <512 512 512 512 512 512 512 512>; ++ snps,priority = <0 1 2 3 4 5 6 7>; ++ snps,axi-max-burst-len = <256>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0514-FROMLIST-riscv-dts-ultrarisc-add-Rongda-M0-board-dev.patch b/SPECS/linux-lts-kmhv2/0514-FROMLIST-riscv-dts-ultrarisc-add-Rongda-M0-board-dev.patch new file mode 100644 index 0000000000..83a8b6fe7e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0514-FROMLIST-riscv-dts-ultrarisc-add-Rongda-M0-board-dev.patch @@ -0,0 +1,249 @@ +From 351dafdb70244bb991776985260367ade2579893 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:03 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: ultrarisc: add Rongda M0 board + device tree + +Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-7-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/Makefile | 1 + + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + + .../ultrarisc/dp1000-rongda-m0-pinctrl.dtsi | 85 ++++++++++++++ + .../boot/dts/ultrarisc/dp1000-rongda-m0.dts | 111 ++++++++++++++++++ + 4 files changed, 199 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts + +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index 3763d199c70a..297b30243037 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -10,3 +10,4 @@ subdir-y += sophgo + subdir-y += spacemit + subdir-y += starfive + subdir-y += thead ++subdir-y += ultrarisc +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +new file mode 100644 +index 000000000000..d01a770d3cba +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi +new file mode 100644 +index 000000000000..101b416b1079 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0-pins { ++ pins = "PA12", "PA13"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c1_pins: i2c1-pins { ++ pins = "PB6", "PB7"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c2_pins: i2c2-pins { ++ pins = "PC0", "PC1"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c3_pins: i2c3-pins { ++ pins = "PC2", "PC3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ pciex4a_link_pins: pciex4a-link-pins { ++ pins = "PC0"; ++ function = "func1"; ++ bias-pull-down; ++ drive-strength = <33>; ++ }; ++ ++ pciex4b_link_pins: pciex4b-link-pins { ++ pins = "PC1"; ++ function = "func1"; ++ bias-pull-down; ++ drive-strength = <33>; ++ }; ++ ++ spi0_pins: spi0-pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ spi1_pins: spi1-pins { ++ pins = "PA0", "PA1", "PA2", "PA3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart0_pins: uart0-pins { ++ pins = "PA8", "PA9"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart1_pins: uart1-pins { ++ pins = "PB4", "PB5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart2_pins: uart2-pins { ++ pins = "PC4", "PC5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts +new file mode 100644 +index 000000000000..6f72d60ad55e +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts +@@ -0,0 +1,111 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-rongda-m0-pinctrl.dtsi" ++#include ++ ++/ { ++ model = "Rongda M0 Board"; ++ compatible = "rongda,m0", "ultrarisc,dp1000"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio_b 0 GPIO_ACTIVE_HIGH>; ++ active-delay-ms = <100>; ++ ++ status = "disabled"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&gpio_b 1 GPIO_ACTIVE_HIGH>; ++ active-delay = <100>; ++ ++ status = "disabled"; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@32 { ++ compatible = "whwave,sd3078"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++ðernet { ++ phy-handle = <&phy0>; ++ /* ++ * YT8531 RGMII timing on this board requires no PHY internal delays. ++ * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX CRC ++ * errors and no usable traffic, so keep plain "rgmii" here. ++ */ ++ phy-mode = "rgmii"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy0: phy@0 { ++ reg = <0x00>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0515-FROMLIST-riscv-dts-ultrarisc-add-Milk-V-Titan-board-.patch b/SPECS/linux-lts-kmhv2/0515-FROMLIST-riscv-dts-ultrarisc-add-Milk-V-Titan-board-.patch new file mode 100644 index 0000000000..814ab91e9e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0515-FROMLIST-riscv-dts-ultrarisc-add-Milk-V-Titan-board-.patch @@ -0,0 +1,331 @@ +From 22c65ac67825963cc9cd853c1df59117ec1f96b1 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:04 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: ultrarisc: add Milk-V Titan board + device tree + +Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-8-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 + + .../ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 107 ++++++++++ + .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 182 ++++++++++++++++++ + 3 files changed, 290 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index d01a770d3cba..9c27256a2f67 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi +new file mode 100644 +index 000000000000..053206190ec7 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi +@@ -0,0 +1,107 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0-pins { ++ pins = "PA12", "PA13"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c1_pins: i2c1-pins { ++ pins = "PB6", "PB7"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c2_pins: i2c2-pins { ++ pins = "PC0", "PC1"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c3_pins: i2c3-pins { ++ pins = "PC2", "PC3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ io_pins: io-pins { ++ pins = "PA10", "PA15", "PB0", "PB1", "PB2", "PD6", "PD7"; ++ function = "gpio"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ gpio_keys_pins: gpio-keys-pins { ++ pins = "PA4", "PA11", "PA14"; ++ function = "gpio"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ mux_dcdc_pins: mux-dcdc-pins { ++ pins = "PA5"; ++ function = "gpio"; ++ }; ++ ++ mux_i2c3_pins: mux-i2c3-pins { ++ pins = "PA6"; ++ function = "gpio"; ++ }; ++ ++ mux_uart0_pins: mux-uart0-pins { ++ pins = "PA7"; ++ function = "gpio"; ++ }; ++ ++ spi0_pins: spi0-pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ spi1_pins: spi1-pins { ++ pins = "PA0", "PA1", "PA2", "PA3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart0_pins: uart0-pins { ++ pins = "PA8", "PA9"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart1_pins: uart1-pins { ++ pins = "PB4", "PB5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart2_pins: uart2-pins { ++ pins = "PC4", "PC5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart3_pins: uart3-pins { ++ pins = "PC6", "PC7"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts +new file mode 100644 +index 000000000000..21d85c03abe1 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts +@@ -0,0 +1,182 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-milkv-titan-pinctrl.dtsi" ++#include ++#include ++#include ++#include ++ ++/ { ++ model = "Milk-V Titan"; ++ compatible = "milkv,titan", "ultrarisc,dp1000"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio_b 0 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ ++ status = "disabled"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&gpio_b 1 GPIO_ACTIVE_LOW>; ++ active-delay = <100>; ++ ++ status = "disabled"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio_keys_pins>; ++ ++ key-wakeup-0 { ++ label = "Wake-Up"; ++ gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ ++ key-wakeup-1 { ++ label = "Power"; ++ gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ ++ key-wakeup-2 { ++ label = "Wake-Up-by-USB"; ++ gpios = <&gpio_a 4 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@68 { ++ compatible = "st,m41t11"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++}; ++ ++&gpio { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&io_pins &mux_dcdc_pins &mux_i2c3_pins &mux_uart0_pins>; ++}; ++ ++ðernet { ++ phy-handle = <&phy0>; ++ /* ++ * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii". ++ * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic. ++ */ ++ phy-mode = "rgmii"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy0: phy@0 { ++ reg = <0x00>; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@1 { ++ label = "eth-link"; ++ reg = <0x01>; ++ color = ; ++ function = LED_FUNCTION_INDICATOR; ++ default-state = "keep"; ++ linux,default-trigger = "netdev"; ++ }; ++ ++ led@2 { ++ label = "eth-activity"; ++ reg = <0x02>; ++ color = ; ++ function = LED_FUNCTION_ACTIVITY; ++ default-state = "keep"; ++ linux,default-trigger = "netdev"; ++ }; ++ }; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0516-FROMLIST-clocksource-drivers-timer-sun4i-Advertise-a.patch b/SPECS/linux-lts-kmhv2/0516-FROMLIST-clocksource-drivers-timer-sun4i-Advertise-a.patch new file mode 100644 index 0000000000..c77f6b3c78 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0516-FROMLIST-clocksource-drivers-timer-sun4i-Advertise-a.patch @@ -0,0 +1,52 @@ +From 129865db72315d91e800a756092f830f8ca3e15a Mon Sep 17 00:00:00 2001 +From: Felix Yan +Date: Thu, 25 Jun 2026 06:04:34 +0800 +Subject: [RUYI PATCH] FROMLIST: clocksource/drivers/timer-sun4i: Advertise a + real minimum delta + +sun4i_clkevt_next_event() compensates for the timer stop/start +synchronization delay by programming evt - TIMER_SYNC_TICKS into the +hardware interval register. The clockevent device currently advertises +TIMER_SYNC_TICKS as min_delta_ticks, so the clockevents core is allowed +to call set_next_event() with evt == TIMER_SYNC_TICKS. + +That programs a zero-tick interval. With oneshot/highres/nohz timer +operation this can leave the next event stuck, which was observed as a +boot hang on Allwinner D1 after the clockevents core started reusing +forced minimum-delta events. + +Advertise one extra tick instead, so the smallest event accepted by the +core still programs at least one hardware tick after the synchronization +compensation. + +Fixes: 12e1480bcb49 ("clocksource: sun4i: Report the minimum tick that we can program") +Cc: stable@vger.kernel.org +Reported-by: Indrek Kruusa +Closes: https://lore.kernel.org/linux-riscv/CA+fTLhgLmTY+exGujKf8OYYQvcEW5X5NJ_5sLq2AYL6zER2c0A@mail.gmail.com/ +Assisted-by: Codex:gpt-5.5 +Signed-off-by: Felix Yan +Acked-by: Jernej Skrabec +Tested-by: Indrek Kruusa +Link: https://lore.kernel.org/linux-riscv/CA+fTLhgLmTY+exGujKf8OYYQvcEW5X5NJ_5sLq2AYL6zER2c0A@mail.gmail.com/ +Link: https://lore.kernel.org/r/20260624220434.4183732-1-felixonmars@archlinux.org +Signed-off-by: Han Gao +--- + drivers/clocksource/timer-sun4i.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c +index 7bdcc60ad43c..c2d04ab7cf2d 100644 +--- a/drivers/clocksource/timer-sun4i.c ++++ b/drivers/clocksource/timer-sun4i.c +@@ -208,7 +208,7 @@ static int __init sun4i_timer_init(struct device_node *node) + sun4i_timer_clear_interrupt(timer_of_base(&to)); + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), +- TIMER_SYNC_TICKS, 0xffffffff); ++ TIMER_SYNC_TICKS + 1, 0xffffffff); + + /* Enable timer0 interrupt */ + val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0517-FROMLIST-riscv-dts-spacemit-Use-symbolic-PDMA-reques.patch b/SPECS/linux-lts-kmhv2/0517-FROMLIST-riscv-dts-spacemit-Use-symbolic-PDMA-reques.patch new file mode 100644 index 0000000000..861c8c75e5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0517-FROMLIST-riscv-dts-spacemit-Use-symbolic-PDMA-reques.patch @@ -0,0 +1,111 @@ +From d322615922ba5ddf1ada2e5bbf9e9dc823068141 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 20 Jun 2026 01:07:48 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Use symbolic PDMA + request numbers on K1 + +The PDMA request numbers (DRQ) are fixed values specific to the SoC from +a hardware perspective. The detailed definition can be found in K1 User +Manual [1], Chapter 9.4.3 DMA Connectivity & Assignments. Add a DTS +header file to define the symbolic names for the DRQs of non-secure DMA +peripherals. + +Convert the K1 SPI3 node to these macros. + +Link: https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md [1] +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260620-b4-k1-pdma-req-macros-v4-1-3cf77d0bd0d6@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-pdma.h | 56 ++++++++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- + 2 files changed, 59 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k1-pdma.h + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pdma.h b/arch/riscv/boot/dts/spacemit/k1-pdma.h +new file mode 100644 +index 000000000000..7e5ad3d7111d +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k1-pdma.h +@@ -0,0 +1,56 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * DMA request number (DRQ) definitions for non-secure peripherals of ++ * the SpacemiT K1 PDMA. ++ * ++ * Copyright (c) 2026 Guodong Xu ++ */ ++ ++#ifndef _DTS_SPACEMIT_K1_PDMA_H ++#define _DTS_SPACEMIT_K1_PDMA_H ++ ++#define K1_PDMA_UART0_TX 3 ++#define K1_PDMA_UART0_RX 4 ++#define K1_PDMA_UART2_TX 5 ++#define K1_PDMA_UART2_RX 6 ++#define K1_PDMA_UART3_TX 7 ++#define K1_PDMA_UART3_RX 8 ++#define K1_PDMA_UART4_TX 9 ++#define K1_PDMA_UART4_RX 10 ++#define K1_PDMA_I2C0_TX 11 ++#define K1_PDMA_I2C0_RX 12 ++#define K1_PDMA_I2C1_TX 13 ++#define K1_PDMA_I2C1_RX 14 ++#define K1_PDMA_I2C2_TX 15 ++#define K1_PDMA_I2C2_RX 16 ++#define K1_PDMA_I2C4_TX 17 ++#define K1_PDMA_I2C4_RX 18 ++#define K1_PDMA_SPI3_TX 19 ++#define K1_PDMA_SPI3_RX 20 ++#define K1_PDMA_I2S0_TX 21 ++#define K1_PDMA_I2S0_RX 22 ++#define K1_PDMA_I2S1_TX 23 ++#define K1_PDMA_I2S1_RX 24 ++#define K1_PDMA_UART5_TX 25 ++#define K1_PDMA_UART5_RX 26 ++#define K1_PDMA_UART6_TX 27 ++#define K1_PDMA_UART6_RX 28 ++#define K1_PDMA_UART7_TX 29 ++#define K1_PDMA_UART7_RX 30 ++#define K1_PDMA_UART8_TX 31 ++#define K1_PDMA_UART8_RX 32 ++#define K1_PDMA_UART9_TX 33 ++#define K1_PDMA_UART9_RX 34 ++#define K1_PDMA_I2C5_TX 35 ++#define K1_PDMA_I2C5_RX 36 ++#define K1_PDMA_I2C6_TX 37 ++#define K1_PDMA_I2C6_RX 38 ++#define K1_PDMA_I2C7_TX 39 ++#define K1_PDMA_I2C7_RX 40 ++#define K1_PDMA_I2C8_TX 41 ++#define K1_PDMA_I2C8_RX 42 ++#define K1_PDMA_CAN0_RX 43 ++#define K1_PDMA_QSPI_RX 44 ++#define K1_PDMA_QSPI_TX 45 ++ ++#endif /* _DTS_SPACEMIT_K1_PDMA_H */ +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 4a359190f633..3fabfd34114b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -6,6 +6,8 @@ + #include + #include + ++#include "k1-pdma.h" ++ + /dts-v1/; + / { + #address-cells = <2>; +@@ -1102,7 +1104,7 @@ spi3: spi@d401c000 { + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_SSP3>; + interrupts = <55>; +- dmas = <&pdma 20>, <&pdma 19>; ++ dmas = <&pdma K1_PDMA_SPI3_RX>, <&pdma K1_PDMA_SPI3_TX>; + dma-names = "rx", "tx"; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0518-FROMLIST-riscv-mm-Fix-concurrency-in-mark_new_valid_.patch b/SPECS/linux-lts-kmhv2/0518-FROMLIST-riscv-mm-Fix-concurrency-in-mark_new_valid_.patch new file mode 100644 index 0000000000..257fde3cd4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0518-FROMLIST-riscv-mm-Fix-concurrency-in-mark_new_valid_.patch @@ -0,0 +1,103 @@ +From 738cb2f8e77e629af7ad3ecb6327b64b0ab8d2cc Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 29 Jun 2026 17:25:45 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Fix concurrency in + mark_new_valid_map() + +Turns out, the concurrency concerns [1] were justified - BOSC reported a +spurious fault in KFENCE that still triggers despite previous fixes, +which KFENCE reports as a false-positive. + +Fix the concurrency problems in mark_new_valid_map(): + +- Add smp_wmb() before filling the bitmap, to make sure page table + writes are "received". +- Use WRITE_ONCE() to fill the bitmap. + +This fixes the KFENCE false positives in internal testing. + +Also update comments in the assembly exception handler code to match. + +Fixes: 26c171fc4853 ("riscv: mm: Use the bitmap API for new_valid_map_cpus") +Reported-by: Yaxing Guo +Suggested-by: David Hildenbrand (Arm) +Link: https://lore.kernel.org/linux-riscv/da19ffcf-8042-4f96-9c2d-649468dc6a0a@kernel.org/ # [1] +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260629-riscv-mm-new-valid-map-ordering-v1-1-60d8c10c6292@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 15 ++++++++++++++- + arch/riscv/kernel/entry.S | 11 ++++------- + 2 files changed, 18 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 8cfe59483a8f..1f191cf801a2 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -6,7 +6,9 @@ + #ifndef _ASM_RISCV_CACHEFLUSH_H + #define _ASM_RISCV_CACHEFLUSH_H + ++#include + #include ++#include + + static inline void local_flush_icache_all(void) + { +@@ -46,12 +48,23 @@ extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; + static inline void mark_new_valid_map(void) + { ++ /* ++ * Orders any previous page table writes before setting bits in ++ * new_valid_map_cpus. Pairs with the sfence.vma in ++ * new_valid_map_cpus_check. ++ */ ++ smp_wmb(); ++ + /* + * We don't care if concurrently a cpu resets this value since + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. ++ * ++ * Not memset() or bitmap_fill() to avoid any possible compiler ++ * shenanigans. + */ +- bitmap_fill(new_valid_map_cpus, NR_CPUS); ++ for (size_t i = 0; i < ARRAY_SIZE(new_valid_map_cpus); i++) ++ WRITE_ONCE(new_valid_map_cpus[i], -1UL); + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 5639031d1437..67d630acf330 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -76,6 +76,8 @@ + amoxor.d a0, a1, (a0) + + /* ++ * Pairs with the smp_wmb() in mark_new_valid_map() ++ * + * A sfence.vma is required here. Even if we had Svvptc, there's no + * guarantee that after returning we wouldn't just fault again. + */ +@@ -112,13 +114,8 @@ SYM_CODE_START(handle_exception) + /* + * The RISC-V kernel does not flush TLBs on all CPUS after each new + * vmalloc mapping or kfence_unprotect(), which may result in +- * exceptions: +- * +- * - if the uarch caches invalid entries, the new mapping would not be +- * observed by the page table walker and an invalidation is needed. +- * - if the uarch does not cache invalid entries, a reordered access +- * could "miss" the new mapping and traps: in that case, we only need +- * to retry the access, no sfence.vma is required. ++ * exceptions. In that case, we need to sfence.vma to "receive" the new ++ * mappings and retry, whether or not we have Svvptc. + */ + new_valid_map_cpus_check + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0519-FROMLIST-clk-spacemit-k3-fix-parent-clock-of-UFS-acl.patch b/SPECS/linux-lts-kmhv2/0519-FROMLIST-clk-spacemit-k3-fix-parent-clock-of-UFS-acl.patch new file mode 100644 index 0000000000..8f6d34d686 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0519-FROMLIST-clk-spacemit-k3-fix-parent-clock-of-UFS-acl.patch @@ -0,0 +1,44 @@ +From adc59ef4d17d4895bf576f3cf8aa3caf6889e7bf Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 12:52:45 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix parent clock of UFS + aclk + +According to SpacemiT updated clock docs, the previous UFS aclk parent +clock was wrong, the correct one is illustrated below, so fix it. + + --> pll1_d5_491p52 --\ + --> pll1_d6_409p6 --| + --> pll2_d6 --|--> div --> gate --> ufs_aclk + --> pll2_d5 --/ + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260630-06-clk-ufs-support-v1-1-cf7521d1d0fe@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 03de04144963..0702b6ecdbd2 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -926,11 +926,10 @@ CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 1 + 20, 3, BIT(16), 0); + + static const struct clk_parent_data ufs_aclk_parents[] = { +- CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), +- CCU_PARENT_HW(pll1_d4_614p4), +- CCU_PARENT_HW(pll1_d8_307p2), +- CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll2_d6), ++ CCU_PARENT_HW(pll2_d5), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), + 2, 3, BIT(1), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0520-FROMLIST-dt-bindings-soc-spacemit-k3-Add-clock-ID-fo.patch b/SPECS/linux-lts-kmhv2/0520-FROMLIST-dt-bindings-soc-spacemit-k3-Add-clock-ID-fo.patch new file mode 100644 index 0000000000..29062567d5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0520-FROMLIST-dt-bindings-soc-spacemit-k3-Add-clock-ID-fo.patch @@ -0,0 +1,31 @@ +From b4f7041ac6bd1aadb453f13a9b30238794f3dac7 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 12:52:46 +0000 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add clock ID + for UFS refclk + +Add clock ID for the UFS refclk clock in SpacemiT K3 SoC. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260630-06-clk-ufs-support-v1-2-cf7521d1d0fe@kernel.org +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index dfae52547cda..69978ab0b29f 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -385,6 +385,7 @@ + #define CLK_APMU_PCIE_PORTC_DBI 91 + #define CLK_APMU_PCIE_PORTD_DBI 92 + #define CLK_APMU_PCIE_PORTE_DBI 93 ++#define CLK_APMU_UFS_REFCLK 94 + + /* DCIU clocks */ + #define CLK_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0521-FROMLIST-clk-spacemit-k3-Add-UFS-refclk-clock.patch b/SPECS/linux-lts-kmhv2/0521-FROMLIST-clk-spacemit-k3-Add-UFS-refclk-clock.patch new file mode 100644 index 0000000000..05cce2a6d8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0521-FROMLIST-clk-spacemit-k3-Add-UFS-refclk-clock.patch @@ -0,0 +1,38 @@ +From aa8baac4138d0aba308fc3e443779253a7d48537 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 12:52:47 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add UFS refclk clock + +Add the UFS reference clock for SpacemiT K3 SoC. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260630-06-clk-ufs-support-v1-3-cf7521d1d0fe@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 0702b6ecdbd2..092446590e41 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -934,6 +934,8 @@ static const struct clk_parent_data ufs_aclk_parents[] = { + CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), + 2, 3, BIT(1), 0); + ++CCU_FACTOR_DEFINE(ufs_refclk, CCU_PARENT_HW(pll1_d64_38p4), 2, 1); ++ + static const struct clk_parent_data edp0_pclk_parents[] = { + CCU_PARENT_HW(lcd_pxclk), + CCU_PARENT_NAME(external_clk), +@@ -1391,6 +1393,7 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { + [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, + [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, + [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, ++ [CLK_APMU_UFS_REFCLK] = &ufs_refclk.common.hw, + [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, + [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, + [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0522-FROMLIST-riscv-Avoid-stack-access-when-CSR_SCRATCH-i.patch b/SPECS/linux-lts-kmhv2/0522-FROMLIST-riscv-Avoid-stack-access-when-CSR_SCRATCH-i.patch new file mode 100644 index 0000000000..7e11efaa4f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0522-FROMLIST-riscv-Avoid-stack-access-when-CSR_SCRATCH-i.patch @@ -0,0 +1,194 @@ +From 888cd2841311164193d9df6e0f99f4d5a3f63d79 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 30 Jun 2026 14:36:24 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: Avoid stack access when CSR_SCRATCH is + incorrect + +The kernel exception handler unconditionally relies on the value in +CSR_SCRATCH, whether it is 0 (meaning kernel mode) or the current +pointer (meaning user mode). Therefore, any exception that happens while +CSR_SCRATCH does not reflect the current privilege mode would be +irrecoverable. + +When VMAP_STACK=y, spurious-seeming page faults can happen while +accessing the stack if the processor has cached/still-in-pipeline +non-valid PTEs. Therefore, it is unsafe to access the stack on entry +before setting CSR_SCRATCH to 0, or on exit to user after setting +CSR_SCRATCH to current. + +Therefore, instead of using the stack, make some scratch space in +task_info for these fragile regions of code, and access them using +offsets from tp. The scratch space for mark_new_valid_map is not reused +because the page fault *can* nest in places where the scratch space is +needed. + +Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") +Reported-by: Yaxing Guo +Link: https://lore.kernel.org/linux-riscv/20260601084524.34584-1-guoyaxing@bosc.ac.cn/ +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260630-riscv-no-stack-when-wrong-scratch-v1-1-0f9b9cb5cf67@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/csr.h | 1 + + arch/riscv/include/asm/thread_info.h | 5 +++ + arch/riscv/kernel/asm-offsets.c | 2 + + arch/riscv/kernel/entry.S | 65 +++++++++++++++++++++------- + 4 files changed, 58 insertions(+), 15 deletions(-) + +diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h +index 543a3364f11d..3ca44349168b 100644 +--- a/arch/riscv/include/asm/csr.h ++++ b/arch/riscv/include/asm/csr.h +@@ -16,6 +16,7 @@ + #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ + #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ + #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ ++#define SR_MPP_SHIFT 11 + #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ + + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h +index 836d80dd2921..0a2767430d0a 100644 +--- a/arch/riscv/include/asm/thread_info.h ++++ b/arch/riscv/include/asm/thread_info.h +@@ -73,6 +73,11 @@ struct thread_info { + */ + unsigned long a0, a1, a2; + #endif ++ /* ++ * Used in ret_from_exception() and handle_exception() as scratch space ++ * when CSR_SCRATCH does not reflect the current privilege mode. ++ */ ++ unsigned long tp, t0; + }; + + #ifdef CONFIG_SHADOW_CALL_STACK +diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c +index 7d42d3b8a32a..63cb1d8e0b5e 100644 +--- a/arch/riscv/kernel/asm-offsets.c ++++ b/arch/riscv/kernel/asm-offsets.c +@@ -49,6 +49,8 @@ void asm_offsets(void) + OFFSET(TASK_TI_A1, task_struct, thread_info.a1); + OFFSET(TASK_TI_A2, task_struct, thread_info.a2); + #endif ++ OFFSET(TASK_TI_TP, task_struct, thread_info.tp); ++ OFFSET(TASK_TI_T0, task_struct, thread_info.t0); + + OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); + OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 67d630acf330..5a97f002bf1f 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -99,6 +99,8 @@ + + + SYM_CODE_START(handle_exception) ++ /* Caution: CSR_SCARTCH does not reflect privilege mode from now on. */ ++ + /* + * If coming from userspace, preserve the user thread pointer and load + * the kernel thread pointer. If we came from the kernel, the scratch +@@ -131,6 +133,19 @@ SYM_CODE_START(handle_exception) + #endif + + .Lsave_context: ++ REG_S t0, TASK_TI_T0(tp) ++ ++ /* ++ * Grab the saved TP, and also set the scratch register back to 0, so ++ * that if a recursive exception occurs, the exception vector knows it ++ * came from the kernel. ++ * ++ * Caution: CSR_SCARTCH does not reflect privilege mode before this. ++ */ ++ csrrw t0, CSR_SCRATCH, zero ++ REG_S t0, TASK_TI_TP(tp) ++ REG_L t0, TASK_TI_T0(tp) ++ + REG_S sp, TASK_TI_USER_SP(tp) + REG_L sp, TASK_TI_KERNEL_SP(tp) + addi sp, sp, -(PT_SIZE_ON_STACK) +@@ -153,7 +168,7 @@ SYM_CODE_START(handle_exception) + csrr s2, CSR_EPC + csrr s3, CSR_TVAL + csrr s4, CSR_CAUSE +- csrr s5, CSR_SCRATCH ++ REG_L s5, TASK_TI_TP(tp) + REG_S s0, PT_SP(sp) + REG_S s1, PT_STATUS(sp) + REG_S s2, PT_EPC(sp) +@@ -161,12 +176,6 @@ SYM_CODE_START(handle_exception) + REG_S s4, PT_CAUSE(sp) + REG_S s5, PT_TP(sp) + +- /* +- * Set the scratch register to 0, so that if a recursive exception +- * occurs, the exception vector knows it came from the kernel +- */ +- csrw CSR_SCRATCH, x0 +- + /* Load the global pointer */ + load_global_pointer + +@@ -234,11 +243,6 @@ SYM_CODE_START_NOALIGN(ret_from_exception) + /* Save the kernel shadow call stack pointer */ + scs_save_current + +- /* +- * Save TP into the scratch register , so we can find the kernel data +- * structures again. +- */ +- csrw CSR_SCRATCH, tp + 1: + #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE + move a0, sp +@@ -270,11 +274,42 @@ SYM_CODE_START_NOALIGN(ret_from_exception) + + REG_L x1, PT_RA(sp) + REG_L x3, PT_GP(sp) +- REG_L x4, PT_TP(sp) +- REG_L x5, PT_T0(sp) + restore_from_x6_to_x31 + +- REG_L x2, PT_SP(sp) ++ /* ++ * Stash t0 and tp in thread_info since we can't access the stack after ++ * switching CSR_SCRATCH. ++ */ ++ REG_L t0, PT_T0(sp) ++ REG_S t0, TASK_TI_T0(tp) ++ REG_L t0, PT_TP(sp) ++ REG_S t0, TASK_TI_TP(tp) ++ ++ REG_L sp, PT_SP(sp) ++ ++ /* If returning to user mode, set CSR_SCRATCH to tp, else 0 */ ++ csrr t0, CSR_STATUS ++#if defined(CONFIG_RISCV_M_MODE) ++ /* the MPP value is too large to be used as an immediate arg for andi */ ++ srli t0, t0, SR_MPP_SHIFT ++ andi t0, t0, SR_MPP >> SR_MPP_SHIFT ++ /* t0 = (mstatus & SR_MPP) >> SR_MPP_SHIFT */ ++#else ++ andi t0, t0, SR_SPP ++ /* t0 = sstatus & SR_SPP */ ++#endif ++ seqz t0, t0 ++ /* t0 = !(status & SR_PP) */ ++ neg t0, t0 ++ /* t0 = (status & SR_PP) ? 0 : -1 */ ++ and t0, t0, tp ++ /* t0 = (status & SR_PP) ? 0 : tp */ ++ csrw CSR_SCRATCH, t0 ++ ++ /* Caution: CSR_SCARTCH does not reflect privilege mode from now on. */ ++ ++ REG_L t0, TASK_TI_T0(tp) ++ REG_L tp, TASK_TI_TP(tp) + + #ifdef CONFIG_RISCV_M_MODE + mret +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0523-FROMLIST-clk-spacemit-k3-set-hdma-clock-as-critical.patch b/SPECS/linux-lts-kmhv2/0523-FROMLIST-clk-spacemit-k3-set-hdma-clock-as-critical.patch new file mode 100644 index 0000000000..e3075be78a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0523-FROMLIST-clk-spacemit-k3-set-hdma-clock-as-critical.patch @@ -0,0 +1,35 @@ +From 09ea1f8afcd909a41d34782732f100b787f25a8c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 08:53:19 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: set hdma clock as critical + +HDMA clock is responsible for the internal TCM access path of X100 RISC-V +core, so set the clock flag as critical to prevent it from being shut off, +otherwise the Linux system will hang. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Han Gao +Signed-off-by: Yixun Lan +Tested-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260630-06-clk-hdma-critial-v1-1-443c0ac88c5f@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 092446590e41..aca61ea76019 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -1027,7 +1027,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT + /* APMU clocks end */ + + /* DCIU clocks start */ +-CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); + CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); + CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); + CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0524-FROMLIST-clk-spacemit-k3-set-rcpu-clock-as-critical.patch b/SPECS/linux-lts-kmhv2/0524-FROMLIST-clk-spacemit-k3-set-rcpu-clock-as-critical.patch new file mode 100644 index 0000000000..cddf6384f8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0524-FROMLIST-clk-spacemit-k3-set-rcpu-clock-as-critical.patch @@ -0,0 +1,36 @@ +From 90c9870addd82d973bf57ae773aee08cfc054c74 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 08:53:20 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: set rcpu clock as critical + +The SpacemiT K3 SoC integrates two RT24 RISC-V little cores (os0_rcpu and +os1_rcpu), each running an independent ESOS instance responsible for +system power management and real-time task. The RCPU clock is required +in order to keep these cores functional, so set its clock as critical to +prevent it from being shut off. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Han Gao +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260630-06-clk-hdma-critial-v1-2-443c0ac88c5f@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index aca61ea76019..5d0e31f07d6d 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { + CCU_PARENT_HW(pll1_d6_409p6), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, +- 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); + + static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { + CCU_PARENT_HW(pll1_d48_51p2_ap), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0525-FROMLIST-scsi-ufs-spacemit-dt-bindings-Add-UFS-contr.patch b/SPECS/linux-lts-kmhv2/0525-FROMLIST-scsi-ufs-spacemit-dt-bindings-Add-UFS-contr.patch new file mode 100644 index 0000000000..b13f6e5e54 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0525-FROMLIST-scsi-ufs-spacemit-dt-bindings-Add-UFS-contr.patch @@ -0,0 +1,86 @@ +From 8a7c0fb3a48fb485653d9f1159654de66caf9b84 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 2 Jul 2026 02:31:35 +0000 +Subject: [RUYI PATCH] FROMLIST: scsi: ufs: spacemit: dt-bindings: Add UFS + controller for K3 SoC + +Document the compatible for UFS (Universal Flash Storage) Host Controller +which found in SpacemiT K3 SoC chip. Its features are listed below: + +- Compliant with MIPI UniPro v1.61 specification. +- Compliant with M-PHY v3.0 specification. +- Compliant with UFS HCI v2.1 specification. +- Supports up to 2 Tx and 2 Rx lanes, up to HS-GEAR3 5.8 Gbps per lane. +- Supports standard low-power hibernate to reduce power consumption. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260702-08-k3-ufs-support-v1-1-1a64a3ab128f@kernel.org +Signed-off-by: Han Gao +--- + .../bindings/ufs/spacemit,k3-ufshc.yaml | 54 +++++++++++++++++++ + 1 file changed, 54 insertions(+) + create mode 100644 Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml + +diff --git a/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml b/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml +new file mode 100644 +index 000000000000..e6cb6fb2496c +--- /dev/null ++++ b/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml +@@ -0,0 +1,54 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/ufs/spacemit,k3-ufshc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K3 SoC UFS Host Controller ++ ++maintainers: ++ - Yixun Lan ++ ++properties: ++ compatible: ++ const: spacemit,k3-ufshc ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: aclk ++ - const: ref_clk ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ ++allOf: ++ - $ref: ufs-common.yaml ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ufs@c0e00000 { ++ compatible = "spacemit,k3-ufshc"; ++ reg = <0xc0e00000 0x40000>; ++ clocks = <&syscon_apmu CLK_APMU_UFS_ACLK>, ++ <&syscon_apmu CLK_APMU_UFS_REFCLK>; ++ clock-names = "aclk", "ref_clk"; ++ resets = <&syscon_apmu RESET_APMU_UFS_ACLK>; ++ freq-table-hz = <491520000 491520000 19200000 19200000>; ++ lanes-per-direction = <2>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0526-FROMLIST-scsi-ufs-spacemit-k3-Add-UFS-Host-Controlle.patch b/SPECS/linux-lts-kmhv2/0526-FROMLIST-scsi-ufs-spacemit-k3-Add-UFS-Host-Controlle.patch new file mode 100644 index 0000000000..49c6e86246 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0526-FROMLIST-scsi-ufs-spacemit-k3-Add-UFS-Host-Controlle.patch @@ -0,0 +1,1093 @@ +From be8fda343078b7b8f8ee71dab4139785a03d9ace Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 2 Jul 2026 02:31:36 +0000 +Subject: [RUYI PATCH] FROMLIST: scsi: ufs: spacemit: k3: Add UFS Host + Controller driver + +SpacemiT K3 SoC consist of UFS (Universal Flash Storage) Host Controller +which has features compatible with JEDEC UFS 2.2, MIPI UniPro v1.61 and +M-PHY v3.0 standard. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260702-08-k3-ufs-support-v1-2-1a64a3ab128f@kernel.org +Signed-off-by: Han Gao +--- + drivers/ufs/host/Kconfig | 12 + + drivers/ufs/host/Makefile | 1 + + drivers/ufs/host/ufs-spacemit.c | 931 ++++++++++++++++++++++++++++++++ + drivers/ufs/host/ufs-spacemit.h | 90 +++ + 4 files changed, 1034 insertions(+) + create mode 100644 drivers/ufs/host/ufs-spacemit.c + create mode 100644 drivers/ufs/host/ufs-spacemit.h + +diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig +index 964ae70e7390..9b57772faf5f 100644 +--- a/drivers/ufs/host/Kconfig ++++ b/drivers/ufs/host/Kconfig +@@ -132,6 +132,18 @@ config SCSI_UFS_VARIABLE_SG_ENTRY_SIZE + bool + default y if SCSI_UFS_EXYNOS && SCSI_UFS_CRYPTO + ++config SCSI_UFS_SPACEMIT ++ tristate "SpacemiT UFS controller driver" ++ depends on SCSI_UFSHCD_PLATFORM && ARCH_SPACEMIT ++ help ++ This selects the SpacemiT specific additions to UFSHCD platform driver. ++ UFS host on SpacemiT needs some vendor specific configuration before ++ accessing the hardware which includes PHY configuration and vendor ++ specific registers. ++ ++ Select this if you have UFS controller on SpacemiT chipset. ++ If unsure, say N. ++ + config SCSI_UFS_SPRD + tristate "Unisoc specific hooks to UFS controller platform driver" + depends on SCSI_UFSHCD_PLATFORM && (ARCH_SPRD || COMPILE_TEST) +diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile +index 65d8bb23ab7b..151bf43dfba7 100644 +--- a/drivers/ufs/host/Makefile ++++ b/drivers/ufs/host/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o + obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o + obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o + obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o ++obj-$(CONFIG_SCSI_UFS_SPACEMIT) += ufs-spacemit.o + obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o + obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o + obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o +diff --git a/drivers/ufs/host/ufs-spacemit.c b/drivers/ufs/host/ufs-spacemit.c +new file mode 100644 +index 000000000000..be475f5566a8 +--- /dev/null ++++ b/drivers/ufs/host/ufs-spacemit.c +@@ -0,0 +1,931 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ufshcd-pltfrm.h" ++#include "ufs-spacemit.h" ++ ++/* PA Layer Gettable and settable M-PHY Specific Attributes */ ++#define PA_TXHSG1SYNCLENGTH 0x1552 ++#define PA_TXHSG1PREPARELENGTH 0x1553 ++#define PA_TXHSG2SYNCLENGTH 0x1554 ++#define PA_TXHSG2PREPARELENGTH 0x1555 ++#define PA_TXHSG3SYNCLENGTH 0x1556 ++#define PA_TXHSG3PREPARELENGTH 0x1557 ++#define PA_TXMK2EXTENSION 0x155A ++#define PA_PEERSCRAMBLING 0x155B ++#define PA_TXSKIP 0x155C ++#define PA_TXSKIPPERIOD 0x155D ++#define PA_PEER_TX_LCC_ENABLE 0x155F ++ ++#define PA_SCRAMBLING 0x1585 ++#define PA_MK2EXTENSIONGUARDBAND 0x15AB ++ ++/*special TX/RX Configuration Attributes*/ ++#define RX_LS_PRE_LEN_CAP 0x008D ++#define RX_LANE_HB8_BKDOOR_ATTR 0x00F4 ++#define RX_PWRM_CLOSURE_LEN_CAP 0x008E ++#define RX_MIN_STALL_CAP 0x0088 ++#define RX_LANE_SOF_BKDOOR_ATT 0x00F2 ++#define RX_GARBAGE_COUNT_OFFSET 0x00F2 ++ ++/*special analog reg*/ ++#define ANA_EQ_CTRL_REG_ATTR 0x00CD ++#define ANA_HSGEAR_CTRL_ATTR 0x00C1 ++ ++/* ++ * Keep UFS ACLK at a lower parent rate (409.6MHz) for stable init. ++ * This mirrors the "ufs-low-aclk-freq" change from the other environment. ++ */ ++#define UFS_ACLK_LOW_FREQ_HZ 409600000UL ++ ++/* PHY register magic values */ ++#define MPHY_PU_ALL 0x87f ++#define MPHY_PU_WITH_HB8_RESET 0xb7f ++#define MPHY_DEVICE_RESET_DEASSERT 0x101 ++#define MPHY_DEVICE_RESET_ASSERT 0x001 ++#define MPHY_PLL_LOCK_BIT BIT(31) ++#define MPHY_PLL_LOCK_TIMEOUT_US 10000 ++ ++/* FSM states */ ++#define FSM_STATE_HIBERN8 0x1 ++#define FSM_STATE_ACTIVE 0x3 ++#define FSM_STATE_LS_BURST 0x5 ++ ++struct ufs_reg_snapshot { ++ u32 reg_utrlba; ++ u32 reg_utrlbau; ++ u32 reg_utrmlba; ++ u32 reg_utrmlbau; ++ ++ u32 reg_sys1clk; ++ u32 reg_tx_symbol_clk; ++ u32 reg_retry_timer; ++ u32 reg_pa_link; ++ u32 reg_cfg1; ++}; ++ ++#define VENDOR_DUMP_BUF_SIZE 2048 ++#define VENDOR_MAX_OFFSET 0xE0 ++ ++static void ufs_spacemit_dump_host_regs(struct ufs_hba *hba) ++{ ++ int i, offset; ++ size_t len = 0; ++ u8 *buf; ++ u32 val; ++ u32 host_reg[] = { ++ (UFS_PHY_MNG_BASE + UFS_MPHY_RST_CTRL), ++ (UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL), ++ (UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL), ++ 0xFFF, ++ }; ++ ++ buf = kzalloc(VENDOR_DUMP_BUF_SIZE, GFP_ATOMIC); ++ if (!buf) ++ return; ++ ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "vendor specific registers:"); ++ ++ for (offset = 0xC0, i = 0; offset < VENDOR_MAX_OFFSET; offset += 4, i++) { ++ val = ufshcd_readl(hba, offset); ++ if (i % 4 == 0) ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n"); ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, " 0x%03x: 0x%08x ", ++ offset, val); ++ } ++ ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n mphy and atop registers:"); ++ ++ for (i = 0; host_reg[i] != 0xFFF; i++) { ++ val = ufshcd_readl(hba, host_reg[i]); ++ if (i % 4 == 0) ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n"); ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, " 0x%03x: 0x%08x ", ++ host_reg[i], val); ++ } ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n"); ++ ++ dev_warn(hba->dev, "%s", buf); ++ ++ kfree(buf); ++} ++ ++/* M-PHY FSM states */ ++#define MPHY_RX_FSM_STATE 0xC1 ++#define MPHY_TX_FSM_STATE 0x41 ++ ++static bool is_fsm_state_valid(u32 state) ++{ ++ return (state == FSM_STATE_ACTIVE || state == FSM_STATE_LS_BURST); ++} ++ ++static int ufs_spacemit_check_hibern8(struct ufs_hba *hba) ++{ ++ u32 tx_fsm_val_0 = 0; ++ u32 tx_fsm_val_1 = 0; ++ int retries = DIV_ROUND_UP(HBRN8_POLL_TOUT_MS * 1000, 100); ++ int err = 0; ++ ++ do { ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ &tx_fsm_val_0); ++ err |= ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ &tx_fsm_val_1); ++ if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && ++ tx_fsm_val_1 == TX_FSM_HIBERN8)) ++ break; ++ ++ usleep_range(100, 200); ++ } while (--retries > 0); ++ ++ if (!err && retries <= 0) { ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ &tx_fsm_val_0); ++ err |= ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ &tx_fsm_val_1); ++ } ++ ++ if (err) { ++ dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", ++ __func__, err); ++ } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || ++ tx_fsm_val_1 != TX_FSM_HIBERN8) { ++ err = -ETIMEDOUT; ++ dev_err(hba->dev, ++ "%s: invalid TX_FSM_STATE, lane0 = %u, lane1 = %u\n", ++ __func__, tx_fsm_val_0, tx_fsm_val_1); ++ } ++ ++ return err; ++} ++ ++static void ufs_spacemit_dump_fsm_state(struct ufs_hba *hba) ++{ ++ u32 tx0_fsm_val, tx1_fsm_val, rx0_fsm_val, rx1_fsm_val; ++ int err; ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ &tx0_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ &tx1_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_RX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &rx0_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_RX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ &rx1_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ if (!is_fsm_state_valid(tx0_fsm_val) || !is_fsm_state_valid(tx1_fsm_val) || ++ !is_fsm_state_valid(rx0_fsm_val) || !is_fsm_state_valid(rx1_fsm_val)) { ++ dev_warn(hba->dev, "FSM state invalid - TX:[0x%x, 0x%x], RX:[0x%x, 0x%x]\n", ++ tx0_fsm_val, tx1_fsm_val, rx0_fsm_val, rx1_fsm_val); ++ } ++} ++ ++static int ufs_spacemit_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes) ++{ ++ int err; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes); ++ if (err) ++ dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n", __func__, err); ++ ++ return err; ++} ++ ++static u32 ufs_spacemit_get_sys1clk_1us(struct ufs_hba *hba) ++{ ++ struct ufs_clk_info *clki, *ufs_aclk = NULL; ++ struct list_head *head = &hba->clk_list_head; ++ unsigned long rate_hz = 0; ++ ++ if (!list_empty(head)) { ++ list_for_each_entry(clki, head, list) { ++ if (clki->name && !strcmp(clki->name, "aclk") && clki->clk) { ++ ufs_aclk = clki; ++ break; ++ } ++ } ++ } ++ ++ if (ufs_aclk && ufs_aclk->clk) ++ rate_hz = clk_get_rate(ufs_aclk->clk); ++ ++ if (!rate_hz) ++ return 0; ++ ++ return DIV_ROUND_CLOSEST(rate_hz, 1000000); ++} ++ ++static int ufs_spacemit_wait_mphy_pll_lock(struct ufs_hba *hba) ++{ ++ int timeout = MPHY_PLL_LOCK_TIMEOUT_US; ++ u32 val; ++ ++ while (timeout-- > 0) { ++ val = ufshcd_readl(hba, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ if (val & MPHY_PLL_LOCK_BIT) ++ return 0; ++ ++ udelay(1); ++ } ++ ++ dev_err(hba->dev, "M-PHY PLL lock timeout\n"); ++ return -ETIMEDOUT; ++} ++ ++/** ++ * ufs_spacemit_mphy_init ++ * @hba: host controller instance ++ */ ++static int ufs_spacemit_mphy_init(struct ufs_hba *hba) ++{ ++ int ret; ++ ++ /* reset all mphy logical */ ++ ufshcd_writel(hba, 0x003, UFS_PHY_MNG_BASE + 0x0); ++ mdelay(1); ++ ++ /* power up all */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + 0x4); ++ mdelay(1); ++ ++ /* asserted ana_rx_hb8_reset */ ++ ufshcd_writel(hba, 0xb7f, UFS_PHY_MNG_BASE + 0x4); ++ mdelay(1); ++ ++ /* deasserted ana_rx_hb8_reset */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + 0x4); ++ mdelay(1); ++ ++ /* deasserted ufs device reset & refer clk output enable */ ++ ufshcd_writel(hba, 0x101, UFS_PHY_MNG_BASE + 0xC); ++ mdelay(1); ++ ++ ret = ufs_spacemit_wait_mphy_pll_lock(hba); ++ if (ret < 0) ++ return ret; ++ ++ dev_dbg(hba->dev, "M-PHY PLL locked successfully\n"); ++ ++ ufshcd_writel(hba, 0x1, UFS_PHY_MNG_BASE + 0x08); ++ udelay(5); ++ ++ ufshcd_writel(hba, 0x40, UFS_ATOP_BASE + (0xC2 << 2)); ++ udelay(5); ++ ++ ufshcd_writel(hba, 0x0, UFS_PHY_MNG_BASE + 0x08); ++ ++ mdelay(2); ++ ++ dev_dbg(hba->dev, "M-PHY init completed\n"); ++ ++ return 0; ++} ++ ++static int ufs_spacemit_uniprov1p6_init(struct ufs_hba *hba) ++{ ++ /* PA_TXHSG1SYNCLENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1552), 0x4f); ++ ++ /* PA_TXHSG1PREPARELENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1553), 0xf); ++ ++ /* PA_TXHSG2SYNCLENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1554), 0x4f); ++ ++ /* PA_TXHSG2PREPARELENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1555), 0xf); ++ ++ /* PA_TXHSG3SYNCLENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x4f); ++ ++ /* PA_TXHSG3PREPARELENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1557), 0xf); ++ ++ /* PA_TXMK2EXTENSION */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155A), 0x0); ++ ++ /* PA_PEERSCRAMBLING */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155B), 0x1); ++ ++ /* PA_TXSKIP */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155C), 0x1); ++ ++ /* PA_TXSKIPPERIOD */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155D), 250); ++ ++ /* PA_LOCAL_TX_LCC_ENABLE */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0); ++ ++ /* PA_PEER_TX_LCC_ENABLE */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155F), 0x0); ++ ++ /* PA_SCRAMBLING */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1585), 0x1); ++ ++ /* PA_GRANULARITY */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15AA), 0x1); ++ ++ /* PA_MK2EXTENSIONGUARDBAND */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15AB), 0x0); ++ ++ /* PA_STALLNOCONFIGTIME */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A3), 15); ++ ++ /* PA_TACTIVATE */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x64); ++ ++ /* PA_TXTRAILINGCLOCKS */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1564), 0x64); ++ ++ /* RX_LS_PREPARELEN_TIME RX0 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008D, 4), 0x0B); ++ ++ /* RX_LS_PREPARELEN_TIME RX1 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008D, 5), 0X0B); ++ ++ /* RX_HIBERNATE_BKEN RX0 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F4, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x9F); ++ ++ /* RX_HIBERNATE_BKEN RX1 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F4, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x9F); ++ ++ /* PWM_BURST_closure_length */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008E, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 15); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008E, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 15); ++ ++ /* min_stall_not_config_time*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0088, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0xFF); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0088, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0xFF); ++ ++ /* TX HB8_TIME CAP */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x64); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), 0x64); ++ ++ /*RX HB8_TIME CAP*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x64); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x64); ++ ++ /*TX EQ 3DB*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00CD, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x5); ++ ++ /*RX garbage cnt = 32 SI*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F2, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x9F); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F2, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x9F); ++ ++ dev_info(hba->dev, "UniPro v1.6 init completed\n"); ++ ++ return 0; ++} ++ ++static void ufs_spacemit_set_dev_cap(struct ufs_host_params *host_params, u32 pwr_hs) ++{ ++ if (!host_params) ++ return; ++ ++ memset(host_params, 0, sizeof(struct ufs_host_params)); ++ host_params->tx_lanes = UFS_SPACEMIT_K3_LIMIT_NUM_LANES_TX; ++ host_params->rx_lanes = UFS_SPACEMIT_K3_LIMIT_NUM_LANES_RX; ++ host_params->hs_rx_gear = UFS_SPACEMIT_K3_LIMIT_HSGEAR_RX; ++ host_params->hs_tx_gear = UFS_SPACEMIT_K3_LIMIT_HSGEAR_TX; ++ host_params->pwm_rx_gear = UFS_SPACEMIT_K3_LIMIT_PWMGEAR_RX; ++ host_params->pwm_tx_gear = UFS_SPACEMIT_K3_LIMIT_PWMGEAR_TX; ++ host_params->rx_pwr_pwm = UFS_SPACEMIT_K3_LIMIT_RX_PWR_PWM; ++ host_params->tx_pwr_pwm = UFS_SPACEMIT_K3_LIMIT_TX_PWR_PWM; ++ host_params->rx_pwr_hs = pwr_hs; ++ host_params->tx_pwr_hs = pwr_hs; ++ host_params->hs_rate = UFS_SPACEMIT_K3_LIMIT_HS_RATE; ++ host_params->desired_working_mode = UFS_HS_MODE; ++} ++ ++static int ufs_spacemit_link_startup_pre_change(struct ufs_hba *hba) ++{ ++ u32 value, sys1clk_1us; ++ ++ ufs_spacemit_mphy_init(hba); ++ ++ ufs_spacemit_uniprov1p6_init(hba); ++ ++ /* config sysclk and tx symbol clk before link startup */ ++ value = UFS_MAX_LINKSTARTUP_TIMER; ++ ++ /* clear bit0~bit3, select b0 design */ ++ value &= ~0xf; ++ ++ ufshcd_writel(hba, value, UFS_PA_LINK_STARTUP_TIMER); ++ ++ sys1clk_1us = ufs_spacemit_get_sys1clk_1us(hba); ++ if (!sys1clk_1us) ++ sys1clk_1us = DIV_ROUND_CLOSEST(UFS_ACLK_LOW_FREQ_HZ, 1000000); ++ ufshcd_writel(hba, sys1clk_1us, UFS_SYS1CLK_1US); ++ ufshcd_writel(hba, UFS_TX_SYMBO_CLK, UFS_TX_SYMBOL_CLK_NS_US); ++ ++ dev_dbg(hba->dev, "REG_UFS_SYS1CLK_1US: 0x%x\n", ufshcd_readl(hba, UFS_SYS1CLK_1US)); ++ dev_dbg(hba->dev, "REG_UFS_TX_SYMBOL_CLK_NS_US: 0x%x\n", ++ ufshcd_readl(hba, UFS_TX_SYMBOL_CLK_NS_US)); ++ ++ return 0; ++} ++ ++static int ufs_spacemit_link_startup_post_change(struct ufs_hba *hba) ++{ ++ u32 tx_lanes; ++ ++ /* add 0xe8 make UFS2.1 run GEAR3 + 2Lane@409M */ ++ mdelay(5); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xe8, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x97); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xe8, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0xd7); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xe8, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x17); ++ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), UFS_DL_AFC0REQTIMEOUTVAL_MAX); ++ ++ return ufs_spacemit_get_connected_tx_lanes(hba, &tx_lanes); ++} ++ ++static int ufs_spacemit_link_startup_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ switch (status) { ++ case PRE_CHANGE: ++ ufs_spacemit_link_startup_pre_change(hba); ++ break; ++ case POST_CHANGE: ++ ufs_spacemit_link_startup_post_change(hba); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int ufs_spacemit_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ int ret; ++ ++ ufs_spacemit_set_dev_cap(&host_params, FAST_MODE); ++ ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, ++ dev_req_params); ++ if (ret) { ++ dev_err(hba->dev, "Failed to negotiate power params: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hba->dev, ++ "Power mode config - gear_rx:%d, gear_tx:%d, lane_rx:%d, lane_tx:%d, pwr_rx:%d, pwr_tx:%d, hs_rate:%d\n", ++ dev_req_params->gear_rx, dev_req_params->gear_tx, dev_req_params->lane_rx, ++ dev_req_params->lane_tx, dev_req_params->pwr_rx, dev_req_params->pwr_tx, ++ dev_req_params->hs_rate); ++ ++ return ret; ++} ++ ++static int ufs_spacemit_pwr_change_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_spacemit_host *host = ufshcd_get_variant(hba); ++ int ret = 0; ++ ++ if (!dev_req_params) { ++ dev_err(hba->dev, "Invalid Parameters\n"); ++ return -EINVAL; ++ } ++ ++ switch (status) { ++ case PRE_CHANGE: ++ break; ++ case POST_CHANGE: ++ /* cache the power mode parameters to use internally */ ++ memcpy(&host->dev_req_params, dev_req_params, sizeof(*dev_req_params)); ++ ret = ufs_spacemit_wait_mphy_pll_lock(hba); ++ if (ret < 0) ++ return ret; ++ ++ dev_dbg(hba->dev, "M-PHY PLL locked after power mode change\n"); ++ /*set ANA_HSGEAR_CTRL_ATTR back to default value*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(ANA_HSGEAR_CTRL_ATTR), 0x00); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static int ufs_spacemit_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) ++{ ++ int err; ++ u32 pa_vs_config_reg1; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(UFS_PA_VS_CONFIG_REG1), &pa_vs_config_reg1); ++ if (err) ++ return err; ++ ++ /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ ++ return ufshcd_dme_set(hba, UIC_ARG_MIB(UFS_PA_VS_CONFIG_REG1), ++ (pa_vs_config_reg1 | (1 << 12))); ++} ++ ++static int ufs_spacemit_apply_dev_quirks(struct ufs_hba *hba) ++{ ++ if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) ++ ufs_spacemit_quirk_host_pa_saveconfigtime(hba); ++ ++ if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) ++ hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; ++ ++ /*LCC_DISABLE*/ ++ mdelay(50); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LCC_ENABLE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LCC_ENABLE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), 0); ++ ++ /*TX_Min_ActivateTime*/ ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ 0x0); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ 0x0); ++ mdelay(10); ++ ++ /*use backdoor reg to pre-set TX RATE/GEAR to let PLL lock before set_power_mode switch*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(ANA_HSGEAR_CTRL_ATTR), 0x25); ++ mdelay(10); ++ ++ return ufs_spacemit_wait_mphy_pll_lock(hba); ++} ++ ++/** ++ * ufs_spacemit_advertise_quirks - advertise the known Spacemit UFS controller quirks ++ * @hba: host controller instance ++ * ++ * Spacemit UFS host controller might have some non standard behaviours (quirks) ++ * than what is specified by UFSHCI specification. Advertise all such ++ * quirks to standard UFS host controller driver so standard takes them into ++ * account. ++ */ ++static void ufs_spacemit_advertise_quirks(struct ufs_hba *hba) ++{ ++ hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; ++} ++ ++/** ++ * ufs_spacemit_fsm_dump_work - Deferred work to dump FSM state ++ * @work: work structure ++ * ++ * This function is called from a workqueue context (not interrupt context), ++ * allowing safe execution of blocking operations like ufshcd_dme_get(). ++ */ ++static void ufs_spacemit_fsm_dump_work(struct work_struct *work) ++{ ++ struct ufs_spacemit_host *host = container_of(work, struct ufs_spacemit_host, ++ fsm_dump_work); ++ struct ufs_hba *hba = host->hba; ++ ++ /* Safe to call blocking functions in workqueue context */ ++ if (ufshcd_is_link_active(hba)) ++ ufs_spacemit_dump_fsm_state(hba); ++} ++ ++/** ++ * ufs_spacemit_init - init phy and prepare clk ++ * @hba: host controller instance ++ */ ++static int ufs_spacemit_init(struct ufs_hba *hba) ++{ ++ int err = 0; ++ struct device *dev = hba->dev; ++ struct ufs_spacemit_host *host; ++ ++ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ host->rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(host->rst)) ++ return dev_err_probe(dev, PTR_ERR(host->rst), ++ "Failed to get reset control\n"); ++ ++ host->hba = hba; ++ ufshcd_set_variant(hba, host); ++ ufs_spacemit_advertise_quirks(hba); ++ ++ /* Initialize workqueue for deferred FSM state dump */ ++ INIT_WORK(&host->fsm_dump_work, ufs_spacemit_fsm_dump_work); ++ ++ err = ufshcd_vops_phy_initialization(host->hba); ++ return err; ++} ++ ++/** ++ * ufs_spacemit_device_reset - Toggle device reset line ++ * @hba: per-adapter instance ++ * ++ * Toggles the reset line to reset the attached UFS device. ++ * ++ * Returns: 0 on success ++ */ ++static int ufs_spacemit_device_reset(struct ufs_hba *hba) ++{ ++ /* Stop device ref_clk & asserted ufs device reset */ ++ ufshcd_writel(hba, 0x000, UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ mdelay(1); ++ ++ /* Enable device ref_clk & de-asserted ufs device reset */ ++ ufshcd_writel(hba, MPHY_DEVICE_RESET_DEASSERT, UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ mdelay(1); ++ ++ return 0; ++} ++ ++/** ++ * ufs_spacemit_event_notify - Handle UFS error events ++ * @hba: host controller instance ++ * @evt: event type ++ * @data: event-specific data ++ * ++ * Handles error events from UFS core, dumps registers immediately ++ * and schedules FSM state dump for later execution in workqueue context. ++ */ ++static void ufs_spacemit_event_notify(struct ufs_hba *hba, enum ufs_event_type evt, void *data) ++{ ++ struct ufs_spacemit_host *host = ufshcd_get_variant(hba); ++ bool dump_regs = false; ++ ++ switch (evt) { ++ case UFS_EVT_PA_ERR: ++ if (data) ++ dev_warn(hba->dev, "PA error event, INT errors:0x%x, PA_ERR_CODE:0x%x\n", ++ hba->errors, *(u32 *)data); ++ ++ dump_regs = true; ++ break; ++ ++ case UFS_EVT_DL_ERR: ++ if (data) ++ dev_warn(hba->dev, "DL error event, INT errors:0x%x, DL_ERR:0x%x\n", ++ hba->errors, *(u32 *)data); ++ ++ dump_regs = true; ++ break; ++ ++ case UFS_EVT_ABORT: ++ dev_warn(hba->dev, "Abort event, INT errors:0x%x\n", hba->errors); ++ break; ++ ++ default: ++ break; ++ } ++ ++ /* Dump registers if error occurred (safe in interrupt context) */ ++ if (hba->errors || dump_regs) ++ ufs_spacemit_dump_host_regs(hba); ++ ++ /* Schedule FSM state dump in workqueue context (not in interrupt context) */ ++ if (ufshcd_is_link_active(hba) && host) ++ queue_work(system_wq, &host->fsm_dump_work); ++} ++ ++/** ++ * ufs_spacemit_hibern8_notify - Handle hibernate enter/exit ++ * @hba: host controller instance ++ * @cmd: UIC command (HIBER_ENTER or HIBER_EXIT) ++ * @status: notification status ++ * ++ * Manages M-PHY power state during hibernate transitions. ++ */ ++static void ufs_spacemit_hibern8_notify(struct ufs_hba *hba, enum uic_cmd_dme cmd, ++ enum ufs_notify_change_status status) ++{ ++ int ret; ++ ++ dev_dbg(hba->dev, "Hibern8 notify: cmd=%d, status=%d\n", cmd, status); ++ if (status == PRE_CHANGE) { ++ if (cmd == UIC_CMD_DME_HIBER_EXIT) { ++ mdelay(1); ++ ++ /* Enable reference clock */ ++ ufshcd_writel(hba, MPHY_DEVICE_RESET_DEASSERT, ++ UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ mdelay(1); ++ ++ /* Power up all */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ mdelay(1); ++ ++ /* Assert ana_rx_hb8_reset */ ++ ufshcd_writel(hba, MPHY_PU_WITH_HB8_RESET, ++ UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ mdelay(1); ++ ++ /* Deassert ana_rx_hb8_reset */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ ++ ret = ufs_spacemit_wait_mphy_pll_lock(hba); ++ if (ret < 0) ++ return; ++ ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xdd), 0x57); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xe8), 0x57); ++ } ++ } ++ ++ if (status == PRE_CHANGE) { ++ if (cmd == UIC_CMD_DME_HIBER_ENTER) { ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x85); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x85); ++ } ++ } ++ ++ if (status == POST_CHANGE) { ++ if (cmd == UIC_CMD_DME_HIBER_ENTER) { ++ ufs_spacemit_check_hibern8(hba); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x80); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x80); ++ ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xdd), 0x57); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xdd), 0xd7); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xe8), 0x57); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xe8), 0xd7); ++ mdelay(1); ++ ++ /* Power down M-PHY */ ++ ufshcd_writel(hba, 0x0, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ mdelay(1); ++ ++ /* Keep reference clock enabled, assert device reset */ ++ ufshcd_writel(hba, MPHY_DEVICE_RESET_ASSERT, ++ UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ } ++ } ++} ++ ++/** ++ * ufs_spacemit_hce_enable_notify - Configure HCE enable sequence ++ * @hba: host controller instance ++ * @status: notification status (PRE_CHANGE or POST_CHANGE) ++ * ++ * Configures host controller enable with proper sequencing. ++ * Handles crypto enable if supported. ++ * ++ * Returns: 0 on success ++ */ ++static int ufs_spacemit_hce_enable_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ struct ufs_spacemit_host *host = ufshcd_get_variant(hba); ++ u32 enable_val, val; ++ ++ if (status == PRE_CHANGE) { ++ enable_val = CONTROLLER_ENABLE; ++ ++ if (hba->caps & UFSHCD_CAP_CRYPTO) ++ enable_val = CRYPTO_GENERAL_ENABLE | CONTROLLER_ENABLE; ++ ++ if (!host->first_hce_done) { ++ host->first_hce_done = true; ++ dev_dbg(hba->dev, "First HCE enable\n"); ++ } else { ++ val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); ++ if (val == enable_val) { ++ ufshcd_writel(hba, enable_val & (1 << CONTROLLER_ENABLE), ++ REG_CONTROLLER_ENABLE); ++ ++ while (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) == ++ (enable_val & (1 << CONTROLLER_ENABLE))) ++ ; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * struct ufs_hba_spacemit_vops - UFS Spacemit specific variant operations ++ * ++ * The variant operations configure the necessary controller and PHY ++ * handshake during initialization. ++ */ ++static const struct ufs_hba_variant_ops ufs_hba_spacemit_vops = { ++ .name = "ufshcd-spacemit", ++ .init = ufs_spacemit_init, ++ .link_startup_notify = ufs_spacemit_link_startup_notify, ++ .negotiate_pwr_mode = ufs_spacemit_negotiate_pwr_mode, ++ .pwr_change_notify = ufs_spacemit_pwr_change_notify, ++ .device_reset = ufs_spacemit_device_reset, ++ .event_notify = ufs_spacemit_event_notify, ++ .apply_dev_quirks = ufs_spacemit_apply_dev_quirks, ++ .hibern8_notify = ufs_spacemit_hibern8_notify, ++ .hce_enable_notify = ufs_spacemit_hce_enable_notify, ++}; ++ ++static const struct of_device_id ufs_spacemit_of_match[] = { ++ { .compatible = "spacemit,k3-ufshc" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, ufs_spacemit_of_match); ++ ++static int ufs_spacemit_probe(struct platform_device *pdev) ++{ ++ return ufshcd_pltfrm_init(pdev, &ufs_hba_spacemit_vops); ++} ++ ++static void ufs_spacemit_remove(struct platform_device *pdev) ++{ ++ ufshcd_pltfrm_remove(pdev); ++} ++ ++static struct platform_driver ufs_spacemit_pltform = { ++ .probe = ufs_spacemit_probe, ++ .remove = ufs_spacemit_remove, ++ .driver = { ++ .name = "ufshcd-spacemit", ++ .of_match_table = of_match_ptr(ufs_spacemit_of_match), ++ }, ++}; ++module_platform_driver(ufs_spacemit_pltform); ++ ++MODULE_DESCRIPTION("SpacemiT UFS Host Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/ufs/host/ufs-spacemit.h b/drivers/ufs/host/ufs-spacemit.h +new file mode 100644 +index 000000000000..6ae3c263a360 +--- /dev/null ++++ b/drivers/ufs/host/ufs-spacemit.h +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * SpacemiT UFS Host Controller driver ++ * ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ */ ++ ++#ifndef _UFS_SPACEMIT_H_ ++#define _UFS_SPACEMIT_H_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* Spacemit K3 UFS host controller vendor specific registers */ ++#define UFS_SYS1CLK_1US 0xC0 ++#define UFS_TX_SYMBOL_CLK_NS_US 0xC4 ++#define UFS_LOCAL_PORT_ID_REG 0xC8 ++#define UFS_PA_ERR_CODE 0xCC ++#define UFS_RETRY_TIMER_REG 0xD0 ++#define UFS_PA_LINK_STARTUP_TIMER 0xD8 ++#define UFS_CFG1 0xDC ++ ++/* MPHY control registers */ ++#define UFS_PHY_MNG_BASE 0x1B00 ++#define UFS_MPHY_RST_CTRL 0x0 ++#define UFS_MPHY_PU_CTRL 0x4 ++#define UFS_MPHY_BKDR_CTRL 0x8 ++#define UFS_DEVICE_IO_CTRL 0xC ++ ++/* ATOP base*/ ++#define UFS_ATOP_BASE 0x1C00 ++ ++#define UFS_SYSCLK 499 ++#define UFS_TX_SYMBO_CLK 0x800 ++#define UFS_MAX_LINKSTARTUP_TIMER 0xFFFFFFFF ++#define UFS_DL_AFC0REQTIMEOUTVAL_MAX 0xFFFF ++ ++#define MPHY_TX_FSM_STATE 0x41 ++#define TX_FSM_HIBERN8 0x1 ++#define HBRN8_POLL_TOUT_MS 100 ++#define DEFAULT_CLK_RATE_HZ 1000000 ++#define BUS_VECTOR_NAME_LEN 32 ++ ++#define UFS_HW_VER_MAJOR_SHFT 28 ++#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) ++#define UFS_HW_VER_MINOR_SHFT 16 ++#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) ++#define UFS_HW_VER_STEP_SHFT 0 ++#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) ++ ++#define UFS_SPACEMIT_K3_LIMIT_NUM_LANES_RX 2 ++#define UFS_SPACEMIT_K3_LIMIT_NUM_LANES_TX 2 ++#define UFS_SPACEMIT_K3_LIMIT_HSGEAR_RX UFS_HS_G3 ++#define UFS_SPACEMIT_K3_LIMIT_HSGEAR_TX UFS_HS_G3 ++#define UFS_SPACEMIT_K3_LIMIT_PWMGEAR_RX UFS_PWM_G4 ++#define UFS_SPACEMIT_K3_LIMIT_PWMGEAR_TX UFS_PWM_G4 ++#define UFS_SPACEMIT_K3_LIMIT_RX_PWR_PWM SLOW_MODE ++#define UFS_SPACEMIT_K3_LIMIT_TX_PWR_PWM SLOW_MODE ++#define UFS_SPACEMIT_K3_LIMIT_RX_PWR_HS FAST_MODE ++#define UFS_SPACEMIT_K3_LIMIT_TX_PWR_HS FAST_MODE ++#define UFS_SPACEMIT_K3_LIMIT_HS_RATE PA_HS_MODE_B ++#define UFS_SPACEMIT_K3_LIMIT_DESIRED_MODE 2 ++ ++#define UFS_PA_VS_CONFIG_REG1 0x9000 ++#define UFS_DME_VS_CORE_CLK_CTRL 0xD002 ++ ++#define UFS_HCLKDIV_REG 0xFC ++ ++struct ufs_spacemit_host { ++ struct ufs_hba *hba; ++ struct ufs_pa_layer_attr dev_req_params; ++ struct reset_control *rst; ++ u32 caps; ++ u32 lpm_qos; ++ u32 unipro_ver; ++ u32 remote_unipro_ver; ++ u8 prev_request_crypto; ++ ++ bool is_lane_clks_on; ++ bool first_init_done; ++ bool first_hce_done; ++ ++ /* Workqueue for deferred FSM state dump */ ++ struct work_struct fsm_dump_work; ++}; ++ ++#endif /* _UFS_SPACEMIT_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0527-FROMLIST-riscv-dts-spacemit-k3-Add-UFS-support.patch b/SPECS/linux-lts-kmhv2/0527-FROMLIST-riscv-dts-spacemit-k3-Add-UFS-support.patch new file mode 100644 index 0000000000..7cfae1033d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0527-FROMLIST-riscv-dts-spacemit-k3-Add-UFS-support.patch @@ -0,0 +1,67 @@ +From d5b71c210c3bcb18e2afe2d3940f43c56d2827bf Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 2 Jul 2026 02:31:37 +0000 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add UFS support + +Add UFS Host Controller support for SpacemiT K3 SoC, and enable +it both on both Pico-ITX and CoM260-IFX boards. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260702-08-k3-ufs-support-v1-3-1a64a3ab128f@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts | 4 ++++ + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 4 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 13 +++++++++++++ + 3 files changed, 21 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +index e7f76cd24b90..91bc8c0a2ed9 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -37,3 +37,7 @@ &sdhci0 { + sd-uhs-sdr104; + status = "okay"; + }; ++ ++&ufshc { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 8b2a120b02d1..c7ecb2f5cb4d 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -317,3 +317,7 @@ hub@1 { + &usb2_phy { + status = "okay"; + }; ++ ++&ufshc { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index fc46e34465e4..862e5698972e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1216,5 +1216,18 @@ maplic: interrupt-controller@f1800000 { + riscv,num-sources = <512>; + status = "reserved"; + }; ++ ++ ufshc: ufshc@c0e00000 { ++ compatible = "spacemit,k3-ufshc"; ++ reg = <0x0 0xc0e00000 0x0 0x40000>; ++ clocks = <&syscon_apmu CLK_APMU_UFS_ACLK>, ++ <&syscon_apmu CLK_APMU_UFS_REFCLK>; ++ clock-names = "aclk", "ref_clk"; ++ resets = <&syscon_apmu RESET_APMU_UFS_ACLK>; ++ interrupts = <135 IRQ_TYPE_LEVEL_HIGH>; ++ freq-table-hz = <491520000 491520000 19200000 19200000>; ++ lanes-per-direction = <2>; ++ status = "disabled"; ++ }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0528-FROMLIST-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-c.patch b/SPECS/linux-lts-kmhv2/0528-FROMLIST-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-c.patch new file mode 100644 index 0000000000..43c521362a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0528-FROMLIST-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-c.patch @@ -0,0 +1,95 @@ +From 761a9312a0023c41f12b4561170ecf1df809dc1d Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 3 Jul 2026 10:10:22 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: Add Spacemit K3 USB3/PCIe + comb phy support + +The USB3/PCIe comb PHY on the K3 is a complex PHY group that +can provide multiple phy for both PCIe and USB controller. +Its mux configuration is controlled by the APMU syscon device. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260703021024.495433-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k3-combo-phy.yaml | 68 +++++++++++++++++++ + 1 file changed, 68 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +new file mode 100644 +index 000000000000..ed820cf697b8 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +@@ -0,0 +1,68 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 PCIE/USB3 Comb PHY ++ ++maintainers: ++ - Inochi Amaoto ++ ++properties: ++ compatible: ++ const: spacemit,k3-combo-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 2 ++ description: ++ The first one is phy id, the second one is phy type. This ++ only supports types are PCIe and USB . ++ ++ spacemit,apb-spare: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to APB SPARE system controller interface, used for ++ PHY calibration. ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle of APMU syscon ++ - description: configuration of the PHY lanes ++ description: | ++ Phandle to control PHY mux configuration. The configuration ++ is described as follows: ++ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode ++ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode ++ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode ++ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode ++ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode ++ ++ The bit[3:0] is only valid when bit 4 is 1. ++ ++ This mux control does not affect the PHY for PCIe E, it is always ++ in PCIe mode. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ - spacemit,apb-spare ++ - spacemit,apmu ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x81d00000 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&apb_spare>; ++ spacemit,apmu = <&apmu 0x00>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0529-FROMLIST-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-.patch b/SPECS/linux-lts-kmhv2/0529-FROMLIST-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-.patch new file mode 100644 index 0000000000..a881ddffb1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0529-FROMLIST-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-.patch @@ -0,0 +1,751 @@ +From 19a2632222f27e50adbb383893af270b0469c06a Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 3 Jul 2026 10:10:23 +0800 +Subject: [RUYI PATCH] FROMLIST: phy: spacemit: Add USB3/PCIe comb PHY driver + for Spacemit K3 + +The comb PHY on K3 requires to configure a syscon device for the +right mux configuration. And it requires calibration before any +usage. + +Add USB3/PCIe comb PHY driver for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260703021024.495433-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/Kconfig | 16 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k3-combo.c | 252 +++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.c | 391 +++++++++++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.h | 27 ++ + 5 files changed, 688 insertions(+) + create mode 100644 drivers/phy/spacemit/phy-k3-combo.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.h + +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 50b0005acf66..5fdf18fce499 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -23,3 +23,19 @@ config PHY_SPACEMIT_K1_USB2 + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. ++ ++config PHY_SPACEMIT_K3_COMMON_OPS ++ tristate ++ select MFD_SYSCON ++ select GENERIC_PHY ++ ++config PHY_SPACEMIT_K3_COMBO_PHY ++ tristate "SpacemiT K3 USB3/PCIe PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ select PHY_SPACEMIT_K3_COMMON_OPS ++ help ++ Enable this to support K3 USB3/PCIe combo PHY driver. This ++ driver takes care of enabling and clock setup and will be used ++ by K3 dwc3 driver. ++ If unsure, say N. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index a821a21d6142..f679c1851b4f 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,3 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o +diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c +new file mode 100644 +index 000000000000..0bc08bb6247a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-combo.c +@@ -0,0 +1,252 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * phy-k3-combo.c - SpacemiT K3 PCIe/USB3 Combo PHY Driver ++ * ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* ++ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs ++ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. ++ * ++ * PMUA_PCIE_SUBSYS_MGMT[4:0] ++ * ++ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A ++ * 1 : PHY lanes shared between PCIe or USB according to [3:0] ++ * ++ * All PHY matrix combinations according to [4:0]: ++ * ++ * 0x0X : PCIe-A X8 ++ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) ++ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) ++ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) ++ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) ++ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) ++ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) ++ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * ++ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. ++ */ ++#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 ++#define PU_MATRIX_CONF_MASK GENMASK(4, 0) ++ ++#define COMBPHY_MAX_SUBPHYS 6 ++ ++struct k3_combo_phy { ++ struct device *dev; ++ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; ++ void __iomem *base; ++ struct regmap *apb_spare; ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x0, 0x400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x100000, 0x100400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { ++ .lanes = 1, ++ .config = 0x14, ++ .mask = 0x14, ++ .offsets = { ++ 0x200000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { ++ .lanes = 1, ++ .config = 0x12, ++ .mask = 0x12, ++ .offsets = { ++ 0x300000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { ++ .lanes = 1, ++ .config = 0x11, ++ .mask = 0x11, ++ .offsets = { ++ 0x400000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { ++ .lanes = 1, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x500000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { ++ &k3_combphy_lane_group0, ++ &k3_combphy_lane_group1, ++ &k3_combphy_lane_group2, ++ &k3_combphy_lane_group3, ++ &k3_combphy_lane_group4, ++ &k3_combphy_lane_group5, ++}; ++ ++static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { ++ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; ++ struct k3_lane_group *lg = &phy->groups[i]; ++ const struct phy_ops *ops; ++ bool is_usb; ++ ++ is_usb = (data->mask & config) == data->config; ++ if (is_usb) ++ ops = &k3_usb3_phy_ops; ++ else ++ ops = &k3_pcie_phy_ops; ++ ++ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); ++ ++ lg->phy = devm_phy_create(phy->dev, NULL, ops); ++ if (IS_ERR(lg->phy)) ++ return PTR_ERR(lg->phy); ++ ++ lg->is_pcie = !is_usb; ++ lg->data = data; ++ lg->base = phy->base; ++ phy_set_drvdata(lg->phy, lg); ++ } ++ ++ return 0; ++} ++ ++static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) ++{ ++ if (config & ~PU_MATRIX_CONF_MASK) ++ return -EINVAL; ++ ++ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); ++} ++ ++static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k3_combo_phy *phy = dev_get_drvdata(dev); ++ struct k3_lane_group *lg; ++ ++ if (args->args_count != 2) { ++ dev_err(dev, "Invalid number of arguments\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { ++ dev_err(dev, "Invalid PHY id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ lg = &phy->groups[args->args[0]]; ++ ++ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || ++ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { ++ dev_err(dev, "Invalid PHY mode\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return lg->phy; ++} ++ ++static int k3_combo_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct phy_provider *provider; ++ struct k3_combo_phy *phy; ++ struct regmap *apmu; ++ u32 config = 0; ++ int ret; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->base)) ++ return PTR_ERR(phy->base); ++ ++ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); ++ if (IS_ERR(phy->apb_spare)) ++ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), ++ "Failed to find APB SPARE syscon"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to find APMU syscon"); ++ ++ ret = k3_combo_phy_update_config(apmu, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to set lane configuration"); ++ ++ phy->dev = dev; ++ platform_set_drvdata(pdev, phy); ++ ++ ret = k3_phy_calibrate(phy->apb_spare); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to calibrate phy"); ++ ++ ret = k3_combo_phy_init_lanes(phy, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to init lanes"); ++ ++ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "Failed to register provider\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id k3_combo_phy_of_match[] = { ++ { .compatible = "spacemit,k3-combo-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); ++ ++static struct platform_driver k3_combo_phy_driver = { ++ .probe = k3_combo_phy_probe, ++ .driver = { ++ .name = "spacemit,k3-combo-phy", ++ .of_match_table = k3_combo_phy_of_match, ++ }, ++}; ++module_platform_driver(k3_combo_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c +new file mode 100644 +index 000000000000..0b289e63db99 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.c +@@ -0,0 +1,391 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* PHY Registers */ ++#define PHY_VERSION 0x0 ++ ++#define PHY_RESET_CFG 0x04 ++ ++#define PHY_RESET_RXBUF_RST BIT(0) ++#define PHY_RESET_SOFT_RST_PCS BIT(1) ++#define PHY_RESET_SOFT_RST_AHB BIT(2) ++#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) ++ ++#define PHY_CLK_CFG 0x08 ++ ++#define PHY_CLK_PLL_READY BIT(0) ++#define PHY_CLK_TXCLK_INV BIT(2) ++#define PHY_CLK_RXCLK_EN BIT(3) ++#define PHY_CLK_TXCLK_EN BIT(4) ++#define PHY_CLK_PCLK_EN BIT(5) ++#define PHY_CLK_PIPE_PCLK_EN BIT(6) ++#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) ++#define PHY_CLK_REFCLK_24M 2 ++#define PHY_CLK_SW_INIT_DONE BIT(11) ++#define PHY_CLK_PU_SSC_OUT BIT(23) ++ ++#define PHY_MODE_CFG 0x0C ++ ++#define PHY_MODE_PCIE_INT_EN BIT(0) ++#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) ++#define PHY_MODE_LFPS_TPERIOD_USB 3 ++ ++#define PHY_PU_SEL 0x40 ++ ++#define PHY_PU_CFG_STATUS BIT(9) ++#define PHY_PU_OVRD_STATUS BIT(10) ++ ++#define PHY_PU_CK_REG 0x54 ++ ++#define PHY_PU_REFCLK_100 BIT(25) ++ ++#define PHY_PLL_REG1 0x58 ++ ++#define PHY_PLL_FREF_SEL GENMASK(15, 13) ++#define PHY_PLL_FREF_24M 0x1 ++#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) ++#define PHY_PLL_SSC_5000PPM 0xa ++#define PHY_PLL_SSC_MODE GENMASK(29, 28) ++#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 ++#define PHY_PLL_SSC_MODE_UP_SPREAD 1 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 ++ ++#define PHY_PLL_REG2 0x5c ++ ++#define PHY_PLL_SEL_REF100 BIT(21) ++ ++/* PHY RX Register Definitions */ ++#define PHY_RX_REG_A 0x60 ++ ++#define PHY_RX_REG0_MASK GENMASK(7, 0) ++#define PHY_RX_REG1_MASK GENMASK(15, 8) ++#define PHY_RX_REG2_MASK GENMASK(23, 16) ++#define PHY_RX_REG3_MASK GENMASK(31, 24) ++ ++#define PHY_RX_REG0_RLOAD BIT(4) ++#define PHY_RX_REG1_RTERM GENMASK(11, 8) ++#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) ++#define PHY_RX_REG2_CSEL GENMASK(19, 16) ++#define PHY_RX_REG2_FORCE_CSEL BIT(20) ++#define PHY_RX_REG2_PSEL GENMASK(23, 21) ++#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) ++#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) ++#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) ++#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) ++ ++#define PHY_RX_REG_B 0x64 ++ ++#define PHY_RX_REG4_MASK GENMASK(7, 0) ++#define PHY_RX_REG5_MASK GENMASK(15, 8) ++#define PHY_RX_REG6_MASK GENMASK(23, 16) ++ ++#define PHY_RX_REGB_MASK GENMASK(23, 0) ++ ++#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) ++#define PHY_RX_REG4_ENVOS BIT(4) ++#define PHY_RX_REG4_RTERM_SEL BIT(5) ++#define PHY_RX_REG4_MANUAL_CFG BIT(7) ++#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) ++#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) ++#define PHY_RX_REG6_H1_REG GENMASK(19, 16) ++#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) ++#define PHY_RX_REG6_BYPASS_ADPT BIT(22) ++ ++#define PHY_ADPT_CFG0 0x140 ++#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) ++#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) ++ ++#define PHY_RXEQ_TIME 0xb4 ++#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) ++#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) ++#define PHY_RXEQ_TIME_AMP_SOC_650M 0 ++#define PHY_RXEQ_TIME_AMP_SOC_800M 1 ++#define PHY_RXEQ_TIME_AMP_SOC_870M 2 ++#define PHY_RXEQ_TIME_AMP_SOC_900M 3 ++#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) ++ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PHY_CLK_PLL_READY BIT(0) ++#define PCIE_INITAL_TIMER GENMASK(6, 3) ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define CFG_SW_PHY_INIT_DONE BIT(11) ++ ++/* Lane RX/TX configuration (per‑lane, at lane_base) */ ++#define PCIE_RX_REG1 0x050 ++#define PCIE_RX_REFCLK_MODE GENMASK(1, 0) ++#define PCIE_RX_REFCLK_MODE_DRIVER 1 ++#define PCIE_RX_SEL_TRI_CODE BIT(2) ++#define PCIE_RX_LEGACY GENMASK(15, 8) ++#define PCIE_RX_LEGACY_DEFAULT 0x65 ++ ++#define PCIE_TX_REG1 0x064 ++ ++#define PCIE_PLL_TIMEOUT 500000 ++#define PCIE_POLL_DELAY 500 ++ ++static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) ++{ ++ struct phy *phy = lg->phy; ++ u32 val, tmp; ++ int ret; ++ ++ /* Do not wait CDR lock before sampling data */ ++ val = readl(base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); ++ writel(val, base + PHY_RESET_CFG); ++ ++ /* Power down 100MHz refclk buffer */ ++ val = readl(base + PHY_PU_CK_REG); ++ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); ++ writel(val, base + PHY_PU_CK_REG); ++ ++ /* Program PLL REG1 configure the SSC */ ++ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | ++ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | ++ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); ++ writel(val, base + PHY_PLL_REG1); ++ ++ /* Un-select 100MHz PLL reference */ ++ val = readl(base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); ++ writel(val, base + PHY_PLL_REG2); ++ ++ /* USB LFPS period configuration */ ++ val = readl(base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); ++ writel(val, base + PHY_MODE_CFG); ++ ++ /* Force AFE adaptation reset */ ++ val = readl(base + PHY_ADPT_CFG0); ++ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; ++ writel(val, base + PHY_ADPT_CFG0); ++ ++ /* Override driver amplitude value to 900m */ ++ val = readl(base + PHY_RXEQ_TIME); ++ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; ++ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); ++ writel(val, base + PHY_RXEQ_TIME); ++ ++ /* Configure RX parameters */ ++ val = PHY_RX_REG0_RLOAD | ++ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | ++ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | ++ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | ++ PHY_RX_REG2_FORCE_CSEL | ++ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | ++ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | ++ PHY_RX_REG3_SEL_CBOOST_CODE | ++ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | ++ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); ++ writel(val, base + PHY_RX_REG_A); ++ ++ val = readl(base + PHY_RX_REG_B); ++ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | ++ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | ++ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | ++ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); ++ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); ++ writel(val, base + PHY_RX_REG_B); ++ ++ /* ++ * Inform PHY that all PLL-related configuration is done. ++ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. ++ */ ++ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | ++ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | ++ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | ++ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; ++ writel(val, base + PHY_CLK_CFG); ++ ++ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), ++ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&phy->dev, "PHY PLL polling timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int k3_usb3phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ int ret, i; ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_usb3_phy_ops = { ++ .init = k3_usb3phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); ++ ++static int k3_pcie_phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ void __iomem *phy_base = lg->base + lg->data->offsets[0]; ++ u32 val; ++ int ret; ++ int i; ++ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, BIT(21)); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ val = readl(lane_base + PCIE_RX_REG1); ++ val = u32_replace_bits(val, 0, 0x3); ++ writel(val, lane_base + PCIE_RX_REG1); ++ } ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val |= BIT(20); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ /* The write is needed as clock requires renegotiation */ ++ val = FIELD_PREP(PCIE_RX_REFCLK_MODE, PCIE_RX_REFCLK_MODE_DRIVER) | ++ PCIE_RX_SEL_TRI_CODE | ++ FIELD_PREP(PCIE_RX_LEGACY, PCIE_RX_LEGACY_DEFAULT); ++ writel(val, phy_base + PCIE_RX_REG1); ++ ++ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0, GENMASK(27, 24)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ ++ val = readl(lane_base + PHY_PU_SEL); ++ val = u32_replace_bits(val, 1, BIT(13)); ++ writel(val, lane_base + PHY_PU_SEL); ++ ++ /* disable en_sample_data_after_cdr_locked */ ++ val = readl(lane_base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, BIT(6)); ++ writel(val, lane_base + PHY_RESET_CFG); ++ ++ /* Dynamic Lock */ ++ val = readl(lane_base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, 1, BIT(2)); ++ writel(val, lane_base + PHY_MODE_CFG); ++ ++ val = FIELD_PREP(PHY_RX_REG0_MASK, 0x10) | ++ FIELD_PREP(PHY_RX_REG1_MASK, 0x78) | ++ FIELD_PREP(PHY_RX_REG2_MASK, 0x98) | ++ FIELD_PREP(PHY_RX_REG3_MASK, 0xdf); ++ writel(val, lane_base + PHY_RX_REG_A); ++ ++ val = readl(lane_base + PHY_RX_REG_B); ++ val &= ~PHY_RX_REGB_MASK; ++ val |= FIELD_PREP(PHY_RX_REG4_MASK, 0xb4) | ++ FIELD_PREP(PHY_RX_REG5_MASK, 0x88) | ++ FIELD_PREP(PHY_RX_REG6_MASK, 0x28); ++ writel(val, lane_base + PHY_RX_REG_B); ++ ++ /* Set init done */ ++ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); ++ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); ++ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); ++ } ++ ++ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, ++ PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_pcie_phy_ops = { ++ .init = k3_pcie_phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); ++ ++/* PHY rcal init requires APB_SPARE regmap access */ ++ ++#define APB_SPARE_PU_CAL 0x178 ++#define PU_CAL BIT(17) ++ ++#define APB_SPARE_RCAL_HSIO 0x17c ++#define APB_SPARE_PU_CAL_DONE BIT(8) ++#define RCAL_OVRD_PTRIM GENMASK(23, 20) ++#define RCAL_OVRD_NTRIM GENMASK(27, 24) ++#define RCAL_OVRD_PTRIM_EN BIT(28) ++#define RCAL_OVRD_NTRIM_EN BIT(29) ++#define RCAL_OVRD_STABLE_VAL BIT(30) ++#define RCAL_OVRD_STABLE_EN BIT(31) ++ ++#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) ++#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) ++ ++#define PU_CAL_TIMEOUT 2000000 ++ ++static DEFINE_MUTEX(calibrate_lock); ++ ++int k3_phy_calibrate(struct regmap *apb_spare) ++{ ++ unsigned int val = 0; ++ int ret; ++ ++ guard(mutex)(&calibrate_lock); ++ ++ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); ++ if (val & APB_SPARE_PU_CAL_DONE) ++ return 0; ++ ++ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, ++ PU_CAL); ++ ++ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, ++ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, ++ PU_CAL_TIMEOUT); ++ ++ if (ret) ++ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | ++ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | ++ RCAL_OVRD_STABLE_EN); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(k3_phy_calibrate); ++ ++MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h +new file mode 100644 +index 000000000000..49009c3c313a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _PHY_K3_COMMON_H ++#define _PHY_K3_COMMON_H ++ ++#include ++ ++struct k3_phy_lane_group_data { ++ u32 lanes; ++ u8 config; ++ u8 mask; ++ u32 offsets[] __counted_by(lanes); ++}; ++ ++struct k3_lane_group { ++ const struct k3_phy_lane_group_data *data; ++ void __iomem *base; ++ struct phy *phy; ++ bool is_pcie; ++}; ++ ++extern const struct phy_ops k3_pcie_phy_ops; ++extern const struct phy_ops k3_usb3_phy_ops; ++ ++int k3_phy_calibrate(struct regmap *apb_spare); ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0530-FROMLIST-gpio-sifive-add-missing-MODULE_DEVICE_TABLE.patch b/SPECS/linux-lts-kmhv2/0530-FROMLIST-gpio-sifive-add-missing-MODULE_DEVICE_TABLE.patch new file mode 100644 index 0000000000..891cf34f03 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0530-FROMLIST-gpio-sifive-add-missing-MODULE_DEVICE_TABLE.patch @@ -0,0 +1,38 @@ +From b4b8c09ba9b89f134f5d2517191a1cdca3cc4916 Mon Sep 17 00:00:00 2001 +From: Pengpeng Hou +Date: Sat, 4 Jul 2026 20:22:30 +0800 +Subject: [RUYI PATCH] FROMLIST: gpio: sifive: add missing + MODULE_DEVICE_TABLE() + +The driver has an OF match table wired to .of_match_table, but does +not export the table with MODULE_DEVICE_TABLE(). + +Add the missing MODULE_DEVICE_TABLE(of, ...) entry so module alias +information is generated for OF based module autoloading. + +This is a source-level fix. It does not claim dynamic hardware +reproduction; the evidence is the driver-owned match table, its use by +the platform driver, and the missing module alias publication. + +Signed-off-by: Pengpeng Hou +Link: https://lore.kernel.org/r/20260704122230.75964-1-pengpeng@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-sifive.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c +index 94ef2efbd14f..e9a992cd4b9c 100644 +--- a/drivers/gpio/gpio-sifive.c ++++ b/drivers/gpio/gpio-sifive.c +@@ -260,6 +260,7 @@ static const struct of_device_id sifive_gpio_match[] = { + { .compatible = "sifive,fu540-c000-gpio" }, + { }, + }; ++MODULE_DEVICE_TABLE(of, sifive_gpio_match); + + static struct platform_driver sifive_gpio_driver = { + .probe = sifive_gpio_probe, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0531-FROMLIST-PCI-dwc-spacemit-add-missing-MODULE_DEVICE_.patch b/SPECS/linux-lts-kmhv2/0531-FROMLIST-PCI-dwc-spacemit-add-missing-MODULE_DEVICE_.patch new file mode 100644 index 0000000000..3e35d82f3e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0531-FROMLIST-PCI-dwc-spacemit-add-missing-MODULE_DEVICE_.patch @@ -0,0 +1,38 @@ +From 099f5123116f3b3a4f1b8f9cd14915ed44b718db Mon Sep 17 00:00:00 2001 +From: Pengpeng Hou +Date: Sat, 4 Jul 2026 20:25:38 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: dwc: spacemit: add missing + MODULE_DEVICE_TABLE() + +The driver has an OF match table wired to .of_match_table, but does +not export the table with MODULE_DEVICE_TABLE(). + +Add the missing MODULE_DEVICE_TABLE(of, ...) entry so module alias +information is generated for OF based module autoloading. + +This is a source-level fix. It does not claim dynamic hardware +reproduction; the evidence is the driver-owned match table, its use by +the platform driver, and the missing module alias publication. + +Signed-off-by: Pengpeng Hou +Link: https://lore.kernel.org/r/20260704122538.92830-1-pengpeng@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 680acc93f539..7502d66bd0d0 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -547,6 +547,7 @@ static const struct of_device_id k1_pcie_of_match_table[] = { + { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, + { } + }; ++MODULE_DEVICE_TABLE(of, k1_pcie_of_match_table); + + static struct platform_driver k1_pcie_driver = { + .probe = k1_pcie_probe, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0532-FROMLIST-riscv-stacktrace-Fix-NULL-task-pointer-in-f.patch b/SPECS/linux-lts-kmhv2/0532-FROMLIST-riscv-stacktrace-Fix-NULL-task-pointer-in-f.patch new file mode 100644 index 0000000000..5ef6a82df3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0532-FROMLIST-riscv-stacktrace-Fix-NULL-task-pointer-in-f.patch @@ -0,0 +1,51 @@ +From 36246e7cbaca481c4c172427c4e9ab9f202f74c4 Mon Sep 17 00:00:00 2001 +From: Anmeng Zhang +Date: Wed, 8 Jul 2026 09:50:46 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: stacktrace: Fix NULL task pointer in + ftrace_graph_ret_addr() + +When dump_backtrace() is called with a NULL task argument, and the +call stack contains functions that are being traced, +walk_stackframe() eventually calls ftrace_graph_ret_addr() with the +NULL task pointer, which results in a NULL pointer dereference when +accessing task->curr_ret_stack. + +Fix this by assigning the task pointer to the current task in +walk_stackframe() when it is NULL, keeping the behavior consistent +with other architectures. + +Fixes: ecbf894165a2 ("riscv: Fix ftrace_graph_ret_addr() to use the correct task pointer") +Reviewed-by: Shengming Hu +Reviewed-by: Rui Gao +Reviewed-by: Luo Haiyang +Reviewed-by: Run Zhang +Signed-off-by: Anmeng Zhang +Link: https://lore.kernel.org/r/20260708095046716mVQlEvhyoXko9eueCxict@zte.com.cn +Signed-off-by: Han Gao +--- + arch/riscv/kernel/stacktrace.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c +index b41b6255751c..694c9c7fde4a 100644 +--- a/arch/riscv/kernel/stacktrace.c ++++ b/arch/riscv/kernel/stacktrace.c +@@ -52,11 +52,14 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, + int graph_idx = 0; + int level = 0; + ++ if (task == NULL) ++ task = current; ++ + if (regs) { + fp = frame_pointer(regs); + sp = user_stack_pointer(regs); + pc = instruction_pointer(regs); +- } else if (task == NULL || task == current) { ++ } else if (task == current) { + fp = (unsigned long)__builtin_frame_address(0); + sp = current_stack_pointer; + pc = (unsigned long)walk_stackframe; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0533-FROMLIST-riscv-ftrace-only-use-pre-function-NOPs-wit.patch b/SPECS/linux-lts-kmhv2/0533-FROMLIST-riscv-ftrace-only-use-pre-function-NOPs-wit.patch new file mode 100644 index 0000000000..ba10609430 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0533-FROMLIST-riscv-ftrace-only-use-pre-function-NOPs-wit.patch @@ -0,0 +1,62 @@ +From 9fc49a04adaf2bb83829be405656fa5d613d5a0c Mon Sep 17 00:00:00 2001 +From: Rui Qi +Date: Mon, 6 Jul 2026 20:35:54 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: only use pre-function NOPs with + call ops + +Commit c217157bcd1d ("riscv: Implement +HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS") changed CC_FLAGS_FTRACE to use +-fpatchable-function-entry=8,4 or -fpatchable-function-entry=4,2 +for all dynamic ftrace builds. That layout makes the compiler place an +8-byte area before the function entry, which is used as the per-callsite +ftrace_ops literal when CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS is enabled. + +RISC-V can still build with CONFIG_DYNAMIC_FTRACE=y and +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS=n, for example when +CONFIG_CFI_CLANG is enabled because HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS +is selected only when !CFI_CLANG. In that configuration +ftrace_call_adjust() does not skip the pre-function literal area and +only returns addr + MCOUNT_AUIPC_SIZE. With the pre-function layout, +that points into the pre-entry padding instead of the callsite jalr, so +dynamic ftrace records the wrong patch address. + +Use the pre-function literal layout only when call ops are enabled. +Otherwise keep the previous patchable-function-entry counts so the +recorded address matches ftrace_call_adjust() non-call-ops path. + +Fixes: c217157bcd1d ("riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS") +Cc: stable@vger.kernel.org +Signed-off-by: Rui Qi +Link: https://lore.kernel.org/r/20260706123554.455065-1-qirui.001@bytedance.com +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 775b5faa4b2e..2dbb6e3c78c9 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -14,11 +14,19 @@ endif + ifeq ($(CONFIG_DYNAMIC_FTRACE),y) + LDFLAGS_vmlinux += --no-relax + KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY ++ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS),y) + ifeq ($(CONFIG_RISCV_ISA_C),y) + CC_FLAGS_FTRACE := -fpatchable-function-entry=8,4 + else + CC_FLAGS_FTRACE := -fpatchable-function-entry=4,2 + endif ++else ++ifeq ($(CONFIG_RISCV_ISA_C),y) ++ CC_FLAGS_FTRACE := -fpatchable-function-entry=4 ++else ++ CC_FLAGS_FTRACE := -fpatchable-function-entry=2 ++endif ++endif + endif + + ifeq ($(CONFIG_CMODEL_MEDLOW),y) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0534-FROMLIST-riscv-vdso-Only-try-to-install-vDSO-when-pr.patch b/SPECS/linux-lts-kmhv2/0534-FROMLIST-riscv-vdso-Only-try-to-install-vDSO-when-pr.patch new file mode 100644 index 0000000000..5a02241193 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0534-FROMLIST-riscv-vdso-Only-try-to-install-vDSO-when-pr.patch @@ -0,0 +1,38 @@ +From 2b8b9475a2f3b59d8c0181d57e39de5dbb38f138 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Thu, 9 Jul 2026 08:49:00 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: vdso: Only try to install vDSO when + present +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +vdso.so.dbg is only built with CONFIG_MMU. + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202607090258.iSAUYlO1-lkp@intel.com/ +Fixes: f157d411a9eb ("riscv: add missing vdso_install target") +Fixes: 3edf39916977 ("vDSO, kbuild: Provide vDSO debug variants at runtime") +Signed-off-by: Thomas Weißschuh +Link: https://lore.kernel.org/r/20260709-riscv-install-vdso-v1-1-0ba4345419ca@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 2dbb6e3c78c9..1256e91714ef 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -172,7 +172,7 @@ vdso_prepare: prepare0 + endif + endif + +-vdso-install-y += arch/riscv/kernel/vdso/vdso.so.dbg ++vdso-install-$(CONFIG_MMU) += arch/riscv/kernel/vdso/vdso.so.dbg + vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg + + BOOT_TARGETS := Image Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zst Image.xz loader loader.bin xipImage vmlinuz.efi +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0535-FROMLIST-riscv-dts-spacemit-k3-add-USB-controller-an.patch b/SPECS/linux-lts-kmhv2/0535-FROMLIST-riscv-dts-spacemit-k3-add-USB-controller-an.patch new file mode 100644 index 0000000000..d1a7910ed0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0535-FROMLIST-riscv-dts-spacemit-k3-add-USB-controller-an.patch @@ -0,0 +1,110 @@ +From 15cf4e848cdfd439dc8f1be567b3141aba5aa4dd Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:04:13 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add USB controller + and USB phy support + +Add all USB device node to the Spacemit K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040415.977784-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index c7ecb2f5cb4d..c418cd4fb7d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -220,6 +220,11 @@ dldo7: dldo7 { + }; + }; + ++&combophy { ++ spacemit,apmu = <&syscon_apmu 0x11>; ++ status = "okay"; ++}; ++ + ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; +@@ -318,6 +323,14 @@ &usb2_phy { + status = "okay"; + }; + ++&usb3d_u2phy { ++ status = "okay"; ++}; ++ ++&usb3d { ++ status = "okay"; ++}; ++ + &ufshc { + status = "okay"; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 862e5698972e..ef75a70c94a0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + /dts-v1/; + +@@ -438,6 +439,47 @@ soc: soc { + dma-noncoherent; + ranges; + ++ usb3d: usb@81a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81a00000 0x0 0x10000>; ++ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_D_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_D_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3d_u2phy>, ++ <&combophy 4 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3d_u2phy: phy@81b00000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81b00000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combophy: phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x0 0x81d00000 0x0 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&pll>; ++ status = "disabled"; ++ }; ++ + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0536-FROMLIST-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts-kmhv2/0536-FROMLIST-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch new file mode 100644 index 0000000000..fa574ac96c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0536-FROMLIST-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch @@ -0,0 +1,318 @@ +From 9f73b927d59d145d16de86b92fa0375f38c2e133 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:04:14 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add PCIe device node + +Add all PCIe device node for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040415.977784-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 195 +++++++++++++++++++ + 3 files changed, 266 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index c418cd4fb7d6..cb51126bf4e4 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -301,6 +301,44 @@ uboot@210000 { + }; + }; + ++&pcie0_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_0_cfg>; ++ num-lanes = <4>; ++ status = "okay"; ++ ++ pcie@0 { ++ vpcie3v3-supply = <®_aux_vcc3v3>; ++ phys = <&combophy 0 PHY_TYPE_PCIE>, ++ <&combophy 1 PHY_TYPE_PCIE>; ++ }; ++}; ++ ++&pcie2_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_cfg>; ++ num-lanes = <2>; ++ status = "okay"; ++ ++ pcie@0 { ++ vpcie3v3-supply = <®_aux_vcc3v3>; ++ phys = <&combophy 2 PHY_TYPE_PCIE>, ++ <&combophy 3 PHY_TYPE_PCIE>; ++ }; ++}; ++ ++&pcie4_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie4_0_cfg>; ++ num-lanes = <1>; ++ status = "okay"; ++ ++ pcie@0 { ++ vpcie3v3-supply = <®_aux_vcc3v3>; ++ phys = <&combophy 5 PHY_TYPE_PCIE>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 5b9045e01434..746eb2ee1799 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -722,6 +722,39 @@ uart0-0-pins { + }; + }; + ++ pcie0_0_cfg: pcie0-0-cfg { ++ pcie0-0-pins { ++ pinmux = , /* pcie0 perst */ ++ ; /* pcie0 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ pcie2_0_cfg: pcie2-0-cfg { ++ pcie2-0-pins { ++ pinmux = , /* pcie2 perst */ ++ ; /* pcie2 clkreq */ ++ ++ drive-strength = <38>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ pcie4_0_cfg: pcie4-0-cfg { ++ pcie4-0-pins { ++ pinmux = , /* pcie4 perst */ ++ , /* pcie4 wake */ ++ ; /* pcie4 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ + mmc1_cfg: mmc1-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1 dat3 */ +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index ef75a70c94a0..d7beabc88d86 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -439,6 +439,201 @@ soc: soc { + dma-noncoherent; + ranges; + ++ pcie0_rc: pcie@80000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80000000 0x0 0x00001000>, ++ <0x0 0x80300000 0x0 0x00003f20>, ++ <0x11 0x00000000 0x0 0x00010000>, ++ <0x0 0x82900000 0x0 0x00001000>, ++ <0x0 0x80100000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ max-link-speed = <3>; ++ linux,pci-domain = <0>; ++ spacemit,apmu = <&syscon_apmu 0x1f0>; ++ status = "disabled"; ++ ++ pcie0_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie1_rc: pcie@80400000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80400000 0x0 0x00001000>, ++ <0x0 0x80700000 0x0 0x00003f20>, ++ <0x11 0x80000000 0x0 0x00010000>, ++ <0x0 0x82c00000 0x0 0x00001000>, ++ <0x0 0x80500000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, ++ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ max-link-speed = <3>; ++ linux,pci-domain = <1>; ++ spacemit,apmu = <&syscon_apmu 0x1d0>; ++ status = "disabled"; ++ ++ pcie1_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie2_rc: pcie@80800000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80800000 0x0 0x00001000>, ++ <0x0 0x80b00000 0x0 0x00003f20>, ++ <0x12 0x00000000 0x0 0x00010000>, ++ <0x0 0x82d00000 0x0 0x00001000>, ++ <0x0 0x80900000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <2>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1c8>; ++ status = "disabled"; ++ ++ pcie2_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie3_rc: pcie@80c00000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80c00000 0x0 0x00001000>, ++ <0x0 0x80f00000 0x0 0x00003f20>, ++ <0x12 0x80000000 0x0 0x00010000>, ++ <0x0 0x82a00000 0x0 0x00001000>, ++ <0x0 0x80d00000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, ++ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, ++ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e0>; ++ status = "disabled"; ++ ++ pcie3_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie4_rc: pcie@81000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x81000000 0x0 0x00001000>, ++ <0x0 0x81300000 0x0 0x00003f20>, ++ <0x12 0xc0000000 0x0 0x00010000>, ++ <0x0 0x82b00000 0x0 0x00001000>, ++ <0x0 0x81100000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, ++ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, ++ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <4>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e8>; ++ status = "disabled"; ++ ++ pcie4_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0537-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch b/SPECS/linux-lts-kmhv2/0537-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch new file mode 100644 index 0000000000..f5c6df9f57 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0537-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch @@ -0,0 +1,35 @@ +From a188bbf049589da3b44ddaf65000884f2167e955 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 10 Jul 2026 14:33:12 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add enough deassert time + for the PHY on PICO ITX + +RTL8211F require at least 50ms deassert to guarantee the register +access, 10ms is only enough for the PHY reset. + +Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") +Signed-off-by: Inochi Amaoto +Tested-by: E Shattow +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260710063314.1030249-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index cb51126bf4e4..c412f7002011 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -238,7 +238,7 @@ phy0: phy@1 { + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; +- reset-deassert-us = <10000>; ++ reset-deassert-us = <50000>; + realtek,aldps-enable; + realtek,clkout-disable; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0538-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch b/SPECS/linux-lts-kmhv2/0538-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch new file mode 100644 index 0000000000..62f0422014 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0538-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch @@ -0,0 +1,33 @@ +From 581d3a2a0e3383f2f9f006c11205d1c5d7d00c91 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 10 Jul 2026 14:33:13 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add enough deassert time + for the PHY on com260 board + +RTL8211F require at least 50ms deassert to guarantee the register +access, 10ms is only enough for the PHY reset. + +Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260710063314.1030249-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +index a38d7b738258..b704b537385c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +@@ -178,7 +178,7 @@ phy1: phy@1 { + reg = <1>; + reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; +- reset-deassert-us = <10000>; ++ reset-deassert-us = <50000>; + }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0539-FROMLIST-Failed-to-reinit-phy-of-spacemit-dwmac-when.patch b/SPECS/linux-lts-kmhv2/0539-FROMLIST-Failed-to-reinit-phy-of-spacemit-dwmac-when.patch new file mode 100644 index 0000000000..19b5cf5d50 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0539-FROMLIST-Failed-to-reinit-phy-of-spacemit-dwmac-when.patch @@ -0,0 +1,74 @@ +From d038896e5e76e45986dcd757f2aa2eb062d59aba Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 12 Jul 2026 12:52:33 +0800 +Subject: [RUYI PATCH] FROMLIST: Failed to reinit phy of spacemit-dwmac when + reset-gpio is present + +TL;DR: + +The DWMAC on Spacemit K3 is failled to register phy after the reload +the driver module (rmmod then insmod). Because the reset-gpio is +asserted while unloading the driver and is not desserted before reading +the c22 id, which leads to a fault. + +Description + +In a few days ago, E Shattow reports he has sufferred the a weird issue, +when unloading the spacemit-dwmac driver and then reloading it, he got +the following error: + +[ 60.713071] mdio_bus stmmac-0: MDIO device at address 1 is missing. + +This only occurs when reloading the driver but the first initialization +successed. After some function tracking, I found it is failed at reading +c22 id. The call graph is as the follows: + +stmmac_mdio_register + mdiobus_alloc + of_mdiobus_register + __of_mdiobus_register + __mdiobus_register + __of_mdiobus_parse_phys + of_mdiobus_child_is_phy + of_mdiobus_register_phy + fwnode_mdiobus_register_phy + get_phy_device + get_phy_c22_id + +By checking the difference between the initialization process and the +reloading process, I found the reset gpio is asserted in the function +mdiobus_unregister(). And there is no any function desserted this reset +gpio in the loading stage. And in the initialization process, the reset +goio is deasserted. + +This bug report is sent as I found it is hard to solve this problem +and ask for help to fix this issue as it is related to the framework +instead of a specific driver. + +The possible workaround I found is as the following, just use the phy +id in the compatible string (Confirmed by dlan): + +Tested-by: E Shattow +Link: https://lore.kernel.org/r/20260712045233.800748-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index c412f7002011..7327eb65593c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -234,7 +234,8 @@ ð0 { + + mdio { + phy0: phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; ++ compatible = "ethernet-phy-id001c.c916", ++ "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0540-FROMLIST-riscv-mm-Make-mark_new_valid_map-stuff-depe.patch b/SPECS/linux-lts-kmhv2/0540-FROMLIST-riscv-mm-Make-mark_new_valid_map-stuff-depe.patch new file mode 100644 index 0000000000..e5a2ec8689 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0540-FROMLIST-riscv-mm-Make-mark_new_valid_map-stuff-depe.patch @@ -0,0 +1,68 @@ +From 346dbf0541b3086cf6e288aa170f5d4cae692dff Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 13 Jul 2026 14:15:20 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Make mark_new_valid_map() stuff + depend on 64BIT && MMU + +None of the code relating to mark_new_valid_map() does anything useful +without CONFIG_64BIT=y && CONFIG_MMU=y, because the +new_valid_map_cpus_check code is only used if CONFIG_64BIT, and the +exception codes checked there can only happen with CONFIG_MMU=y. + +Therefore, make these conditional on CONFIG_64BIT=y && CONFIG_MMU=y to +simplify programming, since we do not have to handle CONFIG_MMU=n when +changing this code in the future. This also removes some unused code on +the entry path for CONFIG_MMU=n. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260713-mark-after-vmemmap-populate-v6-1-b945ceba29d4@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 2 +- + arch/riscv/kernel/entry.S | 2 +- + arch/riscv/mm/init.c | 2 ++ + 3 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 1f191cf801a2..939ac3b61ff2 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -42,7 +42,7 @@ do { \ + flush_icache_mm(vma->vm_mm, 0); \ + } while (0) + +-#ifdef CONFIG_64BIT ++#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) + /* This is accessed in assembly code. cpumask_var_t would be too complex. */ + extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 5a97f002bf1f..df3f720ad61f 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -112,7 +112,7 @@ SYM_CODE_START(handle_exception) + .Lrestore_kernel_tpsp: + csrr tp, CSR_SCRATCH + +-#ifdef CONFIG_64BIT ++#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) + /* + * The RISC-V kernel does not flush TLBs on all CPUS after each new + * vmalloc mapping or kfence_unprotect(), which may result in +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index f10c37999f23..715575f68c69 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,9 @@ + + #include "../kernel/head.h" + ++#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) + DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); ++#endif + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0541-FROMLIST-mm-sparse-vmemmap-flush_cache_vmap-after-ho.patch b/SPECS/linux-lts-kmhv2/0541-FROMLIST-mm-sparse-vmemmap-flush_cache_vmap-after-ho.patch new file mode 100644 index 0000000000..41989f347a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0541-FROMLIST-mm-sparse-vmemmap-flush_cache_vmap-after-ho.patch @@ -0,0 +1,65 @@ +From 0c338eb602e2a4922a7c4f5c6ddc9f58bf0fc53f Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 13 Jul 2026 14:15:21 +0800 +Subject: [RUYI PATCH] FROMLIST: mm/sparse-vmemmap: flush_cache_vmap() after + hotplugging vmemmap + +section_activate() does not flush TLB after populating new vmemmap +pages. On most architectures, this is okay. However it is a problem on +RISC-V since there the TLB caching non-present entries is permitted, +which causes spurious faults on some hardwares. + +This seems to be most easily reproduced with DEBUG_VM=y and +PAGE_POISONING=y, which causes these newly mapped struct pages to be +poisoned i.e. written to immediately after mapping. + +Extend the RISC-V flush_cache_vmap() to also handle the vmemmap range, +and call it after hotplugging vmemmap, which gets the possible spurious +fault handled in the exception handler. + +At least for now, the only other architecture with both +SPARSEMEM_VMEMMAP and flush_cache_vmap() is PowerPC, which has a similar +problem with newly valid PTEs. But there flush_cache_vmap() is just a +ptesync. So it should be safe to do this for generic code while having +minimal performance impact. + +Suggested-by: Muchun Song +Signed-off-by: Vivian Wang +Reviewed-by: Muchun Song +Link: https://lore.kernel.org/r/20260713-mark-after-vmemmap-populate-v6-2-b945ceba29d4@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 3 ++- + mm/sparse-vmemmap.c | 2 ++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 939ac3b61ff2..c6297a1d2645 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -69,7 +69,8 @@ static inline void mark_new_valid_map(void) + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) + { +- if (is_vmalloc_or_module_addr((void *)start)) ++ if (is_vmalloc_or_module_addr((void *)start) || ++ (start >= VMEMMAP_START && end <= VMEMMAP_END)) + mark_new_valid_map(); + } + #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) +diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c +index 37522d6cb398..c9328cc59f52 100644 +--- a/mm/sparse-vmemmap.c ++++ b/mm/sparse-vmemmap.c +@@ -578,6 +578,8 @@ struct page * __meminit __populate_section_memmap(unsigned long pfn, + if (r < 0) + return NULL; + ++ flush_cache_vmap(start, end); ++ + return pfn_to_page(pfn); + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0542-FROMLIST-riscv-mm-Move-dma_contiguous_reserve-after-.patch b/SPECS/linux-lts-kmhv2/0542-FROMLIST-riscv-mm-Move-dma_contiguous_reserve-after-.patch new file mode 100644 index 0000000000..7a0a505a97 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0542-FROMLIST-riscv-mm-Move-dma_contiguous_reserve-after-.patch @@ -0,0 +1,73 @@ +From f895bb784a54d2b918908ac5c9e04f01ae403ed5 Mon Sep 17 00:00:00 2001 +From: Eder Zulian +Date: Tue, 14 Jul 2026 20:56:48 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Move dma_contiguous_reserve() after + NUMA initialization + +Move the dma_contiguous_reserve() call from setup_bootmem() to +misc_mem_init(), placing it after arch_numa_init(). This ensures that +NUMA topology is initialized when reserving contiguous memory for DMA. + +Tested with CMA_SIZE_PERNUMA enabled and two NUMA nodes on QEMU: + +qemu-system-riscv64 \ + -machine virt \ + -nographic \ + -smp 2 -m 512M \ + -numa node,nodeid=0,cpus=0,memdev=m0 \ + -numa node,nodeid=1,cpus=1,memdev=m1 \ + -object memory-backend-ram,id=m0,size=256M \ + -object memory-backend-ram,id=m1,size=256M \ + -kernel arch/riscv/boot/Image \ + -append "console=ttyS0 earlycon loglevel=7 cma=16M" + +Unpatched kernel's log (one global CMA pool and no per-nodepools, 16 MiB +cma-reserved): + + [ 0.000000] cma: Reserved 16 MiB at 0x000000009ee00000 + ... + [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] + [ 0.000000] Initmem setup node 1 [mem 0x0000000090000000-0x000000009fffffff] + ... + [ 0.056397] smp: Brought up 2 nodes, 2 CPUs + [ 0.066135] Memory: 449288K/524288K available (12279K kernel code, 5980K rwdata, 6144K rodata, 2467K init, 482K bss, 54504K reserved, 16384K cma-reserved) + +Patched kernel's log (three CMA pools are created, 48 MiB total), + + [ 0.000000] cma: Reserved 16 MiB at 0x000000009ee00000 + [ 0.000000] cma: Reserved 16 MiB at 0x000000008ee00000 + [ 0.000000] cma: Reserved 16 MiB at 0x000000009de00000 + ... + [ 0.054251] smp: Brought up 2 nodes, 2 CPUs + [ 0.064082] Memory: 416520K/524288K available (12279K kernel code, 5980K rwdata, 6144K rodata, 2467K init, 482K bss, 54504K reserved, 49152K cma-reserved) + +Signed-off-by: Eder Zulian +Link: https://lore.kernel.org/r/20260714185648.1082483-1-ezulian@redhat.com +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 715575f68c69..6b5be15b941c 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -322,7 +322,6 @@ static void __init setup_bootmem(void) + if (!IS_ENABLED(CONFIG_BUILTIN_DTB)) + memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va)); + +- dma_contiguous_reserve(dma32_phys_limit); + if (IS_ENABLED(CONFIG_64BIT)) + hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT); + } +@@ -1472,6 +1471,7 @@ void __init misc_mem_init(void) + { + early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT); + arch_numa_init(); ++ dma_contiguous_reserve(dma32_phys_limit); + sparse_init(); + #ifdef CONFIG_SPARSEMEM_VMEMMAP + /* The entire VMEMMAP region has been populated. Flush TLB for this region */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0543-FROMLIST-dt-bindings-soc-spacemit-k3-add-i2s_sysclk-.patch b/SPECS/linux-lts-kmhv2/0543-FROMLIST-dt-bindings-soc-spacemit-k3-add-i2s_sysclk-.patch new file mode 100644 index 0000000000..bfd5438937 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0543-FROMLIST-dt-bindings-soc-spacemit-k3-add-i2s_sysclk-.patch @@ -0,0 +1,40 @@ +From fd4bdd7000033cfca5f88d4d2c727472ab1fb809 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 17 Jul 2026 00:26:01 -0700 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: add + i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs + +Add three new clock IDs to expose clocks introduced by the topology fix: +- CLK_MPMU_I2S_SYSCLK (51): the common i2s sysclk DDN at MPMU_ISCCR1 +- CLK_MPMU_I2S_BCLK_FACTOR (52): the implicit /2 factor feeding i2s_bclk +- CLK_MPMU_I2S1_SYSCLK_SRC (53): the dedicated i2s1 sysclk source mux + +CLK_MPMU_I2S1_SYSCLK keeps its existing ID (47) but will be repointed to +the real per-instance i2s1 clock in a subsequent patch. No in-tree user +references this ID so the semantic change is contained. + +Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support") +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260717-k3-clk-fix-i2s-v1-1-e95001a692ee@linux.spacemit.com +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index 69978ab0b29f..4f1099f5da1c 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -145,6 +145,9 @@ + #define CLK_MPMU_I2S3_SYSCLK 48 + #define CLK_MPMU_I2S4_SYSCLK 49 + #define CLK_MPMU_I2S5_SYSCLK 50 ++#define CLK_MPMU_I2S_SYSCLK 51 ++#define CLK_MPMU_I2S_BCLK_FACTOR 52 ++#define CLK_MPMU_I2S1_SYSCLK_SRC 53 + + /* APBC clocks */ + #define CLK_APBC_UART0 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0544-FROMLIST-clk-spacemit-k3-fix-i2s-clock-topology.patch b/SPECS/linux-lts-kmhv2/0544-FROMLIST-clk-spacemit-k3-fix-i2s-clock-topology.patch new file mode 100644 index 0000000000..21d74b826a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0544-FROMLIST-clk-spacemit-k3-fix-i2s-clock-topology.patch @@ -0,0 +1,115 @@ +From 65c0b62e10c2a882cc56375fff81db28f94cf8db Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 17 Jul 2026 00:26:02 -0700 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix i2s clock topology + +The K3 i2s clocks were modelled as a single path behind one MPMU +register: + + pll1_d96_25p6 / i2s_153p6_base + `-- i2s_sysclk_src (mux+gate, MPMU_ISCCR) + `-- i2s1_sysclk (DDN, MPMU_ISCCR) + |-- i2s_bclk (div+gate, MPMU_ISCCR) + `-- i2s2_sysclk (mux, parent 0) + +The hardware actually has two i2s clock control registers, ISCCR0 +(0x0040) and ISCCR1 (0x0044): ISCCR1 drives the common sysclk shared +by i2s0/2/3/4/5 and the common bclk, whose divider always implies a +fixed 1/2 factor in front, while ISCCR0 drives a dedicated path for +i2s1: + + pll1_d96_25p6 / i2s_153p6_base + |-- i2s_sysclk_src (mux+gate, MPMU_ISCCR1) + | `-- i2s_sysclk (DDN, MPMU_ISCCR1) + | |-- i2s_bclk_factor (fixed factor, /2) + | | `-- i2s_bclk (div+gate, MPMU_ISCCR1) + | `-- i2s2_sysclk (mux, parent 0) + `-- i2s1_sysclk_src (mux+gate, MPMU_ISCCR0) + `-- i2s1_sysclk (DDN, MPMU_ISCCR0) + +Because of this mismatch, i2s_bclk reported twice the real rate, and +the dedicated i2s1 clock path could not be described in DT at all. + +Model the tree as above: split the MPMU_ISCCR register macro into +MPMU_ISCCR0 and MPMU_ISCCR1 to match the hardware register names, +rename the common DDN to i2s_sysclk, insert the fixed 1/2 factor +i2s_bclk_factor in front of i2s_bclk, and add the i2s1_sysclk_src mux +and i2s1_sysclk DDN backed by MPMU_ISCCR0. CLK_MPMU_I2S1_SYSCLK now +refers to the dedicated i2s1 clock; no in-tree user references this +ID, so nothing is affected by the change of meaning. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260717-k3-clk-fix-i2s-v1-2-e95001a692ee@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 21 ++++++++++++++++----- + include/soc/spacemit/k3-syscon.h | 3 ++- + 2 files changed, 18 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 5d0e31f07d6d..5cb14349358a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -218,11 +218,19 @@ static const struct clk_parent_data i2s_sysclk_src_parents[] = { + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(i2s_153p6_base), + }; +-CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); ++CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR1, 30, 1, BIT(31), 0); + +-CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); ++CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR1, 0, 15, 15, 12, 1, 0); + +-CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0); ++CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1); ++/* ++ * Divider of i2s_bclk always implies a 1/2 factor, which is ++ * described by i2s_bclk_factor. ++ */ ++CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR1, 27, 2, BIT(29), 0); ++ ++CCU_MUX_GATE_DEFINE(i2s1_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR0, 30, 1, BIT(31), 0); ++CCU_DDN_DEFINE(i2s1_sysclk, i2s1_sysclk_src, MPMU_ISCCR0, 0, 15, 15, 12, 1, 0); + + static const struct clk_parent_data i2s_sysclk_parents[] = { + CCU_PARENT_HW(pll1_d4_614p4), +@@ -243,7 +251,7 @@ CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16 + CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); + + static const struct clk_parent_data i2s2_sysclk_parents[] = { +- CCU_PARENT_HW(i2s1_sysclk), ++ CCU_PARENT_HW(i2s_sysclk), + CCU_PARENT_HW(i2s2_sysclk_div), + }; + CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); +@@ -1162,8 +1170,11 @@ static struct clk_hw *k3_ccu_mpmu_hws[] = { + [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, + [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, + [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, +- [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, ++ [CLK_MPMU_I2S_SYSCLK] = &i2s_sysclk.common.hw, ++ [CLK_MPMU_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw, + [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK_SRC] = &i2s1_sysclk_src.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, + [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, + [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, + [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +index a68255dd641f..959d8d0786fe 100644 +--- a/include/soc/spacemit/k3-syscon.h ++++ b/include/soc/spacemit/k3-syscon.h +@@ -45,7 +45,8 @@ + #define POSR_PLL7_LOCK BIT(30) + #define POSR_PLL8_LOCK BIT(31) + #define MPMU_SUCCR 0x0014 +-#define MPMU_ISCCR 0x0044 ++#define MPMU_ISCCR0 0x0040 ++#define MPMU_ISCCR1 0x0044 + #define MPMU_WDTPCR 0x0200 + #define MPMU_RIPCCR 0x0210 + #define MPMU_ACGR 0x1024 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0545-FROMLIST-clk-spacemit-k3-fix-missing-2-factor-in-i2s.patch b/SPECS/linux-lts-kmhv2/0545-FROMLIST-clk-spacemit-k3-fix-missing-2-factor-in-i2s.patch new file mode 100644 index 0000000000..c204c1a71f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0545-FROMLIST-clk-spacemit-k3-fix-missing-2-factor-in-i2s.patch @@ -0,0 +1,46 @@ +From 98f95b9befc76bbe97a77e195f2379b1ff67b242 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 17 Jul 2026 00:26:03 -0700 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix missing /2 factor in + i2s sysclk dividers + +The i2s{0,2,3,4,5}_sysclk_div DDNs have an additional fixed 1/2 +divider in the hardware IP after the configurable divider, so the +real output rate is: + + rate = parent_rate * num / (den * 2) + +Set pre_div to 2 to account for it. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260717-k3-clk-fix-i2s-v1-3-e95001a692ee@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 5cb14349358a..972499084d3a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -244,11 +244,11 @@ CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, + CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); + CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); + +-CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 2, 0); + + static const struct clk_parent_data i2s2_sysclk_parents[] = { + CCU_PARENT_HW(i2s_sysclk), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0546-FROMLIST-riscv-defconfig-enable-RFKILL-and-RFKILL_GP.patch b/SPECS/linux-lts-kmhv2/0546-FROMLIST-riscv-defconfig-enable-RFKILL-and-RFKILL_GP.patch new file mode 100644 index 0000000000..57b9331fbd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0546-FROMLIST-riscv-defconfig-enable-RFKILL-and-RFKILL_GP.patch @@ -0,0 +1,32 @@ +From 4b6155e2dea7292e4daa582ebea5a0a8c24f7e98 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:01 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: defconfig: enable RFKILL and + RFKILL_GPIO + +The SpacemiT K3 Pico-ITX requires RFKILL_GPIO to enable Bluetooth and +WLAN. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-2-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/configs/defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig +index 140c12d4ab15..d68b4ed087f7 100644 +--- a/arch/riscv/configs/defconfig ++++ b/arch/riscv/configs/defconfig +@@ -97,6 +97,8 @@ CONFIG_NET_CLS_CGROUP=m + CONFIG_NETLINK_DIAG=y + CONFIG_CGROUP_NET_PRIO=y + CONFIG_CAN=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_GPIO=m + CONFIG_NET_9P=y + CONFIG_NET_9P_VIRTIO=y + CONFIG_PCI=y +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0547-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-B.patch b/SPECS/linux-lts-kmhv2/0547-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-B.patch new file mode 100644 index 0000000000..4b550bd706 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0547-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-B.patch @@ -0,0 +1,40 @@ +From b6510b4dfc53a0394f8a382a793f34a3d57faa75 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:02 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add rfkill node for + Bluetooth on Pico-ITX board + +On the K3 PICO-ITX board, by default the GPIO pin that connects to the +RTL8852BE Bluetooth enable signal is driven low, resulting in +impossibility to use Bluetooth. Add a DT node to expose it as an RFKILL +device, which lets the Bluetooth driver or userspace toggle it as +required. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-3-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 7327eb65593c..df6b6201ecc2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -43,6 +43,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ rfkill-usb-bt { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-usb-bt"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio 0 30 GPIO_ACTIVE_HIGH>; ++ }; + }; + + &i2c2 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0548-FROMLIST-riscv-dts-spacemit-k3-add-USB3-B-and-C-cont.patch b/SPECS/linux-lts-kmhv2/0548-FROMLIST-riscv-dts-spacemit-k3-add-USB3-B-and-C-cont.patch new file mode 100644 index 0000000000..6f45293fbe --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0548-FROMLIST-riscv-dts-spacemit-k3-add-USB3-B-and-C-cont.patch @@ -0,0 +1,131 @@ +From 9214c50c885eec7cf26576a52e6223328661f38f Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:03 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add USB3 B and C + controllers for Pico-ITX board + +The SpacemiT K3 has 4 USB3 controllers labelled A to D. + +On the K3 Pico-ITX board, the controllers B and C are used in USB 2 mode +only respectively for the M.2 B-Key slot and for the RTL8852BE Bluetooth +controller. + +Add the two controller nodes and the two corresponding USB2 PHY nodes +(the PCIe/USB3 combo PHY driver is not yet merged) and enable them on +the K3 Pico-ITX board. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-4-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 18 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 64 ++++++++++++++++++++ + 2 files changed, 82 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index df6b6201ecc2..e60d57b0891b 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -369,6 +369,24 @@ &usb2_phy { + status = "okay"; + }; + ++&usb3b { ++ maximum-speed = "high-speed"; ++ status = "okay"; ++}; ++ ++&usb3b_u2phy { ++ status = "okay"; ++}; ++ ++&usb3c { ++ maximum-speed = "high-speed"; ++ status = "okay"; ++}; ++ ++&usb3c_u2phy { ++ status = "okay"; ++}; ++ + &usb3d_u2phy { + status = "okay"; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index d7beabc88d86..ab3d71282da0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -634,6 +634,70 @@ pcie4_port: pcie@0 { + }; + }; + ++ usb3b: usb@81400000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81400000 0x0 0x10000>; ++ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_B_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_B_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_B_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3b_u2phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3b_u2phy: phy@81500000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81500000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usb3c: usb@81700000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81700000 0x0 0x10000>; ++ interrupts = <148 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_C_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_C_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_C_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3c_u2phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3c_u2phy: phy@81800000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81800000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0549-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-W.patch b/SPECS/linux-lts-kmhv2/0549-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-W.patch new file mode 100644 index 0000000000..130dac55f1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0549-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-W.patch @@ -0,0 +1,39 @@ +From 67d1a5fa2166dfbf9e09392ded5bfdc1e0dad09d Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:04 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add rfkill node for + WLAN on Pico-ITX board + +By default the GPIO pin that connects to the RTL8852BE WLAN enable +signal is driven low, resulting in impossibility to connect to any +network. Add a DT node to expose it as an RFKILL device, which lets the +WiFi driver or userspace toggle it as required. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-5-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index e60d57b0891b..9dd60d1acb34 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -44,6 +44,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-always-on; + }; + ++ rfkill-pcie-wlan { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-pcie-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio 1 3 GPIO_ACTIVE_HIGH>; ++ }; ++ + rfkill-usb-bt { + compatible = "rfkill-gpio"; + label = "rfkill-usb-bt"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0550-FROMLIST-riscv-require-vmemmap-for-NUMA-balancing.patch b/SPECS/linux-lts-kmhv2/0550-FROMLIST-riscv-require-vmemmap-for-NUMA-balancing.patch new file mode 100644 index 0000000000..370297dff6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0550-FROMLIST-riscv-require-vmemmap-for-NUMA-balancing.patch @@ -0,0 +1,46 @@ +From 9cc01243978429e6a17c49ccfeaa9840edf79858 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 16 Jul 2026 14:47:10 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: require vmemmap for NUMA balancing + +RISC-V randconfig can enable NUMA balancing while selecting +SPARSEMEM_EXTREME without SPARSEMEM_VMEMMAP. In that layout, the +section and node fields can consume enough page flag bits that +LAST_CPUPID cannot fit in page->flags. + +The generic MM code then stores last_cpupid in struct page and emits +the "Unfortunate NUMA and NUMA Balancing config" warning from +mm/memory.c. + +NUMA balancing needs LAST_CPUPID storage, but this fallback grows +struct page for a configuration that randconfig can select +accidentally. Keep NUMA support available, but advertise RISC-V NUMA +balancing support only when SPARSEMEM_VMEMMAP is enabled, where the +page flag layout leaves room for LAST_CPUPID. + +This was originally seen with a RISC-V randconfig generated from +KCONFIG_SEED=550012. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260716-numa_kconfig-v1-1-b0cd6d29accb@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index afdd6f6a05f6..8832a62b356d 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -486,7 +486,7 @@ endchoice + config NUMA + bool "NUMA Memory Allocation and Scheduler Support" + depends on SMP && MMU +- select ARCH_SUPPORTS_NUMA_BALANCING ++ select ARCH_SUPPORTS_NUMA_BALANCING if SPARSEMEM_VMEMMAP + select GENERIC_ARCH_NUMA + select HAVE_SETUP_PER_CPU_AREA + select NEED_PER_CPU_EMBED_FIRST_CHUNK +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0551-FROMLIST-riscv-time-Add-missing-__iomem-in-get_cycle.patch b/SPECS/linux-lts-kmhv2/0551-FROMLIST-riscv-time-Add-missing-__iomem-in-get_cycle.patch new file mode 100644 index 0000000000..3b18eef6c5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0551-FROMLIST-riscv-time-Add-missing-__iomem-in-get_cycle.patch @@ -0,0 +1,43 @@ +From 23a2e3ab76e9a1c0adc1d4d69cb0d5c722ac491d Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Thu, 16 Jul 2026 07:33:19 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: time: Add missing __iomem in + get_cycles() and get_cycles_hi() + +__iomem is missing while calling readl_relaxed() in get_cycles() and +get_cycles_hi() and sparse complains. + +Add __iomem to silence the sparse warnings. + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202607160619.14G8GHp5-lkp@intel.com/ +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/20260716053319.2178937-1-namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/timex.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h +index a06697846e69..d41acfb3959d 100644 +--- a/arch/riscv/include/asm/timex.h ++++ b/arch/riscv/include/asm/timex.h +@@ -22,13 +22,13 @@ static inline cycles_t get_cycles(void) + #else /* !CONFIG_64BIT */ + static inline u32 get_cycles(void) + { +- return readl_relaxed(((u32 *)clint_time_val)); ++ return readl_relaxed(((u32 __iomem *)clint_time_val)); + } + #define get_cycles get_cycles + + static inline u32 get_cycles_hi(void) + { +- return readl_relaxed(((u32 *)clint_time_val) + 1); ++ return readl_relaxed(((u32 __iomem *)clint_time_val) + 1); + } + #define get_cycles_hi get_cycles_hi + #endif /* CONFIG_64BIT */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0552-FROMLIST-PCI-Move-Spacemit-vendor-and-device-IDs-to-.patch b/SPECS/linux-lts-kmhv2/0552-FROMLIST-PCI-Move-Spacemit-vendor-and-device-IDs-to-.patch new file mode 100644 index 0000000000..e50431db47 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0552-FROMLIST-PCI-Move-Spacemit-vendor-and-device-IDs-to-.patch @@ -0,0 +1,54 @@ +From 64b66eb1e39719aab650752801d8e9f97f010c9a Mon Sep 17 00:00:00 2001 +From: Anirudh Srinivasan +Date: Thu, 16 Jul 2026 18:05:10 -0500 +Subject: [RUYI PATCH] FROMLIST: PCI: Move Spacemit vendor and device IDs to + linux/pci_ids.h + +Move the vendor and device ID for the existing Spacemit K1 PCIe Root +Complex to include/linux/pci_ids.h. Also add K3's Root Complex device ID +to this header. This is done so that these values can be referenced in +the rtw89 driver to enable 36-bit DMA ability in it for WiFi to function +on the K3 Pico ITX board. + +Acked-by: Bjorn Helgaas +Signed-off-by: Anirudh Srinivasan +Link: https://lore.kernel.org/r/20260716-rtw89-spacemit-k3-v2-1-392b577ebf75@oss.tenstorrent.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 4 ---- + include/linux/pci_ids.h | 4 ++++ + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 7502d66bd0d0..bf2ab5cb59ce 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -21,10 +21,6 @@ + + #include "pcie-designware.h" + +-#define PCI_VENDOR_ID_SPACEMIT 0x201f +-#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 +-#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 +- + /* Offsets and field definitions for link management registers */ + #define K1_PHY_AHB_IRQ_EN 0x0000 + #define PCIE_INTERRUPT_EN BIT(0) +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 7c01548a6ddb..26ac13010cb5 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2643,6 +2643,10 @@ + #define PCI_VENDOR_ID_SUNIX 0x1fd4 + #define PCI_DEVICE_ID_SUNIX_1999 0x1999 + ++#define PCI_VENDOR_ID_SPACEMIT 0x201f ++#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 ++ + #define PCI_VENDOR_ID_HINT 0x3388 + #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0553-FROMLIST-wifi-rtw89-pci-enable-36-bit-DMA-on-spacemi.patch b/SPECS/linux-lts-kmhv2/0553-FROMLIST-wifi-rtw89-pci-enable-36-bit-DMA-on-spacemi.patch new file mode 100644 index 0000000000..d52003d2e0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0553-FROMLIST-wifi-rtw89-pci-enable-36-bit-DMA-on-spacemi.patch @@ -0,0 +1,39 @@ +From d3fadb381f8e426840c03b032c474eb1535c31f5 Mon Sep 17 00:00:00 2001 +From: Anirudh Srinivasan +Date: Thu, 16 Jul 2026 18:05:11 -0500 +Subject: [RUYI PATCH] FROMLIST: wifi: rtw89: pci: enable 36-bit DMA on + spacemit K3 + +The Spacemit K3 Pico ITX Board has a RTL8852BE pcie card behind a PCIe +root port, but the SoC doesn't have any 32 bit DMA addreseses which the +rtw89 seems to use by default. Enable 36 bit DMA ability that the driver +has when this particular root port is detected so that the driver can +probe on this SoC. + +Tested-by: Aurelien Jarno +Acked-by: Ping-Ke Shih +Signed-off-by: Anirudh Srinivasan +Link: https://lore.kernel.org/r/20260716-rtw89-spacemit-k3-v2-2-392b577ebf75@oss.tenstorrent.com +Signed-off-by: Han Gao +--- + drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +index 6be1849b0c4d..5058ebadb604 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.c ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) + if (bridge->device == 0x2806) + return true; + break; ++ case PCI_VENDOR_ID_SPACEMIT: ++ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) ++ return true; ++ break; + } + + return false; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0554-FROMLIST-riscv-cmpxchg-Use-.option-arch-for-Zacas-an.patch b/SPECS/linux-lts-kmhv2/0554-FROMLIST-riscv-cmpxchg-Use-.option-arch-for-Zacas-an.patch new file mode 100644 index 0000000000..0f5c5a9158 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0554-FROMLIST-riscv-cmpxchg-Use-.option-arch-for-Zacas-an.patch @@ -0,0 +1,97 @@ +From 5cb1625f1dd1575c52963517c166d900063ac6fa Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 17 Jul 2026 20:40:06 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: cmpxchg: Use .option arch for Zacas and + Zabha + +Instead of adding these to -march globally, use .option arch to use +instructions from these extensions only in code paths where we know they +are available, like how it is done for most other extensions. +TOOLCHAIN_HAS_{ZACAS,ZABHA} already depend on AS_HAS_OPTION_ARCH, so +this is not a functionality regression even on older assemblers. + +Although the compiler is unlikely to generate atomics on its own accord, +this aligns handling of Zacas and Zabha with most other extensions and +improves consistency on how assembly code requiring extra extensions is +written in kernel code. + +This is analogous to the use of __LSE_PREAMBLE or .arch_extension lse in +arm64 code. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260717-riscv-no-zacas-zabha-in-march-v1-1-82b5b0799fb6@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 6 ------ + arch/riscv/include/asm/cmpxchg.h | 14 +++++++++++++- + 2 files changed, 13 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 1256e91714ef..478451141341 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -83,12 +83,6 @@ else + riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei + endif + +-# Check if the toolchain supports Zacas +-riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas +- +-# Check if the toolchain supports Zabha +-riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha +- + # Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by + # matching non-v and non-multi-letter extensions out with the filter ([^v_]*) + KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/') +diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h +index 122e1485d39a..e68263343403 100644 +--- a/arch/riscv/include/asm/cmpxchg.h ++++ b/arch/riscv/include/asm/cmpxchg.h +@@ -23,7 +23,10 @@ + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + __asm__ __volatile__ ( \ + prepend \ ++ " .option push\n" \ ++ " .option arch, +zabha\n" \ + " amoswap" swap_sfx " %0, %z2, %1\n" \ ++ " .option pop\n" \ + swap_append \ + : "=&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ +@@ -141,7 +144,10 @@ + \ + __asm__ __volatile__ ( \ + cas_prepend \ ++ " .option push\n" \ ++ " .option arch, +zacas, +zabha\n" \ + " amocas" cas_sfx " %0, %z2, %1\n" \ ++ " .option pop\n" \ + cas_append \ + : "+&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ +@@ -188,7 +194,10 @@ + \ + __asm__ __volatile__ ( \ + cas_prepend \ ++ " .option push\n" \ ++ " .option arch, +zacas\n" \ + " amocas" cas_sfx " %0, %z2, %1\n" \ ++ " .option pop\n" \ + cas_append \ + : "+&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ +@@ -340,7 +349,10 @@ union __u128_halves { + register unsigned long t4 asm ("t4") = __ho.high; \ + \ + __asm__ __volatile__ ( \ +- " amocas.q" cas_sfx " %0, %z3, %2" \ ++ " .option push\n" \ ++ " .option arch, +zacas\n" \ ++ " amocas.q" cas_sfx " %0, %z3, %2\n" \ ++ " .option pop\n" \ + : "+&r" (t3), "+&r" (t4), "+A" (*(p)) \ + : "rJ" (t1), "rJ" (t2) \ + : "memory"); \ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0555-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts-kmhv2/0555-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch new file mode 100644 index 0000000000..9919124010 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0555-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch @@ -0,0 +1,49 @@ +From ac7aa3430e8c8a4228ddd613179ea61f723a9574 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 24 Nov 2025 20:38:44 +0800 +Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support + +From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/Makefile | 1 + + .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ + 2 files changed, 19 insertions(+) + create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts + +diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile +index b55a17127c2b..281849e71ccb 100644 +--- a/arch/riscv/boot/dts/thead/Makefile ++++ b/arch/riscv/boot/dts/thead/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb ++dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +new file mode 100644 +index 000000000000..a3a991baf716 +--- /dev/null ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Han Gao ++ */ ++ ++/dts-v1/; ++ ++#include "th1520-lichee-pi-4a.dts" ++ ++/ { ++ model = "Sipeed Lichee Pi 4A 16G"; ++ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x00000000 0x4 0x00000000>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0556-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts-kmhv2/0556-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch new file mode 100644 index 0000000000..3fa38cb786 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0556-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch @@ -0,0 +1,28 @@ +From 057f072a9105eb987d4152d0c9488cc3495eaf18 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:16:15 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie + +Signed-off-by: Han Gao +[Icenowy: preserve the original compatible to allow Linux to match] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index aa757ddd6046..108205d5d4a6 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { + }; + + aon: aon { +- compatible = "thead,th1520-aon"; ++ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0557-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts-kmhv2/0557-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch new file mode 100644 index 0000000000..437e7fe52e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0557-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch @@ -0,0 +1,44 @@ +From af4d8f5cb53889a1c1486fef77dc3d7e6ebcbd4a Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:27:18 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r + +Signed-off-by: Han Gao +[Icenowy: remove the interrupt-controller property] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 108205d5d4a6..fdef5fb82b45 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -292,6 +292,24 @@ aon: aon { + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; + #power-domain-cells = <1>; ++ opensbi-mboxes = <&mbox_910r>; ++ status = "okay"; ++ }; ++ ++ mbox_910r: mbox@ffefc53000 { ++ compatible = "xuantie,th1520-mbox-r"; ++ reg = <0xff 0xefc53000 0x0 0x4000>, ++ <0xff 0xefc3f000 0x0 0x1000>, ++ <0xff 0xefc47000 0x0 0x1000>, ++ <0xff 0xefc4f000 0x0 0x1000>; ++ reg-names = "local_base", ++ "remote_icu0", ++ "remote_icu1", ++ "remote_icu2"; ++ clocks = <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ipg"; ++ icu_cpu_id = <3>; ++ #mbox-cells = <2>; + }; + + soc { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0558-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts-kmhv2/0558-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch new file mode 100644 index 0000000000..866a2cfc89 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0558-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch @@ -0,0 +1,84 @@ +From e2eb8f9600dd3a09b456111bd9cb4f7ed4c60d45 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:31 +0800 +Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller + +Sophgo SG2044 uses eFuses used to store factory-programmed data +such as ROM patch, public keys and other factory information. + +Signed-off-by: Inochi Amaoto +--- + .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml + +diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +new file mode 100644 +index 000000000000..d4bffe2724ac +--- /dev/null ++++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sophgo SoC eFuse-based NVMEM ++ ++description: ++ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, ++ public key and other factory information. ++ ++maintainers: ++ - Inochi Amaoto ++ ++allOf: ++ - $ref: nvmem.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - sophgo,sg2044-efuse ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ items: ++ - description: Core clock ++ - description: APB clock ++ ++ clock-names: ++ minItems: 1 ++ items: ++ - const: core ++ - const: apb ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ efuse@40000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x40000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk 0>, ++ <&clk 1>; ++ clock-names = "core", "apb"; ++ }; ++ ++... +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0559-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts-kmhv2/0559-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch new file mode 100644 index 0000000000..47c78a2e2a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0559-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch @@ -0,0 +1,241 @@ +From 3482c1d615fc8998a6fab569b8d8c1dc63c2dba0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:32 +0800 +Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver + +Sophgo SoCs such as SG2044 contain eFuses used to store +factory-programmed data. + +As for SG2044, HW automatically loads the eFuse content +into shadow registers which are organized as 32bit values +exposed as MMIO. + +Signed-off-by: Inochi Amaoto +--- + drivers/nvmem/Kconfig | 12 +++ + drivers/nvmem/Makefile | 2 + + drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 drivers/nvmem/sophgo-efuse.c + +diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig +index 11b098705ec6..42f46eb0462a 100644 +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR + This driver can also be built as a module. If so, the module + will be called nvmem-snvs-lpgpr. + ++config NVMEM_SOPHGO_EFUSE ++ tristate "Sophgo eFuse support" ++ depends on ARCH_SOPHGO || COMPILE_TEST ++ default ARCH_SOPHGO ++ help ++ Say y here to enable support for reading eFuses on Sophgo SoCs ++ such as the CV1800B. These are e.g. used to store factory programmed ++ calibration data required for the builtin ethernet PHY. ++ ++ This driver can also be built as a module. If so, the module will ++ be called nvmem-sophgo-efuse. ++ + config NVMEM_SPMI_SDAM + tristate "SPMI SDAM Support" + depends on SPMI +diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile +index 70a4464dcb1e..6cc324aaa757 100644 +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o + nvmem-sc27xx-efuse-y := sc27xx-efuse.o + obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o + nvmem_snvs_lpgpr-y := snvs_lpgpr.o ++obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o ++nvmem-sophgo-efuse-y := sophgo-efuse.o + obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o + nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o + obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o +diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c +new file mode 100644 +index 000000000000..5f90adaf8e4f +--- /dev/null ++++ b/drivers/nvmem/sophgo-efuse.c +@@ -0,0 +1,176 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Sophgo SoC eFuse driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SG2044_EFUSE_CONTENT_SIZE 0x400 ++ ++#define SG2044_EFUSE_MD 0x000 ++#define SG2044_EFUSE_ADR 0x004 ++#define SG2044_EFUSE_RD_DATA 0x00c ++ ++#define SG2044_EFUSE_MODE GENMASK(1, 0) ++#define SG2044_EFUSE_MODE_READ 2 ++ ++#define SG2044_EFUSE_BOOT_DONE BIT(7) ++#define SG2044_BOOT_TIMEOUT 10000 ++ ++#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) ++ ++#define SG2044_EFUSE_ALIGN 4 ++ ++struct sophgo_efuses { ++ void __iomem *base; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct mutex mutex; ++}; ++ ++static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) ++{ ++ u32 value; ++ ++ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, ++ 1, SG2044_BOOT_TIMEOUT); ++} ++ ++static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) ++{ ++ u32 val = readl(efuse->base + SG2044_EFUSE_MD); ++ ++ val &= ~SG2044_EFUSE_MODE; ++ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); ++ ++ writel(val, efuse->base + SG2044_EFUSE_MD); ++ ++ return sg2044_efuse_wait_mode(efuse); ++} ++ ++static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, ++ unsigned int offset, u32 *strip) ++{ ++ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); ++ int ret; ++ ++ guard(mutex)(&efuse->mutex); ++ ++ writel(val, efuse->base + SG2044_EFUSE_ADR); ++ ++ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); ++ if (ret < 0) ++ return ret; ++ ++ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); ++ ++ return 0; ++} ++ ++static int sg2044_efuses_read(void *context, unsigned int offset, void *val, ++ size_t bytes) ++{ ++ struct sophgo_efuses *efuse = context; ++ unsigned int start, start_offset, end, i; ++ u32 value; ++ u8 *buf; ++ int ret; ++ ++ start = rounddown(offset, SG2044_EFUSE_ALIGN); ++ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); ++ start_offset = offset - start; ++ ++ start /= SG2044_EFUSE_ALIGN; ++ end /= SG2044_EFUSE_ALIGN; ++ ++ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ (value & SG2044_EFUSE_BOOT_DONE), ++ 1, SG2044_BOOT_TIMEOUT); ++ if (ret < 0) ++ return ret; ++ ++ buf = kzalloc(end - start, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (i = start; i < end; i++) { ++ ret = sg2044_efuses_read_strip(efuse, i, &value); ++ if (ret) ++ goto failed; ++ ++ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); ++ } ++ ++ memcpy(val, buf + start_offset, bytes); ++ ++failed: ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int sophgo_efuses_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct sophgo_efuses *efuse; ++ struct nvmem_config config = { ++ .dev = &pdev->dev, ++ .add_legacy_fixed_of_cells = true, ++ .read_only = true, ++ .reg_read = sg2044_efuses_read, ++ .stride = 1, ++ .word_size = 1, ++ .name = "sophgo-efuse", ++ .id = NVMEM_DEVID_AUTO, ++ .root_only = true, ++ }; ++ ++ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); ++ if (!efuse) ++ return -ENOMEM; ++ ++ efuse->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(efuse->base)) ++ return PTR_ERR(efuse->base); ++ ++ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); ++ if (efuse->num_clks < 0) ++ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); ++ ++ config.priv = efuse; ++ config.size = SG2044_EFUSE_CONTENT_SIZE; ++ ++ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); ++} ++ ++static const struct of_device_id sophgo_efuses_of_match[] = { ++ { .compatible = "sophgo,sg2044-efuse", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); ++ ++static struct platform_driver sophgo_efuses_driver = { ++ .driver = { ++ .name = "sophgo_efuse", ++ .of_match_table = sophgo_efuses_of_match, ++ }, ++ .probe = sophgo_efuses_probe, ++}; ++ ++module_platform_driver(sophgo_efuses_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Sophgo efuse driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0560-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts-kmhv2/0560-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch new file mode 100644 index 0000000000..a57f9e3a3e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0560-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch @@ -0,0 +1,54 @@ +From e2679ad091eadd0d4c8e4e8bf0bbf36257b98c1c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 5 Dec 2024 13:24:13 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device + +Add eFUSE controller node for SG2044. + +Signed-off-by: Inochi Amaoto +--- + arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index fed3d9a384a0..1b506972d465 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -36,6 +36,10 @@ &emmc { + status = "okay"; + }; + ++&efuse0 { ++ status = "okay"; ++}; ++ + &gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 320c4d1d08e6..9577aae08f7f 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -408,6 +408,18 @@ sd: mmc@703000b000 { + status = "disabled"; + }; + ++ efuse0: efuse@7040000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x70 0x40000000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk CLK_GATE_EFUSE>, ++ <&clk CLK_GATE_APB_EFUSE>; ++ clock-names = "core", "apb"; ++ resets = <&rst RST_EFUSE0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@7040005000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40005000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0561-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts-kmhv2/0561-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch new file mode 100644 index 0000000000..246eb06539 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0561-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch @@ -0,0 +1,30 @@ +From 9bdc31cdfcf7352a39af835175692dad1e9875e3 Mon Sep 17 00:00:00 2001 +From: Xiaoguang Xing +Date: Mon, 22 Jan 2024 10:31:30 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean + with flush + +FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 + +Signed-off-by: Xiaoguang Xing +Signed-off-by: Han Gao +--- + arch/riscv/errata/thead/errata.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index fbe46f2fa8fb..9be8c45f4531 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, + * 0000000 11001 00000 000 00000 0001011 + */ + #define THEAD_INVAL_A0 ".long 0x02a5000b" +-#define THEAD_CLEAN_A0 ".long 0x0295000b" ++#define THEAD_CLEAN_A0 ".long 0x02b5000b" + #define THEAD_FLUSH_A0 ".long 0x02b5000b" + #define THEAD_SYNC_S ".long 0x0190000b" + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0562-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts-kmhv2/0562-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch new file mode 100644 index 0000000000..bf61df6a36 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0562-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch @@ -0,0 +1,102 @@ +From 6bf71169183a4dec0533a946b56929ef4c3eaf20 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 28 Dec 2025 23:02:15 +0800 +Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address + +FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 9577aae08f7f..f1377ee8e149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00000000 0x0 0x00001000>, + <0x6c 0x00300000 0x0 0x00004000>, +- <0x48 0x00000000 0x0 0x00001000>, ++ <0x50 0x00000000 0x0 0x00001000>, + <0x6c 0x000c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, + <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc0: interrupt-controller { +@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { + ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc1: interrupt-controller { +@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04000000 0x0 0x00001000>, + <0x6c 0x04300000 0x0 0x00004000>, +- <0x58 0x00000000 0x0 0x00001000>, ++ <0x7c 0x00000000 0x0 0x00001000>, + <0x6c 0x040c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, + <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, +- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc2: interrupt-controller { +@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04400000 0x0 0x00001000>, + <0x6c 0x04700000 0x0 0x00004000>, +- <0x50 0x00000000 0x0 0x00001000>, ++ <0x78 0x00000000 0x0 0x00001000>, + <0x6c 0x04780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, + <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, +- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, +- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc3: interrupt-controller { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0563-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts-kmhv2/0563-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch new file mode 100644 index 0000000000..ca3265badb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0563-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch @@ -0,0 +1,145 @@ +From 412ab5bced3838d09062ee243fa024c8075a6999 Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Mon, 5 Jan 2026 20:05:04 +0800 +Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is + not cacheable + +FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f + +Change-Id: I040d597ee246777767f7be747fa9202154524538 +[ Vivian: Rebase and move check into enter_vector_usercopy ] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/uaccess.h | 5 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/riscv_v_helpers.c | 5 +++ + arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ + 4 files changed, 76 insertions(+) + create mode 100644 arch/riscv/lib/uaccess_cache_check.c + +diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h +index 6aef591a6bfc..b028208b05ec 100644 +--- a/arch/riscv/include/asm/uaccess.h ++++ b/arch/riscv/include/asm/uaccess.h +@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } + if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ + goto label; + ++/* Memory cacheability check for vector uaccess optimization */ ++#ifdef CONFIG_RISCV_ISA_V ++int is_cacheable_safe(const void *addr); ++#endif ++ + #else /* CONFIG_MMU */ + #include + #endif /* CONFIG_MMU */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 735d0b665536..43fe69db9803 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -14,6 +14,7 @@ endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) + lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o ++lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o + endif + lib-$(CONFIG_MMU) += uaccess.o + lib-$(CONFIG_64BIT) += tishift.o +diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c +index 7bbdfc6d4552..7ab2cea280f8 100644 +--- a/arch/riscv/lib/riscv_v_helpers.c ++++ b/arch/riscv/lib/riscv_v_helpers.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + + #ifdef CONFIG_MMU + #include +@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, + if (!may_use_simd()) + goto fallback; + ++ /* HACK */ ++ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) ++ goto fallback; ++ + kernel_vector_begin(); + remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : + __asm_vector_usercopy_sum_enabled(dst, src, n); +diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c +new file mode 100644 +index 000000000000..0b0996fa2d37 +--- /dev/null ++++ b/arch/riscv/lib/uaccess_cache_check.c +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Memory cacheability check for RISC-V uaccess optimization ++ * ++ * This file provides a C function that can be called from assembly ++ * to determine if a buffer is cacheable before using vector instructions. ++ */ ++ ++#include ++#include ++#include ++ ++/** ++ * is_cacheable_safe - Check if memory buffer is cacheable ++ * @addr: Virtual address to check (kernel or user space) ++ * ++ * Returns: 1 if cacheable, 0 if non-cacheable ++ * ++ * This function is designed to be called from assembly code in uaccess.S ++ * to determine if vector instructions are safe to use for memory copy. ++ * ++ * Non-cacheable memory (device IO, DMA coherent buffers) should not use ++ * vector instructions as they may cause cache coherency issues. ++ * ++ * Handles both kernel and user space addresses safely: ++ * - Kernel direct mapping: Always cacheable ++ * - Kernel vmalloc: Check VM flags ++ * - User space: Check page table (most are cacheable) ++ * - ioremap/DMA: Non-cacheable ++ */ ++int is_cacheable_safe(const void *addr) ++{ ++ unsigned long vaddr = (unsigned long)addr; ++ ++ /* Kernel direct mapped memory - always cacheable */ ++ if (virt_addr_valid(addr)) ++ return 1; ++ ++ if (vaddr < TASK_SIZE) { ++ /* ++ * User space address, Determine it as a cacheable buffer, ++ * maybe not safe!! ++ */ ++ return 1; ++ } ++ ++ /* Check if it's a vmalloc region (kernel virtual address) */ ++ if (is_vmalloc_addr(addr)) { ++ struct vm_struct *vm; ++ ++ vm = find_vm_area(addr); ++ if (!vm) ++ return 0; ++ ++ /* Exclude ioremap and DMA coherent buffers */ ++ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) ++ return 0; ++ ++ /* Normal vmalloc - cacheable */ ++ return 1; ++ } ++ ++ /* Unknown kernel region - assume non-cacheable for safety */ ++ return 0; ++} +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0564-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts-kmhv2/0564-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch new file mode 100644 index 0000000000..af2c7896d5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0564-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch @@ -0,0 +1,57 @@ +From 8e003247f1ea7a299ee88d58637eb93a70aff1b5 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 19 May 2026 19:57:52 +0800 +Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on + SpacemiT K3 + +The dynamic speed switch functionality seems to be broken on SpacemiT +K3, and leads to frequent GPU crashes at least with Polaris GPUs. + +Disable dynamic speed switch on this platform. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index c22aea46efcd..b54f7cdd0ce8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) + */ + static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) + { ++ struct pci_dev *parent = adev->pdev; ++ static const struct pci_device_id broken_devids[] = { ++ /* SpacemiT K3 */ ++ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, ++ PCI_DEVICE_ID_SPACEMIT_K3) }, ++ {} ++ }; ++ + #if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); + +@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device + if (c->x86_vendor == X86_VENDOR_INTEL) + return false; + #endif ++ /* skip upstream/downstream switches internal to dGPU */ ++ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { ++ parent = pci_upstream_bridge(parent); ++ } ++ ++ if (!parent) ++ return true; ++ ++ if (pci_match_id(broken_devids, parent)) ++ return false; ++ + return true; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0565-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts-kmhv2/0565-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch new file mode 100644 index 0000000000..9e11504188 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0565-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch @@ -0,0 +1,65 @@ +From f443eaed7912e8a966fc81edd153f42d28cd0043 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 28 May 2026 14:18:23 +0800 +Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA + variant + +Add support for a testing variant of the SG2042 SDHCI controller without +PHY reset and without the "timer" clock. + +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 90aa146a1be3..292940d9c45b 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1664,6 +1664,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { ++ .set_clock = sdhci_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = dwcmshc_set_uhs_signaling, ++ .get_max_clock = dwcmshc_get_max_clock, ++ .reset = sdhci_reset, ++ .adma_write_desc = dwcmshc_adma_write_desc, ++ .platform_execute_tuning = th1520_execute_tuning, ++}; ++ + static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_clock = sdhci_eic7700_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, +@@ -1746,6 +1756,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++ }, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_eic7700_ops, +@@ -1857,6 +1875,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "sophgo,sg2042-fpga-dwcmshc", ++ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, ++ }, + { + .compatible = "eswin,eic7700-dwcmshc", + .data = &sdhci_dwcmshc_eic7700_pdata, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0566-RUYI-riscv-dts-sophgo-sg2044-srd3-add-spifmc-node.patch b/SPECS/linux-lts-kmhv2/0566-RUYI-riscv-dts-sophgo-sg2044-srd3-add-spifmc-node.patch new file mode 100644 index 0000000000..00a52c24cf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0566-RUYI-riscv-dts-sophgo-sg2044-srd3-add-spifmc-node.patch @@ -0,0 +1,49 @@ +From d82d17cf8643eba9acc05af4e18863a62db99ef8 Mon Sep 17 00:00:00 2001 +From: Hangfan Li +Date: Fri, 3 Jul 2026 17:29:21 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: sophgo: sg2044: srd3: add spifmc node + +Signed-off-by: Hangfan Li +Signed-off-by: Han Gao +--- + .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index 1b506972d465..6003d92c50a7 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -113,6 +113,30 @@ &sd { + status = "okay"; + }; + ++&spifmc0 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <133000000>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++}; ++ ++&spifmc1 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <133000000>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++}; ++ + &uart0 { + /* for firmware */ + status = "reserved"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0567-RUYI-HACK-riscv-entry-nmi_exit-before-die.patch b/SPECS/linux-lts-kmhv2/0567-RUYI-HACK-riscv-entry-nmi_exit-before-die.patch new file mode 100644 index 0000000000..0575ade162 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0567-RUYI-HACK-riscv-entry-nmi_exit-before-die.patch @@ -0,0 +1,45 @@ +From 0cbaf29b9b337231c6c786852d96d9ecc6d9038d Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 7 Jul 2026 09:35:50 +0800 +Subject: [RUYI PATCH] RUYI: HACK: riscv: entry: nmi_exit() before die() + +Breakpoint exceptions are handled in_nmi() since they could be kernel +breakpoints. As such, nmi_exit() before die() to give the kernel a +chance to recover instead of having make_task_dead() generate a +full-machine panic. + +This is similar to how some exceptions are handled in powerpc. + +This is a bit of a hack. A better solution was being discussed [1] but +no concrete conclusion has been arrived to yet. + +Link: https://lore.kernel.org/linux-riscv/20230702025708.784106-1-guoren@kernel.org/ # [1] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/kernel/traps.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c +index 47afea4ff1a8..65172f072f37 100644 +--- a/arch/riscv/kernel/traps.c ++++ b/arch/riscv/kernel/traps.c +@@ -298,10 +298,13 @@ void handle_break(struct pt_regs *regs) + return; + #endif + else if (report_bug(regs->epc, regs) == BUG_TRAP_TYPE_WARN || +- handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) ++ handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) { + regs->epc += get_break_insn_length(regs->epc); +- else ++ } else { ++ /* Avoid a panic, since we're in_nmi(). */ ++ nmi_exit(); + die(regs, "Kernel BUG"); ++ } + } + + asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0568-XIANGSHAN-Flush-all-tlb-in-set_pte.patch b/SPECS/linux-lts-kmhv2/0568-XIANGSHAN-Flush-all-tlb-in-set_pte.patch new file mode 100644 index 0000000000..0adbffbd63 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0568-XIANGSHAN-Flush-all-tlb-in-set_pte.patch @@ -0,0 +1,26 @@ +From 628eb4e072204d685f4745b679b15ca7b9c548df Mon Sep 17 00:00:00 2001 +From: Ran Wang +Date: Fri, 20 Mar 2026 15:31:20 +0800 +Subject: [RUYI PATCH] XIANGSHAN: Flush all tlb in set_pte() + +Signed-off-by: Ran Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/pgtable.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 9b2e967c9fe0..efd7617da903 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -550,6 +550,7 @@ static inline int pte_same(pte_t pte_a, pte_t pte_b) + static inline void set_pte(pte_t *ptep, pte_t pteval) + { + WRITE_ONCE(*ptep, pteval); ++ __asm__ __volatile__ ("sfence.vma" : : : "memory"); + } + + void flush_icache_pte(struct mm_struct *mm, pte_t pte); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0569-XIANGSHAN-Add-two-sbi-calls.patch b/SPECS/linux-lts-kmhv2/0569-XIANGSHAN-Add-two-sbi-calls.patch new file mode 100644 index 0000000000..9f4556319e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0569-XIANGSHAN-Add-two-sbi-calls.patch @@ -0,0 +1,60 @@ +From 2974d9bf0efbcdcd79b71fa3781594fbc516dee7 Mon Sep 17 00:00:00 2001 +From: Ran Wang +Date: Fri, 20 Mar 2026 15:36:58 +0800 +Subject: [RUYI PATCH] XIANGSHAN: Add two sbi calls + +Signed-off-by: Ran Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/sbi.h | 4 ++++ + arch/riscv/kernel/sbi.c | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h +index ccc77a89b1e2..189956420b4c 100644 +--- a/arch/riscv/include/asm/sbi.h ++++ b/arch/riscv/include/asm/sbi.h +@@ -55,6 +55,8 @@ enum sbi_ext_base_fid { + SBI_EXT_BASE_GET_MVENDORID, + SBI_EXT_BASE_GET_MARCHID, + SBI_EXT_BASE_GET_MIMPID, ++ SBI_EXT_BASE_GET_MHARTID, ++ SBI_EXT_BASE_FLUSH_L2CACHE, + }; + + enum sbi_ext_time_fid { +@@ -664,6 +666,8 @@ unsigned long riscv_get_marchid(void); + unsigned long riscv_cached_mvendorid(unsigned int cpu_id); + unsigned long riscv_cached_marchid(unsigned int cpu_id); + unsigned long riscv_cached_mimpid(unsigned int cpu_id); ++long sbi_get_mhartid(void); ++long sbi_flush_l2cache(void); + + #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) + DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence); +diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c +index c443337056ab..05c27dd1e397 100644 +--- a/arch/riscv/kernel/sbi.c ++++ b/arch/riscv/kernel/sbi.c +@@ -646,6 +646,18 @@ int sbi_debug_console_read(char *bytes, unsigned int num_bytes) + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; + } + ++long sbi_get_mhartid(void) ++{ ++ return __sbi_base_ecall(SBI_EXT_BASE_GET_MHARTID); ++} ++EXPORT_SYMBOL(sbi_get_mhartid); ++ ++long sbi_flush_l2cache(void) ++{ ++ return __sbi_base_ecall(SBI_EXT_BASE_FLUSH_L2CACHE); ++} ++EXPORT_SYMBOL(sbi_flush_l2cache); ++ + void __init sbi_init(void) + { + bool srst_power_off = false; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0570-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch b/SPECS/linux-lts-kmhv2/0570-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch new file mode 100644 index 0000000000..4e9e55c1a6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0570-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch @@ -0,0 +1,250 @@ +From 8d30844b09ba90d4e1d1543e8042d01f1b7f5769 Mon Sep 17 00:00:00 2001 +From: Ran Wang +Date: Fri, 20 Mar 2026 15:50:27 +0800 +Subject: [RUYI PATCH] XIANGSHAN: Add workaround to retry when access fault + +Signed-off-by: Ran Wang +Signed-off-by: Han Gao +--- + .../include/asm/bosc_mm_fault_workaround.h | 9 ++ + arch/riscv/kernel/Makefile | 2 + + arch/riscv/kernel/bosc_mm_fault_workaround.c | 91 +++++++++++++++++++ + arch/riscv/kernel/traps.c | 14 ++- + arch/riscv/mm/fault.c | 8 ++ + kernel/watchdog.c | 3 + + 6 files changed, 126 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/include/asm/bosc_mm_fault_workaround.h + create mode 100644 arch/riscv/kernel/bosc_mm_fault_workaround.c + +diff --git a/arch/riscv/include/asm/bosc_mm_fault_workaround.h b/arch/riscv/include/asm/bosc_mm_fault_workaround.h +new file mode 100644 +index 000000000000..33c7743052f6 +--- /dev/null ++++ b/arch/riscv/include/asm/bosc_mm_fault_workaround.h +@@ -0,0 +1,9 @@ ++#ifndef __BOSC_MM_FAULT_WORKAROUND_H__ ++#define __BOSC_MM_FAULT_WORKAROUND_H__ ++ ++#include ++ ++int bosc_kernel_fault_workaround(struct pt_regs *regs); ++int bosc_segment_fault_workaround(struct pt_regs *regs); ++ ++#endif +diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile +index 0b9008a6f4e0..4b258a6d367d 100644 +--- a/arch/riscv/kernel/Makefile ++++ b/arch/riscv/kernel/Makefile +@@ -46,6 +46,8 @@ endif + + always-$(KBUILD_BUILTIN) += vmlinux.lds + ++obj-y += bosc_mm_fault_workaround.o ++ + obj-y += head.o + obj-y += soc.o + obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o +diff --git a/arch/riscv/kernel/bosc_mm_fault_workaround.c b/arch/riscv/kernel/bosc_mm_fault_workaround.c +new file mode 100644 +index 000000000000..8d97984b7879 +--- /dev/null ++++ b/arch/riscv/kernel/bosc_mm_fault_workaround.c +@@ -0,0 +1,91 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BOSC_WORKAROUND_SEGMENT_FAULT_TRY_CNT 3 ++#define BOSC_WORKAROUND_KERNEL_FAULT_TRY_CNT 3 ++ ++static unsigned long last_segment_fault_addr = 0; ++static unsigned long last_kernel_fault_addr = 0; ++ ++static int segment_fault_workaround_cnt = 0; ++static int kernel_fault_workaround_cnt = 0; ++ ++#define CSR_FLUSH_PWR 0xBC1 ++#define FLUSH_PWR_FLUSH_L2_EN 0 ++#define FLUSH_PWR_FLUSH_L2_DONE 1 ++static void core_cache_ctrl(void) ++{ ++ uint64_t value = 0; ++ ++ smp_mb(); ++ ++ csr_set(CSR_FLUSH_PWR, BIT(0)); ++ value = csr_read(CSR_FLUSH_PWR); ++ while((value & BIT(FLUSH_PWR_FLUSH_L2_DONE)) == 0) { ++ value = csr_read(CSR_FLUSH_PWR); ++ } ++} ++ ++int bosc_kernel_fault_workaround(struct pt_regs *regs) ++{ ++ unsigned long addr = regs->badaddr; ++ ++ if (addr != last_kernel_fault_addr) { ++ kernel_fault_workaround_cnt = 0; ++ goto kernel_workaround; ++ } ++ ++ kernel_fault_workaround_cnt++; ++ ++ if (kernel_fault_workaround_cnt < BOSC_WORKAROUND_KERNEL_FAULT_TRY_CNT) ++ goto kernel_workaround; ++ ++ return 0; ++ ++kernel_workaround: ++ printk("##### BOSC KERNEL FAULT WORKAROUND, cnt:%d\n", kernel_fault_workaround_cnt); ++ last_kernel_fault_addr = addr; ++ printk("badaddr: 0x%lx\n", addr); ++ dump_stack(); ++ ++ asm volatile ("sfence.vma" ::: "memory"); ++ sbi_flush_l2cache(); ++ ++ return 1; ++} ++EXPORT_SYMBOL(bosc_kernel_fault_workaround); ++ ++int bosc_segment_fault_workaround(struct pt_regs *regs) ++{ ++ unsigned long addr = regs->badaddr; ++ ++ if (addr != last_segment_fault_addr) { ++ segment_fault_workaround_cnt = 0; ++ goto segment_workaround; ++ } ++ ++ segment_fault_workaround_cnt++; ++ ++ if (segment_fault_workaround_cnt < BOSC_WORKAROUND_SEGMENT_FAULT_TRY_CNT) ++ goto segment_workaround; ++ ++ return 0; ++ ++segment_workaround: ++ printk("##### BOSC SEGMENT FAULT WORKAROUND, cnt:%d\n", segment_fault_workaround_cnt); ++ last_segment_fault_addr = addr; ++ printk("badaddr: 0x%lx\n", addr); ++ dump_stack(); ++ ++ asm volatile ("sfence.vma" ::: "memory"); ++ sbi_flush_l2cache(); ++ ++ return 1; ++} ++EXPORT_SYMBOL(bosc_segment_fault_workaround); +diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c +index 65172f072f37..784eb5986c48 100644 +--- a/arch/riscv/kernel/traps.c ++++ b/arch/riscv/kernel/traps.c +@@ -34,6 +34,9 @@ + #include + #include + ++#include ++#include ++ + int show_unhandled_signals = 1; + + static DEFINE_RAW_SPINLOCK(die_lock); +@@ -116,6 +119,9 @@ void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) + { + struct task_struct *tsk = current; + ++ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); ++ if (bosc_segment_fault_workaround(regs)) ++ return; + if (show_unhandled_signals && unhandled_signal(tsk, signo) + && printk_ratelimit()) { + pr_info("%s[%d]: unhandled signal %d code 0x%x at 0x" REG_FMT, +@@ -126,6 +132,7 @@ void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) + dump_instr(KERN_INFO, regs); + } + ++ printk("!!! BOSC DEBUG: bosc mm_fault workaround failed\n"); + force_sig_fault(signo, code, (void __user *)addr); + } + +@@ -137,8 +144,12 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, + if (user_mode(regs)) { + do_trap(regs, signo, code, addr); + } else { +- if (!fixup_exception(regs)) ++ if (!fixup_exception(regs)) { ++ if (bosc_kernel_fault_workaround(regs)) ++ return; ++ printk("!!! BOSC DEBUG: bosc mm_fault workaround failed\n"); + die(regs, str); ++ } + } + } + +@@ -150,6 +161,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, + #define DO_ERROR_INFO(name, signo, code, str) \ + asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ + { \ ++ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); \ + if (user_mode(regs)) { \ + irqentry_enter_from_user_mode(regs); \ + local_irq_enable(); \ +diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c +index 04ed6f8acae4..eed270e76581 100644 +--- a/arch/riscv/mm/fault.c ++++ b/arch/riscv/mm/fault.c +@@ -20,6 +20,9 @@ + #include + #include + ++#include ++#include ++ + #define CREATE_TRACE_POINTS + #include + +@@ -81,9 +84,14 @@ static void die_kernel_fault(const char *msg, unsigned long addr, + { + bust_spinlocks(1); + ++ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); + pr_alert("Unable to handle kernel %s at virtual address " REG_FMT "\n", msg, + addr); + ++ if (bosc_kernel_fault_workaround(regs)) ++ return; ++ ++ printk("!!! BOSC DEBUG: bosc mm_fault workaround failed\n"); + bust_spinlocks(0); + show_pte(addr); + die(regs, "Oops"); +diff --git a/kernel/watchdog.c b/kernel/watchdog.c +index 25d134306e14..4bc8448cd6ad 100644 +--- a/kernel/watchdog.c ++++ b/kernel/watchdog.c +@@ -32,6 +32,8 @@ + + #include + ++#include ++ + static DEFINE_MUTEX(watchdog_mutex); + + #if defined(CONFIG_HARDLOCKUP_DETECTOR) || defined(CONFIG_HARDLOCKUP_DETECTOR_SPARC64) +@@ -831,6 +833,7 @@ static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer) + smp_processor_id(), duration, + current->comm, task_pid_nr(current)); + report_cpu_status(); ++ printk("BOSC DEBUG: mhartid:%d\n", sbi_get_mhartid()); + print_modules(); + print_irqtrace_events(current); + if (regs) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/config.riscv64 b/SPECS/linux-lts-kmhv2/config.riscv64 index 147cea1b83..6bf3a8a1e1 100644 --- a/SPECS/linux-lts-kmhv2/config.riscv64 +++ b/SPECS/linux-lts-kmhv2/config.riscv64 @@ -1,1856 +1,7207 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_KERNEL_UNCOMPRESSED=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BPF_SYSCALL=y -CONFIG_BPF_JIT=y -CONFIG_BPF_JIT_ALWAYS_ON=y -CONFIG_PREEMPT_DYNAMIC=y -CONFIG_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_PSI=y -CONFIG_PSI_DEFAULT_DISABLED=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=20 -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_MISC=y -CONFIG_NAMESPACES=y -CONFIG_USER_NS=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -CONFIG_DEBUG_PERF_USE_VMALLOC=y -CONFIG_PROFILING=y -CONFIG_RUST=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y +# CONFIG_ERRATA_THEAD_GHOSTWRITE is not set +# CONFIG_ERRATA_THEAD_WRITE_ONCE is not set +CONFIG_64BIT=y +# CONFIG_6LOWPAN is not set +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_9P_FS=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +# CONFIG_ACCESSIBILITY is not set +CONFIG_ACLINT_SSWI=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI=y +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +# CONFIG_ACPI_BGRT is not set +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_DEBUG=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_DOCK=y +# CONFIG_ACPI_EC is not set +CONFIG_ACPI_FAN=y +CONFIG_ACPI_FFH=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +# CONFIG_ACPI_HOTPLUG_MEMORY is not set +CONFIG_ACPI_I2C_OPREGION=y +# CONFIG_ACPI_IPMI is not set +CONFIG_ACPI_MCFG=y +CONFIG_ACPI_MDIO=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NHLT=y +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PPTT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ACPI_RIMT=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_TABLE_LIB=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_THERMAL_LIB=y +CONFIG_ACPI_VIDEO=m +# CONFIG_AD525X_DPOT is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIN1100_PHY is not set +# CONFIG_ADIN1110 is not set +# CONFIG_ADIN_PHY is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_KCM is not set +# CONFIG_AF_RXRPC is not set +CONFIG_AF_UNIX_OOB=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_DWC is not set +# CONFIG_AHCI_SUNXI is not set +CONFIG_AIO=y +# CONFIG_AIR_EN8811H_PHY is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_ALIM7101_WDT=m +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ALTERA_MSGDMA is not set +CONFIG_ALTERA_STAPL=m +# CONFIG_ALTERA_TSE is not set +CONFIG_ALX=m +# CONFIG_AL_FIC is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_AMD8111_ETH is not set +CONFIG_AMD_PHY=m +# CONFIG_AMD_QDMA is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMT is not set +CONFIG_ANDES_CUSTOM_PMU=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_ANDROID_BINDER_IPC_RUST is not set +# CONFIG_ANON_VMA_NAME is not set +CONFIG_APDS9802ALS=m +CONFIG_APERTURE_HELPERS=y +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_APPLICOM is not set +# CONFIG_AQTION is not set +CONFIG_AQUANTIA_PHY=m +# CONFIG_AR5523 is not set CONFIG_ARCH_ANDES=y +CONFIG_ARCH_CANAAN=y +CONFIG_ARCH_CC_CAN_LINK=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_ARCH_ESWIN=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_CC_CAN_LINK=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_ELF_CORE_EFLAGS=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD=y +CONFIG_ARCH_HAS_PTDUMP=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAS_UBSAN=y +CONFIG_ARCH_HAS_VDSO_ARCH_DATA=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECTS_KEXEC=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y CONFIG_ARCH_SPACEMIT=y -CONFIG_SOC_STARFIVE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_STARFIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_CFI=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_RT=y +CONFIG_ARCH_SUPPORTS_SCHED_MC=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_THEAD=y CONFIG_ARCH_ULTRARISC=y +CONFIG_ARCH_USERFLAGS="-march=rv64g -mabi=lp64d" +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_ARCH_VIRT=y -CONFIG_ARCH_CANAAN=y -CONFIG_ERRATA_MIPS=y -CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y -CONFIG_SMP=y -CONFIG_NR_CPUS=256 -CONFIG_NUMA=y -CONFIG_NODES_SHIFT=7 +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y +# CONFIG_ARCNET is not set +CONFIG_ARM_AMBA=y +# CONFIG_ARM_HISI_UNCORE_DEVFREQ is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set +# CONFIG_AS21XXX_PHY is not set +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASN1_ENCODER=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_ASYNC_XOR=m +CONFIG_AS_HAS_INSN=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_AS_HAS_OPTION_ARCH=y +CONFIG_AS_HAS_ULEB128=y +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24690 +CONFIG_AT803X_PHY=m +CONFIG_ATA=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=m +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=m +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATH10K=m +# CONFIG_ATH10K_AHB is not set +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +CONFIG_ATH10K_LEDS=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_TRACING is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH11K is not set +# CONFIG_ATH12K is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_AT_XDMAC is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUTOFS_FS=y +CONFIG_AUXDISPLAY=y +CONFIG_AUXILIARY_BUS=y +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_AX88796B_PHY=m +# CONFIG_B44 is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_BD6107 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=m +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +# CONFIG_BACKLIGHT_LED is not set +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_MP3309C is not set +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BALLOON_COMPACTION=y +# CONFIG_BAREUDP is not set +# CONFIG_BASE_SMALL is not set +CONFIG_BASIC_MODVERSIONS=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_CHAGALL is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_UG3105 is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA=m +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_NET_PHYPTP=m +# CONFIG_BCM_VK is not set +CONFIG_BE2ISCSI=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFQ_CGROUP_DEBUG is not set +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFS_FS is not set +# CONFIG_BIG_KEYS is not set +CONFIG_BINARY_PRINTF=y +CONFIG_BINDGEN_VERSION_TEXT="bindgen 0.72.1" +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +CONFIG_BLK_CGROUP=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_DM=m +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_RUST_NULL is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_DEV_ZONED_LOOP is not set +CONFIG_BLK_ICQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BLK_MQ_STACKING=y +CONFIG_BLK_PM=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +# CONFIG_BNGE is not set +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +# CONFIG_BNXT_HWMON is not set +CONFIG_BNXT_SRIOV=y +CONFIG_BONDING=m +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTTIME_TRACING=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BPF=y +CONFIG_BPF_EVENTS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPF_LSM is not set +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_STREAM_PARSER=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +CONFIG_BRIDGE=m +# CONFIG_BRIDGE_CFM is not set +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_BT is not set +CONFIG_BTREE=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +CONFIG_BTRFS_EXPERIMENTAL=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTT=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUG=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +CONFIG_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_BUILD_SALT="" +# CONFIG_C2PORT is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_CAIF=y +# CONFIG_CAIF_DEBUG is not set +# CONFIG_CAIF_DRIVERS is not set +CONFIG_CAIF_NETDEV=y +# CONFIG_CAIF_USB is not set +CONFIG_CAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_C_CAN_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +# CONFIG_CAN_ESD_USB is not set +# CONFIG_CAN_ETAS_ES58X is not set +# CONFIG_CAN_F81601 is not set +# CONFIG_CAN_F81604 is not set +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_GS_USB is not set +CONFIG_CAN_GW=m +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_ISOTP is not set +# CONFIG_CAN_J1939 is not set +CONFIG_CAN_KVASER_PCI=m +# CONFIG_CAN_KVASER_PCIEFD is not set +CONFIG_CAN_KVASER_USB=m +# CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# CONFIG_CAN_M_CAN is not set +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +# CONFIG_CAN_PEAK_PCIEFD is not set +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_RAW=m +# CONFIG_CAN_RCAR is not set +# CONFIG_CAN_RCAR_CANFD is not set +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SOFTING=m +# CONFIG_CAN_SUN4I is not set +# CONFIG_CAN_UCAN is not set +CONFIG_CAN_VCAN=m +# CONFIG_CAN_VXCAN is not set +# CONFIG_CARL9170 is not set +CONFIG_CAVIUM_PTP=y +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_ASSUME=y +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_IS_GCC=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (Debian 15.3.0-1) 15.3.0" +CONFIG_CDROM=y +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +# CONFIG_CGROUP_DMEM is not set +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_WRITEBACK=y +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_MAX8971 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_RT9467 is not set +# CONFIG_CHARGER_RT9471 is not set +# CONFIG_CHARGER_SBS is not set +CONFIG_CHARGER_SMB347=m +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_LIB=m +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +# CONFIG_CHELSIO_T4_DCB is not set +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_ST=m +CONFIG_CICADA_PHY=m +CONFIG_CIFS=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_COMPRESSION is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_SWN_UPCALL is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CLANG_VERSION=0 +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set +CONFIG_CLK_RENESAS=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +# CONFIG_CLK_SOPHGO_CV1800 is not set +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y +CONFIG_CLK_SOPHGO_SG2044=y +CONFIG_CLK_SOPHGO_SG2044_PLL=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7110_AON=m +CONFIG_CLK_STARFIVE_JH7110_ISP=m +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_STG=m +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=m +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_THEAD_TH1520_AP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLOSURES=y +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=19 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CNIC=m +# CONFIG_CODA_FS is not set +# CONFIG_COMEDI is not set +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_RPMI=y +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_VC3 is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_COMPAT is not set -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_PM_DEBUG=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_CONSOLE_POLL=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTEXT_TRACKING_USER=y +# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set +CONFIG_CONTIG_ALLOC=y +CONFIG_CORDIC=m +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_CORTINA_PHY is not set +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_CPUFREQ_DT_RUST is not set +# CONFIG_CPUFREQ_VIRT is not set +CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=m -CONFIG_ACPI=y -CONFIG_ACPI_TAD=m -CONFIG_ACPI_DOCK=y -CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_HED=y -CONFIG_ACPI_NFIT=m -CONFIG_ACPI_CONFIGFS=m -CONFIG_ACPI_PFRUT=m -CONFIG_ACPI_FFH=y -CONFIG_PMIC_OPREGION=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_GENDWARFKSYMS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_MODULE_SIG_SHA256=y -CONFIG_MODULE_COMPRESS=y -CONFIG_MODULE_COMPRESS_XZ=y -CONFIG_MODULE_DECOMPRESS=y -CONFIG_BLK_DEV_ZONED=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BLK_WBT=y -CONFIG_BLK_INLINE_ENCRYPTION=y -CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_KARMA_PARTITION=y -CONFIG_MQ_IOSCHED_KYBER=m -CONFIG_BINFMT_MISC=m -CONFIG_ZSWAP=y -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y -CONFIG_ZSMALLOC_STAT=y -CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_SLAB_FREELIST_HARDENED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y -CONFIG_MEMORY_HOTREMOVE=y -CONFIG_KSM=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y -CONFIG_CMA_SYSFS=y -CONFIG_CMA_AREAS=19 -CONFIG_IDLE_PAGE_TRACKING=y -CONFIG_ZONE_DEVICE=y -CONFIG_DEVICE_PRIVATE=y -CONFIG_USERFAULTFD=y -CONFIG_LRU_GEN=y -CONFIG_LRU_GEN_ENABLED=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set +# CONFIG_CRASH_DM_CRYPT is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_CRC32_ARCH=y +CONFIG_CRC64=y +CONFIG_CRC64_ARCH=y +CONFIG_CRC7=y +CONFIG_CRC8=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_OPTIMIZATIONS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_T10DIF_ARCH=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_BENCHMARK is not set +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DEV_ALLWINNER=y +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_QAT_420XX is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_SUN4I_SS is not set +# CONFIG_CRYPTO_DEV_SUN8I_CE is not set +# CONFIG_CRYPTO_DEV_SUN8I_SS is not set +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set +CONFIG_CRYPTO_ECHAINIV=m +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_HCTR2 is not set +CONFIG_CRYPTO_HKDF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_KRB5 is not set +# CONFIG_CRYPTO_KRB5ENC is not set +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_MD5=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_ARCH=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SHA512=y +CONFIG_CRYPTO_LIB_SM3=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4=y +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SELFTESTS is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_SM3_GENERIC=y +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_RNG=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=y +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +# CONFIG_CV1800_MBOX is not set +CONFIG_CXD2880_SPI_DRV=m +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=y +# CONFIG_CXL_FEATURES is not set +CONFIG_CXL_MEM=y +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=y +CONFIG_CXL_PMEM=m +# CONFIG_CXL_PMU is not set +CONFIG_CXL_PORT=y +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_SUSPEND=y +CONFIG_DA9063_WATCHDOG=m CONFIG_DAMON=y -CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_LRU_SORT=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_STAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX_DIAG=m -CONFIG_TLS_DEVICE=y -CONFIG_XFRM_USER=m -CONFIG_XFRM_INTERFACE=m -CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y -CONFIG_XDP_SOCKETS=y -CONFIG_XDP_SOCKETS_DIAG=m -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_NET_IPVTI=m -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_DIAG=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_BBR=m -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_GRE=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_NETLABEL=y -CONFIG_MPTCP=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE_NETFILTER=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_PROCFS=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NF_CT_NETLINK_HELPER=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_NAT=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NFT_FIB_INET=m -CONFIG_NFT_DUP_NETDEV=m -CONFIG_NFT_FWD_NETDEV=m -CONFIG_NFT_FIB_NETDEV=m -CONFIG_NETFILTER_XTABLES=y -CONFIG_NETFILTER_XT_SET=m -CONFIG_NETFILTER_XT_TARGET_AUDIT=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_SET=m -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_PE_SIP=m -CONFIG_NFT_DUP_IPV4=m -CONFIG_NFT_FIB_IPV4=m -CONFIG_NF_TABLES_ARP=y -CONFIG_NF_LOG_ARP=m -CONFIG_NF_LOG_IPV4=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_SCTP=m -CONFIG_TIPC=m -CONFIG_TIPC_MEDIA_IB=y -CONFIG_L2TP=m -CONFIG_L2TP_DEBUGFS=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_SCH_DEFAULT=y -CONFIG_DEFAULT_FQ_CODEL=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_DAMON_STAT_ENABLED_DEFAULT=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y CONFIG_DCB=y -CONFIG_OPENVSWITCH=m -CONFIG_VSOCKETS=m -CONFIG_VIRTIO_VSOCKETS=m -CONFIG_NETLINK_DIAG=y -CONFIG_NET_SWITCHDEV=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_STREAM_PARSER=y -CONFIG_NET_PKTGEN=m -CONFIG_NET_DROP_MONITOR=m -CONFIG_CAN=m -CONFIG_CFG80211=m -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_NET_9P=y -CONFIG_NET_9P_FD=m -CONFIG_NET_9P_VIRTIO=y -CONFIG_CAIF=y -CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -CONFIG_LWTUNNEL=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEAER_INJECT=m -CONFIG_PCIE_ECRC=y -CONFIG_PCIE_DPC=y -CONFIG_PCIE_PTM=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_STUB=m -CONFIG_PCI_PF_STUB=m -CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -CONFIG_VGA_ARB_MAX_GPUS=64 -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCIE_XILINX=y -CONFIG_PCIE_SG2042_HOST=m -CONFIG_PCIE_DW_PLAT_HOST=y -CONFIG_PCIE_DW_PLAT_EP=y -CONFIG_PCIE_FU740=y -CONFIG_PCIE_SOPHGO_DW=y -CONFIG_PCIE_ULTRARISC=m -CONFIG_PCIE_MICROCHIP_HOST=y -CONFIG_PCIE_STARFIVE_HOST=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_CXL_BUS=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NET_SMALL_RTNL is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_PERF_USE_VMALLOC=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_VFS is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_ZSTD=y +# CONFIG_DEFAULT_CODEL is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_FQ is not set +CONFIG_DEFAULT_FQ_CODEL=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_DEFAULT_NET_SCH="fq_codel" +# CONFIG_DEFAULT_PFIFO_FAST is not set +# CONFIG_DEFAULT_RENO is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SFQ is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DETECT_HUNG_TASK_BLOCKER=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVICE_MIGRATION=y +CONFIG_DEVICE_PRIVATE=y +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_COMPRESS=y -CONFIG_FW_LOADER_COMPRESS_ZSTD=y -# CONFIG_ALLOW_DEV_COREDUMP is not set -CONFIG_SIFIVE_CCACHE=y -CONFIG_CONNECTOR=y -CONFIG_SYSFB_SIMPLEFB=y -CONFIG_TH1520_AON_PROTOCOL=y -CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y -CONFIG_MTD=m -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_MAP_BANK_WIDTH_8=y -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_BLOCK2MTD=m -CONFIG_MTD_SPI_NOR=m -CONFIG_MTD_UBI=m -CONFIG_MTD_UBI_GLUEBI=m -CONFIG_OF_OVERLAY=y -CONFIG_BLK_DEV_NULL_BLK=m -CONFIG_ZRAM=m -CONFIG_ZRAM_MULTI_COMP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 -CONFIG_BLK_DEV_DRBD=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=m -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_ATA_OVER_ETH=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_RBD=m -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_MULTIPATH=y -CONFIG_NVME_HWMON=y -CONFIG_NVME_RDMA=m -CONFIG_NVME_FC=m -CONFIG_NVME_TCP=m -CONFIG_NVME_TCP_TLS=y -CONFIG_NVME_HOST_AUTH=y -CONFIG_NVME_TARGET=m -CONFIG_NVME_TARGET_PASSTHRU=y -CONFIG_NVME_TARGET_LOOP=m -CONFIG_NVME_TARGET_RDMA=m -CONFIG_NVME_TARGET_FC=m -CONFIG_NVME_TARGET_FCLOOP=m -CONFIG_NVME_TARGET_TCP=m -CONFIG_ENCLOSURE_SERVICES=m -CONFIG_APDS9802ALS=m -CONFIG_ISL29003=m -CONFIG_ISL29020=m -CONFIG_SENSORS_TSL2550=m -CONFIG_SENSORS_BH1770=m -CONFIG_SENSORS_APDS990X=m -CONFIG_SRAM=y -CONFIG_NTSYNC=m -CONFIG_EEPROM_MAX6875=m -CONFIG_SENSORS_LIS3_I2C=m -CONFIG_ALTERA_STAPL=m -CONFIG_MISC_RTSX_PCI=m -CONFIG_MISC_RTSX_USB=m -CONFIG_UACCE=m -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_ENCLOSURE=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SAS_ATA=y -CONFIG_ISCSI_TCP=m -CONFIG_SCSI_CXGB4_ISCSI=m -CONFIG_SCSI_BNX2_ISCSI=m -CONFIG_SCSI_BNX2X_FCOE=m -CONFIG_BE2ISCSI=m -CONFIG_SCSI_HPSA=m -CONFIG_SCSI_AACRAID=m -CONFIG_MEGARAID_SAS=m -CONFIG_SCSI_MPT2SAS=m -CONFIG_SCSI_SMARTPQI=m -CONFIG_LIBFC=m -CONFIG_LIBFCOE=m -CONFIG_FCOE=m -CONFIG_SCSI_IPR=m -CONFIG_SCSI_QLA_FC=m -CONFIG_SCSI_QLA_ISCSI=m -CONFIG_QEDI=m -CONFIG_QEDF=m -CONFIG_SCSI_LPFC=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_VIRTIO=y -CONFIG_SCSI_CHELSIO_FCOE=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=y -CONFIG_SCSI_DH_HP_SW=y -CONFIG_SCSI_DH_EMC=y -CONFIG_SCSI_DH_ALUA=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_ATA_PIIX=m -CONFIG_ATA_GENERIC=m -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_DEBUG=y -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_THIN_PROVISIONING=m +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +CONFIG_DEV_DAX_HMEM_DEVICES=y +CONFIG_DEV_DAX_KMEM=m +CONFIG_DEV_DAX_PMEM=m +# CONFIG_DIBS is not set +CONFIG_DIMLIB=y +# CONFIG_DLM is not set +# CONFIG_DM9051 is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMAPOOL_TEST is not set +# CONFIG_DMATEST is not set +CONFIG_DMA_ACPI=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_CMA=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_MAP_BENCHMARK=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_NONCOHERENT_MMAP=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_OF=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_SUN6I is not set +CONFIG_DMI=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DM_AUDIT=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_BUFIO=m CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +# CONFIG_DM_CLONE is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_DEBUG=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_DUST is not set +# CONFIG_DM_EBS is not set CONFIG_DM_ERA=m -CONFIG_DM_MIRROR=m +CONFIG_DM_FLAKEY=m +CONFIG_DM_INTEGRITY=m CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=m CONFIG_DM_MULTIPATH=m +# CONFIG_DM_MULTIPATH_HST is not set +# CONFIG_DM_MULTIPATH_IOA is not set CONFIG_DM_MULTIPATH_QL=m CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_DELAY=m -CONFIG_DM_UEVENT=y -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m +# CONFIG_DM_PCACHE is not set +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=m CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_DM_INTEGRITY=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +# CONFIG_DM_UNSTRIPED is not set CONFIG_DM_VDO=m -CONFIG_TARGET_CORE=m -CONFIG_TCM_IBLOCK=m -CONFIG_TCM_FILEIO=m -CONFIG_TCM_PSCSI=m -CONFIG_TCM_USER2=m -CONFIG_LOOPBACK_TARGET=m -CONFIG_TCM_FC=m -CONFIG_ISCSI_TARGET=m -CONFIG_ISCSI_TARGET_CXGB4=m -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -CONFIG_OVPN=m -CONFIG_EQUALIZER=m -CONFIG_NET_FC=y -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN=m -CONFIG_IPVTAP=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NLMON=m -CONFIG_NET_VRF=m -CONFIG_VSOCKMON=m -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_ADAPTEC is not set -# CONFIG_NET_VENDOR_AGERE is not set -# CONFIG_NET_VENDOR_ALTEON is not set -CONFIG_ENA_ETHERNET=m -CONFIG_ATL1=m -CONFIG_ATL1E=m -CONFIG_ATL1C=m -CONFIG_ALX=m -CONFIG_TIGON3=m -CONFIG_BNX2X=m -CONFIG_BNXT=m -CONFIG_BNXT_DCB=y -# CONFIG_BNXT_HWMON is not set -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=m -CONFIG_THUNDER_NIC_VF=m -CONFIG_CAVIUM_PTP=y -CONFIG_LIQUIDIO=m -CONFIG_LIQUIDIO_VF=m -CONFIG_CHELSIO_T4VF=m -CONFIG_CHELSIO_IPSEC_INLINE=m -CONFIG_CHELSIO_TLS_DEVICE=m -# CONFIG_NET_VENDOR_CISCO is not set -# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_FEC is not set +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +# CONFIG_DM_WRITECACHE is not set +CONFIG_DM_ZERO=m +# CONFIG_DM_ZONED is not set CONFIG_DNET=m -# CONFIG_NET_VENDOR_DEC is not set -# CONFIG_NET_VENDOR_DLINK is not set -# CONFIG_NET_VENDOR_EMULEX is not set -# CONFIG_NET_VENDOR_EZCHIP is not set -# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=y +CONFIG_DP83640_PHY=m +# CONFIG_DP83822_PHY is not set +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +# CONFIG_DP83869_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set +CONFIG_DPLL=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRM=y +# CONFIG_DRM_ACCEL is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ACP is not set +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_FP=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DRM_AMD_ISP is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BRIDGE_CONNECTOR=y +CONFIG_DRM_BUDDY=m +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_CLIENT=y +CONFIG_DRM_CLIENT_DEFAULT="fbdev" +CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y +CONFIG_DRM_CLIENT_LIB=y +# CONFIG_DRM_CLIENT_LOG is not set +CONFIG_DRM_CLIENT_SELECTION=y +CONFIG_DRM_CLIENT_SETUP=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_DP_TUNNEL=y +CONFIG_DRM_DISPLAY_DSC_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DW_HDMI=m +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +# CONFIG_DRM_DW_HDMI_CEC is not set +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_EXEC=m +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=y +# CONFIG_DRM_GM12U320 is not set +CONFIG_DRM_GPUSVM=m +CONFIG_DRM_GPUVM=m +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_ITE_IT6263 is not set +# CONFIG_DRM_ITE_IT6505 is not set +# CONFIG_DRM_ITE_IT66121 is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_KOMEDA is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LOGICVC is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MGAG200=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_CH7006=m +CONFIG_DRM_NOUVEAU_SIL164=m +# CONFIG_DRM_NOVA is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS=m +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TD4320 is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112B is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_HYDIS_HV101HD1 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_RENESAS_R61307 is not set +# CONFIG_DRM_PANEL_RENESAS_R69328 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_SUMMIT is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# CONFIG_DRM_PANIC is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_PIXPAPER is not set +# CONFIG_DRM_POWERVR is not set +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_SAMSUNG_DSIM is not set +CONFIG_DRM_SCHED=m +# CONFIG_DRM_SHMOBILE is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIL_SII8620 is not set +CONFIG_DRM_SIMPLEDRM=y +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_SOLOMON_SSD2825 is not set +# CONFIG_DRM_SSD130X is not set +# CONFIG_DRM_ST7571_I2C is not set +# CONFIG_DRM_ST7586 is not set +# CONFIG_DRM_ST7735R is not set +CONFIG_DRM_SUBALLOC_HELPER=m +# CONFIG_DRM_SUN4I is not set +CONFIG_DRM_SYSFB_HELPER=y +CONFIG_DRM_THEAD_TH1520_DW_HDMI=m +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TI_DLPC3433 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TDP158 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VERISILICON_DC=m +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_WAVESHARE_BRIDGE is not set +# CONFIG_DRM_WERROR is not set +CONFIG_DRM_XE=m +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_MEMIRQ is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_DP_TUNNEL=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_GPUSVM=y +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +CONFIG_DRM_XE_PAGEMAP=y +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +# CONFIG_DS1682 is not set +CONFIG_DST_CACHE=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY=m +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_DUMMY_IRQ is not set +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m +# CONFIG_DVB_AS102 is not set +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_CXD2099=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_CXD2880=m +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_DRXK=m +CONFIG_DVB_DS3000=m +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_EC100=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_L64781=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MB86A20S=m +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_MN88443X=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_MT312=m +CONFIG_DVB_MT352=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_MXL692=m +# CONFIG_DVB_NET is not set +CONFIG_DVB_NXT200X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +# CONFIG_DVB_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLL=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_S921=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_SP2=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0297=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_TC90522=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TS2020=m +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_ULE_DEBUG is not set +# CONFIG_DVB_USB_V2 is not set +CONFIG_DVB_VES1820=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_ZL10353=m +# CONFIG_DWC_PCIE_PMU is not set +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_RENESAS_GBETH=m +CONFIG_DWMAC_SOPHGO=m +CONFIG_DWMAC_SPACEMIT=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_SUN55I=m +CONFIG_DWMAC_SUN8I=m +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_THEAD=m +# CONFIG_DW_AXI_DMAC is not set +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC_PCI=m +# CONFIG_DW_EDMA is not set +CONFIG_DW_WATCHDOG=m +# CONFIG_DW_XDATA_PCIE is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_SIGFRAME=y +# CONFIG_E100 is not set CONFIG_E1000=m CONFIG_E1000E=y -CONFIG_IGB=m -CONFIG_IGBVF=m -CONFIG_IXGBE=m -CONFIG_IXGBE_DCB=y -CONFIG_IXGBEVF=m -CONFIG_I40E=m -CONFIG_I40EVF=m -CONFIG_ICE=m -CONFIG_FM10K=m -# CONFIG_NET_VENDOR_MARVELL is not set -CONFIG_MLX4_EN=m -# CONFIG_MLX4_CORE_GEN2 is not set -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_CORE_IPOIB=y -CONFIG_MLXSW_CORE=m -# CONFIG_MLXSW_SPECTRUM is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NI is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_NETERION is not set -CONFIG_NFP=m -# CONFIG_NET_VENDOR_NVIDIA is not set -CONFIG_ETHOC=m -# CONFIG_NET_VENDOR_PACKET_ENGINES is not set -CONFIG_QLA3XXX=m -CONFIG_NETXEN_NIC=m -CONFIG_QED=m -CONFIG_QEDE=m -# CONFIG_NET_VENDOR_BROCADE is not set -CONFIG_QCOM_EMAC=m -# CONFIG_NET_VENDOR_RDC is not set -CONFIG_8139CP=m -CONFIG_8139TOO=m -# CONFIG_8139TOO_PIO is not set -CONFIG_8139TOO_8129=y -CONFIG_R8169=y -# CONFIG_NET_VENDOR_RENESAS is not set -CONFIG_ROCKER=m -# CONFIG_NET_VENDOR_SAMSUNG is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SILAN is not set -# CONFIG_NET_VENDOR_SIS is not set -CONFIG_SFC=m +# CONFIG_ECRYPT_FS is not set +CONFIG_EDAC=y +# CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_ECS is not set +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_MEM_REPAIR is not set +# CONFIG_EDAC_SCRUB is not set +CONFIG_EDAC_SIFIVE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_M24LR is not set +CONFIG_EEPROM_MAX6875=m +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +# CONFIG_EFI_ZBOOT is not set +# CONFIG_EFS_FS is not set +CONFIG_ELFCORE=y +CONFIG_ELF_CORE=y +CONFIG_ENA_ETHERNET=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENERGY_MODEL is not set CONFIG_EPIC100=m -CONFIG_SMSC911X=m -CONFIG_SMSC9420=m -# CONFIG_NET_VENDOR_SOCIONEXT is not set -CONFIG_STMMAC_ETH=m -CONFIG_DWMAC_THEAD=m -CONFIG_DWMAC_INTEL_PLAT=m -CONFIG_STMMAC_PCI=m -# CONFIG_NET_VENDOR_SUN is not set -# CONFIG_NET_VENDOR_SYNOPSYS is not set -# CONFIG_NET_VENDOR_TEHUTI is not set -# CONFIG_NET_VENDOR_TI is not set -# CONFIG_NET_VENDOR_VIA is not set -CONFIG_NGBE=m -CONFIG_TXGBE=m -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_NET_VENDOR_XILINX is not set -CONFIG_AMD_PHY=m -CONFIG_AQUANTIA_PHY=m -CONFIG_BROADCOM_PHY=m -CONFIG_BCM87XX_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_ICPLUS_PHY=m -CONFIG_LXT_PHY=m -CONFIG_LSI_ET1011C_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MICREL_PHY=m -CONFIG_MICROSEMI_PHY=m -CONFIG_NATIONAL_PHY=m -CONFIG_AT803X_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_STE10XP=m -CONFIG_TERANETICS_PHY=m -CONFIG_DP83848_PHY=m -CONFIG_DP83867_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_PLATFORM=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_MDIO_BITBANG=m -CONFIG_MDIO_BCM_UNIMAC=m -CONFIG_MDIO_GPIO=m -CONFIG_MDIO_OCTEON=m -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=m -CONFIG_PPTP=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -# CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -# CONFIG_WLAN_VENDOR_ATMEL is not set -# CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_INTEL is not set -# CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set -# CONFIG_WLAN_VENDOR_MEDIATEK is not set -CONFIG_RT2X00=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT53XX=y -CONFIG_RTL8180=m -CONFIG_RTL8187=m -CONFIG_RTL8192CE=m -CONFIG_RTL8192SE=m -CONFIG_RTL8192DE=m -CONFIG_RTL8723AE=m -CONFIG_RTL8723BE=m -CONFIG_RTL8188EE=m -CONFIG_RTL8192EE=m -CONFIG_RTL8821AE=m -CONFIG_RTL8192CU=m -CONFIG_RTL8192DU=m -# CONFIG_RTLWIFI_DEBUG is not set -CONFIG_RTL8XXXU=m -CONFIG_RTW88=m -CONFIG_RTW88_8822BE=m -CONFIG_RTW88_8822BS=m -CONFIG_RTW88_8822BU=m -CONFIG_RTW88_8822CE=m -CONFIG_RTW88_8822CS=m -CONFIG_RTW88_8822CU=m -CONFIG_RTW88_8723DE=m -CONFIG_RTW88_8723DS=m -CONFIG_RTW88_8723CS=m -CONFIG_RTW88_8723DU=m -CONFIG_RTW88_8821CE=m -CONFIG_RTW88_8821CS=m -CONFIG_RTW88_8821CU=m -CONFIG_RTW88_8821AU=m -CONFIG_RTW88_8812AU=m -CONFIG_RTW88_8814AE=m -CONFIG_RTW88_8814AU=m -CONFIG_RTW89=m -CONFIG_RTW89_8851BE=m -CONFIG_RTW89_8851BU=m -CONFIG_RTW89_8852AE=m -CONFIG_RTW89_8852BE=m -CONFIG_RTW89_8852BU=m -CONFIG_RTW89_8852BTE=m -CONFIG_RTW89_8852CE=m -CONFIG_RTW89_8922AE=m -# CONFIG_WLAN_VENDOR_RSI is not set -# CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set -# CONFIG_WLAN_VENDOR_ZYDAS is not set -# CONFIG_WLAN_VENDOR_QUANTENNA is not set -CONFIG_WAN=y +CONFIG_EPOLL=y +CONFIG_EPROBE_EVENTS=y +CONFIG_EQUALIZER=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_BACKED_BY_FILE=y +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ACCEL is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +# CONFIG_EROFS_FS_ZIP_LZMA is not set +# CONFIG_EROFS_FS_ZIP_ZSTD is not set +CONFIG_ERRATA_ANDES=y +CONFIG_ERRATA_MIPS=y +CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_MAE=y +CONFIG_ERRATA_THEAD_PMU=y +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_EVENTFD=y +CONFIG_EVENT_TRACING=y +CONFIG_EVM=y +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +CONFIG_EVM_LOAD_X509=y +CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=y +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXTCON=y +# CONFIG_EXTCON_FSA9480 is not set +CONFIG_EXTCON_GPIO=m +# CONFIG_EXTCON_LC824206XA is not set +# CONFIG_EXTCON_MAX14526 is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTENDED_MODVERSIONS=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +# CONFIG_FARSYNC is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_FB=y +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_CARMINE is not set +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CIRRUS is not set +CONFIG_FB_CORE=y +# CONFIG_FB_CYBER2000 is not set +CONFIG_FB_DDC=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +# CONFIG_FB_KYRO is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_NEOMAGIC is not set +CONFIG_FB_NOTIFY=y +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_RADEON_I2C=y +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_SSD1307=m +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +CONFIG_FCOE=m +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +CONFIG_FHANDLE=y +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_FIRMWARE_TABLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FM10K=m +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_FPGA is not set +# CONFIG_FPROBE is not set +CONFIG_FPU=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMER is not set +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +# CONFIG_FSCACHE is not set +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_DAX is not set +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +# CONFIG_FS_VERITY is not set +# CONFIG_FTL is not set +CONFIG_FTRACE=y +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set +# CONFIG_FUEL_GAUGE_STC3117 is not set +# CONFIG_FUJITSU_ES is not set +CONFIG_FUNCTION_ALIGNMENT=8 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ALIGNMENT_8B=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FUNCTION_GRAPH_RETADDR is not set +# CONFIG_FUNCTION_GRAPH_RETVAL is not set +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_TRACE_ARGS=y +# CONFIG_FUN_ETH is not set +CONFIG_FUSE_FS=y +CONFIG_FUSE_IO_URING=y +CONFIG_FUSE_PASSTHROUGH=y +# CONFIG_FUSION is not set +CONFIG_FUTEX=y +CONFIG_FUTEX_MPOL=y +CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y +# CONFIG_FWCTL is not set +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_FW_UPLOAD=y +CONFIG_GACT_PROB=y +# CONFIG_GAMEPORT is not set +CONFIG_GARP=m +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_GCC_VERSION=150300 +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_GENDWARFKSYMS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_NUMA=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_ENTRY=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_SYSCALL=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_TRACER=y +CONFIG_GENEVE=m +# CONFIG_GENKSYMS is not set +# CONFIG_GENWQE is not set +CONFIG_GET_FREE_REGION=y +# CONFIG_GFS2_FS is not set +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GNSS is not set +CONFIG_GOLDFISH=y +# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH_TTY is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIOLIB_LEGACY=y +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +CONFIG_GPIO_ACPI=y +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_BT8XX is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +# CONFIG_GPIO_DS4520 is not set +CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_FXL6408 is not set +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=m +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPSSE is not set +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_POLARFIRE_SOC is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_SIM is not set +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +CONFIG_GPIO_SPACEMIT_K1=y +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SYSFS_LEGACY=y +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set +CONFIG_GPIO_WATCHDOG=m +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_GP_PCI1XXXX is not set +CONFIG_GRACE_PERIOD=y +# CONFIG_GREENASIA_FF is not set +# CONFIG_GREYBUS is not set +CONFIG_GROUP_SCHED_BANDWIDTH=y +CONFIG_GROUP_SCHED_WEIGHT=y +CONFIG_GRO_CELLS=y +# CONFIG_GTP is not set +CONFIG_GUEST_PERF_EVENTS=y +# CONFIG_GUP_TEST is not set +# CONFIG_HAMRADIO is not set +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_DEFAULT_ON=y +CONFIG_HARDIRQS_SW_RESEND=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_SECURITY_AUDIT=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_HAVE_ARCH_KFENCE=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_HAVE_ARCH_KSTACK_ERASE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_GRAPH_FUNC=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_TIF_BITS=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_GIGANTIC_FOLIOS=y +CONFIG_HAVE_GUP_FAST=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_UNCOMPRESSED=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KVM_DIRTY_RING=y +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_READONLY_MEM=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_TRUSTED_KEYS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HD44780 is not set CONFIG_HDLC=m -CONFIG_HDLC_RAW=m CONFIG_HDLC_CISCO=m CONFIG_HDLC_FR=m CONFIG_HDLC_PPP=m -CONFIG_USB4_NET=m -CONFIG_INPUT_SPARSEKMAP=m -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_EVDEV=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_MOUSE_PS2_ELANTECH=y -CONFIG_MOUSE_PS2_SENTELIC=y -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -CONFIG_MOUSE_CYAPA=m -CONFIG_MOUSE_VSXXXAA=m -CONFIG_MOUSE_SYNAPTICS_I2C=m -CONFIG_MOUSE_SYNAPTICS_USB=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_RMI4_I2C=m -CONFIG_RMI4_SPI=m -CONFIG_RMI4_SMB=m -CONFIG_SERIO_RAW=m -CONFIG_SERIO_ALTERA_PS2=m -CONFIG_SERIO_ARC_PS2=m -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_EARLYCON_RISCV_SBI=y -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_N_HDLC=m -CONFIG_N_GSM=m -CONFIG_TTY_PRINTK=m -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SSIF=m -CONFIG_IPMI_WATCHDOG=m -CONFIG_IPMI_POWEROFF=m +CONFIG_HDLC_RAW=m +# CONFIG_HDLC_RAW_ETH is not set +CONFIG_HDMI=y +CONFIG_HEADERS_INSTALL=y +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFS_FS is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_DEF_COMP="lzo" +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +# CONFIG_HIBMCGE is not set +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +CONFIG_HID_ACRUX=m +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_ALPS is not set +CONFIG_HID_APPLE=y +CONFIG_HID_APPLEIR=m +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BETOP_FF=m +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_BPF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CORSAIR=m +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=m +# CONFIG_HID_ELAN is not set +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EVISION is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=y +CONFIG_HID_GFRM=m +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_GOODIX_SPI is not set +# CONFIG_HID_GOOGLE_STADIA_FF is not set +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +# CONFIG_HID_HAPTIC is not set +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=y +# CONFIG_HID_JABRA is not set +CONFIG_HID_KENSINGTON=y +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +# CONFIG_HID_KYSONA is not set +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +# CONFIG_HID_MACALLY is not set +CONFIG_HID_MAGICMOUSE=y +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MCP2200 is not set +# CONFIG_HID_MCP2221 is not set +# CONFIG_HID_MEGAWORLD_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=m +# CONFIG_HID_NINTENDO is not set +# CONFIG_HID_NTI is not set +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_RETRODE is not set +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_SENSOR_HUB=m +# CONFIG_HID_SIGMAMICRO is not set +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +# CONFIG_HID_STEAM is not set +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +# CONFIG_HID_TOPRE is not set +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +# CONFIG_HID_U2FZERO is not set +CONFIG_HID_UCLOGIC=m +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_UNIVERSAL_PIDFF is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_VRC2 is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set +# CONFIG_HID_XIAOMI is not set +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_HMC6352 is not set +CONFIG_HMEM_REPORTING=y +CONFIG_HMM_MIRROR=y +# CONFIG_HOLTEK_FF is not set +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_OCTEONEP is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +# CONFIG_HPFS_FS is not set +# CONFIG_HP_ILO is not set +CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HT16K33 is not set +# CONFIG_HTE is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HVC_DRIVER=y +CONFIG_HWLAT_TRACER=y +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON_VID=m +CONFIG_HWSPINLOCK=y +# CONFIG_HWSPINLOCK_SUN6I is not set CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_JH7110 is not set CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y CONFIG_HW_RANDOM_VIRTIO=y -# CONFIG_DEVPORT is not set -CONFIG_TCG_TIS=y -CONFIG_TCG_TIS_SPI=y -CONFIG_TCG_TIS_I2C_ATMEL=m -CONFIG_TCG_TIS_I2C_INFINEON=m -CONFIG_TCG_TIS_I2C_NUVOTON=m -CONFIG_TCG_ATMEL=m -CONFIG_TCG_TIS_ST33ZP24_I2C=m -CONFIG_TCG_TIS_ST33ZP24_SPI=m +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=m +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +# CONFIG_I2C_AT91 is not set +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_CCGX_UCSI=m CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DIOLAN_U2C=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_CORE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +CONFIG_I2C_K1=m +# CONFIG_I2C_MICROCHIP_CORE is not set CONFIG_I2C_MUX=m -CONFIG_I2C_ARB_GPIO_CHALLENGE=m CONFIG_I2C_MUX_GPIO=m +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_MULE is not set CONFIG_I2C_MUX_PCA9541=m CONFIG_I2C_MUX_PCA954x=m CONFIG_I2C_MUX_PINCTRL=m -CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MV64XXX is not set CONFIG_I2C_NFORCE2=m -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_SLAVE=y -CONFIG_I2C_DESIGNWARE_PCI=m -CONFIG_I2C_GPIO=m -CONFIG_I2C_K1=m +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_NVIDIA_GPU is not set CONFIG_I2C_OCORES=m CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RIIC is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_RZV2M is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set CONFIG_I2C_SIMTEC=m -CONFIG_I2C_DIOLAN_U2C=m -CONFIG_I2C_TINY_USB=m -CONFIG_I2C_STUB=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=m -CONFIG_SPI=y -CONFIG_SPI_CADENCE=m -CONFIG_SPI_DESIGNWARE=y -CONFIG_SPI_DW_PCI=m -CONFIG_SPI_DW_MMIO=y -CONFIG_SPI_FSL_QUADSPI=m -CONFIG_SPI_SIFIVE=y -CONFIG_SPI_SG2044_NOR=m -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_GPIO=m -CONFIG_DP83640_PHY=m -CONFIG_PINCTRL_TH1520=y -CONFIG_PINCTRL_SOPHGO_SG2042=y -CONFIG_PINCTRL_SOPHGO_SG2044=y -CONFIG_PINCTRL_ULTRARISC_DP1000=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_CADENCE=m -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC_PLATFORM=m -CONFIG_GPIO_SIFIVE=y -CONFIG_GPIO_SPACEMIT_K1=y -CONFIG_GPIO_PCA953X=m -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_TH1520_AON=m -CONFIG_POWER_SEQUENCING=m -CONFIG_POWER_SEQUENCING_TH1520_GPU=m -CONFIG_CHARGER_SMB347=m -CONFIG_SENSORS_AD7314=m -CONFIG_SENSORS_AD7414=m -CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1025=m -CONFIG_SENSORS_ADM1026=m -CONFIG_SENSORS_ADM1029=m -CONFIG_SENSORS_ADM1031=m -CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_ADT7310=m -CONFIG_SENSORS_ADT7410=m -CONFIG_SENSORS_ADT7411=m -CONFIG_SENSORS_ADT7462=m -CONFIG_SENSORS_ADT7470=m -CONFIG_SENSORS_ADT7475=m -CONFIG_SENSORS_ASC7621=m -CONFIG_SENSORS_ATXP1=m -CONFIG_SENSORS_COREPVT_ULTRARISC=m -CONFIG_SENSORS_DS620=m -CONFIG_SENSORS_DS1621=m -CONFIG_SENSORS_F71805F=m -CONFIG_SENSORS_F71882FG=m -CONFIG_SENSORS_F75375S=m -CONFIG_SENSORS_GL518SM=m -CONFIG_SENSORS_GL520SM=m -CONFIG_SENSORS_G760A=m -CONFIG_SENSORS_G762=m -CONFIG_SENSORS_IBMAEM=m -CONFIG_SENSORS_IBMPEX=m -CONFIG_SENSORS_IT87=m -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_POWR1220=m -CONFIG_SENSORS_LINEAGE=m -CONFIG_SENSORS_LTC2945=m -CONFIG_SENSORS_LTC4151=m -CONFIG_SENSORS_LTC4215=m -CONFIG_SENSORS_LTC4222=m -CONFIG_SENSORS_LTC4245=m -CONFIG_SENSORS_LTC4260=m -CONFIG_SENSORS_LTC4261=m -CONFIG_SENSORS_MAX1111=m -CONFIG_SENSORS_MAX16065=m -CONFIG_SENSORS_MAX1619=m -CONFIG_SENSORS_MAX1668=m -CONFIG_SENSORS_MAX197=m -CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6650=m -CONFIG_SENSORS_MAX6697=m -CONFIG_SENSORS_MAX31790=m -CONFIG_SENSORS_MCP3021=m -CONFIG_SENSORS_MR75203=m -CONFIG_SENSORS_ADCXX=m -CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM70=m -CONFIG_SENSORS_LM73=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM77=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM80=m -CONFIG_SENSORS_LM83=m -CONFIG_SENSORS_LM85=m -CONFIG_SENSORS_LM87=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_LM92=m -CONFIG_SENSORS_LM93=m -CONFIG_SENSORS_LM95234=m -CONFIG_SENSORS_LM95241=m -CONFIG_SENSORS_LM95245=m -CONFIG_SENSORS_PC87360=m -CONFIG_SENSORS_PC87427=m -CONFIG_SENSORS_NCT6683=m -CONFIG_SENSORS_NCT7802=m -CONFIG_SENSORS_NCT7904=m -CONFIG_SENSORS_PCF8591=m -CONFIG_PMBUS=m -CONFIG_SENSORS_ADM1275=m -CONFIG_SENSORS_LM25066=m -CONFIG_SENSORS_LTC2978=m -CONFIG_SENSORS_LTC3815=m -CONFIG_SENSORS_MAX16064=m -CONFIG_SENSORS_MAX20751=m -CONFIG_SENSORS_MAX34440=m -CONFIG_SENSORS_MAX8688=m -CONFIG_SENSORS_TPS40422=m -CONFIG_SENSORS_UCD9000=m -CONFIG_SENSORS_UCD9200=m -CONFIG_SENSORS_ZL6100=m -CONFIG_SENSORS_PWM_FAN=y -CONFIG_SENSORS_SHT15=m -CONFIG_SENSORS_SHT21=m -CONFIG_SENSORS_SHTC1=m -CONFIG_SENSORS_SIS5595=m -CONFIG_SENSORS_DME1737=m -CONFIG_SENSORS_EMC1403=m -CONFIG_SENSORS_EMC6W201=m -CONFIG_SENSORS_SMSC47M1=m -CONFIG_SENSORS_SMSC47M192=m -CONFIG_SENSORS_SMSC47B397=m -CONFIG_SENSORS_SCH5627=m -CONFIG_SENSORS_SCH5636=m -CONFIG_SENSORS_SG2042_MCU=m -CONFIG_SENSORS_ADC128D818=m -CONFIG_SENSORS_ADS7828=m -CONFIG_SENSORS_ADS7871=m -CONFIG_SENSORS_AMC6821=m -CONFIG_SENSORS_INA209=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_TC74=m -CONFIG_SENSORS_THMC50=m -CONFIG_SENSORS_TMP102=m -CONFIG_SENSORS_TMP103=m -CONFIG_SENSORS_TMP401=m -CONFIG_SENSORS_TMP421=m -CONFIG_SENSORS_VIA686A=m -CONFIG_SENSORS_VT1211=m -CONFIG_SENSORS_VT8231=m -CONFIG_SENSORS_W83781D=m -CONFIG_SENSORS_W83791D=m -CONFIG_SENSORS_W83792D=m -CONFIG_SENSORS_W83793=m -CONFIG_SENSORS_W83795=m -CONFIG_SENSORS_W83L785TS=m -CONFIG_SENSORS_W83L786NG=m -CONFIG_SENSORS_W83627HF=m -CONFIG_SENSORS_W83627EHF=m -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_SPACEMIT_K1_TSENSOR=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_SYSFS=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_DA9063_WATCHDOG=m -CONFIG_GPIO_WATCHDOG=m -CONFIG_DW_WATCHDOG=m -CONFIG_ALIM7101_WDT=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_STUB=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VIRTIO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2C_ZHAOXIN is not set +# CONFIG_I3C is not set +CONFIG_I40E=m +CONFIG_I40EVF=m +# CONFIG_I40E_DCB is not set CONFIG_I6300ESB_WDT=m -CONFIG_PCIPCWATCHDOG=m -CONFIG_WDTPCI=m -CONFIG_USBPCWATCHDOG=m -CONFIG_BCMA=m -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_MFD_DA9063=m -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PWM=y -# CONFIG_MEDIA_CEC_SUPPORT is not set -CONFIG_MEDIA_SUPPORT=m -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -# CONFIG_DVB_NET is not set -# CONFIG_DVB_DYNAMIC_MINORS is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_AUXDISPLAY=y -CONFIG_DRM=y -CONFIG_DRM_LOAD_EDID_FIRMWARE=y -CONFIG_DRM_SIMPLEDRM=y -CONFIG_DRM_RADEON=m -CONFIG_DRM_RADEON_USERPTR=y -CONFIG_DRM_AMDGPU=m -CONFIG_DRM_AMDGPU_SI=y -CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMD_DC_SI=y -CONFIG_HSA_AMD=y -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_XE=m -CONFIG_DRM_UDL=m -CONFIG_DRM_AST=m -CONFIG_DRM_MGAG200=m -CONFIG_DRM_QXL=m -CONFIG_DRM_VIRTIO_GPU=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_THEAD_TH1520_DW_HDMI=m -CONFIG_DRM_BOCHS=m -CONFIG_DRM_CIRRUS_QEMU=m -CONFIG_DRM_VERISILICON_DC=m -CONFIG_FB=y -CONFIG_FB_EFI=y -CONFIG_FB_RADEON=y -CONFIG_FB_SSD1307=m -CONFIG_FB_TILEBLITTING=y -CONFIG_LCD_CLASS_DEVICE=m -CONFIG_LCD_PLATFORM=m -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_BACKLIGHT_GPIO=m -CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_ALOOP=m -CONFIG_SND_HDA_INTEL=m -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_SOC=m -CONFIG_SND_SOC_K1_I2S=m -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HIDRAW=y -CONFIG_UHID=m -CONFIG_HID_A4TECH=y -CONFIG_HID_ACRUX=m -CONFIG_HID_APPLE=y -CONFIG_HID_APPLEIR=m -CONFIG_HID_AUREAL=m -CONFIG_HID_BELKIN=y -CONFIG_HID_BETOP_FF=m -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CORSAIR=m -CONFIG_HID_CYPRESS=y -CONFIG_HID_DRAGONRISE=m -CONFIG_HID_ELECOM=m -CONFIG_HID_ELO=m -CONFIG_HID_EZKEY=y -CONFIG_HID_GEMBIRD=m -CONFIG_HID_GFRM=m -CONFIG_HID_HOLTEK=m -CONFIG_HID_GT683R=m -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_GYRATION=m -CONFIG_HID_ICADE=m -CONFIG_HID_ITE=y -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=y -CONFIG_HID_LCPOWER=m -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NTRIG=y -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_HID_PENMOUNT=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PLANTRONICS=m -CONFIG_HID_PRIMAX=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_SONY_FF=y -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_STEELSERIES=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_RMI=m -CONFIG_HID_GREENASIA=m -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_THINGM=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -CONFIG_HID_XINMO=m -CONFIG_HID_ZEROPLUS=m -CONFIG_HID_ZYDACRON=m -CONFIG_HID_SENSOR_HUB=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_I2C_HID_OF_ELAN=m -CONFIG_I2C_HID_OF_GOODIX=m -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_LED_TRIG=y -CONFIG_USB_ULPI_BUS=m -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=m -CONFIG_USB_MON=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_PRINTER=m -CONFIG_USB_TMC=m -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=y -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_DWC3=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_HSIC_USB3503=m -CONFIG_USB_CHAOSKEY=m -CONFIG_USB_ONBOARD_DEV=m -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_UCSI=m -CONFIG_TYPEC_DP_ALTMODE=m -CONFIG_USB_ROLE_SWITCH=y -CONFIG_MMC=y -CONFIG_PWRSEQ_EMMC=m -CONFIG_PWRSEQ_SIMPLE=m -CONFIG_SDIO_UART=m -CONFIG_MMC_CRYPTO=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PCI=m -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=m -CONFIG_MMC_SDHCI_OF_K1=m -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_TIFM_SD=m -CONFIG_MMC_SPI=y -CONFIG_MMC_CB710=m -CONFIG_MMC_VIA_SDMMC=m -CONFIG_MMC_DW=m -CONFIG_MMC_DW_BLUEFIELD=m -CONFIG_MMC_DW_PCI=m -CONFIG_MMC_VUB300=m -CONFIG_MMC_USHC=m -CONFIG_MMC_REALTEK_PCI=m -CONFIG_MMC_REALTEK_USB=m -CONFIG_MMC_CQHCI=y -CONFIG_MMC_TOSHIBA_PCI=m -CONFIG_MMC_MTK=m -CONFIG_MMC_SDHCI_XENON=m -CONFIG_MEMSTICK=m -CONFIG_MSPRO_BLOCK=m -CONFIG_MEMSTICK_TIFM_MS=m -CONFIG_MEMSTICK_JMICRON_38X=m -CONFIG_MEMSTICK_R592=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_CLASS_FLASH=m -CONFIG_LEDS_LM3530=m -CONFIG_LEDS_LP3944=m -CONFIG_LEDS_LT3593=m -CONFIG_LEDS_BLINKM=m -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_ONESHOT=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_IAVF=m +CONFIG_ICE=m +CONFIG_ICE_HWMON=y +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICPLUS_PHY=m +# CONFIG_ICS932S401 is not set +CONFIG_IDLE_PAGE_TRACKING=y +# CONFIG_IDPF is not set +# CONFIG_IEEE802154 is not set +CONFIG_IFB=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGB_HWMON=y +# CONFIG_IGC is not set +# CONFIG_IIO is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMA=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +# CONFIG_IMA_APPRAISE_MODSIG is not set +# CONFIG_IMA_APPRAISE_SIGNED_INIT is not set +# CONFIG_IMA_ARCH_POLICY is not set +# CONFIG_IMA_BLACKLIST_KEYRING is not set +CONFIG_IMA_DEFAULT_HASH="sha256" +# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set +CONFIG_IMA_DEFAULT_HASH_SHA256=y +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +# CONFIG_IMA_DEFAULT_HASH_SM3 is not set +CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" +# CONFIG_IMA_DISABLE_HTABLE is not set +# CONFIG_IMA_KEXEC is not set +# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set +CONFIG_IMA_LOAD_X509=y +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y +CONFIG_IMA_READ_POLICY=y +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_WRITE_POLICY is not set +CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_INET=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=m +# CONFIG_INET_PSP is not set +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_SCTP_DIAG=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_XFRM_TUNNEL=m CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_MAD=m -CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y CONFIG_INFINIBAND_BNXT_RE=m CONFIG_INFINIBAND_CXGB4=m -CONFIG_MLX4_INFINIBAND=m -CONFIG_MLX5_INFINIBAND=m -CONFIG_INFINIBAND_QEDR=m -CONFIG_RDMA_RXE=m +# CONFIG_INFINIBAND_EFA is not set +# CONFIG_INFINIBAND_ERDMA is not set CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB_CM=y # CONFIG_INFINIBAND_IPOIB_DEBUG is not set -CONFIG_INFINIBAND_SRP=m -CONFIG_INFINIBAND_SRPT=m CONFIG_INFINIBAND_ISER=m CONFIG_INFINIBAND_ISERT=m -CONFIG_EDAC=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_SYSTOHC is not set -CONFIG_RTC_DRV_ABB5ZES3=m -CONFIG_RTC_DRV_ABX80X=m -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_DS1374=m -CONFIG_RTC_DRV_DS1374_WDT=y -CONFIG_RTC_DRV_DS1672=m -CONFIG_RTC_DRV_MAX6900=m -CONFIG_RTC_DRV_RS5C372=m -CONFIG_RTC_DRV_ISL1208=m -CONFIG_RTC_DRV_ISL12022=m -CONFIG_RTC_DRV_X1205=m -CONFIG_RTC_DRV_PCF8523=m -CONFIG_RTC_DRV_PCF8563=m -CONFIG_RTC_DRV_PCF8583=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_M41T80_WDT=y -CONFIG_RTC_DRV_BQ32K=m -CONFIG_RTC_DRV_FM3130=m -CONFIG_RTC_DRV_RX8010=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RX8025=m -CONFIG_RTC_DRV_EM3027=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_M41T93=m -CONFIG_RTC_DRV_M41T94=m -CONFIG_RTC_DRV_DS1305=m -CONFIG_RTC_DRV_DS1343=m -CONFIG_RTC_DRV_DS1347=m -CONFIG_RTC_DRV_DS1390=m -CONFIG_RTC_DRV_R9701=m -CONFIG_RTC_DRV_RX4581=m -CONFIG_RTC_DRV_RS5C348=m -CONFIG_RTC_DRV_MAX6902=m -CONFIG_RTC_DRV_PCF2123=m -CONFIG_RTC_DRV_MCP795=m -CONFIG_RTC_DRV_DS3232=m -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_RV3029C2=m -# CONFIG_RTC_DRV_RV3029_HWMON is not set -CONFIG_RTC_DRV_DS1286=m -CONFIG_RTC_DRV_DS1511=m -CONFIG_RTC_DRV_DS1553=m -CONFIG_RTC_DRV_DS1685_FAMILY=m -CONFIG_RTC_DRV_DS1742=m -CONFIG_RTC_DRV_DS2404=m -CONFIG_RTC_DRV_DA9063=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_STK17TA8=m -CONFIG_RTC_DRV_M48T35=m -CONFIG_RTC_DRV_M48T59=m -CONFIG_RTC_DRV_MSM6242=m -CONFIG_RTC_DRV_RP5C01=m -CONFIG_DMADEVICES=y -CONFIG_QCOM_HIDMA_MGMT=m -CONFIG_QCOM_HIDMA=m -CONFIG_DW_DMAC=m -CONFIG_DW_DMAC_PCI=m -CONFIG_ASYNC_TX_DMA=y +# CONFIG_INFINIBAND_MTHCA is not set +# CONFIG_INFINIBAND_OCRDMA is not set +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_RTRS_CLIENT is not set +# CONFIG_INFINIBAND_RTRS_SERVER is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_VIRT_DMA=y +# CONFIG_INFTL is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_STACK_NONE=y +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_AW86927 is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_DA9063_ONKEY is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_IBM_PANEL is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_VIVALDIFMAP=y +# CONFIG_INPUT_YEALINK is not set +CONFIG_INTEGRITY=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_INTEGRITY_MACHINE_KEYRING is not set +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_TH is not set +# CONFIG_INTEL_XWAY_PHY is not set +CONFIG_INTERCONNECT=y +CONFIG_INTERVAL_TREE=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IONIC is not set +CONFIG_IOSCHED_BFQ=y +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IO_URING_MOCK_FILE is not set +CONFIG_IO_URING_ZCRX=y +CONFIG_IO_WQ=y +# CONFIG_IP5XXX_POWER is not set +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_MATCH_SRH is not set +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +# CONFIG_IPACK_BUS is not set +CONFIG_IPC_NS=y +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_IPMB is not set +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPV6=y +CONFIG_IPV6_GRE=m +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +# CONFIG_IPV6_SUBTREES is not set +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPVLAN=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVTAP=m +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +# CONFIG_IP_SET_HASH_IPMAC is not set +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +# CONFIG_IP_VS_MH is not set +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +# CONFIG_IP_VS_TWOS is not set +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IRQCHIP=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TCP=m +# CONFIG_ISDN is not set +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_ISO9660_FS=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_JH71XX_PMU=y +# CONFIG_JME is not set +CONFIG_JOLIET=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KARMA_PARTITION=y +# CONFIG_KASAN is not set +CONFIG_KCMP=y +# CONFIG_KCOV is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x0 +CONFIG_KDB_KEYBOARD=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_UNCOMPRESSED=y +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KERNFS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_ELF=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_KEY_DH_OPERATIONS is not set +CONFIG_KFENCE=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=100 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +CONFIG_KGDB_TESTS=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +CONFIG_KPROBES=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_KSM=y +# CONFIG_KUNIT is not set +CONFIG_KVFREE_RCU_BATCHED=y +CONFIG_KVM=m +CONFIG_KVM_COMMON=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_KVM_GENERIC_MMU_NOTIFIER=y +CONFIG_KVM_MMIO=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP_V3=y +# CONFIG_LAPB is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LCD2S is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_PARTITION is not set +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set +CONFIG_LD_IS_BFD=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_LD_VERSION=24690 +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_AW200XX is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_BLINKM=m +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3601X is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3697 is not set +CONFIG_LEDS_LP3944=m +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LP8864 is not set +CONFIG_LEDS_LT3593=m +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_ST1202 is not set +# CONFIG_LEDS_SY7802 is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_TPS6131X is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +CONFIG_LEDS_TRIGGER_ONESHOT=m +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +# CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LIBETH=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y +CONFIG_LIBIE=m +CONFIG_LIBIE_ADMINQ=m +CONFIG_LIBIE_FWLOG=m +CONFIG_LIBNVDIMM=m +CONFIG_LIBWX=m +CONFIG_LINEAR_RANGES=y +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_CORE=m +CONFIG_LIQUIDIO_VF=m +CONFIG_LIST_HARDENED=y +# CONFIG_LITEX_LITEETH is not set +# CONFIG_LITEX_SOC_CONTROLLER is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +CONFIG_LLD_VERSION=0 +# CONFIG_LMK04832 is not set +CONFIG_LOAD_UEFI_KEYS=y +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKD=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=20 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOOPBACK_TARGET=m +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +CONFIG_LRU_CACHE=m +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" +CONFIG_LSM_MMAP_MIN_ADDR=32768 +CONFIG_LTO_NONE=y +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_LXT_PHY=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211=m +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_HWSIM is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +# CONFIG_MAC_PARTITION is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +# CONFIG_MANAGER_SBS is not set +CONFIG_MARVELL_10G_PHY=m +# CONFIG_MARVELL_88Q2XXX_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +CONFIG_MARVELL_PHY=m +# CONFIG_MAX31827 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX6959 is not set +# CONFIG_MAXLINEAR_86110_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +CONFIG_MAX_SKB_FRAGS=17 +# CONFIG_MCB is not set +CONFIG_MCHP_CLK_MPFS=y +# CONFIG_MCHP_LAN966X_PCI is not set +# CONFIG_MCHP_SBI_IPC_MBOX is not set +# CONFIG_MCTP is not set +CONFIG_MD=y +CONFIG_MDIO=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_MVUSB is not set +CONFIG_MDIO_OCTEON=m +# CONFIG_MDIO_SUN4I is not set +CONFIG_MDIO_THUNDER=m +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP=y +CONFIG_MD_BITMAP_FILE=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_LLBITMAP is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MEDIATEK_GE_PHY is not set +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +CONFIG_MEGARAID_SAS=m +CONFIG_MEMBARRIER=y +CONFIG_MEMCG=y +# CONFIG_MEMCG_V1 is not set +CONFIG_MEMFD_CREATE=y +# CONFIG_MEMORY is not set +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMREGION=y +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +# CONFIG_MEMSTICK_REALTEK_USB is not set +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +# CONFIG_MEMTEST is not set +# CONFIG_MEM_ALLOC_PROFILING is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_ADP5585 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_AT91_USART is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_BQ257XX is not set +CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +CONFIG_MFD_DA9063=m +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_LS2K_BMC_CORE is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX5970 is not set +# CONFIG_MFD_MAX7360 is not set +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77705 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77759 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_NCT6694 is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_SEC_I2C is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMPRO is not set +CONFIG_MFD_SPACEMIT_P1=m +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_SUN4I_GPADC is not set +# CONFIG_MFD_SUN6I_PRCM is not set +# CONFIG_MFD_SY7636A is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE is not set +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set +CONFIG_MHP_MEMMAP_ON_MEMORY=y +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1S_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROSEMI_PHY=m +CONFIG_MIGRATION=y +CONFIG_MII=m +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_MIN_HEAP=y +# CONFIG_MISC_ALCOR_PCI is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISC_RP1 is not set +CONFIG_MISC_RTSX=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MLX4_CORE=m +# CONFIG_MLX4_CORE_GEN2 is not set +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_DPLL is not set +CONFIG_MLX5_EN_ARFS=y +# CONFIG_MLX5_EN_IPSEC is not set +CONFIG_MLX5_EN_RXNFC=y +# CONFIG_MLX5_EN_TLS is not set +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_HW_STEERING=y +CONFIG_MLX5_INFINIBAND=m +# CONFIG_MLX5_MACSEC is not set +CONFIG_MLX5_MPFS=y +# CONFIG_MLX5_SF is not set +CONFIG_MLX5_SW_STEERING=y +# CONFIG_MLX5_VFIO_PCI is not set +CONFIG_MLXFW=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +# CONFIG_MLXSW_SPECTRUM is not set +CONFIG_MMC=y +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=y +CONFIG_MMC_CRYPTO=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_BLUEFIELD=m +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_MTK=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_ACPI is not set +CONFIG_MMC_SDHCI_CADENCE=y +# CONFIG_MMC_SDHCI_F_SDH30 is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_OF_K1=m +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_UHS2=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHI is not set +# CONFIG_MMC_SH_MMCIF is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_SUNXI is not set +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_TOSHIBA_PCI=m +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMIOWB=y +CONFIG_MMP_PDMA=m +CONFIG_MMU=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MM_ID=y +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ALL=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_DECOMPRESS=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULE_SIG_HASH="sha256" +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_SHA1 is not set +CONFIG_MODULE_SIG_SHA256=y +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +# CONFIG_MOST is not set +# CONFIG_MOTORCOMM_PHY is not set +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXTET is not set +CONFIG_MPILIB=y +CONFIG_MPLS=y +# CONFIG_MPLS_ROUTING is not set +CONFIG_MPTCP=y +CONFIG_MPTCP_IPV6=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_MRP=m +# CONFIG_MSCC_OCELOT_SWITCH is not set +CONFIG_MSDOS_FS=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSE102X is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set +CONFIG_MTD=m +# CONFIG_MTD_ABSENT is not set +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +# CONFIG_MTD_BLOCK_RO is not set +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CMDLINE_PARTS=m +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD_INTEL_DG is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PHRAM is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_NVMEM is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTIUSER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MYRI10GE is not set +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +# CONFIG_NCN26000_PHY is not set +CONFIG_ND_BTT=m +CONFIG_ND_CLAIM=y +CONFIG_ND_PFN=m +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET=y +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVSIM is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XTABLES_LEGACY is not set +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_NETFILTER_XT_NAT is not set +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +# CONFIG_NETFILTER_XT_TARGET_HL is not set +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_MASQUERADE is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +# CONFIG_NETFS_DEBUG is not set +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETKIT is not set +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=y +CONFIG_NETPOLL=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETXEN_NIC=m +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +# CONFIG_NET_9P_RDMA is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_ACT_BPF=m +# CONFIG_NET_ACT_CONNMARK is not set +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_GACT=m +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_ACT_IFE is not set +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CORE=y +CONFIG_NET_CRC32C=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NET_DROP_MONITOR=m +# CONFIG_NET_DSA is not set +CONFIG_NET_EGRESS=y +CONFIG_NET_EMATCH=y +# CONFIG_NET_EMATCH_CANID is not set +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_FAILOVER=y +CONFIG_NET_FC=y +CONFIG_NET_FLOW_LIMIT=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_NET_HANDSHAKE=y +# CONFIG_NET_IFE is not set +CONFIG_NET_INGRESS=y +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_NET_NCSI is not set +CONFIG_NET_NS=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_REDIRECT=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_BPF is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_CBS is not set +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_DEFAULT=y +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_DUALPI2 is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_ETS is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_CODEL=m +# CONFIG_NET_SCH_FQ_PIE is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SHAPER=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_NET_VENDOR_AGERE is not set +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALLWINNER=y +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_SPACEMIT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +CONFIG_NET_VENDOR_VERTEXCOM=y +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_NET_VRF=m +CONFIG_NET_XGRESS=y +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_APP_FLOWER=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP_NET_IPSEC=y +CONFIG_NFSD=m +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_LEGACY_CLIENT_TRACKING=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_V4_2_INTER_SSC=y +# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_DEBUG=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_LOCALIO is not set +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_2=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_NFS_V4_SECURITY_LABEL=y +# CONFIG_NFTL is not set +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COMPAT_ARP=m +# CONFIG_NFT_CONNLIMIT is not set +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +# CONFIG_NFT_EXTHDR_DCCP is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +# CONFIG_NFT_OSF is not set +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +# CONFIG_NFT_REJECT_NETDEV is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_SYNPROXY is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_XFRM is not set +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_AMANDA=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NGBE=m +# CONFIG_NGBEVF is not set +# CONFIG_NIC7018_WDT is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +CONFIG_NLMON=m +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +CONFIG_NODES_SHIFT=7 +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_TRACER=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +# CONFIG_NOVA_CORE is not set +# CONFIG_NOZOMI is not set +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_PAGE_MAPCOUNT is not set +CONFIG_NR_CPUS=256 +# CONFIG_NSM is not set +# CONFIG_NTB is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS_FS=m +CONFIG_NTSYNC=m +# CONFIG_NULL_TTY is not set +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NUMA_EMU is not set +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NVDIMM_DAX=y +CONFIG_NVDIMM_KEYS=y +CONFIG_NVDIMM_PFN=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SOPHGO_EFUSE=m +# CONFIG_NVMEM_SUNXI_SID is not set +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_U_BOOT_ENV is not set +CONFIG_NVME_AUTH=y +CONFIG_NVME_CORE=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_KEYRING=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_AUTH is not set +# CONFIG_NVME_TARGET_DEBUGFS is not set +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_PASSTHRU=y +# CONFIG_NVME_TARGET_PCI_EPF is not set +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_TCP_TLS is not set +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NUMA=y +CONFIG_OF_OVERLAY=y +# CONFIG_OF_PARTITION is not set +CONFIG_OF_PMEM=m +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OID_REGISTRY=y +# CONFIG_OMFS_FS is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +# CONFIG_OPEN_DICE is not set +# CONFIG_ORANGEFS_FS is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OSNOISE_TRACER=y +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVMF_DEBUG_LOG is not set +CONFIG_OVPN=m +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_PAGE_COUNTER=y +# CONFIG_PAGE_EXTENSION is not set +CONFIG_PAGE_IDLE_FLAG=y +CONFIG_PAGE_MAPCOUNT=y +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_VERSION=131 +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARAVIRT is not set +# CONFIG_PARPORT is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ACPI is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +CONFIG_PATA_TIMINGS=y +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PC104 is not set +# CONFIG_PC300TOO is not set +CONFIG_PCC=y +# CONFIG_PCCARD is not set +CONFIG_PCI=y +# CONFIG_PCI200SYN is not set +CONFIG_PCIEAER=y +CONFIG_PCIEAER_CXL=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_CADENCE=m +CONFIG_PCIE_CADENCE_HOST=m +# CONFIG_PCIE_CADENCE_PLAT_EP is not set +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +CONFIG_PCIE_DPC=y +CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_DEBUGFS is not set +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_ECRC=y +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_FU740=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_PLDA_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_RCAR_EP is not set +# CONFIG_PCIE_RCAR_GEN4_EP is not set +# CONFIG_PCIE_RCAR_GEN4_HOST is not set +# CONFIG_PCIE_RCAR_HOST is not set +CONFIG_PCIE_SG2042_HOST=m +CONFIG_PCIE_SOPHGO_DW=y +CONFIG_PCIE_SPACEMIT_K1=y +CONFIG_PCIE_STARFIVE_HOST=y +# CONFIG_PCIE_THERMAL is not set +# CONFIG_PCIE_TPH is not set +CONFIG_PCIE_ULTRARISC=m +CONFIG_PCIE_XILINX=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_ATS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_DOE=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCI_ECAM=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +# CONFIG_PCI_ENDPOINT_MSI_DOORBELL is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_PCI_EPF_NTB is not set +# CONFIG_PCI_EPF_TEST is not set +# CONFIG_PCI_FTPCI100 is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI=y +# CONFIG_PCI_NPEM is not set +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_PASID=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTRL=y +CONFIG_PCI_PWRCTRL_SLOT=y +CONFIG_PCI_QUIRKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +# CONFIG_PCI_SW_SWITCHTEC is not set +# CONFIG_PCNET32 is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCS_RZN1_MIIC=m +CONFIG_PCS_XPCS=m +# CONFIG_PDC_ADMA is not set +# CONFIG_PDS_CORE is not set +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_PFCP is not set +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=5 +# CONFIG_PHANTOM is not set +# CONFIG_PHONET is not set +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_NXP_PTN3222 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_PACKAGE=m +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set +# CONFIG_PHY_RCAR_GEN2 is not set +# CONFIG_PHY_RCAR_GEN3_PCIE is not set +# CONFIG_PHY_RCAR_GEN3_USB2 is not set +# CONFIG_PHY_RCAR_GEN3_USB3 is not set +# CONFIG_PHY_SOPHGO_CV1800_USB2 is not set +CONFIG_PHY_SPACEMIT_K1_PCIE=y +CONFIG_PHY_SPACEMIT_K1_USB2=m +CONFIG_PHY_SPACEMIT_K3_COMBO_PHY=m +CONFIG_PHY_SPACEMIT_K3_COMMON_OPS=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_SUN4I_USB is not set +# CONFIG_PHY_SUN50I_USB3 is not set +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PHY_TH1520_USB=m +# CONFIG_PHY_TUSB1210 is not set +CONFIG_PID_NS=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_AW9523 is not set +# CONFIG_PINCTRL_CY8C95X0 is not set +# CONFIG_PINCTRL_EIC7700 is not set +# CONFIG_PINCTRL_K230 is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RENESAS=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_SOPHGO_COMMON=y +# CONFIG_PINCTRL_SOPHGO_CV1800B is not set +# CONFIG_PINCTRL_SOPHGO_CV1812H is not set +# CONFIG_PINCTRL_SOPHGO_SG2000 is not set +# CONFIG_PINCTRL_SOPHGO_SG2002 is not set +CONFIG_PINCTRL_SOPHGO_SG2042=y +CONFIG_PINCTRL_SOPHGO_SG2042_OPS=y +CONFIG_PINCTRL_SOPHGO_SG2044=y +CONFIG_PINCTRL_SPACEMIT_K1=y +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN55I_A523 is not set +# CONFIG_PINCTRL_SUN55I_A523_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_TH1520=y +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set +CONFIG_PLDMFW=y +# CONFIG_PLFXLC is not set +# CONFIG_PLX_DMA is not set +CONFIG_PM=y +CONFIG_PMBUS=m +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +CONFIG_PMIC_OPREGION=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_FLEXFILE_LAYOUT=y +CONFIG_PNP=y +CONFIG_PNPACPI=y +CONFIG_PNP_DEBUG_MESSAGES=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set +CONFIG_PORTABLE=y +# CONFIG_POSIX_AUX_CLOCKS is not set +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POSIX_TIMERS=y +# CONFIG_POWERCAP is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SPACEMIT_P1=m +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_TH1520_AON=m +CONFIG_POWER_SEQUENCING=m +# CONFIG_POWER_SEQUENCING_QCOM_WCN is not set +CONFIG_POWER_SEQUENCING_TH1520_GPU=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPP=m +CONFIG_PPPOE=m +CONFIG_PPPOE_HASH_BITS=4 +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS=y +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPS_GENERATOR is not set +CONFIG_PPTP=m +# CONFIG_PREEMPT is not set +CONFIG_PREEMPTION=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPT_LAZY is not set +CONFIG_PREEMPT_NONE=y +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +# CONFIG_PREEMPT_RT is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_PRIME_NUMBERS is not set +CONFIG_PRINTK=y +CONFIG_PRINTK_CALLER=y +# CONFIG_PRINTK_INDEX is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +# CONFIG_PROVE_LOCKING is not set +CONFIG_PSAMPLE=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTP_1588_CLOCK=y +# CONFIG_PTP_1588_CLOCK_FC3W is not set +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_INES is not set +# CONFIG_PTP_1588_CLOCK_MOCK is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +# CONFIG_PTP_NETC_V4_TIMER is not set +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +# CONFIG_PWM_ARGON_FAN_HAT is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set +# CONFIG_PWM_MC33XS2410 is not set +# CONFIG_PWM_MICROCHIP_CORE is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_PROVIDE_GPIO is not set +# CONFIG_PWM_PXA is not set +# CONFIG_PWM_RENESAS_RCAR is not set +# CONFIG_PWM_RENESAS_TPU is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_SOPHGO_SG2042=m +# CONFIG_PWM_SUN4I is not set +CONFIG_PWM_TH1520=m +# CONFIG_PWM_XILINX is not set +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA807X_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +CONFIG_QCOM_EMAC=m +CONFIG_QCOM_HIDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_NET_PHYLIB=m +# CONFIG_QCOM_PMIC_GLINK is not set +# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED_FCOE=y +CONFIG_QED_ISCSI=y +CONFIG_QED_LL2=y +CONFIG_QED_OOO=y +CONFIG_QED_RDMA=y +CONFIG_QED_SRIOV=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QLA3XXX=m +# CONFIG_QLCNIC is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QRTR is not set +CONFIG_QSEMI_PHY=m +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=y +CONFIG_R8169=y +CONFIG_RADIO_ADAPTERS=m +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RAPIDIO is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RCAR_DMAC is not set +# CONFIG_RCAR_GEN3_THERMAL is not set +# CONFIG_RCAR_THERMAL is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RC_CORE is not set +CONFIG_RDMA_RXE=m +# CONFIG_RDMA_SIW is not set +# CONFIG_RDS is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=y +# CONFIG_REALTEK_PHY_HWMON is not set +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=m +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ADP5055 is not set +# CONFIG_REGULATOR_AW37503 is not set +# CONFIG_REGULATOR_DA9063 is not set +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX20411 is not set +# CONFIG_REGULATOR_MAX77503 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MAX77838 is not set +# CONFIG_REGULATOR_MAX77857 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF0900 is not set +# CONFIG_REGULATOR_PF530X is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PF9453 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RAA215300 is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT4803 is not set +# CONFIG_REGULATOR_RT5133 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5739 is not set +# CONFIG_REGULATOR_RT5759 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTQ2208 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_SLG51000 is not set +CONFIG_REGULATOR_SPACEMIT_P1=m +CONFIG_REGULATOR_SUN20I=y +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC is not set +# CONFIG_REMOTE_TARGET is not set +# CONFIG_RENESAS_OSTM is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_RENESAS_RZAWDT is not set +# CONFIG_RENESAS_RZN1WDT is not set +# CONFIG_RENESAS_RZV2HWDT is not set +# CONFIG_RENESAS_USB_DMAC is not set +# CONFIG_RENESAS_WDT is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_RESET_K230=y +CONFIG_RESET_POLARFIRE_SOC=y +# CONFIG_RESET_RZV2H_USB2PHY is not set +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SPACEMIT_COMMON=y +CONFIG_RESET_SPACEMIT_K1=y +CONFIG_RESET_SPACEMIT_K3=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_SUNXI=y +CONFIG_RESET_TH1520=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set +CONFIG_RETHOOK=y +# CONFIG_RFD_FTL is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFS_ACCEL=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_APLIC=y +CONFIG_RISCV_APLIC_MSI=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_RISCV_COMBO_SPINLOCKS=y +CONFIG_RISCV_DMA_NONCOHERENT=y +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set +CONFIG_RISCV_IMSIC=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_IOMMU=y +CONFIG_RISCV_IOMMU_PCI=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SUPM=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_VENDOR_EXT=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y +CONFIG_RISCV_ISA_VENDOR_EXT_MIPS=y +CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y +CONFIG_RISCV_ISA_VENDOR_EXT_THEAD=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_V_PREEMPTIVE=y +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 +CONFIG_RISCV_ISA_XTHEADVECTOR=y +CONFIG_RISCV_ISA_ZABHA=y +CONFIG_RISCV_ISA_ZACAS=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y +CONFIG_RISCV_ISA_ZBKB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOP=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_MISALIGNED=y +CONFIG_RISCV_NONSTANDARD_CACHE_OPS=y +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS=y +CONFIG_RISCV_RPMI_SYSMSI=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_CPUIDLE=y +CONFIG_RISCV_SBI_MPXY_MBOX=y +# CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SCALAR_MISALIGNED=y +# CONFIG_RISCV_TICKET_SPINLOCKS is not set +CONFIG_RISCV_TIMER=y +CONFIG_RISCV_VECTOR_MISALIGNED=y +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +# CONFIG_RMI4_F1A is not set +# CONFIG_RMI4_F21 is not set +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +# CONFIG_RMI4_F55 is not set +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +# CONFIG_RMNET is not set +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_ROCKER=m +# CONFIG_ROMFS_FS is not set +CONFIG_ROOT_NFS=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set +# CONFIG_RPMB is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_NS=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_TTY is not set +CONFIG_RPMSG_VIRTIO=y +CONFIG_RPS=y +CONFIG_RSEQ=y +# CONFIG_RT2400PCI is not set +# CONFIG_RT2500PCI is not set +# CONFIG_RT2500USB is not set +# CONFIG_RT2800PCI is not set +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +# CONFIG_RT2800USB_RT3573 is not set +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +# CONFIG_RT2800USB_RT55XX is not set +# CONFIG_RT2800USB_UNKNOWN is not set +CONFIG_RT2800_LIB=m +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_USB=m +# CONFIG_RT61PCI is not set +# CONFIG_RT73USB is not set +# CONFIG_RTASE is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_DRV_ABB5ZES3=m +# CONFIG_RTC_DRV_ABEOZ9 is not set +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_CADENCE is not set +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685=y +CONFIG_RTC_DRV_DS1685_FAMILY=m +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +# CONFIG_RTC_DRV_FTRTC010 is not set +CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_ISL12026 is not set +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX31335 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +# CONFIG_RTC_DRV_MAX6916 is not set +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +# CONFIG_RTC_DRV_NCT3018Y is not set +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_POLARFIRE_SOC is not set +# CONFIG_RTC_DRV_R7301 is not set +CONFIG_RTC_DRV_R9701=m +# CONFIG_RTC_DRV_RENESAS_RTCA3 is not set +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3029C2=m +# CONFIG_RTC_DRV_RV3029_HWMON is not set +# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_RX4581=m +# CONFIG_RTC_DRV_RX6110 is not set +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +# CONFIG_RTC_DRV_RX8111 is not set +CONFIG_RTC_DRV_RX8581=m +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SD2405AL is not set +# CONFIG_RTC_DRV_SD3078 is not set +# CONFIG_RTC_DRV_SH is not set +CONFIG_RTC_DRV_SPACEMIT_P1=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_NVMEM=y +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192D_COMMON=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +# CONFIG_RTL8XXXU_UNTESTED is not set +CONFIG_RTLBTCOEXIST=m +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTL_CARDS=m +CONFIG_RTW88=m +CONFIG_RTW88_8703B=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8723X=m +CONFIG_RTW88_8812A=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_8814A=m +CONFIG_RTW88_8814AE=m +CONFIG_RTW88_8814AU=m +CONFIG_RTW88_8821A=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_88XXA=m +CONFIG_RTW88_CORE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW88_LEDS=y +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW89=m +CONFIG_RTW89_8851B=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BT=m +CONFIG_RTW89_8852BTE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852B_COMMON=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922A=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_CORE=m +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89_PCI=m +CONFIG_RTW89_USB=m +CONFIG_RT_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED_DEFAULT_DISABLED is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RUST=y +CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_FILE_AS_C_STR=y +CONFIG_RUSTC_HAS_FILE_WITH_NUL=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y +CONFIG_RUSTC_LLVM_VERSION=210108 +CONFIG_RUSTC_SUPPORTS_RISCV=y +CONFIG_RUSTC_VERSION=109500 +CONFIG_RUSTC_VERSION_TEXT="rustc 1.95.0 (59807616e 2026-04-14) (built from a source tarball)" +CONFIG_RUST_BINDGEN_HAS_ZICSR_ZIFENCEI=y +# CONFIG_RUST_BITMAP_HARDENED is not set +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +CONFIG_RUST_IS_AVAILABLE=y +CONFIG_RUST_OVERFLOW_CHECKS=y +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set +CONFIG_RUST_PWM_ABSTRACTIONS=y +# CONFIG_RV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_RZG2L_THERMAL is not set +# CONFIG_RZG3E_THERMAL is not set +CONFIG_SAMPLES=y +# CONFIG_SAMPLES_RUST is not set +# CONFIG_SAMPLE_ANDROID_BINDERFS is not set +# CONFIG_SAMPLE_AUXDISPLAY is not set +# CONFIG_SAMPLE_CGROUP is not set +# CONFIG_SAMPLE_CHECK_EXEC is not set +# CONFIG_SAMPLE_CONFIGFS is not set +# CONFIG_SAMPLE_CONNECTOR is not set +# CONFIG_SAMPLE_DAMON_MTIER is not set +# CONFIG_SAMPLE_DAMON_PRCL is not set +# CONFIG_SAMPLE_DAMON_WSSE is not set +# CONFIG_SAMPLE_FANOTIFY_ERROR is not set +# CONFIG_SAMPLE_FTRACE_DIRECT is not set +# CONFIG_SAMPLE_FTRACE_DIRECT_MULTI is not set +# CONFIG_SAMPLE_FTRACE_OPS is not set +# CONFIG_SAMPLE_HIDRAW is not set +# CONFIG_SAMPLE_HUNG_TASK is not set +# CONFIG_SAMPLE_KDB is not set +# CONFIG_SAMPLE_KFIFO is not set +# CONFIG_SAMPLE_KOBJECT is not set +# CONFIG_SAMPLE_KPROBES is not set +# CONFIG_SAMPLE_LANDLOCK is not set +# CONFIG_SAMPLE_PIDFD is not set +# CONFIG_SAMPLE_RPMSG_CLIENT is not set +# CONFIG_SAMPLE_SECCOMP is not set +# CONFIG_SAMPLE_TIMER is not set +# CONFIG_SAMPLE_TPS6594_PFSM is not set +# CONFIG_SAMPLE_TRACE_ARRAY is not set +# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set +# CONFIG_SAMPLE_TRACE_EVENTS is not set +# CONFIG_SAMPLE_TRACE_PRINTK is not set +# CONFIG_SAMPLE_TSM_MR is not set +# CONFIG_SAMPLE_UHID is not set +# CONFIG_SAMPLE_VFIO_MDEV_MBOCHS is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set +# CONFIG_SAMPLE_VFIO_MDEV_MTTY is not set +# CONFIG_SAMPLE_VFS is not set +# CONFIG_SAMPLE_WATCHDOG is not set +# CONFIG_SAMPLE_WATCH_QUEUE is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_DWC is not set +CONFIG_SATA_HOST=y +# CONFIG_SATA_INIC162X is not set +CONFIG_SATA_MOBILE_LPM_POLICY=0 +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_ZPODD is not set +CONFIG_SBITMAP=y +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CLASS_EXT is not set +CONFIG_SCHED_HRTICK=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MM_CID=y +# CONFIG_SCHED_PROXY_EXEC is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_SCHED_TRACER=y +CONFIG_SCREEN_INFO=y +CONFIG_SCSI=y +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +CONFIG_SCSI_AACRAID=m +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BNX2_ISCSI=m +# CONFIG_SCSI_BUSLOGIC is not set +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_CXGB3_ISCSI is not set +CONFIG_SCSI_CXGB4_ISCSI=m +# CONFIG_SCSI_DC395x is not set +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_ALUA=y +CONFIG_SCSI_DH_EMC=y +CONFIG_SCSI_DH_HP_SW=y +CONFIG_SCSI_DH_RDAC=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EFCT is not set +CONFIG_SCSI_ENCLOSURE=m +# CONFIG_SCSI_ESAS2R is not set +CONFIG_SCSI_FC_ATTRS=m +# CONFIG_SCSI_FDOMAIN_PCI is not set +CONFIG_SCSI_HPSA=m +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR_TRACE=y +# CONFIG_SCSI_IPS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPI3MR is not set +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SCSI_NETLINK=y +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +# CONFIG_SCSI_SNIC is not set +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +CONFIG_SCSI_UFSHCD=m +# CONFIG_SCSI_UFSHCD_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_BSG=y +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +CONFIG_SCSI_UFS_CRYPTO=y +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_HWMON=y +# CONFIG_SCSI_UFS_RENESAS is not set +CONFIG_SCSI_UFS_SPACEMIT=m +CONFIG_SCSI_VIRTIO=y +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y +CONFIG_SDIO_UART=m +# CONFIG_SDR_MAX2175 is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP_FILTER=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY_INFINIBAND=y +# CONFIG_SECURITY_IPE is not set +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +# CONFIG_SECURITY_SELINUX_DEBUG is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ACBEL_FSG032 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM1266 is not set +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +# CONFIG_SENSORS_ADP1050 is not set +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_AHT10 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set +CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_BEL_PFE is not set +CONFIG_SENSORS_BH1770=m +# CONFIG_SENSORS_BPA_RS600 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_CRPS is not set +# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set +CONFIG_SENSORS_DME1737=m +# CONFIG_SENSORS_DPS920AB is not set +# CONFIG_SENSORS_DRIVETEMP is not set +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +# CONFIG_SENSORS_FSP_3Y is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_HTU31 is not set +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_INA209=m +# CONFIG_SENSORS_INA233 is not set +# CONFIG_SENSORS_INA238 is not set +CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL28022 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM25066=m +# CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +# CONFIG_SENSORS_LT3074 is not set +# CONFIG_SENSORS_LT7182S is not set +CONFIG_SENSORS_LTC2945=m +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +# CONFIG_SENSORS_LTC4286 is not set +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX16601 is not set +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +# CONFIG_SENSORS_MAX6620 is not set +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX8688=m +# CONFIG_SENSORS_MC34VR500 is not set +CONFIG_SENSORS_MCP3021=m +# CONFIG_SENSORS_MP2856 is not set +# CONFIG_SENSORS_MP2869 is not set +# CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set +# CONFIG_SENSORS_MP29502 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set +# CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set +# CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set +# CONFIG_SENSORS_MPQ7932 is not set +# CONFIG_SENSORS_MPQ8785 is not set +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set +# CONFIG_SENSORS_NCT7363 is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +# CONFIG_SENSORS_PIM4328 is not set +# CONFIG_SENSORS_PLI1209BC is not set +# CONFIG_SENSORS_PM6764TR is not set +CONFIG_SENSORS_PMBUS=m +# CONFIG_SENSORS_POWERZ is not set +CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PT5161L is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_PXE1610 is not set +# CONFIG_SENSORS_Q54SJ108A2 is not set +# CONFIG_SENSORS_SBTSI is not set +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SCH56XX_COMMON=m +# CONFIG_SENSORS_SFCTEMP is not set +CONFIG_SENSORS_SG2042_MCU=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +# CONFIG_SENSORS_SPD5118 is not set +# CONFIG_SENSORS_STPDDC60 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_TC654 is not set +CONFIG_SENSORS_TC74=m +# CONFIG_SENSORS_TDA38640 is not set +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +# CONFIG_SENSORS_TMP108 is not set +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +# CONFIG_SENSORS_TMP464 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_TPS25990 is not set +CONFIG_SENSORS_TPS40422=m +# CONFIG_SENSORS_TPS53679 is not set +# CONFIG_SENSORS_TPS546D24 is not set +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +# CONFIG_SENSORS_W83773G is not set +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +# CONFIG_SENSORS_XDP710 is not set +# CONFIG_SENSORS_XDPE122 is not set +# CONFIG_SENSORS_XDPE152 is not set +# CONFIG_SENSORS_XGENE is not set +CONFIG_SENSORS_ZL6100=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +# CONFIG_SERIAL_8250_EM is not set +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PCI1XXXX is not set +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_ATMEL is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SPRD is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIO=y +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_GPIO_PS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_SUN4I_PS2 is not set +CONFIG_SFC=m +# CONFIG_SFC_FALCON is not set +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_SFC_SRIOV=y +CONFIG_SFP=m +# CONFIG_SF_PDMA is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SIGNALFD=y +CONFIG_SIGNATURE=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIOX is not set +CONFIG_SKB_DECRYPTED=y +CONFIG_SKB_EXTENSIONS=y +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_OBJ_EXT=y +CONFIG_SLHC=m +# CONFIG_SLICOSS is not set +# CONFIG_SLIMBUS is not set +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_SLIP_SMART=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_SMBFS=m +# CONFIG_SMB_SERVER is not set +CONFIG_SMP=y +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_SM_FTL is not set +CONFIG_SND=m +# CONFIG_SND_AD1889 is not set +CONFIG_SND_ALOOP=m +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CTL_FAST_LOOKUP=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +CONFIG_SND_HDA=m +# CONFIG_SND_HDA_ACPI is not set +# CONFIG_SND_HDA_CODEC_ANALOG is not set +# CONFIG_SND_HDA_CODEC_CA0110 is not set +# CONFIG_SND_HDA_CODEC_CA0132 is not set +# CONFIG_SND_HDA_CODEC_CIRRUS is not set +# CONFIG_SND_HDA_CODEC_CM9825 is not set +# CONFIG_SND_HDA_CODEC_CMEDIA is not set +# CONFIG_SND_HDA_CODEC_CONEXANT is not set +# CONFIG_SND_HDA_CODEC_HDMI is not set +# CONFIG_SND_HDA_CODEC_REALTEK is not set +# CONFIG_SND_HDA_CODEC_SENARYTECH is not set +# CONFIG_SND_HDA_CODEC_SI3054 is not set +# CONFIG_SND_HDA_CODEC_SIGMATEL is not set +# CONFIG_SND_HDA_CODEC_VIA is not set +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_CORE=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# CONFIG_SND_HDA_GENERIC is not set +# CONFIG_SND_HDA_HWDEP is not set +CONFIG_SND_HDA_I915=y +# CONFIG_SND_HDA_INPUT_BEEP is not set +CONFIG_SND_HDA_INTEL=m +# CONFIG_SND_HDA_PATCH_LOADER is not set +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDA_RECONFIG is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_SPI is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_HWDEP=m +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OSSEMUL is not set +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +CONFIG_SND_PCM=m +# CONFIG_SND_PCMTEST is not set +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCXHR is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_RAWMIDI=m +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +CONFIG_SND_SOC=m +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1373 is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_ADI_AXI_I2S is not set +# CONFIG_SND_SOC_ADI_AXI_SPDIF is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_SOC_AW8738 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88081 is not set +# CONFIG_SND_SOC_AW88166 is not set +# CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88399 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CHV3_CODEC is not set +# CONFIG_SND_SOC_CHV3_I2S is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L45_I2C is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS35L56_I2C is not set +# CONFIG_SND_SOC_CS35L56_SPI is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L83 is not set +# CONFIG_SND_SOC_CS42L84 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS48L32 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8323 is not set +# CONFIG_SND_SOC_ES8326 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_ES8375 is not set +# CONFIG_SND_SOC_ES8389 is not set +# CONFIG_SND_SOC_FS210X is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_IDT821034 is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_JH7110_PWMDAC is not set +# CONFIG_SND_SOC_JH7110_TDM is not set +CONFIG_SND_SOC_K1_I2S=m +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98388 is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX98396 is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX98520 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MIKROE_PROTO is not set +# CONFIG_SND_SOC_MSIOF is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8325 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_NTP8835 is not set +# CONFIG_SND_SOC_NTP8918 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1754 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_RCAR is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RT9123 is not set +# CONFIG_SND_SOC_RT9123P is not set +# CONFIG_SND_SOC_RTQ9124 is not set +# CONFIG_SND_SOC_RTQ9128 is not set +CONFIG_SND_SOC_SDCA_OPTIONAL=m +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SH4_FSI is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SMA1303 is not set +# CONFIG_SND_SOC_SMA1307 is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM3515 is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set +# CONFIG_SND_SOC_TAS2781_I2C is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS5805M is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_UDA1342 is not set +# CONFIG_SND_SOC_USB is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731_I2C is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8940 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SOC_ZL38060 is not set +CONFIG_SND_SPI=y +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SND_SUPPORT_OLD_API=y +# CONFIG_SND_TEST_COMPONENT is not set +CONFIG_SND_TIMER=m +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_UTIMER is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTIO is not set +# CONFIG_SND_VIRTUOSO is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_SOC_BUS=y +CONFIG_SOC_RENESAS=y +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_TI is not set +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM is not set +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONY_FF=y +# CONFIG_SOPHGO_CV1800B_DMAMUX is not set +# CONFIG_SOPHGO_CV1800_RTCSYS is not set +CONFIG_SOPHGO_SG2042_MSI=y +CONFIG_SOPHGO_SG2044_TOPSYS=y +CONFIG_SOUND=m +# CONFIG_SOUNDWIRE is not set +CONFIG_SPACEMIT_CCU=y +CONFIG_SPACEMIT_K1_CCU=y +CONFIG_SPACEMIT_K1_EMAC=m +CONFIG_SPACEMIT_K1_TSENSOR=m +CONFIG_SPACEMIT_K3_CCU=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_ATMEL is not set +# CONFIG_SPI_AX88796C is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_CADENCE=m +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_DESIGNWARE=y +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_FSL_QUADSPI=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_POLARFIRE_SOC is not set +# CONFIG_SPI_RSPI is not set +# CONFIG_SPI_RZV2H_RSPI is not set +# CONFIG_SPI_RZV2M_CSI is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SG2044_NOR=m +# CONFIG_SPI_SH_HSPI is not set +# CONFIG_SPI_SH_MSIOF is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI_SN_F_OSPI is not set +CONFIG_SPI_SPACEMIT_K1=m +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_VIRTIO is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +# CONFIG_SPMI is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_ZSTD is not set +CONFIG_SRAM=y +# CONFIG_SSB is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSFDC is not set +# CONFIG_SSIF_IPMI_BMC is not set +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_STACK_TRACER=y +# CONFIG_STAGING is not set +CONFIG_STANDALONE=y +CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set +# CONFIG_STARFIVE_STARLINK_PMU is not set +CONFIG_STARFIVE_WATCHDOG=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +# CONFIG_STM is not set +CONFIG_STMMAC_ETH=m +CONFIG_STMMAC_PCI=m +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STP=m +CONFIG_STREAM_PARSER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN20I_PPU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +# CONFIG_SUN50I_DE2_BUS is not set +# CONFIG_SUN50I_H6_PRCM_PPU is not set +# CONFIG_SUN50I_IOMMU is not set +CONFIG_SUN55I_PCK600=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUNRPC=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_DEBUG=y +# CONFIG_SUNRPC_DEBUG_TRACE is not set +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +# CONFIG_SUNXI_WATCHDOG is not set +# CONFIG_SUN_PARTITION is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SWPHY=y +# CONFIG_SW_SYNC is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYN_COOKIES=y +# CONFIG_SYSCON_REBOOT_MODE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +CONFIG_SYSFB_SIMPLEFB=y +CONFIG_SYSFS=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set +CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_REVOCATION_KEYS="" +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_TAP=m +CONFIG_TARGET_CORE=m +CONFIG_TASKSTATS=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_CORE=y +# CONFIG_TCG_TIS_I2C is not set +CONFIG_TCG_TIS_I2C_ATMEL=m +# CONFIG_TCG_TIS_I2C_CR50 is not set +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI=y +# CONFIG_TCG_TIS_SPI_CR50 is not set +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_TCG_TPM=y +# CONFIG_TCG_TPM2_HMAC is not set +# CONFIG_TCG_VTPM_PROXY is not set +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +# CONFIG_TCM_QLA2XXX is not set +CONFIG_TCM_USER2=m +# CONFIG_TCP_AO is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +# CONFIG_TCP_CONG_CDG is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +CONFIG_TCP_SIGPOOL=y +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_TEST_LOCKUP is not set +# CONFIG_TEST_POWER is not set +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TH1520_AON_PROTOCOL=y +CONFIG_TH1520_PM_DOMAINS=m +CONFIG_THEAD_TH1520_MBOX=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_CORE_TESTING is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +# CONFIG_THERMAL_NETLINK is not set +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SIZE_ORDER=2 +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_THUNDER_NIC_VF=m +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIMERFD=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TIME_NS=y +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_SHARP_MEMORY is not set +CONFIG_TIPC=m +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_TI_FPC202 is not set +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_XATTR=y +CONFIG_TOOLCHAIN_HAS_V=y +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO=y +CONFIG_TOOLCHAIN_HAS_ZABHA=y +CONFIG_TOOLCHAIN_HAS_ZACAS=y +CONFIG_TOOLCHAIN_HAS_ZBA=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_TOOLCHAIN_HAS_ZBC=y +CONFIG_TOOLCHAIN_HAS_ZBKB=y +CONFIG_TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y +CONFIG_TRACEPOINTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_GPU_MEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_TRUSTED_KEYS=y +CONFIG_TRUSTED_KEYS_TPM=y +# CONFIG_TSNEP is not set +CONFIG_TTY=y +CONFIG_TTY_PRINTK=m +CONFIG_TTY_PRINTK_LEVEL=6 +CONFIG_TUN=m +CONFIG_TUNE_GENERIC=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_TXGBE=m +# CONFIG_TXGBEVF is not set +CONFIG_TYPEC=m +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_DP_ALTMODE=m +# CONFIG_TYPEC_FUSB302 is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_IT5205 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_PS883X is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set +# CONFIG_TYPEC_MUX_TUSB1046 is not set +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TBT_ALTMODE is not set +CONFIG_TYPEC_TCPCI=m +# CONFIG_TYPEC_TCPCI_MAXIM is not set +CONFIG_TYPEC_TCPM=m +# CONFIG_TYPEC_TPS6598X is not set +CONFIG_TYPEC_UCSI=m +# CONFIG_TYPEC_WUSB3801 is not set +CONFIG_UACCE=m +# CONFIG_UAPI_HEADER_TEST is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_UBSAN is not set +# CONFIG_UCLAMP_TASK is not set +CONFIG_UCS2_STRING=y +# CONFIG_UCSI_ACPI is not set +# CONFIG_UCSI_CCG is not set +# CONFIG_UCSI_STM32G0 is not set +CONFIG_UDF_FS=m +# CONFIG_UDMABUF is not set +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UFS_FS is not set +CONFIG_UHID=m +CONFIG_UIO=m +CONFIG_UIO_AEC=m CONFIG_UIO_CIF=m +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +CONFIG_UIO_PCI_GENERIC=m CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_AEC=m CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNION_FIND=y +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX_DIAG=m +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y +CONFIG_USB=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +CONFIG_USB4_NET=m +# CONFIG_USBIP_CORE is not set +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +# CONFIG_USB_AIRSPY is not set +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_BELKIN=y +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_CATC=m +# CONFIG_USB_CDNS_SUPPORT is not set +CONFIG_USB_CHAOSKEY=m +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_COMMON=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DWC2 is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_GENERIC_PLAT=m +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_PCI=m +# CONFIG_USB_DWC3_ULPI is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_HSIC_USB3503=m +# CONFIG_USB_HSIC_USB4604 is not set +CONFIG_USB_HSO=m +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_IPHETH=m +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1760 is not set +CONFIG_USB_KAWETH=m +CONFIG_USB_KC2190=y +# CONFIG_USB_KEENE is not set +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_LJCA is not set +# CONFIG_USB_MA901 is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y +# CONFIG_USB_MR800 is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_ONBOARD_DEV=m +# CONFIG_USB_ONBOARD_DEV_USB5744 is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set +CONFIG_USB_PEGASUS=m +CONFIG_USB_PRINTER=m +# CONFIG_USB_PWC is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +# CONFIG_USB_S2255 is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +# CONFIG_USB_SERIAL_UPD78F0730 is not set +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_WWAN=m +# CONFIG_USB_SERIAL_XR is not set +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEST is not set +CONFIG_USB_TMC=m +# CONFIG_USB_TRANCEVIBRATOR is not set +CONFIG_USB_UAS=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_USBNET=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_XHCI_RCAR=y +# CONFIG_USB_XHCI_SIDEBAND is not set +# CONFIG_USB_YUREX is not set +CONFIG_USERFAULTFD=y +# CONFIG_USERIO is not set +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USER_NS=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_UTS_NS=y +CONFIG_UVC_COMMON=m +CONFIG_V4L2_ASYNC=m +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L2_FWNODE=m +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +CONFIG_VALIDATE_FS_PARSER=y +# CONFIG_VCPU_STALL_DETECTOR is not set +# CONFIG_VDPA is not set +CONFIG_VDSO_GETRANDOM=y +CONFIG_VETH=m +CONFIG_VFAT_FS=y CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +CONFIG_VFIO_GROUP=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI=m -CONFIG_VIRT_DRIVERS=y -CONFIG_VIRTIO_PCI=y +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=64 +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST_VSOCK=m +CONFIG_VIDEO=y +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_ALVIUM_CSI2 is not set +# CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +# CONFIG_VIDEO_CADENCE_CSI2TX is not set +CONFIG_VIDEO_CAMERA_LENS=y +CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_DEV=m +# CONFIG_VIDEO_DS90UB913 is not set +# CONFIG_VIDEO_DS90UB953 is not set +# CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9719 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_ET8EK8 is not set +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC0310 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_HI846 is not set +# CONFIG_VIDEO_HI847 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX296 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_IMX415 is not set +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# CONFIG_VIDEO_LT6911UXE is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_OG01A1B is not set +# CONFIG_VIDEO_OG0VE1B is not set +# CONFIG_VIDEO_OV01A10 is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV02C10 is not set +# CONFIG_VIDEO_OV02E10 is not set +# CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV08X40 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_OV13B10 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV2735 is not set +# CONFIG_VIDEO_OV2740 is not set +# CONFIG_VIDEO_OV4689 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV6211 is not set +# CONFIG_VIDEO_OV64A40 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8858 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_RP1_CFE is not set +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_STK1160 is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THP7312 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VD55G1 is not set +# CONFIG_VIDEO_VD56G3 is not set +# CONFIG_VIDEO_VGXY61 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VIRTIO_FS=y CONFIG_VIRTIO_INPUT=y +# CONFIG_VIRTIO_MEM is not set +CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +# CONFIG_VIRTIO_PMEM is not set CONFIG_VIRTIO_RTC=m -CONFIG_VHOST_NET=m -CONFIG_VHOST_SCSI=m -CONFIG_VHOST_VSOCK=m -CONFIG_CLK_SOPHGO_SG2042_PLL=y -CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y -CONFIG_CLK_SOPHGO_SG2042_RPGATE=y -CONFIG_CLK_SOPHGO_SG2044=y -CONFIG_CLK_SOPHGO_SG2044_PLL=y -CONFIG_SPACEMIT_K1_CCU=y -CONFIG_SPACEMIT_K3_CCU=y -CONFIG_HWSPINLOCK=y -CONFIG_THEAD_TH1520_MBOX=y -CONFIG_IOMMU_DEFAULT_DMA_LAZY=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_CTRL=y -CONFIG_RPMSG_VIRTIO=y -CONFIG_SOPHGO_SG2044_TOPSYS=y -CONFIG_TH1520_PM_DOMAINS=m -CONFIG_EXTCON=y -CONFIG_EXTCON_GPIO=m -CONFIG_PWM=y -CONFIG_PWM_SIFIVE=m -CONFIG_PWM_SOPHGO_SG2042=m -CONFIG_PWM_TH1520=m -CONFIG_ACLINT_SSWI=y -CONFIG_SOPHGO_SG2042_MSI=y -CONFIG_RESET_TH1520=m -CONFIG_PHY_SPACEMIT_K1_USB2=m -CONFIG_PHY_SPACEMIT_K3_COMBO_PHY=m -CONFIG_USB4=m -CONFIG_DAX=y -CONFIG_DEV_DAX=m -CONFIG_NVMEM_SOPHGO_EFUSE=m -CONFIG_INTERCONNECT=y -CONFIG_VALIDATE_FS_PARSER=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y +CONFIG_VIRTIO_RTC_CLASS=y +CONFIG_VIRTIO_RTC_PTP=y +# CONFIG_VIRTIO_VFIO_PCI is not set +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_VIRTUALIZATION=y +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_VIRT_DRIVERS=y +# CONFIG_VIRT_WIFI is not set +CONFIG_VIRT_XFER_TO_GUEST_WORK=y +CONFIG_VITESSE_PHY=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_PFN=y +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_VMXNET3 is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKMON=m +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VXFS_FS is not set +CONFIG_VXLAN=m +# CONFIG_W1 is not set +CONFIG_WAN=y +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_WANXL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +# CONFIG_WATCH_QUEUE is not set +# CONFIG_WCN36XX is not set +# CONFIG_WDAT_WDT is not set +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +# CONFIG_WFX is not set +# CONFIG_WIL6210 is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIRELESS=y +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WPCM450_SOC is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WQ_WATCHDOG=y +# CONFIG_WWAN is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_X25 is not set +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_XARRAY_MULTI=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XFRM=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_IPCOMP=m +# CONFIG_XFRM_IPTFS is not set +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_USER=m +CONFIG_XFS_BTREE_IN_MEM=y +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_DRAIN_INTENTS=y CONFIG_XFS_FS=y -CONFIG_XFS_QUOTA=y +CONFIG_XFS_LIVE_HOOKS=y +CONFIG_XFS_MEMORY_BUFS=y +CONFIG_XFS_ONLINE_REPAIR=y +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_XFS_ONLINE_SCRUB_STATS=y CONFIG_XFS_POSIX_ACL=y -CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set -# CONFIG_OCFS2_DEBUG_MASKLOG is not set -CONFIG_BTRFS_FS=y -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_BTRFS_EXPERIMENTAL=y -CONFIG_F2FS_FS=m -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_FS_COMPRESSION=y -CONFIG_F2FS_UNFAIR_RWSEM=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_QFMT_V2=y -CONFIG_AUTOFS_FS=y -CONFIG_FUSE_FS=y -CONFIG_CUSE=m -CONFIG_VIRTIO_FS=y -CONFIG_OVERLAY_FS=m -CONFIG_NETFS_STATS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +# CONFIG_XFS_SUPPORT_ASCII_CI is not set +# CONFIG_XFS_SUPPORT_V4 is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_XILINX_INTC is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_VCU is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_XDMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_RISCV=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_XZ_DEC_X86=y +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZERO_CALL_USED_REGS is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -CONFIG_EXFAT_FS=y -CONFIG_NTFS3_LZX_XPRESS=y -CONFIG_NTFS3_FS_POSIX_ACL=y -CONFIG_NTFS_FS=m -CONFIG_PROC_KCORE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_EFIVAR_FS=y -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_PSTORE=y -CONFIG_PSTORE_RAM=m -CONFIG_EROFS_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V2=m -CONFIG_NFS_V3=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set -# CONFIG_NFS_V4_2_READ_PLUS is not set -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_BLOCKLAYOUT=y -CONFIG_NFSD_SCSILAYOUT=y -CONFIG_NFSD_FLEXFILELAYOUT=y -CONFIG_NFSD_V4_2_INTER_SSC=y -CONFIG_NFSD_V4_SECURITY_LABEL=y -CONFIG_RPCSEC_GSS_KRB5=m -CONFIG_SUNRPC_DEBUG=y -CONFIG_CEPH_FS=m -CONFIG_CEPH_FS_POSIX_ACL=y -CONFIG_CIFS=m -# CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_9P_FS=y -CONFIG_9P_FS_POSIX_ACL=y -CONFIG_9P_FS_SECURITY=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_NLS_UTF8=m -CONFIG_PERSISTENT_KEYRINGS=y -CONFIG_TRUSTED_KEYS=y -CONFIG_SECURITY=y -CONFIG_SECURITY_INFINIBAND=y -CONFIG_SECURITY_NETWORK_XFRM=y -CONFIG_LSM_MMAP_MIN_ADDR=32768 -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_APPARMOR=y -CONFIG_SECURITY_YAMA=y -CONFIG_SECURITY_LOCKDOWN_LSM=y -CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y -CONFIG_SECURITY_LANDLOCK=y -CONFIG_INTEGRITY_SIGNATURE=y -CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y -CONFIG_INTEGRITY_PLATFORM_KEYRING=y -CONFIG_IMA=y -CONFIG_IMA_DEFAULT_HASH_SHA256=y -CONFIG_IMA_READ_POLICY=y -CONFIG_IMA_APPRAISE=y -CONFIG_IMA_LOAD_X509=y -CONFIG_EVM=y -CONFIG_EVM_LOAD_X509=y -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" -CONFIG_INIT_STACK_NONE=y -CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y -CONFIG_FORTIFY_SOURCE=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_LIST_HARDENED=y -CONFIG_CRYPTO_USER=m -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_PCRYPT=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_ECDH=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_SM4_GENERIC=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SM3_GENERIC=y -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_CRC32=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZ4HC=m -CONFIG_CRYPTO_ZSTD=y -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_USER_API_SKCIPHER=y -CONFIG_CRYPTO_USER_API_RNG=y -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_CRYPTO_DEV_CHELSIO=m -CONFIG_CRYPTO_DEV_VIRTIO=y -CONFIG_SIGNED_PE_FILE_VERIFICATION=y -CONFIG_SECONDARY_TRUSTED_KEYRING=y -CONFIG_SYSTEM_BLACKLIST_KEYRING=y -CONFIG_SYSTEM_REVOCATION_LIST=y -CONFIG_CORDIC=m -CONFIG_CMA_SIZE_MBYTES=256 -CONFIG_DMA_MAP_BENCHMARK=y -CONFIG_PRINTK_TIME=y -CONFIG_PRINTK_CALLER=y -CONFIG_BOOT_PRINTK_DELAY=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_HEADERS_INSTALL=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_KGDB=y -CONFIG_KGDB_TESTS=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x0 -CONFIG_KDB_KEYBOARD=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_SOFTLOCKUP_DETECTOR=y -CONFIG_WQ_WATCHDOG=y -CONFIG_SCHEDSTATS=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_RCU_CPU_STALL_TIMEOUT=60 -# CONFIG_RCU_TRACE is not set -CONFIG_BOOTTIME_TRACING=y -CONFIG_FUNCTION_PROFILER=y -CONFIG_STACK_TRACER=y -CONFIG_SCHED_TRACER=y -CONFIG_HWLAT_TRACER=y -CONFIG_TIMERLAT_TRACER=y -CONFIG_FTRACE_SYSCALLS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_SYNTH_EVENTS=y -CONFIG_RING_BUFFER_BENCHMARK=m -CONFIG_SAMPLES=y -CONFIG_IO_STRICT_DEVMEM=y -# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_ZL3073X_I2C is not set +# CONFIG_ZL3073X_SPI is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZONEFS_FS is not set +CONFIG_ZONE_DEVICE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZRAM=m +# CONFIG_ZRAM_BACKEND_842 is not set +# CONFIG_ZRAM_BACKEND_DEFLATE is not set +CONFIG_ZRAM_BACKEND_FORCE_LZO=y +# CONFIG_ZRAM_BACKEND_LZ4 is not set +# CONFIG_ZRAM_BACKEND_LZ4HC is not set +CONFIG_ZRAM_BACKEND_LZO=y +# CONFIG_ZRAM_BACKEND_ZSTD is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC=y +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +CONFIG_ZSMALLOC_STAT=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lz4" +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set diff --git a/SPECS/linux-lts-kmhv2/config.riscv64-rva20 b/SPECS/linux-lts-kmhv2/config.riscv64-rva20 new file mode 100644 index 0000000000..8376eaad74 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/config.riscv64-rva20 @@ -0,0 +1,7207 @@ +CONFIG_ERRATA_THEAD_GHOSTWRITE=y +CONFIG_ERRATA_THEAD_WRITE_ONCE=y +CONFIG_64BIT=y +# CONFIG_6LOWPAN is not set +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_9P_FS=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +# CONFIG_ACCESSIBILITY is not set +CONFIG_ACLINT_SSWI=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI=y +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +# CONFIG_ACPI_BGRT is not set +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_DEBUG=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_DOCK=y +# CONFIG_ACPI_EC is not set +CONFIG_ACPI_FAN=y +CONFIG_ACPI_FFH=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +# CONFIG_ACPI_HOTPLUG_MEMORY is not set +CONFIG_ACPI_I2C_OPREGION=y +# CONFIG_ACPI_IPMI is not set +CONFIG_ACPI_MCFG=y +CONFIG_ACPI_MDIO=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NHLT=y +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PPTT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ACPI_RIMT=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_TABLE_LIB=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_THERMAL_LIB=y +CONFIG_ACPI_VIDEO=m +# CONFIG_AD525X_DPOT is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIN1100_PHY is not set +# CONFIG_ADIN1110 is not set +# CONFIG_ADIN_PHY is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_KCM is not set +# CONFIG_AF_RXRPC is not set +CONFIG_AF_UNIX_OOB=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_DWC is not set +# CONFIG_AHCI_SUNXI is not set +CONFIG_AIO=y +# CONFIG_AIR_EN8811H_PHY is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_ALIM7101_WDT=m +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ALTERA_MSGDMA is not set +CONFIG_ALTERA_STAPL=m +# CONFIG_ALTERA_TSE is not set +CONFIG_ALX=m +# CONFIG_AL_FIC is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_AMD8111_ETH is not set +CONFIG_AMD_PHY=m +# CONFIG_AMD_QDMA is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMT is not set +CONFIG_ANDES_CUSTOM_PMU=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_ANDROID_BINDER_IPC_RUST is not set +# CONFIG_ANON_VMA_NAME is not set +CONFIG_APDS9802ALS=m +CONFIG_APERTURE_HELPERS=y +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_APPLICOM is not set +# CONFIG_AQTION is not set +CONFIG_AQUANTIA_PHY=m +# CONFIG_AR5523 is not set +CONFIG_ARCH_ANDES=y +CONFIG_ARCH_CANAAN=y +CONFIG_ARCH_CC_CAN_LINK=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_ARCH_ESWIN=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_CC_CAN_LINK=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_ELF_CORE_EFLAGS=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD=y +CONFIG_ARCH_HAS_PTDUMP=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAS_UBSAN=y +CONFIG_ARCH_HAS_VDSO_ARCH_DATA=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECTS_KEXEC=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SIFIVE=y +CONFIG_ARCH_SOPHGO=y +CONFIG_ARCH_SPACEMIT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_STARFIVE=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_CFI=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_RT=y +CONFIG_ARCH_SUPPORTS_SCHED_MC=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_THEAD=y +CONFIG_ARCH_ULTRARISC=y +CONFIG_ARCH_USERFLAGS="-march=rv64g -mabi=lp64d" +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +CONFIG_ARCH_VIRT=y +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y +# CONFIG_ARCNET is not set +CONFIG_ARM_AMBA=y +# CONFIG_ARM_HISI_UNCORE_DEVFREQ is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set +# CONFIG_AS21XXX_PHY is not set +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASN1_ENCODER=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_ASYNC_XOR=m +CONFIG_AS_HAS_INSN=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_AS_HAS_OPTION_ARCH=y +CONFIG_AS_HAS_ULEB128=y +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24690 +CONFIG_AT803X_PHY=m +CONFIG_ATA=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=m +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=m +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATH10K=m +# CONFIG_ATH10K_AHB is not set +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +CONFIG_ATH10K_LEDS=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_TRACING is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH11K is not set +# CONFIG_ATH12K is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_AT_XDMAC is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUTOFS_FS=y +CONFIG_AUXDISPLAY=y +CONFIG_AUXILIARY_BUS=y +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_AX88796B_PHY=m +# CONFIG_B44 is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_BD6107 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=m +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +# CONFIG_BACKLIGHT_LED is not set +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_MP3309C is not set +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BALLOON_COMPACTION=y +# CONFIG_BAREUDP is not set +# CONFIG_BASE_SMALL is not set +CONFIG_BASIC_MODVERSIONS=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_CHAGALL is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_UG3105 is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA=m +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_NET_PHYPTP=m +# CONFIG_BCM_VK is not set +CONFIG_BE2ISCSI=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFQ_CGROUP_DEBUG is not set +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFS_FS is not set +# CONFIG_BIG_KEYS is not set +CONFIG_BINARY_PRINTF=y +CONFIG_BINDGEN_VERSION_TEXT="bindgen 0.72.1" +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +CONFIG_BLK_CGROUP=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_DM=m +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_RUST_NULL is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_DEV_ZONED_LOOP is not set +CONFIG_BLK_ICQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BLK_MQ_STACKING=y +CONFIG_BLK_PM=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +# CONFIG_BNGE is not set +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +# CONFIG_BNXT_HWMON is not set +CONFIG_BNXT_SRIOV=y +CONFIG_BONDING=m +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTTIME_TRACING=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BPF=y +CONFIG_BPF_EVENTS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPF_LSM is not set +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_STREAM_PARSER=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +CONFIG_BRIDGE=m +# CONFIG_BRIDGE_CFM is not set +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_BT is not set +CONFIG_BTREE=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +CONFIG_BTRFS_EXPERIMENTAL=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTT=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUG=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +CONFIG_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_BUILD_SALT="" +# CONFIG_C2PORT is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_CAIF=y +# CONFIG_CAIF_DEBUG is not set +# CONFIG_CAIF_DRIVERS is not set +CONFIG_CAIF_NETDEV=y +# CONFIG_CAIF_USB is not set +CONFIG_CAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_C_CAN_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +# CONFIG_CAN_ESD_USB is not set +# CONFIG_CAN_ETAS_ES58X is not set +# CONFIG_CAN_F81601 is not set +# CONFIG_CAN_F81604 is not set +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_GS_USB is not set +CONFIG_CAN_GW=m +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_ISOTP is not set +# CONFIG_CAN_J1939 is not set +CONFIG_CAN_KVASER_PCI=m +# CONFIG_CAN_KVASER_PCIEFD is not set +CONFIG_CAN_KVASER_USB=m +# CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# CONFIG_CAN_M_CAN is not set +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +# CONFIG_CAN_PEAK_PCIEFD is not set +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_RAW=m +# CONFIG_CAN_RCAR is not set +# CONFIG_CAN_RCAR_CANFD is not set +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SOFTING=m +# CONFIG_CAN_SUN4I is not set +# CONFIG_CAN_UCAN is not set +CONFIG_CAN_VCAN=m +# CONFIG_CAN_VXCAN is not set +# CONFIG_CARL9170 is not set +CONFIG_CAVIUM_PTP=y +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_ASSUME=y +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_IS_GCC=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (Debian 15.3.0-1) 15.3.0" +CONFIG_CDROM=y +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +# CONFIG_CGROUP_DMEM is not set +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_WRITEBACK=y +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_MAX8971 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_RT9467 is not set +# CONFIG_CHARGER_RT9471 is not set +# CONFIG_CHARGER_SBS is not set +CONFIG_CHARGER_SMB347=m +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_LIB=m +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +# CONFIG_CHELSIO_T4_DCB is not set +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_ST=m +CONFIG_CICADA_PHY=m +CONFIG_CIFS=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_COMPRESSION is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_SWN_UPCALL is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CLANG_VERSION=0 +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set +CONFIG_CLK_RENESAS=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +# CONFIG_CLK_SOPHGO_CV1800 is not set +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y +CONFIG_CLK_SOPHGO_SG2044=y +CONFIG_CLK_SOPHGO_SG2044_PLL=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7110_AON=m +CONFIG_CLK_STARFIVE_JH7110_ISP=m +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_STG=m +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=m +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_THEAD_TH1520_AP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLOSURES=y +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=19 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CNIC=m +# CONFIG_CODA_FS is not set +# CONFIG_COMEDI is not set +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_RPMI=y +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_VC3 is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT is not set +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_CONSOLE_POLL=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTEXT_TRACKING_USER=y +# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set +CONFIG_CONTIG_ALLOC=y +CONFIG_CORDIC=m +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_CORTINA_PHY is not set +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_CPUFREQ_DT_RUST is not set +# CONFIG_CPUFREQ_VIRT is not set +CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set +# CONFIG_CRASH_DM_CRYPT is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_CRC32_ARCH=y +CONFIG_CRC64=y +CONFIG_CRC64_ARCH=y +CONFIG_CRC7=y +CONFIG_CRC8=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_OPTIMIZATIONS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_T10DIF_ARCH=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_BENCHMARK is not set +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DEV_ALLWINNER=y +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_QAT_420XX is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_SUN4I_SS is not set +# CONFIG_CRYPTO_DEV_SUN8I_CE is not set +# CONFIG_CRYPTO_DEV_SUN8I_SS is not set +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set +CONFIG_CRYPTO_ECHAINIV=m +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_HCTR2 is not set +CONFIG_CRYPTO_HKDF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_KRB5 is not set +# CONFIG_CRYPTO_KRB5ENC is not set +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_MD5=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_ARCH=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SHA512=y +CONFIG_CRYPTO_LIB_SM3=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4=y +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SELFTESTS is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_SM3_GENERIC=y +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_RNG=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=y +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +# CONFIG_CV1800_MBOX is not set +CONFIG_CXD2880_SPI_DRV=m +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=y +# CONFIG_CXL_FEATURES is not set +CONFIG_CXL_MEM=y +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=y +CONFIG_CXL_PMEM=m +# CONFIG_CXL_PMU is not set +CONFIG_CXL_PORT=y +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_SUSPEND=y +CONFIG_DA9063_WATCHDOG=m +CONFIG_DAMON=y +CONFIG_DAMON_LRU_SORT=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_STAT=y +CONFIG_DAMON_STAT_ENABLED_DEFAULT=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y +CONFIG_DCB=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NET_SMALL_RTNL is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_PERF_USE_VMALLOC=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_VFS is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_ZSTD=y +# CONFIG_DEFAULT_CODEL is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_FQ is not set +CONFIG_DEFAULT_FQ_CODEL=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_DEFAULT_NET_SCH="fq_codel" +# CONFIG_DEFAULT_PFIFO_FAST is not set +# CONFIG_DEFAULT_RENO is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SFQ is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DETECT_HUNG_TASK_BLOCKER=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVICE_MIGRATION=y +CONFIG_DEVICE_PRIVATE=y +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +CONFIG_DEV_DAX_HMEM_DEVICES=y +CONFIG_DEV_DAX_KMEM=m +CONFIG_DEV_DAX_PMEM=m +# CONFIG_DIBS is not set +CONFIG_DIMLIB=y +# CONFIG_DLM is not set +# CONFIG_DM9051 is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMAPOOL_TEST is not set +# CONFIG_DMATEST is not set +CONFIG_DMA_ACPI=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_CMA=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_MAP_BENCHMARK=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_NONCOHERENT_MMAP=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_OF=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_SUN6I is not set +CONFIG_DMI=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DM_AUDIT=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_BUFIO=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +# CONFIG_DM_CLONE is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_DEBUG=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_DUST is not set +# CONFIG_DM_EBS is not set +CONFIG_DM_ERA=m +CONFIG_DM_FLAKEY=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=m +CONFIG_DM_MULTIPATH=m +# CONFIG_DM_MULTIPATH_HST is not set +# CONFIG_DM_MULTIPATH_IOA is not set +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_PCACHE is not set +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_SWITCH=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_VDO=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_FEC is not set +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +# CONFIG_DM_WRITECACHE is not set +CONFIG_DM_ZERO=m +# CONFIG_DM_ZONED is not set +CONFIG_DNET=m +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=y +CONFIG_DP83640_PHY=m +# CONFIG_DP83822_PHY is not set +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +# CONFIG_DP83869_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set +CONFIG_DPLL=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRM=y +# CONFIG_DRM_ACCEL is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ACP is not set +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_FP=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DRM_AMD_ISP is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BRIDGE_CONNECTOR=y +CONFIG_DRM_BUDDY=m +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_CLIENT=y +CONFIG_DRM_CLIENT_DEFAULT="fbdev" +CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y +CONFIG_DRM_CLIENT_LIB=y +# CONFIG_DRM_CLIENT_LOG is not set +CONFIG_DRM_CLIENT_SELECTION=y +CONFIG_DRM_CLIENT_SETUP=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_DP_TUNNEL=y +CONFIG_DRM_DISPLAY_DSC_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DW_HDMI=m +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +# CONFIG_DRM_DW_HDMI_CEC is not set +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_EXEC=m +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=y +# CONFIG_DRM_GM12U320 is not set +CONFIG_DRM_GPUSVM=m +CONFIG_DRM_GPUVM=m +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_ITE_IT6263 is not set +# CONFIG_DRM_ITE_IT6505 is not set +# CONFIG_DRM_ITE_IT66121 is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_KOMEDA is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LOGICVC is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MGAG200=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_CH7006=m +CONFIG_DRM_NOUVEAU_SIL164=m +# CONFIG_DRM_NOVA is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS=m +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TD4320 is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112B is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_HYDIS_HV101HD1 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_RENESAS_R61307 is not set +# CONFIG_DRM_PANEL_RENESAS_R69328 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_SUMMIT is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# CONFIG_DRM_PANIC is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_PIXPAPER is not set +# CONFIG_DRM_POWERVR is not set +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_SAMSUNG_DSIM is not set +CONFIG_DRM_SCHED=m +# CONFIG_DRM_SHMOBILE is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIL_SII8620 is not set +CONFIG_DRM_SIMPLEDRM=y +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_SOLOMON_SSD2825 is not set +# CONFIG_DRM_SSD130X is not set +# CONFIG_DRM_ST7571_I2C is not set +# CONFIG_DRM_ST7586 is not set +# CONFIG_DRM_ST7735R is not set +CONFIG_DRM_SUBALLOC_HELPER=m +# CONFIG_DRM_SUN4I is not set +CONFIG_DRM_SYSFB_HELPER=y +CONFIG_DRM_THEAD_TH1520_DW_HDMI=m +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TI_DLPC3433 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TDP158 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VERISILICON_DC=m +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_WAVESHARE_BRIDGE is not set +# CONFIG_DRM_WERROR is not set +CONFIG_DRM_XE=m +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_MEMIRQ is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_DP_TUNNEL=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_GPUSVM=y +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +CONFIG_DRM_XE_PAGEMAP=y +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +# CONFIG_DS1682 is not set +CONFIG_DST_CACHE=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY=m +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_DUMMY_IRQ is not set +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m +# CONFIG_DVB_AS102 is not set +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_CXD2099=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_CXD2880=m +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_DRXK=m +CONFIG_DVB_DS3000=m +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_EC100=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_L64781=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MB86A20S=m +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_MN88443X=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_MT312=m +CONFIG_DVB_MT352=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_MXL692=m +# CONFIG_DVB_NET is not set +CONFIG_DVB_NXT200X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +# CONFIG_DVB_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLL=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_S921=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_SP2=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0297=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_TC90522=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TS2020=m +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_ULE_DEBUG is not set +# CONFIG_DVB_USB_V2 is not set +CONFIG_DVB_VES1820=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_ZL10353=m +# CONFIG_DWC_PCIE_PMU is not set +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_RENESAS_GBETH=m +CONFIG_DWMAC_SOPHGO=m +CONFIG_DWMAC_SPACEMIT=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_SUN55I=m +CONFIG_DWMAC_SUN8I=m +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_THEAD=m +# CONFIG_DW_AXI_DMAC is not set +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC_PCI=m +# CONFIG_DW_EDMA is not set +CONFIG_DW_WATCHDOG=m +# CONFIG_DW_XDATA_PCIE is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_SIGFRAME=y +# CONFIG_E100 is not set +CONFIG_E1000=m +CONFIG_E1000E=y +# CONFIG_ECRYPT_FS is not set +CONFIG_EDAC=y +# CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_ECS is not set +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_MEM_REPAIR is not set +# CONFIG_EDAC_SCRUB is not set +CONFIG_EDAC_SIFIVE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_M24LR is not set +CONFIG_EEPROM_MAX6875=m +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +# CONFIG_EFI_ZBOOT is not set +# CONFIG_EFS_FS is not set +CONFIG_ELFCORE=y +CONFIG_ELF_CORE=y +CONFIG_ENA_ETHERNET=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_EPIC100=m +CONFIG_EPOLL=y +CONFIG_EPROBE_EVENTS=y +CONFIG_EQUALIZER=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_BACKED_BY_FILE=y +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ACCEL is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +# CONFIG_EROFS_FS_ZIP_LZMA is not set +# CONFIG_EROFS_FS_ZIP_ZSTD is not set +CONFIG_ERRATA_ANDES=y +CONFIG_ERRATA_MIPS=y +CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_MAE=y +CONFIG_ERRATA_THEAD_PMU=y +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_EVENTFD=y +CONFIG_EVENT_TRACING=y +CONFIG_EVM=y +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +CONFIG_EVM_LOAD_X509=y +CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=y +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXTCON=y +# CONFIG_EXTCON_FSA9480 is not set +CONFIG_EXTCON_GPIO=m +# CONFIG_EXTCON_LC824206XA is not set +# CONFIG_EXTCON_MAX14526 is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTENDED_MODVERSIONS=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +# CONFIG_FARSYNC is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_FB=y +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_CARMINE is not set +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CIRRUS is not set +CONFIG_FB_CORE=y +# CONFIG_FB_CYBER2000 is not set +CONFIG_FB_DDC=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +# CONFIG_FB_KYRO is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_NEOMAGIC is not set +CONFIG_FB_NOTIFY=y +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_RADEON_I2C=y +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_SSD1307=m +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +CONFIG_FCOE=m +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +CONFIG_FHANDLE=y +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_FIRMWARE_TABLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FM10K=m +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_FPGA is not set +# CONFIG_FPROBE is not set +CONFIG_FPU=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMER is not set +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +# CONFIG_FSCACHE is not set +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_DAX is not set +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +# CONFIG_FS_VERITY is not set +# CONFIG_FTL is not set +CONFIG_FTRACE=y +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set +# CONFIG_FUEL_GAUGE_STC3117 is not set +# CONFIG_FUJITSU_ES is not set +CONFIG_FUNCTION_ALIGNMENT=8 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ALIGNMENT_8B=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FUNCTION_GRAPH_RETADDR is not set +# CONFIG_FUNCTION_GRAPH_RETVAL is not set +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_TRACE_ARGS=y +# CONFIG_FUN_ETH is not set +CONFIG_FUSE_FS=y +CONFIG_FUSE_IO_URING=y +CONFIG_FUSE_PASSTHROUGH=y +# CONFIG_FUSION is not set +CONFIG_FUTEX=y +CONFIG_FUTEX_MPOL=y +CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y +# CONFIG_FWCTL is not set +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_FW_UPLOAD=y +CONFIG_GACT_PROB=y +# CONFIG_GAMEPORT is not set +CONFIG_GARP=m +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_GCC_VERSION=150300 +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_GENDWARFKSYMS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_NUMA=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_ENTRY=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_SYSCALL=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_TRACER=y +CONFIG_GENEVE=m +# CONFIG_GENKSYMS is not set +# CONFIG_GENWQE is not set +CONFIG_GET_FREE_REGION=y +# CONFIG_GFS2_FS is not set +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GNSS is not set +CONFIG_GOLDFISH=y +# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH_TTY is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIOLIB_LEGACY=y +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +CONFIG_GPIO_ACPI=y +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_BT8XX is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +# CONFIG_GPIO_DS4520 is not set +CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_FXL6408 is not set +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=m +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPSSE is not set +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_POLARFIRE_SOC is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_SIM is not set +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +CONFIG_GPIO_SPACEMIT_K1=y +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SYSFS_LEGACY=y +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set +CONFIG_GPIO_WATCHDOG=m +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_GP_PCI1XXXX is not set +CONFIG_GRACE_PERIOD=y +# CONFIG_GREENASIA_FF is not set +# CONFIG_GREYBUS is not set +CONFIG_GROUP_SCHED_BANDWIDTH=y +CONFIG_GROUP_SCHED_WEIGHT=y +CONFIG_GRO_CELLS=y +# CONFIG_GTP is not set +CONFIG_GUEST_PERF_EVENTS=y +# CONFIG_GUP_TEST is not set +# CONFIG_HAMRADIO is not set +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_DEFAULT_ON=y +CONFIG_HARDIRQS_SW_RESEND=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_SECURITY_AUDIT=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_HAVE_ARCH_KFENCE=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_HAVE_ARCH_KSTACK_ERASE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_GRAPH_FUNC=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_TIF_BITS=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_GIGANTIC_FOLIOS=y +CONFIG_HAVE_GUP_FAST=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_UNCOMPRESSED=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KVM_DIRTY_RING=y +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_READONLY_MEM=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_TRUSTED_KEYS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HD44780 is not set +CONFIG_HDLC=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_RAW=m +# CONFIG_HDLC_RAW_ETH is not set +CONFIG_HDMI=y +CONFIG_HEADERS_INSTALL=y +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFS_FS is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_DEF_COMP="lzo" +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +# CONFIG_HIBMCGE is not set +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +CONFIG_HID_ACRUX=m +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_ALPS is not set +CONFIG_HID_APPLE=y +CONFIG_HID_APPLEIR=m +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BETOP_FF=m +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_BPF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CORSAIR=m +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=m +# CONFIG_HID_ELAN is not set +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EVISION is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=y +CONFIG_HID_GFRM=m +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_GOODIX_SPI is not set +# CONFIG_HID_GOOGLE_STADIA_FF is not set +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +# CONFIG_HID_HAPTIC is not set +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=y +# CONFIG_HID_JABRA is not set +CONFIG_HID_KENSINGTON=y +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +# CONFIG_HID_KYSONA is not set +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +# CONFIG_HID_MACALLY is not set +CONFIG_HID_MAGICMOUSE=y +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MCP2200 is not set +# CONFIG_HID_MCP2221 is not set +# CONFIG_HID_MEGAWORLD_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=m +# CONFIG_HID_NINTENDO is not set +# CONFIG_HID_NTI is not set +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_RETRODE is not set +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_SENSOR_HUB=m +# CONFIG_HID_SIGMAMICRO is not set +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +# CONFIG_HID_STEAM is not set +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +# CONFIG_HID_TOPRE is not set +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +# CONFIG_HID_U2FZERO is not set +CONFIG_HID_UCLOGIC=m +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_UNIVERSAL_PIDFF is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_VRC2 is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set +# CONFIG_HID_XIAOMI is not set +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_HMC6352 is not set +CONFIG_HMEM_REPORTING=y +CONFIG_HMM_MIRROR=y +# CONFIG_HOLTEK_FF is not set +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_OCTEONEP is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +# CONFIG_HPFS_FS is not set +# CONFIG_HP_ILO is not set +CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HT16K33 is not set +# CONFIG_HTE is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HVC_DRIVER=y +CONFIG_HWLAT_TRACER=y +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON_VID=m +CONFIG_HWSPINLOCK=y +# CONFIG_HWSPINLOCK_SUN6I is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_JH7110 is not set +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=m +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +# CONFIG_I2C_AT91 is not set +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DIOLAN_U2C=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_CORE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +CONFIG_I2C_K1=m +# CONFIG_I2C_MICROCHIP_CORE is not set +CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_GPIO=m +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_MULE is not set +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MV64XXX is not set +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_NVIDIA_GPU is not set +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RIIC is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_RZV2M is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_STUB=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VIRTIO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2C_ZHAOXIN is not set +# CONFIG_I3C is not set +CONFIG_I40E=m +CONFIG_I40EVF=m +# CONFIG_I40E_DCB is not set +CONFIG_I6300ESB_WDT=m +CONFIG_IAVF=m +CONFIG_ICE=m +CONFIG_ICE_HWMON=y +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICPLUS_PHY=m +# CONFIG_ICS932S401 is not set +CONFIG_IDLE_PAGE_TRACKING=y +# CONFIG_IDPF is not set +# CONFIG_IEEE802154 is not set +CONFIG_IFB=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGB_HWMON=y +# CONFIG_IGC is not set +# CONFIG_IIO is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMA=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +# CONFIG_IMA_APPRAISE_MODSIG is not set +# CONFIG_IMA_APPRAISE_SIGNED_INIT is not set +# CONFIG_IMA_ARCH_POLICY is not set +# CONFIG_IMA_BLACKLIST_KEYRING is not set +CONFIG_IMA_DEFAULT_HASH="sha256" +# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set +CONFIG_IMA_DEFAULT_HASH_SHA256=y +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +# CONFIG_IMA_DEFAULT_HASH_SM3 is not set +CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" +# CONFIG_IMA_DISABLE_HTABLE is not set +# CONFIG_IMA_KEXEC is not set +# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set +CONFIG_IMA_LOAD_X509=y +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y +CONFIG_IMA_READ_POLICY=y +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_WRITE_POLICY is not set +CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_INET=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=m +# CONFIG_INET_PSP is not set +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_SCTP_DIAG=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +# CONFIG_INFINIBAND_EFA is not set +# CONFIG_INFINIBAND_ERDMA is not set +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +# CONFIG_INFINIBAND_MTHCA is not set +# CONFIG_INFINIBAND_OCRDMA is not set +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_RTRS_CLIENT is not set +# CONFIG_INFINIBAND_RTRS_SERVER is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_VIRT_DMA=y +# CONFIG_INFTL is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_STACK_NONE=y +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_AW86927 is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_DA9063_ONKEY is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_IBM_PANEL is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_VIVALDIFMAP=y +# CONFIG_INPUT_YEALINK is not set +CONFIG_INTEGRITY=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_INTEGRITY_MACHINE_KEYRING is not set +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_TH is not set +# CONFIG_INTEL_XWAY_PHY is not set +CONFIG_INTERCONNECT=y +CONFIG_INTERVAL_TREE=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IONIC is not set +CONFIG_IOSCHED_BFQ=y +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IO_URING_MOCK_FILE is not set +CONFIG_IO_URING_ZCRX=y +CONFIG_IO_WQ=y +# CONFIG_IP5XXX_POWER is not set +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_MATCH_SRH is not set +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +# CONFIG_IPACK_BUS is not set +CONFIG_IPC_NS=y +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_IPMB is not set +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPV6=y +CONFIG_IPV6_GRE=m +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +# CONFIG_IPV6_SUBTREES is not set +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPVLAN=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVTAP=m +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +# CONFIG_IP_SET_HASH_IPMAC is not set +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +# CONFIG_IP_VS_MH is not set +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +# CONFIG_IP_VS_TWOS is not set +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IRQCHIP=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TCP=m +# CONFIG_ISDN is not set +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_ISO9660_FS=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_JH71XX_PMU=y +# CONFIG_JME is not set +CONFIG_JOLIET=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KARMA_PARTITION=y +# CONFIG_KASAN is not set +CONFIG_KCMP=y +# CONFIG_KCOV is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x0 +CONFIG_KDB_KEYBOARD=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_UNCOMPRESSED=y +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KERNFS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_ELF=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_KEY_DH_OPERATIONS is not set +CONFIG_KFENCE=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=100 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +CONFIG_KGDB_TESTS=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +CONFIG_KPROBES=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_KSM=y +# CONFIG_KUNIT is not set +CONFIG_KVFREE_RCU_BATCHED=y +CONFIG_KVM=m +CONFIG_KVM_COMMON=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_KVM_GENERIC_MMU_NOTIFIER=y +CONFIG_KVM_MMIO=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP_V3=y +# CONFIG_LAPB is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LCD2S is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_PARTITION is not set +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set +CONFIG_LD_IS_BFD=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_LD_VERSION=24690 +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_AW200XX is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_BLINKM=m +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3601X is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3697 is not set +CONFIG_LEDS_LP3944=m +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LP8864 is not set +CONFIG_LEDS_LT3593=m +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_ST1202 is not set +# CONFIG_LEDS_SY7802 is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_TPS6131X is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +CONFIG_LEDS_TRIGGER_ONESHOT=m +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +# CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LIBETH=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y +CONFIG_LIBIE=m +CONFIG_LIBIE_ADMINQ=m +CONFIG_LIBIE_FWLOG=m +CONFIG_LIBNVDIMM=m +CONFIG_LIBWX=m +CONFIG_LINEAR_RANGES=y +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_CORE=m +CONFIG_LIQUIDIO_VF=m +CONFIG_LIST_HARDENED=y +# CONFIG_LITEX_LITEETH is not set +# CONFIG_LITEX_SOC_CONTROLLER is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +CONFIG_LLD_VERSION=0 +# CONFIG_LMK04832 is not set +CONFIG_LOAD_UEFI_KEYS=y +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKD=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=20 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOOPBACK_TARGET=m +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +CONFIG_LRU_CACHE=m +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" +CONFIG_LSM_MMAP_MIN_ADDR=32768 +CONFIG_LTO_NONE=y +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_LXT_PHY=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211=m +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_HWSIM is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +# CONFIG_MAC_PARTITION is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +# CONFIG_MANAGER_SBS is not set +CONFIG_MARVELL_10G_PHY=m +# CONFIG_MARVELL_88Q2XXX_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +CONFIG_MARVELL_PHY=m +# CONFIG_MAX31827 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX6959 is not set +# CONFIG_MAXLINEAR_86110_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +CONFIG_MAX_SKB_FRAGS=17 +# CONFIG_MCB is not set +CONFIG_MCHP_CLK_MPFS=y +# CONFIG_MCHP_LAN966X_PCI is not set +# CONFIG_MCHP_SBI_IPC_MBOX is not set +# CONFIG_MCTP is not set +CONFIG_MD=y +CONFIG_MDIO=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_MVUSB is not set +CONFIG_MDIO_OCTEON=m +# CONFIG_MDIO_SUN4I is not set +CONFIG_MDIO_THUNDER=m +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP=y +CONFIG_MD_BITMAP_FILE=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_LLBITMAP is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MEDIATEK_GE_PHY is not set +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +CONFIG_MEGARAID_SAS=m +CONFIG_MEMBARRIER=y +CONFIG_MEMCG=y +# CONFIG_MEMCG_V1 is not set +CONFIG_MEMFD_CREATE=y +# CONFIG_MEMORY is not set +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMREGION=y +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +# CONFIG_MEMSTICK_REALTEK_USB is not set +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +# CONFIG_MEMTEST is not set +# CONFIG_MEM_ALLOC_PROFILING is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_ADP5585 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_AT91_USART is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_BQ257XX is not set +CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +CONFIG_MFD_DA9063=m +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_LS2K_BMC_CORE is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX5970 is not set +# CONFIG_MFD_MAX7360 is not set +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77705 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77759 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_NCT6694 is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_SEC_I2C is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMPRO is not set +CONFIG_MFD_SPACEMIT_P1=m +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_SUN4I_GPADC is not set +# CONFIG_MFD_SUN6I_PRCM is not set +# CONFIG_MFD_SY7636A is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE is not set +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set +CONFIG_MHP_MEMMAP_ON_MEMORY=y +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1S_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROSEMI_PHY=m +CONFIG_MIGRATION=y +CONFIG_MII=m +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_MIN_HEAP=y +# CONFIG_MISC_ALCOR_PCI is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISC_RP1 is not set +CONFIG_MISC_RTSX=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MLX4_CORE=m +# CONFIG_MLX4_CORE_GEN2 is not set +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_DPLL is not set +CONFIG_MLX5_EN_ARFS=y +# CONFIG_MLX5_EN_IPSEC is not set +CONFIG_MLX5_EN_RXNFC=y +# CONFIG_MLX5_EN_TLS is not set +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_HW_STEERING=y +CONFIG_MLX5_INFINIBAND=m +# CONFIG_MLX5_MACSEC is not set +CONFIG_MLX5_MPFS=y +# CONFIG_MLX5_SF is not set +CONFIG_MLX5_SW_STEERING=y +# CONFIG_MLX5_VFIO_PCI is not set +CONFIG_MLXFW=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +# CONFIG_MLXSW_SPECTRUM is not set +CONFIG_MMC=y +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=y +CONFIG_MMC_CRYPTO=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_BLUEFIELD=m +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_MTK=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_ACPI is not set +CONFIG_MMC_SDHCI_CADENCE=y +# CONFIG_MMC_SDHCI_F_SDH30 is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_OF_K1=m +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_UHS2=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHI is not set +# CONFIG_MMC_SH_MMCIF is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_SUNXI is not set +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_TOSHIBA_PCI=m +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMIOWB=y +CONFIG_MMP_PDMA=m +CONFIG_MMU=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MM_ID=y +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ALL=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_DECOMPRESS=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULE_SIG_HASH="sha256" +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_SHA1 is not set +CONFIG_MODULE_SIG_SHA256=y +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +# CONFIG_MOST is not set +# CONFIG_MOTORCOMM_PHY is not set +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXTET is not set +CONFIG_MPILIB=y +CONFIG_MPLS=y +# CONFIG_MPLS_ROUTING is not set +CONFIG_MPTCP=y +CONFIG_MPTCP_IPV6=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_MRP=m +# CONFIG_MSCC_OCELOT_SWITCH is not set +CONFIG_MSDOS_FS=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSE102X is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set +CONFIG_MTD=m +# CONFIG_MTD_ABSENT is not set +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +# CONFIG_MTD_BLOCK_RO is not set +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CMDLINE_PARTS=m +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD_INTEL_DG is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PHRAM is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_NVMEM is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTIUSER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MYRI10GE is not set +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +# CONFIG_NCN26000_PHY is not set +CONFIG_ND_BTT=m +CONFIG_ND_CLAIM=y +CONFIG_ND_PFN=m +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET=y +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVSIM is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XTABLES_LEGACY is not set +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_NETFILTER_XT_NAT is not set +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +# CONFIG_NETFILTER_XT_TARGET_HL is not set +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_MASQUERADE is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +# CONFIG_NETFS_DEBUG is not set +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETKIT is not set +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=y +CONFIG_NETPOLL=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETXEN_NIC=m +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +# CONFIG_NET_9P_RDMA is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_ACT_BPF=m +# CONFIG_NET_ACT_CONNMARK is not set +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_GACT=m +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_ACT_IFE is not set +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CORE=y +CONFIG_NET_CRC32C=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NET_DROP_MONITOR=m +# CONFIG_NET_DSA is not set +CONFIG_NET_EGRESS=y +CONFIG_NET_EMATCH=y +# CONFIG_NET_EMATCH_CANID is not set +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_FAILOVER=y +CONFIG_NET_FC=y +CONFIG_NET_FLOW_LIMIT=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_NET_HANDSHAKE=y +# CONFIG_NET_IFE is not set +CONFIG_NET_INGRESS=y +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_NET_NCSI is not set +CONFIG_NET_NS=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_REDIRECT=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_BPF is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_CBS is not set +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_DEFAULT=y +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_DUALPI2 is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_ETS is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_CODEL=m +# CONFIG_NET_SCH_FQ_PIE is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SHAPER=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_NET_VENDOR_AGERE is not set +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALLWINNER=y +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_SPACEMIT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +CONFIG_NET_VENDOR_VERTEXCOM=y +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_NET_VRF=m +CONFIG_NET_XGRESS=y +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_APP_FLOWER=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP_NET_IPSEC=y +CONFIG_NFSD=m +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_LEGACY_CLIENT_TRACKING=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_V4_2_INTER_SSC=y +# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_DEBUG=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_LOCALIO is not set +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_2=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_NFS_V4_SECURITY_LABEL=y +# CONFIG_NFTL is not set +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COMPAT_ARP=m +# CONFIG_NFT_CONNLIMIT is not set +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +# CONFIG_NFT_EXTHDR_DCCP is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +# CONFIG_NFT_OSF is not set +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +# CONFIG_NFT_REJECT_NETDEV is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_SYNPROXY is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_XFRM is not set +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_AMANDA=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NGBE=m +# CONFIG_NGBEVF is not set +# CONFIG_NIC7018_WDT is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +CONFIG_NLMON=m +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +CONFIG_NODES_SHIFT=7 +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_TRACER=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +# CONFIG_NOVA_CORE is not set +# CONFIG_NOZOMI is not set +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_PAGE_MAPCOUNT is not set +CONFIG_NR_CPUS=256 +# CONFIG_NSM is not set +# CONFIG_NTB is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS_FS=m +CONFIG_NTSYNC=m +# CONFIG_NULL_TTY is not set +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NUMA_EMU is not set +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NVDIMM_DAX=y +CONFIG_NVDIMM_KEYS=y +CONFIG_NVDIMM_PFN=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SOPHGO_EFUSE=m +# CONFIG_NVMEM_SUNXI_SID is not set +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_U_BOOT_ENV is not set +CONFIG_NVME_AUTH=y +CONFIG_NVME_CORE=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_KEYRING=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_AUTH is not set +# CONFIG_NVME_TARGET_DEBUGFS is not set +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_PASSTHRU=y +# CONFIG_NVME_TARGET_PCI_EPF is not set +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_TCP_TLS is not set +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NUMA=y +CONFIG_OF_OVERLAY=y +# CONFIG_OF_PARTITION is not set +CONFIG_OF_PMEM=m +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OID_REGISTRY=y +# CONFIG_OMFS_FS is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +# CONFIG_OPEN_DICE is not set +# CONFIG_ORANGEFS_FS is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OSNOISE_TRACER=y +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVMF_DEBUG_LOG is not set +CONFIG_OVPN=m +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_PAGE_COUNTER=y +# CONFIG_PAGE_EXTENSION is not set +CONFIG_PAGE_IDLE_FLAG=y +CONFIG_PAGE_MAPCOUNT=y +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_VERSION=131 +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARAVIRT is not set +# CONFIG_PARPORT is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ACPI is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +CONFIG_PATA_TIMINGS=y +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PC104 is not set +# CONFIG_PC300TOO is not set +CONFIG_PCC=y +# CONFIG_PCCARD is not set +CONFIG_PCI=y +# CONFIG_PCI200SYN is not set +CONFIG_PCIEAER=y +CONFIG_PCIEAER_CXL=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_CADENCE=m +CONFIG_PCIE_CADENCE_HOST=m +# CONFIG_PCIE_CADENCE_PLAT_EP is not set +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +CONFIG_PCIE_DPC=y +CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_DEBUGFS is not set +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_ECRC=y +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_FU740=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_PLDA_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_RCAR_EP is not set +# CONFIG_PCIE_RCAR_GEN4_EP is not set +# CONFIG_PCIE_RCAR_GEN4_HOST is not set +# CONFIG_PCIE_RCAR_HOST is not set +CONFIG_PCIE_SG2042_HOST=m +CONFIG_PCIE_SOPHGO_DW=y +CONFIG_PCIE_SPACEMIT_K1=y +CONFIG_PCIE_STARFIVE_HOST=y +# CONFIG_PCIE_THERMAL is not set +# CONFIG_PCIE_TPH is not set +CONFIG_PCIE_ULTRARISC=m +CONFIG_PCIE_XILINX=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_ATS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_DOE=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCI_ECAM=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +# CONFIG_PCI_ENDPOINT_MSI_DOORBELL is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_PCI_EPF_NTB is not set +# CONFIG_PCI_EPF_TEST is not set +# CONFIG_PCI_FTPCI100 is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI=y +# CONFIG_PCI_NPEM is not set +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_PASID=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTRL=y +CONFIG_PCI_PWRCTRL_SLOT=y +CONFIG_PCI_QUIRKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +# CONFIG_PCI_SW_SWITCHTEC is not set +# CONFIG_PCNET32 is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCS_RZN1_MIIC=m +CONFIG_PCS_XPCS=m +# CONFIG_PDC_ADMA is not set +# CONFIG_PDS_CORE is not set +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_PFCP is not set +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=5 +# CONFIG_PHANTOM is not set +# CONFIG_PHONET is not set +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_NXP_PTN3222 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_PACKAGE=m +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set +# CONFIG_PHY_RCAR_GEN2 is not set +# CONFIG_PHY_RCAR_GEN3_PCIE is not set +# CONFIG_PHY_RCAR_GEN3_USB2 is not set +# CONFIG_PHY_RCAR_GEN3_USB3 is not set +# CONFIG_PHY_SOPHGO_CV1800_USB2 is not set +CONFIG_PHY_SPACEMIT_K1_PCIE=y +CONFIG_PHY_SPACEMIT_K1_USB2=m +CONFIG_PHY_SPACEMIT_K3_COMBO_PHY=m +CONFIG_PHY_SPACEMIT_K3_COMMON_OPS=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_SUN4I_USB is not set +# CONFIG_PHY_SUN50I_USB3 is not set +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PHY_TH1520_USB=m +# CONFIG_PHY_TUSB1210 is not set +CONFIG_PID_NS=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_AW9523 is not set +# CONFIG_PINCTRL_CY8C95X0 is not set +# CONFIG_PINCTRL_EIC7700 is not set +# CONFIG_PINCTRL_K230 is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RENESAS=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_SOPHGO_COMMON=y +# CONFIG_PINCTRL_SOPHGO_CV1800B is not set +# CONFIG_PINCTRL_SOPHGO_CV1812H is not set +# CONFIG_PINCTRL_SOPHGO_SG2000 is not set +# CONFIG_PINCTRL_SOPHGO_SG2002 is not set +CONFIG_PINCTRL_SOPHGO_SG2042=y +CONFIG_PINCTRL_SOPHGO_SG2042_OPS=y +CONFIG_PINCTRL_SOPHGO_SG2044=y +CONFIG_PINCTRL_SPACEMIT_K1=y +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN55I_A523 is not set +# CONFIG_PINCTRL_SUN55I_A523_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_TH1520=y +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set +CONFIG_PLDMFW=y +# CONFIG_PLFXLC is not set +# CONFIG_PLX_DMA is not set +CONFIG_PM=y +CONFIG_PMBUS=m +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +CONFIG_PMIC_OPREGION=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_FLEXFILE_LAYOUT=y +CONFIG_PNP=y +CONFIG_PNPACPI=y +CONFIG_PNP_DEBUG_MESSAGES=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set +CONFIG_PORTABLE=y +# CONFIG_POSIX_AUX_CLOCKS is not set +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POSIX_TIMERS=y +# CONFIG_POWERCAP is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SPACEMIT_P1=m +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_TH1520_AON=m +CONFIG_POWER_SEQUENCING=m +# CONFIG_POWER_SEQUENCING_QCOM_WCN is not set +CONFIG_POWER_SEQUENCING_TH1520_GPU=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPP=m +CONFIG_PPPOE=m +CONFIG_PPPOE_HASH_BITS=4 +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS=y +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPS_GENERATOR is not set +CONFIG_PPTP=m +# CONFIG_PREEMPT is not set +CONFIG_PREEMPTION=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPT_LAZY is not set +CONFIG_PREEMPT_NONE=y +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +# CONFIG_PREEMPT_RT is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_PRIME_NUMBERS is not set +CONFIG_PRINTK=y +CONFIG_PRINTK_CALLER=y +# CONFIG_PRINTK_INDEX is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +# CONFIG_PROVE_LOCKING is not set +CONFIG_PSAMPLE=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTP_1588_CLOCK=y +# CONFIG_PTP_1588_CLOCK_FC3W is not set +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_INES is not set +# CONFIG_PTP_1588_CLOCK_MOCK is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +# CONFIG_PTP_NETC_V4_TIMER is not set +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +# CONFIG_PWM_ARGON_FAN_HAT is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set +# CONFIG_PWM_MC33XS2410 is not set +# CONFIG_PWM_MICROCHIP_CORE is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_PROVIDE_GPIO is not set +# CONFIG_PWM_PXA is not set +# CONFIG_PWM_RENESAS_RCAR is not set +# CONFIG_PWM_RENESAS_TPU is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_SOPHGO_SG2042=m +# CONFIG_PWM_SUN4I is not set +CONFIG_PWM_TH1520=m +# CONFIG_PWM_XILINX is not set +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA807X_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +CONFIG_QCOM_EMAC=m +CONFIG_QCOM_HIDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_NET_PHYLIB=m +# CONFIG_QCOM_PMIC_GLINK is not set +# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED_FCOE=y +CONFIG_QED_ISCSI=y +CONFIG_QED_LL2=y +CONFIG_QED_OOO=y +CONFIG_QED_RDMA=y +CONFIG_QED_SRIOV=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QLA3XXX=m +# CONFIG_QLCNIC is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QRTR is not set +CONFIG_QSEMI_PHY=m +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=y +CONFIG_R8169=y +CONFIG_RADIO_ADAPTERS=m +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RAPIDIO is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RCAR_DMAC is not set +# CONFIG_RCAR_GEN3_THERMAL is not set +# CONFIG_RCAR_THERMAL is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RC_CORE is not set +CONFIG_RDMA_RXE=m +# CONFIG_RDMA_SIW is not set +# CONFIG_RDS is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=y +# CONFIG_REALTEK_PHY_HWMON is not set +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=m +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ADP5055 is not set +# CONFIG_REGULATOR_AW37503 is not set +# CONFIG_REGULATOR_DA9063 is not set +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX20411 is not set +# CONFIG_REGULATOR_MAX77503 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MAX77838 is not set +# CONFIG_REGULATOR_MAX77857 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF0900 is not set +# CONFIG_REGULATOR_PF530X is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PF9453 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RAA215300 is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT4803 is not set +# CONFIG_REGULATOR_RT5133 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5739 is not set +# CONFIG_REGULATOR_RT5759 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTQ2208 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_SLG51000 is not set +CONFIG_REGULATOR_SPACEMIT_P1=m +CONFIG_REGULATOR_SUN20I=y +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC is not set +# CONFIG_REMOTE_TARGET is not set +# CONFIG_RENESAS_OSTM is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_RENESAS_RZAWDT is not set +# CONFIG_RENESAS_RZN1WDT is not set +# CONFIG_RENESAS_RZV2HWDT is not set +# CONFIG_RENESAS_USB_DMAC is not set +# CONFIG_RENESAS_WDT is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_RESET_K230=y +CONFIG_RESET_POLARFIRE_SOC=y +# CONFIG_RESET_RZV2H_USB2PHY is not set +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SPACEMIT_COMMON=y +CONFIG_RESET_SPACEMIT_K1=y +CONFIG_RESET_SPACEMIT_K3=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_SUNXI=y +CONFIG_RESET_TH1520=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set +CONFIG_RETHOOK=y +# CONFIG_RFD_FTL is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFS_ACCEL=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_APLIC=y +CONFIG_RISCV_APLIC_MSI=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_RISCV_COMBO_SPINLOCKS=y +CONFIG_RISCV_DMA_NONCOHERENT=y +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set +CONFIG_RISCV_IMSIC=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_IOMMU=y +CONFIG_RISCV_IOMMU_PCI=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SUPM=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_VENDOR_EXT=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y +CONFIG_RISCV_ISA_VENDOR_EXT_MIPS=y +CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y +CONFIG_RISCV_ISA_VENDOR_EXT_THEAD=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_V_PREEMPTIVE=y +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 +CONFIG_RISCV_ISA_XTHEADVECTOR=y +CONFIG_RISCV_ISA_ZABHA=y +CONFIG_RISCV_ISA_ZACAS=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y +CONFIG_RISCV_ISA_ZBKB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOP=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_MISALIGNED=y +CONFIG_RISCV_NONSTANDARD_CACHE_OPS=y +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS=y +CONFIG_RISCV_RPMI_SYSMSI=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_CPUIDLE=y +CONFIG_RISCV_SBI_MPXY_MBOX=y +# CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SCALAR_MISALIGNED=y +# CONFIG_RISCV_TICKET_SPINLOCKS is not set +CONFIG_RISCV_TIMER=y +CONFIG_RISCV_VECTOR_MISALIGNED=y +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +# CONFIG_RMI4_F1A is not set +# CONFIG_RMI4_F21 is not set +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +# CONFIG_RMI4_F55 is not set +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +# CONFIG_RMNET is not set +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_ROCKER=m +# CONFIG_ROMFS_FS is not set +CONFIG_ROOT_NFS=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set +# CONFIG_RPMB is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_NS=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_TTY is not set +CONFIG_RPMSG_VIRTIO=y +CONFIG_RPS=y +CONFIG_RSEQ=y +# CONFIG_RT2400PCI is not set +# CONFIG_RT2500PCI is not set +# CONFIG_RT2500USB is not set +# CONFIG_RT2800PCI is not set +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +# CONFIG_RT2800USB_RT3573 is not set +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +# CONFIG_RT2800USB_RT55XX is not set +# CONFIG_RT2800USB_UNKNOWN is not set +CONFIG_RT2800_LIB=m +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_USB=m +# CONFIG_RT61PCI is not set +# CONFIG_RT73USB is not set +# CONFIG_RTASE is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_DRV_ABB5ZES3=m +# CONFIG_RTC_DRV_ABEOZ9 is not set +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_CADENCE is not set +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685=y +CONFIG_RTC_DRV_DS1685_FAMILY=m +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +# CONFIG_RTC_DRV_FTRTC010 is not set +CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_ISL12026 is not set +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX31335 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +# CONFIG_RTC_DRV_MAX6916 is not set +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +# CONFIG_RTC_DRV_NCT3018Y is not set +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_POLARFIRE_SOC is not set +# CONFIG_RTC_DRV_R7301 is not set +CONFIG_RTC_DRV_R9701=m +# CONFIG_RTC_DRV_RENESAS_RTCA3 is not set +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3029C2=m +# CONFIG_RTC_DRV_RV3029_HWMON is not set +# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_RX4581=m +# CONFIG_RTC_DRV_RX6110 is not set +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +# CONFIG_RTC_DRV_RX8111 is not set +CONFIG_RTC_DRV_RX8581=m +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SD2405AL is not set +# CONFIG_RTC_DRV_SD3078 is not set +# CONFIG_RTC_DRV_SH is not set +CONFIG_RTC_DRV_SPACEMIT_P1=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_NVMEM=y +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192D_COMMON=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +# CONFIG_RTL8XXXU_UNTESTED is not set +CONFIG_RTLBTCOEXIST=m +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTL_CARDS=m +CONFIG_RTW88=m +CONFIG_RTW88_8703B=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8723X=m +CONFIG_RTW88_8812A=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_8814A=m +CONFIG_RTW88_8814AE=m +CONFIG_RTW88_8814AU=m +CONFIG_RTW88_8821A=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_88XXA=m +CONFIG_RTW88_CORE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW88_LEDS=y +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW89=m +CONFIG_RTW89_8851B=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BT=m +CONFIG_RTW89_8852BTE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852B_COMMON=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922A=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_CORE=m +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89_PCI=m +CONFIG_RTW89_USB=m +CONFIG_RT_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED_DEFAULT_DISABLED is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RUST=y +CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_FILE_AS_C_STR=y +CONFIG_RUSTC_HAS_FILE_WITH_NUL=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y +CONFIG_RUSTC_LLVM_VERSION=210108 +CONFIG_RUSTC_SUPPORTS_RISCV=y +CONFIG_RUSTC_VERSION=109500 +CONFIG_RUSTC_VERSION_TEXT="rustc 1.95.0 (59807616e 2026-04-14) (built from a source tarball)" +CONFIG_RUST_BINDGEN_HAS_ZICSR_ZIFENCEI=y +# CONFIG_RUST_BITMAP_HARDENED is not set +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +CONFIG_RUST_IS_AVAILABLE=y +CONFIG_RUST_OVERFLOW_CHECKS=y +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set +CONFIG_RUST_PWM_ABSTRACTIONS=y +# CONFIG_RV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_RZG2L_THERMAL is not set +# CONFIG_RZG3E_THERMAL is not set +CONFIG_SAMPLES=y +# CONFIG_SAMPLES_RUST is not set +# CONFIG_SAMPLE_ANDROID_BINDERFS is not set +# CONFIG_SAMPLE_AUXDISPLAY is not set +# CONFIG_SAMPLE_CGROUP is not set +# CONFIG_SAMPLE_CHECK_EXEC is not set +# CONFIG_SAMPLE_CONFIGFS is not set +# CONFIG_SAMPLE_CONNECTOR is not set +# CONFIG_SAMPLE_DAMON_MTIER is not set +# CONFIG_SAMPLE_DAMON_PRCL is not set +# CONFIG_SAMPLE_DAMON_WSSE is not set +# CONFIG_SAMPLE_FANOTIFY_ERROR is not set +# CONFIG_SAMPLE_FTRACE_DIRECT is not set +# CONFIG_SAMPLE_FTRACE_DIRECT_MULTI is not set +# CONFIG_SAMPLE_FTRACE_OPS is not set +# CONFIG_SAMPLE_HIDRAW is not set +# CONFIG_SAMPLE_HUNG_TASK is not set +# CONFIG_SAMPLE_KDB is not set +# CONFIG_SAMPLE_KFIFO is not set +# CONFIG_SAMPLE_KOBJECT is not set +# CONFIG_SAMPLE_KPROBES is not set +# CONFIG_SAMPLE_LANDLOCK is not set +# CONFIG_SAMPLE_PIDFD is not set +# CONFIG_SAMPLE_RPMSG_CLIENT is not set +# CONFIG_SAMPLE_SECCOMP is not set +# CONFIG_SAMPLE_TIMER is not set +# CONFIG_SAMPLE_TPS6594_PFSM is not set +# CONFIG_SAMPLE_TRACE_ARRAY is not set +# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set +# CONFIG_SAMPLE_TRACE_EVENTS is not set +# CONFIG_SAMPLE_TRACE_PRINTK is not set +# CONFIG_SAMPLE_TSM_MR is not set +# CONFIG_SAMPLE_UHID is not set +# CONFIG_SAMPLE_VFIO_MDEV_MBOCHS is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set +# CONFIG_SAMPLE_VFIO_MDEV_MTTY is not set +# CONFIG_SAMPLE_VFS is not set +# CONFIG_SAMPLE_WATCHDOG is not set +# CONFIG_SAMPLE_WATCH_QUEUE is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_DWC is not set +CONFIG_SATA_HOST=y +# CONFIG_SATA_INIC162X is not set +CONFIG_SATA_MOBILE_LPM_POLICY=0 +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_ZPODD is not set +CONFIG_SBITMAP=y +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CLASS_EXT is not set +CONFIG_SCHED_HRTICK=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MM_CID=y +# CONFIG_SCHED_PROXY_EXEC is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_SCHED_TRACER=y +CONFIG_SCREEN_INFO=y +CONFIG_SCSI=y +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +CONFIG_SCSI_AACRAID=m +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BNX2_ISCSI=m +# CONFIG_SCSI_BUSLOGIC is not set +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_CXGB3_ISCSI is not set +CONFIG_SCSI_CXGB4_ISCSI=m +# CONFIG_SCSI_DC395x is not set +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_ALUA=y +CONFIG_SCSI_DH_EMC=y +CONFIG_SCSI_DH_HP_SW=y +CONFIG_SCSI_DH_RDAC=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EFCT is not set +CONFIG_SCSI_ENCLOSURE=m +# CONFIG_SCSI_ESAS2R is not set +CONFIG_SCSI_FC_ATTRS=m +# CONFIG_SCSI_FDOMAIN_PCI is not set +CONFIG_SCSI_HPSA=m +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR_TRACE=y +# CONFIG_SCSI_IPS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPI3MR is not set +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SCSI_NETLINK=y +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +# CONFIG_SCSI_SNIC is not set +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +CONFIG_SCSI_UFSHCD=m +# CONFIG_SCSI_UFSHCD_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_BSG=y +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +CONFIG_SCSI_UFS_CRYPTO=y +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_HWMON=y +# CONFIG_SCSI_UFS_RENESAS is not set +CONFIG_SCSI_UFS_SPACEMIT=m +CONFIG_SCSI_VIRTIO=y +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y +CONFIG_SDIO_UART=m +# CONFIG_SDR_MAX2175 is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP_FILTER=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY_INFINIBAND=y +# CONFIG_SECURITY_IPE is not set +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +# CONFIG_SECURITY_SELINUX_DEBUG is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ACBEL_FSG032 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM1266 is not set +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +# CONFIG_SENSORS_ADP1050 is not set +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_AHT10 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set +CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_BEL_PFE is not set +CONFIG_SENSORS_BH1770=m +# CONFIG_SENSORS_BPA_RS600 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_CRPS is not set +# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set +CONFIG_SENSORS_DME1737=m +# CONFIG_SENSORS_DPS920AB is not set +# CONFIG_SENSORS_DRIVETEMP is not set +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +# CONFIG_SENSORS_FSP_3Y is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_HTU31 is not set +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_INA209=m +# CONFIG_SENSORS_INA233 is not set +# CONFIG_SENSORS_INA238 is not set +CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL28022 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM25066=m +# CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +# CONFIG_SENSORS_LT3074 is not set +# CONFIG_SENSORS_LT7182S is not set +CONFIG_SENSORS_LTC2945=m +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +# CONFIG_SENSORS_LTC4286 is not set +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX16601 is not set +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +# CONFIG_SENSORS_MAX6620 is not set +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX8688=m +# CONFIG_SENSORS_MC34VR500 is not set +CONFIG_SENSORS_MCP3021=m +# CONFIG_SENSORS_MP2856 is not set +# CONFIG_SENSORS_MP2869 is not set +# CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set +# CONFIG_SENSORS_MP29502 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set +# CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set +# CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set +# CONFIG_SENSORS_MPQ7932 is not set +# CONFIG_SENSORS_MPQ8785 is not set +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set +# CONFIG_SENSORS_NCT7363 is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +# CONFIG_SENSORS_PIM4328 is not set +# CONFIG_SENSORS_PLI1209BC is not set +# CONFIG_SENSORS_PM6764TR is not set +CONFIG_SENSORS_PMBUS=m +# CONFIG_SENSORS_POWERZ is not set +CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PT5161L is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_PXE1610 is not set +# CONFIG_SENSORS_Q54SJ108A2 is not set +# CONFIG_SENSORS_SBTSI is not set +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SCH56XX_COMMON=m +# CONFIG_SENSORS_SFCTEMP is not set +CONFIG_SENSORS_SG2042_MCU=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +# CONFIG_SENSORS_SPD5118 is not set +# CONFIG_SENSORS_STPDDC60 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_TC654 is not set +CONFIG_SENSORS_TC74=m +# CONFIG_SENSORS_TDA38640 is not set +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +# CONFIG_SENSORS_TMP108 is not set +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +# CONFIG_SENSORS_TMP464 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_TPS25990 is not set +CONFIG_SENSORS_TPS40422=m +# CONFIG_SENSORS_TPS53679 is not set +# CONFIG_SENSORS_TPS546D24 is not set +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +# CONFIG_SENSORS_W83773G is not set +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +# CONFIG_SENSORS_XDP710 is not set +# CONFIG_SENSORS_XDPE122 is not set +# CONFIG_SENSORS_XDPE152 is not set +# CONFIG_SENSORS_XGENE is not set +CONFIG_SENSORS_ZL6100=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +# CONFIG_SERIAL_8250_EM is not set +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PCI1XXXX is not set +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_ATMEL is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SPRD is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIO=y +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_GPIO_PS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_SUN4I_PS2 is not set +CONFIG_SFC=m +# CONFIG_SFC_FALCON is not set +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_SFC_SRIOV=y +CONFIG_SFP=m +# CONFIG_SF_PDMA is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SIGNALFD=y +CONFIG_SIGNATURE=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIOX is not set +CONFIG_SKB_DECRYPTED=y +CONFIG_SKB_EXTENSIONS=y +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_OBJ_EXT=y +CONFIG_SLHC=m +# CONFIG_SLICOSS is not set +# CONFIG_SLIMBUS is not set +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_SLIP_SMART=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_SMBFS=m +# CONFIG_SMB_SERVER is not set +CONFIG_SMP=y +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_SM_FTL is not set +CONFIG_SND=m +# CONFIG_SND_AD1889 is not set +CONFIG_SND_ALOOP=m +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CTL_FAST_LOOKUP=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +CONFIG_SND_HDA=m +# CONFIG_SND_HDA_ACPI is not set +# CONFIG_SND_HDA_CODEC_ANALOG is not set +# CONFIG_SND_HDA_CODEC_CA0110 is not set +# CONFIG_SND_HDA_CODEC_CA0132 is not set +# CONFIG_SND_HDA_CODEC_CIRRUS is not set +# CONFIG_SND_HDA_CODEC_CM9825 is not set +# CONFIG_SND_HDA_CODEC_CMEDIA is not set +# CONFIG_SND_HDA_CODEC_CONEXANT is not set +# CONFIG_SND_HDA_CODEC_HDMI is not set +# CONFIG_SND_HDA_CODEC_REALTEK is not set +# CONFIG_SND_HDA_CODEC_SENARYTECH is not set +# CONFIG_SND_HDA_CODEC_SI3054 is not set +# CONFIG_SND_HDA_CODEC_SIGMATEL is not set +# CONFIG_SND_HDA_CODEC_VIA is not set +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_CORE=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# CONFIG_SND_HDA_GENERIC is not set +# CONFIG_SND_HDA_HWDEP is not set +CONFIG_SND_HDA_I915=y +# CONFIG_SND_HDA_INPUT_BEEP is not set +CONFIG_SND_HDA_INTEL=m +# CONFIG_SND_HDA_PATCH_LOADER is not set +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDA_RECONFIG is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_SPI is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_HWDEP=m +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OSSEMUL is not set +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +CONFIG_SND_PCM=m +# CONFIG_SND_PCMTEST is not set +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCXHR is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_RAWMIDI=m +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +CONFIG_SND_SOC=m +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1373 is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_ADI_AXI_I2S is not set +# CONFIG_SND_SOC_ADI_AXI_SPDIF is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_SOC_AW8738 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88081 is not set +# CONFIG_SND_SOC_AW88166 is not set +# CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88399 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CHV3_CODEC is not set +# CONFIG_SND_SOC_CHV3_I2S is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L45_I2C is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS35L56_I2C is not set +# CONFIG_SND_SOC_CS35L56_SPI is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L83 is not set +# CONFIG_SND_SOC_CS42L84 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS48L32 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8323 is not set +# CONFIG_SND_SOC_ES8326 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_ES8375 is not set +# CONFIG_SND_SOC_ES8389 is not set +# CONFIG_SND_SOC_FS210X is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_IDT821034 is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_JH7110_PWMDAC is not set +# CONFIG_SND_SOC_JH7110_TDM is not set +CONFIG_SND_SOC_K1_I2S=m +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98388 is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX98396 is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX98520 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MIKROE_PROTO is not set +# CONFIG_SND_SOC_MSIOF is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8325 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_NTP8835 is not set +# CONFIG_SND_SOC_NTP8918 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1754 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_RCAR is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RT9123 is not set +# CONFIG_SND_SOC_RT9123P is not set +# CONFIG_SND_SOC_RTQ9124 is not set +# CONFIG_SND_SOC_RTQ9128 is not set +CONFIG_SND_SOC_SDCA_OPTIONAL=m +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SH4_FSI is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SMA1303 is not set +# CONFIG_SND_SOC_SMA1307 is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM3515 is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set +# CONFIG_SND_SOC_TAS2781_I2C is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS5805M is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_UDA1342 is not set +# CONFIG_SND_SOC_USB is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731_I2C is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8940 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SOC_ZL38060 is not set +CONFIG_SND_SPI=y +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SND_SUPPORT_OLD_API=y +# CONFIG_SND_TEST_COMPONENT is not set +CONFIG_SND_TIMER=m +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_UTIMER is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTIO is not set +# CONFIG_SND_VIRTUOSO is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_SOC_BUS=y +CONFIG_SOC_RENESAS=y +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_TI is not set +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM is not set +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONY_FF=y +# CONFIG_SOPHGO_CV1800B_DMAMUX is not set +# CONFIG_SOPHGO_CV1800_RTCSYS is not set +CONFIG_SOPHGO_SG2042_MSI=y +CONFIG_SOPHGO_SG2044_TOPSYS=y +CONFIG_SOUND=m +# CONFIG_SOUNDWIRE is not set +CONFIG_SPACEMIT_CCU=y +CONFIG_SPACEMIT_K1_CCU=y +CONFIG_SPACEMIT_K1_EMAC=m +CONFIG_SPACEMIT_K1_TSENSOR=m +CONFIG_SPACEMIT_K3_CCU=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_ATMEL is not set +# CONFIG_SPI_AX88796C is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_CADENCE=m +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_DESIGNWARE=y +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_FSL_QUADSPI=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_POLARFIRE_SOC is not set +# CONFIG_SPI_RSPI is not set +# CONFIG_SPI_RZV2H_RSPI is not set +# CONFIG_SPI_RZV2M_CSI is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SG2044_NOR=m +# CONFIG_SPI_SH_HSPI is not set +# CONFIG_SPI_SH_MSIOF is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI_SN_F_OSPI is not set +CONFIG_SPI_SPACEMIT_K1=m +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_VIRTIO is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +# CONFIG_SPMI is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_ZSTD is not set +CONFIG_SRAM=y +# CONFIG_SSB is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSFDC is not set +# CONFIG_SSIF_IPMI_BMC is not set +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_STACK_TRACER=y +# CONFIG_STAGING is not set +CONFIG_STANDALONE=y +CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set +# CONFIG_STARFIVE_STARLINK_PMU is not set +CONFIG_STARFIVE_WATCHDOG=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +# CONFIG_STM is not set +CONFIG_STMMAC_ETH=m +CONFIG_STMMAC_PCI=m +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STP=m +CONFIG_STREAM_PARSER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN20I_PPU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +# CONFIG_SUN50I_DE2_BUS is not set +# CONFIG_SUN50I_H6_PRCM_PPU is not set +# CONFIG_SUN50I_IOMMU is not set +CONFIG_SUN55I_PCK600=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUNRPC=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_DEBUG=y +# CONFIG_SUNRPC_DEBUG_TRACE is not set +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +# CONFIG_SUNXI_WATCHDOG is not set +# CONFIG_SUN_PARTITION is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SWPHY=y +# CONFIG_SW_SYNC is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYN_COOKIES=y +# CONFIG_SYSCON_REBOOT_MODE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +CONFIG_SYSFB_SIMPLEFB=y +CONFIG_SYSFS=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set +CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_REVOCATION_KEYS="" +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_TAP=m +CONFIG_TARGET_CORE=m +CONFIG_TASKSTATS=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_CORE=y +# CONFIG_TCG_TIS_I2C is not set +CONFIG_TCG_TIS_I2C_ATMEL=m +# CONFIG_TCG_TIS_I2C_CR50 is not set +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI=y +# CONFIG_TCG_TIS_SPI_CR50 is not set +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_TCG_TPM=y +# CONFIG_TCG_TPM2_HMAC is not set +# CONFIG_TCG_VTPM_PROXY is not set +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +# CONFIG_TCM_QLA2XXX is not set +CONFIG_TCM_USER2=m +# CONFIG_TCP_AO is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +# CONFIG_TCP_CONG_CDG is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +CONFIG_TCP_SIGPOOL=y +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_TEST_LOCKUP is not set +# CONFIG_TEST_POWER is not set +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TH1520_AON_PROTOCOL=y +CONFIG_TH1520_PM_DOMAINS=m +CONFIG_THEAD_TH1520_MBOX=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_CORE_TESTING is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +# CONFIG_THERMAL_NETLINK is not set +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SIZE_ORDER=2 +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_THUNDER_NIC_VF=m +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIMERFD=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TIME_NS=y +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_SHARP_MEMORY is not set +CONFIG_TIPC=m +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_TI_FPC202 is not set +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_XATTR=y +CONFIG_TOOLCHAIN_HAS_V=y +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO=y +CONFIG_TOOLCHAIN_HAS_ZABHA=y +CONFIG_TOOLCHAIN_HAS_ZACAS=y +CONFIG_TOOLCHAIN_HAS_ZBA=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_TOOLCHAIN_HAS_ZBC=y +CONFIG_TOOLCHAIN_HAS_ZBKB=y +CONFIG_TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y +CONFIG_TRACEPOINTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_GPU_MEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_TRUSTED_KEYS=y +CONFIG_TRUSTED_KEYS_TPM=y +# CONFIG_TSNEP is not set +CONFIG_TTY=y +CONFIG_TTY_PRINTK=m +CONFIG_TTY_PRINTK_LEVEL=6 +CONFIG_TUN=m +CONFIG_TUNE_GENERIC=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_TXGBE=m +# CONFIG_TXGBEVF is not set +CONFIG_TYPEC=m +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_DP_ALTMODE=m +# CONFIG_TYPEC_FUSB302 is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_IT5205 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_PS883X is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set +# CONFIG_TYPEC_MUX_TUSB1046 is not set +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TBT_ALTMODE is not set +CONFIG_TYPEC_TCPCI=m +# CONFIG_TYPEC_TCPCI_MAXIM is not set +CONFIG_TYPEC_TCPM=m +# CONFIG_TYPEC_TPS6598X is not set +CONFIG_TYPEC_UCSI=m +# CONFIG_TYPEC_WUSB3801 is not set +CONFIG_UACCE=m +# CONFIG_UAPI_HEADER_TEST is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_UBSAN is not set +# CONFIG_UCLAMP_TASK is not set +CONFIG_UCS2_STRING=y +# CONFIG_UCSI_ACPI is not set +# CONFIG_UCSI_CCG is not set +# CONFIG_UCSI_STM32G0 is not set +CONFIG_UDF_FS=m +# CONFIG_UDMABUF is not set +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UFS_FS is not set +CONFIG_UHID=m +CONFIG_UIO=m +CONFIG_UIO_AEC=m +CONFIG_UIO_CIF=m +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_SERCOS3=m +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNION_FIND=y +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX_DIAG=m +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y +CONFIG_USB=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +CONFIG_USB4_NET=m +# CONFIG_USBIP_CORE is not set +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +# CONFIG_USB_AIRSPY is not set +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_BELKIN=y +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_CATC=m +# CONFIG_USB_CDNS_SUPPORT is not set +CONFIG_USB_CHAOSKEY=m +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_COMMON=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DWC2 is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_GENERIC_PLAT=m +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_PCI=m +# CONFIG_USB_DWC3_ULPI is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_HSIC_USB3503=m +# CONFIG_USB_HSIC_USB4604 is not set +CONFIG_USB_HSO=m +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_IPHETH=m +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1760 is not set +CONFIG_USB_KAWETH=m +CONFIG_USB_KC2190=y +# CONFIG_USB_KEENE is not set +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_LJCA is not set +# CONFIG_USB_MA901 is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y +# CONFIG_USB_MR800 is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_ONBOARD_DEV=m +# CONFIG_USB_ONBOARD_DEV_USB5744 is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set +CONFIG_USB_PEGASUS=m +CONFIG_USB_PRINTER=m +# CONFIG_USB_PWC is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +# CONFIG_USB_S2255 is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +# CONFIG_USB_SERIAL_UPD78F0730 is not set +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_WWAN=m +# CONFIG_USB_SERIAL_XR is not set +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEST is not set +CONFIG_USB_TMC=m +# CONFIG_USB_TRANCEVIBRATOR is not set +CONFIG_USB_UAS=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_USBNET=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_XHCI_RCAR=y +# CONFIG_USB_XHCI_SIDEBAND is not set +# CONFIG_USB_YUREX is not set +CONFIG_USERFAULTFD=y +# CONFIG_USERIO is not set +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USER_NS=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_UTS_NS=y +CONFIG_UVC_COMMON=m +CONFIG_V4L2_ASYNC=m +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L2_FWNODE=m +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +CONFIG_VALIDATE_FS_PARSER=y +# CONFIG_VCPU_STALL_DETECTOR is not set +# CONFIG_VDPA is not set +CONFIG_VDSO_GETRANDOM=y +CONFIG_VETH=m +CONFIG_VFAT_FS=y +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +CONFIG_VFIO_GROUP=y +CONFIG_VFIO_NOIOMMU=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=64 +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST_VSOCK=m +CONFIG_VIDEO=y +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_ALVIUM_CSI2 is not set +# CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +# CONFIG_VIDEO_CADENCE_CSI2TX is not set +CONFIG_VIDEO_CAMERA_LENS=y +CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_DEV=m +# CONFIG_VIDEO_DS90UB913 is not set +# CONFIG_VIDEO_DS90UB953 is not set +# CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9719 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_ET8EK8 is not set +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC0310 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_HI846 is not set +# CONFIG_VIDEO_HI847 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX296 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_IMX415 is not set +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# CONFIG_VIDEO_LT6911UXE is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_OG01A1B is not set +# CONFIG_VIDEO_OG0VE1B is not set +# CONFIG_VIDEO_OV01A10 is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV02C10 is not set +# CONFIG_VIDEO_OV02E10 is not set +# CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV08X40 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_OV13B10 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV2735 is not set +# CONFIG_VIDEO_OV2740 is not set +# CONFIG_VIDEO_OV4689 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV6211 is not set +# CONFIG_VIDEO_OV64A40 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8858 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_RP1_CFE is not set +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_STK1160 is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THP7312 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VD55G1 is not set +# CONFIG_VIDEO_VD56G3 is not set +# CONFIG_VIDEO_VGXY61 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VIRTIO_FS=y +CONFIG_VIRTIO_INPUT=y +# CONFIG_VIRTIO_MEM is not set +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +# CONFIG_VIRTIO_PMEM is not set +CONFIG_VIRTIO_RTC=m +CONFIG_VIRTIO_RTC_CLASS=y +CONFIG_VIRTIO_RTC_PTP=y +# CONFIG_VIRTIO_VFIO_PCI is not set +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_VIRTUALIZATION=y +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_VIRT_DRIVERS=y +# CONFIG_VIRT_WIFI is not set +CONFIG_VIRT_XFER_TO_GUEST_WORK=y +CONFIG_VITESSE_PHY=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_PFN=y +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_VMXNET3 is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKMON=m +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VXFS_FS is not set +CONFIG_VXLAN=m +# CONFIG_W1 is not set +CONFIG_WAN=y +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_WANXL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +# CONFIG_WATCH_QUEUE is not set +# CONFIG_WCN36XX is not set +# CONFIG_WDAT_WDT is not set +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +# CONFIG_WFX is not set +# CONFIG_WIL6210 is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIRELESS=y +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WPCM450_SOC is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WQ_WATCHDOG=y +# CONFIG_WWAN is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_X25 is not set +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_XARRAY_MULTI=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XFRM=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_IPCOMP=m +# CONFIG_XFRM_IPTFS is not set +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_USER=m +CONFIG_XFS_BTREE_IN_MEM=y +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_DRAIN_INTENTS=y +CONFIG_XFS_FS=y +CONFIG_XFS_LIVE_HOOKS=y +CONFIG_XFS_MEMORY_BUFS=y +CONFIG_XFS_ONLINE_REPAIR=y +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_XFS_ONLINE_SCRUB_STATS=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +# CONFIG_XFS_SUPPORT_ASCII_CI is not set +# CONFIG_XFS_SUPPORT_V4 is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_XILINX_INTC is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_VCU is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_XDMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_RISCV=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_XZ_DEC_X86=y +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZERO_CALL_USED_REGS is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +CONFIG_ZISOFS=y +# CONFIG_ZL3073X_I2C is not set +# CONFIG_ZL3073X_SPI is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZONEFS_FS is not set +CONFIG_ZONE_DEVICE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZRAM=m +# CONFIG_ZRAM_BACKEND_842 is not set +# CONFIG_ZRAM_BACKEND_DEFLATE is not set +CONFIG_ZRAM_BACKEND_FORCE_LZO=y +# CONFIG_ZRAM_BACKEND_LZ4 is not set +# CONFIG_ZRAM_BACKEND_LZ4HC is not set +CONFIG_ZRAM_BACKEND_LZO=y +# CONFIG_ZRAM_BACKEND_ZSTD is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC=y +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +CONFIG_ZSMALLOC_STAT=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lz4" +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set diff --git a/SPECS/linux-lts-kmhv2/config.x86_64 b/SPECS/linux-lts-kmhv2/config.x86_64 index d18be35c7e..c228f70942 100644 --- a/SPECS/linux-lts-kmhv2/config.x86_64 +++ b/SPECS/linux-lts-kmhv2/config.x86_64 @@ -1,4826 +1,2712 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_WATCH_QUEUE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 -CONFIG_BPF_JIT=y -CONFIG_BPF_JIT_ALWAYS_ON=y -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_SCHED_CORE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_PSI=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_MEMCG_V1=y -CONFIG_BLK_CGROUP=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_DMEM=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_MISC=y -CONFIG_NAMESPACES=y -CONFIG_USER_NS=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BOOT_CONFIG=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -CONFIG_PROFILING=y -CONFIG_KEXEC=y -CONFIG_KEXEC_JUMP=y -CONFIG_KEXEC_HANDOVER=y -CONFIG_SMP=y -CONFIG_X86_NUMACHIP=y -CONFIG_X86_INTEL_LPSS=y -CONFIG_X86_AMD_PLATFORM_DEVICE=y -CONFIG_IOSF_MBI_DEBUG=y -CONFIG_HYPERVISOR_GUEST=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_XEN=y -CONFIG_XEN_PVH=y -CONFIG_JAILHOUSE_GUEST=y -CONFIG_INTEL_TDX_GUEST=y -CONFIG_PROCESSOR_SELECT=y -CONFIG_GART_IOMMU=y -CONFIG_NR_CPUS=256 -CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_PERF_EVENTS_AMD_POWER=m -CONFIG_PERF_EVENTS_AMD_UNCORE=m -CONFIG_PERF_EVENTS_AMD_BRS=y -CONFIG_X86_MSR=m -CONFIG_X86_CPUID=m -CONFIG_NUMA=y -CONFIG_ARCH_MEMORY_PROBE=y -CONFIG_X86_PMEM_LEGACY=y -CONFIG_X86_CHECK_BIOS_CORRUPTION=y -CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 -CONFIG_X86_SGX=y -CONFIG_EFI=y -CONFIG_EFI_STUB=y -CONFIG_EFI_MIXED=y -CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_LEGACY_VSYSCALL_NONE=y -CONFIG_LIVEPATCH=y -CONFIG_HIBERNATION=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_DEBUG=y -CONFIG_PM_ADVANCED_DEBUG=y -CONFIG_PM_TRACE_RTC=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ACPI_FPDT=y -CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_60XX_WDT=m +CONFIG_64BIT=y +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6PACK=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_842_COMPRESS=m +CONFIG_842_DECOMPRESS=m +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +CONFIG_ABP060MG=m +CONFIG_AC97_BUS=m +CONFIG_ACCESSIBILITY=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_ACERHDF=m +CONFIG_ACER_WIRELESS=m +CONFIG_ACER_WMI=m +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI=y CONFIG_ACPI_AC=m -CONFIG_ACPI_BATTERY=m -CONFIG_ACPI_TAD=m -CONFIG_ACPI_DOCK=y -CONFIG_ACPI_IPMI=m -CONFIG_ACPI_PROCESSOR_AGGREGATOR=m -# CONFIG_ACPI_DEBUG is not set -CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_HOTPLUG_MEMORY=y -CONFIG_ACPI_SBS=m -CONFIG_ACPI_BGRT=y -CONFIG_ACPI_NFIT=m +CONFIG_ACPI_ADXL=y +CONFIG_ACPI_ALS=m CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_EINJ_CXL=y +# CONFIG_ACPI_APEI_ERST_DEBUG is not set CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_BATTERY=m +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CMPC=m +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_CUSTOM_DSDT_FILE="" +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_DOCK=y CONFIG_ACPI_DPTF=y +CONFIG_ACPI_EC=y +CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_EXTLOG=m -CONFIG_ACPI_CONFIGFS=m -CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_FAN=y CONFIG_ACPI_FFH=y -CONFIG_TPS68470_PMIC_OPREGION=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_X86_PCC_CPUFREQ=y -CONFIG_X86_ACPI_CPUFREQ=y -CONFIG_X86_POWERNOW_K8=y -CONFIG_X86_AMD_FREQ_SENSITIVITY=m -CONFIG_X86_SPEEDSTEP_CENTRINO=y -CONFIG_X86_P4_CLOCKMOD=m -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_HALTPOLL_CPUIDLE=m -CONFIG_INTEL_IDLE=y -CONFIG_IA32_EMULATION=y -CONFIG_X86_X32_ABI=y -CONFIG_KVM=m -CONFIG_KVM_WERROR=y -CONFIG_KVM_INTEL=m -CONFIG_X86_SGX_KVM=y -CONFIG_KVM_AMD=m -CONFIG_KVM_XEN=y -CONFIG_JUMP_LABEL=y -CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_MODULE_COMPRESS=y -CONFIG_MODULE_COMPRESS_ZSTD=y -CONFIG_MODULE_DECOMPRESS=y -CONFIG_BLK_DEV_ZONED=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BLK_WBT=y -CONFIG_BLK_CGROUP_FC_APPID=y -CONFIG_BLK_CGROUP_IOCOST=y -CONFIG_BLK_CGROUP_IOPRIO=y -CONFIG_BLK_INLINE_ENCRYPTION=y -CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_AIX_PARTITION=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_KARMA_PARTITION=y -CONFIG_SYSV68_PARTITION=y -CONFIG_CMDLINE_PARTITION=y -CONFIG_MQ_IOSCHED_KYBER=m -# CONFIG_BFQ_GROUP_IOSCHED is not set -CONFIG_BINFMT_MISC=m -CONFIG_ZSWAP=y -CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_SLAB_FREELIST_HARDENED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTREMOVE=y -CONFIG_KSM=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_MEMORY_FAILURE=y -CONFIG_HWPOISON_INJECT=m -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CMA_SYSFS=y -CONFIG_CMA_AREAS=7 -CONFIG_MEM_SOFT_DIRTY=y -CONFIG_IDLE_PAGE_TRACKING=y -CONFIG_ZONE_DEVICE=y -CONFIG_ANON_VMA_NAME=y -CONFIG_USERFAULTFD=y -CONFIG_LRU_GEN=y -CONFIG_DAMON=y -CONFIG_DAMON_RECLAIM=y -CONFIG_DAMON_LRU_SORT=y -CONFIG_DAMON_STAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX_DIAG=m -CONFIG_XFRM_USER=m -CONFIG_XFRM_USER_COMPAT=m -CONFIG_XFRM_INTERFACE=m -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=m -CONFIG_XDP_SOCKETS=y -CONFIG_XDP_SOCKETS_DIAG=m -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_NET_IPVTI=m -CONFIG_NET_FOU_IP_TUNNELS=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_DIAG=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_CDG=m -CONFIG_TCP_CONG_BBR=m -CONFIG_TCP_AO=y -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_ILA=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_GRE=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_MPTCP=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE_NETFILTER=m -CONFIG_NETFILTER_NETLINK_HOOK=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NF_CT_NETLINK_HELPER=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_CONNLIMIT=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_NAT=m -CONFIG_NFT_TUNNEL=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NFT_FIB_INET=m -CONFIG_NFT_XFRM=m -CONFIG_NFT_SOCKET=m -CONFIG_NFT_OSF=m -CONFIG_NFT_TPROXY=m -CONFIG_NFT_SYNPROXY=m -CONFIG_NFT_DUP_NETDEV=m -CONFIG_NFT_FWD_NETDEV=m -CONFIG_NFT_FIB_NETDEV=m -CONFIG_NFT_REJECT_NETDEV=m -CONFIG_NF_FLOW_TABLE_INET=m -CONFIG_NF_FLOW_TABLE=m -CONFIG_NF_FLOW_TABLE_PROCFS=y -CONFIG_NETFILTER_XTABLES_COMPAT=y -CONFIG_NETFILTER_XTABLES_LEGACY=y -CONFIG_NETFILTER_XT_SET=m -CONFIG_NETFILTER_XT_TARGET_AUDIT=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_CT=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_SET=m -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_IPMAC=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_MH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_TWOS=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_PE_SIP=m -CONFIG_NFT_DUP_IPV4=m -CONFIG_NFT_FIB_IPV4=m -CONFIG_NF_TABLES_ARP=y -CONFIG_NF_LOG_ARP=m -CONFIG_NF_LOG_IPV4=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_SECURITY=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_SECURITY=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_META=m -CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_CONNTRACK_BRIDGE=m -CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_SCTP=m -CONFIG_RDS=m -CONFIG_RDS_RDMA=m -CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_TIPC_MEDIA_IB=y -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_L2TP=m -CONFIG_L2TP_DEBUGFS=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_BRIDGE_MRP=y -CONFIG_BRIDGE_CFM=y -CONFIG_NET_DSA=m -CONFIG_NET_DSA_TAG_RTL4_A=m -CONFIG_NET_DSA_TAG_RTL8_4=m -CONFIG_NET_DSA_TAG_RZN1_A5PSW=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_6LOWPAN=m -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m -CONFIG_IEEE802154=m -CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y -CONFIG_IEEE802154_6LOWPAN=m -CONFIG_MAC802154=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_SKBPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_CAKE=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_FQ_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_SCH_ETS=m -CONFIG_NET_SCH_DUALPI2=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_CANID=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_EMATCH_IPT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_MPLS=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_CONNMARK=m -CONFIG_NET_ACT_CTINFO=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_IFE=m -CONFIG_NET_ACT_TUNNEL_KEY=m -CONFIG_NET_ACT_CT=m -CONFIG_NET_ACT_GATE=m -CONFIG_NET_IFE_SKBMARK=m -CONFIG_NET_IFE_SKBPRIO=m -CONFIG_NET_IFE_SKBTCINDEX=m -CONFIG_DNS_RESOLVER=y -CONFIG_BATMAN_ADV=m -# CONFIG_BATMAN_ADV_BATMAN_V is not set -CONFIG_OPENVSWITCH=m -CONFIG_VSOCKETS=m -CONFIG_VMWARE_VMCI_VSOCKETS=m -CONFIG_VIRTIO_VSOCKETS=m -CONFIG_NETLINK_DIAG=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m -CONFIG_HSR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_NET_NCSI=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_NET_PKTGEN=m -CONFIG_NET_DROP_MONITOR=m -CONFIG_HAMRADIO=y -CONFIG_AX25=m -CONFIG_NETROM=m -CONFIG_ROSE=m -CONFIG_MKISS=m -CONFIG_6PACK=m -CONFIG_BPQETHER=m -CONFIG_BAYCOM_SER_FDX=m -CONFIG_BAYCOM_SER_HDX=m -CONFIG_BAYCOM_PAR=m -CONFIG_YAM=m -CONFIG_CAN=m -CONFIG_CAN_J1939=m -CONFIG_CAN_ISOTP=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_6LOWPAN=m -CONFIG_BT_MSFTEXT=y -CONFIG_BT_AOSPEXT=y -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTUSB_MTK=y -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_NOKIA=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_INTEL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_RTL=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_AG6XX=y -CONFIG_BT_HCIUART_MRVL=y -CONFIG_BT_HCIUART_AML=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBCM4377=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIDTL1=m -CONFIG_BT_HCIBT3C=m -CONFIG_BT_HCIBLUECARD=m -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -CONFIG_BT_ATH3K=m -CONFIG_BT_MTKSDIO=m -CONFIG_BT_MTKUART=m -CONFIG_BT_VIRTIO=m -CONFIG_BT_NXPUART=m -CONFIG_BT_INTEL_PCIE=m -CONFIG_AF_RXRPC_IPV6=y -CONFIG_RXGK=y -CONFIG_AF_KCM=m -CONFIG_MCTP=y -CONFIG_CFG80211=m -CONFIG_CFG80211_DEBUGFS=y -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=m -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_DEBUGFS=y -CONFIG_MAC80211_MESSAGE_TRACING=y -CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_NET_9P=m -CONFIG_NET_9P_VIRTIO=m -CONFIG_NET_9P_XEN=m -CONFIG_NET_9P_USBG=m -CONFIG_NET_9P_RDMA=m -CONFIG_CAIF=m -CONFIG_CAIF_USB=m -CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -CONFIG_NFC=m -CONFIG_NFC_DIGITAL=m -CONFIG_NFC_NCI=m -CONFIG_NFC_NCI_SPI=m -CONFIG_NFC_NCI_UART=m -CONFIG_NFC_HCI=m -CONFIG_NFC_SHDLC=y -CONFIG_NFC_TRF7970A=m -CONFIG_NFC_MEI_PHY=m -CONFIG_NFC_SIM=m -CONFIG_NFC_PORT100=m -CONFIG_NFC_VIRTUAL_NCI=m -CONFIG_NFC_FDP=m -CONFIG_NFC_FDP_I2C=m -CONFIG_NFC_PN544_I2C=m -CONFIG_NFC_PN544_MEI=m -CONFIG_NFC_PN533_USB=m -CONFIG_NFC_PN533_I2C=m -CONFIG_NFC_PN532_UART=m -CONFIG_NFC_MICROREAD_I2C=m -CONFIG_NFC_MICROREAD_MEI=m -CONFIG_NFC_MRVL_USB=m -CONFIG_NFC_MRVL_UART=m -CONFIG_NFC_MRVL_I2C=m -CONFIG_NFC_MRVL_SPI=m -CONFIG_NFC_ST21NFCA_I2C=m -CONFIG_NFC_ST_NCI_I2C=m -CONFIG_NFC_ST_NCI_SPI=m -CONFIG_NFC_NXP_NCI=m -CONFIG_NFC_NXP_NCI_I2C=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_NFC_S3FWRN82_UART=m -CONFIG_NFC_ST95HF=m -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIE_DPC=y -CONFIG_PCIE_PTM=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_STUB=m -CONFIG_XEN_PCIDEV_FRONTEND=m -CONFIG_PCI_NPEM=y -CONFIG_PCIE_TPH=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_HOTPLUG_PCI_ACPI_IBM=m -CONFIG_HOTPLUG_PCI_CPCI=y -CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m -CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m -CONFIG_HOTPLUG_PCI_OCTEONEP=y -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_VMD=m -CONFIG_PCI_PWRCTRL_SLOT=m -CONFIG_CXL_BUS=m -CONFIG_PCCARD=m -CONFIG_YENTA=m -CONFIG_PD6729=m -CONFIG_I82092=m -CONFIG_RAPIDIO=y -CONFIG_RAPIDIO_TSI721=m -CONFIG_RAPIDIO_DMA_ENGINE=y -CONFIG_RAPIDIO_ENUM_BASIC=m -CONFIG_RAPIDIO_CHMAN=m -CONFIG_RAPIDIO_MPORT_CDEV=m -CONFIG_RAPIDIO_CPS_XX=m -CONFIG_RAPIDIO_CPS_GEN2=m -CONFIG_RAPIDIO_RXS_GEN3=m -CONFIG_UEVENT_HELPER=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DEVTMPFS_SAFE=y -# CONFIG_STANDALONE is not set -CONFIG_FW_LOADER_COMPRESS=y -CONFIG_FW_LOADER_COMPRESS_ZSTD=y -CONFIG_MHI_BUS_PCI_GENERIC=m -CONFIG_MHI_BUS_EP=m -CONFIG_CONNECTOR=y -CONFIG_EDD=y -CONFIG_EDD_OFF=y -CONFIG_DMI_SYSFS=m -CONFIG_ISCSI_IBFT=m -CONFIG_FW_CFG_SYSFS=m -CONFIG_EFI_VARS_PSTORE=m -CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y -CONFIG_EFI_BOOTLOADER_CONTROL=m -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_FWCTL=y -CONFIG_FWCTL_MLX5=m -CONFIG_FWCTL_PDS=m -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_GNSS_SIRF_SERIAL=m -CONFIG_GNSS_UBX_SERIAL=m -CONFIG_GNSS_USB=m -CONFIG_MTD=m -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_REDBOOT_PARTS=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_BLOCK_RO=m -CONFIG_FTL=m -CONFIG_NFTL=m -CONFIG_NFTL_RW=y -CONFIG_INFTL=m -CONFIG_RFD_FTL=m -CONFIG_SSFDC=m -CONFIG_SM_FTL=m -CONFIG_MTD_OOPS=m -CONFIG_MTD_SWAP=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_ROM=m -CONFIG_MTD_ABSENT=m -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_PHYSMAP_GPIO_ADDR=y -CONFIG_MTD_SBC_GXX=m -CONFIG_MTD_AMD76XROM=m -CONFIG_MTD_ICHXROM=m -CONFIG_MTD_ESB2ROM=m -CONFIG_MTD_CK804XROM=m -CONFIG_MTD_SCB2_FLASH=m -CONFIG_MTD_NETtel=m -CONFIG_MTD_L440GX=m -CONFIG_MTD_PCI=m -CONFIG_MTD_PCMCIA=m -CONFIG_MTD_PLATRAM=m -CONFIG_MTD_PMC551=m -CONFIG_MTD_DATAFLASH=m -CONFIG_MTD_DATAFLASH_OTP=y -CONFIG_MTD_MCHP23K256=m -CONFIG_MTD_MCHP48L640=m -CONFIG_MTD_SST25L=m -CONFIG_MTD_SLRAM=m -CONFIG_MTD_PHRAM=m -CONFIG_MTD_MTDRAM=m -CONFIG_MTD_BLOCK2MTD=m -CONFIG_MTD_INTEL_DG=m -CONFIG_MTD_DOCG3=m -CONFIG_MTD_ONENAND=m -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_ONENAND_GENERIC=m -CONFIG_MTD_ONENAND_2X_PROGRAM=y -CONFIG_MTD_RAW_NAND=m -CONFIG_MTD_NAND_DENALI_PCI=m -CONFIG_MTD_NAND_CAFE=m -CONFIG_MTD_NAND_MXIC=m -CONFIG_MTD_NAND_GPIO=m -CONFIG_MTD_NAND_PLATFORM=m -CONFIG_MTD_NAND_ARASAN=m -CONFIG_MTD_NAND_NANDSIM=m -CONFIG_MTD_NAND_RICOH=m -CONFIG_MTD_NAND_DISKONCHIP=m -CONFIG_MTD_SPI_NAND=m -CONFIG_MTD_LPDDR=m -CONFIG_MTD_UBI=m -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_GLUEBI=m -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_HYPERBUS=m -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_SERIAL=m -CONFIG_PARPORT_PC_FIFO=y -CONFIG_PARPORT_PC_PCMCIA=m -CONFIG_PARPORT_1284=y -# CONFIG_PNP_DEBUG_MESSAGES is not set -CONFIG_BLK_DEV_NULL_BLK=m -CONFIG_BLK_DEV_FD=m -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m -CONFIG_ZRAM=m -CONFIG_ZRAM_BACKEND_LZ4=y -CONFIG_ZRAM_BACKEND_LZ4HC=y -CONFIG_ZRAM_BACKEND_ZSTD=y -CONFIG_ZRAM_BACKEND_DEFLATE=y -CONFIG_ZRAM_BACKEND_842=y -CONFIG_ZRAM_BACKEND_LZO=y -CONFIG_ZRAM_MULTI_COMP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_DRBD=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_ATA_OVER_ETH=m -CONFIG_XEN_BLKDEV_BACKEND=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_RBD=m -CONFIG_BLK_DEV_RNBD_CLIENT=m -CONFIG_BLK_DEV_RNBD_SERVER=m -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_HWMON=y -CONFIG_NVME_RDMA=m -CONFIG_NVME_FC=m -CONFIG_NVME_TCP=m -CONFIG_NVME_TCP_TLS=y -CONFIG_NVME_HOST_AUTH=y -CONFIG_NVME_TARGET=m -CONFIG_NVME_TARGET_DEBUGFS=y -CONFIG_NVME_TARGET_LOOP=m -CONFIG_NVME_TARGET_RDMA=m -CONFIG_NVME_TARGET_FC=m -CONFIG_NVME_TARGET_FCLOOP=m -CONFIG_NVME_TARGET_TCP=m -CONFIG_NVME_TARGET_TCP_TLS=y -CONFIG_AD525X_DPOT=m -CONFIG_AD525X_DPOT_I2C=m -CONFIG_AD525X_DPOT_SPI=m -CONFIG_DUMMY_IRQ=m -CONFIG_IBM_ASM=m -CONFIG_PHANTOM=m -CONFIG_RPMB=m -CONFIG_TI_FPC202=m -CONFIG_ICS932S401=m -CONFIG_ENCLOSURE_SERVICES=m -CONFIG_SMPRO_ERRMON=m -CONFIG_SMPRO_MISC=m -CONFIG_HP_ILO=m -CONFIG_APDS9802ALS=m -CONFIG_ISL29003=m -CONFIG_ISL29020=m -CONFIG_SENSORS_TSL2550=m -CONFIG_SENSORS_BH1770=m -CONFIG_SENSORS_APDS990X=m -CONFIG_HMC6352=m -CONFIG_DS1682=m -CONFIG_VMWARE_BALLOON=m -CONFIG_LATTICE_ECP3_CONFIG=m -CONFIG_SRAM=y -CONFIG_DW_XDATA_PCIE=m -CONFIG_XILINX_SDFEC=m -CONFIG_NTSYNC=m -CONFIG_NSM=m -CONFIG_C2PORT=m -CONFIG_C2PORT_DURAMAR_2150=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_EEPROM_MAX6875=m -CONFIG_EEPROM_93XX46=m -CONFIG_EEPROM_IDT_89HPESX=m -CONFIG_EEPROM_EE1004=m -CONFIG_SENSORS_LIS3_I2C=m -CONFIG_INTEL_MEI=m -CONFIG_INTEL_MEI_GSC=m -CONFIG_INTEL_MEI_VSC_HW=m -CONFIG_INTEL_MEI_VSC=m -CONFIG_INTEL_MEI_GSC_PROXY=m -CONFIG_VMWARE_VMCI=m -CONFIG_GENWQE=m -CONFIG_BCM_VK=m -CONFIG_BCM_VK_TTY=y -CONFIG_MISC_ALCOR_PCI=m -CONFIG_MISC_RTSX_PCI=m -CONFIG_MISC_RTSX_USB=m -CONFIG_UACCE=m -CONFIG_PVPANIC=y -CONFIG_PVPANIC_MMIO=m -CONFIG_PVPANIC_PCI=m -CONFIG_GP_PCI1XXXX=m -CONFIG_KEBA_CP500=m -CONFIG_KEBA_LAN9252=m -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_ENCLOSURE=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_SAS_ATA=y -CONFIG_ISCSI_TCP=m -CONFIG_SCSI_CXGB3_ISCSI=m -CONFIG_SCSI_CXGB4_ISCSI=m -CONFIG_SCSI_BNX2_ISCSI=m -CONFIG_SCSI_BNX2X_FCOE=m -CONFIG_BE2ISCSI=m -CONFIG_BLK_DEV_3W_XXXX_RAID=m -CONFIG_SCSI_HPSA=m -CONFIG_SCSI_3W_9XXX=m -CONFIG_SCSI_3W_SAS=m -CONFIG_SCSI_ACARD=m -CONFIG_SCSI_AACRAID=m -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 -# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -CONFIG_SCSI_AIC79XX=m -# CONFIG_AIC79XX_DEBUG_ENABLE is not set -CONFIG_SCSI_AIC94XX=m -# CONFIG_AIC94XX_DEBUG is not set -CONFIG_SCSI_MVSAS=m -# CONFIG_SCSI_MVSAS_DEBUG is not set -CONFIG_SCSI_MVUMI=m -CONFIG_SCSI_ADVANSYS=m -CONFIG_SCSI_ARCMSR=m -CONFIG_SCSI_ESAS2R=m -CONFIG_MEGARAID_NEWGEN=y -CONFIG_MEGARAID_MM=m -CONFIG_MEGARAID_MAILBOX=m -CONFIG_MEGARAID_LEGACY=m -CONFIG_MEGARAID_SAS=m -CONFIG_SCSI_MPT2SAS=m -CONFIG_SCSI_MPI3MR=m -CONFIG_SCSI_SMARTPQI=m -CONFIG_SCSI_HPTIOP=m -CONFIG_SCSI_BUSLOGIC=m -CONFIG_SCSI_FLASHPOINT=y -CONFIG_SCSI_MYRB=m -CONFIG_SCSI_MYRS=m -CONFIG_VMWARE_PVSCSI=m -CONFIG_XEN_SCSI_FRONTEND=m -CONFIG_LIBFC=m -CONFIG_LIBFCOE=m -CONFIG_FCOE=m -CONFIG_FCOE_FNIC=m -CONFIG_SCSI_SNIC=m -CONFIG_SCSI_DMX3191D=m -CONFIG_SCSI_FDOMAIN_PCI=m -CONFIG_SCSI_ISCI=m -CONFIG_SCSI_IPS=m -CONFIG_SCSI_INITIO=m -CONFIG_SCSI_INIA100=m -CONFIG_SCSI_PPA=m -CONFIG_SCSI_IMM=m -CONFIG_SCSI_STEX=m -CONFIG_SCSI_SYM53C8XX_2=m -CONFIG_SCSI_IPR=m -CONFIG_SCSI_QLOGIC_1280=m -CONFIG_SCSI_QLA_FC=m -CONFIG_TCM_QLA2XXX=m -CONFIG_SCSI_QLA_ISCSI=m -CONFIG_QEDI=m -CONFIG_QEDF=m -CONFIG_SCSI_LPFC=m -CONFIG_SCSI_EFCT=m -CONFIG_SCSI_DC395x=m -CONFIG_SCSI_AM53C974=m -CONFIG_SCSI_WD719X=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_PMCRAID=m -CONFIG_SCSI_PM8001=m -CONFIG_SCSI_BFA_FC=m -CONFIG_SCSI_VIRTIO=m -CONFIG_SCSI_CHELSIO_FCOE=m -CONFIG_SCSI_LOWLEVEL_PCMCIA=y -CONFIG_PCMCIA_AHA152X=m -CONFIG_PCMCIA_FDOMAIN=m -CONFIG_PCMCIA_QLOGIC=m -CONFIG_PCMCIA_SYM53C500=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=m -CONFIG_SCSI_DH_HP_SW=m -CONFIG_SCSI_DH_EMC=m -CONFIG_SCSI_DH_ALUA=m -CONFIG_ATA=y -CONFIG_SATA_ZPODD=y -CONFIG_SATA_AHCI=m -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=m -CONFIG_AHCI_DWC=m -CONFIG_SATA_INIC162X=m -CONFIG_SATA_ACARD_AHCI=m -CONFIG_SATA_SIL24=m -CONFIG_PDC_ADMA=m -CONFIG_SATA_QSTOR=m -CONFIG_SATA_SX4=m -CONFIG_ATA_PIIX=y -CONFIG_SATA_DWC=m -CONFIG_SATA_MV=m -CONFIG_SATA_NV=m -CONFIG_SATA_PROMISE=m -CONFIG_SATA_SIL=m -CONFIG_SATA_SIS=m -CONFIG_SATA_SVW=m -CONFIG_SATA_ULI=m -CONFIG_SATA_VIA=m -CONFIG_SATA_VITESSE=m -CONFIG_PATA_ALI=m -CONFIG_PATA_AMD=m -CONFIG_PATA_ARTOP=m -CONFIG_PATA_ATIIXP=m -CONFIG_PATA_ATP867X=m -CONFIG_PATA_CMD64X=m -CONFIG_PATA_CYPRESS=m -CONFIG_PATA_EFAR=m -CONFIG_PATA_HPT366=m -CONFIG_PATA_HPT37X=m -CONFIG_PATA_HPT3X2N=m -CONFIG_PATA_HPT3X3=m -CONFIG_PATA_IT8213=m -CONFIG_PATA_IT821X=m -CONFIG_PATA_JMICRON=m -CONFIG_PATA_MARVELL=m -CONFIG_PATA_NETCELL=m -CONFIG_PATA_NINJA32=m -CONFIG_PATA_NS87415=m -CONFIG_PATA_OLDPIIX=m -CONFIG_PATA_OPTIDMA=m -CONFIG_PATA_PDC2027X=m -CONFIG_PATA_PDC_OLD=m -CONFIG_PATA_RADISYS=m -CONFIG_PATA_RDC=m -CONFIG_PATA_SCH=m -CONFIG_PATA_SERVERWORKS=m -CONFIG_PATA_SIL680=m -CONFIG_PATA_SIS=y -CONFIG_PATA_TOSHIBA=m -CONFIG_PATA_TRIFLEX=m -CONFIG_PATA_VIA=m -CONFIG_PATA_WINBOND=m -CONFIG_PATA_CMD640_PCI=m -CONFIG_PATA_MPIIX=m -CONFIG_PATA_NS87410=m -CONFIG_PATA_OPTI=m -CONFIG_PATA_PCMCIA=m -CONFIG_PATA_RZ1000=m -CONFIG_PATA_PARPORT=m -CONFIG_PATA_PARPORT_ATEN=m -CONFIG_PATA_PARPORT_BPCK=m -CONFIG_PATA_PARPORT_BPCK6=m -CONFIG_PATA_PARPORT_COMM=m -CONFIG_PATA_PARPORT_DSTR=m -CONFIG_PATA_PARPORT_FIT2=m -CONFIG_PATA_PARPORT_FIT3=m -CONFIG_PATA_PARPORT_EPAT=m -CONFIG_PATA_PARPORT_EPATC8=y -CONFIG_PATA_PARPORT_EPIA=m -CONFIG_PATA_PARPORT_FRIQ=m -CONFIG_PATA_PARPORT_FRPW=m -CONFIG_PATA_PARPORT_KBIC=m -CONFIG_PATA_PARPORT_KTTI=m -CONFIG_PATA_PARPORT_ON20=m -CONFIG_PATA_PARPORT_ON26=m -CONFIG_PATA_ACPI=m -CONFIG_ATA_GENERIC=y -CONFIG_PATA_LEGACY=m -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_LINEAR=m -CONFIG_MD_CLUSTER=m -CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=y -CONFIG_DM_UNSTRIPED=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_THIN_PROVISIONING=m -CONFIG_DM_CACHE=m -CONFIG_DM_WRITECACHE=m -CONFIG_DM_ERA=m -CONFIG_DM_CLONE=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_MULTIPATH_HST=m -CONFIG_DM_MULTIPATH_IOA=m -CONFIG_DM_DELAY=m -CONFIG_DM_DUST=m -CONFIG_DM_UEVENT=y -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m -CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y -CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_DM_INTEGRITY=m -CONFIG_DM_ZONED=m -CONFIG_DM_VDO=m -CONFIG_TARGET_CORE=m -CONFIG_TCM_IBLOCK=m -CONFIG_TCM_FILEIO=m -CONFIG_TCM_PSCSI=m -CONFIG_TCM_USER2=m -CONFIG_LOOPBACK_TARGET=m -CONFIG_TCM_FC=m -CONFIG_ISCSI_TARGET=m -CONFIG_ISCSI_TARGET_CXGB4=m -CONFIG_SBP_TARGET=m -CONFIG_REMOTE_TARGET=m -CONFIG_FUSION=y -CONFIG_FUSION_SPI=m -CONFIG_FUSION_FC=m -CONFIG_FUSION_SAS=m -CONFIG_FUSION_CTL=m -CONFIG_FUSION_LAN=m -CONFIG_FUSION_LOGGING=y -CONFIG_FIREWIRE=m -CONFIG_FIREWIRE_OHCI=m -CONFIG_FIREWIRE_SBP2=m -CONFIG_FIREWIRE_NET=m -CONFIG_FIREWIRE_NOSY=m -CONFIG_MACINTOSH_DRIVERS=y -CONFIG_MAC_EMUMOUSEBTN=m -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -CONFIG_OVPN=y -CONFIG_EQUALIZER=m -CONFIG_NET_FC=y -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN=m -CONFIG_IPVTAP=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_BAREUDP=m -CONFIG_GTP=m -CONFIG_PFCP=m -CONFIG_AMT=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NTB_NETDEV=m -CONFIG_RIONET=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NLMON=m -CONFIG_NET_VRF=m -CONFIG_VSOCKMON=m -CONFIG_MHI_NET=m -CONFIG_ARCNET=m -CONFIG_ARCNET_1201=m -CONFIG_ARCNET_1051=m -CONFIG_ARCNET_RAW=m -CONFIG_ARCNET_CAP=m -CONFIG_ARCNET_COM90xx=m -CONFIG_ARCNET_COM90xxIO=m -CONFIG_ARCNET_RIM_I=m -CONFIG_ARCNET_COM20020=m -CONFIG_ARCNET_COM20020_PCI=m -CONFIG_ARCNET_COM20020_CS=m -CONFIG_ATM_DUMMY=m -CONFIG_ATM_TCP=m -CONFIG_ATM_LANAI=m -CONFIG_ATM_ENI=m -CONFIG_ATM_NICSTAR=m -CONFIG_ATM_IDT77252=m -CONFIG_ATM_IA=m -CONFIG_ATM_FORE200E=m -CONFIG_ATM_HE=m -CONFIG_ATM_HE_USE_SUNI=y -CONFIG_ATM_SOLOS=m -CONFIG_CAIF_DRIVERS=y -CONFIG_CAIF_TTY=m -CONFIG_CAIF_VIRTIO=m -CONFIG_B53_SPI_DRIVER=m -CONFIG_B53_MDIO_DRIVER=m -CONFIG_B53_MMAP_DRIVER=m -CONFIG_B53_SRAB_DRIVER=m -CONFIG_B53_SERDES=m -CONFIG_NET_DSA_BCM_SF2=m -CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m -CONFIG_NET_DSA_LANTIQ_GSWIP=m -CONFIG_NET_DSA_MT7530=m -CONFIG_NET_DSA_MV88E6060=m -CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m -CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m -CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y -CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m -CONFIG_NET_DSA_MV88E6XXX=m -CONFIG_NET_DSA_MV88E6XXX_PTP=y -CONFIG_NET_DSA_MSCC_OCELOT_EXT=m -CONFIG_NET_DSA_MSCC_SEVILLE=m -CONFIG_NET_DSA_AR9331=m -CONFIG_NET_DSA_QCA8K=m -CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y -CONFIG_NET_DSA_SJA1105=m -CONFIG_NET_DSA_SJA1105_PTP=y -CONFIG_NET_DSA_XRS700X_I2C=m -CONFIG_NET_DSA_XRS700X_MDIO=m -CONFIG_NET_DSA_REALTEK=m -CONFIG_NET_DSA_SMSC_LAN9303_I2C=m -CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m -CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m -CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m -CONFIG_PCMCIA_3C574=m -CONFIG_PCMCIA_3C589=m -CONFIG_VORTEX=m -CONFIG_TYPHOON=m -CONFIG_ADAPTEC_STARFIRE=m -CONFIG_ET131X=m -CONFIG_SLICOSS=m -CONFIG_ACENIC=m -CONFIG_ALTERA_TSE=m -CONFIG_ENA_ETHERNET=m -CONFIG_AMD8111_ETH=m -CONFIG_PCNET32=m -CONFIG_PCMCIA_NMCLAN=m -CONFIG_AMD_XGBE=m -CONFIG_PDS_CORE=m -CONFIG_AQTION=m -CONFIG_SPI_AX88796C=m -CONFIG_SPI_AX88796C_COMPRESSION=y -CONFIG_ATL2=m -CONFIG_ATL1=m -CONFIG_ATL1E=m -CONFIG_ATL1C=m -CONFIG_ALX=m -CONFIG_CX_ECAT=m -CONFIG_B44=m -CONFIG_BCMGENET=m -CONFIG_TIGON3=m -CONFIG_BNX2X=m -CONFIG_BNXT=m -CONFIG_BNGE=y -CONFIG_MACB=m -CONFIG_MACB_PCI=m -CONFIG_THUNDER_NIC_PF=m -CONFIG_THUNDER_NIC_VF=m -CONFIG_LIQUIDIO=m -CONFIG_LIQUIDIO_VF=m -CONFIG_CHELSIO_T1=m -CONFIG_CHELSIO_T1_1G=y -CONFIG_CHELSIO_T4_DCB=y -CONFIG_CHELSIO_T4_FCOE=y -CONFIG_CHELSIO_T4VF=m -# CONFIG_NET_VENDOR_CORTINA is not set -CONFIG_DM9051=m -CONFIG_DNET=m -CONFIG_NET_TULIP=y -CONFIG_DE2104X=m -CONFIG_TULIP=m -CONFIG_WINBOND_840=m -CONFIG_DM9102=m -CONFIG_ULI526X=m -CONFIG_PCMCIA_XIRCOM=m -CONFIG_DL2K=m -CONFIG_TSNEP=m -CONFIG_PCMCIA_FMVJ18X=m -CONFIG_FUN_ETH=m -CONFIG_GVE=m -CONFIG_HIBMCGE=m -CONFIG_HINIC=m -CONFIG_HINIC3=m -CONFIG_E100=m -CONFIG_E1000=m -CONFIG_E1000E=m -CONFIG_IGB=m -CONFIG_IGBVF=m -CONFIG_IXGBE=m -CONFIG_IXGBE_DCB=y -CONFIG_IXGBEVF=m -CONFIG_I40E=m -CONFIG_I40E_DCB=y -CONFIG_I40EVF=m -CONFIG_ICE=m -CONFIG_FM10K=m -CONFIG_IGC=m -CONFIG_IDPF=m -CONFIG_JME=m -CONFIG_ADIN1110=m -CONFIG_MVMDIO=m -CONFIG_SKGE=m -CONFIG_SKGE_GENESIS=y -CONFIG_SKY2=m -CONFIG_OCTEON_EP=m -CONFIG_PRESTERA=m -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_EN_IPSEC=y -CONFIG_MLX5_SF=y -CONFIG_MLX5_DPLL=m -CONFIG_MLXSW_CORE=m -CONFIG_FBNIC=m -CONFIG_KS8842=m -CONFIG_KS8851=m -CONFIG_KS8851_MLL=m -CONFIG_KSZ884X_PCI=m -CONFIG_ENC28J60=m -CONFIG_ENCX24J600=m -CONFIG_LAN743X=m -CONFIG_LAN865X=m -CONFIG_VCAP=y -CONFIG_MYRI10GE=m -CONFIG_FEALNX=m -CONFIG_NI_XGE_MANAGEMENT_ENET=m -CONFIG_NATSEMI=m -CONFIG_NS83820=m -CONFIG_S2IO=m -CONFIG_NFP=m -# CONFIG_NFP_APP_FLOWER is not set -CONFIG_PCMCIA_AXNET=m -CONFIG_NE2K_PCI=m -CONFIG_PCMCIA_PCNET=m -CONFIG_FORCEDETH=m -CONFIG_ETHOC=m -CONFIG_HAMACHI=m -CONFIG_YELLOWFIN=m -CONFIG_IONIC=m -CONFIG_QLA3XXX=m -CONFIG_QLCNIC=m -CONFIG_NETXEN_NIC=m -CONFIG_QED=m -CONFIG_QEDE=m -CONFIG_BNA=m -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_R6040=m -CONFIG_ATP=m -CONFIG_8139CP=m -CONFIG_8139TOO=m -CONFIG_8139TOO_8129=y -CONFIG_R8169=m -CONFIG_R8169_LEDS=y -CONFIG_RTASE=m -CONFIG_ROCKER=m -CONFIG_SXGBE_ETH=m -CONFIG_SC92031=m -CONFIG_SIS900=m -CONFIG_SIS190=m -CONFIG_SFC=m -CONFIG_SFC_FALCON=m -CONFIG_SFC_SIENA=m -CONFIG_SFC_SIENA_SRIOV=y -CONFIG_PCMCIA_SMC91C92=m -CONFIG_EPIC100=m -CONFIG_SMSC911X=m -CONFIG_SMSC9420=m -# CONFIG_NET_VENDOR_SOCIONEXT is not set -CONFIG_STMMAC_ETH=m -CONFIG_HAPPYMEAL=m -CONFIG_SUNGEM=m -CONFIG_CASSINI=m -CONFIG_NIU=m -CONFIG_DWC_XLGMAC=m -CONFIG_DWC_XLGMAC_PCI=m -CONFIG_TEHUTI=m -CONFIG_TEHUTI_TN40=m -CONFIG_TLAN=m -CONFIG_MSE102X=m -CONFIG_VIA_RHINE=m -CONFIG_VIA_RHINE_MMIO=y -CONFIG_VIA_VELOCITY=m -CONFIG_NGBE=m -CONFIG_TXGBE=m -CONFIG_TXGBEVF=m -CONFIG_NGBEVF=m -CONFIG_WIZNET_W5100=m -CONFIG_WIZNET_W5300=m -CONFIG_XILINX_EMACLITE=m -CONFIG_XILINX_AXI_EMAC=m -CONFIG_XILINX_LL_TEMAC=m -CONFIG_PCMCIA_XIRC2PS=m -CONFIG_FDDI=y -CONFIG_DEFXX=m -CONFIG_SKFP=m -CONFIG_PHYLIB=y -CONFIG_AS21XXX_PHY=m -CONFIG_AIR_EN8811H_PHY=m -CONFIG_AMD_PHY=m -CONFIG_ADIN_PHY=m -CONFIG_ADIN1100_PHY=m -CONFIG_AQUANTIA_PHY=m -CONFIG_BROADCOM_PHY=m -CONFIG_BCM54140_PHY=m -CONFIG_BCM84881_PHY=m -CONFIG_BCM87XX_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_CORTINA_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_ICPLUS_PHY=m -CONFIG_LXT_PHY=m -CONFIG_INTEL_XWAY_PHY=m -CONFIG_LSI_ET1011C_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_88Q2XXX_PHY=m -CONFIG_MARVELL_88X2222_PHY=m -CONFIG_MAXLINEAR_GPHY=m -CONFIG_MAXLINEAR_86110_PHY=m -CONFIG_MICROCHIP_T1S_PHY=m -CONFIG_MICROCHIP_T1_PHY=m -CONFIG_MICROSEMI_PHY=m -CONFIG_NATIONAL_PHY=m -CONFIG_NXP_CBTX_PHY=m -CONFIG_NXP_C45_TJA11XX_PHY=m -CONFIG_NXP_TJA11XX_PHY=m -CONFIG_NCN26000_PHY=m -CONFIG_AT803X_PHY=m -CONFIG_QCA83XX_PHY=m -CONFIG_QCA808X_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_REALTEK_PHY_HWMON=y -CONFIG_RENESAS_PHY=m -CONFIG_ROCKCHIP_PHY=m -CONFIG_STE10XP=m -CONFIG_TERANETICS_PHY=m -CONFIG_DP83822_PHY=m -CONFIG_DP83TC811_PHY=m -CONFIG_DP83848_PHY=m -CONFIG_DP83867_PHY=m -CONFIG_DP83869_PHY=m -CONFIG_DP83TD510_PHY=m -CONFIG_DP83TG720_PHY=m -CONFIG_XILINX_GMII2RGMII=m -CONFIG_PSE_CONTROLLER=y -CONFIG_PSE_REGULATOR=m -CONFIG_PSE_PD692X0=m -CONFIG_PSE_TPS23881=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_CAN327=m -CONFIG_CAN_JANZ_ICAN3=m -CONFIG_CAN_KVASER_PCIEFD=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_PLATFORM=m -CONFIG_CAN_CTUCANFD_PCI=m -CONFIG_CAN_IFI_CANFD=m -CONFIG_CAN_M_CAN=m -CONFIG_CAN_M_CAN_PCI=m -CONFIG_CAN_M_CAN_PLATFORM=m -CONFIG_CAN_M_CAN_TCAN4X5X=m -CONFIG_CAN_PEAK_PCIEFD=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_EMS_PCMCIA=m -CONFIG_CAN_F81601=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PEAK_PCMCIA=m -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m -CONFIG_CAN_SOFTING_CS=m -CONFIG_CAN_HI311X=m -CONFIG_CAN_MCP251X=m -CONFIG_CAN_MCP251XFD=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB=m -CONFIG_CAN_ETAS_ES58X=m -CONFIG_CAN_F81604=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -CONFIG_MCTP_SERIAL=m -CONFIG_MCTP_TRANSPORT_I2C=m -CONFIG_MCTP_TRANSPORT_USB=m -CONFIG_MDIO_GPIO=m -CONFIG_MDIO_MVUSB=m -CONFIG_PLIP=m -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOATM=m -CONFIG_PPPOE=m -CONFIG_PPTP=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_USB_NET_DRIVERS=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_CDC_PHONET=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -CONFIG_USB_NET_AQC111=m -CONFIG_ADM8211=m -CONFIG_ATH5K=m -CONFIG_ATH9K=m -CONFIG_ATH9K_AHB=y -CONFIG_ATH9K_DEBUGFS=y -CONFIG_ATH9K_STATION_STATISTICS=y -CONFIG_ATH9K_WOW=y -CONFIG_ATH9K_CHANNEL_CONTEXT=y -CONFIG_ATH9K_PCI_NO_EEPROM=m -CONFIG_ATH9K_HTC=m -CONFIG_ATH9K_HTC_DEBUGFS=y -CONFIG_ATH9K_HWRNG=y -CONFIG_CARL9170=m -CONFIG_CARL9170_HWRNG=y -CONFIG_ATH6KL=m -CONFIG_ATH6KL_SDIO=m -CONFIG_ATH6KL_USB=m -CONFIG_AR5523=m -CONFIG_WIL6210=m -CONFIG_WIL6210_TRACING=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_SDIO=m -CONFIG_ATH10K_USB=m -CONFIG_ATH10K_DEBUGFS=y -CONFIG_ATH10K_TRACING=y -CONFIG_WCN36XX=m -CONFIG_ATH11K=m -CONFIG_ATH11K_PCI=m -CONFIG_ATH12K=m -CONFIG_AT76C50X_USB=m -CONFIG_B43=m -CONFIG_B43LEGACY=m -# CONFIG_B43LEGACY_DEBUG is not set -CONFIG_BRCMSMAC=m -CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_USB=y -CONFIG_BRCMFMAC_PCIE=y -CONFIG_BRCM_TRACING=y -CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -CONFIG_IWL4965=m -CONFIG_IWL3945=m -CONFIG_IWLEGACY_DEBUGFS=y -CONFIG_IWLWIFI=m -CONFIG_IWLDVM=m -CONFIG_IWLMVM=m -CONFIG_IWLMLD=m -CONFIG_IWLWIFI_DEBUGFS=y -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -CONFIG_P54_PCI=m -CONFIG_P54_SPI=m -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -CONFIG_LIBERTAS_MESH=y -CONFIG_LIBERTAS_THINFIRM=m -CONFIG_LIBERTAS_THINFIRM_USB=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_MWIFIEX_USB=m -CONFIG_MWL8K=m -CONFIG_MT7601U=m -CONFIG_MT76x2U=m -CONFIG_MT7921E=m -CONFIG_MT7925E=m -CONFIG_MT7925U=m -CONFIG_WILC1000_SDIO=m -CONFIG_WILC1000_SPI=m -CONFIG_PLFXLC=m -CONFIG_RT2X00=m -CONFIG_RT2400PCI=m -CONFIG_RT2500PCI=m -CONFIG_RT61PCI=m -CONFIG_RT2800PCI=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT3573=y -CONFIG_RT2800USB_RT53XX=y -CONFIG_RT2800USB_RT55XX=y -CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RTL8180=m -CONFIG_RTL8187=m -CONFIG_RTL8192CE=m -CONFIG_RTL8192SE=m -CONFIG_RTL8192DE=m -CONFIG_RTL8723AE=m -CONFIG_RTL8723BE=m -CONFIG_RTL8188EE=m -CONFIG_RTL8192EE=m -CONFIG_RTL8821AE=m -CONFIG_RTL8192CU=m -CONFIG_RTL8192DU=m -# CONFIG_RTLWIFI_DEBUG is not set -CONFIG_RTL8XXXU=m -CONFIG_RTL8XXXU_UNTESTED=y -CONFIG_RTW88=m -CONFIG_RTW88_8822BE=m -CONFIG_RTW88_8822BS=m -CONFIG_RTW88_8822BU=m -CONFIG_RTW88_8822CE=m -CONFIG_RTW88_8822CS=m -CONFIG_RTW88_8822CU=m -CONFIG_RTW88_8723DE=m -CONFIG_RTW88_8723DS=m -CONFIG_RTW88_8723CS=m -CONFIG_RTW88_8723DU=m -CONFIG_RTW88_8821CE=m -CONFIG_RTW88_8821CS=m -CONFIG_RTW88_8821CU=m -CONFIG_RTW88_8821AU=m -CONFIG_RTW88_8812AU=m -CONFIG_RTW88_8814AE=m -CONFIG_RTW88_8814AU=m -CONFIG_RTW89=m -CONFIG_RTW89_8851BE=m -CONFIG_RTW89_8851BU=m -CONFIG_RTW89_8852AE=m -CONFIG_RTW89_8852BE=m -CONFIG_RTW89_8852BU=m -CONFIG_RTW89_8852BTE=m -CONFIG_RTW89_8852CE=m -CONFIG_RTW89_8922AE=m -CONFIG_RSI_91X=m -# CONFIG_RSI_DEBUGFS is not set -CONFIG_WFX=m -CONFIG_CW1200=m -CONFIG_CW1200_WLAN_SDIO=m -CONFIG_CW1200_WLAN_SPI=m -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL12XX=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_ZD1211RW=m -CONFIG_QTNFMAC_PCIE=m -CONFIG_MAC80211_HWSIM=m -CONFIG_VIRT_WIFI=m -CONFIG_WAN=y -CONFIG_HDLC=m -CONFIG_HDLC_RAW=m -CONFIG_HDLC_RAW_ETH=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_X25=m -CONFIG_FRAMER=m -CONFIG_PCI200SYN=m -CONFIG_WANXL=m -CONFIG_PC300TOO=m -CONFIG_FARSYNC=m -CONFIG_LAPBETHER=m -CONFIG_IEEE802154_FAKELB=m -CONFIG_IEEE802154_AT86RF230=m -CONFIG_IEEE802154_MRF24J40=m -CONFIG_IEEE802154_CC2520=m -CONFIG_IEEE802154_ATUSB=m -CONFIG_IEEE802154_ADF7242=m -CONFIG_IEEE802154_CA8210=m -CONFIG_IEEE802154_MCR20A=m -CONFIG_WWAN=y -# CONFIG_WWAN_DEBUGFS is not set -CONFIG_MHI_WWAN_CTRL=m -CONFIG_MHI_WWAN_MBIM=m -CONFIG_RPMSG_WWAN_CTRL=m -CONFIG_IOSM=m -CONFIG_MTK_T7XX=m -CONFIG_XEN_NETDEV_BACKEND=m -CONFIG_VMXNET3=m -CONFIG_FUJITSU_ES=m -CONFIG_USB4_NET=m -CONFIG_NETDEVSIM=m -CONFIG_ISDN=y -CONFIG_MISDN=m -CONFIG_MISDN_DSP=m -CONFIG_MISDN_L1OIP=m -CONFIG_MISDN_HFCPCI=m -CONFIG_MISDN_HFCMULTI=m -CONFIG_MISDN_HFCUSB=m -CONFIG_MISDN_AVMFRITZ=m -CONFIG_MISDN_SPEEDFAX=m -CONFIG_MISDN_INFINEON=m -CONFIG_MISDN_W6692=m -CONFIG_MISDN_NETJET=m -CONFIG_INPUT_LEDS=m -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_ADP5520=m -CONFIG_KEYBOARD_ADP5588=m -CONFIG_KEYBOARD_APPLESPI=m -CONFIG_KEYBOARD_QT1050=m -CONFIG_KEYBOARD_QT1070=m -CONFIG_KEYBOARD_QT2160=m -CONFIG_KEYBOARD_DLINK_DIR685=m -CONFIG_KEYBOARD_LKKBD=m -CONFIG_KEYBOARD_GPIO=m -CONFIG_KEYBOARD_TCA8418=m -CONFIG_KEYBOARD_MATRIX=m -CONFIG_KEYBOARD_LM8323=m -CONFIG_KEYBOARD_LM8333=m -CONFIG_KEYBOARD_MAX7359=m -CONFIG_KEYBOARD_MPR121=m -CONFIG_KEYBOARD_NEWTON=m -CONFIG_KEYBOARD_OPENCORES=m -CONFIG_KEYBOARD_PINEPHONE=m -CONFIG_KEYBOARD_SAMSUNG=m -CONFIG_KEYBOARD_STOWAWAY=m -CONFIG_KEYBOARD_SUNKBD=m -CONFIG_KEYBOARD_IQS62X=m -CONFIG_KEYBOARD_TM2_TOUCHKEY=m -CONFIG_KEYBOARD_TWL4030=m -CONFIG_KEYBOARD_XTKBD=m -CONFIG_KEYBOARD_CROS_EC=m -CONFIG_KEYBOARD_MTK_PMIC=m -CONFIG_KEYBOARD_CYPRESS_SF=m -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_PS2_ELANTECH=y -CONFIG_MOUSE_PS2_SENTELIC=y -CONFIG_MOUSE_PS2_TOUCHKIT=y -CONFIG_MOUSE_PS2_VMMOUSE=y -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -CONFIG_MOUSE_CYAPA=m -CONFIG_MOUSE_ELAN_I2C=m -CONFIG_MOUSE_ELAN_I2C_SMBUS=y -CONFIG_MOUSE_VSXXXAA=m -CONFIG_MOUSE_GPIO=m -CONFIG_MOUSE_SYNAPTICS_I2C=m -CONFIG_MOUSE_SYNAPTICS_USB=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADC=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=m -CONFIG_JOYSTICK_IFORCE_232=m -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_DB9=m -CONFIG_JOYSTICK_GAMECON=m -CONFIG_JOYSTICK_TURBOGRAFX=m -CONFIG_JOYSTICK_AS5011=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y -CONFIG_JOYSTICK_WALKERA0701=m -CONFIG_JOYSTICK_PSXPAD_SPI=m -CONFIG_JOYSTICK_PXRC=m -CONFIG_JOYSTICK_QWIIC=m -CONFIG_JOYSTICK_FSIA6B=m -CONFIG_JOYSTICK_SENSEHAT=m -CONFIG_JOYSTICK_SEESAW=m -CONFIG_INPUT_TABLET=y -CONFIG_TABLET_USB_ACECAD=m -CONFIG_TABLET_USB_AIPTEK=m -CONFIG_TABLET_USB_HANWANG=m -CONFIG_TABLET_USB_KBTAB=m -CONFIG_TABLET_USB_PEGASUS=m -CONFIG_TABLET_SERIAL_WACOM4=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_88PM860X=m -CONFIG_TOUCHSCREEN_ADS7846=m -CONFIG_TOUCHSCREEN_AD7877=m -CONFIG_TOUCHSCREEN_AD7879=m -CONFIG_TOUCHSCREEN_AD7879_I2C=m -CONFIG_TOUCHSCREEN_AD7879_SPI=m -CONFIG_TOUCHSCREEN_ADC=m -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_AUO_PIXCIR=m -CONFIG_TOUCHSCREEN_BU21013=m -CONFIG_TOUCHSCREEN_BU21029=m -CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m -CONFIG_TOUCHSCREEN_CY8CTMA140=m -CONFIG_TOUCHSCREEN_CY8CTMG110=m -CONFIG_TOUCHSCREEN_CYTTSP_CORE=m -CONFIG_TOUCHSCREEN_CYTTSP_I2C=m -CONFIG_TOUCHSCREEN_CYTTSP_SPI=m -CONFIG_TOUCHSCREEN_CYTTSP5=m -CONFIG_TOUCHSCREEN_DA9034=m -CONFIG_TOUCHSCREEN_DA9052=m -CONFIG_TOUCHSCREEN_DYNAPRO=m -CONFIG_TOUCHSCREEN_HAMPSHIRE=m -CONFIG_TOUCHSCREEN_EETI=m -CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m -CONFIG_TOUCHSCREEN_EXC3000=m -CONFIG_TOUCHSCREEN_FUJITSU=m -CONFIG_TOUCHSCREEN_GOODIX=m -CONFIG_TOUCHSCREEN_HIDEEP=m -CONFIG_TOUCHSCREEN_HYCON_HY46XX=m -CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m -CONFIG_TOUCHSCREEN_ILI210X=m -CONFIG_TOUCHSCREEN_ILITEK=m -CONFIG_TOUCHSCREEN_S6SY761=m -CONFIG_TOUCHSCREEN_GUNZE=m -CONFIG_TOUCHSCREEN_EKTF2127=m -CONFIG_TOUCHSCREEN_ELAN=m -CONFIG_TOUCHSCREEN_ELO=m -CONFIG_TOUCHSCREEN_WACOM_W8001=m -CONFIG_TOUCHSCREEN_WACOM_I2C=m -CONFIG_TOUCHSCREEN_MAX11801=m -CONFIG_TOUCHSCREEN_MMS114=m -CONFIG_TOUCHSCREEN_MELFAS_MIP4=m -CONFIG_TOUCHSCREEN_MSG2638=m -CONFIG_TOUCHSCREEN_MTOUCH=m -CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m -CONFIG_TOUCHSCREEN_IMAGIS=m -CONFIG_TOUCHSCREEN_INEXIO=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -CONFIG_TOUCHSCREEN_PIXCIR=m -CONFIG_TOUCHSCREEN_WDT87XX_I2C=m -CONFIG_TOUCHSCREEN_WM831X=m -CONFIG_TOUCHSCREEN_WM97XX=m -CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -CONFIG_TOUCHSCREEN_MC13783=m -CONFIG_TOUCHSCREEN_TOUCHIT213=m -CONFIG_TOUCHSCREEN_TSC_SERIO=m -CONFIG_TOUCHSCREEN_TSC2004=m -CONFIG_TOUCHSCREEN_TSC2005=m -CONFIG_TOUCHSCREEN_TSC2007=m -CONFIG_TOUCHSCREEN_PCAP=m -CONFIG_TOUCHSCREEN_RM_TS=m -CONFIG_TOUCHSCREEN_SILEAD=m -CONFIG_TOUCHSCREEN_SIS_I2C=m -CONFIG_TOUCHSCREEN_ST1232=m -CONFIG_TOUCHSCREEN_STMFTS=m -CONFIG_TOUCHSCREEN_SUR40=m -CONFIG_TOUCHSCREEN_SURFACE3_SPI=m -CONFIG_TOUCHSCREEN_SX8654=m -CONFIG_TOUCHSCREEN_TPS6507X=m -CONFIG_TOUCHSCREEN_ZET6223=m -CONFIG_TOUCHSCREEN_ZFORCE=m -CONFIG_TOUCHSCREEN_COLIBRI_VF50=m -CONFIG_TOUCHSCREEN_ROHM_BU21023=m -CONFIG_TOUCHSCREEN_IQS5XX=m -CONFIG_TOUCHSCREEN_IQS7211=m -CONFIG_TOUCHSCREEN_ZINITIX=m -CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_88PM860X_ONKEY=m -CONFIG_INPUT_88PM80X_ONKEY=m -CONFIG_INPUT_AD714X=m -CONFIG_INPUT_ARIZONA_HAPTICS=m -CONFIG_INPUT_ATC260X_ONKEY=m -CONFIG_INPUT_BMA150=m -CONFIG_INPUT_CS40L50_VIBRA=m -CONFIG_INPUT_E3X0_BUTTON=m -CONFIG_INPUT_PCSPKR=m -CONFIG_INPUT_MAX77693_HAPTIC=m -CONFIG_INPUT_MAX8925_ONKEY=m -CONFIG_INPUT_MAX8997_HAPTIC=m -CONFIG_INPUT_MC13783_PWRBUTTON=m -CONFIG_INPUT_MMA8450=m -CONFIG_INPUT_APANEL=m -CONFIG_INPUT_GPIO_BEEPER=m -CONFIG_INPUT_GPIO_DECODER=m -CONFIG_INPUT_GPIO_VIBRA=m -CONFIG_INPUT_ATLAS_BTNS=m -CONFIG_INPUT_ATI_REMOTE2=m -CONFIG_INPUT_KEYSPAN_REMOTE=m -CONFIG_INPUT_KXTJ9=m -CONFIG_INPUT_POWERMATE=m -CONFIG_INPUT_YEALINK=m -CONFIG_INPUT_CM109=m -CONFIG_INPUT_REGULATOR_HAPTIC=m -CONFIG_INPUT_RETU_PWRBUTTON=m -CONFIG_INPUT_AXP20X_PEK=m -CONFIG_INPUT_TWL4030_PWRBUTTON=m -CONFIG_INPUT_TWL4030_VIBRA=m -CONFIG_INPUT_TWL6040_VIBRA=m -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_PALMAS_PWRBUTTON=m -CONFIG_INPUT_PCF8574=m -CONFIG_INPUT_PWM_BEEPER=m -CONFIG_INPUT_PWM_VIBRA=m -CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -CONFIG_INPUT_DA7280_HAPTICS=m -CONFIG_INPUT_DA9052_ONKEY=m -CONFIG_INPUT_DA9055_ONKEY=m -CONFIG_INPUT_DA9063_ONKEY=m -CONFIG_INPUT_WM831X_ON=m -CONFIG_INPUT_PCAP=m -CONFIG_INPUT_ADXL34X=m -CONFIG_INPUT_IBM_PANEL=m -CONFIG_INPUT_IMS_PCU=m -CONFIG_INPUT_IQS269A=m -CONFIG_INPUT_IQS626A=m -CONFIG_INPUT_IQS7222=m -CONFIG_INPUT_CMA3000=m -CONFIG_INPUT_CMA3000_I2C=m -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m -CONFIG_INPUT_IDEAPAD_SLIDEBAR=m -CONFIG_INPUT_SOC_BUTTON_ARRAY=m -CONFIG_INPUT_DRV260X_HAPTICS=m -CONFIG_INPUT_DRV2665_HAPTICS=m -CONFIG_INPUT_DRV2667_HAPTICS=m -CONFIG_INPUT_QNAP_MCU=m -CONFIG_INPUT_RAVE_SP_PWRBUTTON=m -CONFIG_INPUT_RT5120_PWRKEY=m -CONFIG_RMI4_I2C=m -CONFIG_RMI4_SPI=m -CONFIG_RMI4_SMB=m -CONFIG_RMI4_F1A=y -CONFIG_RMI4_F21=y -CONFIG_RMI4_F55=y -CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_CT82C710=m -CONFIG_SERIO_PARKBD=m -CONFIG_SERIO_PCIPS2=m -CONFIG_SERIO_RAW=m -CONFIG_SERIO_ALTERA_PS2=m -CONFIG_SERIO_PS2MULT=m -CONFIG_SERIO_ARC_PS2=m -CONFIG_SERIO_GPIO_PS2=m -CONFIG_USERIO=m -CONFIG_GAMEPORT_EMU10K1=m -CONFIG_GAMEPORT_FM801=m -CONFIG_LEGACY_PTY_COUNT=0 -# CONFIG_LEGACY_TIOCSTI is not set -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXAR=m -CONFIG_SERIAL_8250_CS=m -CONFIG_SERIAL_8250_MEN_MCB=m -CONFIG_SERIAL_8250_NR_UARTS=48 -CONFIG_SERIAL_8250_RUNTIME_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_PCI1XXXX=m -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DFL=m -CONFIG_SERIAL_8250_DW=m -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_8250_LPSS=m -CONFIG_SERIAL_8250_MID=m -CONFIG_SERIAL_8250_PERICOM=m -CONFIG_SERIAL_8250_NI=m -CONFIG_SERIAL_MAX3100=m -CONFIG_SERIAL_MAX310X=y -CONFIG_SERIAL_UARTLITE=m -CONFIG_SERIAL_JSM=m -CONFIG_SERIAL_LANTIQ=m -CONFIG_SERIAL_SCCNXP=y -CONFIG_SERIAL_SCCNXP_CONSOLE=y -CONFIG_SERIAL_SC16IS7XX=m -CONFIG_SERIAL_ALTERA_JTAGUART=m -CONFIG_SERIAL_ALTERA_UART=m -CONFIG_SERIAL_ARC=m -CONFIG_SERIAL_RP2=m -CONFIG_SERIAL_FSL_LPUART=m -CONFIG_SERIAL_FSL_LINFLEXUART=m -CONFIG_SERIAL_MEN_Z135=m -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_MOXA_INTELLIO=m -CONFIG_MOXA_SMARTIO=m -CONFIG_N_HDLC=m -CONFIG_IPWIRELESS=m -CONFIG_N_GSM=m -CONFIG_NOZOMI=m -CONFIG_NULL_TTY=m -CONFIG_RPMSG_TTY=m -CONFIG_SERIAL_DEV_BUS=y -CONFIG_TTY_PRINTK=y -CONFIG_PRINTER=m -CONFIG_PPDEV=m -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SSIF=m -CONFIG_IPMI_IPMB=m -CONFIG_IPMI_WATCHDOG=m -CONFIG_IPMI_POWEROFF=m -CONFIG_SSIF_IPMI_BMC=m -CONFIG_IPMB_DEVICE_INTERFACE=m -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=m -CONFIG_HW_RANDOM_INTEL=m -CONFIG_HW_RANDOM_AMD=m -CONFIG_HW_RANDOM_BA431=m -CONFIG_HW_RANDOM_VIA=m -CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_HW_RANDOM_XIPHERA=m -CONFIG_APPLICOM=m -CONFIG_MWAVE=m -CONFIG_HPET=y -CONFIG_HANGCHECK_TIMER=m -CONFIG_TCG_TPM2_HMAC=y -CONFIG_TCG_TIS_SPI=m -CONFIG_TCG_TIS_I2C=m -CONFIG_TCG_TIS_I2C_ATMEL=m -CONFIG_TCG_TIS_I2C_INFINEON=m -CONFIG_TCG_TIS_I2C_NUVOTON=m -CONFIG_TCG_NSC=m -CONFIG_TCG_ATMEL=m -CONFIG_TCG_INFINEON=m -CONFIG_TCG_XEN=m -CONFIG_TCG_VTPM_PROXY=m -CONFIG_TCG_TIS_ST33ZP24_I2C=m -CONFIG_TCG_TIS_ST33ZP24_SPI=m -CONFIG_TELCLOCK=m -CONFIG_XILLYBUS=m -CONFIG_XILLYBUS_PCIE=m -CONFIG_XILLYUSB=m -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX_GPIO=m -CONFIG_I2C_MUX_LTC4306=m -CONFIG_I2C_MUX_PCA9541=m -CONFIG_I2C_MUX_PCA954x=m -CONFIG_I2C_MUX_REG=m -CONFIG_I2C_MUX_MLXCPLD=m -CONFIG_I2C_ALI1535=m -CONFIG_I2C_ALI1563=m -CONFIG_I2C_ALI15X3=m -CONFIG_I2C_AMD756=m -CONFIG_I2C_AMD8111=m -CONFIG_I2C_AMD_MP2=m -CONFIG_I2C_AMD_ASF=m -CONFIG_I2C_I801=m -CONFIG_I2C_ISCH=m -CONFIG_I2C_ISMT=m -CONFIG_I2C_PIIX4=m -CONFIG_I2C_CHT_WC=m -CONFIG_I2C_NFORCE2=m -CONFIG_I2C_NVIDIA_GPU=m -CONFIG_I2C_SIS5595=m -CONFIG_I2C_SIS630=m -CONFIG_I2C_SIS96X=m -CONFIG_I2C_VIA=m -CONFIG_I2C_VIAPRO=m -CONFIG_I2C_ZHAOXIN=m -CONFIG_I2C_SCMI=m -CONFIG_I2C_CBUS_GPIO=m -CONFIG_I2C_CGBC=m -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_AMDISP=m -CONFIG_I2C_DESIGNWARE_BAYTRAIL=y -CONFIG_I2C_DESIGNWARE_PCI=m -CONFIG_I2C_EMEV2=m -CONFIG_I2C_GPIO=m -CONFIG_I2C_KEBA=m -CONFIG_I2C_KEMPLD=m -CONFIG_I2C_OCORES=m -CONFIG_I2C_PCA_PLATFORM=m -CONFIG_I2C_SIMTEC=m -CONFIG_I2C_DIOLAN_U2C=m -CONFIG_I2C_DLN2=m -CONFIG_I2C_CP2615=m -CONFIG_I2C_PARPORT=m -CONFIG_I2C_PCI1XXXX=m -CONFIG_I2C_ROBOTFUZZ_OSIF=m -CONFIG_I2C_TAOS_EVM=m -CONFIG_I2C_TINY_USB=m -CONFIG_I2C_VIPERBOARD=m -CONFIG_I2C_MLXCPLD=m -CONFIG_I2C_VIRTIO=m -CONFIG_I2C_STUB=m -CONFIG_I2C_SLAVE_EEPROM=m -CONFIG_I3C=m -CONFIG_CDNS_I3C_MASTER=m -CONFIG_DW_I3C_MASTER=m -CONFIG_SVC_I3C_MASTER=m -CONFIG_SPI=y -CONFIG_SPI_ALTERA=m -CONFIG_SPI_ALTERA_DFL=m -CONFIG_SPI_AXI_SPI_ENGINE=m -CONFIG_SPI_BUTTERFLY=m -CONFIG_SPI_CADENCE=m -CONFIG_SPI_CH341=m -CONFIG_SPI_DESIGNWARE=m -CONFIG_SPI_DW_PCI=m -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_DLN2=m -CONFIG_SPI_GPIO=m -CONFIG_SPI_KSPI2=m -CONFIG_SPI_LM70_LLP=m -CONFIG_SPI_MICROCHIP_CORE_QSPI=m -CONFIG_SPI_LANTIQ_SSC=m -CONFIG_SPI_OC_TINY=m -CONFIG_SPI_PCI1XXXX=m -CONFIG_SPI_SC18IS602=m -CONFIG_SPI_SIFIVE=m -CONFIG_SPI_MXIC=m -CONFIG_SPI_XCOMM=m -CONFIG_SPI_ZYNQMP_GQSPI=m -CONFIG_SPI_AMD=m -CONFIG_SPI_MUX=m -CONFIG_SPI_SPIDEV=m -CONFIG_SPI_TLE62X0=m -CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m -CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m -CONFIG_SPMI=m -CONFIG_HSI=m -CONFIG_HSI_CHAR=m -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_PARPORT=m -CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PPS_GENERATOR=m -CONFIG_PPS_GENERATOR_TIO=m -CONFIG_PTP_1588_CLOCK=m -CONFIG_PTP_1588_CLOCK_IDT82P33=m -CONFIG_PTP_1588_CLOCK_IDTCM=m -CONFIG_PTP_1588_CLOCK_OCP=m -CONFIG_PTP_DFL_TOD=m -CONFIG_ZL3073X_I2C=m -CONFIG_ZL3073X_SPI=m -CONFIG_PINCTRL_AMD=y -CONFIG_PINCTRL_AMDISP=m -CONFIG_PINCTRL_CY8C95X0=m -CONFIG_PINCTRL_MCP23S08=m -CONFIG_PINCTRL_SX150X=y -CONFIG_PINCTRL_BAYTRAIL=y -CONFIG_PINCTRL_CHERRYVIEW=y -CONFIG_PINCTRL_LYNXPOINT=m -CONFIG_PINCTRL_INTEL_PLATFORM=m -CONFIG_PINCTRL_ALDERLAKE=m -CONFIG_PINCTRL_BROXTON=m -CONFIG_PINCTRL_CANNONLAKE=m -CONFIG_PINCTRL_CEDARFORK=m -CONFIG_PINCTRL_DENVERTON=m -CONFIG_PINCTRL_ELKHARTLAKE=m -CONFIG_PINCTRL_EMMITSBURG=m -CONFIG_PINCTRL_GEMINILAKE=m -CONFIG_PINCTRL_ICELAKE=m -CONFIG_PINCTRL_JASPERLAKE=m -CONFIG_PINCTRL_LAKEFIELD=m -CONFIG_PINCTRL_LEWISBURG=m -CONFIG_PINCTRL_METEORLAKE=m -CONFIG_PINCTRL_METEORPOINT=m -CONFIG_PINCTRL_SUNRISEPOINT=m -CONFIG_PINCTRL_TIGERLAKE=m -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_AMDPT=m -CONFIG_GPIO_DWAPB=m -CONFIG_GPIO_EXAR=m -CONFIG_GPIO_GENERIC_PLATFORM=m -CONFIG_GPIO_GRANITERAPIDS=m -CONFIG_GPIO_ICH=m -CONFIG_GPIO_MB86S7X=m -CONFIG_GPIO_MENZ127=m -CONFIG_GPIO_POLARFIRE_SOC=y -CONFIG_GPIO_XILINX=m -CONFIG_GPIO_VX855=m -CONFIG_GPIO_F7188X=m -CONFIG_GPIO_IT87=m -CONFIG_GPIO_SCH=m -CONFIG_GPIO_SCH311X=m -CONFIG_GPIO_WINBOND=m -CONFIG_GPIO_WS16C48=m -CONFIG_GPIO_FXL6408=m -CONFIG_GPIO_DS4520=m -CONFIG_GPIO_MAX7300=m -CONFIG_GPIO_MAX732X=m -CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_PCA9570=m -CONFIG_GPIO_PCF857X=m -CONFIG_GPIO_TPIC2810=m -CONFIG_GPIO_ADP5520=m -CONFIG_GPIO_ARIZONA=m -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_CGBC=m -CONFIG_GPIO_CRYSTAL_COVE=m -CONFIG_GPIO_DA9052=m -CONFIG_GPIO_DA9055=m -CONFIG_GPIO_DLN2=m -CONFIG_GPIO_ELKHARTLAKE=m -CONFIG_GPIO_JANZ_TTL=m -CONFIG_GPIO_KEMPLD=m -CONFIG_GPIO_LP3943=m -CONFIG_GPIO_LP873X=m -CONFIG_GPIO_MADERA=m -CONFIG_GPIO_PALMAS=y -CONFIG_GPIO_RC5T583=y -CONFIG_GPIO_TPS65086=m -CONFIG_GPIO_TPS6586X=y -CONFIG_GPIO_TPS65910=y -CONFIG_GPIO_TPS65912=m -CONFIG_GPIO_TPS68470=m -CONFIG_GPIO_TQMX86=m -CONFIG_GPIO_TWL4030=m -CONFIG_GPIO_TWL6040=m -CONFIG_GPIO_WHISKEY_COVE=m -CONFIG_GPIO_WM831X=m -CONFIG_GPIO_WM8350=m -CONFIG_GPIO_WM8994=m -CONFIG_GPIO_AMD8111=m -CONFIG_GPIO_ML_IOH=m -CONFIG_GPIO_PCI_IDIO_16=m -CONFIG_GPIO_PCIE_IDIO_24=m -CONFIG_GPIO_RDC321X=m -CONFIG_GPIO_74X164=m -CONFIG_GPIO_MAX3191X=m -CONFIG_GPIO_MAX7301=m -CONFIG_GPIO_MC33880=m -CONFIG_GPIO_PISOSR=m -CONFIG_GPIO_XRA1403=m -CONFIG_GPIO_VIPERBOARD=m -CONFIG_GPIO_MPSSE=m -CONFIG_GPIO_AGGREGATOR=m -CONFIG_GPIO_LATCH=m -CONFIG_GPIO_VIRTIO=m -CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER=m -CONFIG_GPIO_VIRTUSER=m -CONFIG_W1_MASTER_AMD_AXI=m -CONFIG_W1_MASTER_MATROX=m -CONFIG_W1_MASTER_DS2490=m -CONFIG_W1_MASTER_DS2482=m -CONFIG_W1_MASTER_GPIO=m -CONFIG_W1_MASTER_SGI=m -CONFIG_W1_SLAVE_THERM=m -CONFIG_W1_SLAVE_SMEM=m -CONFIG_W1_SLAVE_DS2405=m -CONFIG_W1_SLAVE_DS2408=m -CONFIG_W1_SLAVE_DS2413=m -CONFIG_W1_SLAVE_DS2406=m -CONFIG_W1_SLAVE_DS2423=m -CONFIG_W1_SLAVE_DS2805=m -CONFIG_W1_SLAVE_DS2430=m -CONFIG_W1_SLAVE_DS2431=m -CONFIG_W1_SLAVE_DS2433=m -CONFIG_W1_SLAVE_DS2438=m -CONFIG_W1_SLAVE_DS250X=m -CONFIG_W1_SLAVE_DS28E04=m -CONFIG_W1_SLAVE_DS28E17=m -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_ATC260X=m -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_TPS65086=y -CONFIG_POWER_SEQUENCING=m -CONFIG_GENERIC_ADC_BATTERY=m -CONFIG_IP5XXX_POWER=m -CONFIG_MAX8925_POWER=m -CONFIG_WM831X_BACKUP=m -CONFIG_WM831X_POWER=m -CONFIG_WM8350_POWER=m -CONFIG_TEST_POWER=m -CONFIG_BATTERY_88PM860X=m -CONFIG_CHARGER_ADP5061=m -CONFIG_BATTERY_CHAGALL=m -CONFIG_BATTERY_CW2015=m -CONFIG_BATTERY_DS2760=m -CONFIG_BATTERY_DS2780=m -CONFIG_BATTERY_DS2781=m -CONFIG_BATTERY_DS2782=m -CONFIG_BATTERY_SBS=m -CONFIG_CHARGER_SBS=m -CONFIG_MANAGER_SBS=m -CONFIG_BATTERY_BQ27XXX=m -CONFIG_BATTERY_DA9030=m -CONFIG_BATTERY_DA9052=m -CONFIG_CHARGER_DA9150=m -CONFIG_BATTERY_DA9150=m -CONFIG_CHARGER_AXP20X=m -CONFIG_BATTERY_AXP20X=m -CONFIG_AXP20X_POWER=m -CONFIG_AXP288_CHARGER=m -CONFIG_AXP288_FUEL_GAUGE=m -CONFIG_BATTERY_MAX17040=m -CONFIG_BATTERY_MAX17042=m -CONFIG_BATTERY_MAX1720X=m -CONFIG_BATTERY_MAX1721X=m -CONFIG_BATTERY_TWL4030_MADC=m -CONFIG_CHARGER_88PM860X=m -CONFIG_BATTERY_RX51=m -CONFIG_CHARGER_ISP1704=m -CONFIG_CHARGER_MAX8903=m -CONFIG_CHARGER_TWL4030=m -CONFIG_CHARGER_TWL6030=m -CONFIG_CHARGER_LP8727=m -CONFIG_CHARGER_LP8788=m -CONFIG_CHARGER_GPIO=m -CONFIG_CHARGER_MANAGER=y -CONFIG_CHARGER_LT3651=m -CONFIG_CHARGER_LTC4162L=m -CONFIG_CHARGER_MAX14577=m -CONFIG_CHARGER_MAX77693=m -CONFIG_CHARGER_MAX77705=m -CONFIG_CHARGER_MAX77976=m -CONFIG_CHARGER_MAX8971=m -CONFIG_CHARGER_MAX8997=m -CONFIG_CHARGER_MAX8998=m -CONFIG_CHARGER_MP2629=m -CONFIG_CHARGER_MT6360=m -CONFIG_CHARGER_MT6370=m -CONFIG_CHARGER_BQ2415X=m -CONFIG_CHARGER_BQ24190=m -CONFIG_CHARGER_BQ24257=m -CONFIG_CHARGER_BQ24735=m -CONFIG_CHARGER_BQ2515X=m -CONFIG_CHARGER_BQ25890=m -CONFIG_CHARGER_BQ25980=m -CONFIG_CHARGER_BQ256XX=m -CONFIG_CHARGER_SMB347=m -CONFIG_CHARGER_TPS65090=m -CONFIG_BATTERY_GAUGE_LTC2941=m -CONFIG_BATTERY_GOLDFISH=m -CONFIG_BATTERY_RT5033=m -CONFIG_CHARGER_RT5033=m -CONFIG_CHARGER_RT9455=m -CONFIG_CHARGER_RT9467=m -CONFIG_CHARGER_RT9471=m -CONFIG_CHARGER_CROS_USBPD=m -CONFIG_FUEL_GAUGE_STC3117=m -CONFIG_CHARGER_BD99954=m -CONFIG_CHARGER_WILCO=m -CONFIG_BATTERY_SURFACE=m -CONFIG_CHARGER_SURFACE=m -CONFIG_BATTERY_UG3105=m -CONFIG_FUEL_GAUGE_MM8013=m -CONFIG_SENSORS_ABITUGURU=m -CONFIG_SENSORS_ABITUGURU3=m -CONFIG_SENSORS_SMPRO=m -CONFIG_SENSORS_AD7314=m -CONFIG_SENSORS_AD7414=m -CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1025=m -CONFIG_SENSORS_ADM1026=m -CONFIG_SENSORS_ADM1029=m -CONFIG_SENSORS_ADM1031=m -CONFIG_SENSORS_ADM1177=m -CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_ADT7310=m -CONFIG_SENSORS_ADT7410=m -CONFIG_SENSORS_ADT7411=m -CONFIG_SENSORS_ADT7462=m -CONFIG_SENSORS_ADT7470=m -CONFIG_SENSORS_ADT7475=m -CONFIG_SENSORS_AHT10=m -CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m -CONFIG_SENSORS_AS370=m -CONFIG_SENSORS_ASC7621=m -CONFIG_SENSORS_AXI_FAN_CONTROL=m -CONFIG_SENSORS_K8TEMP=m -CONFIG_SENSORS_K10TEMP=m -CONFIG_SENSORS_KBATT=m -CONFIG_SENSORS_KFAN=m -CONFIG_SENSORS_FAM15H_POWER=m -CONFIG_SENSORS_APPLESMC=m -CONFIG_SENSORS_ASB100=m -CONFIG_SENSORS_ATXP1=m -CONFIG_SENSORS_CGBC=m -CONFIG_SENSORS_CORSAIR_CPRO=m -CONFIG_SENSORS_CORSAIR_PSU=m -CONFIG_SENSORS_DRIVETEMP=y -CONFIG_SENSORS_DS620=m -CONFIG_SENSORS_DS1621=m -CONFIG_SENSORS_DELL_SMM=m -CONFIG_SENSORS_DA9052_ADC=m -CONFIG_SENSORS_DA9055=m -CONFIG_SENSORS_I5K_AMB=m -CONFIG_SENSORS_F71805F=m -CONFIG_SENSORS_F71882FG=m -CONFIG_SENSORS_F75375S=m -CONFIG_SENSORS_MC13783_ADC=m -CONFIG_SENSORS_FSCHMD=m -CONFIG_SENSORS_FTSTEUTATES=m -CONFIG_SENSORS_GIGABYTE_WATERFORCE=m -CONFIG_SENSORS_GL518SM=m -CONFIG_SENSORS_GL520SM=m -CONFIG_SENSORS_G760A=m -CONFIG_SENSORS_G762=m -CONFIG_SENSORS_HIH6130=m -CONFIG_SENSORS_HS3001=m -CONFIG_SENSORS_HTU31=m -CONFIG_SENSORS_IBMAEM=m -CONFIG_SENSORS_IBMPEX=m -CONFIG_SENSORS_IIO_HWMON=m -CONFIG_SENSORS_I5500=m -CONFIG_SENSORS_CORETEMP=m -CONFIG_SENSORS_ISL28022=m -CONFIG_SENSORS_IT87=m -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_POWERZ=m -CONFIG_SENSORS_POWR1220=m -CONFIG_SENSORS_LENOVO_EC=m -CONFIG_SENSORS_LINEAGE=m -CONFIG_SENSORS_LTC2945=m -CONFIG_SENSORS_LTC2947_I2C=m -CONFIG_SENSORS_LTC2947_SPI=m -CONFIG_SENSORS_LTC2990=m -CONFIG_SENSORS_LTC2991=m -CONFIG_SENSORS_LTC2992=m -CONFIG_SENSORS_LTC4151=m -CONFIG_SENSORS_LTC4215=m -CONFIG_SENSORS_LTC4222=m -CONFIG_SENSORS_LTC4245=m -CONFIG_SENSORS_LTC4260=m -CONFIG_SENSORS_LTC4261=m -CONFIG_SENSORS_MAX1111=m -CONFIG_SENSORS_MAX127=m -CONFIG_SENSORS_MAX16065=m -CONFIG_SENSORS_MAX1619=m -CONFIG_SENSORS_MAX1668=m -CONFIG_SENSORS_MAX197=m -CONFIG_SENSORS_MAX31722=m -CONFIG_SENSORS_MAX31730=m -CONFIG_SENSORS_MAX31760=m -CONFIG_MAX31827=m -CONFIG_SENSORS_MAX6620=m -CONFIG_SENSORS_MAX6621=m -CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6650=m -CONFIG_SENSORS_MAX6697=m -CONFIG_SENSORS_MAX31790=m -CONFIG_SENSORS_MAX77705=m -CONFIG_SENSORS_MC34VR500=m -CONFIG_SENSORS_MCP3021=m -CONFIG_SENSORS_TC654=m -CONFIG_SENSORS_TPS23861=m -CONFIG_SENSORS_MENF21BMC_HWMON=m -CONFIG_SENSORS_MR75203=m -CONFIG_SENSORS_ADCXX=m -CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM70=m -CONFIG_SENSORS_LM73=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM77=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM80=m -CONFIG_SENSORS_LM83=m -CONFIG_SENSORS_LM85=m -CONFIG_SENSORS_LM87=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_LM92=m -CONFIG_SENSORS_LM93=m -CONFIG_SENSORS_LM95234=m -CONFIG_SENSORS_LM95241=m -CONFIG_SENSORS_LM95245=m -CONFIG_SENSORS_PC87360=m -CONFIG_SENSORS_PC87427=m -CONFIG_SENSORS_NTC_THERMISTOR=m -CONFIG_SENSORS_NCT6683=m -CONFIG_SENSORS_NCT6775=m -CONFIG_SENSORS_NCT6775_I2C=m -CONFIG_SENSORS_NCT7363=m -CONFIG_SENSORS_NCT7802=m -CONFIG_SENSORS_NCT7904=m -CONFIG_SENSORS_NPCM7XX=m -CONFIG_SENSORS_NZXT_KRAKEN2=m -CONFIG_SENSORS_NZXT_SMART2=m -CONFIG_SENSORS_OCC_P8_I2C=m -CONFIG_SENSORS_PCF8591=m -CONFIG_PMBUS=m -CONFIG_SENSORS_ACBEL_FSG032=m -CONFIG_SENSORS_ADM1266=m -CONFIG_SENSORS_ADM1275=m -CONFIG_SENSORS_ADP1050=m -CONFIG_SENSORS_BEL_PFE=m -CONFIG_SENSORS_BPA_RS600=m -CONFIG_SENSORS_CRPS=m -CONFIG_SENSORS_DELTA_AHE50DC_FAN=m -CONFIG_SENSORS_FSP_3Y=m -CONFIG_SENSORS_IBM_CFFPS=m -CONFIG_SENSORS_DPS920AB=m -CONFIG_SENSORS_INA233=m -CONFIG_SENSORS_INSPUR_IPSPS=m -CONFIG_SENSORS_IR35221=m -CONFIG_SENSORS_IR36021=m -CONFIG_SENSORS_IR38064=m -CONFIG_SENSORS_IR38064_REGULATOR=y -CONFIG_SENSORS_IRPS5401=m -CONFIG_SENSORS_ISL68137=m -CONFIG_SENSORS_LM25066=m -CONFIG_SENSORS_LM25066_REGULATOR=y -CONFIG_SENSORS_LT3074=m -CONFIG_SENSORS_LT3074_REGULATOR=m -CONFIG_SENSORS_LT7182S=m -CONFIG_SENSORS_LTC2978=m -CONFIG_SENSORS_LTC2978_REGULATOR=y -CONFIG_SENSORS_LTC3815=m -CONFIG_SENSORS_LTC4286=y -CONFIG_SENSORS_MAX15301=m -CONFIG_SENSORS_MAX16064=m -CONFIG_SENSORS_MAX16601=m -CONFIG_SENSORS_MAX20730=m -CONFIG_SENSORS_MAX20751=m -CONFIG_SENSORS_MAX31785=m -CONFIG_SENSORS_MAX34440=m -CONFIG_SENSORS_MAX8688=m -CONFIG_SENSORS_MP2856=m -CONFIG_SENSORS_MP2888=m -CONFIG_SENSORS_MP2891=m -CONFIG_SENSORS_MP2975=m -CONFIG_SENSORS_MP2993=m -CONFIG_SENSORS_MP2975_REGULATOR=y -CONFIG_SENSORS_MP5023=m -CONFIG_SENSORS_MP5920=m -CONFIG_SENSORS_MP5990=m -CONFIG_SENSORS_MP9941=m -CONFIG_SENSORS_MPQ7932_REGULATOR=y -CONFIG_SENSORS_MPQ7932=m -CONFIG_SENSORS_PIM4328=m -CONFIG_SENSORS_PLI1209BC=m -CONFIG_SENSORS_PLI1209BC_REGULATOR=y -CONFIG_SENSORS_PM6764TR=m -CONFIG_SENSORS_PXE1610=m -CONFIG_SENSORS_Q54SJ108A2=m -CONFIG_SENSORS_STPDDC60=m -CONFIG_SENSORS_TDA38640=m -CONFIG_SENSORS_TDA38640_REGULATOR=y -CONFIG_SENSORS_TPS25990=m -CONFIG_SENSORS_TPS40422=m -CONFIG_SENSORS_TPS53679=m -CONFIG_SENSORS_TPS546D24=m -CONFIG_SENSORS_UCD9000=m -CONFIG_SENSORS_UCD9200=m -CONFIG_SENSORS_XDP710=m -CONFIG_SENSORS_XDPE152=m -CONFIG_SENSORS_XDPE122=m -CONFIG_SENSORS_XDPE122_REGULATOR=y -CONFIG_SENSORS_ZL6100=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_QNAP_MCU_HWMON=m -CONFIG_SENSORS_SBTSI=m -CONFIG_SENSORS_SHT15=m -CONFIG_SENSORS_SHT21=m -CONFIG_SENSORS_SHT3x=m -CONFIG_SENSORS_SHT4x=m -CONFIG_SENSORS_SHTC1=m -CONFIG_SENSORS_SIS5595=m -CONFIG_SENSORS_SY7636A=m -CONFIG_SENSORS_DME1737=m -CONFIG_SENSORS_EMC1403=m -CONFIG_SENSORS_EMC2103=m -CONFIG_SENSORS_EMC2305=m -CONFIG_SENSORS_EMC6W201=m -CONFIG_SENSORS_SMSC47M1=m -CONFIG_SENSORS_SMSC47M192=m -CONFIG_SENSORS_SMSC47B397=m -CONFIG_SENSORS_SCH5627=m -CONFIG_SENSORS_SCH5636=m -CONFIG_SENSORS_STTS751=m -CONFIG_SENSORS_SURFACE_TEMP=m -CONFIG_SENSORS_ADC128D818=m -CONFIG_SENSORS_ADS7828=m -CONFIG_SENSORS_ADS7871=m -CONFIG_SENSORS_AMC6821=m -CONFIG_SENSORS_INA209=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA238=m -CONFIG_SENSORS_INA3221=m -CONFIG_SENSORS_SPD5118=m -CONFIG_SENSORS_SPD5118_DETECT=y -CONFIG_SENSORS_TC74=m -CONFIG_SENSORS_THMC50=m -CONFIG_SENSORS_TMP102=m -CONFIG_SENSORS_TMP103=m -CONFIG_SENSORS_TMP108=m -CONFIG_SENSORS_TMP401=m -CONFIG_SENSORS_TMP421=m -CONFIG_SENSORS_TMP464=m -CONFIG_SENSORS_TMP513=m -CONFIG_SENSORS_VIA_CPUTEMP=m -CONFIG_SENSORS_VIA686A=m -CONFIG_SENSORS_VT1211=m -CONFIG_SENSORS_VT8231=m -CONFIG_SENSORS_W83773G=m -CONFIG_SENSORS_W83781D=m -CONFIG_SENSORS_W83791D=m -CONFIG_SENSORS_W83792D=m -CONFIG_SENSORS_W83793=m -CONFIG_SENSORS_W83795=m -CONFIG_SENSORS_W83L785TS=m -CONFIG_SENSORS_W83L786NG=m -CONFIG_SENSORS_W83627HF=m -CONFIG_SENSORS_W83627EHF=m -CONFIG_SENSORS_WM831X=m -CONFIG_SENSORS_WM8350=m -CONFIG_SENSORS_XGENE=m -CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m -CONFIG_SENSORS_ACPI_POWER=m -CONFIG_SENSORS_ATK0110=m -CONFIG_SENSORS_ASUS_WMI=m -CONFIG_SENSORS_ASUS_EC=m -CONFIG_SENSORS_HP_WMI=m -CONFIG_THERMAL_DEBUGFS=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_PCIE_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_INTEL_POWERCLAMP=m -CONFIG_INTEL_SOC_DTS_THERMAL=m -CONFIG_INT340X_THERMAL=m -CONFIG_INT3406_THERMAL=m -CONFIG_INTEL_BXT_PMIC_THERMAL=m -CONFIG_INTEL_PCH_THERMAL=m -CONFIG_INTEL_TCC_COOLING=m -CONFIG_INTEL_HFI_THERMAL=y -CONFIG_GENERIC_ADC_THERMAL=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_SYSFS=y -CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_DA9052_WATCHDOG=m -CONFIG_DA9055_WATCHDOG=m -CONFIG_DA9063_WATCHDOG=m -CONFIG_DA9062_WATCHDOG=m -CONFIG_LENOVO_SE10_WDT=m -CONFIG_LENOVO_SE30_WDT=m -CONFIG_MENF21BMC_WATCHDOG=m -CONFIG_MENZ069_WATCHDOG=m -CONFIG_WDAT_WDT=m -CONFIG_WM831X_WATCHDOG=m -CONFIG_WM8350_WATCHDOG=m -CONFIG_XILINX_WATCHDOG=m -CONFIG_ZIIRAVE_WATCHDOG=m -CONFIG_RAVE_SP_WATCHDOG=m -CONFIG_CADENCE_WATCHDOG=m -CONFIG_DW_WATCHDOG=m -CONFIG_TWL4030_WATCHDOG=m -CONFIG_MAX63XX_WATCHDOG=m -CONFIG_RETU_WATCHDOG=m -CONFIG_ACQUIRE_WDT=m -CONFIG_ADVANTECH_WDT=m -CONFIG_ADVANTECH_EC_WDT=m -CONFIG_ALIM1535_WDT=m -CONFIG_ALIM7101_WDT=m -CONFIG_EBC_C384_WDT=m -CONFIG_EXAR_WDT=m -CONFIG_F71808E_WDT=m -CONFIG_SP5100_TCO=m -CONFIG_SBC_FITPC2_WATCHDOG=m -CONFIG_EUROTECH_WDT=m -CONFIG_IB700_WDT=m -CONFIG_IBMASR=m -CONFIG_WAFER_WDT=m -CONFIG_I6300ESB_WDT=m -CONFIG_IE6XX_WDT=m -CONFIG_INTEL_OC_WATCHDOG=m -CONFIG_ITCO_WDT=m -CONFIG_ITCO_VENDOR_SUPPORT=y -CONFIG_IT8712F_WDT=m -CONFIG_IT87_WDT=m -CONFIG_HP_WATCHDOG=m -CONFIG_KEMPLD_WDT=m -CONFIG_SC1200_WDT=m -CONFIG_PC87413_WDT=m -CONFIG_NV_TCO=m -CONFIG_60XX_WDT=m -CONFIG_SMSC_SCH311X_WDT=m -CONFIG_SMSC37B787_WDT=m -CONFIG_TQMX86_WDT=m -CONFIG_VIA_WDT=m -CONFIG_W83627HF_WDT=m -CONFIG_W83877F_WDT=m -CONFIG_W83977F_WDT=m -CONFIG_MACHZ_WDT=m -CONFIG_SBC_EPX_C3_WATCHDOG=m -CONFIG_INTEL_MEI_WDT=m -CONFIG_NI903X_WDT=m -CONFIG_NIC7018_WDT=m -CONFIG_MEN_A21_WDT=m -CONFIG_XEN_WDT=m -CONFIG_PCIPCWATCHDOG=m -CONFIG_WDTPCI=m -CONFIG_USBPCWATCHDOG=m -CONFIG_SSB_SDIOHOST=y -CONFIG_SSB_DRIVER_GPIO=y -CONFIG_BCMA_HOST_SOC=y -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_MFD_AS3711=y -CONFIG_MFD_SMPRO=m -CONFIG_PMIC_ADP5520=y -CONFIG_MFD_AAT2870_CORE=y -CONFIG_MFD_BCM590XX=m -CONFIG_MFD_BD9571MWV=m -CONFIG_MFD_AXP20X_I2C=m -CONFIG_MFD_CGBC=m -CONFIG_MFD_CS40L50_I2C=m -CONFIG_MFD_CS40L50_SPI=m -CONFIG_MFD_CS42L43_I2C=m -CONFIG_MFD_MADERA=m -CONFIG_MFD_MADERA_I2C=m -CONFIG_MFD_MADERA_SPI=m -CONFIG_PMIC_DA903X=y -CONFIG_MFD_DA9052_SPI=y -CONFIG_MFD_DA9052_I2C=y -CONFIG_MFD_DA9055=y -CONFIG_MFD_DA9062=m -CONFIG_MFD_DA9063=y -CONFIG_MFD_DA9150=m -CONFIG_MFD_DLN2=m -CONFIG_MFD_MC13XXX_SPI=m -CONFIG_MFD_MC13XXX_I2C=m -CONFIG_MFD_MP2629=m -CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m -CONFIG_LPC_ICH=m -CONFIG_INTEL_SOC_PMIC=y -CONFIG_INTEL_SOC_PMIC_BXTWC=m -CONFIG_INTEL_SOC_PMIC_CHTWC=y -CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m -CONFIG_INTEL_SOC_PMIC_MRFLD=m -CONFIG_MFD_INTEL_LPSS_ACPI=m -CONFIG_MFD_INTEL_LPSS_PCI=m -CONFIG_MFD_INTEL_PMC_BXT=m -CONFIG_MFD_IQS62X=m -CONFIG_MFD_JANZ_CMODIO=m -CONFIG_MFD_KEMPLD=m -CONFIG_MFD_88PM800=m -CONFIG_MFD_88PM805=m -CONFIG_MFD_88PM860X=y -CONFIG_MFD_MAX14577=y -CONFIG_MFD_MAX77541=m -CONFIG_MFD_MAX77693=y -CONFIG_MFD_MAX77705=m -CONFIG_MFD_MAX77843=y -CONFIG_MFD_MAX8907=m -CONFIG_MFD_MAX8925=y -CONFIG_MFD_MAX8997=y -CONFIG_MFD_MAX8998=y -CONFIG_MFD_MT6360=m -CONFIG_MFD_MT6370=m -CONFIG_MFD_MT6397=m -CONFIG_MFD_MENF21BMC=m -CONFIG_EZX_PCAP=y -CONFIG_MFD_VIPERBOARD=m -CONFIG_MFD_RETU=m -CONFIG_MFD_SY7636A=m -CONFIG_MFD_RT4831=m -CONFIG_MFD_RT5033=m -CONFIG_MFD_RT5120=m -CONFIG_MFD_RC5T583=y -CONFIG_MFD_SI476X_CORE=m -CONFIG_MFD_SM501=m -CONFIG_MFD_SM501_GPIO=y -CONFIG_MFD_SKY81452=m -CONFIG_MFD_LP3943=m -CONFIG_MFD_LP8788=y -CONFIG_MFD_TI_LMU=m -CONFIG_MFD_PALMAS=y -CONFIG_TPS6105X=m -CONFIG_TPS65010=m -CONFIG_TPS6507X=m -CONFIG_MFD_TPS65086=m -CONFIG_MFD_TPS65090=y -CONFIG_MFD_TI_LP873X=m -CONFIG_MFD_TPS6586X=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_TPS65912_I2C=y -CONFIG_MFD_TPS65912_SPI=y -CONFIG_MFD_TPS6594_I2C=y -CONFIG_MFD_TPS6594_SPI=y -CONFIG_TWL4030_CORE=y -CONFIG_TWL6040_CORE=y -CONFIG_MFD_WL1273_CORE=m -CONFIG_MFD_LM3533=m -CONFIG_MFD_TQMX86=m -CONFIG_MFD_ARIZONA_I2C=m -CONFIG_MFD_ARIZONA_SPI=m -CONFIG_MFD_CS47L24=y -CONFIG_MFD_WM5102=y -CONFIG_MFD_WM5110=y -CONFIG_MFD_WM8997=y -CONFIG_MFD_WM8998=y -CONFIG_MFD_WM8400=y -CONFIG_MFD_WM831X_I2C=y -CONFIG_MFD_WM831X_SPI=y -CONFIG_MFD_WM8350_I2C=y -CONFIG_MFD_WM8994=m -CONFIG_MFD_ATC260X_I2C=m -CONFIG_RAVE_SP_CORE=m -CONFIG_MFD_INTEL_M10_BMC_SPI=m -CONFIG_MFD_INTEL_M10_BMC_PMCI=m -CONFIG_MFD_QNAP_MCU=m -CONFIG_MFD_UPBOARD_FPGA=m -CONFIG_REGULATOR_VIRTUAL_CONSUMER=m -CONFIG_REGULATOR_USERSPACE_CONSUMER=m -CONFIG_REGULATOR_88PG86X=m -CONFIG_REGULATOR_88PM800=m -CONFIG_REGULATOR_88PM8607=m -CONFIG_REGULATOR_ACT8865=m -CONFIG_REGULATOR_AD5398=m -CONFIG_REGULATOR_ADP5055=m -CONFIG_REGULATOR_AAT2870=m -CONFIG_REGULATOR_ARIZONA_LDO1=m -CONFIG_REGULATOR_ARIZONA_MICSUPP=m -CONFIG_REGULATOR_AS3711=m -CONFIG_REGULATOR_ATC260X=m -CONFIG_REGULATOR_AW37503=m -CONFIG_REGULATOR_AXP20X=m -CONFIG_REGULATOR_BCM590XX=m -CONFIG_REGULATOR_BD9571MWV=m -CONFIG_REGULATOR_DA903X=m -CONFIG_REGULATOR_DA9052=m -CONFIG_REGULATOR_DA9055=m -CONFIG_REGULATOR_DA9062=m -CONFIG_REGULATOR_DA9210=m -CONFIG_REGULATOR_DA9211=m -CONFIG_REGULATOR_FAN53555=m -CONFIG_REGULATOR_GPIO=m -CONFIG_REGULATOR_ISL9305=m -CONFIG_REGULATOR_ISL6271A=m -CONFIG_REGULATOR_LM363X=m -CONFIG_REGULATOR_LP3971=m -CONFIG_REGULATOR_LP3972=m -CONFIG_REGULATOR_LP872X=m -CONFIG_REGULATOR_LP8755=m -CONFIG_REGULATOR_LP8788=m -CONFIG_REGULATOR_LTC3589=m -CONFIG_REGULATOR_LTC3676=m -CONFIG_REGULATOR_MAX14577=m -CONFIG_REGULATOR_MAX1586=m -CONFIG_REGULATOR_MAX77503=m -CONFIG_REGULATOR_MAX77541=m -CONFIG_REGULATOR_MAX77857=m -CONFIG_REGULATOR_MAX8649=m -CONFIG_REGULATOR_MAX8660=m -CONFIG_REGULATOR_MAX8893=m -CONFIG_REGULATOR_MAX8907=m -CONFIG_REGULATOR_MAX8925=m -CONFIG_REGULATOR_MAX8952=m -CONFIG_REGULATOR_MAX8997=m -CONFIG_REGULATOR_MAX8998=m -CONFIG_REGULATOR_MAX20086=m -CONFIG_REGULATOR_MAX20411=m -CONFIG_REGULATOR_MAX77693=m -CONFIG_REGULATOR_MAX77826=m -CONFIG_REGULATOR_MC13783=m -CONFIG_REGULATOR_MC13892=m -CONFIG_REGULATOR_MP8859=m -CONFIG_REGULATOR_MT6311=m -CONFIG_REGULATOR_MT6315=m -CONFIG_REGULATOR_MT6323=m -CONFIG_REGULATOR_MT6331=m -CONFIG_REGULATOR_MT6332=m -CONFIG_REGULATOR_MT6357=m -CONFIG_REGULATOR_MT6358=m -CONFIG_REGULATOR_MT6359=m -CONFIG_REGULATOR_MT6360=m -CONFIG_REGULATOR_MT6370=m -CONFIG_REGULATOR_MT6397=m -CONFIG_REGULATOR_PALMAS=m -CONFIG_REGULATOR_PCA9450=m -CONFIG_REGULATOR_PF9453=m -CONFIG_REGULATOR_PCAP=m -CONFIG_REGULATOR_PV88060=m -CONFIG_REGULATOR_PV88080=m -CONFIG_REGULATOR_PV88090=m -CONFIG_REGULATOR_PWM=m -CONFIG_REGULATOR_QCOM_SPMI=m -CONFIG_REGULATOR_QCOM_USB_VBUS=m -CONFIG_REGULATOR_RAA215300=m -CONFIG_REGULATOR_RC5T583=m -CONFIG_REGULATOR_RT4801=m -CONFIG_REGULATOR_RT4803=m -CONFIG_REGULATOR_RT4831=m -CONFIG_REGULATOR_RT5033=m -CONFIG_REGULATOR_RT5120=m -CONFIG_REGULATOR_RT5190A=m -CONFIG_REGULATOR_RT5739=m -CONFIG_REGULATOR_RT5759=m -CONFIG_REGULATOR_RT6160=m -CONFIG_REGULATOR_RT6190=m -CONFIG_REGULATOR_RT6245=m -CONFIG_REGULATOR_RTQ2134=m -CONFIG_REGULATOR_RTMV20=m -CONFIG_REGULATOR_RTQ6752=m -CONFIG_REGULATOR_RTQ2208=m -CONFIG_REGULATOR_SKY81452=m -CONFIG_REGULATOR_SLG51000=m -CONFIG_REGULATOR_SY7636A=m -CONFIG_REGULATOR_TPS51632=m -CONFIG_REGULATOR_TPS62360=m -CONFIG_REGULATOR_TPS65023=m -CONFIG_REGULATOR_TPS6507X=m -CONFIG_REGULATOR_TPS65086=m -CONFIG_REGULATOR_TPS65090=m -CONFIG_REGULATOR_TPS65132=m -CONFIG_REGULATOR_TPS6524X=m -CONFIG_REGULATOR_TPS6586X=m -CONFIG_REGULATOR_TPS65910=m -CONFIG_REGULATOR_TPS65912=m -CONFIG_REGULATOR_TPS68470=m -CONFIG_REGULATOR_TWL4030=m -CONFIG_REGULATOR_WM831X=m -CONFIG_REGULATOR_WM8350=m -CONFIG_REGULATOR_WM8400=m -CONFIG_REGULATOR_WM8994=m -CONFIG_REGULATOR_QCOM_LABIBB=m -CONFIG_RC_CORE=m -CONFIG_LIRC=y -CONFIG_RC_DECODERS=y -CONFIG_IR_IMON_DECODER=m -CONFIG_IR_JVC_DECODER=m -CONFIG_IR_MCE_KBD_DECODER=m -CONFIG_IR_NEC_DECODER=m -CONFIG_IR_RC5_DECODER=m -CONFIG_IR_RC6_DECODER=m -CONFIG_IR_RCMM_DECODER=m -CONFIG_IR_SANYO_DECODER=m -CONFIG_IR_SHARP_DECODER=m -CONFIG_IR_SONY_DECODER=m -CONFIG_IR_XMP_DECODER=m -CONFIG_RC_DEVICES=y -CONFIG_IR_ENE=m -CONFIG_IR_FINTEK=m -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_IMON=m -CONFIG_IR_IMON_RAW=m -CONFIG_IR_ITE_CIR=m -CONFIG_IR_MCEUSB=m -CONFIG_IR_NUVOTON=m -CONFIG_IR_REDRAT3=m -CONFIG_IR_SERIAL=m -CONFIG_IR_SERIAL_TRANSMITTER=y -CONFIG_IR_STREAMZAP=m -CONFIG_IR_TOY=m -CONFIG_IR_TTUSBIR=m -CONFIG_IR_WINBOND_CIR=m -CONFIG_RC_ATI_REMOTE=m -CONFIG_RC_LOOPBACK=m -CONFIG_RC_XBOX_DVD=m -CONFIG_MEDIA_CEC_RC=y -CONFIG_CEC_CH7322=m -CONFIG_CEC_CROS_EC=m -CONFIG_CEC_GPIO=m -CONFIG_CEC_SECO=m -CONFIG_CEC_SECO_RC=y -CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC=m -CONFIG_USB_PULSE8_CEC=m -CONFIG_USB_RAINSHADOW_CEC=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y -CONFIG_V4L2_FLASH_LED_CLASS=m -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_GSPCA=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_GL860=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_PWC=m -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m -CONFIG_USB_VIDEO_CLASS=m -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_GO7007_USB=m -CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_STK1160=m -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_AU0828_RC=y -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_DVB_AS102=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_DVB_USB=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_CXUSB_ANALOG=y -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_VP7045=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -CONFIG_MEDIA_PCI_SUPPORT=y -CONFIG_VIDEO_MGB4=m -CONFIG_VIDEO_SOLO6X10=m -CONFIG_VIDEO_TW5864=m -CONFIG_VIDEO_TW68=m -CONFIG_VIDEO_TW686X=m -CONFIG_VIDEO_DT3155=m -CONFIG_VIDEO_IVTV=m -CONFIG_VIDEO_IVTV_ALSA=m -CONFIG_VIDEO_FB_IVTV=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_MXB=m -CONFIG_VIDEO_BT848=m -CONFIG_DVB_BT8XX=m -CONFIG_VIDEO_COBALT=m -CONFIG_VIDEO_CX18=m -CONFIG_VIDEO_CX18_ALSA=m -CONFIG_VIDEO_CX23885=m -CONFIG_MEDIA_ALTERA_CI=m -CONFIG_VIDEO_CX25821=m -CONFIG_VIDEO_CX25821_ALSA=m -CONFIG_VIDEO_CX88=m -CONFIG_VIDEO_CX88_ALSA=m -CONFIG_VIDEO_CX88_BLACKBIRD=m -CONFIG_VIDEO_CX88_DVB=m -CONFIG_VIDEO_SAA7134=m -CONFIG_VIDEO_SAA7134_ALSA=m -CONFIG_VIDEO_SAA7134_DVB=m -CONFIG_VIDEO_SAA7134_GO7007=m -CONFIG_VIDEO_SAA7164=m -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -CONFIG_DVB_DDBRIDGE=m -CONFIG_DVB_DM1105=m -CONFIG_MANTIS_CORE=m -CONFIG_DVB_MANTIS=m -CONFIG_DVB_HOPPER=m -CONFIG_DVB_NETUP_UNIDVB=m -CONFIG_DVB_NGENE=m -CONFIG_DVB_PLUTO2=m -CONFIG_DVB_PT1=m -CONFIG_DVB_PT3=m -CONFIG_DVB_SMIPCIE=m -CONFIG_DVB_BUDGET_CORE=m -CONFIG_DVB_BUDGET=m -CONFIG_DVB_BUDGET_CI=m -CONFIG_DVB_BUDGET_AV=m -CONFIG_VIDEO_IPU3_CIO2=m -CONFIG_VIDEO_INTEL_IPU6=m -CONFIG_INTEL_VSC=m -CONFIG_IPU_BRIDGE=m -CONFIG_RADIO_MAXIRADIO=m -CONFIG_RADIO_SAA7706H=m -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_RADIO_SI4713=m -CONFIG_RADIO_SI476X=m -CONFIG_RADIO_TEA5764=m -CONFIG_RADIO_TEF6862=m -CONFIG_USB_DSBR=m -CONFIG_USB_KEENE=m -CONFIG_USB_MA901=m -CONFIG_USB_MR800=m -CONFIG_USB_RAREMONO=m -CONFIG_RADIO_SI470X=m -CONFIG_USB_SI470X=m -CONFIG_I2C_SI470X=m -CONFIG_USB_SI4713=m -CONFIG_PLATFORM_SI4713=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_DVB_PLATFORM_DRIVERS=y -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m -CONFIG_VIDEO_CADENCE_CSI2RX=m -CONFIG_VIDEO_CADENCE_CSI2TX=m -CONFIG_VIDEO_CAFE_CCIC=m -CONFIG_VIDEO_RP1_CFE=m -CONFIG_VIDEO_VIA_CAMERA=m -CONFIG_SMS_SDIO_DRV=m -CONFIG_V4L_TEST_DRIVERS=y -CONFIG_VIDEO_VIM2M=m -CONFIG_VIDEO_VICODEC=m -CONFIG_VIDEO_VIVID=m -CONFIG_VIDEO_VIVID_CEC=y -# CONFIG_VIDEO_VIVID_OSD is not set -CONFIG_DVB_FIREDTV=m -CONFIG_SMS_SIANO_DEBUGFS=y -CONFIG_VIDEO_ALVIUM_CSI2=m -CONFIG_VIDEO_AR0521=m -CONFIG_VIDEO_GC0308=m -CONFIG_VIDEO_GC05A2=m -CONFIG_VIDEO_GC08A3=m -CONFIG_VIDEO_GC2145=m -CONFIG_VIDEO_HI556=m -CONFIG_VIDEO_HI846=m -CONFIG_VIDEO_HI847=m -CONFIG_VIDEO_IMX208=m -CONFIG_VIDEO_IMX214=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_IMX258=m -CONFIG_VIDEO_IMX274=m -CONFIG_VIDEO_IMX283=m -CONFIG_VIDEO_IMX290=m -CONFIG_VIDEO_IMX296=m -CONFIG_VIDEO_IMX319=m -CONFIG_VIDEO_IMX355=m -CONFIG_VIDEO_MT9M001=m -CONFIG_VIDEO_MT9M111=m -CONFIG_VIDEO_MT9M114=m -CONFIG_VIDEO_MT9P031=m -CONFIG_VIDEO_MT9T112=m -CONFIG_VIDEO_MT9V111=m -CONFIG_VIDEO_OG01A1B=m -CONFIG_VIDEO_OV01A10=m -CONFIG_VIDEO_OV02A10=m -CONFIG_VIDEO_OV02E10=m -CONFIG_VIDEO_OV02C10=m -CONFIG_VIDEO_OV08D10=m -CONFIG_VIDEO_OV08X40=m -CONFIG_VIDEO_OV13858=m -CONFIG_VIDEO_OV13B10=m -CONFIG_VIDEO_OV2659=m -CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV2685=m -CONFIG_VIDEO_OV2740=m -CONFIG_VIDEO_OV4689=m -CONFIG_VIDEO_OV5647=m -CONFIG_VIDEO_OV5648=m -CONFIG_VIDEO_OV5670=m -CONFIG_VIDEO_OV5675=m -CONFIG_VIDEO_OV5693=m -CONFIG_VIDEO_OV5695=m -CONFIG_VIDEO_OV64A40=m -CONFIG_VIDEO_OV7251=m -CONFIG_VIDEO_OV772X=m -CONFIG_VIDEO_OV7740=m -CONFIG_VIDEO_OV8856=m -CONFIG_VIDEO_OV8858=m -CONFIG_VIDEO_OV8865=m -CONFIG_VIDEO_OV9640=m -CONFIG_VIDEO_OV9650=m -CONFIG_VIDEO_OV9734=m -CONFIG_VIDEO_RDACM20=m -CONFIG_VIDEO_RDACM21=m -CONFIG_VIDEO_RJ54N1=m -CONFIG_VIDEO_S5C73M3=m -CONFIG_VIDEO_S5K5BAF=m -CONFIG_VIDEO_S5K6A3=m -CONFIG_VIDEO_VD55G1=m -CONFIG_VIDEO_VD56G3=m -CONFIG_VIDEO_CCS=m -CONFIG_VIDEO_ET8EK8=m -CONFIG_VIDEO_THP7312=m -CONFIG_VIDEO_AD5820=m -CONFIG_VIDEO_AK7375=m -CONFIG_VIDEO_DW9714=m -CONFIG_VIDEO_DW9719=m -CONFIG_VIDEO_DW9768=m -CONFIG_VIDEO_DW9807_VCM=m -CONFIG_VIDEO_ADP1653=m -CONFIG_VIDEO_LM3560=m -CONFIG_VIDEO_LM3646=m -CONFIG_VIDEO_TDA1997X=m -CONFIG_VIDEO_TLV320AIC23B=m -CONFIG_VIDEO_ADV7180=m -CONFIG_VIDEO_ADV7183=m -CONFIG_VIDEO_ADV7604_CEC=y -CONFIG_VIDEO_ADV7842_CEC=y -CONFIG_VIDEO_BT819=m -CONFIG_VIDEO_BT856=m -CONFIG_VIDEO_BT866=m -CONFIG_VIDEO_LT6911UXE=m -CONFIG_VIDEO_KS0127=m -CONFIG_VIDEO_ML86V7667=m -CONFIG_VIDEO_SAA7110=m -CONFIG_VIDEO_TC358743=m -CONFIG_VIDEO_TC358743_CEC=y -CONFIG_VIDEO_TC358746=m -CONFIG_VIDEO_TVP514X=m -CONFIG_VIDEO_TVP7002=m -CONFIG_VIDEO_TW9900=m -CONFIG_VIDEO_TW9910=m -CONFIG_VIDEO_VPX3220=m -CONFIG_VIDEO_ADV7170=m -CONFIG_VIDEO_ADV7175=m -CONFIG_VIDEO_ADV7343=m -CONFIG_VIDEO_ADV7393=m -CONFIG_VIDEO_ADV7511_CEC=y -CONFIG_VIDEO_AK881X=m -CONFIG_VIDEO_SAA7185=m -CONFIG_VIDEO_THS8200=m -CONFIG_SDR_MAX2175=m -CONFIG_VIDEO_I2C=m -CONFIG_VIDEO_ST_MIPID02=m -CONFIG_VIDEO_THS7303=m -CONFIG_VIDEO_MAX96717=m -CONFIG_CXD2880_SPI_DRV=m -CONFIG_VIDEO_GS1662=m -CONFIG_DVB_DIB9000=m -CONFIG_DVB_S5H1432=m -CONFIG_DVB_CXD2880=m -CONFIG_DVB_MN88443X=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DVB_LNBH29=m -CONFIG_DVB_DUMMY_FE=m -CONFIG_HD44780=m -CONFIG_LCD2S=m -CONFIG_KS0108=m -CONFIG_CFAG12864B=m -CONFIG_IMG_ASCII_LCD=m -CONFIG_HT16K33=m -CONFIG_PANEL=m -CONFIG_AGP=y -CONFIG_AGP_AMD64=y -CONFIG_AGP_INTEL=y -CONFIG_AGP_SIS=m -CONFIG_AGP_VIA=y -CONFIG_VGA_SWITCHEROO=y -CONFIG_DRM=m -CONFIG_DRM_PANIC=y -CONFIG_DRM_CLIENT_LOG=y -CONFIG_DRM_LOAD_EDID_FIRMWARE=y -CONFIG_DRM_DISPLAY_DP_AUX_CEC=y -CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y -CONFIG_DRM_EFIDRM=m -CONFIG_DRM_VESADRM=m -CONFIG_DRM_RADEON=m -CONFIG_DRM_AMDGPU=m -CONFIG_DRM_AMDGPU_SI=y -CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMD_ISP=y -CONFIG_DRM_AMD_SECURE_DISPLAY=y -CONFIG_HSA_AMD=y -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_I915=m -CONFIG_DRM_I915_GVT_KVMGT=m -CONFIG_DRM_XE=m -CONFIG_DRM_VGEM=m -CONFIG_DRM_VMWGFX=m -CONFIG_DRM_GMA500=m -CONFIG_DRM_UDL=m -CONFIG_DRM_AST=m -CONFIG_DRM_QXL=m -CONFIG_DRM_VIRTIO_GPU=m -CONFIG_DRM_PANEL_AUO_A030JTN01=m -CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m -CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_ANALOGIX_ANX78XX=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_APPLETBDRM=m -CONFIG_DRM_BOCHS=m -CONFIG_DRM_CIRRUS_QEMU=m -CONFIG_DRM_GM12U320=m -CONFIG_DRM_PANEL_MIPI_DBI=m -CONFIG_TINYDRM_HX8357D=m -CONFIG_TINYDRM_ILI9163=m -CONFIG_TINYDRM_ILI9225=m -CONFIG_TINYDRM_ILI9341=m -CONFIG_TINYDRM_ILI9486=m -CONFIG_TINYDRM_MI0283QT=m -CONFIG_TINYDRM_REPAPER=m -CONFIG_TINYDRM_SHARP_MEMORY=m -CONFIG_DRM_XEN_FRONTEND=m -CONFIG_DRM_VBOXVIDEO=m -CONFIG_DRM_GUD=m -CONFIG_DRM_ST7571_I2C=m -CONFIG_DRM_ST7586=m -CONFIG_DRM_ST7735R=m -CONFIG_DRM_SSD130X=m -CONFIG_DRM_SSD130X_I2C=m -CONFIG_DRM_SSD130X_SPI=m -CONFIG_FB=y -CONFIG_FB_CIRRUS=m -CONFIG_FB_PM2=m -CONFIG_FB_PM2_FIFO_DISCONNECT=y -CONFIG_FB_CYBER2000=m -CONFIG_FB_ARC=m -CONFIG_FB_ASILIANT=y -CONFIG_FB_IMSTT=y -CONFIG_FB_VGA16=m -CONFIG_FB_UVESA=m -CONFIG_FB_VESA=y -CONFIG_FB_EFI=y -CONFIG_FB_N411=m -CONFIG_FB_HGA=m -CONFIG_FB_OPENCORES=m -CONFIG_FB_S1D13XXX=m -CONFIG_FB_RIVA=m -CONFIG_FB_RIVA_I2C=y -CONFIG_FB_I740=m -CONFIG_FB_MATROX=m -CONFIG_FB_MATROX_MILLENIUM=y -CONFIG_FB_MATROX_MYSTIQUE=y -CONFIG_FB_MATROX_G=y -CONFIG_FB_MATROX_I2C=m -CONFIG_FB_MATROX_MAVEN=m -CONFIG_FB_RADEON=m -CONFIG_FB_ATY128=m -CONFIG_FB_ATY=m -CONFIG_FB_ATY_CT=y -CONFIG_FB_ATY_GX=y -CONFIG_FB_S3=m -CONFIG_FB_SAVAGE=m -CONFIG_FB_SAVAGE_I2C=y -CONFIG_FB_SIS=m -CONFIG_FB_SIS_300=y -CONFIG_FB_SIS_315=y -CONFIG_FB_VIA=m -CONFIG_FB_VIA_X_COMPATIBILITY=y -CONFIG_FB_NEOMAGIC=m -CONFIG_FB_KYRO=m -CONFIG_FB_3DFX=m -# CONFIG_FB_3DFX_I2C is not set -CONFIG_FB_VOODOO1=m -CONFIG_FB_VT8623=m -CONFIG_FB_TRIDENT=m -CONFIG_FB_ARK=m -CONFIG_FB_PM3=m -CONFIG_FB_CARMINE=m -CONFIG_FB_SM501=m -CONFIG_FB_SMSCUFX=m -CONFIG_FB_UDL=m -CONFIG_FB_IBM_GXT4500=m -CONFIG_XEN_FBDEV_FRONTEND=m -CONFIG_FB_METRONOME=m -CONFIG_FB_MB862XX=m -CONFIG_FB_SIMPLE=y -CONFIG_FB_SSD1307=m -CONFIG_FB_SM712=m -CONFIG_LCD_CLASS_DEVICE=m -CONFIG_LCD_L4F00242T03=m -CONFIG_LCD_LMS283GF05=m -CONFIG_LCD_LTV350QV=m -CONFIG_LCD_ILI922X=m -CONFIG_LCD_TDO24M=m -CONFIG_LCD_VGG2432A4=m -CONFIG_LCD_PLATFORM=m -CONFIG_LCD_AMS369FG06=m -CONFIG_LCD_LMS501KF03=m -CONFIG_LCD_HX8357=m -CONFIG_LCD_OTM3225A=m -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_KTD253=m -CONFIG_BACKLIGHT_KTZ8866=m -CONFIG_BACKLIGHT_LM3533=m -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_DA903X=m -CONFIG_BACKLIGHT_DA9052=m -CONFIG_BACKLIGHT_MAX8925=m -CONFIG_BACKLIGHT_MT6370=m -CONFIG_BACKLIGHT_APPLE=m -CONFIG_BACKLIGHT_QCOM_WLED=m -CONFIG_BACKLIGHT_RT4831=m -CONFIG_BACKLIGHT_SAHARA=m -CONFIG_BACKLIGHT_WM831X=m -CONFIG_BACKLIGHT_ADP5520=m -CONFIG_BACKLIGHT_ADP8860=m -CONFIG_BACKLIGHT_ADP8870=m -CONFIG_BACKLIGHT_88PM860X=m -CONFIG_BACKLIGHT_AAT2870=m -CONFIG_BACKLIGHT_LM3509=m -CONFIG_BACKLIGHT_LM3630A=m -CONFIG_BACKLIGHT_LM3639=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_BACKLIGHT_LP8788=m -CONFIG_BACKLIGHT_MP3309C=m -CONFIG_BACKLIGHT_PANDORA=m -CONFIG_BACKLIGHT_SKY81452=m -CONFIG_BACKLIGHT_AS3711=m -CONFIG_BACKLIGHT_GPIO=m -CONFIG_BACKLIGHT_LV5207LP=m -CONFIG_BACKLIGHT_BD6107=m -CONFIG_BACKLIGHT_ARCXCNN=m -CONFIG_BACKLIGHT_RAVE_SP=m -CONFIG_FIRMWARE_EDID=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -CONFIG_DRM_ACCEL=y -CONFIG_DRM_ACCEL_AMDXDNA=m -CONFIG_DRM_ACCEL_HABANALABS=m -CONFIG_DRM_ACCEL_IVPU=m -CONFIG_DRM_ACCEL_QAIC=m -CONFIG_SOUND=m -# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set -CONFIG_SND=m -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_HRTIMER=m -CONFIG_SND_CTL_INPUT_VALIDATION=y -CONFIG_SND_UTIMER=y -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_DUMMY=m -CONFIG_SND_ALOOP=m -CONFIG_SND_VIRMIDI=m -CONFIG_SND_MTPAV=m -CONFIG_SND_MTS64=m -CONFIG_SND_SERIAL_U16550=m -CONFIG_SND_MPU401=m -CONFIG_SND_PORTMAN2X4=m -CONFIG_SND_AC97_POWER_SAVE=y -CONFIG_SND_AD1889=m -CONFIG_SND_ALS300=m -CONFIG_SND_ALS4000=m -CONFIG_SND_ALI5451=m -CONFIG_SND_ASIHPI=m -CONFIG_SND_ATIIXP=m -CONFIG_SND_ATIIXP_MODEM=m -CONFIG_SND_AU8810=m -CONFIG_SND_AU8820=m -CONFIG_SND_AU8830=m -CONFIG_SND_AW2=m -CONFIG_SND_AZT3328=m -CONFIG_SND_BT87X=m -CONFIG_SND_CA0106=m -CONFIG_SND_CMIPCI=m -CONFIG_SND_OXYGEN=m -CONFIG_SND_CS4281=m -CONFIG_SND_CS46XX=m -CONFIG_SND_CTXFI=m -CONFIG_SND_DARLA20=m -CONFIG_SND_GINA20=m -CONFIG_SND_LAYLA20=m -CONFIG_SND_DARLA24=m -CONFIG_SND_GINA24=m -CONFIG_SND_LAYLA24=m -CONFIG_SND_MONA=m -CONFIG_SND_MIA=m -CONFIG_SND_ECHO3G=m -CONFIG_SND_INDIGO=m -CONFIG_SND_INDIGOIO=m -CONFIG_SND_INDIGODJ=m -CONFIG_SND_INDIGOIOX=m -CONFIG_SND_INDIGODJX=m -CONFIG_SND_EMU10K1=m -CONFIG_SND_EMU10K1X=m -CONFIG_SND_ENS1370=m -CONFIG_SND_ENS1371=m -CONFIG_SND_ES1938=m -CONFIG_SND_ES1968=m -CONFIG_SND_ES1968_INPUT=y -CONFIG_SND_ES1968_RADIO=y -CONFIG_SND_FM801=m -CONFIG_SND_FM801_TEA575X_BOOL=y -CONFIG_SND_HDSP=m -CONFIG_SND_HDSPM=m -CONFIG_SND_ICE1712=m -CONFIG_SND_ICE1724=m -CONFIG_SND_INTEL8X0=m -CONFIG_SND_INTEL8X0M=m -CONFIG_SND_KORG1212=m -CONFIG_SND_LOLA=m -CONFIG_SND_LX6464ES=m -CONFIG_SND_MAESTRO3=m -CONFIG_SND_MAESTRO3_INPUT=y -CONFIG_SND_MIXART=m -CONFIG_SND_NM256=m -CONFIG_SND_PCXHR=m -CONFIG_SND_RIPTIDE=m -CONFIG_SND_RME32=m -CONFIG_SND_RME96=m -CONFIG_SND_RME9652=m -CONFIG_SND_SONICVIBES=m -CONFIG_SND_TRIDENT=m -CONFIG_SND_VIA82XX=m -CONFIG_SND_VIA82XX_MODEM=m -CONFIG_SND_VIRTUOSO=m -CONFIG_SND_VX222=m -CONFIG_SND_YMFPCI=m -CONFIG_SND_HDA_HWDEP=y -CONFIG_SND_HDA_INPUT_BEEP=y -CONFIG_SND_HDA_INPUT_BEEP_MODE=0 -CONFIG_SND_HDA_PATCH_LOADER=y -CONFIG_SND_HDA_INTEL=m -CONFIG_SND_HDA_ACPI=m -CONFIG_SND_HDA_CODEC_ANALOG=m -CONFIG_SND_HDA_CODEC_SIGMATEL=m -CONFIG_SND_HDA_CODEC_VIA=m -CONFIG_SND_HDA_CODEC_CONEXANT=m -CONFIG_SND_HDA_CODEC_SENARYTECH=m -CONFIG_SND_HDA_CODEC_CA0110=m -CONFIG_SND_HDA_CODEC_CA0132=m -CONFIG_SND_HDA_CODEC_CMEDIA=m -CONFIG_SND_HDA_CODEC_CM9825=m -CONFIG_SND_HDA_CODEC_SI3054=m -CONFIG_SND_HDA_CODEC_REALTEK=m -CONFIG_SND_HDA_CODEC_CIRRUS=m -CONFIG_SND_HDA_CODEC_CS8409=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y -CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m -CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m -CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m -CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m -CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m -CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m -CONFIG_SND_INTEL_BYT_PREFER_SOF=y -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_AUDIO_MIDI_V2=y -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_USX2Y=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_USB_US122L=m -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_AUDIO_QMI=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m -CONFIG_SND_DICE=m -CONFIG_SND_OXFW=m -CONFIG_SND_ISIGHT=m -CONFIG_SND_FIREWORKS=m -CONFIG_SND_BEBOB=m -CONFIG_SND_FIREWIRE_DIGI00X=m -CONFIG_SND_FIREWIRE_TASCAM=m -CONFIG_SND_FIREWIRE_MOTU=m -CONFIG_SND_FIREFACE=m -CONFIG_SND_VXPOCKET=m -CONFIG_SND_PDAUDIOCF=m -CONFIG_SND_SOC=m -CONFIG_SND_SOC_USB=m -CONFIG_SND_SOC_ADI_AXI_I2S=m -CONFIG_SND_SOC_ADI_AXI_SPDIF=m -CONFIG_SND_SOC_AMD_ACP=m -CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m -CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m -CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m -CONFIG_SND_SOC_AMD_ACP3x=m -CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m -CONFIG_SND_SOC_AMD_RENOIR=m -CONFIG_SND_SOC_AMD_RENOIR_MACH=m -CONFIG_SND_SOC_AMD_ACP5x=m -CONFIG_SND_SOC_AMD_VANGOGH_MACH=m -CONFIG_SND_SOC_AMD_ACP6x=m -CONFIG_SND_SOC_AMD_YC_MACH=m -CONFIG_SND_SOC_AMD_ACP_COMMON=m -CONFIG_SND_SOC_AMD_ACP_PCI=m -CONFIG_SND_AMD_ASOC_RENOIR=m -CONFIG_SND_AMD_ASOC_REMBRANDT=m -CONFIG_SND_AMD_ASOC_ACP63=m -CONFIG_SND_AMD_ASOC_ACP70=m -CONFIG_SND_SOC_AMD_LEGACY_MACH=m -CONFIG_SND_SOC_AMD_SOF_MACH=m -CONFIG_SND_SOC_AMD_SOF_SDW_MACH=m -CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH=m -CONFIG_SND_SOC_AMD_RPL_ACP6x=m -CONFIG_SND_SOC_AMD_PS=m -CONFIG_SND_SOC_AMD_PS_MACH=m -CONFIG_SND_BCM63XX_I2S_WHISTLER=m -CONFIG_SND_DESIGNWARE_I2S=m -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_FSL_MQS=m -CONFIG_SND_SOC_FSL_AUDMIX=m -CONFIG_SND_SOC_FSL_SSI=m -CONFIG_SND_SOC_FSL_SPDIF=m -CONFIG_SND_SOC_FSL_ESAI=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_SOC_FSL_XCVR=m -CONFIG_SND_SOC_IMX_AUDMUX=m -CONFIG_SND_SOC_CHV3_I2S=m -CONFIG_SND_I2S_HI6210_I2S=m -CONFIG_SND_SOC_INTEL_CATPT=m -CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m -CONFIG_SND_SOC_INTEL_AVS=m -CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m -CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m -CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336=m -CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m -CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m -CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=m -CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m -CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m -CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m -CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A=m -CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m -CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m -CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y -CONFIG_SND_SOC_INTEL_HASWELL_MACH=m -CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m -CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m -CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m -CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m -CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m -CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m -CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m -CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m -CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m -CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m -CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m -CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m -CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m -CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m -CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m -CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m -CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m -CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m -CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=m -CONFIG_SND_SOC_MTK_BTCVSD=m -CONFIG_SND_SOC_XILINX_I2S=m -CONFIG_SND_SOC_XTFPGA_I2S=m -CONFIG_SND_SOC_SOF_TOPLEVEL=y -CONFIG_SND_SOC_SOF_PCI=m -CONFIG_SND_SOC_SOF_ACPI=m -CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m -CONFIG_SND_SOC_SOF_AMD_RENOIR=m -CONFIG_SND_SOC_SOF_AMD_VANGOGH=m -CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m -CONFIG_SND_SOC_SOF_AMD_ACP63=m -CONFIG_SND_SOC_SOF_AMD_ACP70=m -CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y -CONFIG_SND_SOC_SOF_HDA_LINK=y -CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y -CONFIG_SND_SOC_AC97_CODEC=m -CONFIG_SND_SOC_ADAU1372_I2C=m -CONFIG_SND_SOC_ADAU1372_SPI=m -CONFIG_SND_SOC_ADAU1373=m -CONFIG_SND_SOC_ADAU1701=m -CONFIG_SND_SOC_ADAU1761_I2C=m -CONFIG_SND_SOC_ADAU1761_SPI=m -CONFIG_SND_SOC_ADAU7118_HW=m -CONFIG_SND_SOC_ADAU7118_I2C=m -CONFIG_SND_SOC_AK4104=m -CONFIG_SND_SOC_AK4118=m -CONFIG_SND_SOC_AK4375=m -CONFIG_SND_SOC_AK4458=m -CONFIG_SND_SOC_AK4554=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_AK4619=m -CONFIG_SND_SOC_AK4642=m -CONFIG_SND_SOC_AK5386=m -CONFIG_SND_SOC_AK5558=m -CONFIG_SND_SOC_ALC5623=m -CONFIG_SND_SOC_AUDIO_IIO_AUX=m -CONFIG_SND_SOC_AW8738=m -CONFIG_SND_SOC_AW88395=m -CONFIG_SND_SOC_AW88166=m -CONFIG_SND_SOC_AW88261=m -CONFIG_SND_SOC_AW88081=m -CONFIG_SND_SOC_AW87390=m -CONFIG_SND_SOC_AW88399=m -CONFIG_SND_SOC_BD28623=m -CONFIG_SND_SOC_BT_SCO=m -CONFIG_SND_SOC_CHV3_CODEC=m -CONFIG_SND_SOC_CS35L32=m -CONFIG_SND_SOC_CS35L33=m -CONFIG_SND_SOC_CS35L34=m -CONFIG_SND_SOC_CS35L35=m -CONFIG_SND_SOC_CS35L36=m -CONFIG_SND_SOC_CS35L45_SPI=m -CONFIG_SND_SOC_CS35L45_I2C=m -CONFIG_SND_SOC_CS35L56_I2C=m -CONFIG_SND_SOC_CS40L50=m -CONFIG_SND_SOC_CS42L51_I2C=m -CONFIG_SND_SOC_CS42L52=m -CONFIG_SND_SOC_CS42L56=m -CONFIG_SND_SOC_CS42L73=m -CONFIG_SND_SOC_CS42L83=m -CONFIG_SND_SOC_CS42L84=m -CONFIG_SND_SOC_CS4234=m -CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4270=m -CONFIG_SND_SOC_CS4271_I2C=m -CONFIG_SND_SOC_CS4271_SPI=m -CONFIG_SND_SOC_CS42XX8_I2C=m -CONFIG_SND_SOC_CS43130=m -CONFIG_SND_SOC_CS4341=m -CONFIG_SND_SOC_CS4349=m -CONFIG_SND_SOC_CS48L32=m -CONFIG_SND_SOC_CS53L30=m -CONFIG_SND_SOC_CS530X_I2C=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_ES8311=m -CONFIG_SND_SOC_ES8323=m -CONFIG_SND_SOC_ES8328_I2C=m -CONFIG_SND_SOC_ES8328_SPI=m -CONFIG_SND_SOC_ES8375=m -CONFIG_SND_SOC_ES8389=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_ICS43432=m -CONFIG_SND_SOC_IDT821034=m -CONFIG_SND_SOC_MAX98088=m -CONFIG_SND_SOC_MAX98504=m -CONFIG_SND_SOC_MAX9867=m -CONFIG_SND_SOC_MAX98520=m -CONFIG_SND_SOC_MAX98396=m -CONFIG_SND_SOC_MAX9860=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM1681=m -CONFIG_SND_SOC_PCM1789_I2C=m -CONFIG_SND_SOC_PCM179X_I2C=m -CONFIG_SND_SOC_PCM179X_SPI=m -CONFIG_SND_SOC_PCM186X_I2C=m -CONFIG_SND_SOC_PCM186X_SPI=m -CONFIG_SND_SOC_PCM3060_I2C=m -CONFIG_SND_SOC_PCM3060_SPI=m -CONFIG_SND_SOC_PCM3168A_SPI=m -CONFIG_SND_SOC_PCM5102A=m -CONFIG_SND_SOC_PCM512x_SPI=m -CONFIG_SND_SOC_PCM6240=m -CONFIG_SND_SOC_PEB2466=m -CONFIG_SND_SOC_RT1017_SDCA_SDW=m -CONFIG_SND_SOC_RT5616=m -CONFIG_SND_SOC_RT5631=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_RT9120=m -CONFIG_SND_SOC_RT9123=m -CONFIG_SND_SOC_RT9123P=m -CONFIG_SND_SOC_RTQ9124=m -CONFIG_SND_SOC_RTQ9128=m -CONFIG_SND_SOC_SGTL5000=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -CONFIG_SND_SOC_SMA1303=m -CONFIG_SND_SOC_SMA1307=m -CONFIG_SND_SOC_SPDIF=m -CONFIG_SND_SOC_SRC4XXX_I2C=m -CONFIG_SND_SOC_SSM2305=m -CONFIG_SND_SOC_SSM2518=m -CONFIG_SND_SOC_SSM2602_SPI=m -CONFIG_SND_SOC_SSM2602_I2C=m -CONFIG_SND_SOC_STA32X=m -CONFIG_SND_SOC_STA350=m -CONFIG_SND_SOC_STI_SAS=m -CONFIG_SND_SOC_TAS2552=m -CONFIG_SND_SOC_TAS2562=m -CONFIG_SND_SOC_TAS2764=m -CONFIG_SND_SOC_TAS2770=m -CONFIG_SND_SOC_TAS2780=m -CONFIG_SND_SOC_TAS2781_I2C=m -CONFIG_SND_SOC_TAS5086=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TAS5720=m -CONFIG_SND_SOC_TAS5805M=m -CONFIG_SND_SOC_TAS6424=m -CONFIG_SND_SOC_TDA7419=m -CONFIG_SND_SOC_TFA9879=m -CONFIG_SND_SOC_TFA989X=m -CONFIG_SND_SOC_TLV320ADC3XXX=m -CONFIG_SND_SOC_TLV320AIC23_I2C=m -CONFIG_SND_SOC_TLV320AIC23_SPI=m -CONFIG_SND_SOC_TLV320AIC31XX=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_TLV320AIC32X4_SPI=m -CONFIG_SND_SOC_TLV320AIC3X_I2C=m -CONFIG_SND_SOC_TLV320AIC3X_SPI=m -CONFIG_SND_SOC_TLV320ADCX140=m -CONFIG_SND_SOC_TSCS42XX=m -CONFIG_SND_SOC_TSCS454=m -CONFIG_SND_SOC_UDA1334=m -CONFIG_SND_SOC_UDA1342=m -CONFIG_SND_SOC_WCD937X_SDW=m -CONFIG_SND_SOC_WCD938X_SDW=m -CONFIG_SND_SOC_WM8510=m -CONFIG_SND_SOC_WM8523=m -CONFIG_SND_SOC_WM8524=m -CONFIG_SND_SOC_WM8580=m -CONFIG_SND_SOC_WM8711=m -CONFIG_SND_SOC_WM8728=m -CONFIG_SND_SOC_WM8731_I2C=m -CONFIG_SND_SOC_WM8731_SPI=m -CONFIG_SND_SOC_WM8737=m -CONFIG_SND_SOC_WM8741=m -CONFIG_SND_SOC_WM8750=m -CONFIG_SND_SOC_WM8753=m -CONFIG_SND_SOC_WM8770=m -CONFIG_SND_SOC_WM8776=m -CONFIG_SND_SOC_WM8782=m -CONFIG_SND_SOC_WM8804_SPI=m -CONFIG_SND_SOC_WM8903=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8940=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8961=m -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8974=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WM8985=m -CONFIG_SND_SOC_WM8998=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_WSA883X=m -CONFIG_SND_SOC_WSA884X=m -CONFIG_SND_SOC_ZL38060=m -CONFIG_SND_SOC_MAX9759=m -CONFIG_SND_SOC_MT6351=m -CONFIG_SND_SOC_MT6357=m -CONFIG_SND_SOC_MT6358=m -CONFIG_SND_SOC_MT6660=m -CONFIG_SND_SOC_NAU8540=m -CONFIG_SND_SOC_NAU8810=m -CONFIG_SND_SOC_NAU8822=m -CONFIG_SND_SOC_NTP8918=m -CONFIG_SND_SOC_NTP8835=m -CONFIG_SND_SOC_TPA6130A2=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SOC_LPASS_RX_MACRO=m -CONFIG_SND_SOC_LPASS_TX_MACRO=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_HDMI_LPE_AUDIO=m -CONFIG_SND_XEN_FRONTEND=m -CONFIG_SND_VIRTIO=m -CONFIG_HID=m -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HIDRAW=y -CONFIG_UHID=m -CONFIG_HID_A4TECH=m -CONFIG_HID_ACCUTOUCH=m -CONFIG_HID_ACRUX=m -CONFIG_HID_ACRUX_FF=y -CONFIG_HID_APPLE=m -CONFIG_HID_APPLEIR=m -CONFIG_HID_APPLETB_KBD=m -CONFIG_HID_ASUS=m -CONFIG_HID_AUREAL=m -CONFIG_HID_BELKIN=m -CONFIG_HID_BETOP_FF=m -CONFIG_HID_BIGBEN_FF=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CORSAIR=m -CONFIG_HID_COUGAR=m -CONFIG_HID_MACALLY=m -CONFIG_HID_PRODIKEYS=m -CONFIG_HID_CMEDIA=m -CONFIG_HID_CP2112=m -CONFIG_HID_CREATIVE_SB0540=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DRAGONRISE=m -CONFIG_DRAGONRISE_FF=y -CONFIG_HID_EMS_FF=m -CONFIG_HID_ELAN=m -CONFIG_HID_ELECOM=m -CONFIG_HID_ELO=m -CONFIG_HID_EVISION=m -CONFIG_HID_EZKEY=m -CONFIG_HID_FT260=m -CONFIG_HID_GEMBIRD=m -CONFIG_HID_GFRM=m -CONFIG_HID_GLORIOUS=m -CONFIG_HID_HOLTEK=m -CONFIG_HOLTEK_FF=y -CONFIG_HID_GOODIX_SPI=m -CONFIG_HID_GOOGLE_HAMMER=m -CONFIG_HID_GOOGLE_STADIA_FF=m -CONFIG_HID_VIVALDI=m -CONFIG_HID_GT683R=m -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_KYSONA=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_VIEWSONIC=m -CONFIG_HID_VRC2=m -CONFIG_HID_XIAOMI=m -CONFIG_HID_GYRATION=m -CONFIG_HID_ICADE=m -CONFIG_HID_ITE=m -CONFIG_HID_JABRA=m -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LCPOWER=m -CONFIG_HID_LENOVO=m -CONFIG_HID_LETSKETCH=m -CONFIG_HID_LOGITECH=m -CONFIG_HID_LOGITECH_DJ=m -CONFIG_LOGITECH_FF=y -CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_LOGIG940_FF=y -CONFIG_HID_MAGICMOUSE=m -CONFIG_HID_MALTRON=m -CONFIG_HID_MAYFLASH=m -CONFIG_HID_MEGAWORLD_FF=m -CONFIG_HID_REDRAGON=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NINTENDO=m -CONFIG_NINTENDO_FF=y -CONFIG_HID_NTI=m -CONFIG_HID_NTRIG=m -CONFIG_HID_NVIDIA_SHIELD=m -CONFIG_NVIDIA_SHIELD_FF=y -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_PANTHERLORD_FF=y -CONFIG_HID_PENMOUNT=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PICOLCD_CIR=y -CONFIG_HID_PLANTRONICS=m -CONFIG_HID_PLAYSTATION=m -CONFIG_PLAYSTATION_FF=y -CONFIG_HID_PXRC=m -CONFIG_HID_RAZER=m -CONFIG_HID_PRIMAX=m -CONFIG_HID_RETRODE=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SEMITEK=m -CONFIG_HID_SIGMAMICRO=m -CONFIG_HID_SONY=m -CONFIG_SONY_FF=y -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_STEAM=m -CONFIG_STEAM_FF=y -CONFIG_HID_STEELSERIES=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_RMI=m -CONFIG_HID_GREENASIA=m -CONFIG_GREENASIA_FF=y -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_SMARTJOYPLUS_FF=y -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_TOPRE=m -CONFIG_HID_THINGM=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_THRUSTMASTER_FF=y -CONFIG_HID_UDRAW_PS3=m -CONFIG_HID_U2FZERO=m -CONFIG_HID_UNIVERSAL_PIDFF=m -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -CONFIG_HID_WINWING=m -CONFIG_HID_XINMO=m -CONFIG_HID_ZEROPLUS=m -CONFIG_ZEROPLUS_FF=y -CONFIG_HID_ZYDACRON=m -CONFIG_HID_SENSOR_HUB=m -CONFIG_HID_SENSOR_CUSTOM_SENSOR=m -CONFIG_HID_ALPS=m -CONFIG_HID_MCP2200=m -CONFIG_HID_MCP2221=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_INTEL_ISH_HID=m -CONFIG_AMD_SFH_HID=m -CONFIG_SURFACE_HID=m -CONFIG_SURFACE_KBD=m -CONFIG_INTEL_THC_HID=m -CONFIG_INTEL_QUICKSPI=m -CONFIG_INTEL_QUICKI2C=m -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_KBD=m -CONFIG_USB_MOUSE=m -CONFIG_USB_LED_TRIG=y -CONFIG_USB_CONN_GPIO=m -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=m -CONFIG_USB_MON=m -CONFIG_USB_C67X00_HCD=m -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_SIDEBAND=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OXU210HP_HCD=m -CONFIG_USB_ISP116X_HCD=m -CONFIG_USB_MAX3421_HCD=m -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_SL811_HCD=m -CONFIG_USB_SL811_HCD_ISO=y -CONFIG_USB_SL811_CS=m -CONFIG_USB_R8A66597_HCD=m -CONFIG_USB_HCD_BCMA=m -CONFIG_USB_HCD_SSB=m -CONFIG_USB_XEN_HCD=m -CONFIG_USB_PRINTER=m -CONFIG_USB_TMC=m -CONFIG_USB_STORAGE=m -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USBIP_CORE=m -CONFIG_USBIP_VHCI_HCD=m -CONFIG_USBIP_HOST=m -CONFIG_USBIP_VUDC=m -CONFIG_USB_CDNS_SUPPORT=m -CONFIG_USB_CDNS3=m -CONFIG_USB_CDNSP_PCI=m -CONFIG_USB_CDNSP_GADGET=y -CONFIG_USB_CDNSP_HOST=y -CONFIG_USB_MUSB_HDRC=m -CONFIG_MUSB_PIO_ONLY=y -CONFIG_USB_DWC3=m -CONFIG_USB_DWC3_ULPI=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_PCI=m -CONFIG_USB_CHIPIDEA=m -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_F81232=m -CONFIG_USB_SERIAL_F8153X=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_METRO=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7715_PARPORT=y -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MXUPORT=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_WISHBONE=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_XR=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_USS720=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_APPLE_MFI_FASTCHARGE=m -CONFIG_USB_LJCA=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_YUREX=m -CONFIG_USB_HUB_USB251XB=m -CONFIG_USB_HSIC_USB3503=m -CONFIG_USB_HSIC_USB4604=m -CONFIG_USB_LINK_LAYER_TEST=m -CONFIG_USB_CHAOSKEY=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GPIO_VBUS=m -CONFIG_TAHVO_USB=m -CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y -CONFIG_USB_ISP1301=m -CONFIG_USB_GADGET=m -CONFIG_USB_GR_UDC=m -CONFIG_USB_R8A66597=m -CONFIG_USB_PXA27X=m -CONFIG_USB_BDC_UDC=m -CONFIG_USB_AMD5536UDC=m -CONFIG_USB_NET2280=m -CONFIG_USB_GOKU=m -CONFIG_USB_EG20T=m -CONFIG_USB_MAX3420_UDC=m -CONFIG_USB_CDNS2_UDC=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_PHONET=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_MIDI2=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m -CONFIG_GADGET_UAC1=y -CONFIG_USB_ETH=m -CONFIG_USB_ETH_EEM=y -CONFIG_USB_G_NCM=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_FUNCTIONFS_ETH=y -CONFIG_USB_FUNCTIONFS_RNDIS=y -CONFIG_USB_FUNCTIONFS_GENERIC=y -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_GADGET_TARGET=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_NOKIA=m -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_HID=m -CONFIG_USB_G_DBGP=m -CONFIG_USB_G_WEBCAM=m -CONFIG_USB_RAW_GADGET=m -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_RT1711H=m -CONFIG_TYPEC_MT6360=m -CONFIG_TYPEC_TCPCI_MT6370=m -CONFIG_TYPEC_TCPCI_MAXIM=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_UCSI=m -CONFIG_UCSI_CCG=m -CONFIG_UCSI_ACPI=m -CONFIG_UCSI_STM32G0=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_TYPEC_ANX7411=m -CONFIG_TYPEC_RT1719=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_TYPEC_STUSB160X=m -CONFIG_TYPEC_WUSB3801=m -CONFIG_TYPEC_MUX_FSA4480=m -CONFIG_TYPEC_MUX_GPIO_SBU=m -CONFIG_TYPEC_MUX_PI3USB30532=m -CONFIG_TYPEC_MUX_INTEL_PMC=m -CONFIG_TYPEC_MUX_NB7VPQ904M=m -CONFIG_TYPEC_MUX_PS883X=m -CONFIG_TYPEC_MUX_PTN36502=m -CONFIG_TYPEC_MUX_TUSB1046=m -CONFIG_TYPEC_MUX_WCD939X_USBSS=m -CONFIG_TYPEC_DP_ALTMODE=m -CONFIG_TYPEC_NVIDIA_ALTMODE=m -CONFIG_TYPEC_TBT_ALTMODE=m -CONFIG_USB_ROLES_INTEL_XHCI=m -CONFIG_MMC=y -CONFIG_SDIO_UART=m -CONFIG_MMC_CRYPTO=y -CONFIG_MMC_SDHCI=m -CONFIG_MMC_SDHCI_PCI=m -CONFIG_MMC_SDHCI_ACPI=m -CONFIG_MMC_SDHCI_PLTFM=m -CONFIG_MMC_SDHCI_F_SDH30=m -CONFIG_MMC_WBSD=m -CONFIG_MMC_ALCOR=m -CONFIG_MMC_TIFM_SD=m -CONFIG_MMC_SPI=m -CONFIG_MMC_SDRICOH_CS=m -CONFIG_MMC_CB710=m -CONFIG_MMC_VIA_SDMMC=m -CONFIG_MMC_VUB300=m -CONFIG_MMC_USHC=m -CONFIG_MMC_USDHI6ROL0=m -CONFIG_MMC_REALTEK_PCI=m -CONFIG_MMC_REALTEK_USB=m -CONFIG_MMC_TOSHIBA_PCI=m -CONFIG_MMC_MTK=m -CONFIG_MMC_SDHCI_XENON=m -CONFIG_SCSI_UFSHCD=m -CONFIG_SCSI_UFS_CRYPTO=y -CONFIG_SCSI_UFS_HWMON=y -CONFIG_SCSI_UFSHCD_PCI=m -CONFIG_SCSI_UFSHCD_PLATFORM=m -CONFIG_SCSI_UFS_CDNS_PLATFORM=m -CONFIG_MEMSTICK=m -CONFIG_MSPRO_BLOCK=m -CONFIG_MS_BLOCK=m -CONFIG_MEMSTICK_TIFM_MS=m -CONFIG_MEMSTICK_JMICRON_38X=m -CONFIG_MEMSTICK_R592=m -CONFIG_MEMSTICK_REALTEK_USB=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_CLASS_FLASH=m -CONFIG_LEDS_CLASS_MULTICOLOR=m -CONFIG_LEDS_88PM860X=m -CONFIG_LEDS_APU=m -CONFIG_LEDS_AW200XX=m -CONFIG_LEDS_CHT_WCOVE=m -CONFIG_LEDS_LM3530=m -CONFIG_LEDS_LM3532=m -CONFIG_LEDS_LM3533=m -CONFIG_LEDS_LM3642=m -CONFIG_LEDS_MT6323=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_LP3944=m -CONFIG_LEDS_LP3952=m -CONFIG_LEDS_LP50XX=m -CONFIG_LEDS_LP8788=m -CONFIG_LEDS_PCA955X=m -CONFIG_LEDS_PCA963X=m -CONFIG_LEDS_PCA995X=m -CONFIG_LEDS_QNAP_MCU=m -CONFIG_LEDS_WM831X_STATUS=m -CONFIG_LEDS_WM8350=m -CONFIG_LEDS_DA903X=m -CONFIG_LEDS_DA9052=m -CONFIG_LEDS_DAC124S085=m -CONFIG_LEDS_PWM=m -CONFIG_LEDS_REGULATOR=m -CONFIG_LEDS_BD2606MVV=m -CONFIG_LEDS_BD2802=m -CONFIG_LEDS_INTEL_SS4200=m -CONFIG_LEDS_LT3593=m -CONFIG_LEDS_ADP5520=m -CONFIG_LEDS_MC13783=m -CONFIG_LEDS_TCA6507=m -CONFIG_LEDS_TLC591XX=m -CONFIG_LEDS_MAX77705=m -CONFIG_LEDS_MAX8997=m -CONFIG_LEDS_LM355x=m -CONFIG_LEDS_MENF21BMC=m -CONFIG_LEDS_IS31FL319X=m -CONFIG_LEDS_UPBOARD=m -CONFIG_LEDS_BLINKM=m -CONFIG_LEDS_BLINKM_MULTICOLOR=y -CONFIG_LEDS_MLXCPLD=m -CONFIG_LEDS_MLXREG=m -CONFIG_LEDS_USER=m -CONFIG_LEDS_NIC78BX=m -CONFIG_LEDS_SPI_BYTE=m -CONFIG_LEDS_LM36274=m -CONFIG_LEDS_AS3645A=m -CONFIG_LEDS_LM3601X=m -CONFIG_LEDS_MT6370_FLASH=m -CONFIG_LEDS_SGM3140=m -CONFIG_LEDS_KTD202X=m -CONFIG_LEDS_PWM_MULTICOLOR=m -CONFIG_LEDS_MT6370_RGB=m -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_ONESHOT=m -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEDS_TRIGGER_NETDEV=m -CONFIG_LEDS_TRIGGER_PATTERN=m -CONFIG_LEDS_TRIGGER_TTY=m -CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m -CONFIG_ACCESSIBILITY=y -CONFIG_A11Y_BRAILLE_CONSOLE=y -CONFIG_SPEAKUP=m -CONFIG_SPEAKUP_SYNTH_SOFT=m -CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_MAD=m -CONFIG_INFINIBAND_USER_ACCESS=m -CONFIG_INFINIBAND_BNXT_RE=m -CONFIG_INFINIBAND_CXGB4=m -CONFIG_INFINIBAND_EFA=m -CONFIG_INFINIBAND_ERDMA=m -CONFIG_INFINIBAND_HFI1=m -CONFIG_INFINIBAND_IRDMA=m -CONFIG_MLX4_INFINIBAND=m -CONFIG_MLX5_INFINIBAND=m -CONFIG_INFINIBAND_MTHCA=m -# CONFIG_INFINIBAND_MTHCA_DEBUG is not set -CONFIG_INFINIBAND_OCRDMA=m -CONFIG_INFINIBAND_QEDR=m -CONFIG_INFINIBAND_USNIC=m -CONFIG_INFINIBAND_VMWARE_PVRDMA=m -CONFIG_INFINIBAND_RDMAVT=m -CONFIG_RDMA_RXE=m -CONFIG_RDMA_SIW=m -CONFIG_INFINIBAND_IPOIB=m -CONFIG_INFINIBAND_IPOIB_CM=y -# CONFIG_INFINIBAND_IPOIB_DEBUG is not set -CONFIG_INFINIBAND_SRP=m -CONFIG_INFINIBAND_SRPT=m -CONFIG_INFINIBAND_ISER=m -CONFIG_INFINIBAND_ISERT=m -CONFIG_INFINIBAND_RTRS_CLIENT=m -CONFIG_INFINIBAND_RTRS_SERVER=m -CONFIG_INFINIBAND_OPA_VNIC=m -CONFIG_EDAC=y -# CONFIG_EDAC_LEGACY_SYSFS is not set -CONFIG_EDAC_DECODE_MCE=m -CONFIG_EDAC_GHES=y -CONFIG_EDAC_SCRUB=y -CONFIG_EDAC_ECS=y -CONFIG_EDAC_MEM_REPAIR=y -CONFIG_EDAC_AMD64=m -CONFIG_EDAC_E752X=m -CONFIG_EDAC_I82975X=m -CONFIG_EDAC_I3000=m -CONFIG_EDAC_I3200=m -CONFIG_EDAC_IE31200=m -CONFIG_EDAC_X38=m -CONFIG_EDAC_I5400=m -CONFIG_EDAC_I7CORE=m -CONFIG_EDAC_I5100=m -CONFIG_EDAC_I7300=m -CONFIG_EDAC_SBRIDGE=m -CONFIG_EDAC_SKX=m -CONFIG_EDAC_I10NM=m -CONFIG_EDAC_PND2=m -CONFIG_EDAC_IGEN6=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_88PM860X=m -CONFIG_RTC_DRV_88PM80X=m -CONFIG_RTC_DRV_ABB5ZES3=m -CONFIG_RTC_DRV_ABEOZ9=m -CONFIG_RTC_DRV_ABX80X=m -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_DS1374=m -CONFIG_RTC_DRV_DS1374_WDT=y -CONFIG_RTC_DRV_DS1672=m -CONFIG_RTC_DRV_LP8788=m -CONFIG_RTC_DRV_MAX6900=m -CONFIG_RTC_DRV_MAX8907=m -CONFIG_RTC_DRV_MAX8925=m -CONFIG_RTC_DRV_MAX8998=m -CONFIG_RTC_DRV_MAX8997=m -CONFIG_RTC_DRV_MAX31335=m -CONFIG_RTC_DRV_RS5C372=m -CONFIG_RTC_DRV_ISL1208=m -CONFIG_RTC_DRV_ISL12022=m -CONFIG_RTC_DRV_X1205=m -CONFIG_RTC_DRV_PCF8523=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_PCF8563=m -CONFIG_RTC_DRV_PCF8583=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_M41T80_WDT=y -CONFIG_RTC_DRV_BQ32K=m -CONFIG_RTC_DRV_PALMAS=m -CONFIG_RTC_DRV_TPS6586X=m -CONFIG_RTC_DRV_TPS6594=m -CONFIG_RTC_DRV_TPS65910=m -CONFIG_RTC_DRV_RC5T583=m -CONFIG_RTC_DRV_S35390A=m -CONFIG_RTC_DRV_FM3130=m -CONFIG_RTC_DRV_RX8010=m -CONFIG_RTC_DRV_RX8111=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RX8025=m -CONFIG_RTC_DRV_EM3027=m -CONFIG_RTC_DRV_RV3028=m -CONFIG_RTC_DRV_RV3032=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_SD2405AL=m -CONFIG_RTC_DRV_SD3078=m -CONFIG_RTC_DRV_M41T93=m -CONFIG_RTC_DRV_M41T94=m -CONFIG_RTC_DRV_DS1302=m -CONFIG_RTC_DRV_DS1305=m -CONFIG_RTC_DRV_DS1343=m -CONFIG_RTC_DRV_DS1347=m -CONFIG_RTC_DRV_DS1390=m -CONFIG_RTC_DRV_MAX6916=m -CONFIG_RTC_DRV_R9701=m -CONFIG_RTC_DRV_RX4581=m -CONFIG_RTC_DRV_RS5C348=m -CONFIG_RTC_DRV_MAX6902=m -CONFIG_RTC_DRV_PCF2123=m -CONFIG_RTC_DRV_MCP795=m -CONFIG_RTC_DRV_DS3232=m -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_RV3029C2=m -CONFIG_RTC_DRV_RX6110=m -CONFIG_RTC_DRV_DS1286=m -CONFIG_RTC_DRV_DS1511=m -CONFIG_RTC_DRV_DS1553=m -CONFIG_RTC_DRV_DS1685_FAMILY=m -CONFIG_RTC_DRV_DS1742=m -CONFIG_RTC_DRV_DS2404=m -CONFIG_RTC_DRV_DA9052=m -CONFIG_RTC_DRV_DA9055=m -CONFIG_RTC_DRV_DA9063=m -CONFIG_RTC_DRV_STK17TA8=m -CONFIG_RTC_DRV_M48T86=m -CONFIG_RTC_DRV_M48T35=m -CONFIG_RTC_DRV_M48T59=m -CONFIG_RTC_DRV_MSM6242=m -CONFIG_RTC_DRV_RP5C01=m -CONFIG_RTC_DRV_WM831X=m -CONFIG_RTC_DRV_WM8350=m -CONFIG_RTC_DRV_CROS_EC=m -CONFIG_RTC_DRV_FTRTC010=m -CONFIG_RTC_DRV_PCAP=m -CONFIG_RTC_DRV_MC13XXX=m -CONFIG_RTC_DRV_MT6397=m -CONFIG_RTC_DRV_GOLDFISH=m -CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_ACPI_FPDT=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_IPMI=m +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_MADT_WAKEUP=y +CONFIG_ACPI_MDIO=y +CONFIG_ACPI_MRRM=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NHLT=y +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PLATFORM_PROFILE=m +CONFIG_ACPI_PRMT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_QUICKSTART=m +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_SLEEP=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +CONFIG_ACPI_TABLE_LIB=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_THERMAL_LIB=y +CONFIG_ACPI_THERMAL_REL=m +CONFIG_ACPI_TOSHIBA=m +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_VIOT=y +CONFIG_ACPI_WATCHDOG=y +CONFIG_ACPI_WMI=m +# CONFIG_ACPI_WMI_LEGACY_DEVICE_NAMES is not set +CONFIG_ACQUIRE_WDT=m +# CONFIG_ACRN_GUEST is not set +CONFIG_AD2S1200=m +CONFIG_AD2S1210=m +CONFIG_AD2S90=m +CONFIG_AD3530R=m +CONFIG_AD3552R=m +CONFIG_AD3552R_HS=m +CONFIG_AD3552R_LIB=m +CONFIG_AD4000=m +CONFIG_AD4030=m +CONFIG_AD4080=m +CONFIG_AD4130=m +CONFIG_AD4170_4=m +CONFIG_AD4695=m +CONFIG_AD4851=m +CONFIG_AD5064=m +CONFIG_AD5110=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m +CONFIG_AD5272=m +CONFIG_AD5360=m +CONFIG_AD5380=m +CONFIG_AD5421=m +CONFIG_AD5446=m +CONFIG_AD5449=m +CONFIG_AD5504=m +CONFIG_AD5592R=m +CONFIG_AD5592R_BASE=m +CONFIG_AD5593R=m +CONFIG_AD5624R_SPI=m +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +CONFIG_AD5755=m +CONFIG_AD5758=m +CONFIG_AD5761=m +CONFIG_AD5764=m +CONFIG_AD5766=m +CONFIG_AD5770R=m +CONFIG_AD5791=m +CONFIG_AD5933=m +CONFIG_AD7091R=m +CONFIG_AD7091R5=m +CONFIG_AD7091R8=m +CONFIG_AD7124=m +CONFIG_AD7150=m +CONFIG_AD7173=m +CONFIG_AD7191=m +CONFIG_AD7192=m +CONFIG_AD7266=m +CONFIG_AD7280=m +CONFIG_AD7291=m +CONFIG_AD7292=m +CONFIG_AD7293=m +CONFIG_AD7298=m +CONFIG_AD7303=m +CONFIG_AD7380=m +CONFIG_AD7405=m +CONFIG_AD74115=m +CONFIG_AD74413R=m +CONFIG_AD7476=m +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7625=m +CONFIG_AD7746=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +CONFIG_AD7779=m +CONFIG_AD7780=m +CONFIG_AD7791=m +CONFIG_AD7793=m +CONFIG_AD7816=m +CONFIG_AD7887=m +CONFIG_AD7923=m +CONFIG_AD7944=m +CONFIG_AD7949=m +CONFIG_AD799X=m +CONFIG_AD8366=m +CONFIG_AD8460=m +CONFIG_AD8801=m +# CONFIG_AD9467 is not set +CONFIG_AD9523=m +CONFIG_AD9739A=m +CONFIG_AD9832=m +CONFIG_AD9834=m +CONFIG_ADA4250=m +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_ADC_BATTERY_HELPER=m +# CONFIG_ADE9000 is not set +CONFIG_ADF4350=m +CONFIG_ADF4371=m +CONFIG_ADF4377=m +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_ADIN1100_PHY=m +CONFIG_ADIN1110=m +CONFIG_ADIN_PHY=m +CONFIG_ADIS16080=m +CONFIG_ADIS16130=m +CONFIG_ADIS16136=m +CONFIG_ADIS16201=m +CONFIG_ADIS16203=m +CONFIG_ADIS16209=m +CONFIG_ADIS16260=m +CONFIG_ADIS16400=m +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +CONFIG_ADIS16480=m +CONFIG_ADIS16550=m +# CONFIG_ADI_I3C_MASTER is not set +CONFIG_ADJD_S311=m +CONFIG_ADM8211=m +# CONFIG_ADMFM2000 is not set +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +CONFIG_ADMV8818=m +CONFIG_ADRF6780=m +CONFIG_ADT7316=m +CONFIG_ADT7316_I2C=m +CONFIG_ADT7316_SPI=m +CONFIG_ADUX1020=m +CONFIG_ADVANTECH_EC_WDT=m +CONFIG_ADVANTECH_WDT=m +CONFIG_ADVISE_SYSCALLS=y +CONFIG_ADV_SWBUTTON=m +CONFIG_ADXL313=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL372=m +CONFIG_ADXL372_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL380=m +CONFIG_ADXL380_I2C=m +CONFIG_ADXL380_SPI=m +CONFIG_ADXRS290=m +CONFIG_ADXRS450=m +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_AFFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_DEBUG_CURSOR is not set +CONFIG_AFS_FS=m +CONFIG_AFS_FSCACHE=y +CONFIG_AF_KCM=m +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +CONFIG_AF_RXRPC_IPV6=y +CONFIG_AF_UNIX_OOB=y +CONFIG_AGP=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +CONFIG_AGP_SIS=m +CONFIG_AGP_VIA=y +CONFIG_AHCI_DWC=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_AIC7XXX_RESET_DELAY_MS=5000 +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_AIO=y +CONFIG_AIR_EN8811H_PHY=m +CONFIG_AIX_PARTITION=y +CONFIG_AK09911=m +CONFIG_AK8974=m +CONFIG_AK8975=m +CONFIG_AL3000A=m +CONFIG_AL3010=m +CONFIG_AL3320A=m +CONFIG_ALIBABA_ENI_VDPA=m +CONFIG_ALIENWARE_WMI=m +CONFIG_ALIENWARE_WMI_LEGACY=y +CONFIG_ALIENWARE_WMI_WMAX=y +CONFIG_ALIM1535_WDT=m +CONFIG_ALIM7101_WDT=m +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_ALS31300=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_ALTERA_MBOX=m +CONFIG_ALTERA_MSGDMA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_STAPL=m +CONFIG_ALTERA_TSE=m +CONFIG_ALX=m +CONFIG_AM2315=m +CONFIG_AMD8111_ETH=m +CONFIG_AMDTEE=m +CONFIG_AMD_3D_VCACHE=m +CONFIG_AMD_AE4DMA=m +CONFIG_AMD_ATL=m +CONFIG_AMD_ATL_PRM=y +CONFIG_AMD_HFI=y +CONFIG_AMD_HSMP=y +CONFIG_AMD_HSMP_ACPI=y +CONFIG_AMD_HSMP_PLAT=m +CONFIG_AMD_IOMMU=y +CONFIG_AMD_ISP_PLATFORM=m +# CONFIG_AMD_MEM_ENCRYPT is not set +CONFIG_AMD_MP2_STB=y +CONFIG_AMD_NB=y +CONFIG_AMD_NODE=y +CONFIG_AMD_NUMA=y +CONFIG_AMD_PHY=m +CONFIG_AMD_PMC=m +CONFIG_AMD_PMF=m +# CONFIG_AMD_PMF_DEBUG is not set +CONFIG_AMD_PTDMA=m +CONFIG_AMD_QDMA=m +CONFIG_AMD_SFH_HID=m +CONFIG_AMD_WBRF=y +CONFIG_AMD_XGBE=m +# CONFIG_AMD_XGBE_DCB is not set +CONFIG_AMD_XGBE_HAVE_ECC=y +CONFIG_AMIGA_PARTITION=y +CONFIG_AMILO_RFKILL=m +CONFIG_AMT=m +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANON_VMA_NAME=y +CONFIG_AOSONG_AGS02MA=m +CONFIG_APDS9160=m +CONFIG_APDS9300=m +CONFIG_APDS9306=m +CONFIG_APDS9802ALS=m +CONFIG_APDS9960=m +CONFIG_APERTURE_HELPERS=y +CONFIG_APPLE_GMUX=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_APPLE_PROPERTIES=y +CONFIG_APPLICOM=m +CONFIG_AQTION=m +CONFIG_AQUANTIA_PHY=m +CONFIG_AR5523=m +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_CONFIGURES_CPU_MITIGATIONS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_CC_PLATFORM=y +CONFIG_ARCH_HAS_COPY_MC=y +CONFIG_ARCH_HAS_CPU_ATTACK_VECTORS=y +CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y +CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y +CONFIG_ARCH_HAS_CPU_PASID=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_ARCH_HAS_DMA_OPS=y +CONFIG_ARCH_HAS_EARLY_DEBUG=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_EXECMEM_ROX=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y +CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y +CONFIG_ARCH_HAS_PKEYS=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y +CONFIG_ARCH_HAS_PTDUMP=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_UBSAN=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ARCH_HAVE_EXTRA_ELF_NOTES=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_PKEY_BITS=4 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_AUTOFDO_CLANG=y +CONFIG_ARCH_SUPPORTS_CFI=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_SUPPORTS_CRASH_HOTPLUG=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER=y +CONFIG_ARCH_SUPPORTS_KEXEC_JUMP=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_SIG_FORCE=y +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_PROPELLER_CLANG=y +CONFIG_ARCH_SUPPORTS_PT_RECLAIM=y +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_RT=y +CONFIG_ARCH_SUPPORTS_SCHED_CLUSTER=y +CONFIG_ARCH_SUPPORTS_SCHED_MC=y +CONFIG_ARCH_SUPPORTS_SCHED_SMT=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_USES_PG_ARCH_2=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_HUGETLB_VMEMMAP_PREINIT=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_IRQS_OFF_ACTIVATE_MM=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_ARCNET=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM20020=m +CONFIG_ARCNET_COM20020_CS=m +CONFIG_ARCNET_COM20020_PCI=m +CONFIG_ARCNET_COM90xx=m +CONFIG_ARCNET_COM90xxIO=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_RIM_I=m +CONFIG_AS21XXX_PHY=m +CONFIG_AS3935=m +CONFIG_AS73211=m +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASN1_ENCODER=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASUS_LAPTOP=m +CONFIG_ASUS_NB_WMI=m +CONFIG_ASUS_TF103C_DOCK=m +CONFIG_ASUS_WIRELESS=m +CONFIG_ASUS_WMI=m +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_KERNEL_PGTABLE_FREE=y +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_ASYNC_XOR=m +CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24690 +CONFIG_AS_WRUSS=y +CONFIG_AT76C50X_USB=m +CONFIG_AT803X_PHY=m +CONFIG_ATA=y +CONFIG_ATALK=m +CONFIG_ATARI_PARTITION=y +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=y +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=y +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_DEBUG is not set +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_LEDS=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_SDIO=m +# CONFIG_ATH10K_SPECTRAL is not set +CONFIG_ATH10K_TRACING=y +CONFIG_ATH10K_USB=m +CONFIG_ATH11K=m +# CONFIG_ATH11K_DEBUG is not set +# CONFIG_ATH11K_DEBUGFS is not set +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH12K=m +# CONFIG_ATH12K_COREDUMP is not set +# CONFIG_ATH12K_DEBUG is not set +# CONFIG_ATH12K_DEBUGFS is not set +# CONFIG_ATH12K_TRACING is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +CONFIG_ATH5K_PCI=y +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH6KL=m +# CONFIG_ATH6KL_DEBUG is not set +CONFIG_ATH6KL_SDIO=m +# CONFIG_ATH6KL_TRACING is not set +CONFIG_ATH6KL_USB=m +CONFIG_ATH9K=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_COMMON_DEBUG=y +# CONFIG_ATH9K_COMMON_SPECTRAL is not set +CONFIG_ATH9K_DEBUGFS=y +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_HTC_DEBUGFS=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_HWRNG=y +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_STATION_STATISTICS=y +CONFIG_ATH9K_WOW=y +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +CONFIG_ATL2=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATM=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_FORE200E_TX_RETRY=16 +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_LANAI=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +CONFIG_ATM_SOLOS=m +CONFIG_ATM_TCP=m +# CONFIG_ATOMIC64_SELFTEST is not set +CONFIG_ATP=m +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_ARCH=y +CONFIG_AUTOFS_FS=m +CONFIG_AUXDISPLAY=y +CONFIG_AUXILIARY_BUS=y +CONFIG_AW96103=m +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_AX88796B_PHY=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP20X_POWER=m +CONFIG_AXP288_ADC=m +CONFIG_AXP288_CHARGER=m +CONFIG_AXP288_FUEL_GAUGE=m +CONFIG_B43=m +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +CONFIG_B43LEGACY_HWRNG=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PIO=y +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_B43_BCMA=y +CONFIG_B43_BCMA_PIO=y +# CONFIG_B43_BUSES_BCMA is not set +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_SSB is not set +# CONFIG_B43_DEBUG is not set +CONFIG_B43_HWRNG=y +CONFIG_B43_LEDS=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PIO=y +# CONFIG_B43_SDIO is not set +CONFIG_B43_SSB=y +CONFIG_B44=m +CONFIG_B44_PCI=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B53=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_BACKLIGHT_88PM860X=m +CONFIG_BACKLIGHT_AAT2870=m +CONFIG_BACKLIGHT_ADP5520=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_APPLE=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_AS3711=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_DA903X=m +CONFIG_BACKLIGHT_DA9052=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_KTD253=m +# CONFIG_BACKLIGHT_KTD2801 is not set +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LM3509=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_LP8788=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_MAX8925=m +CONFIG_BACKLIGHT_MP3309C=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_PANDORA=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RAVE_SP=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_SAHARA=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_WM831X=m +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BALLOON_COMPACTION=y +CONFIG_BARCO_P50_GPIO=m +CONFIG_BAREUDP=m +# CONFIG_BASE_SMALL is not set +CONFIG_BASIC_MODVERSIONS=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV_MCAST=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_BATTERY_88PM860X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_BATTERY_BQ27XXX=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_BATTERY_BQ27XXX_HDQ=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_CHAGALL=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DA9030=m +CONFIG_BATTERY_DA9052=m +CONFIG_BATTERY_DA9150=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_BATTERY_GOLDFISH=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_BATTERY_RT5033=m +CONFIG_BATTERY_RX51=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_SURFACE=m +CONFIG_BATTERY_TWL4030_MADC=m +CONFIG_BATTERY_UG3105=m +CONFIG_BAYCOM_PAR=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_DEBUG is not set +CONFIG_BCH=m +CONFIG_BCH_CONST_M=14 +CONFIG_BCH_CONST_PARAMS=y +CONFIG_BCH_CONST_T=4 +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMGENET=m +CONFIG_BCM_KONA_USB2_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_BD79703=m +CONFIG_BE2ISCSI=m +CONFIG_BE2NET=m +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +# CONFIG_BEFS_DEBUG is not set +CONFIG_BEFS_FS=m +# CONFIG_BFQ_GROUP_IOSCHED is not set +CONFIG_BFS_FS=m +CONFIG_BH1745=m +CONFIG_BH1750=m +CONFIG_BH1780=m +# CONFIG_BHYVE_GUEST is not set +# CONFIG_BIG_KEYS is not set +CONFIG_BINARY_PRINTF=y +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +CONFIG_BLK_CGROUP=y +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +# CONFIG_BLK_CGROUP_IOLATENCY is not set +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_DM=y +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_DEV_FD_RAWCMD is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_DEV_ZONED_LOOP is not set +CONFIG_BLK_ICQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BLK_MQ_STACKING=y +CONFIG_BLK_PM=y +CONFIG_BLK_RQ_ALLOC_TIME=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMC150_MAGN=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_BMG160=m +CONFIG_BMG160_I2C=m +CONFIG_BMG160_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_I2C=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BMI270=m +CONFIG_BMI270_I2C=m +CONFIG_BMI270_SPI=m +CONFIG_BMI323=m +CONFIG_BMI323_I2C=m +CONFIG_BMI323_SPI=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_BNA=m +CONFIG_BNGE=y +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT=m +# CONFIG_BNXT_DCB is not set +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_HWMON=y +CONFIG_BNXT_SRIOV=y +CONFIG_BOARD_TPCI200=m +CONFIG_BONDING=m +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +# CONFIG_BOOTTIME_TRACING is not set +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BOOT_VESA_SUPPORT=y +CONFIG_BOSCH_BNO055=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BPF=y +CONFIG_BPF_EVENTS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPF_LSM is not set +# CONFIG_BPF_PRELOAD is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BPQETHER=m +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMDBG is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMSMAC=m +CONFIG_BRCMSMAC_LEDS=y +CONFIG_BRCMUTIL=m +CONFIG_BRCM_TRACING=y +CONFIG_BRIDGE=m +CONFIG_BRIDGE_CFM=y +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCAST_TLB_FLUSH=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BT=m +CONFIG_BTREE=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_EXPERIMENTAL is not set +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTT=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_AOSPEXT=y +CONFIG_BT_ATH3K=m +CONFIG_BT_BCM=m +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_BREDR=y +CONFIG_BT_DEBUGFS=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIBTUSB=m +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_AML=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIVHCI=m +CONFIG_BT_HIDP=m +CONFIG_BT_INTEL=m +CONFIG_BT_INTEL_PCIE=m +CONFIG_BT_LE=y +# CONFIG_BT_LEDS is not set +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_MSFTEXT=y +CONFIG_BT_MTK=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_NXPUART=m +CONFIG_BT_QCA=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_RTL=m +# CONFIG_BT_SELFTEST is not set +CONFIG_BT_VIRTIO=m +CONFIG_BUFFER_HEAD=y +CONFIG_BUG=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +CONFIG_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_BUILD_SALT="" +CONFIG_C2PORT=m +CONFIG_C2PORT_DURAMAR_2150=m +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +CONFIG_CACHESTAT_SYSCALL=y +CONFIG_CADENCE_WATCHDOG=m +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_DRIVERS=y +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_TTY=m +CONFIG_CAIF_USB=m +CONFIG_CAIF_VIRTIO=m +CONFIG_CALL_PADDING=y +CONFIG_CALL_THUNKS=y +# CONFIG_CALL_THUNKS_DEBUG is not set +CONFIG_CAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_CAN327=m +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m +CONFIG_CAN_CTUCANFD=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_C_CAN_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_F81601=m +CONFIG_CAN_F81604=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_GW=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_J1939=m +CONFIG_CAN_JANZ_ICAN3=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_RAW=m +CONFIG_CAN_RX_OFFLOAD=y +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m +CONFIG_CAN_UCAN=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CARDBUS=y +CONFIG_CARL9170=m +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_HWRNG=y +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170_WPC=y +# CONFIG_CARMINE_DRAM_CUSTOM is not set +CONFIG_CASSINI=m +CONFIG_CAVIUM_PTP=m +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y +CONFIG_CC10001_ADC=m +CONFIG_CCS811=m +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_ASSUME=y +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_ENTRY_PADDING=y +CONFIG_CC_HAS_IBT=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_KASAN_SW_TAGS=y +CONFIG_CC_HAS_MARCH_NATIVE=y +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_CC_HAS_NAMED_AS=y +CONFIG_CC_HAS_NAMED_AS_FIXED_SANITIZERS=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_CC_HAS_RETURN_THUNK=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_SLS=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_IS_GCC=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_VERSION_TEXT="gcc (Debian 15.3.0-1) 15.3.0" +CONFIG_CDNS_I3C_MASTER=m +CONFIG_CDROM=y +CONFIG_CEC_CH7322=m +CONFIG_CEC_CORE=m +CONFIG_CEC_CROS_EC=m +CONFIG_CEC_GPIO=m +CONFIG_CEC_NOTIFIER=y +CONFIG_CEC_NXP_TDA9950=m +CONFIG_CEC_PIN=y +# CONFIG_CEC_PIN_ERROR_INJ is not set +CONFIG_CEC_SECO=m +CONFIG_CEC_SECO_RC=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_CFAG12864B=m +CONFIG_CFAG12864B_RATE=20 +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_CGBC_WDT is not set +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_DMEM=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CHARGER_88PM860X=m +CONFIG_CHARGER_ADP5061=m +CONFIG_CHARGER_AXP20X=m +CONFIG_CHARGER_BD99954=m +CONFIG_CHARGER_BQ2415X=m +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_CROS_CONTROL=m +CONFIG_CHARGER_CROS_PCHG=m +CONFIG_CHARGER_CROS_USBPD=m +CONFIG_CHARGER_DA9150=m +CONFIG_CHARGER_GPIO=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_LP8788=m +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_MANAGER=y +CONFIG_CHARGER_MAX14577=m +CONFIG_CHARGER_MAX77693=m +CONFIG_CHARGER_MAX77705=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_MAX8971=m +CONFIG_CHARGER_MAX8997=m +CONFIG_CHARGER_MAX8998=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6360=m +CONFIG_CHARGER_MT6370=m +CONFIG_CHARGER_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +CONFIG_CHARGER_SBS=m +CONFIG_CHARGER_SMB347=m +CONFIG_CHARGER_SURFACE=m +CONFIG_CHARGER_TPS65090=m +CONFIG_CHARGER_TWL4030=m +CONFIG_CHARGER_TWL6030=m +CONFIG_CHARGER_WILCO=m +CONFIG_CHARLCD=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CHELSIO_INLINE_CRYPTO=y +# CONFIG_CHELSIO_IPSEC_INLINE is not set +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHROMEOS_ACPI=m +CONFIG_CHROMEOS_LAPTOP=m +CONFIG_CHROMEOS_PRIVACY_SCREEN=m +CONFIG_CHROMEOS_PSTORE=m +CONFIG_CHROMEOS_TBMC=m +CONFIG_CHROME_PLATFORMS=y +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_ST=m +CONFIG_CICADA_PHY=m +CONFIG_CIFS=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_COMPRESSION is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CLANG_VERSION=0 +CONFIG_CLKBLD_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_CLK_TWL=m +CONFIG_CLK_TWL6040=m +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLOSURES=y +CONFIG_CLS_U32_MARK=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLZ_TAB=y +CONFIG_CM32181=m +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +CONFIG_CM36651=m +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=0 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMA_SYSFS=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_CNIC=m +CONFIG_CODA_FS=m +CONFIG_CODE_TAGGING=y +CONFIG_COMEDI=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_PCI=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_ADDI_APCI_1032=m +CONFIG_COMEDI_ADDI_APCI_1500=m +CONFIG_COMEDI_ADDI_APCI_1516=m +CONFIG_COMEDI_ADDI_APCI_1564=m +CONFIG_COMEDI_ADDI_APCI_16XX=m +CONFIG_COMEDI_ADDI_APCI_2032=m +CONFIG_COMEDI_ADDI_APCI_2200=m +CONFIG_COMEDI_ADDI_APCI_3120=m +CONFIG_COMEDI_ADDI_APCI_3501=m +CONFIG_COMEDI_ADDI_APCI_3XXX=m +CONFIG_COMEDI_ADDI_WATCHDOG=m +CONFIG_COMEDI_ADL_PCI6208=m +# CONFIG_COMEDI_ADL_PCI7250 is not set +CONFIG_COMEDI_ADL_PCI7X3X=m +CONFIG_COMEDI_ADL_PCI8164=m +CONFIG_COMEDI_ADL_PCI9111=m +CONFIG_COMEDI_ADL_PCI9118=m +CONFIG_COMEDI_ADV_PCI1710=m +CONFIG_COMEDI_ADV_PCI1720=m +CONFIG_COMEDI_ADV_PCI1723=m +CONFIG_COMEDI_ADV_PCI1724=m +CONFIG_COMEDI_ADV_PCI1760=m +CONFIG_COMEDI_ADV_PCI_DIO=m +CONFIG_COMEDI_AMPLC_DIO200=m +CONFIG_COMEDI_AMPLC_DIO200_PCI=m +CONFIG_COMEDI_AMPLC_PC236=m +CONFIG_COMEDI_AMPLC_PC236_PCI=m +CONFIG_COMEDI_AMPLC_PC263_PCI=m +CONFIG_COMEDI_AMPLC_PCI224=m +CONFIG_COMEDI_AMPLC_PCI230=m +CONFIG_COMEDI_BOND=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_CB_PCIDAS=m +CONFIG_COMEDI_CB_PCIDAS64=m +CONFIG_COMEDI_CB_PCIDDA=m +CONFIG_COMEDI_CB_PCIMDAS=m +CONFIG_COMEDI_CB_PCIMDDA=m +CONFIG_COMEDI_CONTEC_PCI_DIO=m +CONFIG_COMEDI_DAQBOARD2000=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_DAS08_PCI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DT3000=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_DYNA_PCI10XX=m +CONFIG_COMEDI_GSC_HPDI=m +CONFIG_COMEDI_ICP_MULTI=m +CONFIG_COMEDI_JR3_PCI=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_KE_COUNTER=m +CONFIG_COMEDI_ME4000=m +CONFIG_COMEDI_ME_DAQ=m +CONFIG_COMEDI_MF6X4=m +CONFIG_COMEDI_MISC_DRIVERS=y +CONFIG_COMEDI_MITE=m +CONFIG_COMEDI_NI_6527=m +CONFIG_COMEDI_NI_65XX=m +CONFIG_COMEDI_NI_660X=m +CONFIG_COMEDI_NI_670X=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_LABPC_PCI=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_NI_PCIDIO=m +CONFIG_COMEDI_NI_PCIMIO=m +CONFIG_COMEDI_NI_ROUTING=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_TIOCMD=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_PARPORT=m +CONFIG_COMEDI_PCI_DRIVERS=m +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_RTD520=m +CONFIG_COMEDI_S626=m +CONFIG_COMEDI_TEST=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_PALMAS=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_SI5341=m +CONFIG_COMMON_CLK_SI5351=m +CONFIG_COMMON_CLK_SI544=m +CONFIG_COMMON_CLK_TPS68470=m +CONFIG_COMMON_CLK_WM831X=m +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAL_LAPTOP=m +CONFIG_COMPAT=y +CONFIG_COMPAT_32=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_COMPAT_BRK is not set +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_COMPAT_OLD_SIGACTION=y +# CONFIG_COMPAT_VDSO is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=m +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_CONSOLE_POLL=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CORDIC=m +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CORTINA_PHY=m +CONFIG_COUNTER=m +# CONFIG_CPA_DEBUG is not set +CONFIG_CPUFREQ_ARCH_CUR_FREQ=y +CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_HALTPOLL=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set +# CONFIG_CRASH_DM_CRYPT is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_HOTPLUG=y +CONFIG_CRASH_MAX_MEMORY_RANGES=8192 +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_CRC32_ARCH=y +CONFIG_CRC64=y +CONFIG_CRC64_ARCH=y +CONFIG_CRC7=m +CONFIG_CRC8=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC_OPTIMIZATIONS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_T10DIF_ARCH=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CROS_EC=m +CONFIG_CROS_EC_CHARDEV=m +CONFIG_CROS_EC_DEBUGFS=m +CONFIG_CROS_EC_I2C=m +CONFIG_CROS_EC_ISHTP=m +CONFIG_CROS_EC_LIGHTBAR=m +CONFIG_CROS_EC_LPC=m +CONFIG_CROS_EC_MKBP_PROXIMITY=m +CONFIG_CROS_EC_PROTO=m +CONFIG_CROS_EC_SENSORHUB=m +CONFIG_CROS_EC_SPI=m +CONFIG_CROS_EC_SYSFS=m +CONFIG_CROS_EC_TYPEC=m +CONFIG_CROS_EC_TYPEC_ALTMODES=y +CONFIG_CROS_EC_UART=m +CONFIG_CROS_EC_UCSI=m +# CONFIG_CROS_EC_WATCHDOG is not set +CONFIG_CROS_HPS_I2C=m +CONFIG_CROS_KBD_LED_BACKLIGHT=m +CONFIG_CROS_TYPEC_SWITCH=m +CONFIG_CROS_USBPD_LOGGER=m +CONFIG_CROS_USBPD_NOTIFY=m +CONFIG_CRYPTO=y +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_NI_INTEL=m +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_ARIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_BENCHMARK is not set +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_BLOWFISH_X86_64=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_CAMELLIA_X86_64=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST5_AVX_X86_64=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST6_AVX_X86_64=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CHACHA20=y +CONFIG_CRYPTO_CHACHA20POLY1305=y +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DES3_EDE_X86_64=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CRYPTO_DEV_CCP_CRYPTO=m +CONFIG_CRYPTO_DEV_CCP_DD=m +# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_IAA_CRYPTO=m +# CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS is not set +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_PADLOCK=y +CONFIG_CRYPTO_DEV_PADLOCK_AES=m +CONFIG_CRYPTO_DEV_PADLOCK_SHA=m +CONFIG_CRYPTO_DEV_QAT=m +CONFIG_CRYPTO_DEV_QAT_420XX=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_6XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +# CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION is not set +CONFIG_CRYPTO_DEV_SAFEXCEL=m +CONFIG_CRYPTO_DEV_SP_CCP=y +CONFIG_CRYPTO_DEV_SP_PSP=y +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_ENGINE=m +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_HKDF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KDF800108_CTR=y +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KRB5=m +CONFIG_CRYPTO_KRB5ENC=m +# CONFIG_CRYPTO_KRB5_SELFTESTS is not set +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_AESCFB=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_ARCH=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA_ARCH=y +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_ARCH=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_MD5=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_ARCH=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA1_ARCH=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SHA256_ARCH=y +CONFIG_CRYPTO_LIB_SHA512=y +CONFIG_CRYPTO_LIB_SHA512_ARCH=y +CONFIG_CRYPTO_LIB_SM3=m +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NHPOLY1305=m +CONFIG_CRYPTO_NHPOLY1305_AVX2=m +CONFIG_CRYPTO_NHPOLY1305_SSE2=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SELFTESTS is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX_X86_64=m +CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_SM3_AVX_X86_64=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_TWOFISH_X86_64=m +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=m +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_CXD2880_SPI_DRV=m +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=m +# CONFIG_CXL_FEATURES is not set +CONFIG_CXL_MCE=y +CONFIG_CXL_MEM=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=m +CONFIG_CXL_PMEM=m +CONFIG_CXL_PMU=m +CONFIG_CXL_PORT=m +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_SUSPEND=y +CONFIG_CX_ECAT=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_D3323AA=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DA9052_WATCHDOG=m +CONFIG_DA9055_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=m +CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9150_GPADC=m +CONFIG_DAMON=y +CONFIG_DAMON_LRU_SORT=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_STAT=y +CONFIG_DAMON_STAT_ENABLED_DEFAULT=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DASHARO_ACPI=m +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y +CONFIG_DCA=m +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DCB=y +CONFIG_DCDBAS=m +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NET_SMALL_RTNL is not set +# CONFIG_DEBUG_NMI_SELFTEST is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_TLBFLUSH is not set +# CONFIG_DEBUG_VFS is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DEFXX=m +CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m +CONFIG_DELL_RBTN=m +CONFIG_DELL_RBU=m +CONFIG_DELL_SMBIOS=m +CONFIG_DELL_SMBIOS_SMM=y +CONFIG_DELL_SMBIOS_WMI=y +CONFIG_DELL_SMO8800=m +CONFIG_DELL_UART_BACKLIGHT=m +CONFIG_DELL_WMI=m +CONFIG_DELL_WMI_AIO=m +CONFIG_DELL_WMI_DDV=m +CONFIG_DELL_WMI_DESCRIPTOR=m +CONFIG_DELL_WMI_LED=m +CONFIG_DELL_WMI_PRIVACY=y +CONFIG_DELL_WMI_SYSMAN=m +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DETECT_HUNG_TASK_BLOCKER is not set +CONFIG_DEVFREQ_GOV_PASSIVE=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_DEVICE_MIGRATION=y +# CONFIG_DEVICE_PRIVATE is not set +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_DEV_COREDUMP=y +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +CONFIG_DEV_DAX_HMEM_DEVICES=y +CONFIG_DEV_DAX_KMEM=m +CONFIG_DEV_DAX_PMEM=m +CONFIG_DEV_SYNC_PROBE=m +CONFIG_DHT11=m +# CONFIG_DIBS is not set +CONFIG_DIMLIB=y +CONFIG_DL2K=m +CONFIG_DLHL60D=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set +CONFIG_DLN2_ADC=m +CONFIG_DM9051=m +CONFIG_DM9102=m +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMADEVICES=y -CONFIG_ALTERA_MSGDMA=m -CONFIG_INTEL_IDMA64=m -CONFIG_INTEL_IDXD=m -CONFIG_INTEL_IDXD_SVM=y -CONFIG_INTEL_IDXD_PERFMON=y -CONFIG_INTEL_IOATDMA=m -CONFIG_PLX_DMA=m -CONFIG_XILINX_DMA=m -CONFIG_AMD_AE4DMA=m -CONFIG_AMD_PTDMA=m -CONFIG_AMD_QDMA=m -CONFIG_QCOM_HIDMA_MGMT=m -CONFIG_QCOM_HIDMA=m +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMAPOOL_TEST is not set +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_DMAR_TABLE=y +# CONFIG_DMATEST is not set +CONFIG_DMA_ACPI=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +# CONFIG_DMA_FENCE_TRACE is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_DMA_NEED_SYNC=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMI=y +CONFIG_DMIID=y +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +CONFIG_DMI_SYSFS=m +CONFIG_DM_AUDIT=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_BUFIO=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_CLONE=m +CONFIG_DM_CRYPT=m +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +# CONFIG_DM_EBS is not set +CONFIG_DM_ERA=m +CONFIG_DM_FLAKEY=m +# CONFIG_DM_INIT is not set +CONFIG_DM_INTEGRITY=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_PCACHE is not set +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_SWITCH=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_VDO=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_FEC is not set +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ZERO=m +CONFIG_DM_ZONED=m +CONFIG_DNET=m +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=y +CONFIG_DP83822_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83TD510_PHY=m +CONFIG_DP83TG720_PHY=m +CONFIG_DPLL=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DPOT_DAC=m +CONFIG_DPS310=m +CONFIG_DPTF_PCH_FIVR=m +CONFIG_DPTF_POWER=m +CONFIG_DQL=y +CONFIG_DRAGONRISE_FF=y +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRM=m +CONFIG_DRM_ACCEL=y +CONFIG_DRM_ACCEL_AMDXDNA=m +CONFIG_DRM_ACCEL_HABANALABS=m +CONFIG_DRM_ACCEL_IVPU=m +# CONFIG_DRM_ACCEL_IVPU_DEBUG is not set +CONFIG_DRM_ACCEL_QAIC=m +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ACP is not set +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_FP=y +# CONFIG_DRM_AMD_DC_SI is not set +CONFIG_DRM_AMD_ISP=y +CONFIG_DRM_AMD_SECURE_DISPLAY=y +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_APPLETBDRM=m +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BUDDY=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_CLIENT=y +CONFIG_DRM_CLIENT_DEFAULT="fbdev" +CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y +# CONFIG_DRM_CLIENT_DEFAULT_LOG is not set +CONFIG_DRM_CLIENT_LIB=m +CONFIG_DRM_CLIENT_LOG=y +CONFIG_DRM_CLIENT_SELECTION=m +CONFIG_DRM_CLIENT_SETUP=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_DISPLAY_DP_AUX_CEC=y +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_DP_TUNNEL=y +CONFIG_DRM_DISPLAY_DSC_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DRAW=y +CONFIG_DRM_EFIDRM=m +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_EXEC=m +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_GMA500=m +CONFIG_DRM_GPUSVM=m +CONFIG_DRM_GPUVM=m +CONFIG_DRM_GUD=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I915=m +CONFIG_DRM_I915_CAPTURE_ERROR=y +CONFIG_DRM_I915_COMPRESS_ERROR=y +# CONFIG_DRM_I915_DEBUG is not set +# CONFIG_DRM_I915_DEBUG_GUC is not set +# CONFIG_DRM_I915_DEBUG_MMIO is not set +# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set +# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set +# CONFIG_DRM_I915_DEBUG_WAKEREF is not set +CONFIG_DRM_I915_DP_TUNNEL=y +CONFIG_DRM_I915_FENCE_TIMEOUT=10000 +CONFIG_DRM_I915_FORCE_PROBE="" +CONFIG_DRM_I915_GVT=y +CONFIG_DRM_I915_GVT_KVMGT=m +CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 +# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set +CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 +CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 +CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set +CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 +# CONFIG_DRM_I915_SELFTEST is not set +CONFIG_DRM_I915_STOP_TIMEOUT=100 +# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set +# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set +CONFIG_DRM_I915_TIMESLICE_DURATION=1 +CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 +CONFIG_DRM_I915_USERPTR=y +# CONFIG_DRM_I915_WERROR is not set +CONFIG_DRM_KMS_HELPER=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_MGAG200 is not set +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_CH7006=m +CONFIG_DRM_NOUVEAU_SIL164=m +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_AUO_A030JTN01=m +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS=m +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANIC=y +CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000 +# CONFIG_DRM_PANIC_DEBUG is not set +CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xffffff +CONFIG_DRM_PANIC_SCREEN="user" +# CONFIG_DRM_PIXPAPER is not set +CONFIG_DRM_PRIVACY_SCREEN=y +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +# CONFIG_DRM_RADEON_USERPTR is not set +CONFIG_DRM_SCHED=m +# CONFIG_DRM_SIMPLEDRM is not set +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +CONFIG_DRM_ST7571_I2C=m +CONFIG_DRM_ST7586=m +CONFIG_DRM_ST7735R=m +CONFIG_DRM_SUBALLOC_HELPER=m +CONFIG_DRM_SYSFB_HELPER=m +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VBOXVIDEO=m +CONFIG_DRM_VESADRM=m +CONFIG_DRM_VGEM=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +# CONFIG_DRM_VKMS is not set +CONFIG_DRM_VMWGFX=m +# CONFIG_DRM_VMWGFX_MKSSTATS is not set +CONFIG_DRM_VRAM_HELPER=m +# CONFIG_DRM_WERROR is not set +CONFIG_DRM_XE=m +CONFIG_DRM_XEN=y +CONFIG_DRM_XEN_FRONTEND=m +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_MEMIRQ is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_DP_TUNNEL=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +CONFIG_DS1682=m +CONFIG_DS1803=m +CONFIG_DS4424=m +CONFIG_DST_CACHE=y +CONFIG_DUMMY=m +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_DUMMY_IRQ=m +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_AS102=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_BT8XX=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_CXD2099=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_CXD2880=m +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DM1105=m +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_DRXK=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_DUMMY_FE=m +CONFIG_DVB_DYNAMIC_MINORS=y +CONFIG_DVB_EC100=m +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_L64781=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MB86A20S=m +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_MN88443X=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_MT312=m +CONFIG_DVB_MT352=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_MXL692=m +CONFIG_DVB_NET=y +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_DVB_PLL=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_S921=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_SP2=m +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0297=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_TC90522=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TS2020=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_ULE_DEBUG is not set +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_VES1820=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_ZL10353=m +CONFIG_DWC_PCIE_PMU=m +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL=m CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC_PCI=m CONFIG_DW_EDMA=m CONFIG_DW_EDMA_PCIE=m -CONFIG_SF_PDMA=m -CONFIG_INTEL_LDMA=y -CONFIG_ASYNC_TX_DMA=y -CONFIG_UIO_CIF=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_AEC=m -CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_UIO_NETX=m -CONFIG_UIO_MF624=m -CONFIG_UIO_DFL=m -CONFIG_VFIO=m -CONFIG_VFIO_NOIOMMU=y -CONFIG_VFIO_PCI=m -CONFIG_VFIO_PCI_VGA=y -CONFIG_MLX5_VFIO_PCI=m -CONFIG_PDS_VFIO_PCI=m -CONFIG_VIRTIO_VFIO_PCI=m -CONFIG_QAT_VFIO_PCI=m -CONFIG_VIRT_DRIVERS=y -CONFIG_VBOXGUEST=m -CONFIG_NITRO_ENCLAVES=m -CONFIG_EFI_SECRET=m -CONFIG_TDX_GUEST_DRIVER=m -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_VDPA=m -CONFIG_VIRTIO_PMEM=m -CONFIG_VIRTIO_BALLOON=m -CONFIG_VIRTIO_MEM=m -CONFIG_VIRTIO_INPUT=m -CONFIG_VIRTIO_MMIO=m -CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y -CONFIG_VIRTIO_DEBUG=y -CONFIG_VIRTIO_RTC=m -CONFIG_VDPA=m -CONFIG_VDPA_USER=m -CONFIG_IFCVF=m -CONFIG_MLX5_VDPA_NET=m -CONFIG_VP_VDPA=m -CONFIG_ALIBABA_ENI_VDPA=m -CONFIG_SNET_VDPA=m -CONFIG_PDS_VDPA=m -CONFIG_OCTEONEP_VDPA=m -CONFIG_VHOST_NET=m -CONFIG_VHOST_SCSI=m -CONFIG_VHOST_VSOCK=m -CONFIG_VHOST_VDPA=m -CONFIG_XEN_DEV_EVTCHN=m -CONFIG_XENFS=m -CONFIG_XEN_PVCALLS_FRONTEND=m -CONFIG_XEN_SCSI_BACKEND=m -CONFIG_XEN_PRIVCMD_EVENTFD=y -CONFIG_XEN_ACPI_PROCESSOR=y -CONFIG_XEN_MCE_LOG=y -CONFIG_XEN_VIRTIO=y -CONFIG_COMEDI=m -CONFIG_COMEDI_MISC_DRIVERS=y -CONFIG_COMEDI_BOND=m -CONFIG_COMEDI_TEST=m -CONFIG_COMEDI_PARPORT=m -CONFIG_COMEDI_PCI_DRIVERS=m -CONFIG_COMEDI_8255_PCI=m -CONFIG_COMEDI_ADDI_APCI_1032=m -CONFIG_COMEDI_ADDI_APCI_1500=m -CONFIG_COMEDI_ADDI_APCI_1516=m -CONFIG_COMEDI_ADDI_APCI_1564=m -CONFIG_COMEDI_ADDI_APCI_16XX=m -CONFIG_COMEDI_ADDI_APCI_2032=m -CONFIG_COMEDI_ADDI_APCI_2200=m -CONFIG_COMEDI_ADDI_APCI_3120=m -CONFIG_COMEDI_ADDI_APCI_3501=m -CONFIG_COMEDI_ADDI_APCI_3XXX=m -CONFIG_COMEDI_ADL_PCI6208=m -CONFIG_COMEDI_ADL_PCI7X3X=m -CONFIG_COMEDI_ADL_PCI8164=m -CONFIG_COMEDI_ADL_PCI9111=m -CONFIG_COMEDI_ADL_PCI9118=m -CONFIG_COMEDI_ADV_PCI1710=m -CONFIG_COMEDI_ADV_PCI1720=m -CONFIG_COMEDI_ADV_PCI1723=m -CONFIG_COMEDI_ADV_PCI1724=m -CONFIG_COMEDI_ADV_PCI1760=m -CONFIG_COMEDI_ADV_PCI_DIO=m -CONFIG_COMEDI_AMPLC_DIO200_PCI=m -CONFIG_COMEDI_AMPLC_PC236_PCI=m -CONFIG_COMEDI_AMPLC_PC263_PCI=m -CONFIG_COMEDI_AMPLC_PCI224=m -CONFIG_COMEDI_AMPLC_PCI230=m -CONFIG_COMEDI_CONTEC_PCI_DIO=m -CONFIG_COMEDI_DAS08_PCI=m -CONFIG_COMEDI_DT3000=m -CONFIG_COMEDI_DYNA_PCI10XX=m -CONFIG_COMEDI_GSC_HPDI=m -CONFIG_COMEDI_MF6X4=m -CONFIG_COMEDI_ICP_MULTI=m -CONFIG_COMEDI_DAQBOARD2000=m -CONFIG_COMEDI_JR3_PCI=m -CONFIG_COMEDI_KE_COUNTER=m -CONFIG_COMEDI_CB_PCIDAS64=m -CONFIG_COMEDI_CB_PCIDAS=m -CONFIG_COMEDI_CB_PCIDDA=m -CONFIG_COMEDI_CB_PCIMDAS=m -CONFIG_COMEDI_CB_PCIMDDA=m -CONFIG_COMEDI_ME4000=m -CONFIG_COMEDI_ME_DAQ=m -CONFIG_COMEDI_NI_6527=m -CONFIG_COMEDI_NI_65XX=m -CONFIG_COMEDI_NI_660X=m -CONFIG_COMEDI_NI_670X=m -CONFIG_COMEDI_NI_LABPC_PCI=m -CONFIG_COMEDI_NI_PCIDIO=m -CONFIG_COMEDI_NI_PCIMIO=m -CONFIG_COMEDI_RTD520=m -CONFIG_COMEDI_S626=m -CONFIG_COMEDI_PCMCIA_DRIVERS=m -CONFIG_COMEDI_CB_DAS16_CS=m -CONFIG_COMEDI_DAS08_CS=m -CONFIG_COMEDI_NI_DAQ_700_CS=m -CONFIG_COMEDI_NI_DAQ_DIO24_CS=m -CONFIG_COMEDI_NI_LABPC_CS=m -CONFIG_COMEDI_NI_MIO_CS=m -CONFIG_COMEDI_QUATECH_DAQP_CS=m -CONFIG_COMEDI_USB_DRIVERS=m -CONFIG_COMEDI_DT9812=m -CONFIG_COMEDI_NI_USB6501=m -CONFIG_COMEDI_USBDUX=m -CONFIG_COMEDI_USBDUXFAST=m -CONFIG_COMEDI_USBDUXSIGMA=m -CONFIG_COMEDI_VMK80XX=m -CONFIG_COMEDI_8255_SA=m -CONFIG_STAGING=y -CONFIG_RTL8723BS=m -CONFIG_ADIS16203=m -CONFIG_AD7816=m -CONFIG_ADT7316=m -CONFIG_ADT7316_I2C=m -CONFIG_AD9832=m -CONFIG_AD9834=m -CONFIG_AD5933=m +CONFIG_DW_I3C_MASTER=m +CONFIG_DW_WATCHDOG=m +CONFIG_DW_XDATA_PCIE=m +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_DYNAMIC_PHYSICAL_MASK=y +CONFIG_DYNAMIC_SIGFRAME=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_E1000E_HWTS=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_DBGP=y +CONFIG_EARLY_PRINTK_USB=y +# CONFIG_EARLY_PRINTK_USB_XDBC is not set +CONFIG_EBC_C384_WDT=m +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_EDAC=y +CONFIG_EDAC_AMD64=m +CONFIG_EDAC_ATOMIC_SCRUB=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_DECODE_MCE=m +CONFIG_EDAC_E752X=m +CONFIG_EDAC_ECS=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_I10NM=m +CONFIG_EDAC_I3000=m +CONFIG_EDAC_I3200=m +CONFIG_EDAC_I5100=m +CONFIG_EDAC_I5400=m +CONFIG_EDAC_I7300=m +CONFIG_EDAC_I7CORE=m +CONFIG_EDAC_I82975X=m +CONFIG_EDAC_IE31200=m +CONFIG_EDAC_IGEN6=m +# CONFIG_EDAC_LEGACY_SYSFS is not set +CONFIG_EDAC_MEM_REPAIR=y +CONFIG_EDAC_PND2=m +CONFIG_EDAC_SBRIDGE=m +CONFIG_EDAC_SCRUB=y +CONFIG_EDAC_SKX=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC_X38=m +CONFIG_EDD=y +CONFIG_EDD_OFF=y +CONFIG_EEEPC_LAPTOP=m +CONFIG_EEEPC_WMI=m +CONFIG_EEPROM_93CX6=m +CONFIG_EEPROM_93XX46=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_EEPROM_EE1004=m +CONFIG_EEPROM_IDT_89HPESX=m +# CONFIG_EEPROM_M24LR is not set +CONFIG_EEPROM_MAX6875=m +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +CONFIG_EFI_BOOTLOADER_CONTROL=m +# CONFIG_EFI_CAPSULE_LOADER is not set +CONFIG_EFI_COCO_SECRET=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +CONFIG_EFI_DEV_PATH_PARSER=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_DXE_MEM_ATTRIBUTES=y +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_HANDOVER_PROTOCOL=y +CONFIG_EFI_MIXED=y +CONFIG_EFI_PARTITION=y +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_EFI_RCI2_TABLE is not set +CONFIG_EFI_RUNTIME_MAP=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_SBAT_FILE="" +CONFIG_EFI_SECRET=m +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_VARS_PSTORE=m +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFS_FS=m +CONFIG_ELFCORE=y +CONFIG_ELF_CORE=y +CONFIG_ENA_ETHERNET=m +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +CONFIG_ENCX24J600=m +# CONFIG_ENERGY_MODEL is not set +CONFIG_ENIC=m +CONFIG_ENS160=m +CONFIG_ENS160_I2C=m +CONFIG_ENS160_SPI=m +CONFIG_ENS210=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_EPIC100=m +CONFIG_EPOLL=y +CONFIG_EPROBE_EVENTS=y +CONFIG_EQUALIZER=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_BACKED_BY_FILE=y +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_ONDEMAND is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +# CONFIG_EROFS_FS_ZIP is not set +CONFIG_ET131X=m +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_EUROTECH_WDT=m +CONFIG_EVENTFD=y +CONFIG_EVENT_TRACING=y +CONFIG_EVM=y +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +CONFIG_EVM_EXTRA_SMACK_XATTRS=y +# CONFIG_EVM_LOAD_X509 is not set +CONFIG_EXAR_WDT=m +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=m +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXTCON=y +CONFIG_EXTCON_ADC_JACK=m +CONFIG_EXTCON_AXP288=m +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_INTEL_CHT_WC=m +CONFIG_EXTCON_INTEL_INT3496=m +CONFIG_EXTCON_INTEL_MRFLD=m +CONFIG_EXTCON_LC824206XA=m +# CONFIG_EXTCON_MAX14526 is not set +CONFIG_EXTCON_MAX14577=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_MAX77693=m +CONFIG_EXTCON_MAX77843=m +CONFIG_EXTCON_MAX8997=m +CONFIG_EXTCON_PALMAS=m +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_RT8973A=m +CONFIG_EXTCON_SM5502=m +CONFIG_EXTCON_USBC_CROS_EC=m +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_EXTCON_USB_GPIO=m +# CONFIG_EXTENDED_MODVERSIONS is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_EZX_PCAP=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +# CONFIG_F2FS_IOSTAT is not set +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_F71808E_WDT=m +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_FARSYNC=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_FB=y +CONFIG_FBNIC=m +CONFIG_FB_3DFX=m +# CONFIG_FB_3DFX_ACCEL is not set +# CONFIG_FB_3DFX_I2C is not set +CONFIG_FB_ARC=m +CONFIG_FB_ARK=m +CONFIG_FB_ASILIANT=y +CONFIG_FB_ATY=m +CONFIG_FB_ATY128=m +CONFIG_FB_ATY128_BACKLIGHT=y +CONFIG_FB_ATY_BACKLIGHT=y +CONFIG_FB_ATY_CT=y +# CONFIG_FB_ATY_GENERIC_LCD is not set +CONFIG_FB_ATY_GX=y +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_CARMINE=m +CONFIG_FB_CARMINE_DRAM_EVAL=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y +CONFIG_FB_CIRRUS=m +CONFIG_FB_CORE=y +CONFIG_FB_CYBER2000=m +CONFIG_FB_CYBER2000_DDC=y +CONFIG_FB_DDC=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_HECUBA=m +CONFIG_FB_HGA=m +CONFIG_FB_I740=m +CONFIG_FB_IBM_GXT4500=m +CONFIG_FB_IMSTT=y +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +CONFIG_FB_KYRO=m +CONFIG_FB_MATROX=m +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_I2C=y +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_METRONOME=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_N411=m +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_NOTIFY=y +# CONFIG_FB_NVIDIA is not set +CONFIG_FB_OPENCORES=m +CONFIG_FB_PM2=m +CONFIG_FB_PM2_FIFO_DISCONNECT=y +CONFIG_FB_PM3=m +CONFIG_FB_RADEON=m +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RIVA=m +CONFIG_FB_RIVA_BACKLIGHT=y +# CONFIG_FB_RIVA_DEBUG is not set +CONFIG_FB_RIVA_I2C=y +CONFIG_FB_S1D13XXX=m +CONFIG_FB_S3=m +CONFIG_FB_S3_DDC=y +CONFIG_FB_SAVAGE=m +# CONFIG_FB_SAVAGE_ACCEL is not set +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SIS=m +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +CONFIG_FB_SM501=m +CONFIG_FB_SM712=m CONFIG_FB_SM750=m -CONFIG_STAGING_MEDIA=y -CONFIG_INTEL_ATOMISP=y -CONFIG_DVB_AV7110=m -CONFIG_VIDEO_IPU3_IMGU=m -CONFIG_VIDEO_INTEL_IPU7=m +CONFIG_FB_SMSCUFX=m +CONFIG_FB_SSD1307=m +CONFIG_FB_SVGALIB=m +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m @@ -4853,1140 +2739,7927 @@ CONFIG_FB_TFT_TLS8204=m CONFIG_FB_TFT_UC1611=m CONFIG_FB_TFT_UC1701=m CONFIG_FB_TFT_UPD161704=m +CONFIG_FB_TILEBLITTING=y +CONFIG_FB_TRIDENT=m +CONFIG_FB_UDL=m +CONFIG_FB_UVESA=m +CONFIG_FB_VESA=y +CONFIG_FB_VGA16=m +CONFIG_FB_VIA=m +# CONFIG_FB_VIA_DIRECT_PROCFS is not set +CONFIG_FB_VIA_X_COMPATIBILITY=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_VOODOO1=m +CONFIG_FB_VT8623=m +CONFIG_FCOE=m +CONFIG_FCOE_FNIC=m +CONFIG_FDDI=y +CONFIG_FEALNX=m +CONFIG_FHANDLE=y +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_FIND_NORMAL_PAGE=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIRMWARE_EDID=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_FIRMWARE_TABLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FM10K=m +CONFIG_FONTS=y +# CONFIG_FONT_10x18 is not set +CONFIG_FONT_6x10=y +# CONFIG_FONT_6x11 is not set +CONFIG_FONT_6x8=y +# CONFIG_FONT_7x14 is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_SUN8x16 is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONT_TER16x32=y +CONFIG_FORCEDETH=m +CONFIG_FORTIFY_SOURCE=y +CONFIG_FPGA=m +CONFIG_FPGA_BRIDGE=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +CONFIG_FPGA_MGR_XILINX_CORE=m +CONFIG_FPGA_MGR_XILINX_SELECTMAP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_REGION=m +CONFIG_FPROBE=y +CONFIG_FPROBE_EVENTS=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMER=m +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=1024 +CONFIG_FREEZER=y +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSNOTIFY=y +CONFIG_FS_DAX=y +CONFIG_FS_DAX_PMD=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +# CONFIG_FS_ENCRYPTION_INLINE_CRYPT is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +CONFIG_FS_VERITY=y +# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set +CONFIG_FTL=m +CONFIG_FTRACE=y +CONFIG_FTRACE_MCOUNT_USE_CC=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +CONFIG_FUEL_GAUGE_MM8013=m +CONFIG_FUEL_GAUGE_STC3117=m +CONFIG_FUJITSU_ES=m +CONFIG_FUJITSU_LAPTOP=m +CONFIG_FUJITSU_TABLET=m +CONFIG_FUNCTION_ALIGNMENT=16 +CONFIG_FUNCTION_ALIGNMENT_16B=y +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FUNCTION_GRAPH_RETADDR is not set +# CONFIG_FUNCTION_GRAPH_RETVAL is not set +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PADDING_BYTES=16 +CONFIG_FUNCTION_PADDING_CFI=11 +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_TRACE_ARGS=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m +CONFIG_FUSE_DAX=y +CONFIG_FUSE_FS=m +CONFIG_FUSE_IO_URING=y +CONFIG_FUSE_PASSTHROUGH=y +CONFIG_FUSION=y +CONFIG_FUSION_CTL=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_SAS=m +CONFIG_FUSION_SPI=m +CONFIG_FUTEX=y +CONFIG_FUTEX_MPOL=y +CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y +CONFIG_FWCTL=y +CONFIG_FWCTL_MLX5=m +CONFIG_FWCTL_PDS=m +CONFIG_FWNODE_MDIO=y +CONFIG_FW_ATTR_CLASS=m +CONFIG_FW_CACHE=y +CONFIG_FW_CFG_SYSFS=m +# CONFIG_FW_CFG_SYSFS_CMDLINE is not set +CONFIG_FW_CS_DSP=m +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_UPLOAD=y +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_GACT_PROB=y +CONFIG_GADGET_UAC1=y +# CONFIG_GADGET_UAC1_LEGACY is not set +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_GARP=m +CONFIG_GART_IOMMU=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_VERSION=150300 +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_GEHC_PMC_ADC=m +# CONFIG_GENDWARFKSYMS is not set +CONFIG_GENERIC_ADC_BATTERY=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_ENTRY=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_SYSCALL=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_TRACER=y +CONFIG_GENERIC_VDSO_OVERFLOW_PROTECT=y +CONFIG_GENEVE=m +CONFIG_GENKSYMS=y +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_GET_FREE_REGION=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_GIGABYTE_WMI=m +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +# CONFIG_GOLDFISH is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GP2AP002=m +CONFIG_GP2AP020A00F=m +CONFIG_GPD_POCKET_FAN=m +CONFIG_GPIB=m +CONFIG_GPIB_AGILENT_82350B=m +CONFIG_GPIB_AGILENT_82357A=m +CONFIG_GPIB_CB7210=m +CONFIG_GPIB_CEC_PCI=m +CONFIG_GPIB_COMMON=m +CONFIG_GPIB_INES=m +CONFIG_GPIB_LPVO=m +CONFIG_GPIB_NEC7210=m +CONFIG_GPIB_NI_PCI_ISA=m +CONFIG_GPIB_NI_USB=m +CONFIG_GPIB_PCMCIA=y +CONFIG_GPIB_TMS9914=m +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIOLIB_LEGACY=y +CONFIG_GPIO_74X164=m +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_ADP5520=m +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_AMD8111=m +CONFIG_GPIO_AMDPT=m +CONFIG_GPIO_AMD_FCH=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_CGBC=m +# CONFIG_GPIO_CROS_EC is not set +CONFIG_GPIO_CRYSTAL_COVE=m +CONFIG_GPIO_DA9052=m +CONFIG_GPIO_DA9055=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_DS4520=m +CONFIG_GPIO_DWAPB=m +CONFIG_GPIO_ELKHARTLAKE=m +CONFIG_GPIO_EXAR=m +CONFIG_GPIO_F7188X=m +CONFIG_GPIO_FXL6408=m +CONFIG_GPIO_GENERIC=m +CONFIG_GPIO_GENERIC_PLATFORM=m +CONFIG_GPIO_GRANITERAPIDS=m +CONFIG_GPIO_ICH=m +CONFIG_GPIO_IDIO_16=m +CONFIG_GPIO_IT87=m +CONFIG_GPIO_JANZ_TTL=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LATCH=m +CONFIG_GPIO_LJCA=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX3191X=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MAX730X=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_MC33880=m +CONFIG_GPIO_MENZ127=m +CONFIG_GPIO_ML_IOH=m +# CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_MPSSE=m +CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_PCIE_IDIO_24=m +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_POLARFIRE_SOC=y +CONFIG_GPIO_RC5T583=y +CONFIG_GPIO_RDC321X=m +CONFIG_GPIO_REGMAP=m +CONFIG_GPIO_SCH=m +CONFIG_GPIO_SCH311X=m +# CONFIG_GPIO_SIM is not set +CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SYSFS_LEGACY=y +CONFIG_GPIO_TANGIER=m +CONFIG_GPIO_TPIC2810=m +CONFIG_GPIO_TPS65086=m +CONFIG_GPIO_TPS6586X=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TPS65912=m +CONFIG_GPIO_TPS68470=m +CONFIG_GPIO_TQMX86=m +CONFIG_GPIO_TWL4030=m +CONFIG_GPIO_TWL6040=m +CONFIG_GPIO_VIPERBOARD=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m +CONFIG_GPIO_VX855=m +CONFIG_GPIO_WHISKEY_COVE=m +CONFIG_GPIO_WINBOND=m +CONFIG_GPIO_WM831X=m +CONFIG_GPIO_WM8350=m +CONFIG_GPIO_WM8994=m +CONFIG_GPIO_WS16C48=m +CONFIG_GPIO_XILINX=m +CONFIG_GPIO_XRA1403=m +CONFIG_GP_PCI1XXXX=m +CONFIG_GRACE_PERIOD=m +CONFIG_GREENASIA_FF=y +# CONFIG_GREYBUS is not set +CONFIG_GROUP_SCHED_BANDWIDTH=y +CONFIG_GROUP_SCHED_WEIGHT=y +CONFIG_GRO_CELLS=y +CONFIG_GTP=m +CONFIG_GUEST_PERF_EVENTS=y +# CONFIG_GUP_TEST is not set +CONFIG_GVE=m +CONFIG_HALTPOLL_CPUIDLE=m +CONFIG_HAMACHI=m +CONFIG_HAMRADIO=y +CONFIG_HANGCHECK_TIMER=m +CONFIG_HAPPYMEAL=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_DEFAULT_ON=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_HARDLOCKUP_DETECTOR_ARCH is not set +# CONFIG_HARDLOCKUP_DETECTOR_BUDDY is not set +CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER=y +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +# CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_SECURITY_AUDIT=y +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_HAVE_ARCH_KCSAN=y +CONFIG_HAVE_ARCH_KFENCE=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KMSAN=y +CONFIG_HAVE_ARCH_KSTACK_ERASE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_HAVE_ARCH_NODE_DEV_GROUP=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +CONFIG_HAVE_ARCH_USERFAULTFD_WP=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_HAVE_CALL_THUNKS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_FTRACE_GRAPH_FUNC=y +CONFIG_HAVE_FTRACE_REGS_HAVING_PT_REGS=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_TIF_BITS=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_GIGANTIC_FOLIOS=y +CONFIG_HAVE_GUP_FAST=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_HAVE_INTEL_TXT=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_JUMP_LABEL_HACK=y +CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KVM_ARCH_GMEM_INVALIDATE=y +CONFIG_HAVE_KVM_ARCH_GMEM_POPULATE=y +CONFIG_HAVE_KVM_ARCH_GMEM_PREPARE=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_HAVE_KVM_DIRTY_RING=y +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y +CONFIG_HAVE_KVM_DIRTY_RING_TSO=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQ_BYPASS=m +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_NO_POLL=y +CONFIG_HAVE_KVM_PFNCACHE=y +CONFIG_HAVE_KVM_PM_NOTIFIER=y +CONFIG_HAVE_KVM_READONLY_MEM=y +CONFIG_HAVE_LIVEPATCH=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_NOINSTR_HACK=y +CONFIG_HAVE_NOINSTR_VALIDATION=y +CONFIG_HAVE_OBJTOOL=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y +CONFIG_HAVE_OBJTOOL_NOP_MCOUNT=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_TRUSTED_KEYS=y +CONFIG_HAVE_UACCESS_VALIDATION=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y +CONFIG_HAVE_UNWIND_USER_FP=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HD44780=m +CONFIG_HD44780_COMMON=m +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HDC3020=m +CONFIG_HDLC=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_X25=m +CONFIG_HDMI=y +CONFIG_HDMI_LPE_AUDIO=m +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_HFI1_DEBUG_SDMA_ORDER is not set +CONFIG_HFSPLUS_FS=m +CONFIG_HFS_FS=m +CONFIG_HI8435=m +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_DEF_COMP="lzo" +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HIBMCGE=m +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_ALPS=m +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_APPLETB_BL=m +CONFIG_HID_APPLETB_KBD=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +# CONFIG_HID_BPF is not set +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_GOODIX_SPI=m +CONFIG_HID_GOOGLE_HAMMER=m +CONFIG_HID_GOOGLE_STADIA_FF=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +# CONFIG_HID_HAPTIC is not set +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_KYSONA=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_HID_MACALLY=m +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MCP2200=m +CONFIG_HID_MCP2221=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_NVIDIA_SHIELD=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_RETRODE=m +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_HID_SENSOR_PRESS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_HID_SENSOR_TEMP=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +CONFIG_HID_TOPRE=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_UNIVERSAL_PIDFF=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_VIVALDI_COMMON=m +CONFIG_HID_VRC2=m +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WINWING=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +CONFIG_HINIC=m +CONFIG_HINIC3=m +# CONFIG_HIPPI is not set +# CONFIG_HIST_TRIGGERS is not set +CONFIG_HMC425=m +CONFIG_HMC6352=m +CONFIG_HMEM_REPORTING=y +CONFIG_HMM_MIRROR=y +CONFIG_HOLTEK_FF=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CORE_SYNC_FULL=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PARALLEL=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_HOTPLUG_PCI_ACPI_IBM=m +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m +CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m +CONFIG_HOTPLUG_PCI_OCTEONEP=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_HOTPLUG_SMT=y +CONFIG_HOTPLUG_SPLIT_STARTUP=y +CONFIG_HP03=m +CONFIG_HP206C=m +CONFIG_HPET=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_HPET_MMAP=y +CONFIG_HPET_MMAP_DEFAULT=y +CONFIG_HPET_TIMER=y +CONFIG_HPFS_FS=m +CONFIG_HPWDT_NMI_DECODING=y +CONFIG_HP_ACCEL=m +CONFIG_HP_BIOSCFG=m +CONFIG_HP_ILO=m +CONFIG_HP_WATCHDOG=m +CONFIG_HP_WMI=m +CONFIG_HSA_AMD=y +CONFIG_HSC030PA=m +CONFIG_HSC030PA_I2C=m +CONFIG_HSC030PA_SPI=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y +CONFIG_HSI_CHAR=m +CONFIG_HSR=m +CONFIG_HSU_DMA=m +CONFIG_HT16K33=m +CONFIG_HTE=y +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +CONFIG_HUAWEI_WMI=m +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y +# CONFIG_HWLAT_TRACER is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON_VID=m +CONFIG_HWPOISON_INJECT=m +# CONFIG_HWSPINLOCK is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_AMD=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_INTEL=m +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_HW_RANDOM_VIA=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HX711=m +CONFIG_HX9023S=m +# CONFIG_HYPERV is not set +CONFIG_HYPERVISOR_GUEST=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_AMD_ASF=m +CONFIG_I2C_AMD_MP2=m +CONFIG_I2C_ATR=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_CGBC=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CHT_WC=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_CROS_EC_TUNNEL=m +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +CONFIG_I2C_DESIGNWARE_AMDISP=m +CONFIG_I2C_DESIGNWARE_BAYTRAIL=y +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_EMEV2=m +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID=m +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_CORE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_I801=m +CONFIG_I2C_I801_MUX=y +CONFIG_I2C_ISCH=m +CONFIG_I2C_ISMT=m +CONFIG_I2C_KEBA=m +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_LJCA=m +CONFIG_I2C_MLXCPLD=m +CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_SCMI=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_SMBUS=m +CONFIG_I2C_STUB=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m +CONFIG_I2C_VIPERBOARD=m +CONFIG_I2C_VIRTIO=m +CONFIG_I2C_XILINX=m +CONFIG_I2C_ZHAOXIN=m +CONFIG_I3C=m +CONFIG_I40E=m +CONFIG_I40EVF=m +CONFIG_I40E_DCB=y +CONFIG_I6300ESB_WDT=m +CONFIG_I82092=m +CONFIG_I8253_LOCK=y +# CONFIG_I8K is not set +CONFIG_IA32_EMULATION=y +# CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set +CONFIG_IA32_FEAT_CTL=y +CONFIG_IAQCORE=m +CONFIG_IAVF=m +CONFIG_IB700_WDT=m +CONFIG_IBMASR=m +CONFIG_IBM_ASM=m +CONFIG_IBM_RTL=m +CONFIG_ICE=m +CONFIG_ICE_HWMON=y +CONFIG_ICE_HWTS=y +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICP10100=m +CONFIG_ICPLUS_PHY=m +CONFIG_ICS932S401=m +CONFIG_IDEAPAD_LAPTOP=m +CONFIG_IDLE_INJECT=y +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set +CONFIG_IE6XX_WDT=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_CA8210=m +# CONFIG_IEEE802154_CA8210_DEBUGFS is not set +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_HWSIM is not set +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IFB=m +CONFIG_IFCVF=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGB_DCA=y +CONFIG_IGB_HWMON=y +CONFIG_IGC=m +CONFIG_IGC_LEDS=y +CONFIG_IIO=m +CONFIG_IIO_ADC_HELPER=m +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y +CONFIG_IIO_BACKEND=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m +CONFIG_IIO_CROS_EC_ACTIVITY=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m +CONFIG_IIO_GTS_HELPER=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_INV_SENSORS_TIMESTAMP=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_KX022A=m +CONFIG_IIO_KX022A_I2C=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO_MS_SENSORS_I2C=m +CONFIG_IIO_MUX=m +CONFIG_IIO_RESCALE=m +CONFIG_IIO_SIMPLE_DUMMY=m +# CONFIG_IIO_SIMPLE_DUMMY_BUFFER is not set +# CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set +CONFIG_IIO_SSP_SENSORHUB=m +CONFIG_IIO_SSP_SENSORS_COMMONS=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_ST_GYRO_I2C_3AXIS=m +CONFIG_IIO_ST_GYRO_SPI_3AXIS=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM9DS0=m +CONFIG_IIO_ST_LSM9DS0_I2C=m +CONFIG_IIO_ST_LSM9DS0_SPI=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMA=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +# CONFIG_IMA_APPRAISE_MODSIG is not set +# CONFIG_IMA_ARCH_POLICY is not set +# CONFIG_IMA_BLACKLIST_KEYRING is not set +CONFIG_IMA_DEFAULT_HASH="sha1" +CONFIG_IMA_DEFAULT_HASH_SHA1=y +# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" +CONFIG_IMA_DISABLE_HTABLE=y +CONFIG_IMA_KEXEC=y +CONFIG_IMA_KEXEC_EXTRA_MEMORY_KB=0 +# CONFIG_IMA_LOAD_X509 is not set +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y +# CONFIG_IMA_READ_POLICY is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_WRITE_POLICY is not set +CONFIG_IMG_ASCII_LCD=m +CONFIG_INA2XX_ADC=m +CONFIG_INET=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=m +# CONFIG_INET_PSP is not set +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_SCTP_DIAG=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_XFRM_TUNNEL=m +# CONFIG_INFINEON_TLV493D is not set +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_HFI1=m +# CONFIG_INFINIBAND_IONIC is not set +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set +CONFIG_INFINIBAND_IRDMA=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_MTHCA=m +# CONFIG_INFINIBAND_MTHCA_DEBUG is not set +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_OPA_VNIC=m +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_RDMAVT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_USNIC=m +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_VMWARE_PVRDMA=m +CONFIG_INFTL=m +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INIT_STACK_ALL_PATTERN is not set +CONFIG_INIT_STACK_ALL_ZERO=y +# CONFIG_INIT_STACK_NONE is not set +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +CONFIG_INPUT_88PM80X_ONKEY=m +CONFIG_INPUT_88PM860X_ONKEY=m +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +CONFIG_INPUT_AD714X_SPI=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_APANEL=m +CONFIG_INPUT_ARIZONA_HAPTICS=m +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_ATLAS_BTNS=m +# CONFIG_INPUT_AW86927 is not set +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_CS40L50_VIBRA=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_DA9052_ONKEY=m +CONFIG_INPUT_DA9055_ONKEY=m +CONFIG_INPUT_DA9063_ONKEY=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_GPIO_BEEPER=m +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IDEAPAD_SLIDEBAR=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_LEDS=m +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_MAX77693_HAPTIC=m +CONFIG_INPUT_MAX8925_ONKEY=m +CONFIG_INPUT_MAX8997_HAPTIC=m +CONFIG_INPUT_MC13783_PWRBUTTON=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_PALMAS_PWRBUTTON=m +CONFIG_INPUT_PCAP=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PCSPKR=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_QNAP_MCU=m +CONFIG_INPUT_RAVE_SP_PWRBUTTON=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_RETU_PWRBUTTON=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_SOC_BUTTON_ARRAY=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_TABLET=y +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_INPUT_TPS6594_PWRBUTTON is not set +CONFIG_INPUT_TWL4030_PWRBUTTON=m +CONFIG_INPUT_TWL4030_VIBRA=m +CONFIG_INPUT_TWL6040_VIBRA=m +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_VIVALDIFMAP=y +CONFIG_INPUT_WM831X_ON=m +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m +CONFIG_INPUT_YEALINK=m +CONFIG_INSPUR_PLATFORM_PROFILE=m +CONFIG_INSTRUCTION_DECODER=y +CONFIG_INT3406_THERMAL=m +CONFIG_INT340X_THERMAL=m +CONFIG_INTEGRITY=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +CONFIG_INTEL_ATOMISP=y +CONFIG_INTEL_ATOMISP2_LED=m +CONFIG_INTEL_ATOMISP2_PDX86=y +CONFIG_INTEL_BXTWC_PMIC_TMU=m +CONFIG_INTEL_BXT_PMIC_THERMAL=m +CONFIG_INTEL_BYTCRC_PWRSRC=m +CONFIG_INTEL_CHTDC_TI_PWRBTN=m +CONFIG_INTEL_CHTWC_INT33FE=m +# CONFIG_INTEL_DC_TI_ADC is not set +CONFIG_INTEL_GTT=y +CONFIG_INTEL_HFI_THERMAL=y +CONFIG_INTEL_HID_EVENT=m +CONFIG_INTEL_IDLE=y +CONFIG_INTEL_IDMA64=m +CONFIG_INTEL_IDXD=m +CONFIG_INTEL_IDXD_BUS=m +# CONFIG_INTEL_IDXD_COMPAT is not set +CONFIG_INTEL_IDXD_PERFMON=y +CONFIG_INTEL_IDXD_SVM=y +CONFIG_INTEL_IFS=m +CONFIG_INTEL_INT0002_VGPIO=m +CONFIG_INTEL_IOATDMA=m +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_PERF_EVENTS is not set +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set +CONFIG_INTEL_IOMMU_SVM=y +CONFIG_INTEL_IPS=m +CONFIG_INTEL_ISHTP_ECLITE=m +# CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set +CONFIG_INTEL_ISH_HID=m +CONFIG_INTEL_LDMA=y +CONFIG_INTEL_MEI=m +CONFIG_INTEL_MEI_GSC=m +CONFIG_INTEL_MEI_GSC_PROXY=m +# CONFIG_INTEL_MEI_HDCP is not set +# CONFIG_INTEL_MEI_LB is not set +CONFIG_INTEL_MEI_ME=m +# CONFIG_INTEL_MEI_PXP is not set +# CONFIG_INTEL_MEI_TXE is not set +CONFIG_INTEL_MEI_VSC=m +CONFIG_INTEL_MEI_VSC_HW=m +CONFIG_INTEL_MEI_WDT=m +CONFIG_INTEL_MRFLD_ADC=m +CONFIG_INTEL_MRFLD_PWRBTN=m +CONFIG_INTEL_OAKTRAIL=m +CONFIG_INTEL_OC_WATCHDOG=m +CONFIG_INTEL_PCH_THERMAL=m +CONFIG_INTEL_PLR_TPMI=m +CONFIG_INTEL_PMC_CORE=m +CONFIG_INTEL_PMC_SSRAM_TELEMETRY=m +CONFIG_INTEL_PMT_CLASS=m +CONFIG_INTEL_PMT_CRASHLOG=m +CONFIG_INTEL_PMT_DISCOVERY=m +CONFIG_INTEL_PMT_TELEMETRY=m +CONFIG_INTEL_POWERCLAMP=m +CONFIG_INTEL_PUNIT_IPC=m +CONFIG_INTEL_QEP=m +CONFIG_INTEL_QUICKI2C=m +CONFIG_INTEL_QUICKSPI=m +CONFIG_INTEL_RAPL=m +CONFIG_INTEL_RAPL_CORE=m +CONFIG_INTEL_RAPL_TPMI=m +CONFIG_INTEL_RST=m +CONFIG_INTEL_SAR_INT1092=m +CONFIG_INTEL_SCU=y +CONFIG_INTEL_SCU_IPC=y +CONFIG_INTEL_SCU_IPC_UTIL=m +CONFIG_INTEL_SCU_PCI=y +CONFIG_INTEL_SCU_PLATFORM=m +CONFIG_INTEL_SDSI=m +CONFIG_INTEL_SKL_INT3472=m +CONFIG_INTEL_SMARTCONNECT=m +CONFIG_INTEL_SOC_DTS_IOSF_CORE=m +CONFIG_INTEL_SOC_DTS_THERMAL=m +CONFIG_INTEL_SOC_PMIC=y +CONFIG_INTEL_SOC_PMIC_BXTWC=m +CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m +CONFIG_INTEL_SOC_PMIC_CHTWC=y +CONFIG_INTEL_SOC_PMIC_MRFLD=m +CONFIG_INTEL_SPEED_SELECT_INTERFACE=m +CONFIG_INTEL_SPEED_SELECT_TPMI=m +CONFIG_INTEL_TCC=y +CONFIG_INTEL_TCC_COOLING=m +CONFIG_INTEL_TDX_GUEST=y +# CONFIG_INTEL_TDX_HOST is not set +CONFIG_INTEL_TELEMETRY=m +CONFIG_INTEL_TH=m +CONFIG_INTEL_THC_HID=m +CONFIG_INTEL_TH_ACPI=m +# CONFIG_INTEL_TH_DEBUG is not set +CONFIG_INTEL_TH_GTH=m +CONFIG_INTEL_TH_MSU=m +CONFIG_INTEL_TH_PCI=m +CONFIG_INTEL_TH_PTI=m +CONFIG_INTEL_TH_STH=m +CONFIG_INTEL_TPMI=m +CONFIG_INTEL_TPMI_POWER_DOMAINS=m +# CONFIG_INTEL_TURBO_MAX_3 is not set +CONFIG_INTEL_TXT=y +CONFIG_INTEL_UNCORE_FREQ_CONTROL=m +CONFIG_INTEL_UNCORE_FREQ_CONTROL_TPMI=m +CONFIG_INTEL_VBTN=m +CONFIG_INTEL_VSC=m +CONFIG_INTEL_VSEC=m +CONFIG_INTEL_WMI=y +CONFIG_INTEL_WMI_SBL_FW_UPDATE=m +CONFIG_INTEL_WMI_THUNDERBOLT=m +CONFIG_INTEL_XWAY_PHY=m +# CONFIG_INTERCONNECT is not set +CONFIG_INTERRUPT_CNT=m +CONFIG_INTERVAL_TREE=y +CONFIG_INTERVAL_TREE_TEST=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_SPI=m +# CONFIG_IOMMUFD is not set +CONFIG_IOMMUFD_DRIVER=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUG is not set +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_HELPER=y +CONFIG_IOMMU_IOPF=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_MM_DATA=y +CONFIG_IOMMU_SUPPORT=y +CONFIG_IOMMU_SVA=y +CONFIG_IONIC=m +CONFIG_IOSCHED_BFQ=m +CONFIG_IOSF_MBI=y +CONFIG_IOSF_MBI_DEBUG=y +CONFIG_IOSM=m +# CONFIG_IO_DELAY_0X80 is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_IO_DELAY_UDELAY is not set +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IO_URING_MOCK_FILE is not set +CONFIG_IO_URING_ZCRX=y +CONFIG_IO_WQ=y +CONFIG_IP5XXX_POWER=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_IPTABLES_LEGACY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IPACK_BUS=m +CONFIG_IPC_NS=y +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_IPMB=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPU_BRIDGE=m +CONFIG_IPV6=y +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_ILA=m +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPVLAN=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVTAP=m +CONFIG_IPW2100=m +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2200=m +# CONFIG_IPW2200_DEBUG is not set +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPWIRELESS=m +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_COMMON=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_IPTABLES_LEGACY=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +CONFIG_IP_VS_TWOS=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IQS620AT_TEMP=m +CONFIG_IQS621_ALS=m +CONFIG_IQS624_POS=m +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_REMAP=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_IRQ_WORK=y +CONFIG_IRSD200=m +CONFIG_IR_ENE=m +CONFIG_IR_FINTEK=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_XMP_DECODER=m +# CONFIG_ISA_BUS is not set +CONFIG_ISA_BUS_API=y +CONFIG_ISA_DMA_API=y +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ISCSI_IBFT=m +CONFIG_ISCSI_IBFT_FIND=y +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TCP=m +CONFIG_ISDN=y +CONFIG_ISDN_CAPI=y +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_ISL29125=m +CONFIG_ISL29501=m +CONFIG_ISL76682=m +CONFIG_ISO9660_FS=m +CONFIG_IT8712F_WDT=m +CONFIG_IT87_WDT=m +CONFIG_ITCO_VENDOR_SUPPORT=y +CONFIG_ITCO_WDT=m +CONFIG_ITG3200=m +CONFIG_IWL3945=m +CONFIG_IWL4965=m +CONFIG_IWLDVM=m +CONFIG_IWLEGACY=m +# CONFIG_IWLEGACY_DEBUG is not set +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLMLD=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI=m +# CONFIG_IWLWIFI_DEBUG is not set +CONFIG_IWLWIFI_DEBUGFS=y +CONFIG_IWLWIFI_DEVICE_TRACING=y +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLWIFI_OPMODE_MODULAR=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBE_DCA=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_JAILHOUSE_GUEST=y +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_JFFS2_CMODE_FAVOURLZO=y +# CONFIG_JFFS2_CMODE_NONE is not set +# CONFIG_JFFS2_CMODE_PRIORITY is not set +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_JME=m +CONFIG_JOLIET=y +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +# CONFIG_JOYSTICK_PSXPAD_SPI_FF is not set +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_SEESAW=m +CONFIG_JOYSTICK_SENSEHAT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JSA1212=m +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KARMA_PARTITION=y +# CONFIG_KASAN is not set +CONFIG_KCMP=y +# CONFIG_KCOV is not set +# CONFIG_KCSAN is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m +CONFIG_KEBA_LAN9252=m +CONFIG_KEMPLD_WDT=m +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KERNFS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_HANDOVER=y +# CONFIG_KEXEC_HANDOVER_DEBUG is not set +CONFIG_KEXEC_HANDOVER_DEBUGFS=y +CONFIG_KEXEC_JUMP=y +# CONFIG_KEXEC_SIG is not set +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_ADP5520=m +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_APPLESPI=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_CROS_EC=m +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_KEYBOARD_DLINK_DIR685=m +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_IQS62X=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_MTK_PMIC=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_TWL4030=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYS=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_KFENCE=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=0 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KMX61=m +CONFIG_KPROBES=y +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_KS0108=m +CONFIG_KS0108_DELAY=2 +CONFIG_KS0108_PORT=0x378 +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSM=y +CONFIG_KSZ884X_PCI=m +# CONFIG_KUNIT is not set +CONFIG_KVFREE_RCU_BATCHED=y +CONFIG_KVM=m +CONFIG_KVM_AMD=m +CONFIG_KVM_AMD_SEV=y +CONFIG_KVM_ASYNC_PF=y +CONFIG_KVM_COMMON=y +CONFIG_KVM_COMPAT=y +CONFIG_KVM_ELIDE_TLB_FLUSH_IF_YOUNG=y +CONFIG_KVM_EXTERNAL_WRITE_TRACKING=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES=y +CONFIG_KVM_GENERIC_MMU_NOTIFIER=y +CONFIG_KVM_GENERIC_PRE_FAULT_MEMORY=y +CONFIG_KVM_GUEST=y +CONFIG_KVM_GUEST_MEMFD=y +CONFIG_KVM_HYPERV=y +CONFIG_KVM_INTEL=m +# CONFIG_KVM_INTEL_PROVE_VE is not set +CONFIG_KVM_IOAPIC=y +CONFIG_KVM_MAX_NR_VCPUS=1024 +CONFIG_KVM_MMIO=y +CONFIG_KVM_MMU_LOCKLESS_AGING=y +# CONFIG_KVM_PROVE_MMU is not set +CONFIG_KVM_SMM=y +# CONFIG_KVM_SW_PROTECTED_VM is not set +CONFIG_KVM_VFIO=y +CONFIG_KVM_WERROR=y +CONFIG_KVM_X86=m +CONFIG_KVM_XEN=y +CONFIG_KXCJK1013=m +CONFIG_KXSD9=m +CONFIG_KXSD9_I2C=m +CONFIG_KXSD9_SPI=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +CONFIG_LAN865X=m +CONFIG_LAPB=m +CONFIG_LAPBETHER=m +# CONFIG_LATENCYTOP is not set +CONFIG_LATTICE_ECP3_CONFIG=m +CONFIG_LCD2S=m +CONFIG_LCD_AMS369FG06=m +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_HX8357=m +CONFIG_LCD_ILI922X=m +CONFIG_LCD_ILI9320=m +CONFIG_LCD_L4F00242T03=m +CONFIG_LCD_LMS283GF05=m +CONFIG_LCD_LMS501KF03=m +CONFIG_LCD_LTV350QV=m +CONFIG_LCD_OTM3225A=m +CONFIG_LCD_PLATFORM=m +CONFIG_LCD_TDO24M=m +CONFIG_LCD_VGG2432A4=m +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_DEBUG is not set +CONFIG_LDM_PARTITION=y +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y +CONFIG_LD_IS_BFD=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_LD_VERSION=24690 +CONFIG_LEDS_88PM860X=m +CONFIG_LEDS_ADP5520=m +CONFIG_LEDS_APU=m +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_AW200XX=m +CONFIG_LEDS_BD2606MVV=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_BLINKM_MULTICOLOR=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CHT_WCOVE=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_CROS_EC=m +CONFIG_LEDS_DA903X=m +CONFIG_LEDS_DA9052=m +CONFIG_LEDS_DAC124S085=m +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_INTEL_SS4200=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_KTD202X=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_LM36274=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP8788=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_MAX77705=m +CONFIG_LEDS_MAX8997=m +CONFIG_LEDS_MC13783=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_MLXCPLD=m +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_MT6323=m +CONFIG_LEDS_MT6370_FLASH=m +CONFIG_LEDS_MT6370_RGB=m +CONFIG_LEDS_NIC78BX=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_PCA955X=m +# CONFIG_LEDS_PCA955X_GPIO is not set +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QNAP_MCU=m +CONFIG_LEDS_REGULATOR=m +# CONFIG_LEDS_RT8515 is not set +CONFIG_LEDS_SGM3140=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_APOLLOLAKE=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_ELKHARTLAKE=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_F7188X=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TCA6507=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_TLC591XX=m +CONFIG_LEDS_TPS6105X=m +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m +# CONFIG_LEDS_TRIGGER_MTD is not set +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_LEDS_UPBOARD=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_WM831X_STATUS=m +CONFIG_LEDS_WM8350=m +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_LEGACY_VSYSCALL_NONE=y +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +CONFIG_LENOVO_SE10_WDT=m +CONFIG_LENOVO_SE30_WDT=m +CONFIG_LENOVO_WMI_CAMERA=m +CONFIG_LENOVO_WMI_DATA01=m +CONFIG_LENOVO_WMI_EVENTS=m +CONFIG_LENOVO_WMI_GAMEZONE=m +CONFIG_LENOVO_WMI_HELPERS=m +CONFIG_LENOVO_WMI_HOTKEY_UTILITIES=m +CONFIG_LENOVO_WMI_TUNING=m +CONFIG_LENOVO_YMC=m +CONFIG_LG_LAPTOP=m +CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBETH=m +CONFIG_LIBETH_XDP=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y +CONFIG_LIBIE=m +CONFIG_LIBIE_ADMINQ=m +CONFIG_LIBIE_FWLOG=m +CONFIG_LIBIPW=m +# CONFIG_LIBIPW_DEBUG is not set +CONFIG_LIBNVDIMM=y +CONFIG_LIBWX=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_LINEAR_RANGES=y +CONFIG_LINEDISP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_CORE=m +CONFIG_LIQUIDIO_VF=m +CONFIG_LIRC=y +# CONFIG_LIST_HARDENED is not set +CONFIG_LIVEPATCH=y +# CONFIG_LKDTM is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_LLD_VERSION=0 +CONFIG_LMK04832=m +CONFIG_LMP91000=m +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKD=m +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_TORTURE_TEST=m +CONFIG_LOGIG940_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOOPBACK_TARGET=m +CONFIG_LP8788_ADC=m +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +# CONFIG_LP_CONSOLE is not set +CONFIG_LRU_CACHE=m +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo" +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_LTC1660=m +CONFIG_LTC2309=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +CONFIG_LTC2632=m +CONFIG_LTC2664=m +CONFIG_LTC2688=m +CONFIG_LTC2983=m +CONFIG_LTO_NONE=y +CONFIG_LTR390=m +CONFIG_LTR501=m +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_LXT_PHY=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_M62332=m +CONFIG_MAC80211=m +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_HWSIM=m +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MAC802154=m +CONFIG_MACB=m +CONFIG_MACB_PCI=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACHZ_WDT=m +CONFIG_MACINTOSH_DRIVERS=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_MAC_EMUMOUSEBTN=m +CONFIG_MAC_PARTITION=y +CONFIG_MADERA_IRQ=m +CONFIG_MAG3110=m +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAILBOX=y +CONFIG_MANAGER_SBS=m +CONFIG_MANTIS_CORE=m +CONFIG_MAPPING_DIRTY_HELPERS=y +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88Q2XXX_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MAX1027=m +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +CONFIG_MAX30208=m +CONFIG_MAX31827=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_MAX34408=m +CONFIG_MAX44000=m +CONFIG_MAX44009=m +CONFIG_MAX517=m +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MAX5522=m +CONFIG_MAX5821=m +CONFIG_MAX63XX_WATCHDOG=m +# CONFIG_MAX6959 is not set +CONFIG_MAX77541_ADC=m +CONFIG_MAX8925_POWER=m +CONFIG_MAX9611=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAXLINEAR_86110_PHY=m +CONFIG_MAXLINEAR_GPHY=m +# CONFIG_MAXSMP is not set +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_MB1232=m +CONFIG_MC3230=m +CONFIG_MCB=m +CONFIG_MCB_LPC=m +CONFIG_MCB_PCI=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_MCP3564=m +CONFIG_MCP3911=m +CONFIG_MCP4018=m +CONFIG_MCP41010=m +CONFIG_MCP4131=m +CONFIG_MCP4531=m +CONFIG_MCP4725=m +CONFIG_MCP4728=m +CONFIG_MCP4821=m +CONFIG_MCP4922=m +CONFIG_MCP9600=m +CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +# CONFIG_MCTP_TRANSPORT_I3C is not set +CONFIG_MCTP_TRANSPORT_USB=m +CONFIG_MD=y +CONFIG_MDIO=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BUS=y +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_REGMAP=m +CONFIG_MDIO_THUNDER=m +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP=y +CONFIG_MD_BITMAP_FILE=y +CONFIG_MD_CLUSTER=m +CONFIG_MD_LINEAR=m +# CONFIG_MD_LLBITMAP is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MEDIATEK_GE_PHY=m +# CONFIG_MEDIATEK_GE_SOC_PHY is not set +CONFIG_MEDIATEK_MT6359_AUXADC=m +# CONFIG_MEDIATEK_MT6360_ADC is not set +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_COMMON_OPTIONS=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_MEEGOPAD_ANX7428=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_SAS=m +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_MEMBARRIER=y +CONFIG_MEMBLOCK_KHO_SCRATCH=y +CONFIG_MEMCG=y +CONFIG_MEMCG_V1=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_FAILURE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m +CONFIG_MEMREGION=y +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MEMTEST=y +CONFIG_MEM_ALLOC_PROFILING=y +CONFIG_MEM_ALLOC_PROFILING_DEBUG=y +CONFIG_MEM_ALLOC_PROFILING_ENABLED_BY_DEFAULT=y +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_MENF21BMC_WATCHDOG=m +CONFIG_MENZ069_WATCHDOG=m +CONFIG_MEN_A21_WDT=m +CONFIG_MEN_Z188_ADC=m +CONFIG_MERAKI_MX100=m +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_MFD_88PM800=m +CONFIG_MFD_88PM805=m +CONFIG_MFD_88PM860X=y +CONFIG_MFD_AAT2870_CORE=y +CONFIG_MFD_ARIZONA=m +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_AS3711=y +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_BCM590XX=m +CONFIG_MFD_BD9571MWV=m +# CONFIG_MFD_BQ257XX is not set +CONFIG_MFD_CGBC=m +CONFIG_MFD_CORE=y +CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_CORE=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m +CONFIG_MFD_CS42L43=m +CONFIG_MFD_CS42L43_I2C=m +CONFIG_MFD_CS42L43_SDW=m +# CONFIG_MFD_CS47L15 is not set +CONFIG_MFD_CS47L24=y +# CONFIG_MFD_CS47L35 is not set +# CONFIG_MFD_CS47L85 is not set +# CONFIG_MFD_CS47L90 is not set +# CONFIG_MFD_CS47L92 is not set +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9052_SPI=y +CONFIG_MFD_DA9055=y +CONFIG_MFD_DA9062=m +CONFIG_MFD_DA9063=y +CONFIG_MFD_DA9150=m +CONFIG_MFD_DLN2=m +CONFIG_MFD_INTEL_LPSS=m +CONFIG_MFD_INTEL_LPSS_ACPI=m +CONFIG_MFD_INTEL_LPSS_PCI=m +CONFIG_MFD_INTEL_M10_BMC_CORE=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +CONFIG_MFD_INTEL_PMC_BXT=m +CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m +CONFIG_MFD_IQS62X=m +CONFIG_MFD_JANZ_CMODIO=m +CONFIG_MFD_KEMPLD=m +CONFIG_MFD_LM3533=m +CONFIG_MFD_LP3943=m +CONFIG_MFD_LP8788=y +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_MAX14577=y +# CONFIG_MFD_MAX7360 is not set +CONFIG_MFD_MAX77541=m +CONFIG_MFD_MAX77693=y +CONFIG_MFD_MAX77705=m +CONFIG_MFD_MAX77843=y +CONFIG_MFD_MAX8907=m +CONFIG_MFD_MAX8925=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_MAX8998=y +CONFIG_MFD_MC13XXX=m +CONFIG_MFD_MC13XXX_I2C=m +CONFIG_MFD_MC13XXX_SPI=m +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_MP2629=m +CONFIG_MFD_MT6360=m +CONFIG_MFD_MT6370=m +CONFIG_MFD_MT6397=m +# CONFIG_MFD_NCT6694 is not set +CONFIG_MFD_OCELOT=m +CONFIG_MFD_PALMAS=y +CONFIG_MFD_QNAP_MCU=m +CONFIG_MFD_RC5T583=y +CONFIG_MFD_RDC321X=m +CONFIG_MFD_RETU=m +CONFIG_MFD_RT4831=m +CONFIG_MFD_RT5033=m +CONFIG_MFD_RT5120=m +CONFIG_MFD_SI476X_CORE=m +CONFIG_MFD_SIMPLE_MFD_I2C=m +CONFIG_MFD_SKY81452=m +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_SMPRO=m +CONFIG_MFD_SY7636A=m +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_LMU=m +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TPS65086=m +CONFIG_MFD_TPS65090=y +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_TPS65912=y +CONFIG_MFD_TPS65912_I2C=y +CONFIG_MFD_TPS65912_SPI=y +CONFIG_MFD_TPS6594=y +CONFIG_MFD_TPS6594_I2C=y +CONFIG_MFD_TPS6594_SPI=y +CONFIG_MFD_TQMX86=m +CONFIG_MFD_TWL4030_AUDIO=y +CONFIG_MFD_UPBOARD_FPGA=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_VX855=m +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_WM5102=y +CONFIG_MFD_WM5110=y +CONFIG_MFD_WM831X=y +CONFIG_MFD_WM831X_I2C=y +CONFIG_MFD_WM831X_SPI=y +CONFIG_MFD_WM8350=y +CONFIG_MFD_WM8350_I2C=y +CONFIG_MFD_WM8400=y +CONFIG_MFD_WM8994=m +CONFIG_MFD_WM8997=y +CONFIG_MFD_WM8998=y +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_EP=m +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_NET=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE=y +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set +CONFIG_MHP_MEMMAP_ON_MEMORY=y +CONFIG_MHZ19B=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROCODE=y +# CONFIG_MICROCODE_DBG is not set +# CONFIG_MICROCODE_LATE_LOADING is not set +CONFIG_MICROSEMI_PHY=m +CONFIG_MIGRATION=y +CONFIG_MII=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_SUBPARTITION=y +CONFIG_MIN_HEAP=y +# CONFIG_MIPI_I3C_HCI is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_FILESYSTEMS=y +CONFIG_MISC_RTSX=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MISDN=m +CONFIG_MISDN_AVMFRITZ=m +CONFIG_MISDN_DSP=m +CONFIG_MISDN_HDLC=m +CONFIG_MISDN_HFCMULTI=m +CONFIG_MISDN_HFCPCI=m +CONFIG_MISDN_HFCUSB=m +CONFIG_MISDN_INFINEON=m +CONFIG_MISDN_IPAC=m +CONFIG_MISDN_ISAR=m +CONFIG_MISDN_L1OIP=m +CONFIG_MISDN_NETJET=m +CONFIG_MISDN_SPEEDFAX=m +CONFIG_MISDN_W6692=m +CONFIG_MITIGATION_CALL_DEPTH_TRACKING=y +CONFIG_MITIGATION_GDS=y +CONFIG_MITIGATION_IBPB_ENTRY=y +CONFIG_MITIGATION_IBRS_ENTRY=y +CONFIG_MITIGATION_ITS=y +CONFIG_MITIGATION_L1TF=y +CONFIG_MITIGATION_MDS=y +CONFIG_MITIGATION_MMIO_STALE_DATA=y +CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=y +CONFIG_MITIGATION_RETBLEED=y +CONFIG_MITIGATION_RETHUNK=y +CONFIG_MITIGATION_RETPOLINE=y +CONFIG_MITIGATION_RFDS=y +# CONFIG_MITIGATION_SLS is not set +CONFIG_MITIGATION_SPECTRE_BHI=y +CONFIG_MITIGATION_SPECTRE_V1=y +CONFIG_MITIGATION_SPECTRE_V2=y +CONFIG_MITIGATION_SRBDS=y +CONFIG_MITIGATION_SRSO=y +CONFIG_MITIGATION_SSB=y +CONFIG_MITIGATION_TAA=y +CONFIG_MITIGATION_TSA=y +CONFIG_MITIGATION_UNRET_ENTRY=y +CONFIG_MITIGATION_VMSCAPE=y +CONFIG_MKISS=m +CONFIG_MLX4_CORE=m +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_EN_DCB=y +# CONFIG_MLX5_CORE_IPOIB is not set +CONFIG_MLX5_DPLL=m +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_HW_STEERING=y +CONFIG_MLX5_INFINIBAND=m +# CONFIG_MLX5_MACSEC is not set +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_MLX5_VFIO_PCI=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +CONFIG_MLX90635=m +CONFIG_MLXFW=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +CONFIG_MMA8452=m +CONFIG_MMA9551=m +CONFIG_MMA9551_CORE=m +CONFIG_MMA9553=m +CONFIG_MMC=y +CONFIG_MMC35240=m +CONFIG_MMCONF_FAM10H=y +CONFIG_MMC_ALCOR=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_CRYPTO=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_HSQ=m +CONFIG_MMC_MTK=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_ACPI=m +CONFIG_MMC_SDHCI_F_SDH30=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_UHS2=m +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_SPI=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_WBSD=m +CONFIG_MMIOTRACE=y +# CONFIG_MMIOTRACE_TEST is not set +CONFIG_MMU=y +CONFIG_MMU_GATHER_MERGE_VMAS=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MM_ID=y +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ALL=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +CONFIG_MODULE_COMPRESS_ZSTD=y +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_DECOMPRESS=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +CONFIG_MOST=m +CONFIG_MOST_CDEV=m CONFIG_MOST_COMPONENTS=m CONFIG_MOST_NET=m +CONFIG_MOST_SND=m +CONFIG_MOST_USB_HDM=m CONFIG_MOST_VIDEO=m -CONFIG_VME_BUS=y -CONFIG_VME_TSI148=m -CONFIG_VME_USER=m -CONFIG_GPIB=m -CONFIG_GPIB_AGILENT_82350B=m -CONFIG_GPIB_AGILENT_82357A=m -CONFIG_GPIB_CEC_PCI=m -CONFIG_GPIB_NI_PCI_ISA=m -CONFIG_GPIB_CB7210=m -CONFIG_GPIB_NI_USB=m -CONFIG_GPIB_INES=m -CONFIG_GPIB_LPVO=m -CONFIG_CHROME_PLATFORMS=y -CONFIG_CHROMEOS_ACPI=m -CONFIG_CHROMEOS_LAPTOP=m -CONFIG_CHROMEOS_PSTORE=m -CONFIG_CHROMEOS_TBMC=m -CONFIG_CROS_EC=m -CONFIG_CROS_EC_I2C=m -CONFIG_CROS_EC_ISHTP=m -CONFIG_CROS_EC_SPI=m -CONFIG_CROS_EC_UART=m -CONFIG_CROS_EC_LPC=m -CONFIG_CROS_KBD_LED_BACKLIGHT=m -CONFIG_CROS_HPS_I2C=m -CONFIG_CHROMEOS_PRIVACY_SCREEN=m -CONFIG_WILCO_EC=m -CONFIG_WILCO_EC_EVENTS=m -CONFIG_WILCO_EC_TELEMETRY=m -CONFIG_SURFACE3_WMI=m -CONFIG_SURFACE_3_POWER_OPREGION=m -CONFIG_SURFACE_ACPI_NOTIFY=m -CONFIG_SURFACE_AGGREGATOR_HUB=m -CONFIG_SURFACE_AGGREGATOR_REGISTRY=m -CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m -CONFIG_SURFACE_DTX=m -CONFIG_SURFACE_GPE=m -CONFIG_SURFACE_HOTPLUG=m -CONFIG_SURFACE_PLATFORM_PROFILE=m -CONFIG_SURFACE_PRO3_BUTTON=m -CONFIG_SURFACE_AGGREGATOR=m -CONFIG_HUAWEI_WMI=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_VMMOUSE=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_MP2629_ADC=m +CONFIG_MPILIB=y +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +CONFIG_MPL3115=m +CONFIG_MPLS=y +CONFIG_MPLS_IPTUNNEL=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPRLS0025PA=m +CONFIG_MPRLS0025PA_I2C=m +CONFIG_MPRLS0025PA_SPI=m +CONFIG_MPTCP=y +CONFIG_MPTCP_IPV6=y +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_MRP=m +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_MS5611_SPI=m +CONFIG_MS5637=m +CONFIG_MSA311=m +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSDOS_FS=m +CONFIG_MSDOS_PARTITION=y +CONFIG_MSE102X=m +CONFIG_MSI_EC=m +CONFIG_MSI_LAPTOP=m +CONFIG_MSI_WMI=m +CONFIG_MSI_WMI_PLATFORM=m +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m +CONFIG_MT7601U=m +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7663U is not set +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +# CONFIG_MT76x0E is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x2E is not set +CONFIG_MT76x2U=m +CONFIG_MT76x2_COMMON=m +# CONFIG_MT7915E is not set +CONFIG_MT7921E=m +# CONFIG_MT7921S is not set +# CONFIG_MT7921U is not set +CONFIG_MT7921_COMMON=m +CONFIG_MT7925E=m +CONFIG_MT7925U=m +CONFIG_MT7925_COMMON=m +CONFIG_MT792x_LIB=m +CONFIG_MT792x_USB=m +# CONFIG_MT7996E is not set +CONFIG_MTD=m +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTD_ABSENT=m +CONFIG_MTD_AMD76XROM=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_MTD_CFI=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CK804XROM=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_DATAFLASH_OTP=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_DOCG3=m +CONFIG_MTD_ESB2ROM=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_HYPERBUS=m +CONFIG_MTD_ICHXROM=m +CONFIG_MTD_INTEL_DG=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_L440GX=m +CONFIG_MTD_LPDDR=m +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_NAND_DENALI=m +CONFIG_MTD_NAND_DENALI_PCI=m +CONFIG_MTD_NAND_DISKONCHIP=m +# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 +# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MXIC=y +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NETtel=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_ONENAND_GENERIC=m +# CONFIG_MTD_ONENAND_OTP is not set +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_OOPS=m +# CONFIG_MTD_PARTITIONED_MASTER is not set +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_PHRAM=m +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PLATRAM=m +CONFIG_MTD_PMC551=m +# CONFIG_MTD_PMC551_BUGFIX is not set +# CONFIG_MTD_PMC551_DEBUG is not set +CONFIG_MTD_QINFO_PROBE=m +CONFIG_MTD_RAM=m +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +CONFIG_MTD_REDBOOT_PARTS=m +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +CONFIG_MTD_ROM=m +CONFIG_MTD_SBC_GXX=m +CONFIG_MTD_SCB2_FLASH=m +CONFIG_MTD_SLRAM=m +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SST25L=m +CONFIG_MTD_SWAP=m +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_NVMEM is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTK_NET_PHYLIB=m +CONFIG_MTK_T7XX=m +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_MULTIPLEXER=m +CONFIG_MULTIUSER=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MVMDIO=m +CONFIG_MWAVE=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_MXM_WMI=m +CONFIG_MYRI10GE=m +CONFIG_MYRI10GE_DCA=y +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +CONFIG_NATSEMI=m +CONFIG_NAU7802=m +CONFIG_NCN26000_PHY=m +# CONFIG_NCSI_OEM_CMD_GET_MAC is not set +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_NCT7201=m +CONFIG_ND_BTT=m +CONFIG_ND_CLAIM=y +CONFIG_ND_PFN=m +CONFIG_NE2K_PCI=m +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_SG_DMA_FLAGS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET=y +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETDEVICES=y +CONFIG_NETDEVSIM=m +CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y +CONFIG_NETFILTER_XTABLES_LEGACY=y +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFS_DEBUG=y +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=m +# CONFIG_NETKIT is not set +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=m +CONFIG_NETPOLL=y +CONFIG_NETROM=m +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETXEN_NIC=m +CONFIG_NET_9P=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_RDMA=m +CONFIG_NET_9P_USBG=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CORE=y +CONFIG_NET_CRC32C=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NET_DROP_MONITOR=m +CONFIG_NET_DSA=m +CONFIG_NET_DSA_AR9331=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +# CONFIG_NET_DSA_KS8995 is not set +CONFIG_NET_DSA_LANTIQ_GSWIP=m +# CONFIG_NET_DSA_LOOP is not set +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=m +CONFIG_NET_DSA_MSCC_OCELOT_EXT=m +CONFIG_NET_DSA_MSCC_SEVILLE=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MT7530_MDIO=m +CONFIG_NET_DSA_MT7530_MMIO=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_LEDS=y +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +# CONFIG_NET_DSA_SJA1105_TAS is not set +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_NONE=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +CONFIG_NET_DSA_TAG_RZN1_A5PSW=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_VSC73XX_8021Q=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_EGRESS=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_FAILOVER=y +CONFIG_NET_FC=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_NET_HANDSHAKE=y +CONFIG_NET_IEEE8021Q_HELPERS=y +CONFIG_NET_IFE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_INGRESS=y +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_MPLS_GSO=m +CONFIG_NET_NCSI=y +CONFIG_NET_NS=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_REDIRECT=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_BPF is not set +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +# CONFIG_NET_SCH_DEFAULT is not set +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_DUALPI2=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_SCH_FIFO=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SHAPER=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TULIP=y +CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_ADI=y +CONFIG_NET_VENDOR_AGERE=y +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_ENGLEDER=y +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NETERION=y +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NET_VENDOR_NI=y +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_NET_VENDOR_VIA=y +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_NET_VRF=m +CONFIG_NET_XGRESS=y +CONFIG_NEW_LEDS=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_FDP=m +CONFIG_NFC_FDP_I2C=m +CONFIG_NFC_HCI=m +CONFIG_NFC_MEI_PHY=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MICROREAD_MEI=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_MRVL_SPI=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN544_MEI=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_SIM=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST95HF=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_APP_ABM_NIC=y +# CONFIG_NFP_APP_FLOWER is not set +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP_NET_IPSEC=y +CONFIG_NFSD=m +# CONFIG_NFSD_BLOCKLAYOUT is not set +# CONFIG_NFSD_FLEXFILELAYOUT is not set +# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set +# CONFIG_NFSD_SCSILAYOUT is not set +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +# CONFIG_NFSD_V4_2_INTER_SSC is not set +# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_COMMON_LOCALIO_SUPPORT=m +CONFIG_NFS_DEBUG=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFS_FS=m +CONFIG_NFS_FSCACHE=y +CONFIG_NFS_LOCALIO=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_NFS_V4_2=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COMPAT_ARP=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +# CONFIG_NFT_EXTHDR_DCCP is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_OSF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_XFRM=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CONNTRACK_PPTP=m +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE_PROCFS=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NGBE=m +CONFIG_NGBEVF=m +CONFIG_NI903X_WDT=m +CONFIG_NIC7018_WDT=m +CONFIG_NILFS2_FS=m +CONFIG_NINTENDO_FF=y +CONFIG_NITRO_ENCLAVES=m +CONFIG_NIU=m +CONFIG_NI_XGE_MANAGEMENT_ENET=m +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +CONFIG_NLMON=m +CONFIG_NLS=y +CONFIG_NLS_ASCII=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +# CONFIG_NMI_CHECK_CPU is not set +CONFIG_NOA1305=m +CONFIG_NODES_SHIFT=6 +CONFIG_NOP_TRACER=y +CONFIG_NOP_USB_XCEIV=m +CONFIG_NOTIFIER_ERROR_INJECTION=m +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_NOZOMI=m +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_PAGE_MAPCOUNT is not set +CONFIG_NR_CPUS=256 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NS83820=m +CONFIG_NSM=m +CONFIG_NTB=m +CONFIG_NTB_AMD=m +CONFIG_NTB_EPF=m +CONFIG_NTB_IDT=m +CONFIG_NTB_INTEL=m +CONFIG_NTB_MSI=y +CONFIG_NTB_MSI_TEST=m +CONFIG_NTB_NETDEV=m +CONFIG_NTB_PERF=m +CONFIG_NTB_PINGPONG=m +CONFIG_NTB_SWITCHTEC=m +CONFIG_NTB_TOOL=m +CONFIG_NTB_TRANSPORT=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_FS_POSIX_ACL is not set +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS_FS=m +CONFIG_NTSYNC=m +CONFIG_NULL_TTY=m +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NUMA_EMU is not set +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NVDIMM_DAX=y +CONFIG_NVDIMM_KEYS=y +CONFIG_NVDIMM_PFN=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_NVIDIA_SHIELD_FF=y CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m -CONFIG_XIAOMI_WMI=m -CONFIG_GIGABYTE_WMI=m -CONFIG_ACERHDF=m -CONFIG_ACER_WIRELESS=m -CONFIG_ACER_WMI=m -CONFIG_AMD_HSMP_ACPI=y -CONFIG_AMD_HSMP_PLAT=m -CONFIG_AMD_PMF=m -CONFIG_AMD_PMC=m -CONFIG_AMD_HFI=y -CONFIG_AMD_3D_VCACHE=m -CONFIG_AMD_WBRF=y -CONFIG_AMD_ISP_PLATFORM=m -CONFIG_ADV_SWBUTTON=m -CONFIG_APPLE_GMUX=m -CONFIG_ASUS_LAPTOP=m -CONFIG_ASUS_WIRELESS=m -CONFIG_ASUS_WMI=m -CONFIG_ASUS_NB_WMI=m -CONFIG_ASUS_TF103C_DOCK=m -CONFIG_MERAKI_MX100=m -CONFIG_EEEPC_LAPTOP=m -CONFIG_EEEPC_WMI=m -CONFIG_X86_PLATFORM_DRIVERS_DELL=y -CONFIG_DELL_UART_BACKLIGHT=m -CONFIG_DELL_WMI_PRIVACY=y -CONFIG_AMILO_RFKILL=m -CONFIG_FUJITSU_LAPTOP=m -CONFIG_FUJITSU_TABLET=m -CONFIG_GPD_POCKET_FAN=m -CONFIG_X86_PLATFORM_DRIVERS_HP=y -CONFIG_WIRELESS_HOTKEY=m -CONFIG_IBM_RTL=m -CONFIG_SENSORS_HDAPS=m -CONFIG_INTEL_ATOMISP2_LED=m -CONFIG_INTEL_IFS=m -CONFIG_INTEL_SAR_INT1092=m -CONFIG_INTEL_SKL_INT3472=m -CONFIG_INTEL_PMC_CORE=m -CONFIG_INTEL_PMT_TELEMETRY=m -CONFIG_INTEL_PMT_CRASHLOG=m -CONFIG_INTEL_SPEED_SELECT_INTERFACE=m -CONFIG_INTEL_TELEMETRY=m -CONFIG_INTEL_WMI_SBL_FW_UPDATE=m -CONFIG_INTEL_WMI_THUNDERBOLT=m -CONFIG_INTEL_UNCORE_FREQ_CONTROL=m -CONFIG_INTEL_HID_EVENT=m -CONFIG_INTEL_VBTN=m -CONFIG_INTEL_INT0002_VGPIO=m -CONFIG_INTEL_OAKTRAIL=m -CONFIG_INTEL_BXTWC_PMIC_TMU=m -CONFIG_INTEL_BYTCRC_PWRSRC=m -CONFIG_INTEL_CHTDC_TI_PWRBTN=m -CONFIG_INTEL_CHTWC_INT33FE=m -CONFIG_INTEL_ISHTP_ECLITE=m -CONFIG_INTEL_MRFLD_PWRBTN=m -CONFIG_INTEL_PUNIT_IPC=m -CONFIG_INTEL_RST=m -CONFIG_INTEL_SDSI=m -CONFIG_INTEL_SMARTCONNECT=m -CONFIG_INTEL_TPMI=m -CONFIG_INTEL_PLR_TPMI=m -CONFIG_INTEL_VSEC=m -CONFIG_LENOVO_WMI_HOTKEY_UTILITIES=m -CONFIG_LENOVO_WMI_CAMERA=m -CONFIG_LENOVO_YMC=m -CONFIG_THINKPAD_ACPI=m -CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y -CONFIG_THINKPAD_LMI=m -CONFIG_YOGABOOK=m -CONFIG_YT2_1380=m -CONFIG_LENOVO_WMI_GAMEZONE=m -CONFIG_ACPI_QUICKSTART=m -CONFIG_MEEGOPAD_ANX7428=m -CONFIG_MSI_EC=m -CONFIG_MSI_LAPTOP=m -CONFIG_MSI_WMI=m -CONFIG_MSI_WMI_PLATFORM=m +CONFIG_NVMEM=y +# CONFIG_NVMEM_LAYOUTS is not set +CONFIG_NVMEM_RAVE_SP_EEPROM=m +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_SYSFS=y +CONFIG_NVME_AUTH=y +CONFIG_NVME_CORE=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_KEYRING=y +# CONFIG_NVME_MULTIPATH is not set +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_AUTH is not set +CONFIG_NVME_TARGET_DEBUGFS=y +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_LOOP=m +# CONFIG_NVME_TARGET_PASSTHRU is not set +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_TCP_TLS=y +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +CONFIG_NVRAM=m +CONFIG_NV_TCO=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_CBTX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +CONFIG_OA_TC6=m +CONFIG_OBJAGG=m +CONFIG_OBJTOOL=y +# CONFIG_OBJTOOL_WERROR is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_OCFS2_DEBUG_MASKLOG=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCTEONEP_VDPA=m +CONFIG_OCTEON_EP=m +# CONFIG_OCTEON_EP_VF is not set +# CONFIG_OF is not set +CONFIG_OID_REGISTRY=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OMFS_FS=m +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPEN_ALLIANCE_HELPERS=y +CONFIG_OPT3001=m +CONFIG_OPT4001=m +CONFIG_OPT4060=m +CONFIG_OPTPROBES=y +CONFIG_ORANGEFS_FS=m +CONFIG_OSF_PARTITION=y +# CONFIG_OSNOISE_TRACER is not set +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVMF_DEBUG_LOG is not set +CONFIG_OVPN=y +CONFIG_OXP_EC=m +CONFIG_P2SB=y +CONFIG_P54_COMMON=m +CONFIG_P54_LEDS=y +CONFIG_P54_PCI=m +CONFIG_P54_SPI=m +# CONFIG_P54_SPI_DEFAULT_EEPROM is not set +CONFIG_P54_USB=m +CONFIG_PA12203001=m +CONFIG_PAC1921=m +# CONFIG_PAC1934 is not set +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_PAGE_COUNTER=y +CONFIG_PAGE_EXTENSION=y +CONFIG_PAGE_IDLE_FLAG=y +CONFIG_PAGE_MAPCOUNT=y +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_VERSION=131 +CONFIG_PALMAS_GPADC=m +CONFIG_PANASONIC_LAPTOP=m +CONFIG_PANEL=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PANTHERLORD_FF=y +CONFIG_PARAVIRT=y +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_PARAVIRT_DEBUG is not set +CONFIG_PARAVIRT_SPINLOCKS=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_PARAVIRT_XXL=y +CONFIG_PARMAN=m +CONFIG_PARPORT=m +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_PARPORT_PANEL=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_PC_FIFO=y +CONFIG_PARPORT_PC_PCMCIA=m +# CONFIG_PARPORT_PC_SUPERIO is not set +CONFIG_PARPORT_SERIAL=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_PATA_ACPI=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_LEGACY=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PARPORT=m +CONFIG_PATA_PARPORT_ATEN=m +CONFIG_PATA_PARPORT_BPCK=m +CONFIG_PATA_PARPORT_BPCK6=m +CONFIG_PATA_PARPORT_COMM=m +CONFIG_PATA_PARPORT_DSTR=m +CONFIG_PATA_PARPORT_EPAT=m +CONFIG_PATA_PARPORT_EPATC8=y +CONFIG_PATA_PARPORT_EPIA=m +CONFIG_PATA_PARPORT_FIT2=m +CONFIG_PATA_PARPORT_FIT3=m +CONFIG_PATA_PARPORT_FRIQ=m +CONFIG_PATA_PARPORT_FRPW=m +CONFIG_PATA_PARPORT_KBIC=m +CONFIG_PATA_PARPORT_KTTI=m +CONFIG_PATA_PARPORT_ON20=m +CONFIG_PATA_PARPORT_ON26=m +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_RZ1000=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=y +CONFIG_PATA_TIMINGS=y +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +# CONFIG_PC104 is not set +CONFIG_PC300TOO=m +CONFIG_PC87413_WDT=m +CONFIG_PCC=y +CONFIG_PCCARD=m +CONFIG_PCCARD_NONSTATIC=y CONFIG_PCENGINES_APU2=m +CONFIG_PCI=y +CONFIG_PCI200SYN=m +CONFIG_PCIEAER=y +CONFIG_PCIEAER_CXL=y +# CONFIG_PCIEAER_INJECT is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_DPC=y +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +CONFIG_PCIE_THERMAL=y +CONFIG_PCIE_TPH=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_ATS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_DIRECT=y +CONFIG_PCI_DOE=y +CONFIG_PCI_DOMAINS=y +# CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +CONFIG_PCI_LOCKLESS_CONFIG=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MMCONFIG=y +CONFIG_PCI_MSI=y +CONFIG_PCI_NPEM=y +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_PASID=y +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTRL=m +CONFIG_PCI_PWRCTRL_SLOT=m +CONFIG_PCI_QUIRKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +CONFIG_PCI_SW_SWITCHTEC=m +CONFIG_PCI_XEN=y +CONFIG_PCMCIA=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_AXNET=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PCMCIA_PCNET=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SMC91C92=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_PCNET32=m +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PCS_LYNX=m +CONFIG_PCS_MTK_LYNXI=m +CONFIG_PCS_XPCS=m +CONFIG_PD6729=m +CONFIG_PDC_ADMA=m +CONFIG_PDS_CORE=m +CONFIG_PDS_VDPA=m +CONFIG_PDS_VFIO_PCI=m +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_PERCPU_TEST=m +CONFIG_PERF_EVENTS=y +CONFIG_PERF_EVENTS_AMD_BRS=y +CONFIG_PERF_EVENTS_AMD_POWER=m +CONFIG_PERF_EVENTS_AMD_UNCORE=m +CONFIG_PERF_EVENTS_INTEL_CSTATE=y +CONFIG_PERF_EVENTS_INTEL_RAPL=y +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +CONFIG_PFCP=m +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_PHANTOM=m +CONFIG_PHONET=m +CONFIG_PHYLIB=y +CONFIG_PHYLINK=m +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_INTEL_LGM_EMMC=m +CONFIG_PHY_PACKAGE=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_PHY_TUSB1210=m +CONFIG_PID_NS=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ALDERLAKE=m +CONFIG_PINCTRL_AMD=y +CONFIG_PINCTRL_AMDISP=m +CONFIG_PINCTRL_BAYTRAIL=y +CONFIG_PINCTRL_BROXTON=m +CONFIG_PINCTRL_CANNONLAKE=m +CONFIG_PINCTRL_CEDARFORK=m +CONFIG_PINCTRL_CHERRYVIEW=y +# CONFIG_PINCTRL_CS42L43 is not set +CONFIG_PINCTRL_CY8C95X0=m +# CONFIG_PINCTRL_DA9062 is not set +CONFIG_PINCTRL_DENVERTON=m +CONFIG_PINCTRL_ELKHARTLAKE=m +CONFIG_PINCTRL_EMMITSBURG=m +CONFIG_PINCTRL_GEMINILAKE=m +CONFIG_PINCTRL_ICELAKE=m +CONFIG_PINCTRL_INTEL=y +CONFIG_PINCTRL_INTEL_PLATFORM=m +CONFIG_PINCTRL_JASPERLAKE=m +CONFIG_PINCTRL_LAKEFIELD=m +CONFIG_PINCTRL_LEWISBURG=m +CONFIG_PINCTRL_LYNXPOINT=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_METEORLAKE=m +CONFIG_PINCTRL_METEORPOINT=m +CONFIG_PINCTRL_SUNRISEPOINT=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_TIGERLAKE=m +# CONFIG_PINCTRL_UPBOARD is not set +CONFIG_PING=m +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PLATFORM_SI4713=m +CONFIG_PLAYSTATION_FF=y +CONFIG_PLDMFW=y +CONFIG_PLFXLC=m +CONFIG_PLIP=m +CONFIG_PLX_DMA=m +CONFIG_PM=y +CONFIG_PMBUS=m +CONFIG_PMIC_ADP5520=y +CONFIG_PMIC_DA903X=y +CONFIG_PMIC_DA9052=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_PMS7003=m +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_NOTIFIER_ERROR_INJECT=m +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNP=y +CONFIG_PNPACPI=y +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_POLYNOMIAL=m CONFIG_PORTWELL_EC=m -CONFIG_BARCO_P50_GPIO=m -CONFIG_SAMSUNG_GALAXYBOOK=m -CONFIG_SAMSUNG_LAPTOP=m -CONFIG_SAMSUNG_Q10=m -CONFIG_ACPI_TOSHIBA=m -CONFIG_TOSHIBA_BT_RFKILL=m -CONFIG_TOSHIBA_HAPS=m -CONFIG_TOSHIBA_WMI=m -CONFIG_ACPI_CMPC=m -CONFIG_COMPAL_LAPTOP=m -CONFIG_LG_LAPTOP=m -CONFIG_PANASONIC_LAPTOP=m -CONFIG_SONY_LAPTOP=m -CONFIG_SONYPI_COMPAT=y -CONFIG_SYSTEM76_ACPI=m -CONFIG_TOPSTAR_LAPTOP=m -CONFIG_INSPUR_PLATFORM_PROFILE=m -CONFIG_DASHARO_ACPI=m -CONFIG_INTEL_IPS=m -CONFIG_INTEL_SCU_PCI=y -CONFIG_INTEL_SCU_PLATFORM=m -CONFIG_INTEL_SCU_IPC_UTIL=m -CONFIG_SIEMENS_SIMATIC_IPC=m -CONFIG_SILICOM_PLATFORM=m -CONFIG_WINMATE_FM07_KEYS=m -CONFIG_SEL3350_PLATFORM=m -CONFIG_OXP_EC=m -CONFIG_TUXEDO_NB04_WMI_AB=m -CONFIG_COMMON_CLK_WM831X=m -CONFIG_LMK04832=m -CONFIG_COMMON_CLK_MAX9485=m -CONFIG_COMMON_CLK_SI5341=m -CONFIG_COMMON_CLK_SI5351=m -CONFIG_COMMON_CLK_SI544=m -CONFIG_COMMON_CLK_CDCE706=m -CONFIG_COMMON_CLK_TPS68470=m -CONFIG_COMMON_CLK_CS2000_CP=m -CONFIG_CLK_TWL=m -CONFIG_CLK_TWL6040=m -CONFIG_COMMON_CLK_PALMAS=m -CONFIG_COMMON_CLK_PWM=m -CONFIG_XILINX_VCU=m -CONFIG_ALTERA_MBOX=m -CONFIG_AMD_IOMMU=y -CONFIG_INTEL_IOMMU=y -CONFIG_INTEL_IOMMU_SVM=y -# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set -# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set -# CONFIG_INTEL_IOMMU_PERF_EVENTS is not set -CONFIG_IRQ_REMAP=y -CONFIG_VIRTIO_IOMMU=m -CONFIG_RPMSG_QCOM_GLINK_RPM=m -CONFIG_RPMSG_VIRTIO=m -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_AMD=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_WPCM450_SOC=m +# CONFIG_POSIX_AUX_CLOCKS is not set +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POSIX_TIMERS=y +CONFIG_POWERCAP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +# CONFIG_POWER_RESET_MT6323 is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_TPS65086=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPDEV=m +CONFIG_PPP=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOE_HASH_BITS=4 +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS=m +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +# CONFIG_PPS_DEBUG is not set +CONFIG_PPS_GENERATOR=m +# CONFIG_PPS_GENERATOR_DUMMY is not set +CONFIG_PPS_GENERATOR_TIO=m +CONFIG_PPTP=m +# CONFIG_PREEMPT is not set +CONFIG_PREEMPTION=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPT_LAZY is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +# CONFIG_PREEMPT_RT is not set +# CONFIG_PREEMPT_TRACER is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREFIX_SYMBOLS=y +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRIME_NUMBERS=m +CONFIG_PRINTER=m +CONFIG_PRINTK=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_PRINTK_INDEX is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_THERMAL_MMIO_RAPL=m +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +CONFIG_PSAMPLE=m +CONFIG_PSE_CONTROLLER=y +CONFIG_PSE_PD692X0=m +CONFIG_PSE_REGULATOR=m +# CONFIG_PSE_SI3474 is not set +CONFIG_PSE_TPS23881=m +CONFIG_PSI=y +# CONFIG_PSI_DEFAULT_DISABLED is not set +CONFIG_PSTORE=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTE_MARKER_UFFD_WP=y +CONFIG_PTP_1588_CLOCK=m +# CONFIG_PTP_1588_CLOCK_FC3W is not set +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_KVM=m +# CONFIG_PTP_1588_CLOCK_MOCK is not set +CONFIG_PTP_1588_CLOCK_OCP=m +CONFIG_PTP_1588_CLOCK_OPTIONAL=m +CONFIG_PTP_1588_CLOCK_VMCLOCK=m +# CONFIG_PTP_1588_CLOCK_VMW is not set +CONFIG_PTP_DFL_TOD=m +# CONFIG_PTP_NETC_V4_TIMER is not set +CONFIG_PT_RECLAIM=y +CONFIG_PUNIT_ATOM_DEBUG=m +CONFIG_PVH=y +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_PWM=y +CONFIG_PWM_CLK=m +CONFIG_PWM_CRC=y +CONFIG_PWM_CROS_EC=m +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_DWC=m +CONFIG_PWM_DWC_CORE=m +CONFIG_PWM_GPIO=m +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_LPSS=m +CONFIG_PWM_LPSS_PCI=m +CONFIG_PWM_LPSS_PLATFORM=m +CONFIG_PWM_PCA9685=m +# CONFIG_PWM_PROVIDE_GPIO is not set +CONFIG_PWM_TWL=m +CONFIG_PWM_TWL_LED=m +CONFIG_QAT_VFIO_PCI=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m +CONFIG_QCOM_EMAC=m +CONFIG_QCOM_HIDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_NET_PHYLIB=m +# CONFIG_QCOM_PBS is not set CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m -CONFIG_SOC_TI=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -CONFIG_DEVFREQ_GOV_PASSIVE=m -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_EXTCON_ADC_JACK=m -CONFIG_EXTCON_AXP288=m -CONFIG_EXTCON_FSA9480=m -CONFIG_EXTCON_GPIO=m -CONFIG_EXTCON_INTEL_INT3496=m -CONFIG_EXTCON_INTEL_CHT_WC=m -CONFIG_EXTCON_INTEL_MRFLD=m -CONFIG_EXTCON_LC824206XA=m -CONFIG_EXTCON_MAX14577=m -CONFIG_EXTCON_MAX3355=m -CONFIG_EXTCON_MAX77693=m -CONFIG_EXTCON_MAX77843=m -CONFIG_EXTCON_MAX8997=m -CONFIG_EXTCON_PALMAS=m -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_RT8973A=m -CONFIG_EXTCON_SM5502=m -CONFIG_EXTCON_USB_GPIO=m -CONFIG_EXTCON_USBC_CROS_EC=m -CONFIG_EXTCON_USBC_TUSB320=m -CONFIG_MEMORY=y -CONFIG_FPGA_DFL_EMIF=m -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_ADIS16201=m -CONFIG_ADIS16209=m -CONFIG_ADXL313_I2C=m -CONFIG_ADXL313_SPI=m -CONFIG_ADXL355_I2C=m -CONFIG_ADXL355_SPI=m -CONFIG_ADXL367_SPI=m -CONFIG_ADXL367_I2C=m -CONFIG_ADXL372_SPI=m -CONFIG_ADXL372_I2C=m -CONFIG_ADXL380_SPI=m -CONFIG_ADXL380_I2C=m -CONFIG_BMA220=m -CONFIG_BMA400=m -CONFIG_BMC150_ACCEL=m -CONFIG_BMI088_ACCEL=m -CONFIG_DA280=m -CONFIG_DA311=m -CONFIG_DMARD06=m -CONFIG_DMARD09=m -CONFIG_DMARD10=m -CONFIG_FXLS8962AF_I2C=m -CONFIG_FXLS8962AF_SPI=m -CONFIG_HID_SENSOR_ACCEL_3D=m -CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m -CONFIG_IIO_KX022A_SPI=m -CONFIG_IIO_KX022A_I2C=m -CONFIG_KXSD9=m -CONFIG_KXCJK1013=m -CONFIG_MC3230=m -CONFIG_MMA7455_I2C=m -CONFIG_MMA7455_SPI=m -CONFIG_MMA7660=m -CONFIG_MMA8452=m -CONFIG_MMA9551=m -CONFIG_MMA9553=m -CONFIG_MSA311=m -CONFIG_MXC4005=m -CONFIG_MXC6255=m -CONFIG_SCA3000=m -CONFIG_SCA3300=m -CONFIG_STK8312=m -CONFIG_STK8BA50=m -CONFIG_AD4000=m -CONFIG_AD4030=m -CONFIG_AD4080=m -CONFIG_AD4130=m -CONFIG_AD4170_4=m -CONFIG_AD4695=m -CONFIG_AD4851=m -CONFIG_AD7091R5=m -CONFIG_AD7091R8=m -CONFIG_AD7124=m -CONFIG_AD7173=m -CONFIG_AD7191=m -CONFIG_AD7192=m -CONFIG_AD7266=m -CONFIG_AD7280=m -CONFIG_AD7291=m -CONFIG_AD7292=m -CONFIG_AD7298=m -CONFIG_AD7380=m -CONFIG_AD7405=m -CONFIG_AD7476=m -CONFIG_AD7606_IFACE_PARALLEL=m -CONFIG_AD7606_IFACE_SPI=m -CONFIG_AD7625=m -CONFIG_AD7766=m -CONFIG_AD7768_1=m -CONFIG_AD7779=m -CONFIG_AD7780=m -CONFIG_AD7791=m -CONFIG_AD7793=m -CONFIG_AD7887=m -CONFIG_AD7923=m -CONFIG_AD7944=m -CONFIG_AD7949=m -CONFIG_AD799X=m -CONFIG_AXP20X_ADC=m -CONFIG_AXP288_ADC=m -CONFIG_CC10001_ADC=m -CONFIG_DA9150_GPADC=m -CONFIG_DLN2_ADC=m -CONFIG_ENVELOPE_DETECTOR=m -CONFIG_GEHC_PMC_ADC=m -CONFIG_HI8435=m -CONFIG_HX711=m -CONFIG_INA2XX_ADC=m -CONFIG_INTEL_MRFLD_ADC=m -CONFIG_LP8788_ADC=m -CONFIG_LTC2309=m -CONFIG_LTC2471=m -CONFIG_LTC2485=m -CONFIG_LTC2496=m -CONFIG_LTC2497=m -CONFIG_MAX1027=m -CONFIG_MAX11100=m -CONFIG_MAX1118=m -CONFIG_MAX11205=m -CONFIG_MAX11410=m -CONFIG_MAX1241=m -CONFIG_MAX1363=m -CONFIG_MAX34408=m -CONFIG_MAX77541_ADC=m -CONFIG_MAX9611=m -CONFIG_MCP320X=m -CONFIG_MCP3422=m -CONFIG_MCP3564=m -CONFIG_MCP3911=m -CONFIG_MEDIATEK_MT6359_AUXADC=m -CONFIG_MEDIATEK_MT6370_ADC=m -CONFIG_MEN_Z188_ADC=m -CONFIG_MP2629_ADC=m -CONFIG_NAU7802=m -CONFIG_NCT7201=m -CONFIG_PAC1921=m -CONFIG_PALMAS_GPADC=m +CONFIG_QCOM_QMI_HELPERS=m +CONFIG_QCOM_SPMI_ADC5=m CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROHM_BD79124=m +CONFIG_QCOM_VADC_COMMON=m +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED_FCOE=y +CONFIG_QED_ISCSI=y +CONFIG_QED_LL2=y +CONFIG_QED_OOO=y +CONFIG_QED_RDMA=y +CONFIG_QED_SRIOV=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_QLCNIC_SRIOV=y +CONFIG_QNX4FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_QNX6FS_FS=m +CONFIG_QRTR=m +CONFIG_QRTR_MHI=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QSEMI_PHY=m +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=m +CONFIG_R6040=m +CONFIG_R8169=m +CONFIG_R8169_LEDS=y +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI470X=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_SI476X=m +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_CPS_XX=m +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAS=y +# CONFIG_RAS_CEC is not set +CONFIG_RAS_FMPM=m +CONFIG_RATIONAL=y +CONFIG_RAVE_SP_CORE=m +CONFIG_RAVE_SP_WATCHDOG=m +# CONFIG_RBTREE_TEST is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_RC_LOOPBACK=m +CONFIG_RC_MAP=m +CONFIG_RC_XBOX_DVD=m +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_RDS=m +# CONFIG_RDS_DEBUG is not set +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=m +CONFIG_REALTEK_PHY_HWMON=y +# CONFIG_REDMI_WMI is not set +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +# CONFIG_REED_SOLOMON_TEST is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SCCB=m +CONFIG_REGMAP_SOUNDWIRE=m +CONFIG_REGMAP_SOUNDWIRE_MBQ=m +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_88PG86X=m +CONFIG_REGULATOR_88PM800=m +CONFIG_REGULATOR_88PM8607=m +CONFIG_REGULATOR_AAT2870=m +CONFIG_REGULATOR_ACT8865=m +CONFIG_REGULATOR_AD5398=m +CONFIG_REGULATOR_ADP5055=m +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_AS3711=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AW37503=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BCM590XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_DA903X=m +CONFIG_REGULATOR_DA9052=m +CONFIG_REGULATOR_DA9055=m +CONFIG_REGULATOR_DA9062=m +CONFIG_REGULATOR_DA9210=m +CONFIG_REGULATOR_DA9211=m +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FIXED_VOLTAGE=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_ISL6271A=m +CONFIG_REGULATOR_ISL9305=m +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LP3971=m +CONFIG_REGULATOR_LP3972=m +CONFIG_REGULATOR_LP872X=m +CONFIG_REGULATOR_LP8755=m +CONFIG_REGULATOR_LP8788=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +CONFIG_REGULATOR_MAX14577=m +CONFIG_REGULATOR_MAX1586=m +CONFIG_REGULATOR_MAX20086=m +CONFIG_REGULATOR_MAX20411=m +CONFIG_REGULATOR_MAX77503=m +CONFIG_REGULATOR_MAX77541=m +CONFIG_REGULATOR_MAX77693=m +CONFIG_REGULATOR_MAX77826=m +# CONFIG_REGULATOR_MAX77838 is not set +CONFIG_REGULATOR_MAX77857=m +CONFIG_REGULATOR_MAX8649=m +CONFIG_REGULATOR_MAX8660=m +CONFIG_REGULATOR_MAX8893=m +CONFIG_REGULATOR_MAX8907=m +CONFIG_REGULATOR_MAX8925=m +CONFIG_REGULATOR_MAX8952=m +CONFIG_REGULATOR_MAX8997=m +CONFIG_REGULATOR_MAX8998=m +CONFIG_REGULATOR_MC13783=m +CONFIG_REGULATOR_MC13892=m +CONFIG_REGULATOR_MC13XXX_CORE=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MT6311=m +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6323=m +CONFIG_REGULATOR_MT6331=m +CONFIG_REGULATOR_MT6332=m +CONFIG_REGULATOR_MT6357=m +CONFIG_REGULATOR_MT6358=m +CONFIG_REGULATOR_MT6359=m +CONFIG_REGULATOR_MT6360=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_MT6397=m +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +CONFIG_REGULATOR_PALMAS=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PCAP=m +# CONFIG_REGULATOR_PF0900 is not set +CONFIG_REGULATOR_PF9453=m +CONFIG_REGULATOR_PV88060=m +CONFIG_REGULATOR_PV88080=m +CONFIG_REGULATOR_PV88090=m +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RAA215300=m +CONFIG_REGULATOR_RC5T583=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5033=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTQ2208=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_TPS51632=m +CONFIG_REGULATOR_TPS6105X=m +CONFIG_REGULATOR_TPS62360=m +CONFIG_REGULATOR_TPS65023=m +CONFIG_REGULATOR_TPS6507X=m +CONFIG_REGULATOR_TPS65086=m +CONFIG_REGULATOR_TPS65090=m +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS6524X=m +CONFIG_REGULATOR_TPS6586X=m +CONFIG_REGULATOR_TPS65910=m +CONFIG_REGULATOR_TPS65912=m +CONFIG_REGULATOR_TPS68470=m +CONFIG_REGULATOR_TWL4030=m +CONFIG_REGULATOR_USERSPACE_CONSUMER=m +CONFIG_REGULATOR_VIRTUAL_CONSUMER=m +CONFIG_REGULATOR_WM831X=m +CONFIG_REGULATOR_WM8350=m +CONFIG_REGULATOR_WM8400=m +CONFIG_REGULATOR_WM8994=m +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC is not set +CONFIG_REMOTE_TARGET=m +CONFIG_RENESAS_PHY=m +CONFIG_RESET_ATTACK_MITIGATION=y +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_RETHOOK=y +CONFIG_RETU_WATCHDOG=m +CONFIG_RFD77402=m +CONFIG_RFD_FTL=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFS_ACCEL=y CONFIG_RICHTEK_RTQ6056=m -CONFIG_SD_ADC_MODULATOR=m -CONFIG_TI_ADC081C=m -CONFIG_TI_ADC0832=m -CONFIG_TI_ADC084S021=m -CONFIG_TI_ADC108S102=m -CONFIG_TI_ADC12138=m -CONFIG_TI_ADC128S052=m -CONFIG_TI_ADC161S626=m -CONFIG_TI_ADS1015=m -CONFIG_TI_ADS1100=m -CONFIG_TI_ADS1119=m -CONFIG_TI_ADS124S08=m -CONFIG_TI_ADS131E08=m -CONFIG_TI_ADS7138=m -CONFIG_TI_ADS7924=m -CONFIG_TI_ADS7950=m -CONFIG_TI_ADS8344=m -CONFIG_TI_ADS8688=m -CONFIG_TI_LMP92064=m -CONFIG_TI_TLC4541=m -CONFIG_TI_TSC2046=m -CONFIG_TWL4030_MADC=m -CONFIG_TWL6030_GPADC=m -CONFIG_VF610_ADC=m -CONFIG_VIPERBOARD_ADC=m -CONFIG_XILINX_XADC=m -CONFIG_AD74115=m -CONFIG_AD74413R=m -CONFIG_IIO_RESCALE=m -CONFIG_AD8366=m -CONFIG_ADA4250=m -CONFIG_HMC425=m -CONFIG_AD7150=m -CONFIG_AD7746=m -CONFIG_AOSONG_AGS02MA=m -CONFIG_ATLAS_PH_SENSOR=m -CONFIG_ATLAS_EZO_SENSOR=m -CONFIG_BME680=m -CONFIG_CCS811=m -CONFIG_ENS160=m -CONFIG_IAQCORE=m -CONFIG_MHZ19B=m -CONFIG_PMS7003=m +CONFIG_RING_BUFFER=y +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RIONET=m +CONFIG_RIONET_RX_SIZE=128 +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F1A=y +CONFIG_RMI4_F21=y +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +CONFIG_RMI4_F55=y +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +CONFIG_RMNET=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_ROCKER=m +# CONFIG_ROHM_BD79112 is not set +CONFIG_ROHM_BD79124=m +CONFIG_ROHM_BM1390=m +CONFIG_ROHM_BU27034=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROSE=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +CONFIG_RPMB=m +CONFIG_RPMSG=m +# CONFIG_RPMSG_CHAR is not set +# CONFIG_RPMSG_CTRL is not set +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_TTY=m +CONFIG_RPMSG_VIRTIO=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_RPR0521=m +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RSI_91X=m +CONFIG_RSI_COEX=y +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT2500USB=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_CRYPTO=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT61PCI=m +CONFIG_RT73USB=m +CONFIG_RTASE=m +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_DRV_88PM80X=m +CONFIG_RTC_DRV_88PM860X=m +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_CROS_EC=m +CONFIG_RTC_DRV_DA9052=m +CONFIG_RTC_DRV_DA9055=m +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685=y +CONFIG_RTC_DRV_DS1685_FAMILY=m +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_GOLDFISH=m +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_LP8788=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_M48T86=m +CONFIG_RTC_DRV_MAX31335=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_MAX8907=m +CONFIG_RTC_DRV_MAX8925=m +CONFIG_RTC_DRV_MAX8997=m +CONFIG_RTC_DRV_MAX8998=m +CONFIG_RTC_DRV_MC13XXX=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_MT6397=m +CONFIG_RTC_DRV_PALMAS=m +CONFIG_RTC_DRV_PCAP=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RC5T583=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RV3029_HWMON=y +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RX6110=m +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_RX8111=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_SD2405AL=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_TPS6586X=m +CONFIG_RTC_DRV_TPS65910=m +CONFIG_RTC_DRV_TPS6594=m +CONFIG_RTC_DRV_WILCO_EC=m +CONFIG_RTC_DRV_WM831X=m +CONFIG_RTC_DRV_WM8350=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_NVMEM=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192D_COMMON=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723BS=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTLBTCOEXIST=m +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTL_CARDS=m +CONFIG_RTW88=m +CONFIG_RTW88_8703B=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8723X=m +CONFIG_RTW88_8812A=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_8814A=m +CONFIG_RTW88_8814AE=m +CONFIG_RTW88_8814AU=m +CONFIG_RTW88_8821A=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_88XXA=m +CONFIG_RTW88_CORE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW88_LEDS=y +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW89=m +CONFIG_RTW89_8851B=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BT=m +CONFIG_RTW89_8852BTE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852B_COMMON=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922A=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_CORE=m +# CONFIG_RTW89_DEBUGFS is not set +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89_PCI=m +CONFIG_RTW89_USB=m +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_RT_MUTEXES=y +CONFIG_RUNTIME_TESTING_MENU=y +CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_FILE_AS_C_STR=y +CONFIG_RUSTC_HAS_FILE_WITH_NUL=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y +CONFIG_RUSTC_LLVM_VERSION=210108 +CONFIG_RUSTC_VERSION=109500 +CONFIG_RUST_IS_AVAILABLE=y +# CONFIG_RV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RXGK=y +# CONFIG_RXKAD is not set +# CONFIG_RXPERF is not set +CONFIG_S2IO=m +# CONFIG_SAMPLES is not set +CONFIG_SAMSUNG_GALAXYBOOK=m +CONFIG_SAMSUNG_LAPTOP=m +CONFIG_SAMSUNG_Q10=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_SATA_DWC=m +# CONFIG_SATA_DWC_OLD_DMA is not set +CONFIG_SATA_HOST=y +CONFIG_SATA_INIC162X=m +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PMP=y +CONFIG_SATA_PROMISE=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_SX4=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_SATA_ZPODD=y +CONFIG_SBC_EPX_C3_WATCHDOG=m +CONFIG_SBC_FITPC2_WATCHDOG=m +CONFIG_SBITMAP=y +CONFIG_SBP_TARGET=m +CONFIG_SC1200_WDT=m +CONFIG_SC92031=m +CONFIG_SCA3000=m +CONFIG_SCA3300=m CONFIG_SCD30_CORE=m CONFIG_SCD30_I2C=m CONFIG_SCD30_SERIAL=m CONFIG_SCD4X=m -CONFIG_SEN0322=m -CONFIG_SENSIRION_SGP30=m -CONFIG_SENSIRION_SGP40=m -CONFIG_SPS30_I2C=m -CONFIG_SPS30_SERIAL=m -CONFIG_SENSEAIR_SUNRISE_CO2=m -CONFIG_VZ89X=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m -CONFIG_IIO_CROS_EC_ACTIVITY=m -CONFIG_IIO_SSP_SENSORS_COMMONS=m -CONFIG_IIO_SSP_SENSORHUB=m -CONFIG_AD3530R=m -CONFIG_AD3552R_HS=m -CONFIG_AD3552R=m -CONFIG_AD5064=m -CONFIG_AD5360=m -CONFIG_AD5380=m -CONFIG_AD5421=m -CONFIG_AD5446=m -CONFIG_AD5449=m -CONFIG_AD5592R=m -CONFIG_AD5593R=m -CONFIG_AD5504=m -CONFIG_AD5624R_SPI=m -CONFIG_AD9739A=m -CONFIG_LTC2688=m -CONFIG_AD5686_SPI=m -CONFIG_AD5696_I2C=m -CONFIG_AD5755=m -CONFIG_AD5758=m -CONFIG_AD5761=m -CONFIG_AD5764=m -CONFIG_AD5766=m -CONFIG_AD5770R=m -CONFIG_AD5791=m -CONFIG_AD7293=m -CONFIG_AD7303=m -CONFIG_AD8460=m -CONFIG_AD8801=m -CONFIG_BD79703=m -CONFIG_DPOT_DAC=m -CONFIG_DS4424=m -CONFIG_LTC1660=m -CONFIG_LTC2632=m -CONFIG_LTC2664=m -CONFIG_M62332=m -CONFIG_MAX517=m -CONFIG_MAX5522=m -CONFIG_MAX5821=m -CONFIG_MCP4725=m -CONFIG_MCP4728=m -CONFIG_MCP4821=m -CONFIG_MCP4922=m -CONFIG_TI_DAC082S085=m -CONFIG_TI_DAC5571=m -CONFIG_TI_DAC7311=m -CONFIG_TI_DAC7612=m -CONFIG_VF610_DAC=m -CONFIG_IIO_SIMPLE_DUMMY=m -CONFIG_ADMV8818=m -CONFIG_AD9523=m -CONFIG_ADF4350=m -CONFIG_ADF4371=m -CONFIG_ADF4377=m -CONFIG_ADMV1013=m -CONFIG_ADMV1014=m -CONFIG_ADMV4420=m -CONFIG_ADRF6780=m -CONFIG_ADIS16080=m -CONFIG_ADIS16130=m -CONFIG_ADIS16136=m -CONFIG_ADIS16260=m -CONFIG_ADXRS290=m -CONFIG_ADXRS450=m -CONFIG_BMG160=m -CONFIG_FXAS21002C=m -CONFIG_HID_SENSOR_GYRO_3D=m -CONFIG_MPU3050_I2C=m -CONFIG_IIO_ST_GYRO_3AXIS=m -CONFIG_ITG3200=m -CONFIG_AFE4403=m -CONFIG_AFE4404=m -CONFIG_MAX30100=m -CONFIG_MAX30102=m -CONFIG_AM2315=m -CONFIG_DHT11=m -CONFIG_ENS210=m -CONFIG_HDC100X=m -CONFIG_HDC2010=m -CONFIG_HDC3020=m -CONFIG_HID_SENSOR_HUMIDITY=m -CONFIG_HTS221=m -CONFIG_HTU21=m -CONFIG_SI7005=m -CONFIG_SI7020=m -CONFIG_ADIS16400=m -CONFIG_ADIS16460=m -CONFIG_ADIS16475=m -CONFIG_ADIS16480=m -CONFIG_ADIS16550=m -CONFIG_BMI160_I2C=m -CONFIG_BMI160_SPI=m -CONFIG_BMI270_I2C=m -CONFIG_BMI270_SPI=m -CONFIG_BMI323_I2C=m -CONFIG_BMI323_SPI=m -CONFIG_BOSCH_BNO055_SERIAL=m -CONFIG_BOSCH_BNO055_I2C=m -CONFIG_FXOS8700_I2C=m -CONFIG_FXOS8700_SPI=m -CONFIG_KMX61=m -CONFIG_INV_ICM42600_I2C=m -CONFIG_INV_ICM42600_SPI=m -CONFIG_INV_MPU6050_I2C=m -CONFIG_INV_MPU6050_SPI=m -CONFIG_SMI240=m -CONFIG_IIO_ST_LSM6DSX=m -CONFIG_IIO_ST_LSM9DS0=m -CONFIG_ACPI_ALS=m -CONFIG_ADJD_S311=m -CONFIG_ADUX1020=m -CONFIG_AL3000A=m -CONFIG_AL3010=m -CONFIG_AL3320A=m -CONFIG_APDS9160=m -CONFIG_APDS9300=m -CONFIG_APDS9306=m -CONFIG_APDS9960=m -CONFIG_AS73211=m -CONFIG_BH1745=m -CONFIG_BH1750=m -CONFIG_BH1780=m -CONFIG_CM32181=m -CONFIG_CM3232=m -CONFIG_CM3323=m -CONFIG_CM3605=m -CONFIG_CM36651=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_GP2AP002=m -CONFIG_GP2AP020A00F=m -CONFIG_IQS621_ALS=m +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CLASS_EXT is not set +CONFIG_SCHED_CLUSTER=y +CONFIG_SCHED_CORE=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_SCHED_MM_CID=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCHED_PROXY_EXEC is not set +CONFIG_SCHED_SMT=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_SCHED_TRACER=y +CONFIG_SCREEN_INFO=y +CONFIG_SCSI=y +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_AIC79XX=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_SCSI_AIC94XX=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DMA=y +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_ESAS2R=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_FLASHPOINT=y +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_IMM=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPS=m +CONFIG_SCSI_ISCI=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_IZIP_SLOW_CTR is not set +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_MOD=y +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +# CONFIG_SCSI_MVSAS_TASKLET is not set +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PPA=m +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PCI=m +CONFIG_SCSI_UFSHCD_PLATFORM=m +# CONFIG_SCSI_UFS_BSG is not set +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +CONFIG_SCSI_UFS_CRYPTO=y +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_WD719X=m +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y +CONFIG_SDIO_UART=m +# CONFIG_SDMA_VERBOSITY is not set +CONFIG_SDP500=m +CONFIG_SDR_MAX2175=m +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_SD_ADC_MODULATOR=m +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +CONFIG_SECURITY_DMESG_RESTRICT=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_IPE is not set +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DEBUG=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SMACK=y +# CONFIG_SECURITY_SMACK_APPEND_SIGNALS is not set +# CONFIG_SECURITY_SMACK_BRINGUP is not set +CONFIG_SECURITY_SMACK_NETFILTER=y +CONFIG_SECURITY_TOMOYO=y +CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init" +# CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set +CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048 +CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024 +# CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER is not set +CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init" +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +CONFIG_SEL3350_PLATFORM=m +CONFIG_SEN0322=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SENSIRION_SGP40=m +CONFIG_SENSORS_ABITUGURU=m +CONFIG_SENSORS_ABITUGURU3=m +CONFIG_SENSORS_ACBEL_FSG032=m +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADP1050=m +# CONFIG_SENSORS_ADP1050_REGULATOR is not set +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ADT7X10=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +CONFIG_SENSORS_APPLESMC=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASB100=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ASUS_EC=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set +CONFIG_SENSORS_ASUS_WMI=m +CONFIG_SENSORS_ATK0110=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_CGBC=m +# CONFIG_SENSORS_CHIPCAP2 is not set +CONFIG_SENSORS_CORETEMP=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m +CONFIG_SENSORS_CRPS=m +CONFIG_SENSORS_DA9052_ADC=m +CONFIG_SENSORS_DA9055=m +CONFIG_SENSORS_DELL_SMM=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_DRIVETEMP=y +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FAM15H_POWER=m +CONFIG_SENSORS_FSCHMD=m +CONFIG_SENSORS_FSP_3Y=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GIGABYTE_WATERFORCE=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPD is not set +CONFIG_SENSORS_HDAPS=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_HMC5843=m +CONFIG_SENSORS_HMC5843_I2C=m +CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_SENSORS_HP_WMI=m +CONFIG_SENSORS_HS3001=m +CONFIG_SENSORS_HTU31=m +CONFIG_SENSORS_I5500=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IBM_CFFPS=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA233=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +CONFIG_SENSORS_IR38064_REGULATOR=y +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL28022=m CONFIG_SENSORS_ISL29018=m CONFIG_SENSORS_ISL29028=m -CONFIG_ISL29125=m -CONFIG_ISL76682=m -CONFIG_HID_SENSOR_ALS=m -CONFIG_HID_SENSOR_PROX=m -CONFIG_JSA1212=m -CONFIG_ROHM_BU27034=m -CONFIG_RPR0521=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_SENSORS_K8TEMP=m +CONFIG_SENSORS_KBATT=m +CONFIG_SENSORS_KFAN=m +CONFIG_SENSORS_LENOVO_EC=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y CONFIG_SENSORS_LM3533=m -CONFIG_LTR390=m -CONFIG_LTR501=m -CONFIG_LTRF216A=m -CONFIG_LV0104CS=m -CONFIG_MAX44000=m -CONFIG_MAX44009=m -CONFIG_NOA1305=m -CONFIG_OPT3001=m -CONFIG_OPT4001=m -CONFIG_OPT4060=m -CONFIG_PA12203001=m -CONFIG_SI1133=m -CONFIG_SI1145=m -CONFIG_STK3310=m -CONFIG_ST_UVIS25=m -CONFIG_TCS3414=m -CONFIG_TCS3472=m -CONFIG_SENSORS_TSL2563=m -CONFIG_TSL2583=m -CONFIG_TSL2591=m -CONFIG_TSL2772=m -CONFIG_TSL4531=m -CONFIG_US5182D=m -CONFIG_VCNL4000=m -CONFIG_VCNL4035=m -CONFIG_VEML3235=m -CONFIG_VEML6030=m -CONFIG_VEML6040=m -CONFIG_VEML6070=m -CONFIG_VEML6075=m -CONFIG_VL6180=m -CONFIG_ZOPT2201=m -CONFIG_AK8974=m -CONFIG_AK09911=m -CONFIG_ALS31300=m -CONFIG_BMC150_MAGN_I2C=m -CONFIG_BMC150_MAGN_SPI=m -CONFIG_MAG3110=m -CONFIG_HID_SENSOR_MAGNETOMETER_3D=m -CONFIG_MMC35240=m -CONFIG_SENSORS_HMC5843_I2C=m -CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_LT3074=m +CONFIG_SENSORS_LT3074_REGULATOR=m +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC2978_REGULATOR=y +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2991=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +CONFIG_SENSORS_LTC4286=y +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX77705=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MC13783_ADC=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_MENF21BMC_HWMON=m +CONFIG_SENSORS_MP2856=m +# CONFIG_SENSORS_MP2869 is not set +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +# CONFIG_SENSORS_MP29502 is not set +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m +CONFIG_SENSORS_MP5990=m +CONFIG_SENSORS_MP9941=m +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +# CONFIG_SENSORS_MPQ8785 is not set +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT6775_CORE=m +CONFIG_SENSORS_NCT6775_I2C=m +CONFIG_SENSORS_NCT7363=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_OCC=m +CONFIG_SENSORS_OCC_P8_I2C=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_POWERZ=m +CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PT5161L is not set +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_QNAP_MCU_HWMON=m +CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m CONFIG_SENSORS_RM3100_SPI=m -CONFIG_SI7210=m -CONFIG_YAMAHA_YAS530=m -CONFIG_IIO_MUX=m -CONFIG_HID_SENSOR_INCLINOMETER_3D=m -CONFIG_HID_SENSOR_DEVICE_ROTATION=m -CONFIG_IIO_HRTIMER_TRIGGER=m -CONFIG_IIO_INTERRUPT_TRIGGER=m -CONFIG_IIO_TIGHTLOOP_TRIGGER=m -CONFIG_IIO_SYSFS_TRIGGER=m -CONFIG_IQS624_POS=m -CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m -CONFIG_AD5110=m -CONFIG_AD5272=m -CONFIG_DS1803=m -CONFIG_MAX5432=m -CONFIG_MAX5481=m -CONFIG_MAX5487=m -CONFIG_MCP4018=m -CONFIG_MCP4131=m -CONFIG_MCP4531=m -CONFIG_MCP41010=m -CONFIG_TPL0102=m -CONFIG_X9250=m -CONFIG_LMP91000=m -CONFIG_ABP060MG=m -CONFIG_ROHM_BM1390=m -CONFIG_BMP280=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_DLHL60D=m -CONFIG_DPS310=m -CONFIG_HID_SENSOR_PRESS=m -CONFIG_HP03=m -CONFIG_HSC030PA=m -CONFIG_ICP10100=m -CONFIG_MPL115_I2C=m -CONFIG_MPL115_SPI=m -CONFIG_MPL3115=m -CONFIG_MPRLS0025PA=m -CONFIG_MS5611=m -CONFIG_MS5611_I2C=m -CONFIG_MS5611_SPI=m -CONFIG_MS5637=m -CONFIG_SDP500=m -CONFIG_IIO_ST_PRESS=m -CONFIG_T5403=m -CONFIG_HP206C=m -CONFIG_ZPA2326=m -CONFIG_AS3935=m -CONFIG_CROS_EC_MKBP_PROXIMITY=m -CONFIG_D3323AA=m -CONFIG_HX9023S=m -CONFIG_IRSD200=m -CONFIG_ISL29501=m -CONFIG_LIDAR_LITE_V2=m -CONFIG_MB1232=m -CONFIG_PING=m -CONFIG_RFD77402=m -CONFIG_SRF04=m -CONFIG_SX9310=m -CONFIG_SX9324=m -CONFIG_SX9360=m -CONFIG_SX9500=m -CONFIG_SRF08=m -CONFIG_VCNL3020=m -CONFIG_VL53L0X_I2C=m -CONFIG_AW96103=m -CONFIG_AD2S90=m -CONFIG_AD2S1200=m -CONFIG_AD2S1210=m -CONFIG_IQS620AT_TEMP=m -CONFIG_LTC2983=m -CONFIG_MAXIM_THERMOCOUPLE=m -CONFIG_HID_SENSOR_TEMP=m -CONFIG_MLX90614=m -CONFIG_MLX90632=m -CONFIG_MLX90635=m -CONFIG_TMP006=m -CONFIG_TMP007=m -CONFIG_TMP117=m -CONFIG_TSYS01=m -CONFIG_TSYS02D=m -CONFIG_MAX30208=m -CONFIG_MAX31856=m -CONFIG_MAX31865=m -CONFIG_MCP9600=m -CONFIG_NTB=m -CONFIG_NTB_MSI=y -CONFIG_NTB_AMD=m -CONFIG_NTB_IDT=m -CONFIG_NTB_INTEL=m -CONFIG_NTB_EPF=m -CONFIG_NTB_SWITCHTEC=m -CONFIG_NTB_PINGPONG=m -CONFIG_NTB_TOOL=m -CONFIG_NTB_PERF=m -CONFIG_NTB_MSI_TEST=m -CONFIG_NTB_TRANSPORT=m -CONFIG_PWM=y -CONFIG_PWM_CLK=m -CONFIG_PWM_CRC=y -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_DWC=m -CONFIG_PWM_GPIO=m -CONFIG_PWM_IQS620A=m -CONFIG_PWM_LP3943=m -CONFIG_PWM_LPSS_PCI=m -CONFIG_PWM_LPSS_PLATFORM=m -CONFIG_PWM_PCA9685=m -CONFIG_PWM_TWL=m -CONFIG_PWM_TWL_LED=m -CONFIG_IPACK_BUS=m -CONFIG_BOARD_TPCI200=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMPRO=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SPD5118=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_STTS751=m +# CONFIG_SENSORS_SURFACE_FAN is not set +CONFIG_SENSORS_SURFACE_TEMP=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_TPS23861=m +CONFIG_SENSORS_TPS25990=m +CONFIG_SENSORS_TPS25990_REGULATOR=y +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_TSL2563=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VIA_CPUTEMP=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_WM831X=m +CONFIG_SENSORS_WM8350=m +CONFIG_SENSORS_XDP710=m +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_XGENE=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_CS=m +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=m +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_LPSS=m +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_MEN_MCB=m +CONFIG_SERIAL_8250_MID=m +CONFIG_SERIAL_8250_NI=m +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PCI1XXXX=m +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_ALTERA_JTAGUART=m +CONFIG_SERIAL_ALTERA_UART=m +CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 +CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_FSL_LINFLEXUART=m +CONFIG_SERIAL_FSL_LPUART=m CONFIG_SERIAL_IPOCTAL=m -CONFIG_RESET_SIMPLE=y -CONFIG_RESET_TI_SYSCON=m -CONFIG_RESET_TI_TPS380X=m -CONFIG_USB_LGM_PHY=m -CONFIG_PHY_CAN_TRANSCEIVER=m -CONFIG_BCM_KONA_USB2_PHY=m -CONFIG_PHY_PXA_28NM_HSIC=m -CONFIG_PHY_PXA_28NM_USB2=m -CONFIG_PHY_CPCAP_USB=m -CONFIG_PHY_QCOM_USB_HS=m -CONFIG_PHY_QCOM_USB_HSIC=m -CONFIG_PHY_SAMSUNG_USB2=m -CONFIG_PHY_TUSB1210=m -CONFIG_PHY_INTEL_LGM_EMMC=m -CONFIG_INTEL_RAPL=m -CONFIG_INTEL_RAPL_TPMI=m -CONFIG_MCB=m -CONFIG_MCB_PCI=m -CONFIG_MCB_LPC=m -CONFIG_DWC_PCIE_PMU=m -CONFIG_CXL_PMU=m -CONFIG_USB4=m -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_BINDERFS=y -CONFIG_BLK_DEV_PMEM=m -CONFIG_DEV_DAX=m -CONFIG_NVMEM_RAVE_SP_EEPROM=m -CONFIG_NVMEM_RMEM=m -CONFIG_NVMEM_SPMI_SDAM=m -CONFIG_STM=m -CONFIG_STM_PROTO_BASIC=m -CONFIG_STM_PROTO_SYS_T=m -CONFIG_STM_DUMMY=m -CONFIG_STM_SOURCE_CONSOLE=m -CONFIG_STM_SOURCE_HEARTBEAT=m -CONFIG_STM_SOURCE_FTRACE=m -CONFIG_INTEL_TH=m -CONFIG_INTEL_TH_PCI=m -CONFIG_INTEL_TH_ACPI=m -CONFIG_INTEL_TH_GTH=m -CONFIG_INTEL_TH_STH=m -CONFIG_INTEL_TH_MSU=m -CONFIG_INTEL_TH_PTI=m -CONFIG_FPGA=m -CONFIG_ALTERA_PR_IP_CORE=m -CONFIG_FPGA_MGR_ALTERA_PS_SPI=m -CONFIG_FPGA_MGR_ALTERA_CVP=m -CONFIG_FPGA_MGR_XILINX_SELECTMAP=m -CONFIG_FPGA_MGR_XILINX_SPI=m -CONFIG_FPGA_MGR_MACHXO2_SPI=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_XILINX_PR_DECOUPLER=m -CONFIG_FPGA_DFL=m -CONFIG_FPGA_DFL_FME=m -CONFIG_FPGA_DFL_FME_MGR=m -CONFIG_FPGA_DFL_FME_BRIDGE=m -CONFIG_FPGA_DFL_FME_REGION=m -CONFIG_FPGA_DFL_AFU=m -CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m -CONFIG_FPGA_DFL_PCI=m -CONFIG_FPGA_M10_BMC_SEC_UPDATE=m -CONFIG_FPGA_MGR_MICROCHIP_SPI=m -CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m -CONFIG_TEE=m -CONFIG_MUX_ADG792A=m -CONFIG_MUX_ADGS1408=m -CONFIG_MUX_GPIO=m +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_LANTIQ=m +CONFIG_SERIAL_MAX3100=m +CONFIG_SERIAL_MAX310X=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MEN_Z135=m +CONFIG_SERIAL_MULTI_INSTANTIATE=m +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=m +CONFIG_SERIAL_SC16IS7XX_SPI=m +CONFIG_SERIAL_SCCNXP=y +CONFIG_SERIAL_SCCNXP_CONSOLE=y +# CONFIG_SERIAL_SPRD is not set +CONFIG_SERIAL_UARTLITE=m +CONFIG_SERIAL_UARTLITE_NR_UARTS=1 +CONFIG_SERIO=y +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_ARC_PS2=m +CONFIG_SERIO_CT82C710=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_SERIO_I8042=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_PS2MULT=m +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=m +CONFIG_SFC=m +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_MTD=y +CONFIG_SFC_SIENA=m +CONFIG_SFC_SIENA_MCDI_LOGGING=y +CONFIG_SFC_SIENA_MCDI_MON=y +CONFIG_SFC_SIENA_MTD=y +CONFIG_SFC_SIENA_SRIOV=y +CONFIG_SFC_SRIOV=y +CONFIG_SFP=m +CONFIG_SF_PDMA=m +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SGI_PARTITION=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SI1133=m +CONFIG_SI1145=m +CONFIG_SI7005=m +CONFIG_SI7020=m +CONFIG_SI7210=m +CONFIG_SIEMENS_SIMATIC_IPC=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT_APOLLOLAKE=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT_ELKHARTLAKE=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT_F7188X=m +CONFIG_SIEMENS_SIMATIC_IPC_WDT=m +CONFIG_SIGNALFD=y +CONFIG_SIGNATURE=y +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set +CONFIG_SILICOM_PLATFORM=m +# CONFIG_SIOX is not set +CONFIG_SIS190=m +CONFIG_SIS900=m +CONFIG_SKB_EXTENSIONS=y +CONFIG_SKFP=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_OBJ_EXT=y +CONFIG_SLHC=y +CONFIG_SLICOSS=m # CONFIG_SLIMBUS is not set -CONFIG_COUNTER=m -CONFIG_INTEL_QEP=m -CONFIG_INTERRUPT_CNT=m -CONFIG_MOST=m -CONFIG_MOST_USB_HDM=m -CONFIG_MOST_CDEV=m -CONFIG_MOST_SND=m -CONFIG_HTE=y -CONFIG_VALIDATE_FS_PARSER=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -CONFIG_JFS_STATISTICS=y -CONFIG_XFS_FS=y -CONFIG_XFS_SUPPORT_V4=y -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -# CONFIG_XFS_ONLINE_SCRUB is not set -CONFIG_GFS2_FS=m -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_OCFS2_FS=m -CONFIG_BTRFS_FS=y -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=m -CONFIG_F2FS_FS=m -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_FS_COMPRESSION=y -# CONFIG_F2FS_IOSTAT is not set -CONFIG_F2FS_UNFAIR_RWSEM=y -CONFIG_ZONEFS_FS=m -CONFIG_FS_DAX=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_VERITY=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m -CONFIG_AUTOFS_FS=m -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_VIRTIO_FS=m -CONFIG_OVERLAY_FS=m -# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set -CONFIG_NETFS_DEBUG=y -CONFIG_FSCACHE_STATS=y -CONFIG_CACHEFILES=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=y -CONFIG_EXFAT_FS=m -CONFIG_NTFS3_LZX_XPRESS=y -CONFIG_NTFS_FS=m -CONFIG_PROC_KCORE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_EFIVAR_FS=y -CONFIG_ORANGEFS_FS=m -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=m -CONFIG_UBIFS_ATIME_SUPPORT=y -CONFIG_UBIFS_FS_AUTHENTICATION=y -CONFIG_CRAMFS=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_SLIP_SMART=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_SMBFS=m +# CONFIG_SMB_SERVER is not set +CONFIG_SMI240=m +CONFIG_SMP=y +CONFIG_SMPRO_ERRMON=m +CONFIG_SMPRO_MISC=m +CONFIG_SMSC37B787_WDT=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +CONFIG_SMSC_SCH311X_WDT=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_SMS_SIANO_DEBUGFS=y +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +CONFIG_SMS_USB_DRV=m +CONFIG_SM_FTL=m +CONFIG_SND=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_AD1889=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ALOOP=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +CONFIG_SND_AMD_ACP_CONFIG=m +CONFIG_SND_AMD_ASOC_ACP63=m +CONFIG_SND_AMD_ASOC_ACP70=m +CONFIG_SND_AMD_ASOC_REMBRANDT=m +CONFIG_SND_AMD_ASOC_RENOIR=m +CONFIG_SND_AMD_SOUNDWIRE_ACPI=m +CONFIG_SND_ASIHPI=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_AZT3328=m +CONFIG_SND_BCD2000=m +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_BEBOB=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_COMPRESS_ACCEL=y +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_CTL_INPUT_VALIDATION=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_DARLA24=m +# CONFIG_SND_DEBUG is not set +CONFIG_SND_DESIGNWARE_I2S=m +# CONFIG_SND_DESIGNWARE_PCM is not set +CONFIG_SND_DICE=m +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DMA_SGBUF=y +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_ECHO3G=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_EMU10K1_SEQ=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FIREFACE=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_GINA20=m +CONFIG_SND_GINA24=m +CONFIG_SND_HDA=m +CONFIG_SND_HDA_ACPI=m +CONFIG_SND_HDA_CIRRUS_SCODEC=m +CONFIG_SND_HDA_CODEC_ALC260=m +CONFIG_SND_HDA_CODEC_ALC262=m +CONFIG_SND_HDA_CODEC_ALC268=m +CONFIG_SND_HDA_CODEC_ALC269=m +CONFIG_SND_HDA_CODEC_ALC662=m +CONFIG_SND_HDA_CODEC_ALC680=m +CONFIG_SND_HDA_CODEC_ALC861=m +CONFIG_SND_HDA_CODEC_ALC861VD=m +CONFIG_SND_HDA_CODEC_ALC880=m +CONFIG_SND_HDA_CODEC_ALC882=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CM9825=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CS420X=m +CONFIG_SND_HDA_CODEC_CS421X=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_HDMI_ATI=m +CONFIG_SND_HDA_CODEC_HDMI_GENERIC=m +CONFIG_SND_HDA_CODEC_HDMI_INTEL=m +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m +CONFIG_SND_HDA_CODEC_HDMI_SIMPLE=m +CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_REALTEK_LIB=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_CORE=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_I915=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_PREALLOC_SIZE=0 +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_SCODEC_COMPONENT=m +CONFIG_SND_HDA_SCODEC_CS35L41=m +CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m +CONFIG_SND_HDA_SCODEC_CS35L56=m +CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m +CONFIG_SND_HDA_SCODEC_TAS2781=m +CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m +CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_HWDEP=m +CONFIG_SND_I2S_HI6210_I2S=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_INTEL_BYT_PREFER_SOF=y +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_KORG1212=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_MIA=m +CONFIG_SND_MIXART=m +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_MONA=m +CONFIG_SND_MPU401=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_NM256=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_OXFW=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_PCI=y +CONFIG_SND_PCM=m +CONFIG_SND_PCMCIA=y +# CONFIG_SND_PCMTEST is not set +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCSP is not set +CONFIG_SND_PCXHR=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_PROC_FS=y +CONFIG_SND_RAWMIDI=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SB_COMMON=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQUENCER_OSS is not set +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_UMP=y +CONFIG_SND_SEQ_UMP_CLIENT=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ACPI=m +CONFIG_SND_SOC_ACPI_AMD_MATCH=m +CONFIG_SND_SOC_ACPI_INTEL_MATCH=m +CONFIG_SND_SOC_ACPI_INTEL_SDCA_QUIRKS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1373=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4619=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_ACP3x=m +CONFIG_SND_SOC_AMD_ACP5x=m +CONFIG_SND_SOC_AMD_ACP63_TOPLEVEL=m +CONFIG_SND_SOC_AMD_ACP6x=m +CONFIG_SND_SOC_AMD_ACPI_MACH=m +CONFIG_SND_SOC_AMD_ACP_COMMON=m +CONFIG_SND_SOC_AMD_ACP_I2S=m +CONFIG_SND_SOC_AMD_ACP_LEGACY_COMMON=m +CONFIG_SND_SOC_AMD_ACP_PCI=m +CONFIG_SND_SOC_AMD_ACP_PCM=m +CONFIG_SND_SOC_AMD_ACP_PDM=m +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_SOC_AMD_LEGACY_MACH=m +CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH=m +CONFIG_SND_SOC_AMD_MACH_COMMON=m +CONFIG_SND_SOC_AMD_PS=m +CONFIG_SND_SOC_AMD_PS_MACH=m +CONFIG_SND_SOC_AMD_RENOIR=m +CONFIG_SND_SOC_AMD_RENOIR_MACH=m +CONFIG_SND_SOC_AMD_RPL_ACP6x=m +CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m +CONFIG_SND_SOC_AMD_SDW_MACH_COMMON=m +CONFIG_SND_SOC_AMD_SOF_MACH=m +CONFIG_SND_SOC_AMD_SOF_SDW_MACH=m +CONFIG_SND_SOC_AMD_SOUNDWIRE=m +CONFIG_SND_SOC_AMD_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m +CONFIG_SND_SOC_AMD_VANGOGH_MACH=m +CONFIG_SND_SOC_AMD_YC_MACH=m +CONFIG_SND_SOC_ARIZONA=m +CONFIG_SND_SOC_AUDIO_IIO_AUX=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_AW87390=m +CONFIG_SND_SOC_AW88081=m +CONFIG_SND_SOC_AW88166=m +CONFIG_SND_SOC_AW88261=m +CONFIG_SND_SOC_AW88395=m +CONFIG_SND_SOC_AW88395_LIB=m +CONFIG_SND_SOC_AW88399=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CHV3_CODEC=m +CONFIG_SND_SOC_CHV3_I2S=m +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_CROS_EC_CODEC=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L41_LIB=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L56=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SDW=m +CONFIG_SND_SOC_CS35L56_SHARED=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_CORE=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L43=m +CONFIG_SND_SOC_CS42L43_SDW=m +CONFIG_SND_SOC_CS42L51=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS42L84=m +CONFIG_SND_SOC_CS42XX8=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS48L32=m +CONFIG_SND_SOC_CS530X=m +CONFIG_SND_SOC_CS530X_I2C=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CS_AMP_LIB=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DA7219=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8311=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8323=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_ES8375=m +CONFIG_SND_SOC_ES8389=m +CONFIG_SND_SOC_ES83XX_DSM_COMMON=m +# CONFIG_SND_SOC_FS210X is not set +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_UTILS=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_IDT821034=m +CONFIG_SND_SOC_IMX_AUDMUX=m +CONFIG_SND_SOC_INTEL_AVS=m +# CONFIG_SND_SOC_INTEL_AVS_CARDNAME_OBSOLETE is not set +CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m +CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m +CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336=m +CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m +CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=m +CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m +CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A=m +CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m +CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m +CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m +CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m +CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m +CONFIG_SND_SOC_INTEL_CATPT=m +CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m +CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m +CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_HASWELL_MACH=m +CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m +CONFIG_SND_SOC_INTEL_MACH=y +CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m +CONFIG_SND_SOC_INTEL_SOF_BOARD_HELPERS=m +CONFIG_SND_SOC_INTEL_SOF_CIRRUS_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m +CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m +CONFIG_SND_SOC_INTEL_SOF_DA7219_MACH=m +CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m +CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m +CONFIG_SND_SOC_INTEL_SOF_NUVOTON_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m +CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m +CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m +CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m +CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=m +CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y +CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98090=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98388=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX9860=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6357=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_MTK_BTCVSD=m +CONFIG_SND_SOC_NAU8315=m +# CONFIG_SND_SOC_NAU8325 is not set +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_NAU8825=m +CONFIG_SND_SOC_NTP8835=m +CONFIG_SND_SOC_NTP8918=m +CONFIG_SND_SOC_NTPFW=m +CONFIG_SND_SOC_PCM1681=m +# CONFIG_SND_SOC_PCM1754 is not set +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +CONFIG_SND_SOC_PCM3168A=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_PCM3168A_SPI=m +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_PCM6240=m +CONFIG_SND_SOC_PEB2466=m +# CONFIG_SND_SOC_PM4125_SDW is not set +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RL6347A=m +CONFIG_SND_SOC_RT1011=m +CONFIG_SND_SOC_RT1015=m +CONFIG_SND_SOC_RT1015P=m +CONFIG_SND_SOC_RT1017_SDCA_SDW=m +CONFIG_SND_SOC_RT1019=m +CONFIG_SND_SOC_RT1308=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m +CONFIG_SND_SOC_RT274=m +CONFIG_SND_SOC_RT286=m +CONFIG_SND_SOC_RT298=m +CONFIG_SND_SOC_RT5514=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5651=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5660=m +CONFIG_SND_SOC_RT5663=m +CONFIG_SND_SOC_RT5670=m +CONFIG_SND_SOC_RT5677=m +CONFIG_SND_SOC_RT5677_SPI=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682S=m +CONFIG_SND_SOC_RT5682_I2C=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +CONFIG_SND_SOC_RT712_SDCA_SDW=m +CONFIG_SND_SOC_RT715=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT721_SDCA_SDW=m +CONFIG_SND_SOC_RT722_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_RT9123=m +CONFIG_SND_SOC_RT9123P=m +CONFIG_SND_SOC_RTQ9124=m +CONFIG_SND_SOC_RTQ9128=m +CONFIG_SND_SOC_RT_SDW_COMMON=m +CONFIG_SND_SOC_SDCA=m +CONFIG_SND_SOC_SDCA_HID=y +CONFIG_SND_SOC_SDCA_IRQ=y +CONFIG_SND_SOC_SDCA_OPTIONAL=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SDW_UTILS=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SI476X=m +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SMA1303=m +CONFIG_SND_SOC_SMA1307=m +CONFIG_SND_SOC_SOF=m +CONFIG_SND_SOC_SOF_ACPI=m +CONFIG_SND_SOC_SOF_ACPI_DEV=m +CONFIG_SND_SOC_SOF_ACP_PROBES=m +CONFIG_SND_SOC_SOF_ALDERLAKE=m +CONFIG_SND_SOC_SOF_AMD_ACP63=m +CONFIG_SND_SOC_SOF_AMD_ACP70=m +CONFIG_SND_SOC_SOF_AMD_COMMON=m +CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m +CONFIG_SND_SOC_SOF_AMD_RENOIR=m +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE=m +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m +CONFIG_SND_SOC_SOF_AMD_VANGOGH=m +CONFIG_SND_SOC_SOF_APOLLOLAKE=m +CONFIG_SND_SOC_SOF_BAYTRAIL=m +CONFIG_SND_SOC_SOF_BROADWELL=m +CONFIG_SND_SOC_SOF_CANNONLAKE=m +CONFIG_SND_SOC_SOF_CLIENT=m +CONFIG_SND_SOC_SOF_COFFEELAKE=m +CONFIG_SND_SOC_SOF_COMETLAKE=m +CONFIG_SND_SOC_SOF_DEBUG_PROBES=m +# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set +CONFIG_SND_SOC_SOF_ELKHARTLAKE=m +CONFIG_SND_SOC_SOF_GEMINILAKE=m +CONFIG_SND_SOC_SOF_HDA=m +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y +CONFIG_SND_SOC_SOF_HDA_COMMON=m +CONFIG_SND_SOC_SOF_HDA_GENERIC=m +CONFIG_SND_SOC_SOF_HDA_LINK=y +CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_HDA_MLINK=m +CONFIG_SND_SOC_SOF_HDA_PROBES=m +CONFIG_SND_SOC_SOF_ICELAKE=m +CONFIG_SND_SOC_SOF_INTEL_APL=m +CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m +CONFIG_SND_SOC_SOF_INTEL_CNL=m +CONFIG_SND_SOC_SOF_INTEL_COMMON=m +CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m +CONFIG_SND_SOC_SOF_INTEL_ICL=m +CONFIG_SND_SOC_SOF_INTEL_LNL=m +CONFIG_SND_SOC_SOF_INTEL_MTL=m +CONFIG_SND_SOC_SOF_INTEL_PTL=m +CONFIG_SND_SOC_SOF_INTEL_SKL=m +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_INTEL_TGL=m +CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IPC3=y +CONFIG_SND_SOC_SOF_IPC4=y +CONFIG_SND_SOC_SOF_JASPERLAKE=m +CONFIG_SND_SOC_SOF_KABYLAKE=m +CONFIG_SND_SOC_SOF_LUNARLAKE=m +CONFIG_SND_SOC_SOF_MERRIFIELD=m +CONFIG_SND_SOC_SOF_METEORLAKE=m +CONFIG_SND_SOC_SOF_PANTHERLAKE=m +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_PCI_DEV=m +CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y +CONFIG_SND_SOC_SOF_SKYLAKE=m +CONFIG_SND_SOC_SOF_TIGERLAKE=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_XTENSA=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS2781_COMLIB=m +CONFIG_SND_SOC_TAS2781_COMLIB_I2C=m +CONFIG_SND_SOC_TAS2781_FMWLIB=m +CONFIG_SND_SOC_TAS2781_I2C=m +# CONFIG_SND_SOC_TAS2783_SDW is not set +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TLV320AIC23=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TOPOLOGY=y +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_UDA1342=m +CONFIG_SND_SOC_USB=m +CONFIG_SND_SOC_WCD937X=m +CONFIG_SND_SOC_WCD937X_SDW=m +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +# CONFIG_SND_SOC_WCD939X_SDW is not set +CONFIG_SND_SOC_WCD_CLASSH=m +CONFIG_SND_SOC_WCD_COMMON=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WM5102=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8961=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WM8998=m +CONFIG_SND_SOC_WM_ADSP=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_WSA884X=m +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +CONFIG_SND_SOC_XILINX_I2S=m +# CONFIG_SND_SOC_XILINX_SPDIF is not set +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOF_SOF_HDA_SDW_BPT=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_SPI=y +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_SYNTH_EMUX=m +CONFIG_SND_TIMER=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_UMP=m +CONFIG_SND_UMP_LEGACY_RAWMIDI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_USB_AUDIO_QMI=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_US122L=m +# CONFIG_SND_USB_US144MKII is not set +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_UTIMER=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_VIRTIO=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VMASTER=y +CONFIG_SND_VX222=m +CONFIG_SND_VXPOCKET=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_X86=y +CONFIG_SND_XEN_FRONTEND=m +CONFIG_SND_YMFPCI=m +CONFIG_SNET_VDPA=m +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOC_TI=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONYPI_COMPAT=y +CONFIG_SONY_FF=y +CONFIG_SONY_LAPTOP=m +CONFIG_SOUND=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_AMD=m +CONFIG_SOUNDWIRE_CADENCE=m +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m +CONFIG_SOUNDWIRE_INTEL=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SP5100_TCO=m +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP_PREINIT=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPEAKUP=m +# CONFIG_SPEAKUP_SYNTH_ACNTSA is not set +# CONFIG_SPEAKUP_SYNTH_APOLLO is not set +# CONFIG_SPEAKUP_SYNTH_AUDPTR is not set +# CONFIG_SPEAKUP_SYNTH_BNS is not set +# CONFIG_SPEAKUP_SYNTH_DECEXT is not set +# CONFIG_SPEAKUP_SYNTH_DECTLK is not set +# CONFIG_SPEAKUP_SYNTH_DUMMY is not set +# CONFIG_SPEAKUP_SYNTH_LTLK is not set +CONFIG_SPEAKUP_SYNTH_SOFT=m +# CONFIG_SPEAKUP_SYNTH_SPKOUT is not set +# CONFIG_SPEAKUP_SYNTH_TXPRT is not set +CONFIG_SPI=y +CONFIG_SPI_ALTERA=m +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +CONFIG_SPI_AMD=m +CONFIG_SPI_AX88796C=m +CONFIG_SPI_AX88796C_COMPRESSION=y +CONFIG_SPI_AXI_SPI_ENGINE=m +CONFIG_SPI_BITBANG=m +CONFIG_SPI_BUTTERFLY=m +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CH341=m +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DLN2=m +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_GPIO=m +# CONFIG_SPI_INTEL_PCI is not set +# CONFIG_SPI_INTEL_PLATFORM is not set +CONFIG_SPI_KSPI2=m +CONFIG_SPI_LANTIQ_SSC=m +CONFIG_SPI_LJCA=m +CONFIG_SPI_LM70_LLP=m +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_MUX=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_OFFLOAD=y +CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m +CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m +CONFIG_SPI_PCI1XXXX=m +CONFIG_SPI_PXA2XX=m +CONFIG_SPI_PXA2XX_PCI=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SIFIVE=m +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_TLE62X0=m +# CONFIG_SPI_VIRTIO is not set +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SPMI=m +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_FILE_DIRECT=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE is not set CONFIG_SQUASHFS_COMP_CACHE_FULL=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XATTR=y CONFIG_SQUASHFS_XZ=y -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_QNX6FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_PSTORE_RAM=m -CONFIG_UFS_FS=m -CONFIG_EROFS_FS=m -# CONFIG_EROFS_FS_ZIP is not set -CONFIG_VBOXSF_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V2=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=m -CONFIG_NFS_SWAP=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_NFS_V4_1_MIGRATION=y -CONFIG_NFS_FSCACHE=y -# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set -# CONFIG_NFS_V4_2_READ_PLUS is not set -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_V4_SECURITY_LABEL=y -# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set -CONFIG_NFS_LOCALIO=y -CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y -CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_ZSTD is not set +CONFIG_SRAM=y +CONFIG_SRF04=m +CONFIG_SRF08=m +CONFIG_SSB=m +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SPROM=y +CONFIG_SSFDC=m +CONFIG_SSIF_IPMI_BMC=m +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +CONFIG_STACKTRACE_BUILD_ID=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_STACK_TRACER=y +CONFIG_STACK_VALIDATION=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_STANDALONE is not set +# CONFIG_STATIC_CALL_SELFTEST is not set +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +CONFIG_STEAM_FF=y +CONFIG_STK3310=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +CONFIG_STM=m +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_PCI is not set +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STM_DUMMY=m +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +CONFIG_STM_SOURCE_CONSOLE=m +CONFIG_STM_SOURCE_FTRACE=m +CONFIG_STM_SOURCE_HEARTBEAT=m +CONFIG_STP=m +CONFIG_STREAM_PARSER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +# CONFIG_STRICT_SIGALTSTACK_SIZE is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_SUNDANCE is not set +CONFIG_SUNGEM=m +CONFIG_SUNGEM_PHY=m +CONFIG_SUNRPC=m +CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_SUNRPC_DEBUG=y -CONFIG_CEPH_FS=m -CONFIG_CEPH_FSCACHE=y -CONFIG_CEPH_FS_POSIX_ACL=y -CONFIG_CEPH_FS_SECURITY_LABEL=y -CONFIG_CIFS=m -# CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_CIFS_SWN_UPCALL=y -CONFIG_CIFS_FSCACHE=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_AFS_FSCACHE=y -CONFIG_9P_FS=m -CONFIG_9P_FSCACHE=y -CONFIG_9P_FS_POSIX_ACL=y -CONFIG_9P_FS_SECURITY=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_DLM=m -CONFIG_KEYS_REQUEST_CACHE=y -CONFIG_PERSISTENT_KEYRINGS=y +# CONFIG_SUNRPC_DEBUG_TRACE is not set +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_SWAP=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUN_PARTITION=y +CONFIG_SURFACE3_WMI=m +CONFIG_SURFACE_3_POWER_OPREGION=m +CONFIG_SURFACE_ACPI_NOTIFY=m +CONFIG_SURFACE_AGGREGATOR=m +CONFIG_SURFACE_AGGREGATOR_BUS=y +# CONFIG_SURFACE_AGGREGATOR_CDEV is not set +# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set +CONFIG_SURFACE_AGGREGATOR_HUB=m +CONFIG_SURFACE_AGGREGATOR_REGISTRY=m +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m +CONFIG_SURFACE_DTX=m +CONFIG_SURFACE_GPE=m +CONFIG_SURFACE_HID=m +CONFIG_SURFACE_HID_CORE=m +CONFIG_SURFACE_HOTPLUG=m +CONFIG_SURFACE_KBD=m +CONFIG_SURFACE_PLATFORMS=y +CONFIG_SURFACE_PLATFORM_PROFILE=m +CONFIG_SURFACE_PRO3_BUTTON=m +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SVC_I3C_MASTER=m +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SWIOTLB_XEN=y +CONFIG_SWPHY=y +# CONFIG_SW_SYNC is not set +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SXGBE_ETH=m +CONFIG_SX_COMMON=m +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYN_COOKIES=y +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_SYSFS=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSTEM76_ACPI=m +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +CONFIG_SYSV68_PARTITION=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYS_HYPERVISOR=y +CONFIG_T5403=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TAHVO_USB=m +CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y +CONFIG_TAP=m +CONFIG_TARGET_CORE=m +CONFIG_TASKSTATS=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +CONFIG_TCG_INFINEON=m +CONFIG_TCG_NSC=m +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_ATMEL=m +# CONFIG_TCG_TIS_I2C_CR50 is not set +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI=m +# CONFIG_TCG_TIS_SPI_CR50 is not set +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TPM2_HMAC=y +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_XEN=m +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_TCM_USER2=m +CONFIG_TCP_AO=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +CONFIG_TCP_SIGPOOL=y +CONFIG_TCS3414=m +CONFIG_TCS3472=m +CONFIG_TDX_GUEST_DRIVER=m +CONFIG_TEE=m +CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m +CONFIG_TELCLOCK=m +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_BPF=m +# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set +# CONFIG_TEST_DHRY is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +CONFIG_TEST_FIRMWARE=m +# CONFIG_TEST_FPU is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_IDA=m +# CONFIG_TEST_KALLSYMS is not set +# CONFIG_TEST_KEXEC_HANDOVER is not set +# CONFIG_TEST_KMOD is not set +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_LKM=m +# CONFIG_TEST_LOCKUP is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_MULDIV64 is not set +CONFIG_TEST_OBJAGG=m +CONFIG_TEST_OBJPOOL=m +CONFIG_TEST_PARMAN=m +CONFIG_TEST_POWER=m +# CONFIG_TEST_REF_TRACKER is not set +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_STATIC_KEYS=m +# CONFIG_TEST_SYSCTL is not set +CONFIG_TEST_UDELAY=m +CONFIG_TEST_UUID=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_XARRAY=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_TEXTSEARCH_KMP=m +CONFIG_THERMAL=y +# CONFIG_THERMAL_CORE_TESTING is not set +CONFIG_THERMAL_DEBUGFS=y +# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_NETLINK=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THINKPAD_ACPI=m +CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y +# CONFIG_THINKPAD_ACPI_DEBUG is not set +CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y +CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y +# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set +CONFIG_THINKPAD_ACPI_VIDEO=y +CONFIG_THINKPAD_LMI=m +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TICK_ONESHOT=y +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIMERFD=y +# CONFIG_TIMERLAT_TRACER is not set +CONFIG_TIME_NS=y +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_SHARP_MEMORY=m +CONFIG_TIPC=m +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TI_ADC081C=m +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC108S102=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC128S052=m +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS1100=m +CONFIG_TI_ADS1119=m +CONFIG_TI_ADS124S08=m +# CONFIG_TI_ADS1298 is not set +CONFIG_TI_ADS131E08=m +CONFIG_TI_ADS7138=m +CONFIG_TI_ADS7924=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +CONFIG_TI_ADS8688=m +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +CONFIG_TI_FPC202=m +CONFIG_TI_LMP92064=m +CONFIG_TI_TLC4541=m +# CONFIG_TI_TMAG5273 is not set +CONFIG_TI_TSC2046=m +CONFIG_TLAN=m +CONFIG_TLS=m +# CONFIG_TLS_DEVICE is not set +# CONFIG_TLS_TOE is not set +CONFIG_TMP006=m +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TMPFS=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_XATTR=y +CONFIG_TOOLS_SUPPORT_RELR=y +CONFIG_TOPSTAR_LAPTOP=m +CONFIG_TORTURE_TEST=m +CONFIG_TOSHIBA_BT_RFKILL=m +CONFIG_TOSHIBA_HAPS=m +CONFIG_TOSHIBA_WMI=m +CONFIG_TOUCHSCREEN_88PM860X=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP5=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP_SPI=m +CONFIG_TOUCHSCREEN_DA9034=m +CONFIG_TOUCHSCREEN_DA9052=m +# CONFIG_TOUCHSCREEN_DMI is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +# CONFIG_TOUCHSCREEN_HIMAX_HX852X is not set +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +# CONFIG_TOUCHSCREEN_HYNITRON_CST816X is not set +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_IMAGIS=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_IQS7211=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MC13783=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +CONFIG_TOUCHSCREEN_PCAP=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_SUR40=m +CONFIG_TOUCHSCREEN_SURFACE3_SPI=m +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM831X=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TPL0102=m +CONFIG_TPS6105X=m +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +CONFIG_TPS6594_ESM=y +CONFIG_TPS6594_PFSM=y +CONFIG_TPS68470_PMIC_OPREGION=y +CONFIG_TQMX86_WDT=m +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y +CONFIG_TRACEPOINTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_GPU_MEM is not set +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_TRUSTED_KEYS=y -CONFIG_KEY_DH_OPERATIONS=y -CONFIG_KEY_NOTIFICATIONS=y -CONFIG_SECURITY_DMESG_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK_XFRM=y -CONFIG_INTEL_TXT=y -CONFIG_LSM_MMAP_MIN_ADDR=0 -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_SELINUX_DEBUG=y -CONFIG_SECURITY_SMACK=y -CONFIG_SECURITY_SMACK_NETFILTER=y -CONFIG_SECURITY_TOMOYO=y -CONFIG_SECURITY_APPARMOR=y -CONFIG_SECURITY_YAMA=y -CONFIG_SECURITY_LANDLOCK=y -CONFIG_INTEGRITY_SIGNATURE=y -CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y -CONFIG_IMA=y -CONFIG_IMA_KEXEC=y -CONFIG_IMA_APPRAISE=y -CONFIG_IMA_DISABLE_HTABLE=y -CONFIG_EVM=y -CONFIG_EVM_EXTRA_SMACK_XATTRS=y -CONFIG_DEFAULT_SECURITY_APPARMOR=y -CONFIG_LSM="yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo" -CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y -CONFIG_ZERO_CALL_USED_REGS=y -CONFIG_FORTIFY_SOURCE=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_CRYPTO_USER=m -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_PCRYPT=m -CONFIG_CRYPTO_ECDSA=m -CONFIG_CRYPTO_ECRDSA=m -CONFIG_CRYPTO_AES_TI=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SM4_GENERIC=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_ADIANTUM=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_HCTR2=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SM3_GENERIC=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_CRC32=m -CONFIG_CRYPTO_842=m -CONFIG_CRYPTO_LZ4=m -CONFIG_CRYPTO_LZ4HC=m -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y -CONFIG_CRYPTO_USER_API_HASH=m -CONFIG_CRYPTO_USER_API_SKCIPHER=m -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_USER_API_AEAD=m -CONFIG_CRYPTO_AES_NI_INTEL=m -CONFIG_CRYPTO_BLOWFISH_X86_64=m -CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m -CONFIG_CRYPTO_CAST5_AVX_X86_64=m -CONFIG_CRYPTO_CAST6_AVX_X86_64=m -CONFIG_CRYPTO_DES3_EDE_X86_64=m -CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m -CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m -CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m -CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m -CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64=m -CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m -CONFIG_CRYPTO_NHPOLY1305_SSE2=m -CONFIG_CRYPTO_NHPOLY1305_AVX2=m -CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m -CONFIG_CRYPTO_SM3_AVX_X86_64=m -CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m -CONFIG_CRYPTO_DEV_PADLOCK=y -CONFIG_CRYPTO_DEV_PADLOCK_AES=m -CONFIG_CRYPTO_DEV_PADLOCK_SHA=m -CONFIG_CRYPTO_DEV_ATMEL_ECC=m -CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m -CONFIG_CRYPTO_DEV_CCP=y -CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m -CONFIG_CRYPTO_DEV_QAT_DH895xCC=m -CONFIG_CRYPTO_DEV_QAT_C3XXX=m -CONFIG_CRYPTO_DEV_QAT_C62X=m -CONFIG_CRYPTO_DEV_QAT_4XXX=m -CONFIG_CRYPTO_DEV_QAT_420XX=m -CONFIG_CRYPTO_DEV_QAT_6XXX=m -CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m -CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m -CONFIG_CRYPTO_DEV_QAT_C62XVF=m -CONFIG_CRYPTO_DEV_IAA_CRYPTO=m -CONFIG_CRYPTO_DEV_CHELSIO=m -CONFIG_CRYPTO_DEV_VIRTIO=m -CONFIG_CRYPTO_DEV_SAFEXCEL=m -CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m -CONFIG_PKCS8_PRIVATE_KEY_PARSER=m -CONFIG_PRIME_NUMBERS=m -CONFIG_XZ_DEC_MICROLZMA=y -CONFIG_XZ_DEC_TEST=m -CONFIG_DMA_CMA=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_6x10=y -CONFIG_FONT_TER16x32=y -CONFIG_FONT_6x8=y -CONFIG_PRINTK_TIME=y -CONFIG_STACKTRACE_BUILD_ID=y -CONFIG_BOOT_PRINTK_DELAY=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_DEBUG_INFO_BTF=y -CONFIG_FRAME_WARN=1024 -CONFIG_STACK_VALIDATION=y -CONFIG_KGDB=y -CONFIG_KGDB_LOW_LEVEL_TRAP=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_KEYBOARD=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m -CONFIG_MEM_ALLOC_PROFILING=y -CONFIG_MEM_ALLOC_PROFILING_DEBUG=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=0 -CONFIG_HARDLOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK_BLOCKER is not set -CONFIG_SCHEDSTATS=y -CONFIG_LOCK_TORTURE_TEST=m +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_TSL2583=m +CONFIG_TSL2591=m +CONFIG_TSL2772=m +CONFIG_TSL4531=m +CONFIG_TSM_GUEST=y +CONFIG_TSM_MEASUREMENTS=y +CONFIG_TSM_REPORTS=m +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_TTPCI_EEPROM=m +CONFIG_TTY=y +CONFIG_TTY_PRINTK=y +CONFIG_TTY_PRINTK_LEVEL=6 +CONFIG_TULIP=m +# CONFIG_TULIP_MMIO is not set +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_NAPI is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_TUXEDO_NB04_WMI_AB=m +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_MADC=m +CONFIG_TWL4030_WATCHDOG=m +CONFIG_TWL6030_GPADC=m +CONFIG_TWL6040_CORE=y +CONFIG_TXGBE=m +CONFIG_TXGBEVF=m +CONFIG_TYPEC=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_MT6360=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_INTEL_PMC=m +# CONFIG_TYPEC_MUX_IT5205 is not set +CONFIG_TYPEC_MUX_NB7VPQ904M=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_MUX_PS883X=m +CONFIG_TYPEC_MUX_PTN36502=m +CONFIG_TYPEC_MUX_TUSB1046=m +CONFIG_TYPEC_MUX_WCD939X_USBSS=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_TBT_ALTMODE=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_UCSI=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPHOON=m +CONFIG_UACCE=m +CONFIG_UBIFS_ATIME_SUPPORT=y +CONFIG_UBIFS_FS=m +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_SECURITY=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y +# CONFIG_UBSAN is not set +# CONFIG_UCLAMP_TASK is not set +CONFIG_UCS2_STRING=y +CONFIG_UCSI_ACPI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_UDF_FS=m +# CONFIG_UDMABUF is not set +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UFS_DEBUG is not set +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +CONFIG_UHID=m +CONFIG_UID16=y +CONFIG_UIO=m +CONFIG_UIO_AEC=m +CONFIG_UIO_CIF=m +CONFIG_UIO_DFL=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_MF624=m +CONFIG_UIO_NETX=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_SERCOS3=m +CONFIG_ULI526X=m +CONFIG_ULTRIX_PARTITION=y +CONFIG_UNACCEPTED_MEMORY=y +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNION_FIND=y +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX_DIAG=m +CONFIG_UNWINDER_FRAME_POINTER=y +# CONFIG_UNWINDER_ORC is not set +CONFIG_UNWIND_USER=y +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y +CONFIG_US5182D=m +CONFIG_USB=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +CONFIG_USB4_NET=m +CONFIG_USBIP_CORE=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_VUDC=m +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AMD5536UDC=m +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_ATM=m +CONFIG_USB_AUDIO=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_BDC_UDC=m +CONFIG_USB_BELKIN=y +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_CATC=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_CDNS2_UDC=m +CONFIG_USB_CDNS3=m +# CONFIG_USB_CDNS3_GADGET is not set +# CONFIG_USB_CDNS3_HOST is not set +CONFIG_USB_CDNS3_PCI_WRAP=m +CONFIG_USB_CDNSP_GADGET=y +CONFIG_USB_CDNSP_HOST=y +CONFIG_USB_CDNSP_PCI=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_CHIPIDEA=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_NPCM=m +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_COMMON=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_MIDI2=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +# CONFIG_USB_CONFIGFS_F_TCM is not set +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_CXACRU=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DSBR=m +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_DEBUG is not set +CONFIG_USB_DWC2_HOST=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_HAPS=m +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3_PCI=m +CONFIG_USB_DWC3_ULPI=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_EG20T=m +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC=m +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_F_ACM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_MIDI2=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_TCM=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_GADGET=m +CONFIG_USB_GADGETFS=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GL860=m +CONFIG_USB_GOKU=m +CONFIG_USB_GPIO_VBUS=m +CONFIG_USB_GR_UDC=m +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_HID=m +# CONFIG_USB_G_MULTI is not set +CONFIG_USB_G_NCM=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_HACKRF=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=m +CONFIG_USB_HIDDEV=y +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_HSO=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_IPHETH=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_ISP1301=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_DUAL_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +CONFIG_USB_ISP1760_HCD=y +# CONFIG_USB_ISP1760_HOST_ROLE is not set +CONFIG_USB_ISP1761_UDC=y +CONFIG_USB_KAWETH=m +CONFIG_USB_KBD=m +CONFIG_USB_KC2190=y +CONFIG_USB_KEENE=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LGM_PHY=m +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_LINK_LAYER_TEST=m +CONFIG_USB_LJCA=m +CONFIG_USB_M5602=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_MA901=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_MAX3420_UDC=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_MON=m +CONFIG_USB_MOUSE=m +CONFIG_USB_MR800=m +CONFIG_USB_MSI2500=m +CONFIG_USB_MUSB_DUAL_ROLE=y +# CONFIG_USB_MUSB_GADGET is not set +CONFIG_USB_MUSB_HDRC=m +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_NET2280=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_PCI=y +CONFIG_USB_PCI_AMD=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_PHY=y +CONFIG_USB_PRINTER=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_PXA27X=m +CONFIG_USB_R8A66597=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_RAINSHADOW_CEC=m +CONFIG_USB_RAREMONO=m +CONFIG_USB_RAW_GADGET=m +CONFIG_USB_ROLES_INTEL_XHCI=m +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_USB_S2255=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_SI470X=m +CONFIG_USB_SI4713=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SL811_CS=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STV06XX=m +CONFIG_USB_SUPPORT=y +CONFIG_USB_TEST=m +CONFIG_USB_TMC=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_UAS=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +# CONFIG_USB_USBIO is not set +CONFIG_USB_USBNET=m +CONFIG_USB_USS720=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +CONFIG_USB_XEN_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XHCI_SIDEBAND=y +CONFIG_USB_XUSBATM=m +CONFIG_USB_YUREX=m +CONFIG_USB_ZERO=m +CONFIG_USERFAULTFD=y +CONFIG_USERIO=m +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USER_NS=y +CONFIG_USER_RETURN_NOTIFIER=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_USE_X86_SEG_SUPPORT=y +CONFIG_UTS_NS=y +CONFIG_UVC_COMMON=m +# CONFIG_U_SERIAL_CONSOLE is not set +CONFIG_V4L2_ASYNC=m +CONFIG_V4L2_CCI=m +CONFIG_V4L2_CCI_I2C=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_MEM2MEM_DEV=m +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_VBOXGUEST=m +CONFIG_VBOXSF_FS=m +CONFIG_VCAP=y +CONFIG_VCNL3020=m +CONFIG_VCNL4000=m +CONFIG_VCNL4035=m +CONFIG_VDPA=m +# CONFIG_VDPA_SIM is not set +CONFIG_VDPA_USER=m +CONFIG_VDSO_GETRANDOM=y +CONFIG_VEML3235=m +CONFIG_VEML6030=m +CONFIG_VEML6040=m +# CONFIG_VEML6046X00 is not set +CONFIG_VEML6070=m +CONFIG_VEML6075=m +CONFIG_VETH=m +CONFIG_VF610_ADC=m +CONFIG_VF610_DAC=m +CONFIG_VFAT_FS=y +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +CONFIG_VFIO_GROUP=y +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_MDEV=m +CONFIG_VFIO_NOIOMMU=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_IGD=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI_VGA=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGASTATE=m +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VGA_CONSOLE=y +CONFIG_VGA_SWITCHEROO=y +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_RING=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST_VDPA=m +CONFIG_VHOST_VSOCK=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_VIA_WDT=m +CONFIG_VIDEO=y +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_ADV7511=m +CONFIG_VIDEO_ADV7511_CEC=y +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_ALVIUM_CSI2=m +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT848=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m +CONFIG_VIDEO_CAFE_CCIC=m +CONFIG_VIDEO_CAMERA_LENS=y +CONFIG_VIDEO_CAMERA_SENSOR=y +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_COBALT=m +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_CX23885=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9719=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_FB_IVTV=m +# CONFIG_VIDEO_FB_IVTV_FORCE_PAT is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC0310 is not set +CONFIG_VIDEO_GC05A2=m +CONFIG_VIDEO_GC08A3=m +CONFIG_VIDEO_GC2145=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GS1662=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_INTEL_IPU6=m +CONFIG_VIDEO_INTEL_IPU7=m +CONFIG_VIDEO_IPU3_CIO2=m +CONFIG_VIDEO_IPU3_IMGU=m +CONFIG_VIDEO_IR_I2C=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_VIDEO_LT6911UXE=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MAX96717=m +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MGB4=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9M114=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_OG01A1B=m +# CONFIG_VIDEO_OG0VE1B is not set +CONFIG_VIDEO_OV01A10=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV02C10=m +CONFIG_VIDEO_OV02E10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +# CONFIG_VIDEO_OV2735 is not set +CONFIG_VIDEO_OV2740=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +# CONFIG_VIDEO_OV6211 is not set +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_OV9734=m +CONFIG_VIDEO_PVRUSB2=m +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_PVRUSB2_DVB=y +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_RP1_CFE=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_SAA6588=m +CONFIG_VIDEO_SAA6752HS=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_SAA7164=m +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TC358746=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_THP7312=m +CONFIG_VIDEO_THS7303=m +CONFIG_VIDEO_THS8200=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +CONFIG_VIDEO_TW9900=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEO_VD55G1=m +CONFIG_VIDEO_VD56G3=m +CONFIG_VIDEO_VIA_CAMERA=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIM2M=m +# CONFIG_VIDEO_VIMC is not set +# CONFIG_VIDEO_VISL is not set +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +# CONFIG_VIDEO_VIVID_OSD is not set +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_ZORAN is not set +CONFIG_VIPERBOARD_ADC=m +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_DEBUG=y +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VIRTIO_FS=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_IOMMU=m +CONFIG_VIRTIO_MEM=m +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_ADMIN_LEGACY=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_RTC=m +CONFIG_VIRTIO_RTC_CLASS=y +CONFIG_VIRTIO_RTC_PTP=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_VFIO_PCI=m +CONFIG_VIRTIO_VFIO_PCI_ADMIN_LEGACY=y +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_VIRTUALIZATION=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRT_WIFI=m +CONFIG_VIRT_XFER_TO_GUEST_WORK=y +CONFIG_VITESSE_PHY=m +CONFIG_VL53L0X_I2C=m +CONFIG_VL6180=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_PFN=y +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VMD=m +CONFIG_VME_BUS=y +# CONFIG_VME_FAKE is not set +CONFIG_VME_TSI148=m +CONFIG_VME_USER=m +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_VMWARE_BALLOON=m +CONFIG_VMWARE_PVSCSI=m +CONFIG_VMWARE_VMCI=m +CONFIG_VMWARE_VMCI_VSOCKETS=m +CONFIG_VMXNET3=m +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VORTEX=m +CONFIG_VP_VDPA=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKMON=m +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VXFS_FS=m +CONFIG_VXLAN=m +CONFIG_VZ89X=m +CONFIG_W1=m +CONFIG_W1_CON=y +CONFIG_W1_MASTER_AMD_AXI=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_SGI=m +# CONFIG_W1_MASTER_UART is not set +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +# CONFIG_W1_SLAVE_DS2433_CRC is not set +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W83627HF_WDT=m +CONFIG_W83877F_WDT=m +CONFIG_W83977F_WDT=m +CONFIG_WAFER_WDT=m +CONFIG_WAN=y +CONFIG_WANT_COMPAT_NETLINK_MESSAGES=y +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_WANXL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCH_QUEUE=y +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WDAT_WDT=m +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +CONFIG_WFX=m +CONFIG_WIL6210=m +CONFIG_WIL6210_DEBUGFS=y +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +CONFIG_WILC1000=m +# CONFIG_WILC1000_HW_OOB_INTR is not set +CONFIG_WILC1000_SDIO=m +CONFIG_WILC1000_SPI=m +CONFIG_WILCO_EC=m +# CONFIG_WILCO_EC_DEBUGFS is not set +CONFIG_WILCO_EC_EVENTS=m +CONFIG_WILCO_EC_TELEMETRY=m +CONFIG_WINBOND_840=m +CONFIG_WINMATE_FM07_KEYS=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_HOTKEY=m +CONFIG_WIZNET_BUS_ANY=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_W5100=m +# CONFIG_WIZNET_W5100_SPI is not set +CONFIG_WIZNET_W5300=m +CONFIG_WL1251=m +CONFIG_WL1251_SDIO=m +CONFIG_WL1251_SPI=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_PURELIFI=y +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLCORE=m +CONFIG_WLCORE_SDIO=m +CONFIG_WM831X_BACKUP=m +CONFIG_WM831X_POWER=m +CONFIG_WM831X_WATCHDOG=m +CONFIG_WM8350_POWER=m +CONFIG_WM8350_WATCHDOG=m +CONFIG_WMI_BMOF=m +CONFIG_WPCM450_SOC=m +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_WQ_WATCHDOG is not set +CONFIG_WWAN=y +# CONFIG_WWAN_DEBUGFS is not set +# CONFIG_WWAN_HWSIM is not set CONFIG_WW_MUTEX_SELFTEST=m -CONFIG_RCU_CPU_STALL_TIMEOUT=60 -# CONFIG_RCU_TRACE is not set -CONFIG_FPROBE=y -CONFIG_FUNCTION_PROFILER=y -CONFIG_STACK_TRACER=y -CONFIG_SCHED_TRACER=y -CONFIG_MMIOTRACE=y -CONFIG_FTRACE_SYSCALLS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_SYNTH_EVENTS=y -CONFIG_IO_STRICT_DEVMEM=y +CONFIG_X25=m +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_X86=y +CONFIG_X86_16BIT=y +CONFIG_X86_64=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_X86_ACPI_CPUFREQ=y +CONFIG_X86_ACPI_CPUFREQ_CPB=y +CONFIG_X86_AMD_FREQ_SENSITIVITY=m +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_X86_AMD_PSTATE=y +CONFIG_X86_AMD_PSTATE_DEFAULT_MODE=3 +# CONFIG_X86_AMD_PSTATE_UT is not set +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y +CONFIG_X86_BUS_LOCK_DETECT=y +CONFIG_X86_CET=y +CONFIG_X86_CHECK_BIOS_CORRUPTION=y +CONFIG_X86_CMOV=y +# CONFIG_X86_CPA_STATISTICS is not set +CONFIG_X86_CPUID=m +# CONFIG_X86_CPU_RESCTRL is not set +CONFIG_X86_CX8=y +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_X86_DEBUG_FPU=y +# CONFIG_X86_DECODER_SELFTEST is not set +CONFIG_X86_DIRECT_GBPAGES=y +CONFIG_X86_DISABLED_FEATURE_CENTAUR_MCR=y +CONFIG_X86_DISABLED_FEATURE_CYRIX_ARR=y +CONFIG_X86_DISABLED_FEATURE_K6_MTRR=y +CONFIG_X86_DISABLED_FEATURE_LAM=y +CONFIG_X86_DISABLED_FEATURE_USER_SHSTK=y +CONFIG_X86_DISABLED_FEATURE_VME=y +CONFIG_X86_ESPFIX64=y +CONFIG_X86_EXTENDED_PLATFORM=y +CONFIG_X86_FRED=y +# CONFIG_X86_GOLDFISH is not set +CONFIG_X86_HAVE_PAE=y +CONFIG_X86_HV_CALLBACK_VECTOR=y +CONFIG_X86_INTEL_LPSS=y +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +# CONFIG_X86_INTEL_MID is not set +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_IOPL_IOPERM=y +CONFIG_X86_IO_APIC=y +CONFIG_X86_KERNEL_IBT=y +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_AMD=y +# CONFIG_X86_MCE_INJECT is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_THRESHOLD=y +CONFIG_X86_MEM_ENCRYPT=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_MPPARSE=y +CONFIG_X86_MSR=m +# CONFIG_X86_NATIVE_CPU is not set +CONFIG_X86_NEED_RELOCS=y +CONFIG_X86_NUMACHIP=y +CONFIG_X86_P4_CLOCKMOD=m +CONFIG_X86_PAT=y +CONFIG_X86_PCC_CPUFREQ=y +CONFIG_X86_PKG_TEMP_THERMAL=m +CONFIG_X86_PLATFORM_DEVICES=y +CONFIG_X86_PLATFORM_DRIVERS_DELL=y +CONFIG_X86_PLATFORM_DRIVERS_HP=y +CONFIG_X86_PMEM_LEGACY=y +CONFIG_X86_PMEM_LEGACY_DEVICE=y +CONFIG_X86_PM_TIMER=y +# CONFIG_X86_POSTED_MSI is not set +CONFIG_X86_POWERNOW_K8=y +CONFIG_X86_REQUIRED_FEATURE_ALWAYS=y +CONFIG_X86_REQUIRED_FEATURE_CMOV=y +CONFIG_X86_REQUIRED_FEATURE_CPUID=y +CONFIG_X86_REQUIRED_FEATURE_CX8=y +CONFIG_X86_REQUIRED_FEATURE_FPU=y +CONFIG_X86_REQUIRED_FEATURE_FXSR=y +CONFIG_X86_REQUIRED_FEATURE_LM=y +CONFIG_X86_REQUIRED_FEATURE_MSR=y +CONFIG_X86_REQUIRED_FEATURE_NOPL=y +CONFIG_X86_REQUIRED_FEATURE_PAE=y +CONFIG_X86_REQUIRED_FEATURE_XMM=y +CONFIG_X86_REQUIRED_FEATURE_XMM2=y +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_SGX=y +CONFIG_X86_SGX_KVM=y +CONFIG_X86_SPEEDSTEP_CENTRINO=y +CONFIG_X86_SPEEDSTEP_LIB=m +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_X86_THERMAL_VECTOR=y +CONFIG_X86_TSC=y +CONFIG_X86_UMIP=y +# CONFIG_X86_USER_SHADOW_STACK is not set +# CONFIG_X86_UV is not set # CONFIG_X86_VERBOSE_BOOTUP is not set -CONFIG_EARLY_PRINTK_DBGP=y -CONFIG_IO_DELAY_0XED=y -CONFIG_PUNIT_ATOM_DEBUG=m -CONFIG_UNWINDER_FRAME_POINTER=y -CONFIG_NOTIFIER_ERROR_INJECTION=m -CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m -CONFIG_FUNCTION_ERROR_INJECTION=y -CONFIG_INTERVAL_TREE_TEST=m -CONFIG_PERCPU_TEST=m -CONFIG_ASYNC_RAID6_TEST=m -CONFIG_TEST_HEXDUMP=m -CONFIG_TEST_KSTRTOX=m -CONFIG_TEST_BITMAP=m -CONFIG_TEST_UUID=m -CONFIG_TEST_XARRAY=m -CONFIG_TEST_RHASHTABLE=m -CONFIG_TEST_IDA=m -CONFIG_TEST_PARMAN=m -CONFIG_TEST_LKM=m -CONFIG_TEST_BITOPS=m -CONFIG_TEST_VMALLOC=m -CONFIG_TEST_BPF=m -CONFIG_FIND_BIT_BENCHMARK=m -CONFIG_TEST_FIRMWARE=m -CONFIG_TEST_UDELAY=m -CONFIG_TEST_STATIC_KEYS=m -CONFIG_TEST_OBJAGG=m -CONFIG_TEST_OBJPOOL=m -CONFIG_MEMTEST=y +CONFIG_X86_VMX_FEATURE_NAMES=y +# CONFIG_X86_VSMP is not set +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_X2APIC=y +CONFIG_X86_X32_ABI=y +CONFIG_X9250=m +CONFIG_XARRAY_MULTI=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XEN=y +CONFIG_XENFS=m +CONFIG_XEN_512GB=y +CONFIG_XEN_ACPI=y +CONFIG_XEN_ACPI_PROCESSOR=y +CONFIG_XEN_AUTO_XLATE=y +CONFIG_XEN_BACKEND=y +CONFIG_XEN_BALLOON=y +CONFIG_XEN_BALLOON_MEMORY_HOTPLUG=y +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_XEN_BLKDEV_FRONTEND=y +CONFIG_XEN_COMPAT_XENFS=y +# CONFIG_XEN_DEBUG_FS is not set +CONFIG_XEN_DEV_EVTCHN=m +CONFIG_XEN_DOM0=y +CONFIG_XEN_EFI=y +CONFIG_XEN_FBDEV_FRONTEND=m +CONFIG_XEN_FRONT_PGDIR_SHBUF=m +CONFIG_XEN_GNTDEV=m +CONFIG_XEN_GRANT_DEV_ALLOC=m +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_XEN_GRANT_DMA_OPS=y +CONFIG_XEN_HAVE_PVMMU=y +CONFIG_XEN_HAVE_VPMU=y +CONFIG_XEN_MCE_LOG=y +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT=512 +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_XEN_NETDEV_FRONTEND=y +CONFIG_XEN_PCIDEV_BACKEND=m +CONFIG_XEN_PCIDEV_FRONTEND=m +CONFIG_XEN_PCI_STUB=y +CONFIG_XEN_PRIVCMD=m +CONFIG_XEN_PRIVCMD_EVENTFD=y +CONFIG_XEN_PV=y +# CONFIG_XEN_PVCALLS_BACKEND is not set +CONFIG_XEN_PVCALLS_FRONTEND=m +CONFIG_XEN_PVH=y +CONFIG_XEN_PVHVM=y +CONFIG_XEN_PVHVM_GUEST=y +CONFIG_XEN_PVHVM_SMP=y +CONFIG_XEN_PV_DOM0=y +CONFIG_XEN_PV_MSR_SAFE=y +CONFIG_XEN_PV_SMP=y +CONFIG_XEN_SCRUB_PAGES_DEFAULT=y +CONFIG_XEN_SCSI_BACKEND=m +CONFIG_XEN_SCSI_FRONTEND=m +CONFIG_XEN_SYMS=y +CONFIG_XEN_SYS_HYPERVISOR=y +CONFIG_XEN_UNPOPULATED_ALLOC=y +CONFIG_XEN_VIRTIO=y +# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set +CONFIG_XEN_WDT=m +CONFIG_XEN_XENBUS_FRONTEND=y +CONFIG_XFRM=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_IPCOMP=m +# CONFIG_XFRM_IPTFS is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_USER=m +CONFIG_XFRM_USER_COMPAT=m +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_ONLINE_SCRUB is not set +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +# CONFIG_XFS_SUPPORT_ASCII_CI is not set +CONFIG_XFS_SUPPORT_V4=y +# CONFIG_XFS_WARN is not set +CONFIG_XIAOMI_WMI=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_DMA=m +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_XILINX_SDFEC=m +CONFIG_XILINX_VCU=m +CONFIG_XILINX_WATCHDOG=m +CONFIG_XILINX_XADC=m +CONFIG_XILINX_XDMA=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_RISCV=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m +CONFIG_XZ_DEC_X86=y +CONFIG_YAM=m +CONFIG_YAMAHA_YAS530=m +CONFIG_YELLOWFIN=m +CONFIG_YENTA=m +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_YOGABOOK=m +CONFIG_YT2_1380=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_ZEROPLUS_FF=y +CONFIG_ZERO_CALL_USED_REGS=y +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_ZISOFS=y +CONFIG_ZL3073X=m +CONFIG_ZL3073X_I2C=m +CONFIG_ZL3073X_SPI=m +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONEFS_FS=m +CONFIG_ZONE_DEVICE=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ZOPT2201=m +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +CONFIG_ZRAM=m +CONFIG_ZRAM_BACKEND_842=y +CONFIG_ZRAM_BACKEND_DEFLATE=y +CONFIG_ZRAM_BACKEND_LZ4=y +CONFIG_ZRAM_BACKEND_LZ4HC=y +CONFIG_ZRAM_BACKEND_LZO=y +CONFIG_ZRAM_BACKEND_ZSTD=y +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_DEF_COMP_842 is not set +# CONFIG_ZRAM_DEF_COMP_DEFLATE is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC=y +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set diff --git a/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec b/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec index 1f25b5dd75..196b81df4d 100644 --- a/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec +++ b/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec @@ -25,16 +25,24 @@ %global kver %{version}-%{release} %global kernel_make_flags LD=ld.bfd KBUILD_BUILD_VERSION=%{release} +%if "%{?openruyi_riscv_arch}" == "-march=rva20u64" + %global arch_suffix -rva20 +%else + %global arch_suffix %{nil} +%endif + Name: linux-lts-kmhv2 -Version: 6.18.34 +Version: 6.18.38 Release: %autorelease Summary: The Linux lts Kernel License: GPL-2.0-only URL: https://www.kernel.org/ -#!RemoteAsset: sha256:640c4732fb42842166db97e032c1fe7e5ff72c85a8982c75b40f74be3555d760 +#!RemoteAsset: sha256:ac26e508abd56e9f8b89872b6e10c49fc823bcc70d8068a5d8504c1a7c4ff045 Source0: https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-%{version}.tar.xz -Source1: config.%{_arch} -Source2: series +Source1: series +Source2: config.x86_64 +Source3: config.riscv64 +Source4: config.riscv64-rva20 ExclusiveArch: riscv64 @@ -84,7 +92,7 @@ Requires(post): kernel-install Requires(postun): kernel-install %patchlist -%include %{SOURCE2} +%include %{SOURCE1} %description This is a meta-package that installs the core kernel image and modules. @@ -127,7 +135,7 @@ for booting. %prep %autosetup -p1 -n linux-%{version} -cp %{SOURCE1} .config +cp -v %{_sourcedir}/config.%{_arch}%{arch_suffix} .config echo "-%{release}" > localversion %conf diff --git a/SPECS/linux-lts-kmhv2/series b/SPECS/linux-lts-kmhv2/series index 356e712fb0..5afecc7f53 100644 --- a/SPECS/linux-lts-kmhv2/series +++ b/SPECS/linux-lts-kmhv2/series @@ -289,187 +289,282 @@ 0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch 0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch 0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch -0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch -0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch -0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch -0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch -0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch -0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch -0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch -0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch -0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch -0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch -0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch -0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch -0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch -0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch -0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch -0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch -0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch -0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch -0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch -0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch -0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch -0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch 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+0568-XIANGSHAN-Flush-all-tlb-in-set_pte.patch +0569-XIANGSHAN-Add-two-sbi-calls.patch +0570-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch diff --git a/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch b/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch index dd82e46153..8a2c392775 100644 --- a/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch +++ b/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch @@ -1,4 +1,4 @@ -From e8197b44ac58d76565180793e59b2ff39d0ff8a1 Mon Sep 17 00:00:00 2001 +From 97ce2bdaf4b2f91ebc9016642d5cc671eabce12f Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 5 Dec 2025 10:42:07 +0800 Subject: [RUYI PATCH] UPSTREAM: drm/ttm: add pgprot handling for RISC-V diff --git a/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch b/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch index b8cb7f6ff0..85a75bc27b 100644 --- a/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch +++ b/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch @@ -1,4 +1,4 @@ -From 172fa2e5a76c1351ea1bb6903e1d03944ce8a778 Mon Sep 17 00:00:00 2001 +From 97be83a032e9301602d9de79b068c7f8643c14b5 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:33:43 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: add PCIe controllers for diff --git a/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch b/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch index 43e4f49e7c..afac2af701 100644 --- a/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch +++ b/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch @@ -1,4 +1,4 @@ -From eb8e783adc4036ef80be48cfc8469b4be20fb577 Mon Sep 17 00:00:00 2001 +From 3690d132b79814fcc0c66ab440226e50704d3483 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:34:05 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for PioneerBox diff --git a/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index 46b8b479dc..29dfacf6a1 100644 --- a/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,4 +1,4 @@ -From 97f3ca4bfb8cf08fc5f01da48adbd2e295d9bf62 Mon Sep 17 00:00:00 2001 +From e80454feebb2dfa5da9609ea55fce6f9519c8be2 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:39:22 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for diff --git a/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index 118243db74..1a055cfef7 100644 --- a/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,4 +1,4 @@ -From adfc1b75ef3710cc675487e2d856fe811e92c9cf Mon Sep 17 00:00:00 2001 +From 71bf5268f5ef1cc80ed546655694263fd3097451 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:40:09 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for diff --git a/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch b/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch index 0105843995..a5d596c0c0 100644 --- a/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch +++ b/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch @@ -1,4 +1,4 @@ -From 0fe3f721fe45c7b4cfd9c65eaea2e94c7d05d05a Mon Sep 17 00:00:00 2001 +From 0d419dceddbb45354691c13c2af18305fe6547b4 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:50 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for diff --git a/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch b/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch index e7d51ad4e9..33418a23c5 100644 --- a/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch +++ b/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch @@ -1,4 +1,4 @@ -From 9e5ebf3bb03d5951a1ac6273a557a7d3b42aaf5d Mon Sep 17 00:00:00 2001 +From 43537896ac9425049eb19027394a36723e71fa30 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:51 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for diff --git a/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index 0353c0d45c..b9c0dedbfc 100644 --- a/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,4 +1,4 @@ -From ca6b4bc1ae282908399370569de96b507b11a199 Mon Sep 17 00:00:00 2001 +From 1279d407915d0d8872feb831ab0057a57cfc7766 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:52 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for diff --git a/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index 849dbb07fb..45faa67a83 100644 --- a/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,4 +1,4 @@ -From ef69ecb5f71cc9ec10bbe973e96dec13a22d83c5 Mon Sep 17 00:00:00 2001 +From 4a6215528dd5e1ef5ed45e47dcc2156905f17457 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:53 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for diff --git a/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch b/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch index f9aa138c7a..afabfcf38d 100644 --- a/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch +++ b/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch @@ -1,4 +1,4 @@ -From 4cec01963100499caa46c4c97acb3d80549132f6 Mon Sep 17 00:00:00 2001 +From 220eda5b92a6554f6629a577c1a4f8c8c540ea62 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 14 Nov 2025 08:38:03 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add phy diff --git a/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch b/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch index d0b72dcb45..4953853a2a 100644 --- a/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch +++ b/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch @@ -1,4 +1,4 @@ -From 97f62d7522d266af5df939fe3f50a0e365d78d37 Mon Sep 17 00:00:00 2001 +From c617ae290d1fc44e19de8a6eabb0f9eb646b2a89 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 14 Oct 2025 09:48:29 +0800 Subject: [RUYI PATCH] UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 diff --git a/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch b/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch index de2b418bcf..c5d0087211 100644 --- a/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch +++ b/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch @@ -1,4 +1,4 @@ -From e140a5124e38afd1d68eb3c9da0a96a9bc0c1fd8 Mon Sep 17 00:00:00 2001 +From 030a12284f19a1cb1f1e7f9b99be40c5f772e430 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:32 +0100 Subject: [RUYI PATCH] UPSTREAM: rust: macros: Add support for 'imports_ns' to diff --git a/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch b/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch index a4878efc8e..1d4036d2b5 100644 --- a/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch +++ b/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch @@ -1,4 +1,4 @@ -From 6eec5416f899b995199e6a78acdba366552fe74b Mon Sep 17 00:00:00 2001 +From d90ef5c3db441ba7f0277b9d3d8dd93c6be76480 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:01 +0200 Subject: [RUYI PATCH] UPSTREAM: pwm: Export `pwmchip_release` for external use diff --git a/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch b/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch index 3a11557826..2372b43853 100644 --- a/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch +++ b/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch @@ -1,4 +1,4 @@ -From dc77d3e5fd4e58d58519c452e5ab3a3dc0d30352 Mon Sep 17 00:00:00 2001 +From d22b703423b02fef77f92c7c296b729cb930987e Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:02 +0200 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add Kconfig and basic data diff --git a/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch b/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch index ae5c79af9d..6f84a9b336 100644 --- a/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch +++ b/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch @@ -1,4 +1,4 @@ -From fad4bc85d938d1fa411bfc7c09b2c327dc21cad2 Mon Sep 17 00:00:00 2001 +From ccb66826aea8948cb3035bb3cb97dee900cc6a33 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:03 +0200 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add complete abstraction layer diff --git a/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch b/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch index abdc4b8594..52e33544ff 100644 --- a/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch +++ b/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch @@ -1,4 +1,4 @@ -From a8369a239ce03856b5d63e39d5c92586c0641c18 Mon Sep 17 00:00:00 2001 +From 8d6832a03f3e1f228dcf5140425930cc757b7bdb Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:33 +0100 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add module_pwm_platform_driver! diff --git a/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch b/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch index a2e4a4474c..b615b2a628 100644 --- a/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch +++ b/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch @@ -1,4 +1,4 @@ -From 0bed1f7ddadef9191b85230b6f078bf48a1ddfc1 Mon Sep 17 00:00:00 2001 +From 871900020c098bb21b573743517cd57c5ec7f81b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 25 Oct 2025 14:23:56 +0200 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Drop wrapping of PWM polarity and diff --git a/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch b/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch index aaf7682aaf..55ea08cfbf 100644 --- a/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch +++ b/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch @@ -1,4 +1,4 @@ -From ce0cfe6521836f8d1bff1dbb1dd784f8dbe2f0f1 Mon Sep 17 00:00:00 2001 +From 151e60806c4961978acb15059175ebf859943f2a Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:19:40 +0100 Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Fix broken intra-doc link diff --git a/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch b/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch index 4a1351eb60..531fc8e38c 100644 --- a/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch +++ b/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch @@ -1,4 +1,4 @@ -From 323a18dcdb57c3c4a56d687fff097af3249b0fe3 Mon Sep 17 00:00:00 2001 +From bd117df72465a339cb37c8f8f294b14b31cfff74 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:04 +0200 Subject: [RUYI PATCH] UPSTREAM: pwm: Add Rust driver for T-HEAD TH1520 SoC diff --git a/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch b/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch index 72b7b6e552..01819c9dc5 100644 --- a/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch +++ b/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch @@ -1,4 +1,4 @@ -From 1ff5f22be0212ca408aa7b7fb452742a1c0e44d8 Mon Sep 17 00:00:00 2001 +From ee6d3ec9107c0fd772c16584ca526ebe78cd30b0 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:05 +0200 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 PWM diff --git a/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch b/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch index b045d4a3cf..45a30f7acd 100644 --- a/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch +++ b/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch @@ -1,4 +1,4 @@ -From d512570ff756b751d74f27121ccd6784be182855 Mon Sep 17 00:00:00 2001 +From 65a1dab86ebddc9772731df5c32673238785b7b2 Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:25:02 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: Fix Rust formatting diff --git a/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch b/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch index 06d4f3cc31..2925a46886 100644 --- a/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch +++ b/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch @@ -1,4 +1,4 @@ -From b8e48fd0e9516c83f6a6193730b5d042ed5263bd Mon Sep 17 00:00:00 2001 +From 4053bab2d005ebc6eab1680de449edd8a6e5f903 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:35 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix clippy warning for redundant diff --git a/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch b/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch index b4384ef364..212c3eab71 100644 --- a/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch +++ b/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch @@ -1,4 +1,4 @@ -From e4ad935868f5592d06155265261be5934f1821ec Mon Sep 17 00:00:00 2001 +From 8a1293a6044b839a46bfd2af6ce741fffaec1cdd Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:34 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Use module_pwm_platform_driver! diff --git a/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch b/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch index f01d4fe843..581f11f37d 100644 --- a/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch +++ b/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch @@ -1,4 +1,4 @@ -From 04ac502626ab9c23c88cb52a8447f2a6d6871231 Mon Sep 17 00:00:00 2001 +From af00b8640fb223e6e97755df058706ff91f96ad7 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 9 Dec 2025 21:06:03 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix missing Kconfig dependencies diff --git a/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch b/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch index 4f6592382a..b70ceaaef4 100644 --- a/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch +++ b/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch @@ -1,4 +1,4 @@ -From c413ed4426b184f8cb2304ff2897825e2a215871 Mon Sep 17 00:00:00 2001 +From 1cfd24d0ebea3fd30addd6ab38dfb349a1ec08be Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:47 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add xtheadvector to the diff --git a/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch b/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch index 645a855fa1..b0ae390f9e 100644 --- a/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch +++ b/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch @@ -1,4 +1,4 @@ -From d86f79c2f13ca9a4c232cce2f5dd5020f18a9656 Mon Sep 17 00:00:00 2001 +From bd68ddac12b197d63d695ebee877c658babc4935 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:48 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add ziccrse for th1520 diff --git a/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch b/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch index 02c41e4add..bd025678fa 100644 --- a/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch +++ b/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch @@ -1,4 +1,4 @@ -From 6c54c277dfd8b9c53a91aac3aa08d80a40eef35d Mon Sep 17 00:00:00 2001 +From c97f4fa9442fe9725a615f5b29d980ecb8e34e1b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:49 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add zfh for th1520 diff --git a/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch b/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch index 1da5ef41e5..2c486fced0 100644 --- a/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch +++ b/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch @@ -1,4 +1,4 @@ -From 3ca9f9c1f974516ed56055f86fe810e70234d2e0 Mon Sep 17 00:00:00 2001 +From ddfa1f0d437d597ddc5ed035dbb6fd04295dd9a1 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:06 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM controller node diff --git a/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch b/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch index 16a6ff7a16..b5eca2e20a 100644 --- a/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch +++ b/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch @@ -1,4 +1,4 @@ -From 34e6c9de17b9ff861746760bfc9334e3fc3060cb Mon Sep 17 00:00:00 2001 +From 7df49938ca1e4c3188674cf01b6d943ceea80c9b Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:07 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM fan and thermal diff --git a/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch b/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch index 073023bb11..366f7e9343 100644 --- a/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch +++ b/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch @@ -1,4 +1,4 @@ -From 185f8436e47e0844df0a0d25fbb995a69a565fd1 Mon Sep 17 00:00:00 2001 +From 6a8f49b2e92014e689c4e68927683e244639e7c1 Mon Sep 17 00:00:00 2001 From: Lucas Zampieri Date: Fri, 24 Oct 2025 09:36:40 +0100 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: Add UltraRISC diff --git a/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch b/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch index a9e42fff55..0831bef573 100644 --- a/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch +++ b/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch @@ -1,4 +1,4 @@ -From 38033dfbe309976053db7684228a93e90a76f54f Mon Sep 17 00:00:00 2001 +From b013929e5a0773eea0cce650019592024dfacecb Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:41 +0100 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: Add diff --git a/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch b/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch index c47e05232b..a38920d845 100644 --- a/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch +++ b/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch @@ -1,4 +1,4 @@ -From 3f8b27c28b0516d4675130d799e52fe0e47cc190 Mon Sep 17 00:00:00 2001 +From 370b8af4c2f631e8d3a0e7984d878a7c80ed6d18 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:42 +0100 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Cache the interrupt diff --git a/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch b/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch index 35bf32dde3..50298bada1 100644 --- a/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch +++ b/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch @@ -1,4 +1,4 @@ -From 4ef8a6c6a0ad3046bd79c8e7ba68b55f65faba37 Mon Sep 17 00:00:00 2001 +From d347e2130641f7e7091dd8afbe67c9619baf88f0 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:43 +0100 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Add support for UltraRISC diff --git a/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch b/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch index d80cdc947a..bc65b7abfc 100644 --- a/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch +++ b/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch @@ -1,4 +1,4 @@ -From 88d1fb14b13933d5016b00a18582e2c2dec28c29 Mon Sep 17 00:00:00 2001 +From 5cfe296d78b80974d17bf71f4b20c59e5c4df2e7 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 2 Jan 2026 14:58:39 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: cpu_ops_sbi: smp_processor_id() returns diff --git a/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch index 8df22862a6..a73b5bae6d 100644 --- a/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ b/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -1,4 +1,4 @@ -From b73688a2f1f8a16a7bb9609da304ebfd1dd7f968 Mon Sep 17 00:00:00 2001 +From e9bf2921885bbc475e11a6f89d7d1325bf4ea382 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:29:59 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT diff --git a/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch b/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch index 398331aef3..38f0c36ca6 100644 --- a/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch +++ b/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch @@ -1,4 +1,4 @@ -From 10c6bee274527e1fa5cf933eade792a8269bfa6e Mon Sep 17 00:00:00 2001 +From 89018ba28165fc32aa888271948560c35503a2be Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:00 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: add optional diff --git a/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch b/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch index cb7815d689..cb75c0acf5 100644 --- a/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch +++ b/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch @@ -1,4 +1,4 @@ -From eef2e7554dce124c0d27d06663f545ebf8b06b4f Mon Sep 17 00:00:00 2001 +From ea61a74942a5004fa215d79c58105f1338ec541e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:01 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add optional reset support diff --git a/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch b/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch index 78d52fb913..64929819ae 100644 --- a/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch +++ b/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch @@ -1,4 +1,4 @@ -From 01d5441431b796aa0c7bef71294e87584b3a7ac2 Mon Sep 17 00:00:00 2001 +From e1c8bcfee6e779f426c1daae2fb82866708e10a9 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:02 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: switch predicates to bool diff --git a/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch b/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch index 2a381e6fb3..a3a82feb09 100644 --- a/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch +++ b/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch @@ -1,4 +1,4 @@ -From 513e5c7ca8e7b4847c1a9fa9328ecc1da6e03ca4 Mon Sep 17 00:00:00 2001 +From 981675f3ee85d491d051c4664c508128ac988504 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:03 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add a clock disable quirk diff --git a/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch b/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch index c71778c496..246aa58431 100644 --- a/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch +++ b/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch @@ -1,4 +1,4 @@ -From a5d94c358a562e2cf863fff92b78f0ee109abf10 Mon Sep 17 00:00:00 2001 +From 7c46eafe84df109f4c91da322c3c0936ca5e6f42 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:04 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: introduce sfa_size devtype data diff --git a/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch b/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch index f9a55c89ea..13087ca9aa 100644 --- a/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch +++ b/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch @@ -1,4 +1,4 @@ -From 014a6255ae46191c6eae14aa9de40535b4226ff0 Mon Sep 17 00:00:00 2001 +From 53c83a343355c01284a123c0592f92e488eec006 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:05 -0500 Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: support the SpacemiT K1 SoC diff --git a/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch b/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch index 8ad45c9e57..6fe980dae8 100644 --- a/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch +++ b/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch @@ -1,4 +1,4 @@ -From 0d6c9d0a071fcea507cb2b62195d329fbfd4e3fa Mon Sep 17 00:00:00 2001 +From f77dddee6ad705b31db5dd8e1d46b89de99b5994 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:35 -0600 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pci: spacemit: Introduce PCIe diff --git a/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch b/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch index 15f880c23c..c80fe8da68 100644 --- a/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch +++ b/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch @@ -1,4 +1,4 @@ -From e886894eecb01fde7c6d687a520c00f8f8c6577b Mon Sep 17 00:00:00 2001 +From a27cebcdff7f78becf2072cae2b951e1e7f41b1e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:37 -0600 Subject: [RUYI PATCH] UPSTREAM: PCI: spacemit: Add SpacemiT PCIe host driver diff --git a/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch b/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch index 9f87089128..07eb7775f3 100644 --- a/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch +++ b/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch @@ -1,4 +1,4 @@ -From dd167e5e356efc521fea95cca3dab9214d112f2f Mon Sep 17 00:00:00 2001 +From 1db3accfb97de5435d3b1a655351b544f98c89c2 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:17 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: dt-bindings: Add bindings for SpacemiT diff --git a/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch b/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch index 79edb29c56..7a21b86b45 100644 --- a/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch +++ b/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch @@ -1,4 +1,4 @@ -From f80e4dd0f340bda7a0c1d1cbcb59d4a346aa00dd Mon Sep 17 00:00:00 2001 +From a978e202507f82d0e77d476e6346bc3100e2af3e Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:18 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: add i2s support for K1 SoC diff --git a/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch b/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch index 0efa4da8f2..2948efb926 100644 --- a/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch +++ b/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch @@ -1,4 +1,4 @@ -From affb820dfce75897605fbf89105fc1537a97d75b Mon Sep 17 00:00:00 2001 +From d14c1a3674a4d257ec1714aeb83e0c890a87e6fe Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 17 Sep 2025 08:59:07 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add UART pinctrl diff --git a/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch b/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch index 0351d09704..bfd2c0a2a3 100644 --- a/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch +++ b/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch @@ -1,4 +1,4 @@ -From 1df92e173f9dd68d0498d92fb07c15a5b2ddf8eb Mon Sep 17 00:00:00 2001 +From 09fc6e652c8500c58d3fe27c7be9bebf2b59bc5b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:54 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c8 adapter diff --git a/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch b/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch index 3b5e57ed41..0653225c30 100644 --- a/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch +++ b/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch @@ -1,4 +1,4 @@ -From b0c37d9383e9fff2cfae5d13e29a5b2fd134e33b Mon Sep 17 00:00:00 2001 +From 7aec3f89f4115172f971713a137996eabfdc10bb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:55 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define fixed regulators diff --git a/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch b/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch index 4b13e15e20..9a83a11db5 100644 --- a/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch +++ b/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch @@ -1,4 +1,4 @@ -From 7fc9ff12b887fdc874ebb28f553e807648b6a4d4 Mon Sep 17 00:00:00 2001 +From cc04c613686436bcdfd3c38b6ae7ea2d7241c0d7 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:56 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define regulator diff --git a/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch b/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch index c64be604a7..0e7a5aedef 100644 --- a/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch +++ b/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch @@ -1,4 +1,4 @@ -From a276be6d58f16c9c62bd6c0f76f6b2133fcfff5b Mon Sep 17 00:00:00 2001 +From 26663ffe8f0db3a92cf070903f9191745b97444f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:37 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c2 adapter diff --git a/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch b/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch index 5c72618d50..0d0bfb67b2 100644 --- a/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch +++ b/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch @@ -1,4 +1,4 @@ -From c34d30a8bde9d30953c0d83f0fa993d925f5e038 Mon Sep 17 00:00:00 2001 +From fffc0e28825613d507f1e6731d2f011415adf550 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:38 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c02 eeprom on diff --git a/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch b/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch index 3e089bc47b..f014ffc559 100644 --- a/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch +++ b/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch @@ -1,4 +1,4 @@ -From d0ff2694bd729289ac0e0a95bd0ad9c82b10cbe1 Mon Sep 17 00:00:00 2001 +From 27fd4e9ef652768f524108ac9cb344f6b83be392 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:39 +0200 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on diff --git a/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch b/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch index 2f6950c455..6a5e851bdf 100644 --- a/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch +++ b/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch @@ -1,4 +1,4 @@ -From 13fa4b662d56827d91fb4cbc78cbaf44253e90c9 Mon Sep 17 00:00:00 2001 +From 3f7306681f2f070c4888af54efa4240ca6d758a8 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 22 Oct 2025 20:18:38 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add Ethernet and PDMA to diff --git a/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch b/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch index e1ebb490cb..51c6e7be59 100644 --- a/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch +++ b/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch @@ -1,4 +1,4 @@ -From 3dafd093bd3316afd9db38030ed61ebb2382f469 Mon Sep 17 00:00:00 2001 +From 9e47855f7a253279381f70b063ba245703e3814d Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 23 Oct 2025 15:28:30 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add MusePi Pro board diff --git a/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch b/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch index 1d90bd8999..4e53d6e7ad 100644 --- a/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch +++ b/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch @@ -1,4 +1,4 @@ -From ba2b866292f1f2f274ff75a54e87fe7bc5dad3e2 Mon Sep 17 00:00:00 2001 +From 6a39505c993f5f01158a6f6a70f4ad76c6db5234 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:06 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable K1 SoC QSPI on diff --git a/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch b/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch index 6288d13917..845dd10c3b 100644 --- a/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch +++ b/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch @@ -1,4 +1,4 @@ -From 24c1c297e0c77c81c2e3a9ed9690f3e133986a22 Mon Sep 17 00:00:00 2001 +From a99210e73092a2a51e626e76bb6eb8ae63c8eb26 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 12 Nov 2025 04:44:42 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add OrangePi R2S board diff --git a/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch b/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch index d6b11da6e5..af827b2735 100644 --- a/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch +++ b/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch @@ -1,4 +1,4 @@ -From 1831ac73812e9bb0337b60cf0cbe5e61baaf4769 Mon Sep 17 00:00:00 2001 +From d6478eccb6e7703c6cda7c1146e5ed08bd362aaa Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:43 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder i2c2 node diff --git a/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch b/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch index 128376f03e..db9f77e153 100644 --- a/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch +++ b/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch @@ -1,4 +1,4 @@ -From 30931c3912167e96f982909390b4cb13d61548d5 Mon Sep 17 00:00:00 2001 +From 9a289212a972f7808021f2d5895dbff5dc2a5404 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:44 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define all missing I2C diff --git a/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch b/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch index 637f8129fd..a117d16322 100644 --- a/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch +++ b/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch @@ -1,4 +1,4 @@ -From 915b04c620188a1aac7cc9e8481bd1dc3069817d Mon Sep 17 00:00:00 2001 +From ea689de88bfd93717b97a988d285c2bcfee10d08 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 18 Nov 2025 14:08:06 +0800 Subject: [RUYI PATCH] UPSTREAM: rtc: spacemit: MFD_SPACEMIT_P1 as dependencies diff --git a/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch b/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch index 8765e4955a..0ac16df408 100644 --- a/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch +++ b/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch @@ -1,4 +1,4 @@ -From 6069d468c347c12814556df14bbe53dade5799be Mon Sep 17 00:00:00 2001 +From 22786d133cae491a4a2d7486ced9707305762fd1 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 27 Oct 2025 13:48:05 +0800 Subject: [RUYI PATCH] UPSTREAM: mfd: simple-mfd-i2c: Remove select I2C_K1 from diff --git a/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch b/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch index 29f66cd23f..a9a2a89eea 100644 --- a/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch +++ b/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch @@ -1,4 +1,4 @@ -From eef8f9cc817fec7a4c2229a9b9ee475a0efcf53b Mon Sep 17 00:00:00 2001 +From 6469b6c2dfd9d66deecc8708629891e31602adc2 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:01:59 +0100 Subject: [RUYI PATCH] UPSTREAM: driver: reset: spacemit-p1: add driver for diff --git a/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch b/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch index 9e03454da1..ab98a6d4ca 100644 --- a/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch +++ b/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch @@ -1,4 +1,4 @@ -From a33608232c9c99d13d018635c30ee0ff1983de7e Mon Sep 17 00:00:00 2001 +From 719033a111f6554842d971b2a40a5ef67c69d4d3 Mon Sep 17 00:00:00 2001 From: Yunhui Cui Date: Tue, 16 Dec 2025 09:47:19 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: remove irqflags.h inclusion in diff --git a/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch b/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch index 0fb3f34661..ee28c704dc 100644 --- a/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch +++ b/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch @@ -1,4 +1,4 @@ -From 34f41ea98d21a5605f1d5973259656f6e6557de0 Mon Sep 17 00:00:00 2001 +From db019f57db04d4ece4511823ca49186776ac1572 Mon Sep 17 00:00:00 2001 From: Zongmin Zhou Date: Thu, 20 Nov 2025 17:58:31 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv/atomic.h: use RISCV_FULL_BARRIER in diff --git a/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch b/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch index 0604111102..cf28af6f0f 100644 --- a/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch +++ b/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch @@ -1,4 +1,4 @@ -From 8030689f50a72fc225dd6c31ad77d6b868549463 Mon Sep 17 00:00:00 2001 +From 476b5a142396e7b932e3fd2d8af5632718cfb3d4 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:08 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Sanitize output on errors diff --git a/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch b/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch index c249232713..7a841d166c 100644 --- a/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch +++ b/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch @@ -1,4 +1,4 @@ -From cf1dda8a91f6866dead5cfac3205be1ea706a065 Mon Sep 17 00:00:00 2001 +From 3b06167014830657863b7333d0ed9be00567cf8f Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:09 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Provide helper to set pitch diff --git a/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch b/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch index d3d98f5867..56f4549640 100644 --- a/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch +++ b/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch @@ -1,4 +1,4 @@ -From 5a54ac19c87347a2165595055cab86383cefac4f Mon Sep 17 00:00:00 2001 +From 8050563879938dc6a528fb8e06da2fa438e114f5 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 16 Sep 2025 10:36:22 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/hypervdrm: Use vblank timer @@ -20,7 +20,7 @@ Signed-off-by: Han Gao 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -index 945b9482bcb3..6e6eb1c12a68 100644 +index 86696a9a32c5..208fb14e837a 100644 --- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c @@ -19,6 +19,8 @@ @@ -56,7 +56,7 @@ index 945b9482bcb3..6e6eb1c12a68 100644 }; static int hyperv_plane_atomic_check(struct drm_plane *plane, -@@ -321,6 +328,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) +@@ -322,6 +329,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) return ret; } diff --git a/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch b/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch index d6a9555b97..cdab38c37e 100644 --- a/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch +++ b/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch @@ -1,4 +1,4 @@ -From 82e88d4cfa7af6b1ae6ffc952a7d1903d2c8e3ea Mon Sep 17 00:00:00 2001 +From 3a566409d11abdf4ed3f08d0621eb8a348aa265f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:06 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi flag diff --git a/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch b/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch index 46bc6278e3..df245d7bd7 100644 --- a/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch +++ b/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch @@ -1,4 +1,4 @@ -From 4f4b809bc01cd7d00cf117b7e99a2a2b18a9d9f9 Mon Sep 17 00:00:00 2001 +From 9442e52784b43c32211b4e810635c32d91c7d43c Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:07 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Check the device specific address diff --git a/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch b/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch index 02e46aef2a..e53d537b75 100644 --- a/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch +++ b/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch @@ -1,4 +1,4 @@ -From 9dcbec59b17ddb9befc7e35efebe9f69ebeb2745 Mon Sep 17 00:00:00 2001 +From e81fc8efac9cdfbf8941cd958c7f14a70b05ced4 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:08 +0800 Subject: [RUYI PATCH] UPSTREAM: drm/radeon: Make MSI address limit based on diff --git a/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch b/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch index 5f8bf385cf..6a0b93617d 100644 --- a/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch +++ b/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch @@ -1,4 +1,4 @@ -From ed396d380559185d5e0dfad4f40fc5cd8c0382d1 Mon Sep 17 00:00:00 2001 +From e9d1d6424ea9a52e0ce1580012d17aa48ebc283a Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 29 Jan 2026 09:56:09 +0800 Subject: [RUYI PATCH] UPSTREAM: ALSA: hda/intel: Make MSI address limit based diff --git a/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch b/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch index 9eb8c66514..1036dd7a87 100644 --- a/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch +++ b/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch @@ -1,4 +1,4 @@ -From f4bd9635e84e4d37d8e56a08bbd43581faeddc96 Mon Sep 17 00:00:00 2001 +From e2b86dfca9b04a702a70dd90f7c6af620e01f74e Mon Sep 17 00:00:00 2001 From: Michael Orlitzky Date: Wed, 7 Jan 2026 06:29:22 -0500 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: enable hardware clock diff --git a/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch b/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch index 0d1f78cb37..b5f9d9be9b 100644 --- a/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch +++ b/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch @@ -1,4 +1,4 @@ -From 4a0cc33492f3fc8e642380ddcf6f355a4ec6cfc1 Mon Sep 17 00:00:00 2001 +From d16888fafcae066525f88c792e413cc3400018cc Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:26 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT node diff --git a/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch b/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch index 0d20c75013..4cf0b017ff 100644 --- a/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch +++ b/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch @@ -1,4 +1,4 @@ -From 05c376f7568773671fcd81b7cc92e365126410d0 Mon Sep 17 00:00:00 2001 +From bf4a8b5e720e6d5a59e0bb296f971c97f2e459ff Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:27 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: fix the node order of diff --git a/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch index 5f97d6ec8f..21e30d751b 100644 --- a/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ b/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -1,4 +1,4 @@ -From 7b375e6d39b2d52853eaff4e1f70555adadc5253 Mon Sep 17 00:00:00 2001 +From 44e1df9c4c4219596fdc954025a00aa104ddd99e Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:53 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter for diff --git a/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch b/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch index 1a8e836f5a..d90930252e 100644 --- a/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch +++ b/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch @@ -1,4 +1,4 @@ -From 4274a55a8dac98543297e2416ea7c7f40c4f641a Mon Sep 17 00:00:00 2001 +From 0c38553b279ac02b2a359a7b4819fb73a88ea124 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:54 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define fixed regulators diff --git a/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch index 1be8407564..d905650557 100644 --- a/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ b/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -1,4 +1,4 @@ -From 0af31fdff636f13c96b48c14fe2dce73dbf55dfd Mon Sep 17 00:00:00 2001 +From 0158a4cea182893db9285ae888a490568bfb0c99 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:55 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC diff --git a/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch b/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch index 51bfee722a..65e1676bda 100644 --- a/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch +++ b/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch @@ -1,4 +1,4 @@ -From 0cb6f99b1dee1c78c2cb66de8612480e505be4b7 Mon Sep 17 00:00:00 2001 +From 2b6a2bbdc6760821fd7a9064c53288bc35c8aef3 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:27 -0600 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT diff --git a/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch b/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch index 9b069cb469..1cbf2f0e1e 100644 --- a/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch +++ b/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch @@ -1,4 +1,4 @@ -From 69d5a6d06db546fbe5f911a20eff130b7eb44927 Mon Sep 17 00:00:00 2001 +From 7301cd7cc4d2125fd7d73e478e7953cb4b1231d4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:28 -0600 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe PHY diff --git a/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch b/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch index 78fc295801..a28b820967 100644 --- a/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch +++ b/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch @@ -1,4 +1,4 @@ -From ec3144e3a9c21e5c60712fe8b72eb68e9f8c120f Mon Sep 17 00:00:00 2001 +From b7b89bae19eacd45891217afe462435355afe7c4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:29 -0600 Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY diff --git a/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch b/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch index 4a013ca623..23a912fdf4 100644 --- a/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch +++ b/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch @@ -1,4 +1,4 @@ -From 1fce0749e1bf54d192dde74d2c105f51a35ab4d4 Mon Sep 17 00:00:00 2001 +From cb491457b06017d38dedbedfb07cdec5c77a8aeb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:30 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator diff --git a/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch b/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch index ba9f3b4975..ef609732b6 100644 --- a/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch +++ b/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch @@ -1,4 +1,4 @@ -From cca8801247fe6e5967002d5519f537917e6a9bf5 Mon Sep 17 00:00:00 2001 +From 8ebfab2105d336f53b29a5971f076b60a2ee5e69 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:31 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related diff --git a/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch b/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch index c158eae42a..edc74d65d0 100644 --- a/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch +++ b/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch @@ -1,4 +1,4 @@ -From f388858d4abee4592cdb3e48a66ed3c681b5801f Mon Sep 17 00:00:00 2001 +From 2b4b7b00547de7db090321cbe060f0785bbe1c2b Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:51 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: add optional diff --git a/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch b/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch index 8df67ed42a..d3b292f234 100644 --- a/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch +++ b/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch @@ -1,4 +1,4 @@ -From ed3b67eff1ecc6048f6b6a76bff5a97ff2abb964 Mon Sep 17 00:00:00 2001 +From 45a6bb02347afa594bbae7babfc102a290c50a62 Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:52 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: k1: add reset support diff --git a/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch b/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch index 19f85450fa..176bb49c3f 100644 --- a/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch +++ b/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch @@ -1,4 +1,4 @@ -From 3aa8e6c84101edb3c499478758e4a82cc230af36 Mon Sep 17 00:00:00 2001 +From 657d162bba66c43fc3a57fcd6e53ed141c7625ef Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:53 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add reset property diff --git a/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch b/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch index eae9b4c51d..1e3c5f1464 100644 --- a/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch +++ b/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch @@ -1,4 +1,4 @@ -From 9d8fbb22b0d4fc7ec75661abcee3d71ca556f67a Mon Sep 17 00:00:00 2001 +From ad6fa0373403bcbf2e3a081de0862952e93bf85a Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 17 Oct 2025 22:49:52 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY diff --git a/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch b/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch index dd0a27e19d..ce5ed07b8d 100644 --- a/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch +++ b/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch @@ -1,4 +1,4 @@ -From 6fe75e59d1834ffff41681bcd52b6a1a83446f3e Mon Sep 17 00:00:00 2001 +From 978937fc8ad0698573d5ac3329dbeda4e1271432 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Fri, 17 Oct 2025 22:49:53 +0800 Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY diff --git a/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch b/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch index dc4568a151..33133ebf9d 100644 --- a/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch +++ b/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch @@ -1,4 +1,4 @@ -From 11169d35e4ee7faf38d3e24da227dd6ca781964d Mon Sep 17 00:00:00 2001 +From 2b433a56c490efe1d3b7f1959b4a3d984435e597 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:02 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for K1 diff --git a/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch b/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch index f327e7bfc3..3ade8356be 100644 --- a/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch +++ b/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch @@ -1,4 +1,4 @@ -From f38cd0cdcf8e8fecf3db47eb57caf5849e92aa36 Mon Sep 17 00:00:00 2001 +From 60ab55f64eb13e9141c5bcfb1ff3cc4e60bb4da3 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:03 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0 diff --git a/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch b/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch index ada9b260b3..160d49673d 100644 --- a/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch +++ b/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch @@ -1,4 +1,4 @@ -From 35bdc15291717adfaa52c4c9d060b5da8fac5ddf Mon Sep 17 00:00:00 2001 +From 10b5f752d64626320eaaf74011f5529216f78b0c Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:04 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on diff --git a/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch b/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch index 3e646a9468..38f67b4381 100644 --- a/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch +++ b/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch @@ -1,4 +1,4 @@ -From 58100bb2e0beb94bf6f7d14ee1fbc0ba755686ab Mon Sep 17 00:00:00 2001 +From 478df24a60b0581f53a916963c82d8343aafd642 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:22 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: convert drive diff --git a/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch b/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch index 39afc5d902..d442eb6694 100644 --- a/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch +++ b/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch @@ -1,4 +1,4 @@ -From 2038df152864bcab073a9afa519466c854b79d21 Mon Sep 17 00:00:00 2001 +From 5faf2537137da89b63a6dd0f45db560e43884bb2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:23 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC diff --git a/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch b/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch index 36707ca688..026ce4fb40 100644 --- a/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch +++ b/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch @@ -1,4 +1,4 @@ -From fa64b4a9c989f85c6522c5cb06ef127c6dab3d27 Mon Sep 17 00:00:00 2001 +From 2ca77029c54bb4a4d9a85faca5542299e38f0282 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:24 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: add initial pin support diff --git a/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch b/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch index 1885c27345..fe01a940c1 100644 --- a/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch +++ b/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch @@ -1,4 +1,4 @@ -From 57250a2d8e90085ff17ab7670d16519f41b64f28 Mon Sep 17 00:00:00 2001 +From dd0d5ad91e6226005daefdfc363c05a7c4089dfd Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 2 Jan 2026 15:00:25 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: adjust drive strength diff --git a/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch b/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch index b203991c2d..d3156e2bc5 100644 --- a/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch +++ b/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch @@ -1,4 +1,4 @@ -From f3a4b85d5279965fc53d7163a005b2e64ff1327a Mon Sep 17 00:00:00 2001 +From 4d3f2ca4b8bf03c8f5764bd4e3a4755a87d96507 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:38 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon diff --git a/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch b/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch index 377503eb76..0b5aeb4e99 100644 --- a/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch +++ b/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch @@ -1,4 +1,4 @@ -From 0a07233b0f550ed136cd45130d55ac5e079fc795 Mon Sep 17 00:00:00 2001 +From 4ca7dd892e3dbd74973376cc721c85ece7df006b Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:39 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: support I/O power domain diff --git a/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch b/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch index 8f6837bba8..a953ffe5db 100644 --- a/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch +++ b/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch @@ -1,4 +1,4 @@ -From 404911e71521a30847ea8198f0e48c7d6c92dac5 Mon Sep 17 00:00:00 2001 +From 7e7f51d3fc168ccbde756bef719027fd2756f3b9 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:40 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pinctrl: update register diff --git a/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch b/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch index 9c1db3eb89..8b8b633d02 100644 --- a/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch +++ b/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch @@ -1,4 +1,4 @@ -From 33a192939d2dd110bc17a0f1c65a5c654c617d16 Mon Sep 17 00:00:00 2001 +From 1f57c45be3689590c431a322325a942d2901e7ec Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 25 Dec 2025 14:24:20 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: update ratified version of diff --git a/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch b/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch index 03b356c1c3..8632f73349 100644 --- a/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch +++ b/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch @@ -1,4 +1,4 @@ -From 8b082ec91bd4cfaf11f3a1b69d1b66ea599ba3f1 Mon Sep 17 00:00:00 2001 +From 8425255e16de969339af85fd2795543cf2be9c01 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:18 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add B ISA extension diff --git a/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch b/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch index f6b09dc50b..c652ef40f1 100644 --- a/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch +++ b/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch @@ -1,4 +1,4 @@ -From 293192824603c354264f56113a64fc91d889d750 Mon Sep 17 00:00:00 2001 +From 6cbec3202b4d49296d75d3affadb5eefe4743984 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:19 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add descriptions for diff --git a/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch b/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch index 347e39618f..099030ead4 100644 --- a/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch +++ b/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch @@ -1,4 +1,4 @@ -From 9f1f119c5d51420861951a5660e8714b87fcf2ce Mon Sep 17 00:00:00 2001 +From d0ef39b0cd8f2f7fdd998909bc6ee021fe3ac16c Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:20 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Ssccptr, Sscounterenw, diff --git a/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch b/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch index f4ee934072..47fccd8d5c 100644 --- a/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch +++ b/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch @@ -1,4 +1,4 @@ -From 1642e810c6656b4e941561a7bb884e733c44a2f6 Mon Sep 17 00:00:00 2001 +From 1d68e1c298a704de7dcb9aa56f680650c887b572 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:21 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Sha and its comprised diff --git a/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch b/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch index 7eef93f3d7..a783a6a155 100644 --- a/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch +++ b/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch @@ -1,4 +1,4 @@ -From 815614b3265facda28aaa4572e120d8f049a9c79 Mon Sep 17 00:00:00 2001 +From 6c758ac967a8de6127491a395f361b7031c10667 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:59 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA diff --git a/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch b/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch index 1f0aba5728..908e74991b 100644 --- a/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch +++ b/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch @@ -1,4 +1,4 @@ -From 039b44e9b855295ac8945486ffea47d65240d000 Mon Sep 17 00:00:00 2001 +From e145877df03e9a22048d70a6df37565741c52bef Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:19:00 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA diff --git a/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch b/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch index 8f2845d570..9cc4198638 100644 --- a/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch +++ b/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch @@ -1,4 +1,4 @@ -From 3a49674fb8ec24236b9a789e322ccc05b66c4d65 Mon Sep 17 00:00:00 2001 +From da3921d821fb8fc226467e03f7c4e9547f1bebef Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:40 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU diff --git a/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch b/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch index 10acec0266..ad33a9bcb8 100644 --- a/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch +++ b/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch @@ -1,4 +1,4 @@ -From 9e4be2e7c734325e83668eba93f9e2dbc1220efa Mon Sep 17 00:00:00 2001 +From de3d7ed88147aebae73ec5f42e045e4238eae7a3 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:41 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT diff --git a/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch index f8b908b4e1..581f2654b6 100644 --- a/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ b/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -1,4 +1,4 @@ -From 57ea95edd2da52d808cbd5a6d874d1cb368dea05 Mon Sep 17 00:00:00 2001 +From 0c563395177127fadd547b5db1ccfd04a9c16977 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:42 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add diff --git a/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch index 9699a897cf..7bae75be65 100644 --- a/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ b/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -1,4 +1,4 @@ -From 7d7a00a794501c279b94f46e44c33a60cc0ecf71 Mon Sep 17 00:00:00 2001 +From ef6567dabee9b15b35444d738ddd223bba73bbaf Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:43 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add diff --git a/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch b/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch index 0f66a78fa3..eb346ddbd0 100644 --- a/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch +++ b/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch @@ -1,4 +1,4 @@ -From 90385ee4dee92d3b318cb4a03b5de245c87b06f2 Mon Sep 17 00:00:00 2001 +From 8e6028a04fddc05779e162a8306ec8f0e290946a Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:44 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and diff --git a/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch b/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch index f038974db6..49c6e610c1 100644 --- a/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch +++ b/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch @@ -1,4 +1,4 @@ -From b4a0b52d7cdbe329b44301f63847faf1c8631060 Mon Sep 17 00:00:00 2001 +From d8089feae87ad613be7fe448ae79b3f785e8744b Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:45 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add initial support for diff --git a/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch b/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch index f252517e9d..47897f776b 100644 --- a/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch +++ b/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch @@ -1,4 +1,4 @@ -From 377151dae3f25558fd27556e52c4f0854c988c8b Mon Sep 17 00:00:00 2001 +From 61e63997cecc9eb549744cbe7688cd6f77265382 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:46 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board diff --git a/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch b/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch index ec9ea29ffd..afef29e668 100644 --- a/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch +++ b/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch @@ -1,4 +1,4 @@ -From 2503ec0c2acbeba44796cf9a39cd65176b1b41b8 Mon Sep 17 00:00:00 2001 +From 75570444f9b7f29881d04479bc6f1727d37f53b6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 19 Dec 2025 09:28:18 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: Hide common clock driver from diff --git a/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch b/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch index 02f0837e38..2b42a0972e 100644 --- a/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch +++ b/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch @@ -1,4 +1,4 @@ -From 5fd55e32b05d7b1c89471933925ea500ab96dc8f Mon Sep 17 00:00:00 2001 +From 58da181f8fee4e3f7af2a1cfe8708acb62d1b3f2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 21:52:08 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: prepare common ccu header diff --git a/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch b/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch index 07bf26b3d3..5dc8e89514 100644 --- a/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch +++ b/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch @@ -1,4 +1,4 @@ -From 882ae01390f0d71acbaa666ad62660f1690558cb Mon Sep 17 00:00:00 2001 +From c52fe85b94bae057810710b424cbb6f7497aa8d7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 08:07:23 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: extract common ccu functions diff --git a/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch b/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch index 195fb33162..b8301bbf76 100644 --- a/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch +++ b/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch @@ -1,4 +1,4 @@ -From 597e2f7d18294ec1b59dc52d5be6ac61f4ef6075 Mon Sep 17 00:00:00 2001 +From 1dadb848fd39698b7cecc8d424161d3a1652a452 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 3 Jan 2026 14:14:36 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: add platform SoC prefix to diff --git a/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch b/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch index 1bbdfdf4b9..f2bd1b002d 100644 --- a/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch +++ b/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch @@ -1,4 +1,4 @@ -From 195ce637ead66f8aff72ecf491637b937ab32985 Mon Sep 17 00:00:00 2001 +From 37095deb7ea0ea8d388930e4fdf433a994d29c51 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 05:34:39 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: fix auxiliary device id diff --git a/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch b/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch index eb8a0da4ac..5b0b3c0bbf 100644 --- a/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch +++ b/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch @@ -1,4 +1,4 @@ -From 4887997f9fc66c19a62763d21f3beb9036a5470b Mon Sep 17 00:00:00 2001 +From 49261bf8d197d630f32c6a54165fcbe3aad3c5cc Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 1 Nov 2025 20:56:42 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: k3: add clock diff --git a/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch b/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch index 3bd158963f..96035ae024 100644 --- a/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch +++ b/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch @@ -1,4 +1,4 @@ -From f461f20d8d5d33bdf1d9fa07acf5a6337f03e57c Mon Sep 17 00:00:00 2001 +From 7c8f2552576b5ef6a1ae9a1bd2b110a50dcf3633 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 31 Oct 2025 20:40:46 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_mix: add inverted enable diff --git a/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch b/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch index 6dfcedf96e..2ddb21e2b7 100644 --- a/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch +++ b/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch @@ -1,4 +1,4 @@ -From a7ce4c7a2f5e9b248b21befc2f291b0d3ae3b195 Mon Sep 17 00:00:00 2001 +From f7657a9e6b3d91927ebb7a35c3f3092378c5f8aa Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 27 Oct 2025 21:41:24 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_pll: add plla type clock diff --git a/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch b/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch index 8ce677d1e4..a98118158f 100644 --- a/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch +++ b/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch @@ -1,4 +1,4 @@ -From 22c56093a5cbcc8d011f81d4523ee8160d5caa5f Mon Sep 17 00:00:00 2001 +From c5d576f1d3fffff794dcb2f9bfce1fd8afbbef56 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 20 Dec 2025 21:28:15 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: extract common header diff --git a/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch b/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch index ca7b6c2396..3125f4a4ed 100644 --- a/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch +++ b/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch @@ -1,4 +1,4 @@ -From 878e4e3217cc3b8b51d6d5480b8c6c8120d47144 Mon Sep 17 00:00:00 2001 +From dab0ffb790023615ccdc8e736b12d107c416cc83 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sun, 2 Nov 2025 21:17:17 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: add the clock tree diff --git a/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch b/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch index c049403590..0e13a0bee6 100644 --- a/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch +++ b/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch @@ -1,4 +1,4 @@ -From c8b8aab18243d5ad3ee4a6b980f1448aee344adb Mon Sep 17 00:00:00 2001 +From 566fcedda50493fdac4cf1d88354555164577b90 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:49 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: Add K3 reset diff --git a/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch b/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch index 6775e0de91..c8f32ba7a9 100644 --- a/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch +++ b/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch @@ -1,4 +1,4 @@ -From f58dcbda59da2a11300427e92f4c1abb7c6898f7 Mon Sep 17 00:00:00 2001 +From e0766e7503cd6e4f874013061c4df306cf4a9540 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:50 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: Create subdirectory for SpacemiT diff --git a/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch b/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch index 326c078c60..5218ff3c62 100644 --- a/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch +++ b/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch @@ -1,4 +1,4 @@ -From 1928fc1030c03e43f009ef60762dac1829c39b0c Mon Sep 17 00:00:00 2001 +From b2aa1a3066056632c7182ef5ac38340b5b14f5f9 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:51 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Extract common K1 reset code diff --git a/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch b/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch index 3e39a6ab56..251d00a39b 100644 --- a/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch +++ b/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch @@ -1,4 +1,4 @@ -From ba7026a22c43e830be9a0dccce75c3867b2bcaad Mon Sep 17 00:00:00 2001 +From 4c225ec987cb2053efdd142d8abf8bb02ebb1121 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:52 +0800 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Add SpacemiT K3 reset driver diff --git a/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch b/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch index 87f1321e5c..fc4d1c180c 100644 --- a/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch +++ b/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch @@ -1,4 +1,4 @@ -From 69b50555993d0e015534df599be1be5f756f84ea Mon Sep 17 00:00:00 2001 +From 404eff5e632be9663a75c9d1c490d8f56b121d6b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 6 Jan 2026 11:09:32 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: gpio: spacemit: add compatible diff --git a/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch b/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch index 7b6a45b12a..e442687036 100644 --- a/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch +++ b/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch @@ -1,4 +1,4 @@ -From 409dadffdee997565a81b01180b046890adbdd47 Mon Sep 17 00:00:00 2001 +From 5926baabc063083c74e19f79f6caa78d3830e043 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 6 Jan 2026 11:09:33 +0800 Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit: Add GPIO support for K3 SoC diff --git a/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch b/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch index a2882d0c20..8f33f33fb9 100644 --- a/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch +++ b/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch @@ -1,4 +1,4 @@ -From ea85c56c78cbe48a0e645e57bb5d0151fa6f9bfa Mon Sep 17 00:00:00 2001 +From c0f9160d762fe57a9b53602372b37198d2ad5fc2 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 20 Jan 2026 18:00:01 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Disable ETH PHY sleep diff --git a/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch b/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch index 412075183b..46720dd038 100644 --- a/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch +++ b/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch @@ -1,4 +1,4 @@ -From 8731712faebb3034f523e3ed6e95191f5e47a01b Mon Sep 17 00:00:00 2001 +From 773b8c05e06091b578891911eeff117b405029a2 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:10 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: clock: thead,th1520-clk-ap: Add diff --git a/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch b/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch index e28d1d6f4f..64f304df30 100644 --- a/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch +++ b/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch @@ -1,4 +1,4 @@ -From 43765d604a0ac503f549b2772fc89a67b6df8779 Mon Sep 17 00:00:00 2001 +From 633624709863afc1b51408b875f42181a2e72fb2 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:12 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add C910 bus clock diff --git a/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch b/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch index 0f3eeb5de1..ce108a583e 100644 --- a/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch +++ b/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch @@ -1,4 +1,4 @@ -From 00eda1e45b3379884782a9a27d245fcff13f8772 Mon Sep 17 00:00:00 2001 +From 45fffc60883bc1f85479379c30d0c9771bf2d73b Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:13 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support setting PLL diff --git a/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch b/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch index 2518407886..628f0a6d60 100644 --- a/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch +++ b/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch @@ -1,4 +1,4 @@ -From 17338e1f386a810ea7bbe685d7cf3953dae6a51f Mon Sep 17 00:00:00 2001 +From 52617b1d3610227d206fb38f5fde1cfeeb213fbb Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:14 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add macro to define diff --git a/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch b/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch index 5e088a3818..4aa1be25ed 100644 --- a/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch +++ b/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch @@ -1,4 +1,4 @@ -From fc08e30c489223facf41c8c180c1d3685bad9ee9 Mon Sep 17 00:00:00 2001 +From bc39dc8773ca6dc48b317957a658017dbde02f04 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:15 +0000 Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support CPU frequency diff --git a/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch b/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch index ee84bea6d5..f0b4698266 100644 --- a/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch +++ b/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch @@ -1,4 +1,4 @@ -From 216580fd5ff0f2f9d1b045a0eebd53199b169c09 Mon Sep 17 00:00:00 2001 +From 8f647c44bb22dd0196ff6853795c4f0184e64b0f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 1 Feb 2026 18:00:01 +0800 Subject: [RUYI PATCH] UPSTREAM: net: spacemit: display phy driver information diff --git a/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch b/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch index 71279bcd12..c255e2902b 100644 --- a/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch +++ b/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch @@ -1,4 +1,4 @@ -From a000c3124b2434f1d7da679574181a5b8295c9b8 Mon Sep 17 00:00:00 2001 +From c782e1f412db9ce5888fcbe1308dba4c872f3c6f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 27 Jan 2026 10:58:49 +0800 Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Use PDR for pin direction, diff --git a/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch b/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch index 315761b942..acdbf52e2f 100644 --- a/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch +++ b/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch @@ -1,4 +1,4 @@ -From 9a9a68a7eddae8077db583fd6db0e31a7e837eab Mon Sep 17 00:00:00 2001 +From aa414e48229dc861d14cbbc8f68b96518d390f55 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Fri, 26 Dec 2025 11:32:27 -0600 Subject: [RUYI PATCH] UPSTREAM: phy: Kconfig: spacemit: add COMMON_CLK diff --git a/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch b/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch index 661b7fce58..458610c6be 100644 --- a/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch +++ b/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch @@ -1,4 +1,4 @@ -From 13956aef479172118fb402bab2ecea2f30a4a744 Mon Sep 17 00:00:00 2001 +From a0a9fabc15452e81c179b036d17a57ed00e1ba9d Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 25 Dec 2025 15:46:32 +0800 Subject: [RUYI PATCH] UPSTREAM: mfd: Kconfig: Default MFD_SPACEMIT_P1 to 'm' diff --git a/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch b/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch index f0ab6e429d..a272afc143 100644 --- a/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch +++ b/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch @@ -1,4 +1,4 @@ -From c37e910069a44317c77ac4d11b37028e5c7a3473 Mon Sep 17 00:00:00 2001 +From a4fc20e9548ce112196421b63ebe0ae151978397 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 23 Dec 2025 10:24:51 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: sdhci: add reset support diff --git a/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch b/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch index d3ca21faa5..0a8bbb6113 100644 --- a/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch +++ b/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch @@ -1,4 +1,4 @@ -From cbbdae1821a5dd4f90a95e88d5c536f2421da1b6 Mon Sep 17 00:00:00 2001 +From f2ab06c62c043be194f5704ea040192c919d5ab1 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Mon, 3 Nov 2025 11:18:13 -0500 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Fix call to diff --git a/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch b/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch index a2ed1e4b8d..ff85f56c29 100644 --- a/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch +++ b/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch @@ -1,4 +1,4 @@ -From d25027971bf83bf11dd914b3ce914fa9ada558c4 Mon Sep 17 00:00:00 2001 +From 01c7afb37293f8274d577acd592a1c6f97b8fbef Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Wed, 4 Feb 2026 01:21:48 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: diff --git a/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch b/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch index b6309ec5fd..8508268b39 100644 --- a/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch +++ b/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch @@ -1,4 +1,4 @@ -From 8c3cf0715b0fdf641d78f56c2a4a207b6fb93525 Mon Sep 17 00:00:00 2001 +From 2aa0cd948f924b6efe91a62370729599c711b60c Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 3 Feb 2026 20:16:12 +0100 Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Handle number of hardware diff --git a/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch b/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch index ec4bffaa6b..d60263eb5b 100644 --- a/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch +++ b/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch @@ -1,4 +1,4 @@ -From fd2ed2a093642f9ae52054344b23d1c512e4d4b6 Mon Sep 17 00:00:00 2001 +From 395317c0c69e903fa5a663ebf87b3f57ee0c3aa7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 9 Jan 2026 19:34:30 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Use multiple iATU windows for diff --git a/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch b/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch index 35a46d601c..6bc42d0c73 100644 --- a/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch +++ b/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch @@ -1,4 +1,4 @@ -From b88d7d9315cd6748d47a8ced520004d8f68ec0fc Mon Sep 17 00:00:00 2001 +From 1474b5e2b184b4ebd68e60bf501ee8c8940bbfc2 Mon Sep 17 00:00:00 2001 From: Thomas Gerner Date: Tue, 20 Jan 2026 09:59:26 +0100 Subject: [RUYI PATCH] UPSTREAM: pinctrl: th1520: Fix typo diff --git a/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch b/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch index 88cfd245f1..e11d1b87ef 100644 --- a/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch +++ b/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch @@ -1,4 +1,4 @@ -From e3974191639e3270eddc65bb437b729a750e5dc7 Mon Sep 17 00:00:00 2001 +From 3925d60ee24f34a9cdb4d9014b867388be990164 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:56 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add module support for platform diff --git a/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch b/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch index 53a32a761a..65e6563973 100644 --- a/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch +++ b/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch @@ -1,4 +1,4 @@ -From 3918539e5418b2d1151b2a2e086601ded67796a3 Mon Sep 17 00:00:00 2001 +From 0bece09cf85e2707fde8ad276dd6c46b150d6097 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:57 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Split PCIe controller header diff --git a/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch b/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch index 666272aa6c..a170a309af 100644 --- a/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch +++ b/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch @@ -1,4 +1,4 @@ -From 4fb7d19f2e7e5112722787c8f89b8ca56f6943be Mon Sep 17 00:00:00 2001 +From 1eb042051f3e2906d1caa4c5ab624056b0991758 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:58 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Move PCIe RP common functions to diff --git a/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch b/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch index c0c607ce23..17aeae1b45 100644 --- a/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch +++ b/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch @@ -1,4 +1,4 @@ -From 169a3b6c0054a1a90e9a56316ce2530a6e1d21ad Mon Sep 17 00:00:00 2001 +From 3a5a11f7bc5c3ab8c769fc5b75f92bd4c1da3788 Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Sat, 8 Nov 2025 22:02:59 +0800 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add support for High Perf diff --git a/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch b/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch index 45d4cc96d9..b2abcc9136 100644 --- a/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch +++ b/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch @@ -1,4 +1,4 @@ -From 668b64875b3a39ad0c809fd84baba5596b3f93c1 Mon Sep 17 00:00:00 2001 +From 44e86a41e45f097ea3716174df8988299502fbf4 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:49:55 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use phylink's interface mode diff --git a/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch b/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch index e6e34a7195..1c8feb9296 100644 --- a/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch +++ b/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch @@ -1,4 +1,4 @@ -From 821bb874c9ee51f801501a53f0bfaff22992f2fb Mon Sep 17 00:00:00 2001 +From 43f0647cb3c08ebc84b841e37b0d55747e913beb Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:00 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: s32: move PHY_INTF_SEL_x diff --git a/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch b/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch index 2109b174e4..a21895259f 100644 --- a/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch +++ b/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch @@ -1,4 +1,4 @@ -From 90e4dd06e790973bb6661abbcb3f3e584ec56f1e Mon Sep 17 00:00:00 2001 +From 117b92c58e2f5cd407352654edc8faf142ee0657 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:05 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add phy_intf_sel and ACTPHYIF diff --git a/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch index 9a20bd485f..1ee02b4963 100644 --- a/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch +++ b/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch @@ -1,4 +1,4 @@ -From 624275e49ff1dc397c4e821f30d8afcc4c8f621e Mon Sep 17 00:00:00 2001 +From 113a8840b97620b513498119a2b35fbf442c0c9b Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:10 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add stmmac_get_phy_intf_sel() @@ -33,7 +33,7 @@ index 865531d6cd3b..a628b5039448 100644 int stmmac_suspend(struct device *dev); void stmmac_dvr_remove(struct device *dev); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 41b270a48630..efe313a59b33 100644 +index 1ceedd74e429..bd705136ccc0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3035,6 +3035,26 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv) diff --git a/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch b/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch index b7fa7e6a46..5e6fdda67c 100644 --- a/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch +++ b/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch @@ -1,4 +1,4 @@ -From f194dd514161599163226c56b2674969caea19ca Mon Sep 17 00:00:00 2001 +From d63a611184e9b8f84b7f4aefa950b64c8da7edc1 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:15 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add support for configuring the @@ -22,7 +22,7 @@ Signed-off-by: Han Gao 2 files changed, 35 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index efe313a59b33..0f7fda75f7fe 100644 +index bd705136ccc0..e86b1378bc8b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3055,6 +3055,36 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface) diff --git a/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch b/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch index 9563df2a93..d68f286dd0 100644 --- a/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch +++ b/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch @@ -1,4 +1,4 @@ -From 89d282d18f9a93cdff176ee6469c67a8b11cb528 Mon Sep 17 00:00:00 2001 +From 0bbb0e593c104ca6db38519b0f2e01d0a565288d Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:21 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: convert to PHY_INTF_SEL_xxx diff --git a/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch b/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch index 3546e04959..16f424bc0b 100644 --- a/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch +++ b/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch @@ -1,4 +1,4 @@ -From cc8ade8e3e83180c2b2c2458f61161c29f310f53 Mon Sep 17 00:00:00 2001 +From 9115a394b543402831d6296170c8473755216a9b Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:26 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use FIELD_PREP()/FIELD_GET() diff --git a/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch index 133ab7846d..3b77c41813 100644 --- a/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch +++ b/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch @@ -1,4 +1,4 @@ -From c242a53cab013ff50b42785236d0b703b63c9e37 Mon Sep 17 00:00:00 2001 +From a3036bb05f0f0ba49141f757e8a9c682124b897f Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:31 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use diff --git a/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch b/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch index cc5171568d..2755d3b7f6 100644 --- a/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch +++ b/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch @@ -1,4 +1,4 @@ -From 38044c901de858463843f7c8cfab808a34627f56 Mon Sep 17 00:00:00 2001 +From 316608f6a973202aecff9d544c0c8df73b28974f Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:36 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: simplify set_intf_mode() diff --git a/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch b/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch index 7f2c908494..eb07230bdb 100644 --- a/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch +++ b/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch @@ -1,4 +1,4 @@ -From 3c89184f3302aafeabc618409bf916aa970f4f16 Mon Sep 17 00:00:00 2001 +From 7c1bcafe332511c19de7c7ac676bb3858d39410c Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:41 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: cleanup arguments for diff --git a/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch b/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch index 20bb16df38..24dab4413e 100644 --- a/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch +++ b/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch @@ -1,4 +1,4 @@ -From e0a6c2e873b5d2ba2e3a62461407c4523f488812 Mon Sep 17 00:00:00 2001 +From 1eabcd14c3a8ae06847f6a7af868db90fdd417d2 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Mon, 3 Nov 2025 11:50:46 +0000 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use ->set_phy_intf_sel() diff --git a/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch b/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch index f73e1f62b4..b6df6f8e72 100644 --- a/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch +++ b/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch @@ -1,4 +1,4 @@ -From d219e86b2ba446033884ed9b3f3cb9d0edcd98ef Mon Sep 17 00:00:00 2001 +From eadf535b70265b367eb6619033594dad637807b2 Mon Sep 17 00:00:00 2001 From: Nilay Shroff Date: Fri, 20 Feb 2026 12:32:27 +0530 Subject: [RUYI PATCH] UPSTREAM: powerpc/pci: Initialize msi_addr_mask for diff --git a/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch b/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch index e75eecbde3..a3aa543955 100644 --- a/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch +++ b/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch @@ -1,4 +1,4 @@ -From 9e9a5cb4c3cd15b6b321a0ec71d41d8318cfd254 Mon Sep 17 00:00:00 2001 +From 2b9cdafd6924c78f840a81079b9b3460ca015f62 Mon Sep 17 00:00:00 2001 From: Nilay Shroff Date: Fri, 20 Feb 2026 12:32:28 +0530 Subject: [RUYI PATCH] UPSTREAM: sparc/PCI: Initialize msi_addr_mask for diff --git a/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch b/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch index 9f8cb3b4b0..b7814169fb 100644 --- a/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch +++ b/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch @@ -1,4 +1,4 @@ -From 94993ae18a9db8b1a6f5939a8bfc465712f0e760 Mon Sep 17 00:00:00 2001 +From a2a523e92eddce6fd85a0553540d59423a4b779d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 29 Oct 2025 17:33:30 +0100 Subject: [RUYI PATCH] UPSTREAM: syscore: Pass context data to callbacks @@ -700,7 +700,7 @@ index 6f63b90f9e1a..e7807356dfab 100644 spin_lock(&rac_lock); reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c -index 46036d98da75..8b2fcb3fb874 100644 +index 5d6a60294fb2..24f947e4b219 100644 --- a/arch/loongarch/kernel/smp.c +++ b/arch/loongarch/kernel/smp.c @@ -535,28 +535,32 @@ int hibernate_resume_nonboot_cpu_disable(void) @@ -2903,7 +2903,7 @@ index b19bc60cc627..3372e1f90561 100644 static void psci_idle_init_cpuhp(void) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c -index 441ba95b38cf..647b6f4861b7 100644 +index dbdf0f41b6bb..12f11a6c9665 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -675,7 +675,7 @@ static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { @@ -3034,10 +3034,10 @@ index 7f6a62f5d1ee..1938ffa2f4f3 100644 } diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c -index 3ab62277b6be..7000e2a5511f 100644 +index 137cf82e2292..40646ddaf3fe 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c -@@ -2861,7 +2861,7 @@ static void hv_crash_handler(struct pt_regs *regs) +@@ -2907,7 +2907,7 @@ static void hv_crash_handler(struct pt_regs *regs) hv_synic_disable_regs(cpu); }; @@ -3046,7 +3046,7 @@ index 3ab62277b6be..7000e2a5511f 100644 { /* * When we reach here, all the non-boot CPUs have been offlined. -@@ -2888,7 +2888,7 @@ static int hv_synic_suspend(void) +@@ -2934,7 +2934,7 @@ static int hv_synic_suspend(void) return 0; } @@ -3055,7 +3055,7 @@ index 3ab62277b6be..7000e2a5511f 100644 { hv_synic_enable_regs(0); -@@ -2900,11 +2900,15 @@ static void hv_synic_resume(void) +@@ -2946,11 +2946,15 @@ static void hv_synic_resume(void) } /* The callbacks run only on CPU0, with irqs_disabled. */ @@ -3072,7 +3072,7 @@ index 3ab62277b6be..7000e2a5511f 100644 static int __init hv_acpi_init(void) { int ret; -@@ -2947,7 +2951,7 @@ static int __init hv_acpi_init(void) +@@ -2993,7 +2997,7 @@ static int __init hv_acpi_init(void) hv_setup_kexec_handler(hv_kexec_handler); hv_setup_crash_handler(hv_crash_handler); @@ -3081,7 +3081,7 @@ index 3ab62277b6be..7000e2a5511f 100644 return 0; -@@ -2961,7 +2965,7 @@ static void __exit vmbus_exit(void) +@@ -3007,7 +3011,7 @@ static void __exit vmbus_exit(void) { int cpu; @@ -4839,10 +4839,10 @@ index c7dcccc5f3d6..c07e562ee4c1 100644 } device_initcall(timekeeping_init_ops); diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c -index 46581554abfb..3ec22d034e73 100644 +index 8d55bbc6f34a..c75fea0c9bad 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c -@@ -5629,7 +5629,7 @@ static int kvm_offline_cpu(unsigned int cpu) +@@ -5630,7 +5630,7 @@ static int kvm_offline_cpu(unsigned int cpu) return 0; } @@ -4851,7 +4851,7 @@ index 46581554abfb..3ec22d034e73 100644 { /* * Disable hardware virtualization and set kvm_rebooting to indicate -@@ -5647,7 +5647,7 @@ static void kvm_shutdown(void) +@@ -5648,7 +5648,7 @@ static void kvm_shutdown(void) on_each_cpu(kvm_disable_virtualization_cpu, NULL, 1); } @@ -4860,7 +4860,7 @@ index 46581554abfb..3ec22d034e73 100644 { /* * Secondary CPUs and CPU hotplug are disabled across the suspend/resume -@@ -5664,7 +5664,7 @@ static int kvm_suspend(void) +@@ -5665,7 +5665,7 @@ static int kvm_suspend(void) return 0; } @@ -4869,7 +4869,7 @@ index 46581554abfb..3ec22d034e73 100644 { lockdep_assert_not_held(&kvm_usage_lock); lockdep_assert_irqs_disabled(); -@@ -5672,12 +5672,16 @@ static void kvm_resume(void) +@@ -5673,12 +5673,16 @@ static void kvm_resume(void) WARN_ON_ONCE(kvm_enable_virtualization_cpu()); } @@ -4887,7 +4887,7 @@ index 46581554abfb..3ec22d034e73 100644 int kvm_enable_virtualization(void) { int r; -@@ -5694,7 +5698,7 @@ int kvm_enable_virtualization(void) +@@ -5695,7 +5699,7 @@ int kvm_enable_virtualization(void) if (r) goto err_cpuhp; @@ -4896,7 +4896,7 @@ index 46581554abfb..3ec22d034e73 100644 /* * Undo virtualization enabling and bail if the system is going down. -@@ -5716,7 +5720,7 @@ int kvm_enable_virtualization(void) +@@ -5717,7 +5721,7 @@ int kvm_enable_virtualization(void) return 0; err_rebooting: @@ -4905,7 +4905,7 @@ index 46581554abfb..3ec22d034e73 100644 cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); err_cpuhp: kvm_arch_disable_virtualization(); -@@ -5732,7 +5736,7 @@ void kvm_disable_virtualization(void) +@@ -5733,7 +5737,7 @@ void kvm_disable_virtualization(void) if (--kvm_usage_count) return; diff --git a/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch b/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch index 778297758c..204163fd5e 100644 --- a/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch +++ b/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch @@ -1,4 +1,4 @@ -From dc079d2d3ef26e7fc9ba38e7af9c67873ed5fc55 Mon Sep 17 00:00:00 2001 +From 6dc6cd1f8b082a07a30cb10ffb8a1403350e506b Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Tue, 2 Dec 2025 14:07:41 +0800 Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Preserve APLIC states diff --git a/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch b/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch index 9ede52445f..c7285fc313 100644 --- a/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch +++ b/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch @@ -1,4 +1,4 @@ -From 9030f2dc70b9b4bd8e20de88dcbbd8afa905d20e Mon Sep 17 00:00:00 2001 +From b767d9568f3b66f92d69207f325a2b16a652c531 Mon Sep 17 00:00:00 2001 From: Jessica Liu Date: Tue, 10 Mar 2026 14:16:00 +0800 Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Do not clear ACPI diff --git a/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch b/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch index 7e5c262b22..85281a4886 100644 --- a/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch +++ b/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch @@ -1,4 +1,4 @@ -From f0f6537007b57483923b71a9da409d7811b4a6a1 Mon Sep 17 00:00:00 2001 +From 85a95040d75c291fbc93e0e561d3568b14954b13 Mon Sep 17 00:00:00 2001 From: Jessica Liu Date: Tue, 10 Mar 2026 14:17:31 +0800 Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Register syscore diff --git a/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch b/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch index edf918ccc1..53005c0618 100644 --- a/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch +++ b/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch @@ -1,4 +1,4 @@ -From 362bcba652bd4b28531fbf93691ef6fba9a852a7 Mon Sep 17 00:00:00 2001 +From a6f845b2f096257348eb1751bb207a536f04a311 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Sep 2025 10:24:14 -0400 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: add missed compatible string diff --git a/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch b/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch index 3f06b45545..2d0aad73f6 100644 --- a/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch +++ b/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch @@ -1,4 +1,4 @@ -From 95da822dbecb61c821f0748e19304ec198992377 Mon Sep 17 00:00:00 2001 +From 17845b8b81cac4442af465cdf6758b45d6d8560d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Sep 2025 10:24:15 -0400 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add software-managed properties for diff --git a/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch b/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch index 0ff5ac0f10..14eb37d81f 100644 --- a/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch +++ b/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch @@ -1,4 +1,4 @@ -From 336f616b6d4b4f53eb9ffdf8822f067ff0820efa Mon Sep 17 00:00:00 2001 +From 237f1c42bc214c3cb3a624c24de08b613706e2f0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Sep 2025 10:24:16 -0400 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: Add layerscape diff --git a/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch b/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch index 85f93bef67..e612d006cb 100644 --- a/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch +++ b/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch @@ -1,4 +1,4 @@ -From 4b1c4f9c84bda4bcf482c0efe496c3a6648372ca Mon Sep 17 00:00:00 2001 +From 0b176d28630308e769098ac5e29e0edf51a0b398 Mon Sep 17 00:00:00 2001 From: Hang Cao Date: Wed, 12 Nov 2025 13:53:21 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add ESWIN EIC7700 USB diff --git a/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch b/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch index c664c16a80..d17829474c 100644 --- a/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch +++ b/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch @@ -1,4 +1,4 @@ -From a2ce6ee9f23da731a7f30c0869f5b48c66d727e1 Mon Sep 17 00:00:00 2001 +From f9fb0523e8826c570898c56b50bf9779f894ce26 Mon Sep 17 00:00:00 2001 From: Hang Cao Date: Wed, 12 Nov 2025 13:53:45 +0800 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: eic7700: Add EIC7700 USB driver diff --git a/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch b/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch index 0830c4cd17..c3a4eb335d 100644 --- a/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch +++ b/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch @@ -1,4 +1,4 @@ -From 9acac5b146b312ddb8525d13c2ba273dff6508a0 Mon Sep 17 00:00:00 2001 +From e2c5643e1715c990fc07ce560139625f2edd5827 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 16 Feb 2026 23:26:53 +0800 Subject: [RUYI PATCH] UPSTREAM: phy: k1-usb: add disconnect function support diff --git a/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch b/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch index f563981345..174cd8a8f1 100644 --- a/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch +++ b/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch @@ -1,4 +1,4 @@ -From 8aba9c8ffd6f7bf33950abcc2bb276254f6749cf Mon Sep 17 00:00:00 2001 +From c6a6a28a720c061231c7672505fe6b1692dc0c55 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Wed, 17 Dec 2025 07:45:28 -0800 Subject: [RUYI PATCH] UPSTREAM: PCI: Add ASPEED vendor ID to pci_ids.h diff --git a/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch b/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch index dba743541d..fbb2b87937 100644 --- a/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch +++ b/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch @@ -1,4 +1,4 @@ -From ebc23bfadb5fbe0d0f28b65fd9c6837238e6e941 Mon Sep 17 00:00:00 2001 +From a642f8bcf0cf62d7cf1642f8f24b2fbcfe80fc37 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Wed, 17 Dec 2025 07:45:29 -0800 Subject: [RUYI PATCH] UPSTREAM: PCI: Add PCI_BRIDGE_NO_ALIAS quirk for ASPEED diff --git a/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch b/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch index b717a1f71f..0e1b88fcc9 100644 --- a/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch +++ b/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch @@ -1,4 +1,4 @@ -From 9b54a8b4866b22ba764ced5eadb4df836758c46b Mon Sep 17 00:00:00 2001 +From e3d9fb3bd8c7d99e6f808702d5335a99df089451 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 23 Mar 2026 17:43:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: patch: Avoid early phys_to_page() diff --git a/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch b/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch index 7274ae6b1a..123c56b68d 100644 --- a/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch +++ b/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch @@ -1,4 +1,4 @@ -From 6727a0a8b7add2ff9543cd2e8e0f4e29a5a9b89a Mon Sep 17 00:00:00 2001 +From ee641316ba28b407fa3c0e2e30ff68676b24911c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 20 Jan 2026 23:17:44 +0530 Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Fail dw_pcie_host_init() if diff --git a/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch b/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch index 1cc4f9a6b9..58fb655677 100644 --- a/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch +++ b/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch @@ -1,4 +1,4 @@ -From a21ca9741cdf655d806097dd0285fc759b7550dd Mon Sep 17 00:00:00 2001 +From 50e513b530f9e8ff4e5efaa0d2a9c1ddf0ed96fe Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 11:06:17 +0000 Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: k3: Decouple composite reset diff --git a/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch index f22e81a3cb..b9680b0e9a 100644 --- a/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch +++ b/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch @@ -1,4 +1,4 @@ -From 36c2fd3cabf5ec62efb4f91282e7b4afd1034963 Mon Sep 17 00:00:00 2001 +From b177ff56efc790143fcad8774a0fa6295390e2c9 Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:25 +0000 Subject: [RUYI PATCH] UPSTREAM: rust: clk: implement Send and Sync diff --git a/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch index de7554e891..5f4ad88656 100644 --- a/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch +++ b/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch @@ -1,4 +1,4 @@ -From 83865522aaf93ce13b4bf32daff035cc0ffb1875 Mon Sep 17 00:00:00 2001 +From 656a7926c150505d9e7116c44047cb98b9b144ac Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:26 +0000 Subject: [RUYI PATCH] UPSTREAM: tyr: remove impl Send/Sync for TyrData diff --git a/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch b/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch index 96d1a40105..14ac0db488 100644 --- a/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch +++ b/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch @@ -1,4 +1,4 @@ -From 196de3c6b4e75a74ef0157f0c59ca867711beb1f Mon Sep 17 00:00:00 2001 +From c8b2cc93f304e121425f8ab08537d10ae2a5110a Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 21 Jan 2026 19:37:19 +0100 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: fix `CLIPPY=1` warning diff --git a/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch index bfdd63b39b..e20e980eb2 100644 --- a/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch +++ b/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch @@ -1,4 +1,4 @@ -From b521133241a4f965f50ccf4af99769c36904d779 Mon Sep 17 00:00:00 2001 +From 1c00f5d8f76d51936665551442e935339855075a Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:27 +0000 Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: remove impl Send/Sync for diff --git a/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch index 3373671d06..4cf0c7a3ce 100644 --- a/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch +++ b/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch @@ -1,4 +1,4 @@ -From 32264ffa5210859b00dbce09fa640779874438f7 Mon Sep 17 00:00:00 2001 +From 6b739d775a13c509e838c68cb864879eb5035a21 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 5 Mar 2026 15:00:29 +0800 Subject: [RUYI PATCH] UPSTREAM: net: spacemit: Remove unused buff_addr fields diff --git a/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch index 9f38d216be..81a0a8d8e7 100644 --- a/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch +++ b/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch @@ -1,4 +1,4 @@ -From c446f352ebab05c2cef0a9835bd9224e19c24ccb Mon Sep 17 00:00:00 2001 +From da2e9a8963b952986b932b293479350fe4dbebc0 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:37 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: Add support for Spacemit K3 diff --git a/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch index e0e422ae4b..4d058142e7 100644 --- a/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch +++ b/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch @@ -1,4 +1,4 @@ -From 415d3b3b2a8fe07f5d9c84225c47c6f3be8fd827 Mon Sep 17 00:00:00 2001 +From 2587e7c305cdac8ba52da0a37169d1b9c8064588 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:38 +0800 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a IP diff --git a/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch index e3ca4ecc6c..a953c62cbe 100644 --- a/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch +++ b/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch @@ -1,4 +1,4 @@ -From 945ce43958e6a4b22a3bf632d66514c6e279d2e9 Mon Sep 17 00:00:00 2001 +From 8877fbd548452797ddc8b8ea1e278fe120e4ed3e Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:39 +0800 Subject: [RUYI PATCH] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 diff --git a/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch index be1102a0eb..b43ad2ba8c 100644 --- a/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch +++ b/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch @@ -1,4 +1,4 @@ -From eaea87333b8ad51ffef8e8e2939c8aedc0c6f5f5 Mon Sep 17 00:00:00 2001 +From 89f93eb859e29528753f46b119d8e592d8df98b4 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Fri, 6 Feb 2026 16:02:12 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve handling of unknown diff --git a/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch index d0de8aa1e5..bf83516e20 100644 --- a/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch +++ b/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch @@ -1,4 +1,4 @@ -From 74c17747b1c536e207645c2cd6bd1399b9d2ec05 Mon Sep 17 00:00:00 2001 +From d3c0e1ed28ef36b7a478ab1e5a1d43b177252681 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Fri, 6 Feb 2026 16:02:13 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Mark FWCCB_CMD_UPDATE_STATS diff --git a/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch index 50ffd104f5..2b791ebf69 100644 --- a/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch +++ b/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch @@ -1,4 +1,4 @@ -From 913bf005c8fcc762460c945ae4c4b99a3b30e116 Mon Sep 17 00:00:00 2001 +From 38fc4d550a8ceafb242fc13b315cf8978c21de80 Mon Sep 17 00:00:00 2001 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:24 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve firmware power off diff --git a/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch index 30928dca28..a80553db97 100644 --- a/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch +++ b/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch @@ -1,4 +1,4 @@ -From 1c4786d466085bd7d5e793bc432f8d9d77048fb9 Mon Sep 17 00:00:00 2001 +From 3c81b0118a1dae65d34dd8ccfcc3c139756498ab Mon Sep 17 00:00:00 2001 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:25 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip 2nd thread DM diff --git a/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch index 74f768a3dd..1000a5b0eb 100644 --- a/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch +++ b/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch @@ -1,4 +1,4 @@ -From 2af0a8e17c8cfcbee59a2a2f6315c394a0342dc5 Mon Sep 17 00:00:00 2001 +From 90791ed1e854870177f6c1d1b77e2676feac639f Mon Sep 17 00:00:00 2001 From: Alexandru Dadu Date: Mon, 23 Mar 2026 20:31:28 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Add missing rogue context diff --git a/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch index 0b560df8fc..1b0b881b05 100644 --- a/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch +++ b/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch @@ -1,4 +1,4 @@ -From 3ea351d649da005c14bb7563aff7c5a258116a18 Mon Sep 17 00:00:00 2001 +From 401d51c0efd933cbb72ce194feb019d8ec7119d1 Mon Sep 17 00:00:00 2001 From: Alexandru Dadu Date: Mon, 23 Mar 2026 20:31:30 +0200 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Implement handling of context diff --git a/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch index f7d478ada1..eed39f4394 100644 --- a/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch +++ b/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch @@ -1,4 +1,4 @@ -From e88d780551651b13977fcb9a0fc500f0edc4ec8d Mon Sep 17 00:00:00 2001 +From 17ffbb0f5a1fccd445f675bb3c6c05253578a74a Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:15 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: add verisilicon diff --git a/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch index 3ab06308e6..b530b8d352 100644 --- a/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch +++ b/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch @@ -1,4 +1,4 @@ -From 0097108abfd8e7e0526f283feef46f9ff85d3019 Mon Sep 17 00:00:00 2001 +From cc17be16d91b62778ed9f985371b1e03411d8938 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:16 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display: add verisilicon,dc diff --git a/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch index f6b7875e3a..1bcbd0654a 100644 --- a/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch +++ b/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch @@ -1,4 +1,4 @@ -From 6b2f35b64e7c0486c46921e2bae819b08dc83a72 Mon Sep 17 00:00:00 2001 +From 232492bd64c5a453597b4bc3bfd8d0c1e4c1be57 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:17 +0800 Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add a driver for Verisilicon diff --git a/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch index 641e31a30d..6982aad95b 100644 --- a/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch +++ b/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch @@ -1,4 +1,4 @@ -From f3c9d099748a9f334530dc8d3b829667282a09e2 Mon Sep 17 00:00:00 2001 +From 6274472f0a7aacec6bf75732549eb8801ce79364 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:18 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display/bridge: add binding for diff --git a/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch index cf9d00a163..98cacc3de7 100644 --- a/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch +++ b/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch @@ -1,4 +1,4 @@ -From 58ad5626c4911a37f2e711c60ae825d55251511b Mon Sep 17 00:00:00 2001 +From b4768d8979f02ad4d17b11a4bd4a0c97b33d5fbc Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:19 +0800 Subject: [RUYI PATCH] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 diff --git a/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch index 6f796d9cbc..bb1851b7f9 100644 --- a/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch +++ b/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch @@ -1,4 +1,4 @@ -From ea4a0e0935587b36a14380693c67c8cd0a9b30f1 Mon Sep 17 00:00:00 2001 +From 95eff11a4892693dbe633e1582a8e9359fcd79f7 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:02 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add individual diff --git a/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch index c1c7ac83ec..9fc6e8dfd3 100644 --- a/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch +++ b/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch @@ -1,4 +1,4 @@ -From 42b7ba3e5273fbdc3ca27c1fb551be6f0eccab97 Mon Sep 17 00:00:00 2001 +From b190e35d2b5d27e768e7b1ab0e227d0a768a2159 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:03 +0800 Subject: [RUYI PATCH] UPSTREAM: regulator: spacemit-p1: Update supply names diff --git a/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch index 7a0dd9d20a..391aba0e06 100644 --- a/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch +++ b/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch @@ -1,4 +1,4 @@ -From a16a762a96646468762203524a13847057523875 Mon Sep 17 00:00:00 2001 +From dd2cc43099815a13549008e14bc55ac63e84a1c7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 23 Dec 2025 10:24:50 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add reset support diff --git a/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch index 271bd70fc5..b268f7565b 100644 --- a/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch +++ b/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch @@ -1,4 +1,4 @@ -From 3661bb1bda184323b7f27ca11c4f6aa2453a891b Mon Sep 17 00:00:00 2001 +From 34f466edac754bd7fcecd9a421744a5f4ad5280a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 22 Jan 2026 17:37:30 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add support diff --git a/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch index 067922ab83..b3e8c6be5f 100644 --- a/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch +++ b/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch @@ -1,4 +1,4 @@ -From aef7fb87d55efc5bff2a628b6196c36b7eaf3e12 Mon Sep 17 00:00:00 2001 +From ab33d441a051812b365999d837b8afaa448e3da7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 22 Jan 2026 17:37:31 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for K3 diff --git a/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch b/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch index bd29a279bd..71b4897e14 100644 --- a/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch +++ b/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch @@ -1,4 +1,4 @@ -From 71fc35504a003f43684f36757050f5c7e1ca7c23 Mon Sep 17 00:00:00 2001 +From f96f9ecbf2aa737fe00a69a78cc04b4004e5a254 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Sun, 5 Apr 2026 15:41:53 +0000 Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add flags for disabling ASPM diff --git a/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch b/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch index 863472668a..d36042d2d2 100644 --- a/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch +++ b/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch @@ -1,4 +1,4 @@ -From b79c6a8e8737f691e21ed1f9492ed9784de03550 Mon Sep 17 00:00:00 2001 +From 7634a34dc15383e81523eec67c157edc7f6267d5 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Sun, 5 Apr 2026 15:41:54 +0000 Subject: [RUYI PATCH] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 diff --git a/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch index 45d9a8f9de..2c9e5a12a7 100644 --- a/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch +++ b/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch @@ -1,4 +1,4 @@ -From e8797e3dcfc25acbd3f8c8b268ec9d8bd1c28295 Mon Sep 17 00:00:00 2001 +From e7eda2ad9f7e602ec3c79a20c05dbcb621c6ac76 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Mar 2026 00:24:56 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt diff --git a/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch b/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch index 3011e77bd5..800736102b 100644 --- a/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch +++ b/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch @@ -1,4 +1,4 @@ -From 42218f60a7def59ca6f9513365c5aed9fb77a124 Mon Sep 17 00:00:00 2001 +From 71420ca546d63613ee47267fdcfcb0a761bf330f Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Tue, 10 Mar 2026 11:41:12 +0000 Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Disable interrupts before diff --git a/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch index 97daa0a8b0..ffe40672f2 100644 --- a/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch +++ b/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch @@ -1,4 +1,4 @@ -From 9714f16b48717549d0332bbcd37661290bf0a765 Mon Sep 17 00:00:00 2001 +From 890f73d1b5c1319a9308842d0a118a23799701a6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:20 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add DPU and HDMI device diff --git a/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch index df92d3aeea..81f79d6d5b 100644 --- a/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch +++ b/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch @@ -1,4 +1,4 @@ -From 4633a7a2c68426c3f3fc28382fd6cba7df6134d8 Mon Sep 17 00:00:00 2001 +From 81676c69d6cf6b645944ad1e96c72e35e483f069 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:21 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable HDMI diff --git a/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch index dfee292fb6..7e8edfaeb8 100644 --- a/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch +++ b/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch @@ -1,4 +1,4 @@ -From 00020f3b46c3943b6ce714ac17de5fd1573b399b Mon Sep 17 00:00:00 2001 +From 8e3494bc849eb33a26b0fc1e3c0662ecc6cbdaba Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Mar 2026 00:24:57 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: th1520: add coefficients to diff --git a/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch index 03da857375..7ab4fffc43 100644 --- a/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch +++ b/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch @@ -1,4 +1,4 @@ -From 1cce6a25c0cf7aab271eb21e6d8b9ed58ed13b84 Mon Sep 17 00:00:00 2001 +From dceaa01db9088494f93a2bc9dd7fd5887f44e60e Mon Sep 17 00:00:00 2001 From: Robert Mazur Date: Wed, 25 Mar 2026 09:18:59 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable HDMI diff --git a/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch index 0128ba9bc1..f42029e4e2 100644 --- a/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch +++ b/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch @@ -1,4 +1,4 @@ -From d2ce0203a4d1455b03013278280f7ac698fce115 Mon Sep 17 00:00:00 2001 +From 383020d47e926f8e6e10db7f404c0f22f4ac37b7 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Sat, 7 Feb 2026 23:08:21 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() diff --git a/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch index 34101370a3..e5c199eec8 100644 --- a/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch +++ b/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch @@ -1,4 +1,4 @@ -From 4fa4815280ddada7e960eb90a9ccccd015916c00 Mon Sep 17 00:00:00 2001 +From 85a82954acd965a8e7f06acf2b98533ffe944b92 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Sat, 7 Feb 2026 23:08:22 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: introduce pio for k1 diff --git a/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch index d01da0caa4..a0402db174 100644 --- a/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch +++ b/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch @@ -1,4 +1,4 @@ -From 55a3d0c1bf77d828f3581b3c07e12d8a25775e1c Mon Sep 17 00:00:00 2001 +From 189d71e00b28cf84bdef8a3368c473675599b5a4 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:42 +0800 Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for diff --git a/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch index 5b07efea54..330746bdaa 100644 --- a/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch +++ b/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch @@ -1,4 +1,4 @@ -From 698e2cf6a0e40c6a445aeefa403bb4ac1b28919a Mon Sep 17 00:00:00 2001 +From 4588a083d35aa5e2e2c1c4ad364eb4de88d6a7ad Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:43 +0800 Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Add set_config callback diff --git a/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch b/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch index e3ff5c7bb8..64650bb229 100644 --- a/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch +++ b/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch @@ -1,4 +1,4 @@ -From 8572451bc96b2e6e3f43ce554e3806a5b1c7778c Mon Sep 17 00:00:00 2001 +From 3972df874b39a17accecea4ef294937b0b4db42d Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 08:17:55 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pcie: fix missing power diff --git a/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch index c1a03ad44a..e598325fe2 100644 --- a/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch +++ b/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch @@ -1,4 +1,4 @@ -From d591170d2ed25e8716eb3db09e686e859c5c318b Mon Sep 17 00:00:00 2001 +From c74eeb3e1afb91310fa36cfdf25bd8dccaf5dc72 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:04 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Update PMIC supply diff --git a/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch index 2dce8101f3..53c8565593 100644 --- a/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch +++ b/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch @@ -1,4 +1,4 @@ -From d068a8147daedba4965fc79a896ad7dcaa91b9e4 Mon Sep 17 00:00:00 2001 +From 706c6c7d0a2819ecb157351bcb6b9d3c85c72f8a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 09:35:00 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: adapt regulator node diff --git a/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch index dd31af6364..8e8e77d707 100644 --- a/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch +++ b/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch @@ -1,4 +1,4 @@ -From 3c942f15e5112f8554b39f1c889cb52184bd3e90 Mon Sep 17 00:00:00 2001 +From b1b9cbb75e922569afad4faecf4626e8bde3e7d7 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 9 Mar 2026 11:00:00 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add 'linux,pci-domain' diff --git a/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch index 1a6351971a..565fb8abda 100644 --- a/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch +++ b/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch @@ -1,4 +1,4 @@ -From e6fddcb8065f3568285549e732cda7618b1e5065 Mon Sep 17 00:00:00 2001 +From 88d533f1c6bfb3181035649386387a8d59f75318 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:19:39 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix clock diff --git a/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch index d84cac3c6d..80b8be71a3 100644 --- a/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch +++ b/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch @@ -1,4 +1,4 @@ -From d685ab6d599ba502610b5f425c35683c2c838c0a Mon Sep 17 00:00:00 2001 +From 60519a3245f5c93f0bbe6ec9f8502c9031994419 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:42 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add clock tree diff --git a/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch index 43081756d0..12c9c99597 100644 --- a/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch +++ b/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch @@ -1,4 +1,4 @@ -From 26584036220607376da285b0c0cf42306e1dc824 Mon Sep 17 00:00:00 2001 +From 6cefb7d0dcc59b4d29c4b66e52d86a7e80d4db06 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:43 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl support diff --git a/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch index dae1e8f109..a2207de4f1 100644 --- a/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch +++ b/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch @@ -1,4 +1,4 @@ -From d0197dc9c7ce0b6d04f508db631f06668553d958 Mon Sep 17 00:00:00 2001 +From 67a9dfd22c5cefa5860160d30c1b5bce5719c5a6 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:44 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support diff --git a/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch index 581044da67..e7737fa5c7 100644 --- a/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch +++ b/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch @@ -1,4 +1,4 @@ -From 186d384a785aeb3b664585647bd06ee2009145dd Mon Sep 17 00:00:00 2001 +From 44eedf0908b4e6c2893a89cb94053d973411abab Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:45 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add full resource to diff --git a/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch index a15e56ca61..dfeb6a4a3f 100644 --- a/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch +++ b/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch @@ -1,4 +1,4 @@ -From 8ded8df1d9dccc63760629834a87ae2c8615e042 Mon Sep 17 00:00:00 2001 +From bae97e71f9ca4558461de9dd135102ef2c5a4f0b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 07:15:37 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add support diff --git a/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch index 45a1cbb328..90eb42bbb1 100644 --- a/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch +++ b/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch @@ -1,4 +1,4 @@ -From 27133a501e88e5b271c1a5c98f2013d1f8dc931a Mon Sep 17 00:00:00 2001 +From 7d4a17760463805b041533b09751e181e870e5e4 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 07:15:38 +0000 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add diff --git a/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch index e9139f8f74..f6606cf138 100644 --- a/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch +++ b/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch @@ -1,4 +1,4 @@ -From ec33bc462214da036d45ea0a3822c34e9f3d422b Mon Sep 17 00:00:00 2001 +From 395f6faa5c6eaee1206ab83d69d671da8d8bf5e3 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 26 Mar 2026 18:00:10 +0800 Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add optional VBUS regulator support diff --git a/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch index 4c498e66d6..29c7c2bea5 100644 --- a/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch +++ b/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch @@ -1,4 +1,4 @@ -From feb6ae05030bda7ec7a43a8384cfdffc80d33e30 Mon Sep 17 00:00:00 2001 +From 8ad8078b131f6aea0fde2e411f43212dbb92b54b Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 18 Mar 2026 18:00:00 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for K1 diff --git a/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch b/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch index 7d60f42287..4198effb46 100644 --- a/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch +++ b/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch @@ -1,4 +1,4 @@ -From 9c90526d6c53498c2b0fce296ea54822274f4e03 Mon Sep 17 00:00:00 2001 +From cc73195bc241ce392226f27e718ad6bb23c7dc33 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 22 Mar 2026 21:25:01 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: drop incorrect pinctrl diff --git a/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch index daa6d30ac8..0ebc98616d 100644 --- a/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch +++ b/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch @@ -1,4 +1,4 @@ -From f1fd9849a3a86e6e7567394bcfbd7e80314e1925 Mon Sep 17 00:00:00 2001 +From 8199942289fa74a51c30bec529cab134501ee2be Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 26 Mar 2026 09:46:17 +0800 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add ethernet device for diff --git a/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch index 0ef10a2c37..7651ca9ac9 100644 --- a/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch +++ b/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch @@ -1,4 +1,4 @@ -From 22e068c1b0db347abe57240b5f4e6aea284b400a Mon Sep 17 00:00:00 2001 +From 9350d479493c039562a167931c2a148bb2257368 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:29 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V diff --git a/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch index d1757910da..78c7581d06 100644 --- a/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch +++ b/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch @@ -1,4 +1,4 @@ -From fd0cc30ddc8df5ecd44ae759b0d7ba0d8b5140c5 Mon Sep 17 00:00:00 2001 +From a28cfbc8b3633e1c31dc2dd1b607c515e3d9473a Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:30 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on diff --git a/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch index d6371cd157..199d048656 100644 --- a/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch +++ b/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch @@ -1,4 +1,4 @@ -From 82fab0710b5af85d582db37f1628e0efe0783003 Mon Sep 17 00:00:00 2001 +From d33a5a7d922d3c7562e7169a9c50caf7b81d39dd Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:31 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on diff --git a/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch index 7da7a14692..6f72accab4 100644 --- a/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch +++ b/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch @@ -1,4 +1,4 @@ -From 8cd168c0e1c6761c9dc36dba489883961c115b69 Mon Sep 17 00:00:00 2001 +From 7bf7522c2f3ea687882aebaef45a23db49a253a6 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:32 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI and add SPI diff --git a/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch index ab6defa852..53bcae1cda 100644 --- a/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch +++ b/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch @@ -1,4 +1,4 @@ -From 7c97859e0dc8e3a13976fbd8fa3512d2a6469e32 Mon Sep 17 00:00:00 2001 +From 16315cf1d62e428f4ffd7477fe748a579e08c767 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:33 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on diff --git a/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch index 37c7e74275..bfdf3f0566 100644 --- a/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch +++ b/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch @@ -1,4 +1,4 @@ -From a6af60e5b4b61218cbfe45507b2a9c0740b13741 Mon Sep 17 00:00:00 2001 +From 008e9161472e33b735cabb897a883483eb1d62ce Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:34 +0100 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on diff --git a/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch index 636cc98729..2105efb33b 100644 --- a/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch +++ b/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch @@ -1,4 +1,4 @@ -From ffb258a6f70ad79ca6c7b0a4c04cd38fbdd33471 Mon Sep 17 00:00:00 2001 +From eaf94de0b17a7f2c6c983d703f6f3bd8dbd4db38 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 25 Mar 2026 09:49:24 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add compatible diff --git a/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch index 4fa6b0eb20..692dc582f5 100644 --- a/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch +++ b/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch @@ -1,4 +1,4 @@ -From 2e5ff84331e9d469cf732e06694632b4d7f0a64e Mon Sep 17 00:00:00 2001 +From dc51053b1e9c63bf238c7324e2bfb06cacd96efd Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:40:40 +0000 Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes diff --git a/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch index fec47cecd6..69f27b1739 100644 --- a/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch +++ b/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch @@ -1,4 +1,4 @@ -From 7602638398631706b3b851eeb82562691d9fbf20 Mon Sep 17 00:00:00 2001 +From 5eadd54b1f4d67bed0234caa109dfa0bce785c40 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:51:18 +0000 Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC diff --git a/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch index dc246bac07..1dda4ae65f 100644 --- a/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch +++ b/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch @@ -1,4 +1,4 @@ -From e2f15b90c20c9acc8b6524640ad61e8dd279261b Mon Sep 17 00:00:00 2001 +From 852e5e193c12e0e5eb26b24e0eb9517eaeaf46b9 Mon Sep 17 00:00:00 2001 From: Chen Pei Date: Tue, 17 Mar 2026 11:48:47 +0800 Subject: [RUYI PATCH] UPSTREAM: perf symbol: Add RISCV case in get_plt_sizes diff --git a/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch index 4135dc8422..cd178c2295 100644 --- a/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch +++ b/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch @@ -1,4 +1,4 @@ -From 88b461165ff138a8bc16b7a3d1540a19c8a3710e Mon Sep 17 00:00:00 2001 +From 90646c816a8e1bb5cf43743f706066bc525133ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 4 Apr 2026 18:42:40 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE diff --git a/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch index c12445faca..ac47ff42ee 100644 --- a/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch +++ b/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch @@ -1,4 +1,4 @@ -From f64acae7865de9be5e3490b46bc253b9e0d8464e Mon Sep 17 00:00:00 2001 +From a3b19f0358177e3a9a105a429a45332a53464e30 Mon Sep 17 00:00:00 2001 From: Austin Kim Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to diff --git a/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch index 53eb710553..558694da38 100644 --- a/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch +++ b/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch @@ -1,4 +1,4 @@ -From 50da2d0c20ed5daeac5e56fc3b173a315118dc29 Mon Sep 17 00:00:00 2001 +From 55bd39f8dbbb10df72d54d5154629679a7c26d5b Mon Sep 17 00:00:00 2001 From: Yufeng Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: acpi: update FADT revision check to 6.6 diff --git a/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch index 03b0b8232a..1717b0a8f0 100644 --- a/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch +++ b/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch @@ -1,4 +1,4 @@ -From 527bf47071201cafeeb74ad89ac94e5d61eb3691 Mon Sep 17 00:00:00 2001 +From c96326e9beaa6d43dee68a3d895b432c6d47151c Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in diff --git a/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch index d8e8ef3623..039119e151 100644 --- a/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch +++ b/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch @@ -1,4 +1,4 @@ -From 21223e48716232b52be9719f8d4361bc9f82af59 Mon Sep 17 00:00:00 2001 +From bf80711365ff96f172a52b4e8ccac4322a7a3b48 Mon Sep 17 00:00:00 2001 From: Yufeng Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT diff --git a/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch b/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch index 1647db78f8..b5da7e906d 100644 --- a/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch +++ b/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch @@ -1,4 +1,4 @@ -From 94b2dc80662df98e75c5893573a98c832aa7b104 Mon Sep 17 00:00:00 2001 +From 2192890eb62375ada4534f4dca4d8fc75d8e97d4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 12 Nov 2025 14:55:30 +0100 Subject: [RUYI PATCH] UPSTREAM: string: provide strends() diff --git a/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index 98ac349bfa..46309a18d1 100644 --- a/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,4 +1,4 @@ -From 79e2cd89898e36fdb3d1714bbd7988fb286c84c7 Mon Sep 17 00:00:00 2001 +From 7ae2a067cd00b1c714466b1d1f02b9b411af5d76 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for diff --git a/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index cf2e77deb8..306e922690 100644 --- a/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,4 +1,4 @@ -From 902bdb8bb0a0f55816f458cf513b52da08e503fb Mon Sep 17 00:00:00 2001 +From 1dd18b43a3cfbc4596a549638d881be3fb39fe5f Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for diff --git a/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index b303a23ddc..3fe7266d90 100644 --- a/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,4 +1,4 @@ -From a35e09fa31b7cc0d163e681b2acef99edf7f626b Mon Sep 17 00:00:00 2001 +From 6b47c4d6992b0b42614e5c42cd68a690c32a445c Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for diff --git a/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch index 8ed6b57c83..4216e5a9b8 100644 --- a/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch +++ b/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch @@ -1,4 +1,4 @@ -From 3157c725cd7a5774a6e772aee7c537b7bc65a90e Mon Sep 17 00:00:00 2001 +From d032a3bac6de0685705b92695173bf82d6eeb886 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add performance benchmark diff --git a/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch index 8a4b47a942..2012c69aaf 100644 --- a/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch +++ b/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch @@ -1,4 +1,4 @@ -From d4f3b19d0ba9850b6052f6adfda81bdd61650371 Mon Sep 17 00:00:00 2001 +From 11b6137f31389cecbf4ac42f2cd0da5955d5509e Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: extend benchmarks to diff --git a/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch index da2b0c30de..115899af46 100644 --- a/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch +++ b/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch @@ -1,4 +1,4 @@ -From d7fce76a1ce208fab598335c38ae8071bb4d893d Mon Sep 17 00:00:00 2001 +From 1a8b9de36cf32d4946ac90848ae0f16b4436b71d Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strnlen() implementation diff --git a/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch index 82e732ebcb..681090539c 100644 --- a/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch +++ b/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch @@ -1,4 +1,4 @@ -From 2f4c1bb28db6a3485cd348d5484cabeee5afb672 Mon Sep 17 00:00:00 2001 +From 5720372e6ff0e8dc4f75e5d70b798c3dd898d8e6 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strchr() implementation diff --git a/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch index 4a1a619b26..d3723941b6 100644 --- a/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch +++ b/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch @@ -1,4 +1,4 @@ -From 7a1bef3a9306a7c4cd45d233b4965356c86f23d4 Mon Sep 17 00:00:00 2001 +From c9a314cc16c1422c4922b0a902f8f01ef17ad06f Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strrchr() implementation diff --git a/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch b/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch index a11233ee84..e40c8137ae 100644 --- a/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch +++ b/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch @@ -1,4 +1,4 @@ -From 0bd7f056d6569dc61e0cc65e7eaab3c9d9d1e879 Mon Sep 17 00:00:00 2001 +From 51dd8eef5e0f89c2b72fd1f0b6c6bc8177438545 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 21 Nov 2025 17:49:18 +0100 Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Add register and bitfield diff --git a/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch index 9b9454daa8..a9c3f4d779 100644 --- a/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch +++ b/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch @@ -1,4 +1,4 @@ -From 22c3a93bf61eb47e3b47fd1cbfb9bed064b5de81 Mon Sep 17 00:00:00 2001 +From 5f7beedf8c1e1cf4cc2d8915cd12d47296a9f445 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 09:38:47 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: move hw constraints from diff --git a/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch index a235db3255..42acd706e3 100644 --- a/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch +++ b/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch @@ -1,4 +1,4 @@ -From b81d7e8285e49c07fa31cdb599fdeedddec0fb3c Mon Sep 17 00:00:00 2001 +From 0b445558d4400c7c06a9225f92fc58434d9c4d63 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 09:38:48 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: adjust FIFO trigger threshold diff --git a/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch b/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch index dbc1d4ed46..61f13b52f2 100644 --- a/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch +++ b/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch @@ -1,4 +1,4 @@ -From 42cd6879691919aaf3200276ed71a8c7f081bf8f Mon Sep 17 00:00:00 2001 +From 0dee3c150e4f31a42ee5358c2fb16cedbad43f79 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:28 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Remove diff --git a/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch b/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch index 20d4cb4ce7..9a271b21cf 100644 --- a/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch +++ b/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch @@ -1,4 +1,4 @@ -From 729fb80f40c116319af3f00f273cb56718995e42 Mon Sep 17 00:00:00 2001 +From 0a037ecaecd5d3d6451db6da957486d31735aa89 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:29 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Add diff --git a/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch b/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch index 46e0cf3948..c1f80c30ab 100644 --- a/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch +++ b/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch @@ -1,4 +1,4 @@ -From 822ec8590fdd9c6e8152814eca6d64a56660f962 Mon Sep 17 00:00:00 2001 +From b7535d42730ac17d83ccbadc8307100224b35705 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:30 +0000 Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Prepare for supporting multiple diff --git a/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch b/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch index 7a6c0e9f96..16798fa2d1 100644 --- a/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch +++ b/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch @@ -1,4 +1,4 @@ -From 34aaa4adc6171c1a972e81edbb9861406d7dfa83 Mon Sep 17 00:00:00 2001 +From faec33d63e5af3e07a519daa81a8d9e953889eaf Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:31 +0000 Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Support reset controllers in diff --git a/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch b/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch index 0509d7a26d..7b5917de8c 100644 --- a/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch +++ b/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch @@ -1,4 +1,4 @@ -From 9edafc5f3980e8fcb1a7a18a54466898f1279c14 Mon Sep 17 00:00:00 2001 +From 990eca59b3d00bfc3fd84a349b32be602ef7eeb9 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 14 Oct 2025 13:10:32 +0000 Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add reset controllers of diff --git a/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch index 983dd64913..f40121b1d7 100644 --- a/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch +++ b/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch @@ -1,4 +1,4 @@ -From 5f50d2a328f7b2daa106bafdb1d4a794f52fbdb4 Mon Sep 17 00:00:00 2001 +From 9a05689ddb515469b8dd3b3c86c6e461cb930936 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 24 Apr 2026 16:20:32 +0800 Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: mark top_dclk as diff --git a/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch index b11d06885a..fb64bb8356 100644 --- a/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch +++ b/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch @@ -1,4 +1,4 @@ -From a7739f1ea5fb20b796b4b1d3758fd44635a40ea9 Mon Sep 17 00:00:00 2001 +From ceac6c799226bf0a55e750f8dfda4457a57c8b30 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 17:00:50 +0800 Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: fix RX DMA params not set when diff --git a/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch b/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch index 23a5e1bf51..99abbd9388 100644 --- a/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch +++ b/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch @@ -1,4 +1,4 @@ -From 2c946683705fc6706119c588fd5499c0c91b2369 Mon Sep 17 00:00:00 2001 +From 6d414cc0992e8a50a71176942000ae8b501050ec Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 26 Dec 2025 16:31:59 +0800 Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: drop useless spaces diff --git a/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch b/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch index dbb5d3dfe0..41e1d30f6d 100644 --- a/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch +++ b/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch @@ -1,4 +1,4 @@ -From fa80698856016bcd983f8ac31a38e4f108170879 Mon Sep 17 00:00:00 2001 +From 0889d1b742e0a98a0d7f090055580115acf747e6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:49 +0100 Subject: [RUYI PATCH] UPSTREAM: clk: at91: pmc: #undef field_{get,prep}() diff --git a/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch b/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch index 28c2c8a5db..cd542378fa 100644 --- a/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch +++ b/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch @@ -1,4 +1,4 @@ -From 0443b117c46d5530b02f66cefa36882031ef8c7f Mon Sep 17 00:00:00 2001 +From b493426d9cce7da21f2865b6e67975ecb05db09f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:50 +0100 Subject: [RUYI PATCH] UPSTREAM: crypto: qat - #undef field_get() before local diff --git a/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch b/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch index 5bd7f8e544..c21ab5a1c2 100644 --- a/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch +++ b/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch @@ -1,4 +1,4 @@ -From 8d1903d76c78fd4c3f54ccb47a84b23de8c65c5a Mon Sep 17 00:00:00 2001 +From 55c96fbd859895ac18ef19bf2cb66a79be5a441b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:51 +0100 Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: #undef field_get() before local diff --git a/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch b/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch index 8d05fa846c..d8f64a7fc9 100644 --- a/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch +++ b/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch @@ -1,4 +1,4 @@ -From 8490549e86aef53fa8416d6accaa31283186c10b Mon Sep 17 00:00:00 2001 +From 737621e196c8ba0b53475a9010406b9314bac718 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:52 +0100 Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: #undef field_{get,prep}() before diff --git a/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch b/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch index 7595552488..c5ec822ba4 100644 --- a/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch +++ b/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch @@ -1,4 +1,4 @@ -From 2fda7cbf1f4289cbb26b12faf98ad22cbbf1c6b6 Mon Sep 17 00:00:00 2001 +From 200aa85cc99066caf1bfe42bc48afde3f5f165de Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:53 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: dac: ad3530r: #undef field_prep() before @@ -20,7 +20,7 @@ Signed-off-by: Han Gao 1 file changed, 1 insertion(+) diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 6134613777b8..5684d11137f2 100644 +index a0625fc7ad48..84ce89dd76a4 100644 --- a/drivers/iio/dac/ad3530r.c +++ b/drivers/iio/dac/ad3530r.c @@ -54,6 +54,7 @@ diff --git a/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch index 9deec2c78e..b4200b44f7 100644 --- a/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch +++ b/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch @@ -1,4 +1,4 @@ -From a31ca7ca552212b34bea5cb3fcf52759dc2a28a0 Mon Sep 17 00:00:00 2001 +From 56a0c498eb7202b1712b5d25176fd0f45ba6ab53 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:54 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: #undef field_{get,prep}() diff --git a/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch index 747d0f1115..74d6b8ea5f 100644 --- a/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch +++ b/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch @@ -1,4 +1,4 @@ -From 92ba8033d4f60d619ebeb8f1f465e68d66004e81 Mon Sep 17 00:00:00 2001 +From 9d7dbecad1fa5819d037808617b077ceccfaf798 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:55 +0100 Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: #undef field_{get,prep}() diff --git a/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch b/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch index a8085f2c11..716a908a6d 100644 --- a/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch +++ b/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch @@ -1,4 +1,4 @@ -From f43d3afeb48fc78d1fa9aec7aaaefdf6964e4b6c Mon Sep 17 00:00:00 2001 +From 3de69d18d8eb1ecf72128605e7f0f320f0504078 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:56 +0100 Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: #undef field_get() diff --git a/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch b/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch index ae69b76f2a..857453db7c 100644 --- a/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch +++ b/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch @@ -1,4 +1,4 @@ -From a743678cdf95c66206f1cefd74ad8f2e3157f680 Mon Sep 17 00:00:00 2001 +From dd326795b66465f04d08f11807c402dc08b8e615 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:33:57 +0100 Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: #undef field_{get,prep}() diff --git a/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch b/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch index 9a78322adf..4554119461 100644 --- a/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch +++ b/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch @@ -1,4 +1,4 @@ -From c59127e75e8cf8ce74f12bd0fe0bb2574674fbe4 Mon Sep 17 00:00:00 2001 +From 7d48e0ac649a9c8f4b760a91b4eb1e76fa1ec967 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:00 +0100 Subject: [RUYI PATCH] UPSTREAM: bitfield: Add less-checking diff --git a/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch b/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch index 68212a5dda..851db8f7ac 100644 --- a/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch +++ b/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch @@ -1,4 +1,4 @@ -From 9508a0e99753a0d15b30509ead3b2314fe5d2572 Mon Sep 17 00:00:00 2001 +From 29093ed6a42705c11d9aad5ea6ad64a74dc62910 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:01 +0100 Subject: [RUYI PATCH] UPSTREAM: bitfield: Add non-constant field_{prep,get}() diff --git a/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch b/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch index 5f249092c8..a587b97492 100644 --- a/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch +++ b/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch @@ -1,4 +1,4 @@ -From 7ab27d3da88e00fd0367baf7b18fb5484ac4fd65 Mon Sep 17 00:00:00 2001 +From 8096ab2dd7593c509f2914244c681f02c9b33108 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:02 +0100 Subject: [RUYI PATCH] UPSTREAM: clk: at91: Convert to common diff --git a/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch b/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch index ad7e2a30bc..2e3e3e992e 100644 --- a/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch +++ b/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch @@ -1,4 +1,4 @@ -From e7cc1307805b330990170342cd2e17a4790cae37 Mon Sep 17 00:00:00 2001 +From 9434386120d19e42a43e97baa0574d3919723bda Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:03 +0100 Subject: [RUYI PATCH] UPSTREAM: crypto: qat - convert to common field_get() diff --git a/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch b/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch index 15800bac47..316ceb06f1 100644 --- a/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch +++ b/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch @@ -1,4 +1,4 @@ -From 435c6fcc72eff501ecd29fabd2fedec939c67aa6 Mon Sep 17 00:00:00 2001 +From 01de375c11e96785ae483780df945db623280b95 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:04 +0100 Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: Convert to common field_get() diff --git a/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch b/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch index 8bbf1a93ec..62a1d60f9d 100644 --- a/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch +++ b/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch @@ -1,4 +1,4 @@ -From d812b182981498ab3054a3c64531710d096f4e8a Mon Sep 17 00:00:00 2001 +From 99f9fe7759f561b8b37477c015e1186da1e3b182 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:05 +0100 Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: Convert to common diff --git a/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch b/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch index 0c7f9de5cc..5247b913ab 100644 --- a/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch +++ b/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch @@ -1,4 +1,4 @@ -From 8c762e56b97e2dfa47081feffdf43f03d3f977e5 Mon Sep 17 00:00:00 2001 +From f9bc08e080dccd44f22a6dcd7d0cb5ee72455eb5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:06 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: dac: Convert to common field_prep() @@ -17,7 +17,7 @@ Signed-off-by: Han Gao 1 file changed, 4 deletions(-) diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 5684d11137f2..b97b46090d80 100644 +index 84ce89dd76a4..d9db3226ecd6 100644 --- a/drivers/iio/dac/ad3530r.c +++ b/drivers/iio/dac/ad3530r.c @@ -53,10 +53,6 @@ diff --git a/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch index 5dec21e9bb..f037318cef 100644 --- a/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch +++ b/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch @@ -1,4 +1,4 @@ -From c7ea1c7ee160166a1ed64ca27681872c97335904 Mon Sep 17 00:00:00 2001 +From 4b5147a1b6e7c57b1d67fd4d34f4d245d368401e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:07 +0100 Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: Convert to common diff --git a/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch index d757b43507..fd71abcfbc 100644 --- a/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch +++ b/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch @@ -1,4 +1,4 @@ -From 2cbda24297eace09de563cb06455c5936a00088e Mon Sep 17 00:00:00 2001 +From 02ff752ecdd8f77567b57dd2fe015f4b52f0173c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:08 +0100 Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: Convert to common diff --git a/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch b/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch index f9d9f0c492..7022d54f29 100644 --- a/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch +++ b/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch @@ -1,4 +1,4 @@ -From 8833c4b417190dce1a91dbf31da82221a266f133 Mon Sep 17 00:00:00 2001 +From 9d7b112b2c4bd1ec0fa4fefeb7dd17be7100c322 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:09 +0100 Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: Convert to common diff --git a/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch b/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch index 9e36e61789..d504a4d562 100644 --- a/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch +++ b/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch @@ -1,4 +1,4 @@ -From d565f3b6ace21a51f62812c86add16af8553952d Mon Sep 17 00:00:00 2001 +From 1e575c7526236eca8a9557805ef5a712cc7c3062 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:10 +0100 Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: Convert to common diff --git a/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch index 383627c806..e2898f65d6 100644 --- a/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch +++ b/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch @@ -1,4 +1,4 @@ -From 019a7bd0c854f0ec67ae6e379c46f05ccf4be4dd Mon Sep 17 00:00:00 2001 +From fbba92fc24439fb25b3afc63b3bc7576193ba10f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:13 +0100 Subject: [RUYI PATCH] UPSTREAM: clk: renesas: Use bitfield helpers diff --git a/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch index 4685894400..a8bc5a6f32 100644 --- a/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch +++ b/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch @@ -1,4 +1,4 @@ -From 23fef80ff6550ef4d1ece307b5c601d37a1fe71c Mon Sep 17 00:00:00 2001 +From faddb8617190ce6db91b8957ad5a6e3a98024931 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 Nov 2025 14:34:14 +0100 Subject: [RUYI PATCH] UPSTREAM: soc: renesas: Use bitfield helpers diff --git a/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch index 45f824af71..604dfc454f 100644 --- a/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch +++ b/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch @@ -1,4 +1,4 @@ -From 56a298b59d7189961a4e6a04e449718ff2944c21 Mon Sep 17 00:00:00 2001 +From 55eb935ad6a55992f79be588fa21fc97cc4a0368 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 19 Mar 2026 07:51:03 +0000 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add support for Terminus diff --git a/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch index d9fcc7fdbd..9b5d33a19d 100644 --- a/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch +++ b/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch @@ -1,4 +1,4 @@ -From 7cc16fe69696bb942fb6f1b9a227fd74082707ae Mon Sep 17 00:00:00 2001 +From 08f28ce8702a79a701c3eac1b17da588327be574 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 19 Mar 2026 07:51:04 +0000 Subject: [RUYI PATCH] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus diff --git a/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch index 366e334f76..dc42ff010a 100644 --- a/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch +++ b/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch @@ -1,4 +1,4 @@ -From 3df7916fd6c198c8e58d6d4914ab06ebca3918bc Mon Sep 17 00:00:00 2001 +From 827c515038d43e1143d418d94d84f5e524f379aa Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 29 Apr 2026 20:38:17 -0600 Subject: [RUYI PATCH] UPSTREAM: riscv: Define diff --git a/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch index 74474ab04e..7f1f3d4585 100644 --- a/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ b/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -1,4 +1,4 @@ -From 2eae98ea7476677c8119a80ff9bf50c8a3600315 Mon Sep 17 00:00:00 2001 +From b950709b055b0574ff76824bfdb674410a09112d Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Thu, 21 May 2026 22:44:45 +0800 Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT diff --git a/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch index cee092d499..4042da2a5e 100644 --- a/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch +++ b/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch @@ -1,4 +1,4 @@ -From 4f4bff270953588decae0547de96ac02939beaad Mon Sep 17 00:00:00 2001 +From b7da1d402e48e261c72ea3f0b3cd368e88cd0731 Mon Sep 17 00:00:00 2001 From: Jiakai Xu Date: Sun, 17 May 2026 12:44:14 +0000 Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference in diff --git a/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch b/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch index e7deac9aea..931abf6629 100644 --- a/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch +++ b/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch @@ -1,4 +1,4 @@ -From bb40d8362ee33eb3d7341201cc0193113631e03c Mon Sep 17 00:00:00 2001 +From 6c7ef4de721d3b9e0965553bfc8242f28e0f350b Mon Sep 17 00:00:00 2001 From: Huan He Date: Sun, 19 Oct 2025 19:52:38 +0800 Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin diff --git a/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch b/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch index ca470143dd..f219d49ad8 100644 --- a/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch +++ b/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch @@ -1,4 +1,4 @@ -From 09f0d19162ff660efb7b93fd764ae93f6d004129 Mon Sep 17 00:00:00 2001 +From 4ec2ef8d7b9dde2c8f044bead5b65d4e39e3fd8c Mon Sep 17 00:00:00 2001 From: Huan He Date: Sun, 19 Oct 2025 19:53:16 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Add support for Eswin diff --git a/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch b/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch index 8991fa572e..e30b7d99e8 100644 --- a/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch +++ b/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch @@ -1,4 +1,4 @@ -From eec5a961f5c9f3a5b4a99624544700e30ae02323 Mon Sep 17 00:00:00 2001 +From 956564167124dc4f8549d22339a980eaf7730bf0 Mon Sep 17 00:00:00 2001 From: Huan He Date: Wed, 14 Jan 2026 20:21:41 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix init for AXI clock diff --git a/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch b/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch index 25b1fd7b47..861a6640bb 100644 --- a/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch +++ b/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch @@ -1,4 +1,4 @@ -From 3cd03e009502a385f88e1102cb0517e2f25f455c Mon Sep 17 00:00:00 2001 +From b96b065a3520d9551fc5a976f91c53ad36374536 Mon Sep 17 00:00:00 2001 From: Huan He Date: Wed, 14 Jan 2026 20:22:56 +0800 Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix DMA 128MB boundary diff --git a/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch b/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch deleted file mode 100644 index c72f779250..0000000000 --- a/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 07935065ada83928cfb96ceab6a5ec204787eed5 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:36 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Count paired job fence as - dependency in prepare_job() - -The DRM scheduler's prepare_job() callback counts the remaining -non-signaled native dependencies for a job, preventing job submission -until those (plus job data and fence update) can fit in the job queue's -CCCB. - -This means checking which dependencies can be waited upon in the -firmware, i.e. whether they are backed by a UFO object, i.e. whether -their drm_sched_fence::parent has been assigned to a -pvr_queue_fence::base fence. That happens when the job owning the fence -is submitted to the firmware. - -Paired geometry and fragment jobs are submitted at the same time, which -means the dependency between them can't be checked this way before -submission. - -Update job_count_remaining_native_deps() to take into account the -dependency between paired jobs. - -This fixes cases where prepare_job() underestimated the space left in -an almost full fragment CCCB, wrongly unblocking run_job(), which then -returned early without writing the full sequence of commands to the -CCCB. - -The above lead to kernel warnings such as the following and potentially -job timeouts (depending on waiters on the missing commands): - - [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 - [ 375.703160] Modules linked in: - [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT - [ 375.703613] Tainted: [W]=WARN - [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) - [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] - [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) - [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] - [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] - [ 375.703921] sp : ffff800084a97650 - [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 - [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 - [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 - [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 - [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 - [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 - [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 - [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 - [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 - [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f - [ 375.704317] Call trace: - [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) - [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] - [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] - [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] - [ 375.704623] process_one_work+0x520/0x1288 - [ 375.704658] worker_thread+0x3f0/0xb3c - [ 375.704680] kthread+0x334/0x3d8 - [ 375.704706] ret_from_fork+0x10/0x20 - [ 375.704736] ---[ end trace 0000000000000000 ]--- - -Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") -Cc: stable@vger.kernel.org -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 9cd74f935306cd857f46686975c43383e1d95f94 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 27 +++++++++++++++++++++---- - 1 file changed, 23 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index fc415dd0d7a7..8829c65747b6 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -179,7 +179,7 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { - - /** - * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is -- * backed by a UFO. -+ * already backed by a UFO. - * @f: The dma_fence to turn into a pvr_queue_fence. - * - * Return: -@@ -356,6 +356,15 @@ static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) - pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); - } - -+static bool -+is_paired_job_fence(struct dma_fence *fence, struct pvr_job *job) -+{ -+ /* This assumes "fence" is one of "job"'s drm_sched_job::dependencies */ -+ return job->type == DRM_PVR_JOB_TYPE_FRAGMENT && -+ job->paired_job && -+ &job->paired_job->base.s_fence->scheduled == fence; -+} -+ - /** - * job_count_remaining_native_deps() - Count the number of non-signaled native dependencies. - * @job: Job to operate on. -@@ -371,6 +380,17 @@ static unsigned long job_count_remaining_native_deps(struct pvr_job *job) - xa_for_each(&job->base.dependencies, index, fence) { - struct pvr_queue_fence *jfence; - -+ if (is_paired_job_fence(fence, job)) { -+ /* -+ * A fence between paired jobs won't resolve to a pvr_queue_fence (i.e. -+ * be backed by a UFO) until the jobs have been submitted, together. -+ * The submitting code will insert a partial render fence command for this. -+ */ -+ WARN_ON(dma_fence_is_signaled(fence)); -+ remaining_count++; -+ continue; -+ } -+ - jfence = to_pvr_queue_job_fence(fence); - if (!jfence) - continue; -@@ -630,9 +650,8 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -- /* Skip the partial render fence, we will place it at the end. */ -- if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job && -- &job->paired_job->base.s_fence->scheduled == fence) -+ /* This fence will be placed last, as partial render fence. */ -+ if (is_paired_job_fence(fence, job)) - continue; - - if (dma_fence_is_signaled(&jfence->base)) --- -2.53.0 - diff --git a/SPECS/linux-lts/0292-UPSTREAM-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux-lts/0292-UPSTREAM-riscv-Fix-fast_unaligned_access_speed_key-n.patch new file mode 100644 index 0000000000..bc05c34f71 --- /dev/null +++ b/SPECS/linux-lts/0292-UPSTREAM-riscv-Fix-fast_unaligned_access_speed_key-n.patch @@ -0,0 +1,68 @@ +From 6e571fa8e67dbd674e29f78d81c3ac573c603e38 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Tue, 7 Apr 2026 14:06:39 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: Fix fast_unaligned_access_speed_key not + getting initialized + +The static key fast_unaligned_access_speed_key is supposed to be +initialized after check_unaligned_access_all_cpus() has been completed. + +However, check_unaligned_access_all_cpus() has been moved to late_initcall +while setting fast_unaligned_access_speed_key still happens at +arch_initcall_sync, thus the static key does not get properly initialized. + +fast_unaligned_access_speed_key can still be initialized in CPU hotplug +events, but that cannot be relied on. + +Move fast_unaligned_access_speed_key's initialization into +check_unaligned_access_all_cpus() to fix this issue. This also prevent +someone from moving one initcall while forgetting the other in the future. + +Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") +Reported-by: Michael Neuling +Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ +Signed-off-by: Nam Cao +Link: https://patch.msgid.link/20260407120639.4006031-1-namcao@linutronix.de +Signed-off-by: Paul Walmsley +(cherry picked from commit aad60bdd0b5a6dfa40454ab03ce658408eaf4615) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/unaligned_access_speed.c | 15 ++++----------- + 1 file changed, 4 insertions(+), 11 deletions(-) + +diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c +index 70b5e6927620..5e224cc48c62 100644 +--- a/arch/riscv/kernel/unaligned_access_speed.c ++++ b/arch/riscv/kernel/unaligned_access_speed.c +@@ -223,17 +223,6 @@ static void set_unaligned_access_static_branches(void) + modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); + } + +-static int __init lock_and_set_unaligned_access_static_branch(void) +-{ +- cpus_read_lock(); +- set_unaligned_access_static_branches(); +- cpus_read_unlock(); +- +- return 0; +-} +- +-arch_initcall_sync(lock_and_set_unaligned_access_static_branch); +- + static int riscv_online_cpu(unsigned int cpu) + { + int ret = cpu_online_unaligned_access_init(cpu); +@@ -491,6 +480,10 @@ static int __init check_unaligned_access_all_cpus(void) + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu_vec, NULL); + ++ cpus_read_lock(); ++ set_unaligned_access_static_branches(); ++ cpus_read_unlock(); ++ + return 0; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch b/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch deleted file mode 100644 index 26a9e98208..0000000000 --- a/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch +++ /dev/null @@ -1,161 +0,0 @@ -From cc7e1eff70086b94e4cc0442c78e493d14ea2a91 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:37 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Fit paired fragment job in the - correct CCCB - -For geometry jobs with a paired fragment job, at the moment, the -DRM scheduler's prepare_job() callback: - -- checks for internal (driver) dependencies for the geometry job; -- calls into pvr_queue_get_paired_frag_job_dep() to check for external - dependencies for the fragment job (the two jobs are submitted together - but the common scheduler code doesn't know about it, so this needs to - be done at this point in time); -- calls into the prepare_job() callback again, but for the fragment job, - to check its internal dependencies as well, passing the fragment job's - drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. - -The problem with the last step is that pvr_queue_prepare_job() doesn't -always take the mismatched fragment job and geometry queue into account, -in particular when checking whether there is space for the fragment -command to be submitted, so the code ends up checking for space in the -geometry (i.e. wrong) CCCB. -The rest of the nested prepare_job() callback happens to work fine at -the moment as the other internal dependencies are not relevant for a -paired fragment job. - -Move the initialisation of a paired fragment job's done fence and CCCB -fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct -queue from the fragment job itself. - -This fixes cases where prepare_job() wrongly assumed that there was -enough space for a paired fragment job in its own CCCB, unblocking -run_job(), which then returned early without writing the full sequence -of commands to the CCCB. - -The above lead to kernel warnings such as the following and potentially -job timeouts (depending on waiters on the missing commands): - - [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 - [ 552.421230] Modules linked in: - [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT - [ 552.421625] Tainted: [W]=WARN - [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) - [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] - [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) - [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] - [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] - [ 552.421923] sp : ffff800084c47650 - [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 - [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 - [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 - [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 - [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 - [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 - [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 - [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 - [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 - [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f - [ 552.422316] Call trace: - [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) - [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] - [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] - [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] - [ 552.422623] process_one_work+0x520/0x1288 - [ 552.422657] worker_thread+0x3f0/0xb3c - [ 552.422679] kthread+0x334/0x3d8 - [ 552.422706] ret_from_fork+0x10/0x20 - -Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") -Cc: stable@vger.kernel.org -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 4baf9e70cb756d78dd56419f8baee2978a72d0c3 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 32 +++++++++++-------------- - 1 file changed, 14 insertions(+), 18 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 8829c65747b6..7d0d09026b82 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -488,10 +488,11 @@ pvr_queue_get_job_kccb_fence(struct pvr_queue *queue, struct pvr_job *job) - } - - static struct dma_fence * --pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) -+pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) - { - struct pvr_job *frag_job = job->type == DRM_PVR_JOB_TYPE_GEOMETRY ? - job->paired_job : NULL; -+ struct pvr_queue *frag_queue = frag_job ? frag_job->ctx->queues.fragment : NULL; - struct dma_fence *f; - unsigned long index; - -@@ -510,7 +511,10 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) - return dma_fence_get(f); - } - -- return frag_job->base.sched->ops->prepare_job(&frag_job->base, &queue->entity); -+ /* Initialize the paired fragment job's done_fence, so we can signal it. */ -+ pvr_queue_job_fence_init(frag_job->done_fence, frag_queue); -+ -+ return pvr_queue_get_job_cccb_fence(frag_queue, frag_job); - } - - /** -@@ -529,11 +533,6 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - struct pvr_queue *queue = container_of(s_entity, struct pvr_queue, entity); - struct dma_fence *internal_dep = NULL; - -- /* -- * Initialize the done_fence, so we can signal it. This must be done -- * here because otherwise by the time of run_job() the job will end up -- * in the pending list without a valid fence. -- */ - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { - /* - * This will be called on a paired fragment job after being -@@ -543,18 +542,15 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - */ - if (job->paired_job->has_pm_ref) - return NULL; -- -- /* -- * In this case we need to use the job's own ctx to initialise -- * the done_fence. The other steps are done in the ctx of the -- * paired geometry job. -- */ -- pvr_queue_job_fence_init(job->done_fence, -- job->ctx->queues.fragment); -- } else { -- pvr_queue_job_fence_init(job->done_fence, queue); - } - -+ /* -+ * Initialize the done_fence, so we can signal it. This must be done -+ * here because otherwise by the time of run_job() the job will end up -+ * in the pending list without a valid fence. -+ */ -+ pvr_queue_job_fence_init(job->done_fence, queue); -+ - /* CCCB fence is used to make sure we have enough space in the CCCB to - * submit our commands. - */ -@@ -575,7 +571,7 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - - /* The paired job fence should come last, when everything else is ready. */ - if (!internal_dep) -- internal_dep = pvr_queue_get_paired_frag_job_dep(queue, job); -+ internal_dep = pvr_queue_get_paired_frag_job_dep(job); - - return internal_dep; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0293-UPSTREAM-checkpatch-Suggest-kmalloc_obj-family-for-s.patch b/SPECS/linux-lts/0293-UPSTREAM-checkpatch-Suggest-kmalloc_obj-family-for-s.patch new file mode 100644 index 0000000000..bb7d00253d --- /dev/null +++ b/SPECS/linux-lts/0293-UPSTREAM-checkpatch-Suggest-kmalloc_obj-family-for-s.patch @@ -0,0 +1,84 @@ +From 0f2c5d969282094ed883fc5f1c347726659aad3d Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 3 Dec 2025 15:30:32 -0800 +Subject: [RUYI PATCH] UPSTREAM: checkpatch: Suggest kmalloc_obj family for + sizeof allocations + +To support shifting away from sized allocation towards typed +allocations, suggest the kmalloc_obj family of macros when a sizeof() is +present in the argument lists. + +Link: https://patch.msgid.link/20251203233036.3212363-2-kees@kernel.org +Signed-off-by: Kees Cook +(cherry picked from commit 070580b0b1740a4b930f367d21fdb5b253a8b3fb) +Signed-off-by: Han Gao +--- + scripts/checkpatch.pl | 39 +++++++++++++++++++++++++++++++++------ + 1 file changed, 33 insertions(+), 6 deletions(-) + +diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl +index 9979bf9f87bc..d85a5891e741 100755 +--- a/scripts/checkpatch.pl ++++ b/scripts/checkpatch.pl +@@ -7257,17 +7257,42 @@ sub process { + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +-# check for (kv|k)[mz]alloc with multiplies that could be kmalloc_array/kvmalloc_array/kvcalloc/kcalloc ++# check for (kv|k)[mz]alloc that could be kmalloc_obj/kvmalloc_obj/kzalloc_obj/kvzalloc_obj ++ if ($perl_version_ok && ++ defined $stat && ++ $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*,/) { ++ my $oldfunc = $3; ++ my $a1 = $4; ++ my $newfunc = "kmalloc_obj"; ++ $newfunc = "kvmalloc_obj" if ($oldfunc eq "kvmalloc"); ++ $newfunc = "kvzalloc_obj" if ($oldfunc eq "kvzalloc"); ++ $newfunc = "kzalloc_obj" if ($oldfunc eq "kzalloc"); ++ ++ if ($a1 =~ s/^sizeof\s*\S\(?([^\)]*)\)?$/$1/) { ++ my $cnt = statement_rawlines($stat); ++ my $herectx = get_stat_here($linenr, $cnt, $here); ++ ++ if (WARN("ALLOC_WITH_SIZEOF", ++ "Prefer $newfunc over $oldfunc with sizeof\n" . $herectx) && ++ $cnt == 1 && ++ $fix) { ++ $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*,/$1 = $newfunc($a1,/; ++ } ++ } ++ } ++ ++ ++# check for (kv|k)[mz]alloc with multiplies that could be kmalloc_objs/kvmalloc_objs/kzalloc_objs/kvzalloc_objs + if ($perl_version_ok && + defined $stat && + $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) { + my $oldfunc = $3; + my $a1 = $4; + my $a2 = $10; +- my $newfunc = "kmalloc_array"; +- $newfunc = "kvmalloc_array" if ($oldfunc eq "kvmalloc"); +- $newfunc = "kvcalloc" if ($oldfunc eq "kvzalloc"); +- $newfunc = "kcalloc" if ($oldfunc eq "kzalloc"); ++ my $newfunc = "kmalloc_objs"; ++ $newfunc = "kvmalloc_objs" if ($oldfunc eq "kvmalloc"); ++ $newfunc = "kvzalloc_objs" if ($oldfunc eq "kvzalloc"); ++ $newfunc = "kzalloc_objs" if ($oldfunc eq "kzalloc"); + my $r1 = $a1; + my $r2 = $a2; + if ($a1 =~ /^sizeof\s*\S/) { +@@ -7283,7 +7308,9 @@ sub process { + "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) && + $cnt == 1 && + $fix) { +- $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e; ++ my $sized = trim($r2); ++ $sized =~ s/^sizeof\s*\S\(?([^\)]*)\)?$/$1/; ++ $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k)[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . $sized . ', ' . trim($r1)/e; + } + } + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch b/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch deleted file mode 100644 index ef8b49eec6..0000000000 --- a/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch +++ /dev/null @@ -1,58 +0,0 @@ -From a64a810c6fa9b9f608d345c1c8fddcb487bf750a Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:38 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Skip check on paired job fence - during job submission - -While submitting a paired fragment job, there is no need to manually -look for, and skip, the paired job fence, as the existing logic to -resolve dependencies to pvr_queue_fence objects will have failed to -resolve it already and continued with the next one. - -Point this out where the fence is actually accessed and drop the related -check. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 18998b3cb7595850b8b2da55adb3fdc7aef8bc22 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 7d0d09026b82..6fdf74a1b73c 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -646,10 +646,6 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -- /* This fence will be placed last, as partial render fence. */ -- if (is_paired_job_fence(fence, job)) -- continue; -- - if (dma_fence_is_signaled(&jfence->base)) - continue; - -@@ -664,8 +660,13 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - } - } - -- /* Partial render fence goes last. */ - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { -+ /* -+ * The loop above will only process dependencies backed by a UFO i.e. with -+ * a valid parent fence assigned, but the paired job dependency won't have -+ * one until both jobs have been submitted. Access the parent fence directly -+ * here instead, submitting it last as partial render fence. -+ */ - jfence = to_pvr_queue_job_fence(job->paired_job->done_fence); - if (!WARN_ON(!jfence)) { - pvr_fw_object_get_fw_addr(jfence->queue->timeline_ufo.fw_obj, --- -2.53.0 - diff --git a/SPECS/linux-lts/0294-UPSTREAM-compiler_types-Introduce-__flex_counter-and.patch b/SPECS/linux-lts/0294-UPSTREAM-compiler_types-Introduce-__flex_counter-and.patch new file mode 100644 index 0000000000..905c983507 --- /dev/null +++ b/SPECS/linux-lts/0294-UPSTREAM-compiler_types-Introduce-__flex_counter-and.patch @@ -0,0 +1,145 @@ +From bb0199964817fab2ed25a40ae6a8b6f1df4e3bb9 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 3 Dec 2025 15:30:33 -0800 +Subject: [RUYI PATCH] UPSTREAM: compiler_types: Introduce __flex_counter() and + family + +Introduce __flex_counter() which wraps __builtin_counted_by_ref(), +as newly introduced by GCC[1] and Clang[2]. Use of __flex_counter() +allows access to the counter member of a struct's flexible array member +when it has been annotated with __counted_by(). + +Introduce typeof_flex_counter(), overflows_flex_counter_type(), and +__set_flex_counter() to provide the needed _Generic() wrappers to get +sane results out of __flex_counter(). + +For example, with: + + struct foo { + int counter; + short array[] __counted_by(counter); + } *p; + +__flex_counter(p->array) will resolve to: &p->counter + +typeof_flex_counter(p->array) will resolve to "int". (If p->array was not +annotated, it would resolve to "size_t".) + +overflows_flex_counter_type(typeof(*p), array, COUNT) is the same as: + + COUNT <= type_max(p->counter) && COUNT >= type_min(p->counter) + +(If p->array was not annotated it would return true since everything +fits in size_t.) + +__set_flex_counter(p->array, COUNT) is the same as: + + p->counter = COUNT; + +(It is a no-op if p->array is not annotated with __counted_by().) + +Link: https://patch.msgid.link/20251203233036.3212363-3-kees@kernel.org +Signed-off-by: Kees Cook +(cherry picked from commit 81cee9166a9073b4da28e970e75d7f89c98ed966) +Signed-off-by: Han Gao +--- + include/linux/compiler_types.h | 31 +++++++++++++++++++++++++ + include/linux/overflow.h | 42 ++++++++++++++++++++++++++++++++++ + 2 files changed, 73 insertions(+) + +diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h +index 2f18b8a01afe..1da5ab00193d 100644 +--- a/include/linux/compiler_types.h ++++ b/include/linux/compiler_types.h +@@ -529,6 +529,37 @@ struct ftrace_likely_data { + #define __annotated(var, attr) __builtin_has_attribute(var, attr) + #endif + ++/* ++ * Optional: only supported since gcc >= 15, clang >= 19 ++ * ++ * gcc: https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#index-_005f_005fbuiltin_005fcounted_005fby_005fref ++ * clang: https://clang.llvm.org/docs/LanguageExtensions.html#builtin-counted-by-ref ++ */ ++#if __has_builtin(__builtin_counted_by_ref) ++/** ++ * __flex_counter() - Get pointer to counter member for the given ++ * flexible array, if it was annotated with __counted_by() ++ * @FAM: Pointer to flexible array member of an addressable struct instance ++ * ++ * For example, with: ++ * ++ * struct foo { ++ * int counter; ++ * short array[] __counted_by(counter); ++ * } *p; ++ * ++ * __flex_counter(p->array) will resolve to &p->counter. ++ * ++ * Note that Clang may not allow this to be assigned to a separate ++ * variable; it must be used directly. ++ * ++ * If p->array is unannotated, this returns (void *)NULL. ++ */ ++#define __flex_counter(FAM) __builtin_counted_by_ref(FAM) ++#else ++#define __flex_counter(FAM) ((void *)NULL) ++#endif ++ + /* + * Some versions of gcc do not mark 'asm goto' volatile: + * +diff --git a/include/linux/overflow.h b/include/linux/overflow.h +index 725f95f7e416..f362e155a7ec 100644 +--- a/include/linux/overflow.h ++++ b/include/linux/overflow.h +@@ -540,4 +540,46 @@ static inline size_t __must_check size_sub(size_t minuend, size_t subtrahend) + (__member_size((name)->array) / sizeof(*(name)->array) + \ + __must_be_array((name)->array)) + ++/** ++ * typeof_flex_counter() - Return the type of the counter variable of a given ++ * flexible array member annotated by __counted_by(). ++ * @FAM: Instance of flexible array member within a given struct. ++ * ++ * Returns: "size_t" if no annotation exists. ++ */ ++#define typeof_flex_counter(FAM) \ ++ typeof(_Generic(__flex_counter(FAM), \ ++ void *: (size_t)0, \ ++ default: *__flex_counter(FAM))) ++ ++/** ++ * overflows_flex_counter_type() - Check if the counter associated with the ++ * given flexible array member can represent ++ * a value. ++ * @TYPE: Type of the struct that contains the @FAM. ++ * @FAM: Member name of the FAM within @TYPE. ++ * @COUNT: Value to check against the __counted_by annotated @FAM's counter. ++ * ++ * Returns: true if @COUNT can be represented in the @FAM's counter. When ++ * @FAM is not annotated with __counted_by(), always returns true. ++ */ ++#define overflows_flex_counter_type(TYPE, FAM, COUNT) \ ++ (!overflows_type(COUNT, typeof_flex_counter(((TYPE *)NULL)->FAM))) ++ ++/** ++ * __set_flex_counter() - Set the counter associated with the given flexible ++ * array member that has been annoated by __counted_by(). ++ * @FAM: Instance of flexible array member within a given struct. ++ * @COUNT: Value to store to the __counted_by annotated @FAM_PTR's counter. ++ * ++ * This is a no-op if no annotation exists. Count needs to be checked with ++ * overflows_flex_counter_type() before using this function. ++ */ ++#define __set_flex_counter(FAM, COUNT) \ ++({ \ ++ *_Generic(__flex_counter(FAM), \ ++ void *: &(size_t){ 0 }, \ ++ default: __flex_counter(FAM)) = (COUNT); \ ++}) ++ + #endif /* __LINUX_OVERFLOW_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch b/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch deleted file mode 100644 index 9cc27fddc4..0000000000 --- a/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 37bce3dfda3d6bfd8120dd4ca4ce59da566ffd8c Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:39 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename - pvr_queue_fence_is_ufo_backed() to reflect usage - -This function is only used by the synchronization code to figure out if -a fence belongs to this driver. -Rename it to pvr_queue_fence_is_native() and update its documentation to -reflect its current purpose. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit c162e655092de8de2e0f7776d72919dd5e3b84f2 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 14 +++++++------- - drivers/gpu/drm/imagination/pvr_queue.h | 2 +- - drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- - 3 files changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 6fdf74a1b73c..609ba457a619 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -898,16 +898,16 @@ static const struct drm_sched_backend_ops pvr_queue_sched_ops = { - }; - - /** -- * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO object -+ * pvr_queue_fence_is_native() - Check if a dma_fence is native to this driver. - * @f: Fence to test. - * -- * A UFO-backed fence is a fence that can be signaled or waited upon FW-side. -- * pvr_job::done_fence objects are backed by the timeline UFO attached to the queue -- * they are pushed to, but those fences are not directly exposed to the outside -- * world, so we also need to check if the fence we're being passed is a -- * drm_sched_fence that was coming from our driver. -+ * Check if the fence we're being passed is a drm_sched_fence that is coming from this driver. -+ * -+ * It may be a UFO-backed fence i.e. a fence that can be signaled or waited upon FW-side, -+ * such as pvr_job::done_fence objects that are backed by the timeline UFO attached to the queue -+ * they are pushed to. - */ --bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f) -+bool pvr_queue_fence_is_native(struct dma_fence *f) - { - struct drm_sched_fence *sched_fence = f ? to_drm_sched_fence(f) : NULL; - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.h b/drivers/gpu/drm/imagination/pvr_queue.h -index fc1986d73fc8..4aa72665ce25 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.h -+++ b/drivers/gpu/drm/imagination/pvr_queue.h -@@ -141,7 +141,7 @@ struct pvr_queue { - u64 callstack_addr; - }; - --bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f); -+bool pvr_queue_fence_is_native(struct dma_fence *f); - - int pvr_queue_job_init(struct pvr_job *job, u64 drm_client_id); - -diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c -index 129f646d14ba..d627c36e262f 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.c -+++ b/drivers/gpu/drm/imagination/pvr_sync.c -@@ -211,7 +211,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) - int err = 0; - - dma_fence_unwrap_for_each(uf, &iter, f) { -- if (pvr_queue_fence_is_ufo_backed(uf)) -+ if (pvr_queue_fence_is_native(uf)) - native_fence_count++; - } - -@@ -227,7 +227,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) - if (err) - continue; - -- if (pvr_queue_fence_is_ufo_backed(uf)) { -+ if (pvr_queue_fence_is_native(uf)) { - struct drm_sched_fence *s_fence = to_drm_sched_fence(uf); - - /* If this is a native dependency, we wait for the scheduled fence, --- -2.53.0 - diff --git a/SPECS/linux-lts/0295-UPSTREAM-slab-Introduce-kmalloc_flex-and-family.patch b/SPECS/linux-lts/0295-UPSTREAM-slab-Introduce-kmalloc_flex-and-family.patch new file mode 100644 index 0000000000..769e87b11d --- /dev/null +++ b/SPECS/linux-lts/0295-UPSTREAM-slab-Introduce-kmalloc_flex-and-family.patch @@ -0,0 +1,175 @@ +From d9fa1d68d8b36823ee40a365f0eab558c675d8f9 Mon Sep 17 00:00:00 2001 +From: Kees Cook +Date: Wed, 3 Dec 2025 15:30:34 -0800 +Subject: [RUYI PATCH] UPSTREAM: slab: Introduce kmalloc_flex() and family + +As done for kmalloc_obj*(), introduce a type-aware allocator for flexible +arrays, which may also have "counted_by" annotations: + + ptr = kmalloc(struct_size(ptr, flex_member, count), gfp); + +becomes: + + ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + +The internal use of __flex_counter() allows for automatically setting +the counter member of a struct's flexible array member when it has +been annotated with __counted_by(), avoiding any missed early size +initializations while __counted_by() annotations are added to the +kernel. Additionally, this also checks for "too large" allocations based +on the type size of the counter variable. For example: + + if (count > type_max(ptr->flex_counter)) + fail...; + size = struct_size(ptr, flex_member, count); + ptr = kmalloc(size, gfp); + if (!ptr) + fail...; + ptr->flex_counter = count; + +becomes (n.b. unchanged from earlier example): + + ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + if (!ptr) + fail...; + ptr->flex_counter = count; + +Note that manual initialization of the flexible array counter is still +required (at some point) after allocation as not all compiler versions +support the __counted_by annotation yet. But doing it internally makes +sure they cannot be missed when __counted_by _is_ available, meaning +that the bounds checker will not trip due to the lack of "early enough" +initializations that used to work before enabling the stricter bounds +checking. For example: + + ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + fill(ptr->flex, count); + ptr->flex_count = count; + +This works correctly before adding a __counted_by annotation (since +nothing is checking ptr->flex accesses against ptr->flex_count). After +adding the annotation, the bounds sanitizer would trip during fill() +because ptr->flex_count wasn't set yet. But with kmalloc_flex() setting +ptr->flex_count internally at allocation time, the existing code works +without needing to move the ptr->flex_count assignment before the call +to fill(). (This has been a stumbling block for __counted_by adoption.) + +Link: https://patch.msgid.link/20251203233036.3212363-4-kees@kernel.org +Acked-by: Vlastimil Babka +Signed-off-by: Kees Cook +(cherry picked from commit e4c8b46b924eb8de66c6f0accc9cdd0c2e8fa23b) +Signed-off-by: Han Gao +--- + Documentation/process/deprecated.rst | 7 ++++ + include/linux/slab.h | 48 ++++++++++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/Documentation/process/deprecated.rst b/Documentation/process/deprecated.rst +index 91c628fa2d59..fed56864d036 100644 +--- a/Documentation/process/deprecated.rst ++++ b/Documentation/process/deprecated.rst +@@ -387,6 +387,7 @@ allocations. For example, these open coded assignments:: + ptr = kzalloc(sizeof(*ptr), gfp); + ptr = kmalloc_array(count, sizeof(*ptr), gfp); + ptr = kcalloc(count, sizeof(*ptr), gfp); ++ ptr = kmalloc(struct_size(ptr, flex_member, count), gfp); + ptr = kmalloc(sizeof(struct foo, gfp); + + become, respectively:: +@@ -395,4 +396,10 @@ become, respectively:: + ptr = kzalloc_obj(*ptr, gfp); + ptr = kmalloc_objs(*ptr, count, gfp); + ptr = kzalloc_objs(*ptr, count, gfp); ++ ptr = kmalloc_flex(*ptr, flex_member, count, gfp); + __auto_type ptr = kmalloc_obj(struct foo, gfp); ++ ++If `ptr->flex_member` is annotated with __counted_by(), the allocation ++will automatically fail if `count` is larger than the maximum ++representable value that can be stored in the counter member associated ++with `flex_member`. +diff --git a/include/linux/slab.h b/include/linux/slab.h +index cbb64a2698f5..7701b38cedec 100644 +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -982,6 +982,33 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + (TYPE *)KMALLOC(__obj_size, GFP); \ + }) + ++/** ++ * __alloc_flex - Allocate an object that has a trailing flexible array ++ * @KMALLOC: kmalloc wrapper function to use for allocation. ++ * @GFP: GFP flags for the allocation. ++ * @TYPE: type of structure to allocate space for. ++ * @FAM: The name of the flexible array member of @TYPE structure. ++ * @COUNT: how many @FAM elements to allocate space for. ++ * ++ * Returns: Newly allocated pointer to @TYPE with @COUNT-many trailing ++ * @FAM elements, or NULL on failure or if @COUNT cannot be represented ++ * by the member of @TYPE that counts the @FAM elements (annotated via ++ * __counted_by()). ++ */ ++#define __alloc_flex(KMALLOC, GFP, TYPE, FAM, COUNT) \ ++({ \ ++ const size_t __count = (COUNT); \ ++ const size_t __obj_size = struct_size_t(TYPE, FAM, __count); \ ++ TYPE *__obj_ptr; \ ++ if (WARN_ON_ONCE(overflows_flex_counter_type(TYPE, FAM, __count))) \ ++ __obj_ptr = NULL; \ ++ else \ ++ __obj_ptr = KMALLOC(__obj_size, GFP); \ ++ if (__obj_ptr) \ ++ __set_flex_counter(__obj_ptr->FAM, __count); \ ++ __obj_ptr; \ ++}) ++ + /** + * kmalloc_obj - Allocate a single instance of the given type + * @VAR_OR_TYPE: Variable or type to allocate. +@@ -1005,23 +1032,44 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + #define kmalloc_objs(VAR_OR_TYPE, COUNT, GFP) \ + __alloc_objs(kmalloc, GFP, typeof(VAR_OR_TYPE), COUNT) + ++/** ++ * kmalloc_flex - Allocate a single instance of the given flexible structure ++ * @VAR_OR_TYPE: Variable or type to allocate (with its flex array). ++ * @FAM: The name of the flexible array member of the structure. ++ * @COUNT: How many flexible array member elements are desired. ++ * @GFP: GFP flags for the allocation. ++ * ++ * Returns: newly allocated pointer to @VAR_OR_TYPE on success, NULL on ++ * failure. If @FAM has been annotated with __counted_by(), the allocation ++ * will immediately fail if @COUNT is larger than what the type of the ++ * struct's counter variable can represent. ++ */ ++#define kmalloc_flex(VAR_OR_TYPE, FAM, COUNT, GFP) \ ++ __alloc_flex(kmalloc, GFP, typeof(VAR_OR_TYPE), FAM, COUNT) ++ + /* All kzalloc aliases for kmalloc_(obj|objs|flex). */ + #define kzalloc_obj(P, GFP) \ + __alloc_objs(kzalloc, GFP, typeof(P), 1) + #define kzalloc_objs(P, COUNT, GFP) \ + __alloc_objs(kzalloc, GFP, typeof(P), COUNT) ++#define kzalloc_flex(P, FAM, COUNT, GFP) \ ++ __alloc_flex(kzalloc, GFP, typeof(P), FAM, COUNT) + + /* All kvmalloc aliases for kmalloc_(obj|objs|flex). */ + #define kvmalloc_obj(P, GFP) \ + __alloc_objs(kvmalloc, GFP, typeof(P), 1) + #define kvmalloc_objs(P, COUNT, GFP) \ + __alloc_objs(kvmalloc, GFP, typeof(P), COUNT) ++#define kvmalloc_flex(P, FAM, COUNT, GFP) \ ++ __alloc_flex(kvmalloc, GFP, typeof(P), FAM, COUNT) + + /* All kvzalloc aliases for kmalloc_(obj|objs|flex). */ + #define kvzalloc_obj(P, GFP) \ + __alloc_objs(kvzalloc, GFP, typeof(P), 1) + #define kvzalloc_objs(P, COUNT, GFP) \ + __alloc_objs(kvzalloc, GFP, typeof(P), COUNT) ++#define kvzalloc_flex(P, FAM, COUNT, GFP) \ ++ __alloc_flex(kvzalloc, GFP, typeof(P), FAM, COUNT) + + #define kmem_buckets_alloc(_b, _size, _flags) \ + alloc_hooks(__kmalloc_node_noprof(PASS_BUCKET_PARAMS(_size, _b), _flags, NUMA_NO_NODE)) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch b/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch deleted file mode 100644 index 726a6e00f1..0000000000 --- a/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 1b5c97a61b1f397f31c97959e50a7bafe4997757 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:40 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename fence returned by - pvr_queue_job_arm() - -Rename from done_fence to finished_fence, both because the function -returns a drm_sched_fence's finished fence, and to avoid confusion with -the job fence, which is called the same but has a different purpose. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 5dae1a21f1e7128a19c68212422383f700699d01 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_job.c | 8 ++++---- - drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- - drivers/gpu/drm/imagination/pvr_sync.h | 2 +- - 3 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c -index 7564b0f21b42..2da61083ab3e 100644 ---- a/drivers/gpu/drm/imagination/pvr_job.c -+++ b/drivers/gpu/drm/imagination/pvr_job.c -@@ -326,7 +326,7 @@ prepare_job_syncs(struct pvr_file *pvr_file, - struct pvr_job_data *job_data, - struct xarray *signal_array) - { -- struct dma_fence *done_fence; -+ struct dma_fence *finished_fence; - int err = pvr_sync_signal_array_collect_ops(signal_array, - from_pvr_file(pvr_file), - job_data->sync_op_count, -@@ -359,13 +359,13 @@ prepare_job_syncs(struct pvr_file *pvr_file, - return err; - } - -- /* We need to arm the job to get the job done fence. */ -- done_fence = pvr_queue_job_arm(job_data->job); -+ /* We need to arm the job to get the job finished fence. */ -+ finished_fence = pvr_queue_job_arm(job_data->job); - - err = pvr_sync_signal_array_update_fences(signal_array, - job_data->sync_op_count, - job_data->sync_ops, -- done_fence); -+ finished_fence); - return err; - } - -diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c -index d627c36e262f..45ac7a0aff65 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.c -+++ b/drivers/gpu/drm/imagination/pvr_sync.c -@@ -160,7 +160,7 @@ int - pvr_sync_signal_array_update_fences(struct xarray *array, - u32 sync_op_count, - const struct drm_pvr_sync_op *sync_ops, -- struct dma_fence *done_fence) -+ struct dma_fence *finished_fence) - { - for (u32 i = 0; i < sync_op_count; i++) { - struct dma_fence *old_fence; -@@ -175,7 +175,7 @@ pvr_sync_signal_array_update_fences(struct xarray *array, - return -EINVAL; - - old_fence = sig_sync->fence; -- sig_sync->fence = dma_fence_get(done_fence); -+ sig_sync->fence = dma_fence_get(finished_fence); - dma_fence_put(old_fence); - - if (WARN_ON(!sig_sync->fence)) -diff --git a/drivers/gpu/drm/imagination/pvr_sync.h b/drivers/gpu/drm/imagination/pvr_sync.h -index db6ccfda104a..48501ad27794 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.h -+++ b/drivers/gpu/drm/imagination/pvr_sync.h -@@ -70,7 +70,7 @@ int - pvr_sync_signal_array_update_fences(struct xarray *array, - u32 sync_op_count, - const struct drm_pvr_sync_op *sync_ops, -- struct dma_fence *done_fence); -+ struct dma_fence *finished_fence); - - void - pvr_sync_signal_array_push_fences(struct xarray *array); --- -2.53.0 - diff --git a/SPECS/linux-lts/0296-UPSTREAM-slab.h-disable-completely-broken-overflow-h.patch b/SPECS/linux-lts/0296-UPSTREAM-slab.h-disable-completely-broken-overflow-h.patch new file mode 100644 index 0000000000..4eb6820d4d --- /dev/null +++ b/SPECS/linux-lts/0296-UPSTREAM-slab.h-disable-completely-broken-overflow-h.patch @@ -0,0 +1,70 @@ +From e163512ed18c577583d18b04cc24da6dfff50e4d Mon Sep 17 00:00:00 2001 +From: Linus Torvalds +Date: Sat, 21 Feb 2026 15:12:09 -0800 +Subject: [RUYI PATCH] UPSTREAM: slab.h: disable completely broken overflow + handling in flex allocations + +Commit 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for +non-scalar types") started using the new allocation helpers, and in the +process showed that they were completely non-working. + +The overflow logic in overflows_flex_counter_type() is completely the +wrong way around, and that broke __alloc_flex() completely. By chance, +the resulting code was then such a mess that clang generated +sufficiently garbage code that objtool warned about it all. Which made +it somewhat quicker to narrow things down. + +While fixing overflows_flex_counter_type() would presumably fix this +all, I'm excising the whole broken overflow logic from __alloc_flex(), +because we don't want that kind of code in basic allocation functions +anyway. + +That (no longer) broken overflows_flex_counter_type() thing needs to be +inserted into the actual __set_flex_counter() logic in the unlikely case +that we ever want this at all. And made conditional. + +Fixes: 81cee9166a90 ("compiler_types: Introduce __flex_counter() and family") +Fixes: 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for non-scalar types") +Cc: Kees Cook +Link: https://lore.kernel.org/all/CAHk-=whEd020BYzGTzYrENjD9Z5_82xx6h8HsQvH5xDSnv0=Hw@mail.gmail.com/ +Signed-off-by: Linus Torvalds +(cherry picked from commit fa5c82f4d2bbde10e9fd3a32aecacfe3813919ba) +Signed-off-by: Han Gao +--- + include/linux/overflow.h | 2 +- + include/linux/slab.h | 6 +----- + 2 files changed, 2 insertions(+), 6 deletions(-) + +diff --git a/include/linux/overflow.h b/include/linux/overflow.h +index f362e155a7ec..7b2e5b1d30ed 100644 +--- a/include/linux/overflow.h ++++ b/include/linux/overflow.h +@@ -564,7 +564,7 @@ static inline size_t __must_check size_sub(size_t minuend, size_t subtrahend) + * @FAM is not annotated with __counted_by(), always returns true. + */ + #define overflows_flex_counter_type(TYPE, FAM, COUNT) \ +- (!overflows_type(COUNT, typeof_flex_counter(((TYPE *)NULL)->FAM))) ++ (overflows_type(COUNT, typeof_flex_counter(((TYPE *)NULL)->FAM))) + + /** + * __set_flex_counter() - Set the counter associated with the given flexible +diff --git a/include/linux/slab.h b/include/linux/slab.h +index 7701b38cedec..4e9119d8bd4c 100644 +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -999,11 +999,7 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + ({ \ + const size_t __count = (COUNT); \ + const size_t __obj_size = struct_size_t(TYPE, FAM, __count); \ +- TYPE *__obj_ptr; \ +- if (WARN_ON_ONCE(overflows_flex_counter_type(TYPE, FAM, __count))) \ +- __obj_ptr = NULL; \ +- else \ +- __obj_ptr = KMALLOC(__obj_size, GFP); \ ++ TYPE *__obj_ptr = KMALLOC(__obj_size, GFP); \ + if (__obj_ptr) \ + __set_flex_counter(__obj_ptr->FAM, __count); \ + __obj_ptr; \ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch b/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch deleted file mode 100644 index aaa07dc5cb..0000000000 --- a/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 03aa10e9329f54737669ec56c2b2ab66eac2f987 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:41 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Move repeated job fence check - to its own function - -This should make the code slightly clearer. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 402562e60c6c1b15ee359ba7ffed907baa886a99 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 25 ++++++++++++++++++++----- - 1 file changed, 20 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 609ba457a619..2a26b87d146d 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -177,6 +177,24 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { - .release = pvr_queue_fence_release, - }; - -+/** -+ * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO. -+ * @f: The dma_fence to check. -+ * -+ * Return: -+ * * true if the dma_fence is backed by a UFO, or -+ * * false otherwise. -+ */ -+static inline bool -+pvr_queue_fence_is_ufo_backed(struct dma_fence *f) -+{ -+ /* -+ * Currently the only dma_fence backed by a UFO object is the job fence, -+ * e.g. pvr_job::done_fence, wrapped by a pvr_queue_fence object. -+ */ -+ return f && f->ops == &pvr_queue_job_fence_ops; -+} -+ - /** - * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is - * already backed by a UFO. -@@ -194,7 +212,7 @@ to_pvr_queue_job_fence(struct dma_fence *f) - if (sched_fence) - f = sched_fence->parent; - -- if (f && f->ops == &pvr_queue_job_fence_ops) -+ if (pvr_queue_fence_is_ufo_backed(f)) - return container_of(f, struct pvr_queue_fence, base); - - return NULL; -@@ -915,10 +933,7 @@ bool pvr_queue_fence_is_native(struct dma_fence *f) - sched_fence->sched->ops == &pvr_queue_sched_ops) - return true; - -- if (f && f->ops == &pvr_queue_job_fence_ops) -- return true; -- -- return false; -+ return pvr_queue_fence_is_ufo_backed(f); - } - - /** --- -2.53.0 - diff --git a/SPECS/linux-lts/0297-UPSTREAM-add-default_gfp-helper-macro-and-use-it-in-.patch b/SPECS/linux-lts/0297-UPSTREAM-add-default_gfp-helper-macro-and-use-it-in-.patch new file mode 100644 index 0000000000..40dd16ac19 --- /dev/null +++ b/SPECS/linux-lts/0297-UPSTREAM-add-default_gfp-helper-macro-and-use-it-in-.patch @@ -0,0 +1,135 @@ +From 6d5529550ccb5aa91a302877ba0554fc515ace92 Mon Sep 17 00:00:00 2001 +From: Linus Torvalds +Date: Sat, 21 Feb 2026 16:14:11 -0800 +Subject: [RUYI PATCH] UPSTREAM: add default_gfp() helper macro and use it in + the new *alloc_obj() helpers + +Most simple allocations use GFP_KERNEL, and with the new allocation +helpers being introduced, let's just take advantage of that to simplify +that default case. + +It's a numbers game: + + git grep 'alloc_obj(' | + sed 's/.*\(GFP_[_A-Z]*\).*/\1/' | + sort | uniq -c | sort -n | tail + +shows that about 90% of all those new allocator instances just use that +standard GFP_KERNEL. + +Those helpers are already macros, and we can easily just make it be the +default case when the gfp argument is missing. + +And yes, we could do that for all the legacy interfaces too, but let's +keep it to just the new ones at least for now, since those all got +converted recently anyway, so this is not any "extra" noise outside of +that limited conversion. + +And, in fact, I want to do this before doing the -rc1 release, exactly +so that we don't get extra merge conflicts. + +Signed-off-by: Linus Torvalds +(cherry picked from commit e19e1b480ac73c3e62ffebbca1174f0f511f43e7) +Signed-off-by: Han Gao +--- + include/linux/gfp.h | 4 ++++ + include/linux/slab.h | 48 ++++++++++++++++++++++---------------------- + 2 files changed, 28 insertions(+), 24 deletions(-) + +diff --git a/include/linux/gfp.h b/include/linux/gfp.h +index b155929af5b1..09559f7126ac 100644 +--- a/include/linux/gfp.h ++++ b/include/linux/gfp.h +@@ -13,6 +13,10 @@ + struct vm_area_struct; + struct mempolicy; + ++/* Helper macro to avoid gfp flags if they are the default one */ ++#define __default_gfp(a,...) a ++#define default_gfp(...) __default_gfp(__VA_ARGS__ __VA_OPT__(,) GFP_KERNEL) ++ + /* Convert GFP flags to their corresponding migrate type */ + #define GFP_MOVABLE_MASK (__GFP_RECLAIMABLE|__GFP_MOVABLE) + #define GFP_MOVABLE_SHIFT 3 +diff --git a/include/linux/slab.h b/include/linux/slab.h +index 4e9119d8bd4c..8f3c7f4948eb 100644 +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -1013,8 +1013,8 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + * Returns: newly allocated pointer to a @VAR_OR_TYPE on success, or NULL + * on failure. + */ +-#define kmalloc_obj(VAR_OR_TYPE, GFP) \ +- __alloc_objs(kmalloc, GFP, typeof(VAR_OR_TYPE), 1) ++#define kmalloc_obj(VAR_OR_TYPE, ...) \ ++ __alloc_objs(kmalloc, default_gfp(__VA_ARGS__), typeof(VAR_OR_TYPE), 1) + + /** + * kmalloc_objs - Allocate an array of the given type +@@ -1025,8 +1025,8 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + * Returns: newly allocated pointer to array of @VAR_OR_TYPE on success, + * or NULL on failure. + */ +-#define kmalloc_objs(VAR_OR_TYPE, COUNT, GFP) \ +- __alloc_objs(kmalloc, GFP, typeof(VAR_OR_TYPE), COUNT) ++#define kmalloc_objs(VAR_OR_TYPE, COUNT, ...) \ ++ __alloc_objs(kmalloc, default_gfp(__VA_ARGS__), typeof(VAR_OR_TYPE), COUNT) + + /** + * kmalloc_flex - Allocate a single instance of the given flexible structure +@@ -1040,32 +1040,32 @@ void *kmalloc_nolock_noprof(size_t size, gfp_t gfp_flags, int node); + * will immediately fail if @COUNT is larger than what the type of the + * struct's counter variable can represent. + */ +-#define kmalloc_flex(VAR_OR_TYPE, FAM, COUNT, GFP) \ +- __alloc_flex(kmalloc, GFP, typeof(VAR_OR_TYPE), FAM, COUNT) ++#define kmalloc_flex(VAR_OR_TYPE, FAM, COUNT, ...) \ ++ __alloc_flex(kmalloc, default_gfp(__VA_ARGS__), typeof(VAR_OR_TYPE), FAM, COUNT) + + /* All kzalloc aliases for kmalloc_(obj|objs|flex). */ +-#define kzalloc_obj(P, GFP) \ +- __alloc_objs(kzalloc, GFP, typeof(P), 1) +-#define kzalloc_objs(P, COUNT, GFP) \ +- __alloc_objs(kzalloc, GFP, typeof(P), COUNT) +-#define kzalloc_flex(P, FAM, COUNT, GFP) \ +- __alloc_flex(kzalloc, GFP, typeof(P), FAM, COUNT) ++#define kzalloc_obj(P, ...) \ ++ __alloc_objs(kzalloc, default_gfp(__VA_ARGS__), typeof(P), 1) ++#define kzalloc_objs(P, COUNT, ...) \ ++ __alloc_objs(kzalloc, default_gfp(__VA_ARGS__), typeof(P), COUNT) ++#define kzalloc_flex(P, FAM, COUNT, ...) \ ++ __alloc_flex(kzalloc, default_gfp(__VA_ARGS__), typeof(P), FAM, COUNT) + + /* All kvmalloc aliases for kmalloc_(obj|objs|flex). */ +-#define kvmalloc_obj(P, GFP) \ +- __alloc_objs(kvmalloc, GFP, typeof(P), 1) +-#define kvmalloc_objs(P, COUNT, GFP) \ +- __alloc_objs(kvmalloc, GFP, typeof(P), COUNT) +-#define kvmalloc_flex(P, FAM, COUNT, GFP) \ +- __alloc_flex(kvmalloc, GFP, typeof(P), FAM, COUNT) ++#define kvmalloc_obj(P, ...) \ ++ __alloc_objs(kvmalloc, default_gfp(__VA_ARGS__), typeof(P), 1) ++#define kvmalloc_objs(P, COUNT, ...) \ ++ __alloc_objs(kvmalloc, default_gfp(__VA_ARGS__), typeof(P), COUNT) ++#define kvmalloc_flex(P, FAM, COUNT, ...) \ ++ __alloc_flex(kvmalloc, default_gfp(__VA_ARGS__), typeof(P), FAM, COUNT) + + /* All kvzalloc aliases for kmalloc_(obj|objs|flex). */ +-#define kvzalloc_obj(P, GFP) \ +- __alloc_objs(kvzalloc, GFP, typeof(P), 1) +-#define kvzalloc_objs(P, COUNT, GFP) \ +- __alloc_objs(kvzalloc, GFP, typeof(P), COUNT) +-#define kvzalloc_flex(P, FAM, COUNT, GFP) \ +- __alloc_flex(kvzalloc, GFP, typeof(P), FAM, COUNT) ++#define kvzalloc_obj(P, ...) \ ++ __alloc_objs(kvzalloc, default_gfp(__VA_ARGS__), typeof(P), 1) ++#define kvzalloc_objs(P, COUNT, ...) \ ++ __alloc_objs(kvzalloc, default_gfp(__VA_ARGS__), typeof(P), COUNT) ++#define kvzalloc_flex(P, FAM, COUNT, ...) \ ++ __alloc_flex(kvzalloc, default_gfp(__VA_ARGS__), typeof(P), FAM, COUNT) + + #define kmem_buckets_alloc(_b, _size, _flags) \ + alloc_hooks(__kmalloc_node_noprof(PASS_BUCKET_PARAMS(_size, _b), _flags, NUMA_NO_NODE)) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch b/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch deleted file mode 100644 index c27054fa2d..0000000000 --- a/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch +++ /dev/null @@ -1,49 +0,0 @@ -From de6096b77f0bf0bf39ff10bd616f13c5e0945d58 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:42 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Update check to skip - prepare_job() for fragment jobs - -By the time prepare_job() is called on a paired fragment job, the paired -geometry job might already be finished and its PM reference dropped. - -Check the fragment job's PM reference instead which is a bit more likely -to be still set. This is a very minor optimization. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 5c81eb2970133ad073214eb1e5b0c34a1ae793eb - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 2a26b87d146d..00cc0dd4ca2b 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -553,12 +553,13 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { - /* -- * This will be called on a paired fragment job after being -- * submitted to firmware. We can tell if this is the case and -- * bail early from whether run_job() has been called on the -- * geometry job, which would issue a pm ref. -+ * This will be called on a paired fragment job after being submitted -+ * to the firmware as part of the paired geometry job's submission. -+ * We can tell if this is the case and bail early from whether run_job() -+ * has been called on the geometry job, which would issue a pm ref on -+ * this job as well. - */ -- if (job->paired_job->has_pm_ref) -+ if (job->has_pm_ref) - return NULL; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0298-UPSTREAM-of-Add-wrappers-to-match-root-node-with-OF-.patch b/SPECS/linux-lts/0298-UPSTREAM-of-Add-wrappers-to-match-root-node-with-OF-.patch new file mode 100644 index 0000000000..7288fce455 --- /dev/null +++ b/SPECS/linux-lts/0298-UPSTREAM-of-Add-wrappers-to-match-root-node-with-OF-.patch @@ -0,0 +1,125 @@ +From fe8a4dbdb43b413a60322ec8219c7316b5bf8125 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Wed, 12 Nov 2025 11:28:46 +0100 +Subject: [RUYI PATCH] UPSTREAM: of: Add wrappers to match root node with OF + device ID tables + +Several drivers duplicate same code for getting reference to the root +node, matching it against 'struct of_device_id' table and getting out +the match data from the table entry. + +There is a of_machine_compatible_match() wrapper but it takes array of +strings, which is not suitable for many drivers since they want the +driver data associated with each compatible. + +Add two wrappers, similar to existing of_device_get_match_data(): +1. of_machine_device_match() doing only matching against 'struct + of_device_id' and returning bool. +2. of_machine_get_match_data() doing the matching and returning + associated driver data for found compatible. + +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Lukasz Luba +Tested-by: AngeloGioacchino Del Regno +Link: https://patch.msgid.link/20251112-b4-of-match-matchine-data-v2-1-d46b72003fd6@linaro.org +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 4a93adcbd201aad5ba607810cfe1b19d44e5d171) +Signed-off-by: Han Gao +--- + drivers/of/base.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++ + include/linux/of.h | 13 +++++++++++++ + 2 files changed, 60 insertions(+) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index 6620bf07b79b..8d1972e18161 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -434,6 +434,53 @@ bool of_machine_compatible_match(const char *const *compats) + } + EXPORT_SYMBOL(of_machine_compatible_match); + ++/** ++ * of_machine_device_match - Test root of device tree against a of_device_id array ++ * @matches: NULL terminated array of of_device_id match structures to search in ++ * ++ * Returns true if the root node has any of the given compatible values in its ++ * compatible property. ++ */ ++bool of_machine_device_match(const struct of_device_id *matches) ++{ ++ struct device_node *root; ++ const struct of_device_id *match = NULL; ++ ++ root = of_find_node_by_path("/"); ++ if (root) { ++ match = of_match_node(matches, root); ++ of_node_put(root); ++ } ++ ++ return match != NULL; ++} ++EXPORT_SYMBOL(of_machine_device_match); ++ ++/** ++ * of_machine_get_match_data - Tell if root of device tree has a matching of_match structure ++ * @matches: NULL terminated array of of_device_id match structures to search in ++ * ++ * Returns data associated with matched entry or NULL ++ */ ++const void *of_machine_get_match_data(const struct of_device_id *matches) ++{ ++ const struct of_device_id *match; ++ struct device_node *root; ++ ++ root = of_find_node_by_path("/"); ++ if (!root) ++ return NULL; ++ ++ match = of_match_node(matches, root); ++ of_node_put(root); ++ ++ if (!match) ++ return NULL; ++ ++ return match->data; ++} ++EXPORT_SYMBOL(of_machine_get_match_data); ++ + static bool __of_device_is_status(const struct device_node *device, + const char * const*strings) + { +diff --git a/include/linux/of.h b/include/linux/of.h +index 121a288ca92d..01bb3affcd49 100644 +--- a/include/linux/of.h ++++ b/include/linux/of.h +@@ -407,6 +407,8 @@ extern int of_alias_get_id(const struct device_node *np, const char *stem); + extern int of_alias_get_highest_id(const char *stem); + + bool of_machine_compatible_match(const char *const *compats); ++bool of_machine_device_match(const struct of_device_id *matches); ++const void *of_machine_get_match_data(const struct of_device_id *matches); + + /** + * of_machine_is_compatible - Test root of device tree for a given compatible value +@@ -855,6 +857,17 @@ static inline bool of_machine_compatible_match(const char *const *compats) + return false; + } + ++static inline bool of_machine_device_match(const struct of_device_id *matches) ++{ ++ return false; ++} ++ ++static inline const void * ++of_machine_get_match_data(const struct of_device_id *matches) ++{ ++ return NULL; ++} ++ + static inline bool of_console_check(const struct device_node *dn, const char *name, int index) + { + return false; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch b/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch deleted file mode 100644 index e093399458..0000000000 --- a/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch +++ /dev/null @@ -1,141 +0,0 @@ -From fea5671abc67fb18ac13ed5ac838464e6ac1d034 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:43 +0100 -Subject: [RUYI PATCH] FROMGIT: drm/imagination: Minor improvements to job - submission code documentation - -Mixed list of clarifications and typo fixes. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-8-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 62a36c2da774800bef893bc4bf8922fb9c07c1d0 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 38 ++++++++++++------- - .../drm/imagination/pvr_rogue_fwif_shared.h | 10 +---- - 2 files changed, 26 insertions(+), 22 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 00cc0dd4ca2b..21803d3cfbb4 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -200,6 +200,13 @@ pvr_queue_fence_is_ufo_backed(struct dma_fence *f) - * already backed by a UFO. - * @f: The dma_fence to turn into a pvr_queue_fence. - * -+ * This could be called on: -+ * - a job fence directly, in which case it simply returns the containing pvr_queue_fence; -+ * - a drm_sched_fence's scheduled or finished fence, in which case it will first try to follow -+ * the parent pointer to find the job fence (note that the parent pointer is initialized -+ * only after the run_job() callback is called on the drm_sched_fence's owning job); -+ * - any other dma_fence, in which case it will return NULL. -+ * - * Return: - * * A non-NULL pvr_queue_fence object if the dma_fence is backed by a UFO, or - * * NULL otherwise. -@@ -367,11 +374,14 @@ static u32 ufo_cmds_size(u32 elem_count) - - static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) - { -- /* One UFO cmd for the fence signaling, one UFO cmd per native fence native, -- * and a command for the job itself. -+ /* -+ * One UFO command per native fence this job will be waiting on (unless any are -+ * signaled by the time the job is submitted), plus a command for the job itself, -+ * plus one UFO command for the fence signaling. - */ -- return ufo_cmds_size(1) + ufo_cmds_size(ufo_wait_count) + -- pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); -+ return ufo_cmds_size(ufo_wait_count) + -+ pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len) + -+ ufo_cmds_size(1); - } - - static bool -@@ -517,12 +527,16 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) - if (!frag_job) - return NULL; - -+ /* Have the geometry job wait on the paired fragment job's dependencies as well. */ - xa_for_each(&frag_job->base.dependencies, index, f) { - /* Skip already signaled fences. */ - if (dma_fence_is_signaled(f)) - continue; - -- /* Skip our own fence. */ -+ /* -+ * The paired job fence won't be signaled until both jobs have -+ * been submitted, so we can't wait on it to schedule them. -+ */ - if (f == &job->base.s_fence->scheduled) - continue; - -@@ -665,6 +679,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -+ /* Some dependencies might have been signaled since prepare_job() */ - if (dma_fence_is_signaled(&jfence->base)) - continue; - -@@ -714,7 +729,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - pvr_cccb_write_command_with_header(cccb, job->fw_ccb_cmd_type, job->cmd_len, job->cmd, - job->id, job->id); - -- /* Signal the job fence. */ -+ /* Update command to signal the job fence. */ - pvr_fw_object_get_fw_addr(queue->timeline_ufo.fw_obj, &ufos[0].addr); - ufos[0].value = job->done_fence->seqno; - pvr_cccb_write_command_with_header(cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE, -@@ -744,10 +759,8 @@ static struct dma_fence *pvr_queue_run_job(struct drm_sched_job *sched_job) - } - - /* The only kind of jobs that can be paired are geometry and fragment, and -- * we bail out early if we see a fragment job that's paired with a geomtry -- * job. -- * Paired jobs must also target the same context and point to the same -- * HWRT. -+ * we bail out early if we see a fragment job that's paired with a geometry job. -+ * Paired jobs must also target the same context and point to the same HWRT. - */ - if (WARN_ON(job->paired_job && - (job->type != DRM_PVR_JOB_TYPE_GEOMETRY || -@@ -966,9 +979,8 @@ pvr_queue_signal_done_fences(struct pvr_queue *queue) - } - - /** -- * pvr_queue_check_job_waiting_for_cccb_space() - Check if the job waiting for CCCB space -- * can be unblocked -- * pushed to the CCCB -+ * pvr_queue_check_job_waiting_for_cccb_space() - Check if a job waiting for CCCB space -+ * can be unblocked and pushed to the CCCB. - * @queue: Queue to check - * - * If we have a job waiting for CCCB, and this job now fits in the CCCB, we signal -diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -index 869d904e3649..fe54c1cad7a9 100644 ---- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -@@ -14,15 +14,7 @@ - - #define ROGUE_NUM_GEOM_CORES_SIZE 2U - --/* -- * Maximum number of UFOs in a CCB command. -- * The number is based on having 32 sync prims (as originally), plus 32 sync -- * checkpoints. -- * Once the use of sync prims is no longer supported, we will retain -- * the same total (64) as the number of sync checkpoints which may be -- * supporting a fence is not visible to the client driver and has to -- * allow for the number of different timelines involved in fence merges. -- */ -+/* Maximum number of UFOs in a CCB command. */ - #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) - - /* --- -2.53.0 - diff --git a/SPECS/linux-lts/0299-UPSTREAM-cpufreq-qcom-nvmem-add-compatible-fallback-.patch b/SPECS/linux-lts/0299-UPSTREAM-cpufreq-qcom-nvmem-add-compatible-fallback-.patch new file mode 100644 index 0000000000..9e4db2f1b7 --- /dev/null +++ b/SPECS/linux-lts/0299-UPSTREAM-cpufreq-qcom-nvmem-add-compatible-fallback-.patch @@ -0,0 +1,88 @@ +From 6855c96e22f6f0a72a729f84c4bc445490ba7569 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 5 Nov 2025 12:21:34 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: qcom-nvmem: add compatible fallback + for ipq806x for no SMEM + +On some IPQ806x SoC SMEM might be not initialized by SBL. This is the +case for some Google devices (the OnHub family) that can't make use of +SMEM to detect the SoC ID (and socinfo can't be used either as it does +depends on SMEM presence). + +To handle these specific case, check if the SMEM is not initialized (by +checking if the qcom_smem_get_soc_id returns -ENODEV) and fallback to +OF machine compatible checking to identify the SoC variant. + +Suggested-by: Dmitry Baryshkov +Reviewed-by: Konrad Dybcio +Signed-off-by: Christian Marangi +Signed-off-by: Viresh Kumar +(cherry picked from commit 58f5d39d5ed8f2e43f230389ea0d59791afdcd55) +Signed-off-by: Han Gao +--- + drivers/cpufreq/qcom-cpufreq-nvmem.c | 35 ++++++++++++++++++++++++++-- + 1 file changed, 33 insertions(+), 2 deletions(-) + +diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c +index 765a5bb81829..d5af74bf71c6 100644 +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -256,13 +256,22 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, + return ret; + } + ++static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] = { ++ { .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 }, ++ { .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 }, ++ { .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 }, ++ { .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 }, ++ { .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 }, ++ { .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 }, ++}; ++ + static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) + { ++ int msm_id = -1, ret = 0; + int speed = 0, pvs = 0; +- int msm_id, ret = 0; + u8 *speedbin; + size_t len; + +@@ -279,8 +288,30 @@ static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + ret = qcom_smem_get_soc_id(&msm_id); +- if (ret) ++ if (ret == -ENODEV) { ++ const struct of_device_id *match; ++ struct device_node *root; ++ ++ root = of_find_node_by_path("/"); ++ if (!root) { ++ ret = -ENODEV; ++ goto exit; ++ } ++ ++ /* Fallback to compatible match with no SMEM initialized */ ++ match = of_match_node(qcom_cpufreq_ipq806x_match_list, root); ++ of_node_put(root); ++ if (!match) { ++ ret = -ENODEV; ++ goto exit; ++ } ++ ++ /* We found a matching device, get the msm_id from the data entry */ ++ msm_id = (int)(uintptr_t)match->data; ++ ret = 0; ++ } else if (ret) { + goto exit; ++ } + + switch (msm_id) { + case QCOM_ID_IPQ8062: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch b/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch deleted file mode 100644 index ed087c87c3..0000000000 --- a/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From d6e9674d63435e685b8f714dd05c6d76d0cd3383 Mon Sep 17 00:00:00 2001 -From: Li Guan -Date: Thu, 14 May 2026 02:07:21 +0800 -Subject: [RUYI PATCH] FROMGIT: perf riscv: Fix discarded const qualifier in - _get_field() - -The assignment of strrchr() return values to non-const char * variables -triggers a -Werror=discarded-qualifiers warning when building with GCC -14. - -This happens because in newer glibc versions, strrchr() returns a 'const -char *' if the input string is const. - -Properly declare 'line2' and 'nl' as const char * to match the glibc -function signature and ensure type safety. This avoids the need for -explicit type casting and aligns with the design pattern of not -modifying read-only memory in the perf tool. - -Reviewed-by: Ian Rogers -Signed-off-by: Li Guan -Cc: Adrian Hunter -Cc: Namhyung Kim -Cc: Palmer Dabbelt -Cc: Paul Walmsley -Signed-off-by: Arnaldo Carvalho de Melo -(cherry picked from commit 7378b6656aa46fda56f2743d5a7c1f619c2f6f9b - https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git perf-tools-next) -Signed-off-by: Han Gao ---- - tools/perf/arch/riscv/util/header.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c -index 4b839203d4a5..891984e909bd 100644 ---- a/tools/perf/arch/riscv/util/header.c -+++ b/tools/perf/arch/riscv/util/header.c -@@ -19,7 +19,7 @@ - - static char *_get_field(const char *line) - { -- char *line2, *nl; -+ const char *line2, *nl; - - line2 = strrchr(line, ' '); - if (!line2) --- -2.53.0 - diff --git a/SPECS/linux-lts/0300-UPSTREAM-of-Add-of_machine_get_match-helper.patch b/SPECS/linux-lts/0300-UPSTREAM-of-Add-of_machine_get_match-helper.patch new file mode 100644 index 0000000000..d7d13d10c7 --- /dev/null +++ b/SPECS/linux-lts/0300-UPSTREAM-of-Add-of_machine_get_match-helper.patch @@ -0,0 +1,103 @@ +From 148e741934cb1a6081d7f61769f15d4b34bdebcc Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:05 +0100 +Subject: [RUYI PATCH] UPSTREAM: of: Add of_machine_get_match() helper + +Currently, there are two helpers to match the root compatible value +against an of_device_id array: + - of_machine_device_match() returns true if a match is found, + - of_machine_get_match_data() returns the match data if a match is + found. +However, there is no helper that returns the actual of_device_id +structure corresponding to the match, leading to code duplication in +various drivers. + +Fix this by reworking of_machine_device_match() to return the actual +match structure, and renaming it to of_machine_get_match(). +Retain the old of_machine_device_match() functionality using a cheap +static inline wrapper around the new of_machine_get_match() helper. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/14e1c03d443b1a5f210609ec3a1ebbaeab8fb3d9.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 82b6c1b542ea0530318c6f2a880d884eb4dce49f) +Signed-off-by: Han Gao +--- + drivers/of/base.c | 11 +++++------ + include/linux/of.h | 11 ++++++++--- + 2 files changed, 13 insertions(+), 9 deletions(-) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index 8d1972e18161..aca156128e3e 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -435,13 +435,12 @@ bool of_machine_compatible_match(const char *const *compats) + EXPORT_SYMBOL(of_machine_compatible_match); + + /** +- * of_machine_device_match - Test root of device tree against a of_device_id array ++ * of_machine_get_match - Test root of device tree against an of_device_id array + * @matches: NULL terminated array of of_device_id match structures to search in + * +- * Returns true if the root node has any of the given compatible values in its +- * compatible property. ++ * Returns matched entry or NULL + */ +-bool of_machine_device_match(const struct of_device_id *matches) ++const struct of_device_id *of_machine_get_match(const struct of_device_id *matches) + { + struct device_node *root; + const struct of_device_id *match = NULL; +@@ -452,9 +451,9 @@ bool of_machine_device_match(const struct of_device_id *matches) + of_node_put(root); + } + +- return match != NULL; ++ return match; + } +-EXPORT_SYMBOL(of_machine_device_match); ++EXPORT_SYMBOL(of_machine_get_match); + + /** + * of_machine_get_match_data - Tell if root of device tree has a matching of_match structure +diff --git a/include/linux/of.h b/include/linux/of.h +index 01bb3affcd49..698f42670c51 100644 +--- a/include/linux/of.h ++++ b/include/linux/of.h +@@ -407,7 +407,7 @@ extern int of_alias_get_id(const struct device_node *np, const char *stem); + extern int of_alias_get_highest_id(const char *stem); + + bool of_machine_compatible_match(const char *const *compats); +-bool of_machine_device_match(const struct of_device_id *matches); ++const struct of_device_id *of_machine_get_match(const struct of_device_id *matches); + const void *of_machine_get_match_data(const struct of_device_id *matches); + + /** +@@ -857,9 +857,9 @@ static inline bool of_machine_compatible_match(const char *const *compats) + return false; + } + +-static inline bool of_machine_device_match(const struct of_device_id *matches) ++static inline const struct of_device_id *of_machine_get_match(const struct of_device_id *matches) + { +- return false; ++ return NULL; + } + + static inline const void * +@@ -967,6 +967,11 @@ static inline int of_numa_init(void) + } + #endif + ++static inline bool of_machine_device_match(const struct of_device_id *matches) ++{ ++ return of_machine_get_match(matches) != NULL; ++} ++ + static inline struct device_node *of_find_matching_node( + struct device_node *from, + const struct of_device_id *matches) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch deleted file mode 100644 index df45fcf2dc..0000000000 --- a/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 9312f5952083473da163ade5c4b5f0cd1170caf2 Mon Sep 17 00:00:00 2001 -From: "Guo Ren (Alibaba DAMO Academy)" -Date: Tue, 21 Apr 2026 10:31:40 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE - fixup - -The early version of XuanTie C910 core has a store merge buffer -delay problem. The store merge buffer could improve the store queue -performance by merging multi-store requests, but when there are not -continued store requests, the prior single store request would be -waiting in the store queue for a long time. That would cause -significant problems for communication between multi-cores. This -problem was found on sg2042 & th1520 platforms with the qspinlock -lock torture test. - -So appending a fence w.o could immediately flush the store merge -buffer and let other cores see the write result. - -This will apply the WRITE_ONCE errata to handle the non-standard -behavior via appending a fence w.o instruction for WRITE_ONCE(). - -This problem is only observed on the sg2042 hardware platform by -running the lock_torture test program for half an hour. The problem -was not found in the user space application, because interrupt can -break the livelock. - -Acked-by: Arnd Bergmann -Reviewed-by: Alexandre Ghiti -Reviewed-by: Leonardo Bras -Reviewed-by: Inochi Amaoto -Tested-by: Han Gao -Tested-by: Yao Zi -Cc: Chen Wang -Cc: Xiaoguang Xing -Cc: Paul Walmsley -Signed-off-by: Guo Ren (Alibaba DAMO Academy) -Link: https://lore.kernel.org/r/20260421143154.1590156-1-guoren@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig.errata | 17 ++++++++++ - arch/riscv/errata/thead/errata.c | 20 ++++++++++++ - arch/riscv/include/asm/errata_list_vendors.h | 3 +- - arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ - include/asm-generic/rwonce.h | 2 ++ - 5 files changed, 75 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/include/asm/rwonce.h - -diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata -index aca9b0cfcfec..ac64123433e7 100644 ---- a/arch/riscv/Kconfig.errata -+++ b/arch/riscv/Kconfig.errata -@@ -153,4 +153,21 @@ config ERRATA_THEAD_GHOSTWRITE - - If you don't know what to do here, say "Y". - -+config ERRATA_THEAD_WRITE_ONCE -+ bool "Apply T-Head WRITE_ONCE errata" -+ depends on ERRATA_THEAD -+ default y -+ help -+ The early version of T-Head C9xx cores of sg2042 & th1520 have a store -+ merge buffer delay problem. The store merge buffer could improve the -+ store queue performance by merging multi-store requests, but when there -+ are no continued store requests, the prior single store request would be -+ waiting in the store queue for a long time. That would cause signifi- -+ cant problems for communication between multi-cores. Appending a -+ fence w.o could immediately flush the store merge buffer and let other -+ cores see the write result. -+ -+ This will apply the WRITE_ONCE errata to handle the non-standard beh- -+ avior via appending a fence w.o instruction for WRITE_ONCE(). -+ - endmenu # "CPU errata selection" -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index 0b942183f708..fbe46f2fa8fb 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, - return true; - } - -+static bool errata_probe_write_once(unsigned int stage, -+ unsigned long arch_id, unsigned long impid) -+{ -+ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) -+ return false; -+ -+ /* target-c9xx cores report arch_id and impid as 0 */ -+ if (arch_id != 0 || impid != 0) -+ return false; -+ -+ if (stage == RISCV_ALTERNATIVES_BOOT || -+ stage == RISCV_ALTERNATIVES_MODULE) -+ return true; -+ -+ return false; -+} -+ - static u32 thead_errata_probe(unsigned int stage, - unsigned long archid, unsigned long impid) - { -@@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, - - errata_probe_ghostwrite(stage, archid, impid); - -+ if (errata_probe_write_once(stage, archid, impid)) -+ cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); -+ - return cpu_req_errata; - } - -diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h -index ec7eba373437..8fd7c36307e2 100644 ---- a/arch/riscv/include/asm/errata_list_vendors.h -+++ b/arch/riscv/include/asm/errata_list_vendors.h -@@ -18,7 +18,8 @@ - #define ERRATA_THEAD_MAE 0 - #define ERRATA_THEAD_PMU 1 - #define ERRATA_THEAD_GHOSTWRITE 2 --#define ERRATA_THEAD_NUMBER 3 -+#define ERRATA_THEAD_WRITE_ONCE 3 -+#define ERRATA_THEAD_NUMBER 4 - #endif - - #ifdef CONFIG_ERRATA_MIPS -diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h -new file mode 100644 -index 000000000000..081793d4d772 ---- /dev/null -+++ b/arch/riscv/include/asm/rwonce.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __ASM_RWONCE_H -+#define __ASM_RWONCE_H -+ -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) -+ -+#define write_once_fence() \ -+do { \ -+ asm volatile(ALTERNATIVE( \ -+ "nop", \ -+ "fence w, o", \ -+ THEAD_VENDOR_ID, \ -+ ERRATA_THEAD_WRITE_ONCE, \ -+ CONFIG_ERRATA_THEAD_WRITE_ONCE) \ -+ : : : "memory"); \ -+} while (0) -+ -+#define __WRITE_ONCE(x, val) \ -+do { \ -+ *(volatile typeof(x) *)&(x) = (val); \ -+ write_once_fence(); \ -+} while (0) -+ -+#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ -+ -+#include -+ -+#endif /* __ASM_RWONCE_H */ -diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h -index 52b969c7cef9..4e2d941f15a1 100644 ---- a/include/asm-generic/rwonce.h -+++ b/include/asm-generic/rwonce.h -@@ -50,10 +50,12 @@ - __READ_ONCE(x); \ - }) - -+#ifndef __WRITE_ONCE - #define __WRITE_ONCE(x, val) \ - do { \ - *(volatile typeof(x) *)&(x) = (val); \ - } while (0) -+#endif - - #define WRITE_ONCE(x, val) \ - do { \ --- -2.53.0 - diff --git a/SPECS/linux-lts/0301-UPSTREAM-of-Convert-to-of_machine_get_match.patch b/SPECS/linux-lts/0301-UPSTREAM-of-Convert-to-of_machine_get_match.patch new file mode 100644 index 0000000000..017a7b3d0c --- /dev/null +++ b/SPECS/linux-lts/0301-UPSTREAM-of-Convert-to-of_machine_get_match.patch @@ -0,0 +1,42 @@ +From 17fc1a4886108c056f9d0729bbd97965fcb74e37 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:06 +0100 +Subject: [RUYI PATCH] UPSTREAM: of: Convert to of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/83ed49314b94dab7781e1d74236af72dd5c349c6.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 57814f2e0cd7960fc8bbe097c05fdf2c3f8c67e4) +Signed-off-by: Han Gao +--- + drivers/of/base.c | 9 +-------- + 1 file changed, 1 insertion(+), 8 deletions(-) + +diff --git a/drivers/of/base.c b/drivers/of/base.c +index aca156128e3e..ff142b650732 100644 +--- a/drivers/of/base.c ++++ b/drivers/of/base.c +@@ -464,15 +464,8 @@ EXPORT_SYMBOL(of_machine_get_match); + const void *of_machine_get_match_data(const struct of_device_id *matches) + { + const struct of_device_id *match; +- struct device_node *root; +- +- root = of_find_node_by_path("/"); +- if (!root) +- return NULL; +- +- match = of_match_node(matches, root); +- of_node_put(root); + ++ match = of_machine_get_match(matches); + if (!match) + return NULL; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch deleted file mode 100644 index 747ee38919..0000000000 --- a/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 4c835b4cf54a8879850b5743cbe7d75d2b218c9c Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:56:57 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native - PCIe port services - -Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe -port service driver from probing specific devices. This provides a -per-device equivalent of the global pcie_ports=compat kernel parameter. - -Some platforms have PCIe root ports that break MSI delivery to downstream -devices when native port services (AER, PME, bwctrl, etc.) are active. -The existing pci_host_bridge native_* flags do not cover all services -(notably bwctrl), so a mechanism to skip port driver probing entirely -on a per-device basis is needed. - -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331175658.1015829-2-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pci/pcie/portdrv.c | 3 +++ - include/linux/pci.h | 2 ++ - 2 files changed, 5 insertions(+) - -diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c -index a0991da48213..315a8d9cb440 100644 ---- a/drivers/pci/pcie/portdrv.c -+++ b/drivers/pci/pcie/portdrv.c -@@ -684,6 +684,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { - static int pcie_portdrv_probe(struct pci_dev *dev, - const struct pci_device_id *id) - { -+ if (dev->dev_flags & PCI_DEV_FLAGS_NO_PORT_SERVICES) -+ return -ENODEV; -+ - int type = pci_pcie_type(dev); - int status; - -diff --git a/include/linux/pci.h b/include/linux/pci.h -index cdf67f5aa239..daf7f2363658 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -253,6 +253,8 @@ enum pci_dev_flags { - * integrated with the downstream devices and doesn't use real PCI. - */ - PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), -+ /* Do not use native PCIe port services (equivalent to pcie_ports=compat) */ -+ PCI_DEV_FLAGS_NO_PORT_SERVICES = (__force pci_dev_flags_t) (1 << 15), - }; - - enum pci_irq_reroute_variant { --- -2.53.0 - diff --git a/SPECS/linux-lts/0302-UPSTREAM-cpufreq-airoha-Convert-to-of_machine_get_ma.patch b/SPECS/linux-lts/0302-UPSTREAM-cpufreq-airoha-Convert-to-of_machine_get_ma.patch new file mode 100644 index 0000000000..dbb7d59334 --- /dev/null +++ b/SPECS/linux-lts/0302-UPSTREAM-cpufreq-airoha-Convert-to-of_machine_get_ma.patch @@ -0,0 +1,43 @@ +From 0fee0e576719e3ba3b9977be709f64a2e4dd6957 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:07 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: airoha: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/cc76137755d93af982bf255095adafc7d523692c.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 1838e0924e508eb30e140ad8f037863ee53be3c6) +Signed-off-by: Han Gao +--- + drivers/cpufreq/airoha-cpufreq.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/cpufreq/airoha-cpufreq.c b/drivers/cpufreq/airoha-cpufreq.c +index b6b1cdc4d11d..3e7770860d13 100644 +--- a/drivers/cpufreq/airoha-cpufreq.c ++++ b/drivers/cpufreq/airoha-cpufreq.c +@@ -115,15 +115,10 @@ MODULE_DEVICE_TABLE(of, airoha_cpufreq_match_list); + + static int __init airoha_cpufreq_init(void) + { +- struct device_node *np = of_find_node_by_path("/"); + const struct of_device_id *match; + int ret; + +- if (!np) +- return -ENODEV; +- +- match = of_match_node(airoha_cpufreq_match_list, np); +- of_node_put(np); ++ match = of_machine_get_match(airoha_cpufreq_match_list); + if (!match) + return -ENODEV; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch deleted file mode 100644 index 58cd59ae0c..0000000000 --- a/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch +++ /dev/null @@ -1,60 +0,0 @@ -From cfb56bdda1f734ba778e001d5436e62217a69a3c Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:56:58 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services - on Sophgo SG2042 - -SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to -downstream devices when native port services are enabled. Devices under -an affected root port receive zero interrupts despite successful vector -allocation, causing driver timeouts (e.g. amdgpu fence fallback timer -expired on all rings). - -Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the -port service driver from probing, restoring correct MSI delivery. - -Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 12 ++++++++++++ - include/linux/pci_ids.h | 2 ++ - 2 files changed, 14 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 481e4186a5c1..28d23f8dfd60 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -6388,3 +6388,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); - #endif -+ -+/* -+ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to -+ * downstream devices when native PCIe port services are enabled. All -+ * services including bwctrl must be disabled, equivalent to pcie_ports=compat. -+ */ -+static void quirk_sg2042_no_port_services(struct pci_dev *dev) -+{ -+ pci_info(dev, "SG2042: disabling native PCIe port services\n"); -+ dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 2b6692a5005f..7c01548a6ddb 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2633,6 +2633,8 @@ - - #define PCI_VENDOR_ID_CXL 0x1e98 - -+#define PCI_VENDOR_ID_SOPHGO 0x1f1c -+ - #define PCI_VENDOR_ID_TEHUTI 0x1fc9 - #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 - #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --- -2.53.0 - diff --git a/SPECS/linux-lts/0303-UPSTREAM-cpufreq-qcom-nvmem-Convert-to-of_machine_ge.patch b/SPECS/linux-lts/0303-UPSTREAM-cpufreq-qcom-nvmem-Convert-to-of_machine_ge.patch new file mode 100644 index 0000000000..37ca1acf10 --- /dev/null +++ b/SPECS/linux-lts/0303-UPSTREAM-cpufreq-qcom-nvmem-Convert-to-of_machine_ge.patch @@ -0,0 +1,61 @@ +From eaadc023345ed1e272a0f77cdd4cc7f503116a3d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:08 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: qcom-nvmem: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/886a603a7a1de6c8cb14ee0783ee0bceea4d914a.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 8cd94ead5184c5bdde74dc0afc316c6f3c41fdd7) +Signed-off-by: Han Gao +--- + drivers/cpufreq/qcom-cpufreq-nvmem.c | 16 ++-------------- + 1 file changed, 2 insertions(+), 14 deletions(-) + +diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c +index d5af74bf71c6..be06a4762e35 100644 +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -290,17 +290,9 @@ static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + ret = qcom_smem_get_soc_id(&msm_id); + if (ret == -ENODEV) { + const struct of_device_id *match; +- struct device_node *root; +- +- root = of_find_node_by_path("/"); +- if (!root) { +- ret = -ENODEV; +- goto exit; +- } + + /* Fallback to compatible match with no SMEM initialized */ +- match = of_match_node(qcom_cpufreq_ipq806x_match_list, root); +- of_node_put(root); ++ match = of_machine_get_match(qcom_cpufreq_ipq806x_match_list); + if (!match) { + ret = -ENODEV; + goto exit; +@@ -646,14 +638,10 @@ MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); + */ + static int __init qcom_cpufreq_init(void) + { +- struct device_node *np __free(device_node) = of_find_node_by_path("/"); + const struct of_device_id *match; + int ret; + +- if (!np) +- return -ENODEV; +- +- match = of_match_node(qcom_cpufreq_match_list, np); ++ match = of_machine_get_match(qcom_cpufreq_match_list); + if (!match) + return -ENODEV; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch deleted file mode 100644 index 92052a71a6..0000000000 --- a/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch +++ /dev/null @@ -1,83 +0,0 @@ -From ef760574ea2b96b482691e4b76ea4544d2b04231 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= -Date: Thu, 18 Sep 2025 13:58:56 -0700 -Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to - allow GPU BAR resize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Resizing BAR to a larger size has to release upstream bridge windows in -order make the bridge windows larger as well (and to potential relocate -them into a larger free block within iomem space). Some GPUs have an -integrated PCI switch that has BAR0. The resource allocation assigns -space for that BAR0 as it does for any resource. - -An extra resource on a bridge will pin its upstream bridge window in -place which prevents BAR resize for anything beneath that bridge. - -Nothing in the pcieport driver provided by PCI core, which typically is -the driver bound to these bridges, requires that BAR0. Because of that, -releasing the extra BAR does not seem to have notable downsides but -comes with a clear upside. - -Therefore, release BAR0 of such switches using a quirk and clear its -flags to prevent any new invocation of the resource assignment -algorithm from assigning the resource again. - -Due to other siblings within the PCI hierarchy of all the devices -integrated into the GPU, some other devices may still have to be -manually removed before the resize is free of any bridge window pins. -Such siblings can be released through sysfs to unpin windows while -leaving access to GPU's sysfs entries required for initiating the -resize operation, whereas removing the topmost bridge this quirk -targets would result in removing the GPU device as well so no manual -workaround for this problem exists. - -Reported-by: Lucas De Marchi -Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ -Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ -Signed-off-by: Ilpo Järvinen -Cc: stable@vger.kernel.org # v6.12+ -Signed-off-by: Lucas De Marchi -Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com -Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 28d23f8dfd60..f0cd6c2a7827 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -6400,3 +6400,26 @@ static void quirk_sg2042_no_port_services(struct pci_dev *dev) - dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; - } - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); -+ -+/* -+ * PCI switches integrated into Intel Arc GPUs have BAR0 that prevents -+ * resizing the BARs of the GPU device due to that bridge BAR0 pinning the -+ * bridge window it's under in place. Nothing in pcieport requires that -+ * BAR0. -+ * -+ * Release and disable BAR0 permanently by clearing its flags to prevent -+ * anything from assigning it again. -+ */ -+static void pci_release_bar0(struct pci_dev *pdev) -+{ -+ struct resource *res = pci_resource_n(pdev, 0); -+ -+ if (!res->parent) -+ return; -+ -+ pci_release_resource(pdev, 0); -+ res->flags = 0; -+} -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa0, pci_release_bar0); -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa1, pci_release_bar0); -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0xe2ff, pci_release_bar0); --- -2.53.0 - diff --git a/SPECS/linux-lts/0304-UPSTREAM-cpufreq-ti-cpufreq-Convert-to-of_machine_ge.patch b/SPECS/linux-lts/0304-UPSTREAM-cpufreq-ti-cpufreq-Convert-to-of_machine_ge.patch new file mode 100644 index 0000000000..9c60d5bb9c --- /dev/null +++ b/SPECS/linux-lts/0304-UPSTREAM-cpufreq-ti-cpufreq-Convert-to-of_machine_ge.patch @@ -0,0 +1,52 @@ +From 9cd245b383317da14e142085b8c2bc2e39f8874e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:09 +0100 +Subject: [RUYI PATCH] UPSTREAM: cpufreq: ti-cpufreq: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/bba0631aea78b6db7d453a9f9e98ea16b7e2c269.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 951318c4651a646f4835ae33abe7c4cb232e7c6e) +Signed-off-by: Han Gao +--- + drivers/cpufreq/ti-cpufreq.c | 12 +----------- + 1 file changed, 1 insertion(+), 11 deletions(-) + +diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c +index 6ee76f5fe9c5..0c27c89b7853 100644 +--- a/drivers/cpufreq/ti-cpufreq.c ++++ b/drivers/cpufreq/ti-cpufreq.c +@@ -470,16 +470,6 @@ static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = { + {}, + }; + +-static const struct of_device_id *ti_cpufreq_match_node(void) +-{ +- struct device_node *np __free(device_node) = of_find_node_by_path("/"); +- const struct of_device_id *match; +- +- match = of_match_node(ti_cpufreq_of_match, np); +- +- return match; +-} +- + static int ti_cpufreq_probe(struct platform_device *pdev) + { + u32 version[VERSION_COUNT]; +@@ -564,7 +554,7 @@ static int __init ti_cpufreq_init(void) + const struct of_device_id *match; + + /* Check to ensure we are on a compatible platform */ +- match = ti_cpufreq_match_node(); ++ match = of_machine_get_match(ti_cpufreq_of_match); + if (match) + platform_device_register_data(NULL, "ti-cpufreq", -1, match, + sizeof(*match)); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch deleted file mode 100644 index 826058c0bf..0000000000 --- a/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 1f52ff4a8952f2dcd39f984b094e0d3ba4227bcd Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sat, 29 Jun 2024 13:22:46 +0800 -Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA - coherency status in ttm_device - -Currently TTM utilizes cached memory regardless of whether the device -have full DMA coherency (can snoop CPU cache). - -Save the device's DMA coherency status in struct ttm_device, to allow -further support of devices w/o snooping capability (the capability -missing on at least one part of the transmission between the CPU and the -device). - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20240629052247.2653363-2-uwu@icenowy.me -[ Han Gao: add conditional compilation for dma_coherent ] -Signed-off-by: Han Gao ---- - drivers/gpu/drm/ttm/ttm_device.c | 6 ++++++ - include/drm/ttm/ttm_device.h | 9 +++++++++ - 2 files changed, 15 insertions(+) - -diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c -index c3e2fcbdd2cc..1758d94b3d44 100644 ---- a/drivers/gpu/drm/ttm/ttm_device.c -+++ b/drivers/gpu/drm/ttm/ttm_device.c -@@ -246,6 +246,12 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func - list_add_tail(&bdev->device_list, &glob->device_list); - mutex_unlock(&ttm_global_mutex); - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ bdev->dma_coherent = dev->dma_coherent; -+#endif -+ - return 0; - } - EXPORT_SYMBOL(ttm_device_init); -diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h -index 592b5f802859..c2e61312a43a 100644 ---- a/include/drm/ttm/ttm_device.h -+++ b/include/drm/ttm/ttm_device.h -@@ -225,6 +225,15 @@ struct ttm_device { - */ - const struct ttm_device_funcs *funcs; - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /** -+ * @dma_coherent: if the device backed is dma-coherent. -+ */ -+ bool dma_coherent; -+#endif -+ - /** - * @sysman: Resource manager for the system domain. - * Access via ttm_manager_type. --- -2.53.0 - diff --git a/SPECS/linux-lts/0305-UPSTREAM-soc-qcom-pd-mapper-Convert-to-of_machine_ge.patch b/SPECS/linux-lts/0305-UPSTREAM-soc-qcom-pd-mapper-Convert-to-of_machine_ge.patch new file mode 100644 index 0000000000..7550a0c61e --- /dev/null +++ b/SPECS/linux-lts/0305-UPSTREAM-soc-qcom-pd-mapper-Convert-to-of_machine_ge.patch @@ -0,0 +1,44 @@ +From e2e5cd5b291fd8acdb66195ec90de58a96638242 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 2 Mar 2026 17:29:10 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: qcom: pd-mapper: Convert to + of_machine_get_match() + +Use the of_machine_get_match() helper instead of open-coding the same +operation. + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Konrad Dybcio +Acked-by: Viresh Kumar +Link: https://patch.msgid.link/0d23a449e62ac85f04ff07bc2758efbaa709c9d1.1772468323.git.geert+renesas@glider.be +Signed-off-by: Rob Herring (Arm) +(cherry picked from commit 3ee3d8a44976ac7e39584637ee4c840d70ab2ad1) +Signed-off-by: Han Gao +--- + drivers/soc/qcom/qcom_pd_mapper.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c +index 6384f271953d..56d2377fb8b1 100644 +--- a/drivers/soc/qcom/qcom_pd_mapper.c ++++ b/drivers/soc/qcom/qcom_pd_mapper.c +@@ -605,15 +605,9 @@ static struct qcom_pdm_data *qcom_pdm_start(void) + const struct qcom_pdm_domain_data * const *domains; + const struct of_device_id *match; + struct qcom_pdm_data *data; +- struct device_node *root; + int ret, i; + +- root = of_find_node_by_path("/"); +- if (!root) +- return ERR_PTR(-ENODEV); +- +- match = of_match_node(qcom_pdm_domains, root); +- of_node_put(root); ++ match = of_machine_get_match(qcom_pdm_domains); + if (!match) { + pr_notice("PDM: no support for the platform, userspace daemon might be required.\n"); + return ERR_PTR(-ENODEV); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch deleted file mode 100644 index bb46fa248c..0000000000 --- a/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 555ac6aeaf274981371546928300e152ff7ac153 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sat, 29 Jun 2024 13:22:47 +0800 -Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to - write_combined when snooping not available - -As we can now acquire the presence of the full DMA coherency (snooping -capability) from ttm_device, we can now map the CPU side memory as -write-combined when cached is requested and snooping is not avilable. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20240629052247.2653363-3-uwu@icenowy.me -[ Han Gao: add conditional compilation for dma coherent operations ] -[ Icenowy: omit single page ttm_cached optimization when non-coherent and handle linear io iter ] -Signed-off-by: Han Gao ---- - drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +++++++++++++ - drivers/gpu/drm/ttm/ttm_resource.c | 13 +++++++++++-- - drivers/gpu/drm/ttm/ttm_tt.c | 8 ++++++++ - include/drm/ttm/ttm_caching.h | 3 ++- - 4 files changed, 34 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c -index acbbca9d5c92..2a8777d1f2b8 100644 ---- a/drivers/gpu/drm/ttm/ttm_bo_util.c -+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c -@@ -307,6 +307,14 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res, - caching = res->bus.caching; - } - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bo->bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - return ttm_prot_from_caching(caching, tmp); - } - EXPORT_SYMBOL(ttm_io_prot); -@@ -360,6 +368,11 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, - return ret; - - if (num_pages == 1 && ttm->caching == ttm_cached && -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ bo->bdev->dma_coherent && -+#endif - !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { - /* - * We're mapping a single page, and the desired -diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c -index 2a05fbd07546..4f18a9a98f11 100644 ---- a/drivers/gpu/drm/ttm/ttm_resource.c -+++ b/drivers/gpu/drm/ttm/ttm_resource.c -@@ -830,8 +830,17 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, - struct ttm_device *bdev, - struct ttm_resource *mem) - { -+ enum ttm_caching caching = mem->bus.caching; - int ret; - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - ret = ttm_mem_io_reserve(bdev, mem); - if (ret) - goto out_err; -@@ -846,11 +855,11 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, - } else { - iter_io->needs_unmap = true; - memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); -- if (mem->bus.caching == ttm_write_combined) -+ if (caching == ttm_write_combined) - iosys_map_set_vaddr_iomem(&iter_io->dmap, - ioremap_wc(mem->bus.offset, - mem->size)); -- else if (mem->bus.caching == ttm_cached) -+ else if (caching == ttm_cached) - iosys_map_set_vaddr(&iter_io->dmap, - memremap(mem->bus.offset, mem->size, - MEMREMAP_WB | -diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c -index 506e257dfba8..8338deb3330f 100644 ---- a/drivers/gpu/drm/ttm/ttm_tt.c -+++ b/drivers/gpu/drm/ttm/ttm_tt.c -@@ -154,6 +154,14 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, - enum ttm_caching caching, - unsigned long extra_pages) - { -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bo->bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; - ttm->page_flags = page_flags; - ttm->dma_address = NULL; -diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h -index a18f43e93aba..f92d7911f50e 100644 ---- a/include/drm/ttm/ttm_caching.h -+++ b/include/drm/ttm/ttm_caching.h -@@ -47,7 +47,8 @@ enum ttm_caching { - - /** - * @ttm_cached: Fully cached like normal system memory, requires that -- * devices snoop the CPU cache on accesses. -+ * devices snoop the CPU cache on accesses. Downgraded to -+ * ttm_write_combined when the snooping capaiblity is missing. - */ - ttm_cached - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0306-UPSTREAM-init-deduplicate-cc-can-link.sh-invocations.patch b/SPECS/linux-lts/0306-UPSTREAM-init-deduplicate-cc-can-link.sh-invocations.patch new file mode 100644 index 0000000000..d9ac5cc345 --- /dev/null +++ b/SPECS/linux-lts/0306-UPSTREAM-init-deduplicate-cc-can-link.sh-invocations.patch @@ -0,0 +1,57 @@ +From 47f12485bbbdd57fa80c7323c7c2e70e379985f1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Fri, 14 Nov 2025 14:43:57 +0100 +Subject: [RUYI PATCH] UPSTREAM: init: deduplicate cc-can-link.sh invocations +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The command to invoke scripts/cc-can-link.sh is very long and new usages +are about to be added. + +Add a helper variable to make the code easier to read and maintain. + +Signed-off-by: Thomas Weißschuh +Reviewed-by: Nicolas Schier +Reviewed-by: Nathan Chancellor +Link: https://patch.msgid.link/20251114-kbuild-userprogs-bits-v3-2-4dee0d74d439@linutronix.de +Signed-off-by: Nicolas Schier +(cherry picked from commit 80623f2c83d7de5c289d4240b8f4cef4103c51fc) +Signed-off-by: Han Gao +--- + init/Kconfig | 4 ++-- + scripts/Kconfig.include | 3 +++ + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/init/Kconfig b/init/Kconfig +index cab3ad28ca49..7b722e714d5c 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -84,8 +84,8 @@ config RUSTC_LLVM_VERSION + + config CC_CAN_LINK + bool +- default $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(m64-flag)) if 64BIT +- default $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(m32-flag)) ++ default $(cc_can_link_user,$(m64-flag)) if 64BIT ++ default $(cc_can_link_user,$(m32-flag)) + + # Fixed in GCC 14, 13.3, 12.4 and 11.5 + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113921 +diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include +index 33193ca6e803..d42042b6c9e2 100644 +--- a/scripts/Kconfig.include ++++ b/scripts/Kconfig.include +@@ -65,6 +65,9 @@ cc-option-bit = $(if-success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null,$ + m32-flag := $(cc-option-bit,-m32) + m64-flag := $(cc-option-bit,-m64) + ++# Test whether the compiler can link userspace applications ++cc_can_link_user = $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(1)) ++ + rustc-version := $(shell,$(srctree)/scripts/rustc-version.sh $(RUSTC)) + rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch deleted file mode 100644 index 58e516d738..0000000000 --- a/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 5911aa5fe93310aba068d9a4361bc5827ce35b62 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:16 +0000 -Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP - table for TH1520 - -Add operating point table for CPU cores, and wire up clocks for CPU -nodes. - -This patch isn't intended for upstreaming but only for testing purpose, -since the PMIC driver for scaling CPU voltage isn't ready yet. Only -operating points whose voltage is satisified by Lichee Module 4A's PMIC -default, i.e. <= 1.5GHz, are enabled. - -Signed-off-by: Yao Zi -Link: https://lore.kernel.org/r/20251120131416.26236-8-ziyao@disroot.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 35 +++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 5e91dc1d2b9b..2910249e1f0c 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -38,6 +38,8 @@ c910_0: cpu@0 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -65,6 +67,8 @@ c910_1: cpu@1 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -92,6 +96,8 @@ c910_2: cpu@2 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -119,6 +125,8 @@ c910_3: cpu@3 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -137,6 +145,33 @@ l2_cache: l2-cache { - }; - }; - -+ cpu_opp: opp-table-cpu { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <600000>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <700000>; -+ }; -+ -+ opp-1500000000 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <800000>; -+ }; -+ -+/* -+ opp-1848000000 { -+ opp-hz = /bits/ 64 <1848000000>; -+ opp-microvolt = <1000000>; -+ }; -+ */ -+ }; -+ - pmu { - compatible = "riscv,pmu"; - riscv,event-to-mhpmcounters = --- -2.53.0 - diff --git a/SPECS/linux-lts/0307-UPSTREAM-kbuild-allow-architectures-to-override-CC_C.patch b/SPECS/linux-lts/0307-UPSTREAM-kbuild-allow-architectures-to-override-CC_C.patch new file mode 100644 index 0000000000..8fe2478493 --- /dev/null +++ b/SPECS/linux-lts/0307-UPSTREAM-kbuild-allow-architectures-to-override-CC_C.patch @@ -0,0 +1,76 @@ +From 5145724870f7f6189dd6daa9500771e4c3184a29 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Fri, 14 Nov 2025 14:43:58 +0100 +Subject: [RUYI PATCH] UPSTREAM: kbuild: allow architectures to override + CC_CAN_LINK +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The generic test for CC_CAN_LINK assumes that all architectures use -m32 +and -m64 to switch between 32-bit and 64-bit compilation. This is overly +simplistic. Architectures may use other flags (-mabi, -m31, etc.) or may +also require byte order handling (-mlittle-endian, -EL). Expressing all +of the different possibilities will be very complicated and brittle. +Instead allow architectures to supply their own logic which will be +easy to understand and evolve. + +Both the boolean ARCH_HAS_CC_CAN_LINK and the string ARCH_USERFLAGS need +to be implemented as kconfig does not allow the reuse of string options. + +Signed-off-by: Thomas Weißschuh +Reviewed-by: Nicolas Schier +Reviewed-by: Nathan Chancellor +Link: https://patch.msgid.link/20251114-kbuild-userprogs-bits-v3-3-4dee0d74d439@linutronix.de +Signed-off-by: Nicolas Schier +(cherry picked from commit deab487e0f9b39ae4603e22d7d00908ebfc9753c) +Signed-off-by: Han Gao +--- + Makefile | 13 +++++++++++-- + init/Kconfig | 4 ++++ + 2 files changed, 15 insertions(+), 2 deletions(-) + +diff --git a/Makefile b/Makefile +index 7ee3beedceca..8ae52cf42da5 100644 +--- a/Makefile ++++ b/Makefile +@@ -1156,8 +1156,17 @@ ifneq ($(CONFIG_ARCH_VMLINUX_NEEDS_RELOCS),) + LDFLAGS_vmlinux += --emit-relocs --discard-none + endif + +-# Align the bit size of userspace programs with the kernel +-USERFLAGS_FROM_KERNEL := -m32 -m64 --target=% ++# Align the architecture of userspace programs with the kernel ++USERFLAGS_FROM_KERNEL := --target=% ++ ++ifdef CONFIG_ARCH_USERFLAGS ++KBUILD_USERCFLAGS += $(CONFIG_ARCH_USERFLAGS) ++KBUILD_USERLDFLAGS += $(CONFIG_ARCH_USERFLAGS) ++else ++# If not overridden also inherit the bit size ++USERFLAGS_FROM_KERNEL += -m32 -m64 ++endif ++ + KBUILD_USERCFLAGS += $(filter $(USERFLAGS_FROM_KERNEL), $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS)) + KBUILD_USERLDFLAGS += $(filter $(USERFLAGS_FROM_KERNEL), $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS)) + +diff --git a/init/Kconfig b/init/Kconfig +index 7b722e714d5c..4a2ae3cfbf26 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -82,8 +82,12 @@ config RUSTC_LLVM_VERSION + int + default $(rustc-llvm-version) + ++config ARCH_HAS_CC_CAN_LINK ++ bool ++ + config CC_CAN_LINK + bool ++ default ARCH_CC_CAN_LINK if ARCH_HAS_CC_CAN_LINK + default $(cc_can_link_user,$(m64-flag)) if 64BIT + default $(cc_can_link_user,$(m32-flag)) + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch deleted file mode 100644 index 207ec24976..0000000000 --- a/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 1331a7f7caf771503583f18f7576c01b13e887ec Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:54 +0100 -Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate - Makefile - -A subsequent commit will add a new function `bindgen-option` to -`scripts/Kconfig.include`. The bindgen backend requires the `--target` -option for cross compiling, but variable `BINDGEN_TARGET` in -`rust/Makefile` cannot be exported to `scripts/Kconfig.include`. - -Therefore, move this variable to a separate new `Makefile.rust` file and -include it from `scripts/Makefile` to make the exported variable -available for use in Kconfig. Place the include in the `need-compiler` -branch to avoid including it in irrelevant make targets. - -Since the new file name is `Makefile.rust`, it matches an existing -MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS -file is needed. - -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-1-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - Makefile | 3 ++- - rust/Makefile | 8 -------- - scripts/Makefile.rust | 9 +++++++++ - 3 files changed, 11 insertions(+), 9 deletions(-) - create mode 100644 scripts/Makefile.rust - -diff --git a/Makefile b/Makefile -index 5087bd6183dd..e5901ed88254 100644 ---- a/Makefile -+++ b/Makefile -@@ -724,9 +724,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) - include $(srctree)/scripts/Makefile.clang - endif - -+ifdef need-compiler -+include $(srctree)/scripts/Makefile.rust - # Include this also for config targets because some architectures need - # cc-cross-prefix to determine CROSS_COMPILE. --ifdef need-compiler - include $(srctree)/scripts/Makefile.compiler - endif - -diff --git a/rust/Makefile b/rust/Makefile -index d4618f646b05..c311d16e7e74 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -300,14 +300,6 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fzero-init-padding-bits=% -mno-fdpic \ - --param=% --param asan-% -fno-isolate-erroneous-paths-dereference - --# Derived from `scripts/Makefile.clang`. --BINDGEN_TARGET_x86 := x86_64-linux-gnu --BINDGEN_TARGET_arm64 := aarch64-linux-gnu --BINDGEN_TARGET_arm := arm-linux-gnueabi --BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf --BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) --BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) -- - # All warnings are inhibited since GCC builds are very experimental, - # many GCC warnings are not supported by Clang, they may only appear in - # some configurations, with new GCC versions, etc. -diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust -new file mode 100644 -index 000000000000..5c12b4b8c8b6 ---- /dev/null -+++ b/scripts/Makefile.rust -@@ -0,0 +1,9 @@ -+# Derived from `scripts/Makefile.clang`. -+BINDGEN_TARGET_x86 := x86_64-linux-gnu -+BINDGEN_TARGET_arm64 := aarch64-linux-gnu -+BINDGEN_TARGET_arm := arm-linux-gnueabi -+BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf -+BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) -+BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) -+ -+export BINDGEN_TARGET --- -2.53.0 - diff --git a/SPECS/linux-lts/0308-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux-lts/0308-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch new file mode 100644 index 0000000000..6e1d1080ec --- /dev/null +++ b/SPECS/linux-lts/0308-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch @@ -0,0 +1,44 @@ +From cf338d06de5e4ef58b84b81bbc067c2c24163a24 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add reset + support + +The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus +which shared by all controllers, while another one connect to individual +controller separately. + +Signed-off-by: Yixun Lan +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Ulf Hansson +(cherry picked from commit 4231325cfb87f712fcbe1fcbeea4186d18c78513) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 383841369fb2..9a055d963a7f 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -34,6 +34,16 @@ properties: + - const: core + - const: io + ++ resets: ++ items: ++ - description: axi reset, connect to AXI bus, shared by all controllers ++ - description: sdh reset, connect to individual controller separately ++ ++ reset-names: ++ items: ++ - const: axi ++ - const: sdh ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch deleted file mode 100644 index 99ff4e9cc0..0000000000 --- a/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 22c8be25d1ed7a76f36d5f1d30f0c61faa68b951 Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:55 +0100 -Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET - is undefined - -Generate a friendly fatal error if the target triplet is undefined for -bindgen, rather than having the compiler generate obscure error messages -during the build stage. - -`BINDGEN_TARGET` is actually defined in `scripts/Makefile.rust`, but the -file is included regardless of whether Rust is enabled, so perform this -check in `rust/Makefile` to avoid breaking targets that do not yet -support Rust builds. - -This piece of code is copied from `scripts/Makefile.clang`. - -Before this commit, error messages might look like: - -error: unknown argument: '-mno-riscv-attribute' -error: unsupported argument 'medany' to option '-mcmodel=' for target -'unknown' -error: unsupported option '-march=' for target '' -error: unsupported option '-mno-save-restore' for target '' -error: unknown target triple 'unknown' -panicked at bindgen/ir/context.rs:562:15: -libclang error; possible causes include: -- Invalid flag syntax -- Unrecognized flags -- Invalid flag arguments -- File I/O errors -- Host vs. target architecture mismatch - -Acked-by: Miguel Ojeda -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-2-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - rust/Makefile | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/rust/Makefile b/rust/Makefile -index c311d16e7e74..6d2d542a55e8 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -300,6 +300,12 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fzero-init-padding-bits=% -mno-fdpic \ - --param=% --param asan-% -fno-isolate-erroneous-paths-dereference - -+# Because scripts/Makefile.rust is included regardless of whether Rust is enabled, -+# we perform this check here to avoid breaking targets that do not yet support Rust builds. -+ifeq ($(BINDGEN_TARGET),) -+$(error add '--target=' option to scripts/Makefile.rust) -+endif -+ - # All warnings are inhibited since GCC builds are very experimental, - # many GCC warnings are not supported by Clang, they may only appear in - # some configurations, with new GCC versions, etc. --- -2.53.0 - diff --git a/SPECS/linux-lts/0309-UPSTREAM-drm-imagination-Count-paired-job-fence-as-d.patch b/SPECS/linux-lts/0309-UPSTREAM-drm-imagination-Count-paired-job-fence-as-d.patch new file mode 100644 index 0000000000..077a474e9a --- /dev/null +++ b/SPECS/linux-lts/0309-UPSTREAM-drm-imagination-Count-paired-job-fence-as-d.patch @@ -0,0 +1,137 @@ +From b3bf69fd4a4d2738496929312af9b0b7f59e8ca3 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:36 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Count paired job fence as + dependency in prepare_job() + +The DRM scheduler's prepare_job() callback counts the remaining +non-signaled native dependencies for a job, preventing job submission +until those (plus job data and fence update) can fit in the job queue's +CCCB. + +This means checking which dependencies can be waited upon in the +firmware, i.e. whether they are backed by a UFO object, i.e. whether +their drm_sched_fence::parent has been assigned to a +pvr_queue_fence::base fence. That happens when the job owning the fence +is submitted to the firmware. + +Paired geometry and fragment jobs are submitted at the same time, which +means the dependency between them can't be checked this way before +submission. + +Update job_count_remaining_native_deps() to take into account the +dependency between paired jobs. + +This fixes cases where prepare_job() underestimated the space left in +an almost full fragment CCCB, wrongly unblocking run_job(), which then +returned early without writing the full sequence of commands to the +CCCB. + +The above lead to kernel warnings such as the following and potentially +job timeouts (depending on waiters on the missing commands): + + [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 + [ 375.703160] Modules linked in: + [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT + [ 375.703613] Tainted: [W]=WARN + [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) + [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] + [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] + [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] + [ 375.703921] sp : ffff800084a97650 + [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 + [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 + [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 + [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 + [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 + [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 + [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 + [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 + [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 + [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f + [ 375.704317] Call trace: + [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) + [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] + [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] + [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] + [ 375.704623] process_one_work+0x520/0x1288 + [ 375.704658] worker_thread+0x3f0/0xb3c + [ 375.704680] kthread+0x334/0x3d8 + [ 375.704706] ret_from_fork+0x10/0x20 + [ 375.704736] ---[ end trace 0000000000000000 ]--- + +Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") +Cc: stable@vger.kernel.org +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 9cd74f935306cd857f46686975c43383e1d95f94) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 27 +++++++++++++++++++++---- + 1 file changed, 23 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index fc415dd0d7a7..8829c65747b6 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -179,7 +179,7 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { + + /** + * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is +- * backed by a UFO. ++ * already backed by a UFO. + * @f: The dma_fence to turn into a pvr_queue_fence. + * + * Return: +@@ -356,6 +356,15 @@ static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) + pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); + } + ++static bool ++is_paired_job_fence(struct dma_fence *fence, struct pvr_job *job) ++{ ++ /* This assumes "fence" is one of "job"'s drm_sched_job::dependencies */ ++ return job->type == DRM_PVR_JOB_TYPE_FRAGMENT && ++ job->paired_job && ++ &job->paired_job->base.s_fence->scheduled == fence; ++} ++ + /** + * job_count_remaining_native_deps() - Count the number of non-signaled native dependencies. + * @job: Job to operate on. +@@ -371,6 +380,17 @@ static unsigned long job_count_remaining_native_deps(struct pvr_job *job) + xa_for_each(&job->base.dependencies, index, fence) { + struct pvr_queue_fence *jfence; + ++ if (is_paired_job_fence(fence, job)) { ++ /* ++ * A fence between paired jobs won't resolve to a pvr_queue_fence (i.e. ++ * be backed by a UFO) until the jobs have been submitted, together. ++ * The submitting code will insert a partial render fence command for this. ++ */ ++ WARN_ON(dma_fence_is_signaled(fence)); ++ remaining_count++; ++ continue; ++ } ++ + jfence = to_pvr_queue_job_fence(fence); + if (!jfence) + continue; +@@ -630,9 +650,8 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + +- /* Skip the partial render fence, we will place it at the end. */ +- if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job && +- &job->paired_job->base.s_fence->scheduled == fence) ++ /* This fence will be placed last, as partial render fence. */ ++ if (is_paired_job_fence(fence, job)) + continue; + + if (dma_fence_is_signaled(&jfence->base)) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch deleted file mode 100644 index f14c7c2ccd..0000000000 --- a/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0bae0d06c2aca802becde0cd7d5cb153390dcd4d Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:56 +0100 -Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for - support of bindgen options - -Add a new `bindgen-backend-option` Kconfig function to test whether the -bindgen backend supports a given flag. - -A subsequent commit will use this function to test for RISC-V extension -flags. - -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-3-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - scripts/Kconfig.include | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include -index 33193ca6e803..c7360e1e59ab 100644 ---- a/scripts/Kconfig.include -+++ b/scripts/Kconfig.include -@@ -75,3 +75,8 @@ rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) - # If you are testing for unstable features, consider testing RUSTC_VERSION - # instead, as features may have different completeness while available. - rustc-option = $(success,trap "rm -rf .tmp_$$" EXIT; mkdir .tmp_$$; $(RUSTC) $(1) --crate-type=rlib /dev/null --out-dir=.tmp_$$ -o .tmp_$$/tmp.rlib) -+ -+# $(bindgen-backend-option,) -+# Return y if bindgen backend supports , n otherwise -+# For now, the backend refers only to libclang, so more specifically, this function tests whether the given flag is recognized by the libclang used by bindgen. -+bindgen-backend-option = $(success,$(BINDGEN) /dev/null -- -x c --target=$(BINDGEN_TARGET) $(1)) --- -2.53.0 - diff --git a/SPECS/linux-lts/0310-UPSTREAM-drm-imagination-Fit-paired-fragment-job-in-.patch b/SPECS/linux-lts/0310-UPSTREAM-drm-imagination-Fit-paired-fragment-job-in-.patch new file mode 100644 index 0000000000..25983da88f --- /dev/null +++ b/SPECS/linux-lts/0310-UPSTREAM-drm-imagination-Fit-paired-fragment-job-in-.patch @@ -0,0 +1,160 @@ +From 6dcaba0f69bca88b0f2f3aaebc2164b16f142bcc Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:37 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Fit paired fragment job in + the correct CCCB + +For geometry jobs with a paired fragment job, at the moment, the +DRM scheduler's prepare_job() callback: + +- checks for internal (driver) dependencies for the geometry job; +- calls into pvr_queue_get_paired_frag_job_dep() to check for external + dependencies for the fragment job (the two jobs are submitted together + but the common scheduler code doesn't know about it, so this needs to + be done at this point in time); +- calls into the prepare_job() callback again, but for the fragment job, + to check its internal dependencies as well, passing the fragment job's + drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. + +The problem with the last step is that pvr_queue_prepare_job() doesn't +always take the mismatched fragment job and geometry queue into account, +in particular when checking whether there is space for the fragment +command to be submitted, so the code ends up checking for space in the +geometry (i.e. wrong) CCCB. +The rest of the nested prepare_job() callback happens to work fine at +the moment as the other internal dependencies are not relevant for a +paired fragment job. + +Move the initialisation of a paired fragment job's done fence and CCCB +fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct +queue from the fragment job itself. + +This fixes cases where prepare_job() wrongly assumed that there was +enough space for a paired fragment job in its own CCCB, unblocking +run_job(), which then returned early without writing the full sequence +of commands to the CCCB. + +The above lead to kernel warnings such as the following and potentially +job timeouts (depending on waiters on the missing commands): + + [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 + [ 552.421230] Modules linked in: + [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT + [ 552.421625] Tainted: [W]=WARN + [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) + [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] + [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] + [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] + [ 552.421923] sp : ffff800084c47650 + [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 + [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 + [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 + [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 + [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 + [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 + [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 + [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 + [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 + [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f + [ 552.422316] Call trace: + [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) + [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] + [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] + [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] + [ 552.422623] process_one_work+0x520/0x1288 + [ 552.422657] worker_thread+0x3f0/0xb3c + [ 552.422679] kthread+0x334/0x3d8 + [ 552.422706] ret_from_fork+0x10/0x20 + +Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") +Cc: stable@vger.kernel.org +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 4baf9e70cb756d78dd56419f8baee2978a72d0c3) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 32 +++++++++++-------------- + 1 file changed, 14 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 8829c65747b6..7d0d09026b82 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -488,10 +488,11 @@ pvr_queue_get_job_kccb_fence(struct pvr_queue *queue, struct pvr_job *job) + } + + static struct dma_fence * +-pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) ++pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) + { + struct pvr_job *frag_job = job->type == DRM_PVR_JOB_TYPE_GEOMETRY ? + job->paired_job : NULL; ++ struct pvr_queue *frag_queue = frag_job ? frag_job->ctx->queues.fragment : NULL; + struct dma_fence *f; + unsigned long index; + +@@ -510,7 +511,10 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) + return dma_fence_get(f); + } + +- return frag_job->base.sched->ops->prepare_job(&frag_job->base, &queue->entity); ++ /* Initialize the paired fragment job's done_fence, so we can signal it. */ ++ pvr_queue_job_fence_init(frag_job->done_fence, frag_queue); ++ ++ return pvr_queue_get_job_cccb_fence(frag_queue, frag_job); + } + + /** +@@ -529,11 +533,6 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + struct pvr_queue *queue = container_of(s_entity, struct pvr_queue, entity); + struct dma_fence *internal_dep = NULL; + +- /* +- * Initialize the done_fence, so we can signal it. This must be done +- * here because otherwise by the time of run_job() the job will end up +- * in the pending list without a valid fence. +- */ + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { + /* + * This will be called on a paired fragment job after being +@@ -543,18 +542,15 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + */ + if (job->paired_job->has_pm_ref) + return NULL; +- +- /* +- * In this case we need to use the job's own ctx to initialise +- * the done_fence. The other steps are done in the ctx of the +- * paired geometry job. +- */ +- pvr_queue_job_fence_init(job->done_fence, +- job->ctx->queues.fragment); +- } else { +- pvr_queue_job_fence_init(job->done_fence, queue); + } + ++ /* ++ * Initialize the done_fence, so we can signal it. This must be done ++ * here because otherwise by the time of run_job() the job will end up ++ * in the pending list without a valid fence. ++ */ ++ pvr_queue_job_fence_init(job->done_fence, queue); ++ + /* CCCB fence is used to make sure we have enough space in the CCCB to + * submit our commands. + */ +@@ -575,7 +571,7 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + + /* The paired job fence should come last, when everything else is ready. */ + if (!internal_dep) +- internal_dep = pvr_queue_get_paired_frag_job_dep(queue, job); ++ internal_dep = pvr_queue_get_paired_frag_job_dep(job); + + return internal_dep; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch deleted file mode 100644 index 22dad26c59..0000000000 --- a/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch +++ /dev/null @@ -1,183 +0,0 @@ -From bdb364df3673e4e729a0e33788d91c7ace67e22e Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:57 +0100 -Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, - re-enable gcc + rust builds - -Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC -+ Rust builds for RISC-V due to differences in extension handling -compared to LLVM. This commit enables GCC + Rust builds again. - -Add `bindgen-option` conditions for the availability of libclang to the -RISC-V extension Kconfig symbols that depend on the `cc-option` -function. - -For Zicsr/Zifencei special handling, since LLVM/Clang always enables -these two extensions, either don't pass them to `-march`, or pass them -explicitly and Rust bindgen libclang must recognize them. - -Clang does not support `-mno-riscv-attribute` flag, filter it out to -resolve error: unknown argument: '-mno-riscv-attribute'. - -Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen -libclang for RISC-V to resolve error: unsupported argument 'medany' to -option '-mcmodel=' for target 'unknown'. - -Update the documentation, GCC + Rust builds for RISC-V are now -maintained. - -Acked-by: Miguel Ojeda -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - Documentation/rust/arch-support.rst | 2 +- - arch/riscv/Kconfig | 35 ++++++++++++++++++++++++++++- - rust/Makefile | 3 ++- - scripts/Makefile.rust | 1 + - 4 files changed, 38 insertions(+), 3 deletions(-) - -diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst -index 6e6a515d0899..5282e0e174e8 100644 ---- a/Documentation/rust/arch-support.rst -+++ b/Documentation/rust/arch-support.rst -@@ -18,7 +18,7 @@ Architecture Level of support Constraints - ``arm`` Maintained ARMv7 Little Endian only. - ``arm64`` Maintained Little Endian only. - ``loongarch`` Maintained \- --``riscv`` Maintained ``riscv64`` and LLVM/Clang only. -+``riscv`` Maintained ``riscv64`` only. - ``um`` Maintained \- - ``x86`` Maintained ``x86_64`` only. - ============= ================ ============================================== -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 9c43346fabcd..1aa7fec41c09 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -194,7 +194,7 @@ config RISCV - select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_RETHOOK if !XIP_KERNEL - select HAVE_RSEQ -- select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG -+ select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI - select HAVE_SAMPLE_FTRACE_DIRECT - select HAVE_SAMPLE_FTRACE_DIRECT_MULTI - select HAVE_STACKPROTECTOR -@@ -618,6 +618,8 @@ config TOOLCHAIN_HAS_V - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv) - depends on LD_IS_LLD || LD_VERSION >= 23800 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64imv) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32imv) - - config RISCV_ISA_V - bool "Vector extension support" -@@ -682,6 +684,8 @@ config TOOLCHAIN_HAS_ZABHA - depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha) - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha) - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zabha) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zabha) - - config RISCV_ISA_ZABHA - bool "Zabha extension support for atomic byte/halfword operations" -@@ -700,6 +704,8 @@ config TOOLCHAIN_HAS_ZACAS - depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas) - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas) - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zacas) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zacas) - - config RISCV_ISA_ZACAS - bool "Zacas extension support for atomic CAS" -@@ -718,6 +724,8 @@ config TOOLCHAIN_HAS_ZBB - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbb) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbb) - - # This symbol indicates that the toolchain supports all v1.0 vector crypto - # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once. -@@ -733,6 +741,8 @@ config TOOLCHAIN_HAS_ZBA - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zba) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zba) - - config RISCV_ISA_ZBA - bool "Zba extension support for bit manipulation instructions" -@@ -768,6 +778,8 @@ config TOOLCHAIN_HAS_ZBC - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbc) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbc) - - config RISCV_ISA_ZBC - bool "Zbc extension support for carry-less multiplication instructions" -@@ -791,6 +803,8 @@ config TOOLCHAIN_HAS_ZBKB - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbkb) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbkb) - - config RISCV_ISA_ZBKB - bool "Zbkb extension support for bit manipulation instructions" -@@ -878,6 +892,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC - versions of clang and GCC to be passed to GAS, which has the same result - as passing zicsr and zifencei to -march. - -+config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI -+ def_bool y -+ depends on !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zicsr_zifencei) -+ depends on !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zicsr_zifencei) -+ -+config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI -+ def_bool y -+ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 -+ depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI -+ help -+ LLVM/Clang >= 17.0.0 starts recognizing Zicsr/Zifencei in -march, passing -+ them to -march doesn't generate an error anymore, and passing them or not -+ doesn't have any real difference, it still follows ISA before version -+ 20190608 - Zicsr/Zifencei are included in base ISA. -+ -+ The current latest version of LLVM/Clang still does not require explicit -+ Zicsr/Zifencei to enable these two extensions, Clang just accepts them in -+ -march and then silently ignores them. -+ - config FPU - bool "FPU support" - default y -diff --git a/rust/Makefile b/rust/Makefile -index 6d2d542a55e8..046492426017 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -298,7 +298,8 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fno-inline-functions-called-once -fsanitize=bounds-strict \ - -fstrict-flex-arrays=% -fmin-function-alignment=% \ - -fzero-init-padding-bits=% -mno-fdpic \ -- --param=% --param asan-% -fno-isolate-erroneous-paths-dereference -+ --param=% --param asan-% -fno-isolate-erroneous-paths-dereference \ -+ -mno-riscv-attribute - - # Because scripts/Makefile.rust is included regardless of whether Rust is enabled, - # we perform this check here to avoid breaking targets that do not yet support Rust builds. -diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust -index 5c12b4b8c8b6..bfdad4a0a3ce 100644 ---- a/scripts/Makefile.rust -+++ b/scripts/Makefile.rust -@@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 := x86_64-linux-gnu - BINDGEN_TARGET_arm64 := aarch64-linux-gnu - BINDGEN_TARGET_arm := arm-linux-gnueabi - BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf -+BINDGEN_TARGET_riscv := riscv64-linux-gnu - BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) - BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) - --- -2.53.0 - diff --git a/SPECS/linux-lts/0311-UPSTREAM-drm-imagination-Skip-check-on-paired-job-fe.patch b/SPECS/linux-lts/0311-UPSTREAM-drm-imagination-Skip-check-on-paired-job-fe.patch new file mode 100644 index 0000000000..1b153151ce --- /dev/null +++ b/SPECS/linux-lts/0311-UPSTREAM-drm-imagination-Skip-check-on-paired-job-fe.patch @@ -0,0 +1,57 @@ +From f167ab31c2dd0055541129478ef3ea0991a79898 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:38 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip check on paired job + fence during job submission + +While submitting a paired fragment job, there is no need to manually +look for, and skip, the paired job fence, as the existing logic to +resolve dependencies to pvr_queue_fence objects will have failed to +resolve it already and continued with the next one. + +Point this out where the fence is actually accessed and drop the related +check. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 18998b3cb7595850b8b2da55adb3fdc7aef8bc22) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 7d0d09026b82..6fdf74a1b73c 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -646,10 +646,6 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + +- /* This fence will be placed last, as partial render fence. */ +- if (is_paired_job_fence(fence, job)) +- continue; +- + if (dma_fence_is_signaled(&jfence->base)) + continue; + +@@ -664,8 +660,13 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + } + } + +- /* Partial render fence goes last. */ + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { ++ /* ++ * The loop above will only process dependencies backed by a UFO i.e. with ++ * a valid parent fence assigned, but the paired job dependency won't have ++ * one until both jobs have been submitted. Access the parent fence directly ++ * here instead, submitting it last as partial render fence. ++ */ + jfence = to_pvr_queue_job_fence(job->paired_job->done_fence); + if (!WARN_ON(!jfence)) { + pvr_fw_object_get_fw_addr(jfence->queue->timeline_ufo.fw_obj, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch deleted file mode 100644 index cde256c3dd..0000000000 --- a/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 6b99e40ab4ea69deb0bef324e4a5160a020862f2 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sun, 21 Dec 2025 16:20:26 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset - support - -The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus -which shared by all controllers, while another one connect to individual -controller separately. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20251221-07-k1-sdhci-reset-v1-1-6780af7fa6e7@gentoo.org -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 383841369fb2..1081ea687702 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -34,12 +34,24 @@ properties: - - const: core - - const: io - -+ resets: -+ items: -+ - description: axi reset, connect to AXI bus, shared by all controllers -+ - description: sdh reset, connect to individual controller separately -+ -+ reset-names: -+ items: -+ - const: axi -+ - const: sdh -+ - required: - - compatible - - reg - - interrupts - - clocks - - clock-names -+ - resets -+ - reset-names - - unevaluatedProperties: false - -@@ -52,4 +64,6 @@ examples: - interrupt-parent = <&plic>; - clocks = <&clk_apmu 10>, <&clk_apmu 13>; - clock-names = "core", "io"; -+ resets = <&syscon_apmu 2>, <&syscon_apmu 5>; -+ reset-names = "axi", "sdh"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0312-UPSTREAM-drm-imagination-Rename-pvr_queue_fence_is_u.patch b/SPECS/linux-lts/0312-UPSTREAM-drm-imagination-Rename-pvr_queue_fence_is_u.patch new file mode 100644 index 0000000000..2eda8c732e --- /dev/null +++ b/SPECS/linux-lts/0312-UPSTREAM-drm-imagination-Rename-pvr_queue_fence_is_u.patch @@ -0,0 +1,89 @@ +From 351437995884f517e697b735ff5f09abc94f598c Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:39 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Rename + pvr_queue_fence_is_ufo_backed() to reflect usage + +This function is only used by the synchronization code to figure out if +a fence belongs to this driver. +Rename it to pvr_queue_fence_is_native() and update its documentation to +reflect its current purpose. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit c162e655092de8de2e0f7776d72919dd5e3b84f2) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 14 +++++++------- + drivers/gpu/drm/imagination/pvr_queue.h | 2 +- + drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- + 3 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 6fdf74a1b73c..609ba457a619 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -898,16 +898,16 @@ static const struct drm_sched_backend_ops pvr_queue_sched_ops = { + }; + + /** +- * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO object ++ * pvr_queue_fence_is_native() - Check if a dma_fence is native to this driver. + * @f: Fence to test. + * +- * A UFO-backed fence is a fence that can be signaled or waited upon FW-side. +- * pvr_job::done_fence objects are backed by the timeline UFO attached to the queue +- * they are pushed to, but those fences are not directly exposed to the outside +- * world, so we also need to check if the fence we're being passed is a +- * drm_sched_fence that was coming from our driver. ++ * Check if the fence we're being passed is a drm_sched_fence that is coming from this driver. ++ * ++ * It may be a UFO-backed fence i.e. a fence that can be signaled or waited upon FW-side, ++ * such as pvr_job::done_fence objects that are backed by the timeline UFO attached to the queue ++ * they are pushed to. + */ +-bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f) ++bool pvr_queue_fence_is_native(struct dma_fence *f) + { + struct drm_sched_fence *sched_fence = f ? to_drm_sched_fence(f) : NULL; + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.h b/drivers/gpu/drm/imagination/pvr_queue.h +index fc1986d73fc8..4aa72665ce25 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.h ++++ b/drivers/gpu/drm/imagination/pvr_queue.h +@@ -141,7 +141,7 @@ struct pvr_queue { + u64 callstack_addr; + }; + +-bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f); ++bool pvr_queue_fence_is_native(struct dma_fence *f); + + int pvr_queue_job_init(struct pvr_job *job, u64 drm_client_id); + +diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c +index 129f646d14ba..d627c36e262f 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.c ++++ b/drivers/gpu/drm/imagination/pvr_sync.c +@@ -211,7 +211,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) + int err = 0; + + dma_fence_unwrap_for_each(uf, &iter, f) { +- if (pvr_queue_fence_is_ufo_backed(uf)) ++ if (pvr_queue_fence_is_native(uf)) + native_fence_count++; + } + +@@ -227,7 +227,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) + if (err) + continue; + +- if (pvr_queue_fence_is_ufo_backed(uf)) { ++ if (pvr_queue_fence_is_native(uf)) { + struct drm_sched_fence *s_fence = to_drm_sched_fence(uf); + + /* If this is a native dependency, we wait for the scheduled fence, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch b/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch deleted file mode 100644 index 27e125777e..0000000000 --- a/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch +++ /dev/null @@ -1,31 +0,0 @@ -From e4c3413f71ca577a9344235a8e76978b9df6b41d Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Mon, 3 Nov 2025 00:02:00 +0100 -Subject: [RUYI PATCH] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for the - SpacemiT P1 chip - -Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20251102230352.914421-3-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - drivers/mfd/simple-mfd-i2c.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c -index 9f911afafc25..c4166e8aeb9d 100644 ---- a/drivers/mfd/simple-mfd-i2c.c -+++ b/drivers/mfd/simple-mfd-i2c.c -@@ -99,6 +99,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { - }; - - static const struct mfd_cell spacemit_p1_cells[] = { -+ { .name = "spacemit-p1-reboot", }, - { .name = "spacemit-p1-regulator", }, - { .name = "spacemit-p1-rtc", }, - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0313-UPSTREAM-drm-imagination-Rename-fence-returned-by-pv.patch b/SPECS/linux-lts/0313-UPSTREAM-drm-imagination-Rename-fence-returned-by-pv.patch new file mode 100644 index 0000000000..f75151b8b4 --- /dev/null +++ b/SPECS/linux-lts/0313-UPSTREAM-drm-imagination-Rename-fence-returned-by-pv.patch @@ -0,0 +1,90 @@ +From b6f87f4ccf25cada139114a10bc4d9c644d91f5e Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:40 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Rename fence returned by + pvr_queue_job_arm() + +Rename from done_fence to finished_fence, both because the function +returns a drm_sched_fence's finished fence, and to avoid confusion with +the job fence, which is called the same but has a different purpose. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 5dae1a21f1e7128a19c68212422383f700699d01) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_job.c | 8 ++++---- + drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- + drivers/gpu/drm/imagination/pvr_sync.h | 2 +- + 3 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c +index 7564b0f21b42..2da61083ab3e 100644 +--- a/drivers/gpu/drm/imagination/pvr_job.c ++++ b/drivers/gpu/drm/imagination/pvr_job.c +@@ -326,7 +326,7 @@ prepare_job_syncs(struct pvr_file *pvr_file, + struct pvr_job_data *job_data, + struct xarray *signal_array) + { +- struct dma_fence *done_fence; ++ struct dma_fence *finished_fence; + int err = pvr_sync_signal_array_collect_ops(signal_array, + from_pvr_file(pvr_file), + job_data->sync_op_count, +@@ -359,13 +359,13 @@ prepare_job_syncs(struct pvr_file *pvr_file, + return err; + } + +- /* We need to arm the job to get the job done fence. */ +- done_fence = pvr_queue_job_arm(job_data->job); ++ /* We need to arm the job to get the job finished fence. */ ++ finished_fence = pvr_queue_job_arm(job_data->job); + + err = pvr_sync_signal_array_update_fences(signal_array, + job_data->sync_op_count, + job_data->sync_ops, +- done_fence); ++ finished_fence); + return err; + } + +diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c +index d627c36e262f..45ac7a0aff65 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.c ++++ b/drivers/gpu/drm/imagination/pvr_sync.c +@@ -160,7 +160,7 @@ int + pvr_sync_signal_array_update_fences(struct xarray *array, + u32 sync_op_count, + const struct drm_pvr_sync_op *sync_ops, +- struct dma_fence *done_fence) ++ struct dma_fence *finished_fence) + { + for (u32 i = 0; i < sync_op_count; i++) { + struct dma_fence *old_fence; +@@ -175,7 +175,7 @@ pvr_sync_signal_array_update_fences(struct xarray *array, + return -EINVAL; + + old_fence = sig_sync->fence; +- sig_sync->fence = dma_fence_get(done_fence); ++ sig_sync->fence = dma_fence_get(finished_fence); + dma_fence_put(old_fence); + + if (WARN_ON(!sig_sync->fence)) +diff --git a/drivers/gpu/drm/imagination/pvr_sync.h b/drivers/gpu/drm/imagination/pvr_sync.h +index db6ccfda104a..48501ad27794 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.h ++++ b/drivers/gpu/drm/imagination/pvr_sync.h +@@ -70,7 +70,7 @@ int + pvr_sync_signal_array_update_fences(struct xarray *array, + u32 sync_op_count, + const struct drm_pvr_sync_op *sync_ops, +- struct dma_fence *done_fence); ++ struct dma_fence *finished_fence); + + void + pvr_sync_signal_array_push_fences(struct xarray *array); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch deleted file mode 100644 index 2e6395db50..0000000000 --- a/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 976f3a509c35b7b5a88d9f5f44f15301bbfef945 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 16:38:54 +0800 -Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as - dependencies - -REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on -MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' -does not always respect the parent's dependencies, so 'depends on' -is the safer and more correct choice. - -Since MFD_SPACEMIT_P1 already depends on I2C_K1, the dependency -in REGULATOR_SPACEMIT_P1 is now redundant. - -Additionally, the default value depends on MFD_SPACEMIT_P1 rather -than ARCH_SPACEMIT. - -Acked-by: Mark Brown -Acked-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-1-6fe19f460269@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/regulator/Kconfig | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index d84f3d054c59..3701d0fe3e06 100644 ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1455,9 +1455,8 @@ config REGULATOR_SLG51000 - config REGULATOR_SPACEMIT_P1 - tristate "SpacemiT P1 regulators" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on I2C -- select MFD_SPACEMIT_P1 -- default ARCH_SPACEMIT -+ depends on MFD_SPACEMIT_P1 -+ default m if MFD_SPACEMIT_P1 - help - Enable support for regulators implemented by the SpacemiT P1 - power controller. The P1 implements 6 high-efficiency buck --- -2.53.0 - diff --git a/SPECS/linux-lts/0314-UPSTREAM-drm-imagination-Move-repeated-job-fence-che.patch b/SPECS/linux-lts/0314-UPSTREAM-drm-imagination-Move-repeated-job-fence-che.patch new file mode 100644 index 0000000000..a3106f6d7d --- /dev/null +++ b/SPECS/linux-lts/0314-UPSTREAM-drm-imagination-Move-repeated-job-fence-che.patch @@ -0,0 +1,71 @@ +From c00d4f006162665ea56fcd25375f61e34fa161a4 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:41 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Move repeated job fence check + to its own function + +This should make the code slightly clearer. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 402562e60c6c1b15ee359ba7ffed907baa886a99) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 25 ++++++++++++++++++++----- + 1 file changed, 20 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 609ba457a619..2a26b87d146d 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -177,6 +177,24 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { + .release = pvr_queue_fence_release, + }; + ++/** ++ * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO. ++ * @f: The dma_fence to check. ++ * ++ * Return: ++ * * true if the dma_fence is backed by a UFO, or ++ * * false otherwise. ++ */ ++static inline bool ++pvr_queue_fence_is_ufo_backed(struct dma_fence *f) ++{ ++ /* ++ * Currently the only dma_fence backed by a UFO object is the job fence, ++ * e.g. pvr_job::done_fence, wrapped by a pvr_queue_fence object. ++ */ ++ return f && f->ops == &pvr_queue_job_fence_ops; ++} ++ + /** + * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is + * already backed by a UFO. +@@ -194,7 +212,7 @@ to_pvr_queue_job_fence(struct dma_fence *f) + if (sched_fence) + f = sched_fence->parent; + +- if (f && f->ops == &pvr_queue_job_fence_ops) ++ if (pvr_queue_fence_is_ufo_backed(f)) + return container_of(f, struct pvr_queue_fence, base); + + return NULL; +@@ -915,10 +933,7 @@ bool pvr_queue_fence_is_native(struct dma_fence *f) + sched_fence->sched->ops == &pvr_queue_sched_ops) + return true; + +- if (f && f->ops == &pvr_queue_job_fence_ops) +- return true; +- +- return false; ++ return pvr_queue_fence_is_ufo_backed(f); + } + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch deleted file mode 100644 index a28f57c29e..0000000000 --- a/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch +++ /dev/null @@ -1,37 +0,0 @@ -From f7a63859a84191dd8619e6a34c9bf4d6664dcf23 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 16:38:56 +0800 -Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when - MFD_SPACEMIT_P1 is enabled - -The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which -caused it to be built-in automatically whenever the PMIC support was -set to y. - -This is not always desirable, as the RTC function is not required on -all platforms using the SpacemiT P1 PMIC. - -Acked-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-3-6fe19f460269@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/rtc/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig -index b392e6d096ed..4fc77f6b8a72 100644 ---- a/drivers/rtc/Kconfig -+++ b/drivers/rtc/Kconfig -@@ -410,7 +410,7 @@ config RTC_DRV_SPACEMIT_P1 - tristate "SpacemiT P1 RTC" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on MFD_SPACEMIT_P1 -- default MFD_SPACEMIT_P1 -+ default m if MFD_SPACEMIT_P1 - help - Enable support for the RTC function in the SpacemiT P1 PMIC. - This driver can also be built as a module, which will be called --- -2.53.0 - diff --git a/SPECS/linux-lts/0315-UPSTREAM-drm-imagination-Update-check-to-skip-prepar.patch b/SPECS/linux-lts/0315-UPSTREAM-drm-imagination-Update-check-to-skip-prepar.patch new file mode 100644 index 0000000000..1e50d28b34 --- /dev/null +++ b/SPECS/linux-lts/0315-UPSTREAM-drm-imagination-Update-check-to-skip-prepar.patch @@ -0,0 +1,48 @@ +From 03c76855dc91a9dc6f7676155ff8621b7585106d Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:42 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Update check to skip + prepare_job() for fragment jobs + +By the time prepare_job() is called on a paired fragment job, the paired +geometry job might already be finished and its PM reference dropped. + +Check the fragment job's PM reference instead which is a bit more likely +to be still set. This is a very minor optimization. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 5c81eb2970133ad073214eb1e5b0c34a1ae793eb) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 2a26b87d146d..00cc0dd4ca2b 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -553,12 +553,13 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { + /* +- * This will be called on a paired fragment job after being +- * submitted to firmware. We can tell if this is the case and +- * bail early from whether run_job() has been called on the +- * geometry job, which would issue a pm ref. ++ * This will be called on a paired fragment job after being submitted ++ * to the firmware as part of the paired geometry job's submission. ++ * We can tell if this is the case and bail early from whether run_job() ++ * has been called on the geometry job, which would issue a pm ref on ++ * this job as well. + */ +- if (job->paired_job->has_pm_ref) ++ if (job->has_pm_ref) + return NULL; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch deleted file mode 100644 index 6981bb7c1e..0000000000 --- a/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 2a9661946f61c576e2b7534403eae881deb90a82 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:51 -0400 -Subject: [RUYI PATCH] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI support - -Add support for the SPI controller implemented by the SpacemiT K1 SoC. - -Acked-by: Conor Dooley -Acked-by: Troy Mitchell -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - .../bindings/spi/spacemit,k1-spi.yaml | 84 +++++++++++++++++++ - 1 file changed, 84 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml - -diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml -new file mode 100644 -index 000000000000..e82c7f8d0b98 ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml -@@ -0,0 +1,84 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) -+ -+maintainers: -+ - Alex Elder -+ -+description: -+ The SpacemiT K1 SoC implements a SPI controller that has two 32-entry -+ FIFOs, for transmit and receive. Details are currently available in -+ section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone -+ K1 Documentation[1]. The controller transfers words using PIO. DMA -+ transfers are supported as well, if both TX and RX DMA channels are -+ specified, -+ -+ [1] https://developer.spacemit.com/documentation -+ -+allOf: -+ - $ref: /schemas/spi/spi-controller.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k1-spi -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Core clock -+ - description: Bus clock -+ -+ clock-names: -+ items: -+ - const: core -+ - const: bus -+ -+ resets: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ dmas: -+ items: -+ - description: RX DMA channel -+ - description: TX DMA channel -+ -+ dma-names: -+ items: -+ - const: rx -+ - const: tx -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - interrupts -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ -+ #include -+ spi@d401c000 { -+ compatible = "spacemit,k1-spi"; -+ reg = <0xd401c000 0x30>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&syscon_apbc CLK_SSP3>, -+ <&syscon_apbc CLK_SSP3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_SSP3>; -+ interrupts = <55>; -+ dmas = <&pdma 20>, <&pdma 19>; -+ dma-names = "rx", "tx"; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0316-UPSTREAM-drm-imagination-Minor-improvements-to-job-s.patch b/SPECS/linux-lts/0316-UPSTREAM-drm-imagination-Minor-improvements-to-job-s.patch new file mode 100644 index 0000000000..4bb8046782 --- /dev/null +++ b/SPECS/linux-lts/0316-UPSTREAM-drm-imagination-Minor-improvements-to-job-s.patch @@ -0,0 +1,140 @@ +From 0ff6dd4a04aca768dcdcdc8a5eb44ce7095a4c92 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:43 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Minor improvements to job + submission code documentation + +Mixed list of clarifications and typo fixes. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-8-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 62a36c2da774800bef893bc4bf8922fb9c07c1d0) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 38 ++++++++++++------- + .../drm/imagination/pvr_rogue_fwif_shared.h | 10 +---- + 2 files changed, 26 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 00cc0dd4ca2b..21803d3cfbb4 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -200,6 +200,13 @@ pvr_queue_fence_is_ufo_backed(struct dma_fence *f) + * already backed by a UFO. + * @f: The dma_fence to turn into a pvr_queue_fence. + * ++ * This could be called on: ++ * - a job fence directly, in which case it simply returns the containing pvr_queue_fence; ++ * - a drm_sched_fence's scheduled or finished fence, in which case it will first try to follow ++ * the parent pointer to find the job fence (note that the parent pointer is initialized ++ * only after the run_job() callback is called on the drm_sched_fence's owning job); ++ * - any other dma_fence, in which case it will return NULL. ++ * + * Return: + * * A non-NULL pvr_queue_fence object if the dma_fence is backed by a UFO, or + * * NULL otherwise. +@@ -367,11 +374,14 @@ static u32 ufo_cmds_size(u32 elem_count) + + static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) + { +- /* One UFO cmd for the fence signaling, one UFO cmd per native fence native, +- * and a command for the job itself. ++ /* ++ * One UFO command per native fence this job will be waiting on (unless any are ++ * signaled by the time the job is submitted), plus a command for the job itself, ++ * plus one UFO command for the fence signaling. + */ +- return ufo_cmds_size(1) + ufo_cmds_size(ufo_wait_count) + +- pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); ++ return ufo_cmds_size(ufo_wait_count) + ++ pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len) + ++ ufo_cmds_size(1); + } + + static bool +@@ -517,12 +527,16 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) + if (!frag_job) + return NULL; + ++ /* Have the geometry job wait on the paired fragment job's dependencies as well. */ + xa_for_each(&frag_job->base.dependencies, index, f) { + /* Skip already signaled fences. */ + if (dma_fence_is_signaled(f)) + continue; + +- /* Skip our own fence. */ ++ /* ++ * The paired job fence won't be signaled until both jobs have ++ * been submitted, so we can't wait on it to schedule them. ++ */ + if (f == &job->base.s_fence->scheduled) + continue; + +@@ -665,6 +679,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + ++ /* Some dependencies might have been signaled since prepare_job() */ + if (dma_fence_is_signaled(&jfence->base)) + continue; + +@@ -714,7 +729,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + pvr_cccb_write_command_with_header(cccb, job->fw_ccb_cmd_type, job->cmd_len, job->cmd, + job->id, job->id); + +- /* Signal the job fence. */ ++ /* Update command to signal the job fence. */ + pvr_fw_object_get_fw_addr(queue->timeline_ufo.fw_obj, &ufos[0].addr); + ufos[0].value = job->done_fence->seqno; + pvr_cccb_write_command_with_header(cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE, +@@ -744,10 +759,8 @@ static struct dma_fence *pvr_queue_run_job(struct drm_sched_job *sched_job) + } + + /* The only kind of jobs that can be paired are geometry and fragment, and +- * we bail out early if we see a fragment job that's paired with a geomtry +- * job. +- * Paired jobs must also target the same context and point to the same +- * HWRT. ++ * we bail out early if we see a fragment job that's paired with a geometry job. ++ * Paired jobs must also target the same context and point to the same HWRT. + */ + if (WARN_ON(job->paired_job && + (job->type != DRM_PVR_JOB_TYPE_GEOMETRY || +@@ -966,9 +979,8 @@ pvr_queue_signal_done_fences(struct pvr_queue *queue) + } + + /** +- * pvr_queue_check_job_waiting_for_cccb_space() - Check if the job waiting for CCCB space +- * can be unblocked +- * pushed to the CCCB ++ * pvr_queue_check_job_waiting_for_cccb_space() - Check if a job waiting for CCCB space ++ * can be unblocked and pushed to the CCCB. + * @queue: Queue to check + * + * If we have a job waiting for CCCB, and this job now fits in the CCCB, we signal +diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +index 869d904e3649..fe54c1cad7a9 100644 +--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h ++++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +@@ -14,15 +14,7 @@ + + #define ROGUE_NUM_GEOM_CORES_SIZE 2U + +-/* +- * Maximum number of UFOs in a CCB command. +- * The number is based on having 32 sync prims (as originally), plus 32 sync +- * checkpoints. +- * Once the use of sync prims is no longer supported, we will retain +- * the same total (64) as the number of sync checkpoints which may be +- * supporting a fence is not visible to the client driver and has to +- * allow for the number of different timelines involved in fence merges. +- */ ++/* Maximum number of UFOs in a CCB command. */ + #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) + + /* +-- +2.53.0 + diff --git a/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch deleted file mode 100644 index 0ee0c336df..0000000000 --- a/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch +++ /dev/null @@ -1,852 +0,0 @@ -From 36ae899198d9231685aaf77e1dbcd6d51b0c9a76 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:52 -0400 -Subject: [RUYI PATCH] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI - controller driver - -This patch introduces the driver for the SPI controller found in the -SpacemiT K1 SoC. Currently the driver supports master mode only. -The SPI hardware implements RX and TX FIFOs, 32 entries each, and -supports both PIO and DMA mode transfers. - -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - drivers/spi/Kconfig | 9 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-spacemit-k1.c | 789 ++++++++++++++++++++++++++++++++++ - 3 files changed, 799 insertions(+) - create mode 100644 drivers/spi/spi-spacemit-k1.c - -diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index a63fb0a40be5..7cc04b5a1444 100644 ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -1073,6 +1073,15 @@ config SPI_SG2044_NOR - also supporting 3Byte address devices and 4Byte address - devices. - -+config SPI_SPACEMIT_K1 -+ tristate "K1 SPI Controller" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on OF -+ imply MMP_PDMA if ARCH_SPACEMIT -+ default m if ARCH_SPACEMIT -+ help -+ Enable support for the SpacemiT K1 SPI controller. -+ - config SPI_SPRD - tristate "Spreadtrum SPI controller" - depends on ARCH_SPRD || COMPILE_TEST -diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 1f7c06a3091d..f2beb2eb8b48 100644 ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -140,6 +140,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o - obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o - obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o - obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o -+obj-$(CONFIG_SPI_SPACEMIT_K1) += spi-spacemit-k1.o - obj-$(CONFIG_SPI_SPRD) += spi-sprd.o - obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o - obj-$(CONFIG_SPI_STM32) += spi-stm32.o -diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c -new file mode 100644 -index 000000000000..99db429db0b2 ---- /dev/null -+++ b/drivers/spi/spi-spacemit-k1.c -@@ -0,0 +1,789 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// SpacemiT K1 SPI controller driver -+// -+// Copyright (C) 2026, RISCstar Solutions Corporation -+// Copyright (C) 2023, SpacemiT Corporation -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "internals.h" -+ -+/* This is the range of transfer rates supported by the K1 SoC */ -+#define K1_SPI_MIN_SPEED_HZ 6250 -+#define K1_SPI_MAX_SPEED_HZ 51200000 -+ -+/* DMA constraints */ -+#define K1_SPI_DMA_ALIGNMENT 64 -+#define K1_SPI_MAX_DMA_LEN SZ_512K -+ -+/* SSP Top Control Register */ -+#define SSP_TOP_CTRL 0x00 -+#define TOP_SSE BIT(0) /* Enable port */ -+#define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ -+#define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ -+#define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ -+#define TOP_SPO BIT(10) /* Polarity: 0=low */ -+#define TOP_SPH BIT(11) /* Half-cycle phase */ -+#define TOP_LBM BIT(12) /* Loopback mode */ -+#define TOP_TRAIL BIT(13) /* Trailing bytes */ -+#define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ -+ -+/* SSP FIFO Control Register */ -+#define SSP_FIFO_CTRL 0x04 -+#define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ -+#define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ -+#define FIFO_TSRE BIT(10) /* TX service request */ -+#define FIFO_RSRE BIT(11) /* RX service request */ -+ -+/* SSP Interrupt Enable Register */ -+#define SSP_INT_EN 0x08 -+#define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ -+#define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ -+#define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ -+#define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ -+#define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ -+#define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ -+ -+/* TX interrupts, RX interrupts, and error interrupts */ -+#define SSP_INT_EN_TX SSP_INT_EN_TIE -+#define SSP_INT_EN_RX \ -+ (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) -+#define SSP_INT_EN_ERROR \ -+ (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) -+ -+/* SSP Time Out Register */ -+#define SSP_TIMEOUT 0x0c -+#define SSP_TIMEOUT_MASK GENMASK(23, 0) -+ -+/* SSP Data Register */ -+#define SSP_DATAR 0x10 -+ -+/* SSP Status Register */ -+#define SSP_STATUS 0x14 -+#define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ -+#define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ -+#define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ -+#define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ -+#define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ -+#define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ -+#define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ -+#define SSP_STATUS_BCE BIT(21) /* Bit count error */ -+ -+/* Error status mask */ -+#define SSP_STATUS_ERROR \ -+ (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) -+ -+/* The FIFO sizes and thresholds are the same for RX and TX */ -+#define K1_SPI_FIFO_SIZE 32 -+#define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) -+ -+struct k1_spi_driver_data { -+ struct spi_controller *host; -+ void __iomem *base; -+ phys_addr_t base_addr; -+ unsigned long bus_rate; -+ struct clk *clk; -+ unsigned long rate; -+ int irq; -+ -+ /* Current transfer information; not valid if message is null */ -+ u32 bytes; /* Bytes used for bits_per_word */ -+ unsigned int rx_resid; /* RX bytes left in transfer */ -+ unsigned int tx_resid; /* TX bytes left in transfer */ -+ struct spi_transfer *transfer; /* Current transfer */ -+ -+ bool dma_enabled; -+}; -+ -+/* Set our registers to a known initial state */ -+static void -+k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) -+{ -+ u32 val = 0; -+ -+ writel(0, drv_data->base + SSP_TOP_CTRL); -+ -+ if (initial) { -+ /* -+ * The TX and RX FIFO thresholds are the same no matter -+ * what the speed or bits per word, so we can just set -+ * them once. The thresholds are one more than the values -+ * in the register. -+ */ -+ val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); -+ val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); -+ } -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ writel(0, drv_data->base + SSP_INT_EN); -+ writel(0, drv_data->base + SSP_TIMEOUT); -+ -+ /* Clear any pending interrupt conditions */ -+ writel(~0, drv_data->base + SSP_STATUS); -+} -+ -+/* -+ * The client can call the setup function multiple times, and each call -+ * can specify a different SPI mode (and transfer speed). Each transfer -+ * can specify its own speed though, and the core code ensures each -+ * transfer's speed is set to something nonzero and supported by both -+ * the controller and the device. We just set the speed for each transfer. -+ */ -+static int k1_spi_setup(struct spi_device *spi) -+{ -+ struct k1_spi_driver_data *drv_data; -+ u32 val; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ -+ /* -+ * Configure the message format for this device. We only -+ * support Motorola SPI format in master mode. -+ */ -+ val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); -+ -+ /* Translate the mode into the value used to program the hardware. */ -+ if (spi->mode & SPI_CPHA) -+ val |= TOP_SPH; /* 1/2 cycle */ -+ if (spi->mode & SPI_CPOL) -+ val |= TOP_SPO; /* active low */ -+ if (spi->mode & SPI_LOOP) -+ val |= TOP_LBM; /* enable loopback */ -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ return 0; -+} -+ -+static void k1_spi_cleanup(struct spi_device *spi) -+{ -+ struct k1_spi_driver_data *drv_data; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ k1_spi_register_reset(drv_data, false); -+} -+ -+static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 burst_size; -+ -+ if (!drv_data->dma_enabled) -+ return false; -+ -+ if (transfer->len > SZ_2K) -+ return false; -+ -+ /* Don't bother with DMA if we can't do even a single burst */ -+ burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); -+ -+ return transfer->len >= burst_size; -+} -+ -+static void k1_spi_dma_callback(void *param) -+{ -+ struct k1_spi_driver_data *drv_data = param; -+ u32 val; -+ -+ val = readl(drv_data->base + SSP_FIFO_CTRL); -+ val &= ~(FIFO_TSRE | FIFO_RSRE); -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val &= ~TOP_TRAIL; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ /* Check for any error conditions */ -+ val = readl(drv_data->base + SSP_STATUS); -+ if (val & SSP_STATUS_ERROR) -+ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; -+ -+ /* Disable the port */ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val &= ~TOP_SSE; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ drv_data->transfer = NULL; -+ -+ spi_finalize_current_transfer(drv_data->host); -+} -+ -+/* Prepare a descriptor for TX or RX DMA */ -+static struct dma_async_tx_descriptor * -+k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, -+ struct spi_transfer *transfer, bool tx) -+{ -+ phys_addr_t addr = drv_data->base_addr + SSP_DATAR; -+ u32 burst_size = K1_SPI_THRESH * drv_data->bytes; -+ struct dma_slave_config cfg = { }; -+ enum dma_transfer_direction dir; -+ enum dma_slave_buswidth width; -+ struct dma_chan *chan; -+ struct sg_table *sgt; -+ -+ switch (drv_data->bytes) { -+ case 1: -+ width = DMA_SLAVE_BUSWIDTH_1_BYTE; -+ break; -+ case 2: -+ width = DMA_SLAVE_BUSWIDTH_2_BYTES; -+ break; -+ default: /* bytes == 4 */ -+ width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ break; -+ } -+ -+ if (tx) { -+ chan = drv_data->host->dma_tx; -+ sgt = &transfer->tx_sg; -+ dir = DMA_MEM_TO_DEV; -+ -+ cfg.dst_addr = addr; -+ cfg.dst_addr_width = width; -+ cfg.dst_maxburst = burst_size; -+ } else { -+ chan = drv_data->host->dma_rx; -+ sgt = &transfer->rx_sg; -+ dir = DMA_DEV_TO_MEM; -+ -+ cfg.src_addr = addr; -+ cfg.src_addr_width = width; -+ cfg.src_maxburst = burst_size; -+ } -+ cfg.direction = dir; -+ -+ if (dmaengine_slave_config(chan, &cfg)) -+ return NULL; -+ -+ return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); -+ -+} -+ -+static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ struct dma_async_tx_descriptor *desc; -+ u32 val; -+ -+ /* Prepare the TX descriptor and submit it */ -+ desc = k1_spi_dma_prep(drv_data, transfer, true); -+ if (!desc) -+ goto fallback; -+ dmaengine_submit(desc); -+ -+ /* Prepare the RX descriptor and submit it */ -+ desc = k1_spi_dma_prep(drv_data, transfer, false); -+ if (!desc) -+ goto fallback; -+ -+ /* When RX is complete we also know TX has completed */ -+ desc->callback = k1_spi_dma_callback; -+ desc->callback_param = drv_data; -+ -+ dmaengine_submit(desc); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ val = readl(drv_data->base + SSP_FIFO_CTRL); -+ val |= FIFO_TSRE | FIFO_RSRE; -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ /* Start RX first so we're ready the instant we start transmitting */ -+ dma_async_issue_pending(host->dma_rx); -+ dma_async_issue_pending(host->dma_tx); -+ -+ return 1; -+fallback: -+ transfer->error |= SPI_TRANS_FAIL_NO_START; -+ -+ return -EAGAIN; -+} -+ -+/* Flush the RX FIFO of any leftover data before processing a message */ -+static int k1_spi_prepare_message(struct spi_controller *host, -+ struct spi_message *message) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 val = readl(drv_data->base + SSP_STATUS); -+ u32 count; -+ -+ /* If there's nothing in the FIFO, we're done */ -+ if (!(val & SSP_STATUS_RNE)) -+ return 0; -+ -+ /* Read and discard what's there (one more than what the field says) */ -+ count = FIELD_GET(SSP_STATUS_RFL, val) + 1; -+ do -+ (void)readl(drv_data->base + SSP_DATAR); -+ while (--count); -+ -+ return 0; -+} -+ -+/* Set logic level of chip select line (high=true means CS deasserted) */ -+static void k1_spi_set_cs(struct spi_device *spi, bool high) -+{ -+ struct k1_spi_driver_data *drv_data; -+ u32 val; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ if (high) -+ val &= ~TOP_HOLD_FRAME_LOW; -+ else -+ val |= TOP_HOLD_FRAME_LOW; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+} -+ -+/* Set the transfer speed; the SPI core code ensures it is supported */ -+static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, -+ struct spi_transfer *transfer) -+{ -+ struct clk *clk = drv_data->clk; -+ u64 nsec_per_word; -+ u64 bus_ticks; -+ u32 timeout; -+ u32 val; -+ int ret; -+ -+ ret = clk_set_rate(clk, transfer->speed_hz); -+ if (ret) -+ return ret; -+ -+ drv_data->rate = clk_get_rate(clk); -+ -+ /* No need for RX FIFO timeout if we're not receiving anything */ -+ if (!transfer->rx_buf) -+ return 0; -+ -+ /* -+ * Compute the RX FIFO inactivity timeout value that should be used. -+ * The inactivity timer restarts with each word that lands in the -+ * FIFO. If several "word transfer times" pass without any new data -+ * in the RX FIFO, we might as well read what's there. -+ * -+ * The rate at which words land in the FIFO is determined by the -+ * word size and the transfer rate. One bit is transferred per -+ * clock tick, and 8 (or 16 or 32) bits are transferred per word. -+ * -+ * So we can get word transfer time (in nanoseconds) from: -+ * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; -+ * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; -+ * We do the divide last for better accuracy. -+ */ -+ nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; -+ nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); -+ -+ /* -+ * The timeout (which we'll set to three word transfer times) is -+ * expressed as a number of APB clock ticks. -+ * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) -+ */ -+ bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; -+ timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); -+ -+ /* Set the RX timeout period (required for both DMA and PIO) */ -+ val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); -+ writel(val, drv_data->base + SSP_TIMEOUT); -+ -+ return 0; -+} -+ -+static int k1_spi_transfer_one(struct spi_controller *host, -+ struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 ctrl; -+ u32 val; -+ int ret; -+ -+ /* Bits per word can change on a per-transfer basis */ -+ drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); -+ -+ /* Each transfer can also specify a different rate */ -+ ret = k1_spi_set_speed(drv_data, transfer); -+ if (ret) { -+ dev_err(&host->dev, -+ "failed to set transfer speed: %d\n", ret); -+ return ret; -+ } -+ -+ drv_data->rx_resid = transfer->len; -+ drv_data->tx_resid = transfer->len; -+ -+ drv_data->transfer = transfer; -+ -+ /* Clear any existing interrupt conditions */ -+ writel(~0, drv_data->base + SSP_STATUS); -+ -+ /* Set the data (word) size, and enable the port */ -+ ctrl = readl(drv_data->base + SSP_TOP_CTRL); -+ ctrl &= ~TOP_DSS_MASK; -+ ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); -+ ctrl |= TOP_SSE; -+ writel(ctrl, drv_data->base + SSP_TOP_CTRL); -+ -+ if (spi_xfer_is_dma_mapped(host, spi, transfer)) -+ return k1_spi_dma_one(host, spi, transfer); -+ -+ /* An interrupt will initiate the transfer */ -+ val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; -+ writel(val, drv_data->base + SSP_INT_EN); -+ -+ return 1; /* We will call spi_finalize_current_transfer() */ -+} -+ -+static void -+k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ -+ if (drv_data->dma_enabled) { -+ dmaengine_terminate_sync(host->dma_rx); -+ dmaengine_terminate_sync(host->dma_tx); -+ } -+} -+ -+static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) -+{ -+ struct spi_transfer *transfer = drv_data->transfer; -+ u32 bytes = drv_data->bytes; -+ u32 val; -+ -+ if (transfer->tx_buf) { -+ const void *buf; -+ -+ buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); -+ if (bytes == 1) -+ val = *(u8 *)buf; -+ else if (bytes == 2) -+ val = *(u16 *)buf; -+ else /* bytes == 4 */ -+ val = *(u32 *)buf; -+ } else { -+ val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ -+ } -+ /* Fill the next TX FIFO entry */ -+ writel(val, drv_data->base + SSP_DATAR); -+ -+ drv_data->tx_resid -= bytes; -+} -+ -+/* The last-read status value is provided; we know SSP_STATUS_TNF is set */ -+static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) -+{ -+ unsigned int count; -+ -+ /* Get the number of open slots in the FIFO; zero means all */ -+ count = FIELD_GET(SSP_STATUS_TFL, val) ? : K1_SPI_FIFO_SIZE; -+ -+ /* -+ * Limit how much we try to send at a time, to reduce the -+ * chance the other side can overrun our RX FIFO. -+ */ -+ count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); -+ do -+ k1_spi_write_word(drv_data); -+ while (--count); -+ -+ return !drv_data->tx_resid; -+} -+ -+static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) -+{ -+ struct spi_transfer *transfer = drv_data->transfer; -+ u32 bytes = drv_data->bytes; -+ u32 val; -+ -+ /* Consume the next RX FIFO entry */ -+ val = readl(drv_data->base + SSP_DATAR); -+ if (transfer->rx_buf) { -+ void *buf; -+ -+ buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); -+ -+ if (bytes == 1) -+ *(u8 *)buf = val; -+ else if (bytes == 2) -+ *(u16 *)buf = val; -+ else /* bytes == 4 */ -+ *(u32 *)buf = val; -+ } /* Otherwise null reader: discard the data */ -+ -+ drv_data->rx_resid -= bytes; -+} -+ -+/* The last-read status value is provided; we know SSP_STATUS_RNE is set */ -+static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) -+{ -+ do { -+ unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; -+ -+ /* Only read what we need */ -+ count = min(count, drv_data->rx_resid / drv_data->bytes); -+ do -+ k1_spi_read_word(drv_data); -+ while (--count); -+ -+ /* If there's no more to read, we're done */ -+ if (!drv_data->rx_resid) -+ return true; -+ -+ /* Check again in case more became available to read */ -+ val = readl(drv_data->base + SSP_STATUS); -+ if (val & SSP_STATUS_RNE) -+ writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); -+ else -+ return false; -+ } while (true); -+} -+ -+static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) -+{ -+ struct k1_spi_driver_data *drv_data = dev_id; -+ u32 status; -+ u32 top_ctrl; -+ -+ /* Get status and clear pending interrupts */ -+ status = readl(drv_data->base + SSP_STATUS); -+ writel(status, drv_data->base + SSP_STATUS); -+ -+ /* If no actionable status bits are set, this is not our interrupt */ -+ if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) -+ return IRQ_NONE; -+ -+ /* Check for any error conditions first */ -+ if (status & SSP_STATUS_ERROR) { -+ if (drv_data->transfer) -+ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; -+ goto done; -+ } -+ -+ /* -+ * For SPI, bytes are transferred in both directions equally, and -+ * RX always follows TX. Start by writing if there is anything to -+ * write, then read. Once there's no more to read, we're done. -+ */ -+ if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { -+ /* If we finish writing, disable TX interrupts */ -+ if (k1_spi_write(drv_data, status)) -+ writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, -+ drv_data->base + SSP_INT_EN); -+ } -+ -+ /* We're not done unless we've read all that was requested */ -+ if (drv_data->rx_resid) { -+ /* Read more if the FIFO is not empty */ -+ if (status & SSP_STATUS_RNE) -+ if (k1_spi_read(drv_data, status)) -+ goto done; -+ -+ return IRQ_HANDLED; -+ } -+done: -+ /* Disable the port */ -+ top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); -+ top_ctrl &= ~TOP_SSE; -+ writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); -+ -+ /* Disable all interrupts */ -+ writel(0, drv_data->base + SSP_INT_EN); -+ -+ if (drv_data->transfer) { -+ drv_data->transfer = NULL; -+ spi_finalize_current_transfer(drv_data->host); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int -+k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) -+{ -+ struct spi_controller *host = drv_data->host; -+ struct dma_chan *chan; -+ -+ chan = dma_request_chan(dev, "tx"); -+ if (IS_ERR(chan)) -+ return PTR_ERR(chan); -+ host->dma_tx = chan; -+ -+ chan = dma_request_chan(dev, "rx"); -+ if (IS_ERR(chan)) { -+ dma_release_channel(host->dma_tx); -+ host->dma_tx = NULL; -+ return PTR_ERR(chan); -+ } -+ host->dma_rx = chan; -+ -+ drv_data->dma_enabled = true; -+ -+ return 0; -+} -+ -+static void k1_spi_dma_cleanup(struct device *dev, void *res) -+{ -+ struct k1_spi_driver_data **ptr = res; -+ struct k1_spi_driver_data *drv_data = *ptr; -+ struct spi_controller *host = drv_data->host; -+ -+ if (!drv_data->dma_enabled) -+ return; -+ -+ drv_data->dma_enabled = false; -+ -+ dma_release_channel(host->dma_rx); -+ host->dma_rx = NULL; -+ dma_release_channel(host->dma_tx); -+ host->dma_tx = NULL; -+} -+ -+static int -+devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) -+{ -+ struct k1_spi_driver_data **ptr; -+ int ret; -+ -+ if (!IS_ENABLED(CONFIG_MMP_PDMA)) { -+ dev_info(dev, "DMA not available; using PIO\n"); -+ return 0; -+ } -+ -+ ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); -+ if (!ptr) -+ return -ENOMEM; -+ -+ ret = k1_spi_dma_setup(drv_data, dev); -+ if (ret) { -+ devres_free(ptr); -+ return ret; -+ } -+ -+ *ptr = drv_data; -+ devres_add(dev, ptr); -+ -+ return 0; -+} -+ -+static int k1_spi_probe(struct platform_device *pdev) -+{ -+ struct k1_spi_driver_data *drv_data; -+ struct device *dev = &pdev->dev; -+ struct reset_control *reset; -+ struct spi_controller *host; -+ struct resource *iores; -+ struct clk *clk_bus; -+ int ret; -+ -+ host = devm_spi_alloc_host(dev, sizeof(*drv_data)); -+ if (!host) -+ return -ENOMEM; -+ drv_data = spi_controller_get_devdata(host); -+ drv_data->host = host; -+ platform_set_drvdata(pdev, drv_data); -+ -+ ret = devm_k1_spi_dma_setup(drv_data, dev); -+ if (ret == -EPROBE_DEFER) -+ return ret; -+ if (ret) -+ dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); -+ -+ drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, -+ &iores); -+ if (IS_ERR(drv_data->base)) -+ return dev_err_probe(dev, PTR_ERR(drv_data->base), -+ "error mapping memory\n"); -+ drv_data->base_addr = iores->start; -+ -+ clk_bus = devm_clk_get_enabled(dev, "bus"); -+ if (IS_ERR(clk_bus)) -+ return dev_err_probe(dev, PTR_ERR(clk_bus), -+ "error getting/enabling bus clock\n"); -+ drv_data->bus_rate = clk_get_rate(clk_bus); -+ -+ drv_data->clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(drv_data->clk)) -+ return dev_err_probe(dev, PTR_ERR(drv_data->clk), -+ "error getting/enabling core clock\n"); -+ -+ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(reset)) -+ return dev_err_probe(dev, PTR_ERR(reset), -+ "error getting/deasserting reset\n"); -+ -+ k1_spi_register_reset(drv_data, true); -+ -+ drv_data->irq = platform_get_irq(pdev, 0); -+ if (drv_data->irq < 0) -+ return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); -+ -+ ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, -+ IRQF_SHARED, dev_name(dev), drv_data); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "error requesting IRQ\n"); -+ -+ /* Initialize the host structure, then register it */ -+ host->dev.of_node = dev_of_node(dev); -+ host->dev.parent = dev; -+ host->num_chipselect = 1; -+ if (drv_data->dma_enabled) -+ host->dma_alignment = K1_SPI_DMA_ALIGNMENT; -+ host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; -+ host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); -+ host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; -+ host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; -+ host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; -+ host->max_dma_len = K1_SPI_MAX_DMA_LEN; -+ -+ host->setup = k1_spi_setup; -+ host->cleanup = k1_spi_cleanup; -+ host->can_dma = k1_spi_can_dma; -+ host->prepare_message = k1_spi_prepare_message; -+ host->set_cs = k1_spi_set_cs; -+ host->transfer_one = k1_spi_transfer_one; -+ host->handle_err = k1_spi_handle_err; -+ -+ ret = devm_spi_register_controller(dev, host); -+ if (ret) -+ dev_err(dev, "error registering controller\n"); -+ -+ return ret; -+} -+ -+static const struct of_device_id k1_spi_dt_ids[] = { -+ { .compatible = "spacemit,k1-spi", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); -+ -+static struct platform_driver k1_spi_driver = { -+ .probe = k1_spi_probe, -+ .driver = { -+ .name = "k1-spi", -+ .of_match_table = k1_spi_dt_ids, -+ }, -+}; -+module_platform_driver(k1_spi_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0317-UPSTREAM-perf-riscv-Fix-discarded-const-qualifier-in.patch b/SPECS/linux-lts/0317-UPSTREAM-perf-riscv-Fix-discarded-const-qualifier-in.patch new file mode 100644 index 0000000000..3c33130788 --- /dev/null +++ b/SPECS/linux-lts/0317-UPSTREAM-perf-riscv-Fix-discarded-const-qualifier-in.patch @@ -0,0 +1,47 @@ +From cd1e45b5876eb3ddcb7d82dbb6af6141b27e83b1 Mon Sep 17 00:00:00 2001 +From: Li Guan +Date: Thu, 14 May 2026 02:07:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: perf riscv: Fix discarded const qualifier in + _get_field() + +The assignment of strrchr() return values to non-const char * variables +triggers a -Werror=discarded-qualifiers warning when building with GCC +14. + +This happens because in newer glibc versions, strrchr() returns a 'const +char *' if the input string is const. + +Properly declare 'line2' and 'nl' as const char * to match the glibc +function signature and ensure type safety. This avoids the need for +explicit type casting and aligns with the design pattern of not +modifying read-only memory in the perf tool. + +Reviewed-by: Ian Rogers +Signed-off-by: Li Guan +Cc: Adrian Hunter +Cc: Namhyung Kim +Cc: Palmer Dabbelt +Cc: Paul Walmsley +Signed-off-by: Arnaldo Carvalho de Melo +(cherry picked from commit 7378b6656aa46fda56f2743d5a7c1f619c2f6f9b) +Signed-off-by: Han Gao +--- + tools/perf/arch/riscv/util/header.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c +index 4b839203d4a5..891984e909bd 100644 +--- a/tools/perf/arch/riscv/util/header.c ++++ b/tools/perf/arch/riscv/util/header.c +@@ -19,7 +19,7 @@ + + static char *_get_field(const char *line) + { +- char *line2, *nl; ++ const char *line2, *nl; + + line2 = strrchr(line, ' '); + if (!line2) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch deleted file mode 100644 index e4a7aa5c83..0000000000 --- a/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch +++ /dev/null @@ -1,114 +0,0 @@ -From e61e5b8803d80c43b4959f8e4b6e863d1730fe51 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:53 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: define a SPI controller - node - -Define a node for the fourth SoC SPI controller (number 3) on the -SpacemiT K1 SoC. - -Enable it on the Banana Pi BPI-F3 board, which exposes this feature -via its GPIO block: - GPIO PIN 19: MOSI - GPIO PIN 21: MISO - GPIO PIN 23: SCLK - GPIO PIN 24: SS (inverted) - -Define pincontrol configurations for the pins as used on that board. - -(This was tested using a GigaDevice GD25Q64E SPI NOR chip.) - -Reviewed-by: Yixun Lan -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ - 3 files changed, 42 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 5790d927b93d..9429189354d6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -14,6 +14,7 @@ aliases { - ethernet0 = ð0; - ethernet1 = ð1; - serial0 = &uart0; -+ spi3 = &spi3; - i2c2 = &i2c2; - i2c8 = &i2c8; - }; -@@ -335,6 +336,12 @@ &pcie2 { - status = "okay"; - }; - -+&spi3 { -+ pinctrl-0 = <&ssp3_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index b13dcb10f4d6..34d88334e95e 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -570,4 +570,24 @@ pwm14-1-pins { - drive-strength = <32>; - }; - }; -+ -+ ssp3_0_cfg: ssp3-0-cfg { -+ ssp3-0-pins { -+ pinmux = , /* SCLK */ -+ , /* MOSI */ -+ ; /* MISO */ -+ -+ bias-disable; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ -+ ssp3-0-frm-pins { -+ pinmux = ; /* FRM (frame) */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index f0bad6855c97..f8747190d2e1 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -983,6 +983,21 @@ qspi: spi@d420c000 { - status = "disabled"; - }; - -+ spi3: spi@d401c000 { -+ compatible = "spacemit,k1-spi"; -+ reg = <0x0 0xd401c000 0x0 0x30>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&syscon_apbc CLK_SSP3>, -+ <&syscon_apbc CLK_SSP3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_SSP3>; -+ interrupts = <55>; -+ dmas = <&pdma 20>, <&pdma 19>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ - /* sec_uart1: 0xf0612000, not available from Linux */ - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0318-UPSTREAM-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-th.patch b/SPECS/linux-lts/0318-UPSTREAM-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-th.patch new file mode 100644 index 0000000000..87fa2e5dd5 --- /dev/null +++ b/SPECS/linux-lts/0318-UPSTREAM-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-th.patch @@ -0,0 +1,34 @@ +From 0918127a4ec2839945f0afb57e86f0c0efe7f856 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Mon, 3 Nov 2025 00:02:00 +0100 +Subject: [RUYI PATCH] UPSTREAM: mfd: simple-mfd-i2c: Add a reboot cell for the + SpacemiT P1 chip + +Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll # OrangePi-RV2 +Link: https://patch.msgid.link/20251102230352.914421-3-aurelien@aurel32.net +Signed-off-by: Lee Jones +(cherry picked from commit 25c80f08e54ef5298eb68866f755f35b59a26d2b) +Signed-off-by: Han Gao +--- + drivers/mfd/simple-mfd-i2c.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c +index 9f911afafc25..c4166e8aeb9d 100644 +--- a/drivers/mfd/simple-mfd-i2c.c ++++ b/drivers/mfd/simple-mfd-i2c.c +@@ -99,6 +99,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { + }; + + static const struct mfd_cell spacemit_p1_cells[] = { ++ { .name = "spacemit-p1-reboot", }, + { .name = "spacemit-p1-regulator", }, + { .name = "spacemit-p1-rtc", }, + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch deleted file mode 100644 index 7bd9ac4c2d..0000000000 --- a/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 7769d31e702d0f09a02488efb2a7b55c42255417 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:15 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 thermal - sensor - -Document the SpacemiT K1 Thermal Sensor, which supports -monitoring temperatures for five zones: soc, package, gpu, cluster0, -and cluster1. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-1-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - .../bindings/thermal/spacemit,k1-tsensor.yaml | 76 +++++++++++++++++++ - 1 file changed, 76 insertions(+) - create mode 100644 Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml - -diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml -new file mode 100644 -index 000000000000..6dad76a7dd36 ---- /dev/null -+++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml -@@ -0,0 +1,76 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 Thermal Sensor -+ -+description: -+ The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC -+ using multiple internal sensors (e.g., soc, package, gpu, clusters). -+ -+maintainers: -+ - Shuwei Wu -+ -+$ref: thermal-sensor.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k1-tsensor -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Core clock for thermal sensor -+ - description: Bus clock for thermal sensor -+ -+ clock-names: -+ items: -+ - const: core -+ - const: bus -+ -+ interrupts: -+ maxItems: 1 -+ -+ resets: -+ items: -+ - description: Reset for the thermal sensor -+ -+ "#thermal-sensor-cells": -+ const: 1 -+ description: -+ The first cell indicates the sensor ID. -+ 0 = soc -+ 1 = package -+ 2 = gpu -+ 3 = cluster0 -+ 4 = cluster1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - resets -+ - "#thermal-sensor-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ thermal@d4018000 { -+ compatible = "spacemit,k1-tsensor"; -+ reg = <0xd4018000 0x100>; -+ clocks = <&syscon_apbc CLK_TSEN>, -+ <&syscon_apbc CLK_TSEN_BUS>; -+ clock-names = "core", "bus"; -+ interrupts = <61>; -+ resets = <&syscon_apbc RESET_TSEN>; -+ #thermal-sensor-cells = <1>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0319-UPSTREAM-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux-lts/0319-UPSTREAM-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch new file mode 100644 index 0000000000..97cb2590ec --- /dev/null +++ b/SPECS/linux-lts/0319-UPSTREAM-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch @@ -0,0 +1,114 @@ +From c9de083b123ef9d664fb29c8f853770804df02fb Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:51 -0400 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: add SpacemiT K1 SPI support + +Add support for the SPI controller implemented by the SpacemiT K1 SoC. + +Acked-by: Conor Dooley +Acked-by: Troy Mitchell +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit b610d5333c4b93389240b62d1b6299e7e2ee2e65) +Signed-off-by: Han Gao +--- + .../bindings/spi/spacemit,k1-spi.yaml | 84 +++++++++++++++++++ + 1 file changed, 84 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml + +diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml +new file mode 100644 +index 000000000000..e82c7f8d0b98 +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml +@@ -0,0 +1,84 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) ++ ++maintainers: ++ - Alex Elder ++ ++description: ++ The SpacemiT K1 SoC implements a SPI controller that has two 32-entry ++ FIFOs, for transmit and receive. Details are currently available in ++ section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone ++ K1 Documentation[1]. The controller transfers words using PIO. DMA ++ transfers are supported as well, if both TX and RX DMA channels are ++ specified, ++ ++ [1] https://developer.spacemit.com/documentation ++ ++allOf: ++ - $ref: /schemas/spi/spi-controller.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k1-spi ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Core clock ++ - description: Bus clock ++ ++ clock-names: ++ items: ++ - const: core ++ - const: bus ++ ++ resets: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ dmas: ++ items: ++ - description: RX DMA channel ++ - description: TX DMA channel ++ ++ dma-names: ++ items: ++ - const: rx ++ - const: tx ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - interrupts ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ ++ #include ++ spi@d401c000 { ++ compatible = "spacemit,k1-spi"; ++ reg = <0xd401c000 0x30>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_SSP3>, ++ <&syscon_apbc CLK_SSP3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_SSP3>; ++ interrupts = <55>; ++ dmas = <&pdma 20>, <&pdma 19>; ++ dma-names = "rx", "tx"; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch b/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch deleted file mode 100644 index 0a1aad818b..0000000000 --- a/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch +++ /dev/null @@ -1,380 +0,0 @@ -From e87ee0243fcb7c4480eb9766f9800d4905e11b24 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:16 +0800 -Subject: [RUYI PATCH] FROMLIST: thermal: spacemit: k1: Add thermal sensor - support - -The thermal sensor on K1 supports monitoring five temperature zones. -The driver registers these sensors with the thermal framework -and supports standard operations: -- Reading temperature (millidegree Celsius) -- Setting high/low thresholds for interrupts - -Reviewed-by: Anand Moon -Tested-by: Anand Moon -Reviewed-by: Troy Mitchell -Reviewed-by: Yao Zi -Tested-by: Vincent Legoll # OrangePi-RV2 -Tested-by: Gong Shuai -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-2-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - drivers/thermal/Kconfig | 2 + - drivers/thermal/Makefile | 1 + - drivers/thermal/spacemit/Kconfig | 19 ++ - drivers/thermal/spacemit/Makefile | 3 + - drivers/thermal/spacemit/k1_tsensor.c | 280 ++++++++++++++++++++++++++ - 5 files changed, 305 insertions(+) - create mode 100644 drivers/thermal/spacemit/Kconfig - create mode 100644 drivers/thermal/spacemit/Makefile - create mode 100644 drivers/thermal/spacemit/k1_tsensor.c - -diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index a09c188b9ad1..a96e2d045d97 100644 ---- a/drivers/thermal/Kconfig -+++ b/drivers/thermal/Kconfig -@@ -462,6 +462,8 @@ endmenu - - source "drivers/thermal/renesas/Kconfig" - -+source "drivers/thermal/spacemit/Kconfig" -+ - source "drivers/thermal/tegra/Kconfig" - - config GENERIC_ADC_THERMAL -diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index d7718978db24..64cbed51d4fb 100644 ---- a/drivers/thermal/Makefile -+++ b/drivers/thermal/Makefile -@@ -64,6 +64,7 @@ obj-y += mediatek/ - obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o - obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o - obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o -+obj-y += spacemit/ - obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o - obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o - obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o -diff --git a/drivers/thermal/spacemit/Kconfig b/drivers/thermal/spacemit/Kconfig -new file mode 100644 -index 000000000000..de7b5ece5af2 ---- /dev/null -+++ b/drivers/thermal/spacemit/Kconfig -@@ -0,0 +1,19 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+menu "SpacemiT thermal drivers" -+depends on ARCH_SPACEMIT || COMPILE_TEST -+ -+config SPACEMIT_K1_TSENSOR -+ tristate "SpacemiT K1 thermal sensor driver" -+ depends on THERMAL_OF -+ help -+ This driver provides support for the thermal sensor -+ integrated in the SpacemiT K1 SoC. -+ -+ The thermal sensor monitors temperatures for five thermal zones: -+ soc, package, gpu, cluster0, and cluster1. It supports reporting -+ temperature values and handling high/low threshold interrupts. -+ -+ Say Y here if you want to enable thermal monitoring on SpacemiT K1. -+ If compiled as a module, it will be called k1_tsensor. -+ -+endmenu -diff --git a/drivers/thermal/spacemit/Makefile b/drivers/thermal/spacemit/Makefile -new file mode 100644 -index 000000000000..82b30741e4ec ---- /dev/null -+++ b/drivers/thermal/spacemit/Makefile -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_SPACEMIT_K1_TSENSOR) += k1_tsensor.o -diff --git a/drivers/thermal/spacemit/k1_tsensor.c b/drivers/thermal/spacemit/k1_tsensor.c -new file mode 100644 -index 000000000000..79222d233129 ---- /dev/null -+++ b/drivers/thermal/spacemit/k1_tsensor.c -@@ -0,0 +1,280 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Thermal sensor driver for SpacemiT K1 SoC -+ * -+ * Copyright (C) 2026 Shuwei Wu -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../thermal_hwmon.h" -+ -+#define K1_TSENSOR_PCTRL_REG 0x00 -+#define K1_TSENSOR_PCTRL_ENABLE BIT(0) -+#define K1_TSENSOR_PCTRL_TEMP_MODE BIT(3) -+#define K1_TSENSOR_PCTRL_RAW_SEL BIT(7) -+ -+#define K1_TSENSOR_PCTRL_CTUNE GENMASK(11, 8) -+#define K1_TSENSOR_PCTRL_SW_CTRL GENMASK(21, 18) -+#define K1_TSENSOR_PCTRL_HW_AUTO_MODE BIT(23) -+ -+#define K1_TSENSOR_EN_REG 0x08 -+#define K1_TSENSOR_EN_ALL GENMASK(MAX_SENSOR_NUMBER - 1, 0) -+ -+#define K1_TSENSOR_TIME_REG 0x0C -+#define K1_TSENSOR_TIME_WAIT_REF_CNT GENMASK(3, 0) -+#define K1_TSENSOR_TIME_ADC_CNT_RST GENMASK(7, 4) -+#define K1_TSENSOR_TIME_FILTER_PERIOD GENMASK(21, 20) -+#define K1_TSENSOR_TIME_MASK GENMASK(23, 0) -+ -+#define K1_TSENSOR_INT_CLR_REG 0x10 -+#define K1_TSENSOR_INT_EN_REG 0x14 -+#define K1_TSENSOR_INT_STA_REG 0x18 -+ -+#define K1_TSENSOR_INT_EN_MASK BIT(0) -+#define K1_TSENSOR_INT_MASK(x) (GENMASK(2, 1) << ((x) * 2)) -+ -+#define K1_TSENSOR_DATA_BASE_REG 0x20 -+#define K1_TSENSOR_DATA_REG(x) (K1_TSENSOR_DATA_BASE_REG + ((x) / 2) * 4) -+#define K1_TSENSOR_DATA_LOW_MASK GENMASK(15, 0) -+#define K1_TSENSOR_DATA_HIGH_MASK GENMASK(31, 16) -+ -+#define K1_TSENSOR_THRSH_BASE_REG 0x40 -+#define K1_TSENSOR_THRSH_REG(x) (K1_TSENSOR_THRSH_BASE_REG + ((x) * 4)) -+#define K1_TSENSOR_THRSH_LOW_MASK GENMASK(15, 0) -+#define K1_TSENSOR_THRSH_HIGH_MASK GENMASK(31, 16) -+ -+#define MAX_SENSOR_NUMBER 5 -+ -+/* Hardware offset value required for temperature calculation */ -+#define TEMPERATURE_OFFSET 278 -+ -+struct k1_tsensor_channel { -+ struct k1_tsensor *ts; -+ struct thermal_zone_device *tzd; -+ int id; -+}; -+ -+struct k1_tsensor { -+ void __iomem *base; -+ struct k1_tsensor_channel ch[MAX_SENSOR_NUMBER]; -+}; -+ -+static void k1_tsensor_init(struct k1_tsensor *ts) -+{ -+ u32 val; -+ -+ /* Disable all the interrupts */ -+ writel(0xffffffff, ts->base + K1_TSENSOR_INT_EN_REG); -+ -+ /* Configure ADC sampling time and filter period */ -+ val = readl(ts->base + K1_TSENSOR_TIME_REG); -+ val &= ~K1_TSENSOR_TIME_MASK; -+ val |= K1_TSENSOR_TIME_FILTER_PERIOD | -+ K1_TSENSOR_TIME_ADC_CNT_RST | -+ K1_TSENSOR_TIME_WAIT_REF_CNT; -+ writel(val, ts->base + K1_TSENSOR_TIME_REG); -+ -+ /* -+ * Enable all sensors' auto mode, enable dither control, -+ * consecutive mode, and power up sensor. -+ */ -+ val = readl(ts->base + K1_TSENSOR_PCTRL_REG); -+ val &= ~K1_TSENSOR_PCTRL_SW_CTRL; -+ val &= ~K1_TSENSOR_PCTRL_CTUNE; -+ val |= K1_TSENSOR_PCTRL_RAW_SEL | -+ K1_TSENSOR_PCTRL_TEMP_MODE | -+ K1_TSENSOR_PCTRL_HW_AUTO_MODE | -+ K1_TSENSOR_PCTRL_ENABLE; -+ writel(val, ts->base + K1_TSENSOR_PCTRL_REG); -+ -+ /* Enable each sensor */ -+ val = readl(ts->base + K1_TSENSOR_EN_REG); -+ val |= K1_TSENSOR_EN_ALL; -+ writel(val, ts->base + K1_TSENSOR_EN_REG); -+} -+ -+static void k1_tsensor_enable_irq(struct k1_tsensor_channel *ch) -+{ -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ val = readl(ts->base + K1_TSENSOR_INT_CLR_REG); -+ val |= K1_TSENSOR_INT_MASK(ch->id); -+ writel(val, ts->base + K1_TSENSOR_INT_CLR_REG); -+ -+ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); -+ val &= ~K1_TSENSOR_INT_MASK(ch->id); -+ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); -+ -+ /* Enable thermal interrupt */ -+ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); -+ val |= K1_TSENSOR_INT_EN_MASK; -+ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); -+} -+ -+/* -+ * The conversion formula used is: -+ * T(m°C) = (((raw_value & mask) >> shift) - TEMPERATURE_OFFSET) * 1000 -+ */ -+static int k1_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) -+{ -+ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ val = readl(ts->base + K1_TSENSOR_DATA_REG(ch->id)); -+ if (ch->id % 2) -+ *temp = FIELD_GET(K1_TSENSOR_DATA_HIGH_MASK, val); -+ else -+ *temp = FIELD_GET(K1_TSENSOR_DATA_LOW_MASK, val); -+ -+ *temp -= TEMPERATURE_OFFSET; -+ *temp *= 1000; -+ -+ return 0; -+} -+ -+/* -+ * For each sensor, the hardware threshold register is 32 bits: -+ * - Lower 16 bits [15:0] configure the low threshold temperature. -+ * - Upper 16 bits [31:16] configure the high threshold temperature. -+ */ -+static int k1_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) -+{ -+ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ if (low >= high) -+ return -EINVAL; -+ -+ low = clamp_val(low / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, -+ FIELD_MAX(K1_TSENSOR_THRSH_LOW_MASK)); -+ high = clamp_val(high / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, -+ FIELD_MAX(K1_TSENSOR_THRSH_HIGH_MASK)); -+ -+ val = readl(ts->base + K1_TSENSOR_THRSH_REG(ch->id)); -+ -+ val &= ~(K1_TSENSOR_THRSH_LOW_MASK | K1_TSENSOR_THRSH_HIGH_MASK); -+ val |= FIELD_PREP(K1_TSENSOR_THRSH_LOW_MASK, low); -+ val |= FIELD_PREP(K1_TSENSOR_THRSH_HIGH_MASK, high); -+ -+ writel(val, ts->base + K1_TSENSOR_THRSH_REG(ch->id)); -+ -+ return 0; -+} -+ -+static const struct thermal_zone_device_ops k1_tsensor_ops = { -+ .get_temp = k1_tsensor_get_temp, -+ .set_trips = k1_tsensor_set_trips, -+}; -+ -+static irqreturn_t k1_tsensor_irq_thread(int irq, void *data) -+{ -+ struct k1_tsensor *ts = (struct k1_tsensor *)data; -+ int mask, status, i; -+ -+ status = readl(ts->base + K1_TSENSOR_INT_STA_REG); -+ -+ for (i = 0; i < MAX_SENSOR_NUMBER; i++) { -+ if (status & K1_TSENSOR_INT_MASK(i)) { -+ mask = readl(ts->base + K1_TSENSOR_INT_CLR_REG); -+ mask |= K1_TSENSOR_INT_MASK(i); -+ writel(mask, ts->base + K1_TSENSOR_INT_CLR_REG); -+ thermal_zone_device_update(ts->ch[i].tzd, THERMAL_EVENT_UNSPECIFIED); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int k1_tsensor_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct k1_tsensor *ts; -+ struct reset_control *reset; -+ struct clk *clk; -+ int i, irq, ret; -+ -+ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); -+ if (!ts) -+ return -ENOMEM; -+ -+ ts->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ts->base)) -+ return dev_err_probe(dev, PTR_ERR(ts->base), "Failed to get reg\n"); -+ -+ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(reset)) -+ return dev_err_probe(dev, PTR_ERR(reset), "Failed to get/deassert reset control\n"); -+ -+ clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(clk)) -+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get core clock\n"); -+ -+ clk = devm_clk_get_enabled(dev, "bus"); -+ if (IS_ERR(clk)) -+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get bus clock\n"); -+ -+ k1_tsensor_init(ts); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = devm_request_threaded_irq(dev, irq, NULL, -+ k1_tsensor_irq_thread, -+ IRQF_ONESHOT, "k1_tsensor", ts); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 0; i < MAX_SENSOR_NUMBER; ++i) { -+ ts->ch[i].id = i; -+ ts->ch[i].ts = ts; -+ ts->ch[i].tzd = devm_thermal_of_zone_register(dev, i, ts->ch + i, &k1_tsensor_ops); -+ if (IS_ERR(ts->ch[i].tzd)) -+ return PTR_ERR(ts->ch[i].tzd); -+ -+ /* Attach sysfs hwmon attributes for userspace monitoring */ -+ ret = devm_thermal_add_hwmon_sysfs(dev, ts->ch[i].tzd); -+ if (ret) -+ dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); -+ -+ k1_tsensor_enable_irq(ts->ch + i); -+ } -+ -+ platform_set_drvdata(pdev, ts); -+ -+ return 0; -+} -+ -+static const struct of_device_id k1_tsensor_dt_ids[] = { -+ { .compatible = "spacemit,k1-tsensor" }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, k1_tsensor_dt_ids); -+ -+static struct platform_driver k1_tsensor_driver = { -+ .driver = { -+ .name = "k1_tsensor", -+ .of_match_table = k1_tsensor_dt_ids, -+ }, -+ .probe = k1_tsensor_probe, -+}; -+module_platform_driver(k1_tsensor_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 Thermal Sensor Driver"); -+MODULE_AUTHOR("Shuwei Wu "); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0320-UPSTREAM-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux-lts/0320-UPSTREAM-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch new file mode 100644 index 0000000000..a7a050e1c1 --- /dev/null +++ b/SPECS/linux-lts/0320-UPSTREAM-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch @@ -0,0 +1,854 @@ +From 55568d74ff1ea521fbf5f33880177c367a364577 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:52 -0400 +Subject: [RUYI PATCH] UPSTREAM: spi: spacemit: introduce SpacemiT K1 SPI + controller driver + +This patch introduces the driver for the SPI controller found in the +SpacemiT K1 SoC. Currently the driver supports master mode only. +The SPI hardware implements RX and TX FIFOs, 32 entries each, and +supports both PIO and DMA mode transfers. + +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://patch.msgid.link/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit efcd8b9d111177d48c841d09beca43b15d5b9e5f) +Signed-off-by: Han Gao +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-spacemit-k1.c | 789 ++++++++++++++++++++++++++++++++++ + 3 files changed, 799 insertions(+) + create mode 100644 drivers/spi/spi-spacemit-k1.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index a63fb0a40be5..7cc04b5a1444 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -1073,6 +1073,15 @@ config SPI_SG2044_NOR + also supporting 3Byte address devices and 4Byte address + devices. + ++config SPI_SPACEMIT_K1 ++ tristate "K1 SPI Controller" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on OF ++ imply MMP_PDMA if ARCH_SPACEMIT ++ default m if ARCH_SPACEMIT ++ help ++ Enable support for the SpacemiT K1 SPI controller. ++ + config SPI_SPRD + tristate "Spreadtrum SPI controller" + depends on ARCH_SPRD || COMPILE_TEST +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 1f7c06a3091d..f2beb2eb8b48 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -140,6 +140,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o + obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o + obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o + obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o ++obj-$(CONFIG_SPI_SPACEMIT_K1) += spi-spacemit-k1.o + obj-$(CONFIG_SPI_SPRD) += spi-sprd.o + obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o + obj-$(CONFIG_SPI_STM32) += spi-stm32.o +diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c +new file mode 100644 +index 000000000000..99db429db0b2 +--- /dev/null ++++ b/drivers/spi/spi-spacemit-k1.c +@@ -0,0 +1,789 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// SpacemiT K1 SPI controller driver ++// ++// Copyright (C) 2026, RISCstar Solutions Corporation ++// Copyright (C) 2023, SpacemiT Corporation ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "internals.h" ++ ++/* This is the range of transfer rates supported by the K1 SoC */ ++#define K1_SPI_MIN_SPEED_HZ 6250 ++#define K1_SPI_MAX_SPEED_HZ 51200000 ++ ++/* DMA constraints */ ++#define K1_SPI_DMA_ALIGNMENT 64 ++#define K1_SPI_MAX_DMA_LEN SZ_512K ++ ++/* SSP Top Control Register */ ++#define SSP_TOP_CTRL 0x00 ++#define TOP_SSE BIT(0) /* Enable port */ ++#define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ ++#define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ ++#define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ ++#define TOP_SPO BIT(10) /* Polarity: 0=low */ ++#define TOP_SPH BIT(11) /* Half-cycle phase */ ++#define TOP_LBM BIT(12) /* Loopback mode */ ++#define TOP_TRAIL BIT(13) /* Trailing bytes */ ++#define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ ++ ++/* SSP FIFO Control Register */ ++#define SSP_FIFO_CTRL 0x04 ++#define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ ++#define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ ++#define FIFO_TSRE BIT(10) /* TX service request */ ++#define FIFO_RSRE BIT(11) /* RX service request */ ++ ++/* SSP Interrupt Enable Register */ ++#define SSP_INT_EN 0x08 ++#define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ ++#define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ ++#define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ ++#define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ ++#define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ ++#define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ ++ ++/* TX interrupts, RX interrupts, and error interrupts */ ++#define SSP_INT_EN_TX SSP_INT_EN_TIE ++#define SSP_INT_EN_RX \ ++ (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) ++#define SSP_INT_EN_ERROR \ ++ (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) ++ ++/* SSP Time Out Register */ ++#define SSP_TIMEOUT 0x0c ++#define SSP_TIMEOUT_MASK GENMASK(23, 0) ++ ++/* SSP Data Register */ ++#define SSP_DATAR 0x10 ++ ++/* SSP Status Register */ ++#define SSP_STATUS 0x14 ++#define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ ++#define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ ++#define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ ++#define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ ++#define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ ++#define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ ++#define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ ++#define SSP_STATUS_BCE BIT(21) /* Bit count error */ ++ ++/* Error status mask */ ++#define SSP_STATUS_ERROR \ ++ (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) ++ ++/* The FIFO sizes and thresholds are the same for RX and TX */ ++#define K1_SPI_FIFO_SIZE 32 ++#define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) ++ ++struct k1_spi_driver_data { ++ struct spi_controller *host; ++ void __iomem *base; ++ phys_addr_t base_addr; ++ unsigned long bus_rate; ++ struct clk *clk; ++ unsigned long rate; ++ int irq; ++ ++ /* Current transfer information; not valid if message is null */ ++ u32 bytes; /* Bytes used for bits_per_word */ ++ unsigned int rx_resid; /* RX bytes left in transfer */ ++ unsigned int tx_resid; /* TX bytes left in transfer */ ++ struct spi_transfer *transfer; /* Current transfer */ ++ ++ bool dma_enabled; ++}; ++ ++/* Set our registers to a known initial state */ ++static void ++k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) ++{ ++ u32 val = 0; ++ ++ writel(0, drv_data->base + SSP_TOP_CTRL); ++ ++ if (initial) { ++ /* ++ * The TX and RX FIFO thresholds are the same no matter ++ * what the speed or bits per word, so we can just set ++ * them once. The thresholds are one more than the values ++ * in the register. ++ */ ++ val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); ++ val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); ++ } ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ writel(0, drv_data->base + SSP_INT_EN); ++ writel(0, drv_data->base + SSP_TIMEOUT); ++ ++ /* Clear any pending interrupt conditions */ ++ writel(~0, drv_data->base + SSP_STATUS); ++} ++ ++/* ++ * The client can call the setup function multiple times, and each call ++ * can specify a different SPI mode (and transfer speed). Each transfer ++ * can specify its own speed though, and the core code ensures each ++ * transfer's speed is set to something nonzero and supported by both ++ * the controller and the device. We just set the speed for each transfer. ++ */ ++static int k1_spi_setup(struct spi_device *spi) ++{ ++ struct k1_spi_driver_data *drv_data; ++ u32 val; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ ++ /* ++ * Configure the message format for this device. We only ++ * support Motorola SPI format in master mode. ++ */ ++ val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); ++ ++ /* Translate the mode into the value used to program the hardware. */ ++ if (spi->mode & SPI_CPHA) ++ val |= TOP_SPH; /* 1/2 cycle */ ++ if (spi->mode & SPI_CPOL) ++ val |= TOP_SPO; /* active low */ ++ if (spi->mode & SPI_LOOP) ++ val |= TOP_LBM; /* enable loopback */ ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ return 0; ++} ++ ++static void k1_spi_cleanup(struct spi_device *spi) ++{ ++ struct k1_spi_driver_data *drv_data; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ k1_spi_register_reset(drv_data, false); ++} ++ ++static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 burst_size; ++ ++ if (!drv_data->dma_enabled) ++ return false; ++ ++ if (transfer->len > SZ_2K) ++ return false; ++ ++ /* Don't bother with DMA if we can't do even a single burst */ ++ burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); ++ ++ return transfer->len >= burst_size; ++} ++ ++static void k1_spi_dma_callback(void *param) ++{ ++ struct k1_spi_driver_data *drv_data = param; ++ u32 val; ++ ++ val = readl(drv_data->base + SSP_FIFO_CTRL); ++ val &= ~(FIFO_TSRE | FIFO_RSRE); ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val &= ~TOP_TRAIL; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ /* Check for any error conditions */ ++ val = readl(drv_data->base + SSP_STATUS); ++ if (val & SSP_STATUS_ERROR) ++ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; ++ ++ /* Disable the port */ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val &= ~TOP_SSE; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ drv_data->transfer = NULL; ++ ++ spi_finalize_current_transfer(drv_data->host); ++} ++ ++/* Prepare a descriptor for TX or RX DMA */ ++static struct dma_async_tx_descriptor * ++k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, ++ struct spi_transfer *transfer, bool tx) ++{ ++ phys_addr_t addr = drv_data->base_addr + SSP_DATAR; ++ u32 burst_size = K1_SPI_THRESH * drv_data->bytes; ++ struct dma_slave_config cfg = { }; ++ enum dma_transfer_direction dir; ++ enum dma_slave_buswidth width; ++ struct dma_chan *chan; ++ struct sg_table *sgt; ++ ++ switch (drv_data->bytes) { ++ case 1: ++ width = DMA_SLAVE_BUSWIDTH_1_BYTE; ++ break; ++ case 2: ++ width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ default: /* bytes == 4 */ ++ width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ } ++ ++ if (tx) { ++ chan = drv_data->host->dma_tx; ++ sgt = &transfer->tx_sg; ++ dir = DMA_MEM_TO_DEV; ++ ++ cfg.dst_addr = addr; ++ cfg.dst_addr_width = width; ++ cfg.dst_maxburst = burst_size; ++ } else { ++ chan = drv_data->host->dma_rx; ++ sgt = &transfer->rx_sg; ++ dir = DMA_DEV_TO_MEM; ++ ++ cfg.src_addr = addr; ++ cfg.src_addr_width = width; ++ cfg.src_maxburst = burst_size; ++ } ++ cfg.direction = dir; ++ ++ if (dmaengine_slave_config(chan, &cfg)) ++ return NULL; ++ ++ return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ ++} ++ ++static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ struct dma_async_tx_descriptor *desc; ++ u32 val; ++ ++ /* Prepare the TX descriptor and submit it */ ++ desc = k1_spi_dma_prep(drv_data, transfer, true); ++ if (!desc) ++ goto fallback; ++ dmaengine_submit(desc); ++ ++ /* Prepare the RX descriptor and submit it */ ++ desc = k1_spi_dma_prep(drv_data, transfer, false); ++ if (!desc) ++ goto fallback; ++ ++ /* When RX is complete we also know TX has completed */ ++ desc->callback = k1_spi_dma_callback; ++ desc->callback_param = drv_data; ++ ++ dmaengine_submit(desc); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ val = readl(drv_data->base + SSP_FIFO_CTRL); ++ val |= FIFO_TSRE | FIFO_RSRE; ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ /* Start RX first so we're ready the instant we start transmitting */ ++ dma_async_issue_pending(host->dma_rx); ++ dma_async_issue_pending(host->dma_tx); ++ ++ return 1; ++fallback: ++ transfer->error |= SPI_TRANS_FAIL_NO_START; ++ ++ return -EAGAIN; ++} ++ ++/* Flush the RX FIFO of any leftover data before processing a message */ ++static int k1_spi_prepare_message(struct spi_controller *host, ++ struct spi_message *message) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 val = readl(drv_data->base + SSP_STATUS); ++ u32 count; ++ ++ /* If there's nothing in the FIFO, we're done */ ++ if (!(val & SSP_STATUS_RNE)) ++ return 0; ++ ++ /* Read and discard what's there (one more than what the field says) */ ++ count = FIELD_GET(SSP_STATUS_RFL, val) + 1; ++ do ++ (void)readl(drv_data->base + SSP_DATAR); ++ while (--count); ++ ++ return 0; ++} ++ ++/* Set logic level of chip select line (high=true means CS deasserted) */ ++static void k1_spi_set_cs(struct spi_device *spi, bool high) ++{ ++ struct k1_spi_driver_data *drv_data; ++ u32 val; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ if (high) ++ val &= ~TOP_HOLD_FRAME_LOW; ++ else ++ val |= TOP_HOLD_FRAME_LOW; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++} ++ ++/* Set the transfer speed; the SPI core code ensures it is supported */ ++static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, ++ struct spi_transfer *transfer) ++{ ++ struct clk *clk = drv_data->clk; ++ u64 nsec_per_word; ++ u64 bus_ticks; ++ u32 timeout; ++ u32 val; ++ int ret; ++ ++ ret = clk_set_rate(clk, transfer->speed_hz); ++ if (ret) ++ return ret; ++ ++ drv_data->rate = clk_get_rate(clk); ++ ++ /* No need for RX FIFO timeout if we're not receiving anything */ ++ if (!transfer->rx_buf) ++ return 0; ++ ++ /* ++ * Compute the RX FIFO inactivity timeout value that should be used. ++ * The inactivity timer restarts with each word that lands in the ++ * FIFO. If several "word transfer times" pass without any new data ++ * in the RX FIFO, we might as well read what's there. ++ * ++ * The rate at which words land in the FIFO is determined by the ++ * word size and the transfer rate. One bit is transferred per ++ * clock tick, and 8 (or 16 or 32) bits are transferred per word. ++ * ++ * So we can get word transfer time (in nanoseconds) from: ++ * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; ++ * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; ++ * We do the divide last for better accuracy. ++ */ ++ nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; ++ nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); ++ ++ /* ++ * The timeout (which we'll set to three word transfer times) is ++ * expressed as a number of APB clock ticks. ++ * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) ++ */ ++ bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; ++ timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); ++ ++ /* Set the RX timeout period (required for both DMA and PIO) */ ++ val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); ++ writel(val, drv_data->base + SSP_TIMEOUT); ++ ++ return 0; ++} ++ ++static int k1_spi_transfer_one(struct spi_controller *host, ++ struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 ctrl; ++ u32 val; ++ int ret; ++ ++ /* Bits per word can change on a per-transfer basis */ ++ drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); ++ ++ /* Each transfer can also specify a different rate */ ++ ret = k1_spi_set_speed(drv_data, transfer); ++ if (ret) { ++ dev_err(&host->dev, ++ "failed to set transfer speed: %d\n", ret); ++ return ret; ++ } ++ ++ drv_data->rx_resid = transfer->len; ++ drv_data->tx_resid = transfer->len; ++ ++ drv_data->transfer = transfer; ++ ++ /* Clear any existing interrupt conditions */ ++ writel(~0, drv_data->base + SSP_STATUS); ++ ++ /* Set the data (word) size, and enable the port */ ++ ctrl = readl(drv_data->base + SSP_TOP_CTRL); ++ ctrl &= ~TOP_DSS_MASK; ++ ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); ++ ctrl |= TOP_SSE; ++ writel(ctrl, drv_data->base + SSP_TOP_CTRL); ++ ++ if (spi_xfer_is_dma_mapped(host, spi, transfer)) ++ return k1_spi_dma_one(host, spi, transfer); ++ ++ /* An interrupt will initiate the transfer */ ++ val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; ++ writel(val, drv_data->base + SSP_INT_EN); ++ ++ return 1; /* We will call spi_finalize_current_transfer() */ ++} ++ ++static void ++k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ ++ if (drv_data->dma_enabled) { ++ dmaengine_terminate_sync(host->dma_rx); ++ dmaengine_terminate_sync(host->dma_tx); ++ } ++} ++ ++static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) ++{ ++ struct spi_transfer *transfer = drv_data->transfer; ++ u32 bytes = drv_data->bytes; ++ u32 val; ++ ++ if (transfer->tx_buf) { ++ const void *buf; ++ ++ buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); ++ if (bytes == 1) ++ val = *(u8 *)buf; ++ else if (bytes == 2) ++ val = *(u16 *)buf; ++ else /* bytes == 4 */ ++ val = *(u32 *)buf; ++ } else { ++ val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ ++ } ++ /* Fill the next TX FIFO entry */ ++ writel(val, drv_data->base + SSP_DATAR); ++ ++ drv_data->tx_resid -= bytes; ++} ++ ++/* The last-read status value is provided; we know SSP_STATUS_TNF is set */ ++static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) ++{ ++ unsigned int count; ++ ++ /* Get the number of open slots in the FIFO; zero means all */ ++ count = FIELD_GET(SSP_STATUS_TFL, val) ? : K1_SPI_FIFO_SIZE; ++ ++ /* ++ * Limit how much we try to send at a time, to reduce the ++ * chance the other side can overrun our RX FIFO. ++ */ ++ count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); ++ do ++ k1_spi_write_word(drv_data); ++ while (--count); ++ ++ return !drv_data->tx_resid; ++} ++ ++static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) ++{ ++ struct spi_transfer *transfer = drv_data->transfer; ++ u32 bytes = drv_data->bytes; ++ u32 val; ++ ++ /* Consume the next RX FIFO entry */ ++ val = readl(drv_data->base + SSP_DATAR); ++ if (transfer->rx_buf) { ++ void *buf; ++ ++ buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); ++ ++ if (bytes == 1) ++ *(u8 *)buf = val; ++ else if (bytes == 2) ++ *(u16 *)buf = val; ++ else /* bytes == 4 */ ++ *(u32 *)buf = val; ++ } /* Otherwise null reader: discard the data */ ++ ++ drv_data->rx_resid -= bytes; ++} ++ ++/* The last-read status value is provided; we know SSP_STATUS_RNE is set */ ++static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) ++{ ++ do { ++ unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; ++ ++ /* Only read what we need */ ++ count = min(count, drv_data->rx_resid / drv_data->bytes); ++ do ++ k1_spi_read_word(drv_data); ++ while (--count); ++ ++ /* If there's no more to read, we're done */ ++ if (!drv_data->rx_resid) ++ return true; ++ ++ /* Check again in case more became available to read */ ++ val = readl(drv_data->base + SSP_STATUS); ++ if (val & SSP_STATUS_RNE) ++ writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); ++ else ++ return false; ++ } while (true); ++} ++ ++static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) ++{ ++ struct k1_spi_driver_data *drv_data = dev_id; ++ u32 status; ++ u32 top_ctrl; ++ ++ /* Get status and clear pending interrupts */ ++ status = readl(drv_data->base + SSP_STATUS); ++ writel(status, drv_data->base + SSP_STATUS); ++ ++ /* If no actionable status bits are set, this is not our interrupt */ ++ if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) ++ return IRQ_NONE; ++ ++ /* Check for any error conditions first */ ++ if (status & SSP_STATUS_ERROR) { ++ if (drv_data->transfer) ++ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; ++ goto done; ++ } ++ ++ /* ++ * For SPI, bytes are transferred in both directions equally, and ++ * RX always follows TX. Start by writing if there is anything to ++ * write, then read. Once there's no more to read, we're done. ++ */ ++ if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { ++ /* If we finish writing, disable TX interrupts */ ++ if (k1_spi_write(drv_data, status)) ++ writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, ++ drv_data->base + SSP_INT_EN); ++ } ++ ++ /* We're not done unless we've read all that was requested */ ++ if (drv_data->rx_resid) { ++ /* Read more if the FIFO is not empty */ ++ if (status & SSP_STATUS_RNE) ++ if (k1_spi_read(drv_data, status)) ++ goto done; ++ ++ return IRQ_HANDLED; ++ } ++done: ++ /* Disable the port */ ++ top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); ++ top_ctrl &= ~TOP_SSE; ++ writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); ++ ++ /* Disable all interrupts */ ++ writel(0, drv_data->base + SSP_INT_EN); ++ ++ if (drv_data->transfer) { ++ drv_data->transfer = NULL; ++ spi_finalize_current_transfer(drv_data->host); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) ++{ ++ struct spi_controller *host = drv_data->host; ++ struct dma_chan *chan; ++ ++ chan = dma_request_chan(dev, "tx"); ++ if (IS_ERR(chan)) ++ return PTR_ERR(chan); ++ host->dma_tx = chan; ++ ++ chan = dma_request_chan(dev, "rx"); ++ if (IS_ERR(chan)) { ++ dma_release_channel(host->dma_tx); ++ host->dma_tx = NULL; ++ return PTR_ERR(chan); ++ } ++ host->dma_rx = chan; ++ ++ drv_data->dma_enabled = true; ++ ++ return 0; ++} ++ ++static void k1_spi_dma_cleanup(struct device *dev, void *res) ++{ ++ struct k1_spi_driver_data **ptr = res; ++ struct k1_spi_driver_data *drv_data = *ptr; ++ struct spi_controller *host = drv_data->host; ++ ++ if (!drv_data->dma_enabled) ++ return; ++ ++ drv_data->dma_enabled = false; ++ ++ dma_release_channel(host->dma_rx); ++ host->dma_rx = NULL; ++ dma_release_channel(host->dma_tx); ++ host->dma_tx = NULL; ++} ++ ++static int ++devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) ++{ ++ struct k1_spi_driver_data **ptr; ++ int ret; ++ ++ if (!IS_ENABLED(CONFIG_MMP_PDMA)) { ++ dev_info(dev, "DMA not available; using PIO\n"); ++ return 0; ++ } ++ ++ ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); ++ if (!ptr) ++ return -ENOMEM; ++ ++ ret = k1_spi_dma_setup(drv_data, dev); ++ if (ret) { ++ devres_free(ptr); ++ return ret; ++ } ++ ++ *ptr = drv_data; ++ devres_add(dev, ptr); ++ ++ return 0; ++} ++ ++static int k1_spi_probe(struct platform_device *pdev) ++{ ++ struct k1_spi_driver_data *drv_data; ++ struct device *dev = &pdev->dev; ++ struct reset_control *reset; ++ struct spi_controller *host; ++ struct resource *iores; ++ struct clk *clk_bus; ++ int ret; ++ ++ host = devm_spi_alloc_host(dev, sizeof(*drv_data)); ++ if (!host) ++ return -ENOMEM; ++ drv_data = spi_controller_get_devdata(host); ++ drv_data->host = host; ++ platform_set_drvdata(pdev, drv_data); ++ ++ ret = devm_k1_spi_dma_setup(drv_data, dev); ++ if (ret == -EPROBE_DEFER) ++ return ret; ++ if (ret) ++ dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); ++ ++ drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, ++ &iores); ++ if (IS_ERR(drv_data->base)) ++ return dev_err_probe(dev, PTR_ERR(drv_data->base), ++ "error mapping memory\n"); ++ drv_data->base_addr = iores->start; ++ ++ clk_bus = devm_clk_get_enabled(dev, "bus"); ++ if (IS_ERR(clk_bus)) ++ return dev_err_probe(dev, PTR_ERR(clk_bus), ++ "error getting/enabling bus clock\n"); ++ drv_data->bus_rate = clk_get_rate(clk_bus); ++ ++ drv_data->clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(drv_data->clk)) ++ return dev_err_probe(dev, PTR_ERR(drv_data->clk), ++ "error getting/enabling core clock\n"); ++ ++ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(reset)) ++ return dev_err_probe(dev, PTR_ERR(reset), ++ "error getting/deasserting reset\n"); ++ ++ k1_spi_register_reset(drv_data, true); ++ ++ drv_data->irq = platform_get_irq(pdev, 0); ++ if (drv_data->irq < 0) ++ return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); ++ ++ ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, ++ IRQF_SHARED, dev_name(dev), drv_data); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "error requesting IRQ\n"); ++ ++ /* Initialize the host structure, then register it */ ++ host->dev.of_node = dev_of_node(dev); ++ host->dev.parent = dev; ++ host->num_chipselect = 1; ++ if (drv_data->dma_enabled) ++ host->dma_alignment = K1_SPI_DMA_ALIGNMENT; ++ host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; ++ host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); ++ host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; ++ host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; ++ host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; ++ host->max_dma_len = K1_SPI_MAX_DMA_LEN; ++ ++ host->setup = k1_spi_setup; ++ host->cleanup = k1_spi_cleanup; ++ host->can_dma = k1_spi_can_dma; ++ host->prepare_message = k1_spi_prepare_message; ++ host->set_cs = k1_spi_set_cs; ++ host->transfer_one = k1_spi_transfer_one; ++ host->handle_err = k1_spi_handle_err; ++ ++ ret = devm_spi_register_controller(dev, host); ++ if (ret) ++ dev_err(dev, "error registering controller\n"); ++ ++ return ret; ++} ++ ++static const struct of_device_id k1_spi_dt_ids[] = { ++ { .compatible = "spacemit,k1-spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); ++ ++static struct platform_driver k1_spi_driver = { ++ .probe = k1_spi_probe, ++ .driver = { ++ .name = "k1-spi", ++ .of_match_table = k1_spi_dt_ids, ++ }, ++}; ++module_platform_driver(k1_spi_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch deleted file mode 100644 index 6ad93704d4..0000000000 --- a/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch +++ /dev/null @@ -1,142 +0,0 @@ -From 99bf7248cb67723d749134575afb9fcb3425bccd Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:17 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add thermal sensor for - K1 SoC - -Include the Thermal Sensor node in the SpacemiT K1 dtsi -with definitions for registers, clocks, and interrupts. -Additionally, configure thermal zones for the soc, package, gpu, and -clusters to enable temperature monitoring via the thermal framework. - -Tested-by: Vincent Legoll # OrangePi-RV2 -Tested-by: Gong Shuai -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ - 1 file changed, 101 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index f8747190d2e1..2ed5cc24e505 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -339,6 +339,96 @@ osc_32k: clock-32k { - }; - }; - -+ thermal-zones { -+ soc-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 0>; -+ -+ trips { -+ soc-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ package-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 1>; -+ -+ trips { -+ package-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 2>; -+ -+ trips { -+ gpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ gpu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cluster0-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 3>; -+ -+ trips { -+ cluster0-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cluster0-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cluster1-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 4>; -+ -+ trips { -+ cluster1-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cluster1-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; -@@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { - #reset-cells = <1>; - }; - -+ thermal: thermal@d4018000 { -+ compatible = "spacemit,k1-tsensor"; -+ reg = <0x0 0xd4018000 0x0 0x100>; -+ clocks = <&syscon_apbc CLK_TSEN>, -+ <&syscon_apbc CLK_TSEN_BUS>; -+ clock-names = "core", "bus"; -+ interrupts = <61>; -+ resets = <&syscon_apbc RESET_TSEN>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - i2c6: i2c@d4018800 { - compatible = "spacemit,k1-i2c"; - reg = <0x0 0xd4018800 0x0 0x38>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0321-UPSTREAM-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux-lts/0321-UPSTREAM-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch new file mode 100644 index 0000000000..28f651871d --- /dev/null +++ b/SPECS/linux-lts/0321-UPSTREAM-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch @@ -0,0 +1,43 @@ +From aa4a2c86728cf32921d3fbe11265934fd65f4792 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 5 May 2026 09:53:34 -0400 +Subject: [RUYI PATCH] UPSTREAM: spi: spacemit: add u64 cast to NSEC_PER_SEC to + avoid 32-bit overflow + +NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * +BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures +before the result reaches the u64 nsec_per_word. + +Promote the multiplication to u64 by casting the first operand, which is +NSEC_PER_SEC. + +Fixes: efcd8b9d1111 ("spi: spacemit: introduce SpacemiT K1 SPI controller driver") +Suggested-by: Alex Elder +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202605050437.RS6mmV2b-lkp@intel.com/ +Closes: https://lore.kernel.org/oe-kbuild-all/202605050317.Tf9j487w-lkp@intel.com/ +Signed-off-by: Guodong Xu +Link: https://patch.msgid.link/20260505-spi-spacemit-k1-fix-overflow-v1-1-77564c2e4e86@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit 00cef7eb08c8b9af0978f667c77c6a30b71b7e22) +Signed-off-by: Han Gao +--- + drivers/spi/spi-spacemit-k1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c +index 99db429db0b2..215fe66d27b4 100644 +--- a/drivers/spi/spi-spacemit-k1.c ++++ b/drivers/spi/spi-spacemit-k1.c +@@ -390,7 +390,7 @@ static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, + * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; + * We do the divide last for better accuracy. + */ +- nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; ++ nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; + nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); + + /* +-- +2.53.0 + diff --git a/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch deleted file mode 100644 index 560b162481..0000000000 --- a/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 83a04d13a39350e2059289ae74da6a837187c63e Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 17:24:21 +0800 -Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after - unmapping DMA - -In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA -before calling kfree() to deallocate the memory, instead of the other -way around. - -Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-4-0ab0122fdd14@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index 359b409f8203..48c80c075fdf 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -463,12 +463,12 @@ static void emac_free_tx_resources(struct emac_priv *priv) - - emac_clean_tx_desc_ring(priv); - -- kfree(tr->tx_desc_buf); -- tr->tx_desc_buf = NULL; -- - dma_free_coherent(dev, tr->total_size, tr->desc_addr, - tr->desc_dma_addr); - tr->desc_addr = NULL; -+ -+ kfree(tr->tx_desc_buf); -+ tr->tx_desc_buf = NULL; - } - - static void emac_free_rx_resources(struct emac_priv *priv) -@@ -478,12 +478,12 @@ static void emac_free_rx_resources(struct emac_priv *priv) - - emac_clean_rx_desc_ring(priv); - -- kfree(rr->rx_desc_buf); -- rr->rx_desc_buf = NULL; -- - dma_free_coherent(dev, rr->total_size, rr->desc_addr, - rr->desc_dma_addr); - rr->desc_addr = NULL; -+ -+ kfree(rr->rx_desc_buf); -+ rr->rx_desc_buf = NULL; - } - - static int emac_tx_clean_desc(struct emac_priv *priv) --- -2.53.0 - diff --git a/SPECS/linux-lts/0322-UPSTREAM-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux-lts/0322-UPSTREAM-riscv-dts-spacemit-define-a-SPI-controller-.patch new file mode 100644 index 0000000000..c4fb36efd0 --- /dev/null +++ b/SPECS/linux-lts/0322-UPSTREAM-riscv-dts-spacemit-define-a-SPI-controller-.patch @@ -0,0 +1,116 @@ +From 2e4e61ca226d44b5ce1e7e2f945827d19bd181ce Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:53 -0400 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define a SPI controller + node + +Define a node for the fourth SoC SPI controller (number 3) on the +SpacemiT K1 SoC. + +Enable it on the Banana Pi BPI-F3 board, which exposes this feature +via its GPIO block: + GPIO PIN 19: MOSI + GPIO PIN 21: MISO + GPIO PIN 23: SCLK + GPIO PIN 24: SS (inverted) + +Define pincontrol configurations for the pins as used on that board. + +(This was tested using a GigaDevice GD25Q64E SPI NOR chip.) + +Reviewed-by: Yixun Lan +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit c580774185426ea316396b1dc3f1737a3ad3800a) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ + 3 files changed, 42 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 5790d927b93d..9429189354d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -14,6 +14,7 @@ aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; ++ spi3 = &spi3; + i2c2 = &i2c2; + i2c8 = &i2c8; + }; +@@ -335,6 +336,12 @@ &pcie2 { + status = "okay"; + }; + ++&spi3 { ++ pinctrl-0 = <&ssp3_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index b13dcb10f4d6..34d88334e95e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -570,4 +570,24 @@ pwm14-1-pins { + drive-strength = <32>; + }; + }; ++ ++ ssp3_0_cfg: ssp3-0-cfg { ++ ssp3-0-pins { ++ pinmux = , /* SCLK */ ++ , /* MOSI */ ++ ; /* MISO */ ++ ++ bias-disable; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ ssp3-0-frm-pins { ++ pinmux = ; /* FRM (frame) */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index f0bad6855c97..f8747190d2e1 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -983,6 +983,21 @@ qspi: spi@d420c000 { + status = "disabled"; + }; + ++ spi3: spi@d401c000 { ++ compatible = "spacemit,k1-spi"; ++ reg = <0x0 0xd401c000 0x0 0x30>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_SSP3>, ++ <&syscon_apbc CLK_SSP3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_SSP3>; ++ interrupts = <55>; ++ dmas = <&pdma 20>, <&pdma 19>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + /* sec_uart1: 0xf0612000, not available from Linux */ + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch b/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch deleted file mode 100644 index 5a383caca0..0000000000 --- a/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 0615284b82b82ee1dc7ccbc7146e31afa8bbbc9f Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:45 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Extract helper mark_new_valid_map() - -In preparation of a future patch using the same mechanism for -non-vmalloc addresses, extract the mark_new_valid_map() helper from -flush_cache_vmap(). - -No functional change intended. - -Cc: stable@vger.kernel.org -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-1-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 25 ++++++++++++++----------- - 1 file changed, 14 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index 0092513c3376..b1a2ac665792 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -43,20 +43,23 @@ do { \ - #ifdef CONFIG_64BIT - extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; - extern char _end[]; -+static inline void mark_new_valid_map(void) -+{ -+ int i; -+ -+ /* -+ * We don't care if concurrently a cpu resets this value since -+ * the only place this can happen is in handle_exception() where -+ * an sfence.vma is emitted. -+ */ -+ for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -+ new_vmalloc[i] = -1ULL; -+} - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) - { -- if (is_vmalloc_or_module_addr((void *)start)) { -- int i; -- -- /* -- * We don't care if concurrently a cpu resets this value since -- * the only place this can happen is in handle_exception() where -- * an sfence.vma is emitted. -- */ -- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -- new_vmalloc[i] = -1ULL; -- } -+ if (is_vmalloc_or_module_addr((void *)start)) -+ mark_new_valid_map(); - } - #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0323-UPSTREAM-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux-lts/0323-UPSTREAM-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch new file mode 100644 index 0000000000..2a22e408af --- /dev/null +++ b/SPECS/linux-lts/0323-UPSTREAM-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch @@ -0,0 +1,106 @@ +From a1ad9185aadd589ed707c4b1e557eb8013447fde Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: thermal: Add SpacemiT K1 thermal + sensor + +Document the SpacemiT K1 Thermal Sensor, which supports +monitoring temperatures for five zones: soc, package, gpu, cluster0, +and cluster1. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Shuwei Wu +Signed-off-by: Daniel Lezcano +Link: https://patch.msgid.link/20260427-k1-thermal-v5-1-df39187480ed@mailbox.org +(cherry picked from commit 0309075e080306ad2e3b3148a3495b10dd252ef2) +Signed-off-by: Han Gao +--- + .../bindings/thermal/spacemit,k1-tsensor.yaml | 76 +++++++++++++++++++ + 1 file changed, 76 insertions(+) + create mode 100644 Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml + +diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml +new file mode 100644 +index 000000000000..6dad76a7dd36 +--- /dev/null ++++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml +@@ -0,0 +1,76 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 Thermal Sensor ++ ++description: ++ The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC ++ using multiple internal sensors (e.g., soc, package, gpu, clusters). ++ ++maintainers: ++ - Shuwei Wu ++ ++$ref: thermal-sensor.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k1-tsensor ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Core clock for thermal sensor ++ - description: Bus clock for thermal sensor ++ ++ clock-names: ++ items: ++ - const: core ++ - const: bus ++ ++ interrupts: ++ maxItems: 1 ++ ++ resets: ++ items: ++ - description: Reset for the thermal sensor ++ ++ "#thermal-sensor-cells": ++ const: 1 ++ description: ++ The first cell indicates the sensor ID. ++ 0 = soc ++ 1 = package ++ 2 = gpu ++ 3 = cluster0 ++ 4 = cluster1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - resets ++ - "#thermal-sensor-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ thermal@d4018000 { ++ compatible = "spacemit,k1-tsensor"; ++ reg = <0xd4018000 0x100>; ++ clocks = <&syscon_apbc CLK_TSEN>, ++ <&syscon_apbc CLK_TSEN_BUS>; ++ clock-names = "core", "bus"; ++ interrupts = <61>; ++ resets = <&syscon_apbc RESET_TSEN>; ++ #thermal-sensor-cells = <1>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch b/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch deleted file mode 100644 index 24cfe28e1b..0000000000 --- a/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch +++ /dev/null @@ -1,80 +0,0 @@ -From a6ee02e2ad7a759a5906206b87b7525c1ac580e4 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:46 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: kfence: Call mark_new_valid_map() for - kfence_unprotect() - -In kfence_protect_page(), which kfence_unprotect() calls, we cannot send -IPIs to other CPUs to ask them to flush TLB. This may lead to those CPUs -spuriously faulting on a recently allocated kfence object despite it -being valid, leading to false positive use-after-free reports. - -Fix this by calling mark_new_valid_map() so that the page fault handling -code path notices the spurious fault and flushes TLB then retries the -access. - -Update the comment in handle_exception to indicate that -new_valid_map_cpus_check also handles kfence_unprotect() spurious -faults. - -Note that kfence_protect() has the same stale TLB entries problem, but -that leads to false negatives, which is fine with kfence. - -Cc: stable@vger.kernel.org -Reported-by: Yanko Kaneti -Fixes: b3431a8bb336 ("riscv: Fix IPIs usage in kfence_protect_page()") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-2-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/kfence.h | 7 +++++-- - arch/riscv/kernel/entry.S | 6 ++++-- - 2 files changed, 9 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/include/asm/kfence.h b/arch/riscv/include/asm/kfence.h -index d08bf7fb3aee..29cb3a6ee113 100644 ---- a/arch/riscv/include/asm/kfence.h -+++ b/arch/riscv/include/asm/kfence.h -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - - static inline bool arch_kfence_init_pool(void) -@@ -17,10 +18,12 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect) - { - pte_t *pte = virt_to_kpte(addr); - -- if (protect) -+ if (protect) { - set_pte(pte, __pte(pte_val(ptep_get(pte)) & ~_PAGE_PRESENT)); -- else -+ } else { - set_pte(pte, __pte(pte_val(ptep_get(pte)) | _PAGE_PRESENT)); -+ mark_new_valid_map(); -+ } - - preempt_disable(); - local_flush_tlb_kernel_range(addr, addr + PAGE_SIZE); -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index 9b9dec6893b8..e7bd03a9ced5 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -107,8 +107,10 @@ SYM_CODE_START(handle_exception) - - #ifdef CONFIG_64BIT - /* -- * The RISC-V kernel does not eagerly emit a sfence.vma after each -- * new vmalloc mapping, which may result in exceptions: -+ * The RISC-V kernel does not flush TLBs on all CPUS after each new -+ * vmalloc mapping or kfence_unprotect(), which may result in -+ * exceptions: -+ * - * - if the uarch caches invalid entries, the new mapping would not be - * observed by the page table walker and an invalidation is needed. - * - if the uarch does not cache invalid entries, a reordered access --- -2.53.0 - diff --git a/SPECS/linux-lts/0324-UPSTREAM-thermal-drivers-spacemit-k1-Add-thermal-sen.patch b/SPECS/linux-lts/0324-UPSTREAM-thermal-drivers-spacemit-k1-Add-thermal-sen.patch new file mode 100644 index 0000000000..2ace22f808 --- /dev/null +++ b/SPECS/linux-lts/0324-UPSTREAM-thermal-drivers-spacemit-k1-Add-thermal-sen.patch @@ -0,0 +1,382 @@ +From 71b21b20b4bdeada625862067165bb41c7e15671 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: thermal/drivers/spacemit/k1: Add thermal + sensor support + +The thermal sensor on K1 supports monitoring five temperature zones. +The driver registers these sensors with the thermal framework +and supports standard operations: +- Reading temperature (millidegree Celsius) +- Setting high/low thresholds for interrupts + +Signed-off-by: Shuwei Wu +Signed-off-by: Daniel Lezcano +Reviewed-by: Anand Moon +Reviewed-by: Troy Mitchell +Reviewed-by: Yao Zi +Tested-by: Anand Moon +Tested-by: Vincent Legoll # OrangePi-RV2 +Tested-by: Gong Shuai +Link: https://patch.msgid.link/20260427-k1-thermal-v5-2-df39187480ed@mailbox.org +(cherry picked from commit 296a977f2bac45759a427dc57a21edb628f5c86c) +Signed-off-by: Han Gao +--- + drivers/thermal/Kconfig | 2 + + drivers/thermal/Makefile | 1 + + drivers/thermal/spacemit/Kconfig | 19 ++ + drivers/thermal/spacemit/Makefile | 3 + + drivers/thermal/spacemit/k1_tsensor.c | 280 ++++++++++++++++++++++++++ + 5 files changed, 305 insertions(+) + create mode 100644 drivers/thermal/spacemit/Kconfig + create mode 100644 drivers/thermal/spacemit/Makefile + create mode 100644 drivers/thermal/spacemit/k1_tsensor.c + +diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig +index a09c188b9ad1..a96e2d045d97 100644 +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -462,6 +462,8 @@ endmenu + + source "drivers/thermal/renesas/Kconfig" + ++source "drivers/thermal/spacemit/Kconfig" ++ + source "drivers/thermal/tegra/Kconfig" + + config GENERIC_ADC_THERMAL +diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile +index d7718978db24..64cbed51d4fb 100644 +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -64,6 +64,7 @@ obj-y += mediatek/ + obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o + obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o + obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o ++obj-y += spacemit/ + obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o + obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o + obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o +diff --git a/drivers/thermal/spacemit/Kconfig b/drivers/thermal/spacemit/Kconfig +new file mode 100644 +index 000000000000..de7b5ece5af2 +--- /dev/null ++++ b/drivers/thermal/spacemit/Kconfig +@@ -0,0 +1,19 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++menu "SpacemiT thermal drivers" ++depends on ARCH_SPACEMIT || COMPILE_TEST ++ ++config SPACEMIT_K1_TSENSOR ++ tristate "SpacemiT K1 thermal sensor driver" ++ depends on THERMAL_OF ++ help ++ This driver provides support for the thermal sensor ++ integrated in the SpacemiT K1 SoC. ++ ++ The thermal sensor monitors temperatures for five thermal zones: ++ soc, package, gpu, cluster0, and cluster1. It supports reporting ++ temperature values and handling high/low threshold interrupts. ++ ++ Say Y here if you want to enable thermal monitoring on SpacemiT K1. ++ If compiled as a module, it will be called k1_tsensor. ++ ++endmenu +diff --git a/drivers/thermal/spacemit/Makefile b/drivers/thermal/spacemit/Makefile +new file mode 100644 +index 000000000000..82b30741e4ec +--- /dev/null ++++ b/drivers/thermal/spacemit/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_SPACEMIT_K1_TSENSOR) += k1_tsensor.o +diff --git a/drivers/thermal/spacemit/k1_tsensor.c b/drivers/thermal/spacemit/k1_tsensor.c +new file mode 100644 +index 000000000000..79222d233129 +--- /dev/null ++++ b/drivers/thermal/spacemit/k1_tsensor.c +@@ -0,0 +1,280 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Thermal sensor driver for SpacemiT K1 SoC ++ * ++ * Copyright (C) 2026 Shuwei Wu ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../thermal_hwmon.h" ++ ++#define K1_TSENSOR_PCTRL_REG 0x00 ++#define K1_TSENSOR_PCTRL_ENABLE BIT(0) ++#define K1_TSENSOR_PCTRL_TEMP_MODE BIT(3) ++#define K1_TSENSOR_PCTRL_RAW_SEL BIT(7) ++ ++#define K1_TSENSOR_PCTRL_CTUNE GENMASK(11, 8) ++#define K1_TSENSOR_PCTRL_SW_CTRL GENMASK(21, 18) ++#define K1_TSENSOR_PCTRL_HW_AUTO_MODE BIT(23) ++ ++#define K1_TSENSOR_EN_REG 0x08 ++#define K1_TSENSOR_EN_ALL GENMASK(MAX_SENSOR_NUMBER - 1, 0) ++ ++#define K1_TSENSOR_TIME_REG 0x0C ++#define K1_TSENSOR_TIME_WAIT_REF_CNT GENMASK(3, 0) ++#define K1_TSENSOR_TIME_ADC_CNT_RST GENMASK(7, 4) ++#define K1_TSENSOR_TIME_FILTER_PERIOD GENMASK(21, 20) ++#define K1_TSENSOR_TIME_MASK GENMASK(23, 0) ++ ++#define K1_TSENSOR_INT_CLR_REG 0x10 ++#define K1_TSENSOR_INT_EN_REG 0x14 ++#define K1_TSENSOR_INT_STA_REG 0x18 ++ ++#define K1_TSENSOR_INT_EN_MASK BIT(0) ++#define K1_TSENSOR_INT_MASK(x) (GENMASK(2, 1) << ((x) * 2)) ++ ++#define K1_TSENSOR_DATA_BASE_REG 0x20 ++#define K1_TSENSOR_DATA_REG(x) (K1_TSENSOR_DATA_BASE_REG + ((x) / 2) * 4) ++#define K1_TSENSOR_DATA_LOW_MASK GENMASK(15, 0) ++#define K1_TSENSOR_DATA_HIGH_MASK GENMASK(31, 16) ++ ++#define K1_TSENSOR_THRSH_BASE_REG 0x40 ++#define K1_TSENSOR_THRSH_REG(x) (K1_TSENSOR_THRSH_BASE_REG + ((x) * 4)) ++#define K1_TSENSOR_THRSH_LOW_MASK GENMASK(15, 0) ++#define K1_TSENSOR_THRSH_HIGH_MASK GENMASK(31, 16) ++ ++#define MAX_SENSOR_NUMBER 5 ++ ++/* Hardware offset value required for temperature calculation */ ++#define TEMPERATURE_OFFSET 278 ++ ++struct k1_tsensor_channel { ++ struct k1_tsensor *ts; ++ struct thermal_zone_device *tzd; ++ int id; ++}; ++ ++struct k1_tsensor { ++ void __iomem *base; ++ struct k1_tsensor_channel ch[MAX_SENSOR_NUMBER]; ++}; ++ ++static void k1_tsensor_init(struct k1_tsensor *ts) ++{ ++ u32 val; ++ ++ /* Disable all the interrupts */ ++ writel(0xffffffff, ts->base + K1_TSENSOR_INT_EN_REG); ++ ++ /* Configure ADC sampling time and filter period */ ++ val = readl(ts->base + K1_TSENSOR_TIME_REG); ++ val &= ~K1_TSENSOR_TIME_MASK; ++ val |= K1_TSENSOR_TIME_FILTER_PERIOD | ++ K1_TSENSOR_TIME_ADC_CNT_RST | ++ K1_TSENSOR_TIME_WAIT_REF_CNT; ++ writel(val, ts->base + K1_TSENSOR_TIME_REG); ++ ++ /* ++ * Enable all sensors' auto mode, enable dither control, ++ * consecutive mode, and power up sensor. ++ */ ++ val = readl(ts->base + K1_TSENSOR_PCTRL_REG); ++ val &= ~K1_TSENSOR_PCTRL_SW_CTRL; ++ val &= ~K1_TSENSOR_PCTRL_CTUNE; ++ val |= K1_TSENSOR_PCTRL_RAW_SEL | ++ K1_TSENSOR_PCTRL_TEMP_MODE | ++ K1_TSENSOR_PCTRL_HW_AUTO_MODE | ++ K1_TSENSOR_PCTRL_ENABLE; ++ writel(val, ts->base + K1_TSENSOR_PCTRL_REG); ++ ++ /* Enable each sensor */ ++ val = readl(ts->base + K1_TSENSOR_EN_REG); ++ val |= K1_TSENSOR_EN_ALL; ++ writel(val, ts->base + K1_TSENSOR_EN_REG); ++} ++ ++static void k1_tsensor_enable_irq(struct k1_tsensor_channel *ch) ++{ ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ val = readl(ts->base + K1_TSENSOR_INT_CLR_REG); ++ val |= K1_TSENSOR_INT_MASK(ch->id); ++ writel(val, ts->base + K1_TSENSOR_INT_CLR_REG); ++ ++ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); ++ val &= ~K1_TSENSOR_INT_MASK(ch->id); ++ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); ++ ++ /* Enable thermal interrupt */ ++ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); ++ val |= K1_TSENSOR_INT_EN_MASK; ++ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); ++} ++ ++/* ++ * The conversion formula used is: ++ * T(m°C) = (((raw_value & mask) >> shift) - TEMPERATURE_OFFSET) * 1000 ++ */ ++static int k1_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) ++{ ++ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ val = readl(ts->base + K1_TSENSOR_DATA_REG(ch->id)); ++ if (ch->id % 2) ++ *temp = FIELD_GET(K1_TSENSOR_DATA_HIGH_MASK, val); ++ else ++ *temp = FIELD_GET(K1_TSENSOR_DATA_LOW_MASK, val); ++ ++ *temp -= TEMPERATURE_OFFSET; ++ *temp *= 1000; ++ ++ return 0; ++} ++ ++/* ++ * For each sensor, the hardware threshold register is 32 bits: ++ * - Lower 16 bits [15:0] configure the low threshold temperature. ++ * - Upper 16 bits [31:16] configure the high threshold temperature. ++ */ ++static int k1_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) ++{ ++ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ if (low >= high) ++ return -EINVAL; ++ ++ low = clamp_val(low / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, ++ FIELD_MAX(K1_TSENSOR_THRSH_LOW_MASK)); ++ high = clamp_val(high / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, ++ FIELD_MAX(K1_TSENSOR_THRSH_HIGH_MASK)); ++ ++ val = readl(ts->base + K1_TSENSOR_THRSH_REG(ch->id)); ++ ++ val &= ~(K1_TSENSOR_THRSH_LOW_MASK | K1_TSENSOR_THRSH_HIGH_MASK); ++ val |= FIELD_PREP(K1_TSENSOR_THRSH_LOW_MASK, low); ++ val |= FIELD_PREP(K1_TSENSOR_THRSH_HIGH_MASK, high); ++ ++ writel(val, ts->base + K1_TSENSOR_THRSH_REG(ch->id)); ++ ++ return 0; ++} ++ ++static const struct thermal_zone_device_ops k1_tsensor_ops = { ++ .get_temp = k1_tsensor_get_temp, ++ .set_trips = k1_tsensor_set_trips, ++}; ++ ++static irqreturn_t k1_tsensor_irq_thread(int irq, void *data) ++{ ++ struct k1_tsensor *ts = (struct k1_tsensor *)data; ++ int mask, status, i; ++ ++ status = readl(ts->base + K1_TSENSOR_INT_STA_REG); ++ ++ for (i = 0; i < MAX_SENSOR_NUMBER; i++) { ++ if (status & K1_TSENSOR_INT_MASK(i)) { ++ mask = readl(ts->base + K1_TSENSOR_INT_CLR_REG); ++ mask |= K1_TSENSOR_INT_MASK(i); ++ writel(mask, ts->base + K1_TSENSOR_INT_CLR_REG); ++ thermal_zone_device_update(ts->ch[i].tzd, THERMAL_EVENT_UNSPECIFIED); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int k1_tsensor_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct k1_tsensor *ts; ++ struct reset_control *reset; ++ struct clk *clk; ++ int i, irq, ret; ++ ++ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); ++ if (!ts) ++ return -ENOMEM; ++ ++ ts->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ts->base)) ++ return dev_err_probe(dev, PTR_ERR(ts->base), "Failed to get reg\n"); ++ ++ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(reset)) ++ return dev_err_probe(dev, PTR_ERR(reset), "Failed to get/deassert reset control\n"); ++ ++ clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get core clock\n"); ++ ++ clk = devm_clk_get_enabled(dev, "bus"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get bus clock\n"); ++ ++ k1_tsensor_init(ts); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = devm_request_threaded_irq(dev, irq, NULL, ++ k1_tsensor_irq_thread, ++ IRQF_ONESHOT, "k1_tsensor", ts); ++ if (ret < 0) ++ return ret; ++ ++ for (i = 0; i < MAX_SENSOR_NUMBER; ++i) { ++ ts->ch[i].id = i; ++ ts->ch[i].ts = ts; ++ ts->ch[i].tzd = devm_thermal_of_zone_register(dev, i, ts->ch + i, &k1_tsensor_ops); ++ if (IS_ERR(ts->ch[i].tzd)) ++ return PTR_ERR(ts->ch[i].tzd); ++ ++ /* Attach sysfs hwmon attributes for userspace monitoring */ ++ ret = devm_thermal_add_hwmon_sysfs(dev, ts->ch[i].tzd); ++ if (ret) ++ dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); ++ ++ k1_tsensor_enable_irq(ts->ch + i); ++ } ++ ++ platform_set_drvdata(pdev, ts); ++ ++ return 0; ++} ++ ++static const struct of_device_id k1_tsensor_dt_ids[] = { ++ { .compatible = "spacemit,k1-tsensor" }, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, k1_tsensor_dt_ids); ++ ++static struct platform_driver k1_tsensor_driver = { ++ .driver = { ++ .name = "k1_tsensor", ++ .of_match_table = k1_tsensor_dt_ids, ++ }, ++ .probe = k1_tsensor_probe, ++}; ++module_platform_driver(k1_tsensor_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 Thermal Sensor Driver"); ++MODULE_AUTHOR("Shuwei Wu "); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch deleted file mode 100644 index a75c6a24b4..0000000000 --- a/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch +++ /dev/null @@ -1,162 +0,0 @@ -From 0ff2687ed24d31a6e1dcee2c1fd287112688dabe Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:47 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Rename new_vmalloc into - new_valid_map_cpus - -Since this mechanism is now used for the kfence pool, which comes from -the linear mapping and not vmalloc, rename new_vmalloc into -new_valid_map_cpus to avoid misleading readers. - -No functional change intended. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-3-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 6 ++--- - arch/riscv/kernel/entry.S | 38 ++++++++++++++--------------- - arch/riscv/mm/init.c | 2 +- - 3 files changed, 23 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index b1a2ac665792..8c7a0ef2635a 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -41,7 +41,7 @@ do { \ - } while (0) - - #ifdef CONFIG_64BIT --extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; -+extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; - extern char _end[]; - static inline void mark_new_valid_map(void) - { -@@ -52,8 +52,8 @@ static inline void mark_new_valid_map(void) - * the only place this can happen is in handle_exception() where - * an sfence.vma is emitted. - */ -- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -- new_vmalloc[i] = -1ULL; -+ for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) -+ new_valid_map_cpus[i] = -1ULL; - } - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index e7bd03a9ced5..4f88d3353b00 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -20,44 +20,44 @@ - - .section .irqentry.text, "ax" - --.macro new_vmalloc_check -+.macro new_valid_map_cpus_check - REG_S a0, TASK_TI_A0(tp) - csrr a0, CSR_CAUSE - /* Exclude IRQs */ -- blt a0, zero, .Lnew_vmalloc_restore_context_a0 -+ blt a0, zero, .Lnew_valid_map_cpus_restore_context_a0 - - REG_S a1, TASK_TI_A1(tp) -- /* Only check new_vmalloc if we are in page/protection fault */ -+ /* Only check new_valid_map_cpus if we are in page/protection fault */ - li a1, EXC_LOAD_PAGE_FAULT -- beq a0, a1, .Lnew_vmalloc_kernel_address -+ beq a0, a1, .Lnew_valid_map_cpus_kernel_address - li a1, EXC_STORE_PAGE_FAULT -- beq a0, a1, .Lnew_vmalloc_kernel_address -+ beq a0, a1, .Lnew_valid_map_cpus_kernel_address - li a1, EXC_INST_PAGE_FAULT -- bne a0, a1, .Lnew_vmalloc_restore_context_a1 -+ bne a0, a1, .Lnew_valid_map_cpus_restore_context_a1 - --.Lnew_vmalloc_kernel_address: -+.Lnew_valid_map_cpus_kernel_address: - /* Is it a kernel address? */ - csrr a0, CSR_TVAL -- bge a0, zero, .Lnew_vmalloc_restore_context_a1 -+ bge a0, zero, .Lnew_valid_map_cpus_restore_context_a1 - - /* Check if a new vmalloc mapping appeared that could explain the trap */ - REG_S a2, TASK_TI_A2(tp) - /* - * Computes: -- * a0 = &new_vmalloc[BIT_WORD(cpu)] -+ * a0 = &new_valid_map_cpus[BIT_WORD(cpu)] - * a1 = BIT_MASK(cpu) - */ - lw a2, TASK_TI_CPU(tp) - /* -- * Compute the new_vmalloc element position: -+ * Compute the new_valid_map_cpus element position: - * (cpu / 64) * 8 = (cpu >> 6) << 3 - */ - srli a1, a2, 6 - slli a1, a1, 3 -- la a0, new_vmalloc -+ la a0, new_valid_map_cpus - add a0, a0, a1 - /* -- * Compute the bit position in the new_vmalloc element: -+ * Compute the bit position in the new_valid_map_cpus element: - * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6 - * = cpu - ((cpu >> 6) << 3) << 3 - */ -@@ -67,12 +67,12 @@ - li a2, 1 - sll a1, a2, a1 - -- /* Check the value of new_vmalloc for this cpu */ -+ /* Check the value of new_valid_map_cpus for this cpu */ - REG_L a2, 0(a0) - and a2, a2, a1 -- beq a2, zero, .Lnew_vmalloc_restore_context -+ beq a2, zero, .Lnew_valid_map_cpus_restore_context - -- /* Atomically reset the current cpu bit in new_vmalloc */ -+ /* Atomically reset the current cpu bit in new_valid_map_cpus */ - amoxor.d a0, a1, (a0) - - /* Only emit a sfence.vma if the uarch caches invalid entries */ -@@ -84,11 +84,11 @@ - csrw CSR_SCRATCH, x0 - sret - --.Lnew_vmalloc_restore_context: -+.Lnew_valid_map_cpus_restore_context: - REG_L a2, TASK_TI_A2(tp) --.Lnew_vmalloc_restore_context_a1: -+.Lnew_valid_map_cpus_restore_context_a1: - REG_L a1, TASK_TI_A1(tp) --.Lnew_vmalloc_restore_context_a0: -+.Lnew_valid_map_cpus_restore_context_a0: - REG_L a0, TASK_TI_A0(tp) - .endm - -@@ -117,7 +117,7 @@ SYM_CODE_START(handle_exception) - * could "miss" the new mapping and traps: in that case, we only need - * to retry the access, no sfence.vma is required. - */ -- new_vmalloc_check -+ new_valid_map_cpus_check - #endif - - REG_S sp, TASK_TI_KERNEL_SP(tp) -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 8f4e7e505906..750d3356683a 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -37,7 +37,7 @@ - - #include "../kernel/head.h" - --u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; -+u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; - - struct kernel_mapping kernel_map __ro_after_init; - EXPORT_SYMBOL(kernel_map); --- -2.53.0 - diff --git a/SPECS/linux-lts/0325-UPSTREAM-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux-lts/0325-UPSTREAM-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch new file mode 100644 index 0000000000..43d7a4322d --- /dev/null +++ b/SPECS/linux-lts/0325-UPSTREAM-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch @@ -0,0 +1,145 @@ +From 0a392c75073727b0d88a59c8552d6d1b8cc59aea Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add thermal sensor for + K1 SoC + +Include the Thermal Sensor node in the SpacemiT K1 dtsi +with definitions for registers, clocks, and interrupts. +Additionally, configure thermal zones for the soc, package, gpu, and +clusters to enable temperature monitoring via the thermal framework. + +Tested-by: Vincent Legoll # OrangePi-RV2 +Tested-by: Gong Shuai +Signed-off-by: Shuwei Wu +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org +Signed-off-by: Yixun Lan +(cherry picked from commit 247c77ff5806bcd6a5ff802718de1f0aa2bcba6c) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ + 1 file changed, 101 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index f8747190d2e1..2ed5cc24e505 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -339,6 +339,96 @@ osc_32k: clock-32k { + }; + }; + ++ thermal-zones { ++ soc-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 0>; ++ ++ trips { ++ soc-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ package-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 1>; ++ ++ trips { ++ package-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 2>; ++ ++ trips { ++ gpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ gpu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cluster0-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 3>; ++ ++ trips { ++ cluster0-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cluster0-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cluster1-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 4>; ++ ++ trips { ++ cluster1-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cluster1-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; +@@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { + #reset-cells = <1>; + }; + ++ thermal: thermal@d4018000 { ++ compatible = "spacemit,k1-tsensor"; ++ reg = <0x0 0xd4018000 0x0 0x100>; ++ clocks = <&syscon_apbc CLK_TSEN>, ++ <&syscon_apbc CLK_TSEN_BUS>; ++ clock-names = "core", "bus"; ++ interrupts = <61>; ++ resets = <&syscon_apbc RESET_TSEN>; ++ #thermal-sensor-cells = <1>; ++ }; ++ + i2c6: i2c@d4018800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4018800 0x0 0x38>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch deleted file mode 100644 index 6e8c075234..0000000000 --- a/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch +++ /dev/null @@ -1,61 +0,0 @@ -From e7c9b52a88814781a9b973a8bc5d43cb3655f869 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:48 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Use the bitmap API for - new_valid_map_cpus - -The bitmap was defined with incorrect size. Fix it by using the proper -bitmap API in C code. The corresponding assembly code is still okay and -remains unchanged. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-4-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 8 +++----- - arch/riscv/mm/init.c | 2 +- - 2 files changed, 4 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index 8c7a0ef2635a..8cfe59483a8f 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -41,19 +41,17 @@ do { \ - } while (0) - - #ifdef CONFIG_64BIT --extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; -+/* This is accessed in assembly code. cpumask_var_t would be too complex. */ -+extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); - extern char _end[]; - static inline void mark_new_valid_map(void) - { -- int i; -- - /* - * We don't care if concurrently a cpu resets this value since - * the only place this can happen is in handle_exception() where - * an sfence.vma is emitted. - */ -- for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) -- new_valid_map_cpus[i] = -1ULL; -+ bitmap_fill(new_valid_map_cpus, NR_CPUS); - } - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 750d3356683a..6533cc17825a 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -37,7 +37,7 @@ - - #include "../kernel/head.h" - --u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; -+DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); - - struct kernel_mapping kernel_map __ro_after_init; - EXPORT_SYMBOL(kernel_map); --- -2.53.0 - diff --git a/SPECS/linux-lts/0326-UPSTREAM-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux-lts/0326-UPSTREAM-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch new file mode 100644 index 0000000000..aba60f1573 --- /dev/null +++ b/SPECS/linux-lts/0326-UPSTREAM-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch @@ -0,0 +1,164 @@ +From e8af905f2845703432550c425161b23d3eef9770 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Rename new_vmalloc into + new_valid_map_cpus + +Since this mechanism is now used for the kfence pool, which comes from +the linear mapping and not vmalloc, rename new_vmalloc into +new_valid_map_cpus to avoid misleading readers. + +No functional change intended. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-3-f80d8354d79d@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit a50940adfb8f390337d6ef9afe15b66ec498aceb) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 6 ++--- + arch/riscv/kernel/entry.S | 38 ++++++++++++++--------------- + arch/riscv/mm/init.c | 2 +- + 3 files changed, 23 insertions(+), 23 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index b1a2ac665792..8c7a0ef2635a 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -41,7 +41,7 @@ do { \ + } while (0) + + #ifdef CONFIG_64BIT +-extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; ++extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; + extern char _end[]; + static inline void mark_new_valid_map(void) + { +@@ -52,8 +52,8 @@ static inline void mark_new_valid_map(void) + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. + */ +- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) +- new_vmalloc[i] = -1ULL; ++ for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) ++ new_valid_map_cpus[i] = -1ULL; + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index e7bd03a9ced5..4f88d3353b00 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -20,44 +20,44 @@ + + .section .irqentry.text, "ax" + +-.macro new_vmalloc_check ++.macro new_valid_map_cpus_check + REG_S a0, TASK_TI_A0(tp) + csrr a0, CSR_CAUSE + /* Exclude IRQs */ +- blt a0, zero, .Lnew_vmalloc_restore_context_a0 ++ blt a0, zero, .Lnew_valid_map_cpus_restore_context_a0 + + REG_S a1, TASK_TI_A1(tp) +- /* Only check new_vmalloc if we are in page/protection fault */ ++ /* Only check new_valid_map_cpus if we are in page/protection fault */ + li a1, EXC_LOAD_PAGE_FAULT +- beq a0, a1, .Lnew_vmalloc_kernel_address ++ beq a0, a1, .Lnew_valid_map_cpus_kernel_address + li a1, EXC_STORE_PAGE_FAULT +- beq a0, a1, .Lnew_vmalloc_kernel_address ++ beq a0, a1, .Lnew_valid_map_cpus_kernel_address + li a1, EXC_INST_PAGE_FAULT +- bne a0, a1, .Lnew_vmalloc_restore_context_a1 ++ bne a0, a1, .Lnew_valid_map_cpus_restore_context_a1 + +-.Lnew_vmalloc_kernel_address: ++.Lnew_valid_map_cpus_kernel_address: + /* Is it a kernel address? */ + csrr a0, CSR_TVAL +- bge a0, zero, .Lnew_vmalloc_restore_context_a1 ++ bge a0, zero, .Lnew_valid_map_cpus_restore_context_a1 + + /* Check if a new vmalloc mapping appeared that could explain the trap */ + REG_S a2, TASK_TI_A2(tp) + /* + * Computes: +- * a0 = &new_vmalloc[BIT_WORD(cpu)] ++ * a0 = &new_valid_map_cpus[BIT_WORD(cpu)] + * a1 = BIT_MASK(cpu) + */ + lw a2, TASK_TI_CPU(tp) + /* +- * Compute the new_vmalloc element position: ++ * Compute the new_valid_map_cpus element position: + * (cpu / 64) * 8 = (cpu >> 6) << 3 + */ + srli a1, a2, 6 + slli a1, a1, 3 +- la a0, new_vmalloc ++ la a0, new_valid_map_cpus + add a0, a0, a1 + /* +- * Compute the bit position in the new_vmalloc element: ++ * Compute the bit position in the new_valid_map_cpus element: + * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6 + * = cpu - ((cpu >> 6) << 3) << 3 + */ +@@ -67,12 +67,12 @@ + li a2, 1 + sll a1, a2, a1 + +- /* Check the value of new_vmalloc for this cpu */ ++ /* Check the value of new_valid_map_cpus for this cpu */ + REG_L a2, 0(a0) + and a2, a2, a1 +- beq a2, zero, .Lnew_vmalloc_restore_context ++ beq a2, zero, .Lnew_valid_map_cpus_restore_context + +- /* Atomically reset the current cpu bit in new_vmalloc */ ++ /* Atomically reset the current cpu bit in new_valid_map_cpus */ + amoxor.d a0, a1, (a0) + + /* Only emit a sfence.vma if the uarch caches invalid entries */ +@@ -84,11 +84,11 @@ + csrw CSR_SCRATCH, x0 + sret + +-.Lnew_vmalloc_restore_context: ++.Lnew_valid_map_cpus_restore_context: + REG_L a2, TASK_TI_A2(tp) +-.Lnew_vmalloc_restore_context_a1: ++.Lnew_valid_map_cpus_restore_context_a1: + REG_L a1, TASK_TI_A1(tp) +-.Lnew_vmalloc_restore_context_a0: ++.Lnew_valid_map_cpus_restore_context_a0: + REG_L a0, TASK_TI_A0(tp) + .endm + +@@ -117,7 +117,7 @@ SYM_CODE_START(handle_exception) + * could "miss" the new mapping and traps: in that case, we only need + * to retry the access, no sfence.vma is required. + */ +- new_vmalloc_check ++ new_valid_map_cpus_check + #endif + + REG_S sp, TASK_TI_KERNEL_SP(tp) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 8f4e7e505906..750d3356683a 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,7 @@ + + #include "../kernel/head.h" + +-u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; ++u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch deleted file mode 100644 index 9d00d9a51f..0000000000 --- a/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0236a57f077395bd67012bf4e9d33ba23ecdedd5 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:49 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Unconditionally sfence.vma for - spurious fault - -Svvptc does not guarantee that it's safe to just return here. Since we -have already cleared our bit, if, theoretically, the bounded timeframe -for the accessed page to become valid still hasn't happened after sret, -we could fault again and actually crash. - -Hopefully, these spurious faults should be rare enough that this is an -acceptable slowdown. - -Cc: stable@vger.kernel.org -Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/kernel/entry.S | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index 4f88d3353b00..5639031d1437 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -75,8 +75,11 @@ - /* Atomically reset the current cpu bit in new_valid_map_cpus */ - amoxor.d a0, a1, (a0) - -- /* Only emit a sfence.vma if the uarch caches invalid entries */ -- ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) -+ /* -+ * A sfence.vma is required here. Even if we had Svvptc, there's no -+ * guarantee that after returning we wouldn't just fault again. -+ */ -+ sfence.vma - - REG_L a0, TASK_TI_A0(tp) - REG_L a1, TASK_TI_A1(tp) --- -2.53.0 - diff --git a/SPECS/linux-lts/0327-UPSTREAM-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux-lts/0327-UPSTREAM-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch new file mode 100644 index 0000000000..9237c38792 --- /dev/null +++ b/SPECS/linux-lts/0327-UPSTREAM-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch @@ -0,0 +1,63 @@ +From a587720a8231fc15d1bdddc06c3a527a6bb31177 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Use the bitmap API for + new_valid_map_cpus + +The bitmap was defined with incorrect size. Fix it by using the proper +bitmap API in C code. The corresponding assembly code is still okay and +remains unchanged. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-4-f80d8354d79d@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 26c171fc48539ac88d3697792b1fde9334af836c) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 8 +++----- + arch/riscv/mm/init.c | 2 +- + 2 files changed, 4 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 8c7a0ef2635a..8cfe59483a8f 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -41,19 +41,17 @@ do { \ + } while (0) + + #ifdef CONFIG_64BIT +-extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; ++/* This is accessed in assembly code. cpumask_var_t would be too complex. */ ++extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; + static inline void mark_new_valid_map(void) + { +- int i; +- + /* + * We don't care if concurrently a cpu resets this value since + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. + */ +- for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) +- new_valid_map_cpus[i] = -1ULL; ++ bitmap_fill(new_valid_map_cpus, NR_CPUS); + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 750d3356683a..6533cc17825a 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,7 @@ + + #include "../kernel/head.h" + +-u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; ++DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch deleted file mode 100644 index 113e960802..0000000000 --- a/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1bee6d3eac2cd34b39a8ce2c3e590aaf2f4f38f1 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 5 Mar 2026 01:00:51 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 PHY - support - -Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP -of USB2 PHY mostly shares the same functionalities with K1 SoC, while has -some register layout changes. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org -Signed-off-by: Han Gao ---- - .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -index 43eaca90d88c..18025e5f60d6 100644 ---- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -@@ -4,14 +4,16 @@ - $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 SoC USB 2.0 PHY -+title: SpacemiT K1/K3 SoC USB 2.0 PHY - - maintainers: - - Ze Huang - - properties: - compatible: -- const: spacemit,k1-usb2-phy -+ enum: -+ - spacemit,k1-usb2-phy -+ - spacemit,k3-usb2-phy - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0328-UPSTREAM-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux-lts/0328-UPSTREAM-riscv-mm-Unconditionally-sfence.vma-for-spu.patch new file mode 100644 index 0000000000..5292c92a0e --- /dev/null +++ b/SPECS/linux-lts/0328-UPSTREAM-riscv-mm-Unconditionally-sfence.vma-for-spu.patch @@ -0,0 +1,46 @@ +From ace153ba8b01ae0c26eebe767cf283497f23a6c4 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Unconditionally sfence.vma for + spurious fault + +Svvptc does not guarantee that it's safe to just return here. Since we +have already cleared our bit, if, theoretically, the bounded timeframe +for the accessed page to become valid still hasn't happened after sret, +we could fault again and actually crash. + +Hopefully, these spurious faults should be rare enough that this is an +acceptable slowdown. + +Cc: stable@vger.kernel.org +Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 1b2c6b56a9fa0dcbef461039937de22b1cbecc7d) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/entry.S | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 4f88d3353b00..5639031d1437 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -75,8 +75,11 @@ + /* Atomically reset the current cpu bit in new_valid_map_cpus */ + amoxor.d a0, a1, (a0) + +- /* Only emit a sfence.vma if the uarch caches invalid entries */ +- ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) ++ /* ++ * A sfence.vma is required here. Even if we had Svvptc, there's no ++ * guarantee that after returning we wouldn't just fault again. ++ */ ++ sfence.vma + + REG_L a0, TASK_TI_A0(tp) + REG_L a1, TASK_TI_A1(tp) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch deleted file mode 100644 index 309f8ea1b2..0000000000 --- a/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch +++ /dev/null @@ -1,109 +0,0 @@ -From e42b13b733fe6bf35801da4dd939e98421377976 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 5 Mar 2026 01:00:52 +0000 -Subject: [RUYI PATCH] FROMLIST: phy: k1-usb: k3: add USB2 PHY support - -Add USB2 PHY support for SpacemiT K3 SoC. - -Register layout of handling USB disconnect operation has been changed, -So introducing a platform data to distinguish the different SoCs. - -Reviewed-by: Yao Zi -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-2-15554fb933bc@kernel.org -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++----- - 1 file changed, 29 insertions(+), 5 deletions(-) - -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -index 9215d0b223b2..87b943d9111f 100644 ---- a/drivers/phy/spacemit/phy-k1-usb2.c -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -51,6 +51,9 @@ - #define PHY_K1_HS_HOST_DISC 0x40 - #define PHY_K1_HS_HOST_DISC_CLR BIT(0) - -+#define PHY_K3_HS_HOST_DISC 0x20 -+#define PHY_K3_HS_HOST_DISC_CLR BIT(8) -+ - #define PHY_PLL_DIV_CFG 0x98 - #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) - #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -@@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy) - return 0; - } - --static int spacemit_usb2phy_disconnect(struct phy *phy, int port) -+static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port) - { - struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); - -@@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port) - return 0; - } - --static const struct phy_ops spacemit_usb2phy_ops = { -+static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC, -+ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR); -+ -+ return 0; -+} -+ -+static const struct phy_ops spacemit_k1_usb2phy_ops = { - .init = spacemit_usb2phy_init, - .exit = spacemit_usb2phy_exit, -- .disconnect = spacemit_usb2phy_disconnect, -+ .disconnect = spacemit_k1_usb2phy_disconnect, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct phy_ops spacemit_k3_usb2phy_ops = { -+ .init = spacemit_usb2phy_init, -+ .exit = spacemit_usb2phy_exit, -+ .disconnect = spacemit_k3_usb2phy_disconnect, - .owner = THIS_MODULE, - }; - -@@ -167,12 +187,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct spacemit_usb2phy *sphy; -+ const struct phy_ops *ops; - void __iomem *base; - - sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); - if (!sphy) - return -ENOMEM; - -+ ops = device_get_match_data(dev); -+ - sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); - if (IS_ERR(sphy->clk)) - return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); -@@ -185,7 +208,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - if (IS_ERR(sphy->regmap_base)) - return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); - -- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); -+ sphy->phy = devm_phy_create(dev, NULL, ops); - if (IS_ERR(sphy->phy)) - return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); - -@@ -196,7 +219,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - } - - static const struct of_device_id spacemit_usb2phy_dt_match[] = { -- { .compatible = "spacemit,k1-usb2-phy", }, -+ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops }, -+ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0329-UPSTREAM-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux-lts/0329-UPSTREAM-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch new file mode 100644 index 0000000000..09ed31d943 --- /dev/null +++ b/SPECS/linux-lts/0329-UPSTREAM-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch @@ -0,0 +1,49 @@ +From 1c431753b9cfbc8886977e0bc6e1a1f1031cd8ca Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Sat, 6 Jun 2026 20:17:54 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: Define DIRECT_MAP_PHYSMEM_END + +On RISC-V, the actual mappable range of physical address space is +dependent on the current MMU mode i.e. satp_mode (See +Documentation/arch/riscv/vm-layout.rst). + +Define the DIRECT_MAP_PHYSMEM_END macro based on the existing virtual +address space layout macros to expose this information to +get_free_mem_region(). Otherwise, it returns a region that couldn't be +mapped, which breaks ZONE_DEVICE. + +Cc: stable@vger.kernel.org # v6.13+ +Tested-by: Han Gao # SG2044 +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260309-riscv-sparsemem-vmemmap-limits-v1-2-f40efe18e3cd@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit f3336b48cf9d3f2d1fc78e3289c0ded2f00876ee) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/pgtable.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 30d1ea93dde3..9b2e967c9fe0 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -93,6 +93,16 @@ + */ + #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) + ++/* Needed to limit get_free_mem_region() */ ++#if defined(CONFIG_FLATMEM) ++#define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) ++#elif defined(CONFIG_SPARSEMEM_VMEMMAP) ++#define DIRECT_MAP_PHYSMEM_END \ ++ ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) ++#elif defined(CONFIG_SPARSEMEM) ++/* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ ++#endif ++ + #define PCI_IO_SIZE SZ_16M + #define PCI_IO_END VMEMMAP_START + #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch deleted file mode 100644 index f84dd26276..0000000000 --- a/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 313a26d3fa86f65c2c9bcfdaa1d325594d4d3960 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Fri, 10 Apr 2026 15:58:22 +0800 -Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to - the allowlist - -The SpacemiT K1 SoC uses standard device tree based CPU frequency -scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. - -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-1-4e16b8c0f60e@mailbox.org -Signed-off-by: Han Gao ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c -index 47dd76acd31e..5c048d7351be 100644 ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = { - { .have_governor_per_policy = true, }, - }, - -+ { .compatible = "spacemit,k1", }, - { .compatible = "st-ericsson,u8500", }, - { .compatible = "st-ericsson,u8540", }, - { .compatible = "st-ericsson,u9500", }, --- -2.53.0 - diff --git a/SPECS/linux-lts/0330-UPSTREAM-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux-lts/0330-UPSTREAM-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch new file mode 100644 index 0000000000..15d1e94f44 --- /dev/null +++ b/SPECS/linux-lts/0330-UPSTREAM-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch @@ -0,0 +1,48 @@ +From 5b5b7926b1acc7efd8184d408f7f48ac6348b55c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 5 Mar 2026 01:00:51 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: k3: add USB2 PHY + support + +Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP +of USB2 PHY mostly shares the same functionalities with K1 SoC, while has +some register layout changes. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=c05cf9d274daf72dc7e433480cf2e0e888f6bd89 [1] +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=00b4fe5be06aecd6426930de86b7cffc2330f4b8 [2] +Link: https://patch.msgid.link/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit ad8fdebd40fd25e86331886f4fc6951531691319) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +index 43eaca90d88c..18025e5f60d6 100644 +--- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +@@ -4,14 +4,16 @@ + $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 SoC USB 2.0 PHY ++title: SpacemiT K1/K3 SoC USB 2.0 PHY + + maintainers: + - Ze Huang + + properties: + compatible: +- const: spacemit,k1-usb2-phy ++ enum: ++ - spacemit,k1-usb2-phy ++ - spacemit,k3-usb2-phy + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch deleted file mode 100644 index ab37eecf22..0000000000 --- a/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch +++ /dev/null @@ -1,264 +0,0 @@ -From 76023519e9da3b79768d23f7ffe1a08e230674bd Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Fri, 10 Apr 2026 15:58:23 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 - SoC - -Add Operating Performance Points (OPP) tables and CPU clock properties -for the two clusters in the SpacemiT K1 SoC. - -Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 -board to fully enable CPU DVFS. - -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- - arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ - 3 files changed, 147 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 9429189354d6..2a0caecd9a41 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -5,6 +5,7 @@ - - #include "k1.dtsi" - #include "k1-pinctrl.dtsi" -+#include "k1-opp.dtsi" - - / { - model = "Banana Pi BPI-F3"; -@@ -85,6 +86,38 @@ &combo_phy { - status = "okay"; - }; - -+&cpu_0 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_1 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_2 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_3 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_4 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_5 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_6 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_7 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ - &emmc { - bus-width = <8>; - mmc-hs400-1_8v; -@@ -200,7 +233,7 @@ pmic@41 { - dldoin2-supply = <&buck5>; - - regulators { -- buck1 { -+ buck1_3v45: buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi -new file mode 100644 -index 000000000000..768ae390686d ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi -@@ -0,0 +1,105 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/ { -+ cluster0_opp_table: opp-table-cluster0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-614400000 { -+ opp-hz = /bits/ 64 <614400000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-819000000 { -+ opp-hz = /bits/ 64 <819000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1228800000 { -+ opp-hz = /bits/ 64 <1228800000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <1050000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+ -+ cluster1_opp_table: opp-table-cluster1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-614400000 { -+ opp-hz = /bits/ 64 <614400000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-819000000 { -+ opp-hz = /bits/ 64 <819000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1228800000 { -+ opp-hz = /bits/ 64 <1228800000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <1050000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+}; -+ -+&cpu_0 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_1 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_2 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_3 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_4 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_5 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_6 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_7 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 2ed5cc24e505..aefdbbadc9ef 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -54,6 +54,7 @@ cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -84,6 +85,7 @@ cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -114,6 +116,7 @@ cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -144,6 +147,7 @@ cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -174,6 +178,7 @@ cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -204,6 +209,7 @@ cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -234,6 +240,7 @@ cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -264,6 +271,7 @@ cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", --- -2.53.0 - diff --git a/SPECS/linux-lts/0331-UPSTREAM-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux-lts/0331-UPSTREAM-phy-k1-usb-k3-add-USB2-PHY-support.patch new file mode 100644 index 0000000000..1706c58128 --- /dev/null +++ b/SPECS/linux-lts/0331-UPSTREAM-phy-k1-usb-k3-add-USB2-PHY-support.patch @@ -0,0 +1,114 @@ +From 7847fff353ab57df19db9c9f4b4610ae46dff156 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 5 Mar 2026 01:00:52 +0000 +Subject: [RUYI PATCH] UPSTREAM: phy: k1-usb: k3: add USB2 PHY support + +Add USB2 PHY support for SpacemiT K3 SoC. + +Register layout of handling USB disconnect operation has been changed, +So introducing a platform data to distinguish the different SoCs. + +Reviewed-by: Yao Zi +Signed-off-by: Yixun Lan +Reviewed-by: Neil Armstrong +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=c05cf9d274daf72dc7e433480cf2e0e888f6bd89 [1] +Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=00b4fe5be06aecd6426930de86b7cffc2330f4b8 [2] +Link: https://patch.msgid.link/20260305-11-k3-usb2-phy-v4-2-15554fb933bc@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit 056ee8b37bc91e3230afa11ec1018fa898b983b8) +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++----- + 1 file changed, 29 insertions(+), 5 deletions(-) + +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +index 9215d0b223b2..87b943d9111f 100644 +--- a/drivers/phy/spacemit/phy-k1-usb2.c ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -51,6 +51,9 @@ + #define PHY_K1_HS_HOST_DISC 0x40 + #define PHY_K1_HS_HOST_DISC_CLR BIT(0) + ++#define PHY_K3_HS_HOST_DISC 0x20 ++#define PHY_K3_HS_HOST_DISC_CLR BIT(8) ++ + #define PHY_PLL_DIV_CFG 0x98 + #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) + #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) +@@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy) + return 0; + } + +-static int spacemit_usb2phy_disconnect(struct phy *phy, int port) ++static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port) + { + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + +@@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port) + return 0; + } + +-static const struct phy_ops spacemit_usb2phy_ops = { ++static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC, ++ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR); ++ ++ return 0; ++} ++ ++static const struct phy_ops spacemit_k1_usb2phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, +- .disconnect = spacemit_usb2phy_disconnect, ++ .disconnect = spacemit_k1_usb2phy_disconnect, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops spacemit_k3_usb2phy_ops = { ++ .init = spacemit_usb2phy_init, ++ .exit = spacemit_usb2phy_exit, ++ .disconnect = spacemit_k3_usb2phy_disconnect, + .owner = THIS_MODULE, + }; + +@@ -167,12 +187,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct spacemit_usb2phy *sphy; ++ const struct phy_ops *ops; + void __iomem *base; + + sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); + if (!sphy) + return -ENOMEM; + ++ ops = device_get_match_data(dev); ++ + sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); + if (IS_ERR(sphy->clk)) + return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); +@@ -185,7 +208,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + if (IS_ERR(sphy->regmap_base)) + return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); + +- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); ++ sphy->phy = devm_phy_create(dev, NULL, ops); + if (IS_ERR(sphy->phy)) + return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); + +@@ -196,7 +219,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + } + + static const struct of_device_id spacemit_usb2phy_dt_match[] = { +- { .compatible = "spacemit,k1-usb2-phy", }, ++ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops }, ++ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch deleted file mode 100644 index a5d6058fa5..0000000000 --- a/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch +++ /dev/null @@ -1,47 +0,0 @@ -From b71c8252ef37bceafb077b1ac8b79eb81f094356 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 9 Mar 2026 19:09:38 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END - -On RISC-V, the actual mappable range of physical address space is -dependent on the current MMU mode i.e. satp_mode (See -Documentation/arch/riscv/vm-layout.rst). - -Define the DIRECT_MAP_PHYSMEM_END macro based on the existing virtual -address space layout macros to expose this information to -get_free_mem_region(). Otherwise, it returns a region that couldn't be -mapped, which breaks ZONE_DEVICE. - -Cc: stable@vger.kernel.org # v6.13+ -Tested-by: Han Gao # SG2044 -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260309-riscv-sparsemem-vmemmap-limits-v1-2-f40efe18e3cd@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/pgtable.h | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h -index 30d1ea93dde3..9b2e967c9fe0 100644 ---- a/arch/riscv/include/asm/pgtable.h -+++ b/arch/riscv/include/asm/pgtable.h -@@ -93,6 +93,16 @@ - */ - #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) - -+/* Needed to limit get_free_mem_region() */ -+#if defined(CONFIG_FLATMEM) -+#define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) -+#elif defined(CONFIG_SPARSEMEM_VMEMMAP) -+#define DIRECT_MAP_PHYSMEM_END \ -+ ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) -+#elif defined(CONFIG_SPARSEMEM) -+/* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ -+#endif -+ - #define PCI_IO_SIZE SZ_16M - #define PCI_IO_END VMEMMAP_START - #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) --- -2.53.0 - diff --git a/SPECS/linux-lts/0332-UPSTREAM-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux-lts/0332-UPSTREAM-drm-verisilicon-add-max-cursor-size-to-HWDB.patch new file mode 100644 index 0000000000..d96de5f89a --- /dev/null +++ b/SPECS/linux-lts/0332-UPSTREAM-drm-verisilicon-add-max-cursor-size-to-HWDB.patch @@ -0,0 +1,79 @@ +From 74b04b4bce07d610a797bf8a9e01aa04cc395d49 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 01:56:09 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add max cursor size to HWDB + +Different display controller variants support different maximum cursor +size. All known DC8200 variants support both 32x32 and 64x64, but some +DC8000 variants support either only 32x32 or up to 256x256. + +The minimum size is fixed at 32 and only PoT square sizes are supported. + +Add the max cursor size field to HWDB and fill all entries with 64. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Thomas Zimmermann +Reviewed-by: Dmitry Baryshkov +Link: https://patch.msgid.link/20260506175610.2542888-2-zhengxingda@iscas.ac.cn +(cherry picked from commit 9637867d78a7bc5e76b17fe6cb0be5e054fce973) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 ++++ + drivers/gpu/drm/verisilicon/vs_hwdb.h | 5 +++++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c +index 09336af0900a..2a0f7c59afa3 100644 +--- a/drivers/gpu/drm/verisilicon/vs_hwdb.c ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c +@@ -95,6 +95,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = ~0U, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + { +@@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x30B, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + { +@@ -111,6 +113,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x310, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_with_yuv444, + }, + { +@@ -119,6 +122,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x311, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + }; +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h +index 92192e4fa086..2065ecb73043 100644 +--- a/drivers/gpu/drm/verisilicon/vs_hwdb.h ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h +@@ -20,6 +20,11 @@ struct vs_chip_identity { + u32 customer_id; + + u32 display_count; ++ /* ++ * The hardware only supports square cursor planes, so this field ++ * is both the maximum width and height in pixels. ++ */ ++ int32_t max_cursor_size; + const struct vs_formats *formats; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch deleted file mode 100644 index 3cac36fd67..0000000000 --- a/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 3d54bf791cf5017cc96bc5222094dc98fb50e585 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 01:56:09 +0800 -Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add max cursor size to HWDB - -Different display controller variants support different maximum cursor -size. All known DC8200 variants support both 32x32 and 64x64, but some -DC8000 variants support either only 32x32 or up to 256x256. - -The minimum size is fixed at 32 and only PoT square sizes are supported. - -Add the max cursor size field to HWDB and fill all entries with 64. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Thomas Zimmermann -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20260506175610.2542888-2-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 ++++ - drivers/gpu/drm/verisilicon/vs_hwdb.h | 5 +++++ - 2 files changed, 9 insertions(+) - -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c -index 09336af0900a..2a0f7c59afa3 100644 ---- a/drivers/gpu/drm/verisilicon/vs_hwdb.c -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c -@@ -95,6 +95,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = ~0U, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - { -@@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x30B, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - { -@@ -111,6 +113,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x310, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_with_yuv444, - }, - { -@@ -119,6 +122,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x311, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - }; -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h -index 92192e4fa086..2065ecb73043 100644 ---- a/drivers/gpu/drm/verisilicon/vs_hwdb.h -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h -@@ -20,6 +20,11 @@ struct vs_chip_identity { - u32 customer_id; - - u32 display_count; -+ /* -+ * The hardware only supports square cursor planes, so this field -+ * is both the maximum width and height in pixels. -+ */ -+ int32_t max_cursor_size; - const struct vs_formats *formats; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0333-UPSTREAM-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux-lts/0333-UPSTREAM-drm-verisilicon-add-support-for-cursor-plan.patch new file mode 100644 index 0000000000..1bfbc1c42d --- /dev/null +++ b/SPECS/linux-lts/0333-UPSTREAM-drm-verisilicon-add-support-for-cursor-plan.patch @@ -0,0 +1,412 @@ +From 36a43bb417a3853fa8c3f3571cedd82e1b464bc6 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 01:56:10 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add support for cursor + planes + +Verisilicon display controllers support hardware cursors per output +port. + +Add support for them as cursor planes. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Thomas Zimmermann +Reviewed-by: Dmitry Baryshkov +Link: https://patch.msgid.link/20260506175610.2542888-3-zhengxingda@iscas.ac.cn +(cherry picked from commit 8c4ae218912554ef427440293cdb97319d17ca5d) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/verisilicon/Makefile | 3 +- + drivers/gpu/drm/verisilicon/vs_crtc.c | 11 +- + drivers/gpu/drm/verisilicon/vs_cursor_plane.c | 272 ++++++++++++++++++ + .../drm/verisilicon/vs_cursor_plane_regs.h | 44 +++ + drivers/gpu/drm/verisilicon/vs_plane.h | 1 + + 5 files changed, 328 insertions(+), 3 deletions(-) + create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index fd8d805fbcde..426f4bcaa834 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o ++verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ ++ vs_plane.o vs_primary_plane.o vs_cursor_plane.o + + obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c +index f49401713000..5c9714a3e69a 100644 +--- a/drivers/gpu/drm/verisilicon/vs_crtc.c ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.c +@@ -159,7 +159,7 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + unsigned int output) + { + struct vs_crtc *vcrtc; +- struct drm_plane *primary; ++ struct drm_plane *primary, *cursor; + int ret; + + vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); +@@ -175,9 +175,16 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + return ERR_PTR(PTR_ERR(primary)); + } + ++ /* Create our cursor plane */ ++ cursor = vs_cursor_plane_init(drm_dev, dc); ++ if (IS_ERR(cursor)) { ++ drm_err(drm_dev, "Couldn't create the cursor plane\n"); ++ return ERR_CAST(cursor); ++ } ++ + ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, + primary, +- NULL, ++ cursor, + &vs_crtc_funcs, + NULL); + if (ret) { +diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane.c b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c +new file mode 100644 +index 000000000000..acb9854fa67e +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c +@@ -0,0 +1,272 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) ++ * ++ * Authors: ++ * Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_plane.h" ++#include "vs_dc.h" ++#include "vs_hwdb.h" ++#include "vs_cursor_plane_regs.h" ++ ++#define VSDC_MIN_CURSOR_SIZE 32 ++#define VSDC_MAX_CURSOR_SIZE 256 ++ ++#define VSDC_CURSOR_LOCATION_MAX_POSITIVE BIT_MASK(15) ++#define VSDC_CURSOR_LOCATION_MAX_NEGATIVE BIT_MASK(5) ++ ++static bool vs_cursor_plane_check_coord(int32_t coord) ++{ ++ if (coord >= 0) ++ return coord <= VSDC_CURSOR_LOCATION_MAX_POSITIVE; ++ else ++ return (-coord) <= VSDC_CURSOR_LOCATION_MAX_NEGATIVE; ++} ++ ++static int vs_cursor_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct drm_framebuffer *fb = new_plane_state->fb; ++ struct drm_crtc_state *crtc_state = NULL; ++ struct vs_crtc *vcrtc; ++ struct vs_dc *dc; ++ int ret; ++ ++ if (crtc) ++ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); ++ ++ ret = drm_atomic_helper_check_plane_state(new_plane_state, ++ crtc_state, ++ DRM_PLANE_NO_SCALING, ++ DRM_PLANE_NO_SCALING, ++ true, true); ++ if (ret) ++ return ret; ++ ++ if (!new_plane_state->visible) ++ return 0; /* Skip validity check */ ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ dc = vcrtc->dc; ++ ++ /* Only certain PoT square sizes is supported. */ ++ if (!is_power_of_2(new_plane_state->crtc_w) || ++ new_plane_state->crtc_w < VSDC_MIN_CURSOR_SIZE || ++ new_plane_state->crtc_w > dc->identity.max_cursor_size) ++ return -EINVAL; ++ ++ if (new_plane_state->crtc_w != new_plane_state->crtc_h) ++ return -EINVAL; ++ ++ /* Check if the cursor is inside the register fields' range */ ++ if (!vs_cursor_plane_check_coord(new_plane_state->crtc_x) || ++ !vs_cursor_plane_check_coord(new_plane_state->crtc_y)) ++ return -EINVAL; ++ ++ /* Extra line padding isn't supported */ ++ if (fb->pitches[0] != ++ drm_format_info_min_pitch(fb->format, 0, new_plane_state->crtc_w)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) ++{ ++ regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_COMMIT | ++ VSDC_CURSOR_CONFIG_IMG_UPDATE); ++} ++ ++static void vs_cursor_plane_atomic_enable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_FMT_MASK, ++ VSDC_CURSOR_CONFIG_FMT_ARGB8888); ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static void vs_cursor_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_FMT_MASK, ++ VSDC_CURSOR_CONFIG_FMT_OFF); ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static void vs_cursor_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_framebuffer *fb = state->fb; ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_dc *dc; ++ struct vs_crtc *vcrtc; ++ unsigned int output; ++ dma_addr_t dma_addr; ++ ++ if (!state->visible) { ++ vs_cursor_plane_atomic_disable(plane, atomic_state); ++ return; ++ } ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ output = vcrtc->id; ++ dc = vcrtc->dc; ++ ++ /* Other sizes should be rejected by atomic_check */ ++ switch (state->crtc_w) { ++ case 32: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_32); ++ break; ++ case 64: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_64); ++ break; ++ case 128: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_128); ++ break; ++ case 256: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_256); ++ break; ++ } ++ ++ dma_addr = vs_fb_get_dma_addr(fb, &state->src); ++ ++ regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output), ++ lower_32_bits(dma_addr)); ++ ++ /* ++ * The X_OFF and Y_OFF fields define which point does the LOCATION ++ * register represent in the cursor image, and LOCATION register ++ * values are unsigned. To for positive left-top coordinates the ++ * offset is set to 0 and the location is set to the coordinate, for ++ * negative coordinates the location is set to 0 and the offset ++ * is set to the opposite number of the coordinate to offset the ++ * cursor image partly off-screen. ++ */ ++ if (state->crtc_x >= 0) { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_X_OFF_MASK, 0); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_X_MASK, ++ VSDC_CURSOR_LOCATION_X(state->crtc_x)); ++ } else { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_X_OFF_MASK, ++ -state->crtc_x); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_X_MASK, 0); ++ } ++ ++ if (state->crtc_y >= 0) { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_Y_OFF_MASK, 0); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_Y_MASK, ++ VSDC_CURSOR_LOCATION_Y(state->crtc_y)); ++ } else { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_Y_OFF_MASK, ++ -state->crtc_y); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_Y_MASK, 0); ++ } ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static const struct drm_plane_helper_funcs vs_cursor_plane_helper_funcs = { ++ .atomic_check = vs_cursor_plane_atomic_check, ++ .atomic_update = vs_cursor_plane_atomic_update, ++ .atomic_enable = vs_cursor_plane_atomic_enable, ++ .atomic_disable = vs_cursor_plane_atomic_disable, ++}; ++ ++static const struct drm_plane_funcs vs_cursor_plane_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .reset = drm_atomic_helper_plane_reset, ++ .update_plane = drm_atomic_helper_update_plane, ++}; ++ ++static const u32 vs_cursor_plane_formats[] = { ++ DRM_FORMAT_ARGB8888, ++}; ++ ++static const u64 vs_cursor_plane_modifiers[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ DRM_FORMAT_MOD_INVALID, /* sentinel */ ++}; ++ ++struct drm_plane *vs_cursor_plane_init(struct drm_device *drm_dev, ++ struct vs_dc *dc) ++{ ++ int32_t max_cursor_size = dc->identity.max_cursor_size; ++ struct drm_plane *plane; ++ ++ if (drm_WARN_ON_ONCE(drm_dev, max_cursor_size < VSDC_MIN_CURSOR_SIZE || ++ max_cursor_size > VSDC_MAX_CURSOR_SIZE)) ++ return ERR_PTR(-EINVAL); ++ ++ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, ++ &vs_cursor_plane_funcs, ++ vs_cursor_plane_formats, ++ ARRAY_SIZE(vs_cursor_plane_formats), ++ vs_cursor_plane_modifiers, ++ DRM_PLANE_TYPE_CURSOR, ++ NULL); ++ ++ if (IS_ERR(plane)) ++ return plane; ++ ++ drm_plane_helper_add(plane, &vs_cursor_plane_helper_funcs); ++ ++ return plane; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h +new file mode 100644 +index 000000000000..99693f2c95b9 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h +@@ -0,0 +1,44 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_CURSOR_PLANE_REGS_H_ ++#define _VS_CURSOR_PLANE_REGS_H_ ++ ++#include ++ ++#define VSDC_CURSOR_CONFIG(n) (0x1468 + 0x1080 * (n)) ++#define VSDC_CURSOR_CONFIG_FMT_MASK GENMASK(1, 0) ++#define VSDC_CURSOR_CONFIG_FMT_ARGB8888 (0x2 << 0) ++#define VSDC_CURSOR_CONFIG_FMT_OFF (0x0 << 0) ++#define VSDC_CURSOR_CONFIG_IMG_UPDATE BIT(2) ++#define VSDC_CURSOR_CONFIG_COMMIT BIT(3) ++#define VSDC_CURSOR_CONFIG_SIZE_MASK GENMASK(7, 5) ++#define VSDC_CURSOR_CONFIG_SIZE_32 (0x0 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_64 (0x1 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_128 (0x2 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_256 (0x3 << 5) ++#define VSDC_CURSOR_CONFIG_Y_OFF_MASK GENMASK(12, 8) ++#define VSDC_CURSOR_CONFIG_Y_OFF(v) ((v) << 8) ++#define VSDC_CURSOR_CONFIG_X_OFF_MASK GENMASK(20, 16) ++#define VSDC_CURSOR_CONFIG_X_OFF(v) ((v) << 16) ++ ++#define VSDC_CURSOR_ADDRESS(n) (0x146C + 0x1080 * (n)) ++ ++#define VSDC_CURSOR_LOCATION(n) (0x1470 + 0x1080 * (n)) ++#define VSDC_CURSOR_LOCATION_X_MASK GENMASK(14, 0) ++#define VSDC_CURSOR_LOCATION_X(v) ((v) << 0) ++#define VSDC_CURSOR_LOCATION_Y_MASK GENMASK(30, 16) ++#define VSDC_CURSOR_LOCATION_Y(v) ((v) << 16) ++ ++#define VSDC_CURSOR_BACKGROUND(n) (0x1474 + 0x1080 * (n)) ++#define VSDC_CURSOR_BACKGRUOND_DEFAULT 0x00FFFFFF ++ ++#define VSDC_CURSOR_FOREGROUND(n) (0x1478 + 0x1080 * (n)) ++#define VSDC_CURSOR_FOREGRUOND_DEFAULT 0x00AAAAAA ++ ++#endif /* _VS_CURSOR_PLANE_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h +index 41875ea3d66a..60b5b3a1bc22 100644 +--- a/drivers/gpu/drm/verisilicon/vs_plane.h ++++ b/drivers/gpu/drm/verisilicon/vs_plane.h +@@ -68,5 +68,6 @@ dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, + const struct drm_rect *src_rect); + + struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); ++struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc); + + #endif /* _VS_PLANE_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch deleted file mode 100644 index 0430f73844..0000000000 --- a/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch +++ /dev/null @@ -1,411 +0,0 @@ -From 5b2cb452135b05fe65a5440fa7f2e39d9b28d5f3 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 01:56:10 +0800 -Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add support for cursor - planes - -Verisilicon display controllers support hardware cursors per output -port. - -Add support for them as cursor planes. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Thomas Zimmermann -Link: https://lore.kernel.org/r/20260506175610.2542888-3-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/gpu/drm/verisilicon/Makefile | 3 +- - drivers/gpu/drm/verisilicon/vs_crtc.c | 11 +- - drivers/gpu/drm/verisilicon/vs_cursor_plane.c | 272 ++++++++++++++++++ - .../drm/verisilicon/vs_cursor_plane_regs.h | 44 +++ - drivers/gpu/drm/verisilicon/vs_plane.h | 1 + - 5 files changed, 328 insertions(+), 3 deletions(-) - create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h - -diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile -index fd8d805fbcde..426f4bcaa834 100644 ---- a/drivers/gpu/drm/verisilicon/Makefile -+++ b/drivers/gpu/drm/verisilicon/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0-only - --verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o -+verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ -+ vs_plane.o vs_primary_plane.o vs_cursor_plane.o - - obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c -index f49401713000..5c9714a3e69a 100644 ---- a/drivers/gpu/drm/verisilicon/vs_crtc.c -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.c -@@ -159,7 +159,7 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, - unsigned int output) - { - struct vs_crtc *vcrtc; -- struct drm_plane *primary; -+ struct drm_plane *primary, *cursor; - int ret; - - vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); -@@ -175,9 +175,16 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, - return ERR_PTR(PTR_ERR(primary)); - } - -+ /* Create our cursor plane */ -+ cursor = vs_cursor_plane_init(drm_dev, dc); -+ if (IS_ERR(cursor)) { -+ drm_err(drm_dev, "Couldn't create the cursor plane\n"); -+ return ERR_CAST(cursor); -+ } -+ - ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, - primary, -- NULL, -+ cursor, - &vs_crtc_funcs, - NULL); - if (ret) { -diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane.c b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c -new file mode 100644 -index 000000000000..acb9854fa67e ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c -@@ -0,0 +1,272 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) -+ * -+ * Authors: -+ * Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_plane.h" -+#include "vs_dc.h" -+#include "vs_hwdb.h" -+#include "vs_cursor_plane_regs.h" -+ -+#define VSDC_MIN_CURSOR_SIZE 32 -+#define VSDC_MAX_CURSOR_SIZE 256 -+ -+#define VSDC_CURSOR_LOCATION_MAX_POSITIVE BIT_MASK(15) -+#define VSDC_CURSOR_LOCATION_MAX_NEGATIVE BIT_MASK(5) -+ -+static bool vs_cursor_plane_check_coord(int32_t coord) -+{ -+ if (coord >= 0) -+ return coord <= VSDC_CURSOR_LOCATION_MAX_POSITIVE; -+ else -+ return (-coord) <= VSDC_CURSOR_LOCATION_MAX_NEGATIVE; -+} -+ -+static int vs_cursor_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc *crtc = new_plane_state->crtc; -+ struct drm_framebuffer *fb = new_plane_state->fb; -+ struct drm_crtc_state *crtc_state = NULL; -+ struct vs_crtc *vcrtc; -+ struct vs_dc *dc; -+ int ret; -+ -+ if (crtc) -+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ -+ ret = drm_atomic_helper_check_plane_state(new_plane_state, -+ crtc_state, -+ DRM_PLANE_NO_SCALING, -+ DRM_PLANE_NO_SCALING, -+ true, true); -+ if (ret) -+ return ret; -+ -+ if (!new_plane_state->visible) -+ return 0; /* Skip validity check */ -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ dc = vcrtc->dc; -+ -+ /* Only certain PoT square sizes is supported. */ -+ if (!is_power_of_2(new_plane_state->crtc_w) || -+ new_plane_state->crtc_w < VSDC_MIN_CURSOR_SIZE || -+ new_plane_state->crtc_w > dc->identity.max_cursor_size) -+ return -EINVAL; -+ -+ if (new_plane_state->crtc_w != new_plane_state->crtc_h) -+ return -EINVAL; -+ -+ /* Check if the cursor is inside the register fields' range */ -+ if (!vs_cursor_plane_check_coord(new_plane_state->crtc_x) || -+ !vs_cursor_plane_check_coord(new_plane_state->crtc_y)) -+ return -EINVAL; -+ -+ /* Extra line padding isn't supported */ -+ if (fb->pitches[0] != -+ drm_format_info_min_pitch(fb->format, 0, new_plane_state->crtc_w)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) -+{ -+ regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_COMMIT | -+ VSDC_CURSOR_CONFIG_IMG_UPDATE); -+} -+ -+static void vs_cursor_plane_atomic_enable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_FMT_MASK, -+ VSDC_CURSOR_CONFIG_FMT_ARGB8888); -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static void vs_cursor_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_FMT_MASK, -+ VSDC_CURSOR_CONFIG_FMT_OFF); -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static void vs_cursor_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_framebuffer *fb = state->fb; -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_dc *dc; -+ struct vs_crtc *vcrtc; -+ unsigned int output; -+ dma_addr_t dma_addr; -+ -+ if (!state->visible) { -+ vs_cursor_plane_atomic_disable(plane, atomic_state); -+ return; -+ } -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ output = vcrtc->id; -+ dc = vcrtc->dc; -+ -+ /* Other sizes should be rejected by atomic_check */ -+ switch (state->crtc_w) { -+ case 32: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_32); -+ break; -+ case 64: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_64); -+ break; -+ case 128: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_128); -+ break; -+ case 256: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_256); -+ break; -+ } -+ -+ dma_addr = vs_fb_get_dma_addr(fb, &state->src); -+ -+ regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output), -+ lower_32_bits(dma_addr)); -+ -+ /* -+ * The X_OFF and Y_OFF fields define which point does the LOCATION -+ * register represent in the cursor image, and LOCATION register -+ * values are unsigned. To for positive left-top coordinates the -+ * offset is set to 0 and the location is set to the coordinate, for -+ * negative coordinates the location is set to 0 and the offset -+ * is set to the opposite number of the coordinate to offset the -+ * cursor image partly off-screen. -+ */ -+ if (state->crtc_x >= 0) { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_X_OFF_MASK, 0); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_X_MASK, -+ VSDC_CURSOR_LOCATION_X(state->crtc_x)); -+ } else { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_X_OFF_MASK, -+ -state->crtc_x); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_X_MASK, 0); -+ } -+ -+ if (state->crtc_y >= 0) { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_Y_OFF_MASK, 0); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_Y_MASK, -+ VSDC_CURSOR_LOCATION_Y(state->crtc_y)); -+ } else { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_Y_OFF_MASK, -+ -state->crtc_y); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_Y_MASK, 0); -+ } -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static const struct drm_plane_helper_funcs vs_cursor_plane_helper_funcs = { -+ .atomic_check = vs_cursor_plane_atomic_check, -+ .atomic_update = vs_cursor_plane_atomic_update, -+ .atomic_enable = vs_cursor_plane_atomic_enable, -+ .atomic_disable = vs_cursor_plane_atomic_disable, -+}; -+ -+static const struct drm_plane_funcs vs_cursor_plane_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .reset = drm_atomic_helper_plane_reset, -+ .update_plane = drm_atomic_helper_update_plane, -+}; -+ -+static const u32 vs_cursor_plane_formats[] = { -+ DRM_FORMAT_ARGB8888, -+}; -+ -+static const u64 vs_cursor_plane_modifiers[] = { -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID, /* sentinel */ -+}; -+ -+struct drm_plane *vs_cursor_plane_init(struct drm_device *drm_dev, -+ struct vs_dc *dc) -+{ -+ int32_t max_cursor_size = dc->identity.max_cursor_size; -+ struct drm_plane *plane; -+ -+ if (drm_WARN_ON_ONCE(drm_dev, max_cursor_size < VSDC_MIN_CURSOR_SIZE || -+ max_cursor_size > VSDC_MAX_CURSOR_SIZE)) -+ return ERR_PTR(-EINVAL); -+ -+ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, -+ &vs_cursor_plane_funcs, -+ vs_cursor_plane_formats, -+ ARRAY_SIZE(vs_cursor_plane_formats), -+ vs_cursor_plane_modifiers, -+ DRM_PLANE_TYPE_CURSOR, -+ NULL); -+ -+ if (IS_ERR(plane)) -+ return plane; -+ -+ drm_plane_helper_add(plane, &vs_cursor_plane_helper_funcs); -+ -+ return plane; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h -new file mode 100644 -index 000000000000..99693f2c95b9 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_CURSOR_PLANE_REGS_H_ -+#define _VS_CURSOR_PLANE_REGS_H_ -+ -+#include -+ -+#define VSDC_CURSOR_CONFIG(n) (0x1468 + 0x1080 * (n)) -+#define VSDC_CURSOR_CONFIG_FMT_MASK GENMASK(1, 0) -+#define VSDC_CURSOR_CONFIG_FMT_ARGB8888 (0x2 << 0) -+#define VSDC_CURSOR_CONFIG_FMT_OFF (0x0 << 0) -+#define VSDC_CURSOR_CONFIG_IMG_UPDATE BIT(2) -+#define VSDC_CURSOR_CONFIG_COMMIT BIT(3) -+#define VSDC_CURSOR_CONFIG_SIZE_MASK GENMASK(7, 5) -+#define VSDC_CURSOR_CONFIG_SIZE_32 (0x0 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_64 (0x1 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_128 (0x2 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_256 (0x3 << 5) -+#define VSDC_CURSOR_CONFIG_Y_OFF_MASK GENMASK(12, 8) -+#define VSDC_CURSOR_CONFIG_Y_OFF(v) ((v) << 8) -+#define VSDC_CURSOR_CONFIG_X_OFF_MASK GENMASK(20, 16) -+#define VSDC_CURSOR_CONFIG_X_OFF(v) ((v) << 16) -+ -+#define VSDC_CURSOR_ADDRESS(n) (0x146C + 0x1080 * (n)) -+ -+#define VSDC_CURSOR_LOCATION(n) (0x1470 + 0x1080 * (n)) -+#define VSDC_CURSOR_LOCATION_X_MASK GENMASK(14, 0) -+#define VSDC_CURSOR_LOCATION_X(v) ((v) << 0) -+#define VSDC_CURSOR_LOCATION_Y_MASK GENMASK(30, 16) -+#define VSDC_CURSOR_LOCATION_Y(v) ((v) << 16) -+ -+#define VSDC_CURSOR_BACKGROUND(n) (0x1474 + 0x1080 * (n)) -+#define VSDC_CURSOR_BACKGRUOND_DEFAULT 0x00FFFFFF -+ -+#define VSDC_CURSOR_FOREGROUND(n) (0x1478 + 0x1080 * (n)) -+#define VSDC_CURSOR_FOREGRUOND_DEFAULT 0x00AAAAAA -+ -+#endif /* _VS_CURSOR_PLANE_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h -index 41875ea3d66a..60b5b3a1bc22 100644 ---- a/drivers/gpu/drm/verisilicon/vs_plane.h -+++ b/drivers/gpu/drm/verisilicon/vs_plane.h -@@ -68,5 +68,6 @@ dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, - const struct drm_rect *src_rect); - - struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); -+struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc); - - #endif /* _VS_PLANE_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0334-UPSTREAM-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux-lts/0334-UPSTREAM-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch new file mode 100644 index 0000000000..577d5107c8 --- /dev/null +++ b/SPECS/linux-lts/0334-UPSTREAM-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch @@ -0,0 +1,123 @@ +From f4c857da03891f845d2a43cc281ced8a1b20550c Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 27 Apr 2026 09:32:11 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: PCI: Add UltraRISC DP1000 PCIe + controller + +Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. + +Signed-off-by: Jia Wang +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: squash MAINTAINERS to driver commit update to touch only once] +Signed-off-by: Bjorn Helgaas +Reviewed-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com +(cherry picked from commit d9ff07f459552eabd04f8831bcaa76d761dfe264) +Signed-off-by: Han Gao +--- + .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++++++++++ + 1 file changed, 93 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +new file mode 100644 +index 000000000000..512b935bf5d1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +@@ -0,0 +1,93 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: UltraRISC DP1000 PCIe Host Controller ++ ++description: ++ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. ++ ++maintainers: ++ - Xincheng Zhang ++ - Jia Wang ++ ++allOf: ++ - $ref: /schemas/pci/snps,dw-pcie.yaml# ++ ++properties: ++ compatible: ++ const: ultrarisc,dp1000-pcie ++ ++ reg: ++ items: ++ - description: Data Bus Interface (DBI) registers. ++ - description: PCIe configuration space region. ++ ++ reg-names: ++ items: ++ - const: dbi ++ - const: config ++ ++ num-lanes: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [4, 16] ++ description: Number of lanes to use. ++ ++ interrupts: ++ items: ++ - description: MSI interrupt ++ - description: Legacy INTA interrupt ++ - description: Legacy INTB interrupt ++ - description: Legacy INTC interrupt ++ - description: Legacy INTD interrupt ++ ++ interrupt-names: ++ items: ++ - const: msi ++ - const: inta ++ - const: intb ++ - const: intc ++ - const: intd ++ ++required: ++ - compatible ++ - reg ++ - reg-names ++ - interrupts ++ - interrupt-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie@21000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x21000000 0x0 0x01000000>, ++ <0x0 0x4fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch deleted file mode 100644 index 6d1f390fdf..0000000000 --- a/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 7670121cc9020d50b0705929db01a06e18578be0 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 27 Apr 2026 09:32:10 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: add UltraRISC SoC family Kconfig - support - -The first SoC in the UltraRISC series is UR-DP1000, containing octa -UltraRISC CP100 cores. - -Signed-off-by: Jia Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig.socs | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs -index 848e7149e443..98c70e2ae958 100644 ---- a/arch/riscv/Kconfig.socs -+++ b/arch/riscv/Kconfig.socs -@@ -71,6 +71,12 @@ config ARCH_THEAD - help - This enables support for the RISC-V based T-HEAD SoCs. - -+config ARCH_ULTRARISC -+ bool "UltraRISC RISC-V SoCs" -+ help -+ This enables support for UltraRISC SoC platform hardware, -+ including boards based on the UR-DP1000. -+ - config ARCH_VIRT - bool "QEMU Virt Machine" - select POWER_RESET --- -2.53.0 - diff --git a/SPECS/linux-lts/0335-UPSTREAM-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux-lts/0335-UPSTREAM-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch new file mode 100644 index 0000000000..cdd26c8e81 --- /dev/null +++ b/SPECS/linux-lts/0335-UPSTREAM-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch @@ -0,0 +1,307 @@ +From c76fc49d8b4f1f718bd742fe3ede9b1c0a88bdd2 Mon Sep 17 00:00:00 2001 +From: Xincheng Zhang +Date: Mon, 27 Apr 2026 09:32:12 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root + Complex driver + +Add DP1000 SoC PCIe Root Complex driver. + +The controller only supports 32-bit aligned configuration space accesses. + +Signed-off-by: Xincheng Zhang +Signed-off-by: Jia Wang +[mani: changed to builtin_platform_driver() to prevent irqchip removal] +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: squash MAINTAINERS update here] +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com +(cherry picked from commit 5fc35740c3b32d2c820c97d041282e7bca4ad0bf) +Signed-off-by: Han Gao +--- + MAINTAINERS | 8 + + drivers/pci/controller/dwc/Kconfig | 13 ++ + drivers/pci/controller/dwc/Makefile | 1 + + drivers/pci/controller/dwc/pcie-designware.h | 24 +++ + drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++ + 5 files changed, 221 insertions(+) + create mode 100644 drivers/pci/controller/dwc/pcie-ultrarisc.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 1509fa6ab229..996aa3d41e95 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -20076,6 +20076,14 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + F: drivers/pci/controller/plda/pcie-starfive.c + ++PCIE DRIVER FOR ULTRARISC DP1000 ++M: Xincheng Zhang ++M: Jia Wang ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml ++F: drivers/pci/controller/dwc/pcie-ultrarisc.c ++ + PCIE ENDPOINT DRIVER FOR QUALCOMM + M: Manivannan Sadhasivam + L: linux-pci@vger.kernel.org +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index 718bb54e943f..af024a18621d 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -531,4 +531,17 @@ config PCIE_VISCONTI_HOST + Say Y here if you want PCIe controller support on Toshiba Visconti SoC. + This driver supports TMPV7708 SoC. + ++config PCIE_ULTRARISC ++ tristate "UltraRISC PCIe host controller" ++ depends on ARCH_ULTRARISC || COMPILE_TEST ++ select PCIE_DW_HOST ++ select PCI_MSI ++ default y if ARCH_ULTRARISC ++ help ++ Enables support for the PCIe controller in the UltraRISC SoC. ++ This driver supports UR-DP1000 SoC. ++ ++ By default, this symbol is enabled when ARCH_ULTRARISC is active, ++ requiring no further configuration on that platform. ++ + endmenu +diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile +index 662b0a219ddc..39087e7a06d5 100644 +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -34,6 +34,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o + obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o + obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o + obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o ++obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o + + # The following drivers are for devices that use the generic ACPI + # pci_root.c driver but don't support standard ECAM config access. +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index 295e113189b7..535964be5ac3 100644 +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -71,6 +71,8 @@ + + /* Synopsys-specific PCIe configuration registers */ + #define PCIE_PORT_FORCE 0x708 ++/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ ++#define PORT_LINK_NUM_MASK GENMASK(7, 0) + #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) + + #define PCIE_PORT_AFR 0x70C +@@ -98,6 +100,28 @@ + #define PCIE_PORT_LANE_SKEW 0x714 + #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) + ++/* ++ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number ++ * Register. ++ * ++ * This register holds the ack frequency, latency, replay, fast link ++ * scaling timers, and max function number values. ++ * ++ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. ++ * 0x0 (SF_1024): Scaling Factor is 1024 (1ms is 1us). ++ * When the LTSSM is in Config or L12 Entry State, 1ms ++ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. ++ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) ++ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) ++ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) ++ */ ++#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 ++#define PORT_FLT_SF_MASK GENMASK(30, 29) ++#define PORT_FLT_SF_VAL_1024 0x0 ++#define PORT_FLT_SF_VAL_256 0x1 ++#define PORT_FLT_SF_VAL_64 0x2 ++#define PORT_FLT_SF_VAL_16 0x3 ++ + #define PCIE_PORT_DEBUG0 0x728 + #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f + #define PORT_LOGIC_LTSSM_STATE_L0 0x11 +diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c +new file mode 100644 +index 000000000000..6ee661ceff67 +--- /dev/null ++++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c +@@ -0,0 +1,175 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * DWC PCIe RC driver for UltraRISC SoCs ++ * ++ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#define PCIE_CUS_CORE 0x400000 ++ ++#define LTSSM_ENABLE BIT(7) ++#define FAST_LINK_MODE BIT(12) ++#define HOLD_PHY_RST BIT(14) ++#define L1SUB_DISABLE BIT(15) ++ ++#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 ++ ++static struct pci_ops ultrarisc_pci_ops = { ++ .map_bus = dw_pcie_own_conf_map_bus, ++ .read = pci_generic_config_read32, ++ .write = pci_generic_config_write32, ++}; ++ ++static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct pci_host_bridge *bridge = pp->bridge; ++ u8 cap_exp; ++ u32 val; ++ ++ bridge->ops = &ultrarisc_pci_ops; ++ ++ if (dw_pcie_link_up(pci)) ++ return 0; ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val &= ~FAST_LINK_MODE; ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); ++ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); ++ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); ++ ++ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); ++ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); ++ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); ++ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); ++ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); ++ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); ++ ++ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); ++ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, ++ ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); ++ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ return 0; ++} ++ ++static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) ++{ ++ /* ++ * DP1000 does not support sending PME_Turn_Off from the RC. ++ * Keep this callback empty to skip the generic MSG TLP path. ++ */ ++} ++ ++static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { ++ .init = ultrarisc_pcie_host_init, ++ .pme_turn_off = ultrarisc_pcie_pme_turn_off, ++}; ++ ++static int ultrarisc_pcie_start_link(struct dw_pcie *pci) ++{ ++ u32 val; ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val |= LTSSM_ENABLE; ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ return 0; ++} ++ ++static const struct dw_pcie_ops dw_pcie_ops = { ++ .start_link = ultrarisc_pcie_start_link, ++}; ++ ++static int ultrarisc_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct dw_pcie_rp *pp; ++ struct dw_pcie *pci; ++ int ret; ++ ++ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); ++ if (!pci) ++ return -ENOMEM; ++ ++ pci->dev = dev; ++ pci->ops = &dw_pcie_ops; ++ ++ /* Set a default value suitable for at most 16 in and 16 out windows */ ++ pci->atu_size = SZ_8K; ++ ++ pp = &pci->pp; ++ ++ platform_set_drvdata(pdev, pci); ++ ++ pp->num_vectors = MAX_MSI_IRQS; ++ /* No L2/L3 Ready indication is available on this platform */ ++ pp->skip_l23_ready = true; ++ pp->ops = &ultrarisc_pcie_host_ops; ++ ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(dev, "Failed to initialize host\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ultrarisc_pcie_suspend_noirq(struct device *dev) ++{ ++ struct dw_pcie *pci = dev_get_drvdata(dev); ++ ++ return dw_pcie_suspend_noirq(pci); ++} ++ ++static int ultrarisc_pcie_resume_noirq(struct device *dev) ++{ ++ struct dw_pcie *pci = dev_get_drvdata(dev); ++ ++ return dw_pcie_resume_noirq(pci); ++} ++ ++static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { ++ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, ++ ultrarisc_pcie_resume_noirq) ++}; ++ ++static const struct of_device_id ultrarisc_pcie_of_match[] = { ++ { ++ .compatible = "ultrarisc,dp1000-pcie", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); ++ ++static struct platform_driver ultrarisc_pcie_driver = { ++ .driver = { ++ .name = "ultrarisc-pcie", ++ .of_match_table = ultrarisc_pcie_of_match, ++ .suppress_bind_attrs = true, ++ .pm = &ultrarisc_pcie_pm_ops, ++ }, ++ .probe = ultrarisc_pcie_probe, ++}; ++builtin_platform_driver(ultrarisc_pcie_driver); ++ ++MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch deleted file mode 100644 index e2d8d4c7b2..0000000000 --- a/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 7bdcfb039d0ab0b746a0ee44a449149463a7b94e Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 27 Apr 2026 09:32:11 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe - controller - -Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. - -Signed-off-by: Jia Wang -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++++++++++ - MAINTAINERS | 7 ++ - 2 files changed, 100 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml - -diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -new file mode 100644 -index 000000000000..512b935bf5d1 ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: UltraRISC DP1000 PCIe Host Controller -+ -+description: -+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. -+ -+maintainers: -+ - Xincheng Zhang -+ - Jia Wang -+ -+allOf: -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ -+properties: -+ compatible: -+ const: ultrarisc,dp1000-pcie -+ -+ reg: -+ items: -+ - description: Data Bus Interface (DBI) registers. -+ - description: PCIe configuration space region. -+ -+ reg-names: -+ items: -+ - const: dbi -+ - const: config -+ -+ num-lanes: -+ $ref: /schemas/types.yaml#/definitions/uint32 -+ enum: [4, 16] -+ description: Number of lanes to use. -+ -+ interrupts: -+ items: -+ - description: MSI interrupt -+ - description: Legacy INTA interrupt -+ - description: Legacy INTB interrupt -+ - description: Legacy INTC interrupt -+ - description: Legacy INTD interrupt -+ -+ interrupt-names: -+ items: -+ - const: msi -+ - const: inta -+ - const: intb -+ - const: intc -+ - const: intd -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - interrupts -+ - interrupt-names -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@21000000 { -+ compatible = "ultrarisc,dp1000-pcie"; -+ reg = <0x0 0x21000000 0x0 0x01000000>, -+ <0x0 0x4fff0000 0x0 0x00010000>; -+ reg-names = "dbi", "config"; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ }; -diff --git a/MAINTAINERS b/MAINTAINERS -index 1509fa6ab229..a6cbce2ebe1d 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -20076,6 +20076,13 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml - F: drivers/pci/controller/plda/pcie-starfive.c - -+PCIE DRIVER FOR ULTRARISC DP1000 -+M: Xincheng Zhang -+M: Jia Wang -+L: linux-pci@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -+ - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam - L: linux-pci@vger.kernel.org --- -2.53.0 - diff --git a/SPECS/linux-lts/0336-UPSTREAM-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux-lts/0336-UPSTREAM-serial-8250_dwlib-move-DesignWare-register-.patch new file mode 100644 index 0000000000..8736009541 --- /dev/null +++ b/SPECS/linux-lts/0336-UPSTREAM-serial-8250_dwlib-move-DesignWare-register-.patch @@ -0,0 +1,205 @@ +From 6bc115431a74f3706c15ac3326e475eba1056f47 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:25 +0800 +Subject: [RUYI PATCH] UPSTREAM: serial: 8250_dwlib: move DesignWare register + definitions to header +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move the DW_UART_* register offsets and CPR bit/field definitions from +8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and +8250_dwlib users. + +Add an include guard for 8250_dwlib.h. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Reviewed-by: Ilpo Järvinen +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-1-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 6d7f4890bbb6fc8b70f618aa0407043b32bc738a) +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 11 ----- + drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------- + drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++ + 3 files changed, 67 insertions(+), 60 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 7a0008363543..c5ad459eef01 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -34,22 +34,11 @@ + + #include "8250_dwlib.h" + +-/* Offsets for the DesignWare specific registers */ +-#define DW_UART_USR 0x1f /* UART Status Register */ +-#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ +- + #define OCTEON_UART_USR 0x27 /* UART Status Register */ + + #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ + #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ + +-/* DesignWare specific register fields */ +-#define DW_UART_IIR_IID GENMASK(3, 0) +- +-#define DW_UART_MCR_SIRE BIT(6) +- +-#define DW_UART_USR_BUSY BIT(0) +- + /* Renesas specific register fields */ + #define RZN1_UART_xDMACR_DMA_EN BIT(0) + #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) +diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c +index b055d89cfb39..8859e66d2d71 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.c ++++ b/drivers/tty/serial/8250/8250_dwlib.c +@@ -13,55 +13,6 @@ + + #include "8250_dwlib.h" + +-/* Offsets for the DesignWare specific registers */ +-#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ +-#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ +-#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ +-#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ +-#define DW_UART_RAR 0xc4 /* Receive Address Register */ +-#define DW_UART_TAR 0xc8 /* Transmit Address Register */ +-#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ +-#define DW_UART_CPR 0xf4 /* Component Parameter Register */ +-#define DW_UART_UCV 0xf8 /* UART Component Version */ +- +-/* Receive / Transmit Address Register bits */ +-#define DW_UART_ADDR_MASK GENMASK(7, 0) +- +-/* Line Status Register bits */ +-#define DW_UART_LSR_ADDR_RCVD BIT(8) +- +-/* Transceiver Control Register bits */ +-#define DW_UART_TCR_RS485_EN BIT(0) +-#define DW_UART_TCR_RE_POL BIT(1) +-#define DW_UART_TCR_DE_POL BIT(2) +-#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) +-#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) +-#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) +-#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) +- +-/* Line Extended Control Register bits */ +-#define DW_UART_LCR_EXT_DLS_E BIT(0) +-#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) +-#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) +-#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) +- +-/* Component Parameter Register bits */ +-#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) +-#define DW_UART_CPR_AFCE_MODE BIT(4) +-#define DW_UART_CPR_THRE_MODE BIT(5) +-#define DW_UART_CPR_SIR_MODE BIT(6) +-#define DW_UART_CPR_SIR_LP_MODE BIT(7) +-#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) +-#define DW_UART_CPR_FIFO_ACCESS BIT(9) +-#define DW_UART_CPR_FIFO_STAT BIT(10) +-#define DW_UART_CPR_SHADOW BIT(11) +-#define DW_UART_CPR_ENCODED_PARMS BIT(12) +-#define DW_UART_CPR_DMA_EXTRA BIT(13) +-#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) +- +-/* Helper for FIFO size calculation */ +-#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) +- + /* + * divisor = div(I) + div(F) + * "I" means integer, "F" means fractional +diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h +index 7dd2a8e7b780..2f26f9ecacbe 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.h ++++ b/drivers/tty/serial/8250/8250_dwlib.h +@@ -1,11 +1,76 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* Synopsys DesignWare 8250 library header file. */ + ++#ifndef _SERIAL_8250_DWLIB_H_ ++#define _SERIAL_8250_DWLIB_H_ ++ ++#include ++#include + #include + #include + + #include "8250.h" + ++/* Offsets for the DesignWare specific registers */ ++#define DW_UART_USR 0x1f /* UART Status Register */ ++#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ ++#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ ++#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ ++#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ ++#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ ++#define DW_UART_RAR 0xc4 /* Receive Address Register */ ++#define DW_UART_TAR 0xc8 /* Transmit Address Register */ ++#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ ++#define DW_UART_CPR 0xf4 /* Component Parameter Register */ ++#define DW_UART_UCV 0xf8 /* UART Component Version */ ++ ++/* Interrupt ID Register bits */ ++#define DW_UART_IIR_IID GENMASK(3, 0) ++ ++/* Modem Control Register bits */ ++#define DW_UART_MCR_SIRE BIT(6) ++ ++/* Line Status Register bits */ ++#define DW_UART_LSR_ADDR_RCVD BIT(8) ++ ++/* UART Status Register bits */ ++#define DW_UART_USR_BUSY BIT(0) ++ ++/* Transceiver Control Register bits */ ++#define DW_UART_TCR_RS485_EN BIT(0) ++#define DW_UART_TCR_RE_POL BIT(1) ++#define DW_UART_TCR_DE_POL BIT(2) ++#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) ++#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) ++#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) ++#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) ++ ++/* Receive / Transmit Address Register bits */ ++#define DW_UART_ADDR_MASK GENMASK(7, 0) ++ ++/* Line Extended Control Register bits */ ++#define DW_UART_LCR_EXT_DLS_E BIT(0) ++#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) ++#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) ++#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) ++ ++/* Component Parameter Register bits */ ++#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) ++#define DW_UART_CPR_AFCE_MODE BIT(4) ++#define DW_UART_CPR_THRE_MODE BIT(5) ++#define DW_UART_CPR_SIR_MODE BIT(6) ++#define DW_UART_CPR_SIR_LP_MODE BIT(7) ++#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) ++#define DW_UART_CPR_FIFO_ACCESS BIT(9) ++#define DW_UART_CPR_FIFO_STAT BIT(10) ++#define DW_UART_CPR_SHADOW BIT(11) ++#define DW_UART_CPR_ENCODED_PARMS BIT(12) ++#define DW_UART_CPR_DMA_EXTRA BIT(13) ++#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) ++ ++/* Helper for FIFO size calculation */ ++#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) ++ + struct dw8250_port_data { + /* Port properties */ + int line; +@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) + else + writel(reg, p->membase + offset); + } ++ ++#endif /* _SERIAL_8250_DWLIB_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch deleted file mode 100644 index 520f243b8f..0000000000 --- a/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch +++ /dev/null @@ -1,292 +0,0 @@ -From 4263860bea4eb50e8c9cce4769c096e144fd0400 Mon Sep 17 00:00:00 2001 -From: Xincheng Zhang -Date: Mon, 27 Apr 2026 09:32:12 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root - Complex driver - -Add DP1000 SoC PCIe Root Complex driver. - -The controller only supports 32-bit aligned configuration space accesses. - -Signed-off-by: Xincheng Zhang -Signed-off-by: Jia Wang -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - MAINTAINERS | 1 + - drivers/pci/controller/dwc/Kconfig | 12 ++ - drivers/pci/controller/dwc/Makefile | 1 + - drivers/pci/controller/dwc/pcie-designware.h | 22 +++ - drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++ - 5 files changed, 211 insertions(+) - create mode 100644 drivers/pci/controller/dwc/pcie-ultrarisc.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index a6cbce2ebe1d..996aa3d41e95 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -20082,6 +20082,7 @@ M: Jia Wang - L: linux-pci@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -+F: drivers/pci/controller/dwc/pcie-ultrarisc.c - - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam -diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig -index 718bb54e943f..5e0656eea718 100644 ---- a/drivers/pci/controller/dwc/Kconfig -+++ b/drivers/pci/controller/dwc/Kconfig -@@ -531,4 +531,16 @@ config PCIE_VISCONTI_HOST - Say Y here if you want PCIe controller support on Toshiba Visconti SoC. - This driver supports TMPV7708 SoC. - -+config PCIE_ULTRARISC -+ tristate "UltraRISC PCIe host controller" -+ depends on ARCH_ULTRARISC || COMPILE_TEST -+ select PCIE_DW_HOST -+ select PCI_MSI -+ default y if ARCH_ULTRARISC -+ help -+ Enables support for the PCIe controller in the UltraRISC SoC. -+ This driver supports UR-DP1000 SoC. -+ By default, this symbol is enabled when ARCH_ULTRARISC is active, -+ requiring no further configuration on that platform. -+ - endmenu -diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile -index 662b0a219ddc..39087e7a06d5 100644 ---- a/drivers/pci/controller/dwc/Makefile -+++ b/drivers/pci/controller/dwc/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o - obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o - obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o - obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o -+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o - - # The following drivers are for devices that use the generic ACPI - # pci_root.c driver but don't support standard ECAM config access. -diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h -index 295e113189b7..bd3d35354758 100644 ---- a/drivers/pci/controller/dwc/pcie-designware.h -+++ b/drivers/pci/controller/dwc/pcie-designware.h -@@ -71,6 +71,8 @@ - - /* Synopsys-specific PCIe configuration registers */ - #define PCIE_PORT_FORCE 0x708 -+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ -+#define PORT_LINK_NUM_MASK GENMASK(7, 0) - #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) - - #define PCIE_PORT_AFR 0x70C -@@ -98,6 +100,26 @@ - #define PCIE_PORT_LANE_SKEW 0x714 - #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) - -+/* -+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number -+ * Register. -+ * This register holds the ack frequency, latency, replay, fast link -+ * scaling timers, and max function number values. -+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. -+ * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). -+ * When the LTSSM is in Config or L12 Entry State, 1ms -+ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. -+ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) -+ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) -+ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) -+ */ -+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 -+#define PORT_FLT_SF_MASK GENMASK(30, 29) -+#define PORT_FLT_SF_VAL_1024 0x0 -+#define PORT_FLT_SF_VAL_256 0x1 -+#define PORT_FLT_SF_VAL_64 0x2 -+#define PORT_FLT_SF_VAL_16 0x3 -+ - #define PCIE_PORT_DEBUG0 0x728 - #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f - #define PORT_LOGIC_LTSSM_STATE_L0 0x11 -diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c -new file mode 100644 -index 000000000000..7326bd446590 ---- /dev/null -+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c -@@ -0,0 +1,175 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * DWC PCIe RC driver for UltraRISC SoCs -+ * -+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-designware.h" -+ -+#define PCIE_CUS_CORE 0x400000 -+ -+#define LTSSM_ENABLE BIT(7) -+#define FAST_LINK_MODE BIT(12) -+#define HOLD_PHY_RST BIT(14) -+#define L1SUB_DISABLE BIT(15) -+ -+#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 -+ -+static struct pci_ops ultrarisc_pci_ops = { -+ .map_bus = dw_pcie_own_conf_map_bus, -+ .read = pci_generic_config_read32, -+ .write = pci_generic_config_write32, -+}; -+ -+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ struct pci_host_bridge *bridge = pp->bridge; -+ u8 cap_exp; -+ u32 val; -+ -+ bridge->ops = &ultrarisc_pci_ops; -+ -+ if (dw_pcie_link_up(pci)) -+ return 0; -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val &= ~FAST_LINK_MODE; -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); -+ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); -+ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); -+ -+ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); -+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); -+ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); -+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); -+ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); -+ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); -+ -+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); -+ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, -+ ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); -+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ return 0; -+} -+ -+static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) -+{ -+ /* -+ * DP1000 does not support sending PME_Turn_Off from the RC. -+ * Keep this callback empty to skip the generic MSG TLP path. -+ */ -+} -+ -+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { -+ .init = ultrarisc_pcie_host_init, -+ .pme_turn_off = ultrarisc_pcie_pme_turn_off, -+}; -+ -+static int ultrarisc_pcie_start_link(struct dw_pcie *pci) -+{ -+ u32 val; -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val |= LTSSM_ENABLE; -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ return 0; -+} -+ -+static const struct dw_pcie_ops dw_pcie_ops = { -+ .start_link = ultrarisc_pcie_start_link, -+}; -+ -+static int ultrarisc_pcie_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct dw_pcie_rp *pp; -+ struct dw_pcie *pci; -+ int ret; -+ -+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); -+ if (!pci) -+ return -ENOMEM; -+ -+ pci->dev = dev; -+ pci->ops = &dw_pcie_ops; -+ -+ /* Set a default value suitable for at most 16 in and 16 out windows */ -+ pci->atu_size = SZ_8K; -+ -+ pp = &pci->pp; -+ -+ platform_set_drvdata(pdev, pci); -+ -+ pp->num_vectors = MAX_MSI_IRQS; -+ /* No L2/L3 Ready indication is available on this platform. */ -+ pp->skip_l23_ready = true; -+ pp->ops = &ultrarisc_pcie_host_ops; -+ -+ ret = dw_pcie_host_init(pp); -+ if (ret) { -+ dev_err(dev, "Failed to initialize host\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int ultrarisc_pcie_suspend_noirq(struct device *dev) -+{ -+ struct dw_pcie *pci = dev_get_drvdata(dev); -+ -+ return dw_pcie_suspend_noirq(pci); -+} -+ -+static int ultrarisc_pcie_resume_noirq(struct device *dev) -+{ -+ struct dw_pcie *pci = dev_get_drvdata(dev); -+ -+ return dw_pcie_resume_noirq(pci); -+} -+ -+static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { -+ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, -+ ultrarisc_pcie_resume_noirq) -+}; -+ -+static const struct of_device_id ultrarisc_pcie_of_match[] = { -+ { -+ .compatible = "ultrarisc,dp1000-pcie", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); -+ -+static struct platform_driver ultrarisc_pcie_driver = { -+ .driver = { -+ .name = "ultrarisc-pcie", -+ .of_match_table = ultrarisc_pcie_of_match, -+ .suppress_bind_attrs = true, -+ .pm = &ultrarisc_pcie_pm_ops, -+ }, -+ .probe = ultrarisc_pcie_probe, -+}; -+module_platform_driver(ultrarisc_pcie_driver); -+ -+MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0337-UPSTREAM-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux-lts/0337-UPSTREAM-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch new file mode 100644 index 0000000000..2de45c6c4d --- /dev/null +++ b/SPECS/linux-lts/0337-UPSTREAM-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch @@ -0,0 +1,79 @@ +From 8d0349194b40df1005bf8dbe9fc1d88c0c8cd873 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:26 +0800 +Subject: [RUYI PATCH] UPSTREAM: serial: 8250_dw: build Renesas RZN1 CPR value + from DW_UART_CPR_* definitions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace the magic CPR value for Renesas RZ/N1 with a composition using +DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). + +Introduce a helper macro to convert a FIFO size (bytes) into the CPR +FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and +bounds. Use it to replace the literal FIFO_MODE values in the RZN1. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Reviewed-by: Ilpo Järvinen +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-2-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 07bb8459c443b840c55293cee1c726431dd749cf) +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 10 +++++++++- + drivers/tty/serial/8250/8250_dwlib.h | 8 +++++++- + 2 files changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index c5ad459eef01..81848f2696cd 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -937,7 +937,15 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { + + static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { + .usr_reg = DW_UART_USR, +- .cpr_value = 0x00012f32, ++ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | ++ DW_UART_CPR_AFCE_MODE | ++ DW_UART_CPR_THRE_MODE | ++ DW_UART_CPR_ADDITIONAL_FEATURES | ++ DW_UART_CPR_FIFO_ACCESS | ++ DW_UART_CPR_FIFO_STAT | ++ DW_UART_CPR_SHADOW | ++ DW_UART_CPR_DMA_EXTRA | ++ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16), + .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, + }; + +diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h +index 2f26f9ecacbe..1fe52332e774 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.h ++++ b/drivers/tty/serial/8250/8250_dwlib.h +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + #include + +@@ -68,8 +69,13 @@ + #define DW_UART_CPR_DMA_EXTRA BIT(13) + #define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) + +-/* Helper for FIFO size calculation */ ++/* Helpers for FIFO size calculation */ + #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) ++#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \ ++ (FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, \ ++ BUILD_BUG_ON_ZERO((size) > 2048) + \ ++ BUILD_BUG_ON_ZERO((size) % 16) + \ ++ ((size) / 16))) + + struct dw8250_port_data { + /* Port properties */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch deleted file mode 100644 index 43fcf3979b..0000000000 --- a/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch +++ /dev/null @@ -1,199 +0,0 @@ -From 7215c59bd1680f8f694982585919d6ec01c2e009 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:26 +0800 -Subject: [RUYI PATCH] FROMLIST: serial: 8250_dwlib: move DesignWare register - definitions to header - -Move the DW_UART_* register offsets and CPR bit/field definitions from -8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and -8250_dwlib users. - -Add an include guard for 8250_dwlib.h. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-1-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 ----- - drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------- - drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++ - 3 files changed, 67 insertions(+), 60 deletions(-) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index b1f0303aceab..552455b6f51e 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -34,22 +34,11 @@ - - #include "8250_dwlib.h" - --/* Offsets for the DesignWare specific registers */ --#define DW_UART_USR 0x1f /* UART Status Register */ --#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ -- - #define OCTEON_UART_USR 0x27 /* UART Status Register */ - - #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ - #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ - --/* DesignWare specific register fields */ --#define DW_UART_IIR_IID GENMASK(3, 0) -- --#define DW_UART_MCR_SIRE BIT(6) -- --#define DW_UART_USR_BUSY BIT(0) -- - /* Renesas specific register fields */ - #define RZN1_UART_xDMACR_DMA_EN BIT(0) - #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) -diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c -index b055d89cfb39..8859e66d2d71 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.c -+++ b/drivers/tty/serial/8250/8250_dwlib.c -@@ -13,55 +13,6 @@ - - #include "8250_dwlib.h" - --/* Offsets for the DesignWare specific registers */ --#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ --#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ --#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ --#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ --#define DW_UART_RAR 0xc4 /* Receive Address Register */ --#define DW_UART_TAR 0xc8 /* Transmit Address Register */ --#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ --#define DW_UART_CPR 0xf4 /* Component Parameter Register */ --#define DW_UART_UCV 0xf8 /* UART Component Version */ -- --/* Receive / Transmit Address Register bits */ --#define DW_UART_ADDR_MASK GENMASK(7, 0) -- --/* Line Status Register bits */ --#define DW_UART_LSR_ADDR_RCVD BIT(8) -- --/* Transceiver Control Register bits */ --#define DW_UART_TCR_RS485_EN BIT(0) --#define DW_UART_TCR_RE_POL BIT(1) --#define DW_UART_TCR_DE_POL BIT(2) --#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) --#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) --#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) --#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) -- --/* Line Extended Control Register bits */ --#define DW_UART_LCR_EXT_DLS_E BIT(0) --#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) --#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) --#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) -- --/* Component Parameter Register bits */ --#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) --#define DW_UART_CPR_AFCE_MODE BIT(4) --#define DW_UART_CPR_THRE_MODE BIT(5) --#define DW_UART_CPR_SIR_MODE BIT(6) --#define DW_UART_CPR_SIR_LP_MODE BIT(7) --#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) --#define DW_UART_CPR_FIFO_ACCESS BIT(9) --#define DW_UART_CPR_FIFO_STAT BIT(10) --#define DW_UART_CPR_SHADOW BIT(11) --#define DW_UART_CPR_ENCODED_PARMS BIT(12) --#define DW_UART_CPR_DMA_EXTRA BIT(13) --#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) -- --/* Helper for FIFO size calculation */ --#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -- - /* - * divisor = div(I) + div(F) - * "I" means integer, "F" means fractional -diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h -index 7dd2a8e7b780..2f26f9ecacbe 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.h -+++ b/drivers/tty/serial/8250/8250_dwlib.h -@@ -1,11 +1,76 @@ - /* SPDX-License-Identifier: GPL-2.0+ */ - /* Synopsys DesignWare 8250 library header file. */ - -+#ifndef _SERIAL_8250_DWLIB_H_ -+#define _SERIAL_8250_DWLIB_H_ -+ -+#include -+#include - #include - #include - - #include "8250.h" - -+/* Offsets for the DesignWare specific registers */ -+#define DW_UART_USR 0x1f /* UART Status Register */ -+#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ -+#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ -+#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ -+#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ -+#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ -+#define DW_UART_RAR 0xc4 /* Receive Address Register */ -+#define DW_UART_TAR 0xc8 /* Transmit Address Register */ -+#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ -+#define DW_UART_CPR 0xf4 /* Component Parameter Register */ -+#define DW_UART_UCV 0xf8 /* UART Component Version */ -+ -+/* Interrupt ID Register bits */ -+#define DW_UART_IIR_IID GENMASK(3, 0) -+ -+/* Modem Control Register bits */ -+#define DW_UART_MCR_SIRE BIT(6) -+ -+/* Line Status Register bits */ -+#define DW_UART_LSR_ADDR_RCVD BIT(8) -+ -+/* UART Status Register bits */ -+#define DW_UART_USR_BUSY BIT(0) -+ -+/* Transceiver Control Register bits */ -+#define DW_UART_TCR_RS485_EN BIT(0) -+#define DW_UART_TCR_RE_POL BIT(1) -+#define DW_UART_TCR_DE_POL BIT(2) -+#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) -+#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) -+#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) -+#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) -+ -+/* Receive / Transmit Address Register bits */ -+#define DW_UART_ADDR_MASK GENMASK(7, 0) -+ -+/* Line Extended Control Register bits */ -+#define DW_UART_LCR_EXT_DLS_E BIT(0) -+#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) -+#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) -+#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) -+ -+/* Component Parameter Register bits */ -+#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) -+#define DW_UART_CPR_AFCE_MODE BIT(4) -+#define DW_UART_CPR_THRE_MODE BIT(5) -+#define DW_UART_CPR_SIR_MODE BIT(6) -+#define DW_UART_CPR_SIR_LP_MODE BIT(7) -+#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) -+#define DW_UART_CPR_FIFO_ACCESS BIT(9) -+#define DW_UART_CPR_FIFO_STAT BIT(10) -+#define DW_UART_CPR_SHADOW BIT(11) -+#define DW_UART_CPR_ENCODED_PARMS BIT(12) -+#define DW_UART_CPR_DMA_EXTRA BIT(13) -+#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) -+ -+/* Helper for FIFO size calculation */ -+#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -+ - struct dw8250_port_data { - /* Port properties */ - int line; -@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) - else - writel(reg, p->membase + offset); - } -+ -+#endif /* _SERIAL_8250_DWLIB_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0338-UPSTREAM-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux-lts/0338-UPSTREAM-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch new file mode 100644 index 0000000000..96e947321d --- /dev/null +++ b/SPECS/linux-lts/0338-UPSTREAM-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch @@ -0,0 +1,35 @@ +From 964cdf57a956fa7a689e12f1066079b71ed7e916 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:27 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: snps-dw-apb-uart: Add + UltraRISC DP1000 UART + +UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does +not provide the standard CPR and UCV registers. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Reviewed-by: Andy Shevchenko +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit d22d2e54f660eeb64e06f2cb6db068dac66a5733) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +index cb9da6c97afc..4ed637df0186 100644 +--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml ++++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +@@ -75,6 +75,7 @@ properties: + - starfive,jh7100-hsuart + - starfive,jh7100-uart + - starfive,jh7110-uart ++ - ultrarisc,dp1000-uart + - const: snps,dw-apb-uart + - const: snps,dw-apb-uart + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch deleted file mode 100644 index 361bfc6547..0000000000 --- a/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 6180d1c44da7f8a61ffe42b1aa5f7fed0db947c5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:27 +0800 -Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR value - from DW_UART_CPR_* definitions - -Replace the magic CPR value for Renesas RZ/N1 with a composition using -DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). - -Introduce a helper macro to convert a FIFO size (bytes) into the CPR -FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and -bounds. Use it to replace the literal FIFO_MODE values in the RZN1. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-2-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 ++++++++++- - drivers/tty/serial/8250/8250_dwlib.h | 7 +++++++ - 2 files changed, 17 insertions(+), 1 deletion(-) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 552455b6f51e..57c037f19951 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -935,7 +935,16 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { - - static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { - .usr_reg = DW_UART_USR, -- .cpr_value = 0x00012f32, -+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | -+ DW_UART_CPR_AFCE_MODE | -+ DW_UART_CPR_THRE_MODE | -+ DW_UART_CPR_ADDITIONAL_FEATURES | -+ DW_UART_CPR_FIFO_ACCESS | -+ DW_UART_CPR_FIFO_STAT | -+ DW_UART_CPR_SHADOW | -+ DW_UART_CPR_DMA_EXTRA | -+ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, -+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16)), - .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, - }; - -diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h -index 2f26f9ecacbe..c1f87cd42ecc 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.h -+++ b/drivers/tty/serial/8250/8250_dwlib.h -@@ -6,6 +6,8 @@ - - #include - #include -+#include -+#include - #include - #include - -@@ -70,6 +72,11 @@ - - /* Helper for FIFO size calculation */ - #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -+#define DW_UART_CPR_FIFO_MODE_MAX 0x80 -+#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \ -+ (BUILD_BUG_ON_ZERO(!IS_ALIGNED((size), 16)) + \ -+ BUILD_BUG_ON_ZERO(((size) / 16) > DW_UART_CPR_FIFO_MODE_MAX) + \ -+ ((size) / 16)) - - struct dw8250_port_data { - /* Port properties */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0339-UPSTREAM-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux-lts/0339-UPSTREAM-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch new file mode 100644 index 0000000000..313bdf66bb --- /dev/null +++ b/SPECS/linux-lts/0339-UPSTREAM-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch @@ -0,0 +1,57 @@ +From c3ece7b6088ef015d4826bd725453df7480e087a Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 29 Apr 2026 17:13:28 +0800 +Subject: [RUYI PATCH] UPSTREAM: serial: 8250_dw: Use a fixed CPR value for + UltraRISC DP1000 UART +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The UltraRISC DP1000 UART does not provide the standard CPR register used +by 8250_dw to discover port capabilities. + +Provide a fixed CPR value for the DP1000-specific compatible so the +driver can configure the port correctly. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Reviewed-by: Ilpo Järvinen +Link: https://patch.msgid.link/20260429-ultrarisc-serial-v7-4-e475cce9e274@ultrarisc.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 4a9a0b1a82a8b23eb68032dd19b120e82cd67004) +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 81848f2696cd..9c1ff564e09d 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -959,6 +959,15 @@ static const struct dw8250_platform_data dw8250_intc10ee = { + .quirks = DW_UART_QUIRK_IER_KICK, + }; + ++static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { ++ .usr_reg = DW_UART_USR, ++ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | ++ DW_UART_CPR_THRE_MODE | ++ DW_UART_CPR_DMA_EXTRA | ++ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32), ++ .quirks = DW_UART_QUIRK_CPR_VALUE, ++}; ++ + static const struct of_device_id dw8250_of_match[] = { + { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, + { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, +@@ -966,6 +975,7 @@ static const struct of_device_id dw8250_of_match[] = { + { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, + { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, ++ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, + { /* Sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dw8250_of_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch deleted file mode 100644 index 2d2f322fc8..0000000000 --- a/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0b0183bf49240d8f6c2d66b6eaff2fe17c541d19 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:28 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add - UltraRISC DP1000 UART - -UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does -not provide the standard CPR and UCV registers. - -Signed-off-by: Jia Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-3-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -index cb9da6c97afc..4ed637df0186 100644 ---- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -@@ -75,6 +75,7 @@ properties: - - starfive,jh7100-hsuart - - starfive,jh7100-uart - - starfive,jh7110-uart -+ - ultrarisc,dp1000-uart - - const: snps,dw-apb-uart - - const: snps,dw-apb-uart - --- -2.53.0 - diff --git a/SPECS/linux-lts/0340-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts/0340-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch new file mode 100644 index 0000000000..f6b4b4f799 --- /dev/null +++ b/SPECS/linux-lts/0340-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -0,0 +1,39 @@ +From 1bcfb5adfc0e60be3c2f53a6fd1886e7d18d9968 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:14 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter for + OrangePi RV2 + +The adapter is used to access the SpacemiT P1 PMIC present in this board. + +Tested-by: Vincent Legoll # OrangePi-RV2 +Signed-off-by: Han Gao +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Yixun Lan +(cherry picked from commit ece83d42785e12ab7690c0c13b416baf46a74063) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 7b7331cb3c72..57ec1cc32b03 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -87,6 +87,12 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch deleted file mode 100644 index 710885bf79..0000000000 --- a/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 07e647f6d38a2395768391b1126d6af257685679 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:29 +0800 -Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: Use a fixed CPR value for - UltraRISC DP1000 UART - -The UltraRISC DP1000 UART does not provide the standard CPR register used -by 8250_dw to discover port capabilities. - -Provide a fixed CPR value for the DP1000-specific compatible so the -driver can configure the port correctly. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-4-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 57c037f19951..a13fde96efd9 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -958,6 +958,16 @@ static const struct dw8250_platform_data dw8250_intc10ee = { - .quirks = DW_UART_QUIRK_IER_KICK, - }; - -+static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { -+ .usr_reg = DW_UART_USR, -+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | -+ DW_UART_CPR_THRE_MODE | -+ DW_UART_CPR_DMA_EXTRA | -+ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, -+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32)), -+ .quirks = DW_UART_QUIRK_CPR_VALUE, -+}; -+ - static const struct of_device_id dw8250_of_match[] = { - { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, - { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, -@@ -965,6 +975,7 @@ static const struct of_device_id dw8250_of_match[] = { - { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, - { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, - { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, -+ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, - { /* Sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dw8250_of_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0341-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts/0341-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch new file mode 100644 index 0000000000..2bf6e157aa --- /dev/null +++ b/SPECS/linux-lts/0341-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -0,0 +1,175 @@ +From 38d4eec31f7970169c13d50f1af3d12ce1ef7ee3 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC + regulators for OrangePi RV2 + +Define the DC power input and the 4v power as fixed regulator supplies. + +Define the SpacemiT P1 PMIC voltage regulators and their constraints. + +Co-developed-by: Chukun Pan +Signed-off-by: Chukun Pan +Tested-by: Vincent Legoll # OrangePi-RV2 +Signed-off-by: Han Gao +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Yixun Lan +(cherry picked from commit c02c047b925c0ed101ec6834e1c07a53a45f98d4) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ + 1 file changed, 131 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 57ec1cc32b03..f7a1dadaa95f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -23,6 +23,25 @@ chosen { + stdout-path = "serial0"; + }; + ++ vcc_5v0: regulator-vcc-5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_5v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc4v0: regulator-vcc4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -91,6 +110,118 @@ &i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <&vcc4v0>; ++ vin2-supply = <&vcc4v0>; ++ vin3-supply = <&vcc4v0>; ++ vin4-supply = <&vcc4v0>; ++ vin5-supply = <&vcc4v0>; ++ vin6-supply = <&vcc4v0>; ++ aldoin-supply = <&vcc4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ /* not connected */ ++ }; ++ ++ aldo3 { ++ /* not connected */ ++ }; ++ ++ aldo4 { ++ /* not connected */ ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ /* not connected */ ++ }; ++ ++ dldo3 { ++ /* not connected */ ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ /* not connected */ ++ }; ++ }; ++ }; + }; + + &uart0 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch deleted file mode 100644 index e964c8cfd5..0000000000 --- a/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 53a9a6f9561ecf77c64e14e718b3c6677e450356 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Tue, 17 Mar 2026 16:48:06 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other - CPUs before reboot/shutdown - -Currently, the RISC-V implementation of machine_restart(), machine_halt(), -and machine_power_off() invokes the kernel teardown chains (e.g., -do_kernel_restart()) with local interrupts enabled and other CPUs still -running. - -This implementation fails to provide a deterministic execution environment -for registered handlers in the restart or power-off notifier chains. These -chains are intended to be executed in a strict atomic and single-threaded -context. - -Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increment -the preempt_count. If local interrupts remain enabled, the environment -is not guaranteed to be atomic. This can lead to a context misidentification -within generic kernel teardown code, causing it to incorrectly enter -non-atomic paths (such as attempting to acquire sleeping locks), which -results in fatal "scheduling while atomic" splats or system hangs. - -Additionally, stopping other CPUs ensures the primary CPU has exclusive -access to the hardware state during the final teardown phase, preventing -unpredictable interference from other active cores. - -Align RISC-V with other major architectures by disabling local interrupts -and stopping other CPUs at the beginning of the shutdown sequences. This -guarantees the architectural expectations of the kernel's restart and -power-off handlers are met. - -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Link: https://lore.kernel.org/all/abEP80FoCn4S4-WG@aurel32.net/ [1] -Link: https://lore.kernel.org/r/20260317-v7-0-rc1-rv-dis-int-before-restart-v2-1-0ecc85fbb7ff@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/reset.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c -index 912288572226..8c48466c50e9 100644 ---- a/arch/riscv/kernel/reset.c -+++ b/arch/riscv/kernel/reset.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - - static void default_power_off(void) - { -@@ -17,18 +18,27 @@ EXPORT_SYMBOL(pm_power_off); - - void machine_restart(char *cmd) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_restart(cmd); - while (1); - } - - void machine_halt(void) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_power_off(); - default_power_off(); - } - - void machine_power_off(void) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_power_off(); - default_power_off(); - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0342-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux-lts/0342-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch new file mode 100644 index 0000000000..43acbe1d5e --- /dev/null +++ b/SPECS/linux-lts/0342-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch @@ -0,0 +1,144 @@ +From 4636f951d781851a6b27a746ff2dbd8fbe8f560c Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable USB3.0/PCIe on + OrangePi RV2 + +Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the +OrangePi RV2 board. + +The board utilizes a Genesys Logic GL3523 USB3.0 hub. + +Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and +PHY-related Device Tree nodes for the OrangePi RV2. + +Co-developed-by: Chukun Pan +Signed-off-by: Chukun Pan +Tested-by: Vincent Legoll # OrangePi-RV2 +Signed-off-by: Han Gao +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Yixun Lan +(cherry picked from commit e3e433dd9aa04448f8f98d59359cab1340d994a3) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ + 1 file changed, 80 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index f7a1dadaa95f..3a829e3c9cbc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -23,6 +23,16 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; +@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { + vin-supply = <&vcc_5v0>; + }; + ++ vcc5v0_usb30: regulator-vcc5v0-usb30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc5v0_usb30"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -54,6 +74,10 @@ led1 { + }; + }; + ++&combo_phy { ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -224,8 +248,64 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ vbus-supply = <&vcc5v0_usb30>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb5e3,610"; ++ reg = <0x1>; ++ peer-hub = <&hub_3_0>; ++ vdd-supply = <&vcc_5v0>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb5e3,620"; ++ reg = <0x2>; ++ peer-hub = <&hub_2_0>; ++ vdd-supply = <&vcc_5v0>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch deleted file mode 100644 index baf487668c..0000000000 --- a/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch +++ /dev/null @@ -1,39 +0,0 @@ -From c3dbfd57b9930def2f6e386d4a107127d798a89e Mon Sep 17 00:00:00 2001 -From: Felix Gu -Date: Sat, 21 Mar 2026 03:12:10 +0800 -Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on - dw_hdmi_probe() return value - -The error check after calling dw_hdmi_probe() was incorrectly checking -the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. - -Fix this by checking the correct variable. - -Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") -Signed-off-by: Felix Gu -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260321-th1520-v1-1-ec877197770d@gmail.com -Signed-off-by: Han Gao ---- - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -index 389eead5f1c4..c9968ec1823c 100644 ---- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -136,8 +136,8 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) - plat_data->priv_data = hdmi; - - hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); -- if (IS_ERR(hdmi)) -- return PTR_ERR(hdmi); -+ if (IS_ERR(hdmi->dw_hdmi)) -+ return PTR_ERR(hdmi->dw_hdmi); - - platform_set_drvdata(pdev, hdmi); - --- -2.53.0 - diff --git a/SPECS/linux-lts/0343-UPSTREAM-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux-lts/0343-UPSTREAM-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch new file mode 100644 index 0000000000..2dcb9913c0 --- /dev/null +++ b/SPECS/linux-lts/0343-UPSTREAM-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch @@ -0,0 +1,42 @@ +From fa38bd5eff505e05e5dbc55b313c820b0bc332ed Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: dmaengine: Add SpacemiT K3 DMA + compatible string + +Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. + +While the K3 PDMA IP reuses most of the design found on the earlier +K1 SoC, a new compatible string is required because the DRCMR +(DMA Request/Command Register) base address for extended DMA request +numbers (>= 64) differs from the K1 implementation. + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Vinod Koul +(cherry picked from commit 55620b11186c81757b05fb8e2df9ddc7127d6fd2) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +index ec06235baf5c..62ce6d81526b 100644 +--- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml ++++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +@@ -14,7 +14,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-pdma ++ enum: ++ - spacemit,k1-pdma ++ - spacemit,k3-pdma + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch deleted file mode 100644 index 107fa9a940..0000000000 --- a/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch +++ /dev/null @@ -1,43 +0,0 @@ -From e4498bef7d35202c1d4fff03e1f738c01c63141b Mon Sep 17 00:00:00 2001 -From: Felix Gu -Date: Sat, 21 Mar 2026 03:12:11 +0800 -Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() - callback - -This driver stores struct th1520_hdmi * in platform drvdata, but -th1520_dw_hdmi_remove() was reading it back as struct dw_hdmi * -and passing it to dw_hdmi_remove(), so teardown runs on the wrong -pointer. - -Retrieve struct th1520_hdmi * from platform drvdata and pass -hdmi->dw_hdmi to dw_hdmi_remove(). - -Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") -Signed-off-by: Felix Gu -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260321-th1520-v1-2-ec877197770d@gmail.com -Signed-off-by: Han Gao ---- - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -index c9968ec1823c..6ec9003a8f3f 100644 ---- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -146,9 +146,9 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) - - static void th1520_dw_hdmi_remove(struct platform_device *pdev) - { -- struct dw_hdmi *hdmi = platform_get_drvdata(pdev); -+ struct th1520_hdmi *hdmi = platform_get_drvdata(pdev); - -- dw_hdmi_remove(hdmi); -+ dw_hdmi_remove(hdmi->dw_hdmi); - } - - static const struct of_device_id th1520_dw_hdmi_of_table[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0344-UPSTREAM-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux-lts/0344-UPSTREAM-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch new file mode 100644 index 0000000000..cd6a75207e --- /dev/null +++ b/SPECS/linux-lts/0344-UPSTREAM-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch @@ -0,0 +1,102 @@ +From 18cd7af49f8e0c1a02283d85c51d3eafbb445e5c Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: dmaengine: mmp_pdma: refactor DRCMR access + with helper function + +Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() +to support variable extended DRCMR base addresses across different PDMA +implementations, such as SpacemiT K3. + +Signed-off-by: Guodong Xu +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Vinod Koul +(cherry picked from commit f46b47623e70dea8b03794a5420ffba060425e85) +Signed-off-by: Han Gao +--- + drivers/dma/mmp_pdma.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c +index d12e729ee12c..6112369006ee 100644 +--- a/drivers/dma/mmp_pdma.c ++++ b/drivers/dma/mmp_pdma.c +@@ -51,7 +51,9 @@ + #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ + #define DCSR_EORINTR BIT(9) /* The end of Receive */ + +-#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) ++#define DRCMR_BASE 0x0100 ++#define DRCMR_EXT_BASE_DEFAULT 0x1100 ++#define DRCMR_REQ_LIMIT 64 + #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ + #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ + +@@ -154,6 +156,7 @@ struct mmp_pdma_phy { + * @run_bits: Control bits in DCSR register for channel start/stop + * @dma_width: DMA addressing width in bits (32 or 64). Determines the + * DMA mask capability of the controller hardware. ++ * @drcmr_ext_base: Base DRCMR address for extended requests + */ + struct mmp_pdma_ops { + /* Hardware Register Operations */ +@@ -174,6 +177,7 @@ struct mmp_pdma_ops { + /* Controller Configuration */ + u32 run_bits; + u32 dma_width; ++ u32 drcmr_ext_base; + }; + + struct mmp_pdma_device { +@@ -195,6 +199,13 @@ struct mmp_pdma_device { + #define to_mmp_pdma_dev(dmadev) \ + container_of(dmadev, struct mmp_pdma_device, device) + ++static u32 mmp_pdma_get_drcmr(struct mmp_pdma_device *pdev, u32 drcmr) ++{ ++ if (drcmr < DRCMR_REQ_LIMIT) ++ return DRCMR_BASE + (drcmr << 2); ++ return pdev->ops->drcmr_ext_base + ((drcmr - DRCMR_REQ_LIMIT) << 2); ++} ++ + /* For 32-bit PDMA */ + static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) + { +@@ -301,7 +312,7 @@ static void enable_chan(struct mmp_pdma_phy *phy) + + pdev = to_mmp_pdma_dev(phy->vchan->chan.device); + +- reg = DRCMR(phy->vchan->drcmr); ++ reg = mmp_pdma_get_drcmr(pdev, phy->vchan->drcmr); + writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); + + dalgn = readl(phy->base + DALGN); +@@ -437,7 +448,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) + return; + + /* clear the channel mapping in DRCMR */ +- reg = DRCMR(pchan->drcmr); ++ reg = mmp_pdma_get_drcmr(pdev, pchan->drcmr); + writel(0, pchan->phy->base + reg); + + spin_lock_irqsave(&pdev->phy_lock, flags); +@@ -1179,6 +1190,7 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = { + .get_desc_dst_addr = get_desc_dst_addr_32, + .run_bits = (DCSR_RUN), + .dma_width = 32, ++ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + + static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { +@@ -1192,6 +1204,7 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { + .get_desc_dst_addr = get_desc_dst_addr_64, + .run_bits = (DCSR_RUN | DCSR_LPAEEN), + .dma_width = 64, ++ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + + static const struct of_device_id mmp_pdma_dt_ids[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch deleted file mode 100644 index f320d51fd9..0000000000 --- a/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From b6fedd583f0486d6ff23a73e611445adac11b2b7 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:14 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter for - OrangePi RV2 - -The adapter is used to access the SpacemiT P1 PMIC present in this board. - -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 7b7331cb3c72..57ec1cc32b03 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -87,6 +87,12 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0345-UPSTREAM-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux-lts/0345-UPSTREAM-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch new file mode 100644 index 0000000000..b9220ead09 --- /dev/null +++ b/SPECS/linux-lts/0345-UPSTREAM-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch @@ -0,0 +1,65 @@ +From 6708ff1446d61d3031a99d79e08375f9bafa58b8 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: dmaengine: mmp_pdma: add SpacemiT K3 support + +SpacemiT K3 reuses most of the PDMA IP design found on K1, with one +difference being the extended DRCMR base address. Add "spacemit,k3-pdma" +compatible string and define a new mmp_pdma_ops for K3 PDMA. + +Signed-off-by: Guodong Xu +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Vinod Koul +(cherry picked from commit 6587b8661a0b61c2f4b260bfc9f0e9ef9de0ea2e) +Signed-off-by: Han Gao +--- + drivers/dma/mmp_pdma.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c +index 6112369006ee..386e85cd4882 100644 +--- a/drivers/dma/mmp_pdma.c ++++ b/drivers/dma/mmp_pdma.c +@@ -52,6 +52,7 @@ + #define DCSR_EORINTR BIT(9) /* The end of Receive */ + + #define DRCMR_BASE 0x0100 ++#define DRCMR_EXT_BASE_K3 0x1000 + #define DRCMR_EXT_BASE_DEFAULT 0x1100 + #define DRCMR_REQ_LIMIT 64 + #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ +@@ -1207,6 +1208,20 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { + .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + ++static const struct mmp_pdma_ops spacemit_k3_pdma_ops = { ++ .write_next_addr = write_next_addr_64, ++ .read_src_addr = read_src_addr_64, ++ .read_dst_addr = read_dst_addr_64, ++ .set_desc_next_addr = set_desc_next_addr_64, ++ .set_desc_src_addr = set_desc_src_addr_64, ++ .set_desc_dst_addr = set_desc_dst_addr_64, ++ .get_desc_src_addr = get_desc_src_addr_64, ++ .get_desc_dst_addr = get_desc_dst_addr_64, ++ .run_bits = (DCSR_RUN | DCSR_LPAEEN | DCSR_EORIRQEN | DCSR_EORSTOPEN), ++ .dma_width = 64, ++ .drcmr_ext_base = DRCMR_EXT_BASE_K3, ++}; ++ + static const struct of_device_id mmp_pdma_dt_ids[] = { + { + .compatible = "marvell,pdma-1.0", +@@ -1214,6 +1229,9 @@ static const struct of_device_id mmp_pdma_dt_ids[] = { + }, { + .compatible = "spacemit,k1-pdma", + .data = &spacemit_k1_pdma_ops ++ }, { ++ .compatible = "spacemit,k3-pdma", ++ .data = &spacemit_k3_pdma_ops + }, { + /* sentinel */ + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch deleted file mode 100644 index d8cc2b7e7f..0000000000 --- a/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ /dev/null @@ -1,171 +0,0 @@ -From 8a8b83695e5206dc768419823d357d36066dcc1a Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:15 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC - regulators for OrangePi RV2 - -Define the DC power input and the 4v power as fixed regulator supplies. - -Define the SpacemiT P1 PMIC voltage regulators and their constraints. - -Co-developed-by: Chukun Pan -Signed-off-by: Chukun Pan -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ - 1 file changed, 131 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 57ec1cc32b03..f7a1dadaa95f 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -23,6 +23,25 @@ chosen { - stdout-path = "serial0"; - }; - -+ vcc_5v0: regulator-vcc-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc4v0: regulator-vcc4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -91,6 +110,118 @@ &i2c8 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_cfg>; - status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <&vcc4v0>; -+ vin2-supply = <&vcc4v0>; -+ vin3-supply = <&vcc4v0>; -+ vin4-supply = <&vcc4v0>; -+ vin5-supply = <&vcc4v0>; -+ vin6-supply = <&vcc4v0>; -+ aldoin-supply = <&vcc4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4_3v3: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ /* not connected */ -+ }; -+ -+ aldo3 { -+ /* not connected */ -+ }; -+ -+ aldo4 { -+ /* not connected */ -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ /* not connected */ -+ }; -+ -+ dldo3 { -+ /* not connected */ -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ /* not connected */ -+ }; -+ }; -+ }; - }; - - &uart0 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0346-UPSTREAM-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux-lts/0346-UPSTREAM-riscv-dts-spacemit-Add-PDMA-controller-node.patch new file mode 100644 index 0000000000..8a11de676f --- /dev/null +++ b/SPECS/linux-lts/0346-UPSTREAM-riscv-dts-spacemit-Add-PDMA-controller-node.patch @@ -0,0 +1,50 @@ +From 3f07b7f3337da5b321d0c0c16c56aad0a3d46f7e Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Mon, 18 May 2026 11:32:44 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add PDMA controller node + for K3 SoC + +Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. +The PDMA controller provides general-purpose DMA capabilities for various +peripheral devices across the system to offload CPU data transfers. + +Unlike the previous K1 SoC, where some DMA masters had memory addressing +limitations (e.g. restricted to the 0-4GB space) requiring a dedicated +dma-bus with dma-ranges to restrict memory allocations, the K3 DMA masters +have full memory addressing capabilities. Therefore, the PDMA node is now +instantiated directly under the main soc bus. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Yixun Lan +(cherry picked from commit 3f47ca8bb3c3f4a71688451a0cb7350d3e1e1059) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 815debd16409..01124ff429a2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -555,6 +555,17 @@ gmac2_axi_setup: stmmac-axi-config { + }; + }; + ++ pdma: dma-controller@d4000000 { ++ compatible = "spacemit,k3-pdma"; ++ reg = <0x0 0xd4000000 0x0 0x4000>; ++ clocks = <&syscon_apmu CLK_APMU_DMA>; ++ resets = <&syscon_apmu RESET_APMU_DMA>; ++ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; ++ dma-channels = <16>; ++ #dma-cells = <1>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@d4010800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch deleted file mode 100644 index 2eece049ed..0000000000 --- a/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch +++ /dev/null @@ -1,140 +0,0 @@ -From be6360dcda59815d23e91c2273c7af8ee688b197 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:16 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on - OrangePi RV2 - -Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the -OrangePi RV2 board. - -The board utilizes a Genesys Logic GL3523 USB3.0 hub. - -Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and -PHY-related Device Tree nodes for the OrangePi RV2. - -Co-developed-by: Chukun Pan -Signed-off-by: Chukun Pan -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ - 1 file changed, 80 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index f7a1dadaa95f..3a829e3c9cbc 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -23,6 +23,16 @@ chosen { - stdout-path = "serial0"; - }; - -+ pcie_vcc3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - vcc_5v0: regulator-vcc-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; -@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { - vin-supply = <&vcc_5v0>; - }; - -+ vcc5v0_usb30: regulator-vcc5v0-usb30 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb30"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -54,6 +74,10 @@ led1 { - }; - }; - -+&combo_phy { -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; -@@ -224,8 +248,64 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie2 { -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vbus-supply = <&vcc5v0_usb30>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb5e3,610"; -+ reg = <0x1>; -+ peer-hub = <&hub_3_0>; -+ vdd-supply = <&vcc_5v0>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb5e3,620"; -+ reg = <0x2>; -+ peer-hub = <&hub_2_0>; -+ vdd-supply = <&vcc_5v0>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0347-UPSTREAM-dt-bindings-PCI-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux-lts/0347-UPSTREAM-dt-bindings-PCI-sophgo-Add-dma-coherent-pro.patch new file mode 100644 index 0000000000..d19a362af1 --- /dev/null +++ b/SPECS/linux-lts/0347-UPSTREAM-dt-bindings-PCI-sophgo-Add-dma-coherent-pro.patch @@ -0,0 +1,43 @@ +From 1040b342d286dc0a6a7e0ae1d58ba8702ed96d32 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:12:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: PCI: sophgo: Add dma-coherent + property for SG2042 + +Add dma-coherent as an allowed property in the SG2042 PCIe host controller +binding. SG2042's PCIe Root Complexes are cache-coherent with the CPU. + +Signed-off-by: Han Gao +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Acked-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260331171248.973014-2-gaohan@iscas.ac.cn +(cherry picked from commit c6d51515ee0b79a52b7e532b6b20067fa0cec96f) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +index f8b7ca57fff1..ab482488b047 100644 +--- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml ++++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +@@ -30,6 +30,8 @@ properties: + device-id: + const: 0x2042 + ++ dma-coherent: true ++ + msi-parent: true + + allOf: +@@ -60,5 +62,6 @@ examples: + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch deleted file mode 100644 index ec194d2c76..0000000000 --- a/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 35352343154bd3b77a7ce708b33610ead4fa645b Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:41 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA - compatible string - -Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. - -While the K3 PDMA IP reuses most of the design found on the earlier -K1 SoC, a new compatible string is required because the DRCMR -(DMA Request/Command Register) base address for extended DMA request -numbers (>= 64) differs from the K1 implementation. - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -index ec06235baf5c..62ce6d81526b 100644 ---- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -+++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -@@ -14,7 +14,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-pdma -+ enum: -+ - spacemit,k1-pdma -+ - spacemit,k3-pdma - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0348-UPSTREAM-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux-lts/0348-UPSTREAM-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch new file mode 100644 index 0000000000..4c4b3c944b --- /dev/null +++ b/SPECS/linux-lts/0348-UPSTREAM-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch @@ -0,0 +1,61 @@ +From 051562e4456c9fc4ee03ac5d0f4cbfd785d943c0 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:12:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Add dma-coherent to SG2042 + PCIe controllers + +SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all +four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent +so the kernel uses coherent DMA mappings instead of non-coherent bounce +buffering. + +Cc: stable@vger.kernel.org +Signed-off-by: Han Gao +Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit 2647eabde8de748ee2c9a2816615d4af3bd4bf9d) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index 9fddf3f0b3b9..3af770549742 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch deleted file mode 100644 index 2671371cc9..0000000000 --- a/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 086a8550aad82551854f105777656e655e68512f Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:42 +0800 -Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access - with helper function - -Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() -to support variable extended DRCMR base addresses across different PDMA -implementations, such as SpacemiT K3. - -Signed-off-by: Guodong Xu -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/dma/mmp_pdma.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - -diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c -index d12e729ee12c..6112369006ee 100644 ---- a/drivers/dma/mmp_pdma.c -+++ b/drivers/dma/mmp_pdma.c -@@ -51,7 +51,9 @@ - #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ - #define DCSR_EORINTR BIT(9) /* The end of Receive */ - --#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) -+#define DRCMR_BASE 0x0100 -+#define DRCMR_EXT_BASE_DEFAULT 0x1100 -+#define DRCMR_REQ_LIMIT 64 - #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ - #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ - -@@ -154,6 +156,7 @@ struct mmp_pdma_phy { - * @run_bits: Control bits in DCSR register for channel start/stop - * @dma_width: DMA addressing width in bits (32 or 64). Determines the - * DMA mask capability of the controller hardware. -+ * @drcmr_ext_base: Base DRCMR address for extended requests - */ - struct mmp_pdma_ops { - /* Hardware Register Operations */ -@@ -174,6 +177,7 @@ struct mmp_pdma_ops { - /* Controller Configuration */ - u32 run_bits; - u32 dma_width; -+ u32 drcmr_ext_base; - }; - - struct mmp_pdma_device { -@@ -195,6 +199,13 @@ struct mmp_pdma_device { - #define to_mmp_pdma_dev(dmadev) \ - container_of(dmadev, struct mmp_pdma_device, device) - -+static u32 mmp_pdma_get_drcmr(struct mmp_pdma_device *pdev, u32 drcmr) -+{ -+ if (drcmr < DRCMR_REQ_LIMIT) -+ return DRCMR_BASE + (drcmr << 2); -+ return pdev->ops->drcmr_ext_base + ((drcmr - DRCMR_REQ_LIMIT) << 2); -+} -+ - /* For 32-bit PDMA */ - static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) - { -@@ -301,7 +312,7 @@ static void enable_chan(struct mmp_pdma_phy *phy) - - pdev = to_mmp_pdma_dev(phy->vchan->chan.device); - -- reg = DRCMR(phy->vchan->drcmr); -+ reg = mmp_pdma_get_drcmr(pdev, phy->vchan->drcmr); - writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); - - dalgn = readl(phy->base + DALGN); -@@ -437,7 +448,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) - return; - - /* clear the channel mapping in DRCMR */ -- reg = DRCMR(pchan->drcmr); -+ reg = mmp_pdma_get_drcmr(pdev, pchan->drcmr); - writel(0, pchan->phy->base + reg); - - spin_lock_irqsave(&pdev->phy_lock, flags); -@@ -1179,6 +1190,7 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = { - .get_desc_dst_addr = get_desc_dst_addr_32, - .run_bits = (DCSR_RUN), - .dma_width = 32, -+ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - - static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { -@@ -1192,6 +1204,7 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { - .get_desc_dst_addr = get_desc_dst_addr_64, - .run_bits = (DCSR_RUN | DCSR_LPAEEN), - .dma_width = 64, -+ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - - static const struct of_device_id mmp_pdma_dt_ids[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0349-UPSTREAM-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux-lts/0349-UPSTREAM-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch new file mode 100644 index 0000000000..0e96eb7e06 --- /dev/null +++ b/SPECS/linux-lts/0349-UPSTREAM-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch @@ -0,0 +1,771 @@ +From e77a20759db98180b55de00bfcfdcc48f79fcbf2 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 26 Apr 2026 09:34:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2044: use hex for CPU + unit address + +Previous the CPU unit address cpu of sg2044 use decimal, it is +not following the general convention for unit addresses of the +OF. Convent the unit address to hex to resolve this problem. + +The introduces a small change for the CPU node name, but it should +nothing since there is no direct full-path reference to these +CPU nodes. + +Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") +Reviewed-by: Chen Wang +Reviewed-by: Guo Ren +Link: https://patch.msgid.link/20260426013449.694435-2-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit 207cbc477406a72952e27ace2eadbae55164f129) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- + 1 file changed, 118 insertions(+), 118 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +index 3135409c2149..f66a382c95bd 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +@@ -14,7 +14,7 @@ cpus { + + cpu0: cpu@0 { + compatible = "thead,c920", "riscv"; +- reg = <0>; ++ reg = <0x0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { + + cpu1: cpu@1 { + compatible = "thead,c920", "riscv"; +- reg = <1>; ++ reg = <0x1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { + + cpu2: cpu@2 { + compatible = "thead,c920", "riscv"; +- reg = <2>; ++ reg = <0x2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { + + cpu3: cpu@3 { + compatible = "thead,c920", "riscv"; +- reg = <3>; ++ reg = <0x3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { + + cpu4: cpu@4 { + compatible = "thead,c920", "riscv"; +- reg = <4>; ++ reg = <0x4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { + + cpu5: cpu@5 { + compatible = "thead,c920", "riscv"; +- reg = <5>; ++ reg = <0x5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { + + cpu6: cpu@6 { + compatible = "thead,c920", "riscv"; +- reg = <6>; ++ reg = <0x6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { + + cpu7: cpu@7 { + compatible = "thead,c920", "riscv"; +- reg = <7>; ++ reg = <0x7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { + + cpu8: cpu@8 { + compatible = "thead,c920", "riscv"; +- reg = <8>; ++ reg = <0x8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { + + cpu9: cpu@9 { + compatible = "thead,c920", "riscv"; +- reg = <9>; ++ reg = <0x9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { + }; + }; + +- cpu10: cpu@10 { ++ cpu10: cpu@a { + compatible = "thead,c920", "riscv"; +- reg = <10>; ++ reg = <0xa>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { + }; + }; + +- cpu11: cpu@11 { ++ cpu11: cpu@b { + compatible = "thead,c920", "riscv"; +- reg = <11>; ++ reg = <0xb>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { + }; + }; + +- cpu12: cpu@12 { ++ cpu12: cpu@c { + compatible = "thead,c920", "riscv"; +- reg = <12>; ++ reg = <0xc>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { + }; + }; + +- cpu13: cpu@13 { ++ cpu13: cpu@d { + compatible = "thead,c920", "riscv"; +- reg = <13>; ++ reg = <0xd>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { + }; + }; + +- cpu14: cpu@14 { ++ cpu14: cpu@e { + compatible = "thead,c920", "riscv"; +- reg = <14>; ++ reg = <0xe>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { + }; + }; + +- cpu15: cpu@15 { ++ cpu15: cpu@f { + compatible = "thead,c920", "riscv"; +- reg = <15>; ++ reg = <0xf>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { + }; + }; + +- cpu16: cpu@16 { ++ cpu16: cpu@10 { + compatible = "thead,c920", "riscv"; +- reg = <16>; ++ reg = <0x10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { + }; + }; + +- cpu17: cpu@17 { ++ cpu17: cpu@11 { + compatible = "thead,c920", "riscv"; +- reg = <17>; ++ reg = <0x11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { + }; + }; + +- cpu18: cpu@18 { ++ cpu18: cpu@12 { + compatible = "thead,c920", "riscv"; +- reg = <18>; ++ reg = <0x12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { + }; + }; + +- cpu19: cpu@19 { ++ cpu19: cpu@13 { + compatible = "thead,c920", "riscv"; +- reg = <19>; ++ reg = <0x13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { + }; + }; + +- cpu20: cpu@20 { ++ cpu20: cpu@14 { + compatible = "thead,c920", "riscv"; +- reg = <20>; ++ reg = <0x14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { + }; + }; + +- cpu21: cpu@21 { ++ cpu21: cpu@15 { + compatible = "thead,c920", "riscv"; +- reg = <21>; ++ reg = <0x15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { + }; + }; + +- cpu22: cpu@22 { ++ cpu22: cpu@16 { + compatible = "thead,c920", "riscv"; +- reg = <22>; ++ reg = <0x16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { + }; + }; + +- cpu23: cpu@23 { ++ cpu23: cpu@17 { + compatible = "thead,c920", "riscv"; +- reg = <23>; ++ reg = <0x17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { + }; + }; + +- cpu24: cpu@24 { ++ cpu24: cpu@18 { + compatible = "thead,c920", "riscv"; +- reg = <24>; ++ reg = <0x18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { + }; + }; + +- cpu25: cpu@25 { ++ cpu25: cpu@19 { + compatible = "thead,c920", "riscv"; +- reg = <25>; ++ reg = <0x19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { + }; + }; + +- cpu26: cpu@26 { ++ cpu26: cpu@1a { + compatible = "thead,c920", "riscv"; +- reg = <26>; ++ reg = <0x1a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { + }; + }; + +- cpu27: cpu@27 { ++ cpu27: cpu@1b { + compatible = "thead,c920", "riscv"; +- reg = <27>; ++ reg = <0x1b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { + }; + }; + +- cpu28: cpu@28 { ++ cpu28: cpu@1c { + compatible = "thead,c920", "riscv"; +- reg = <28>; ++ reg = <0x1c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { + }; + }; + +- cpu29: cpu@29 { ++ cpu29: cpu@1d { + compatible = "thead,c920", "riscv"; +- reg = <29>; ++ reg = <0x1d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { + }; + }; + +- cpu30: cpu@30 { ++ cpu30: cpu@1e { + compatible = "thead,c920", "riscv"; +- reg = <30>; ++ reg = <0x1e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { + }; + }; + +- cpu31: cpu@31 { ++ cpu31: cpu@1f { + compatible = "thead,c920", "riscv"; +- reg = <31>; ++ reg = <0x1f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { + }; + }; + +- cpu32: cpu@32 { ++ cpu32: cpu@20 { + compatible = "thead,c920", "riscv"; +- reg = <32>; ++ reg = <0x20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { + }; + }; + +- cpu33: cpu@33 { ++ cpu33: cpu@21 { + compatible = "thead,c920", "riscv"; +- reg = <33>; ++ reg = <0x21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { + }; + }; + +- cpu34: cpu@34 { ++ cpu34: cpu@22 { + compatible = "thead,c920", "riscv"; +- reg = <34>; ++ reg = <0x22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { + }; + }; + +- cpu35: cpu@35 { ++ cpu35: cpu@23 { + compatible = "thead,c920", "riscv"; +- reg = <35>; ++ reg = <0x23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { + }; + }; + +- cpu36: cpu@36 { ++ cpu36: cpu@24 { + compatible = "thead,c920", "riscv"; +- reg = <36>; ++ reg = <0x24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { + }; + }; + +- cpu37: cpu@37 { ++ cpu37: cpu@25 { + compatible = "thead,c920", "riscv"; +- reg = <37>; ++ reg = <0x25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { + }; + }; + +- cpu38: cpu@38 { ++ cpu38: cpu@26 { + compatible = "thead,c920", "riscv"; +- reg = <38>; ++ reg = <0x26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { + }; + }; + +- cpu39: cpu@39 { ++ cpu39: cpu@27 { + compatible = "thead,c920", "riscv"; +- reg = <39>; ++ reg = <0x27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { + }; + }; + +- cpu40: cpu@40 { ++ cpu40: cpu@28 { + compatible = "thead,c920", "riscv"; +- reg = <40>; ++ reg = <0x28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { + }; + }; + +- cpu41: cpu@41 { ++ cpu41: cpu@29 { + compatible = "thead,c920", "riscv"; +- reg = <41>; ++ reg = <0x29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { + }; + }; + +- cpu42: cpu@42 { ++ cpu42: cpu@2a { + compatible = "thead,c920", "riscv"; +- reg = <42>; ++ reg = <0x2a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { + }; + }; + +- cpu43: cpu@43 { ++ cpu43: cpu@2b { + compatible = "thead,c920", "riscv"; +- reg = <43>; ++ reg = <0x2b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { + }; + }; + +- cpu44: cpu@44 { ++ cpu44: cpu@2c { + compatible = "thead,c920", "riscv"; +- reg = <44>; ++ reg = <0x2c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { + }; + }; + +- cpu45: cpu@45 { ++ cpu45: cpu@2d { + compatible = "thead,c920", "riscv"; +- reg = <45>; ++ reg = <0x2d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { + }; + }; + +- cpu46: cpu@46 { ++ cpu46: cpu@2e { + compatible = "thead,c920", "riscv"; +- reg = <46>; ++ reg = <0x2e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { + }; + }; + +- cpu47: cpu@47 { ++ cpu47: cpu@2f { + compatible = "thead,c920", "riscv"; +- reg = <47>; ++ reg = <0x2f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { + }; + }; + +- cpu48: cpu@48 { ++ cpu48: cpu@30 { + compatible = "thead,c920", "riscv"; +- reg = <48>; ++ reg = <0x30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { + }; + }; + +- cpu49: cpu@49 { ++ cpu49: cpu@31 { + compatible = "thead,c920", "riscv"; +- reg = <49>; ++ reg = <0x31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { + }; + }; + +- cpu50: cpu@50 { ++ cpu50: cpu@32 { + compatible = "thead,c920", "riscv"; +- reg = <50>; ++ reg = <0x32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { + }; + }; + +- cpu51: cpu@51 { ++ cpu51: cpu@33 { + compatible = "thead,c920", "riscv"; +- reg = <51>; ++ reg = <0x33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { + }; + }; + +- cpu52: cpu@52 { ++ cpu52: cpu@34 { + compatible = "thead,c920", "riscv"; +- reg = <52>; ++ reg = <0x34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { + }; + }; + +- cpu53: cpu@53 { ++ cpu53: cpu@35 { + compatible = "thead,c920", "riscv"; +- reg = <53>; ++ reg = <0x35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { + }; + }; + +- cpu54: cpu@54 { ++ cpu54: cpu@36 { + compatible = "thead,c920", "riscv"; +- reg = <54>; ++ reg = <0x36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { + }; + }; + +- cpu55: cpu@55 { ++ cpu55: cpu@37 { + compatible = "thead,c920", "riscv"; +- reg = <55>; ++ reg = <0x37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { + }; + }; + +- cpu56: cpu@56 { ++ cpu56: cpu@38 { + compatible = "thead,c920", "riscv"; +- reg = <56>; ++ reg = <0x38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { + }; + }; + +- cpu57: cpu@57 { ++ cpu57: cpu@39 { + compatible = "thead,c920", "riscv"; +- reg = <57>; ++ reg = <0x39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { + }; + }; + +- cpu58: cpu@58 { ++ cpu58: cpu@3a { + compatible = "thead,c920", "riscv"; +- reg = <58>; ++ reg = <0x3a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { + }; + }; + +- cpu59: cpu@59 { ++ cpu59: cpu@3b { + compatible = "thead,c920", "riscv"; +- reg = <59>; ++ reg = <0x3b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { + }; + }; + +- cpu60: cpu@60 { ++ cpu60: cpu@3c { + compatible = "thead,c920", "riscv"; +- reg = <60>; ++ reg = <0x3c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { + }; + }; + +- cpu61: cpu@61 { ++ cpu61: cpu@3d { + compatible = "thead,c920", "riscv"; +- reg = <61>; ++ reg = <0x3d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { + }; + }; + +- cpu62: cpu@62 { ++ cpu62: cpu@3e { + compatible = "thead,c920", "riscv"; +- reg = <62>; ++ reg = <0x3e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { + }; + }; + +- cpu63: cpu@63 { ++ cpu63: cpu@3f { + compatible = "thead,c920", "riscv"; +- reg = <63>; ++ reg = <0x3f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch deleted file mode 100644 index db3d534951..0000000000 --- a/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch +++ /dev/null @@ -1,63 +0,0 @@ -From e077c02ed73be7f8782ceacc9a2f7dd9396857b0 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:43 +0800 -Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 support - -SpacemiT K3 reuses most of the PDMA IP design found on K1, with one -difference being the extended DRCMR base address. Add "spacemit,k3-pdma" -compatible string and define a new mmp_pdma_ops for K3 PDMA. - -Signed-off-by: Guodong Xu -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/dma/mmp_pdma.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c -index 6112369006ee..386e85cd4882 100644 ---- a/drivers/dma/mmp_pdma.c -+++ b/drivers/dma/mmp_pdma.c -@@ -52,6 +52,7 @@ - #define DCSR_EORINTR BIT(9) /* The end of Receive */ - - #define DRCMR_BASE 0x0100 -+#define DRCMR_EXT_BASE_K3 0x1000 - #define DRCMR_EXT_BASE_DEFAULT 0x1100 - #define DRCMR_REQ_LIMIT 64 - #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ -@@ -1207,6 +1208,20 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { - .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - -+static const struct mmp_pdma_ops spacemit_k3_pdma_ops = { -+ .write_next_addr = write_next_addr_64, -+ .read_src_addr = read_src_addr_64, -+ .read_dst_addr = read_dst_addr_64, -+ .set_desc_next_addr = set_desc_next_addr_64, -+ .set_desc_src_addr = set_desc_src_addr_64, -+ .set_desc_dst_addr = set_desc_dst_addr_64, -+ .get_desc_src_addr = get_desc_src_addr_64, -+ .get_desc_dst_addr = get_desc_dst_addr_64, -+ .run_bits = (DCSR_RUN | DCSR_LPAEEN | DCSR_EORIRQEN | DCSR_EORSTOPEN), -+ .dma_width = 64, -+ .drcmr_ext_base = DRCMR_EXT_BASE_K3, -+}; -+ - static const struct of_device_id mmp_pdma_dt_ids[] = { - { - .compatible = "marvell,pdma-1.0", -@@ -1214,6 +1229,9 @@ static const struct of_device_id mmp_pdma_dt_ids[] = { - }, { - .compatible = "spacemit,k1-pdma", - .data = &spacemit_k1_pdma_ops -+ }, { -+ .compatible = "spacemit,k3-pdma", -+ .data = &spacemit_k3_pdma_ops - }, { - /* sentinel */ - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0350-UPSTREAM-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux-lts/0350-UPSTREAM-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch new file mode 100644 index 0000000000..6484dee47a --- /dev/null +++ b/SPECS/linux-lts/0350-UPSTREAM-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch @@ -0,0 +1,1098 @@ +From a2a2a77e5257e95499bd89302751e6e9b3edec32 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 26 Apr 2026 09:34:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2042: use hex for CPU + unit address + +Previous the CPU unit address cpu of sg2042 use decimal, it is +not following the general convention for unit addresses of the +OF. Convent the unit address to hex to resolve this problem. + +The introduces a small change for the CPU node name, but it should +affect nothing since there is no direct full-path reference to +these CPU nodes. + +Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") +Tested-by: Chen Wang # Pioneerbox. +Reviewed-by: Guo Ren +Reviewed-by: Chen Wang +Acked-by: Conor Dooley +Tested-by: Chen Wang on Pioneerbox. +Link: https://patch.msgid.link/20260426013449.694435-3-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit a7e658907686528fe06a11828b04a3e42df9ef18) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- + 1 file changed, 118 insertions(+), 118 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +index 509488eee432..fd8906b313d2 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +@@ -263,7 +263,7 @@ cpu0: cpu@0 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <0>; ++ reg = <0x0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -291,7 +291,7 @@ cpu1: cpu@1 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <1>; ++ reg = <0x1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -319,7 +319,7 @@ cpu2: cpu@2 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <2>; ++ reg = <0x2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -347,7 +347,7 @@ cpu3: cpu@3 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <3>; ++ reg = <0x3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -375,7 +375,7 @@ cpu4: cpu@4 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <4>; ++ reg = <0x4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -403,7 +403,7 @@ cpu5: cpu@5 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <5>; ++ reg = <0x5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -431,7 +431,7 @@ cpu6: cpu@6 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <6>; ++ reg = <0x6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -459,7 +459,7 @@ cpu7: cpu@7 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <7>; ++ reg = <0x7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -487,7 +487,7 @@ cpu8: cpu@8 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <8>; ++ reg = <0x8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -515,7 +515,7 @@ cpu9: cpu@9 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <9>; ++ reg = <0x9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { + }; + }; + +- cpu10: cpu@10 { ++ cpu10: cpu@a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -543,7 +543,7 @@ cpu10: cpu@10 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <10>; ++ reg = <0xa>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { + }; + }; + +- cpu11: cpu@11 { ++ cpu11: cpu@b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -571,7 +571,7 @@ cpu11: cpu@11 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <11>; ++ reg = <0xb>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { + }; + }; + +- cpu12: cpu@12 { ++ cpu12: cpu@c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -599,7 +599,7 @@ cpu12: cpu@12 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <12>; ++ reg = <0xc>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { + }; + }; + +- cpu13: cpu@13 { ++ cpu13: cpu@d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -627,7 +627,7 @@ cpu13: cpu@13 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <13>; ++ reg = <0xd>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { + }; + }; + +- cpu14: cpu@14 { ++ cpu14: cpu@e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -655,7 +655,7 @@ cpu14: cpu@14 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <14>; ++ reg = <0xe>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { + }; + }; + +- cpu15: cpu@15 { ++ cpu15: cpu@f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -683,7 +683,7 @@ cpu15: cpu@15 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <15>; ++ reg = <0xf>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { + }; + }; + +- cpu16: cpu@16 { ++ cpu16: cpu@10 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -711,7 +711,7 @@ cpu16: cpu@16 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <16>; ++ reg = <0x10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { + }; + }; + +- cpu17: cpu@17 { ++ cpu17: cpu@11 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -739,7 +739,7 @@ cpu17: cpu@17 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <17>; ++ reg = <0x11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { + }; + }; + +- cpu18: cpu@18 { ++ cpu18: cpu@12 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -767,7 +767,7 @@ cpu18: cpu@18 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <18>; ++ reg = <0x12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { + }; + }; + +- cpu19: cpu@19 { ++ cpu19: cpu@13 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -795,7 +795,7 @@ cpu19: cpu@19 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <19>; ++ reg = <0x13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { + }; + }; + +- cpu20: cpu@20 { ++ cpu20: cpu@14 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -823,7 +823,7 @@ cpu20: cpu@20 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <20>; ++ reg = <0x14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { + }; + }; + +- cpu21: cpu@21 { ++ cpu21: cpu@15 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -851,7 +851,7 @@ cpu21: cpu@21 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <21>; ++ reg = <0x15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { + }; + }; + +- cpu22: cpu@22 { ++ cpu22: cpu@16 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -879,7 +879,7 @@ cpu22: cpu@22 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <22>; ++ reg = <0x16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { + }; + }; + +- cpu23: cpu@23 { ++ cpu23: cpu@17 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -907,7 +907,7 @@ cpu23: cpu@23 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <23>; ++ reg = <0x17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { + }; + }; + +- cpu24: cpu@24 { ++ cpu24: cpu@18 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -935,7 +935,7 @@ cpu24: cpu@24 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <24>; ++ reg = <0x18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { + }; + }; + +- cpu25: cpu@25 { ++ cpu25: cpu@19 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -963,7 +963,7 @@ cpu25: cpu@25 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <25>; ++ reg = <0x19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { + }; + }; + +- cpu26: cpu@26 { ++ cpu26: cpu@1a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -991,7 +991,7 @@ cpu26: cpu@26 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <26>; ++ reg = <0x1a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { + }; + }; + +- cpu27: cpu@27 { ++ cpu27: cpu@1b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1019,7 +1019,7 @@ cpu27: cpu@27 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <27>; ++ reg = <0x1b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { + }; + }; + +- cpu28: cpu@28 { ++ cpu28: cpu@1c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1047,7 +1047,7 @@ cpu28: cpu@28 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <28>; ++ reg = <0x1c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { + }; + }; + +- cpu29: cpu@29 { ++ cpu29: cpu@1d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1075,7 +1075,7 @@ cpu29: cpu@29 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <29>; ++ reg = <0x1d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { + }; + }; + +- cpu30: cpu@30 { ++ cpu30: cpu@1e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1103,7 +1103,7 @@ cpu30: cpu@30 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <30>; ++ reg = <0x1e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { + }; + }; + +- cpu31: cpu@31 { ++ cpu31: cpu@1f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1131,7 +1131,7 @@ cpu31: cpu@31 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <31>; ++ reg = <0x1f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { + }; + }; + +- cpu32: cpu@32 { ++ cpu32: cpu@20 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1159,7 +1159,7 @@ cpu32: cpu@32 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <32>; ++ reg = <0x20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { + }; + }; + +- cpu33: cpu@33 { ++ cpu33: cpu@21 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1187,7 +1187,7 @@ cpu33: cpu@33 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <33>; ++ reg = <0x21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { + }; + }; + +- cpu34: cpu@34 { ++ cpu34: cpu@22 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1215,7 +1215,7 @@ cpu34: cpu@34 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <34>; ++ reg = <0x22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { + }; + }; + +- cpu35: cpu@35 { ++ cpu35: cpu@23 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1243,7 +1243,7 @@ cpu35: cpu@35 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <35>; ++ reg = <0x23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { + }; + }; + +- cpu36: cpu@36 { ++ cpu36: cpu@24 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1271,7 +1271,7 @@ cpu36: cpu@36 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <36>; ++ reg = <0x24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { + }; + }; + +- cpu37: cpu@37 { ++ cpu37: cpu@25 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1299,7 +1299,7 @@ cpu37: cpu@37 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <37>; ++ reg = <0x25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { + }; + }; + +- cpu38: cpu@38 { ++ cpu38: cpu@26 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1327,7 +1327,7 @@ cpu38: cpu@38 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <38>; ++ reg = <0x26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { + }; + }; + +- cpu39: cpu@39 { ++ cpu39: cpu@27 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1355,7 +1355,7 @@ cpu39: cpu@39 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <39>; ++ reg = <0x27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { + }; + }; + +- cpu40: cpu@40 { ++ cpu40: cpu@28 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1383,7 +1383,7 @@ cpu40: cpu@40 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <40>; ++ reg = <0x28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { + }; + }; + +- cpu41: cpu@41 { ++ cpu41: cpu@29 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1411,7 +1411,7 @@ cpu41: cpu@41 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <41>; ++ reg = <0x29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { + }; + }; + +- cpu42: cpu@42 { ++ cpu42: cpu@2a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1439,7 +1439,7 @@ cpu42: cpu@42 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <42>; ++ reg = <0x2a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { + }; + }; + +- cpu43: cpu@43 { ++ cpu43: cpu@2b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1467,7 +1467,7 @@ cpu43: cpu@43 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <43>; ++ reg = <0x2b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { + }; + }; + +- cpu44: cpu@44 { ++ cpu44: cpu@2c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1495,7 +1495,7 @@ cpu44: cpu@44 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <44>; ++ reg = <0x2c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { + }; + }; + +- cpu45: cpu@45 { ++ cpu45: cpu@2d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1523,7 +1523,7 @@ cpu45: cpu@45 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <45>; ++ reg = <0x2d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { + }; + }; + +- cpu46: cpu@46 { ++ cpu46: cpu@2e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1551,7 +1551,7 @@ cpu46: cpu@46 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <46>; ++ reg = <0x2e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { + }; + }; + +- cpu47: cpu@47 { ++ cpu47: cpu@2f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1579,7 +1579,7 @@ cpu47: cpu@47 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <47>; ++ reg = <0x2f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { + }; + }; + +- cpu48: cpu@48 { ++ cpu48: cpu@30 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1607,7 +1607,7 @@ cpu48: cpu@48 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <48>; ++ reg = <0x30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { + }; + }; + +- cpu49: cpu@49 { ++ cpu49: cpu@31 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1635,7 +1635,7 @@ cpu49: cpu@49 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <49>; ++ reg = <0x31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { + }; + }; + +- cpu50: cpu@50 { ++ cpu50: cpu@32 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1663,7 +1663,7 @@ cpu50: cpu@50 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <50>; ++ reg = <0x32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { + }; + }; + +- cpu51: cpu@51 { ++ cpu51: cpu@33 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1691,7 +1691,7 @@ cpu51: cpu@51 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <51>; ++ reg = <0x33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { + }; + }; + +- cpu52: cpu@52 { ++ cpu52: cpu@34 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1719,7 +1719,7 @@ cpu52: cpu@52 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <52>; ++ reg = <0x34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { + }; + }; + +- cpu53: cpu@53 { ++ cpu53: cpu@35 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1747,7 +1747,7 @@ cpu53: cpu@53 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <53>; ++ reg = <0x35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { + }; + }; + +- cpu54: cpu@54 { ++ cpu54: cpu@36 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1775,7 +1775,7 @@ cpu54: cpu@54 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <54>; ++ reg = <0x36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { + }; + }; + +- cpu55: cpu@55 { ++ cpu55: cpu@37 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1803,7 +1803,7 @@ cpu55: cpu@55 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <55>; ++ reg = <0x37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { + }; + }; + +- cpu56: cpu@56 { ++ cpu56: cpu@38 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1831,7 +1831,7 @@ cpu56: cpu@56 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <56>; ++ reg = <0x38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { + }; + }; + +- cpu57: cpu@57 { ++ cpu57: cpu@39 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1859,7 +1859,7 @@ cpu57: cpu@57 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <57>; ++ reg = <0x39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { + }; + }; + +- cpu58: cpu@58 { ++ cpu58: cpu@3a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1887,7 +1887,7 @@ cpu58: cpu@58 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <58>; ++ reg = <0x3a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { + }; + }; + +- cpu59: cpu@59 { ++ cpu59: cpu@3b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1915,7 +1915,7 @@ cpu59: cpu@59 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <59>; ++ reg = <0x3b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { + }; + }; + +- cpu60: cpu@60 { ++ cpu60: cpu@3c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1943,7 +1943,7 @@ cpu60: cpu@60 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <60>; ++ reg = <0x3c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { + }; + }; + +- cpu61: cpu@61 { ++ cpu61: cpu@3d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1971,7 +1971,7 @@ cpu61: cpu@61 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <61>; ++ reg = <0x3d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { + }; + }; + +- cpu62: cpu@62 { ++ cpu62: cpu@3e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1999,7 +1999,7 @@ cpu62: cpu@62 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <62>; ++ reg = <0x3e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { + }; + }; + +- cpu63: cpu@63 { ++ cpu63: cpu@3f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -2027,7 +2027,7 @@ cpu63: cpu@63 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <63>; ++ reg = <0x3f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch deleted file mode 100644 index 3b955dda90..0000000000 --- a/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 21b7895de7539f827659bef3d905b99563ac4277 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Mon, 18 May 2026 11:32:44 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add PDMA controller node - for K3 SoC - -Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. -The PDMA controller provides general-purpose DMA capabilities for various -peripheral devices across the system to offload CPU data transfers. - -Unlike the previous K1 SoC, where some DMA masters had memory addressing -limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus -with dma-ranges to restrict memory allocations, the K3 DMA masters have -full memory addressing capabilities. Therefore, the PDMA node is now -instantiated directly under the main soc bus. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 815debd16409..81ad575f16a5 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -625,6 +625,18 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ -+ pdma: dma-controller@d4000000 { -+ compatible = "spacemit,k3-pdma"; -+ reg = <0x0 0xd4000000 0x0 0x4000>; -+ clocks = <&syscon_apmu CLK_APMU_DMA>; -+ resets = <&syscon_apmu RESET_APMU_DMA>; -+ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; -+ dma-channels = <16>; -+ #dma-cells = <1>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0351-UPSTREAM-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux-lts/0351-UPSTREAM-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch new file mode 100644 index 0000000000..c929d41c5d --- /dev/null +++ b/SPECS/linux-lts/0351-UPSTREAM-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch @@ -0,0 +1,43 @@ +From 59a46abf3b3bc582bb600ebdf795d8e31927ff02 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 8 Apr 2026 00:01:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: reduce SG2042 MSI count to + 16 + +The SG2042 MSI controller has one 32-bit doorbell register, and each bit +corresponds to an interrupt. At a glance, it seems that the MSI +controller can support 32 interrupts; however the PCI MSI capability +only supports 16-bit messages, which makes the high 16 interrupts +unusable in such way. + +Reduce the MSI count to 16 to prevent producing MSI message values that +cannot fit 16-bit integers. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Chen Wang +Tested-by: Chen Wang on Pioneerbox. +Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +(cherry picked from commit 903a9364e40563faf4730dc63ad7446246f494ff) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index 3af770549742..7eab0655f150 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { + reg-names = "clr", "doorbell"; + msi-controller; + #msi-cells = <0>; +- msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; ++ msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; + }; + + rpgate: clock-controller@7030010368 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch deleted file mode 100644 index 505c1fcf8b..0000000000 --- a/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch +++ /dev/null @@ -1,39 +0,0 @@ -From e45053fa3fb846fee16140a46bfca3810a696d3a Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:12:47 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent - property for SG2042 - -Add dma-coherent as an allowed property in the SG2042 PCIe host -controller binding. SG2042's PCIe root complexes are cache-coherent -with the CPU. - -Link: https://lore.kernel.org/r/20260331171248.973014-2-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -index f8b7ca57fff1..ab482488b047 100644 ---- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -@@ -30,6 +30,8 @@ properties: - device-id: - const: 0x2042 - -+ dma-coherent: true -+ - msi-parent: true - - allOf: -@@ -60,5 +62,6 @@ examples: - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0352-UPSTREAM-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux-lts/0352-UPSTREAM-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch new file mode 100644 index 0000000000..0f3e351bc2 --- /dev/null +++ b/SPECS/linux-lts/0352-UPSTREAM-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch @@ -0,0 +1,99 @@ +From a69ba2041927a2833c0f219d0d7c201b106b9096 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:46:50 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pwm: marvell,pxa-pwm: Add + SpacemiT K3 PWM support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 +generation, while the difference is that one additional bus clock is +added. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org +Signed-off-by: Uwe Kleine-König +(cherry picked from commit e7abbff5e8b2924a53b583e6d57804c6cad0ab81) +Signed-off-by: Han Gao +--- + .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- + 1 file changed, 38 insertions(+), 3 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +index 8df327e52810..f1422a401b6b 100644 +--- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml ++++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +@@ -15,7 +15,9 @@ allOf: + properties: + compatible: + contains: +- const: spacemit,k1-pwm ++ enum: ++ - spacemit,k1-pwm ++ - spacemit,k3-pwm + then: + properties: + "#pwm-cells": +@@ -26,6 +28,26 @@ allOf: + const: 1 + description: | + Used for specifying the period length in nanoseconds. ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - spacemit,k3-pwm ++ then: ++ required: ++ - clock-names ++ properties: ++ clocks: ++ minItems: 2 ++ clock-names: ++ minItems: 2 ++ else: ++ properties: ++ clocks: ++ maxItems: 1 ++ clock-names: ++ maxItems: 1 + + properties: + compatible: +@@ -36,7 +58,9 @@ properties: + - marvell,pxa168-pwm + - marvell,pxa910-pwm + - items: +- - const: spacemit,k1-pwm ++ - enum: ++ - spacemit,k1-pwm ++ - spacemit,k3-pwm + - const: marvell,pxa910-pwm + + reg: +@@ -47,7 +71,18 @@ properties: + description: Number of cells in a pwm specifier. + + clocks: +- maxItems: 1 ++ minItems: 1 ++ items: ++ - description: The function clock ++ - description: An optional bus clock ++ ++ clock-names: ++ minItems: 1 ++ maxItems: 2 ++ oneOf: ++ - items: ++ - const: func ++ - const: bus + + resets: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch deleted file mode 100644 index 59e22401d2..0000000000 --- a/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 4edb2b9deb6868de278295f9df339eb66e2dc5e6 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:12:48 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: Add dma-coherent to SG2042 - PCIe controllers - -SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all -four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent -so the kernel uses coherent DMA mappings instead of non-coherent bounce -buffering. - -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331171248.973014-3-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index 9fddf3f0b3b9..3af770549742 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0353-UPSTREAM-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux-lts/0353-UPSTREAM-pwm-pxa-Add-optional-bus-clock.patch new file mode 100644 index 0000000000..0b8d768f93 --- /dev/null +++ b/SPECS/linux-lts/0353-UPSTREAM-pwm-pxa-Add-optional-bus-clock.patch @@ -0,0 +1,52 @@ +From 3d75a58d454b0668263795bbfdaccf0587a36d08 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:46:51 +0000 +Subject: [RUYI PATCH] UPSTREAM: pwm: pxa: Add optional bus clock +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add one secondary optional bus clock for the PWM PXA driver, also keep it +compatible with old single clock. + +The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and +enable it during probe phase. + +Signed-off-by: Yixun Lan +Link: https://patch.msgid.link/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org +Signed-off-by: Uwe Kleine-König +(cherry picked from commit 74bca0f2d37f5fd9a4bd5378d9f9579e72038556) +Signed-off-by: Han Gao +--- + drivers/pwm/pwm-pxa.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c +index 0f5bdb0e395e..80d2fa10919f 100644 +--- a/drivers/pwm/pwm-pxa.c ++++ b/drivers/pwm/pwm-pxa.c +@@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) + const struct platform_device_id *id = platform_get_device_id(pdev); + struct pwm_chip *chip; + struct pxa_pwm_chip *pc; ++ struct clk *bus_clk; + struct device *dev = &pdev->dev; + struct reset_control *rst; + int ret = 0; +@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) + return PTR_ERR(chip); + pc = to_pxa_pwm_chip(chip); + +- pc->clk = devm_clk_get(dev, NULL); ++ bus_clk = devm_clk_get_optional_enabled(dev, "bus"); ++ if (IS_ERR(bus_clk)) ++ return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); ++ ++ /* Get named func clk if bus clock is valid */ ++ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); + if (IS_ERR(pc->clk)) + return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch deleted file mode 100644 index 54ce584981..0000000000 --- a/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 4d5cd4b1f6fe26dc668fffd055e5d01af826c026 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Tue, 31 Mar 2026 15:37:22 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for - systems with DRAM above 4GB - -On RISC-V platforms where the entire physical memory (DRAM) resides -above the 32-bit address space (i.e., above dma32_phys_limit), the -current SWIOTLB initialization logic fails. - -This patch addresses two interconnected issues on such platforms: - -1. Incorrect 32-bit DMA bounce assumption: -The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes -that a 32-bit DMA bounce buffer is required simply because the maximum -PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, -no memory exists below the limit to satisfy this allocation. Fix -this by adding a check to ensure `memblock_start_of_DRAM()` is actually -below the 32-bit limit before enforcing 32-bit SWIOTLB. - -2. kmalloc() bounce buffer allocation failure on non-coherent systems: -For non-coherent hardware, a bounce buffer is still mandatory for -cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. -Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating -from low memory, which fails completely when DRAM only exists in high -memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is -permitted to allocate this alignment buffer from high memory. - -With this patch, systems with non-coherent DMA and DRAM entirely above -4GB can successfully map the software IO TLB in high memory and boot -normally. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260331-fix-riscv-swiotlb-v1-1-74dd5e6be0f1@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 6533cc17825a..ac5bece70736 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -172,7 +172,9 @@ static void print_vm_layout(void) { } - - void __init arch_mm_preinit(void) - { -- bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit); -+ bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) && -+ memblock_start_of_DRAM() < dma32_phys_limit; -+ unsigned int swiotlb_flags = SWIOTLB_VERBOSE; - #ifdef CONFIG_FLATMEM - BUG_ON(!mem_map); - #endif /* CONFIG_FLATMEM */ -@@ -180,17 +182,21 @@ void __init arch_mm_preinit(void) - if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb && - dma_cache_alignment != 1) { - /* -- * If no bouncing needed for ZONE_DMA, allocate 1MB swiotlb -- * buffer per 1GB of RAM for kmalloc() bouncing on -- * non-coherent platforms. -+ * No 32-bit DMA bouncing needed (either all DRAM is within -+ * the 32-bit limit, or it all starts above it), but -+ * non-coherent hardware still requires cache-line-aligned -+ * bounce buffers for kmalloc(). Use SWIOTLB_ANY so that the -+ * buffer can be allocated from high memory when DRAM starts -+ * above dma32_phys_limit. Allocate ~1 MB per 1 GB of RAM. - */ - unsigned long size = - DIV_ROUND_UP(memblock_phys_mem_size(), 1024); - swiotlb_adjust_size(min(swiotlb_size_or_default(), size)); - swiotlb = true; -+ swiotlb_flags |= SWIOTLB_ANY; - } - -- swiotlb_init(swiotlb, SWIOTLB_VERBOSE); -+ swiotlb_init(swiotlb, swiotlb_flags); - - print_vm_layout(); - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0354-UPSTREAM-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux-lts/0354-UPSTREAM-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch new file mode 100644 index 0000000000..3042a262ab --- /dev/null +++ b/SPECS/linux-lts/0354-UPSTREAM-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch @@ -0,0 +1,48 @@ +From 8681df6aff6818f9e842a3a9ba4757f0cb4acdf1 Mon Sep 17 00:00:00 2001 +From: Chen Pei +Date: Sat, 6 Jun 2026 20:17:53 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: ftrace: select + HAVE_BUILDTIME_MCOUNT_SORT + +RISC-V already satisfies all prerequisites for build-time mcount sorting: +the sorttable host tool handles EM_RISCV in its machine-type dispatch, and +the __mcount_loc section entries are stored as direct virtual addresses in +the final vmlinux binary, so no relocation processing is required during +the sort step. + +Select HAVE_BUILDTIME_MCOUNT_SORT so that BUILDTIME_MCOUNT_SORT is +automatically enabled when DYNAMIC_FTRACE is configured. This allows +sorttable to sort the __mcount_loc section at link time, making the +run-time ftrace initialisation path skip the software sort and reducing +kernel startup overhead. + +Verified with CONFIG_FTRACE_SORT_STARTUP_TEST=y, which confirms that +the section produced by the build is already in ascending order: + + [ 0.000000] ftrace section at ffffffff81015a60 sorted properly + +Signed-off-by: Chen Pei +Tested-by: Guo Ren +Link: https://patch.msgid.link/20260409114736.907-1-cp0613@linux.alibaba.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 9fd44698b11dbdf4d29fdef0f0da25f320c13854) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 9c43346fabcd..4946ac7b6db1 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -150,6 +150,7 @@ config RISCV + select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD + select HAVE_ARCH_VMAP_STACK if MMU && 64BIT + select HAVE_ASM_MODVERSIONS ++ select HAVE_BUILDTIME_MCOUNT_SORT + select HAVE_CONTEXT_TRACKING_USER + select HAVE_DEBUG_KMEMLEAK + select HAVE_DMA_CONTIGUOUS if MMU +-- +2.53.0 + diff --git a/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch deleted file mode 100644 index 223d5a699f..0000000000 --- a/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 1e089bd4441c081e557a84db781ccfe5f79b5601 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:08 +0530 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add - vcc5v0_sys regulator for Banana Pi F3 - -Define the system 5V fixed regulator (vcc5v0_sys) supplied by the -DC input. As per the schematics, vcc5v0_sys is the input power source -for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators -to correctly reference vcc5v0_sys as their parent (vin-supply). - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-2-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 2a0caecd9a41..341d86a8f7ae 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -52,6 +52,16 @@ reg_dc_in: regulator-dc-in-12v { - regulator-always-on; - }; - -+ reg_vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ - reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; -@@ -68,6 +78,7 @@ regulator-usb3-vbus-5v { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; -+ vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -@@ -77,6 +88,7 @@ usb3_hub_5v: regulator-usb3-hub-5v { - regulator-name = "USB30_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0355-UPSTREAM-dts-spacemit-set-console-baud-rate-on-bpif3.patch b/SPECS/linux-lts/0355-UPSTREAM-dts-spacemit-set-console-baud-rate-on-bpif3.patch new file mode 100644 index 0000000000..efeea3b0be --- /dev/null +++ b/SPECS/linux-lts/0355-UPSTREAM-dts-spacemit-set-console-baud-rate-on-bpif3.patch @@ -0,0 +1,37 @@ +From 9f9a29f7d2c0237960ad9bac7e73e25fd16c64ec Mon Sep 17 00:00:00 2001 +From: Conor Dooley +Date: Thu, 30 Apr 2026 19:52:12 +0100 +Subject: [RUYI PATCH] UPSTREAM: dts: spacemit: set console baud rate on bpif3 + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +Suggested-by: Vivian Wang +Fixes: d60d57ab6b2a8 ("riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree") +Signed-off-by: Conor Dooley +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260430-reword-overstep-3be08b7eab25@spud +Signed-off-by: Yixun Lan +(cherry picked from commit 24c12ca43b12c104389d9a159207d0b25779d0af) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 9429189354d6..e20daa50a152 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -20,7 +20,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch deleted file mode 100644 index 5fda255af1..0000000000 --- a/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 9927a583ce5c19e8befcb7ed40a6238c53f79b35 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:09 +0530 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update - USB regulator on onboard usb and lable - -Update the USB regulator labels to align with the board schematics and -power hierarchy. This change renames the regulator to reg_5v_vbus and -its name to 5V_VBUS. Additionally, it fixes the vdd-supply references -for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point -to the 5V_VBUS input source as per the board schematics. - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-3-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 341d86a8f7ae..6c2a2e713121 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -72,9 +72,9 @@ reg_vcc_4v: regulator-vcc-4v { - vin-supply = <®_dc_in>; - }; - -- regulator-usb3-vbus-5v { -+ reg_5v_vbus: regulator-usb3-vbus-5v { - compatible = "regulator-fixed"; -- regulator-name = "USB30_VBUS"; -+ regulator-name = "5V_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; -@@ -406,7 +406,7 @@ &usb_dwc3 { - hub_2_0: hub@1 { - compatible = "usb2109,2817"; - reg = <0x1>; -- vdd-supply = <&usb3_hub_5v>; -+ vdd-supply = <®_5v_vbus>; - peer-hub = <&hub_3_0>; - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; -@@ -414,7 +414,7 @@ hub_2_0: hub@1 { - hub_3_0: hub@2 { - compatible = "usb2109,817"; - reg = <0x2>; -- vdd-supply = <&usb3_hub_5v>; -+ vdd-supply = <®_5v_vbus>; - peer-hub = <&hub_2_0>; - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0356-UPSTREAM-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux-lts/0356-UPSTREAM-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch new file mode 100644 index 0000000000..3ca90c180d --- /dev/null +++ b/SPECS/linux-lts/0356-UPSTREAM-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch @@ -0,0 +1,61 @@ +From 19ef70b8381d25c5d9091e65c6960a6d6f7fbd81 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 18 May 2026 18:00:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB3 on OrangePi + R2S + +Enable the DWC3 USB3.0 controller and its associated PHY on the +OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 +ports, but the USB2 ports are handled by a separate controller. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260518100030.2354606-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit c5ad6737df88bd3c3e83145edb25737cb19f9a1f) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index de75f6aac740..1ecc40749e5a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -21,6 +21,19 @@ aliases { + chosen { + stdout-path = "serial0"; + }; ++ ++ vcc5v0_usb: regulator-vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combo_phy { ++ status = "okay"; + }; + + &emmc { +@@ -90,3 +103,13 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ vbus-supply = <&vcc5v0_usb>; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch deleted file mode 100644 index a3dbb529e4..0000000000 --- a/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch +++ /dev/null @@ -1,52 +0,0 @@ -From c3e497dbbb78a87638bd90cab0bd7540fd683d89 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:10 +0530 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct - USB hub power hierarchy -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to -ensure the USB 3.0 stack is properly powered as per the schematics. -In addition, align the USB hub regulator with the board schematics -by renaming it to VCC5V0_HUB and marking it as regulator-always-on -to maintain power stability. - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-4-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 6c2a2e713121..b48a485f954b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -85,9 +85,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v { - - usb3_hub_5v: regulator-usb3-hub-5v { - compatible = "regulator-fixed"; -- regulator-name = "USB30_HUB"; -+ regulator-name = "VCC5V0_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ regulator-always-on; - vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; - enable-active-high; -@@ -401,6 +402,7 @@ &usb_dwc3 { - dr_mode = "host"; - #address-cells = <1>; - #size-cells = <0>; -+ vbus-supply = <&usb3_hub_5v>; - status = "okay"; - - hub_2_0: hub@1 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0357-UPSTREAM-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux-lts/0357-UPSTREAM-dts-riscv-spacemit-correct-32k-clock-freque.patch new file mode 100644 index 0000000000..8bcc27f67e --- /dev/null +++ b/SPECS/linux-lts/0357-UPSTREAM-dts-riscv-spacemit-correct-32k-clock-freque.patch @@ -0,0 +1,48 @@ +From 9d04d67bbe15d5b1dda5eac0ba8ec11c26b4ec0d Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:57:29 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: correct 32k clock + frequency + +The 32k oscillator's clock frequency is actually 32768Hz, so correct it. + +Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") +Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") +Link: https://patch.msgid.link/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3c350f6284d8ea5e7a9648241b2e9604f2262d42) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- + arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 2ed5cc24e505..cba160c5edc5 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -333,7 +333,7 @@ vctcxo_3m: clock-3m { + + osc_32k: clock-32k { + compatible = "fixed-clock"; +- clock-frequency = <32000>; ++ clock-frequency = <32768>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 01124ff429a2..9e3c005f7bdf 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { + + osc_32k: clock-32k { + compatible = "fixed-clock"; +- clock-frequency = <32000>; ++ clock-frequency = <32768>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch deleted file mode 100644 index 39245052d3..0000000000 --- a/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch +++ /dev/null @@ -1,769 +0,0 @@ -From a19f30eaeebdca312c928a1bd82a354ba9ce2e8e Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 26 Apr 2026 09:34:48 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU - unit address - -Previous the CPU unit address cpu of sg2044 use decimal, it is -not following the general convention for unit addresses of the -OF. Convent the unit address to hex to resolve this problem. - -The introduces a small change for the CPU node name, but it should -nothing since there is no direct full-path reference to these -CPU nodes. - -Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") -Signed-off-by: Inochi Amaoto -Reviewed-by: Chen Wang -Reviewed-by: Guo Ren -Link: https://lore.kernel.org/r/20260426013449.694435-2-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- - 1 file changed, 118 insertions(+), 118 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -index 3135409c2149..f66a382c95bd 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -@@ -14,7 +14,7 @@ cpus { - - cpu0: cpu@0 { - compatible = "thead,c920", "riscv"; -- reg = <0>; -+ reg = <0x0>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { - - cpu1: cpu@1 { - compatible = "thead,c920", "riscv"; -- reg = <1>; -+ reg = <0x1>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { - - cpu2: cpu@2 { - compatible = "thead,c920", "riscv"; -- reg = <2>; -+ reg = <0x2>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { - - cpu3: cpu@3 { - compatible = "thead,c920", "riscv"; -- reg = <3>; -+ reg = <0x3>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { - - cpu4: cpu@4 { - compatible = "thead,c920", "riscv"; -- reg = <4>; -+ reg = <0x4>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { - - cpu5: cpu@5 { - compatible = "thead,c920", "riscv"; -- reg = <5>; -+ reg = <0x5>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { - - cpu6: cpu@6 { - compatible = "thead,c920", "riscv"; -- reg = <6>; -+ reg = <0x6>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { - - cpu7: cpu@7 { - compatible = "thead,c920", "riscv"; -- reg = <7>; -+ reg = <0x7>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { - - cpu8: cpu@8 { - compatible = "thead,c920", "riscv"; -- reg = <8>; -+ reg = <0x8>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { - - cpu9: cpu@9 { - compatible = "thead,c920", "riscv"; -- reg = <9>; -+ reg = <0x9>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { - }; - }; - -- cpu10: cpu@10 { -+ cpu10: cpu@a { - compatible = "thead,c920", "riscv"; -- reg = <10>; -+ reg = <0xa>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { - }; - }; - -- cpu11: cpu@11 { -+ cpu11: cpu@b { - compatible = "thead,c920", "riscv"; -- reg = <11>; -+ reg = <0xb>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { - }; - }; - -- cpu12: cpu@12 { -+ cpu12: cpu@c { - compatible = "thead,c920", "riscv"; -- reg = <12>; -+ reg = <0xc>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { - }; - }; - -- cpu13: cpu@13 { -+ cpu13: cpu@d { - compatible = "thead,c920", "riscv"; -- reg = <13>; -+ reg = <0xd>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { - }; - }; - -- cpu14: cpu@14 { -+ cpu14: cpu@e { - compatible = "thead,c920", "riscv"; -- reg = <14>; -+ reg = <0xe>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { - }; - }; - -- cpu15: cpu@15 { -+ cpu15: cpu@f { - compatible = "thead,c920", "riscv"; -- reg = <15>; -+ reg = <0xf>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { - }; - }; - -- cpu16: cpu@16 { -+ cpu16: cpu@10 { - compatible = "thead,c920", "riscv"; -- reg = <16>; -+ reg = <0x10>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { - }; - }; - -- cpu17: cpu@17 { -+ cpu17: cpu@11 { - compatible = "thead,c920", "riscv"; -- reg = <17>; -+ reg = <0x11>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { - }; - }; - -- cpu18: cpu@18 { -+ cpu18: cpu@12 { - compatible = "thead,c920", "riscv"; -- reg = <18>; -+ reg = <0x12>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { - }; - }; - -- cpu19: cpu@19 { -+ cpu19: cpu@13 { - compatible = "thead,c920", "riscv"; -- reg = <19>; -+ reg = <0x13>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { - }; - }; - -- cpu20: cpu@20 { -+ cpu20: cpu@14 { - compatible = "thead,c920", "riscv"; -- reg = <20>; -+ reg = <0x14>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { - }; - }; - -- cpu21: cpu@21 { -+ cpu21: cpu@15 { - compatible = "thead,c920", "riscv"; -- reg = <21>; -+ reg = <0x15>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { - }; - }; - -- cpu22: cpu@22 { -+ cpu22: cpu@16 { - compatible = "thead,c920", "riscv"; -- reg = <22>; -+ reg = <0x16>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { - }; - }; - -- cpu23: cpu@23 { -+ cpu23: cpu@17 { - compatible = "thead,c920", "riscv"; -- reg = <23>; -+ reg = <0x17>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { - }; - }; - -- cpu24: cpu@24 { -+ cpu24: cpu@18 { - compatible = "thead,c920", "riscv"; -- reg = <24>; -+ reg = <0x18>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { - }; - }; - -- cpu25: cpu@25 { -+ cpu25: cpu@19 { - compatible = "thead,c920", "riscv"; -- reg = <25>; -+ reg = <0x19>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { - }; - }; - -- cpu26: cpu@26 { -+ cpu26: cpu@1a { - compatible = "thead,c920", "riscv"; -- reg = <26>; -+ reg = <0x1a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { - }; - }; - -- cpu27: cpu@27 { -+ cpu27: cpu@1b { - compatible = "thead,c920", "riscv"; -- reg = <27>; -+ reg = <0x1b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { - }; - }; - -- cpu28: cpu@28 { -+ cpu28: cpu@1c { - compatible = "thead,c920", "riscv"; -- reg = <28>; -+ reg = <0x1c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { - }; - }; - -- cpu29: cpu@29 { -+ cpu29: cpu@1d { - compatible = "thead,c920", "riscv"; -- reg = <29>; -+ reg = <0x1d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { - }; - }; - -- cpu30: cpu@30 { -+ cpu30: cpu@1e { - compatible = "thead,c920", "riscv"; -- reg = <30>; -+ reg = <0x1e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { - }; - }; - -- cpu31: cpu@31 { -+ cpu31: cpu@1f { - compatible = "thead,c920", "riscv"; -- reg = <31>; -+ reg = <0x1f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { - }; - }; - -- cpu32: cpu@32 { -+ cpu32: cpu@20 { - compatible = "thead,c920", "riscv"; -- reg = <32>; -+ reg = <0x20>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { - }; - }; - -- cpu33: cpu@33 { -+ cpu33: cpu@21 { - compatible = "thead,c920", "riscv"; -- reg = <33>; -+ reg = <0x21>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { - }; - }; - -- cpu34: cpu@34 { -+ cpu34: cpu@22 { - compatible = "thead,c920", "riscv"; -- reg = <34>; -+ reg = <0x22>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { - }; - }; - -- cpu35: cpu@35 { -+ cpu35: cpu@23 { - compatible = "thead,c920", "riscv"; -- reg = <35>; -+ reg = <0x23>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { - }; - }; - -- cpu36: cpu@36 { -+ cpu36: cpu@24 { - compatible = "thead,c920", "riscv"; -- reg = <36>; -+ reg = <0x24>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { - }; - }; - -- cpu37: cpu@37 { -+ cpu37: cpu@25 { - compatible = "thead,c920", "riscv"; -- reg = <37>; -+ reg = <0x25>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { - }; - }; - -- cpu38: cpu@38 { -+ cpu38: cpu@26 { - compatible = "thead,c920", "riscv"; -- reg = <38>; -+ reg = <0x26>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { - }; - }; - -- cpu39: cpu@39 { -+ cpu39: cpu@27 { - compatible = "thead,c920", "riscv"; -- reg = <39>; -+ reg = <0x27>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { - }; - }; - -- cpu40: cpu@40 { -+ cpu40: cpu@28 { - compatible = "thead,c920", "riscv"; -- reg = <40>; -+ reg = <0x28>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { - }; - }; - -- cpu41: cpu@41 { -+ cpu41: cpu@29 { - compatible = "thead,c920", "riscv"; -- reg = <41>; -+ reg = <0x29>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { - }; - }; - -- cpu42: cpu@42 { -+ cpu42: cpu@2a { - compatible = "thead,c920", "riscv"; -- reg = <42>; -+ reg = <0x2a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { - }; - }; - -- cpu43: cpu@43 { -+ cpu43: cpu@2b { - compatible = "thead,c920", "riscv"; -- reg = <43>; -+ reg = <0x2b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { - }; - }; - -- cpu44: cpu@44 { -+ cpu44: cpu@2c { - compatible = "thead,c920", "riscv"; -- reg = <44>; -+ reg = <0x2c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { - }; - }; - -- cpu45: cpu@45 { -+ cpu45: cpu@2d { - compatible = "thead,c920", "riscv"; -- reg = <45>; -+ reg = <0x2d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { - }; - }; - -- cpu46: cpu@46 { -+ cpu46: cpu@2e { - compatible = "thead,c920", "riscv"; -- reg = <46>; -+ reg = <0x2e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { - }; - }; - -- cpu47: cpu@47 { -+ cpu47: cpu@2f { - compatible = "thead,c920", "riscv"; -- reg = <47>; -+ reg = <0x2f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { - }; - }; - -- cpu48: cpu@48 { -+ cpu48: cpu@30 { - compatible = "thead,c920", "riscv"; -- reg = <48>; -+ reg = <0x30>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { - }; - }; - -- cpu49: cpu@49 { -+ cpu49: cpu@31 { - compatible = "thead,c920", "riscv"; -- reg = <49>; -+ reg = <0x31>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { - }; - }; - -- cpu50: cpu@50 { -+ cpu50: cpu@32 { - compatible = "thead,c920", "riscv"; -- reg = <50>; -+ reg = <0x32>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { - }; - }; - -- cpu51: cpu@51 { -+ cpu51: cpu@33 { - compatible = "thead,c920", "riscv"; -- reg = <51>; -+ reg = <0x33>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { - }; - }; - -- cpu52: cpu@52 { -+ cpu52: cpu@34 { - compatible = "thead,c920", "riscv"; -- reg = <52>; -+ reg = <0x34>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { - }; - }; - -- cpu53: cpu@53 { -+ cpu53: cpu@35 { - compatible = "thead,c920", "riscv"; -- reg = <53>; -+ reg = <0x35>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { - }; - }; - -- cpu54: cpu@54 { -+ cpu54: cpu@36 { - compatible = "thead,c920", "riscv"; -- reg = <54>; -+ reg = <0x36>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { - }; - }; - -- cpu55: cpu@55 { -+ cpu55: cpu@37 { - compatible = "thead,c920", "riscv"; -- reg = <55>; -+ reg = <0x37>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { - }; - }; - -- cpu56: cpu@56 { -+ cpu56: cpu@38 { - compatible = "thead,c920", "riscv"; -- reg = <56>; -+ reg = <0x38>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { - }; - }; - -- cpu57: cpu@57 { -+ cpu57: cpu@39 { - compatible = "thead,c920", "riscv"; -- reg = <57>; -+ reg = <0x39>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { - }; - }; - -- cpu58: cpu@58 { -+ cpu58: cpu@3a { - compatible = "thead,c920", "riscv"; -- reg = <58>; -+ reg = <0x3a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { - }; - }; - -- cpu59: cpu@59 { -+ cpu59: cpu@3b { - compatible = "thead,c920", "riscv"; -- reg = <59>; -+ reg = <0x3b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { - }; - }; - -- cpu60: cpu@60 { -+ cpu60: cpu@3c { - compatible = "thead,c920", "riscv"; -- reg = <60>; -+ reg = <0x3c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { - }; - }; - -- cpu61: cpu@61 { -+ cpu61: cpu@3d { - compatible = "thead,c920", "riscv"; -- reg = <61>; -+ reg = <0x3d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { - }; - }; - -- cpu62: cpu@62 { -+ cpu62: cpu@3e { - compatible = "thead,c920", "riscv"; -- reg = <62>; -+ reg = <0x3e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { - }; - }; - -- cpu63: cpu@63 { -+ cpu63: cpu@3f { - compatible = "thead,c920", "riscv"; -- reg = <63>; -+ reg = <0x3f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0358-UPSTREAM-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux-lts/0358-UPSTREAM-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch new file mode 100644 index 0000000000..6a9f6f6270 --- /dev/null +++ b/SPECS/linux-lts/0358-UPSTREAM-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch @@ -0,0 +1,93 @@ +From 5a9239b601536fb198a2c13be9e6741d874df8fb Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:12:14 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: dt-bindings: add SpacemiT K3 SoC + compatible + +Add the spacemit,k3-i2s compatible string for the K3 SoC I2S +controller. The K3 I2S IP is the same as K1 but requires additional +clocks: a dedicated sysclk_div clock, along with common_sysclk and +common_bclk which are shared across multiple I2S controllers on K3. + +Acked-by: Rob Herring (Arm) +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-k3-i2s-v3-1-08e3eb811d93@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 6bc6b28c031484092ce1f829f59e4768e12b268e) +Signed-off-by: Han Gao +--- + .../bindings/sound/spacemit,k1-i2s.yaml | 31 +++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +index 55bd0b307d22..240d90402e4f 100644 +--- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml ++++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +@@ -4,7 +4,7 @@ + $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: K1 I2S controller ++title: SpacemiT K1/K3 I2S controller + + description: + The I2S bus (Inter-IC sound bus) is a serial link for digital +@@ -15,27 +15,54 @@ maintainers: + + allOf: + - $ref: dai-common.yaml# ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k3-i2s ++ then: ++ properties: ++ clocks: ++ minItems: 7 ++ clock-names: ++ minItems: 7 ++ else: ++ properties: ++ clocks: ++ maxItems: 4 ++ clock-names: ++ maxItems: 4 + + properties: + compatible: +- const: spacemit,k1-i2s ++ enum: ++ - spacemit,k1-i2s ++ - spacemit,k3-i2s + + reg: + maxItems: 1 + + clocks: ++ minItems: 4 + items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller ++ - description: clock for I2S sysclk divider ++ - description: clock for I2S common sysclk ++ - description: clock for I2S common bclk + + clock-names: ++ minItems: 4 + items: + - const: sysclk + - const: bclk + - const: bus + - const: func ++ - const: sysclk_div ++ - const: c_sysclk ++ - const: c_bclk + + dmas: + minItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch deleted file mode 100644 index 56f743e220..0000000000 --- a/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch +++ /dev/null @@ -1,1095 +0,0 @@ -From 1e554a628178f25ce798d80c22f6e32c9013f918 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 26 Apr 2026 09:34:49 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU - unit address - -Previous the CPU unit address cpu of sg2042 use decimal, it is -not following the general convention for unit addresses of the -OF. Convent the unit address to hex to resolve this problem. - -The introduces a small change for the CPU node name, but it should -affect nothing since there is no direct full-path reference to -these CPU nodes. - -Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") -Signed-off-by: Inochi Amaoto -Tested-by: Chen Wang # Pioneerbox. -Reviewed-by: Guo Ren -Reviewed-by: Chen Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260426013449.694435-3-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- - 1 file changed, 118 insertions(+), 118 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -index 509488eee432..fd8906b313d2 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -@@ -263,7 +263,7 @@ cpu0: cpu@0 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <0>; -+ reg = <0x0>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -291,7 +291,7 @@ cpu1: cpu@1 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <1>; -+ reg = <0x1>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -319,7 +319,7 @@ cpu2: cpu@2 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <2>; -+ reg = <0x2>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -347,7 +347,7 @@ cpu3: cpu@3 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <3>; -+ reg = <0x3>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -375,7 +375,7 @@ cpu4: cpu@4 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <4>; -+ reg = <0x4>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -403,7 +403,7 @@ cpu5: cpu@5 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <5>; -+ reg = <0x5>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -431,7 +431,7 @@ cpu6: cpu@6 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <6>; -+ reg = <0x6>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -459,7 +459,7 @@ cpu7: cpu@7 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <7>; -+ reg = <0x7>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -487,7 +487,7 @@ cpu8: cpu@8 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <8>; -+ reg = <0x8>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -515,7 +515,7 @@ cpu9: cpu@9 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <9>; -+ reg = <0x9>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { - }; - }; - -- cpu10: cpu@10 { -+ cpu10: cpu@a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -543,7 +543,7 @@ cpu10: cpu@10 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <10>; -+ reg = <0xa>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { - }; - }; - -- cpu11: cpu@11 { -+ cpu11: cpu@b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -571,7 +571,7 @@ cpu11: cpu@11 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <11>; -+ reg = <0xb>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { - }; - }; - -- cpu12: cpu@12 { -+ cpu12: cpu@c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -599,7 +599,7 @@ cpu12: cpu@12 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <12>; -+ reg = <0xc>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { - }; - }; - -- cpu13: cpu@13 { -+ cpu13: cpu@d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -627,7 +627,7 @@ cpu13: cpu@13 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <13>; -+ reg = <0xd>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { - }; - }; - -- cpu14: cpu@14 { -+ cpu14: cpu@e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -655,7 +655,7 @@ cpu14: cpu@14 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <14>; -+ reg = <0xe>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { - }; - }; - -- cpu15: cpu@15 { -+ cpu15: cpu@f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -683,7 +683,7 @@ cpu15: cpu@15 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <15>; -+ reg = <0xf>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { - }; - }; - -- cpu16: cpu@16 { -+ cpu16: cpu@10 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -711,7 +711,7 @@ cpu16: cpu@16 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <16>; -+ reg = <0x10>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { - }; - }; - -- cpu17: cpu@17 { -+ cpu17: cpu@11 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -739,7 +739,7 @@ cpu17: cpu@17 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <17>; -+ reg = <0x11>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { - }; - }; - -- cpu18: cpu@18 { -+ cpu18: cpu@12 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -767,7 +767,7 @@ cpu18: cpu@18 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <18>; -+ reg = <0x12>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { - }; - }; - -- cpu19: cpu@19 { -+ cpu19: cpu@13 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -795,7 +795,7 @@ cpu19: cpu@19 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <19>; -+ reg = <0x13>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { - }; - }; - -- cpu20: cpu@20 { -+ cpu20: cpu@14 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -823,7 +823,7 @@ cpu20: cpu@20 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <20>; -+ reg = <0x14>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { - }; - }; - -- cpu21: cpu@21 { -+ cpu21: cpu@15 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -851,7 +851,7 @@ cpu21: cpu@21 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <21>; -+ reg = <0x15>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { - }; - }; - -- cpu22: cpu@22 { -+ cpu22: cpu@16 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -879,7 +879,7 @@ cpu22: cpu@22 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <22>; -+ reg = <0x16>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { - }; - }; - -- cpu23: cpu@23 { -+ cpu23: cpu@17 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -907,7 +907,7 @@ cpu23: cpu@23 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <23>; -+ reg = <0x17>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { - }; - }; - -- cpu24: cpu@24 { -+ cpu24: cpu@18 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -935,7 +935,7 @@ cpu24: cpu@24 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <24>; -+ reg = <0x18>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { - }; - }; - -- cpu25: cpu@25 { -+ cpu25: cpu@19 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -963,7 +963,7 @@ cpu25: cpu@25 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <25>; -+ reg = <0x19>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { - }; - }; - -- cpu26: cpu@26 { -+ cpu26: cpu@1a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -991,7 +991,7 @@ cpu26: cpu@26 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <26>; -+ reg = <0x1a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { - }; - }; - -- cpu27: cpu@27 { -+ cpu27: cpu@1b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1019,7 +1019,7 @@ cpu27: cpu@27 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <27>; -+ reg = <0x1b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { - }; - }; - -- cpu28: cpu@28 { -+ cpu28: cpu@1c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1047,7 +1047,7 @@ cpu28: cpu@28 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <28>; -+ reg = <0x1c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { - }; - }; - -- cpu29: cpu@29 { -+ cpu29: cpu@1d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1075,7 +1075,7 @@ cpu29: cpu@29 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <29>; -+ reg = <0x1d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { - }; - }; - -- cpu30: cpu@30 { -+ cpu30: cpu@1e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1103,7 +1103,7 @@ cpu30: cpu@30 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <30>; -+ reg = <0x1e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { - }; - }; - -- cpu31: cpu@31 { -+ cpu31: cpu@1f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1131,7 +1131,7 @@ cpu31: cpu@31 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <31>; -+ reg = <0x1f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { - }; - }; - -- cpu32: cpu@32 { -+ cpu32: cpu@20 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1159,7 +1159,7 @@ cpu32: cpu@32 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <32>; -+ reg = <0x20>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { - }; - }; - -- cpu33: cpu@33 { -+ cpu33: cpu@21 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1187,7 +1187,7 @@ cpu33: cpu@33 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <33>; -+ reg = <0x21>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { - }; - }; - -- cpu34: cpu@34 { -+ cpu34: cpu@22 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1215,7 +1215,7 @@ cpu34: cpu@34 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <34>; -+ reg = <0x22>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { - }; - }; - -- cpu35: cpu@35 { -+ cpu35: cpu@23 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1243,7 +1243,7 @@ cpu35: cpu@35 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <35>; -+ reg = <0x23>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { - }; - }; - -- cpu36: cpu@36 { -+ cpu36: cpu@24 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1271,7 +1271,7 @@ cpu36: cpu@36 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <36>; -+ reg = <0x24>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { - }; - }; - -- cpu37: cpu@37 { -+ cpu37: cpu@25 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1299,7 +1299,7 @@ cpu37: cpu@37 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <37>; -+ reg = <0x25>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { - }; - }; - -- cpu38: cpu@38 { -+ cpu38: cpu@26 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1327,7 +1327,7 @@ cpu38: cpu@38 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <38>; -+ reg = <0x26>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { - }; - }; - -- cpu39: cpu@39 { -+ cpu39: cpu@27 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1355,7 +1355,7 @@ cpu39: cpu@39 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <39>; -+ reg = <0x27>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { - }; - }; - -- cpu40: cpu@40 { -+ cpu40: cpu@28 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1383,7 +1383,7 @@ cpu40: cpu@40 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <40>; -+ reg = <0x28>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { - }; - }; - -- cpu41: cpu@41 { -+ cpu41: cpu@29 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1411,7 +1411,7 @@ cpu41: cpu@41 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <41>; -+ reg = <0x29>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { - }; - }; - -- cpu42: cpu@42 { -+ cpu42: cpu@2a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1439,7 +1439,7 @@ cpu42: cpu@42 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <42>; -+ reg = <0x2a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { - }; - }; - -- cpu43: cpu@43 { -+ cpu43: cpu@2b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1467,7 +1467,7 @@ cpu43: cpu@43 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <43>; -+ reg = <0x2b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { - }; - }; - -- cpu44: cpu@44 { -+ cpu44: cpu@2c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1495,7 +1495,7 @@ cpu44: cpu@44 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <44>; -+ reg = <0x2c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { - }; - }; - -- cpu45: cpu@45 { -+ cpu45: cpu@2d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1523,7 +1523,7 @@ cpu45: cpu@45 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <45>; -+ reg = <0x2d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { - }; - }; - -- cpu46: cpu@46 { -+ cpu46: cpu@2e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1551,7 +1551,7 @@ cpu46: cpu@46 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <46>; -+ reg = <0x2e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { - }; - }; - -- cpu47: cpu@47 { -+ cpu47: cpu@2f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1579,7 +1579,7 @@ cpu47: cpu@47 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <47>; -+ reg = <0x2f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { - }; - }; - -- cpu48: cpu@48 { -+ cpu48: cpu@30 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1607,7 +1607,7 @@ cpu48: cpu@48 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <48>; -+ reg = <0x30>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { - }; - }; - -- cpu49: cpu@49 { -+ cpu49: cpu@31 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1635,7 +1635,7 @@ cpu49: cpu@49 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <49>; -+ reg = <0x31>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { - }; - }; - -- cpu50: cpu@50 { -+ cpu50: cpu@32 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1663,7 +1663,7 @@ cpu50: cpu@50 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <50>; -+ reg = <0x32>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { - }; - }; - -- cpu51: cpu@51 { -+ cpu51: cpu@33 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1691,7 +1691,7 @@ cpu51: cpu@51 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <51>; -+ reg = <0x33>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { - }; - }; - -- cpu52: cpu@52 { -+ cpu52: cpu@34 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1719,7 +1719,7 @@ cpu52: cpu@52 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <52>; -+ reg = <0x34>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { - }; - }; - -- cpu53: cpu@53 { -+ cpu53: cpu@35 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1747,7 +1747,7 @@ cpu53: cpu@53 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <53>; -+ reg = <0x35>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { - }; - }; - -- cpu54: cpu@54 { -+ cpu54: cpu@36 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1775,7 +1775,7 @@ cpu54: cpu@54 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <54>; -+ reg = <0x36>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { - }; - }; - -- cpu55: cpu@55 { -+ cpu55: cpu@37 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1803,7 +1803,7 @@ cpu55: cpu@55 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <55>; -+ reg = <0x37>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { - }; - }; - -- cpu56: cpu@56 { -+ cpu56: cpu@38 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1831,7 +1831,7 @@ cpu56: cpu@56 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <56>; -+ reg = <0x38>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { - }; - }; - -- cpu57: cpu@57 { -+ cpu57: cpu@39 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1859,7 +1859,7 @@ cpu57: cpu@57 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <57>; -+ reg = <0x39>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { - }; - }; - -- cpu58: cpu@58 { -+ cpu58: cpu@3a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1887,7 +1887,7 @@ cpu58: cpu@58 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <58>; -+ reg = <0x3a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { - }; - }; - -- cpu59: cpu@59 { -+ cpu59: cpu@3b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1915,7 +1915,7 @@ cpu59: cpu@59 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <59>; -+ reg = <0x3b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { - }; - }; - -- cpu60: cpu@60 { -+ cpu60: cpu@3c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1943,7 +1943,7 @@ cpu60: cpu@60 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <60>; -+ reg = <0x3c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { - }; - }; - -- cpu61: cpu@61 { -+ cpu61: cpu@3d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1971,7 +1971,7 @@ cpu61: cpu@61 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <61>; -+ reg = <0x3d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { - }; - }; - -- cpu62: cpu@62 { -+ cpu62: cpu@3e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1999,7 +1999,7 @@ cpu62: cpu@62 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <62>; -+ reg = <0x3e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { - }; - }; - -- cpu63: cpu@63 { -+ cpu63: cpu@3f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -2027,7 +2027,7 @@ cpu63: cpu@63 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <63>; -+ reg = <0x3f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0359-UPSTREAM-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux-lts/0359-UPSTREAM-ASoC-spacemit-add-K3-SoC-support-with-addit.patch new file mode 100644 index 0000000000..17706c3876 --- /dev/null +++ b/SPECS/linux-lts/0359-UPSTREAM-ASoC-spacemit-add-K3-SoC-support-with-addit.patch @@ -0,0 +1,114 @@ +From e8e01a1507354c98f3a65db6a5bbf170677c3d57 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:12:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: add K3 SoC support with + additional clocks + +Add support for the SpacemiT K3 SoC I2S controller, which shares the +same IP as K1 but requires additional clocks: sysclk_div, c_sysclk, +and c_bclk. These clocks only exist on K3 and are not present on K1. +The sysclk_div clock is present on most K3 I2S controllers except I2S1. +The c_sysclk and c_bclk clocks are shared across multiple I2S +controllers on K3. + +Use devm_clk_get_optional_enabled() to acquire these clocks so that +the driver works on both K1 (where they are absent) and K3 without +needing SoC-specific match data. For K3, the sysclk_div rate is set +before sysclk in set_sysclk, and the common clock rates are configured +in hw_params based on the sample rate. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-k3-i2s-v3-2-08e3eb811d93@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 1c6ca2ca5c1bdc97912cf3f9b4a1e186919a6a98) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 36 +++++++++++++++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 03cca5d84503..3df94b4ca5a5 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -53,6 +53,9 @@ struct spacemit_i2s_dev { + struct clk *sysclk; + struct clk *bclk; + struct clk *sspa_clk; ++ struct clk *sysclk_div; ++ struct clk *c_sysclk; ++ struct clk *c_bclk; + + struct snd_dmaengine_dai_dma_data capture_dma_data; + struct snd_dmaengine_dai_dma_data playback_dma_data; +@@ -206,6 +209,14 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + params_rate(params) * + data_bits; + ++ ret = clk_set_rate(i2s->c_sysclk, bclk_rate * 2); ++ if (ret) ++ return ret; ++ ++ ret = clk_set_rate(i2s->c_bclk, bclk_rate); ++ if (ret) ++ return ret; ++ + ret = clk_set_rate(i2s->bclk, bclk_rate); + if (ret) + return ret; +@@ -217,10 +228,17 @@ static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, + unsigned int freq, int dir) + { + struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev); ++ int ret; + + if (freq == 0) + return 0; + ++ if (i2s->sysclk_div) { ++ ret = clk_set_rate(i2s->sysclk_div, freq); ++ if (ret) ++ return ret; ++ } ++ + return clk_set_rate(i2s->sysclk, freq); + } + +@@ -435,6 +453,21 @@ static int spacemit_i2s_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(i2s->dev, PTR_ERR(clk), "failed to enable sspa clock\n"); + ++ i2s->sysclk_div = devm_clk_get_optional_enabled(i2s->dev, "sysclk_div"); ++ if (IS_ERR(i2s->sysclk_div)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk_div), ++ "failed to enable sysclk_div clock\n"); ++ ++ i2s->c_sysclk = devm_clk_get_optional_enabled(i2s->dev, "c_sysclk"); ++ if (IS_ERR(i2s->c_sysclk)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_sysclk), ++ "failed to enable c_sysclk clock\n"); ++ ++ i2s->c_bclk = devm_clk_get_optional_enabled(i2s->dev, "c_bclk"); ++ if (IS_ERR(i2s->c_bclk)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_bclk), ++ "failed to enable c_bclk clock\n"); ++ + i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(i2s->base)) + return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n"); +@@ -459,6 +492,7 @@ static int spacemit_i2s_probe(struct platform_device *pdev) + + static const struct of_device_id spacemit_i2s_of_match[] = { + { .compatible = "spacemit,k1-i2s", }, ++ { .compatible = "spacemit,k3-i2s", }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match); +@@ -473,4 +507,4 @@ static struct platform_driver spacemit_i2s_driver = { + module_platform_driver(spacemit_i2s_driver); + + MODULE_LICENSE("GPL"); +-MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1/K3 SoC"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch deleted file mode 100644 index 3978b9eca3..0000000000 --- a/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 344151a10b042115f283ccb3ceb2241243f4f16a Mon Sep 17 00:00:00 2001 -From: Nam Cao -Date: Tue, 7 Apr 2026 14:06:39 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: Fix fast_unaligned_access_speed_key not - getting initialized - -The static key fast_unaligned_access_speed_key is supposed to be -initialized after check_unaligned_access_all_cpus() has been completed. - -However, check_unaligned_access_all_cpus() has been moved to late_initcall -while setting fast_unaligned_access_speed_key still happens at -arch_initcall_sync, thus the static key does not get properly initialized. - -fast_unaligned_access_speed_key can still be initialized in CPU hotplug -events, but that cannot be relied on. - -Move fast_unaligned_access_speed_key's initialization into -check_unaligned_access_all_cpus() to fix this issue. This also prevent -someone from moving one initcall while forgetting the other in the future. - -Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") -Reported-by: Michael Neuling -Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ -Signed-off-by: Nam Cao -Link: https://lore.kernel.org/r/20260407120639.4006031-1-namcao@linutronix.de -Signed-off-by: Han Gao ---- - arch/riscv/kernel/unaligned_access_speed.c | 15 ++++----------- - 1 file changed, 4 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c -index 70b5e6927620..5e224cc48c62 100644 ---- a/arch/riscv/kernel/unaligned_access_speed.c -+++ b/arch/riscv/kernel/unaligned_access_speed.c -@@ -223,17 +223,6 @@ static void set_unaligned_access_static_branches(void) - modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); - } - --static int __init lock_and_set_unaligned_access_static_branch(void) --{ -- cpus_read_lock(); -- set_unaligned_access_static_branches(); -- cpus_read_unlock(); -- -- return 0; --} -- --arch_initcall_sync(lock_and_set_unaligned_access_static_branch); -- - static int riscv_online_cpu(unsigned int cpu) - { - int ret = cpu_online_unaligned_access_init(cpu); -@@ -491,6 +480,10 @@ static int __init check_unaligned_access_all_cpus(void) - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu_vec, NULL); - -+ cpus_read_lock(); -+ set_unaligned_access_static_branches(); -+ cpus_read_unlock(); -+ - return 0; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0360-UPSTREAM-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux-lts/0360-UPSTREAM-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch new file mode 100644 index 0000000000..4cf0690bef --- /dev/null +++ b/SPECS/linux-lts/0360-UPSTREAM-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch @@ -0,0 +1,98 @@ +From 50fa7e06cba360d45ba4e526225eaf114699b5eb Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:33:57 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: soc-dai: add shared BCLK clock for + cross-DAI rate constraints + +Add a bclk field to struct snd_soc_dai and a helper function +snd_soc_dai_set_bclk_clk() that platform drivers can use to declare +which clock is their BCLK. + +Also cache the bclk_ratio in snd_soc_dai_set_bclk_ratio() so that +the framework can use it later in hw_rule evaluation for TDM +configurations where BCLK = rate * slots * slot_width. + +When multiple DAIs on the same card share the same physical BCLK +(detected via clk_is_match()), the ASoC core can automatically +constrain their hw_params so that the resulting BCLK rates are +compatible. This commit adds the data structure support; the actual +constraint logic follows in the next patch. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-i2s-same-blk-v4-1-a71a86faaa20@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 94bdfad3a665da68731deb56b0fe80f00a3e6da8) +Signed-off-by: Han Gao +--- + include/sound/soc-dai.h | 7 +++++++ + sound/soc/soc-dai.c | 18 ++++++++++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h +index 224396927aef..6d3a0ce02fd8 100644 +--- a/include/sound/soc-dai.h ++++ b/include/sound/soc-dai.h +@@ -17,6 +17,7 @@ + struct snd_pcm_substream; + struct snd_soc_dapm_widget; + struct snd_compr_stream; ++struct clk; + + /* + * DAI hardware audio formats. +@@ -173,6 +174,8 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, + + int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); + ++void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); ++ + /* Digital Audio interface formatting */ + int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); + u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); +@@ -451,6 +454,10 @@ struct snd_soc_dai { + unsigned int symmetric_channels; + unsigned int symmetric_sample_bits; + ++ /* shared BCLK clock for cross-DAI rate constraints */ ++ struct clk *bclk; ++ unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ ++ + /* parent platform/codec */ + struct snd_soc_component *component; + +diff --git a/sound/soc/soc-dai.c b/sound/soc/soc-dai.c +index f231b4174b5f..a32501d017f6 100644 +--- a/sound/soc/soc-dai.c ++++ b/sound/soc/soc-dai.c +@@ -116,10 +116,28 @@ int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) + dai->driver->ops->set_bclk_ratio) + ret = dai->driver->ops->set_bclk_ratio(dai, ratio); + ++ if (!ret) ++ dai->bclk_ratio = ratio; ++ + return soc_dai_ret(dai, ret); + } + EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio); + ++/** ++ * snd_soc_dai_set_bclk_clk - set the BCLK clock for shared clock detection ++ * @dai: DAI ++ * @bclk: BCLK clock pointer (or NULL to clear) ++ * ++ * When multiple DAIs share the same physical BCLK (detected via ++ * clk_is_match()), the ASoC core will automatically constrain their ++ * hw_params so that the resulting BCLK rates are compatible. ++ */ ++void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk) ++{ ++ dai->bclk = bclk; ++} ++EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_clk); ++ + int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd) + { + struct snd_soc_dai *dai; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch deleted file mode 100644 index 4ca22126b9..0000000000 --- a/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6f609eb72f740d3d3be5b596fca48b7d76f3a181 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 8 Apr 2026 00:01:43 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count to - 16 - -The SG2042 MSI controller has one 32-bit doorbell register, and each bit -corresponds to an interrupt. At a glance, it seems that the MSI -controller can support 32 interrupts; however the PCI MSI capability -only supports 16-bit messages, which makes the high 16 interrupts -unusable in such way. - -Reduce the MSI count to 16 to prevent producing MSI message values that -cannot fit 16-bit integers. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260407160143.1182430-1-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index 3af770549742..7eab0655f150 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { - reg-names = "clr", "doorbell"; - msi-controller; - #msi-cells = <0>; -- msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; -+ msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; - }; - - rpgate: clock-controller@7030010368 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0361-UPSTREAM-ASoC-soc-pcm-add-DEFINE_GUARD-for-snd_soc_c.patch b/SPECS/linux-lts/0361-UPSTREAM-ASoC-soc-pcm-add-DEFINE_GUARD-for-snd_soc_c.patch new file mode 100644 index 0000000000..20a1ebbdbd --- /dev/null +++ b/SPECS/linux-lts/0361-UPSTREAM-ASoC-soc-pcm-add-DEFINE_GUARD-for-snd_soc_c.patch @@ -0,0 +1,36 @@ +From 97c539645d73a837bfe7f50f9eccec5474f2e8d4 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:33:58 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: soc-pcm: add DEFINE_GUARD for + snd_soc_card_mutex + +Define a guard class wrapping snd_soc_card_mutex_lock() and +snd_soc_card_mutex_unlock() so that scope-based locking can be used +while still picking up the SND_SOC_CARD_CLASS_RUNTIME lockdep subclass. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-i2s-same-blk-v4-2-a71a86faaa20@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 2555c62275a10bb7dfb4476ebe73d48df11f3112) +Signed-off-by: Han Gao +--- + sound/soc/soc-pcm.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c +index 99299364c9ba..f83d06b753b0 100644 +--- a/sound/soc/soc-pcm.c ++++ b/sound/soc/soc-pcm.c +@@ -26,6 +26,9 @@ + #include + #include + ++ ++DEFINE_GUARD(snd_soc_card_mutex, struct snd_soc_card *, ++ snd_soc_card_mutex_lock(_T), snd_soc_card_mutex_unlock(_T)) + #define soc_pcm_ret(rtd, ret) _soc_pcm_ret(rtd, __func__, ret) + static inline int _soc_pcm_ret(struct snd_soc_pcm_runtime *rtd, + const char *func, int ret) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch deleted file mode 100644 index fe8f74bcb4..0000000000 --- a/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch +++ /dev/null @@ -1,93 +0,0 @@ -From a42a4931c6355f9aec78b37eacf4e7f01afaa772 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:46:50 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add - SpacemiT K3 PWM support - -The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 -generation, while the difference is that one additional bus clock is -added. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org -Signed-off-by: Han Gao ---- - .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- - 1 file changed, 38 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -index 8df327e52810..f1422a401b6b 100644 ---- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -+++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -@@ -15,7 +15,9 @@ allOf: - properties: - compatible: - contains: -- const: spacemit,k1-pwm -+ enum: -+ - spacemit,k1-pwm -+ - spacemit,k3-pwm - then: - properties: - "#pwm-cells": -@@ -26,6 +28,26 @@ allOf: - const: 1 - description: | - Used for specifying the period length in nanoseconds. -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - spacemit,k3-pwm -+ then: -+ required: -+ - clock-names -+ properties: -+ clocks: -+ minItems: 2 -+ clock-names: -+ minItems: 2 -+ else: -+ properties: -+ clocks: -+ maxItems: 1 -+ clock-names: -+ maxItems: 1 - - properties: - compatible: -@@ -36,7 +58,9 @@ properties: - - marvell,pxa168-pwm - - marvell,pxa910-pwm - - items: -- - const: spacemit,k1-pwm -+ - enum: -+ - spacemit,k1-pwm -+ - spacemit,k3-pwm - - const: marvell,pxa910-pwm - - reg: -@@ -47,7 +71,18 @@ properties: - description: Number of cells in a pwm specifier. - - clocks: -- maxItems: 1 -+ minItems: 1 -+ items: -+ - description: The function clock -+ - description: An optional bus clock -+ -+ clock-names: -+ minItems: 1 -+ maxItems: 2 -+ oneOf: -+ - items: -+ - const: func -+ - const: bus - - resets: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0362-UPSTREAM-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux-lts/0362-UPSTREAM-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch new file mode 100644 index 0000000000..474ad453d7 --- /dev/null +++ b/SPECS/linux-lts/0362-UPSTREAM-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch @@ -0,0 +1,183 @@ +From b7ac20b9e9a352e22f9cfa322714fd27dd30d1bd Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 22 May 2026 21:33:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: soc-pcm: constrain hw_params when DAIs + share the same BCLK + +When multiple CPU DAIs on the same sound card share the same physical +BCLK, add a hw_rule during PCM open that constrains the sample rate so +the resulting BCLK rate stays consistent across all sharing DAIs. + +The rule callback scans all DAIs on the card at hw_refine time, looking +for an active peer that shares the same physical BCLK (via +clk_is_match()) and has already completed hw_params (checked via +dai->symmetric_rate != 0). This ensures the constraint uses the real +BCLK rate established by the peer's clk_set_rate() in hw_params, not a +stale boot-time default. + +The first DAI to complete hw_params is unconstrained (no active peer +yet); subsequent DAIs are constrained to match. + +The rule supports two modes: +- If the DAI has an explicit bclk_ratio set (e.g. for TDM where + BCLK = rate * slots * slot_width), the rate is constrained to + active_bclk_rate / bclk_ratio. +- Otherwise, the default formula BCLK = rate * channels * sample_bits + is used to derive the valid rate range. + +The constraint is purely additive: DAIs that do not set a bclk clock +pointer are completely unaffected. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260522-i2s-same-blk-v4-3-a71a86faaa20@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit c8c2ffd722a6e497b9c6bb9961a7afb6ee5e2c28) +Signed-off-by: Han Gao +--- + sound/soc/soc-pcm.c | 116 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 116 insertions(+) + +diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c +index f83d06b753b0..e09f262fb827 100644 +--- a/sound/soc/soc-pcm.c ++++ b/sound/soc/soc-pcm.c +@@ -12,6 +12,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -470,6 +471,114 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream, + return 0; + } + ++/* ++ * Shared BCLK constraint: when multiple DAIs share the same physical BCLK, ++ * constrain hw_params so that the BCLK rate (rate * channels * sample_bits, ++ * or rate * slots * slot_width for TDM) remains consistent. ++ */ ++ ++static int soc_pcm_shared_bclk_rule_rate(struct snd_pcm_hw_params *params, ++ struct snd_pcm_hw_rule *rule) ++{ ++ struct snd_soc_dai *dai = rule->private; ++ struct snd_soc_card *card = dai->component->card; ++ struct snd_soc_pcm_runtime *rtd; ++ struct snd_soc_dai *other_dai; ++ unsigned long active_bclk_rate = 0; ++ struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); ++ struct snd_interval constraint = { .empty = 1 }; ++ unsigned int target_rate; ++ int i; ++ ++ /* Protect the rtd list traversal with the ASoC card mutex helper. */ ++ guard(snd_soc_card_mutex)(card); ++ ++ /* Scan all DAIs on the card for an active peer sharing the same BCLK */ ++ for_each_card_rtds(card, rtd) { ++ for_each_rtd_cpu_dais(rtd, i, other_dai) { ++ if (other_dai == dai) ++ continue; ++ if (!other_dai->bclk) ++ continue; ++ if (!snd_soc_dai_active(other_dai)) ++ continue; ++ /* ++ * Skip peers whose hw_params hasn't run yet. ++ * symmetric_rate is set by soc_pcm_set_dai_params() ++ * after snd_soc_dai_hw_params(), so non-zero means ++ * the DAI's clk_set_rate() has already executed. ++ */ ++ if (!other_dai->symmetric_rate) ++ continue; ++ if (!clk_is_match(dai->bclk, other_dai->bclk)) ++ continue; ++ ++ active_bclk_rate = clk_get_rate(other_dai->bclk); ++ if (active_bclk_rate) ++ goto found; ++ } ++ } ++ ++ return 0; ++ ++found: ++ if (dai->bclk_ratio) { ++ /* ++ * Driver has set an explicit BCLK ratio (e.g. for TDM where ++ * BCLK = rate * slots * slot_width). The only valid rate is ++ * active_bclk_rate / bclk_ratio. ++ */ ++ target_rate = active_bclk_rate / dai->bclk_ratio; ++ ++ constraint.min = target_rate; ++ constraint.max = target_rate; ++ } else { ++ struct snd_interval *channels = hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_CHANNELS); ++ struct snd_interval *sample_bits = hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_SAMPLE_BITS); ++ ++ /* ++ * Default: BCLK = rate * channels * sample_bits. ++ * Calculate the range of valid rates given the current ++ * channel and sample_bits intervals. ++ */ ++ if (!channels->min || !sample_bits->min) ++ return 0; ++ ++ constraint.max = active_bclk_rate / ++ ((unsigned long)channels->min * sample_bits->min); ++ ++ if (channels->max && sample_bits->max) ++ constraint.min = active_bclk_rate / ++ ((unsigned long)channels->max * sample_bits->max); ++ else ++ constraint.min = constraint.max; ++ } ++ ++ constraint.integer = 1; ++ constraint.empty = 0; ++ ++ return snd_interval_refine(rate, &constraint); ++} ++ ++static int soc_pcm_apply_shared_bclk(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ if (!dai->bclk) ++ return 0; ++ ++ dev_dbg(dai->dev, ++ "ASoC: registering shared BCLK rate constraint\n"); ++ ++ return snd_pcm_hw_rule_add(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ soc_pcm_shared_bclk_rule_rate, dai, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ SNDRV_PCM_HW_PARAM_SAMPLE_BITS, ++ -1); ++} ++ + static int soc_pcm_params_symmetry(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) + { +@@ -894,6 +1003,13 @@ static int __soc_pcm_open(struct snd_soc_pcm_runtime *rtd, + if (ret != 0) + goto err; + } ++ ++ /* Shared BCLK constraint across DAIs on the same card */ ++ for_each_rtd_cpu_dais(rtd, i, dai) { ++ ret = soc_pcm_apply_shared_bclk(substream, dai); ++ if (ret != 0) ++ goto err; ++ } + dynamic: + snd_soc_runtime_activate(rtd, substream->stream); + ret = 0; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch deleted file mode 100644 index 8346eff059..0000000000 --- a/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 2173dcb3b9c7cd083216f7561ca2c80cc779e6c3 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:46:51 +0000 -Subject: [RUYI PATCH] FROMLIST: pwm: pxa: Add optional bus clock - -Add one secondary optional bus clock for the PWM PXA driver, also keep it -compatible with old single clock. - -The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and -enable it during probe phase. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org -Signed-off-by: Han Gao ---- - drivers/pwm/pwm-pxa.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c -index 0f5bdb0e395e..80d2fa10919f 100644 ---- a/drivers/pwm/pwm-pxa.c -+++ b/drivers/pwm/pwm-pxa.c -@@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) - const struct platform_device_id *id = platform_get_device_id(pdev); - struct pwm_chip *chip; - struct pxa_pwm_chip *pc; -+ struct clk *bus_clk; - struct device *dev = &pdev->dev; - struct reset_control *rst; - int ret = 0; -@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) - return PTR_ERR(chip); - pc = to_pxa_pwm_chip(chip); - -- pc->clk = devm_clk_get(dev, NULL); -+ bus_clk = devm_clk_get_optional_enabled(dev, "bus"); -+ if (IS_ERR(bus_clk)) -+ return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); -+ -+ /* Get named func clk if bus clock is valid */ -+ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); - if (IS_ERR(pc->clk)) - return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); - --- -2.53.0 - diff --git a/SPECS/linux-lts/0363-UPSTREAM-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux-lts/0363-UPSTREAM-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch new file mode 100644 index 0000000000..ab2203fd1b --- /dev/null +++ b/SPECS/linux-lts/0363-UPSTREAM-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch @@ -0,0 +1,44 @@ +From 77d0825c6e1782e7a2f5484d9433738ef80b6f6d Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:05 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: gpio: dwapb: allow GPIO hogs + +GPIO hogs are described in the gpio.txt binding as automatic default +GPIO configuration items. + +Allow them for GPIO ports in DesignWare APB GPIO controller nodes. + +Cc: Hoan Tran +Cc: Linus Walleij +Cc: Bartosz Golaszewski +Cc: Serge Semin +Signed-off-by: Icenowy Zheng +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260507081710.4090814-8-zhengxingda@iscas.ac.cn +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit f76c8be440e53465a306c95a7d50ca8675252f82) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +index ab2afc0e4153..79679a14a02f 100644 +--- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml ++++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +@@ -95,6 +95,12 @@ patternProperties: + '#interrupt-cells': + const: 2 + ++ patternProperties: ++ "^.+-hog(-[0-9]+)?$": ++ type: object ++ required: ++ - gpio-hog ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch deleted file mode 100644 index 169b4e07b6..0000000000 --- a/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch +++ /dev/null @@ -1,45 +0,0 @@ -From a9afe33a20c57d9588e3a723da69fe92572f5726 Mon Sep 17 00:00:00 2001 -From: Chen Pei -Date: Thu, 9 Apr 2026 19:47:36 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: select - HAVE_BUILDTIME_MCOUNT_SORT - -RISC-V already satisfies all prerequisites for build-time mcount sorting: -the sorttable host tool handles EM_RISCV in its machine-type dispatch, and -the __mcount_loc section entries are stored as direct virtual addresses in -the final vmlinux binary, so no relocation processing is required during -the sort step. - -Select HAVE_BUILDTIME_MCOUNT_SORT so that BUILDTIME_MCOUNT_SORT is -automatically enabled when DYNAMIC_FTRACE is configured. This allows -sorttable to sort the __mcount_loc section at link time, making the -run-time ftrace initialisation path skip the software sort and reducing -kernel startup overhead. - -Verified with CONFIG_FTRACE_SORT_STARTUP_TEST=y, which confirms that -the section produced by the build is already in ascending order: - - [ 0.000000] ftrace section at ffffffff81015a60 sorted properly - -Signed-off-by: Chen Pei -Link: https://lore.kernel.org/r/20260409114736.907-1-cp0613@linux.alibaba.com -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 1aa7fec41c09..5cc386e56d13 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -150,6 +150,7 @@ config RISCV - select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD - select HAVE_ARCH_VMAP_STACK if MMU && 64BIT - select HAVE_ASM_MODVERSIONS -+ select HAVE_BUILDTIME_MCOUNT_SORT - select HAVE_CONTEXT_TRACKING_USER - select HAVE_DEBUG_KMEMLEAK - select HAVE_DMA_CONTIGUOUS if MMU --- -2.53.0 - diff --git a/SPECS/linux-lts/0364-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux-lts/0364-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch new file mode 100644 index 0000000000..a5df66a978 --- /dev/null +++ b/SPECS/linux-lts/0364-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch @@ -0,0 +1,181 @@ +From ee545472effccb2aca0af0209c8fede99d5a4ed5 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:49 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: add PMIC + and power infrastructure + +Enable i2c8 and add the connected SpacemiT P1 PMIC with its related +regulators for the board's power infrastructure and voltage regulation +support. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-2-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit e2dac7c7a3a8970feeeb758f782ce86b89625ebd) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 134 ++++++++++++++++++ + 1 file changed, 134 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 29e333b670cf..653e5a1bf41b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -17,6 +17,7 @@ / { + aliases { + ethernet0 = ð0; + serial0 = &uart0; ++ i2c8 = &i2c8; + }; + + chosen { +@@ -33,6 +34,15 @@ led1 { + default-state = "on"; + }; + }; ++ ++ reg_vcc_4v: regulator-vcc-4v { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC4V0"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + &emmc { +@@ -72,6 +82,130 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-0 = <&i2c8_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch deleted file mode 100644 index 63660577e2..0000000000 --- a/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 62c0719d1e7faf6136869e6f6da6b1f069f63523 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 18 May 2026 18:00:30 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable USB3 on OrangePi - R2S - -Enable the DWC3 USB3.0 controller and its associated PHY on the -OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 -ports, but the USB2 ports are handled by a separate controller. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260518100030.2354606-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index de75f6aac740..1ecc40749e5a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -21,6 +21,19 @@ aliases { - chosen { - stdout-path = "serial0"; - }; -+ -+ vcc5v0_usb: regulator-vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combo_phy { -+ status = "okay"; - }; - - &emmc { -@@ -90,3 +103,13 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ vbus-supply = <&vcc5v0_usb>; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0365-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-24c02-.patch b/SPECS/linux-lts/0365-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-24c02-.patch new file mode 100644 index 0000000000..35ab70a8b8 --- /dev/null +++ b/SPECS/linux-lts/0365-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-24c02-.patch @@ -0,0 +1,90 @@ +From e2f8a478f91b32fb059faf0d944707eb7c2b360d Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:50 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: add 24c02 + eeprom + +Enable i2c2 and add the connected GT24C02B EEPROM. + +It contains an ONIE TLV table: +=> tlv_eeprom +TLV: 0 +[ 12.162] TlvInfo Header: +[ 12.162] Id String: TlvInfo +[ 12.165] Version: 1 +[ 12.168] Total Length: 58 +[ 12.171] TLV Name Code Len Value +[ 12.175] -------------------- ---- --- ----- +[ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro +[ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX +[ 12.189] Unknown 0x41 1 0x02 +[ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX +[ 12.199] MAC Addresses 0x2A 2 2 +[ 12.203] CRC-32 0xFE 4 0x395ECD34 +[ 12.207] Checksum is valid. + +(With 0x41 as TLV_CODE_DDR_CSNUM) + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-3-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 6bc75cfa56e885c2eab80e215f0a610075505846) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 33 +++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 653e5a1bf41b..b8e73eed8e62 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -17,6 +17,7 @@ / { + aliases { + ethernet0 = ð0; + serial0 = &uart0; ++ i2c2 = &i2c2; + i2c8 = &i2c8; + }; + +@@ -82,6 +83,38 @@ &pdma { + status = "okay"; + }; + ++&i2c2 { ++ pinctrl-0 = <&i2c2_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ ++ pagesize = <8>; ++ read-only; ++ size = <256>; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ product-name { ++ }; ++ ++ serial-number { ++ }; ++ ++ mac-address { ++ #nvmem-cell-cells = <1>; ++ }; ++ ++ num-macs { ++ }; ++ }; ++ }; ++}; ++ + &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch deleted file mode 100644 index 84486826fc..0000000000 --- a/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5d9676891cd5d6a9735391e8b346e75d7f6559c9 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:57:29 +0000 -Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: correct 32k clock - frequency - -The 32k oscillator's clock frequency is actually 32768Hz, so correct it. - -Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") -Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- - arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index aefdbbadc9ef..8774a00a854b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -341,7 +341,7 @@ vctcxo_3m: clock-3m { - - osc_32k: clock-32k { - compatible = "fixed-clock"; -- clock-frequency = <32000>; -+ clock-frequency = <32768>; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 81ad575f16a5..0408929f7949 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { - - osc_32k: clock-32k { - compatible = "fixed-clock"; -- clock-frequency = <32000>; -+ clock-frequency = <32768>; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0366-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux-lts/0366-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch new file mode 100644 index 0000000000..081b65364f --- /dev/null +++ b/SPECS/linux-lts/0366-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch @@ -0,0 +1,91 @@ +From ec1239c7ad79bc3f3381acb33cbbc01de935cfd8 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:51 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: enable + QSPI and add SPI NOR + +Add the QSPI controller node and describe the attached SPI NOR flash +(Winbond W25Q64FWSSAQ). + +Add a corresponding vendor flash partition layout. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-4-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 735b1b205d07bf7bfa55b1f50f5485b9cc42a251) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index b8e73eed8e62..74841cffd5f5 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -44,6 +44,15 @@ reg_vcc_4v: regulator-vcc-4v { + regulator-boot-on; + regulator-always-on; + }; ++ ++ reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { ++ compatible = "regulator-fixed"; ++ regulator-name = "QSPI_VCC1833"; ++ regulator-min-microvolt = <1833000>; ++ regulator-max-microvolt = <1833000>; ++ regulator-always-on; ++ vin-supply = <&buck4_3v3>; ++ }; + }; + + &emmc { +@@ -239,6 +248,47 @@ dldo7 { + }; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <®_qspi_vcc1v833>; ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x10000>; ++ }; ++ private@10000 { ++ reg = <0x10000 0x10000>; ++ }; ++ fsbl@20000 { ++ reg = <0x20000 0x40000>; ++ }; ++ env@60000 { ++ reg = <0x60000 0x10000>; ++ }; ++ opensbi@70000 { ++ reg = <0x70000 0x30000>; ++ }; ++ uboot@a0000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch deleted file mode 100644 index ae80025a53..0000000000 --- a/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 50c5274eb867073ad2b53bef51e6d9d19aa9ac2a Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 15:33:09 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC - compatible - -Add the spacemit,k3-i2s compatible string for the K3 SoC I2S -controller. The K3 I2S IP is the same as K1 but requires additional -clocks: a dedicated sysclk_div clock, along with common_sysclk and -common_bclk which are shared across multiple I2S controllers on K3. - -Acked-by: Rob Herring (Arm) -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-1-9cdbf95b7533@linux.spacemit.com -Signed-off-by: Han Gao ---- - .../bindings/sound/spacemit,k1-i2s.yaml | 31 +++++++++++++++++-- - 1 file changed, 29 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -index 55bd0b307d22..240d90402e4f 100644 ---- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -+++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -@@ -4,7 +4,7 @@ - $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: K1 I2S controller -+title: SpacemiT K1/K3 I2S controller - - description: - The I2S bus (Inter-IC sound bus) is a serial link for digital -@@ -15,27 +15,54 @@ maintainers: - - allOf: - - $ref: dai-common.yaml# -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: spacemit,k3-i2s -+ then: -+ properties: -+ clocks: -+ minItems: 7 -+ clock-names: -+ minItems: 7 -+ else: -+ properties: -+ clocks: -+ maxItems: 4 -+ clock-names: -+ maxItems: 4 - - properties: - compatible: -- const: spacemit,k1-i2s -+ enum: -+ - spacemit,k1-i2s -+ - spacemit,k3-i2s - - reg: - maxItems: 1 - - clocks: -+ minItems: 4 - items: - - description: clock for I2S sysclk - - description: clock for I2S bclk - - description: clock for I2S bus - - description: clock for I2S controller -+ - description: clock for I2S sysclk divider -+ - description: clock for I2S common sysclk -+ - description: clock for I2S common bclk - - clock-names: -+ minItems: 4 - items: - - const: sysclk - - const: bclk - - const: bus - - const: func -+ - const: sysclk_div -+ - const: c_sysclk -+ - const: c_bclk - - dmas: - minItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0367-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux-lts/0367-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch new file mode 100644 index 0000000000..cadb0c3aba --- /dev/null +++ b/SPECS/linux-lts/0367-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch @@ -0,0 +1,97 @@ +From f74e19d0b02f487933837056c19f7c73e05a26f3 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:52 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: enable + USB 3 ports + +Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) +and usbphy2 (USB 2 PHY) on the MusePi Pro board. + +The board uses a VLI VL817 hub, providing four ports. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-5-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 83c658c7a82304a2bc944cdd4a5b4f98d19322f0) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 52 +++++++++++++++++++ + 1 file changed, 52 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 74841cffd5f5..b284bf416880 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -53,6 +53,26 @@ reg_qspi_vcc1v833: regulator-qspi-vcc1v833 { + regulator-always-on; + vin-supply = <&buck4_3v3>; + }; ++ ++ reg_5v_vbus: regulator-5v-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "5V_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ ++ enable-active-high; ++ }; ++ ++ reg_vcc5v_hub: regulator-vcc5v-hub { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V0_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ ++ enable-active-high; ++ }; + }; + + &emmc { +@@ -65,6 +85,10 @@ &emmc { + status = "okay"; + }; + ++&combo_phy { ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -294,3 +318,31 @@ &uart0 { + pinctrl-names = "default"; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ vbus-supply = <®_5v_vbus>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <®_vcc5v_hub>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <®_vcc5v_hub>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch deleted file mode 100644 index f0c06195d2..0000000000 --- a/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch +++ /dev/null @@ -1,112 +0,0 @@ -From ff69086b4bd33d60ba9c418d37ac92992aae8876 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 15:33:10 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: add K3 SoC support with - additional clocks - -Add support for the SpacemiT K3 SoC I2S controller, which shares the -same IP as K1 but requires additional clocks: sysclk_div, c_sysclk, -and c_bclk. These clocks only exist on K3 and are not present on K1. -The sysclk_div clock is present on most K3 I2S controllers except I2S1. -The c_sysclk and c_bclk clocks are shared across multiple I2S -controllers on K3. - -Use devm_clk_get_optional_enabled() to acquire these clocks so that -the driver works on both K1 (where they are absent) and K3 without -needing SoC-specific match data. For K3, the sysclk_div rate is set -before sysclk in set_sysclk, and the common clock rates are configured -in hw_params based on the sample rate. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-2-9cdbf95b7533@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 36 +++++++++++++++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 03cca5d84503..3df94b4ca5a5 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -53,6 +53,9 @@ struct spacemit_i2s_dev { - struct clk *sysclk; - struct clk *bclk; - struct clk *sspa_clk; -+ struct clk *sysclk_div; -+ struct clk *c_sysclk; -+ struct clk *c_bclk; - - struct snd_dmaengine_dai_dma_data capture_dma_data; - struct snd_dmaengine_dai_dma_data playback_dma_data; -@@ -206,6 +209,14 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - params_rate(params) * - data_bits; - -+ ret = clk_set_rate(i2s->c_sysclk, bclk_rate * 2); -+ if (ret) -+ return ret; -+ -+ ret = clk_set_rate(i2s->c_bclk, bclk_rate); -+ if (ret) -+ return ret; -+ - ret = clk_set_rate(i2s->bclk, bclk_rate); - if (ret) - return ret; -@@ -217,10 +228,17 @@ static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, - unsigned int freq, int dir) - { - struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev); -+ int ret; - - if (freq == 0) - return 0; - -+ if (i2s->sysclk_div) { -+ ret = clk_set_rate(i2s->sysclk_div, freq); -+ if (ret) -+ return ret; -+ } -+ - return clk_set_rate(i2s->sysclk, freq); - } - -@@ -435,6 +453,21 @@ static int spacemit_i2s_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(i2s->dev, PTR_ERR(clk), "failed to enable sspa clock\n"); - -+ i2s->sysclk_div = devm_clk_get_optional_enabled(i2s->dev, "sysclk_div"); -+ if (IS_ERR(i2s->sysclk_div)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk_div), -+ "failed to enable sysclk_div clock\n"); -+ -+ i2s->c_sysclk = devm_clk_get_optional_enabled(i2s->dev, "c_sysclk"); -+ if (IS_ERR(i2s->c_sysclk)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_sysclk), -+ "failed to enable c_sysclk clock\n"); -+ -+ i2s->c_bclk = devm_clk_get_optional_enabled(i2s->dev, "c_bclk"); -+ if (IS_ERR(i2s->c_bclk)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_bclk), -+ "failed to enable c_bclk clock\n"); -+ - i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(i2s->base)) - return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n"); -@@ -459,6 +492,7 @@ static int spacemit_i2s_probe(struct platform_device *pdev) - - static const struct of_device_id spacemit_i2s_of_match[] = { - { .compatible = "spacemit,k1-i2s", }, -+ { .compatible = "spacemit,k3-i2s", }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match); -@@ -473,4 +507,4 @@ static struct platform_driver spacemit_i2s_driver = { - module_platform_driver(spacemit_i2s_driver); - - MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1/K3 SoC"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0368-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux-lts/0368-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch new file mode 100644 index 0000000000..8a6cb446cf --- /dev/null +++ b/SPECS/linux-lts/0368-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch @@ -0,0 +1,77 @@ +From 557a84f989292b858f0edca6c24633d20aa1b406 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:53 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: enable + PCIe ports + +Enable the two PCIe controllers along with their associated PHYs. They +are routed to the M.2 M-key connector and to the PCIe slot. + +Signed-off-by: Andre Heider +Link: https://patch.msgid.link/20260513071958.29574-6-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit d9ab0a855ba13f1db3ae16539348714c74010a22) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index b284bf416880..898b537ba0bc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -36,6 +36,14 @@ led1 { + }; + }; + ++ reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PCIE_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "VCC4V0"; +@@ -272,6 +280,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <®_pcie_vcc_3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <®_pcie_vcc_3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch deleted file mode 100644 index 7eaa0d4690..0000000000 --- a/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 0151c24b6a7cffec1479bc57a27443328f1d2fef Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:42 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: soc-dai: add shared BCLK clock for - cross-DAI rate constraints - -Add a bclk field to struct snd_soc_dai and a helper function -snd_soc_dai_set_bclk_clk() that platform drivers can use to declare -which clock is their BCLK. - -Also cache the bclk_ratio in snd_soc_dai_set_bclk_ratio() so that -the framework can use it later in hw_rule evaluation for TDM -configurations where BCLK = rate * slots * slot_width. - -When multiple DAIs on the same card share the same physical BCLK -(detected via clk_is_match()), the ASoC core can automatically -constrain their hw_params so that the resulting BCLK rates are -compatible. This commit adds the data structure support; the actual -constraint logic follows in the next patch. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-1-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - include/sound/soc-dai.h | 7 +++++++ - sound/soc/soc-dai.c | 18 ++++++++++++++++++ - 2 files changed, 25 insertions(+) - -diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h -index 224396927aef..6d3a0ce02fd8 100644 ---- a/include/sound/soc-dai.h -+++ b/include/sound/soc-dai.h -@@ -17,6 +17,7 @@ - struct snd_pcm_substream; - struct snd_soc_dapm_widget; - struct snd_compr_stream; -+struct clk; - - /* - * DAI hardware audio formats. -@@ -173,6 +174,8 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, - - int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); - -+void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); -+ - /* Digital Audio interface formatting */ - int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); - u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); -@@ -451,6 +454,10 @@ struct snd_soc_dai { - unsigned int symmetric_channels; - unsigned int symmetric_sample_bits; - -+ /* shared BCLK clock for cross-DAI rate constraints */ -+ struct clk *bclk; -+ unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ -+ - /* parent platform/codec */ - struct snd_soc_component *component; - -diff --git a/sound/soc/soc-dai.c b/sound/soc/soc-dai.c -index f231b4174b5f..a32501d017f6 100644 ---- a/sound/soc/soc-dai.c -+++ b/sound/soc/soc-dai.c -@@ -116,10 +116,28 @@ int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) - dai->driver->ops->set_bclk_ratio) - ret = dai->driver->ops->set_bclk_ratio(dai, ratio); - -+ if (!ret) -+ dai->bclk_ratio = ratio; -+ - return soc_dai_ret(dai, ret); - } - EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio); - -+/** -+ * snd_soc_dai_set_bclk_clk - set the BCLK clock for shared clock detection -+ * @dai: DAI -+ * @bclk: BCLK clock pointer (or NULL to clear) -+ * -+ * When multiple DAIs share the same physical BCLK (detected via -+ * clk_is_match()), the ASoC core will automatically constrain their -+ * hw_params so that the resulting BCLK rates are compatible. -+ */ -+void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk) -+{ -+ dai->bclk = bclk; -+} -+EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_clk); -+ - int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd) - { - struct snd_soc_dai *dai; --- -2.53.0 - diff --git a/SPECS/linux-lts/0369-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux-lts/0369-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch new file mode 100644 index 0000000000..5854217cb5 --- /dev/null +++ b/SPECS/linux-lts/0369-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch @@ -0,0 +1,35 @@ +From 207accf16e500677ac7c9b1005d049a90ed0cba5 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 13 May 2026 09:19:54 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: set + default console baud rate + +Allow serial output with the same uboot/opensbi settings so the +console works without providing a cmdline. + +Signed-off-by: Andre Heider +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260513071958.29574-7-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit f125c6085fd775f09a316f61cc89a0ae86826895) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 898b537ba0bc..4aef287353ca 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -22,7 +22,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch deleted file mode 100644 index b2112c73cc..0000000000 --- a/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch +++ /dev/null @@ -1,186 +0,0 @@ -From 811d7e0186f2cec4b5ebbd7506439ef84e15a0ff Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:43 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: soc-pcm: constrain hw_params when DAIs - share the same BCLK - -When multiple CPU DAIs on the same sound card share the same physical -BCLK, add a hw_rule during PCM open that constrains the sample rate so -the resulting BCLK rate stays consistent across all sharing DAIs. - -The hw_rule is registered unconditionally for every DAI that has a bclk -clock pointer set. The actual peer scanning happens inside the rule -callback at hw_refine time: it walks all DAIs on the card, looking for -an active peer that shares the same physical BCLK (via clk_is_match()) -and has already completed hw_params (checked via dai->symmetric_rate -!= 0). This ensures the constraint uses the real BCLK rate established -by the peer's clk_set_rate() in hw_params, not a stale boot-time -default. - -The first DAI to complete hw_params is unconstrained (no active peer -yet); subsequent DAIs are constrained to match. - -The rule supports two modes: -- If the DAI has an explicit bclk_ratio set (e.g. for TDM where - BCLK = rate * slots * slot_width), the rate is constrained to - active_bclk_rate / bclk_ratio. -- Otherwise, the default formula BCLK = rate * channels * sample_bits - is used to derive the valid rate range. - -The constraint is purely additive: DAIs that do not set a bclk clock -pointer are completely unaffected. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-2-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/soc-pcm.c | 119 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 119 insertions(+) - -diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c -index 99299364c9ba..c6b01f802b10 100644 ---- a/sound/soc/soc-pcm.c -+++ b/sound/soc/soc-pcm.c -@@ -12,6 +12,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -467,6 +468,117 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream, - return 0; - } - -+/* -+ * Shared BCLK constraint: when multiple DAIs share the same physical BCLK, -+ * constrain hw_params so that the BCLK rate (rate * channels * sample_bits, -+ * or rate * slots * slot_width for TDM) remains consistent. -+ */ -+ -+static int soc_pcm_shared_bclk_rule_rate(struct snd_pcm_hw_params *params, -+ struct snd_pcm_hw_rule *rule) -+{ -+ struct snd_soc_dai *dai = rule->private; -+ struct snd_soc_card *card = dai->component->card; -+ struct snd_soc_pcm_runtime *rtd; -+ struct snd_soc_dai *other_dai; -+ unsigned long active_bclk_rate = 0; -+ struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); -+ struct snd_interval constraint = { .empty = 1 }; -+ unsigned int target_rate; -+ int i; -+ -+ /* -+ * Protect the rtd list traversal. No nesting: this callback runs -+ * from snd_pcm_hw_refine() which does not hold card->mutex. -+ */ -+ guard(mutex)(&card->mutex); -+ -+ /* Scan all DAIs on the card for an active peer sharing the same BCLK */ -+ for_each_card_rtds(card, rtd) { -+ for_each_rtd_cpu_dais(rtd, i, other_dai) { -+ if (other_dai == dai) -+ continue; -+ if (!other_dai->bclk) -+ continue; -+ if (!snd_soc_dai_active(other_dai)) -+ continue; -+ /* -+ * Skip peers whose hw_params hasn't run yet. -+ * symmetric_rate is set by soc_pcm_set_dai_params() -+ * after snd_soc_dai_hw_params(), so non-zero means -+ * the DAI's clk_set_rate() has already executed. -+ */ -+ if (!other_dai->symmetric_rate) -+ continue; -+ if (!clk_is_match(dai->bclk, other_dai->bclk)) -+ continue; -+ -+ active_bclk_rate = clk_get_rate(other_dai->bclk); -+ if (active_bclk_rate) -+ goto found; -+ } -+ } -+ -+ return 0; -+ -+found: -+ if (dai->bclk_ratio) { -+ /* -+ * Driver has set an explicit BCLK ratio (e.g. for TDM where -+ * BCLK = rate * slots * slot_width). The only valid rate is -+ * active_bclk_rate / bclk_ratio. -+ */ -+ target_rate = active_bclk_rate / dai->bclk_ratio; -+ -+ constraint.min = target_rate; -+ constraint.max = target_rate; -+ } else { -+ struct snd_interval *channels = hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_CHANNELS); -+ struct snd_interval *sample_bits = hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS); -+ -+ /* -+ * Default: BCLK = rate * channels * sample_bits. -+ * Calculate the range of valid rates given the current -+ * channel and sample_bits intervals. -+ */ -+ if (!channels->min || !sample_bits->min) -+ return 0; -+ -+ constraint.max = active_bclk_rate / -+ ((unsigned long)channels->min * sample_bits->min); -+ -+ if (channels->max && sample_bits->max) -+ constraint.min = active_bclk_rate / -+ ((unsigned long)channels->max * sample_bits->max); -+ else -+ constraint.min = constraint.max; -+ } -+ -+ constraint.integer = 1; -+ constraint.empty = 0; -+ -+ return snd_interval_refine(rate, &constraint); -+} -+ -+static int soc_pcm_apply_shared_bclk(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ if (!dai->bclk) -+ return 0; -+ -+ dev_dbg(dai->dev, -+ "ASoC: registering shared BCLK rate constraint\n"); -+ -+ return snd_pcm_hw_rule_add(substream->runtime, 0, -+ SNDRV_PCM_HW_PARAM_RATE, -+ soc_pcm_shared_bclk_rule_rate, dai, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS, -+ -1); -+} -+ - static int soc_pcm_params_symmetry(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) - { -@@ -891,6 +1003,13 @@ static int __soc_pcm_open(struct snd_soc_pcm_runtime *rtd, - if (ret != 0) - goto err; - } -+ -+ /* Shared BCLK constraint across DAIs on the same card */ -+ for_each_rtd_cpu_dais(rtd, i, dai) { -+ ret = soc_pcm_apply_shared_bclk(substream, dai); -+ if (ret != 0) -+ goto err; -+ } - dynamic: - snd_soc_runtime_activate(rtd, substream->stream); - ret = 0; --- -2.53.0 - diff --git a/SPECS/linux-lts/0370-UPSTREAM-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux-lts/0370-UPSTREAM-riscv-dts-spacemit-k3-Add-pwm-support.patch new file mode 100644 index 0000000000..ee40fb24cd --- /dev/null +++ b/SPECS/linux-lts/0370-UPSTREAM-riscv-dts-spacemit-k3-Add-pwm-support.patch @@ -0,0 +1,852 @@ +From fd6e40bc55165f03bde310bec4c7dfe51c8ef371 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 21 May 2026 00:24:41 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Add pwm support + +Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents +the pinctrl info which would easily help to enable them in future. + +Link: https://patch.msgid.link/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 844c29197366e25ad361cf725d80acb4f10e3e19) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ + 2 files changed, 810 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 23899d3f308a..252c64af76fe 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -56,6 +56,596 @@ i2c8-pins { + }; + }; + ++ /omit-if-no-ref/ ++ pwm0_0_cfg: pwm0-0-cfg { ++ pwm0-0-pins { ++ pinmux = ; /* pwm0 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0_1_cfg: pwm0-1-cfg { ++ pwm0-1-pins { ++ pinmux = ; /* pwm0 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_0_cfg: pwm1-0-cfg { ++ pwm1-0-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_1_cfg: pwm1-1-cfg { ++ pwm1-1-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_2_cfg: pwm1-2-cfg { ++ pwm1-2-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_0_cfg: pwm2-0-cfg { ++ pwm2-0-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_1_cfg: pwm2-1-cfg { ++ pwm2-1-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_2_cfg: pwm2-2-cfg { ++ pwm2-2-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_3_cfg: pwm2-3-cfg { ++ pwm2-3-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_0_cfg: pwm3-0-cfg { ++ pwm3-0-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_1_cfg: pwm3-1-cfg { ++ pwm3-1-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_2_cfg: pwm3-2-cfg { ++ pwm3-2-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_3_cfg: pwm3-3-cfg { ++ pwm3-3-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_0_cfg: pwm4-0-cfg { ++ pwm4-0-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_1_cfg: pwm4-1-cfg { ++ pwm4-1-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_2_cfg: pwm4-2-cfg { ++ pwm4-2-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_0_cfg: pwm5-0-cfg { ++ pwm5-0-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_1_cfg: pwm5-1-cfg { ++ pwm5-1-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_2_cfg: pwm5-2-cfg { ++ pwm5-2-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_0_cfg: pwm6-0-cfg { ++ pwm6-0-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_1_cfg: pwm6-1-cfg { ++ pwm6-1-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_2_cfg: pwm6-2-cfg { ++ pwm6-2-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_0_cfg: pwm7-0-cfg { ++ pwm7-0-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_1_cfg: pwm7-1-cfg { ++ pwm7-1-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_2_cfg: pwm7-2-cfg { ++ pwm7-2-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_0_cfg: pwm8-0-cfg { ++ pwm8-0-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_1_cfg: pwm8-1-cfg { ++ pwm8-1-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_2_cfg: pwm8-2-cfg { ++ pwm8-2-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_0_cfg: pwm9-0-cfg { ++ pwm9-0-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_1_cfg: pwm9-1-cfg { ++ pwm9-1-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_2_cfg: pwm9-2-cfg { ++ pwm9-2-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_0_cfg: pwm10-0-cfg { ++ pwm10-0-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_1_cfg: pwm10-1-cfg { ++ pwm10-1-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_2_cfg: pwm10-2-cfg { ++ pwm10-2-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11_0_cfg: pwm11-0-cfg { ++ pwm11-0-pins { ++ pinmux = ; /* pwm11 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11_1_cfg: pwm11-1-cfg { ++ pwm11-1-pins { ++ pinmux = ; /* pwm11 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12_0_cfg: pwm12-0-cfg { ++ pwm12-0-pins { ++ pinmux = ; /* pwm12 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12_1_cfg: pwm12-1-cfg { ++ pwm12-1-pins { ++ pinmux = ; /* pwm12 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_0_cfg: pwm13-0-cfg { ++ pwm13-0-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_1_cfg: pwm13-1-cfg { ++ pwm13-1-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_2_cfg: pwm13-2-cfg { ++ pwm13-2-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_0_cfg: pwm14-0-cfg { ++ pwm14-0-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_1_cfg: pwm14-1-cfg { ++ pwm14-1-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_2_cfg: pwm14-2-cfg { ++ pwm14-2-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_0_cfg: pwm15-0-cfg { ++ pwm15-0-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_1_cfg: pwm15-1-cfg { ++ pwm15-1-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_2_cfg: pwm15-2-cfg { ++ pwm15-2-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_0_cfg: pwm16-0-cfg { ++ pwm16-0-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_1_cfg: pwm16-1-cfg { ++ pwm16-1-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_2_cfg: pwm16-2-cfg { ++ pwm16-2-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_0_cfg: pwm17-0-cfg { ++ pwm17-0-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_1_cfg: pwm17-1-cfg { ++ pwm17-1-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_2_cfg: pwm17-2-cfg { ++ pwm17-2-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_0_cfg: pwm18-0-cfg { ++ pwm18-0-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_1_cfg: pwm18-1-cfg { ++ pwm18-1-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_2_cfg: pwm18-2-cfg { ++ pwm18-2-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_0_cfg: pwm19-0-cfg { ++ pwm19-0-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_1_cfg: pwm19-1-cfg { ++ pwm19-1-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_2_cfg: pwm19-2-cfg { ++ pwm19-2-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 9e3c005f7bdf..97cc9e2dd554 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -808,6 +808,226 @@ i2c8: i2c@d401d800 { + status = "disabled"; + }; + ++ pwm0: pwm@d401a000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM0>, ++ <&syscon_apbc CLK_APBC_PWM0_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM0>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@d401a400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM1>, ++ <&syscon_apbc CLK_APBC_PWM1_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM1>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@d401a800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM2>, ++ <&syscon_apbc CLK_APBC_PWM2_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM2>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@d401ac00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401ac00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM3>, ++ <&syscon_apbc CLK_APBC_PWM3_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM3>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@d401b000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM4>, ++ <&syscon_apbc CLK_APBC_PWM4_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM4>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@d401b400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM5>, ++ <&syscon_apbc CLK_APBC_PWM5_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM5>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@d401b800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM6>, ++ <&syscon_apbc CLK_APBC_PWM6_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM6>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@d401bc00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401bc00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM7>, ++ <&syscon_apbc CLK_APBC_PWM7_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM7>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@d4020000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM8>, ++ <&syscon_apbc CLK_APBC_PWM8_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM8>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@d4020400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM9>, ++ <&syscon_apbc CLK_APBC_PWM9_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM9>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@d4020800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM10>, ++ <&syscon_apbc CLK_APBC_PWM10_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM10>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@d4020c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM11>, ++ <&syscon_apbc CLK_APBC_PWM11_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM11>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@d4021000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM12>, ++ <&syscon_apbc CLK_APBC_PWM12_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM12>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@d4021400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM13>, ++ <&syscon_apbc CLK_APBC_PWM13_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM13>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@d4021800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM14>, ++ <&syscon_apbc CLK_APBC_PWM14_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM14>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@d4021c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM15>, ++ <&syscon_apbc CLK_APBC_PWM15_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM15>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm16: pwm@d4022000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM16>, ++ <&syscon_apbc CLK_APBC_PWM16_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM16>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm17: pwm@d4022400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM17>, ++ <&syscon_apbc CLK_APBC_PWM17_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM17>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm18: pwm@d4022800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM18>, ++ <&syscon_apbc CLK_APBC_PWM18_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM18>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm19: pwm@d4022c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM19>, ++ <&syscon_apbc CLK_APBC_PWM19_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM19>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch deleted file mode 100644 index ff936b2c7c..0000000000 --- a/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch +++ /dev/null @@ -1,37 +0,0 @@ -From ab006e609e125b2253d6016108a7ac52e642a192 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:44 +0800 -Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for - cross-DAI rate constraint - -On SpacemiT K3, multiple I2S controllers share the same physical BCLK -(c_bclk). Declare this clock via snd_soc_dai_set_bclk_clk() so the -ASoC core can automatically constrain hw_params when one controller is -already streaming. - -For K1, c_bclk is NULL (obtained via devm_clk_get_optional_enabled), -so this call is a no-op and behavior is unchanged. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-3-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 3df94b4ca5a5..1a02d7fcc7e1 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -323,6 +323,8 @@ static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai) - - spacemit_i2s_init(i2s); - -+ snd_soc_dai_set_bclk_clk(dai, i2s->c_bclk); -+ - return 0; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0371-UPSTREAM-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux-lts/0371-UPSTREAM-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch new file mode 100644 index 0000000000..8ac8b11460 --- /dev/null +++ b/SPECS/linux-lts/0371-UPSTREAM-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch @@ -0,0 +1,58 @@ +From 8fa4a6e89eabd9eeee5bce6b7db92337c1c77302 Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Sat, 6 Jun 2026 20:17:52 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: use sysfs_emit in cpu_show_ghostwrite + +Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is +preferred for formatting sysfs output because it provides safer bounds +checking. + +While the current code only emits fixed strings that fit easily within +PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. + +Signed-off-by: Thorsten Blum +Link: https://patch.msgid.link/20260510165420.109453-3-thorsten.blum@linux.dev +Signed-off-by: Paul Walmsley +(cherry picked from commit 7d0dec57e52c7b5e14ba4ab6f86e9c17b850f1ec) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/bugs.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c +index 3655fe7d678c..e5758e3f1c7e 100644 +--- a/arch/riscv/kernel/bugs.c ++++ b/arch/riscv/kernel/bugs.c +@@ -5,7 +5,7 @@ + + #include + #include +-#include ++#include + + #include + #include +@@ -46,15 +46,15 @@ ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *attr, c + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { + switch (ghostwrite_state) { + case UNAFFECTED: +- return sprintf(buf, "Not affected\n"); ++ return sysfs_emit(buf, "Not affected\n"); + case MITIGATED: +- return sprintf(buf, "Mitigation: xtheadvector disabled\n"); ++ return sysfs_emit(buf, "Mitigation: xtheadvector disabled\n"); + case VULNERABLE: + fallthrough; + default: +- return sprintf(buf, "Vulnerable\n"); ++ return sysfs_emit(buf, "Vulnerable\n"); + } +- } else { +- return sprintf(buf, "Not affected\n"); + } ++ ++ return sysfs_emit(buf, "Not affected\n"); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch deleted file mode 100644 index 26e3e584c6..0000000000 --- a/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fd1098639a4174a54cfc40a6fe40bbcb9569aee6 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 5 May 2026 09:53:34 -0400 -Subject: [RUYI PATCH] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC to - avoid 32-bit overflow - -NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * -BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures -before the result reaches the u64 nsec_per_word. - -Promote the multiplication to u64 by casting the first operand, which is -NSEC_PER_SEC. - -Fixes: efcd8b9d1111 ("spi: spacemit: introduce SpacemiT K1 SPI controller driver") -Suggested-by: Alex Elder -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202605050437.RS6mmV2b-lkp@intel.com/ -Closes: https://lore.kernel.org/oe-kbuild-all/202605050317.Tf9j487w-lkp@intel.com/ -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260505-spi-spacemit-k1-fix-overflow-v1-1-77564c2e4e86@riscstar.com -Signed-off-by: Han Gao ---- - drivers/spi/spi-spacemit-k1.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c -index 99db429db0b2..215fe66d27b4 100644 ---- a/drivers/spi/spi-spacemit-k1.c -+++ b/drivers/spi/spi-spacemit-k1.c -@@ -390,7 +390,7 @@ static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, - * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; - * We do the divide last for better accuracy. - */ -- nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; -+ nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; - nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); - - /* --- -2.53.0 - diff --git a/SPECS/linux-lts/0372-UPSTREAM-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux-lts/0372-UPSTREAM-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch new file mode 100644 index 0000000000..ddab01031a --- /dev/null +++ b/SPECS/linux-lts/0372-UPSTREAM-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch @@ -0,0 +1,52 @@ +From a93178e11905ffbe2651c6f1c30c59732b11a4ba Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:09 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: Switch to pll2_d6 as parent + for PCIe clock + +According to SpacemiT updated docs, the PCIe master and slave clock's +parent is the pll2_d6 clock, so fix it. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit d8a4cef90b1a4ae9196a5bfba683eb9a0c75acdc) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index bb8b75bdbdb3..1a53b14739fe 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents[] = { + }; + CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); + +-CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); +-CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); +-CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); +-CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); +-CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); +-CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); +-CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); +-CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); +-CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); +-CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); ++CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); ++CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); ++CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); ++CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); ++CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); + + static const struct clk_parent_data emac_1588_parents[] = { + CCU_PARENT_NAME(vctcxo_24m), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch deleted file mode 100644 index 1ec5840379..0000000000 --- a/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 70157c501907a5cde732fdf89f3f458d3aba2959 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:16:59 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC - subsys clock controller - -TH1520 has a subsystem clock controller called MISC_SUBSYS in its -manual, mainly controlling clocks for USB and MMC/SD in non-TEE -environment. - -Add device tree binding for it. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-2-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- - include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ - 2 files changed, 13 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -index 9d058c00ab3d..d46d13597466 100644 ---- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -@@ -23,6 +23,7 @@ properties: - compatible: - enum: - - thead,th1520-clk-ap -+ - thead,th1520-clk-misc - - thead,th1520-clk-vo - - reg: -@@ -32,8 +33,8 @@ properties: - items: - - description: | - One input clock: -- - For "thead,th1520-clk-ap": the clock input must be the 24 MHz -- main oscillator. -+ - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clock -+ input must be the 24 MHz main oscillator. - - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, - which is configured by the AP clock controller. According to the - TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL -diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h -index 68b35cc61204..642c2a69a579 100644 ---- a/include/dt-bindings/clock/thead,th1520-clk-ap.h -+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h -@@ -128,4 +128,14 @@ - #define CLK_MIPIDSI1_PIXCLK 29 - #define CLK_HDMI_PIXCLK 30 - -+/* MISC clocks */ -+#define CLK_MISCSYS_ACLK 0 -+#define CLK_USB 1 -+#define CLK_USB_CTL_REF 2 -+#define CLK_USB_PHY_REF 3 -+#define CLK_USB_SUSPEND 4 -+#define CLK_EMMC 5 -+#define CLK_SDIO0 6 -+#define CLK_SDIO1 7 -+ - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0373-UPSTREAM-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux-lts/0373-UPSTREAM-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch new file mode 100644 index 0000000000..3fcf131ac8 --- /dev/null +++ b/SPECS/linux-lts/0373-UPSTREAM-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch @@ -0,0 +1,37 @@ +From 53b13f1ef4c5ee060d5fc719b83e18200029aac8 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:10 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: Fix PCIe clock register + offset + +The offset of PCIe Clock CTRL register for port B and C controller was +wrongly swapped, correct it here. + +Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 2f20c859a82a291483a8b3f01cbfbb1642782a14) +Signed-off-by: Han Gao +--- + include/soc/spacemit/k3-syscon.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +index 0299bea065a0..a68255dd641f 100644 +--- a/include/soc/spacemit/k3-syscon.h ++++ b/include/soc/spacemit/k3-syscon.h +@@ -168,8 +168,8 @@ + #define APMU_CPU_C2_CLK_CTRL 0x394 + #define APMU_CPU_C3_CLK_CTRL 0x208 + #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 +-#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 +-#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 + #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 + #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 + #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch deleted file mode 100644 index 4e7272cafb..0000000000 --- a/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch +++ /dev/null @@ -1,124 +0,0 @@ -From ff7baa8d99b3acfa161a96f9d572688e8fbfb14f Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:00 +0800 -Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC - subsys clocks - -The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows -controlling of USB related clocks and MMC/SD controller AHB bus clocks. - -Add support for this clock controller, in order to enable USB support. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-3-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ - 1 file changed, 64 insertions(+) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index 3a6847f1c950..24f785f0b329 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", - static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, - 0x4, 0, 0); - -+static struct clk_fixed_factor usb_suspend_div_clk = { -+ .div = 24, -+ .mult = 1, -+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", -+ osc_24m_clk, -+ &clk_fixed_factor_ops, -+ 0), -+}; -+ -+static const struct clk_parent_data usb_suspend_parents[] = { -+ { .hw = &usb_suspend_div_clk.hw }, -+}; -+ -+static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_pd, -+ 0x0, 0, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data miscsys_aclk_pd[] = { -+ { .hw = &miscsys_aclk.gate.hw }, -+}; -+ -+static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, -+ CLK_IS_CRITICAL); -+static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_clk, -+ 0x4, 1, 0); -+static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_clk, -+ 0x4, 2, 0); -+static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", -+ usb_suspend_parents, 0x4, 3, 0); -+static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, -+ 0); -+static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, -+ 0); -+static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, 0, -+ 0); -+ - static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", - &gmac_pll_clk.common.hw, 10, 1, 0); - -@@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] = { - &hdmi_pixclk - }; - -+static struct ccu_gate *th1520_misc_gate_clks[] = { -+ &miscsys_aclk, -+ &usb_clk, -+ &usb_ctl_ref_clk, -+ &usb_phy_ref_clk, -+ &usb_suspend_clk, -+ &emmc_clk, -+ &sdio0_clk, -+ &sdio1_clk -+}; -+ - static const struct regmap_config th1520_clk_regmap_config = { - .reg_bits = 32, - .val_bits = 32, -@@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platdata = { - .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), - }; - -+static const struct th1520_plat_data th1520_misc_platdata = { -+ .th1520_gate_clks = th1520_misc_gate_clks, -+ -+ .nr_clks = CLK_SDIO1 + 1, -+ -+ .nr_gate_clks = ARRAY_SIZE(th1520_misc_gate_clks), -+}; -+ - /* - * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) - * when its parent, c910_clk, changes the rate. -@@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *pdev) - return ret; - } - -+ if (plat_data == &th1520_ap_platdata) { -+ ret = devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); -+ if (ret) -+ return ret; -+ } -+ - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); - if (ret) - return ret; -@@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = { - .compatible = "thead,th1520-clk-vo", - .data = &th1520_vo_platdata, - }, -+ { -+ .compatible = "thead,th1520-clk-misc", -+ .data = &th1520_misc_platdata, -+ }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, th1520_clk_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0374-UPSTREAM-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux-lts/0374-UPSTREAM-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch new file mode 100644 index 0000000000..70f651133b --- /dev/null +++ b/SPECS/linux-lts/0374-UPSTREAM-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch @@ -0,0 +1,36 @@ +From 8f46d831880adb7e2d1fd0f12e3decdfb1481f54 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:11 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: k3: Add PCIe DBI + clock IDs + +Add clock IDs of PCIe DBI (Data Bus Interface) clock. + +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 7a2db70a3196717bfb01415b6dde1f90d4291ab1) +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index b22336f3ae40..dfae52547cda 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -380,6 +380,11 @@ + #define CLK_APMU_ISIM_VCLK1 86 + #define CLK_APMU_ISIM_VCLK2 87 + #define CLK_APMU_ISIM_VCLK3 88 ++#define CLK_APMU_PCIE_PORTA_DBI 89 ++#define CLK_APMU_PCIE_PORTB_DBI 90 ++#define CLK_APMU_PCIE_PORTC_DBI 91 ++#define CLK_APMU_PCIE_PORTD_DBI 92 ++#define CLK_APMU_PCIE_PORTE_DBI 93 + + /* DCIU clocks */ + #define CLK_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch deleted file mode 100644 index 5712f59936..0000000000 --- a/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 25858e77df3fb64d1db8a210aa513630aa172761 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:01 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for - MISC clock controller - -The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller -mainly controlling USB-related clocks (which isn't utilized yet) and -MMC/SD controllers' AHB bus clocks. - -Add the device tree node for it along with the missing bus clock -references for MMC/SD controllers. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-4-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 2910249e1f0c..4d1e71227339 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -401,8 +401,8 @@ emmc: mmc@ffe7080000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -410,8 +410,8 @@ sdio0: mmc@ffe7090000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -419,8 +419,8 @@ sdio1: mmc@ffe70a0000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -568,6 +568,13 @@ rst_misc: reset-controller@ffec02c000 { - #reset-cells = <1>; - }; - -+ clk_misc: clock-controller@ffec02c100 { -+ compatible = "thead,th1520-clk-misc"; -+ reg = <0xff 0xec02c100 0x0 0x100>; -+ clocks = <&osc>; -+ #clock-cells = <1>; -+ }; -+ - rst_vp: reset-controller@ffecc30000 { - compatible = "thead,th1520-reset-vp"; - reg = <0xff 0xecc30000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0375-UPSTREAM-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux-lts/0375-UPSTREAM-clk-spacemit-k3-Add-PCIe-DBI-clock.patch new file mode 100644 index 0000000000..4f2a5c9ce1 --- /dev/null +++ b/SPECS/linux-lts/0375-UPSTREAM-clk-spacemit-k3-Add-PCIe-DBI-clock.patch @@ -0,0 +1,64 @@ +From 081afca5f2f91c2228a833a5801c4728a834dd88 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: Add PCIe DBI clock + +Add PCIe DBI (Data Bus Interface) clock which was missing, This will +support PCIe driver to explicitly request and enable all clocks that +needed. + +Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit a37c75d7b5bb7f3344b0e639b313ac5ace6244ff) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 1a53b14739fe..cb0c4277f72a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT + + CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); + CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0); + CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); + CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0); + CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); + CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0); + CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); + CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0); + CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); + CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0); + + static const struct clk_parent_data emac_1588_parents[] = { + CCU_PARENT_NAME(vctcxo_24m), +@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { + [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, + [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw, + [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, + [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, + [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch deleted file mode 100644 index d6fc48cce2..0000000000 --- a/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch +++ /dev/null @@ -1,102 +0,0 @@ -From bf1bce6b58599f811e5d960528b05a56606c6198 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:02 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head - TH1520 USB PHY - -The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom -glue logic configuring PHY parameters. - -Add a binding for it. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-5-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ - 1 file changed, 74 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml -new file mode 100644 -index 000000000000..37f5cfb95bad ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml -@@ -0,0 +1,74 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: T-Head TH1520 USB PHY -+ -+description: | -+ The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some -+ custom logic to configure PHY parameters. -+ -+maintainers: -+ - Icenowy Zheng -+ - Wei Fu -+ - Drew Fustini -+ -+properties: -+ compatible: -+ const: thead,th1520-usb-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 0 -+ -+ clocks: -+ items: -+ - description: PHY bus clock -+ - description: PHY reference clock -+ -+ clock-names: -+ items: -+ - const: bus -+ - const: ref -+ -+ resets: -+ items: -+ - description: PHY bus reset -+ - description: PHY reset -+ -+ reset-names: -+ items: -+ - const: bus -+ - const: phy -+ -+ avdd33-usb3-supply: -+ description: | -+ 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. -+ -+required: -+ - compatible -+ - "#phy-cells" -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - avdd33-usb3-supply -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@ec030000 { -+ compatible = "thead,th1520-usb-phy"; -+ reg = <0xec030000 0x10000>; -+ #phy-cells = <0>; -+ clocks = <&clk_misc 1>, <&clk_misc 3>; -+ clock-names = "bus", "ref"; -+ resets = <&rst_misc 6>, <&rst_misc 7>; -+ reset-names = "bus", "phy"; -+ avdd33-usb3-supply = <&avdd33_usb3>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0376-UPSTREAM-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux-lts/0376-UPSTREAM-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch new file mode 100644 index 0000000000..72d5f97116 --- /dev/null +++ b/SPECS/linux-lts/0376-UPSTREAM-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch @@ -0,0 +1,43 @@ +From 872ef7cb6e8323840b32a1d5db9356728075bcd0 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 9 May 2026 18:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable eMMC for OrangePi + RV2 + +The OrangePi RV2 board has one eMMC slot, so enable eMMC. +Tested using a 16 GiB AJTD4R eMMC module. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260509100000.3315109-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit f068b204555ad62d6a841a49feb4ea8c4f45b25c) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 3a829e3c9cbc..c95ca38e3d4a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -78,6 +78,16 @@ &combo_phy { + status = "okay"; + }; + ++&emmc { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ no-sd; ++ no-sdio; ++ non-removable; ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch deleted file mode 100644 index f37bec7b80..0000000000 --- a/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 6836defb3d09054866bd4165ee60f3bcd6135b07 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:03 +0800 -Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY - -The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with -some PHY parameters exported as another system controller along with it. - -As a few PHY parameters' default value isn't ready to work, add a driver -configuring them before letting the PHY run, in addition to -clock/reset/regulator management. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-6-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - drivers/phy/Makefile | 1 + - drivers/phy/thead/Kconfig | 12 ++ - drivers/phy/thead/Makefile | 2 + - drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ - 5 files changed, 213 insertions(+) - create mode 100644 drivers/phy/thead/Kconfig - create mode 100644 drivers/phy/thead/Makefile - create mode 100644 drivers/phy/thead/phy-th1520-usb.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 88ea9af445b1..75c4af62f92a 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -140,6 +140,7 @@ source "drivers/phy/st/Kconfig" - source "drivers/phy/starfive/Kconfig" - source "drivers/phy/sunplus/Kconfig" - source "drivers/phy/tegra/Kconfig" -+source "drivers/phy/thead/Kconfig" - source "drivers/phy/ti/Kconfig" - source "drivers/phy/intel/Kconfig" - source "drivers/phy/xilinx/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index 950dd4f14372..5dffb5fcef3d 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -42,5 +42,6 @@ obj-y += allwinner/ \ - starfive/ \ - sunplus/ \ - tegra/ \ -+ thead/ \ - ti/ \ - xilinx/ -diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig -new file mode 100644 -index 000000000000..14012db5973c ---- /dev/null -+++ b/drivers/phy/thead/Kconfig -@@ -0,0 +1,12 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config PHY_TH1520_USB -+ tristate "USB PHY driver for T-Head TH1520 SoC" -+ depends on ARCH_THEAD || COMPILE_TEST -+ depends on COMMON_CLK -+ depends on HAS_IOMEM -+ depends on OF -+ depends on RESET_CONTROLLER -+ select GENERIC_PHY -+ default ARCH_THEAD -+ help -+ Enable support for the USB PHY on the T-Head TH1520 SoC. -diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile -new file mode 100644 -index 000000000000..5b459bc7004b ---- /dev/null -+++ b/drivers/phy/thead/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_TH1520_USB) += phy-th1520-usb.o -diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1520-usb.c -new file mode 100644 -index 000000000000..c87bd779bbb7 ---- /dev/null -+++ b/drivers/phy/thead/phy-th1520-usb.c -@@ -0,0 +1,197 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) -+ * -+ * Authors: -+ * Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define USB_SYSCON_OFFSET 0xf000 -+ -+/* All the below registers are in the USB syscon region */ -+#define USB_CLK_GATE_STS 0x0 -+#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 -+#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 -+#define USB_GPIO 0xc -+#define USB_DEBUG_STS0 0x10 -+#define USB_DEBUG_STS1 0x14 -+#define USB_DEBUG_STS2 0x18 -+#define USBCTL_CLK_CTRL0 0x1c -+#define USBPHY_CLK_CTRL1 0x20 -+#define USBPHY_TEST_CTRL0 0x24 -+#define USBPHY_TEST_CTRL1 0x28 -+#define USBPHY_TEST_CTRL2 0x2c -+#define USBPHY_TEST_CTRL3 0x30 -+#define USB_SSP_EN 0x34 -+#define USB_HADDR_SEL 0x38 -+#define USB_SYS 0x3c -+#define USB_HOST_STATUS 0x40 -+#define USB_HOST_CTRL 0x44 -+#define USBPHY_HOST_CTRL 0x48 -+#define USBPHY_HOST_STATUS 0x4c -+#define USB_TEST_REG0 0x50 -+#define USB_TEST_REG1 0x54 -+#define USB_TEST_REG2 0x58 -+#define USB_TEST_REG3 0x5c -+ -+#define USB_SYS_COMMONONN BIT(0) -+ -+#define USB_SSP_EN_REF_SSP_EN BIT(0) -+ -+struct th1520_usb_phy { -+ struct platform_device *pdev; -+ struct phy *phy; -+ struct regmap *regmap; -+ struct clk *ref_clk; -+ struct reset_control *phy_reset; -+}; -+ -+static int th1520_usb_phy_init(struct phy *phy) -+{ -+ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = clk_prepare_enable(th1520_phy->ref_clk); -+ if (ret) -+ return ret; -+ -+ ret = reset_control_assert(th1520_phy->phy_reset); -+ if (ret) -+ goto err_disable_clk; -+ -+ /* -+ * Do some initial PHY setup: -+ * - Set COMMONONN to allow the PHY to automatically power down. -+ * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed -+ * PHY clock PLL. -+ */ -+ regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); -+ regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); -+ -+ ret = reset_control_deassert(th1520_phy->phy_reset); -+ if (ret) -+ goto err_disable_clk; -+ -+ udelay(10); -+ -+ return 0; -+ -+err_disable_clk: -+ clk_disable_unprepare(th1520_phy->ref_clk); -+ return ret; -+} -+ -+static int th1520_usb_phy_exit(struct phy *phy) -+{ -+ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = reset_control_assert(th1520_phy->phy_reset); -+ if (ret) -+ return ret; -+ -+ clk_disable_unprepare(th1520_phy->ref_clk); -+ -+ return 0; -+} -+ -+static const struct phy_ops th1520_usb_phy_ops = { -+ .init = th1520_usb_phy_init, -+ .exit = th1520_usb_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct regmap_config phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = USB_TEST_REG3, -+}; -+ -+static int th1520_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct th1520_usb_phy *th1520_phy; -+ struct reset_control *bus_reset; -+ void __iomem *base; -+ int ret; -+ -+ th1520_phy = devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); -+ if (!th1520_phy) -+ return -ENOMEM; -+ -+ th1520_phy->pdev = pdev; -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ th1520_phy->ref_clk = devm_clk_get(dev, "ref"); -+ if (IS_ERR(th1520_phy->ref_clk)) -+ return PTR_ERR(th1520_phy->ref_clk); -+ -+ /* De-assert the bus reset and leave it that way */ -+ bus_reset = devm_reset_control_get_exclusive_deasserted(dev, "bus"); -+ if (IS_ERR(bus_reset)) -+ return PTR_ERR(bus_reset); -+ -+ th1520_phy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); -+ if (IS_ERR(th1520_phy->phy_reset)) -+ return PTR_ERR(th1520_phy->phy_reset); -+ -+ /* -+ * Schematics of several boards (Lichee Module 4A/Milk-V Meles) -+ * describe this power rail as always-on. -+ */ -+ ret = devm_regulator_get_enable(dev, "avdd33-usb3"); -+ if (ret) -+ return ret; -+ -+ th1520_phy->regmap = devm_regmap_init_mmio_clk(dev, "bus", -+ base + USB_SYSCON_OFFSET, -+ &phy_regmap_config); -+ if (IS_ERR(th1520_phy->regmap)) -+ return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), -+ "Failed to init regmap\n"); -+ -+ th1520_phy->phy = devm_phy_create(dev, dev->of_node, &th1520_usb_phy_ops); -+ if (IS_ERR(th1520_phy->phy)) { -+ dev_err(dev, "failed to create PHY\n"); -+ return PTR_ERR(th1520_phy->phy); -+ } -+ -+ phy_set_drvdata(th1520_phy->phy, th1520_phy); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id th1520_usb_phy_of_table[] = { -+ { .compatible = "thead,th1520-usb-phy" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); -+ -+static struct platform_driver th1520_usb_phy_driver = { -+ .driver = { -+ .name = "th1520-usb-phy", -+ .of_match_table = th1520_usb_phy_of_table, -+ }, -+ .probe = th1520_usb_phy_probe, -+}; -+ -+module_platform_driver(th1520_usb_phy_driver); -+ -+MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0377-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux-lts/0377-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch new file mode 100644 index 0000000000..0a425df319 --- /dev/null +++ b/SPECS/linux-lts/0377-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch @@ -0,0 +1,60 @@ +From 19b475e9164d312914d231c056b3ef86feca6701 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:56 +0200 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add pinctrl + support for voltage switching + +Document pinctrl properties to support voltage-dependent pin +configuration switching for UHS-I SD card modes. + +Add optional pinctrl-names property with two states: +- "default": For 3.3V operation with standard drive strength +- "state_uhs": For 1.8V operation with optimized drive strength + +These pinctrl states allow the SDHCI driver to coordinate voltage +switching with pin configuration changes, ensuring proper signal +integrity during UHS-I mode transitions. + +Acked-by: Conor Dooley +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit 04a8ddc39e5cfebffb06f383350a6ee393ba89a6) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 9a055d963a7f..34d202af909f 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -44,6 +44,18 @@ properties: + - const: axi + - const: sdh + ++ pinctrl-names: ++ minItems: 1 ++ items: ++ - const: default ++ - const: uhs ++ ++ pinctrl-0: ++ description: Default pinctrl state for 3.3V operation ++ ++ pinctrl-1: ++ description: Optional pinctrl state for 1.8V UHS operation with "uhs" name ++ + required: + - compatible + - reg +@@ -62,4 +74,7 @@ examples: + interrupt-parent = <&plic>; + clocks = <&clk_apmu 10>, <&clk_apmu 13>; + clock-names = "core", "io"; ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&sdhci_default_cfg>; ++ pinctrl-1 = <&sdhci_uhs_cfg>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch deleted file mode 100644 index 01b5e27c73..0000000000 --- a/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 2be6de531146e3cb05e762c17c5d087a15b3ad2d Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:04 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB - -The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 -Dual Role Device controller in addition to a USB2+USB3 combo PHY based -on Synopsys USB3.0 FemtoPHY. - -Add device tree nodes for them. The USB controller is quite generic, new -and properly configured during silicon design, but the PHY is a little -quirky. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-7-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 4d1e71227339..f1746b5fcd40 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -351,6 +351,20 @@ uart0: serial@ffe7014000 { - status = "disabled"; - }; - -+ usb: usb@ffe7040000 { -+ compatible = "snps,dwc3"; -+ reg = <0xff 0xe7040000 0x0 0x10000>; -+ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_misc CLK_USB>, -+ <&clk_misc CLK_USB_CTL_REF>, -+ <&clk_misc CLK_USB_SUSPEND>; -+ clock-names = "bus_early", "ref", "suspend"; -+ resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>; -+ phys = <&usb_phy>; -+ phy-names = "usb3-phy"; -+ status = "disabled"; -+ }; -+ - gmac1: ethernet@ffe7060000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; -@@ -575,6 +589,19 @@ clk_misc: clock-controller@ffec02c100 { - #clock-cells = <1>; - }; - -+ usb_phy: phy@ffec030000 { -+ compatible = "thead,th1520-usb-phy"; -+ reg = <0xff 0xec030000 0x0 0x10000>; -+ clocks = <&clk_misc CLK_USB>, -+ <&clk_misc CLK_USB_PHY_REF>; -+ clock-names = "bus", "ref"; -+ resets = <&rst_misc TH1520_RESET_ID_USB3_APB>, -+ <&rst_misc TH1520_RESET_ID_USB3_PHY>; -+ reset-names = "bus", "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - rst_vp: reset-controller@ffecc30000 { - compatible = "thead,th1520-reset-vp"; - reg = <0xff 0xecc30000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0378-UPSTREAM-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux-lts/0378-UPSTREAM-mmc-sdhci-of-k1-enable-essential-clock-infr.patch new file mode 100644 index 0000000000..5abba2823e --- /dev/null +++ b/SPECS/linux-lts/0378-UPSTREAM-mmc-sdhci-of-k1-enable-essential-clock-infr.patch @@ -0,0 +1,66 @@ +From 512992b87de645b36c37feea9f28f4c99659e543 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:57 +0200 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: enable essential clock + infrastructure for SD operation + +Ensure SD card pins receive clock signals by enabling pad clock +generation and overriding automatic clock gating. Required for all SD +operation modes. + +The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD +and eMMC operation as both protocols use the same physical MMC interface +pins and require proper clock signal generation at the hardware level +for signal integrity and timing. + +Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and +SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only +controllers to handle removable card scenarios. + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit f87b273e4b6dfe57dcd63c24cbe3764d1f6954ae) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 455656f9842d..0dd06fc19b85 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -21,6 +21,13 @@ + #include "sdhci.h" + #include "sdhci-pltfm.h" + ++#define SPACEMIT_SDHC_OP_EXT_REG 0x108 ++#define SDHC_OVRRD_CLK_OEN BIT(11) ++#define SDHC_FORCE_CLK_ON BIT(12) ++ ++#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C ++#define SDHC_GEN_PAD_CLK_ON BIT(6) ++ + #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 + #define SDHC_MISC_INT_EN BIT(1) + #define SDHC_MISC_INT BIT(2) +@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + + if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) + spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); ++ ++ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) ++ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, ++ SPACEMIT_SDHC_OP_EXT_REG); + } + + static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch deleted file mode 100644 index bd9aea764d..0000000000 --- a/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b2708e5bb25843313bbb63f5c6417d756f0ce5e0 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:05 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs - -GPIO hogs are described in the gpio.txt binding as automatic default -GPIO configuration items. - -Allow them for GPIO ports in DesignWare APB GPIO controller nodes. - -Cc: Hoan Tran -Cc: Linus Walleij -Cc: Bartosz Golaszewski -Cc: Serge Semin -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-8-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -index ab2afc0e4153..79679a14a02f 100644 ---- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -+++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -@@ -95,6 +95,12 @@ patternProperties: - '#interrupt-cells': - const: 2 - -+ patternProperties: -+ "^.+-hog(-[0-9]+)?$": -+ type: object -+ required: -+ - gpio-hog -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux-lts/0379-UPSTREAM-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux-lts/0379-UPSTREAM-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch new file mode 100644 index 0000000000..b4b1be4746 --- /dev/null +++ b/SPECS/linux-lts/0379-UPSTREAM-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch @@ -0,0 +1,145 @@ +From 736364c56c6d5f971133c00a40d564d6771ce992 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:58 +0200 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add regulator and pinctrl + voltage switching support + +Add voltage switching infrastructure for UHS-I modes by integrating both +regulator framework (for supply voltage control) and pinctrl state +switching (for pin drive strength optimization). + +- Add regulator supply parsing and voltage switching callback +- Add optional pinctrl state switching between "default" (3.3V) and + "state_uhs" (1.8V) configurations +- Enable coordinated voltage and pin configuration changes for UHS modes + +This provides complete voltage switching support while maintaining +backward compatibility when pinctrl states are not defined. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Acked-by: Adrian Hunter +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit 00a97fc57c09ff1cf71107753d9b5629caeb8c8a) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ + 1 file changed, 72 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 0dd06fc19b85..d9144537032a 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -71,6 +72,9 @@ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pinctrl_default; ++ struct pinctrl_state *pinctrl_uhs; + }; + + /* All helper functions will update clr/set while preserve rest bits */ +@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) + SPACEMIT_SDHC_PHY_CTRL_REG); + } + ++static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, ++ struct mmc_ios *ios) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ struct pinctrl_state *state; ++ int ret; ++ ++ ret = sdhci_start_signal_voltage_switch(mmc, ios); ++ if (ret) ++ return ret; ++ ++ if (!sdhst->pinctrl) ++ return 0; ++ ++ /* Select appropriate pinctrl state based on signal voltage */ ++ switch (ios->signal_voltage) { ++ case MMC_SIGNAL_VOLTAGE_330: ++ state = sdhst->pinctrl_default; ++ break; ++ case MMC_SIGNAL_VOLTAGE_180: ++ state = sdhst->pinctrl_uhs; ++ break; ++ default: ++ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); ++ return 0; ++ } ++ ++ ret = pinctrl_select_state(sdhst->pinctrl, state); ++ if (ret) { ++ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); ++ return 0; ++ } ++ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", ++ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); ++ ++ return 0; ++} ++ + static inline int spacemit_sdhci_get_clocks(struct device *dev, + struct sdhci_pltfm_host *pltfm_host) + { +@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) + return 0; + } + ++static inline void spacemit_sdhci_get_pins(struct device *dev, ++ struct sdhci_pltfm_host *pltfm_host) ++{ ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ ++ sdhst->pinctrl = devm_pinctrl_get(dev); ++ if (IS_ERR(sdhst->pinctrl)) { ++ sdhst->pinctrl = NULL; ++ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); ++ return; ++ } ++ ++ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); ++ if (IS_ERR(sdhst->pinctrl_default)) ++ sdhst->pinctrl_default = NULL; ++ ++ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); ++ if (IS_ERR(sdhst->pinctrl_uhs)) ++ sdhst->pinctrl_uhs = NULL; ++ ++ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", ++ sdhst->pinctrl_default, sdhst->pinctrl_uhs); ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -324,6 +392,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + + host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; + ++ spacemit_sdhci_get_pins(dev, pltfm_host); ++ ++ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; ++ + ret = spacemit_sdhci_get_clocks(dev, pltfm_host); + if (ret) + goto err_pltfm; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch deleted file mode 100644 index 00f4949ecd..0000000000 --- a/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch +++ /dev/null @@ -1,48 +0,0 @@ -From d114c66e2f27fb7d5c538f14399ab98ce4960f83 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:06 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports - property - -As a USB hub device, VL817 can surely be connected to external USB -connectors. The binding for such connectors connection is already -described in the generic usb-hub.yaml binding with ports subnode, but -it's not yet allowed in the VL817 binding. - -Switch the reference binding from usb-device.yaml to usb-hub.yaml (which -recursively references usb-device.yaml and contains definition for ports -subnode) and allow ports subnode in VL817 binding. - -Cc: Anand Moon -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-9-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -index c815010ba9c2..7387f4fae54d 100644 ---- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -+++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -@@ -10,7 +10,7 @@ maintainers: - - Anand Moon - - allOf: -- - $ref: usb-device.yaml# -+ - $ref: usb-hub.yaml# - - properties: - compatible: -@@ -34,6 +34,8 @@ properties: - description: - phandle to the peer hub on the controller. - -+ ports: true -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux-lts/0380-UPSTREAM-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux-lts/0380-UPSTREAM-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch new file mode 100644 index 0000000000..0f282ac34c --- /dev/null +++ b/SPECS/linux-lts/0380-UPSTREAM-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch @@ -0,0 +1,242 @@ +From 3cb51db0e02a736385051491bd5cb3dca2a67ec3 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:59 +0200 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add comprehensive SDR tuning + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Implement software tuning algorithm to enable UHS-I SDR modes for SD +card operation and HS200 mode for eMMC. This adds both TX and RX delay +line tuning based on the SpacemiT K1 controller capabilities. + +Algorithm features: +- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) +- Conditional tuning: only for high-speed modes (≥100MHz) +- TX tuning: configure transmit delay line with optimal values + (dline_reg=0, delaycode=127) to ensure optimal signal output timing +- RX tuning: single-pass window detection algorithm testing full + delay range (0-255) to find optimal receive timing window +- Retry mechanism: multiple fallback delays within optimal window + for improved reliability + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit e9cb83c10071808aa7db4582e007a650aa6aa183) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ + 1 file changed, 172 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index d9144537032a..37b0911e7cf2 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -69,6 +69,28 @@ + #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) + #define SDHC_RX_BIAS_CTRL BIT(5) + ++#define SPACEMIT_SDHC_RX_CFG_REG 0x118 ++#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) ++#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) ++#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) ++ ++#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 ++#define SDHC_DLINE_PU BIT(0) ++#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) ++#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) ++ ++#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 ++#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) ++#define SDHC_RX_DLINE_GAIN BIT(8) ++#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) ++ ++#define SPACEMIT_RX_DLINE_REG 9 ++#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 ++#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF ++ ++#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 ++#define SPACEMIT_TX_TUNING_DELAYCODE 127 ++ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; +@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u + sdhci_writel(host, val, reg); + } + ++static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++} ++ ++static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) ++{ ++ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++} ++ ++static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, ++ SPACEMIT_SDHC_RX_CFG_REG); ++ ++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) ++ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); ++} ++ + static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + { + sdhci_reset(host, mask); +@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) + return clk_get_rate(pltfm_host->clk); + } + ++static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ int current_len = 0, current_start = 0; ++ int max_pass_len = 0, max_pass_start = 0; ++ struct mmc_host *mmc = host->mmc; ++ struct mmc_ios ios = mmc->ios; ++ u8 final_delay; ++ int ret = 0; ++ int i; ++ ++ /* ++ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and ++ * if clock frequency is greater than 100MHz in these modes. ++ */ ++ if (host->clock < 100 * 1000 * 1000 || ++ !(ios.timing == MMC_TIMING_MMC_HS200 || ++ ios.timing == MMC_TIMING_UHS_SDR50 || ++ ios.timing == MMC_TIMING_UHS_SDR104)) ++ return 0; ++ ++ if (mmc->caps2 & MMC_CAP2_NO_MMC) { ++ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); ++ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); ++ spacemit_sdhci_tx_tuning_prepare(host); ++ ++ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", ++ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); ++ } ++ ++ spacemit_sdhci_prepare_tuning(host); ++ ++ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { ++ spacemit_sdhci_set_rx_delay(host, i); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ ++ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", ++ i, ret == 0 ? "pass" : "fail"); ++ ++ if (ret == 0) { ++ /* Test passed - extend current window */ ++ if (current_len == 0) ++ current_start = i; ++ current_len++; ++ } else { ++ /* Test failed - check if current window is best so far */ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ current_len = 0; ++ } ++ } ++ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ ++ if (max_pass_len < 3) { ++ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); ++ return -EIO; ++ } ++ ++ final_delay = max_pass_start + max_pass_len / 2; ++ spacemit_sdhci_set_rx_delay(host, final_delay); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (ret) { ++ u8 retry_delays[] = { ++ max_pass_start + max_pass_len / 4, ++ max_pass_start + (3 * max_pass_len) / 4, ++ max_pass_start, ++ max_pass_start + max_pass_len - 1 ++ }; ++ int retry_count = ARRAY_SIZE(retry_delays); ++ ++ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", ++ final_delay); ++ ++ for (i = 0; i < retry_count; i++) { ++ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && ++ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { ++ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (!ret) { ++ final_delay = retry_delays[i]; ++ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", ++ final_delay); ++ break; ++ } ++ } ++ } ++ ++ if (ret) { ++ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); ++ return -EIO; ++ } ++ } ++ ++ dev_dbg(mmc_dev(host->mmc), ++ "Tuning successful: window %d-%d, using delay %d\n", ++ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); ++ ++ return 0; ++} ++ + static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) + { + struct sdhci_host *host = mmc_priv(mmc); +@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { + .set_bus_width = sdhci_set_bus_width, + .set_clock = spacemit_sdhci_set_clock, + .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, ++ .platform_execute_tuning = spacemit_sdhci_execute_tuning, + }; + + static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch deleted file mode 100644 index 16cdfd9cbf..0000000000 --- a/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch +++ /dev/null @@ -1,66 +0,0 @@ -From f92fde63364be52d61f1457466f5b1697b0e9b09 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:07 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes - -Although "D" and "H" are earlier in the alphabet than "P", the DPU and -HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. - -Sort the nodes in this device tree. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-10-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 7cb7d28683bc..4198dbf953f0 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -96,6 +96,20 @@ fan: pwm-fan { - - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &padctrl0_apsys { - fan_pins: fan-0 { - pwm1-pins { -@@ -132,20 +146,6 @@ rx-pins { - }; - }; - --&dpu { -- status = "okay"; --}; -- --&hdmi { -- status = "okay"; --}; -- --&hdmi_out_port { -- hdmi_out_con: endpoint { -- remote-endpoint = <&hdmi_con_in>; -- }; --}; -- - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0381-UPSTREAM-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux-lts/0381-UPSTREAM-riscv-dts-spacemit-k1-add-SD-card-controlle.patch new file mode 100644 index 0000000000..cae679141d --- /dev/null +++ b/SPECS/linux-lts/0381-UPSTREAM-riscv-dts-spacemit-k1-add-SD-card-controlle.patch @@ -0,0 +1,107 @@ +From 50411cf3e9ec53259b4850193c45b0cf08da771d Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:48:59 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1: add SD card + controller and pinctrl support + +Add SD card controller infrastructure for SpacemiT K1 SoC with complete +pinctrl support for both standard and UHS modes. + +- Add sdhci0 controller definition with clocks, resets and interrupts +- Add mmc1_cfg pinctrl for 3.3V standard SD operation +- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation +- Configure appropriate drive strength and power-source properties + +This provides complete SD card infrastructure that K1-based boards can +enable. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Reviewed-by: Troy Mitchell +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 2d77e577109967ef65f269c1fc1d6a659d4260fb) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ + 2 files changed, 53 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index 34d88334e95e..4e9a62d0e85b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -590,4 +590,44 @@ ssp3-0-frm-pins { + power-source = <3300>; + }; + }; ++ ++ mmc1_cfg: mmc1-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ mmc1_uhs_cfg: mmc1-uhs-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index cba160c5edc5..08a0f28d011f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1315,6 +1315,19 @@ usb_dwc3: usb@c0a00000 { + status = "disabled"; + }; + ++ sdhci0: mmc@d4280000 { ++ compatible = "spacemit,k1-sdhci"; ++ reg = <0x0 0xd4280000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH0>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH0>; ++ reset-names = "axi", "sdh"; ++ interrupts = <99>; ++ status = "disabled"; ++ }; ++ + emmc: mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch b/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch deleted file mode 100644 index e70fcfd352..0000000000 --- a/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 235225ebc673fe3cf62d79eb1936fb0ef9b3aa52 Mon Sep 17 00:00:00 2001 -From: Thomas Bonnefille -Date: Thu, 7 May 2026 16:17:08 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes - -Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. - -Signed-off-by: Thomas Bonnefille -Reviewed-by: Drew Fustini -[Icenowy: rebase on top of v7.1-rc2] -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-11-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 60 +++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f1746b5fcd40..e44010810c07 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -460,6 +460,36 @@ uart3: serial@ffe7f04000 { - status = "disabled"; - }; - -+ i2c0: i2c@ffe7f20000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f20000 0x0 0x4000>; -+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@ffe7f24000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f24000 0x0 0x4000>; -+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@ffe7f28000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f28000 0x0 0x4000>; -+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; -@@ -558,6 +588,16 @@ padctrl0_apsys: pinctrl@ffec007000 { - thead,pad-group = <3>; - }; - -+ i2c2: i2c@ffec00c000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xec00c000 0x0 0x4000>; -+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - uart2: serial@ffec010000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; -@@ -569,6 +609,16 @@ uart2: serial@ffec010000 { - status = "disabled"; - }; - -+ i2c3: i2c@ffec014000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xec014000 0x0 0x4000>; -+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C3>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - pwm: pwm@ffec01c000 { - compatible = "thead,th1520-pwm"; - reg = <0xff 0xec01c000 0x0 0x4000>; -@@ -794,6 +844,16 @@ uart5: serial@fff7f0c000 { - status = "disabled"; - }; - -+ i2c5: i2c@fff7f2c000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xf7f2c000 0x0 0x4000>; -+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C5>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0382-UPSTREAM-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux-lts/0382-UPSTREAM-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch new file mode 100644 index 0000000000..8538a0ef57 --- /dev/null +++ b/SPECS/linux-lts/0382-UPSTREAM-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch @@ -0,0 +1,79 @@ +From 0822961c114acb5124ccf9f66e9d9ea96114be1d Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:00 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-orangepi-rv2: add SD + card support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW logic +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Michael Opdenacker +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 2585c60ce2f977b13f14a67d1e3ed9c73fd7f381) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- + 1 file changed, 21 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index c95ca38e3d4a..bd40bc9011e2 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -17,6 +17,8 @@ aliases { + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -202,7 +204,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -319,3 +321,21 @@ hub_3_0: hub@2 { + vdd-supply = <&vcc_5v0>; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch b/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch deleted file mode 100644 index 6905dfac60..0000000000 --- a/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch +++ /dev/null @@ -1,166 +0,0 @@ -From e7621614a1d93b84b3994cc4e147e2f5f24e8b8c Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Thu, 7 May 2026 16:17:09 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO - expansions - -Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the -I2C0/1/3 busses. - -Add device tree nodes for them. - -Signed-off-by: Emil Renner Berthing -[Icenowy: added commit description] -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-12-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 111 ++++++++++++++++++ - 1 file changed, 111 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 4198dbf953f0..354f3893aa8c 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -16,6 +16,9 @@ aliases { - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &aogpio; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; -@@ -110,6 +113,76 @@ hdmi_out_con: endpoint { - }; - }; - -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp1: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "cam0_dvdd12", -+ "cam0_avdd28", -+ "cam0_dovdd18"; -+ }; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp2: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "", -+ "cam0_reset", -+ "cam1_reset", -+ "cam2_reset", -+ "wl_host_wake", -+ "bt_resetn", -+ "", -+ "bt_host_wake"; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp3: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "tp0_rst", -+ "", -+ "", -+ "vcc5v_usb", -+ "vdd28_tp0", -+ "vdd33_lcd0", -+ "vdd18_lcd0", -+ "lcd0_reset"; -+ }; -+}; -+ - &padctrl0_apsys { - fan_pins: fan-0 { - pwm1-pins { -@@ -123,6 +196,18 @@ pwm1-pins { - }; - }; - -+ i2c3_pins: i2c3-0 { -+ i2c-pins { -+ pins = "I2C3_SCL", "I2C3_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ - uart0_pins: uart0-0 { - tx-pins { - pins = "UART0_TXD"; -@@ -146,6 +231,32 @@ rx-pins { - }; - }; - -+&padctrl1_apsys { -+ i2c0_pins: i2c0-0 { -+ i2c-pins { -+ pins = "I2C0_SCL", "I2C0_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-0 { -+ i2c-pins { -+ pins = "I2C1_SCL", "I2C1_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0383-UPSTREAM-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux-lts/0383-UPSTREAM-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch new file mode 100644 index 0000000000..4eed21973c --- /dev/null +++ b/SPECS/linux-lts/0383-UPSTREAM-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch @@ -0,0 +1,90 @@ +From 1ce95de9f1cfb7d46a05fb2252438dd0c5cbab2c Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:01 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-bananapi-f3: add SD + card support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up + support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Suggested-by: Anand Moon +Tested-by: Anand Moon +Tested-by: Margherita Milani +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit c76e2f058cbcab84e4a703f26857a58bdf6a0042) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- + 1 file changed, 22 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index e20daa50a152..72f77e9edd63 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -17,6 +17,8 @@ aliases { + spi3 = &spi3; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -221,7 +223,7 @@ buck3_1v8: buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -242,7 +244,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -374,3 +376,21 @@ hub_3_0: hub@2 { + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch deleted file mode 100644 index f1e49e1290..0000000000 --- a/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch +++ /dev/null @@ -1,306 +0,0 @@ -From 0b1e399727d5ebc0f998864161be37205403f479 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:10 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee - Pi 4A - -The Lichee Pi 4A board features an onboard VIA VL817 hub connected to -the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as -downstream. - -Enable SoC USB3 and the hub on Lichee Pi 4A. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-13-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 231 ++++++++++++++++++ - 2 files changed, 246 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -index 8e76b63e0100..bfda5a6b56b8 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -@@ -20,6 +20,16 @@ memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - }; -+ -+ /* TODO: Switch to AON regulator when it's available. */ -+ avdd33_usb3: regulator-avdd33-usb3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AVDD33_USB3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ /* Marked as always on on the schematics */ -+ regulator-always-on; -+ }; - }; - - &osc { -@@ -202,3 +212,8 @@ &sdio0 { - max-frequency = <198000000>; - status = "okay"; - }; -+ -+&usb_phy { -+ avdd33-usb3-supply = <&avdd33_usb3>; -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 354f3893aa8c..de38f1f457e6 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -4,6 +4,7 @@ - */ - - #include "th1520-lichee-module-4a.dtsi" -+#include - - / { - model = "Sipeed Lichee Pi 4A"; -@@ -97,6 +98,141 @@ fan: pwm-fan { - cooling-levels = <0 66 196 255>; - }; - -+ hub_5v: regulator-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "HUB_5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&ioexp3 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ vcc5v_usb: regulator-vcc5v-usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC5V_USB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ /* -+ * Workaround for Linux currently being not able to power on -+ * Vbus for USB Type-A connectors. -+ */ -+ regulator-always-on; -+ }; -+ -+ connector-usb-a-1 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_1_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port1_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_1_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port1_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-2 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_2_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port2_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_2_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port2_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-3 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_3_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port3_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_3_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port3_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-4 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_4_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port4_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_4_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port4_ep>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&aogpio { -+ /* Route USB2 to the onboard hub for normal operation */ -+ sel-usb-hub-hog { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; - }; - - &dpu { -@@ -262,3 +398,98 @@ &uart0 { - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; -+ -+&usb { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_hs: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <1>; -+ peer-hub = <&hub_ss>; -+ vdd-supply = <&hub_5v>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ -+ hub_hs_port1_ep: endpoint { -+ remote-endpoint = <&usb_a_1_hs_ep>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ hub_hs_port2_ep: endpoint { -+ remote-endpoint = <&usb_a_2_hs_ep>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ -+ hub_hs_port3_ep: endpoint { -+ remote-endpoint = <&usb_a_3_hs_ep>; -+ }; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ -+ hub_hs_port4_ep: endpoint { -+ remote-endpoint = <&usb_a_4_hs_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ hub_ss: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <2>; -+ peer-hub = <&hub_hs>; -+ vdd-supply = <&hub_5v>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ -+ hub_ss_port1_ep: endpoint { -+ remote-endpoint = <&usb_a_1_ss_ep>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ hub_ss_port2_ep: endpoint { -+ remote-endpoint = <&usb_a_2_ss_ep>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ -+ hub_ss_port3_ep: endpoint { -+ remote-endpoint = <&usb_a_3_ss_ep>; -+ }; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ -+ hub_ss_port4_ep: endpoint { -+ remote-endpoint = <&usb_a_4_ss_ep>; -+ }; -+ }; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0384-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux-lts/0384-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch new file mode 100644 index 0000000000..ebd66256d7 --- /dev/null +++ b/SPECS/linux-lts/0384-UPSTREAM-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch @@ -0,0 +1,79 @@ +From 465fb1c6ace1b648650a742ed279f82514c2c7b9 Mon Sep 17 00:00:00 2001 +From: Trevor Gamblin +Date: Wed, 20 May 2026 15:06:23 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1-musepi-pro: add SD + card support with UHS modes + +Update the Muse Pi Pro devicetree with SD card support to match what +was done for the OrangePi RV2 in [1]. More precisely: + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with internal pull-up support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +[1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# + +Tested-by: Andre Heider +Signed-off-by: Trevor Gamblin +Signed-off-by: Iker Pedrosa +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# +Link: https://patch.msgid.link/20260520130624.1763487-1-a.heider@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 85e4c5733cd7efa39f10d7200095c016ce4a2815) +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 22 ++++++++++++++++++- + 1 file changed, 21 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 4aef287353ca..0d809e4ad3b1 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -19,6 +19,8 @@ aliases { + serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -218,7 +220,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -384,3 +386,21 @@ hub_3_0: hub@2 { + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch deleted file mode 100644 index 9a32cb3ce3..0000000000 --- a/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 52e6648f05a98b5daa57d14ffbc7a8f17e0a2e70 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:08 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add PMIC - and power infrastructure - -Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators -for the board's power infrastructure and voltage regulation support. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-2-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 144 ++++++++++++++++++ - 1 file changed, 144 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 29e333b670cf..88c35ad1ef2a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -17,6 +17,7 @@ / { - aliases { - ethernet0 = ð0; - serial0 = &uart0; -+ i2c8 = &i2c8; - }; - - chosen { -@@ -33,6 +34,25 @@ led1 { - default-state = "on"; - }; - }; -+ -+ reg_usb_vbus: regulator-usb-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "USBVBUS"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_vcc_4v0: regulator-vcc-40v { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC4V0"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; - }; - - &emmc { -@@ -72,6 +92,130 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-0 = <&i2c8_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <®_vcc_4v0>; -+ vin2-supply = <®_vcc_4v0>; -+ vin3-supply = <®_vcc_4v0>; -+ vin4-supply = <®_vcc_4v0>; -+ vin5-supply = <®_vcc_4v0>; -+ vin6-supply = <®_vcc_4v0>; -+ aldoin-supply = <®_vcc_4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0385-UPSTREAM-riscv-dts-thead-Add-TH1520-I2C1-controller.patch b/SPECS/linux-lts/0385-UPSTREAM-riscv-dts-thead-Add-TH1520-I2C1-controller.patch new file mode 100644 index 0000000000..603c6fe38b --- /dev/null +++ b/SPECS/linux-lts/0385-UPSTREAM-riscv-dts-thead-Add-TH1520-I2C1-controller.patch @@ -0,0 +1,44 @@ +From 53070d9fa8472939cc7affc019fbd0a753bd55fe Mon Sep 17 00:00:00 2001 +From: MoeLeak +Date: Fri, 8 May 2026 19:44:13 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add TH1520 I2C1 controller + +Describe the TH1520 I2C1 controller so boards can enable devices attached +to that bus. + +The controller is disabled by default because pinmuxing and connected +peripherals are board-specific. + +Signed-off-by: MoeLeak +Signed-off-by: Drew Fustini +(cherry picked from commit 2f60e351633044dee88b63fb1600e284d2476e9c) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 5e91dc1d2b9b..94932c51b7e3 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -411,6 +411,17 @@ uart3: serial@ffe7f04000 { + status = "disabled"; + }; + ++ i2c1: i2c@ffe7f24000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f24000 0x0 0x4000>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ref", "pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch b/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch deleted file mode 100644 index 27c61ac393..0000000000 --- a/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 766c66afb264021498a9385a2332b05c2ab32653 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:09 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add 24c04 - eeprom - -Enable i2c2 and add the connected 24c04 EEPROM. - -It contains an ONIE TLV table: -=> tlv_eeprom -TLV: 0 -[ 12.162] TlvInfo Header: -[ 12.162] Id String: TlvInfo -[ 12.165] Version: 1 -[ 12.168] Total Length: 58 -[ 12.171] TLV Name Code Len Value -[ 12.175] -------------------- ---- --- ----- -[ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro -[ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX -[ 12.189] Unknown 0x41 1 0x02 -[ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX -[ 12.199] MAC Addresses 0x2A 2 2 -[ 12.203] CRC-32 0xFE 4 0x395ECD34 -[ 12.207] Checksum is valid. - -(With 0x41 as TLV_CODE_DDR_CSNUM) - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-3-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- - 1 file changed, 34 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 88c35ad1ef2a..79415d760f16 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -17,6 +17,7 @@ / { - aliases { - ethernet0 = ð0; - serial0 = &uart0; -+ i2c2 = &i2c2; - i2c8 = &i2c8; - }; - -@@ -92,6 +93,38 @@ &pdma { - status = "okay"; - }; - -+&i2c2 { -+ pinctrl-0 = <&i2c2_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ -+ pagesize = <8>; -+ read-only; -+ size = <256>; -+ -+ nvmem-layout { -+ compatible = "onie,tlv-layout"; -+ -+ product-name { -+ }; -+ -+ serial-number { -+ }; -+ -+ mac-address { -+ #nvmem-cell-cells = <1>; -+ }; -+ -+ num-macs { -+ }; -+ }; -+ }; -+}; -+ - &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; -@@ -126,7 +159,7 @@ buck2 { - regulator-always-on; - }; - -- buck3 { -+ buck3_1v8: buck3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <5000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0386-UPSTREAM-riscv-dts-thead-Enable-WiFi-on-Lichee-Pi-4A.patch b/SPECS/linux-lts/0386-UPSTREAM-riscv-dts-thead-Enable-WiFi-on-Lichee-Pi-4A.patch new file mode 100644 index 0000000000..38b2170b73 --- /dev/null +++ b/SPECS/linux-lts/0386-UPSTREAM-riscv-dts-thead-Enable-WiFi-on-Lichee-Pi-4A.patch @@ -0,0 +1,103 @@ +From 5961ecdee2d1f4769af808a73715baaafdd5d854 Mon Sep 17 00:00:00 2001 +From: MoeLeak +Date: Fri, 8 May 2026 19:44:14 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Enable WiFi on Lichee Pi 4A + +The Lichee Pi 4A has an RTL8723DS WiFi module connected to the TH1520 +SDIO1 controller. The module reset line is driven through a PCA9557 GPIO +expander on the I2C1 bus. + +Enable I2C1 for the GPIO expander and configure SDIO1 as a non-removable +4-bit SDIO bus using an mmc-pwrseq-simple reset sequence so the WiFi +device can be powered and enumerated. + +Signed-off-by: MoeLeak +Signed-off-by: Drew Fustini +(cherry picked from commit a20241c08385c875c4d0deb6c8ffc15f13f5b388) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 47 +++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 7cb7d28683bc..af6f25ebbf60 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -4,6 +4,7 @@ + */ + + #include "th1520-lichee-module-4a.dtsi" ++#include + + / { + model = "Sipeed Lichee Pi 4A"; +@@ -40,6 +41,12 @@ hdmi_con_in: endpoint { + }; + }; + ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&ioexp2 4 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <200>; ++ }; ++ + thermal-zones { + cpu-thermal { + polling-delay = <1000>; +@@ -96,6 +103,20 @@ fan: pwm-fan { + + }; + ++&padctrl1_apsys { ++ i2c1_pins: i2c1-0 { ++ i2c-pins { ++ pins = "I2C1_SCL", "I2C1_SDA"; ++ function = "i2c"; ++ bias-pull-up = <2100>; ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -132,6 +153,32 @@ rx-pins { + }; + }; + ++&i2c1 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ ++ ioexp2: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++}; ++ ++&sdio1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus-width = <4>; ++ max-frequency = <198000000>; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ non-removable; ++ status = "okay"; ++}; ++ + &dpu { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch deleted file mode 100644 index bb1a850bdd..0000000000 --- a/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch +++ /dev/null @@ -1,82 +0,0 @@ -From c117a7fcd7c10d4f8235ca033fe3b09674838cc2 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:10 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - QSPI and add SPI NOR - -Add the QSPI controller node and describe the attached SPI NOR flash -(Winbond W25Q64FWSSAQ). - -Add a corresponding vendor flash partition layout. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-4-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 43 ++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 79415d760f16..7ebace0e46ed 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -166,7 +166,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4_3v3: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -249,6 +249,47 @@ dldo7 { - }; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x10000>; -+ }; -+ private@10000 { -+ reg = <0x10000 0x10000>; -+ }; -+ fsbl@20000 { -+ reg = <0x20000 0x40000>; -+ }; -+ env@60000 { -+ reg = <0x60000 0x10000>; -+ }; -+ opensbi@70000 { -+ reg = <0x70000 0x30000>; -+ }; -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0387-UPSTREAM-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux-lts/0387-UPSTREAM-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch new file mode 100644 index 0000000000..ebb958dcff --- /dev/null +++ b/SPECS/linux-lts/0387-UPSTREAM-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch @@ -0,0 +1,97 @@ +From 9ac45a8228e9832ca354e2ab4a6dbdc805d6f151 Mon Sep 17 00:00:00 2001 +From: Thomas Gerner +Date: Thu, 14 May 2026 20:32:01 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Enable wifi on the + BeagleV-Ahead + +The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology +Inc. connected to SDIO1. The chip is compatible to the broadcom wireless +driver. + +The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and +Bluetooth 5.4 module. Bluetooth is not enabled by this patch. + +Signed-off-by: Thomas Gerner +Signed-off-by: Drew Fustini +(cherry picked from commit 3a5791956edbfa84d7256224167941931cbc46e7) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +index 91f3f9b987bc..e16484a47653 100644 +--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts ++++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +@@ -86,6 +86,11 @@ hdmi_con_in: endpoint { + }; + }; + }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ ++ }; + }; + + &osc { +@@ -239,6 +244,28 @@ rx-pins { + slew-rate = <0>; + }; + }; ++ ++ wifi_pins: wifi-0 { ++ host-wake-pins { ++ pins = "GPIO2_25"; ++ function = "gpio"; ++ bias-disable; ++ drive-strength = <1>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ reg-on-pins { ++ pins = "GPIO2_31"; ++ function = "gpio"; ++ bias-disable; ++ drive-strength = <3>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; + }; + + &sdio0 { +@@ -247,6 +274,27 @@ &sdio0 { + status = "okay"; + }; + ++&sdio1 { ++ bus-width = <4>; ++ max-frequency = <198000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ non-removable; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ status = "okay"; ++ ++ wifi@1 { ++ compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <25 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ + &dpu { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch deleted file mode 100644 index e2dbb68dfc..0000000000 --- a/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch +++ /dev/null @@ -1,97 +0,0 @@ -From a94156daa45213f4dfc1d6f6cc6a3f25b4e635c1 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:11 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - USB 3 ports - -Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) -and usbphy2 (USB 2 PHY) on the MusePi Pro board. - -The board uses a VLI VL817 hub, providing four ports. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-5-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 54 +++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 7ebace0e46ed..9c90c2817ecb 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -54,6 +54,28 @@ reg_vcc_4v0: regulator-vcc-40v { - regulator-always-on; - vin-supply = <®_usb_vbus>; - }; -+ -+ reg_5v_vbus: regulator-5v-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "5V_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ -+ enable-active-high; -+ }; -+ -+ reg_vcc5v_hub: regulator-vcc5v-hub { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC5V0_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ -+ enable-active-high; -+ }; - }; - - &emmc { -@@ -66,6 +88,10 @@ &emmc { - status = "okay"; - }; - -+&combo_phy { -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; -@@ -295,3 +321,31 @@ &uart0 { - pinctrl-names = "default"; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vbus-supply = <®_5v_vbus>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <®_vcc5v_hub>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <®_vcc5v_hub>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0388-UPSTREAM-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux-lts/0388-UPSTREAM-riscv-module-Use-generic-cmp_int-instead-of.patch new file mode 100644 index 0000000000..454b1a615f --- /dev/null +++ b/SPECS/linux-lts/0388-UPSTREAM-riscv-module-Use-generic-cmp_int-instead-of.patch @@ -0,0 +1,49 @@ +From baa25175c1992324a927b6aaecffa5bc1aa01a37 Mon Sep 17 00:00:00 2001 +From: Florian Schmaus +Date: Sat, 6 Jun 2026 20:17:53 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: module: Use generic cmp_int() instead + of custom cmp_3way() + +The module-sections.c file defines a custom cmp_3way() macro to perform +3-way comparisons during relocation sorting. + +Instead of maintaining our own implementation, use the generic +cmp_int() macro provided by the already included . This +removes redundant code and relies on standard kernel interfaces. + +Signed-off-by: Florian Schmaus +Link: https://patch.msgid.link/20260512063231.708256-1-florian.schmaus@codasip.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 3e17a4b443bbaecc723a2d51faeaa1a0097e43e9) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/module-sections.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module-sections.c +index 1675cbad8619..33750a51f157 100644 +--- a/arch/riscv/kernel/module-sections.c ++++ b/arch/riscv/kernel/module-sections.c +@@ -56,17 +56,15 @@ unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) + return (unsigned long)&plt[i]; + } + +-#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) +- + static int cmp_rela(const void *a, const void *b) + { + const Elf_Rela *x = a, *y = b; + int i; + + /* sort by type, symbol index and addend */ +- i = cmp_3way(x->r_info, y->r_info); ++ i = cmp_int(x->r_info, y->r_info); + if (i == 0) +- i = cmp_3way(x->r_addend, y->r_addend); ++ i = cmp_int(x->r_addend, y->r_addend); + return i; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch deleted file mode 100644 index 23832d06b8..0000000000 --- a/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 349e55f2df85d45315a64261930482121af299e5 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:12 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - PCIe ports - -Enable the two PCIe controller along with and their associated PHYs. They -are routed to the M.2 M-key connector and to the PCIe slot. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-6-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ - 1 file changed, 50 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 9c90c2817ecb..2d3e30f0bd80 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -36,6 +36,24 @@ led1 { - }; - }; - -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "PCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; -+ -+ mpcie_vcc_3v3: regulator-mpcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "MPCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; -+ - reg_usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "USBVBUS"; -@@ -275,6 +293,38 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&mpcie_vcc_3v3>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&mpcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0389-UPSTREAM-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux-lts/0389-UPSTREAM-riscv-propagate-insert_resource-result-from.patch new file mode 100644 index 0000000000..468b5bf2f3 --- /dev/null +++ b/SPECS/linux-lts/0389-UPSTREAM-riscv-propagate-insert_resource-result-from.patch @@ -0,0 +1,50 @@ +From a5535ff7504eb1609517707e87e8036a64835533 Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Sat, 6 Jun 2026 20:17:52 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: propagate insert_resource result from + add_resource + +Currently, add_resource() returns 1 on success, even though its callers +only check for negative values. Instead, propagate the insert_resource() +result from add_resource() to align with standard kernel return-value +conventions (0 on success, negative errno on failure). + +Use %pR to print the full resource range while at it. + +Signed-off-by: Thorsten Blum +Link: https://patch.msgid.link/20260512172034.328405-4-thorsten.blum@linux.dev +Signed-off-by: Paul Walmsley +(cherry picked from commit 13fe217f64a7ee71aa58d871c6021a721a5a0c6f) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/setup.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c +index b5bc5fc65cea..13b27a078912 100644 +--- a/arch/riscv/kernel/setup.c ++++ b/arch/riscv/kernel/setup.c +@@ -75,16 +75,13 @@ static struct resource *standard_resources; + static int __init add_resource(struct resource *parent, + struct resource *res) + { +- int ret = 0; ++ int ret; + + ret = insert_resource(parent, res); +- if (ret < 0) { +- pr_err("Failed to add a %s resource at %llx\n", +- res->name, (unsigned long long) res->start); +- return ret; +- } ++ if (ret < 0) ++ pr_err("Failed to add resource %s %pR\n", res->name, res); + +- return 1; ++ return ret; + } + + static int __init add_kernel_resources(void) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch deleted file mode 100644 index 2a721e03c5..0000000000 --- a/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9a43c78660975e06c30cbaf943e981dd50feee99 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:13 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set - default console baud rate - -Allow serial output with the same uboot/opensbi settings so the -console works without providing a cmdline. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-7-a.heider@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 2d3e30f0bd80..c8bf776511c9 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -22,7 +22,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - leds { --- -2.53.0 - diff --git a/SPECS/linux-lts/0390-UPSTREAM-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux-lts/0390-UPSTREAM-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch new file mode 100644 index 0000000000..82871b55b8 --- /dev/null +++ b/SPECS/linux-lts/0390-UPSTREAM-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch @@ -0,0 +1,78 @@ +From 61eba02b59eba26f274780eb63e84e3b66145380 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 16 May 2026 16:00:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI for OrangePi + RV2 + +Enable the QSPI controller and the XM25QU128C SPI NOR flash on the +OrangePi RV2 board. Add a flash partition layout from vendor UBoot. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260516080030.1736836-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit e2518e8cb1dde64af2d1bb246639bb7ef7523f7a) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index bd40bc9011e2..7c49bce427f3 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -290,6 +290,51 @@ &pcie2 { + status = "okay"; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&buck3_1v8>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x00000 0x010000>; ++ }; ++ ++ private@10000 { ++ reg = <0x10000 0x010000>; ++ }; ++ ++ fsbl@20000 { ++ reg = <0x20000 0x040000>; ++ }; ++ ++ env@60000 { ++ reg = <0x60000 0x010000>; ++ }; ++ ++ opensbi@70000 { ++ reg = <0x70000 0x030000>; ++ }; ++ ++ uboot@a0000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch deleted file mode 100644 index e480697ecf..0000000000 --- a/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch +++ /dev/null @@ -1,851 +0,0 @@ -From 19e0459a70fb9e1c62f2eb097e72e73136997ccd Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 21 May 2026 00:24:41 +0000 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add pwm support - -Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents -the pinctrl info which would easily help to enable them in future. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ - 2 files changed, 810 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 23899d3f308a..252c64af76fe 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -56,6 +56,596 @@ i2c8-pins { - }; - }; - -+ /omit-if-no-ref/ -+ pwm0_0_cfg: pwm0-0-cfg { -+ pwm0-0-pins { -+ pinmux = ; /* pwm0 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm0_1_cfg: pwm0-1-cfg { -+ pwm0-1-pins { -+ pinmux = ; /* pwm0 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_0_cfg: pwm1-0-cfg { -+ pwm1-0-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_1_cfg: pwm1-1-cfg { -+ pwm1-1-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_2_cfg: pwm1-2-cfg { -+ pwm1-2-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_0_cfg: pwm2-0-cfg { -+ pwm2-0-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_1_cfg: pwm2-1-cfg { -+ pwm2-1-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_2_cfg: pwm2-2-cfg { -+ pwm2-2-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_3_cfg: pwm2-3-cfg { -+ pwm2-3-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_0_cfg: pwm3-0-cfg { -+ pwm3-0-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_1_cfg: pwm3-1-cfg { -+ pwm3-1-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_2_cfg: pwm3-2-cfg { -+ pwm3-2-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_3_cfg: pwm3-3-cfg { -+ pwm3-3-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_0_cfg: pwm4-0-cfg { -+ pwm4-0-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_1_cfg: pwm4-1-cfg { -+ pwm4-1-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_2_cfg: pwm4-2-cfg { -+ pwm4-2-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_0_cfg: pwm5-0-cfg { -+ pwm5-0-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_1_cfg: pwm5-1-cfg { -+ pwm5-1-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_2_cfg: pwm5-2-cfg { -+ pwm5-2-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_0_cfg: pwm6-0-cfg { -+ pwm6-0-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_1_cfg: pwm6-1-cfg { -+ pwm6-1-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_2_cfg: pwm6-2-cfg { -+ pwm6-2-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_0_cfg: pwm7-0-cfg { -+ pwm7-0-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_1_cfg: pwm7-1-cfg { -+ pwm7-1-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_2_cfg: pwm7-2-cfg { -+ pwm7-2-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_0_cfg: pwm8-0-cfg { -+ pwm8-0-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_1_cfg: pwm8-1-cfg { -+ pwm8-1-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_2_cfg: pwm8-2-cfg { -+ pwm8-2-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_0_cfg: pwm9-0-cfg { -+ pwm9-0-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_1_cfg: pwm9-1-cfg { -+ pwm9-1-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_2_cfg: pwm9-2-cfg { -+ pwm9-2-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_0_cfg: pwm10-0-cfg { -+ pwm10-0-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_1_cfg: pwm10-1-cfg { -+ pwm10-1-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_2_cfg: pwm10-2-cfg { -+ pwm10-2-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11_0_cfg: pwm11-0-cfg { -+ pwm11-0-pins { -+ pinmux = ; /* pwm11 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11_1_cfg: pwm11-1-cfg { -+ pwm11-1-pins { -+ pinmux = ; /* pwm11 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12_0_cfg: pwm12-0-cfg { -+ pwm12-0-pins { -+ pinmux = ; /* pwm12 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12_1_cfg: pwm12-1-cfg { -+ pwm12-1-pins { -+ pinmux = ; /* pwm12 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_0_cfg: pwm13-0-cfg { -+ pwm13-0-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_1_cfg: pwm13-1-cfg { -+ pwm13-1-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_2_cfg: pwm13-2-cfg { -+ pwm13-2-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_0_cfg: pwm14-0-cfg { -+ pwm14-0-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_1_cfg: pwm14-1-cfg { -+ pwm14-1-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_2_cfg: pwm14-2-cfg { -+ pwm14-2-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_0_cfg: pwm15-0-cfg { -+ pwm15-0-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_1_cfg: pwm15-1-cfg { -+ pwm15-1-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_2_cfg: pwm15-2-cfg { -+ pwm15-2-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_0_cfg: pwm16-0-cfg { -+ pwm16-0-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_1_cfg: pwm16-1-cfg { -+ pwm16-1-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_2_cfg: pwm16-2-cfg { -+ pwm16-2-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_0_cfg: pwm17-0-cfg { -+ pwm17-0-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_1_cfg: pwm17-1-cfg { -+ pwm17-1-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_2_cfg: pwm17-2-cfg { -+ pwm17-2-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_0_cfg: pwm18-0-cfg { -+ pwm18-0-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_1_cfg: pwm18-1-cfg { -+ pwm18-1-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_2_cfg: pwm18-2-cfg { -+ pwm18-2-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_0_cfg: pwm19-0-cfg { -+ pwm19-0-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_1_cfg: pwm19-1-cfg { -+ pwm19-1-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_2_cfg: pwm19-2-cfg { -+ pwm19-2-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 0408929f7949..a336de5f3d94 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -809,6 +809,226 @@ i2c8: i2c@d401d800 { - status = "disabled"; - }; - -+ pwm0: pwm@d401a000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM0>, -+ <&syscon_apbc CLK_APBC_PWM0_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM0>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@d401a400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM1>, -+ <&syscon_apbc CLK_APBC_PWM1_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM1>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@d401a800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM2>, -+ <&syscon_apbc CLK_APBC_PWM2_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM2>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@d401ac00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401ac00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM3>, -+ <&syscon_apbc CLK_APBC_PWM3_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM3>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@d401b000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM4>, -+ <&syscon_apbc CLK_APBC_PWM4_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM4>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm5: pwm@d401b400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM5>, -+ <&syscon_apbc CLK_APBC_PWM5_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM5>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm6: pwm@d401b800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM6>, -+ <&syscon_apbc CLK_APBC_PWM6_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM6>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm7: pwm@d401bc00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401bc00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM7>, -+ <&syscon_apbc CLK_APBC_PWM7_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM7>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm8: pwm@d4020000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM8>, -+ <&syscon_apbc CLK_APBC_PWM8_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM8>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm9: pwm@d4020400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM9>, -+ <&syscon_apbc CLK_APBC_PWM9_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM9>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm10: pwm@d4020800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM10>, -+ <&syscon_apbc CLK_APBC_PWM10_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM10>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm11: pwm@d4020c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM11>, -+ <&syscon_apbc CLK_APBC_PWM11_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM11>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm12: pwm@d4021000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM12>, -+ <&syscon_apbc CLK_APBC_PWM12_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM12>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm13: pwm@d4021400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM13>, -+ <&syscon_apbc CLK_APBC_PWM13_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM13>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm14: pwm@d4021800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM14>, -+ <&syscon_apbc CLK_APBC_PWM14_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM14>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm15: pwm@d4021c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM15>, -+ <&syscon_apbc CLK_APBC_PWM15_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM15>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm16: pwm@d4022000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM16>, -+ <&syscon_apbc CLK_APBC_PWM16_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM16>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm17: pwm@d4022400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM17>, -+ <&syscon_apbc CLK_APBC_PWM17_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM17>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm18: pwm@d4022800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM18>, -+ <&syscon_apbc CLK_APBC_PWM18_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM18>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm19: pwm@d4022c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM19>, -+ <&syscon_apbc CLK_APBC_PWM19_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM19>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0391-UPSTREAM-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux-lts/0391-UPSTREAM-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch new file mode 100644 index 0000000000..09077f3893 --- /dev/null +++ b/SPECS/linux-lts/0391-UPSTREAM-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch @@ -0,0 +1,38 @@ +From 480eafda6c00000e59013a52c8ac92b0a0340d2d Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 20:58:16 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Fix I/O power + settings + +SpacemiT K3 SoC support dual-voltage I/O power domain, while initially +configure to 3.3v, and need to access register from APBC space to switch +to 1.8v domain. + +Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken +ethernet driver. + +Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") +Reported-by: Han Gao +Link: https://patch.msgid.link/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3ea695eb111fc5a7ffddd21d5c3fee6d82560413) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 97cc9e2dd554..7e3cdd42ab8e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1034,6 +1034,7 @@ pinctrl: pinctrl@d401e000 { + clocks = <&syscon_apbc CLK_APBC_AIB>, + <&syscon_apbc CLK_APBC_AIB_BUS>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + }; + + uart10: serial@d401f000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch deleted file mode 100644 index dfea8b63a1..0000000000 --- a/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 990e07e7b25d9ad6863585a17875fd32e9b194ed Mon Sep 17 00:00:00 2001 -From: Thorsten Blum -Date: Sun, 10 May 2026 18:54:21 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: use sysfs_emit in cpu_show_ghostwrite - -Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is -preferred for formatting sysfs output because it provides safer bounds -checking. - -While the current code only emits fixed strings that fit easily within -PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. - -Signed-off-by: Thorsten Blum -Link: https://lore.kernel.org/r/20260510165420.109453-3-thorsten.blum@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/bugs.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c -index 3655fe7d678c..e5758e3f1c7e 100644 ---- a/arch/riscv/kernel/bugs.c -+++ b/arch/riscv/kernel/bugs.c -@@ -5,7 +5,7 @@ - - #include - #include --#include -+#include - - #include - #include -@@ -46,15 +46,15 @@ ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *attr, c - if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { - switch (ghostwrite_state) { - case UNAFFECTED: -- return sprintf(buf, "Not affected\n"); -+ return sysfs_emit(buf, "Not affected\n"); - case MITIGATED: -- return sprintf(buf, "Mitigation: xtheadvector disabled\n"); -+ return sysfs_emit(buf, "Mitigation: xtheadvector disabled\n"); - case VULNERABLE: - fallthrough; - default: -- return sprintf(buf, "Vulnerable\n"); -+ return sysfs_emit(buf, "Vulnerable\n"); - } -- } else { -- return sprintf(buf, "Not affected\n"); - } -+ -+ return sysfs_emit(buf, "Not affected\n"); - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0392-UPSTREAM-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0392-UPSTREAM-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..d0a0a0e895 --- /dev/null +++ b/SPECS/linux-lts/0392-UPSTREAM-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,38 @@ +From 4d7d02c5011f52e058f5468879b54e8994f61173 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:35 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: set console baud rate on + Milk-V Jupiter + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") +Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-2-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 4f97acb4f744f516bbe976da8282c0fe213216ff) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index afaad59e6bce..db98dbfadf00 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -20,7 +20,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch deleted file mode 100644 index 61c699fb6b..0000000000 --- a/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 5feeaceeac1d83b0bc4b52a476972edb0633b9b1 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:09 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as parent - for PCIe clock - -According to SpacemiT updated docs, the PCIe master and slave clock's -parent is the pll2_d6 clock, so fix it. - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index bb8b75bdbdb3..1a53b14739fe 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents[] = { - }; - CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); - --CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); --CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); --CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); --CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); --CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); --CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); --CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); --CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); --CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); --CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); -+CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); -+CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); -+CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); -+CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); -+CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); - - static const struct clk_parent_data emac_1588_parents[] = { - CCU_PARENT_NAME(vctcxo_24m), --- -2.53.0 - diff --git a/SPECS/linux-lts/0393-UPSTREAM-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux-lts/0393-UPSTREAM-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch new file mode 100644 index 0000000000..fe18fb722e --- /dev/null +++ b/SPECS/linux-lts/0393-UPSTREAM-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch @@ -0,0 +1,36 @@ +From 76ae3c142243ad74a38a0048541e4e56bcb2be29 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:36 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: sort aliases on Milk-V + Jupiter + +Before adding more aliases, just sort them. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-3-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 9cdeba29d65b10e7bdb1491167141ff2df238ab8) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index db98dbfadf00..fbba33992347 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -14,9 +14,9 @@ / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; +- serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ serial0 = &uart0; + }; + + chosen { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch deleted file mode 100644 index cec142274b..0000000000 --- a/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch +++ /dev/null @@ -1,35 +0,0 @@ -From e7889702a01dfeefc13f75527701150067033d27 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:10 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Fix PCIe clock register - offset - -The offset of PCIe Clock CTRL register for port B and C controller was -wrongly swapped, correct it here. - -Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - include/soc/spacemit/k3-syscon.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h -index 0299bea065a0..a68255dd641f 100644 ---- a/include/soc/spacemit/k3-syscon.h -+++ b/include/soc/spacemit/k3-syscon.h -@@ -168,8 +168,8 @@ - #define APMU_CPU_C2_CLK_CTRL 0x394 - #define APMU_CPU_C3_CLK_CTRL 0x208 - #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 --#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 --#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 - #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 - #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 - #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 --- -2.53.0 - diff --git a/SPECS/linux-lts/0394-UPSTREAM-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux-lts/0394-UPSTREAM-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch new file mode 100644 index 0000000000..d2b113a2d9 --- /dev/null +++ b/SPECS/linux-lts/0394-UPSTREAM-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch @@ -0,0 +1,59 @@ +From 1de348d68788e830d0de3ba1151f1f90cfe31c17 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:37 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable eMMC on Milk-V + Jupiter + +The Milk-V Jupiter board has a connector for an eMMC module. Add an +entry for it in the device tree and alias it mmc0. + +Mark the device as non-removable as eMMC modules have no CD pin and are +not supposed to be inserted or removed while the system is running. On +systems without an eMMC module installed, the kernel emits the following +informational message during boot: + +mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA +mmc0: Failed to initialize a non-removable card + +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-4-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 4bc9f44d581be66718cf7cf6e649fb92b3c2e6c6) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index fbba33992347..1a833e716cb6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -16,6 +16,7 @@ aliases { + ethernet1 = ð1; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; + serial0 = &uart0; + }; + +@@ -105,6 +106,16 @@ &combo_phy { + status = "okay"; + }; + ++&emmc { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch deleted file mode 100644 index 8c7de819c6..0000000000 --- a/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 81e7dee63c57fbbbf525e3b3e475ac4463f4be56 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:11 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe DBI - clock IDs - -Add clock IDs of PCIe DBI (Data Bus Interface) clock. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h -index b22336f3ae40..dfae52547cda 100644 ---- a/include/dt-bindings/clock/spacemit,k3-clocks.h -+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h -@@ -380,6 +380,11 @@ - #define CLK_APMU_ISIM_VCLK1 86 - #define CLK_APMU_ISIM_VCLK2 87 - #define CLK_APMU_ISIM_VCLK3 88 -+#define CLK_APMU_PCIE_PORTA_DBI 89 -+#define CLK_APMU_PCIE_PORTB_DBI 90 -+#define CLK_APMU_PCIE_PORTC_DBI 91 -+#define CLK_APMU_PCIE_PORTD_DBI 92 -+#define CLK_APMU_PCIE_PORTE_DBI 93 - - /* DCIU clocks */ - #define CLK_DCIU_HDMA 0 --- -2.53.0 - diff --git a/SPECS/linux-lts/0395-UPSTREAM-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux-lts/0395-UPSTREAM-riscv-dts-spacemit-enable-SD-card-support-o.patch new file mode 100644 index 0000000000..8ec4e6bda9 --- /dev/null +++ b/SPECS/linux-lts/0395-UPSTREAM-riscv-dts-spacemit-enable-SD-card-support-o.patch @@ -0,0 +1,75 @@ +From ce615bc00efde31f8b47b06b7273fc6d405e2c74 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:38 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable SD card support + on Milk-V Jupiter + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with pull-up +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Alias it as mmc1 + +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-5-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 60b5e027c8c8cab69ad9cc7cab71ee795963e7b1) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 1a833e716cb6..beebf804197e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -17,6 +17,7 @@ aliases { + i2c2 = &i2c2; + i2c8 = &i2c8; + mmc0 = &emmc; ++ mmc1 = &sdhci0; + serial0 = &uart0; + }; + +@@ -250,7 +251,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -385,6 +386,24 @@ uboot@a00000 { + }; + }; + ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch deleted file mode 100644 index b1757a1b9e..0000000000 --- a/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 2e07351b454e444fdff46836d26d0ca8f0f1d241 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:12 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock - -Add PCIe DBI (Data Bus Interface) clock which was missing, This will -support PCIe driver to explicitly request and enable all clocks that -needed. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 1a53b14739fe..cb0c4277f72a 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT - - CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); - CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0); - CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); - CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0); - CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); - CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0); - CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); - CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0); - CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); - CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0); - - static const struct clk_parent_data emac_1588_parents[] = { - CCU_PARENT_NAME(vctcxo_24m), -@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { - [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, - [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw, - [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, - [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, - [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, --- -2.53.0 - diff --git a/SPECS/linux-lts/0396-UPSTREAM-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux-lts/0396-UPSTREAM-riscv-dts-spacemit-fix-uboot-partition-offs.patch new file mode 100644 index 0000000000..911b308320 --- /dev/null +++ b/SPECS/linux-lts/0396-UPSTREAM-riscv-dts-spacemit-fix-uboot-partition-offs.patch @@ -0,0 +1,35 @@ +From 7fde181808d2a610e81bd057e2cac6f82768e559 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:39 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: fix uboot partition + offset on Milk-V Jupiter + +Correct the uboot partition node name to match its actual offset. + +Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260519041458.3287843-6-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 6edd9a0d32e1ef81133b8cb5b3bb3157a44da4d1) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index beebf804197e..2fc8d6533786 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -379,7 +379,7 @@ env@60000 { + opensbi@70000 { + reg = <0x70000 0x30000>; + }; +- uboot@a00000 { ++ uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch deleted file mode 100644 index 3c8f831c46..0000000000 --- a/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 1e42639469619e69ed0fe533281513ebbf8fb45f Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 9 May 2026 18:00:00 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC for OrangePi - RV2 - -The OrangePi RV2 board has one eMMC slot, so enable eMMC. -Tested using a 16 GiB AJTD4R eMMC module. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260509100000.3315109-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 3a829e3c9cbc..c95ca38e3d4a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -78,6 +78,16 @@ &combo_phy { - status = "okay"; - }; - -+&emmc { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0397-UPSTREAM-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux-lts/0397-UPSTREAM-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch new file mode 100644 index 0000000000..dccdeeade1 --- /dev/null +++ b/SPECS/linux-lts/0397-UPSTREAM-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch @@ -0,0 +1,53 @@ +From 0306f8c5802acf2fda8055b82fccbbb1396754cd Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 00:40:07 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: fix NULL check in + spacemit_pin_set_config + +spacemit_pin_set_config() looks up the per-pin descriptor with +spacemit_get_pin() then checks the wrong variable for failure: + + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + ... + if (!pin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); + +pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a +valid pin, so rejecting it here drops the PAD config write for the first +pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as +its first entry, so its drive-strength / bias configuration was silently +ignored. + +The intended guard is against spacemit_get_pin() returning NULL when the +pin id isn't in the SoC's pin table. Check spin instead, which both +restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. + +Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") +Signed-off-by: Han Gao +Reviewed-by: Troy Mitchell +Reviewed-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 09c816e5c4d3a8d6d6e4b7537433e5e98505d934) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index f3c754f78074..f71091254382 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -795,7 +795,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, + void __iomem *reg; + unsigned int mux; + +- if (!pin) ++ if (!spin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch deleted file mode 100644 index f786ba93a4..0000000000 --- a/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch +++ /dev/null @@ -1,318 +0,0 @@ -From 952ad4c278b4a099d4fbcabc3b23304339f3277a Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 8 May 2026 15:25:24 +0800 -Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for - accurate SCL frequency - -The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for -master mode operations is determined by the ILCR (I2C Load Count Register). -Previously, the driver relied on the hardware's reset default -values for this register. - -The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL -frequencies lower than intended. For example, with the default -31.5 MHz input clock, these default settings result in an SCL -frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, -and approximately 338 kHz (fast mode) when targeting 400 kHz. -These frequencies are below the 100 kHz/400 kHz nominal speeds. - -This patch integrates the SCL frequency management into -the Common Clock Framework (CCF). Specifically, the ILCR register, -which acts as a frequency divider for the SCL clock, is now registered -as a managed clock (scl_clk) within the CCF. - -The actual hardware timing formulas are: -- standard mode: SCL = FCLK / (2 * SLV + 8) -- fast mode: SCL = FCLK / (2 * FLV + 10) - -These formulas are only valid when the IWCR (Wait Count Register) is -programmed to 0x142A, a value specified by the I2C IP designer. The -driver now initializes IWCR to this value during controller init. - -Reviewed-by: Yixun Lan -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/i2c/busses/Kconfig | 2 +- - drivers/i2c/busses/i2c-k1.c | 174 ++++++++++++++++++++++++++++++++++-- - 2 files changed, 167 insertions(+), 9 deletions(-) - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 4515ded4338c..e53b9487341d 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -798,7 +798,7 @@ config I2C_JZ4780 - config I2C_K1 - tristate "SpacemiT K1 I2C adapter" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on OF -+ depends on OF && COMMON_CLK - help - This option enables support for the I2C interface on the SpacemiT K1 - platform. -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 9152cf436bea..c6fe2052e479 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -4,7 +4,9 @@ - */ - - #include -+#include - #include -+#include - #include - #include - #include -@@ -17,6 +19,8 @@ - #define SPACEMIT_ISR 0x4 /* Status register */ - #define SPACEMIT_IDBR 0xc /* Data buffer register */ - #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ -+#define SPACEMIT_ILCR 0x10 /* Load Count Register */ -+#define SPACEMIT_IWCR 0x14 /* Wait Count Register */ - #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ - - /* SPACEMIT_ICR register fields */ -@@ -88,6 +92,19 @@ - #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ - #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ - -+#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0) -+#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9) -+ -+/* SPACEMIT_IWCR register fields */ -+#define SPACEMIT_WCR_COUNT GENMASK(4, 0) -+#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5) -+#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10) -+ -+/* Required by I2C IP for correct SCL timing */ -+#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \ -+ FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \ -+ FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5)) -+ - /* i2c bus recover timeout: us */ - #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 - -@@ -109,11 +126,20 @@ enum spacemit_i2c_state { - SPACEMIT_STATE_WRITE, - }; - -+enum spacemit_i2c_mode { -+ SPACEMIT_MODE_STANDARD, -+ SPACEMIT_MODE_FAST -+}; -+ - /* i2c-spacemit driver's main struct */ - struct spacemit_i2c_dev { - struct device *dev; - struct i2c_adapter adapt; - -+ struct clk_hw scl_clk_hw; -+ struct clk *scl_clk; -+ enum spacemit_i2c_mode mode; -+ - /* hardware resources */ - void __iomem *base; - int irq; -@@ -135,6 +161,85 @@ struct spacemit_i2c_dev { - u32 status; - }; - -+static void spacemit_i2c_scl_clk_disable_unprepare(void *data) -+{ -+ clk_disable_unprepare(data); -+} -+ -+/* -+ * Calculate the ILCR divider value (lv) from the target SCL rate. -+ * -+ * Hardware timing formulas: -+ * - standard mode: SCL = FCLK / (2 * SLV + 8) -+ * - fast mode: SCL = FCLK / (2 * FLV + 10) -+ */ -+static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c, -+ unsigned long parent_rate, -+ unsigned long target_rate) -+{ -+ u32 offset, denom; -+ -+ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; -+ denom = DIV_ROUND_CLOSEST(parent_rate, target_rate); -+ -+ return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2); -+} -+ -+static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lv, lcr, mask; -+ -+ lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate); -+ -+ mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ? -+ SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK; -+ -+ lcr = readl(i2c->base + SPACEMIT_ILCR); -+ lcr &= ~mask; -+ lcr |= field_prep(mask, lv); -+ writel(lcr, i2c->base + SPACEMIT_ILCR); -+ -+ return 0; -+} -+ -+static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lv, offset; -+ -+ lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate); -+ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; -+ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset); -+ -+ return 0; -+} -+ -+static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lcr, lv = 0; -+ -+ lcr = readl(i2c->base + SPACEMIT_ILCR); -+ -+ if (i2c->mode == SPACEMIT_MODE_STANDARD) { -+ lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr); -+ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8); -+ } -+ -+ lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr); -+ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10); -+} -+ -+static const struct clk_ops spacemit_i2c_clk_ops = { -+ .set_rate = spacemit_i2c_clk_set_rate, -+ .determine_rate = spacemit_i2c_clk_determine_rate, -+ .recalc_rate = spacemit_i2c_clk_recalc_rate, -+}; -+ - static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) - { - u32 val; -@@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_ICR); - } - -+static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c) -+{ -+ struct clk_init_data init = {}; -+ char name[64]; -+ int ret; -+ -+ ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev)); -+ if (ret >= ARRAY_SIZE(name)) -+ dev_warn(i2c->dev, "scl clock name truncated"); -+ -+ init.name = name; -+ init.ops = &spacemit_i2c_clk_ops; -+ init.parent_data = (struct clk_parent_data[]) { -+ { .fw_name = "func" }, -+ }; -+ init.num_parents = 1; -+ -+ i2c->scl_clk_hw.init = &init; -+ -+ return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw); -+} -+ - static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) - { - writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); -@@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - val |= SPACEMIT_CR_MSDIE; - } - -- if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) -+ if (i2c->mode == SPACEMIT_MODE_FAST) - val |= SPACEMIT_CR_MODE_FAST; - - /* disable response to general call */ -@@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_IRCR); - - spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); -+ -+ /* -+ * Initialize IWCR to the value specified by the I2C IP designer. -+ * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard -+ * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when -+ * IWCR contains this specific value. -+ */ -+ writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR); - } - - static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) -@@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); - - /* For now, this driver doesn't support high-speed. */ -- if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { -- dev_warn(dev, "unsupported clock frequency %u; using %u\n", -- i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); -+ if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && -+ i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { -+ i2c->mode = SPACEMIT_MODE_FAST; -+ } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { -+ i2c->mode = SPACEMIT_MODE_STANDARD; -+ } else { -+ dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); -+ i2c->mode = SPACEMIT_MODE_FAST; - i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; -- } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { -- dev_warn(dev, "unsupported clock frequency %u; using %u\n", -- i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); -- i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; - } - - i2c->dev = &pdev->dev; -@@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); - -+ ret = spacemit_i2c_register_scl_clk(i2c); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register scl clock\n"); -+ -+ i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl"); -+ if (IS_ERR(i2c->scl_clk)) -+ return dev_err_probe(dev, PTR_ERR(i2c->scl_clk), -+ "failed to get scl clock\n"); -+ - clk = devm_clk_get_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); -@@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - return dev_err_probe(dev, PTR_ERR(rst), - "failed to acquire deasserted reset\n"); - -+ ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to set rate for SCL clock"); -+ -+ ret = clk_prepare_enable(i2c->scl_clk); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to prepare and enable clock"); -+ -+ ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare, -+ i2c->scl_clk); -+ if (ret) -+ return ret; -+ - spacemit_i2c_reset(i2c); - - i2c_set_adapdata(&i2c->adapt, i2c); --- -2.53.0 - diff --git a/SPECS/linux-lts/0398-UPSTREAM-riscv-also-select-ARCH_KEEP_MEMBLOCK-if-kex.patch b/SPECS/linux-lts/0398-UPSTREAM-riscv-also-select-ARCH_KEEP_MEMBLOCK-if-kex.patch new file mode 100644 index 0000000000..d946566608 --- /dev/null +++ b/SPECS/linux-lts/0398-UPSTREAM-riscv-also-select-ARCH_KEEP_MEMBLOCK-if-kex.patch @@ -0,0 +1,38 @@ +From ffdcc545657a81c173eccf702463e8e760627d50 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 00:55:46 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: also select ARCH_KEEP_MEMBLOCK if kexec + is selected + +On RISC-V, also select ARCH_KEEP_MEMBLOCK if kexec is selected, not +only if ACPI is selected. This is because kexec requires the memblock +areas to be kept after boot to initialize the secondary kernel. This +is needed for both Device Tree and ACPI platforms. + +Signed-off-by: Han Gao +Link: https://patch.msgid.link/20260519165546.123105-1-gaohan@iscas.ac.cn +[pjw@kernel.org: change to add the dependency on kexec, rather than making it unconditional; + rewrite the patch description accordingly] +Signed-off-by: Paul Walmsley +(cherry picked from commit bce35135fecc7a73c60aaa9d2ec699ead1e32661) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 4946ac7b6db1..5a3e88128ee0 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -56,7 +56,7 @@ config RISCV + select ARCH_HAS_UBSAN + select ARCH_HAS_VDSO_ARCH_DATA if HAVE_GENERIC_VDSO + select ARCH_HAVE_NMI_SAFE_CMPXCHG +- select ARCH_KEEP_MEMBLOCK if ACPI ++ select ARCH_KEEP_MEMBLOCK if ACPI || KEXEC + select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU + select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX + select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT +-- +2.53.0 + diff --git a/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch deleted file mode 100644 index 7e3a638bb7..0000000000 --- a/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 362a9bc03d8080d38e5ea64ba2c39884e945e945 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 8 May 2026 15:25:25 +0800 -Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when - clock-frequency property is absent - -The clock-frequency property is optional according to the DT binding. -Do not emit a warning when the property is missing and fall back to the -default frequency instead. - -Reviewed-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index c6fe2052e479..7cf5c05a20d2 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -833,9 +833,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (!i2c) - return -ENOMEM; - -- ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); -- if (ret && ret != -EINVAL) -- dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); -+ of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); - - /* For now, this driver doesn't support high-speed. */ - if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && -@@ -844,7 +842,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { - i2c->mode = SPACEMIT_MODE_STANDARD; - } else { -- dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); -+ dev_info(dev, "clock-frequency not set or out of range, using fast mode\n"); - i2c->mode = SPACEMIT_MODE_FAST; - i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0399-UPSTREAM-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux-lts/0399-UPSTREAM-riscv-kexec_file-Constrain-segment-placemen.patch new file mode 100644 index 0000000000..7f4b0dceed --- /dev/null +++ b/SPECS/linux-lts/0399-UPSTREAM-riscv-kexec_file-Constrain-segment-placemen.patch @@ -0,0 +1,54 @@ +From c6c0627d65fe33069ebb3a211a784b8f5722c21b Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sat, 6 Jun 2026 20:17:58 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: kexec_file: Constrain segment placement + to direct map + +When kexec_file_load places segments with buf_max=ULONG_MAX and +top_down=true, they land at the highest available physical addresses. +On RISC-V the size of the linear mapping is determined by the active +VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 +extend the range substantially further. When the installed physical +memory exceeds the direct map size of the active mode, top-down +placement puts DTB/initrd at physical addresses outside the linearly +mapped region. The kexec'd kernel cannot reach them during early +boot, triggering a page fault at memcmp in start_kernel. + +Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects +the runtime direct map boundary for the active VM mode (SV39/SV48/ +SV57). This keeps all kexec segments within the linearly mapped +region while preserving the upstream top_down allocation strategy. + +Signed-off-by: Han Gao +Link: https://patch.msgid.link/20260519170641.123517-1-gaohan@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit b67a1ee0db0094c6cc158b087be6c334ad881a41) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/machine_kexec_file.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c +index dd9d92a96517..b5fe17238df2 100644 +--- a/arch/riscv/kernel/machine_kexec_file.c ++++ b/arch/riscv/kernel/machine_kexec_file.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -266,7 +267,7 @@ int load_extra_segments(struct kimage *image, unsigned long kernel_start, + + kbuf.image = image; + kbuf.buf_min = kernel_start + kernel_len; +- kbuf.buf_max = ULONG_MAX; ++ kbuf.buf_max = PFN_PHYS(max_low_pfn); + + #ifdef CONFIG_CRASH_DUMP + /* Add elfcorehdr */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch deleted file mode 100644 index 837fc9207b..0000000000 --- a/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 56ba1d8c335d661163b9d3b1d870a9e07dd575cc Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:56 +0200 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add pinctrl - support for voltage switching - -Document pinctrl properties to support voltage-dependent pin -configuration switching for UHS-I SD card modes. - -Add optional pinctrl-names property with two states: -- "default": For 3.3V operation with standard drive strength -- "state_uhs": For 1.8V operation with optimized drive strength - -These pinctrl states allow the SDHCI driver to coordinate voltage -switching with pin configuration changes, ensuring proper signal -integrity during UHS-I mode transitions. - -Acked-by: Conor Dooley -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-1-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 1081ea687702..e5534c781c19 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -44,6 +44,18 @@ properties: - - const: axi - - const: sdh - -+ pinctrl-names: -+ minItems: 1 -+ items: -+ - const: default -+ - const: uhs -+ -+ pinctrl-0: -+ description: Default pinctrl state for 3.3V operation -+ -+ pinctrl-1: -+ description: Optional pinctrl state for 1.8V UHS operation with "uhs" name -+ - required: - - compatible - - reg -@@ -66,4 +78,7 @@ examples: - clock-names = "core", "io"; - resets = <&syscon_apmu 2>, <&syscon_apmu 5>; - reset-names = "axi", "sdh"; -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&sdhci_default_cfg>; -+ pinctrl-1 = <&sdhci_uhs_cfg>; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0400-UPSTREAM-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux-lts/0400-UPSTREAM-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch new file mode 100644 index 0000000000..8257476d7a --- /dev/null +++ b/SPECS/linux-lts/0400-UPSTREAM-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch @@ -0,0 +1,181 @@ +From 18e50b0e446a995f40df70e3c2285bdac6c0fcd5 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Wed, 20 May 2026 18:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PMIC on OrangePi + R2S + +Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and +its associated regulators to support voltage regulation on the board. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun lan +Link: https://patch.msgid.link/20260520100000.575719-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit 793cc54475b49b5b558902b5c13e4bfe66530a50) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ + 1 file changed, 134 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index 1ecc40749e5a..b13a8d6a2670 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -13,6 +13,7 @@ / { + compatible = "xunlong,orangepi-r2s", "spacemit,k1"; + + aliases { ++ i2c8 = &i2c8; + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; +@@ -22,6 +23,15 @@ chosen { + stdout-path = "serial0"; + }; + ++ vcc4v0: regulator-vcc4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ }; ++ + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; +@@ -94,6 +104,130 @@ rgmii1: phy@1 { + }; + }; + ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <&vcc4v0>; ++ vin2-supply = <&vcc4v0>; ++ vin3-supply = <&vcc4v0>; ++ vin4-supply = <&vcc4v0>; ++ vin5-supply = <&vcc4v0>; ++ vin6-supply = <&vcc4v0>; ++ aldoin-supply = <&vcc4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1_3v3: aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch deleted file mode 100644 index 5583dc6077..0000000000 --- a/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch +++ /dev/null @@ -1,65 +0,0 @@ -From a164c67f524d96eea999938772b0e7664cf8432d Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:57 +0200 -Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: enable essential clock - infrastructure for SD operation - -Ensure SD card pins receive clock signals by enabling pad clock -generation and overriding automatic clock gating. Required for all SD -operation modes. - -The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD -and eMMC operation as both protocols use the same physical MMC interface -pins and require proper clock signal generation at the hardware level -for signal integrity and timing. - -Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and -SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only -controllers to handle removable card scenarios. - -Tested-by: Anand Moon -Acked-by: Adrian Hunter -Tested-by: Trevor Gamblin -Reviewed-by: Troy Mitchell -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-2-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 455656f9842d..0dd06fc19b85 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -21,6 +21,13 @@ - #include "sdhci.h" - #include "sdhci-pltfm.h" - -+#define SPACEMIT_SDHC_OP_EXT_REG 0x108 -+#define SDHC_OVRRD_CLK_OEN BIT(11) -+#define SDHC_FORCE_CLK_ON BIT(12) -+ -+#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C -+#define SDHC_GEN_PAD_CLK_ON BIT(6) -+ - #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 - #define SDHC_MISC_INT_EN BIT(1) - #define SDHC_MISC_INT BIT(2) -@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) - - if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) - spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); -+ -+ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); -+ -+ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) -+ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, -+ SPACEMIT_SDHC_OP_EXT_REG); - } - - static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) --- -2.53.0 - diff --git a/SPECS/linux-lts/0401-UPSTREAM-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux-lts/0401-UPSTREAM-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch new file mode 100644 index 0000000000..e8f37c6f38 --- /dev/null +++ b/SPECS/linux-lts/0401-UPSTREAM-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch @@ -0,0 +1,102 @@ +From b888c1af17bb7d9698d667fe697cf2ce716998fe Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 26 May 2026 15:22:58 -0400 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Add Ziccrse + extension for X100 cores + +Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse +provides a forward progress guarantee on LR/SC sequences in main +memory regions with cacheability and coherence PMAs. + +The SpacemiT X100 core supports it per the SpacemiT K3 hardware +specification. + +Signed-off-by: Guodong Xu +Reviewed-by: Yixun lan +Link: https://patch.msgid.link/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit b4a789799d4c2be03a2c9a4e06f3ea817bb04416) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 7e3cdd42ab8e..0b5c6c741ba1 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -36,7 +36,7 @@ cpu_0: cpu@0 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -77,7 +77,7 @@ cpu_1: cpu@1 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -118,7 +118,7 @@ cpu_2: cpu@2 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -159,7 +159,7 @@ cpu_3: cpu@3 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -200,7 +200,7 @@ cpu_4: cpu@4 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -241,7 +241,7 @@ cpu_5: cpu@5 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -282,7 +282,7 @@ cpu_6: cpu@6 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -323,7 +323,7 @@ cpu_7: cpu@7 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +-- +2.53.0 + diff --git a/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch deleted file mode 100644 index d77d4b7d8e..0000000000 --- a/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 7104b26621a3b8b7a0f213f846d4e94f40cbd6ef Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:58 +0200 -Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl - voltage switching support - -Add voltage switching infrastructure for UHS-I modes by integrating both -regulator framework (for supply voltage control) and pinctrl state -switching (for pin drive strength optimization). - -- Add regulator supply parsing and voltage switching callback -- Add optional pinctrl state switching between "default" (3.3V) and - "state_uhs" (1.8V) configurations -- Enable coordinated voltage and pin configuration changes for UHS modes - -This provides complete voltage switching support while maintaining -backward compatibility when pinctrl states are not defined. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Acked-by: Adrian Hunter -Reviewed-by: Troy Mitchell -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-3-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ - 1 file changed, 72 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 0dd06fc19b85..d9144537032a 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - - #include "sdhci.h" -@@ -71,6 +72,9 @@ - struct spacemit_sdhci_host { - struct clk *clk_core; - struct clk *clk_io; -+ struct pinctrl *pinctrl; -+ struct pinctrl_state *pinctrl_default; -+ struct pinctrl_state *pinctrl_uhs; - }; - - /* All helper functions will update clr/set while preserve rest bits */ -@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) - SPACEMIT_SDHC_PHY_CTRL_REG); - } - -+static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, -+ struct mmc_ios *ios) -+{ -+ struct sdhci_host *host = mmc_priv(mmc); -+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); -+ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); -+ struct pinctrl_state *state; -+ int ret; -+ -+ ret = sdhci_start_signal_voltage_switch(mmc, ios); -+ if (ret) -+ return ret; -+ -+ if (!sdhst->pinctrl) -+ return 0; -+ -+ /* Select appropriate pinctrl state based on signal voltage */ -+ switch (ios->signal_voltage) { -+ case MMC_SIGNAL_VOLTAGE_330: -+ state = sdhst->pinctrl_default; -+ break; -+ case MMC_SIGNAL_VOLTAGE_180: -+ state = sdhst->pinctrl_uhs; -+ break; -+ default: -+ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); -+ return 0; -+ } -+ -+ ret = pinctrl_select_state(sdhst->pinctrl, state); -+ if (ret) { -+ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); -+ return 0; -+ } -+ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", -+ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); -+ -+ return 0; -+} -+ - static inline int spacemit_sdhci_get_clocks(struct device *dev, - struct sdhci_pltfm_host *pltfm_host) - { -@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) - return 0; - } - -+static inline void spacemit_sdhci_get_pins(struct device *dev, -+ struct sdhci_pltfm_host *pltfm_host) -+{ -+ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); -+ -+ sdhst->pinctrl = devm_pinctrl_get(dev); -+ if (IS_ERR(sdhst->pinctrl)) { -+ sdhst->pinctrl = NULL; -+ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); -+ return; -+ } -+ -+ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); -+ if (IS_ERR(sdhst->pinctrl_default)) -+ sdhst->pinctrl_default = NULL; -+ -+ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); -+ if (IS_ERR(sdhst->pinctrl_uhs)) -+ sdhst->pinctrl_uhs = NULL; -+ -+ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", -+ sdhst->pinctrl_default, sdhst->pinctrl_uhs); -+} -+ - static const struct sdhci_ops spacemit_sdhci_ops = { - .get_max_clock = spacemit_sdhci_clk_get_max_clock, - .reset = spacemit_sdhci_reset, -@@ -324,6 +392,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - - host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; - -+ spacemit_sdhci_get_pins(dev, pltfm_host); -+ -+ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; -+ - ret = spacemit_sdhci_get_clocks(dev, pltfm_host); - if (ret) - goto err_pltfm; --- -2.53.0 - diff --git a/SPECS/linux-lts/0402-UPSTREAM-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux-lts/0402-UPSTREAM-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch new file mode 100644 index 0000000000..2ac544628f --- /dev/null +++ b/SPECS/linux-lts/0402-UPSTREAM-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch @@ -0,0 +1,55 @@ +From 4ab83cd1c5eede7457f1f446a59bbaa8a8f3d768 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 28 May 2026 19:38:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Enhance the logging check for mmu + mapping + +When enabling dirty ring, the dirty bitmap is disable, and the logging +check is always false as the RISC-V architecture does not select +"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded +since the write path already trying to add the dirty log, the logic for +logging check is broken and some side effect will occurs. + +Enhance the logging check for mmu mapping so it can check both the dirty +ring and the dirty bitmap. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Anup Patel +Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com +Signed-off-by: Anup Patel +(cherry picked from commit 851334760330dafa68ab8f371e804ea6ad56ff9a) +Signed-off-by: Han Gao +--- + arch/riscv/kvm/mmu.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c +index 58f5f3536ffd..a0d9c113258e 100644 +--- a/arch/riscv/kvm/mmu.c ++++ b/arch/riscv/kvm/mmu.c +@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, + enum kvm_mr_change change) + { + /* +- * At this point memslot has been committed and there is an +- * allocated dirty_bitmap[], dirty pages will be tracked while +- * the memory slot is write protected. ++ * At this point memslot has been committed and dirty pages will be ++ * tracked while the memory slot is write protected. + */ + if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) + mmu_wp_memory_region(kvm, new->id); +@@ -314,8 +313,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, + struct vm_area_struct *vma; + struct kvm *kvm = vcpu->kvm; + struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; +- bool logging = (memslot->dirty_bitmap && +- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; ++ bool logging = kvm_slot_dirty_track_enabled(memslot) && ++ !(memslot->flags & KVM_MEM_READONLY); + unsigned long vma_pagesize, mmu_seq; + struct kvm_gstage gstage; + struct page *page; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch deleted file mode 100644 index a431dd69fd..0000000000 --- a/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 88c16045a194f9da4ac3d1e41104c2bc67bef52f Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:59 +0200 -Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR tuning - support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Implement software tuning algorithm to enable UHS-I SDR modes for SD -card operation and HS200 mode for eMMC. This adds both TX and RX delay -line tuning based on the SpacemiT K1 controller capabilities. - -Algorithm features: -- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) -- Conditional tuning: only for high-speed modes (≥100MHz) -- TX tuning: configure transmit delay line with optimal values - (dline_reg=0, delaycode=127) to ensure optimal signal output timing -- RX tuning: single-pass window detection algorithm testing full - delay range (0-255) to find optimal receive timing window -- Retry mechanism: multiple fallback delays within optimal window - for improved reliability - -Tested-by: Anand Moon -Acked-by: Adrian Hunter -Tested-by: Trevor Gamblin -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-4-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ - 1 file changed, 172 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index d9144537032a..37b0911e7cf2 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -69,6 +69,28 @@ - #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) - #define SDHC_RX_BIAS_CTRL BIT(5) - -+#define SPACEMIT_SDHC_RX_CFG_REG 0x118 -+#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) -+#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) -+#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) -+ -+#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 -+#define SDHC_DLINE_PU BIT(0) -+#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) -+#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) -+ -+#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 -+#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) -+#define SDHC_RX_DLINE_GAIN BIT(8) -+#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) -+ -+#define SPACEMIT_RX_DLINE_REG 9 -+#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 -+#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF -+ -+#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 -+#define SPACEMIT_TX_TUNING_DELAYCODE 127 -+ - struct spacemit_sdhci_host { - struct clk *clk_core; - struct clk *clk_io; -@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u - sdhci_writel(host, val, reg); - } - -+static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, -+ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), -+ SPACEMIT_SDHC_DLINE_CTRL_REG); -+} -+ -+static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, -+ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), -+ SPACEMIT_SDHC_DLINE_CTRL_REG); -+} -+ -+static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, -+ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), -+ SPACEMIT_SDHC_DLINE_CFG_REG); -+} -+ -+static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) -+{ -+ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); -+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); -+ udelay(5); -+} -+ -+static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, -+ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), -+ SPACEMIT_SDHC_DLINE_CFG_REG); -+ -+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); -+ udelay(5); -+ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, -+ SPACEMIT_SDHC_RX_CFG_REG); -+ -+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) -+ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); -+} -+ - static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) - { - sdhci_reset(host, mask); -@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) - return clk_get_rate(pltfm_host->clk); - } - -+static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) -+{ -+ int current_len = 0, current_start = 0; -+ int max_pass_len = 0, max_pass_start = 0; -+ struct mmc_host *mmc = host->mmc; -+ struct mmc_ios ios = mmc->ios; -+ u8 final_delay; -+ int ret = 0; -+ int i; -+ -+ /* -+ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and -+ * if clock frequency is greater than 100MHz in these modes. -+ */ -+ if (host->clock < 100 * 1000 * 1000 || -+ !(ios.timing == MMC_TIMING_MMC_HS200 || -+ ios.timing == MMC_TIMING_UHS_SDR50 || -+ ios.timing == MMC_TIMING_UHS_SDR104)) -+ return 0; -+ -+ if (mmc->caps2 & MMC_CAP2_NO_MMC) { -+ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); -+ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); -+ spacemit_sdhci_tx_tuning_prepare(host); -+ -+ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", -+ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); -+ } -+ -+ spacemit_sdhci_prepare_tuning(host); -+ -+ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { -+ spacemit_sdhci_set_rx_delay(host, i); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ -+ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", -+ i, ret == 0 ? "pass" : "fail"); -+ -+ if (ret == 0) { -+ /* Test passed - extend current window */ -+ if (current_len == 0) -+ current_start = i; -+ current_len++; -+ } else { -+ /* Test failed - check if current window is best so far */ -+ if (current_len > max_pass_len) { -+ max_pass_len = current_len; -+ max_pass_start = current_start; -+ } -+ current_len = 0; -+ } -+ } -+ -+ if (current_len > max_pass_len) { -+ max_pass_len = current_len; -+ max_pass_start = current_start; -+ } -+ -+ if (max_pass_len < 3) { -+ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); -+ return -EIO; -+ } -+ -+ final_delay = max_pass_start + max_pass_len / 2; -+ spacemit_sdhci_set_rx_delay(host, final_delay); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ if (ret) { -+ u8 retry_delays[] = { -+ max_pass_start + max_pass_len / 4, -+ max_pass_start + (3 * max_pass_len) / 4, -+ max_pass_start, -+ max_pass_start + max_pass_len - 1 -+ }; -+ int retry_count = ARRAY_SIZE(retry_delays); -+ -+ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", -+ final_delay); -+ -+ for (i = 0; i < retry_count; i++) { -+ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && -+ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { -+ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ if (!ret) { -+ final_delay = retry_delays[i]; -+ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", -+ final_delay); -+ break; -+ } -+ } -+ } -+ -+ if (ret) { -+ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); -+ return -EIO; -+ } -+ } -+ -+ dev_dbg(mmc_dev(host->mmc), -+ "Tuning successful: window %d-%d, using delay %d\n", -+ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); -+ -+ return 0; -+} -+ - static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) - { - struct sdhci_host *host = mmc_priv(mmc); -@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { - .set_bus_width = sdhci_set_bus_width, - .set_clock = spacemit_sdhci_set_clock, - .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, -+ .platform_execute_tuning = spacemit_sdhci_execute_tuning, - }; - - static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0403-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-phy-int.patch b/SPECS/linux-lts/0403-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-phy-int.patch new file mode 100644 index 0000000000..38bb88c006 --- /dev/null +++ b/SPECS/linux-lts/0403-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-phy-int.patch @@ -0,0 +1,59 @@ +From 27323eb8136e33d506d96efa5b34658c0fe05a8c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 23 Jun 2026 15:46:34 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: dwmac-spacemit: Fix wrong phy + interface definition + +The current MII interface register definition from the vendor is wrong, +use the right number for the macro. Also, correct the interface mask +in spacemit_set_phy_intf_sel() so it can update the register with the +right number + +Fixes: 30f0ba420ed3 ("net: stmmac: Add glue layer for Spacemit K3 SoC") +Signed-off-by: Inochi Amaoto +Reviewed-by: Maxime Chevallier +Link: https://patch.msgid.link/20260623074637.503864-2-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit d1e3a4c3b24d4430d9987a3f349c6c2a959a389a) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +index 223754cc5c79..3bfb6d49be6c 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +@@ -18,8 +18,10 @@ + #include "stmmac_platform.h" + + /* ctrl register bits */ +-#define CTRL_PHY_INTF_RGMII BIT(3) +-#define CTRL_PHY_INTF_MII BIT(4) ++#define CTRL_PHY_INTF_MODE GENMASK(4, 3) ++#define CTRL_PHY_INTF_RMII FIELD_PREP(CTRL_PHY_INTF_MODE, 0) ++#define CTRL_PHY_INTF_RGMII FIELD_PREP(CTRL_PHY_INTF_MODE, 1) ++#define CTRL_PHY_INTF_MII FIELD_PREP(CTRL_PHY_INTF_MODE, 3) + #define CTRL_WAKE_IRQ_EN BIT(9) + #define CTRL_PHY_IRQ_EN BIT(12) + +@@ -118,7 +120,7 @@ static void spacemit_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, + + static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) + { +- unsigned int mask = CTRL_PHY_INTF_MII | CTRL_PHY_INTF_RGMII; ++ unsigned int mask = CTRL_PHY_INTF_MODE; + struct spacmit_dwmac *dwmac = bsp_priv; + unsigned int val = 0; + +@@ -128,6 +130,7 @@ static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) + break; + + case PHY_INTF_SEL_RMII: ++ val = CTRL_PHY_INTF_RMII; + break; + + case PHY_INTF_SEL_RGMII: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch deleted file mode 100644 index acee11c137..0000000000 --- a/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch +++ /dev/null @@ -1,105 +0,0 @@ -From c7ea3695cea289291e871b1d5ee24585b4b969ad Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:48:59 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1: add SD card - controller and pinctrl support - -Add SD card controller infrastructure for SpacemiT K1 SoC with complete -pinctrl support for both standard and UHS modes. - -- Add sdhci0 controller definition with clocks, resets and interrupts -- Add mmc1_cfg pinctrl for 3.3V standard SD operation -- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation -- Configure appropriate drive strength and power-source properties - -This provides complete SD card infrastructure that K1-based boards can -enable. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Tested-by: Vincent Legoll -Reviewed-by: Troy Mitchell -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ - 2 files changed, 53 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index 34d88334e95e..4e9a62d0e85b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -590,4 +590,44 @@ ssp3-0-frm-pins { - power-source = <3300>; - }; - }; -+ -+ mmc1_cfg: mmc1-cfg { -+ mmc1-data-cmd-pins { -+ pinmux = , /* mmc1_d3 */ -+ , /* mmc1_d2 */ -+ , /* mmc1_d1 */ -+ , /* mmc1_d0 */ -+ ; /* mmc1_cmd */ -+ bias-pull-up = <1>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ -+ mmc1-clk-pins { -+ pinmux = ; /* mmc1_clk */ -+ bias-pull-down = <1>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ mmc1_uhs_cfg: mmc1-uhs-cfg { -+ mmc1-data-cmd-pins { -+ pinmux = , /* mmc1_d3 */ -+ , /* mmc1_d2 */ -+ , /* mmc1_d1 */ -+ , /* mmc1_d0 */ -+ ; /* mmc1_cmd */ -+ bias-pull-up = <1>; -+ drive-strength = <42>; -+ power-source = <1800>; -+ }; -+ -+ mmc1-clk-pins { -+ pinmux = ; /* mmc1_clk */ -+ bias-pull-down = <1>; -+ drive-strength = <42>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 8774a00a854b..4a359190f633 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1323,6 +1323,19 @@ usb_dwc3: usb@c0a00000 { - status = "disabled"; - }; - -+ sdhci0: mmc@d4280000 { -+ compatible = "spacemit,k1-sdhci"; -+ reg = <0x0 0xd4280000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_SDH_AXI>, -+ <&syscon_apmu CLK_SDH0>; -+ clock-names = "core", "io"; -+ resets = <&syscon_apmu RESET_SDH_AXI>, -+ <&syscon_apmu RESET_SDH0>; -+ reset-names = "axi", "sdh"; -+ interrupts = <99>; -+ status = "disabled"; -+ }; -+ - emmc: mmc@d4281000 { - compatible = "spacemit,k1-sdhci"; - reg = <0x0 0xd4281000 0x0 0x200>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0404-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-irq-def.patch b/SPECS/linux-lts/0404-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-irq-def.patch new file mode 100644 index 0000000000..d814720d53 --- /dev/null +++ b/SPECS/linux-lts/0404-UPSTREAM-net-stmmac-dwmac-spacemit-Fix-wrong-irq-def.patch @@ -0,0 +1,38 @@ +From 407faee624342cf52e173a9481305cc6eb8e456a Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 23 Jun 2026 15:46:35 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: dwmac-spacemit: Fix wrong irq + definition + +The current irq definition of the wake irq and the lpi irq +is wrong, replace them with the right number and name. + +Fixes: 30f0ba420ed3 ("net: stmmac: Add glue layer for Spacemit K3 SoC") +Signed-off-by: Inochi Amaoto +Reviewed-by: Maxime Chevallier +Link: https://patch.msgid.link/20260623074637.503864-3-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit bf5cd5d4ca423d348e01b3bbcdccd0e02b1b408b) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +index 3bfb6d49be6c..322bdf167a4a 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +@@ -22,8 +22,8 @@ + #define CTRL_PHY_INTF_RMII FIELD_PREP(CTRL_PHY_INTF_MODE, 0) + #define CTRL_PHY_INTF_RGMII FIELD_PREP(CTRL_PHY_INTF_MODE, 1) + #define CTRL_PHY_INTF_MII FIELD_PREP(CTRL_PHY_INTF_MODE, 3) +-#define CTRL_WAKE_IRQ_EN BIT(9) +-#define CTRL_PHY_IRQ_EN BIT(12) ++#define CTRL_LPI_IRQ_EN BIT(9) ++#define CTRL_WAKE_IRQ_EN BIT(12) + + /* dline register bits */ + #define RGMII_RX_DLINE_EN BIT(0) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch deleted file mode 100644 index ba6141397e..0000000000 --- a/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 43968e62edda768281d634a038212b96befc49e5 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:49:00 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add SD - card support with UHS modes - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with GPIO_ACTIVE_LOW logic -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) - -This enables full SD card functionality including high-speed UHS modes -for improved performance. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Tested-by: Michael Opdenacker -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- - 1 file changed, 21 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index c95ca38e3d4a..bd40bc9011e2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -17,6 +17,8 @@ aliases { - serial0 = &uart0; - ethernet0 = ð0; - ethernet1 = ð1; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - - chosen { -@@ -202,7 +204,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -319,3 +321,21 @@ hub_3_0: hub@2 { - vdd-supply = <&vcc_5v0>; - }; - }; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4_3v3>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0405-UPSTREAM-dt-bindings-riscv-spacemit-add-deepcomputin.patch b/SPECS/linux-lts/0405-UPSTREAM-dt-bindings-riscv-spacemit-add-deepcomputin.patch new file mode 100644 index 0000000000..073007da3e --- /dev/null +++ b/SPECS/linux-lts/0405-UPSTREAM-dt-bindings-riscv-spacemit-add-deepcomputin.patch @@ -0,0 +1,37 @@ +From 539b63af7f1e72efe62cb18355b5ffa9e2ea3a9f Mon Sep 17 00:00:00 2001 +From: Sandie Cao +Date: Tue, 21 Apr 2026 14:42:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: add + deepcomputing,fml13v05 + +Document the compatible string for the Deepcomputing fml13v05. +It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework +Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. + +Acked-by: Conor Dooley +Signed-off-by: Sandie Cao +Reviewed-by: Troy Mitchell +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260421064200.1582367-1-sandie.cao@deepcomputing.io +Signed-off-by: Yixun Lan +(cherry picked from commit a17be027dc5ccd51b99b5bc7b487ba9fbdc554e8) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index eca403a8e49e..5fa5080e1f61 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -27,6 +27,7 @@ properties: + - const: spacemit,k1 + - items: + - enum: ++ - deepcomputing,fml13v05 + - spacemit,k3-pico-itx + - const: spacemit,k3 + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch deleted file mode 100644 index 5173364a60..0000000000 --- a/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 139e0716fdfe2ce733d52f88221f1b6727235cf7 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:49:01 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add SD - card support with UHS modes - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up - support -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) - -This enables full SD card functionality including high-speed UHS modes -for improved performance. - -Suggested-by: Anand Moon -Tested-by: Anand Moon -Tested-by: Margherita Milani -Tested-by: Aurelien Jarno -Reviewed-by: Aurelien Jarno -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- - 1 file changed, 22 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index b48a485f954b..b15f4c36e622 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -18,6 +18,8 @@ aliases { - spi3 = &spi3; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - - chosen { -@@ -267,7 +269,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -288,7 +290,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -421,3 +423,21 @@ hub_3_0: hub@2 { - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; - }; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0406-UPSTREAM-riscv-dts-spacemit-add-DeepComputing-FML13V.patch b/SPECS/linux-lts/0406-UPSTREAM-riscv-dts-spacemit-add-DeepComputing-FML13V.patch new file mode 100644 index 0000000000..f8991d0349 --- /dev/null +++ b/SPECS/linux-lts/0406-UPSTREAM-riscv-dts-spacemit-add-DeepComputing-FML13V.patch @@ -0,0 +1,89 @@ +From 5bb2f1fa80f4d0c23b08ab1736164985cf0ee1df Mon Sep 17 00:00:00 2001 +From: Sandie Cao +Date: Tue, 21 Apr 2026 14:43:06 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add DeepComputing + FML13V05 board device tree + +The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V +SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, +which has (Framework) SKU FRANHQ0001. + +The FML13V05 board features: +- SpacemiT K3 RISC-V SoC +- LPDDR5 16GB or 32GB +- eMMC 32GB ~128GB (Optional) +- UFS 3.1 256G (Optional) +- QSPI Flash +- MicroSD Slot +- PCIe-based Wi-Fi +- 4 USB-C Ports + - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1 + - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz) + - Port 3 & 4: USB 3.2 Gen 1 + +This minimal device tree enables booting into a serial console with UART +output. + +Signed-off-by: Sandie Cao +Reviewed-by: Troy Mitchell +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260421064306.1583888-1-sandie.cao@deepcomputing.io +Signed-off-by: Yixun Lan +(cherry picked from commit 448fedd56cdfa68c2e661b16a8dfc8f3c40a1bcf) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + .../spacemit/k3-deepcomputing-fml13v05.dts | 31 +++++++++++++++++++ + 2 files changed, 32 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index 7e2b87702571..acb993c452ba 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +new file mode 100644 +index 000000000000..b5d5112de358 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2026 DeepComputing (HK) Limited ++ */ ++ ++#include "k3.dtsi" ++#include "k3-pinctrl.dtsi" ++ ++/ { ++ model = "DeepComputing FML13V05"; ++ compatible = "deepcomputing,fml13v05", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch deleted file mode 100644 index fc44499a76..0000000000 --- a/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 25997e10bcbb4842cd8f7f69db1754a807b4515b Mon Sep 17 00:00:00 2001 -From: Trevor Gamblin -Date: Fri, 15 May 2026 12:49:02 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD - card support with UHS modes - -Update the Muse Pi Pro devicetree with SD card support to match what -was done for the OrangePi RV2 in [1]. More precisely: - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with internal pull-up support -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) -- Update PMIC configuration to use per-regulator supply properties - -[1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# - -Tested-by: Andre Heider -Signed-off-by: Trevor Gamblin -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-4-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 60 +++++++++++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index c8bf776511c9..9952014701f7 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -19,8 +19,20 @@ aliases { - serial0 = &uart0; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - -+ reg_vcc_4v: vcc-4v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_4v"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ - chosen { - stdout-path = "serial0:115200n8"; - }; -@@ -399,3 +411,51 @@ hub_3_0: hub@2 { - reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ - }; - }; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin4-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ -+ regulators { -+ buck4: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0407-UPSTREAM-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux-lts/0407-UPSTREAM-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch new file mode 100644 index 0000000000..27d9ebfe94 --- /dev/null +++ b/SPECS/linux-lts/0407-UPSTREAM-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch @@ -0,0 +1,49 @@ +From b2ab39df317dc237462f72052e611ab59e6d80a6 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 20 May 2026 23:45:27 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: Add K3 + CoM260-IFX board +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module +with a reference carrier board. + +The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD +card slot and includes interfaces such as dual MIPI CSI-2 connectors, +M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin +expansion header. + +The carrier board is intended as a general-purpose development platform +for CoM260 module and exposes interfaces for all of storage, display, +networking, and camera connectivity. + +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3abf3f5c84fd32a95132a403e0209c8010b227f8) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index 5fa5080e1f61..9f1a6e65c7c8 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -30,6 +30,11 @@ properties: + - deepcomputing,fml13v05 + - spacemit,k3-pico-itx + - const: spacemit,k3 ++ - items: ++ - enum: ++ - spacemit,k3-com260-ifx ++ - const: spacemit,k3-com260 ++ - const: spacemit,k3 + + additionalProperties: true + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch deleted file mode 100644 index 5f154ddf37..0000000000 --- a/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 30f59c0f689a00390e4183a7b58ec3108d1d55a8 Mon Sep 17 00:00:00 2001 -From: Thomas Gerner -Date: Thu, 14 May 2026 20:32:01 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Enable wifi on the - BeagleV-Ahead - -The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology -Inc. connected to SDIO1. The chip is compatible to the broadcom wireless -driver. - -The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and -Bluetooth 5.4 module. Bluetooth is not enabled by this patch. - -Signed-off-by: Thomas Gerner -Link: https://lore.kernel.org/r/20260514183510.234063-1-thomas.gerner@muenchen-mail.de -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -index 91f3f9b987bc..e16484a47653 100644 ---- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -@@ -86,6 +86,11 @@ hdmi_con_in: endpoint { - }; - }; - }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ -+ }; - }; - - &osc { -@@ -239,6 +244,28 @@ rx-pins { - slew-rate = <0>; - }; - }; -+ -+ wifi_pins: wifi-0 { -+ host-wake-pins { -+ pins = "GPIO2_25"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <1>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ reg-on-pins { -+ pins = "GPIO2_31"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <3>; -+ input-disable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ }; - }; - - &sdio0 { -@@ -247,6 +274,27 @@ &sdio0 { - status = "okay"; - }; - -+&sdio1 { -+ bus-width = <4>; -+ max-frequency = <198000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ non-removable; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ status = "okay"; -+ -+ wifi@1 { -+ compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <25 IRQ_TYPE_EDGE_RISING>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &dpu { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0408-UPSTREAM-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux-lts/0408-UPSTREAM-riscv-dts-spacemit-k3-Initial-support-for-C.patch new file mode 100644 index 0000000000..3a96620ed0 --- /dev/null +++ b/SPECS/linux-lts/0408-UPSTREAM-riscv-dts-spacemit-k3-Initial-support-for-C.patch @@ -0,0 +1,308 @@ +From 9bcfedccd2cec21b6492289885ac684deeca84e0 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 20 May 2026 23:45:28 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Initial support for + CoM260-IFX board + +The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer +module with a carrier board. The module integrates the K3 SoC, LPDDR5, +UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers +a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, +DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. + +Add initial support for enabling Serial UART and ethernet. + +Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit cfe5c91cb73c87f9021e446ec9d323c483851c46) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ + arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ + 4 files changed, 245 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts + create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index acb993c452ba..28ec9e1e0a62 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +new file mode 100644 +index 000000000000..238bb03d0e9e +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Yixun Lan ++ */ ++ ++#include "k3-com260.dtsi" ++ ++/ { ++ model = "SpacemiT K3 CoM260 IFX"; ++ compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = ð1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +new file mode 100644 +index 000000000000..a38d7b738258 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +@@ -0,0 +1,190 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Yixun Lan ++ */ ++#include ++ ++#include "k3.dtsi" ++#include "k3-pinctrl.dtsi" ++ ++/ { ++ model = "SpacemiT K3 CoM260 Module"; ++ compatible = "spacemit,k3-com260", "spacemit,k3"; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++ ++ reg_5v_sys: regulator-5v-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "P5V0_SYS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; ++ vin1-supply = <®_5v_sys>; ++ vin2-supply = <®_5v_sys>; ++ vin3-supply = <®_5v_sys>; ++ vin4-supply = <®_5v_sys>; ++ vin5-supply = <®_5v_sys>; ++ vin6-supply = <®_5v_sys>; ++ aldoin-supply = <®_5v_sys>; ++ dldoin1-supply = <&buck4>; ++ dldoin2-supply = <&buck4>; ++ ++ regulators { ++ buck1: buck1 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2: buck2 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3: buck3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4: buck4 { ++ regulator-min-microvolt = <2100000>; ++ regulator-max-microvolt = <2100000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6: buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <500000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1: aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo2: aldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo3: aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4: aldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo1: dldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo2: dldo2 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo3: dldo3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo4: dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ }; ++ ++ dldo5: dldo5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo6: dldo6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo7: dldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; ++}; ++ ++ð1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy1>; ++ status = "okay"; ++ ++ mdio { ++ phy1: phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <10000>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 252c64af76fe..3ee1471f3798 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -45,6 +45,39 @@ gmac0-phy-0-pins { + }; + }; + ++ gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { ++ gmac1-rgmii-0-pins { ++ pinmux = , /* gmac1_rxdv */ ++ , /* gmac1 rx d0 */ ++ , /* gmac1 rx d1 */ ++ , /* gmac1 rx_clk */ ++ , /* gmac1 rx d2 */ ++ , /* gmac1 rx d3 */ ++ , /* gmac1 tx d0 */ ++ , /* gmac1 tx d1 */ ++ , /* gmac1 tx clk */ ++ , /* gmac1 tx d2 */ ++ , /* gmac1 tx d3 */ ++ , /* gmac1 tx_en */ ++ , /* gmac1 mdc */ ++ ; /* gmac1 mdio */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ gmac1_phy_0_cfg: gmac1-phy-0-cfg { ++ gmac1-phy-0-pins { ++ pinmux = ; /* gmac1 int */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch deleted file mode 100644 index d8e8c34faf..0000000000 --- a/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch +++ /dev/null @@ -1,47 +0,0 @@ -From d02e702da21996ccb557b91e5cb594f6c76e0025 Mon Sep 17 00:00:00 2001 -From: Florian Schmaus -Date: Tue, 12 May 2026 08:32:31 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: module: Use generic cmp_int() instead - of custom cmp_3way() - -The module-sections.c file defines a custom cmp_3way() macro to perform -3-way comparisons during relocation sorting. - -Instead of maintaining our own implementation, use the generic -cmp_int() macro provided by the already included . This -removes redundant code and relies on standard kernel interfaces. - -Signed-off-by: Florian Schmaus -Link: https://lore.kernel.org/r/20260512063231.708256-1-florian.schmaus@codasip.com -Signed-off-by: Han Gao ---- - arch/riscv/kernel/module-sections.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module-sections.c -index 1675cbad8619..33750a51f157 100644 ---- a/arch/riscv/kernel/module-sections.c -+++ b/arch/riscv/kernel/module-sections.c -@@ -56,17 +56,15 @@ unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) - return (unsigned long)&plt[i]; - } - --#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) -- - static int cmp_rela(const void *a, const void *b) - { - const Elf_Rela *x = a, *y = b; - int i; - - /* sort by type, symbol index and addend */ -- i = cmp_3way(x->r_info, y->r_info); -+ i = cmp_int(x->r_info, y->r_info); - if (i == 0) -- i = cmp_3way(x->r_addend, y->r_addend); -+ i = cmp_int(x->r_addend, y->r_addend); - return i; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0409-UPSTREAM-riscv-Implement-ARCH_HAS_CC_CAN_LINK.patch b/SPECS/linux-lts/0409-UPSTREAM-riscv-Implement-ARCH_HAS_CC_CAN_LINK.patch new file mode 100644 index 0000000000..17f5734c7e --- /dev/null +++ b/SPECS/linux-lts/0409-UPSTREAM-riscv-Implement-ARCH_HAS_CC_CAN_LINK.patch @@ -0,0 +1,61 @@ +From eb84757dd5d3bdd86b9d2416592634a065006323 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Sat, 6 Jun 2026 20:17:52 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: Implement ARCH_HAS_CC_CAN_LINK +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The generic CC_CAN_LINK detection relies on -m32/-m64 compiler flags. +These are not supported by riscv compilers. + +Use architecture-specific logic using -mabi instead. + +Prefer the 'd' ABI variant when possible as todays toolchains are most +likely to provide a libc for that one. + +Signed-off-by: Thomas Weißschuh +Link: https://patch.msgid.link/20260316-cc-can-link-riscv-v4-1-64c072b456dd@linutronix.de +Signed-off-by: Paul Walmsley +(cherry picked from commit 84894ceb3c2ef5c5404359efd4edc6c438aa6d0c) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 5a3e88128ee0..12bebdbaaf9f 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -25,6 +25,7 @@ config RISCV + select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 + select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE + select ARCH_HAS_BINFMT_FLAT ++ select ARCH_HAS_CC_CAN_LINK + select ARCH_HAS_CURRENT_STACK_POINTER + select ARCH_HAS_DEBUG_VIRTUAL if MMU + select ARCH_HAS_DEBUG_VM_PGTABLE +@@ -1337,6 +1338,20 @@ config PORTABLE + config ARCH_PROC_KCORE_TEXT + def_bool y + ++config ARCH_CC_CAN_LINK ++ bool ++ default $(cc_can_link_user,-march=rv64g -mabi=lp64d) if 64BIT && FPU ++ default $(cc_can_link_user,-march=rv64g -mabi=lp64) if 64BIT ++ default $(cc_can_link_user,-march=rv32g -mabi=ilp32d) if FPU ++ default $(cc_can_link_user,-march=rv32g -mabi=ilp32) ++ ++config ARCH_USERFLAGS ++ string ++ default "-march=rv64g -mabi=lp64d" if 64BIT && FPU ++ default "-march=rv64g -mabi=lp64" if 64BIT ++ default "-march=rv32g -mabi=ilp32d" if FPU ++ default "-march=rv32g -mabi=ilp32" ++ + menu "Power management options" + + source "kernel/power/Kconfig" +-- +2.53.0 + diff --git a/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch deleted file mode 100644 index 616724be18..0000000000 --- a/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 41705cbe35101c7de961fb93f3c0d01b4f424bd3 Mon Sep 17 00:00:00 2001 -From: Thorsten Blum -Date: Tue, 12 May 2026 19:20:35 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: propagate insert_resource result from - add_resource - -Currently, add_resource() returns 1 on success, even though its callers -only check for negative values. Instead, propagate the insert_resource() -result from add_resource() to align with standard kernel return-value -conventions (0 on success, negative errno on failure). - -Use %pR to print the full resource range while at it. - -Signed-off-by: Thorsten Blum -Link: https://lore.kernel.org/r/20260512172034.328405-4-thorsten.blum@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/setup.c | 11 ++++------- - 1 file changed, 4 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c -index b5bc5fc65cea..13b27a078912 100644 ---- a/arch/riscv/kernel/setup.c -+++ b/arch/riscv/kernel/setup.c -@@ -75,16 +75,13 @@ static struct resource *standard_resources; - static int __init add_resource(struct resource *parent, - struct resource *res) - { -- int ret = 0; -+ int ret; - - ret = insert_resource(parent, res); -- if (ret < 0) { -- pr_err("Failed to add a %s resource at %llx\n", -- res->name, (unsigned long long) res->start); -- return ret; -- } -+ if (ret < 0) -+ pr_err("Failed to add resource %s %pR\n", res->name, res); - -- return 1; -+ return ret; - } - - static int __init add_kernel_resources(void) --- -2.53.0 - diff --git a/SPECS/linux-lts/0410-UPSTREAM-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts/0410-UPSTREAM-riscv-dts-spacemit-k3-Add-USB2.0-support.patch new file mode 100644 index 0000000000..f14ee7c204 --- /dev/null +++ b/SPECS/linux-lts/0410-UPSTREAM-riscv-dts-spacemit-k3-Add-USB2.0-support.patch @@ -0,0 +1,104 @@ +From 35e5453fa87c5e5d93a992e15b4581f6940f1037 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 30 Mar 2026 22:15:21 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: Add USB2.0 support + +There is one USB2.0 host in K3 SoC which use DWC3 IP but only provide +USB2.0 functionality, and with only one USB2 PHY connected. + +The USB2.0 controller on Pico-ITX board connects to a Terminus FE1.1 Hub +which fully USB2.0 protocol compliant and provides 4 ports. + +Link: https://patch.msgid.link/20260330-02-k3-usb20-dts-v2-1-46af262fb4a9@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit d3bd58f3060f28ecd30df51925a9b1f62e5e8c9b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 4486dc1fe114..b89c1521e664 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -26,6 +26,14 @@ memory@100000000 { + reg = <0x1 0x00000000 0x4 0x00000000>; + }; + ++ reg_aux_vcc3v3: regulator-aux-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + reg_aux_vcc5v: regulator-aux-vcc5v { + compatible = "regulator-fixed"; + regulator-name = "AUX_VCC5V"; +@@ -197,3 +205,19 @@ &uart0 { + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; ++ ++&usb2_host { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ vdd-supply = <®_aux_vcc3v3>; ++ }; ++}; ++ ++&usb2_phy { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 0b5c6c741ba1..19fc9b49668e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -438,6 +438,37 @@ soc: soc { + dma-noncoherent; + ranges; + ++ usb2_host: usb@c0a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, ++ <&syscon_apmu RESET_APMU_USB2_VCC>, ++ <&syscon_apmu RESET_APMU_USB2_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ phys = <&usb2_phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ dr_mode = "host"; ++ maximum-speed = "high-speed"; ++ status = "disabled"; ++ }; ++ ++ usb2_phy: phy@c0a20000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0xc0a20000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + eth0: ethernet@cac80000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac80000 0x0 0x2000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch deleted file mode 100644 index d8ae0df53d..0000000000 --- a/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch +++ /dev/null @@ -1,91 +0,0 @@ -From a380dc5ba876575445cbffdd6abae226725a9fce Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:36 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support - -To reuse the K1 PCIe driver logic for K3 PCIe controller, add device -data to handle the K1 specific logic and make room for the incoming -logic for K3. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-2-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 25 ++++++++++++++++--- - 1 file changed, 21 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index be20a520255b..1b519d49dcc0 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -57,6 +57,12 @@ struct k1_pcie { - u32 pmu_off; - }; - -+struct k1_pcie_device_data { -+ const struct dw_pcie_host_ops *host_ops; -+ const struct dw_pcie_ops *ops; -+ int (*parse_port)(struct k1_pcie *k1); -+}; -+ - #define to_k1_pcie(dw_pcie) \ - platform_get_drvdata(to_platform_device((dw_pcie)->dev)) - -@@ -278,10 +284,15 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) - - static int k1_pcie_probe(struct platform_device *pdev) - { -+ const struct k1_pcie_device_data *data; - struct device *dev = &pdev->dev; - struct k1_pcie *k1; - int ret; - -+ data = device_get_match_data(dev); -+ if (!data) -+ return -ENODEV; -+ - k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); - if (!k1) - return -ENOMEM; -@@ -299,11 +310,11 @@ static int k1_pcie_probe(struct platform_device *pdev) - "failed to map \"link\" registers\n"); - - k1->pci.dev = dev; -- k1->pci.ops = &k1_pcie_ops; -+ k1->pci.ops = data->ops; - k1->pci.pp.num_vectors = MAX_MSI_IRQS; - dw_pcie_cap_set(&k1->pci, REQ_RES); - -- k1->pci.pp.ops = &k1_pcie_host_ops; -+ k1->pci.pp.ops = data->host_ops; - - /* Hold the PHY in reset until we start the link */ - regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, -@@ -320,7 +331,7 @@ static int k1_pcie_probe(struct platform_device *pdev) - - platform_set_drvdata(pdev, k1); - -- ret = k1_pcie_parse_port(k1); -+ ret = data->parse_port(k1); - if (ret) - return dev_err_probe(dev, ret, "failed to parse root port\n"); - -@@ -338,8 +349,14 @@ static void k1_pcie_remove(struct platform_device *pdev) - dw_pcie_host_deinit(&k1->pci.pp); - } - -+static const struct k1_pcie_device_data k1_pcie_device_data = { -+ .host_ops = &k1_pcie_host_ops, -+ .ops = &k1_pcie_ops, -+ .parse_port = k1_pcie_parse_port, -+}; -+ - static const struct of_device_id k1_pcie_of_match_table[] = { -- { .compatible = "spacemit,k1-pcie", }, -+ { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, - { } - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0411-UPSTREAM-i2c-busses-make-K1-driver-default-for-Space.patch b/SPECS/linux-lts/0411-UPSTREAM-i2c-busses-make-K1-driver-default-for-Space.patch new file mode 100644 index 0000000000..688e56d13d --- /dev/null +++ b/SPECS/linux-lts/0411-UPSTREAM-i2c-busses-make-K1-driver-default-for-Space.patch @@ -0,0 +1,40 @@ +From dd7106a9bf1dc7aa4b0aef4b1974a592d0d194c4 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Tue, 26 May 2026 16:36:57 +0200 +Subject: [RUYI PATCH] UPSTREAM: i2c: busses: make K1 driver default for + SpacemiT platforms + +Enable I2C_K1 by default when ARCH_SPACEMIT is configured to ensure SD +card functionality works out-of-the-box. + +SpacemiT K1 boards use I2C-controlled PMICs (like the P1 chip) to +provide SD card power supplies. Without the I2C_K1 driver enabled, +regulators cannot be controlled and SD card detection/operation fails. + +Suggested-by: Margherita Milani +Suggested-by: Yixun Lan +Signed-off-by: Iker Pedrosa +Reviewed-by: Yixun Lan +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20260526-orangepi-sd-card-i2c-v1-1-b92268bfd467@gmail.com +(cherry picked from commit d38e710fba1806974051972d69fbbd6c69b55734) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 4515ded4338c..e60faac4e337 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -799,6 +799,7 @@ config I2C_K1 + tristate "SpacemiT K1 I2C adapter" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF ++ default ARCH_SPACEMIT + help + This option enables support for the I2C interface on the SpacemiT K1 + platform. +-- +2.53.0 + diff --git a/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch deleted file mode 100644 index b4cf2fd137..0000000000 --- a/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 291d83131cb1a80661bf10272be1b0aab99fb39d Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:37 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles - support - -The PCIe controller on Spacemit K3 may use multiple PHYs at the -same time. The feature is not support by the current driver. -So extend the PHY definition to support multiple PHY handles. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-3-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 16 ++++++++++++---- - 1 file changed, 12 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index 1b519d49dcc0..7f6f1df31cd8 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -51,7 +51,8 @@ - - struct k1_pcie { - struct dw_pcie pci; -- struct phy *phy; -+ struct phy **phy; -+ int phy_count; - void __iomem *link; - struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ - u32 pmu_off; -@@ -171,7 +172,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) - */ - regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); - -- ret = phy_init(k1->phy); -+ ret = phy_init(k1->phy[0]); - if (ret) { - k1_pcie_disable_resources(k1); - -@@ -191,12 +192,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct k1_pcie *k1 = to_k1_pcie(pci); -+ int i; - - /* Assert fundamental reset (drive PERST# low) */ - regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, - PCIE_RC_PERST); - -- phy_exit(k1->phy); -+ for (i = 0; i < k1->phy_count; i++) -+ phy_exit(k1->phy[i]); - - k1_pcie_disable_resources(k1); - } -@@ -277,7 +280,12 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) - if (IS_ERR(phy)) - return PTR_ERR(phy); - -- k1->phy = phy; -+ k1->phy = devm_kmalloc_array(dev, 1, sizeof(*k1->phy), GFP_KERNEL); -+ if (!k1->phy) -+ return -ENOMEM; -+ -+ k1->phy[0] = phy; -+ k1->phy_count = 1; - - return 0; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0412-UPSTREAM-riscv-Add-build-salt-to-the-vDSO.patch b/SPECS/linux-lts/0412-UPSTREAM-riscv-Add-build-salt-to-the-vDSO.patch new file mode 100644 index 0000000000..5bca6d4e2a --- /dev/null +++ b/SPECS/linux-lts/0412-UPSTREAM-riscv-Add-build-salt-to-the-vDSO.patch @@ -0,0 +1,38 @@ +From bcf4bd53a95abd61e8023377edf74cada143466b Mon Sep 17 00:00:00 2001 +From: Bastian Blank +Date: Thu, 18 Jun 2026 18:12:30 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: Add build salt to the vDSO + +The vDSO needs to have a unique build id in a similar manner +to the kernel and modules. Use the build salt macro. + +Signed-off-by: Bastian Blank +Reviewed-by: Nam Cao +Link: https://patch.msgid.link/ajQY7n0an0YwQ--j@steamhammer.waldi.eu.org +Signed-off-by: Paul Walmsley +(cherry picked from commit c8c5a7835f5c9e34c8a15190519a2cc9ecb9b5b5) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/vdso/note.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/kernel/vdso/note.S b/arch/riscv/kernel/vdso/note.S +index 2a956c942211..f42c7ad4f564 100644 +--- a/arch/riscv/kernel/vdso/note.S ++++ b/arch/riscv/kernel/vdso/note.S +@@ -4,9 +4,12 @@ + * Here we can supply some information useful to userland. + */ + ++#include + #include + #include + + ELFNOTE_START(Linux, 0, "a") + .long LINUX_VERSION_CODE + ELFNOTE_END ++ ++BUILD_SALT +-- +2.53.0 + diff --git a/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch deleted file mode 100644 index d0085e05ec..0000000000 --- a/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e1caa735029246df2abdcf416ccc274ca3ff53d5 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:38 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent - for MSI handle check - -The IMSIC device on RISC-V based system does not require ID -remapping for MSI. So this device only needs "msi-parent" -property for IMSIC-based SoC, and the "msi-map" is not a -necessary property. - -Add new condition for MSI handling on IMSIC based SoC. - -Signed-off-by: Inochi Amaoto -Acked-by: Rob Herring (Arm) -Link: https://lore.kernel.org/r/20260517014841.254085-4-inochiama@gmail.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -index b3216141881c..91bbbc8924f6 100644 ---- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -@@ -27,8 +27,11 @@ allOf: - - $ref: /schemas/pci/snps,dw-pcie-common.yaml# - - if: - not: -- required: -- - msi-map -+ anyOf: -+ - required: -+ - msi-map -+ - required: -+ - msi-parent - then: - properties: - interrupt-names: --- -2.53.0 - diff --git a/SPECS/linux-lts/0413-UPSTREAM-riscv-probes-save-original-sp-in-rethook-tr.patch b/SPECS/linux-lts/0413-UPSTREAM-riscv-probes-save-original-sp-in-rethook-tr.patch new file mode 100644 index 0000000000..cc9841a9c2 --- /dev/null +++ b/SPECS/linux-lts/0413-UPSTREAM-riscv-probes-save-original-sp-in-rethook-tr.patch @@ -0,0 +1,62 @@ +From 27f7ea28b3ba5ec4ea6a6cdbf6e2919bc10f0279 Mon Sep 17 00:00:00 2001 +From: Martin Kaiser +Date: Tue, 30 Jun 2026 21:40:03 +0200 +Subject: [RUYI PATCH] UPSTREAM: riscv: probes: save original sp in rethook + trampoline + +Reading a word from the stack in a kretprobe crashes a risc-v kernel. + +$ cd /sys/kernel/tracing/ +$ echo 'r n_tty_write $stack0' > dynamic_events +$ echo 1 > events/kprobes/enable +Unable to handle kernel paging request at virtual address 0000000200000128 +... +[] regs_get_kernel_stack_nth+0x26/0x38 +[] process_fetch_insn+0x3ee/0x760 +[] kretprobe_trace_func+0x116/0x1f0 +[] kretprobe_dispatcher+0x4a/0x58 +[] kretprobe_rethook_handler+0x5e/0x90 +[] rethook_trampoline_handler+0x70/0x108 +[] arch_rethook_trampoline_callback+0x12/0x1c +[] arch_rethook_trampoline+0x48/0x94 +[] tty_write+0x1a/0x30 + +In regs_get_kernel_stack_nth, regs->sp contains an arbitrary value. + +arch_rethook_trampoline saves the registers from the probed function in a +struct pt_regs. sp is not saved. Instead, sp is decremented for +arch_rethook_trampoline's local stack. + +Fix this crash and save the original sp along with the other registers. +Use a0 as a temporary register, it is overwritten anyway. + +Cc: stable@vger.kernel.org +Fixes: c22b0bcb1dd02 ("riscv: Add kprobes supported") +Signed-off-by: Martin Kaiser +Acked-by: Masami Hiramatsu (Google) +Link: https://patch.msgid.link/20260630194010.1824039-1-martin@kaiser.cx +[pjw@kernel.org: added Fixes tag; cc'ed stable] +Signed-off-by: Paul Walmsley +(cherry picked from commit bc7b086a45521a986a49045907f017e3e46c763e) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/probes/rethook_trampoline.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/kernel/probes/rethook_trampoline.S b/arch/riscv/kernel/probes/rethook_trampoline.S +index f2cd83d9b0f0..c3aa8d8cf5af 100644 +--- a/arch/riscv/kernel/probes/rethook_trampoline.S ++++ b/arch/riscv/kernel/probes/rethook_trampoline.S +@@ -41,6 +41,9 @@ + REG_S x29, PT_T4(sp) + REG_S x30, PT_T5(sp) + REG_S x31, PT_T6(sp) ++ /* save original sp */ ++ addi a0, sp, PT_SIZE_ON_STACK ++ REG_S a0, PT_SP(sp) + .endm + + .macro restore_all_base_regs +-- +2.53.0 + diff --git a/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch deleted file mode 100644 index ce7568b3bb..0000000000 --- a/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch +++ /dev/null @@ -1,162 +0,0 @@ -From f9aab33c4cd724380b176901c11e9b2d5dbe7b6f Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:39 +0800 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit - K3 PCIe host controller - -Add binding support for the PCIe controller on the SpacemiT K3 SoC. -This controller is almost a standard Synopsys DesignWare PCIe IP, -with some extra link and reset state control. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-5-inochiama@gmail.com -Signed-off-by: Han Gao ---- - .../bindings/pci/spacemit,k3-pcie-host.yaml | 135 ++++++++++++++++++ - 1 file changed, 135 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml - -diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml -new file mode 100644 -index 000000000000..46147a37a9ce ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml -@@ -0,0 +1,135 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K3 PCI Express Host Controller -+ -+maintainers: -+ - Inochi Amaoto -+ -+description: -+ The SpacemiT K3 SoC PCIe host controller is based on the Synopsys -+ DesignWare PCIe IP. The controller uses the external MSI interrupt -+ controller. -+ -+allOf: -+ - $ref: /schemas/pci/pci-host-bridge.yaml# -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k3-pcie -+ -+ reg: -+ items: -+ - description: DesignWare PCIe registers -+ - description: Data Bus Interface (DBI) shadow registers -+ - description: ATU address space -+ - description: PCIe configuration space -+ - description: Link control registers -+ -+ reg-names: -+ items: -+ - const: dbi -+ - const: dbi2 -+ - const: atu -+ - const: config -+ - const: link -+ -+ clocks: -+ items: -+ - description: DWC PCIe Data Bus Interface (DBI) clock -+ - description: DWC PCIe application AXI-bus master interface clock -+ - description: DWC PCIe application AXI-bus slave interface clock -+ -+ clock-names: -+ items: -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ resets: -+ items: -+ - description: DWC PCIe Data Bus Interface (DBI) reset -+ - description: DWC PCIe application AXI-bus master interface reset -+ - description: DWC PCIe application AXI-bus slave interface reset -+ -+ reset-names: -+ items: -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ msi-parent: true -+ -+ phys: -+ description: -+ PHY phandle from the Combo PHY, the lane number does not depends -+ on this, since the number of lanes provided by Combo PHY can be -+ 1 or 2. -+ minItems: 1 -+ maxItems: 6 -+ -+ phy-names: -+ minItems: 1 -+ maxItems: 6 -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ description: -+ A phandle that refers to the APMU system controller, whose regmap is -+ used in managing resets and link state, along with and offset of its -+ reset control register. -+ items: -+ - items: -+ - description: phandle to APMU system controller -+ - description: register offset -+ -+required: -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - msi-parent -+ - spacemit,apmu -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu 89>, -+ <&syscon_apmu 56>, -+ <&syscon_apmu 57>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu 76>, -+ <&syscon_apmu 78>, -+ <&syscon_apmu 77>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ }; -+ }; -+ --- -2.53.0 - diff --git a/SPECS/linux-lts/0414-UPSTREAM-ACPI-RIMT-Only-defer-the-IOMMU-configuratio.patch b/SPECS/linux-lts/0414-UPSTREAM-ACPI-RIMT-Only-defer-the-IOMMU-configuratio.patch new file mode 100644 index 0000000000..cb693a734d --- /dev/null +++ b/SPECS/linux-lts/0414-UPSTREAM-ACPI-RIMT-Only-defer-the-IOMMU-configuratio.patch @@ -0,0 +1,54 @@ +From 0cec38fef3db4241a48d39e7b155ef7372fb168a Mon Sep 17 00:00:00 2001 +From: Yicong Yang +Date: Thu, 25 Jun 2026 17:47:02 +0800 +Subject: [RUYI PATCH] UPSTREAM: ACPI: RIMT: Only defer the IOMMU configuration + in init stage + +The IOMMU configuration will be deferred if the IOMMU driver +isn't probed by the time. Make this deferral only in the +initialization stage with driver_deferred_probe_check_state(). +Otherwise the devices depends on IOMMU will be deferred forever +in case the IOMMU device probe failed or it doesn't appear in +the ACPI namespace. + +Fixes: 8f7729552582 ("ACPI: RISC-V: Add support for RIMT") +Signed-off-by: Yicong Yang +Link: https://patch.msgid.link/20260625094702.11558-1-yang.yicong@picoheart.com +[pjw@kernel.org: added Fixes line] +Signed-off-by: Paul Walmsley +(cherry picked from commit b8f62414fa05144924257db283c5c35f74d21121) +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/rimt.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c +index 8eaa8731bddd..4c0962e68c94 100644 +--- a/drivers/acpi/riscv/rimt.c ++++ b/drivers/acpi/riscv/rimt.c +@@ -9,6 +9,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -257,11 +258,11 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 + rimt_fwnode = rimt_get_fwnode(node); + + /* +- * The IOMMU drivers may not be probed yet. +- * Defer the IOMMU configuration ++ * The IOMMU drivers may not be probed yet. Defer the IOMMU ++ * configuration if it's still in initialization stage. + */ + if (!rimt_fwnode) +- return -EPROBE_DEFER; ++ return driver_deferred_probe_check_state(dev); + + /* + * EPROBE_DEFER ensures IOMMU is probed before the devices that +-- +2.53.0 + diff --git a/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch deleted file mode 100644 index 66e63181b2..0000000000 --- a/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch +++ /dev/null @@ -1,258 +0,0 @@ -From 28a3c6b229dbe4b76f568ab83a3d0405809c7f1b Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:40 +0800 -Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host - controller support - -The PCIe controller on Spacemit K3 is almost a standard Synopsys -DesignWare PCIe IP with extra link and reset control. Unlike -the PCIe controller on K1, this controller supports external MSI -interrupt controller and can use multiple PHYs at the same time. - -Add driver to support PCIe controller on Spacemit K3 PCIe. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-6-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/Kconfig | 4 +- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 169 ++++++++++++++++++ - 2 files changed, 171 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig -index 5e0656eea718..bb3c32e64c98 100644 ---- a/drivers/pci/controller/dwc/Kconfig -+++ b/drivers/pci/controller/dwc/Kconfig -@@ -417,7 +417,7 @@ config PCIE_SOPHGO_DW - Sophgo SoCs. - - config PCIE_SPACEMIT_K1 -- tristate "SpacemiT K1 PCIe controller (host mode)" -+ tristate "SpacemiT K1/K3 PCIe controller (host mode)" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on HAS_IOMEM - select PCIE_DW_HOST -@@ -425,7 +425,7 @@ config PCIE_SPACEMIT_K1 - default ARCH_SPACEMIT - help - Enables support for the DesignWare based PCIe controller in -- the SpacemiT K1 SoC operating in host mode. Three controllers -+ the SpacemiT K1/K3 SoC operating in host mode. Three controllers - are available on the K1 SoC; the first of these shares a PHY - with a USB 3.0 host controller (one or the other can be used). - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index 7f6f1df31cd8..7854d26220a9 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -23,6 +23,7 @@ - - #define PCI_VENDOR_ID_SPACEMIT 0x201f - #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 - - /* Offsets and field definitions for link management registers */ - #define K1_PHY_AHB_IRQ_EN 0x0000 -@@ -32,8 +33,20 @@ - #define SMLH_LINK_UP BIT(1) - #define RDLH_LINK_UP BIT(12) - -+#define INTR_STATUS 0x0010 -+ - #define INTR_ENABLE 0x0014 - #define MSI_CTRL_INT BIT(11) -+#define RDLH_LINK_UP_INT BIT(20) -+ -+#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 -+ -+#define K3_ADDR_INTR_STATUS1 0x0018 -+ -+#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) -+#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf -+ -+#define K3_MAX_PHY_NUMBER 6 - - /* Some controls require APMU regmap access */ - #define SYSCON_APMU "spacemit,apmu" -@@ -48,6 +61,9 @@ - - #define PCIE_CONTROL_LOGIC 0x0004 - #define PCIE_SOFT_RESET BIT(0) -+#define PCIE_PERSTN_OE BIT(24) -+#define PCIE_PERSTN_OUT BIT(25) -+#define PCIE_IGNORE_PERSTN BIT(31) - - struct k1_pcie { - struct dw_pcie pci; -@@ -262,6 +278,152 @@ static const struct dw_pcie_ops k1_pcie_ops = { - .stop_link = k1_pcie_stop_link, - }; - -+static int k3_pcie_enable_phy(struct k1_pcie *pcie) -+{ -+ int i, ret; -+ -+ for (i = 0; i < pcie->phy_count; i++) { -+ ret = phy_init(pcie->phy[i]); -+ if (ret) -+ goto err_phy; -+ } -+ -+ return 0; -+ -+err_phy: -+ while (--i >= 0) -+ phy_exit(pcie->phy[i]); -+ -+ return ret; -+} -+ -+static int k3_pcie_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ struct k1_pcie *k1 = to_k1_pcie(pci); -+ u32 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; -+ u32 val; -+ int ret; -+ -+ regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); -+ -+ k1_pcie_toggle_soft_reset(k1); -+ -+ ret = k1_pcie_enable_resources(k1); -+ if (ret) -+ return ret; -+ -+ regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); -+ regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); -+ -+ ret = k3_pcie_enable_phy(k1); -+ if (ret) { -+ k1_pcie_disable_resources(k1); -+ return ret; -+ } -+ -+ /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ -+ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, -+ PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); -+ usleep_range(1000, 2000); -+ regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); -+ -+ msleep(PCIE_T_PVPERL_MS); -+ -+ /* -+ * Put the controller in root complex mode, and indicate that -+ * Vaux (3.3v) is present. -+ */ -+ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, -+ PCIE_PERSTN_OUT | PCIE_PERSTN_OE); -+ -+ val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); -+ val = u32_replace_bits(val, GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE, -+ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); -+ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); -+ -+ dw_pcie_dbi_ro_wr_en(pci); -+ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); -+ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K3); -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ /* Finally, as a workaround, disable ASPM L1 */ -+ k1_pcie_disable_aspm_l1(k1); -+ -+ return 0; -+} -+ -+static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ u32 val; -+ -+ dw_pcie_dbi_ro_wr_en(pci); -+ -+ val = dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); -+ val |= u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, -+ K3_CACHE_MSTR_AWCACHE_MODE); -+ dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); -+ -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ return 0; -+} -+ -+static const struct dw_pcie_host_ops k3_pcie_host_ops = { -+ .init = k3_pcie_init, -+ .deinit = k1_pcie_deinit, -+ .msi_init = k3_pcie_msi_host_init, -+}; -+ -+static const struct dw_pcie_ops k3_pcie_ops = { -+ .link_up = k1_pcie_link_up, -+ .start_link = k1_pcie_start_link, -+ .stop_link = k1_pcie_stop_link, -+}; -+ -+static void k3_pcie_clear_irq_status(struct k1_pcie *k1, -+ u32 *status0, u32 *status1, u32 *status2) -+{ -+ *status0 = readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); -+ *status1 = readl_relaxed(k1->link + INTR_STATUS); -+ *status2 = readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); -+ -+ writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); -+ writel_relaxed(*status1, k1->link + INTR_STATUS); -+ writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); -+} -+ -+static int k3_pcie_parse_port(struct k1_pcie *k1) -+{ -+ struct device *dev = k1->pci.dev; -+ u32 status0, status1, status2; -+ int i; -+ -+ k1->phy = devm_kmalloc_array(dev, K3_MAX_PHY_NUMBER, sizeof(*k1->phy), -+ GFP_KERNEL); -+ if (!k1->phy) -+ return -ENOMEM; -+ -+ for (i = 0; i < K3_MAX_PHY_NUMBER; i++) { -+ k1->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); -+ if (IS_ERR(k1->phy[i])) { -+ if (PTR_ERR(k1->phy[i]) == -ENODEV) -+ break; -+ -+ return PTR_ERR(k1->phy[i]); -+ } -+ } -+ -+ k1->phy_count = i; -+ if (k1->phy_count == 0) -+ return -EINVAL; -+ -+ k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); -+ -+ return 0; -+} -+ - static int k1_pcie_parse_port(struct k1_pcie *k1) - { - struct device *dev = k1->pci.dev; -@@ -363,8 +525,15 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { - .parse_port = k1_pcie_parse_port, - }; - -+static const struct k1_pcie_device_data k3_pcie_device_data = { -+ .host_ops = &k3_pcie_host_ops, -+ .ops = &k3_pcie_ops, -+ .parse_port = k3_pcie_parse_port, -+}; -+ - static const struct of_device_id k1_pcie_of_match_table[] = { - { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, -+ { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, - { } - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0415-UPSTREAM-phy-move-spacemit-pcie-driver-to-its-subfol.patch b/SPECS/linux-lts/0415-UPSTREAM-phy-move-spacemit-pcie-driver-to-its-subfol.patch new file mode 100644 index 0000000000..43da71f843 --- /dev/null +++ b/SPECS/linux-lts/0415-UPSTREAM-phy-move-spacemit-pcie-driver-to-its-subfol.patch @@ -0,0 +1,100 @@ +From 96b3e72a2b88678a06248bfb352a95baaa87b976 Mon Sep 17 00:00:00 2001 +From: Vinod Koul +Date: Mon, 23 Feb 2026 12:12:39 +0530 +Subject: [RUYI PATCH] UPSTREAM: phy: move spacemit pcie driver to its + subfolder + +Commit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller") +created spacemit subfolder with usb driver while commit 57e920b92724 +("phy: spacemit: Introduce PCIe/combo PHY") added pcie driver in phy +folder. Move latter into spacemit subfolder and rename file to +phy-k1-pcie.c + +Reviewed-by: Alex Elder +Reviewed-by: Yixun Lan +Link: https://patch.msgid.link/20260223064240.386617-1-vkoul@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit 75fb1a33f9ac4c9730e61bb19aaaab02023a99b2) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 12 ------------ + drivers/phy/Makefile | 1 - + drivers/phy/spacemit/Kconfig | 12 ++++++++++++ + drivers/phy/spacemit/Makefile | 1 + + .../phy-k1-pcie.c} | 0 + 5 files changed, 13 insertions(+), 13 deletions(-) + rename drivers/phy/{phy-spacemit-k1-pcie.c => spacemit/phy-k1-pcie.c} (100%) + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 88ea9af445b1..c39b40876177 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -101,18 +101,6 @@ config PHY_NXP_PTN3222 + schemes. It supports all three USB 2.0 data rates: Low Speed, Full + Speed and High Speed. + +-config PHY_SPACEMIT_K1_PCIE +- tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" +- depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on COMMON_CLK +- depends on HAS_IOMEM +- depends on OF +- select GENERIC_PHY +- default ARCH_SPACEMIT +- help +- Enable support for the PCIe and USB 3 combo PHY and two +- PCIe-only PHYs used in the SpacemiT K1 SoC. +- + source "drivers/phy/allwinner/Kconfig" + source "drivers/phy/amlogic/Kconfig" + source "drivers/phy/broadcom/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index 950dd4f14372..e1aea28dbf6b 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -13,7 +13,6 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o + obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o + obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o + obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o +-obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o + obj-y += allwinner/ \ + amlogic/ \ + broadcom/ \ +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 0136aee2e8a2..50b0005acf66 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -2,6 +2,18 @@ + # + # Phy drivers for SpacemiT platforms + # ++config PHY_SPACEMIT_K1_PCIE ++ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on COMMON_CLK ++ depends on HAS_IOMEM ++ depends on OF ++ select GENERIC_PHY ++ default ARCH_SPACEMIT ++ help ++ Enable support for the PCIe and USB 3 combo PHY and two ++ PCIe-only PHYs used in the SpacemiT K1 SoC. ++ + config PHY_SPACEMIT_K1_USB2 + tristate "SpacemiT K1 USB 2.0 PHY support" + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index fec0b425a948..a821a21d6142 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o +diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/spacemit/phy-k1-pcie.c +similarity index 100% +rename from drivers/phy/phy-spacemit-k1-pcie.c +rename to drivers/phy/spacemit/phy-k1-pcie.c +-- +2.53.0 + diff --git a/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch deleted file mode 100644 index 80bd621ef2..0000000000 --- a/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch +++ /dev/null @@ -1,76 +0,0 @@ -From e933fb1426b50978196a70b05655d5cb7a3bcb76 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 16 May 2026 16:00:30 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable QSPI for OrangePi - RV2 - -Enable the QSPI controller and the XM25QU128C SPI NOR flash on the -OrangePi RV2 board. Add a flash partition layout from vendor UBoot. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260516080030.1736836-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ - 1 file changed, 45 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index bd40bc9011e2..0b4d4d1418e2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -290,6 +290,51 @@ &pcie2 { - status = "okay"; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck3_1v8>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x00000 0x010000>; -+ }; -+ -+ private@10000 { -+ reg = <0x10000 0x010000>; -+ }; -+ -+ fsbl@20000 { -+ reg = <0x20000 0x040000>; -+ }; -+ -+ env@60000 { -+ reg = <0x60000 0x010000>; -+ }; -+ -+ opensbi@70000 { -+ reg = <0x70000 0x030000>; -+ }; -+ -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0416-UPSTREAM-scsi-ufs-dt-bindings-amd-versal2-Add-UFS-Ho.patch b/SPECS/linux-lts/0416-UPSTREAM-scsi-ufs-dt-bindings-amd-versal2-Add-UFS-Ho.patch new file mode 100644 index 0000000000..1de9e1fc38 --- /dev/null +++ b/SPECS/linux-lts/0416-UPSTREAM-scsi-ufs-dt-bindings-amd-versal2-Add-UFS-Ho.patch @@ -0,0 +1,93 @@ +From 717427296655d4abcf6d70e8ca8c7a7403bb684d Mon Sep 17 00:00:00 2001 +From: Sai Krishna Potthuri +Date: Tue, 21 Oct 2025 17:00:00 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: dt-bindings: amd-versal2: Add UFS + Host Controller for AMD Versal Gen 2 SoC + +Add devicetree document for UFS Host Controller on AMD Versal Gen 2 SoC. +This includes clocks and clock-names as mandated by UFS common bindings. + +Signed-off-by: Sai Krishna Potthuri +Co-developed-by: Ajay Neeli +Signed-off-by: Ajay Neeli +Reviewed-by: Conor Dooley +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-2-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 754c6f539effa8ad332e305e34665849638fa40f) +Signed-off-by: Han Gao +--- + .../bindings/ufs/amd,versal2-ufs.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml + +diff --git a/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml +new file mode 100644 +index 000000000000..c00ec342d574 +--- /dev/null ++++ b/Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/ufs/amd,versal2-ufs.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: AMD Versal Gen 2 UFS Host Controller ++ ++maintainers: ++ - Sai Krishna Potthuri ++ ++allOf: ++ - $ref: ufs-common.yaml ++ ++properties: ++ compatible: ++ const: amd,versal2-ufs ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ clock-names: ++ items: ++ - const: core ++ ++ power-domains: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 2 ++ ++ reset-names: ++ items: ++ - const: host ++ - const: phy ++ ++required: ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ufs@f10b0000 { ++ compatible = "amd,versal2-ufs"; ++ reg = <0xf10b0000 0x1000>; ++ clocks = <&ufs_core_clk>; ++ clock-names = "core"; ++ resets = <&scmi_reset 4>, <&scmi_reset 35>; ++ reset-names = "host", "phy"; ++ interrupts = ; ++ freq-table-hz = <0 0>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch deleted file mode 100644 index 7ce6604711..0000000000 --- a/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 9ffbd34c853c426d82f3daf0bb7512fc1b08d611 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 02:58:36 +0000 -Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock - -According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus -clock enable bit was wrongly swapped, the correct one should be: - -Register : APMU_USB_CLK_RES_CTRL -bit[1] : usb2_port_bus_clk_en -bit[0] : usb2_port_ahb_rstn - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Reported-by: Junzhong Pan -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index cb0c4277f72a..03de04144963 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -777,7 +777,7 @@ static const struct clk_parent_data sdh2_parents[] = { - CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, - BIT(11), 5, 3, BIT(4), 0); - --CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); - CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); - CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); - CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); --- -2.53.0 - diff --git a/SPECS/linux-lts/0417-UPSTREAM-scsi-firmware-xilinx-Add-support-for-secure.patch b/SPECS/linux-lts/0417-UPSTREAM-scsi-firmware-xilinx-Add-support-for-secure.patch new file mode 100644 index 0000000000..379e89467c --- /dev/null +++ b/SPECS/linux-lts/0417-UPSTREAM-scsi-firmware-xilinx-Add-support-for-secure.patch @@ -0,0 +1,137 @@ +From 37ad30b40e9c272af82adac50f530c09b367a610 Mon Sep 17 00:00:00 2001 +From: Izhar Ameer Shaikh +Date: Tue, 21 Oct 2025 17:00:01 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: firmware: xilinx: Add support for secure + read/write ioctl interface + +Add support for a generic ioctl read/write interface using which users +can request firmware to perform read/write operations on a protected and +secure address space. + +The functionality is introduced through the means of two new IOCTL IDs +which extend the existing PM_IOCTL EEMI API: + + - IOCTL_READ_REG + - IOCTL_MASK_WRITE_REG + +The caller only passes the node id of the given device and an offset. +The base address is not exposed to the caller and internally retrieved +by the firmware. Firmware will enforce an access policy on the incoming +read/write request. + +Signed-off-by: Izhar Ameer Shaikh +Reviewed-by: Tanmay Shah +Signed-off-by: Radhey Shyam Pandey +Signed-off-by: Ajay Neeli +Acked-by: Senthil Nathan Thangaraj +Acked-by: Michal Simek +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-3-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 00b3e8480be7a49203594bd1fdb4fd46f3b69d59) +Signed-off-by: Han Gao +--- + drivers/firmware/xilinx/zynqmp.c | 46 ++++++++++++++++++++++++++++ + include/linux/firmware/xlnx-zynqmp.h | 15 +++++++++ + 2 files changed, 61 insertions(+) + +diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c +index 02da3e48bc8f..b7cd0eca9eaa 100644 +--- a/drivers/firmware/xilinx/zynqmp.c ++++ b/drivers/firmware/xilinx/zynqmp.c +@@ -1616,6 +1616,52 @@ int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, + return zynqmp_pm_invoke_fn(PM_IOCTL, payload, 3, 0, IOCTL_GET_FEATURE_CONFIG, id); + } + ++/** ++ * zynqmp_pm_sec_read_reg - PM call to securely read from given offset ++ * of the node ++ * @node_id: Node Id of the device ++ * @offset: Offset to be used (20-bit) ++ * @ret_value: Output data read from the given offset after ++ * firmware access policy is successfully enforced ++ * ++ * Return: Returns 0 on success or error value on failure ++ */ ++int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value) ++{ ++ u32 ret_payload[PAYLOAD_ARG_CNT]; ++ u32 count = 1; ++ int ret; ++ ++ if (!ret_value) ++ return -EINVAL; ++ ++ ret = zynqmp_pm_invoke_fn(PM_IOCTL, ret_payload, 4, node_id, IOCTL_READ_REG, ++ offset, count); ++ ++ *ret_value = ret_payload[1]; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_sec_read_reg); ++ ++/** ++ * zynqmp_pm_sec_mask_write_reg - PM call to securely write to given offset ++ * of the node ++ * @node_id: Node Id of the device ++ * @offset: Offset to be used (20-bit) ++ * @mask: Mask to be used ++ * @value: Value to be written ++ * ++ * Return: Returns 0 on success or error value on failure ++ */ ++int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, u32 mask, ++ u32 value) ++{ ++ return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 5, node_id, IOCTL_MASK_WRITE_REG, ++ offset, mask, value); ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_sec_mask_write_reg); ++ + /** + * zynqmp_pm_set_sd_config - PM call to set value of SD config registers + * @node: SD node ID +diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h +index ae48d619c4e0..b161f37de5cc 100644 +--- a/include/linux/firmware/xlnx-zynqmp.h ++++ b/include/linux/firmware/xlnx-zynqmp.h +@@ -241,6 +241,7 @@ enum pm_ioctl_id { + IOCTL_GET_FEATURE_CONFIG = 27, + /* IOCTL for Secure Read/Write Interface */ + IOCTL_READ_REG = 28, ++ IOCTL_MASK_WRITE_REG = 29, + /* Dynamic SD/GEM configuration */ + IOCTL_SET_SD_CONFIG = 30, + IOCTL_SET_GEM_CONFIG = 31, +@@ -619,6 +620,9 @@ int zynqmp_pm_feature(const u32 api_id); + int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); + int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); + int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); ++int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value); ++int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, ++ u32 mask, u32 value); + int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); + int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack); +@@ -916,6 +920,17 @@ static inline int zynqmp_pm_request_wake(const u32 node, + return -ENODEV; + } + ++static inline int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset, ++ u32 mask, u32 value) ++{ ++ return -ENODEV; ++} ++ + static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) + { + return -ENODEV; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch deleted file mode 100644 index ef6c5cfcb2..0000000000 --- a/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d420aa127fcbe63635453a4103d4d013e9027703 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 02:58:37 +0000 -Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset - -According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus -clock enable bit was wrongly swapped, the correct one should be: - -Register : APMU_USB_CLK_RES_CTRL -bit[1] : usb2_port_bus_clk_en -bit[0] : usb2_port_ahb_rstn - -Fixes: a0e0c2f8c5f3 ("reset: spacemit: k3: Decouple composite reset lines") -Reported-by: Junzhong Pan -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/reset-spacemit-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -index 9841f5e057b2..2e87f320cf11 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k3.c -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -- [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), - [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), - [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), --- -2.53.0 - diff --git a/SPECS/linux-lts/0418-UPSTREAM-scsi-firmware-xilinx-Add-APIs-for-UFS-PHY-i.patch b/SPECS/linux-lts/0418-UPSTREAM-scsi-firmware-xilinx-Add-APIs-for-UFS-PHY-i.patch new file mode 100644 index 0000000000..660e27b701 --- /dev/null +++ b/SPECS/linux-lts/0418-UPSTREAM-scsi-firmware-xilinx-Add-APIs-for-UFS-PHY-i.patch @@ -0,0 +1,225 @@ +From 84a63c91f60633a8bea67f024d5cf7fe363b5346 Mon Sep 17 00:00:00 2001 +From: Ajay Neeli +Date: Tue, 21 Oct 2025 17:00:02 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: firmware: xilinx: Add APIs for UFS PHY + initialization + + - Add APIs for UFS PHY initialization. + + - Verify M-PHY TX-RX configuration readiness. + + - Confirm SRAM initialization and Set SRAM bypass. + + - Retrieve UFS calibration values. + +Signed-off-by: Ajay Neeli +Acked-by: Senthil Nathan Thangaraj +Acked-by: Michal Simek +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-4-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 0e4d26f79a74bc633846a27a9a20d52217c108dc) +Signed-off-by: Han Gao +--- + drivers/firmware/xilinx/Makefile | 2 +- + drivers/firmware/xilinx/zynqmp-ufs.c | 118 +++++++++++++++++++++++ + include/linux/firmware/xlnx-zynqmp-ufs.h | 38 ++++++++ + include/linux/firmware/xlnx-zynqmp.h | 1 + + 4 files changed, 158 insertions(+), 1 deletion(-) + create mode 100644 drivers/firmware/xilinx/zynqmp-ufs.c + create mode 100644 include/linux/firmware/xlnx-zynqmp-ufs.h + +diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile +index 875a53703c82..70f8f02f14a3 100644 +--- a/drivers/firmware/xilinx/Makefile ++++ b/drivers/firmware/xilinx/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + # Makefile for Xilinx firmwares + +-obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o ++obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-ufs.o + obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o +diff --git a/drivers/firmware/xilinx/zynqmp-ufs.c b/drivers/firmware/xilinx/zynqmp-ufs.c +new file mode 100644 +index 000000000000..85da8a822f3a +--- /dev/null ++++ b/drivers/firmware/xilinx/zynqmp-ufs.c +@@ -0,0 +1,118 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Firmware Layer for UFS APIs ++ * ++ * Copyright (C) 2025 Advanced Micro Devices, Inc. ++ */ ++ ++#include ++#include ++ ++/* Register Node IDs */ ++#define PM_REGNODE_PMC_IOU_SLCR 0x30000002 /* PMC IOU SLCR */ ++#define PM_REGNODE_EFUSE_CACHE 0x30000003 /* EFUSE Cache */ ++ ++/* Register Offsets for PMC IOU SLCR */ ++#define SRAM_CSR_OFFSET 0x104C /* SRAM Control and Status */ ++#define TXRX_CFGRDY_OFFSET 0x1054 /* M-PHY TX-RX Config ready */ ++ ++/* Masks for SRAM Control and Status Register */ ++#define SRAM_CSR_INIT_DONE_MASK BIT(0) /* SRAM initialization done */ ++#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) /* SRAM External load done */ ++#define SRAM_CSR_BYPASS_MASK BIT(2) /* Bypass SRAM interface */ ++ ++/* Mask to check M-PHY TX-RX configuration readiness */ ++#define TX_RX_CFG_RDY_MASK GENMASK(3, 0) ++ ++/* Register Offsets for EFUSE Cache */ ++#define UFS_CAL_1_OFFSET 0xBE8 /* UFS Calibration Value */ ++ ++/** ++ * zynqmp_pm_is_mphy_tx_rx_config_ready - check M-PHY TX-RX config readiness ++ * @is_ready: Store output status (true/false) ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) ++{ ++ u32 regval; ++ int ret; ++ ++ if (!is_ready) ++ return -EINVAL; ++ ++ ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, TXRX_CFGRDY_OFFSET, ®val); ++ if (ret) ++ return ret; ++ ++ regval &= TX_RX_CFG_RDY_MASK; ++ if (regval) ++ *is_ready = true; ++ else ++ *is_ready = false; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready); ++ ++/** ++ * zynqmp_pm_is_sram_init_done - check SRAM initialization ++ * @is_done: Store output status (true/false) ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_is_sram_init_done(bool *is_done) ++{ ++ u32 regval; ++ int ret; ++ ++ if (!is_done) ++ return -EINVAL; ++ ++ ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, ®val); ++ if (ret) ++ return ret; ++ ++ regval &= SRAM_CSR_INIT_DONE_MASK; ++ if (regval) ++ *is_done = true; ++ else ++ *is_done = false; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_is_sram_init_done); ++ ++/** ++ * zynqmp_pm_set_sram_bypass - Set SRAM bypass Control ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_set_sram_bypass(void) ++{ ++ u32 sram_csr; ++ int ret; ++ ++ ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, &sram_csr); ++ if (ret) ++ return ret; ++ ++ sram_csr &= ~SRAM_CSR_EXT_LD_DONE_MASK; ++ sram_csr |= SRAM_CSR_BYPASS_MASK; ++ ++ return zynqmp_pm_sec_mask_write_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, ++ GENMASK(2, 1), sram_csr); ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_set_sram_bypass); ++ ++/** ++ * zynqmp_pm_get_ufs_calibration_values - Read UFS calibration values ++ * @val: Store the calibration value ++ * ++ * Return: Returns 0 on success or error value on failure. ++ */ ++int zynqmp_pm_get_ufs_calibration_values(u32 *val) ++{ ++ return zynqmp_pm_sec_read_reg(PM_REGNODE_EFUSE_CACHE, UFS_CAL_1_OFFSET, val); ++} ++EXPORT_SYMBOL_GPL(zynqmp_pm_get_ufs_calibration_values); +diff --git a/include/linux/firmware/xlnx-zynqmp-ufs.h b/include/linux/firmware/xlnx-zynqmp-ufs.h +new file mode 100644 +index 000000000000..d3538dd5822a +--- /dev/null ++++ b/include/linux/firmware/xlnx-zynqmp-ufs.h +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Firmware layer for UFS APIs. ++ * ++ * Copyright (c) 2025 Advanced Micro Devices, Inc. ++ */ ++ ++#ifndef __FIRMWARE_XLNX_ZYNQMP_UFS_H__ ++#define __FIRMWARE_XLNX_ZYNQMP_UFS_H__ ++ ++#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) ++int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready); ++int zynqmp_pm_is_sram_init_done(bool *is_done); ++int zynqmp_pm_set_sram_bypass(void); ++int zynqmp_pm_get_ufs_calibration_values(u32 *val); ++#else ++static inline int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_is_sram_init_done(bool *is_done) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_set_sram_bypass(void) ++{ ++ return -ENODEV; ++} ++ ++static inline int zynqmp_pm_get_ufs_calibration_values(u32 *val) ++{ ++ return -ENODEV; ++} ++#endif ++ ++#endif /* __FIRMWARE_XLNX_ZYNQMP_UFS_H__ */ +diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h +index b161f37de5cc..784d5920b4cd 100644 +--- a/include/linux/firmware/xlnx-zynqmp.h ++++ b/include/linux/firmware/xlnx-zynqmp.h +@@ -16,6 +16,7 @@ + #include + + #include ++#include + + #define ZYNQMP_PM_VERSION_MAJOR 1 + #define ZYNQMP_PM_VERSION_MINOR 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch deleted file mode 100644 index 05b9ee6eb7..0000000000 --- a/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch +++ /dev/null @@ -1,37 +0,0 @@ -From cf3c64c0e469dac06db3606b299ff2b6be12345c Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 20:58:16 +0000 -Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power - settings - -SpacemiT K3 SoC support dual-voltage I/O power domain, while initially -configure to 3.3v, and need to access register from APBC space to switch -to 1.8v domain. - -Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken -ethernet driver. - -Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") -Reported-by: Han Gao -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index a336de5f3d94..809067d6383c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -1035,6 +1035,7 @@ pinctrl: pinctrl@d401e000 { - clocks = <&syscon_apbc CLK_APBC_AIB>, - <&syscon_apbc CLK_APBC_AIB_BUS>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - }; - - uart10: serial@d401f000 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0419-UPSTREAM-scsi-ufs-amd-versal2-Add-UFS-support-for-AM.patch b/SPECS/linux-lts/0419-UPSTREAM-scsi-ufs-amd-versal2-Add-UFS-support-for-AM.patch new file mode 100644 index 0000000000..df1c511cd8 --- /dev/null +++ b/SPECS/linux-lts/0419-UPSTREAM-scsi-ufs-amd-versal2-Add-UFS-support-for-AM.patch @@ -0,0 +1,719 @@ +From 52e01c14272ec6eb93bb1f9b435f00c1918c7043 Mon Sep 17 00:00:00 2001 +From: Sai Krishna Potthuri +Date: Tue, 21 Oct 2025 17:00:03 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: amd-versal2: Add UFS support for + AMD Versal Gen 2 SoC + +Add support for the UFS host controller on the AMD Versal Gen 2 SoC, +built on the Synopsys DWC UFS architecture, using the UFSHCD DWC and +UFSHCD platform driver. This controller requires specific configurations +like M-PHY/RMMI/UniPro and vendor specific registers programming before +doing the UIC_LINKSTARTUP. + +Signed-off-by: Sai Krishna Potthuri +Signed-off-by: Ajay Neeli +Acked-by: Bart Van Assche +Link: https://patch.msgid.link/20251021113003.13650-5-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 769b8b2ffded4cd880669edd83e2952efeeb27f7) +Signed-off-by: Han Gao +--- + MAINTAINERS | 7 + + drivers/ufs/host/Kconfig | 13 + + drivers/ufs/host/Makefile | 1 + + drivers/ufs/host/ufs-amd-versal2.c | 564 +++++++++++++++++++++++++++++ + drivers/ufs/host/ufshcd-dwc.h | 46 +++ + include/ufs/unipro.h | 1 + + 6 files changed, 632 insertions(+) + create mode 100644 drivers/ufs/host/ufs-amd-versal2.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 996aa3d41e95..a3bc23926943 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -26403,6 +26403,13 @@ F: Documentation/devicetree/bindings/ufs/ + F: Documentation/scsi/ufs.rst + F: drivers/ufs/core/ + ++UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER AMD VERSAL2 ++M: Sai Krishna Potthuri ++M: Ajay Neeli ++S: Maintained ++F: Documentation/devicetree/bindings/ufs/amd,versal2-ufs.yaml ++F: drivers/ufs/host/ufs-amd-versal2.c ++ + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER DWC HOOKS + M: Pedro Sousa + L: linux-scsi@vger.kernel.org +diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig +index 48ee7e9b665e..964ae70e7390 100644 +--- a/drivers/ufs/host/Kconfig ++++ b/drivers/ufs/host/Kconfig +@@ -155,3 +155,16 @@ config SCSI_UFS_ROCKCHIP + + Select this if you have UFS controller on Rockchip chipset. + If unsure, say N. ++ ++config SCSI_UFS_AMD_VERSAL2 ++ tristate "AMD Versal Gen 2 UFS controller platform driver" ++ depends on SCSI_UFSHCD_PLATFORM && (ARCH_ZYNQMP || COMPILE_TEST) ++ help ++ This selects the AMD Versal Gen 2 specific additions on top of ++ the UFSHCD DWC and UFSHCD platform driver. UFS host on AMD ++ Versal Gen 2 needs some vendor specific configurations like PHY ++ and vendor specific register accesses before accessing the ++ hardware. ++ ++ Select this if you have UFS controller on AMD Versal Gen 2 SoC. ++ If unsure, say N. +diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile +index 2f97feb5db3f..65d8bb23ab7b 100644 +--- a/drivers/ufs/host/Makefile ++++ b/drivers/ufs/host/Makefile +@@ -13,3 +13,4 @@ obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o + obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o + obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o + obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o ++obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o +diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c +new file mode 100644 +index 000000000000..40543db621a1 +--- /dev/null ++++ b/drivers/ufs/host/ufs-amd-versal2.c +@@ -0,0 +1,564 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 Advanced Micro Devices, Inc. ++ * ++ * Authors: Sai Krishna Potthuri ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ufshcd-dwc.h" ++#include "ufshcd-pltfrm.h" ++#include "ufshci-dwc.h" ++ ++/* PHY modes */ ++#define UFSHCD_DWC_PHY_MODE_ROM 0 ++ ++#define MPHY_FAST_RX_AFE_CAL BIT(2) ++#define MPHY_FW_CALIB_CFG_VAL BIT(8) ++ ++#define MPHY_RX_OVRD_EN BIT(3) ++#define MPHY_RX_OVRD_VAL BIT(2) ++#define MPHY_RX_ACK_MASK BIT(0) ++ ++#define TIMEOUT_MICROSEC 1000000 ++ ++struct ufs_versal2_host { ++ struct ufs_hba *hba; ++ struct reset_control *rstc; ++ struct reset_control *rstphy; ++ u32 phy_mode; ++ unsigned long host_clk; ++ u8 attcompval0; ++ u8 attcompval1; ++ u8 ctlecompval0; ++ u8 ctlecompval1; ++}; ++ ++static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) ++{ ++ static struct ufshcd_dme_attr_val phy_write_attrs[] = { ++ { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, ++ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } ++ }; ++ ++ phy_write_attrs[0].mib_val = (u8)addr; ++ phy_write_attrs[1].mib_val = (u8)(addr >> 8); ++ phy_write_attrs[2].mib_val = (u8)val; ++ phy_write_attrs[3].mib_val = (u8)(val >> 8); ++ ++ return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); ++} ++ ++static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) ++{ ++ u32 mib_val; ++ int ret; ++ static struct ufshcd_dme_attr_val phy_read_attrs[] = { ++ { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, ++ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } ++ }; ++ ++ phy_read_attrs[0].mib_val = (u8)addr; ++ phy_read_attrs[1].mib_val = (u8)(addr >> 8); ++ ++ ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); ++ if (ret) ++ return ret; ++ ++ *val = mib_val; ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); ++ if (ret) ++ return ret; ++ ++ *val |= (mib_val << 8); ++ ++ return 0; ++} ++ ++static int ufs_versal2_enable_phy(struct ufs_hba *hba) ++{ ++ u32 offset, reg; ++ int ret; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); ++ if (ret) ++ return ret; ++ ++ /* Check Tx/Rx FSM states */ ++ for (offset = 0; offset < 2; offset++) { ++ u32 time_left, mibsel; ++ ++ time_left = TIMEOUT_MICROSEC; ++ mibsel = UIC_ARG_MIB_SEL(MTX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset)); ++ do { ++ ret = ufshcd_dme_get(hba, mibsel, ®); ++ if (ret) ++ return ret; ++ ++ if (reg == TX_STATE_HIBERN8 || reg == TX_STATE_SLEEP || ++ reg == TX_STATE_LSBURST) ++ break; ++ ++ time_left--; ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Invalid Tx FSM state.\n"); ++ return -ETIMEDOUT; ++ } ++ ++ time_left = TIMEOUT_MICROSEC; ++ mibsel = UIC_ARG_MIB_SEL(MRX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset)); ++ do { ++ ret = ufshcd_dme_get(hba, mibsel, ®); ++ if (ret) ++ return ret; ++ ++ if (reg == RX_STATE_HIBERN8 || reg == RX_STATE_SLEEP || ++ reg == RX_STATE_LSBURST) ++ break; ++ ++ time_left--; ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Invalid Rx FSM state.\n"); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return 0; ++} ++ ++static int ufs_versal2_setup_phy(struct ufs_hba *hba) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ int ret; ++ u32 reg; ++ ++ /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ ++ ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FAST_RX_AFE_CAL; ++ ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FAST_RX_AFE_CAL; ++ ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); ++ if (ret) ++ return ret; ++ ++ /* Program ATT and CTLE compensation values */ ++ if (host->attcompval0) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0); ++ if (ret) ++ return ret; ++ } ++ ++ if (host->attcompval1) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1); ++ if (ret) ++ return ret; ++ } ++ ++ if (host->ctlecompval0) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0); ++ if (ret) ++ return ret; ++ } ++ ++ if (host->ctlecompval1) { ++ ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1); ++ if (ret) ++ return ret; ++ } ++ ++ ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FW_CALIB_CFG_VAL; ++ ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_FW_CALIB_CFG_VAL; ++ return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); ++} ++ ++static int ufs_versal2_phy_init(struct ufs_hba *hba) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ u32 time_left; ++ bool is_ready; ++ int ret; ++ static const struct ufshcd_dme_attr_val rmmi_attrs[] = { ++ { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, DME_LOCAL }, ++ { UIC_ARG_MIB(CBCRCTRL), 1, DME_LOCAL }, ++ { UIC_ARG_MIB(CBC10DIRECTCONF2), 1, DME_LOCAL }, ++ { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } ++ }; ++ ++ /* Wait for Tx/Rx config_rdy */ ++ time_left = TIMEOUT_MICROSEC; ++ do { ++ time_left--; ++ ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready); ++ if (ret) ++ return ret; ++ ++ if (!is_ready) ++ break; ++ ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Tx/Rx configuration signal busy.\n"); ++ return -ETIMEDOUT; ++ } ++ ++ ret = ufshcd_dwc_dme_set_attrs(hba, rmmi_attrs, ARRAY_SIZE(rmmi_attrs)); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_deassert(host->rstphy); ++ if (ret) { ++ dev_err(hba->dev, "ufsphy reset deassert failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ /* Wait for SRAM init done */ ++ time_left = TIMEOUT_MICROSEC; ++ do { ++ time_left--; ++ ret = zynqmp_pm_is_sram_init_done(&is_ready); ++ if (ret) ++ return ret; ++ ++ if (is_ready) ++ break; ++ ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "SRAM initialization failed.\n"); ++ return -ETIMEDOUT; ++ } ++ ++ ret = ufs_versal2_setup_phy(hba); ++ if (ret) ++ return ret; ++ ++ return ufs_versal2_enable_phy(hba); ++} ++ ++static int ufs_versal2_init(struct ufs_hba *hba) ++{ ++ struct ufs_versal2_host *host; ++ struct device *dev = hba->dev; ++ struct ufs_clk_info *clki; ++ int ret; ++ u32 cal; ++ ++ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ host->hba = hba; ++ ufshcd_set_variant(hba, host); ++ ++ host->phy_mode = UFSHCD_DWC_PHY_MODE_ROM; ++ ++ list_for_each_entry(clki, &hba->clk_list_head, list) { ++ if (!strcmp(clki->name, "core")) ++ host->host_clk = clk_get_rate(clki->clk); ++ } ++ ++ host->rstc = devm_reset_control_get_exclusive(dev, "host"); ++ if (IS_ERR(host->rstc)) { ++ dev_err(dev, "failed to get reset ctrl: host\n"); ++ return PTR_ERR(host->rstc); ++ } ++ ++ host->rstphy = devm_reset_control_get_exclusive(dev, "phy"); ++ if (IS_ERR(host->rstphy)) { ++ dev_err(dev, "failed to get reset ctrl: phy\n"); ++ return PTR_ERR(host->rstphy); ++ } ++ ++ ret = reset_control_assert(host->rstc); ++ if (ret) { ++ dev_err(hba->dev, "host reset assert failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_control_assert(host->rstphy); ++ if (ret) { ++ dev_err(hba->dev, "phy reset assert failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ ret = zynqmp_pm_set_sram_bypass(); ++ if (ret) { ++ dev_err(dev, "Bypass SRAM interface failed, err = %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_control_deassert(host->rstc); ++ if (ret) ++ dev_err(hba->dev, "host reset deassert failed, err = %d\n", ret); ++ ++ ret = zynqmp_pm_get_ufs_calibration_values(&cal); ++ if (ret) { ++ dev_err(dev, "failed to read calibration values\n"); ++ return ret; ++ } ++ ++ host->attcompval0 = (u8)cal; ++ host->attcompval1 = (u8)(cal >> 8); ++ host->ctlecompval0 = (u8)(cal >> 16); ++ host->ctlecompval1 = (u8)(cal >> 24); ++ ++ hba->quirks |= UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING; ++ ++ return 0; ++} ++ ++static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ int ret = 0; ++ ++ if (status == PRE_CHANGE) { ++ ret = ufs_versal2_phy_init(hba); ++ if (ret) ++ dev_err(hba->dev, "Phy init failed (%d)\n", ret); ++ } ++ ++ return ret; ++} ++ ++static int ufs_versal2_link_startup_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ int ret = 0; ++ ++ switch (status) { ++ case PRE_CHANGE: ++ if (host->host_clk) ++ ufshcd_writel(hba, host->host_clk / 1000000, DWC_UFS_REG_HCLKDIV); ++ ++ break; ++ case POST_CHANGE: ++ ret = ufshcd_dwc_link_startup_notify(hba, status); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_req) ++{ ++ u32 time_left, reg, lane; ++ int ret; ++ ++ for (lane = 0; lane < activelanes; lane++) { ++ time_left = TIMEOUT_MICROSEC; ++ ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); ++ if (ret) ++ return ret; ++ ++ reg |= MPHY_RX_OVRD_EN; ++ if (rx_req) ++ reg |= MPHY_RX_OVRD_VAL; ++ else ++ reg &= ~MPHY_RX_OVRD_VAL; ++ ++ ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); ++ if (ret) ++ return ret; ++ ++ do { ++ ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); ++ if (ret) ++ return ret; ++ ++ reg &= MPHY_RX_ACK_MASK; ++ if (reg == rx_req) ++ break; ++ ++ time_left--; ++ usleep_range(1, 5); ++ } while (time_left); ++ ++ if (!time_left) { ++ dev_err(hba->dev, "Invalid Rx Ack value.\n"); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return 0; ++} ++ ++static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_versal2_host *host = ufshcd_get_variant(hba); ++ u32 lane, reg, rate = 0; ++ int ret = 0; ++ ++ if (status == PRE_CHANGE) { ++ memcpy(dev_req_params, dev_max_params, sizeof(struct ufs_pa_layer_attr)); ++ ++ /* If it is not a calibrated part, switch PWRMODE to SLOW_MODE */ ++ if (!host->attcompval0 && !host->attcompval1 && !host->ctlecompval0 && ++ !host->ctlecompval1) { ++ dev_req_params->pwr_rx = SLOW_MODE; ++ dev_req_params->pwr_tx = SLOW_MODE; ++ return 0; ++ } ++ ++ if (dev_req_params->pwr_rx == SLOW_MODE || dev_req_params->pwr_rx == SLOWAUTO_MODE) ++ return 0; ++ ++ if (dev_req_params->hs_rate == PA_HS_MODE_B) ++ rate = 1; ++ ++ /* Select the rate */ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), rate); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 1); ++ if (ret) ++ return ret; ++ ++ ret = ufs_versal2_phy_ratesel(hba, dev_req_params->lane_tx, 0); ++ if (ret) ++ return ret; ++ ++ /* Remove rx_req override */ ++ for (lane = 0; lane < dev_req_params->lane_tx; lane++) { ++ ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); ++ if (ret) ++ return ret; ++ ++ reg &= ~MPHY_RX_OVRD_EN; ++ ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); ++ if (ret) ++ return ret; ++ } ++ ++ if (dev_req_params->lane_tx == UFS_LANE_2 && dev_req_params->lane_rx == UFS_LANE_2) ++ ret = ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, ++ PA_INITIAL_ADAPT); ++ } ++ ++ return ret; ++} ++ ++static struct ufs_hba_variant_ops ufs_versal2_hba_vops = { ++ .name = "ufs-versal2-pltfm", ++ .init = ufs_versal2_init, ++ .link_startup_notify = ufs_versal2_link_startup_notify, ++ .hce_enable_notify = ufs_versal2_hce_enable_notify, ++ .pwr_change_notify = ufs_versal2_pwr_change_notify, ++}; ++ ++static const struct of_device_id ufs_versal2_pltfm_match[] = { ++ { ++ .compatible = "amd,versal2-ufs", ++ .data = &ufs_versal2_hba_vops, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, ufs_versal2_pltfm_match); ++ ++static int ufs_versal2_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ /* Perform generic probe */ ++ ret = ufshcd_pltfrm_init(pdev, &ufs_versal2_hba_vops); ++ if (ret) ++ dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", ret); ++ ++ return ret; ++} ++ ++static void ufs_versal2_remove(struct platform_device *pdev) ++{ ++ struct ufs_hba *hba = platform_get_drvdata(pdev); ++ ++ pm_runtime_get_sync(&(pdev)->dev); ++ ufshcd_remove(hba); ++} ++ ++static const struct dev_pm_ops ufs_versal2_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) ++ SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) ++}; ++ ++static struct platform_driver ufs_versal2_pltfm = { ++ .probe = ufs_versal2_probe, ++ .remove = ufs_versal2_remove, ++ .driver = { ++ .name = "ufshcd-versal2", ++ .pm = &ufs_versal2_pm_ops, ++ .of_match_table = of_match_ptr(ufs_versal2_pltfm_match), ++ }, ++}; ++ ++module_platform_driver(ufs_versal2_pltfm); ++ ++MODULE_AUTHOR("Sai Krishna Potthuri "); ++MODULE_DESCRIPTION("AMD Versal Gen 2 UFS Host Controller driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h +index ad91ea56662c..c618bb914904 100644 +--- a/drivers/ufs/host/ufshcd-dwc.h ++++ b/drivers/ufs/host/ufshcd-dwc.h +@@ -12,6 +12,52 @@ + + #include + ++/* RMMI Attributes */ ++#define CBREFCLKCTRL2 0x8132 ++#define CBCRCTRL 0x811F ++#define CBC10DIRECTCONF2 0x810E ++#define CBRATESEL 0x8114 ++#define CBCREGADDRLSB 0x8116 ++#define CBCREGADDRMSB 0x8117 ++#define CBCREGWRLSB 0x8118 ++#define CBCREGWRMSB 0x8119 ++#define CBCREGRDLSB 0x811A ++#define CBCREGRDMSB 0x811B ++#define CBCREGRDWRSEL 0x811C ++ ++#define CBREFREFCLK_GATE_OVR_EN BIT(7) ++ ++/* M-PHY Attributes */ ++#define MTX_FSM_STATE 0x41 ++#define MRX_FSM_STATE 0xC1 ++ ++/* M-PHY registers */ ++#define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100)) ++#define RX_PCS_OUT(n) (0x300F + ((n) * 0x100)) ++#define FAST_FLAGS(n) (0x401C + ((n) * 0x100)) ++#define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100)) ++#define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100)) ++#define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100)) ++ ++/* Tx/Rx FSM state */ ++enum rx_fsm_state { ++ RX_STATE_DISABLED = 0, ++ RX_STATE_HIBERN8 = 1, ++ RX_STATE_SLEEP = 2, ++ RX_STATE_STALL = 3, ++ RX_STATE_LSBURST = 4, ++ RX_STATE_HSBURST = 5, ++}; ++ ++enum tx_fsm_state { ++ TX_STATE_DISABLED = 0, ++ TX_STATE_HIBERN8 = 1, ++ TX_STATE_SLEEP = 2, ++ TX_STATE_STALL = 3, ++ TX_STATE_LSBURST = 4, ++ TX_STATE_HSBURST = 5, ++}; ++ + struct ufshcd_dme_attr_val { + u32 attr_sel; + u32 mib_val; +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 360e1245fb40..faf1c471ad30 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -174,6 +174,7 @@ + #define VS_POWERSTATE 0xD083 + #define VS_MPHYCFGUPDT 0xD085 + #define VS_DEBUGOMC 0xD09E ++#define VS_MPHYDISABLE 0xD0C1 + + #define PA_GRANULARITY_MIN_VAL 1 + #define PA_GRANULARITY_MAX_VAL 6 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch deleted file mode 100644 index 5640477b61..0000000000 --- a/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 24e92b2f714ec09b1217533e18d18a7a1416d52f Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:35 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on - Milk-V Jupiter - -Because the default console's baud rate is not set, defconfig kernels do -not have any serial output on this platform. Set the baud rate to -115200, matching what is used by U-Boot etc on this platform. - -See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") -Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-2-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index afaad59e6bce..db98dbfadf00 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -20,7 +20,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - leds { --- -2.53.0 - diff --git a/SPECS/linux-lts/0420-UPSTREAM-scsi-ufs-amd-versal2-Fix-PHY-initialization.patch b/SPECS/linux-lts/0420-UPSTREAM-scsi-ufs-amd-versal2-Fix-PHY-initialization.patch new file mode 100644 index 0000000000..7a26cf2da7 --- /dev/null +++ b/SPECS/linux-lts/0420-UPSTREAM-scsi-ufs-amd-versal2-Fix-PHY-initialization.patch @@ -0,0 +1,42 @@ +From fde75cf0667176b48c80b52592112e61f8335ade Mon Sep 17 00:00:00 2001 +From: Ajay Neeli +Date: Wed, 24 Dec 2025 11:09:50 +0530 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: amd-versal2: Fix PHY initialization + in HCE enable notify + +Move the PHY initialization from PRE_CHANGE to POST_CHANGE in the +ufs_versal2_hce_enable_notify() callback. This ensures that the PHY is +initialized after the host controller enable sequence is complete, rather +than before it starts. + +The PHY initialization requires the UFS host controller to be in a stable +enabled state to properly configure the MPHY registers. Moving this to +POST_CHANGE aligns with the expected initialization order and prevents +potential timing issues during controller startup. + +Fixes: 769b8b2ffded ("scsi: ufs: amd-versal2: Add UFS support for AMD Versal Gen 2 SoC") +Signed-off-by: Ajay Neeli +Link: https://patch.msgid.link/20251224053950.54213-1-ajay.neeli@amd.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 0444568edbf87c1da76b61c798ce0f1c1e478467) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-amd-versal2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c +index 40543db621a1..6c454ae8a9c8 100644 +--- a/drivers/ufs/host/ufs-amd-versal2.c ++++ b/drivers/ufs/host/ufs-amd-versal2.c +@@ -367,7 +367,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, + { + int ret = 0; + +- if (status == PRE_CHANGE) { ++ if (status == POST_CHANGE) { + ret = ufs_versal2_phy_init(hba); + if (ret) + dev_err(hba->dev, "Phy init failed (%d)\n", ret); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch deleted file mode 100644 index f35dbf7a0b..0000000000 --- a/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8422624a96d6035950f1902cc537f1e7d2a4c281 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:36 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: sort aliases on Milk-V - Jupiter - -Before adding more aliases, just sort them. - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-3-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index db98dbfadf00..fbba33992347 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -14,9 +14,9 @@ / { - aliases { - ethernet0 = ð0; - ethernet1 = ð1; -- serial0 = &uart0; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ serial0 = &uart0; - }; - - chosen { --- -2.53.0 - diff --git a/SPECS/linux-lts/0421-UPSTREAM-scsi-ufs-core-Convert-string-descriptor-for.patch b/SPECS/linux-lts/0421-UPSTREAM-scsi-ufs-core-Convert-string-descriptor-for.patch new file mode 100644 index 0000000000..3756dee1bd --- /dev/null +++ b/SPECS/linux-lts/0421-UPSTREAM-scsi-ufs-core-Convert-string-descriptor-for.patch @@ -0,0 +1,103 @@ +From d6fa6c137f923ae7d7f34fa69ba2c2568d901363 Mon Sep 17 00:00:00 2001 +From: Bean Huo +Date: Sat, 8 Nov 2025 00:05:16 +0100 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Convert string descriptor + format macros to enum + +Convert SD_ASCII_STD and SD_RAW from boolean macros to enum values for +improved code readability. This makes ufshcd_read_string_desc() calls +self-documenting by using explicit enum values instead of true/false. + +Move the ufshcd_read_string_desc() declaration from include/ufs/ufshcd.h +to drivers/ufs/core/ufshcd-priv.h since this function is not exported. + +Co-developed-by: Bart Van Assche +Signed-off-by: Bart Van Assche +Suggested-by: Avri Altman +Signed-off-by: Bean Huo +Link: https://patch.msgid.link/20251107230518.4060231-2-beanhuo@iokpp.de +Signed-off-by: Martin K. Petersen +(cherry picked from commit 0d9a7085ec24983b5b8a4971c0eb6c756c75f1bf) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd-priv.h | 14 ++++++++++---- + drivers/ufs/core/ufshcd.c | 8 +++----- + include/ufs/ufshcd.h | 4 ---- + 3 files changed, 13 insertions(+), 13 deletions(-) + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 1f0d38aa37f9..f3eeaf45cfdb 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -80,11 +80,17 @@ int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag); + void ufshcd_release_scsi_cmd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp); + +-#define SD_ASCII_STD true +-#define SD_RAW false +-int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, +- u8 **buf, bool ascii); ++/** ++ * enum ufs_descr_fmt - UFS string descriptor format ++ * @SD_RAW: Raw UTF-16 format ++ * @SD_ASCII_STD: Convert to null-terminated ASCII string ++ */ ++enum ufs_descr_fmt { ++ SD_RAW = 0, ++ SD_ASCII_STD = 1, ++}; + ++int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, u8 **buf, enum ufs_descr_fmt fmt); + int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); + int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); + +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 5371f173e28b..eaced632623f 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -3773,16 +3773,14 @@ static inline char ufshcd_remove_non_printable(u8 ch) + * @desc_index: descriptor index + * @buf: pointer to buffer where descriptor would be read, + * the caller should free the memory. +- * @ascii: if true convert from unicode to ascii characters +- * null terminated string. ++ * @fmt: if %SD_ASCII_STD, convert from UTF-16 to ASCII + * + * Return: + * * string size on success. + * * -ENOMEM: on allocation failure + * * -EINVAL: on a wrong parameter + */ +-int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, +- u8 **buf, bool ascii) ++int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, u8 **buf, enum ufs_descr_fmt fmt) + { + struct uc_string_id *uc_str; + u8 *str; +@@ -3811,7 +3809,7 @@ int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, + goto out; + } + +- if (ascii) { ++ if (fmt == SD_ASCII_STD) { + ssize_t ascii_len; + int i; + /* remove header and divide by 2 to move from UTF16 to UTF8 */ +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 17fe07dac6a7..a829db551080 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1433,10 +1433,6 @@ static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) + void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); + void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, + const struct ufs_dev_quirk *fixups); +-#define SD_ASCII_STD true +-#define SD_RAW false +-int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, +- u8 **buf, bool ascii); + + void ufshcd_hold(struct ufs_hba *hba); + void ufshcd_release(struct ufs_hba *hba); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch deleted file mode 100644 index ebf0663617..0000000000 --- a/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 72311926929a84047a95c07cdcaf0f7211764d88 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:37 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V - Jupiter - -The Milk-V Jupiter board has a connector for an eMMC module. Add an -entry for it in the device tree and alias it mmc0. - -Mark the device as non-removable as eMMC modules have no CD pin and are -not supposed to be inserted or removed while the system is running. On -systems without an eMMC module installed, the kernel emits the following -informational message during boot: - -mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA -mmc0: Failed to initialize a non-removable card - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-4-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index fbba33992347..1a833e716cb6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -16,6 +16,7 @@ aliases { - ethernet1 = ð1; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; - serial0 = &uart0; - }; - -@@ -105,6 +106,16 @@ &combo_phy { - status = "okay"; - }; - -+&emmc { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0422-UPSTREAM-scsi-ufs-core-Add-OP-TEE-based-RPMB-driver-.patch b/SPECS/linux-lts/0422-UPSTREAM-scsi-ufs-core-Add-OP-TEE-based-RPMB-driver-.patch new file mode 100644 index 0000000000..41feb06ad3 --- /dev/null +++ b/SPECS/linux-lts/0422-UPSTREAM-scsi-ufs-core-Add-OP-TEE-based-RPMB-driver-.patch @@ -0,0 +1,562 @@ +From e5be2897e232f2c9cf7bfd60fc7f251f27659db4 Mon Sep 17 00:00:00 2001 +From: Bean Huo +Date: Sat, 8 Nov 2025 00:05:18 +0100 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add OP-TEE based RPMB driver + for UFS devices + +Add OP-TEE based RPMB support for UFS devices. This enables secure RPMB +operations on UFS devices through OP-TEE, providing the same +functionality available for eMMC devices and extending kernel-based +secure storage support to UFS-based systems. + +Benefits of OP-TEE based RPMB implementation: + + - Eliminates dependency on userspace supplicant for RPMB access + + - Enables early boot secure storage access (e.g., fTPM, secure UEFI + variables) + + - Provides kernel-level RPMB access as soon as UFS driver is + initialized + + - Removes complex initramfs dependencies and boot ordering requirements + + - Ensures reliable and deterministic secure storage operations + + - Supports both built-in and modular fTPM configurations + +[mkp: make this build as a module] + +Co-developed-by: Can Guo +Signed-off-by: Can Guo +Reviewed-by: Avri Altman +Reviewed-by: Bart Van Assche +Signed-off-by: Bean Huo +Link: https://patch.msgid.link/20251107230518.4060231-4-beanhuo@iokpp.de +Signed-off-by: Martin K. Petersen +(cherry picked from commit b06b8c421485e0e96d7fd6aa614fb0b6f2778a03) +Signed-off-by: Han Gao +--- + drivers/misc/Kconfig | 2 +- + drivers/ufs/core/Makefile | 1 + + drivers/ufs/core/ufs-rpmb.c | 254 +++++++++++++++++++++++++++++++++ + drivers/ufs/core/ufshcd-priv.h | 13 ++ + drivers/ufs/core/ufshcd.c | 86 ++++++++++- + include/ufs/ufs.h | 5 + + include/ufs/ufshcd.h | 7 +- + 7 files changed, 361 insertions(+), 7 deletions(-) + create mode 100644 drivers/ufs/core/ufs-rpmb.c + +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index b9c11f67315f..9d1de68dee27 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -106,7 +106,7 @@ config PHANTOM + + config RPMB + tristate "RPMB partition interface" +- depends on MMC ++ depends on MMC || SCSI_UFSHCD + help + Unified RPMB unit interface for RPMB capable devices such as eMMC and + UFS. Provides interface for in-kernel security controllers to access +diff --git a/drivers/ufs/core/Makefile b/drivers/ufs/core/Makefile +index cf820fa09a04..51e1867e524e 100644 +--- a/drivers/ufs/core/Makefile ++++ b/drivers/ufs/core/Makefile +@@ -2,6 +2,7 @@ + + obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o + ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ++ufshcd-core-$(CONFIG_RPMB) += ufs-rpmb.o + ufshcd-core-$(CONFIG_DEBUG_FS) += ufs-debugfs.o + ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o + ufshcd-core-$(CONFIG_SCSI_UFS_CRYPTO) += ufshcd-crypto.o +diff --git a/drivers/ufs/core/ufs-rpmb.c b/drivers/ufs/core/ufs-rpmb.c +new file mode 100644 +index 000000000000..ffad049872b9 +--- /dev/null ++++ b/drivers/ufs/core/ufs-rpmb.c +@@ -0,0 +1,254 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * UFS OP-TEE based RPMB Driver ++ * ++ * Copyright (C) 2025 Micron Technology, Inc. ++ * Copyright (C) 2025 Qualcomm Technologies, Inc. ++ * ++ * Authors: ++ * Bean Huo ++ * Can Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ufshcd-priv.h" ++ ++#define UFS_RPMB_SEC_PROTOCOL 0xEC /* JEDEC UFS application */ ++#define UFS_RPMB_SEC_PROTOCOL_ID 0x01 /* JEDEC UFS RPMB protocol ID, CDB byte3 */ ++ ++static const struct bus_type ufs_rpmb_bus_type = { ++ .name = "ufs_rpmb", ++}; ++ ++/* UFS RPMB device structure */ ++struct ufs_rpmb_dev { ++ u8 region_id; ++ struct device dev; ++ struct rpmb_dev *rdev; ++ struct ufs_hba *hba; ++ struct list_head node; ++}; ++ ++static int ufs_sec_submit(struct ufs_hba *hba, u16 spsp, void *buffer, size_t len, bool send) ++{ ++ struct scsi_device *sdev = hba->ufs_rpmb_wlun; ++ u8 cdb[12] = { }; ++ ++ cdb[0] = send ? SECURITY_PROTOCOL_OUT : SECURITY_PROTOCOL_IN; ++ cdb[1] = UFS_RPMB_SEC_PROTOCOL; ++ put_unaligned_be16(spsp, &cdb[2]); ++ put_unaligned_be32(len, &cdb[6]); ++ ++ return scsi_execute_cmd(sdev, cdb, send ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN, ++ buffer, len, /*timeout=*/30 * HZ, 0, NULL); ++} ++ ++/* UFS RPMB route frames implementation */ ++static int ufs_rpmb_route_frames(struct device *dev, u8 *req, unsigned int req_len, u8 *resp, ++ unsigned int resp_len) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb = dev_get_drvdata(dev); ++ struct rpmb_frame *frm_out = (struct rpmb_frame *)req; ++ bool need_result_read = true; ++ u16 req_type, protocol_id; ++ struct ufs_hba *hba; ++ int ret; ++ ++ if (!ufs_rpmb) { ++ dev_err(dev, "Missing driver data\n"); ++ return -ENODEV; ++ } ++ ++ hba = ufs_rpmb->hba; ++ ++ req_type = be16_to_cpu(frm_out->req_resp); ++ ++ switch (req_type) { ++ case RPMB_PROGRAM_KEY: ++ if (req_len != sizeof(struct rpmb_frame) || resp_len != sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ break; ++ case RPMB_GET_WRITE_COUNTER: ++ if (req_len != sizeof(struct rpmb_frame) || resp_len != sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ need_result_read = false; ++ break; ++ case RPMB_WRITE_DATA: ++ if (req_len % sizeof(struct rpmb_frame) || resp_len != sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ break; ++ case RPMB_READ_DATA: ++ if (req_len != sizeof(struct rpmb_frame) || resp_len % sizeof(struct rpmb_frame)) ++ return -EINVAL; ++ need_result_read = false; ++ break; ++ default: ++ dev_err(dev, "Unknown request type=0x%04x\n", req_type); ++ return -EINVAL; ++ } ++ ++ protocol_id = ufs_rpmb->region_id << 8 | UFS_RPMB_SEC_PROTOCOL_ID; ++ ++ ret = ufs_sec_submit(hba, protocol_id, req, req_len, true); ++ if (ret) { ++ dev_err(dev, "Command failed with ret=%d\n", ret); ++ return ret; ++ } ++ ++ if (need_result_read) { ++ struct rpmb_frame *frm_resp = (struct rpmb_frame *)resp; ++ ++ memset(frm_resp, 0, sizeof(*frm_resp)); ++ frm_resp->req_resp = cpu_to_be16(RPMB_RESULT_READ); ++ ret = ufs_sec_submit(hba, protocol_id, resp, resp_len, true); ++ if (ret) { ++ dev_err(dev, "Result read request failed with ret=%d\n", ret); ++ return ret; ++ } ++ } ++ ++ if (!ret) { ++ ret = ufs_sec_submit(hba, protocol_id, resp, resp_len, false); ++ if (ret) ++ dev_err(dev, "Response read failed with ret=%d\n", ret); ++ } ++ ++ return ret; ++} ++ ++static void ufs_rpmb_device_release(struct device *dev) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb = dev_get_drvdata(dev); ++ ++ rpmb_dev_unregister(ufs_rpmb->rdev); ++} ++ ++/* UFS RPMB device registration */ ++int ufs_rpmb_probe(struct ufs_hba *hba) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb, *it, *tmp; ++ struct rpmb_dev *rdev; ++ char *cid = NULL; ++ int region; ++ u32 cap; ++ int ret; ++ ++ if (!hba->ufs_rpmb_wlun || hba->dev_info.b_advanced_rpmb_en) { ++ dev_info(hba->dev, "Skip OP-TEE RPMB registration\n"); ++ return -ENODEV; ++ } ++ ++ /* Check if device_id is available */ ++ if (!hba->dev_info.device_id) { ++ dev_err(hba->dev, "UFS Device ID not available\n"); ++ return -EINVAL; ++ } ++ ++ INIT_LIST_HEAD(&hba->rpmbs); ++ ++ struct rpmb_descr descr = { ++ .type = RPMB_TYPE_UFS, ++ .route_frames = ufs_rpmb_route_frames, ++ .reliable_wr_count = hba->dev_info.rpmb_io_size, ++ }; ++ ++ for (region = 0; region < ARRAY_SIZE(hba->dev_info.rpmb_region_size); region++) { ++ cap = hba->dev_info.rpmb_region_size[region]; ++ if (!cap) ++ continue; ++ ++ ufs_rpmb = devm_kzalloc(hba->dev, sizeof(*ufs_rpmb), GFP_KERNEL); ++ if (!ufs_rpmb) { ++ ret = -ENOMEM; ++ goto err_out; ++ } ++ ++ ufs_rpmb->hba = hba; ++ ufs_rpmb->dev.parent = &hba->ufs_rpmb_wlun->sdev_gendev; ++ ufs_rpmb->dev.bus = &ufs_rpmb_bus_type; ++ ufs_rpmb->dev.release = ufs_rpmb_device_release; ++ dev_set_name(&ufs_rpmb->dev, "ufs_rpmb%d", region); ++ ++ /* Set driver data BEFORE device_register */ ++ dev_set_drvdata(&ufs_rpmb->dev, ufs_rpmb); ++ ++ ret = device_register(&ufs_rpmb->dev); ++ if (ret) { ++ dev_err(hba->dev, "Failed to register UFS RPMB device %d\n", region); ++ put_device(&ufs_rpmb->dev); ++ goto err_out; ++ } ++ ++ /* Create unique ID by appending region number to device_id */ ++ cid = kasprintf(GFP_KERNEL, "%s-R%d", hba->dev_info.device_id, region); ++ if (!cid) { ++ device_unregister(&ufs_rpmb->dev); ++ ret = -ENOMEM; ++ goto err_out; ++ } ++ ++ descr.dev_id = cid; ++ descr.dev_id_len = strlen(cid); ++ descr.capacity = cap; ++ ++ /* Register RPMB device */ ++ rdev = rpmb_dev_register(&ufs_rpmb->dev, &descr); ++ if (IS_ERR(rdev)) { ++ dev_err(hba->dev, "Failed to register UFS RPMB device.\n"); ++ device_unregister(&ufs_rpmb->dev); ++ ret = PTR_ERR(rdev); ++ goto err_out; ++ } ++ ++ kfree(cid); ++ cid = NULL; ++ ++ ufs_rpmb->rdev = rdev; ++ ufs_rpmb->region_id = region; ++ ++ list_add_tail(&ufs_rpmb->node, &hba->rpmbs); ++ ++ dev_info(hba->dev, "UFS RPMB region %d registered (capacity=%u)\n", region, cap); ++ } ++ ++ return 0; ++err_out: ++ kfree(cid); ++ list_for_each_entry_safe(it, tmp, &hba->rpmbs, node) { ++ list_del(&it->node); ++ device_unregister(&it->dev); ++ } ++ ++ return ret; ++} ++ ++/* UFS RPMB remove handler */ ++void ufs_rpmb_remove(struct ufs_hba *hba) ++{ ++ struct ufs_rpmb_dev *ufs_rpmb, *tmp; ++ ++ if (list_empty(&hba->rpmbs)) ++ return; ++ ++ /* Remove all registered RPMB devices */ ++ list_for_each_entry_safe(ufs_rpmb, tmp, &hba->rpmbs, node) { ++ dev_info(hba->dev, "Removing UFS RPMB region %d\n", ufs_rpmb->region_id); ++ /* Remove from list first */ ++ list_del(&ufs_rpmb->node); ++ /* Unregister device */ ++ device_unregister(&ufs_rpmb->dev); ++ } ++ ++ dev_info(hba->dev, "All UFS RPMB devices unregistered\n"); ++} ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("OP-TEE UFS RPMB driver"); +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index f3eeaf45cfdb..3ccbbdb18a24 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -419,4 +419,17 @@ static inline u32 ufshcd_mcq_get_sq_head_slot(struct ufs_hw_queue *q) + return val / sizeof(struct utp_transfer_req_desc); + } + ++#if IS_ENABLED(CONFIG_RPMB) ++int ufs_rpmb_probe(struct ufs_hba *hba); ++void ufs_rpmb_remove(struct ufs_hba *hba); ++#else ++static inline int ufs_rpmb_probe(struct ufs_hba *hba) ++{ ++ return 0; ++} ++static inline void ufs_rpmb_remove(struct ufs_hba *hba) ++{ ++} ++#endif ++ + #endif /* _UFSHCD_PRIV_H_ */ +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index eaced632623f..707f3243dda3 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -5243,10 +5243,15 @@ static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) + desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) + hba->dev_info.is_lu_power_on_wp = true; + +- /* In case of RPMB LU, check if advanced RPMB mode is enabled */ +- if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && +- desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) +- hba->dev_info.b_advanced_rpmb_en = true; ++ /* In case of RPMB LU, check if advanced RPMB mode is enabled, and get region size */ ++ if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN) { ++ if (desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) ++ hba->dev_info.b_advanced_rpmb_en = true; ++ hba->dev_info.rpmb_region_size[0] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION0_SIZE]; ++ hba->dev_info.rpmb_region_size[1] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION1_SIZE]; ++ hba->dev_info.rpmb_region_size[2] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION2_SIZE]; ++ hba->dev_info.rpmb_region_size[3] = desc_buf[RPMB_UNIT_DESC_PARAM_REGION3_SIZE]; ++ } + + + kfree(desc_buf); +@@ -8206,8 +8211,11 @@ static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) + ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); + if (IS_ERR(sdev_rpmb)) { + ret = PTR_ERR(sdev_rpmb); ++ hba->ufs_rpmb_wlun = NULL; ++ dev_err(hba->dev, "%s: RPMB WLUN not found\n", __func__); + goto remove_ufs_device_wlun; + } ++ hba->ufs_rpmb_wlun = sdev_rpmb; + ufshcd_blk_pm_runtime_init(sdev_rpmb); + scsi_device_put(sdev_rpmb); + +@@ -8475,6 +8483,67 @@ static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) + dev_info->rtc_update_period = 0; + } + ++/** ++ * ufshcd_create_device_id - Generate unique device identifier string ++ * @hba: per-adapter instance ++ * @desc_buf: device descriptor buffer ++ * ++ * Creates a unique device ID string combining manufacturer ID, spec version, ++ * model name, serial number (as hex), device version, and manufacture date. ++ * ++ * Returns: Allocated device ID string on success, NULL on failure ++ */ ++static char *ufshcd_create_device_id(struct ufs_hba *hba, u8 *desc_buf) ++{ ++ struct ufs_dev_info *dev_info = &hba->dev_info; ++ u16 manufacture_date; ++ u16 device_version; ++ u8 *serial_number; ++ char *serial_hex; ++ char *device_id; ++ u8 serial_index; ++ int serial_len; ++ int ret; ++ ++ serial_index = desc_buf[DEVICE_DESC_PARAM_SN]; ++ ++ ret = ufshcd_read_string_desc(hba, serial_index, &serial_number, SD_RAW); ++ if (ret < 0) { ++ dev_err(hba->dev, "Failed reading Serial Number. err = %d\n", ret); ++ return NULL; ++ } ++ ++ device_version = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_DEV_VER]); ++ manufacture_date = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_MANF_DATE]); ++ ++ serial_len = ret; ++ /* Allocate buffer for hex string: 2 chars per byte + null terminator */ ++ serial_hex = kzalloc(serial_len * 2 + 1, GFP_KERNEL); ++ if (!serial_hex) { ++ kfree(serial_number); ++ return NULL; ++ } ++ ++ bin2hex(serial_hex, serial_number, serial_len); ++ ++ /* ++ * Device ID format is ABI with secure world - do not change without firmware ++ * coordination. ++ */ ++ device_id = kasprintf(GFP_KERNEL, "%04X-%04X-%s-%s-%04X-%04X", ++ dev_info->wmanufacturerid, dev_info->wspecversion, ++ dev_info->model, serial_hex, device_version, ++ manufacture_date); ++ ++ kfree(serial_hex); ++ kfree(serial_number); ++ ++ if (!device_id) ++ dev_warn(hba->dev, "Failed to allocate unique device ID\n"); ++ ++ return device_id; ++} ++ + static int ufs_get_device_desc(struct ufs_hba *hba) + { + int err; +@@ -8524,6 +8593,9 @@ static int ufs_get_device_desc(struct ufs_hba *hba) + goto out; + } + ++ /* Generate unique device ID */ ++ dev_info->device_id = ufshcd_create_device_id(hba, desc_buf); ++ + hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + + desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; + +@@ -8559,6 +8631,8 @@ static void ufs_put_device_desc(struct ufs_hba *hba) + + kfree(dev_info->model); + dev_info->model = NULL; ++ kfree(dev_info->device_id); ++ dev_info->device_id = NULL; + } + + /** +@@ -8702,6 +8776,8 @@ static int ufshcd_device_geo_params_init(struct ufs_hba *hba) + else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) + hba->dev_info.max_lu_supported = 8; + ++ hba->dev_info.rpmb_io_size = desc_buf[GEOMETRY_DESC_PARAM_RPMB_RW_SIZE]; ++ + out: + kfree(desc_buf); + return err; +@@ -8888,6 +8964,7 @@ static int ufshcd_add_lus(struct ufs_hba *hba) + + ufs_bsg_probe(hba); + scsi_scan_host(hba->host); ++ ufs_rpmb_probe(hba); + + out: + return ret; +@@ -10455,6 +10532,7 @@ void ufshcd_remove(struct ufs_hba *hba) + ufshcd_rpm_get_sync(hba); + ufs_hwmon_remove(hba); + ufs_bsg_remove(hba); ++ ufs_rpmb_remove(hba); + ufs_sysfs_remove_nodes(hba->dev); + cancel_delayed_work_sync(&hba->ufs_rtc_update_work); + blk_mq_destroy_queue(hba->tmf_queue); +diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h +index 245a6a829ce9..ab8f6c07b5a2 100644 +--- a/include/ufs/ufs.h ++++ b/include/ufs/ufs.h +@@ -651,6 +651,11 @@ struct ufs_dev_info { + u8 rtt_cap; /* bDeviceRTTCap */ + + bool hid_sup; ++ ++ /* Unique device ID string (manufacturer+model+serial+version+date) */ ++ char *device_id; ++ u8 rpmb_io_size; ++ u8 rpmb_region_size[4]; + }; + + #endif /* End of Header */ +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index a829db551080..e59e37753ad7 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -833,6 +833,7 @@ enum ufshcd_mcq_opr { + * @host: Scsi_Host instance of the driver + * @dev: device handle + * @ufs_device_wlun: WLUN that controls the entire UFS device. ++ * @ufs_rpmb_wlun: RPMB WLUN SCSI device + * @hwmon_device: device instance registered with the hwmon core. + * @curr_dev_pwr_mode: active UFS device power mode. + * @uic_link_state: active state of the link to the UFS device. +@@ -948,8 +949,8 @@ enum ufshcd_mcq_opr { + * @pm_qos_mutex: synchronizes PM QoS request and status updates + * @critical_health_count: count of critical health exceptions + * @dev_lvl_exception_count: count of device level exceptions since last reset +- * @dev_lvl_exception_id: vendor specific information about the +- * device level exception event. ++ * @dev_lvl_exception_id: vendor specific information about the device level exception event. ++ * @rpmbs: list of OP-TEE RPMB devices (one per RPMB region) + */ + struct ufs_hba { + void __iomem *mmio_base; +@@ -967,6 +968,7 @@ struct ufs_hba { + struct Scsi_Host *host; + struct device *dev; + struct scsi_device *ufs_device_wlun; ++ struct scsi_device *ufs_rpmb_wlun; + + #ifdef CONFIG_SCSI_UFS_HWMON + struct device *hwmon_device; +@@ -1124,6 +1126,7 @@ struct ufs_hba { + int critical_health_count; + atomic_t dev_lvl_exception_count; + u64 dev_lvl_exception_id; ++ struct list_head rpmbs; + }; + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch deleted file mode 100644 index 7b0fee89d3..0000000000 --- a/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 629f9f3c4e0f9cca344b52a02ceedd2e91ab9756 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:38 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable SD card support - on Milk-V Jupiter - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with pull-up -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Alias it as mmc1 - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-5-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 1a833e716cb6..beebf804197e 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -17,6 +17,7 @@ aliases { - i2c2 = &i2c2; - i2c8 = &i2c8; - mmc0 = &emmc; -+ mmc1 = &sdhci0; - serial0 = &uart0; - }; - -@@ -250,7 +251,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -385,6 +386,24 @@ uboot@a00000 { - }; - }; - -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4_3v3>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0423-UPSTREAM-scsi-ufs-host-mediatek-Correct-clock-scalin.patch b/SPECS/linux-lts/0423-UPSTREAM-scsi-ufs-host-mediatek-Correct-clock-scalin.patch new file mode 100644 index 0000000000..7d13bd32e1 --- /dev/null +++ b/SPECS/linux-lts/0423-UPSTREAM-scsi-ufs-host-mediatek-Correct-clock-scalin.patch @@ -0,0 +1,101 @@ +From ef9429eda550c8a92b95a1a698364f2bf497f3bc Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:23 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Correct clock + scaling with PM QoS flow + +Correct clock scaling with PM QoS during suspend and resume. Ensure PM +QoS is released during suspend if scaling up and re-applied after +resume. This prevents performance issues and maintains proper power +management. + +Signed-off-by: Peter Wang +Reviewed-by: Bart Van Assche +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-2-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 7162536410768ec6b219524c36d3a871ff97adf8) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd.c | 3 ++- + drivers/ufs/host/ufs-mediatek.c | 10 ++++++++++ + include/ufs/ufshcd.h | 1 + + 3 files changed, 13 insertions(+), 1 deletion(-) + +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 707f3243dda3..80c504e270b6 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -1076,7 +1076,7 @@ void ufshcd_pm_qos_exit(struct ufs_hba *hba) + * @hba: per adapter instance + * @on: If True, vote for perf PM QoS mode otherwise power save mode + */ +-static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) ++void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) + { + guard(mutex)(&hba->pm_qos_mutex); + +@@ -1085,6 +1085,7 @@ static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) + + cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); + } ++EXPORT_SYMBOL_GPL(ufshcd_pm_qos_update); + + /** + * ufshcd_set_clk_freq - set UFS controller clock frequencies +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 3c63adca561d..27418ea618ed 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1744,6 +1744,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + { + int err; + struct arm_smccc_res res; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + if (status == PRE_CHANGE) { + if (ufshcd_is_auto_hibern8_supported(hba)) +@@ -1773,6 +1774,10 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + + ufs_mtk_sram_pwr_ctrl(false, res); + ++ /* Release pm_qos if in scale-up mode during suspend */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ ufshcd_pm_qos_update(hba, false); ++ + return 0; + fail: + /* +@@ -1788,6 +1793,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + { + int err; + struct arm_smccc_res res; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) + ufs_mtk_dev_vreg_set_lpm(hba, false); +@@ -1798,6 +1804,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + if (err) + goto fail; + ++ /* Request pm_qos if in scale-up mode after resume */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ ufshcd_pm_qos_update(hba, true); ++ + if (ufshcd_is_link_hibern8(hba)) { + err = ufs_mtk_link_set_hpm(hba); + if (err) +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index e59e37753ad7..9f2160829d80 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1488,5 +1488,6 @@ int ufshcd_write_ee_control(struct ufs_hba *hba); + int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, + const u16 *other_mask, u16 set, u16 clr); + void ufshcd_force_error_recovery(struct ufs_hba *hba); ++void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on); + + #endif /* End of Header */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch deleted file mode 100644 index c52a677920..0000000000 --- a/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 396d9a81ca85057f4a8bc7ad711b684dcffafb06 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:39 +0200 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: fix uboot partition - offset on Milk-V Jupiter - -Correct the uboot partition node name to match its actual offset. - -Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-6-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index beebf804197e..2fc8d6533786 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -379,7 +379,7 @@ env@60000 { - opensbi@70000 { - reg = <0x70000 0x30000>; - }; -- uboot@a00000 { -+ uboot@a0000 { - reg = <0xa0000 0x760000>; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0424-UPSTREAM-scsi-ufs-host-mediatek-Adjust-clock-scaling.patch b/SPECS/linux-lts/0424-UPSTREAM-scsi-ufs-host-mediatek-Adjust-clock-scaling.patch new file mode 100644 index 0000000000..9a66fd41c1 --- /dev/null +++ b/SPECS/linux-lts/0424-UPSTREAM-scsi-ufs-host-mediatek-Adjust-clock-scaling.patch @@ -0,0 +1,56 @@ +From f1d17b7a4f696ff2e0d459ce22f402103a434cde Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:24 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Adjust clock + scaling for PM flow + +Adjust clock scaling during suspend and resume in the UFS Mediatek +driver. Ensure that the clock scales down during suspend if it was +scaled up, and scales up again after resume. This adjustment maintains +proper power management. + +Signed-off-by: Peter Wang +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-3-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 55ce691dc75a356e4b7c552505ce0a427c72f3af) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 27418ea618ed..c25ca23a84cc 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1774,9 +1774,11 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + + ufs_mtk_sram_pwr_ctrl(false, res); + +- /* Release pm_qos if in scale-up mode during suspend */ +- if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ /* Release pm_qos/clk if in scale-up mode during suspend */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, false); ++ _ufs_mtk_clk_scale(hba, false); ++ } + + return 0; + fail: +@@ -1804,9 +1806,11 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + if (err) + goto fail; + +- /* Request pm_qos if in scale-up mode after resume */ +- if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) ++ /* Request pm_qos/clk if in scale-up mode after resume */ ++ if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, true); ++ _ufs_mtk_clk_scale(hba, true); ++ } + + if (ufshcd_is_link_hibern8(hba)) { + err = ufs_mtk_link_set_hpm(hba); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch b/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch deleted file mode 100644 index 3cee4760cd..0000000000 --- a/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 98c6ddea13512cec403705f0e1898daa262466b1 Mon Sep 17 00:00:00 2001 -From: Zhengyu He -Date: Thu, 21 May 2026 22:44:46 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add QSPI support for K3 - Pico-ITX - -Add K3 QSPI controller node into k3.dtsi, and add related pinmux -configuration. - -Enable QSPI on Pico-ITX board, and describe the NOR flash which wires -to it. - -Signed-off-by: Cody Kang -Signed-off-by: Zhengyu He -Link: https://lore.kernel.org/r/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-2-52bce26e5fd8@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 58 ++++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 +++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ - 3 files changed, 96 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 4486dc1fe114..61cbf924830b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -192,6 +192,64 @@ phy0: phy@1 { - }; - }; - -+&pinctrl { -+ qspi-cfg { -+ qspi-pins { -+ power-source = <1800>; -+ }; -+ -+ qspi-cs0-pins { -+ power-source = <1800>; -+ }; -+ }; -+}; -+ -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x20000>; -+ }; -+ -+ fsbl@20000 { -+ reg = <0x20000 0x80000>; -+ }; -+ -+ env@a0000 { -+ reg = <0xa0000 0x10000>; -+ }; -+ -+ esos@b0000 { -+ reg = <0xb0000 0x100000>; -+ }; -+ -+ opensbi@1b0000 { -+ reg = <0x1b0000 0x60000>; -+ }; -+ -+ uboot@210000 { -+ reg = <0x210000 0x5f0000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 252c64af76fe..dffa4d583bb2 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -646,6 +646,27 @@ pwm19-2-pins { - }; - }; - -+ /omit-if-no-ref/ -+ qspi_cfg: qspi-cfg { -+ qspi-pins { -+ pinmux = , /* qspi dat0 */ -+ , /* qspi dat1 */ -+ , /* qspi dat2 */ -+ , /* qspi dat3 */ -+ ; /* qspi clk */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ }; -+ -+ qspi-cs0-pins { -+ pinmux = ; /* qspi cs0 */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 809067d6383c..5b17612fe58e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -1069,6 +1069,23 @@ pll: clock-controller@d4090000 { - #clock-cells = <1>; - }; - -+ qspi: spi@d420c000 { -+ compatible = "spacemit,k3-qspi", -+ "spacemit,k1-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0xd420c000 0x0 0x1000>, -+ <0x0 0xb8000000 0x0 0xc00000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, -+ <&syscon_apmu CLK_APMU_QSPI>; -+ clock-names = "qspi_en", "qspi"; -+ resets = <&syscon_apmu RESET_APMU_QSPI>, -+ <&syscon_apmu RESET_APMU_QSPI_BUS>; -+ interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ - syscon_apmu: system-controller@d4282800 { - compatible = "spacemit,k3-syscon-apmu"; - reg = <0x0 0xd4282800 0x0 0x400>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0425-UPSTREAM-scsi-ufs-host-mediatek-Handle-clock-scaling.patch b/SPECS/linux-lts/0425-UPSTREAM-scsi-ufs-host-mediatek-Handle-clock-scaling.patch new file mode 100644 index 0000000000..55c43cebb7 --- /dev/null +++ b/SPECS/linux-lts/0425-UPSTREAM-scsi-ufs-host-mediatek-Handle-clock-scaling.patch @@ -0,0 +1,48 @@ +From e6b93ad394a4fa2295a2087afc9a956837475724 Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:25 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Handle clock + scaling for high gear in PM flow + +Add clock scaling down for power management flow in the UFS Mediatek +driver. If clock scaling is disabled and fixed in high gear, ensure the +clock scales down during suspend and scales up again after resume to +support high gear. This adjustment maintains proper power management. + +Signed-off-by: Peter Wang +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-4-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 16b42c4281ae536a6ceda97303d9820ac5741293) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index c25ca23a84cc..b8ef8eefa1cc 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1778,6 +1778,9 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, + if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, false); + _ufs_mtk_clk_scale(hba, false); ++ } else if ((!ufshcd_is_clkscaling_supported(hba) && ++ hba->pwr_info.gear_rx >= UFS_HS_G5)) { ++ _ufs_mtk_clk_scale(hba, false); + } + + return 0; +@@ -1810,6 +1813,9 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) + if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { + ufshcd_pm_qos_update(hba, true); + _ufs_mtk_clk_scale(hba, true); ++ } else if ((!ufshcd_is_clkscaling_supported(hba) && ++ hba->pwr_info.gear_rx >= UFS_HS_G5)) { ++ _ufs_mtk_clk_scale(hba, true); + } + + if (ufshcd_is_link_hibern8(hba)) { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch deleted file mode 100644 index 2df47fbbeb..0000000000 --- a/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 4188a3bf42259d212c5d61101e694a2dc05e3dd4 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 00:40:07 +0800 -Subject: [RUYI PATCH] FROMLIST: pinctrl: spacemit: fix NULL check in - spacemit_pin_set_config - -spacemit_pin_set_config() looks up the per-pin descriptor with -spacemit_get_pin() then checks the wrong variable for failure: - - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - ... - if (!pin) - return -EINVAL; - - reg = spacemit_pin_to_reg(pctrl, spin->pin); - -pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a -valid pin, so rejecting it here drops the PAD config write for the first -pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as -its first entry, so its drive-strength / bias configuration was silently -ignored. - -The intended guard is against spacemit_get_pin() returning NULL when the -pin id isn't in the SoC's pin table. Check spin instead, which both -restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. - -Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") -Link: https://lore.kernel.org/r/20260519164007.122574-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index f3c754f78074..f71091254382 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -795,7 +795,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, - void __iomem *reg; - unsigned int mux; - -- if (!pin) -+ if (!spin) - return -EINVAL; - - reg = spacemit_pin_to_reg(pctrl, spin->pin); --- -2.53.0 - diff --git a/SPECS/linux-lts/0426-UPSTREAM-scsi-ufs-host-mediatek-Adjust-sync-length-f.patch b/SPECS/linux-lts/0426-UPSTREAM-scsi-ufs-host-mediatek-Adjust-sync-length-f.patch new file mode 100644 index 0000000000..d4e763ff16 --- /dev/null +++ b/SPECS/linux-lts/0426-UPSTREAM-scsi-ufs-host-mediatek-Adjust-sync-length-f.patch @@ -0,0 +1,100 @@ +From a52aba3f7189c05d469edd5ef59d86ede64eacdb Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:26 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Adjust sync length + for FASTAUTO mode + +Set the sync length for FASTAUTO G1 mode in the UFS Mediatek +driver. This ensures the sync length meets minimum values for high-speed +gears, improving stability during power mode changes. + +Signed-off-by: Peter Wang +Reviewed-by: Bart Van Assche +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-5-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 1fd05367d5b1a5edd3d14c966a5f510e5b8a0c5e) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 32 ++++++++++++++++++++++++++++++++ + include/ufs/unipro.h | 7 ++++++- + 2 files changed, 38 insertions(+), 1 deletion(-) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index b8ef8eefa1cc..0f261c3afc34 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1332,6 +1332,36 @@ static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba, + return true; + } + ++static void ufs_mtk_adjust_sync_length(struct ufs_hba *hba) ++{ ++ int i; ++ u32 value; ++ u32 cnt, att, min; ++ struct attr_min { ++ u32 attr; ++ u32 min_value; ++ } pa_min_sync_length[] = { ++ {PA_TXHSG1SYNCLENGTH, 0x48}, ++ {PA_TXHSG2SYNCLENGTH, 0x48}, ++ {PA_TXHSG3SYNCLENGTH, 0x48}, ++ {PA_TXHSG4SYNCLENGTH, 0x48}, ++ {PA_TXHSG5SYNCLENGTH, 0x48} ++ }; ++ ++ cnt = sizeof(pa_min_sync_length) / sizeof(struct attr_min); ++ for (i = 0; i < cnt; i++) { ++ att = pa_min_sync_length[i].attr; ++ min = pa_min_sync_length[i].min_value; ++ ufshcd_dme_get(hba, UIC_ARG_MIB(att), &value); ++ if (value < min) ++ ufshcd_dme_set(hba, UIC_ARG_MIB(att), min); ++ ++ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(att), &value); ++ if (value < min) ++ ufshcd_dme_peer_set(hba, UIC_ARG_MIB(att), min); ++ } ++} ++ + static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, + const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) +@@ -1355,6 +1385,8 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, + } + + if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) { ++ ufs_mtk_adjust_sync_length(hba); ++ + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1); + +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index faf1c471ad30..59de737490ca 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -111,6 +111,9 @@ + #define PA_TXLINKSTARTUPHS 0x1544 + #define PA_AVAILRXDATALANES 0x1540 + #define PA_MINRXTRAILINGCLOCKS 0x1543 ++#define PA_TXHSG1SYNCLENGTH 0x1552 ++#define PA_TXHSG2SYNCLENGTH 0x1554 ++#define PA_TXHSG3SYNCLENGTH 0x1556 + #define PA_LOCAL_TX_LCC_ENABLE 0x155E + #define PA_ACTIVETXDATALANES 0x1560 + #define PA_CONNECTEDTXDATALANES 0x1561 +@@ -160,7 +163,9 @@ + #define PA_PACPFRAMECOUNT 0x15C0 + #define PA_PACPERRORCOUNT 0x15C1 + #define PA_PHYTESTCONTROL 0x15C2 +-#define PA_TXHSADAPTTYPE 0x15D4 ++#define PA_TXHSG4SYNCLENGTH 0x15D0 ++#define PA_TXHSADAPTTYPE 0x15D4 ++#define PA_TXHSG5SYNCLENGTH 0x15D6 + + /* Adpat type for PA_TXHSADAPTTYPE attribute */ + #define PA_REFRESH_ADAPT 0x00 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch b/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch deleted file mode 100644 index 950680a506..0000000000 --- a/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 2e0cced73e82d39a2fd99776f4972c20778cd27b Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 00:55:46 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: unconditionally select - ARCH_KEEP_MEMBLOCK - -Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock -to be kept after boot to initialize the secondary kernel. Device -Tree platforms also need this for kexec support. - -Link: https://lore.kernel.org/r/20260519165546.123105-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 5cc386e56d13..68faa6cf6ee0 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -56,7 +56,7 @@ config RISCV - select ARCH_HAS_UBSAN - select ARCH_HAS_VDSO_ARCH_DATA if HAVE_GENERIC_VDSO - select ARCH_HAVE_NMI_SAFE_CMPXCHG -- select ARCH_KEEP_MEMBLOCK if ACPI -+ select ARCH_KEEP_MEMBLOCK - select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU - select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX - select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT --- -2.53.0 - diff --git a/SPECS/linux-lts/0427-UPSTREAM-scsi-ufs-host-mediatek-Remove-duplicate-fun.patch b/SPECS/linux-lts/0427-UPSTREAM-scsi-ufs-host-mediatek-Remove-duplicate-fun.patch new file mode 100644 index 0000000000..99520b36e0 --- /dev/null +++ b/SPECS/linux-lts/0427-UPSTREAM-scsi-ufs-host-mediatek-Remove-duplicate-fun.patch @@ -0,0 +1,91 @@ +From 46733bb6b387ba043d987355eb2bb7fef4083ad1 Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:28 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Remove duplicate + function + +Remove the duplicate ufs_mtk_us_to_ahit() function in the UFS Mediatek +driver and export the existing ufshcd_us_to_ahit() function for shared +use. This change reduces redundancy and maintains consistency across the +codebase. + +Signed-off-by: Peter Wang +Reviewed-by: Bart Van Assche +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-7-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 9b2b03b36168bcda298546b121d6ecc530d01d25) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-sysfs.c | 3 ++- + drivers/ufs/host/ufs-mediatek.c | 14 +------------- + include/ufs/ufshcd.h | 1 + + 3 files changed, 4 insertions(+), 14 deletions(-) + +diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c +index 0086816b27cd..b33f8656edb5 100644 +--- a/drivers/ufs/core/ufs-sysfs.c ++++ b/drivers/ufs/core/ufs-sysfs.c +@@ -235,7 +235,7 @@ static int ufshcd_ahit_to_us(u32 ahit) + } + + /* Convert microseconds to Auto-Hibernate Idle Timer register value */ +-static u32 ufshcd_us_to_ahit(unsigned int timer) ++u32 ufshcd_us_to_ahit(unsigned int timer) + { + unsigned int scale; + +@@ -245,6 +245,7 @@ static u32 ufshcd_us_to_ahit(unsigned int timer) + return FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, timer) | + FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, scale); + } ++EXPORT_SYMBOL_GPL(ufshcd_us_to_ahit); + + static int ufshcd_read_hci_reg(struct ufs_hba *hba, u32 *val, unsigned int reg) + { +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 0f261c3afc34..be89cd01d920 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1109,18 +1109,6 @@ static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) + } + } + +-/* Convert microseconds to Auto-Hibernate Idle Timer register value */ +-static u32 ufs_mtk_us_to_ahit(unsigned int timer) +-{ +- unsigned int scale; +- +- for (scale = 0; timer > UFSHCI_AHIBERN8_TIMER_MASK; ++scale) +- timer /= UFSHCI_AHIBERN8_SCALE_FACTOR; +- +- return FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, timer) | +- FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, scale); +-} +- + static void ufs_mtk_fix_ahit(struct ufs_hba *hba) + { + unsigned int us; +@@ -1143,7 +1131,7 @@ static void ufs_mtk_fix_ahit(struct ufs_hba *hba) + break; + } + +- hba->ahit = ufs_mtk_us_to_ahit(us); ++ hba->ahit = ufshcd_us_to_ahit(us); + } + + ufs_mtk_setup_clk_gating(hba); +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 9f2160829d80..775a66f334a3 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1489,5 +1489,6 @@ int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, + const u16 *other_mask, u16 set, u16 clr); + void ufshcd_force_error_recovery(struct ufs_hba *hba); + void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on); ++u32 ufshcd_us_to_ahit(unsigned int timer); + + #endif /* End of Header */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch deleted file mode 100644 index c4ff341f5d..0000000000 --- a/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 3c28d26c50aa548e866a1681ca068993386a91c3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 01:06:41 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: kexec_file: Constrain segment placement - to direct map - -When kexec_file_load places segments with buf_max=ULONG_MAX and -top_down=true, they land at the highest available physical addresses. -On RISC-V the size of the linear mapping is determined by the active -VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 -extend the range substantially further. When the installed physical -memory exceeds the direct map size of the active mode, top-down -placement puts DTB/initrd at physical addresses outside the linearly -mapped region. The kexec'd kernel cannot reach them during early -boot, triggering a page fault at memcmp in start_kernel. - -Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects -the runtime direct map boundary for the active VM mode (SV39/SV48/ -SV57). This keeps all kexec segments within the linearly mapped -region while preserving the upstream top_down allocation strategy. - -Link: https://lore.kernel.org/r/20260519170641.123517-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/kernel/machine_kexec_file.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c -index dd9d92a96517..b5fe17238df2 100644 ---- a/arch/riscv/kernel/machine_kexec_file.c -+++ b/arch/riscv/kernel/machine_kexec_file.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -266,7 +267,7 @@ int load_extra_segments(struct kimage *image, unsigned long kernel_start, - - kbuf.image = image; - kbuf.buf_min = kernel_start + kernel_len; -- kbuf.buf_max = ULONG_MAX; -+ kbuf.buf_max = PFN_PHYS(max_low_pfn); - - #ifdef CONFIG_CRASH_DUMP - /* Add elfcorehdr */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0428-UPSTREAM-scsi-ufs-host-mediatek-Add-support-for-new-.patch b/SPECS/linux-lts/0428-UPSTREAM-scsi-ufs-host-mediatek-Add-support-for-new-.patch new file mode 100644 index 0000000000..163393188f --- /dev/null +++ b/SPECS/linux-lts/0428-UPSTREAM-scsi-ufs-host-mediatek-Add-support-for-new-.patch @@ -0,0 +1,142 @@ +From bf61c88d6f9960d674232aef5b2e3003d6b62dd0 Mon Sep 17 00:00:00 2001 +From: Peter Wang +Date: Wed, 24 Sep 2025 17:43:29 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Add support for new + platform with MMIO_OTSD_CTR + +Introduce support for a new UFS Mediatek platform by adding the +REG_UFS_UFS_MMIO_OTSD_CTRL register. This update includes checks for +legacy platforms and uses the new register to replace debug selection +and handle specific operations. The changes ensure compatibility across +different hardware versions and prevent potential issues with debug +usage on newer platforms. + +Additional updates include error logging improvements during link setup +for newer and legacy platforms, ensuring proper event logging and +debugging. + +Signed-off-by: Peter Wang +Acked-by: Chun-Hung Wu +Link: https://patch.msgid.link/20250924094527.2992256-8-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 4fb4c835a92b6dfa3a461102ba0943b416ae7e55) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 42 +++++++++++++++++++++++++++------ + drivers/ufs/host/ufs-mediatek.h | 1 + + 2 files changed, 36 insertions(+), 7 deletions(-) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index be89cd01d920..074c988c4e3f 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -280,6 +280,9 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, + ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, + REG_UFS_XOUFS_CTRL); + ++ if (host->legacy_ip_ver) ++ return 0; ++ + /* DDR_EN setting */ + if (host->ip_ver >= IP_VER_MT6989) { + ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8), +@@ -405,7 +408,7 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba) + { + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + +- if (((host->ip_ver >> 16) & 0xFF) >= 0x36) { ++ if (!host->legacy_ip_ver && host->ip_ver >= IP_VER_MT6983) { + ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL); + ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0); + ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1); +@@ -422,6 +425,7 @@ static int ufs_mtk_wait_idle_state(struct ufs_hba *hba, + u64 timeout, time_checked; + u32 val, sm; + bool wait_idle; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + /* cannot use plain ktime_get() in suspend */ + timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL; +@@ -432,8 +436,13 @@ static int ufs_mtk_wait_idle_state(struct ufs_hba *hba, + + do { + time_checked = ktime_get_mono_fast_ns(); +- ufs_mtk_dbg_sel(hba); +- val = ufshcd_readl(hba, REG_UFS_PROBE); ++ if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { ++ ufs_mtk_dbg_sel(hba); ++ val = ufshcd_readl(hba, REG_UFS_PROBE); ++ } else { ++ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); ++ val = val >> 16; ++ } + + sm = val & 0x1f; + +@@ -465,13 +474,20 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state, + { + ktime_t timeout, time_checked; + u32 val; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + timeout = ktime_add_ms(ktime_get(), max_wait_ms); + do { + time_checked = ktime_get(); +- ufs_mtk_dbg_sel(hba); +- val = ufshcd_readl(hba, REG_UFS_PROBE); +- val = val >> 28; ++ ++ if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { ++ ufs_mtk_dbg_sel(hba); ++ val = ufshcd_readl(hba, REG_UFS_PROBE); ++ val = val >> 28; ++ } else { ++ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); ++ val = val >> 24; ++ } + + if (val == state) + return 0; +@@ -1639,14 +1655,26 @@ static int ufs_mtk_device_reset(struct ufs_hba *hba) + static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) + { + int err; ++ u32 val; ++ struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + err = ufshcd_hba_enable(hba); + if (err) + return err; + + err = ufs_mtk_unipro_set_lpm(hba, false); +- if (err) ++ if (err) { ++ if (host->ip_ver < IP_VER_MT6899) { ++ ufs_mtk_dbg_sel(hba); ++ val = ufshcd_readl(hba, REG_UFS_PROBE); ++ } else { ++ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); ++ } ++ ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val); ++ val = ufshcd_readl(hba, REG_INTERRUPT_STATUS); ++ ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)val); + return err; ++ } + + err = ufshcd_uic_hibern8_exit(hba); + if (err) +diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h +index dfbf78bd8664..f96fd032371d 100644 +--- a/drivers/ufs/host/ufs-mediatek.h ++++ b/drivers/ufs/host/ufs-mediatek.h +@@ -28,6 +28,7 @@ + */ + #define REG_UFS_XOUFS_CTRL 0x140 + #define REG_UFS_REFCLK_CTRL 0x144 ++#define REG_UFS_UFS_MMIO_OTSD_CTRL 0x14C + #define REG_UFS_MMIO_OPT_CTRL_0 0x160 + #define REG_UFS_EXTREG 0x2100 + #define REG_UFS_MPHYCTRL 0x2200 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch deleted file mode 100644 index 35f6ab7227..0000000000 --- a/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 66203a4e0eefa5812e80d8953dd2e958bbeaa89b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 20 May 2026 23:45:27 +0000 -Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: spacemit: Add K3 - CoM260-IFX board -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module -with a reference carrier board. - -The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD -card slot and includes interfaces such as dual MIPI CSI-2 connectors, -M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin -expansion header. - -The carrier board is intended as a general-purpose development platform -for CoM260 module and exposes interfaces for all of storage, display, -networking, and camera connectivity. - -Acked-by: Conor Dooley -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml -index eca403a8e49e..5273d5bdfc4e 100644 ---- a/Documentation/devicetree/bindings/riscv/spacemit.yaml -+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml -@@ -29,6 +29,11 @@ properties: - - enum: - - spacemit,k3-pico-itx - - const: spacemit,k3 -+ - items: -+ - enum: -+ - spacemit,k3-com260-ifx -+ - const: spacemit,k3-com260 -+ - const: spacemit,k3 - - additionalProperties: true - --- -2.53.0 - diff --git a/SPECS/linux-lts/0429-UPSTREAM-scsi-ufs-host-mediatek-Support-new-features.patch b/SPECS/linux-lts/0429-UPSTREAM-scsi-ufs-host-mediatek-Support-new-features.patch new file mode 100644 index 0000000000..cf6f271c0b --- /dev/null +++ b/SPECS/linux-lts/0429-UPSTREAM-scsi-ufs-host-mediatek-Support-new-features.patch @@ -0,0 +1,61 @@ +From ed665f9af9b48c83b5432971d4b31aa92b19d18d Mon Sep 17 00:00:00 2001 +From: Naomi Chu +Date: Wed, 24 Sep 2025 17:43:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: host: mediatek: Support new + features for MT6991 + +Add support for the MT6991 platform by enabling MRTT settings and random +performance improvements. These enhancements aim to optimize performance +and efficiency on the MT6991 hardware. + +Enable multi-Round Trip Time (MRTT) for improved data handling. Enable +random performance improvement features to boost overall system +responsiveness. + +Signed-off-by: Naomi Chu +Reviewed-by: Peter Wang +Acked-by: Chun-Hung Wu +Signed-off-by: Peter Wang +Link: https://patch.msgid.link/20250924094527.2992256-9-peter.wang@mediatek.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 9ce37e94c30090d26df26b1bbb2fa9c51ede7651) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-mediatek.c | 6 ++++++ + drivers/ufs/host/ufs-mediatek.h | 3 +++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index 074c988c4e3f..a0de39274036 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -289,6 +289,12 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, + 0x453000, REG_UFS_MMIO_OPT_CTRL_0); + } + ++ if (host->ip_ver >= IP_VER_MT6991_A0) { ++ /* Enable multi-rtt */ ++ ufshcd_rmwl(hba, MRTT_EN, MRTT_EN, REG_UFS_MMIO_OPT_CTRL_0); ++ /* Enable random performance improvement */ ++ ufshcd_rmwl(hba, RDN_PFM_IMPV_DIS, 0, REG_UFS_MMIO_OPT_CTRL_0); ++ } + } + + return 0; +diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h +index f96fd032371d..9747277f11e8 100644 +--- a/drivers/ufs/host/ufs-mediatek.h ++++ b/drivers/ufs/host/ufs-mediatek.h +@@ -20,6 +20,9 @@ + #define MCQ_MULTI_INTR_EN BIT(2) + #define MCQ_CMB_INTR_EN BIT(3) + #define MCQ_AH8 BIT(4) ++#define MON_EN BIT(5) ++#define MRTT_EN BIT(25) ++#define RDN_PFM_IMPV_DIS BIT(28) + + #define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN) + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch deleted file mode 100644 index 30fcfb32cb..0000000000 --- a/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch +++ /dev/null @@ -1,306 +0,0 @@ -From 204ddf86a80e19378811ebf324fd4e8474fa0834 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 20 May 2026 23:45:28 +0000 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Initial support for - CoM260-IFX board - -The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer -module with a carrier board. The module integrates the K3 SoC, LPDDR5, -UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers -a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, -DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. - -Add initial support for enabling Serial UART and ethernet. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/Makefile | 1 + - .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ - arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ - 4 files changed, 245 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts - create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile -index 7e2b87702571..bf233ec0683b 100644 ---- a/arch/riscv/boot/dts/spacemit/Makefile -+++ b/arch/riscv/boot/dts/spacemit/Makefile -@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb -+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb -diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts -new file mode 100644 -index 000000000000..238bb03d0e9e ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Yixun Lan -+ */ -+ -+#include "k3-com260.dtsi" -+ -+/ { -+ model = "SpacemiT K3 CoM260 IFX"; -+ compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = ð1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi -new file mode 100644 -index 000000000000..a38d7b738258 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi -@@ -0,0 +1,190 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Yixun Lan -+ */ -+#include -+ -+#include "k3.dtsi" -+#include "k3-pinctrl.dtsi" -+ -+/ { -+ model = "SpacemiT K3 CoM260 Module"; -+ compatible = "spacemit,k3-com260", "spacemit,k3"; -+ -+ memory@100000000 { -+ device_type = "memory"; -+ reg = <0x1 0x00000000 0x4 0x00000000>; -+ }; -+ -+ reg_5v_sys: regulator-5v-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "P5V0_SYS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -+ vin1-supply = <®_5v_sys>; -+ vin2-supply = <®_5v_sys>; -+ vin3-supply = <®_5v_sys>; -+ vin4-supply = <®_5v_sys>; -+ vin5-supply = <®_5v_sys>; -+ vin6-supply = <®_5v_sys>; -+ aldoin-supply = <®_5v_sys>; -+ dldoin1-supply = <&buck4>; -+ dldoin2-supply = <&buck4>; -+ -+ regulators { -+ buck1: buck1 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2: buck2 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3: buck3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4: buck4 { -+ regulator-min-microvolt = <2100000>; -+ regulator-max-microvolt = <2100000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6: buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <500000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo2: aldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo3: aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4: aldo4 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo1: dldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo2: dldo2 { -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo3: dldo3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo4: dldo4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ dldo5: dldo5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo6: dldo6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo7: dldo7 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+}; -+ -+ð1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy1>; -+ status = "okay"; -+ -+ mdio { -+ phy1: phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <10000>; -+ }; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_0_cfg>; -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index dffa4d583bb2..846d5e8cc783 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -45,6 +45,39 @@ gmac0-phy-0-pins { - }; - }; - -+ gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { -+ gmac1-rgmii-0-pins { -+ pinmux = , /* gmac1_rxdv */ -+ , /* gmac1 rx d0 */ -+ , /* gmac1 rx d1 */ -+ , /* gmac1 rx_clk */ -+ , /* gmac1 rx d2 */ -+ , /* gmac1 rx d3 */ -+ , /* gmac1 tx d0 */ -+ , /* gmac1 tx d1 */ -+ , /* gmac1 tx clk */ -+ , /* gmac1 tx d2 */ -+ , /* gmac1 tx d3 */ -+ , /* gmac1 tx_en */ -+ , /* gmac1 mdc */ -+ ; /* gmac1 mdio */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ gmac1_phy_0_cfg: gmac1-phy-0-cfg { -+ gmac1-phy-0-pins { -+ pinmux = ; /* gmac1 int */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ - /omit-if-no-ref/ - i2c8_cfg: i2c8-cfg { - i2c8-pins { --- -2.53.0 - diff --git a/SPECS/linux-lts/0430-UPSTREAM-scsi-ufs-core-Introduce-a-new-ufshcd-vops-n.patch b/SPECS/linux-lts/0430-UPSTREAM-scsi-ufs-core-Introduce-a-new-ufshcd-vops-n.patch new file mode 100644 index 0000000000..a9ddcdf9eb --- /dev/null +++ b/SPECS/linux-lts/0430-UPSTREAM-scsi-ufs-core-Introduce-a-new-ufshcd-vops-n.patch @@ -0,0 +1,583 @@ +From d68daa72d4d5317e8a3494174341147459848a9f Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:43 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Introduce a new ufshcd vops + negotiate_pwr_mode() + +Most vendor specific implemenations of vops pwr_change_notify(PRE_CHANGE) +are fulfilling two things at once: + + - Vendor specific target power mode negotiation + + - Vendor specific power mode change preparation + +When TX Equalization is added into consideration, before power mode change +to a target power mode, TX Equalization Training (EQTR) needs be done for +that target power mode. In addition, UFSHCI spec requires to start TX EQTR +from HS-G1 (the most reliable High Speed Gear). + +Adding TX EQTR before pwr_change_notify(PRE_CHANGE) is not applicable +because we don't know the negotiated power mode yet. + +Adding TX EQTR post pwr_change_notify(PRE_CHANGE) is inappropriate because +pwr_change_notify(PRE_CHANGE) has finished preparation for a power mode +change to negotiated power mode, yet we are changing power mode to HS-G1 +for TX EQTR. + +Add a new vops negotiate_pwr_mode() so that vendor specific power mode +negotiation can be fulfilled in its vendor specific implementations. Later +on, TX EQTR can be added post vops negotiate_pwr_mode() and before vops +pwr_change_notify(PRE_CHANGE). + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-2-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit d3eba21c71708746672587f1de2cc33e6a10d61a) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd-priv.h | 14 +++++- + drivers/ufs/core/ufshcd.c | 70 ++++++++++++++++++++++++------ + drivers/ufs/host/ufs-amd-versal2.c | 3 -- + drivers/ufs/host/ufs-exynos.c | 34 +++++++-------- + drivers/ufs/host/ufs-hisi.c | 23 +++++----- + drivers/ufs/host/ufs-mediatek.c | 40 ++++++++--------- + drivers/ufs/host/ufs-qcom.c | 24 +++++----- + drivers/ufs/host/ufs-sprd.c | 3 -- + drivers/ufs/host/ufshcd-pci.c | 6 +-- + include/ufs/ufshcd.h | 17 +++++--- + 10 files changed, 143 insertions(+), 91 deletions(-) + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 3ccbbdb18a24..087ebf43b09d 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -168,14 +168,24 @@ static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, + return 0; + } + ++static inline int ufshcd_vops_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ if (hba->vops && hba->vops->negotiate_pwr_mode) ++ return hba->vops->negotiate_pwr_mode(hba, dev_max_params, ++ dev_req_params); ++ ++ return -ENOTSUPP; ++} ++ + static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + if (hba->vops && hba->vops->pwr_change_notify) + return hba->vops->pwr_change_notify(hba, status, +- dev_max_params, dev_req_params); ++ dev_req_params); + + return -ENOTSUPP; + } +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 80c504e270b6..5c7b48664147 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -333,8 +333,6 @@ static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); + static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, + bool scale_up); + static irqreturn_t ufshcd_intr(int irq, void *__hba); +-static int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode); + static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); + static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); + static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, +@@ -4666,8 +4664,26 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) + return 0; + } + +-static int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++/** ++ * ufshcd_dme_change_power_mode() - UniPro DME Power Mode change sequence ++ * @hba: per-adapter instance ++ * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * ++ * This function handles the low-level DME (Device Management Entity) ++ * configuration required to transition the UFS link to a new power mode. It ++ * performs the following steps: ++ * 1. Checks if the requested mode matches the current state. ++ * 2. Sets M-PHY and UniPro attributes including Gear (PA_RXGEAR/TXGEAR), ++ * Lanes, Termination, and HS Series (PA_HSSERIES). ++ * 3. Configures default UniPro timeout values (DL_FC0, etc.) unless ++ * explicitly skipped via quirks. ++ * 4. Triggers the actual hardware mode change via ufshcd_uic_change_pwr_mode(). ++ * 5. Updates the HBA's cached power information on success. ++ * ++ * Return: 0 on success, non-zero error code on failure. ++ */ ++static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) + { + int ret; + +@@ -4751,6 +4767,34 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba, + return ret; + } + ++/** ++ * ufshcd_change_power_mode() - Change UFS Link Power Mode ++ * @hba: per-adapter instance ++ * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * ++ * This function handles the high-level sequence for changing the UFS link ++ * power mode. It triggers vendor-specific pre-change notification, ++ * executes the DME (Device Management Entity) power mode change sequence, ++ * and, upon success, triggers vendor-specific post-change notification. ++ * ++ * Return: 0 on success, non-zero error code on failure. ++ */ ++int ufshcd_change_power_mode(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ int ret; ++ ++ ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, pwr_mode); ++ ++ ret = ufshcd_dme_change_power_mode(hba, pwr_mode); ++ ++ if (!ret) ++ ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, pwr_mode); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ufshcd_change_power_mode); ++ + /** + * ufshcd_config_pwr_mode - configure a new power mode + * @hba: per-adapter instance +@@ -4764,19 +4808,17 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr final_params = { 0 }; + int ret; + +- ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, +- desired_pwr_mode, &final_params); ++ ret = ufshcd_vops_negotiate_pwr_mode(hba, desired_pwr_mode, ++ &final_params); ++ if (ret) { ++ if (ret != -ENOTSUPP) ++ dev_err(hba->dev, "Failed to negotiate power mode: %d, use desired as is\n", ++ ret); + +- if (ret) + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); ++ } + +- ret = ufshcd_change_power_mode(hba, &final_params); +- +- if (!ret) +- ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, +- &final_params); +- +- return ret; ++ return ufshcd_change_power_mode(hba, &final_params); + } + EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); + +diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c +index 6c454ae8a9c8..2154d6286817 100644 +--- a/drivers/ufs/host/ufs-amd-versal2.c ++++ b/drivers/ufs/host/ufs-amd-versal2.c +@@ -443,7 +443,6 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_ + } + + static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_versal2_host *host = ufshcd_get_variant(hba); +@@ -451,8 +450,6 @@ static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_ch + int ret = 0; + + if (status == PRE_CHANGE) { +- memcpy(dev_req_params, dev_max_params, sizeof(struct ufs_pa_layer_attr)); +- + /* If it is not a calibrated part, switch PWRMODE to SLOW_MODE */ + if (!host->attcompval0 && !host->attcompval1 && !host->ctlecompval0 && + !host->ctlecompval1) { +diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c +index 70d195179eba..3230c8ffff0b 100644 +--- a/drivers/ufs/host/ufs-exynos.c ++++ b/drivers/ufs/host/ufs-exynos.c +@@ -818,12 +818,10 @@ static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba) + } + + static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct exynos_ufs *ufs = ufshcd_get_variant(hba); + struct phy *generic_phy = ufs->phy; +- struct ufs_host_params host_params; + int ret; + + if (!dev_req_params) { +@@ -832,18 +830,6 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, + goto out; + } + +- ufshcd_init_host_params(&host_params); +- +- /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ +- host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); +- host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); +- +- ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); +- if (ret) { +- pr_err("%s: failed to determine capabilities\n", __func__); +- goto out; +- } +- + if (ufs->drv_data->pre_pwr_change) + ufs->drv_data->pre_pwr_change(ufs, dev_req_params); + +@@ -1667,17 +1653,30 @@ static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, + return ret; + } + ++static int exynos_ufs_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ ++ ufshcd_init_host_params(&host_params); ++ ++ /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ ++ host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); ++ host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); ++ ++ return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); ++} ++ + static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + int ret = 0; + + switch (status) { + case PRE_CHANGE: +- ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, +- dev_req_params); ++ ret = exynos_ufs_pre_pwr_mode(hba, dev_req_params); + break; + case POST_CHANGE: + ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); +@@ -2005,6 +2004,7 @@ static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = { + .exit = exynos_ufs_exit, + .hce_enable_notify = exynos_ufs_hce_enable_notify, + .link_startup_notify = exynos_ufs_link_startup_notify, ++ .negotiate_pwr_mode = exynos_ufs_negotiate_pwr_mode, + .pwr_change_notify = exynos_ufs_pwr_change_notify, + .setup_clocks = exynos_ufs_setup_clocks, + .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req, +diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c +index 6f2e6bf31225..993e20ac211d 100644 +--- a/drivers/ufs/host/ufs-hisi.c ++++ b/drivers/ufs/host/ufs-hisi.c +@@ -298,6 +298,17 @@ static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params) + ufshcd_init_host_params(host_params); + } + ++static int ufs_hisi_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ ++ ufs_hisi_set_dev_cap(&host_params); ++ ++ return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); ++} ++ + static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) + { + struct ufs_hisi_host *host = ufshcd_get_variant(hba); +@@ -362,10 +373,8 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) + + static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { +- struct ufs_host_params host_params; + int ret = 0; + + if (!dev_req_params) { +@@ -377,14 +386,6 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + + switch (status) { + case PRE_CHANGE: +- ufs_hisi_set_dev_cap(&host_params); +- ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); +- if (ret) { +- dev_err(hba->dev, +- "%s: failed to determine capabilities\n", __func__); +- goto out; +- } +- + ufs_hisi_pwr_change_pre_change(hba); + break; + case POST_CHANGE: +@@ -543,6 +544,7 @@ static const struct ufs_hba_variant_ops ufs_hba_hi3660_vops = { + .name = "hi3660", + .init = ufs_hi3660_init, + .link_startup_notify = ufs_hisi_link_startup_notify, ++ .negotiate_pwr_mode = ufs_hisi_negotiate_pwr_mode, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +@@ -552,6 +554,7 @@ static const struct ufs_hba_variant_ops ufs_hba_hi3670_vops = { + .name = "hi3670", + .init = ufs_hi3670_init, + .link_startup_notify = ufs_hisi_link_startup_notify, ++ .negotiate_pwr_mode = ufs_hisi_negotiate_pwr_mode, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c +index a0de39274036..49a83e074926 100644 +--- a/drivers/ufs/host/ufs-mediatek.c ++++ b/drivers/ufs/host/ufs-mediatek.c +@@ -1318,6 +1318,23 @@ static int ufs_mtk_init(struct ufs_hba *hba) + return err; + } + ++static int ufs_mtk_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ ++ ufshcd_init_host_params(&host_params); ++ host_params.hs_rx_gear = UFS_HS_G5; ++ host_params.hs_tx_gear = UFS_HS_G5; ++ ++ if (dev_max_params->pwr_rx == SLOW_MODE || ++ dev_max_params->pwr_tx == SLOW_MODE) ++ host_params.desired_working_mode = UFS_PWM_MODE; ++ ++ return ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); ++} ++ + static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba, + struct ufs_pa_layer_attr *dev_req_params) + { +@@ -1373,26 +1390,10 @@ static void ufs_mtk_adjust_sync_length(struct ufs_hba *hba) + } + + static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_mtk_host *host = ufshcd_get_variant(hba); +- struct ufs_host_params host_params; +- int ret; +- +- ufshcd_init_host_params(&host_params); +- host_params.hs_rx_gear = UFS_HS_G5; +- host_params.hs_tx_gear = UFS_HS_G5; +- +- if (dev_max_params->pwr_rx == SLOW_MODE || +- dev_max_params->pwr_tx == SLOW_MODE) +- host_params.desired_working_mode = UFS_PWM_MODE; +- +- ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); +- if (ret) { +- pr_info("%s: failed to determine capabilities\n", +- __func__); +- } ++ int ret = 0; + + if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) { + ufs_mtk_adjust_sync_length(hba); +@@ -1504,7 +1505,6 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba) + + static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status stage, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + int ret = 0; +@@ -1516,8 +1516,7 @@ static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba, + reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + ufs_mtk_auto_hibern8_disable(hba); + } +- ret = ufs_mtk_pre_pwr_change(hba, dev_max_params, +- dev_req_params); ++ ret = ufs_mtk_pre_pwr_change(hba, dev_req_params); + break; + case POST_CHANGE: + if (ufshcd_is_auto_hibern8_supported(hba)) +@@ -2321,6 +2320,7 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = { + .setup_clocks = ufs_mtk_setup_clocks, + .hce_enable_notify = ufs_mtk_hce_enable_notify, + .link_startup_notify = ufs_mtk_link_startup_notify, ++ .negotiate_pwr_mode = ufs_mtk_negotiate_pwr_mode, + .pwr_change_notify = ufs_mtk_pwr_change_notify, + .apply_dev_quirks = ufs_mtk_apply_dev_quirks, + .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks, +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index eba0e6617483..fec0ecad6be1 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -917,13 +917,21 @@ static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_l + } + } + +-static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, +- enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, +- struct ufs_pa_layer_attr *dev_req_params) ++static int ufs_qcom_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_host_params *host_params = &host->host_params; ++ ++ return ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); ++} ++ ++static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int ret = 0; + + if (!dev_req_params) { +@@ -933,13 +941,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, + + switch (status) { + case PRE_CHANGE: +- ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); +- if (ret) { +- dev_err(hba->dev, "%s: failed to determine capabilities\n", +- __func__); +- return ret; +- } +- + /* + * During UFS driver probe, always update the PHY gear to match the negotiated + * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, +@@ -2218,6 +2219,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .setup_clocks = ufs_qcom_setup_clocks, + .hce_enable_notify = ufs_qcom_hce_enable_notify, + .link_startup_notify = ufs_qcom_link_startup_notify, ++ .negotiate_pwr_mode = ufs_qcom_negotiate_pwr_mode, + .pwr_change_notify = ufs_qcom_pwr_change_notify, + .apply_dev_quirks = ufs_qcom_apply_dev_quirks, + .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, +diff --git a/drivers/ufs/host/ufs-sprd.c b/drivers/ufs/host/ufs-sprd.c +index 65bd8fb96b99..a5e8c591bead 100644 +--- a/drivers/ufs/host/ufs-sprd.c ++++ b/drivers/ufs/host/ufs-sprd.c +@@ -161,14 +161,11 @@ static int ufs_sprd_common_init(struct ufs_hba *hba) + + static int sprd_ufs_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + struct ufs_sprd_host *host = ufshcd_get_variant(hba); + + if (status == PRE_CHANGE) { +- memcpy(dev_req_params, dev_max_params, +- sizeof(struct ufs_pa_layer_attr)); + if (host->unipro_ver >= UFS_UNIPRO_VER_1_8) + ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, + PA_INITIAL_ADAPT); +diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c +index 5f65dfad1a71..8a4f2381a32e 100644 +--- a/drivers/ufs/host/ufshcd-pci.c ++++ b/drivers/ufs/host/ufshcd-pci.c +@@ -145,7 +145,7 @@ static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) + + pwr_info.lane_rx = lanes; + pwr_info.lane_tx = lanes; +- ret = ufshcd_config_pwr_mode(hba, &pwr_info); ++ ret = ufshcd_change_power_mode(hba, &pwr_info); + if (ret) + dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n", + __func__, lanes, ret); +@@ -154,17 +154,15 @@ static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) + + static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) + { + int err = 0; + + switch (status) { + case PRE_CHANGE: +- if (ufshcd_is_hs_mode(dev_max_params) && ++ if (ufshcd_is_hs_mode(dev_req_params) && + (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2)) + ufs_intel_set_lanes(hba, 2); +- memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params)); + break; + case POST_CHANGE: + if (ufshcd_is_hs_mode(dev_req_params)) { +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 775a66f334a3..eb6e8e9b6433 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -307,11 +307,10 @@ struct ufs_pwr_mode_info { + * variant specific Uni-Pro initialization. + * @link_startup_notify: called before and after Link startup is carried out + * to allow variant specific Uni-Pro initialization. ++ * @negotiate_pwr_mode: called to negotiate power mode. + * @pwr_change_notify: called before and after a power mode change + * is carried out to allow vendor spesific capabilities +- * to be set. PRE_CHANGE can modify final_params based +- * on desired_pwr_mode, but POST_CHANGE must not alter +- * the final_params parameter ++ * to be set. + * @setup_xfer_req: called before any transfer request is issued + * to set some things + * @setup_task_mgmt: called before any task management request is issued +@@ -352,10 +351,12 @@ struct ufs_hba_variant_ops { + enum ufs_notify_change_status); + int (*link_startup_notify)(struct ufs_hba *, + enum ufs_notify_change_status); +- int (*pwr_change_notify)(struct ufs_hba *, +- enum ufs_notify_change_status status, +- const struct ufs_pa_layer_attr *desired_pwr_mode, +- struct ufs_pa_layer_attr *final_params); ++ int (*negotiate_pwr_mode)(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *desired_pwr_mode, ++ struct ufs_pa_layer_attr *final_params); ++ int (*pwr_change_notify)(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *final_params); + void (*setup_xfer_req)(struct ufs_hba *hba, int tag, + bool is_scsi_cmd); + void (*setup_task_mgmt)(struct ufs_hba *, int, u8); +@@ -1370,6 +1371,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, + u8 attr_set, u32 mib_val, u8 peer); + extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer); ++extern int ufshcd_change_power_mode(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode); + extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *desired_pwr_mode); + extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch deleted file mode 100644 index 70f7cc89e9..0000000000 --- a/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 78d249e0f67dafbf778883d6990fcb4c34638969 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Wed, 20 May 2026 18:00:00 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PMIC on OrangePi - R2S - -Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and -its associated regulators to support voltage regulation on the board. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260520100000.575719-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ - 1 file changed, 134 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index 1ecc40749e5a..b13a8d6a2670 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -13,6 +13,7 @@ / { - compatible = "xunlong,orangepi-r2s", "spacemit,k1"; - - aliases { -+ i2c8 = &i2c8; - serial0 = &uart0; - ethernet0 = ð0; - ethernet1 = ð1; -@@ -22,6 +23,15 @@ chosen { - stdout-path = "serial0"; - }; - -+ vcc4v0: regulator-vcc4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ }; -+ - vcc5v0_usb: regulator-vcc5v0-usb { - compatible = "regulator-fixed"; - enable-active-high; -@@ -94,6 +104,130 @@ rgmii1: phy@1 { - }; - }; - -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <&vcc4v0>; -+ vin2-supply = <&vcc4v0>; -+ vin3-supply = <&vcc4v0>; -+ vin4-supply = <&vcc4v0>; -+ vin5-supply = <&vcc4v0>; -+ vin6-supply = <&vcc4v0>; -+ aldoin-supply = <&vcc4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4_3v3: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1_3v3: aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; -+}; -+ - &pdma { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0431-UPSTREAM-scsi-ufs-core-Pass-force_pmc-to-ufshcd_conf.patch b/SPECS/linux-lts/0431-UPSTREAM-scsi-ufs-core-Pass-force_pmc-to-ufshcd_conf.patch new file mode 100644 index 0000000000..b1da5ed091 --- /dev/null +++ b/SPECS/linux-lts/0431-UPSTREAM-scsi-ufs-core-Pass-force_pmc-to-ufshcd_conf.patch @@ -0,0 +1,228 @@ +From 64b849ace44e88370c33ba1e12ad636feaa2a9c8 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:44 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Pass force_pmc to + ufshcd_config_pwr_mode() as a parameter + +Currently, callers must manually toggle hba->force_pmc before and after +calling ufshcd_config_pwr_mode() to force a Power Mode change. Introduce +enum ufshcd_pmc_policy and refactor ufshcd_config_pwr_mode() to accept +pmc_policy as a parameter to force a Power Mode change. + +Reviewed-by: Bart Van Assche +Reviewed-by: Bean Huo +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-3-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit c91c83671642d6140b703e999e2aff2d7ad57c74) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd.c | 35 ++++++++++++++++++++++------------- + drivers/ufs/host/ufshcd-pci.c | 3 ++- + include/ufs/ufshcd.h | 19 +++++++++++++++---- + 3 files changed, 39 insertions(+), 18 deletions(-) + +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 5c7b48664147..25ff3629df99 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -1406,7 +1406,8 @@ static int ufshcd_scale_gear(struct ufs_hba *hba, u32 target_gear, bool scale_up + + config_pwr_mode: + /* check if the power mode needs to be changed or not? */ +- ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); ++ ret = ufshcd_config_pwr_mode(hba, &new_pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) + dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", + __func__, ret, +@@ -4260,7 +4261,8 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + pwr_mode_change = true; + } + if (pwr_mode_change) { +- ret = ufshcd_change_power_mode(hba, &temp_pwr_info); ++ ret = ufshcd_change_power_mode(hba, &temp_pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) + goto out; + } +@@ -4284,7 +4286,8 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + + if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) + && pwr_mode_change) +- ufshcd_change_power_mode(hba, &orig_pwr_info); ++ ufshcd_change_power_mode(hba, &orig_pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + out: + return ret; + } +@@ -4668,6 +4671,7 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) + * ufshcd_dme_change_power_mode() - UniPro DME Power Mode change sequence + * @hba: per-adapter instance + * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * @pmc_policy: Power Mode change policy + * + * This function handles the low-level DME (Device Management Entity) + * configuration required to transition the UFS link to a new power mode. It +@@ -4683,12 +4687,13 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) + * Return: 0 on success, non-zero error code on failure. + */ + static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++ struct ufs_pa_layer_attr *pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy) + { + int ret; + + /* if already configured to the requested pwr_mode */ +- if (!hba->force_pmc && ++ if (pmc_policy == UFSHCD_PMC_POLICY_DONT_FORCE && + pwr_mode->gear_rx == hba->pwr_info.gear_rx && + pwr_mode->gear_tx == hba->pwr_info.gear_tx && + pwr_mode->lane_rx == hba->pwr_info.lane_rx && +@@ -4771,6 +4776,7 @@ static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, + * ufshcd_change_power_mode() - Change UFS Link Power Mode + * @hba: per-adapter instance + * @pwr_mode: pointer to the target power mode (gear/lane) attributes ++ * @pmc_policy: Power Mode change policy + * + * This function handles the high-level sequence for changing the UFS link + * power mode. It triggers vendor-specific pre-change notification, +@@ -4780,13 +4786,14 @@ static int ufshcd_dme_change_power_mode(struct ufs_hba *hba, + * Return: 0 on success, non-zero error code on failure. + */ + int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++ struct ufs_pa_layer_attr *pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy) + { + int ret; + + ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, pwr_mode); + +- ret = ufshcd_dme_change_power_mode(hba, pwr_mode); ++ ret = ufshcd_dme_change_power_mode(hba, pwr_mode, pmc_policy); + + if (!ret) + ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, pwr_mode); +@@ -4799,11 +4806,13 @@ EXPORT_SYMBOL_GPL(ufshcd_change_power_mode); + * ufshcd_config_pwr_mode - configure a new power mode + * @hba: per-adapter instance + * @desired_pwr_mode: desired power configuration ++ * @pmc_policy: Power Mode change policy + * + * Return: 0 upon success; < 0 upon failure. + */ + int ufshcd_config_pwr_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *desired_pwr_mode) ++ struct ufs_pa_layer_attr *desired_pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy) + { + struct ufs_pa_layer_attr final_params = { 0 }; + int ret; +@@ -4818,7 +4827,7 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); + } + +- return ufshcd_change_power_mode(hba, &final_params); ++ return ufshcd_change_power_mode(hba, &final_params, pmc_policy); + } + EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); + +@@ -6857,14 +6866,13 @@ static void ufshcd_err_handler(struct work_struct *work) + * are sent via bsg and/or sysfs. + */ + down_write(&hba->clk_scaling_lock); +- hba->force_pmc = true; +- pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); ++ pmc_err = ufshcd_config_pwr_mode(hba, &hba->pwr_info, ++ UFSHCD_PMC_POLICY_FORCE); + if (pmc_err) { + needs_reset = true; + dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", + __func__, pmc_err); + } +- hba->force_pmc = false; + ufshcd_print_pwr_info(hba); + up_write(&hba->clk_scaling_lock); + spin_lock_irqsave(hba->host->host_lock, flags); +@@ -9107,7 +9115,8 @@ static int ufshcd_post_device_init(struct ufs_hba *hba) + if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) + ufshcd_set_dev_ref_clk(hba); + /* Gear up to HS gear. */ +- ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); ++ ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) { + dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", + __func__, ret); +diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c +index 8a4f2381a32e..38d458711c99 100644 +--- a/drivers/ufs/host/ufshcd-pci.c ++++ b/drivers/ufs/host/ufshcd-pci.c +@@ -145,7 +145,8 @@ static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) + + pwr_info.lane_rx = lanes; + pwr_info.lane_tx = lanes; +- ret = ufshcd_change_power_mode(hba, &pwr_info); ++ ret = ufshcd_change_power_mode(hba, &pwr_info, ++ UFSHCD_PMC_POLICY_DONT_FORCE); + if (ret) + dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n", + __func__, lanes, ret); +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index eb6e8e9b6433..c33060f24dfd 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -534,6 +534,17 @@ enum ufshcd_state { + UFSHCD_STATE_ERROR, + }; + ++/** ++ * enum ufshcd_pmc_policy - Power Mode change policy ++ * @UFSHCD_PMC_POLICY_DONT_FORCE: Do not force a Power Mode change. ++ * @UFSHCD_PMC_POLICY_FORCE: Force a Power Mode change even if current Power ++ * Mode is same as target Power Mode. ++ */ ++enum ufshcd_pmc_policy { ++ UFSHCD_PMC_POLICY_DONT_FORCE, ++ UFSHCD_PMC_POLICY_FORCE, ++}; ++ + enum ufshcd_quirks { + /* Interrupt aggregation support is broken */ + UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, +@@ -888,7 +899,6 @@ enum ufshcd_mcq_opr { + * @saved_uic_err: sticky UIC error mask + * @ufs_stats: various error counters + * @force_reset: flag to force eh_work perform a full reset +- * @force_pmc: flag to force a power mode change + * @silence_err_logs: flag to silence error logs + * @dev_cmd: ufs device management command information + * @last_dme_cmd_tstamp: time stamp of the last completed DME command +@@ -1045,7 +1055,6 @@ struct ufs_hba { + u32 saved_uic_err; + struct ufs_stats ufs_stats; + bool force_reset; +- bool force_pmc; + bool silence_err_logs; + + /* Device management request data */ +@@ -1372,9 +1381,11 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, + extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, + u32 *mib_val, u8 peer); + extern int ufshcd_change_power_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode); ++ struct ufs_pa_layer_attr *pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy); + extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *desired_pwr_mode); ++ struct ufs_pa_layer_attr *desired_pwr_mode, ++ enum ufshcd_pmc_policy pmc_policy); + extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); + + /* UIC command interfaces for DME primitives */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch deleted file mode 100644 index 5e9e4db788..0000000000 --- a/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 6aa02cc299f6c36d323e193ab8c1f6118e33d3f9 Mon Sep 17 00:00:00 2001 -From: Jennifer Berringer -Date: Wed, 20 May 2026 07:11:50 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on - OrangePi RV2 - -Set the baud rate to 115200, matching what is used by U-Boot on this -platform so that the console is usable even when console options are not -specified in cmdline. - -Fixes: bab8dea259100 ("riscv: dts: spacemit: Add OrangePi RV2 board device tree") -Signed-off-by: Jennifer Berringer -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520111150.3300707-1-jberring@redhat.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 0b4d4d1418e2..131062325e08 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -22,7 +22,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - pcie_vcc3v3: regulator-pcie-vcc3v3 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0432-UPSTREAM-scsi-ufs-core-Add-UFS_HS_G6-and-UFS_HS_GEAR.patch b/SPECS/linux-lts/0432-UPSTREAM-scsi-ufs-core-Add-UFS_HS_G6-and-UFS_HS_GEAR.patch new file mode 100644 index 0000000000..234f301265 --- /dev/null +++ b/SPECS/linux-lts/0432-UPSTREAM-scsi-ufs-core-Add-UFS_HS_G6-and-UFS_HS_GEAR.patch @@ -0,0 +1,39 @@ +From 2fc2775dc1e08879e18a10daa482189df2a84adc Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:45 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add UFS_HS_G6 and + UFS_HS_GEAR_MAX to enum ufs_hs_gear_tag + +Add UFS_HS_G6 to enum ufs_hs_gear_tag. In addition, add UFS_HS_GEAR_MAX to +enum ufs_hs_gear_tag to facilitate iteration over valid High Speed Gears. + +Reviewed-by: Bart Van Assche +Reviewed-by: Bean Huo +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-4-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 6669ab18c2238299a685ada1acea1c7d4f1da1d5) +Signed-off-by: Han Gao +--- + include/ufs/unipro.h | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 59de737490ca..71a5f643400c 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -233,7 +233,9 @@ enum ufs_hs_gear_tag { + UFS_HS_G2, /* HS Gear 2 */ + UFS_HS_G3, /* HS Gear 3 */ + UFS_HS_G4, /* HS Gear 4 */ +- UFS_HS_G5 /* HS Gear 5 */ ++ UFS_HS_G5, /* HS Gear 5 */ ++ UFS_HS_G6, /* HS Gear 6 */ ++ UFS_HS_GEAR_MAX = UFS_HS_G6, + }; + + enum ufs_lanes { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch b/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch deleted file mode 100644 index cd9e99e6c3..0000000000 --- a/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 82b7ff76828e1cb4e0a7b4cf12583f33f99e37bc Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 25 May 2026 12:23:29 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: mm: Call mark_new_valid_map() after - hotplugging vmemmap - -section_activate() creates new mappings in the vmemmap range without -flushing TLB, which may cause faults on some RISC-V implementations that -cache non-present PTEs and crashes. - -This seems to be most easily reproduced with DEBUG_VM=y and -PAGE_POISONING=y, which causes these newly mapped struct pages to be -poisoned i.e. written to immediately after mapping. - -Add a hook vmemmap_populate_finalize() in __populate_section_memmap(), -and implement it as calling mark_new_valid_map() on RISC-V, which -arranges for the exception handler to deal with these faults if they -happen. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260525-mark-after-vmemmap-populate-v1-1-e698d859ba16@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 6 ++++++ - include/linux/mm.h | 1 + - mm/sparse-vmemmap.c | 6 ++++++ - 3 files changed, 13 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index ac5bece70736..4f39ba717d59 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -1502,6 +1502,12 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, - */ - return vmemmap_populate_hugepages(start, end, node, altmap); - } -+ -+void __meminit vmemmap_populate_finalize(void) -+{ -+ /* Avoid faults on cached non-present TLB entries. */ -+ mark_new_valid_map(); -+} - #endif - - #if defined(CONFIG_MMU) && defined(CONFIG_64BIT) -diff --git a/include/linux/mm.h b/include/linux/mm.h -index 1e74eb7267ac..f75348d9364b 100644 ---- a/include/linux/mm.h -+++ b/include/linux/mm.h -@@ -3995,6 +3995,7 @@ int vmemmap_populate_hugepages(unsigned long start, unsigned long end, - int node, struct vmem_altmap *altmap); - int vmemmap_populate(unsigned long start, unsigned long end, int node, - struct vmem_altmap *altmap); -+void vmemmap_populate_finalize(void); - int vmemmap_populate_hvo(unsigned long start, unsigned long end, int node, - unsigned long headsize); - int vmemmap_undo_hvo(unsigned long start, unsigned long end, int node, -diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c -index 37522d6cb398..3fa299ce0938 100644 ---- a/mm/sparse-vmemmap.c -+++ b/mm/sparse-vmemmap.c -@@ -558,6 +558,10 @@ static int __meminit vmemmap_populate_compound_pages(unsigned long start_pfn, - - #endif - -+void __weak __meminit vmemmap_populate_finalize(void) -+{ -+} -+ - struct page * __meminit __populate_section_memmap(unsigned long pfn, - unsigned long nr_pages, int nid, struct vmem_altmap *altmap, - struct dev_pagemap *pgmap) -@@ -575,6 +579,8 @@ struct page * __meminit __populate_section_memmap(unsigned long pfn, - else - r = vmemmap_populate(start, end, nid, altmap); - -+ vmemmap_populate_finalize(); -+ - if (r < 0) - return NULL; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0433-UPSTREAM-scsi-ufs-core-Add-support-for-TX-Equalizati.patch b/SPECS/linux-lts/0433-UPSTREAM-scsi-ufs-core-Add-support-for-TX-Equalizati.patch new file mode 100644 index 0000000000..517d920365 --- /dev/null +++ b/SPECS/linux-lts/0433-UPSTREAM-scsi-ufs-core-Add-support-for-TX-Equalizati.patch @@ -0,0 +1,1798 @@ +From 08a695c27dd58d49d7657805c5ea6471716a23ca Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:46 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add support for TX + Equalization + +MIPI Unipro3.0 introduced PA_TxEQGnSetting and PA_PreCodeEn attributes for +TX Equalization and Pre-Coding. It is Host Software's responsibility to +configure these attributes for both host and device before initiating Power +Mode Change to High-Speed Gears. + +MIPI Unipro3.0 also introduced TX Equalization Training (EQTR) to identify +optimal TX Equalization settings for use by both Host's and Device's +UniPro. TX EQTR shall be initiated from the most reliable High-Speed Gear +(HS-G1) targeting High-Speed Gears (HS-G4 to HS-G6). + +Implement TX Equalization configuration and TX EQTR procedure as defined +in UFSHCI v5.0 specification. The TX EQTR procedure determines the optimal +TX Equalization settings by iterating through all possible PreShoot and +DeEmphasis combinations and selecting the best combinations for both Host +and Device based on Figure of Merit (FOM) evaluation. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-5-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 03e5d38e2f985d8d0b0a60508c0b422f664808e3) +Signed-off-by: Han Gao +--- + drivers/ufs/core/Makefile | 2 +- + drivers/ufs/core/ufs-txeq.c | 1186 ++++++++++++++++++++++++++++++++ + drivers/ufs/core/ufshcd-priv.h | 38 + + drivers/ufs/core/ufshcd.c | 50 +- + include/ufs/ufshcd.h | 135 ++++ + include/ufs/unipro.h | 114 ++- + 6 files changed, 1516 insertions(+), 9 deletions(-) + create mode 100644 drivers/ufs/core/ufs-txeq.c + +diff --git a/drivers/ufs/core/Makefile b/drivers/ufs/core/Makefile +index 51e1867e524e..ce7d16d2cf35 100644 +--- a/drivers/ufs/core/Makefile ++++ b/drivers/ufs/core/Makefile +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + + obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o +-ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ++ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ufs-txeq.o + ufshcd-core-$(CONFIG_RPMB) += ufs-rpmb.o + ufshcd-core-$(CONFIG_DEBUG_FS) += ufs-debugfs.o + ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +new file mode 100644 +index 000000000000..04f9f1ffa43e +--- /dev/null ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -0,0 +1,1186 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Qualcomm Technologies, Inc. ++ * ++ * Author: ++ * Can Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ufshcd-priv.h" ++ ++static bool use_adaptive_txeq; ++module_param(use_adaptive_txeq, bool, 0644); ++MODULE_PARM_DESC(use_adaptive_txeq, "Find and apply optimal TX Equalization settings before changing Power Mode (default: false)"); ++ ++static int txeq_gear_set(const char *val, const struct kernel_param *kp) ++{ ++ return param_set_uint_minmax(val, kp, UFS_HS_G1, UFS_HS_GEAR_MAX); ++} ++ ++static const struct kernel_param_ops txeq_gear_ops = { ++ .set = txeq_gear_set, ++ .get = param_get_uint, ++}; ++ ++static unsigned int adaptive_txeq_gear = UFS_HS_G6; ++module_param_cb(adaptive_txeq_gear, &txeq_gear_ops, &adaptive_txeq_gear, 0644); ++MODULE_PARM_DESC(adaptive_txeq_gear, "For HS-Gear[n] and above, adaptive txeq shall be used"); ++ ++static bool use_txeq_presets; ++module_param(use_txeq_presets, bool, 0644); ++MODULE_PARM_DESC(use_txeq_presets, "Use only the 8 TX Equalization Presets (pre-defined Pre-Shoot & De-Emphasis combinations) for TX EQTR (default: false)"); ++ ++static bool txeq_presets_selected[UFS_TX_EQ_PRESET_MAX] = {[0 ... (UFS_TX_EQ_PRESET_MAX - 1)] = 1}; ++module_param_array(txeq_presets_selected, bool, NULL, 0644); ++MODULE_PARM_DESC(txeq_presets_selected, "Use only the selected Presets out of the 8 TX Equalization Presets for TX EQTR"); ++ ++/* ++ * ufs_tx_eq_preset - Table of minimum required list of presets. ++ * ++ * A HS-G6 capable M-TX shall support the presets defined in M-PHY v6.0 spec. ++ * Preset Pre-Shoot(dB) De-Emphasis(dB) ++ * P0 0.0 0.0 ++ * P1 0.0 0.8 ++ * P2 0.0 1.6 ++ * P3 0.8 0.0 ++ * P4 1.6 0.0 ++ * P5 0.8 0.8 ++ * P6 0.8 1.6 ++ * P7 1.6 0.8 ++ */ ++static const struct __ufs_tx_eq_preset { ++ u8 preshoot; ++ u8 deemphasis; ++} ufs_tx_eq_preset[UFS_TX_EQ_PRESET_MAX] = { ++ [UFS_TX_EQ_PRESET_P0] = {UFS_TX_HS_PRESHOOT_DB_0P0, UFS_TX_HS_DEEMPHASIS_DB_0P0}, ++ [UFS_TX_EQ_PRESET_P1] = {UFS_TX_HS_PRESHOOT_DB_0P0, UFS_TX_HS_DEEMPHASIS_DB_0P8}, ++ [UFS_TX_EQ_PRESET_P2] = {UFS_TX_HS_PRESHOOT_DB_0P0, UFS_TX_HS_DEEMPHASIS_DB_1P6}, ++ [UFS_TX_EQ_PRESET_P3] = {UFS_TX_HS_PRESHOOT_DB_0P8, UFS_TX_HS_DEEMPHASIS_DB_0P0}, ++ [UFS_TX_EQ_PRESET_P4] = {UFS_TX_HS_PRESHOOT_DB_1P6, UFS_TX_HS_DEEMPHASIS_DB_0P0}, ++ [UFS_TX_EQ_PRESET_P5] = {UFS_TX_HS_PRESHOOT_DB_0P8, UFS_TX_HS_DEEMPHASIS_DB_0P8}, ++ [UFS_TX_EQ_PRESET_P6] = {UFS_TX_HS_PRESHOOT_DB_0P8, UFS_TX_HS_DEEMPHASIS_DB_1P6}, ++ [UFS_TX_EQ_PRESET_P7] = {UFS_TX_HS_PRESHOOT_DB_1P6, UFS_TX_HS_DEEMPHASIS_DB_0P8}, ++}; ++ ++/* ++ * pa_peer_rx_adapt_initial - Table of UniPro PA_PeerRxHSGnAdaptInitial ++ * attribute IDs for High Speed (HS) Gears. ++ * ++ * This table maps HS Gears to their respective UniPro PA_PeerRxHSGnAdaptInitial ++ * attribute IDs. Entries for Gears 1-3 are 0 (unsupported). ++ */ ++static const u32 pa_peer_rx_adapt_initial[UFS_HS_GEAR_MAX] = { ++ 0, ++ 0, ++ 0, ++ PA_PEERRXHSG4ADAPTINITIAL, ++ PA_PEERRXHSG5ADAPTINITIAL, ++ PA_PEERRXHSG6ADAPTINITIALL0L3 ++}; ++ ++/* ++ * rx_adapt_initial_cap - Table of M-PHY RX_HS_Gn_ADAPT_INITIAL_Capability ++ * attribute IDs for High Speed (HS) Gears. ++ * ++ * This table maps HS Gears to their respective M-PHY ++ * RX_HS_Gn_ADAPT_INITIAL_Capability attribute IDs. Entries for Gears 1-3 are 0 ++ * (unsupported). ++ */ ++static const u32 rx_adapt_initial_cap[UFS_HS_GEAR_MAX] = { ++ 0, ++ 0, ++ 0, ++ RX_HS_G4_ADAPT_INITIAL_CAP, ++ RX_HS_G5_ADAPT_INITIAL_CAP, ++ RX_HS_G6_ADAPT_INITIAL_CAP ++}; ++ ++/* ++ * pa_tx_eq_setting - Table of UniPro PA_TxEQGnSetting attribute IDs for High ++ * Speed (HS) Gears. ++ * ++ * This table maps HS Gears to their respective UniPro PA_TxEQGnSetting ++ * attribute IDs. ++ */ ++static const u32 pa_tx_eq_setting[UFS_HS_GEAR_MAX] = { ++ PA_TXEQG1SETTING, ++ PA_TXEQG2SETTING, ++ PA_TXEQG3SETTING, ++ PA_TXEQG4SETTING, ++ PA_TXEQG5SETTING, ++ PA_TXEQG6SETTING ++}; ++ ++/** ++ * ufshcd_configure_precoding - Configure Pre-Coding for all active lanes ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * ++ * Bit[7] in RX_FOM indicates that the receiver needs to enable Pre-Coding when ++ * set. Pre-Coding must be enabled on both the transmitter and receiver to ++ * ensure proper operation. ++ * ++ * Returns 0 on success, non-zero error code otherwise ++ */ ++static int ufshcd_configure_precoding(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params) ++{ ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ u32 local_precode_en = 0; ++ u32 peer_precode_en = 0; ++ int lane, ret; ++ ++ /* Enable Pre-Coding for Host's TX & Device's RX pair */ ++ for (lane = 0; lane < pwr_info->lane_tx; lane++) { ++ if (params->host[lane].precode_en) { ++ local_precode_en |= PRECODEEN_TX_BIT(lane); ++ peer_precode_en |= PRECODEEN_RX_BIT(lane); ++ } ++ } ++ ++ /* Enable Pre-Coding for Device's TX & Host's RX pair */ ++ for (lane = 0; lane < pwr_info->lane_rx; lane++) { ++ if (params->device[lane].precode_en) { ++ peer_precode_en |= PRECODEEN_TX_BIT(lane); ++ local_precode_en |= PRECODEEN_RX_BIT(lane); ++ } ++ } ++ ++ if (!local_precode_en && !peer_precode_en) { ++ dev_dbg(hba->dev, "Pre-Coding is not required for Host and Device\n"); ++ return 0; ++ } ++ ++ /* Set local PA_PreCodeEn */ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PRECODEEN), local_precode_en); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set local PA_PreCodeEn: %d\n", ret); ++ return ret; ++ } ++ ++ /* Set peer PA_PreCodeEn */ ++ ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_PRECODEEN), peer_precode_en); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set peer PA_PreCodeEn: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hba->dev, "Local PA_PreCodeEn: 0x%02x, Peer PA_PreCodeEn: 0x%02x\n", ++ local_precode_en, peer_precode_en); ++ ++ return 0; ++} ++ ++void ufshcd_print_tx_eq_params(struct ufs_hba *hba) ++{ ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ struct ufshcd_tx_eq_params *params; ++ u32 gear = hba->pwr_info.gear_tx; ++ int lane; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) ++ return; ++ ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid || !params->is_applied) ++ return; ++ ++ for (lane = 0; lane < pwr_info->lane_tx; lane++) ++ dev_dbg(hba->dev, "Host TX Lane %d: PreShoot %u, DeEmphasis %u, FOM %u, PreCodeEn %d\n", ++ lane, params->host[lane].preshoot, ++ params->host[lane].deemphasis, ++ params->host[lane].fom_val, ++ params->host[lane].precode_en); ++ ++ for (lane = 0; lane < pwr_info->lane_rx; lane++) ++ dev_dbg(hba->dev, "Device TX Lane %d: PreShoot %u, DeEmphasis %u, FOM %u, PreCodeEn %d\n", ++ lane, params->device[lane].preshoot, ++ params->device[lane].deemphasis, ++ params->device[lane].fom_val, ++ params->device[lane].precode_en); ++} ++ ++static inline u32 ++ufshcd_compose_tx_eq_setting(struct ufshcd_tx_eq_settings *settings, ++ int num_lanes) ++{ ++ u32 setting = 0; ++ int lane; ++ ++ for (lane = 0; lane < num_lanes; lane++, settings++) { ++ setting |= TX_HS_PRESHOOT_BITS(lane, settings->preshoot); ++ setting |= TX_HS_DEEMPHASIS_BITS(lane, settings->deemphasis); ++ } ++ ++ return setting; ++} ++ ++/** ++ * ufshcd_apply_tx_eq_settings - Apply TX Equalization settings for target gear ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * @gear: target gear ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ u32 gear) ++{ ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ u32 setting; ++ int ret; ++ ++ /* Compose settings for Host's TX Lanes */ ++ setting = ufshcd_compose_tx_eq_setting(params->host, pwr_info->lane_tx); ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(pa_tx_eq_setting[gear - 1]), setting); ++ if (ret) ++ return ret; ++ ++ /* Compose settings for Device's TX Lanes */ ++ setting = ufshcd_compose_tx_eq_setting(params->device, pwr_info->lane_rx); ++ ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(pa_tx_eq_setting[gear - 1]), setting); ++ if (ret) ++ return ret; ++ ++ /* Configure Pre-Coding */ ++ if (gear >= UFS_HS_G6) { ++ ret = ufshcd_configure_precoding(hba, params); ++ if (ret) { ++ dev_err(hba->dev, "Failed to configure pre-coding: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * ufshcd_evaluate_tx_eqtr_fom - Evaluate TX EQTR FOM results ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * @eqtr_data: TX EQTR data structure ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * Evaluate TX EQTR FOM results, update host and device TX EQTR data accordingy ++ * if FOM have been improved compared to previous iteration, and record TX EQTR ++ * FOM results. ++ */ ++static void ufshcd_evaluate_tx_eqtr_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct ufshcd_tx_eqtr_data *eqtr_data, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ u8 preshoot, deemphasis, fom_value; ++ bool precode_en; ++ int lane; ++ ++ for (lane = 0; h_iter->is_updated && lane < pwr_mode->lane_tx; lane++) { ++ preshoot = h_iter->preshoot; ++ deemphasis = h_iter->deemphasis; ++ fom_value = h_iter->fom[lane] & RX_FOM_VALUE_MASK; ++ precode_en = h_iter->fom[lane] & RX_FOM_PRECODING_EN_BIT; ++ ++ /* Record host TX EQTR FOM */ ++ eqtr_data->host_fom[lane][preshoot][deemphasis] = h_iter->fom[lane]; ++ ++ /* Check if FOM has been improved for host's TX Lanes */ ++ if (fom_value > eqtr_data->host[lane].fom_val) { ++ eqtr_data->host[lane].preshoot = preshoot; ++ eqtr_data->host[lane].deemphasis = deemphasis; ++ eqtr_data->host[lane].fom_val = fom_value; ++ eqtr_data->host[lane].precode_en = precode_en; ++ } ++ ++ dev_dbg(hba->dev, "TX EQTR: Host TX Lane %d: PreShoot %u, DeEmphasis %u, FOM value %u, PreCodeEn %d\n", ++ lane, preshoot, deemphasis, fom_value, precode_en); ++ } ++ ++ for (lane = 0; d_iter->is_updated && lane < pwr_mode->lane_rx; lane++) { ++ preshoot = d_iter->preshoot; ++ deemphasis = d_iter->deemphasis; ++ fom_value = d_iter->fom[lane] & RX_FOM_VALUE_MASK; ++ precode_en = d_iter->fom[lane] & RX_FOM_PRECODING_EN_BIT; ++ ++ /* Record device TX EQTR FOM */ ++ eqtr_data->device_fom[lane][preshoot][deemphasis] = d_iter->fom[lane]; ++ ++ /* Check if FOM has been improved for Device's TX Lanes */ ++ if (fom_value > eqtr_data->device[lane].fom_val) { ++ eqtr_data->device[lane].preshoot = preshoot; ++ eqtr_data->device[lane].deemphasis = deemphasis; ++ eqtr_data->device[lane].fom_val = fom_value; ++ eqtr_data->device[lane].precode_en = precode_en; ++ } ++ ++ dev_dbg(hba->dev, "TX EQTR: Device TX Lane %d: PreShoot %u, DeEmphasis %u, FOM value %u, PreCodeEn %d\n", ++ lane, preshoot, deemphasis, fom_value, precode_en); ++ } ++} ++ ++/** ++ * ufshcd_get_rx_fom - Get Figure of Merit (FOM) for both sides ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_get_rx_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ int lane, ret; ++ u32 fom; ++ ++ /* Get FOM of host's TX lanes from device's RX_FOM. */ ++ for (lane = 0; lane < pwr_mode->lane_tx; lane++) { ++ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB_SEL(RX_FOM, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &fom); ++ if (ret) ++ return ret; ++ ++ h_iter->fom[lane] = (u8)fom; ++ } ++ ++ /* Get FOM of device's TX lanes from host's RX_FOM. */ ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_FOM, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &fom); ++ if (ret) ++ return ret; ++ ++ d_iter->fom[lane] = (u8)fom; ++ } ++ ++ ret = ufshcd_vops_get_rx_fom(hba, pwr_mode, h_iter, d_iter); ++ if (ret) ++ dev_err(hba->dev, "Failed to get FOM via vops: %d\n", ret); ++ ++ return ret; ++} ++ ++static bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis) ++{ ++ int i; ++ ++ for (i = 0; i < UFS_TX_EQ_PRESET_MAX; i++) { ++ if (!txeq_presets_selected[i]) ++ continue; ++ ++ if (preshoot == ufs_tx_eq_preset[i].preshoot && ++ deemphasis == ufs_tx_eq_preset[i].deemphasis) ++ return true; ++ } ++ ++ return false; ++} ++ ++/** ++ * tx_eqtr_iter_try_update - Try to update a TX EQTR iterator ++ * @iter: TX EQTR iterator data structure ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * ++ * This function validates whether the provided PreShoot and DeEmphasis ++ * combination can be used or not. If yes, it updates the TX EQTR iterator with ++ * the provided PreShoot and DeEmphasis, it also sets the is_updated flag ++ * to indicate the iterator has been updated. ++ */ ++static void tx_eqtr_iter_try_update(struct tx_eqtr_iter *iter, ++ u8 preshoot, u8 deemphasis) ++{ ++ if (!test_bit(preshoot, &iter->preshoot_bitmap) || ++ !test_bit(deemphasis, &iter->deemphasis_bitmap) || ++ (use_txeq_presets && !ufshcd_is_txeq_preset_selected(preshoot, deemphasis))) { ++ iter->is_updated = false; ++ return; ++ } ++ ++ iter->preshoot = preshoot; ++ iter->deemphasis = deemphasis; ++ iter->is_updated = true; ++} ++ ++/** ++ * tx_eqtr_iter_update() - Update host and deviceTX EQTR iterators ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * @h_iter: Host TX EQTR iterator data structure ++ * @d_iter: Device TX EQTR iterator data structure ++ * ++ * Updates host and device TX Equalization training iterators with the ++ * provided PreShoot and DeEmphasis. ++ * ++ * Return: true if host and/or device TX Equalization training iterator has ++ * been updated to the provided PreShoot and DeEmphasis, false otherwise. ++ */ ++static bool tx_eqtr_iter_update(u8 preshoot, u8 deemphasis, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ tx_eqtr_iter_try_update(h_iter, preshoot, deemphasis); ++ tx_eqtr_iter_try_update(d_iter, preshoot, deemphasis); ++ ++ return h_iter->is_updated || d_iter->is_updated; ++} ++ ++/** ++ * ufshcd_tx_eqtr_iter_init - Initialize host and device TX EQTR iterators ++ * @hba: per adapter instance ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * This function initializes the TX EQTR iterator structures for both host and ++ * device by reading their TX equalization capabilities. The capabilities are ++ * cached in the hba structure to avoid redundant DME operations in subsequent ++ * calls. In the TX EQTR procedure, the iterator structures are updated by ++ * tx_eqtr_iter_update() to systematically iterate through supported TX ++ * Equalization setting combinations. ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_tx_eqtr_iter_init(struct ufs_hba *hba, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ u32 cap; ++ int ret; ++ ++ if (!hba->host_preshoot_cap) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(TX_HS_PRESHOOT_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->host_preshoot_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ if (!hba->host_deemphasis_cap) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(TX_HS_DEEMPHASIS_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->host_deemphasis_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ if (!hba->device_preshoot_cap) { ++ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(TX_HS_PRESHOOT_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->device_preshoot_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ if (!hba->device_deemphasis_cap) { ++ ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(TX_HS_DEEMPHASIS_SETTING_CAP), &cap); ++ if (ret) ++ return ret; ++ ++ hba->device_deemphasis_cap = cap & TX_EQTR_CAP_MASK; ++ } ++ ++ /* ++ * Support PreShoot & DeEmphasis of value 0 is mandatory, hence they are ++ * not reflected in PreShoot/DeEmphasis capabilities. Left shift the ++ * capability bitmap by 1 and set bit[0] to reflect value 0 is ++ * supported, such that test_bit() can be used later for convenience. ++ */ ++ h_iter->preshoot_bitmap = (hba->host_preshoot_cap << 0x1) | 0x1; ++ h_iter->deemphasis_bitmap = (hba->host_deemphasis_cap << 0x1) | 0x1; ++ d_iter->preshoot_bitmap = (hba->device_preshoot_cap << 0x1) | 0x1; ++ d_iter->deemphasis_bitmap = (hba->device_deemphasis_cap << 0x1) | 0x1; ++ ++ return 0; ++} ++ ++/** ++ * adapt_cap_to_t_adapt - Calculate TAdapt from adapt capability ++ * @adapt_cap: Adapt capability ++ * ++ * For NRZ: ++ * IF (ADAPT_range = FINE) ++ * TADAPT = 650 x (ADAPT_length + 1) ++ * ELSE (IF ADAPT_range = COARSE) ++ * TADAPT = 650 x 2^ADAPT_length ++ * ++ * Returns calculated TAdapt value in term of Unit Intervals (UI) ++ */ ++static inline u64 adapt_cap_to_t_adapt(u32 adapt_cap) ++{ ++ u64 tadapt; ++ u8 adapt_length = adapt_cap & ADAPT_LENGTH_MASK; ++ ++ if (!IS_ADAPT_RANGE_COARSE(adapt_cap)) ++ tadapt = TADAPT_FACTOR * (adapt_length + 1); ++ else ++ tadapt = TADAPT_FACTOR * (1 << adapt_length); ++ ++ return tadapt; ++} ++ ++/** ++ * adapt_cap_to_t_adapt_l0l3 - Calculate TAdapt_L0_L3 from adapt capability ++ * @adapt_cap: Adapt capability ++ * ++ * For PAM-4: ++ * IF (ADAPT_range = FINE) ++ * TADAPT_L0_L3 = 2^9 x ADAPT_length ++ * ELSE IF (ADAPT_range = COARSE) ++ * TADAPT_L0_L3 = 2^9 x (2^ADAPT_length) ++ * ++ * Returns calculated TAdapt value in term of Unit Intervals (UI) ++ */ ++static inline u64 adapt_cap_to_t_adapt_l0l3(u32 adapt_cap) ++{ ++ u64 tadapt; ++ u8 adapt_length = adapt_cap & ADAPT_LENGTH_MASK; ++ ++ if (!IS_ADAPT_RANGE_COARSE(adapt_cap)) ++ tadapt = TADAPT_L0L3_FACTOR * adapt_length; ++ else ++ tadapt = TADAPT_L0L3_FACTOR * (1 << adapt_length); ++ ++ return tadapt; ++} ++ ++/** ++ * adapt_cap_to_t_adapt_l0l1l2l3 - Calculate TAdapt_L0_L1_L2_L3 from adapt capability ++ * @adapt_cap: Adapt capability ++ * ++ * For PAM-4: ++ * IF (ADAPT_range_L0_L1_L2_L3 = FINE) ++ * TADAPT_L0_L1_L2_L3 = 2^15 x (ADAPT_length_L0_L1_L2_L3 + 1) ++ * ELSE IF (ADAPT_range_L0_L1_L2_L3 = COARSE) ++ * TADAPT_L0_L1_L2_L3 = 2^15 x 2^ADAPT_length_L0_L1_L2_L3 ++ * ++ * Returns calculated TAdapt value in term of Unit Intervals (UI) ++ */ ++static inline u64 adapt_cap_to_t_adapt_l0l1l2l3(u32 adapt_cap) ++{ ++ u64 tadapt; ++ u8 adapt_length = adapt_cap & ADAPT_LENGTH_MASK; ++ ++ if (!IS_ADAPT_RANGE_COARSE(adapt_cap)) ++ tadapt = TADAPT_L0L1L2L3_FACTOR * (adapt_length + 1); ++ else ++ tadapt = TADAPT_L0L1L2L3_FACTOR * (1 << adapt_length); ++ ++ return tadapt; ++} ++ ++/** ++ * ufshcd_setup_tx_eqtr_adapt_length - Setup TX adapt length for EQTR ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * @gear: target gear for EQTR ++ * ++ * This function determines and configures the proper TX adapt length (TAdapt) ++ * for the TX EQTR procedure based on the target gear and RX adapt capabilities ++ * of both host and device. ++ * ++ * Guidelines from MIPI UniPro v3.0 spec - select the minimum Adapt Length for ++ * the Equalization Training procedure based on the following conditions: ++ * ++ * If the target High-Speed Gear n is HS-G4 or HS-G5: ++ * PA_TxAdaptLength_EQTR[7:0] >= Max (10us, RX_HS_Gn_ADAPT_INITIAL_Capability, ++ * PA_PeerRxHsGnAdaptInitial) ++ * PA_TxAdaptLength_EQTR[7:0] shall be shorter than PACP_REQUEST_TIMER (10ms) ++ * PA_TxAdaptLength_EQTR[15:8] is not relevant for HS-G4 and HS-G5. This field ++ * is set to 255 (reserved value). ++ * ++ * If the target High-Speed Gear n is HS-G6: ++ * PA_TxAdapthLength_EQTR >= 10us ++ * PA_TxAdapthLength_EQTR[7:0] >= Max (RX_HS_G6_ADAPT_INITIAL_Capability, ++ * PA_PeerRxHsG6AdaptInitialL0L3) ++ * PA_TxAdapthLength_EQTR[15:8] >= Max (RX_HS_G6_ADAPT_INITIAL_L0_L1_L2_L3_Capability, ++ * PA_PeerRxHsG6AdaptInitialL0L1L2L3) ++ * PA_TxAdaptLength_EQTR shall be shorter than PACP_REQUEST_TIMER value of 10ms. ++ * ++ * Since adapt capabilities encode both range (fine/coarse) and length values, ++ * direct comparison is not possible. This function converts adapt capabilities ++ * to actual time durations in Unit Intervals (UI) using the Adapt time ++ * calculation formular in M-PHY v6.0 spec (Table 8), then selects the maximum ++ * to ensure both host and device use adequate TX adapt length. ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_setup_tx_eqtr_adapt_length(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ u32 gear) ++{ ++ u32 adapt_eqtr; ++ int ret; ++ ++ if (gear == UFS_HS_G4 || gear == UFS_HS_G5) { ++ u64 t_adapt, t_adapt_local, t_adapt_peer; ++ u32 adapt_cap_local, adapt_cap_peer, adapt_length; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(rx_adapt_initial_cap[gear - 1], ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &adapt_cap_local); ++ if (ret) ++ return ret; ++ ++ if (adapt_cap_local > ADAPT_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_cap_local); ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(pa_peer_rx_adapt_initial[gear - 1]), ++ &adapt_cap_peer); ++ if (ret) ++ return ret; ++ ++ if (adapt_cap_peer > ADAPT_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_cap_peer); ++ return -EINVAL; ++ } ++ ++ t_adapt_local = adapt_cap_to_t_adapt(adapt_cap_local); ++ t_adapt_peer = adapt_cap_to_t_adapt(adapt_cap_peer); ++ t_adapt = max(t_adapt_local, t_adapt_peer); ++ ++ dev_dbg(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_cap_local); ++ dev_dbg(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_cap_peer); ++ dev_dbg(hba->dev, "t_adapt_local = %llu UI, t_adapt_peer = %llu UI\n", ++ t_adapt_local, t_adapt_peer); ++ dev_dbg(hba->dev, "TAdapt %llu UI selected for TX EQTR\n", ++ t_adapt); ++ ++ adapt_length = (t_adapt_local >= t_adapt_peer) ? ++ adapt_cap_local : adapt_cap_peer; ++ ++ if (gear == UFS_HS_G4 && t_adapt < TX_EQTR_HS_G4_MIN_T_ADAPT) { ++ dev_dbg(hba->dev, "TAdapt %llu UI is too short for TX EQTR for HS-G%u, use default Adapt 0x%x\n", ++ t_adapt, gear, TX_EQTR_HS_G4_ADAPT_DEFAULT); ++ adapt_length = TX_EQTR_HS_G4_ADAPT_DEFAULT; ++ } else if (gear == UFS_HS_G5 && t_adapt < TX_EQTR_HS_G5_MIN_T_ADAPT) { ++ dev_dbg(hba->dev, "TAdapt %llu UI is too short for TX EQTR for HS-G%u, use default Adapt 0x%x\n", ++ t_adapt, gear, TX_EQTR_HS_G5_ADAPT_DEFAULT); ++ adapt_length = TX_EQTR_HS_G5_ADAPT_DEFAULT; ++ } ++ ++ adapt_eqtr = adapt_length | ++ (TX_EQTR_ADAPT_RESERVED << TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT); ++ } else if (gear == UFS_HS_G6) { ++ u64 t_adapt, t_adapt_l0l3, t_adapt_l0l3_local, t_adapt_l0l3_peer; ++ u64 t_adapt_l0l1l2l3, t_adapt_l0l1l2l3_local, t_adapt_l0l1l2l3_peer; ++ u32 adapt_l0l3_cap_local, adapt_l0l3_cap_peer, adapt_length_l0l3; ++ u32 adapt_l0l1l2l3_cap_local, adapt_l0l1l2l3_cap_peer, adapt_length_l0l1l2l3; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(rx_adapt_initial_cap[gear - 1], ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &adapt_l0l3_cap_local); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l3_cap_local > ADAPT_L0L3_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l3_cap_local); ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(pa_peer_rx_adapt_initial[gear - 1]), ++ &adapt_l0l3_cap_peer); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l3_cap_peer > ADAPT_L0L3_LENGTH_MAX) { ++ dev_err(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l3_cap_peer); ++ return -EINVAL; ++ } ++ ++ t_adapt_l0l3_local = adapt_cap_to_t_adapt_l0l3(adapt_l0l3_cap_local); ++ t_adapt_l0l3_peer = adapt_cap_to_t_adapt_l0l3(adapt_l0l3_cap_peer); ++ ++ dev_dbg(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_l0l3_cap_local); ++ dev_dbg(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_CAP = 0x%x\n", ++ gear, adapt_l0l3_cap_peer); ++ dev_dbg(hba->dev, "t_adapt_l0l3_local = %llu UI, t_adapt_l0l3_peer = %llu UI\n", ++ t_adapt_l0l3_local, t_adapt_l0l3_peer); ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &adapt_l0l1l2l3_cap_local); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l1l2l3_cap_local > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l1l2l3_cap_local); ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), ++ &adapt_l0l1l2l3_cap_peer); ++ if (ret) ++ return ret; ++ ++ if (adapt_l0l1l2l3_cap_peer > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP (0x%x) exceeds MAX\n", ++ gear, adapt_l0l1l2l3_cap_peer); ++ return -EINVAL; ++ } ++ ++ t_adapt_l0l1l2l3_local = adapt_cap_to_t_adapt_l0l1l2l3(adapt_l0l1l2l3_cap_local); ++ t_adapt_l0l1l2l3_peer = adapt_cap_to_t_adapt_l0l1l2l3(adapt_l0l1l2l3_cap_peer); ++ ++ dev_dbg(hba->dev, "local RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP = 0x%x\n", ++ gear, adapt_l0l1l2l3_cap_local); ++ dev_dbg(hba->dev, "peer RX_HS_G%u_ADAPT_INITIAL_L0L1L2L3_CAP = 0x%x\n", ++ gear, adapt_l0l1l2l3_cap_peer); ++ dev_dbg(hba->dev, "t_adapt_l0l1l2l3_local = %llu UI, t_adapt_l0l1l2l3_peer = %llu UI\n", ++ t_adapt_l0l1l2l3_local, t_adapt_l0l1l2l3_peer); ++ ++ t_adapt_l0l1l2l3 = max(t_adapt_l0l1l2l3_local, t_adapt_l0l1l2l3_peer); ++ t_adapt_l0l3 = max(t_adapt_l0l3_local, t_adapt_l0l3_peer); ++ t_adapt = t_adapt_l0l3 + t_adapt_l0l1l2l3; ++ ++ dev_dbg(hba->dev, "TAdapt %llu PAM-4 UI selected for TX EQTR\n", ++ t_adapt); ++ ++ adapt_length_l0l3 = (t_adapt_l0l3_local >= t_adapt_l0l3_peer) ? ++ adapt_l0l3_cap_local : adapt_l0l3_cap_peer; ++ adapt_length_l0l1l2l3 = (t_adapt_l0l1l2l3_local >= t_adapt_l0l1l2l3_peer) ? ++ adapt_l0l1l2l3_cap_local : adapt_l0l1l2l3_cap_peer; ++ ++ if (t_adapt < TX_EQTR_HS_G6_MIN_T_ADAPT) { ++ dev_dbg(hba->dev, "TAdapt %llu UI is too short for TX EQTR for HS-G%u, use default Adapt 0x%x\n", ++ t_adapt, gear, TX_EQTR_HS_G6_ADAPT_DEFAULT); ++ adapt_length_l0l3 = TX_EQTR_HS_G6_ADAPT_DEFAULT; ++ } ++ ++ adapt_eqtr = adapt_length_l0l3 | ++ (adapt_length_l0l1l2l3 << TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT); ++ } else { ++ return -EINVAL; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXADAPTLENGTH_EQTR), adapt_eqtr); ++ if (ret) ++ dev_err(hba->dev, "Failed to set adapt length for TX EQTR: %d\n", ret); ++ else ++ dev_dbg(hba->dev, "PA_TXADAPTLENGTH_EQTR configured to 0x%08x\n", adapt_eqtr); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_compose_tx_eqtr_setting - Compose TX EQTR setting ++ * @iter: TX EQTR iterator data structure ++ * @num_lanes: number of active lanes ++ * ++ * Returns composed TX EQTR setting, same setting is used for all active lanes ++ */ ++static inline u32 ufshcd_compose_tx_eqtr_setting(struct tx_eqtr_iter *iter, ++ int num_lanes) ++{ ++ u32 setting = 0; ++ int lane; ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ setting |= TX_HS_PRESHOOT_BITS(lane, iter->preshoot); ++ setting |= TX_HS_DEEMPHASIS_BITS(lane, iter->deemphasis); ++ } ++ ++ return setting; ++} ++ ++/** ++ * ufshcd_apply_tx_eqtr_settings - Apply TX EQTR setting ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * @h_iter: host TX EQTR iterator data structure ++ * @d_iter: device TX EQTR iterator data structure ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int ufshcd_apply_tx_eqtr_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ u32 setting; ++ int ret; ++ ++ setting = ufshcd_compose_tx_eqtr_setting(h_iter, pwr_mode->lane_tx); ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQTRSETTING), setting); ++ if (ret) ++ return ret; ++ ++ setting = ufshcd_compose_tx_eqtr_setting(d_iter, pwr_mode->lane_rx); ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERTXEQTRSETTING), setting); ++ if (ret) ++ return ret; ++ ++ ret = ufshcd_vops_apply_tx_eqtr_settings(hba, pwr_mode, h_iter, d_iter); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_update_tx_eq_params - Update TX Equalization params ++ * @params: TX EQ parameters data structure ++ * @eqtr_data: TX EQTR data structure ++ * ++ * Update TX Equalization params using results from TX EQTR data. ++ */ ++static inline void ++ufshcd_update_tx_eq_params(struct ufshcd_tx_eq_params *params, ++ struct ufshcd_tx_eqtr_data *eqtr_data) ++{ ++ struct ufshcd_tx_eqtr_record *rec = params->eqtr_record; ++ ++ memcpy(params->host, eqtr_data->host, sizeof(params->host)); ++ memcpy(params->device, eqtr_data->device, sizeof(params->device)); ++ ++ if (!rec) ++ return; ++ ++ memcpy(rec->host_fom, eqtr_data->host_fom, sizeof(rec->host_fom)); ++ memcpy(rec->device_fom, eqtr_data->device_fom, sizeof(rec->device_fom)); ++ rec->last_record_ts = ktime_get(); ++ rec->last_record_index++; ++} ++ ++/** ++ * __ufshcd_tx_eqtr - TX Equalization Training (EQTR) procedure ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure ++ * @pwr_mode: target power mode containing gear and rate information ++ * ++ * This function implements the complete TX EQTR procedure as defined in UFSHCI ++ * v5.0 specification. It iterates through all possible combinations of PreShoot ++ * and DeEmphasis settings to find the optimal TX Equalization settings for all ++ * active lanes. ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++static int __ufshcd_tx_eqtr(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufshcd_tx_eqtr_data *eqtr_data __free(kfree) = ++ kzalloc(sizeof(*eqtr_data), GFP_KERNEL); ++ struct tx_eqtr_iter h_iter = {}; ++ struct tx_eqtr_iter d_iter = {}; ++ u32 gear = pwr_mode->gear_tx; ++ u8 preshoot, deemphasis; ++ ktime_t start; ++ int ret; ++ ++ if (!eqtr_data) ++ return -ENOMEM; ++ ++ dev_info(hba->dev, "Start TX EQTR procedure for HS-G%u, Rate-%s, RX Lanes: %u, TX Lanes: %u\n", ++ gear, ufs_hs_rate_to_str(pwr_mode->hs_rate), ++ pwr_mode->lane_rx, pwr_mode->lane_tx); ++ ++ start = ktime_get(); ++ ++ /* Step 1 - Determine the TX Adapt Length for EQTR */ ++ ret = ufshcd_setup_tx_eqtr_adapt_length(hba, params, gear); ++ if (ret) { ++ dev_err(hba->dev, "Failed to setup TX EQTR Adaptation length: %d\n", ret); ++ return ret; ++ } ++ ++ /* Step 2 - Determine TX Equalization setting capabilities */ ++ ret = ufshcd_tx_eqtr_iter_init(hba, &h_iter, &d_iter); ++ if (ret) { ++ dev_err(hba->dev, "Failed to init TX EQTR data: %d\n", ret); ++ return ret; ++ } ++ ++ /* TX EQTR main loop */ ++ for (preshoot = 0; preshoot < TX_HS_NUM_PRESHOOT; preshoot++) { ++ for (deemphasis = 0; deemphasis < TX_HS_NUM_DEEMPHASIS; deemphasis++) { ++ if (!tx_eqtr_iter_update(preshoot, deemphasis, &h_iter, &d_iter)) ++ continue; ++ ++ /* Step 3 - Apply TX EQTR settings */ ++ ret = ufshcd_apply_tx_eqtr_settings(hba, pwr_mode, &h_iter, &d_iter); ++ if (ret) { ++ dev_err(hba->dev, "Failed to apply TX EQTR settings (PreShoot %u, DeEmphasis %u): %d\n", ++ preshoot, deemphasis, ret); ++ return ret; ++ } ++ ++ /* Step 4 - Trigger UIC TX EQTR */ ++ ret = ufshcd_uic_tx_eqtr(hba, gear); ++ if (ret) { ++ dev_err(hba->dev, "Failed to trigger UIC TX EQTR for target gear %u: %d\n", ++ gear, ret); ++ return ret; ++ } ++ ++ /* Step 5 - Get FOM */ ++ ret = ufshcd_get_rx_fom(hba, pwr_mode, &h_iter, &d_iter); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get RX_FOM: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ufshcd_evaluate_tx_eqtr_fom(hba, pwr_mode, eqtr_data, &h_iter, &d_iter); ++ } ++ } ++ ++ dev_info(hba->dev, "TX EQTR procedure completed! Time elapsed: %llu ms\n", ++ ktime_to_ms(ktime_sub(ktime_get(), start))); ++ ++ ufshcd_update_tx_eq_params(params, eqtr_data); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_tx_eqtr_prepare - Prepare UFS link for TX EQTR procedure ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate ++ * ++ * This function prepares the UFS link for TX Equalization Training (EQTR) by ++ * establishing the proper initial conditions required by the EQTR procedure. ++ * It ensures that EQTR starts from the most reliable Power Mode (HS-G1) with ++ * all connected lanes activated and sets host TX HS Adapt Type to INITIAL. ++ * ++ * Returns 0 on successful preparation, negative error code on failure ++ */ ++static int ufshcd_tx_eqtr_prepare(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufs_pa_layer_attr pwr_mode_hs_g1 = { ++ /* TX EQTR shall be initiated from the most reliable HS-G1 */ ++ .gear_rx = UFS_HS_G1, ++ .gear_tx = UFS_HS_G1, ++ .lane_rx = pwr_mode->lane_rx, ++ .lane_tx = pwr_mode->lane_tx, ++ .pwr_rx = FAST_MODE, ++ .pwr_tx = FAST_MODE, ++ /* Use the target power mode's HS rate */ ++ .hs_rate = pwr_mode->hs_rate, ++ }; ++ u32 rate = pwr_mode->hs_rate; ++ int ret; ++ ++ /* Change power mode to HS-G1, activate all connected lanes. */ ++ ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (ret) { ++ dev_err(hba->dev, "TX EQTR: Failed to change power mode to HS-G1, Rate-%s: %d\n", ++ ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), ++ PA_INITIAL_ADAPT); ++ if (ret) ++ dev_err(hba->dev, "TX EQTR: Failed to set Host Adapt type to INITIAL: %d\n", ++ ret); ++ ++ return ret; ++} ++ ++static void ufshcd_tx_eqtr_unprepare(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ int err; ++ ++ if (pwr_mode->pwr_rx == SLOWAUTO_MODE || pwr_mode->hs_rate == 0) ++ return; ++ ++ err = ufshcd_change_power_mode(hba, pwr_mode, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (err) ++ dev_err(hba->dev, "%s: Failed to restore Power Mode: %d\n", ++ __func__, err); ++} ++ ++/** ++ * ufshcd_tx_eqtr - Perform TX EQTR procedures with vops callbacks ++ * @hba: per adapter instance ++ * @params: TX EQ parameters data structure to populate ++ * @pwr_mode: target power mode containing gear and rate information ++ * ++ * This is the main entry point for performing TX Equalization Training (EQTR) ++ * procedure as defined in UFSCHI v5.0 specification. It serves as a wrapper ++ * around __ufshcd_tx_eqtr() to provide vops support through the variant ++ * operations framework. ++ * ++ * Returns 0 on success, negative error code on failure ++ */ ++static int ufshcd_tx_eqtr(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufs_pa_layer_attr old_pwr_info; ++ int ret; ++ ++ if (!params->eqtr_record) { ++ params->eqtr_record = devm_kzalloc(hba->dev, ++ sizeof(*params->eqtr_record), ++ GFP_KERNEL); ++ if (!params->eqtr_record) ++ return -ENOMEM; ++ } ++ ++ memcpy(&old_pwr_info, &hba->pwr_info, sizeof(struct ufs_pa_layer_attr)); ++ ++ ret = ufshcd_tx_eqtr_prepare(hba, pwr_mode); ++ if (ret) { ++ dev_err(hba->dev, "Failed to prepare TX EQTR: %d\n", ret); ++ goto out; ++ } ++ ++ ret = ufshcd_vops_tx_eqtr_notify(hba, PRE_CHANGE, pwr_mode); ++ if (ret) ++ goto out; ++ ++ ret = __ufshcd_tx_eqtr(hba, params, pwr_mode); ++ if (ret) ++ goto out; ++ ++ ret = ufshcd_vops_tx_eqtr_notify(hba, POST_CHANGE, pwr_mode); ++ ++out: ++ if (ret) ++ ufshcd_tx_eqtr_unprepare(hba, &old_pwr_info); ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_config_tx_eq_settings - Configure TX Equalization settings ++ * @hba: per adapter instance ++ * @pwr_mode: target power mode containing gear and rate information ++ * ++ * This function finds and sets the TX Equalization settings for the given ++ * target power mode. ++ * ++ * Returns 0 on success, error code otherwise ++ */ ++int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufshcd_tx_eq_params *params; ++ u32 gear, rate; ++ ++ if (!ufshcd_is_tx_eq_supported(hba) || !use_adaptive_txeq) ++ return 0; ++ ++ if (!hba->max_pwr_info.is_valid) { ++ dev_err(hba->dev, "Max power info is invalid\n"); ++ return -EINVAL; ++ } ++ ++ if (!pwr_mode) { ++ dev_err(hba->dev, "Target power mode is NULL\n"); ++ return -EINVAL; ++ } ++ ++ gear = pwr_mode->gear_tx; ++ rate = pwr_mode->hs_rate; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) { ++ dev_err(hba->dev, "Invalid HS-Gear (%u) for TX Equalization\n", ++ gear); ++ return -EINVAL; ++ } else if (gear < max_t(u32, adaptive_txeq_gear, UFS_HS_G4)) { ++ /* TX EQTR is supported for HS-G4 and higher Gears */ ++ return 0; ++ } ++ ++ if (rate != PA_HS_MODE_A && rate != PA_HS_MODE_B) { ++ dev_err(hba->dev, "Invalid HS-Rate (%u) for TX Equalization\n", ++ rate); ++ return -EINVAL; ++ } ++ ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid) { ++ int ret; ++ ++ ret = ufshcd_tx_eqtr(hba, params, pwr_mode); ++ if (ret) { ++ dev_err(hba->dev, "Failed to train TX Equalization for HS-G%u, Rate-%s: %d\n", ++ gear, ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ /* Mark TX Equalization settings as valid */ ++ params->is_valid = true; ++ params->is_applied = false; ++ } ++ ++ if (params->is_valid && !params->is_applied) { ++ int ret; ++ ++ ret = ufshcd_apply_tx_eq_settings(hba, params, gear); ++ if (ret) { ++ dev_err(hba->dev, "Failed to apply TX Equalization settings for HS-G%u, Rate-%s: %d\n", ++ gear, ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ params->is_applied = true; ++ } ++ ++ return 0; ++} ++ ++/** ++ * ufshcd_apply_valid_tx_eq_settings - Apply valid TX Equalization settings ++ * @hba: per-adapter instance ++ * ++ * This function iterates through all supported High-Speed (HS) gears and ++ * applies valid TX Equalization settings to both Host and Device. ++ */ ++void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba) ++{ ++ struct ufshcd_tx_eq_params *params; ++ int gear, err; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return; ++ ++ if (!hba->max_pwr_info.is_valid) { ++ dev_err(hba->dev, "Max power info is invalid, cannot apply TX Equalization settings\n"); ++ return; ++ } ++ ++ for (gear = UFS_HS_G1; gear <= UFS_HS_GEAR_MAX; gear++) { ++ params = &hba->tx_eq_params[gear - 1]; ++ ++ if (params->is_valid) { ++ err = ufshcd_apply_tx_eq_settings(hba, params, gear); ++ if (err) { ++ params->is_applied = false; ++ dev_err(hba->dev, "Failed to apply TX Equalization settings for HS-G%u: %d\n", ++ gear, err); ++ } else { ++ params->is_applied = true; ++ } ++ } ++ } ++} +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 087ebf43b09d..fbcea20c8991 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -104,6 +104,12 @@ int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, + int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); + int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id); + ++int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear); ++void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba); ++int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode); ++void ufshcd_print_tx_eq_params(struct ufs_hba *hba); ++ + /* Wrapper functions for safely calling variant operations */ + static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) + { +@@ -298,6 +304,38 @@ static inline u32 ufshcd_vops_freq_to_gear_speed(struct ufs_hba *hba, unsigned l + return 0; + } + ++static inline int ufshcd_vops_get_rx_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ if (hba->vops && hba->vops->get_rx_fom) ++ return hba->vops->get_rx_fom(hba, pwr_mode, h_iter, d_iter); ++ ++ return 0; ++} ++ ++static inline int ufshcd_vops_apply_tx_eqtr_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ if (hba->vops && hba->vops->apply_tx_eqtr_settings) ++ return hba->vops->apply_tx_eqtr_settings(hba, pwr_mode, h_iter, d_iter); ++ ++ return 0; ++} ++ ++static inline int ufshcd_vops_tx_eqtr_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ if (hba->vops && hba->vops->tx_eqtr_notify) ++ return hba->vops->tx_eqtr_notify(hba, status, pwr_mode); ++ ++ return 0; ++} ++ + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; + + /** +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 25ff3629df99..51e431a04ee4 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -4354,16 +4354,18 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) + ret = __ufshcd_send_uic_cmd(hba, cmd); + if (ret) { + dev_err(hba->dev, +- "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", +- cmd->command, cmd->argument3, ret); ++ "pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) uic error %d\n", ++ cmd->command, UIC_GET_ATTR_ID(cmd->argument1), ++ cmd->argument3, ret); + goto out; + } + + if (!wait_for_completion_timeout(hba->uic_async_done, + msecs_to_jiffies(uic_cmd_timeout))) { + dev_err(hba->dev, +- "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", +- cmd->command, cmd->argument3); ++ "pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) completion timeout\n", ++ cmd->command, UIC_GET_ATTR_ID(cmd->argument1), ++ cmd->argument3); + + if (!cmd->cmd_active) { + dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", +@@ -4379,14 +4381,16 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) + status = ufshcd_get_upmcrs(hba); + if (status != PWR_LOCAL) { + dev_err(hba->dev, +- "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", +- cmd->command, status); ++ "pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) failed, host upmcrs:0x%x\n", ++ cmd->command, UIC_GET_ATTR_ID(cmd->argument1), ++ cmd->argument3, status); + ret = (status != PWR_OK) ? status : -1; + } + out: + if (ret) { + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + ufshcd_print_evt_hist(hba); + } + +@@ -4404,6 +4408,29 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) + return ret; + } + ++/** ++ * ufshcd_uic_tx_eqtr - Perform UIC TX Equalization Training ++ * @hba: per adapter instance ++ * @gear: target gear for EQTR ++ * ++ * Returns 0 on success, negative error code otherwise ++ */ ++int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear) ++{ ++ struct uic_command uic_cmd = { ++ .command = UIC_CMD_DME_SET, ++ .argument1 = UIC_ARG_MIB(PA_EQTR_GEAR), ++ .argument3 = gear, ++ }; ++ int ret; ++ ++ ufshcd_hold(hba); ++ ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); ++ ufshcd_release(hba); ++ ++ return ret; ++} ++ + /** + * ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result + * @hba: per adapter instance +@@ -4827,6 +4854,12 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); + } + ++ ret = ufshcd_config_tx_eq_settings(hba, &final_params); ++ if (ret) ++ dev_warn(hba->dev, "Failed to configure TX Equalization for HS-G%u, Rate-%s: %d\n", ++ final_params.gear_tx, ++ ufs_hs_rate_to_str(final_params.hs_rate), ret); ++ + return ufshcd_change_power_mode(hba, &final_params, pmc_policy); + } + EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); +@@ -6808,6 +6841,7 @@ static void ufshcd_err_handler(struct work_struct *work) + spin_unlock_irqrestore(hba->host->host_lock, flags); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + ufshcd_print_evt_hist(hba); + ufshcd_print_tmrs(hba, hba->outstanding_tasks); + ufshcd_print_trs_all(hba, pr_prdt); +@@ -7071,6 +7105,7 @@ static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) + ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, + "host_regs: "); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + } + ufshcd_schedule_eh_work(hba); + retval |= IRQ_HANDLED; +@@ -7833,6 +7868,7 @@ static int ufshcd_abort(struct scsi_cmnd *cmd) + ufshcd_print_evt_hist(hba); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); ++ ufshcd_print_tx_eq_params(hba); + ufshcd_print_tr(hba, tag, true); + } else { + ufshcd_print_tr(hba, tag, false); +@@ -8794,6 +8830,8 @@ static void ufshcd_tune_unipro_params(struct ufs_hba *hba) + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_HIBER8TIME) + ufshcd_quirk_override_pa_h8time(hba); ++ ++ ufshcd_apply_valid_tx_eq_settings(hba); + } + + static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index c33060f24dfd..77634e07cbb3 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -292,6 +292,84 @@ struct ufs_pwr_mode_info { + struct ufs_pa_layer_attr info; + }; + ++#define UFS_MAX_LANES 2 ++ ++/** ++ * struct tx_eqtr_iter - TX Equalization Training iterator ++ * @preshoot_bitmap: PreShoot bitmap ++ * @deemphasis_bitmap: DeEmphasis bitmap ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * @fom: Figure-of-Merit read out from RX_FOM ++ * @is_updated: Flag to indicate if updated since previous iteration ++ */ ++struct tx_eqtr_iter { ++ unsigned long preshoot_bitmap; ++ unsigned long deemphasis_bitmap; ++ u8 preshoot; ++ u8 deemphasis; ++ u8 fom[UFS_MAX_LANES]; ++ bool is_updated; ++}; ++ ++/** ++ * struct ufshcd_tx_eq_settings - TX Equalization settings ++ * @preshoot: PreShoot value ++ * @deemphasis: DeEmphasis value ++ * @fom_val: Figure-of-Merit value read out from RX_FOM (Bit[6:0]) ++ * @precode_en: Flag to indicate whether need to enable pre-coding ++ */ ++struct ufshcd_tx_eq_settings { ++ u8 preshoot; ++ u8 deemphasis; ++ u8 fom_val; ++ bool precode_en; ++}; ++ ++/** ++ * struct ufshcd_tx_eqtr_data - Data used during TX Equalization Training procedure ++ * @host: Optimal TX EQ settings identified for host TX Lanes during TX EQTR ++ * @device: Optimal TX EQ settings identified for device TX Lanes during TX EQTR ++ * @host_fom: Host TX EQTR FOM record ++ * @device_fom: Device TX EQTR FOM record ++ */ ++struct ufshcd_tx_eqtr_data { ++ struct ufshcd_tx_eq_settings host[UFS_MAX_LANES]; ++ struct ufshcd_tx_eq_settings device[UFS_MAX_LANES]; ++ u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++}; ++ ++/** ++ * struct ufshcd_tx_eqtr_record - TX Equalization Training record ++ * @host_fom: Host TX EQTR FOM record ++ * @device_fom: Device TX EQTR FOM record ++ * @last_record_ts: Timestamp of the most recent TX EQTR record ++ * @last_record_index: Index of the most recent TX EQTR record ++ */ ++struct ufshcd_tx_eqtr_record { ++ u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ ktime_t last_record_ts; ++ u16 last_record_index; ++}; ++ ++/** ++ * struct ufshcd_tx_eq_params - TX Equalization parameters structure ++ * @host: TX EQ settings for host TX Lanes ++ * @device: TX EQ settings for device TX Lanes ++ * @eqtr_record: Pointer to TX EQTR record ++ * @is_valid: True if parameter contains valid TX Equalization settings ++ * @is_applied: True if settings have been applied to UniPro of both sides ++ */ ++struct ufshcd_tx_eq_params { ++ struct ufshcd_tx_eq_settings host[UFS_MAX_LANES]; ++ struct ufshcd_tx_eq_settings device[UFS_MAX_LANES]; ++ struct ufshcd_tx_eqtr_record *eqtr_record; ++ bool is_valid; ++ bool is_applied; ++}; ++ + /** + * struct ufs_hba_variant_ops - variant specific callbacks + * @name: variant name +@@ -335,6 +413,11 @@ struct ufs_pwr_mode_info { + * @config_esi: called to config Event Specific Interrupt + * @config_scsi_dev: called to configure SCSI device parameters + * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed ++ * @apply_tx_eqtr_settings: called to apply settings for TX Equalization ++ * Training settings. ++ * @get_rx_fom: called to get Figure of Merit (FOM) value. ++ * @tx_eqtr_notify: called before and after TX Equalization Training procedure ++ * to allow platform vendor specific configs to take place. + */ + struct ufs_hba_variant_ops { + const char *name; +@@ -386,6 +469,17 @@ struct ufs_hba_variant_ops { + int (*config_esi)(struct ufs_hba *hba); + void (*config_scsi_dev)(struct scsi_device *sdev); + u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq); ++ int (*get_rx_fom)(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter); ++ int (*apply_tx_eqtr_settings)(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter); ++ int (*tx_eqtr_notify)(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *pwr_mode); + }; + + /* clock gating state */ +@@ -784,6 +878,13 @@ enum ufshcd_caps { + * WriteBooster when scaling the clock down. + */ + UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, ++ ++ /* ++ * This capability allows the host controller driver to apply TX ++ * Equalization settings discovered from UFS attributes, variant ++ * specific operations and TX Equaliztion Training procedure. ++ */ ++ UFSHCD_CAP_TX_EQUALIZATION = 1 << 13, + }; + + struct ufs_hba_variant_params { +@@ -962,6 +1063,15 @@ enum ufshcd_mcq_opr { + * @dev_lvl_exception_count: count of device level exceptions since last reset + * @dev_lvl_exception_id: vendor specific information about the device level exception event. + * @rpmbs: list of OP-TEE RPMB devices (one per RPMB region) ++ * @host_preshoot_cap: a bitfield to indicate supported PreShoot dBs of host's TX lanes, cache of ++ * host M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15) ++ * @host_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of host's TX lanes, cache ++ * of host M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12) ++ * @device_preshoot_cap: a bitfield to indicate supported PreShoot dBs of device's TX lanes, cache ++ * of device M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15) ++ * @device_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of device's TX lanes, ++ * cache of device M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12) ++ * @tx_eq_params: TX Equalization settings + */ + struct ufs_hba { + void __iomem *mmio_base; +@@ -1137,6 +1247,12 @@ struct ufs_hba { + atomic_t dev_lvl_exception_count; + u64 dev_lvl_exception_id; + struct list_head rpmbs; ++ ++ u8 host_preshoot_cap; ++ u8 host_deemphasis_cap; ++ u8 device_preshoot_cap; ++ u8 device_deemphasis_cap; ++ struct ufshcd_tx_eq_params tx_eq_params[UFS_HS_GEAR_MAX]; + }; + + /** +@@ -1281,6 +1397,13 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) + return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; + } + ++static inline bool ufshcd_is_tx_eq_supported(struct ufs_hba *hba) ++{ ++ return hba->caps & UFSHCD_CAP_TX_EQUALIZATION && ++ hba->ufs_version >= ufshci_version(5, 0) && ++ hba->dev_info.wspecversion >= 0x500; ++} ++ + #define ufsmcq_writel(hba, val, reg) \ + writel((val), (hba)->mcq_base + (reg)) + #define ufsmcq_readl(hba, reg) \ +@@ -1296,6 +1419,18 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) + #define ufshcd_readl(hba, reg) \ + readl((hba)->mmio_base + (reg)) + ++static inline const char *ufs_hs_rate_to_str(enum ufs_hs_gear_rate rate) ++{ ++ switch (rate) { ++ case PA_HS_MODE_A: ++ return "A"; ++ case PA_HS_MODE_B: ++ return "B"; ++ default: ++ return "Unknown"; ++ } ++} ++ + /** + * ufshcd_rmwl - perform read/modify/write for a controller register + * @hba: per adapter instance +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 71a5f643400c..4aa592130b4e 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -10,6 +10,8 @@ + * M-TX Configuration Attributes + */ + #define TX_HIBERN8TIME_CAPABILITY 0x000F ++#define TX_HS_DEEMPHASIS_SETTING_CAP 0x0012 ++#define TX_HS_PRESHOOT_SETTING_CAP 0x0015 + #define TX_MODE 0x0021 + #define TX_HSRATE_SERIES 0x0022 + #define TX_HSGEAR 0x0023 +@@ -38,6 +40,9 @@ + /* + * M-RX Configuration Attributes + */ ++#define RX_HS_G5_ADAPT_INITIAL_CAP 0x0074 ++#define RX_HS_G6_ADAPT_INITIAL_CAP 0x007B ++#define RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP 0x007D + #define RX_HS_G1_SYNC_LENGTH_CAP 0x008B + #define RX_HS_G1_PREP_LENGTH_CAP 0x008C + #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F +@@ -50,6 +55,7 @@ + #define RX_HIBERN8TIME_CAP 0x0092 + #define RX_ADV_HIBERN8TIME_CAP 0x0099 + #define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A ++#define RX_HS_G4_ADAPT_INITIAL_CAP 0x009F + #define RX_MODE 0x00A1 + #define RX_HSRATE_SERIES 0x00A2 + #define RX_HSGEAR 0x00A3 +@@ -64,6 +70,7 @@ + #define CFGRXCDR8 0x00BA + #define CFGRXOVR8 0x00BD + #define CFGRXOVR6 0x00BF ++#define RX_FOM 0x00C2 + #define RXDIRECTCTRL2 0x00C7 + #define CFGRXOVR4 0x00E9 + #define RX_REFCLKFREQ 0x00EB +@@ -73,7 +80,6 @@ + #define ENARXDIRECTCFG3 0x00F3 + #define ENARXDIRECTCFG2 0x00F4 + +- + #define is_mphy_tx_attr(attr) (attr < RX_MODE) + #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) + #define SYNC_LEN_FINE(x) ((x) & 0x3F) +@@ -99,6 +105,18 @@ + + #define UNIPRO_CB_OFFSET(x) (0x8000 | x) + ++#define ADAPT_LENGTH_MASK 0x7F ++#define ADAPT_RANGE_BIT BIT(7) ++#define IS_ADAPT_RANGE_COARSE(x) ((x) & ADAPT_RANGE_BIT) ++ ++/* Adapt definitions */ ++#define ADAPT_LENGTH_MAX 0x91 ++#define ADAPT_L0L3_LENGTH_MAX 0x90 ++#define ADAPT_L0L1L2L3_LENGTH_MAX 0x8C ++#define TADAPT_FACTOR 650 ++#define TADAPT_L0L3_FACTOR (1 << 9) ++#define TADAPT_L0L1L2L3_FACTOR (1 << 15) ++ + /* + * PHY Adapter attributes + */ +@@ -164,10 +182,26 @@ + #define PA_PACPERRORCOUNT 0x15C1 + #define PA_PHYTESTCONTROL 0x15C2 + #define PA_TXHSG4SYNCLENGTH 0x15D0 ++#define PA_PEERRXHSG4ADAPTINITIAL 0x15D3 + #define PA_TXHSADAPTTYPE 0x15D4 + #define PA_TXHSG5SYNCLENGTH 0x15D6 ++#define PA_PEERRXHSG5ADAPTINITIAL 0x15D9 ++#define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3 0x15DE ++#define PA_PEERRXHSG6ADAPTINITIALL0L3 0x15DF ++#define PA_PEERRXHSG6ADAPTINITIALL0L1L2L3 0x15E0 ++#define PA_TXEQG1SETTING 0x15E1 ++#define PA_TXEQG2SETTING 0x15E2 ++#define PA_TXEQG3SETTING 0x15E3 ++#define PA_TXEQG4SETTING 0x15E4 ++#define PA_TXEQG5SETTING 0x15E5 ++#define PA_TXEQG6SETTING 0x15E6 ++#define PA_TXEQTRSETTING 0x15E7 ++#define PA_PEERTXEQTRSETTING 0x15E8 ++#define PA_PRECODEEN 0x15E9 ++#define PA_EQTR_GEAR 0x15EA ++#define PA_TXADAPTLENGTH_EQTR 0x15EB + +-/* Adpat type for PA_TXHSADAPTTYPE attribute */ ++/* Adapt type for PA_TXHSADAPTTYPE attribute */ + #define PA_REFRESH_ADAPT 0x00 + #define PA_INITIAL_ADAPT 0x01 + #define PA_NO_ADAPT 0x03 +@@ -187,6 +221,82 @@ + /* PHY Adapter Protocol Constants */ + #define PA_MAXDATALANES 4 + ++/* ++ * TX EQTR's minimum TAdapt should not be less than 10us. ++ * This value is rounded up into the nearest Unit Intervals (UI) ++ */ ++#define TX_EQTR_HS_G4_MIN_T_ADAPT 166400 ++#define TX_EQTR_HS_G5_MIN_T_ADAPT 332800 ++#define TX_EQTR_HS_G6_MIN_T_ADAPT 262144 ++ ++#define TX_EQTR_HS_G4_ADAPT_DEFAULT 0x88 ++#define TX_EQTR_HS_G5_ADAPT_DEFAULT 0x89 ++#define TX_EQTR_HS_G6_ADAPT_DEFAULT 0x89 ++ ++#define TX_EQTR_CAP_MASK 0x7F ++ ++#define TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT 8 ++#define TX_EQTR_ADAPT_RESERVED 0xFF ++ ++#define TX_HS_NUM_PRESHOOT 8 ++#define TX_HS_NUM_DEEMPHASIS 8 ++#define TX_HS_PRESHOOT_SHIFT 4 ++#define TX_HS_DEEMPHASIS_SHIFT 4 ++#define TX_HS_PRESHOOT_OFFSET 0 ++#define TX_HS_DEEMPHASIS_OFFSET 16 ++ ++#define TX_HS_PRESHOOT_LANE_SHIFT(lane) \ ++ (TX_HS_PRESHOOT_OFFSET + (lane) * TX_HS_PRESHOOT_SHIFT) ++#define TX_HS_DEEMPHASIS_LANE_SHIFT(lane) \ ++ (TX_HS_DEEMPHASIS_OFFSET + (lane) * TX_HS_DEEMPHASIS_SHIFT) ++ ++#define TX_HS_PRESHOOT_BITS(lane, val) \ ++ ((val) << TX_HS_PRESHOOT_LANE_SHIFT(lane)) ++#define TX_HS_DEEMPHASIS_BITS(lane, val) \ ++ ((val) << TX_HS_DEEMPHASIS_LANE_SHIFT(lane)) ++ ++#define RX_FOM_VALUE_MASK 0x7F ++#define RX_FOM_PRECODING_EN_BIT BIT(7) ++ ++#define PRECODEEN_TX_OFFSET 0 ++#define PRECODEEN_RX_OFFSET 4 ++#define PRECODEEN_TX_BIT(lane) (1 << (PRECODEEN_TX_OFFSET + (lane))) ++#define PRECODEEN_RX_BIT(lane) (1 << (PRECODEEN_RX_OFFSET + (lane))) ++ ++enum ufs_tx_eq_preset { ++ UFS_TX_EQ_PRESET_P0, ++ UFS_TX_EQ_PRESET_P1, ++ UFS_TX_EQ_PRESET_P2, ++ UFS_TX_EQ_PRESET_P3, ++ UFS_TX_EQ_PRESET_P4, ++ UFS_TX_EQ_PRESET_P5, ++ UFS_TX_EQ_PRESET_P6, ++ UFS_TX_EQ_PRESET_P7, ++ UFS_TX_EQ_PRESET_MAX, ++}; ++ ++enum ufs_tx_hs_preshoot { ++ UFS_TX_HS_PRESHOOT_DB_0P0, ++ UFS_TX_HS_PRESHOOT_DB_0P4, ++ UFS_TX_HS_PRESHOOT_DB_0P8, ++ UFS_TX_HS_PRESHOOT_DB_1P2, ++ UFS_TX_HS_PRESHOOT_DB_1P6, ++ UFS_TX_HS_PRESHOOT_DB_2P5, ++ UFS_TX_HS_PRESHOOT_DB_3P5, ++ UFS_TX_HS_PRESHOOT_DB_4P7, ++}; ++ ++enum ufs_tx_hs_deemphasis { ++ UFS_TX_HS_DEEMPHASIS_DB_0P0, ++ UFS_TX_HS_DEEMPHASIS_DB_0P8, ++ UFS_TX_HS_DEEMPHASIS_DB_1P6, ++ UFS_TX_HS_DEEMPHASIS_DB_2P5, ++ UFS_TX_HS_DEEMPHASIS_DB_3P5, ++ UFS_TX_HS_DEEMPHASIS_DB_4P7, ++ UFS_TX_HS_DEEMPHASIS_DB_6P0, ++ UFS_TX_HS_DEEMPHASIS_DB_7P6, ++}; ++ + #define DL_FC0ProtectionTimeOutVal_Default 8191 + #define DL_TC0ReplayTimeOutVal_Default 65535 + #define DL_AFC0ReqTimeOutVal_Default 32767 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux-lts/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch deleted file mode 100644 index de078902a8..0000000000 --- a/SPECS/linux-lts/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 39f4f9ff2f7384331b347a162c95587733dbc042 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 26 May 2026 15:22:58 -0400 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add Ziccrse - extension for X100 cores - -Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse -provides a forward progress guarantee on LR/SC sequences in main -memory regions with cacheability and coherence PMAs. - -The SpacemiT X100 core supports it per the SpacemiT K3 hardware -specification. - -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5b17612fe58e..ed046714a7ac 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -36,7 +36,7 @@ cpu_0: cpu@0 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -77,7 +77,7 @@ cpu_1: cpu@1 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -118,7 +118,7 @@ cpu_2: cpu@2 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -159,7 +159,7 @@ cpu_3: cpu@3 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -200,7 +200,7 @@ cpu_4: cpu@4 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -241,7 +241,7 @@ cpu_5: cpu@5 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -282,7 +282,7 @@ cpu_6: cpu@6 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -@@ -323,7 +323,7 @@ cpu_7: cpu@7 { - "zawrs", "zba", "zbb", "zbc", "zbs", "zca", - "zcb", "zcd", "zcmop", "zfa", "zfbfmin", - "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -- "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", - "zicond", "zicsr", "zifencei", "zihintntl", - "zihintpause", "zihpm", "zimop", "zkt", "zvbb", - "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", --- -2.53.0 - diff --git a/SPECS/linux-lts/0434-UPSTREAM-scsi-ufs-core-Add-debugfs-entries-for-TX-Eq.patch b/SPECS/linux-lts/0434-UPSTREAM-scsi-ufs-core-Add-debugfs-entries-for-TX-Eq.patch new file mode 100644 index 0000000000..f6dafbba18 --- /dev/null +++ b/SPECS/linux-lts/0434-UPSTREAM-scsi-ufs-core-Add-debugfs-entries-for-TX-Eq.patch @@ -0,0 +1,327 @@ +From 924b391d3abc1f92cc8dc08f5ed3c8976b083223 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:47 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add debugfs entries for TX + Equalization params + +Add debugfs support for UFS TX Equalization and UFS TX Equalization +Training (EQTR) to facilitate runtime inspection of link quality. These +entries allow developers to monitor and optimize TX Equalization parameters +and EQTR records during live operation. + +The debugfs entries are organized on a per-gear basis under the HBA's +debugfs root. Since TX EQTR is only defined for High Speed Gear 4 (HS-G4) +and above, EQTR-related entries are explicitly excluded for HS-G1 through +HS-G3 to avoid exposing unsupported attributes. + +The ufshcd's debugfs folder structure will look like below: + + /sys/kernel/debug/ufshcd/*ufs*/ + |--tx_eq_hs_gear1/ + | |--device_tx_eq_params + | |--host_tx_eq_params + |--tx_eq_hs_gear2/ + |--tx_eq_hs_gear3/ + |--tx_eq_hs_gear4/ + |--tx_eq_hs_gear5/ + |--tx_eq_hs_gear6/ + |--device_tx_eq_params + |--device_tx_eqtr_record + |--host_tx_eq_params + |--host_tx_eqtr_record + +Reviewed-by: Bart Van Assche +Reviewed-by: Bean Huo +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-6-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 10c40143f369a601cc54dd39777843e000b730a6) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-debugfs.c | 229 +++++++++++++++++++++++++++++++++ + drivers/ufs/core/ufs-txeq.c | 7 +- + drivers/ufs/core/ufshcd-priv.h | 2 + + 3 files changed, 237 insertions(+), 1 deletion(-) + +diff --git a/drivers/ufs/core/ufs-debugfs.c b/drivers/ufs/core/ufs-debugfs.c +index e3baed6c70bd..831758b45163 100644 +--- a/drivers/ufs/core/ufs-debugfs.c ++++ b/drivers/ufs/core/ufs-debugfs.c +@@ -209,6 +209,204 @@ static const struct ufs_debugfs_attr ufs_attrs[] = { + { } + }; + ++static int ufs_tx_eq_params_show(struct seq_file *s, void *data) ++{ ++ const char *file_name = s->file->f_path.dentry->d_name.name; ++ u32 gear = (u32)(uintptr_t)s->file->f_inode->i_private; ++ struct ufs_hba *hba = hba_from_file(s->file); ++ struct ufshcd_tx_eq_settings *settings; ++ struct ufs_pa_layer_attr *pwr_info; ++ struct ufshcd_tx_eq_params *params; ++ u32 rate = hba->pwr_info.hs_rate; ++ u32 num_lanes; ++ int lane; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return -EOPNOTSUPP; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) { ++ seq_printf(s, "Invalid gear selected: %u\n", gear); ++ return 0; ++ } ++ ++ if (!hba->max_pwr_info.is_valid) { ++ seq_puts(s, "Max power info is invalid\n"); ++ return 0; ++ } ++ ++ pwr_info = &hba->max_pwr_info.info; ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid) { ++ seq_printf(s, "TX EQ params are invalid for HS-G%u, Rate-%s\n", ++ gear, ufs_hs_rate_to_str(rate)); ++ return 0; ++ } ++ ++ if (strcmp(file_name, "host_tx_eq_params") == 0) { ++ settings = params->host; ++ num_lanes = pwr_info->lane_tx; ++ seq_printf(s, "Host TX EQ PreShoot Cap: 0x%02x, DeEmphasis Cap: 0x%02x\n", ++ hba->host_preshoot_cap, hba->host_deemphasis_cap); ++ } else if (strcmp(file_name, "device_tx_eq_params") == 0) { ++ settings = params->device; ++ num_lanes = pwr_info->lane_rx; ++ seq_printf(s, "Device TX EQ PreShoot Cap: 0x%02x, DeEmphasis Cap: 0x%02x\n", ++ hba->device_preshoot_cap, hba->device_deemphasis_cap); ++ } else { ++ return -ENOENT; ++ } ++ ++ seq_printf(s, "TX EQ setting for HS-G%u, Rate-%s:\n", gear, ++ ufs_hs_rate_to_str(rate)); ++ for (lane = 0; lane < num_lanes; lane++) ++ seq_printf(s, "TX Lane %d - PreShoot: %d, DeEmphasis: %d, Pre-Coding %senabled\n", ++ lane, settings[lane].preshoot, ++ settings[lane].deemphasis, ++ settings[lane].precode_en ? "" : "not "); ++ ++ return 0; ++} ++ ++static int ufs_tx_eq_params_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ufs_tx_eq_params_show, inode->i_private); ++} ++ ++static const struct file_operations ufs_tx_eq_params_fops = { ++ .owner = THIS_MODULE, ++ .open = ufs_tx_eq_params_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct ufs_debugfs_attr ufs_tx_eq_attrs[] = { ++ { "host_tx_eq_params", 0400, &ufs_tx_eq_params_fops }, ++ { "device_tx_eq_params", 0400, &ufs_tx_eq_params_fops }, ++ { } ++}; ++ ++static int ufs_tx_eqtr_record_show(struct seq_file *s, void *data) ++{ ++ const char *file_name = s->file->f_path.dentry->d_name.name; ++ u8 (*fom_array)[TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; ++ u32 gear = (u32)(uintptr_t)s->file->f_inode->i_private; ++ unsigned long preshoot_bitmap, deemphasis_bitmap; ++ struct ufs_hba *hba = hba_from_file(s->file); ++ struct ufs_pa_layer_attr *pwr_info; ++ struct ufshcd_tx_eq_params *params; ++ struct ufshcd_tx_eqtr_record *rec; ++ u32 rate = hba->pwr_info.hs_rate; ++ u8 preshoot, deemphasis; ++ u32 num_lanes; ++ char name[32]; ++ int lane; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return -EOPNOTSUPP; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) { ++ seq_printf(s, "Invalid gear selected: %u\n", gear); ++ return 0; ++ } ++ ++ if (!hba->max_pwr_info.is_valid) { ++ seq_puts(s, "Max power info is invalid\n"); ++ return 0; ++ } ++ ++ pwr_info = &hba->max_pwr_info.info; ++ params = &hba->tx_eq_params[gear - 1]; ++ if (!params->is_valid) { ++ seq_printf(s, "TX EQ params are invalid for HS-G%u, Rate-%s\n", ++ gear, ufs_hs_rate_to_str(rate)); ++ return 0; ++ } ++ ++ rec = params->eqtr_record; ++ if (!rec || !rec->last_record_index) { ++ seq_printf(s, "No TX EQTR records found for HS-G%u, Rate-%s.\n", ++ gear, ufs_hs_rate_to_str(rate)); ++ return 0; ++ } ++ ++ if (strcmp(file_name, "host_tx_eqtr_record") == 0) { ++ preshoot_bitmap = (hba->host_preshoot_cap << 0x1) | 0x1; ++ deemphasis_bitmap = (hba->host_deemphasis_cap << 0x1) | 0x1; ++ num_lanes = pwr_info->lane_tx; ++ fom_array = rec->host_fom; ++ snprintf(name, sizeof(name), "%s", "Host"); ++ } else if (strcmp(file_name, "device_tx_eqtr_record") == 0) { ++ preshoot_bitmap = (hba->device_preshoot_cap << 0x1) | 0x1; ++ deemphasis_bitmap = (hba->device_deemphasis_cap << 0x1) | 0x1; ++ num_lanes = pwr_info->lane_rx; ++ fom_array = rec->device_fom; ++ snprintf(name, sizeof(name), "%s", "Device"); ++ } else { ++ return -ENOENT; ++ } ++ ++ seq_printf(s, "%s TX EQTR record summary -\n", name); ++ seq_printf(s, "Target Power Mode: HS-G%u, Rate-%s\n", gear, ++ ufs_hs_rate_to_str(rate)); ++ seq_printf(s, "Most recent record index: %d\n", ++ rec->last_record_index); ++ seq_printf(s, "Most recent record timestamp: %llu us\n", ++ ktime_to_us(rec->last_record_ts)); ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ seq_printf(s, "\nTX Lane %d FOM - %s\n", lane, "PreShoot\\DeEmphasis"); ++ seq_puts(s, "\\"); ++ /* Print DeEmphasis header as X-axis. */ ++ for (deemphasis = 0; deemphasis < TX_HS_NUM_DEEMPHASIS; deemphasis++) ++ seq_printf(s, "%8d%s", deemphasis, " "); ++ seq_puts(s, "\n"); ++ /* Print matrix rows with PreShoot as Y-axis. */ ++ for (preshoot = 0; preshoot < TX_HS_NUM_PRESHOOT; preshoot++) { ++ seq_printf(s, "%d", preshoot); ++ for (deemphasis = 0; deemphasis < TX_HS_NUM_DEEMPHASIS; deemphasis++) { ++ if (test_bit(preshoot, &preshoot_bitmap) && ++ test_bit(deemphasis, &deemphasis_bitmap)) { ++ u8 fom = fom_array[lane][preshoot][deemphasis]; ++ u8 fom_val = fom & RX_FOM_VALUE_MASK; ++ bool precode_en = fom & RX_FOM_PRECODING_EN_BIT; ++ ++ if (ufshcd_is_txeq_presets_used(hba) && ++ !ufshcd_is_txeq_preset_selected(preshoot, deemphasis)) ++ seq_printf(s, "%8s%s", "-", " "); ++ else ++ seq_printf(s, "%8u%s", fom_val, ++ precode_en ? "*" : " "); ++ } else { ++ seq_printf(s, "%8s%s", "x", " "); ++ } ++ } ++ seq_puts(s, "\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int ufs_tx_eqtr_record_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ufs_tx_eqtr_record_show, inode->i_private); ++} ++ ++static const struct file_operations ufs_tx_eqtr_record_fops = { ++ .owner = THIS_MODULE, ++ .open = ufs_tx_eqtr_record_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct ufs_debugfs_attr ufs_tx_eqtr_attrs[] = { ++ { "host_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, ++ { "device_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, ++ { } ++}; ++ + void ufs_debugfs_hba_init(struct ufs_hba *hba) + { + const struct ufs_debugfs_attr *attr; +@@ -230,6 +428,37 @@ void ufs_debugfs_hba_init(struct ufs_hba *hba) + hba, &ee_usr_mask_fops); + debugfs_create_u32("exception_event_rate_limit_ms", 0600, hba->debugfs_root, + &hba->debugfs_ee_rate_limit_ms); ++ ++ if (!(hba->caps & UFSHCD_CAP_TX_EQUALIZATION)) ++ return; ++ ++ for (u32 gear = UFS_HS_G1; gear <= UFS_HS_GEAR_MAX; gear++) { ++ struct dentry *txeq_dir; ++ char name[32]; ++ ++ snprintf(name, sizeof(name), "tx_eq_hs_gear%d", gear); ++ txeq_dir = debugfs_create_dir(name, hba->debugfs_root); ++ if (IS_ERR_OR_NULL(txeq_dir)) ++ return; ++ ++ d_inode(txeq_dir)->i_private = hba; ++ ++ /* Create files for TX Equalization parameters */ ++ for (attr = ufs_tx_eq_attrs; attr->name; attr++) ++ debugfs_create_file(attr->name, attr->mode, txeq_dir, ++ (void *)(uintptr_t)gear, ++ attr->fops); ++ ++ /* TX EQTR is supported for HS-G4 and higher Gears */ ++ if (gear < UFS_HS_G4) ++ continue; ++ ++ /* Create files for TX EQTR related attributes */ ++ for (attr = ufs_tx_eqtr_attrs; attr->name; attr++) ++ debugfs_create_file(attr->name, attr->mode, txeq_dir, ++ (void *)(uintptr_t)gear, ++ attr->fops); ++ } + } + + void ufs_debugfs_hba_exit(struct ufs_hba *hba) +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +index 04f9f1ffa43e..b68a7af78290 100644 +--- a/drivers/ufs/core/ufs-txeq.c ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -375,7 +375,12 @@ static int ufshcd_get_rx_fom(struct ufs_hba *hba, + return ret; + } + +-static bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis) ++bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba) ++{ ++ return use_txeq_presets; ++} ++ ++bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis) + { + int i; + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index fbcea20c8991..671f33d153b0 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -109,6 +109,8 @@ void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba); + int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, + struct ufs_pa_layer_attr *pwr_mode); + void ufshcd_print_tx_eq_params(struct ufs_hba *hba); ++bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba); ++bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis); + + /* Wrapper functions for safely calling variant operations */ + static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux-lts/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch deleted file mode 100644 index 3c0a31840b..0000000000 --- a/SPECS/linux-lts/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 5bf0a7bd6d1da26628096529743d98bfd1be37e1 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 28 May 2026 19:38:39 +0800 -Subject: [RUYI PATCH] FROMLIST: RISC-V: KVM: Enhance the logging check for mmu - mapping - -When enabling dirty ring, the dirty bitmap is disable, and the logging -check is always false as the RISC-V architecture does not select -"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded -since the write path already trying to add the dirty log, the logic for -logging check is broken and some side effect will occurs. - -Enhance the logging check for mmu mapping so it can check both the dirty -ring and the dirty bitmap. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/kvm/mmu.c | 9 ++++----- - 1 file changed, 4 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c -index 58f5f3536ffd..a0d9c113258e 100644 ---- a/arch/riscv/kvm/mmu.c -+++ b/arch/riscv/kvm/mmu.c -@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, - enum kvm_mr_change change) - { - /* -- * At this point memslot has been committed and there is an -- * allocated dirty_bitmap[], dirty pages will be tracked while -- * the memory slot is write protected. -+ * At this point memslot has been committed and dirty pages will be -+ * tracked while the memory slot is write protected. - */ - if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) - mmu_wp_memory_region(kvm, new->id); -@@ -314,8 +313,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, - struct vm_area_struct *vma; - struct kvm *kvm = vcpu->kvm; - struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; -- bool logging = (memslot->dirty_bitmap && -- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; -+ bool logging = kvm_slot_dirty_track_enabled(memslot) && -+ !(memslot->flags & KVM_MEM_READONLY); - unsigned long vma_pagesize, mmu_seq; - struct kvm_gstage gstage; - struct page *page; --- -2.53.0 - diff --git a/SPECS/linux-lts/0435-UPSTREAM-scsi-ufs-core-Add-helpers-to-pause-and-resu.patch b/SPECS/linux-lts/0435-UPSTREAM-scsi-ufs-core-Add-helpers-to-pause-and-resu.patch new file mode 100644 index 0000000000..2694528bdd --- /dev/null +++ b/SPECS/linux-lts/0435-UPSTREAM-scsi-ufs-core-Add-helpers-to-pause-and-resu.patch @@ -0,0 +1,99 @@ +From b7110bcf92d44cdc75ad9e168c735756d83d118d Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:48 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add helpers to pause and + resume command processing + +In preparation for supporting TX Equalization refreshing, introduce helper +functions to safely pause and resume command processing. + +ufshcd_pause_command_processing() ensures the host is in a quiescent state +by stopping the block layer tagset, acquiring the necessary locks +(scan_mutex and clk_scaling_lock), and waiting for any in-flight commands +to complete within a specified timeout. + +ufshcd_resume_command_processing() restores the host to its previous +operational state by reversing these steps in the correct order. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-7-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit dc5dcac5327832bffc1971b1445553823bdebc08) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufshcd-priv.h | 2 ++ + drivers/ufs/core/ufshcd.c | 42 ++++++++++++++++++++++++++++++++++ + 2 files changed, 44 insertions(+) + +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 671f33d153b0..6ff4badba0f2 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -79,6 +79,8 @@ int ufshcd_mcq_abort(struct scsi_cmnd *cmd); + int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag); + void ufshcd_release_scsi_cmd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp); ++int ufshcd_pause_command_processing(struct ufs_hba *hba, u64 timeout_us); ++void ufshcd_resume_command_processing(struct ufs_hba *hba); + + /** + * enum ufs_descr_fmt - UFS string descriptor format +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 51e431a04ee4..5f75f95957a4 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -1361,6 +1361,48 @@ static int ufshcd_wait_for_pending_cmds(struct ufs_hba *hba, + return ret; + } + ++/** ++ * ufshcd_pause_command_processing - Pause command processing ++ * @hba: per-adapter instance ++ * @timeout_us: timeout in microseconds to wait for pending commands to finish ++ * ++ * This function stops new command submissions and waits for existing commands ++ * to complete. ++ * ++ * Return: 0 on success, %-EBUSY if commands did not finish within @timeout_us. ++ * On failure, all acquired locks are released and the tagset is unquiesced. ++ */ ++int ufshcd_pause_command_processing(struct ufs_hba *hba, u64 timeout_us) ++{ ++ int ret = 0; ++ ++ mutex_lock(&hba->host->scan_mutex); ++ blk_mq_quiesce_tagset(&hba->host->tag_set); ++ down_write(&hba->clk_scaling_lock); ++ ++ if (ufshcd_wait_for_pending_cmds(hba, timeout_us)) { ++ ret = -EBUSY; ++ up_write(&hba->clk_scaling_lock); ++ blk_mq_unquiesce_tagset(&hba->host->tag_set); ++ mutex_unlock(&hba->host->scan_mutex); ++ } ++ ++ return ret; ++} ++ ++/** ++ * ufshcd_resume_command_processing - Resume command processing ++ * @hba: per-adapter instance ++ * ++ * This function resumes command submissions. ++ */ ++void ufshcd_resume_command_processing(struct ufs_hba *hba) ++{ ++ up_write(&hba->clk_scaling_lock); ++ blk_mq_unquiesce_tagset(&hba->host->tag_set); ++ mutex_unlock(&hba->host->scan_mutex); ++} ++ + /** + * ufshcd_scale_gear - scale up/down UFS gear + * @hba: per adapter instance +-- +2.53.0 + diff --git a/SPECS/linux-lts/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux-lts/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch deleted file mode 100644 index 3af359443c..0000000000 --- a/SPECS/linux-lts/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 1089052df50a4781f12e65e68f2cfeb75dca9d84 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 2 Jun 2026 18:00:00 +0800 -Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi - R2S - -Enable the two RTL8125 network controllers and corresponding -PHYs connected via the PCIe controllers on the OrangePi R2S. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ - 1 file changed, 38 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index b13a8d6a2670..919e5b451109 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -23,6 +23,14 @@ chosen { - stdout-path = "serial0"; - }; - -+ pcie_vcc3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - vcc4v0: regulator-vcc4v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc4v0"; -@@ -228,6 +236,36 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie2 { -+ status = "okay"; -+}; -+ - &pdma { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0436-UPSTREAM-scsi-ufs-core-Add-support-to-retrain-TX-Equ.patch b/SPECS/linux-lts/0436-UPSTREAM-scsi-ufs-core-Add-support-to-retrain-TX-Equ.patch new file mode 100644 index 0000000000..27e31c0520 --- /dev/null +++ b/SPECS/linux-lts/0436-UPSTREAM-scsi-ufs-core-Add-support-to-retrain-TX-Equ.patch @@ -0,0 +1,390 @@ +From fbdcf3ab4ffed53e1826cd4abfb673fb3b5288f7 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:49 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: core: Add support to retrain TX + Equalization via debugfs + +Drastic environmental changes, such as significant temperature shifts, can +impact link signal integrity. In such cases, retraining TX Equalization is +necessary to compensate for these environmental changes. + +Add a debugfs entry, 'tx_eq_ctrl', to allow userspace to manually trigger +the TX Equalization training (EQTR) procedure and apply the identified +optimal settings on the fly. These entries are created on a per-gear basis +for High Speed Gear 4 (HS-G4) and above, as TX EQTR is not supported for +lower gears. + +The 'tx_eq_ctrl' entry currently accepts the 'retrain' command to initiate +the procedure. The interface is designed to be scalable to support +additional commands in the future. + +Reading the 'tx_eq_ctrl' entry provides a usage hint to the user, ensuring +the interface is self-documenting. + +The ufshcd's debugfs folder structure will look like below: + + /sys/kernel/debug/ufshcd/*ufs*/ + |--tx_eq_hs_gear1/ + | |--device_tx_eq_params + | |--host_tx_eq_params + |--tx_eq_hs_gear2/ + |--tx_eq_hs_gear3/ + |--tx_eq_hs_gear4/ + |--tx_eq_hs_gear5/ + |--tx_eq_hs_gear6/ + |--device_tx_eq_params + |--device_tx_eqtr_record + |--host_tx_eq_params + |--host_tx_eqtr_record + |--tx_eq_ctrl + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-8-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit adbabdcf0db0f929e642f95d7528dce0f6bd3a11) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-debugfs.c | 61 ++++++++++++++++++ + drivers/ufs/core/ufs-txeq.c | 110 +++++++++++++++++++++++++++++++-- + drivers/ufs/core/ufshcd-priv.h | 5 +- + drivers/ufs/core/ufshcd.c | 7 +-- + include/ufs/ufshcd.h | 2 + + 5 files changed, 175 insertions(+), 10 deletions(-) + +diff --git a/drivers/ufs/core/ufs-debugfs.c b/drivers/ufs/core/ufs-debugfs.c +index 831758b45163..e3dd81d6fe82 100644 +--- a/drivers/ufs/core/ufs-debugfs.c ++++ b/drivers/ufs/core/ufs-debugfs.c +@@ -401,9 +401,70 @@ static const struct file_operations ufs_tx_eqtr_record_fops = { + .release = single_release, + }; + ++static ssize_t ufs_tx_eq_ctrl_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ u32 gear = (u32)(uintptr_t)file->f_inode->i_private; ++ struct ufs_hba *hba = hba_from_file(file); ++ char kbuf[32]; ++ int ret; ++ ++ if (count >= sizeof(kbuf)) ++ return -EINVAL; ++ ++ if (copy_from_user(kbuf, buf, count)) ++ return -EFAULT; ++ ++ if (!ufshcd_is_tx_eq_supported(hba)) ++ return -EOPNOTSUPP; ++ ++ if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || ++ !hba->max_pwr_info.is_valid) ++ return -EBUSY; ++ ++ if (!hba->ufs_device_wlun) ++ return -ENODEV; ++ ++ kbuf[count] = '\0'; ++ ++ if (sysfs_streq(kbuf, "retrain")) { ++ ret = ufs_debugfs_get_user_access(hba); ++ if (ret) ++ return ret; ++ ret = ufshcd_retrain_tx_eq(hba, gear); ++ ufs_debugfs_put_user_access(hba); ++ } else { ++ /* Unknown operation */ ++ return -EINVAL; ++ } ++ ++ return ret ? ret : count; ++} ++ ++static int ufs_tx_eq_ctrl_show(struct seq_file *s, void *data) ++{ ++ seq_puts(s, "write 'retrain' to retrain TX Equalization settings\n"); ++ return 0; ++} ++ ++static int ufs_tx_eq_ctrl_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ufs_tx_eq_ctrl_show, inode->i_private); ++} ++ ++static const struct file_operations ufs_tx_eq_ctrl_fops = { ++ .owner = THIS_MODULE, ++ .open = ufs_tx_eq_ctrl_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = ufs_tx_eq_ctrl_write, ++ .release = single_release, ++}; ++ + static const struct ufs_debugfs_attr ufs_tx_eqtr_attrs[] = { + { "host_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, + { "device_tx_eqtr_record", 0400, &ufs_tx_eqtr_record_fops }, ++ { "tx_eq_ctrl", 0600, &ufs_tx_eq_ctrl_fops }, + { } + }; + +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +index b68a7af78290..3a879c644faa 100644 +--- a/drivers/ufs/core/ufs-txeq.c ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -628,9 +628,15 @@ static int ufshcd_setup_tx_eqtr_adapt_length(struct ufs_hba *hba, + struct ufshcd_tx_eq_params *params, + u32 gear) + { ++ struct ufshcd_tx_eqtr_record *rec = params->eqtr_record; + u32 adapt_eqtr; + int ret; + ++ if (rec && rec->saved_adapt_eqtr) { ++ adapt_eqtr = rec->saved_adapt_eqtr; ++ goto set_adapt_eqtr; ++ } ++ + if (gear == UFS_HS_G4 || gear == UFS_HS_G5) { + u64 t_adapt, t_adapt_local, t_adapt_peer; + u32 adapt_cap_local, adapt_cap_peer, adapt_length; +@@ -782,6 +788,10 @@ static int ufshcd_setup_tx_eqtr_adapt_length(struct ufs_hba *hba, + return -EINVAL; + } + ++ if (rec) ++ rec->saved_adapt_eqtr = (u16)adapt_eqtr; ++ ++set_adapt_eqtr: + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXADAPTLENGTH_EQTR), adapt_eqtr); + if (ret) + dev_err(hba->dev, "Failed to set adapt length for TX EQTR: %d\n", ret); +@@ -847,16 +857,33 @@ static int ufshcd_apply_tx_eqtr_settings(struct ufs_hba *hba, + /** + * ufshcd_update_tx_eq_params - Update TX Equalization params + * @params: TX EQ parameters data structure ++ * @pwr_mode: target power mode containing gear and rate + * @eqtr_data: TX EQTR data structure + * +- * Update TX Equalization params using results from TX EQTR data. ++ * Update TX Equalization params using results from TX EQTR data. Check also ++ * the TX EQTR FOM value for each TX lane in the TX EQTR data. If a TX lane got ++ * a FOM value of 0, restore the TX Equalization settings from the last known ++ * valid TX Equalization params for that specific TX lane. + */ + static inline void + ufshcd_update_tx_eq_params(struct ufshcd_tx_eq_params *params, ++ struct ufs_pa_layer_attr *pwr_mode, + struct ufshcd_tx_eqtr_data *eqtr_data) + { + struct ufshcd_tx_eqtr_record *rec = params->eqtr_record; + ++ if (params->is_valid) { ++ int lane; ++ ++ for (lane = 0; lane < pwr_mode->lane_tx; lane++) ++ if (eqtr_data->host[lane].fom_val == 0) ++ eqtr_data->host[lane] = params->host[lane]; ++ ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) ++ if (eqtr_data->device[lane].fom_val == 0) ++ eqtr_data->device[lane] = params->device[lane]; ++ } ++ + memcpy(params->host, eqtr_data->host, sizeof(params->host)); + memcpy(params->device, eqtr_data->device, sizeof(params->device)); + +@@ -955,7 +982,7 @@ static int __ufshcd_tx_eqtr(struct ufs_hba *hba, + dev_info(hba->dev, "TX EQTR procedure completed! Time elapsed: %llu ms\n", + ktime_to_ms(ktime_sub(ktime_get(), start))); + +- ufshcd_update_tx_eq_params(params, eqtr_data); ++ ufshcd_update_tx_eq_params(params, pwr_mode, eqtr_data); + + return ret; + } +@@ -1079,6 +1106,7 @@ static int ufshcd_tx_eqtr(struct ufs_hba *hba, + * ufshcd_config_tx_eq_settings - Configure TX Equalization settings + * @hba: per adapter instance + * @pwr_mode: target power mode containing gear and rate information ++ * @force_tx_eqtr: execute the TX EQTR procedure + * + * This function finds and sets the TX Equalization settings for the given + * target power mode. +@@ -1086,7 +1114,8 @@ static int ufshcd_tx_eqtr(struct ufs_hba *hba, + * Returns 0 on success, error code otherwise + */ + int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode) ++ struct ufs_pa_layer_attr *pwr_mode, ++ bool force_tx_eqtr) + { + struct ufshcd_tx_eq_params *params; + u32 gear, rate; +@@ -1123,7 +1152,7 @@ int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, + } + + params = &hba->tx_eq_params[gear - 1]; +- if (!params->is_valid) { ++ if (!params->is_valid || force_tx_eqtr) { + int ret; + + ret = ufshcd_tx_eqtr(hba, params, pwr_mode); +@@ -1189,3 +1218,76 @@ void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba) + } + } + } ++ ++/** ++ * ufshcd_retrain_tx_eq - Retrain TX Equalization and apply new settings ++ * @hba: per-adapter instance ++ * @gear: target High-Speed (HS) gear for retraining ++ * ++ * This function initiates a refresh of the TX Equalization settings for a ++ * specific HS gear. It scales the clocks to maximum frequency, negotiates the ++ * power mode with the device, retrains TX EQ and applies new TX EQ settings ++ * by conducting a Power Mode change. ++ * ++ * Returns 0 on success, non-zero error code otherwise ++ */ ++int ufshcd_retrain_tx_eq(struct ufs_hba *hba, u32 gear) ++{ ++ struct ufs_pa_layer_attr new_pwr_info, final_params = {}; ++ int ret; ++ ++ if (!ufshcd_is_tx_eq_supported(hba) || !use_adaptive_txeq) ++ return -EOPNOTSUPP; ++ ++ if (gear < adaptive_txeq_gear) ++ return -ERANGE; ++ ++ ufshcd_hold(hba); ++ ++ ret = ufshcd_pause_command_processing(hba, 1 * USEC_PER_SEC); ++ if (ret) { ++ ufshcd_release(hba); ++ return ret; ++ } ++ ++ /* scale up clocks to max frequency before TX EQTR */ ++ if (ufshcd_is_clkscaling_supported(hba)) ++ ufshcd_scale_clks(hba, ULONG_MAX, true); ++ ++ new_pwr_info = hba->pwr_info; ++ new_pwr_info.gear_tx = gear; ++ new_pwr_info.gear_rx = gear; ++ ++ ret = ufshcd_vops_negotiate_pwr_mode(hba, &new_pwr_info, &final_params); ++ if (ret) ++ memcpy(&final_params, &new_pwr_info, sizeof(final_params)); ++ ++ if (final_params.gear_tx != gear) { ++ dev_err(hba->dev, "Negotiated Gear (%u) does not match target Gear (%u)\n", ++ final_params.gear_tx, gear); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = ufshcd_config_tx_eq_settings(hba, &final_params, true); ++ if (ret) { ++ dev_err(hba->dev, "Failed to config TX Equalization for HS-G%u, Rate-%s: %d\n", ++ final_params.gear_tx, ++ ufs_hs_rate_to_str(final_params.hs_rate), ret); ++ goto out; ++ } ++ ++ /* Change Power Mode to apply the new TX EQ settings */ ++ ret = ufshcd_change_power_mode(hba, &final_params, ++ UFSHCD_PMC_POLICY_FORCE); ++ if (ret) ++ dev_err(hba->dev, "%s: Failed to change Power Mode to HS-G%u, Rate-%s: %d\n", ++ __func__, final_params.gear_tx, ++ ufs_hs_rate_to_str(final_params.hs_rate), ret); ++ ++out: ++ ufshcd_resume_command_processing(hba); ++ ufshcd_release(hba); ++ ++ return ret; ++} +diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h +index 6ff4badba0f2..dcff75f75dac 100644 +--- a/drivers/ufs/core/ufshcd-priv.h ++++ b/drivers/ufs/core/ufshcd-priv.h +@@ -81,6 +81,7 @@ void ufshcd_release_scsi_cmd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp); + int ufshcd_pause_command_processing(struct ufs_hba *hba, u64 timeout_us); + void ufshcd_resume_command_processing(struct ufs_hba *hba); ++int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, bool scale_up); + + /** + * enum ufs_descr_fmt - UFS string descriptor format +@@ -109,10 +110,12 @@ int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id); + int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear); + void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba); + int ufshcd_config_tx_eq_settings(struct ufs_hba *hba, +- struct ufs_pa_layer_attr *pwr_mode); ++ struct ufs_pa_layer_attr *pwr_mode, ++ bool force_tx_eqtr); + void ufshcd_print_tx_eq_params(struct ufs_hba *hba); + bool ufshcd_is_txeq_presets_used(struct ufs_hba *hba); + bool ufshcd_is_txeq_preset_selected(u8 preshoot, u8 deemphasis); ++int ufshcd_retrain_tx_eq(struct ufs_hba *hba, u32 gear); + + /* Wrapper functions for safely calling variant operations */ + static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) +diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c +index 5f75f95957a4..1686bb5630d4 100644 +--- a/drivers/ufs/core/ufshcd.c ++++ b/drivers/ufs/core/ufshcd.c +@@ -330,8 +330,6 @@ static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); + static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); + static void ufshcd_resume_clkscaling(struct ufs_hba *hba); + static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); +-static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, +- bool scale_up); + static irqreturn_t ufshcd_intr(int irq, void *__hba); + static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); + static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); +@@ -1207,8 +1205,7 @@ static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) + * + * Return: 0 if successful; < 0 upon failure. + */ +-static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, +- bool scale_up) ++int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, bool scale_up) + { + int ret = 0; + ktime_t start = ktime_get(); +@@ -4896,7 +4893,7 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba, + memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); + } + +- ret = ufshcd_config_tx_eq_settings(hba, &final_params); ++ ret = ufshcd_config_tx_eq_settings(hba, &final_params, false); + if (ret) + dev_warn(hba->dev, "Failed to configure TX Equalization for HS-G%u, Rate-%s: %d\n", + final_params.gear_tx, +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 77634e07cbb3..8bb279c0e992 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -346,12 +346,14 @@ struct ufshcd_tx_eqtr_data { + * @device_fom: Device TX EQTR FOM record + * @last_record_ts: Timestamp of the most recent TX EQTR record + * @last_record_index: Index of the most recent TX EQTR record ++ * @saved_adapt_eqtr: Saved Adaptation length setting for TX EQTR + */ + struct ufshcd_tx_eqtr_record { + u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; + u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS]; + ktime_t last_record_ts; + u16 last_record_index; ++ u16 saved_adapt_eqtr; + }; + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch b/SPECS/linux-lts/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch deleted file mode 100644 index 0150c1e446..0000000000 --- a/SPECS/linux-lts/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 63031abd1c4c52dfc3b406612721eff99c69ed49 Mon Sep 17 00:00:00 2001 -From: Wang Yechao -Date: Thu, 4 Jun 2026 14:55:10 +0800 -Subject: [RUYI PATCH] FROMLIST: iommu/riscv: Add dependency between iommu and - devices - -Commit 9156585280f1 ("ACPI: RIMT: Add dependency between iommu and -devices") adds the dependency between iommu and devices on ACPI -systems. On devicetree systems, the incorrect removal order also -occurs. - -It can be reproduced on the QEMU RISC-V machine if the kernel enables -IOMMU_DMA: - -[ 635.081530] e1000e: EEE TX LPI TIMER: 00000000 -[ 656.100306] rcu: INFO: rcu_sched self-detected stall on CPU -[ 656.101374] rcu: 5-....: (5250 ticks this GP) idle=d774/1/0x4000000000000000 softirq=5173/5185 fqs=2625 -[ 656.102237] rcu: (t=5251 jiffies g=36825 q=101 ncpus=16) -[ 656.103801] CPU: 5 UID: 0 PID: 1958 Comm: reboot Tainted: G W 7.1.0-rc5 #31 PREEMPTLAZY -[ 656.104127] Tainted: [W]=WARN -[ 656.104182] Hardware name: QEMU QEMU Virtual Machine, BIOS 2.7 02/02/2022 -[ 656.104339] epc : riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 -[ 656.105352] ra : riscv_iommu_cmd_sync.constprop.0+0xa8/0x148 -[ 656.105433] epc : ffffffff807ca980 ra : ffffffff807ca970 sp : ff60000085dbf960 -[ 656.105475] gp : ffffffff81e0d798 tp : ff60000084b58e00 t0 : ffffffff80021048 -[ 656.105514] t1 : ff60000081b18400 t2 : 45203a6530303031 s0 : ff60000085dbf9c0 -[ 656.105554] s1 : 00000098c92a567c a0 : 00000098c03986f0 a1 : ff60000085dbf970 -[ 656.105594] a2 : 000024bb5cac6aee a3 : ff200000004f1000 a4 : ff6000008140a040 -[ 656.105632] a5 : 0000000000000669 a6 : 0000000000000000 a7 : 00000000ffffa000 -[ 656.105669] s2 : 0000000000000000 s3 : 00000098c0398308 s4 : 000000000000066a -[ 656.105706] s5 : 0000000008f0d180 s6 : 000000a8d08b8de9 s7 : 0000000000001fff -[ 656.105743] s8 : ff6000008140a040 s9 : ff6000008484cb00 s10: ff200000005cc000 -[ 656.105781] s11: ff600000814652a0 t3 : 000000f000000000 t4 : 0000000000000000 -[ 656.105845] t5 : 0000000000000003 t6 : ff600000841666b0 ssp : 0000000000000000 -[ 656.105883] status: 0000000200000120 badaddr: 0000000000000000 cause: 8000000000000005 -[ 656.106072] riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 -[ 656.106321] riscv_iommu_iotlb_inval+0x120/0x160 -[ 656.106373] riscv_iommu_iotlb_sync+0x48/0x60 -[ 656.106422] __iommu_dma_unmap+0xca/0xf8 -[ 656.106470] iommu_dma_unmap_phys+0x58/0xc8 -[ 656.106517] dma_unmap_phys+0x15c/0x248 -[ 656.106564] dma_unmap_page_attrs+0x1e/0x30 -[ 656.106915] e1000_clean_rx_ring+0x1d2/0x200 [e1000e] -[ 656.107668] e1000e_down+0x168/0x1c8 [e1000e] -[ 656.107995] e1000e_pm_freeze+0x94/0x128 [e1000e] -[ 656.108328] e1000_shutdown+0x28/0x48 [e1000e] -[ 656.108652] pci_device_shutdown+0x34/0x48 -[ 656.108706] device_shutdown+0x104/0x1e8 -[ 656.108752] kernel_restart+0x46/0xb8 -[ 656.108797] __do_sys_reboot+0xc0/0x1c8 -[ 656.108840] __riscv_sys_reboot+0x22/0x38 -[ 656.108882] do_trap_ecall_u+0x236/0x3f8 -[ 656.108947] handle_exception+0x15a/0x166 - -So move the device link into the iommu driver to fix both ACPI and -devicetree systems. - -Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") -Signed-off-by: Wang Yechao -Link: https://lore.kernel.org/r/20260604145510898G2kTwM2Pr25QE5H8T4Wh6@zte.com.cn -Signed-off-by: Han Gao ---- - drivers/acpi/riscv/rimt.c | 7 ------- - drivers/iommu/riscv/iommu.c | 7 +++++++ - 2 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c -index 8eaa8731bddd..7f423405e5ef 100644 ---- a/drivers/acpi/riscv/rimt.c -+++ b/drivers/acpi/riscv/rimt.c -@@ -263,13 +263,6 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 - if (!rimt_fwnode) - return -EPROBE_DEFER; - -- /* -- * EPROBE_DEFER ensures IOMMU is probed before the devices that -- * depend on them. During shutdown, however, the IOMMU may be removed -- * first, leading to issues. To avoid this, a device link is added -- * which enforces the correct removal order. -- */ -- device_link_add(dev, rimt_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); - return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode); - } - -diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c -index de286563bd44..07ae3c4ec38e 100644 ---- a/drivers/iommu/riscv/iommu.c -+++ b/drivers/iommu/riscv/iommu.c -@@ -1598,6 +1598,13 @@ static struct iommu_device *riscv_iommu_probe_device(struct device *dev) - - dev_iommu_priv_set(dev, info); - -+ /* -+ * During shutdown, however, the IOMMU may be removed first, leading -+ * to issues. To avoid this, a device link is added which enforces -+ * the correct removal order. -+ */ -+ device_link_add(dev, fwspec->iommu_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); -+ - return &iommu->iommu; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0437-UPSTREAM-scsi-ufs-ufs-qcom-Fixup-PAM-4-TX-L0_L1_L2_L.patch b/SPECS/linux-lts/0437-UPSTREAM-scsi-ufs-ufs-qcom-Fixup-PAM-4-TX-L0_L1_L2_L.patch new file mode 100644 index 0000000000..cb35bed61c --- /dev/null +++ b/SPECS/linux-lts/0437-UPSTREAM-scsi-ufs-ufs-qcom-Fixup-PAM-4-TX-L0_L1_L2_L.patch @@ -0,0 +1,235 @@ +From d1c820cddd79d0e3c2a54ce0cb201d451088a0bf Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:50 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Fixup PAM-4 TX + L0_L1_L2_L3 adaptation pattern length + +If HS-G6 Power Mode change handshake is successful and outbound data Lanes +are expected to transmit ADAPT, M-TX Lanes shall be configured as + + if (Adapt Type == REFRESH) + TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 = PA_PeerRxHsG6AdaptRefreshL0L1L2L3. + else if (Adapt Type == INITIAL) + TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 = PA_PeerRxHsG6AdaptInitialL0L1L2L3. + +On some platforms, the ADAPT_L0_L1_L2_L3 duration on Host TX Lanes is only +a half of theoretical ADAPT_L0_L1_L2_L3 duration TADAPT_L0_L1_L2_L3 (in +PAM-4 UI) calculated from TX_HS_ADAPT_LENGTH_L0_L1_L2_L3. + +For such platforms, the workaround is to double the ADAPT_L0_L1_L2_L3 +duration by uplifting TX_HS_ADAPT_LENGTH_L0_L1_L2_L3. UniPro initializes +TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 during HS-G6 Power Mode change handshake, it +would be too late for SW to update TX_HS_ADAPT_LENGTH_L0_L1_L2_L3 post +HS-G6 Power Mode change. Update PA_PeerRxHsG6AdaptRefreshL0L1L2L3 and +PA_PeerRxHsG6AdaptInitialL0L1L2L3 post Link Startup and before HS-G6 Power +Mode change, so that the UniPro would use the updated value during HS-G6 +Power Mode change handshake. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-9-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 53c94067efa252e20f813c6eb714dc1cddf06aaa) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 178 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 178 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index fec0ecad6be1..f6ba37e1a931 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -1020,10 +1020,188 @@ static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) + dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); + } + ++/** ++ * ufs_qcom_double_t_adapt_l0l1l2l3 - Create a new adapt that doubles the ++ * adaptation duration TADAPT_L0_L1_L2_L3 derived from the old adapt. ++ * ++ * @old_adapt: Original ADAPT_L0_L1_L2_L3 capability ++ * ++ * ADAPT_length_L0_L1_L2_L3 formula from M-PHY spec: ++ * if (ADAPT_range_L0_L1_L2_L3 == COARSE) { ++ * ADAPT_length_L0_L1_L2_L3 = [0, 12] ++ * ADAPT_L0_L1_L2_L3 = 215 x 2^ADAPT_length_L0_L1_L2_L3 ++ * } else if (ADAPT_range_L0_L1_L2_L3 == FINE) { ++ * ADAPT_length_L0_L1_L2_L3 = [0, 127] ++ * TADAPT_L0_L1_L2_L3 = 215 x (ADAPT_length_L0_L1_L2_L3 + 1) ++ * } ++ * ++ * To double the adaptation duration TADAPT_L0_L1_L2_L3: ++ * 1. If adapt range is COARSE (1'b1), new adapt = old adapt + 1. ++ * 2. If adapt range is FINE (1'b0): ++ * a) If old adapt length is < 64, (new adapt + 1) = 2 * (old adapt + 1). ++ * b) If old adapt length is >= 64, set new adapt to 0x88 using COARSE ++ * range, because new adapt get from equation in a) shall exceed 127. ++ * ++ * Examples: ++ * ADAPT_range_L0_L1_L2_L3 | ADAPT_length_L0_L1_L2_L3 | TADAPT_L0_L1_L2_L3 (PAM-4 UI) ++ * 0 3 131072 ++ * 0 7 262144 ++ * 0 63 2097152 ++ * 0 64 2129920 ++ * 0 127 4194304 ++ * 1 8 8388608 ++ * 1 9 16777216 ++ * 1 10 33554432 ++ * 1 11 67108864 ++ * 1 12 134217728 ++ * ++ * Return: new adapt. ++ */ ++static u32 ufs_qcom_double_t_adapt_l0l1l2l3(u32 old_adapt) ++{ ++ u32 adapt_length = old_adapt & ADAPT_LENGTH_MASK; ++ u32 new_adapt; ++ ++ if (IS_ADAPT_RANGE_COARSE(old_adapt)) { ++ new_adapt = (adapt_length + 1) | ADAPT_RANGE_BIT; ++ } else { ++ if (adapt_length < 64) ++ new_adapt = (adapt_length << 1) + 1; ++ else ++ /* ++ * 0x88 is the very coarse Adapt value which is two ++ * times of the largest fine Adapt value (0x7F) ++ */ ++ new_adapt = 0x88; ++ } ++ ++ return new_adapt; ++} ++ ++static void ufs_qcom_limit_max_gear(struct ufs_hba *hba, ++ enum ufs_hs_gear_tag gear) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ struct ufs_host_params *host_params = &host->host_params; ++ ++ host_params->hs_tx_gear = gear; ++ host_params->hs_rx_gear = gear; ++ pwr_info->gear_tx = gear; ++ pwr_info->gear_rx = gear; ++ ++ dev_warn(hba->dev, "Limited max gear of host and device to HS-G%d\n", gear); ++} ++ ++static void ufs_qcom_fixup_tx_adapt_l0l1l2l3(struct ufs_hba *hba) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; ++ struct ufs_host_params *host_params = &host->host_params; ++ u32 old_adapt, new_adapt, actual_adapt; ++ bool limit_speed = false; ++ int err; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 || ++ host_params->hs_tx_gear <= UFS_HS_G5 || ++ pwr_info->gear_tx <= UFS_HS_G5) ++ return; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), &old_adapt); ++ if (err) ++ goto out; ++ ++ if (old_adapt > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "PA_PeerRxHsG6AdaptInitialL0L1L2L3 value (0x%x) exceeds MAX\n", ++ old_adapt); ++ err = -ERANGE; ++ goto out; ++ } ++ ++ new_adapt = ufs_qcom_double_t_adapt_l0l1l2l3(old_adapt); ++ dev_dbg(hba->dev, "Original PA_PeerRxHsG6AdaptInitialL0L1L2L3 = 0x%x, new value = 0x%x\n", ++ old_adapt, new_adapt); ++ ++ /* ++ * 0x8C is the max possible value allowed by UniPro v3.0 spec, some HWs ++ * can accept 0x8D but some cannot. ++ */ ++ if (new_adapt <= ADAPT_L0L1L2L3_LENGTH_MAX || ++ (new_adapt == ADAPT_L0L1L2L3_LENGTH_MAX + 1 && host->hw_ver.minor == 0x1)) { ++ err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), ++ new_adapt); ++ if (err) ++ goto out; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), ++ &actual_adapt); ++ if (err) ++ goto out; ++ ++ if (actual_adapt != new_adapt) { ++ limit_speed = true; ++ dev_warn(hba->dev, "PA_PeerRxHsG6AdaptInitialL0L1L2L3 0x%x, expect 0x%x\n", ++ actual_adapt, new_adapt); ++ } ++ } else { ++ limit_speed = true; ++ dev_warn(hba->dev, "New PA_PeerRxHsG6AdaptInitialL0L1L2L3 (0x%x) is too large!\n", ++ new_adapt); ++ } ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), &old_adapt); ++ if (err) ++ goto out; ++ ++ if (old_adapt > ADAPT_L0L1L2L3_LENGTH_MAX) { ++ dev_err(hba->dev, "PA_PeerRxHsG6AdaptRefreshL0L1L2L3 value (0x%x) exceeds MAX\n", ++ old_adapt); ++ err = -ERANGE; ++ goto out; ++ } ++ ++ new_adapt = ufs_qcom_double_t_adapt_l0l1l2l3(old_adapt); ++ dev_dbg(hba->dev, "Original PA_PeerRxHsG6AdaptRefreshL0L1L2L3 = 0x%x, new value = 0x%x\n", ++ old_adapt, new_adapt); ++ ++ /* ++ * 0x8C is the max possible value allowed by UniPro v3.0 spec, some HWs ++ * can accept 0x8D but some cannot. ++ */ ++ if (new_adapt <= ADAPT_L0L1L2L3_LENGTH_MAX || ++ (new_adapt == ADAPT_L0L1L2L3_LENGTH_MAX + 1 && host->hw_ver.minor == 0x1)) { ++ err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), ++ new_adapt); ++ if (err) ++ goto out; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), ++ &actual_adapt); ++ if (err) ++ goto out; ++ ++ if (actual_adapt != new_adapt) { ++ limit_speed = true; ++ dev_warn(hba->dev, "PA_PeerRxHsG6AdaptRefreshL0L1L2L3 0x%x, expect 0x%x\n", ++ new_adapt, actual_adapt); ++ } ++ } else { ++ limit_speed = true; ++ dev_warn(hba->dev, "New PA_PeerRxHsG6AdaptRefreshL0L1L2L3 (0x%x) is too large!\n", ++ new_adapt); ++ } ++ ++out: ++ if (limit_speed || err) ++ ufs_qcom_limit_max_gear(hba, UFS_HS_G5); ++} ++ + static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) + { + int err = 0; + ++ ufs_qcom_fixup_tx_adapt_l0l1l2l3(hba); ++ + if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) + err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0438-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-tx_eqtr_no.patch b/SPECS/linux-lts/0438-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-tx_eqtr_no.patch new file mode 100644 index 0000000000..a99ee8451f --- /dev/null +++ b/SPECS/linux-lts/0438-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-tx_eqtr_no.patch @@ -0,0 +1,87 @@ +From 7386d5488c789d7d66d43d537816f45eaf515f71 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:51 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Implement vops + tx_eqtr_notify() + +On some platforms, HW does not support triggering TX EQTR from the most +reliable High-Speed (HS) Gear (HS Gear1), but only allows to trigger TX +EQTR for the target HS Gear from the same HS Gear. To work around the HW +limitation, implement vops tx_eqtr_notify() to change Power Mode to the +target TX EQTR HS Gear prior to TX EQTR procedure and change Power Mode +back to HS Gear1 (the most reliable gear) post TX EQTR procedure. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-10-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 385b95893e799885ec54a4ec2e240b1d814205be) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 41 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index f6ba37e1a931..57171f69b12a 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -2382,6 +2382,46 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) + return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); + } + ++static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *pwr_mode) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr pwr_mode_hs_g1 = { ++ .gear_rx = UFS_HS_G1, ++ .gear_tx = UFS_HS_G1, ++ .lane_rx = pwr_mode->lane_rx, ++ .lane_tx = pwr_mode->lane_tx, ++ .pwr_rx = FAST_MODE, ++ .pwr_tx = FAST_MODE, ++ .hs_rate = pwr_mode->hs_rate, ++ }; ++ u32 gear = pwr_mode->gear_tx; ++ u32 rate = pwr_mode->hs_rate; ++ int ret; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) ++ return 0; ++ ++ if (status == PRE_CHANGE) { ++ /* PMC to target HS Gear. */ ++ ret = ufshcd_change_power_mode(hba, pwr_mode, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (ret) ++ dev_err(hba->dev, "%s: Failed to PMC to target HS-G%u, Rate-%s: %d\n", ++ __func__, gear, ufs_hs_rate_to_str(rate), ret); ++ } else { ++ /* PMC back to HS-G1. */ ++ ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, ++ UFSHCD_PMC_POLICY_DONT_FORCE); ++ if (ret) ++ dev_err(hba->dev, "%s: Failed to PMC to HS-G1, Rate-%s: %d\n", ++ __func__, ufs_hs_rate_to_str(rate), ret); ++ } ++ ++ return ret; ++} ++ + /* + * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations + * +@@ -2412,6 +2452,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, + .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, ++ .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, + }; + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch deleted file mode 100644 index 19a9ca6539..0000000000 --- a/SPECS/linux-lts/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 202c07f948325a5c584ae346de90b289bd86b125 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 24 Nov 2025 20:38:44 +0800 -Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support - -From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/Makefile | 1 + - .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ - 2 files changed, 19 insertions(+) - create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts - -diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile -index b55a17127c2b..281849e71ccb 100644 ---- a/arch/riscv/boot/dts/thead/Makefile -+++ b/arch/riscv/boot/dts/thead/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb -+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -new file mode 100644 -index 000000000000..a3a991baf716 ---- /dev/null -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 Han Gao -+ */ -+ -+/dts-v1/; -+ -+#include "th1520-lichee-pi-4a.dts" -+ -+/ { -+ model = "Sipeed Lichee Pi 4A 16G"; -+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x00000000 0x4 0x00000000>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch deleted file mode 100644 index 1c294c8a28..0000000000 --- a/SPECS/linux-lts/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 7b0831ac6fa2e8db34c9c89d4e02bf2aa105fab3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:16:15 +0800 -Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie - -Signed-off-by: Han Gao -[Icenowy: preserve the original compatible to allow Linux to match] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index e44010810c07..f85d93227170 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { - }; - - aon: aon { -- compatible = "thead,th1520-aon"; -+ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; - mboxes = <&mbox_910t 1>; - mbox-names = "aon"; - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0439-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-get_rx_fom.patch b/SPECS/linux-lts/0439-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-get_rx_fom.patch new file mode 100644 index 0000000000..b786e7c773 --- /dev/null +++ b/SPECS/linux-lts/0439-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-get_rx_fom.patch @@ -0,0 +1,504 @@ +From 0ab479b135f8e3355ebce39e841852acda1edc62 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:52 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Implement vops + get_rx_fom() + +On some platforms, host's M-PHY RX_FOM Attribute always reads 0, meaning SW +cannot rely on Figure of Merit (FOM) to identify the optimal TX +Equalization settings for device's TX Lanes. Implement the vops +ufs_qcom_get_rx_fom() such that SW can utilize the UFS Eye Opening Monitor +(EOM) to evaluate the TX Equalization settings for device's TX Lanes. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-11-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 26605db7604deb18cf004cf3ad51e72e5d9b7add) +Signed-off-by: Han Gao +--- + drivers/ufs/core/ufs-txeq.c | 6 +- + drivers/ufs/host/ufs-qcom.c | 312 ++++++++++++++++++++++++++++++++++++ + drivers/ufs/host/ufs-qcom.h | 40 +++++ + include/ufs/ufshcd.h | 3 + + include/ufs/unipro.h | 25 +++ + 5 files changed, 383 insertions(+), 3 deletions(-) + +diff --git a/drivers/ufs/core/ufs-txeq.c b/drivers/ufs/core/ufs-txeq.c +index 3a879c644faa..b2dc89124353 100644 +--- a/drivers/ufs/core/ufs-txeq.c ++++ b/drivers/ufs/core/ufs-txeq.c +@@ -232,9 +232,8 @@ ufshcd_compose_tx_eq_setting(struct ufshcd_tx_eq_settings *settings, + * + * Returns 0 on success, negative error code otherwise + */ +-static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, +- struct ufshcd_tx_eq_params *params, +- u32 gear) ++int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, u32 gear) + { + struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; + u32 setting; +@@ -263,6 +262,7 @@ static int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, + + return 0; + } ++EXPORT_SYMBOL_GPL(ufshcd_apply_tx_eq_settings); + + /** + * ufshcd_evaluate_tx_eqtr_fom - Evaluate TX EQTR FOM results +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index 57171f69b12a..b5e95c7385d1 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -2382,6 +2382,317 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) + return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); + } + ++static int ufs_qcom_host_eom_config(struct ufs_hba *hba, int lane, ++ const struct ufs_eom_coord *eom_coord, ++ u32 target_test_count) ++{ ++ enum ufs_eom_eye_mask eye_mask = eom_coord->eye_mask; ++ int v_step = eom_coord->v_step; ++ int t_step = eom_coord->t_step; ++ u32 volt_step, timing_step; ++ int ret; ++ ++ if (abs(v_step) > UFS_QCOM_EOM_VOLTAGE_STEPS_MAX) { ++ dev_err(hba->dev, "Invalid EOM Voltage Step: %d\n", v_step); ++ return -ERANGE; ++ } ++ ++ if (abs(t_step) > UFS_QCOM_EOM_TIMING_STEPS_MAX) { ++ dev_err(hba->dev, "Invalid EOM Timing Step: %d\n", t_step); ++ return -ERANGE; ++ } ++ ++ if (v_step < 0) ++ volt_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-v_step); ++ else ++ volt_step = (u32)v_step; ++ ++ if (t_step < 0) ++ timing_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-t_step); ++ else ++ timing_step = (u32)t_step; ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ BIT(eye_mask) | RX_EYEMON_EXTENDED_VRANGE_BIT); ++ if (ret) { ++ dev_err(hba->dev, "Failed to enable Host EOM on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TIMING_STEPS, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ timing_step); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set Host EOM timing step on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_VOLTAGE_STEPS, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ volt_step); ++ if (ret) { ++ dev_err(hba->dev, "Failed to set Host EOM voltage step on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TARGET_TEST_COUNT, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ target_test_count); ++ if (ret) ++ dev_err(hba->dev, "Failed to set Host EOM target test count on Lane %d: %d\n", ++ lane, ret); ++ ++ return ret; ++} ++ ++static int ufs_qcom_host_eom_may_stop(struct ufs_hba *hba, int lane, ++ u32 target_test_count, u32 *err_count) ++{ ++ u32 start, tested_count, error_count; ++ int ret; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_START, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &start); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get Host EOM start status on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ if (start & 0x1) ++ return -EAGAIN; ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TESTED_COUNT, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &tested_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get Host EOM tested count on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ERROR_COUNT, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ &error_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get Host EOM error count on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ ++ /* EOM can stop */ ++ if ((tested_count >= target_test_count - 3) || error_count > 0) { ++ *err_count = error_count; ++ ++ /* Disable EOM */ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE, ++ UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), ++ 0x0); ++ if (ret) { ++ dev_err(hba->dev, "Failed to disable Host EOM on Lane %d: %d\n", ++ lane, ret); ++ return ret; ++ } ++ } else { ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++static int ufs_qcom_host_eom_scan(struct ufs_hba *hba, int num_lanes, ++ const struct ufs_eom_coord *eom_coord, ++ u32 target_test_count, u32 *err_count) ++{ ++ bool eom_stopped[PA_MAXDATALANES] = { 0 }; ++ int lane, ret; ++ u32 setting; ++ ++ if (!err_count || !eom_coord) ++ return -EINVAL; ++ ++ if (target_test_count < UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN) { ++ dev_err(hba->dev, "Target test count (%u) too small for Host EOM\n", ++ target_test_count); ++ return -ERANGE; ++ } ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ ret = ufs_qcom_host_eom_config(hba, lane, eom_coord, ++ target_test_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to config Host RX EOM: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ /* ++ * Trigger a PACP_PWR_req to kick start EOM, but not to really change ++ * the Power Mode. ++ */ ++ ret = ufshcd_uic_change_pwr_mode(hba, FAST_MODE << 4 | FAST_MODE); ++ if (ret) { ++ dev_err(hba->dev, "Failed to change power mode to kick start Host EOM: %d\n", ++ ret); ++ return ret; ++ } ++ ++more_burst: ++ /* Create burst on Host RX Lane. */ ++ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &setting); ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ if (eom_stopped[lane]) ++ continue; ++ ++ ret = ufs_qcom_host_eom_may_stop(hba, lane, target_test_count, ++ &err_count[lane]); ++ if (!ret) { ++ eom_stopped[lane] = true; ++ } else if (ret == -EAGAIN) { ++ /* Need more burst to excercise EOM */ ++ goto more_burst; ++ } else { ++ dev_err(hba->dev, "Failed to stop Host EOM: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hba->dev, "Host RX Lane %d EOM, v_step %d, t_step %d, error count %u\n", ++ lane, eom_coord->v_step, eom_coord->t_step, ++ err_count[lane]); ++ } ++ ++ return 0; ++} ++ ++static int ufs_qcom_host_sw_rx_fom(struct ufs_hba *hba, int num_lanes, u32 *fom) ++{ ++ const struct ufs_eom_coord *eom_coord = sw_rx_fom_eom_coords_g6; ++ u32 eom_err_count[PA_MAXDATALANES] = { 0 }; ++ u32 curr_ahit; ++ int lane, i, ret; ++ ++ if (!fom) ++ return -EINVAL; ++ ++ /* Stop the auto hibernate idle timer */ ++ curr_ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); ++ if (curr_ahit) ++ ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); ++ ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), PA_NO_ADAPT); ++ if (ret) { ++ dev_err(hba->dev, "Failed to select NO_ADAPT before starting Host EOM: %d\n", ret); ++ goto out; ++ } ++ ++ for (i = 0; i < SW_RX_FOM_EOM_COORDS; i++, eom_coord++) { ++ ret = ufs_qcom_host_eom_scan(hba, num_lanes, eom_coord, ++ UFS_QCOM_EOM_TARGET_TEST_COUNT_G6, ++ eom_err_count); ++ if (ret) { ++ dev_err(hba->dev, "Failed to run Host EOM scan: %d\n", ret); ++ break; ++ } ++ ++ for (lane = 0; lane < num_lanes; lane++) { ++ /* Bad coordinates have no weights */ ++ if (eom_err_count[lane]) ++ continue; ++ fom[lane] += SW_RX_FOM_EOM_COORDS_WEIGHT; ++ } ++ } ++ ++out: ++ /* Restore the auto hibernate idle timer */ ++ if (curr_ahit) ++ ufshcd_writel(hba, curr_ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); ++ ++ return ret; ++} ++ ++static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ struct ufshcd_tx_eq_params *params __free(kfree) = ++ kzalloc(sizeof(*params), GFP_KERNEL); ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ struct ufs_pa_layer_attr old_pwr_info; ++ u32 fom[PA_MAXDATALANES] = { 0 }; ++ u32 gear = pwr_mode->gear_tx; ++ u32 rate = pwr_mode->hs_rate; ++ int lane, ret; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 || ++ gear <= UFS_HS_G5 || !d_iter || !d_iter->is_updated) ++ return 0; ++ ++ if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) ++ return -ERANGE; ++ ++ if (!params) ++ return -ENOMEM; ++ ++ memcpy(&old_pwr_info, &hba->pwr_info, sizeof(struct ufs_pa_layer_attr)); ++ ++ memcpy(params, &hba->tx_eq_params[gear - 1], sizeof(struct ufshcd_tx_eq_params)); ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) { ++ params->device[lane].preshoot = d_iter->preshoot; ++ params->device[lane].deemphasis = d_iter->deemphasis; ++ } ++ ++ /* Use TX EQTR settings as Device's TX Equalization settings. */ ++ ret = ufshcd_apply_tx_eq_settings(hba, params, gear); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n", ++ __func__, gear, ret); ++ return ret; ++ } ++ ++ /* Force PMC to target HS Gear to use new TX Equalization settings. */ ++ ret = ufshcd_change_power_mode(hba, pwr_mode, UFSHCD_PMC_POLICY_FORCE); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to change power mode to HS-G%u, Rate-%s: %d\n", ++ __func__, gear, ufs_hs_rate_to_str(rate), ret); ++ return ret; ++ } ++ ++ ret = ufs_qcom_host_sw_rx_fom(hba, pwr_mode->lane_rx, fom); ++ if (ret) { ++ dev_err(hba->dev, "Failed to get SW FOM of TX (PreShoot: %u, DeEmphasis: %u): %d\n", ++ d_iter->preshoot, d_iter->deemphasis, ret); ++ return ret; ++ } ++ ++ /* Restore Device's TX Equalization settings. */ ++ ret = ufshcd_apply_tx_eq_settings(hba, &hba->tx_eq_params[gear - 1], gear); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n", ++ __func__, gear, ret); ++ return ret; ++ } ++ ++ /* Restore Power Mode. */ ++ ret = ufshcd_change_power_mode(hba, &old_pwr_info, UFSHCD_PMC_POLICY_FORCE); ++ if (ret) { ++ dev_err(hba->dev, "%s: Failed to retore power mode to HS-G%u: %d\n", ++ __func__, old_pwr_info.gear_tx, ret); ++ return ret; ++ } ++ ++ for (lane = 0; lane < pwr_mode->lane_rx; lane++) ++ d_iter->fom[lane] = fom[lane]; ++ ++ return 0; ++} ++ + static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *pwr_mode) +@@ -2452,6 +2763,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, + .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, ++ .get_rx_fom = ufs_qcom_get_rx_fom, + .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, + }; + +diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h +index 380d02333d38..d38bc0c4fc58 100644 +--- a/drivers/ufs/host/ufs-qcom.h ++++ b/drivers/ufs/host/ufs-qcom.h +@@ -33,6 +33,46 @@ + #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) + #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) + ++#define UFS_QCOM_EOM_VOLTAGE_STEPS_MAX 127 ++#define UFS_QCOM_EOM_TIMING_STEPS_MAX 63 ++#define UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN 8 ++#define UFS_QCOM_EOM_TARGET_TEST_COUNT_G6 0x3F ++ ++#define SW_RX_FOM_EOM_COORDS 23 ++#define SW_RX_FOM_EOM_COORDS_WEIGHT (127 / SW_RX_FOM_EOM_COORDS) ++ ++struct ufs_eom_coord { ++ int t_step; ++ int v_step; ++ u8 eye_mask; ++}; ++ ++static const struct ufs_eom_coord sw_rx_fom_eom_coords_g6[SW_RX_FOM_EOM_COORDS] = { ++ [0] = { -2, -15, UFS_EOM_EYE_MASK_M }, ++ [1] = { 0, -15, UFS_EOM_EYE_MASK_M }, ++ [2] = { 2, -15, UFS_EOM_EYE_MASK_M }, ++ [3] = { -4, -10, UFS_EOM_EYE_MASK_M }, ++ [4] = { -2, -10, UFS_EOM_EYE_MASK_M }, ++ [5] = { 0, -10, UFS_EOM_EYE_MASK_M }, ++ [6] = { 2, -10, UFS_EOM_EYE_MASK_M }, ++ [7] = { 4, -10, UFS_EOM_EYE_MASK_M }, ++ [8] = { -6, 0, UFS_EOM_EYE_MASK_M }, ++ [9] = { -4, 0, UFS_EOM_EYE_MASK_M }, ++ [10] = { -2, 0, UFS_EOM_EYE_MASK_M }, ++ [11] = { 0, 0, UFS_EOM_EYE_MASK_M }, ++ [12] = { 2, 0, UFS_EOM_EYE_MASK_M }, ++ [13] = { 4, 0, UFS_EOM_EYE_MASK_M }, ++ [14] = { 6, 0, UFS_EOM_EYE_MASK_M }, ++ [15] = { -4, 10, UFS_EOM_EYE_MASK_M }, ++ [16] = { -2, 10, UFS_EOM_EYE_MASK_M }, ++ [17] = { 0, 10, UFS_EOM_EYE_MASK_M }, ++ [18] = { 2, 10, UFS_EOM_EYE_MASK_M }, ++ [19] = { 4, 10, UFS_EOM_EYE_MASK_M }, ++ [20] = { -2, 15, UFS_EOM_EYE_MASK_M }, ++ [21] = { 0, 15, UFS_EOM_EYE_MASK_M }, ++ [22] = { 2, 15, UFS_EOM_EYE_MASK_M }, ++}; ++ + /* Qualcomm MCQ Configuration */ + #define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */ + #define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* 0x1C000 */ +diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h +index 8bb279c0e992..8ce8208445e7 100644 +--- a/include/ufs/ufshcd.h ++++ b/include/ufs/ufshcd.h +@@ -1524,6 +1524,9 @@ extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *desired_pwr_mode, + enum ufshcd_pmc_policy pmc_policy); + extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); ++extern int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba, ++ struct ufshcd_tx_eq_params *params, ++ u32 gear); + + /* UIC command interfaces for DME primitives */ + #define DME_LOCAL 0 +diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h +index 4aa592130b4e..f849a2a101ae 100644 +--- a/include/ufs/unipro.h ++++ b/include/ufs/unipro.h +@@ -32,6 +32,8 @@ + #define TX_LCC_SEQUENCER 0x0032 + #define TX_MIN_ACTIVATETIME 0x0033 + #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 ++#define TX_HS_DEEMPHASIS_SETTING 0x0037 ++#define TX_HS_PRESHOOT_SETTING 0x003B + #define TX_REFCLKFREQ 0x00EB + #define TX_CFGCLKFREQVAL 0x00EC + #define CFGEXTRATTR 0x00F0 +@@ -76,10 +78,27 @@ + #define RX_REFCLKFREQ 0x00EB + #define RX_CFGCLKFREQVAL 0x00EC + #define CFGWIDEINLN 0x00F0 ++#define RX_EYEMON_CAP 0x00F1 ++#define RX_EYEMON_TIMING_MAX_STEPS_CAP 0x00F2 ++#define RX_EYEMON_TIMING_MAX_OFFSET_CAP 0x00F3 ++#define RX_EYEMON_VOLTAGE_MAX_STEPS_CAP 0x00F4 ++#define RX_EYEMON_VOLTAGE_MAX_OFFSET_CAP 0x00F5 ++#define RX_EYEMON_ENABLE 0x00F6 ++#define RX_EYEMON_TIMING_STEPS 0x00F7 ++#define RX_EYEMON_VOLTAGE_STEPS 0x00F8 ++#define RX_EYEMON_TARGET_TEST_COUNT 0x00F9 ++#define RX_EYEMON_TESTED_COUNT 0x00FA ++#define RX_EYEMON_ERROR_COUNT 0x00FB ++#define RX_EYEMON_START 0x00FC ++#define RX_EYEMON_EXTENDED_ERROR_COUNT 0x00FD ++ + #define ENARXDIRECTCFG4 0x00F2 + #define ENARXDIRECTCFG3 0x00F3 + #define ENARXDIRECTCFG2 0x00F4 + ++#define RX_EYEMON_NEGATIVE_STEP_BIT BIT(6) ++#define RX_EYEMON_EXTENDED_VRANGE_BIT BIT(6) ++ + #define is_mphy_tx_attr(attr) (attr < RX_MODE) + #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) + #define SYNC_LEN_FINE(x) ((x) & 0x3F) +@@ -297,6 +316,12 @@ enum ufs_tx_hs_deemphasis { + UFS_TX_HS_DEEMPHASIS_DB_7P6, + }; + ++enum ufs_eom_eye_mask { ++ UFS_EOM_EYE_MASK_M, ++ UFS_EOM_EYE_MASK_L, ++ UFS_EOM_EYE_MASK_U, ++}; ++ + #define DL_FC0ProtectionTimeOutVal_Default 8191 + #define DL_TC0ReplayTimeOutVal_Default 65535 + #define DL_AFC0ReqTimeOutVal_Default 32767 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch deleted file mode 100644 index 757ee92472..0000000000 --- a/SPECS/linux-lts/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1fa033781168266e279c276df269822336f8d946 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:27:18 +0800 -Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r - -Signed-off-by: Han Gao -[Icenowy: remove the interrupt-controller property] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f85d93227170..ab681cf850d1 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -292,6 +292,24 @@ aon: aon { - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; - reset-names = "gpu-clkgen"; - #power-domain-cells = <1>; -+ opensbi-mboxes = <&mbox_910r>; -+ status = "okay"; -+ }; -+ -+ mbox_910r: mbox@ffefc53000 { -+ compatible = "xuantie,th1520-mbox-r"; -+ reg = <0xff 0xefc53000 0x0 0x4000>, -+ <0xff 0xefc3f000 0x0 0x1000>, -+ <0xff 0xefc47000 0x0 0x1000>, -+ <0xff 0xefc4f000 0x0 0x1000>; -+ reg-names = "local_base", -+ "remote_icu0", -+ "remote_icu1", -+ "remote_icu2"; -+ clocks = <&clk CLK_PERI_APB_PCLK>; -+ clock-names = "ipg"; -+ icu_cpu_id = <3>; -+ #mbox-cells = <2>; - }; - - soc { --- -2.53.0 - diff --git a/SPECS/linux-lts/0440-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-apply_tx_e.patch b/SPECS/linux-lts/0440-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-apply_tx_e.patch new file mode 100644 index 0000000000..42a1c7874b --- /dev/null +++ b/SPECS/linux-lts/0440-UPSTREAM-scsi-ufs-ufs-qcom-Implement-vops-apply_tx_e.patch @@ -0,0 +1,104 @@ +From 0623b509b86e77bdd30f561590bf76fcd9a798e2 Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:53 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Implement vops + apply_tx_eqtr_settings() + +On some platforms, when Host Software triggers TX Equalization Training, HW +does not take TX EQTR settings programmed in PA_TxEQTRSetting, instead HW +takes TX EQTR settings from PA_TxEQG1Setting. Implement vops +apply_tx_eqtr_setting() to work around it by programming TX EQTR settings +to PA_TxEQG1Setting during TX EQTR procedure. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-12-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 16cbdc8308776270d76340cd52ac63ac4fbf9968) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 31 +++++++++++++++++++++++++++++++ + drivers/ufs/host/ufs-qcom.h | 2 ++ + 2 files changed, 33 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index b5e95c7385d1..c0112ad1db53 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -2693,6 +2693,26 @@ static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, + return 0; + } + ++static int ufs_qcom_apply_tx_eqtr_settings(struct ufs_hba *hba, ++ struct ufs_pa_layer_attr *pwr_mode, ++ struct tx_eqtr_iter *h_iter, ++ struct tx_eqtr_iter *d_iter) ++{ ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ u32 setting = 0; ++ int lane; ++ ++ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) ++ return 0; ++ ++ for (lane = 0; lane < pwr_mode->lane_tx; lane++) { ++ setting |= TX_HS_PRESHOOT_BITS(lane, h_iter->preshoot); ++ setting |= TX_HS_DEEMPHASIS_BITS(lane, h_iter->deemphasis); ++ } ++ ++ return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), setting); ++} ++ + static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *pwr_mode) +@@ -2715,6 +2735,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + return 0; + + if (status == PRE_CHANGE) { ++ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), ++ &host->saved_tx_eq_g1_setting); ++ if (ret) ++ return ret; ++ + /* PMC to target HS Gear. */ + ret = ufshcd_change_power_mode(hba, pwr_mode, + UFSHCD_PMC_POLICY_DONT_FORCE); +@@ -2722,6 +2747,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, + dev_err(hba->dev, "%s: Failed to PMC to target HS-G%u, Rate-%s: %d\n", + __func__, gear, ufs_hs_rate_to_str(rate), ret); + } else { ++ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), ++ host->saved_tx_eq_g1_setting); ++ if (ret) ++ return ret; ++ + /* PMC back to HS-G1. */ + ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, + UFSHCD_PMC_POLICY_DONT_FORCE); +@@ -2764,6 +2794,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { + .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, + .get_rx_fom = ufs_qcom_get_rx_fom, ++ .apply_tx_eqtr_settings = ufs_qcom_apply_tx_eqtr_settings, + .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, + }; + +diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h +index d38bc0c4fc58..5f979daabd53 100644 +--- a/drivers/ufs/host/ufs-qcom.h ++++ b/drivers/ufs/host/ufs-qcom.h +@@ -348,6 +348,8 @@ struct ufs_qcom_host { + u32 phy_gear; + + bool esi_enabled; ++ ++ u32 saved_tx_eq_g1_setting; + }; + + struct ufs_qcom_drvdata { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch deleted file mode 100644 index 79f21e68df..0000000000 --- a/SPECS/linux-lts/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 40d9d7d4261e84ef42987558481248dd8a8a89b0 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:31 +0800 -Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller - -Sophgo SG2044 uses eFuses used to store factory-programmed data -such as ROM patch, public keys and other factory information. - -Signed-off-by: Inochi Amaoto ---- - .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml - -diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -new file mode 100644 -index 000000000000..d4bffe2724ac ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -@@ -0,0 +1,61 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo SoC eFuse-based NVMEM -+ -+description: -+ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, -+ public key and other factory information. -+ -+maintainers: -+ - Inochi Amaoto -+ -+allOf: -+ - $ref: nvmem.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - sophgo,sg2044-efuse -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ items: -+ - description: Core clock -+ - description: APB clock -+ -+ clock-names: -+ minItems: 1 -+ items: -+ - const: core -+ - const: apb -+ -+ resets: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ efuse@40000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x40000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk 0>, -+ <&clk 1>; -+ clock-names = "core", "apb"; -+ }; -+ -+... --- -2.53.0 - diff --git a/SPECS/linux-lts/0441-UPSTREAM-scsi-ufs-ufs-qcom-Enable-TX-Equalization.patch b/SPECS/linux-lts/0441-UPSTREAM-scsi-ufs-ufs-qcom-Enable-TX-Equalization.patch new file mode 100644 index 0000000000..bf5e5b2a6d --- /dev/null +++ b/SPECS/linux-lts/0441-UPSTREAM-scsi-ufs-ufs-qcom-Enable-TX-Equalization.patch @@ -0,0 +1,45 @@ +From 7d50836efe2ea050d9fc54df1cd274bdb7883a2b Mon Sep 17 00:00:00 2001 +From: Can Guo +Date: Wed, 25 Mar 2026 08:21:54 -0700 +Subject: [RUYI PATCH] UPSTREAM: scsi: ufs: ufs-qcom: Enable TX Equalization + +Enable TX Equalization for hosts with HW version 0x7 and onwards. + +Reviewed-by: Bean Huo +Reviewed-by: Bart Van Assche +Signed-off-by: Can Guo +Reviewed-by: Peter Wang +Link: https://patch.msgid.link/20260325152154.1604082-13-can.guo@oss.qualcomm.com +Signed-off-by: Martin K. Petersen +(cherry picked from commit 57b7943fd87f086a3497ecbecc502b7418ed4ab8) +Signed-off-by: Han Gao +--- + drivers/ufs/host/ufs-qcom.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c +index c0112ad1db53..9f9c0e5adc2a 100644 +--- a/drivers/ufs/host/ufs-qcom.c ++++ b/drivers/ufs/host/ufs-qcom.c +@@ -1338,6 +1338,8 @@ static void ufs_qcom_set_host_caps(struct ufs_hba *hba) + + static void ufs_qcom_set_caps(struct ufs_hba *hba) + { ++ struct ufs_qcom_host *host = ufshcd_get_variant(hba); ++ + hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; + hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; +@@ -1345,6 +1347,9 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) + hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; + hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; + ++ if (host->hw_ver.major >= 0x7) ++ hba->caps |= UFSHCD_CAP_TX_EQUALIZATION; ++ + ufs_qcom_set_host_caps(hba); + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch deleted file mode 100644 index 2ebd4453f3..0000000000 --- a/SPECS/linux-lts/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch +++ /dev/null @@ -1,241 +0,0 @@ -From e96eabf82535fd6f2fc338f3f5af2fb50721a459 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:32 +0800 -Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver - -Sophgo SoCs such as SG2044 contain eFuses used to store -factory-programmed data. - -As for SG2044, HW automatically loads the eFuse content -into shadow registers which are organized as 32bit values -exposed as MMIO. - -Signed-off-by: Inochi Amaoto ---- - drivers/nvmem/Kconfig | 12 +++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ - 3 files changed, 190 insertions(+) - create mode 100644 drivers/nvmem/sophgo-efuse.c - -diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig -index 11b098705ec6..42f46eb0462a 100644 ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - -+config NVMEM_SOPHGO_EFUSE -+ tristate "Sophgo eFuse support" -+ depends on ARCH_SOPHGO || COMPILE_TEST -+ default ARCH_SOPHGO -+ help -+ Say y here to enable support for reading eFuses on Sophgo SoCs -+ such as the CV1800B. These are e.g. used to store factory programmed -+ calibration data required for the builtin ethernet PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-sophgo-efuse. -+ - config NVMEM_SPMI_SDAM - tristate "SPMI SDAM Support" - depends on SPMI -diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile -index 70a4464dcb1e..6cc324aaa757 100644 ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o - nvmem-sc27xx-efuse-y := sc27xx-efuse.o - obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o - nvmem_snvs_lpgpr-y := snvs_lpgpr.o -+obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o -+nvmem-sophgo-efuse-y := sophgo-efuse.o - obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o - nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o - obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o -diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c -new file mode 100644 -index 000000000000..5f90adaf8e4f ---- /dev/null -+++ b/drivers/nvmem/sophgo-efuse.c -@@ -0,0 +1,176 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Sophgo SoC eFuse driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SG2044_EFUSE_CONTENT_SIZE 0x400 -+ -+#define SG2044_EFUSE_MD 0x000 -+#define SG2044_EFUSE_ADR 0x004 -+#define SG2044_EFUSE_RD_DATA 0x00c -+ -+#define SG2044_EFUSE_MODE GENMASK(1, 0) -+#define SG2044_EFUSE_MODE_READ 2 -+ -+#define SG2044_EFUSE_BOOT_DONE BIT(7) -+#define SG2044_BOOT_TIMEOUT 10000 -+ -+#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) -+ -+#define SG2044_EFUSE_ALIGN 4 -+ -+struct sophgo_efuses { -+ void __iomem *base; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct mutex mutex; -+}; -+ -+static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) -+{ -+ u32 value; -+ -+ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, -+ 1, SG2044_BOOT_TIMEOUT); -+} -+ -+static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) -+{ -+ u32 val = readl(efuse->base + SG2044_EFUSE_MD); -+ -+ val &= ~SG2044_EFUSE_MODE; -+ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); -+ -+ writel(val, efuse->base + SG2044_EFUSE_MD); -+ -+ return sg2044_efuse_wait_mode(efuse); -+} -+ -+static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, -+ unsigned int offset, u32 *strip) -+{ -+ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); -+ int ret; -+ -+ guard(mutex)(&efuse->mutex); -+ -+ writel(val, efuse->base + SG2044_EFUSE_ADR); -+ -+ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); -+ if (ret < 0) -+ return ret; -+ -+ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); -+ -+ return 0; -+} -+ -+static int sg2044_efuses_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct sophgo_efuses *efuse = context; -+ unsigned int start, start_offset, end, i; -+ u32 value; -+ u8 *buf; -+ int ret; -+ -+ start = rounddown(offset, SG2044_EFUSE_ALIGN); -+ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); -+ start_offset = offset - start; -+ -+ start /= SG2044_EFUSE_ALIGN; -+ end /= SG2044_EFUSE_ALIGN; -+ -+ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ (value & SG2044_EFUSE_BOOT_DONE), -+ 1, SG2044_BOOT_TIMEOUT); -+ if (ret < 0) -+ return ret; -+ -+ buf = kzalloc(end - start, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ for (i = start; i < end; i++) { -+ ret = sg2044_efuses_read_strip(efuse, i, &value); -+ if (ret) -+ goto failed; -+ -+ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); -+ } -+ -+ memcpy(val, buf + start_offset, bytes); -+ -+failed: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int sophgo_efuses_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct sophgo_efuses *efuse; -+ struct nvmem_config config = { -+ .dev = &pdev->dev, -+ .add_legacy_fixed_of_cells = true, -+ .read_only = true, -+ .reg_read = sg2044_efuses_read, -+ .stride = 1, -+ .word_size = 1, -+ .name = "sophgo-efuse", -+ .id = NVMEM_DEVID_AUTO, -+ .root_only = true, -+ }; -+ -+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); -+ if (!efuse) -+ return -ENOMEM; -+ -+ efuse->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(efuse->base)) -+ return PTR_ERR(efuse->base); -+ -+ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); -+ if (efuse->num_clks < 0) -+ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); -+ -+ config.priv = efuse; -+ config.size = SG2044_EFUSE_CONTENT_SIZE; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); -+} -+ -+static const struct of_device_id sophgo_efuses_of_match[] = { -+ { .compatible = "sophgo,sg2044-efuse", }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); -+ -+static struct platform_driver sophgo_efuses_driver = { -+ .driver = { -+ .name = "sophgo_efuse", -+ .of_match_table = sophgo_efuses_of_match, -+ }, -+ .probe = sophgo_efuses_probe, -+}; -+ -+module_platform_driver(sophgo_efuses_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Sophgo efuse driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0442-UPSTREAM-riscv-Prevent-NULL-pointer-dereference-in-m.patch b/SPECS/linux-lts/0442-UPSTREAM-riscv-Prevent-NULL-pointer-dereference-in-m.patch new file mode 100644 index 0000000000..59961d2bb0 --- /dev/null +++ b/SPECS/linux-lts/0442-UPSTREAM-riscv-Prevent-NULL-pointer-dereference-in-m.patch @@ -0,0 +1,56 @@ +From 96011511aea891b691cd12a4580f687531e8c92c Mon Sep 17 00:00:00 2001 +From: Tao Liu +Date: Mon, 6 Jul 2026 11:27:07 +1200 +Subject: [RUYI PATCH] UPSTREAM: riscv: Prevent NULL pointer dereference in + machine_kexec_prepare() + +A NULL pointer dereference issue is noticed in riscv's +machine_kexec_prepare(), where image->segment[i].buf might be NULL and +copied unchecked. + +The NULL buf comes from ima_add_kexec_buffer(), where kbuf is added by +kexec_add_buffer(), but kbuf.buffer is NULL, then it is copied without +a check in machine_kexec_prepare(): + + kexec_file_load + -> kimage_file_alloc_init() + -> kimage_file_prepare_segments() + -> ima_add_kexec_buffer() + -> kexec_add_buffer() + -> machine_kexec_prepare() + -> memcpy() + +Address this by adding a check before the data copy attempt. + +Fixes: b7fb4d78a6ad ("RISC-V: use memcpy for kexec_file mode") +Cc: stable@vger.kernel.org +Closes: https://lore.kernel.org/kexec/CAO7dBbVftLUhd2qrh7hmijTB3PEPfZAhykCGqEfrPoOcSrrj-w@mail.gmail.com/ +Acked-by: Baoquan He +Acked-by: Pratyush Yadav +Reviewed-by: Nutty Liu +Signed-off-by: Tao Liu +Link: https://patch.msgid.link/20260705232706.30265-2-ltao@redhat.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 81bbcff0c053c4f5c711c31a9b72fc492bd96c3f) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/machine_kexec.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c +index 2306ce3e5f22..738df176ff6f 100644 +--- a/arch/riscv/kernel/machine_kexec.c ++++ b/arch/riscv/kernel/machine_kexec.c +@@ -41,6 +41,9 @@ machine_kexec_prepare(struct kimage *image) + if (image->segment[i].memsz <= sizeof(fdt)) + continue; + ++ if (!image->segment[i].buf) ++ continue; ++ + if (image->file_mode) + memcpy(&fdt, image->segment[i].buf, sizeof(fdt)); + else if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt))) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch deleted file mode 100644 index ca1a921e5d..0000000000 --- a/SPECS/linux-lts/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 973bb367e07f78196b1e441326cbdef6c366955f Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 5 Dec 2024 13:24:13 +0800 -Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device - -Add eFUSE controller node for SG2044. - -Signed-off-by: Inochi Amaoto ---- - arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -index fed3d9a384a0..1b506972d465 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -@@ -36,6 +36,10 @@ &emmc { - status = "okay"; - }; - -+&efuse0 { -+ status = "okay"; -+}; -+ - &gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 320c4d1d08e6..9577aae08f7f 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -408,6 +408,18 @@ sd: mmc@703000b000 { - status = "disabled"; - }; - -+ efuse0: efuse@7040000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x70 0x40000000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk CLK_GATE_EFUSE>, -+ <&clk CLK_GATE_APB_EFUSE>; -+ clock-names = "core", "apb"; -+ resets = <&rst RST_EFUSE0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@7040005000 { - compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; - reg = <0x70 0x40005000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0443-UPSTREAM-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux-lts/0443-UPSTREAM-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch new file mode 100644 index 0000000000..1a102f5c13 --- /dev/null +++ b/SPECS/linux-lts/0443-UPSTREAM-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch @@ -0,0 +1,39 @@ +From 1a061ac4b941f7d99ba753e6f208194662f45fd3 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 27 Apr 2026 09:32:10 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: add UltraRISC SoC family Kconfig + support + +The first SoC in the UltraRISC series is UR-DP1000, containing octa +UltraRISC CP100 cores. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com +Signed-off-by: Paul Walmsley +(cherry picked from commit a3320469e3c8a58c808a090f3e1b5bfccb4c59c6) +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig.socs | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs +index 848e7149e443..98c70e2ae958 100644 +--- a/arch/riscv/Kconfig.socs ++++ b/arch/riscv/Kconfig.socs +@@ -71,6 +71,12 @@ config ARCH_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + ++config ARCH_ULTRARISC ++ bool "UltraRISC RISC-V SoCs" ++ help ++ This enables support for UltraRISC SoC platform hardware, ++ including boards based on the UR-DP1000. ++ + config ARCH_VIRT + bool "QEMU Virt Machine" + select POWER_RESET +-- +2.53.0 + diff --git a/SPECS/linux-lts/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch deleted file mode 100644 index 7551151403..0000000000 --- a/SPECS/linux-lts/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch +++ /dev/null @@ -1,102 +0,0 @@ -From e2ed9e487c648247b91a25cef6515dc2a54aba85 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 28 Dec 2025 23:02:15 +0800 -Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address - -FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 9577aae08f7f..f1377ee8e149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x00000000 0x0 0x00001000>, - <0x6c 0x00300000 0x0 0x00004000>, -- <0x48 0x00000000 0x0 0x00001000>, -+ <0x50 0x00000000 0x0 0x00001000>, - <0x6c 0x000c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, - <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc0: interrupt-controller { -@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { - ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, - <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc1: interrupt-controller { -@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04000000 0x0 0x00001000>, - <0x6c 0x04300000 0x0 0x00004000>, -- <0x58 0x00000000 0x0 0x00001000>, -+ <0x7c 0x00000000 0x0 0x00001000>, - <0x6c 0x040c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, - <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, -- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc2: interrupt-controller { -@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04400000 0x0 0x00001000>, - <0x6c 0x04700000 0x0 0x00004000>, -- <0x50 0x00000000 0x0 0x00001000>, -+ <0x78 0x00000000 0x0 0x00001000>, - <0x6c 0x04780000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, - <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, -- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, -- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc3: interrupt-controller { --- -2.53.0 - diff --git a/SPECS/linux-lts/0444-UPSTREAM-riscv-defconfig-enable-ARCH_ULTRARISC.patch b/SPECS/linux-lts/0444-UPSTREAM-riscv-defconfig-enable-ARCH_ULTRARISC.patch new file mode 100644 index 0000000000..35e652c411 --- /dev/null +++ b/SPECS/linux-lts/0444-UPSTREAM-riscv-defconfig-enable-ARCH_ULTRARISC.patch @@ -0,0 +1,31 @@ +From e28418b1445fd81ea0360d13cd0c8a2a794cd7f6 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:05 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: defconfig: enable ARCH_ULTRARISC + +Enable `ARCH_ULTRARISC` in the default RISC-V defconfig. + +Signed-off-by: Jia Wang +Link: https://patch.msgid.link/20260515-ultrarisc-pinctrl-v1-9-bf559589ea8a@ultrarisc.com +Signed-off-by: Paul Walmsley +(cherry picked from commit 3fb29495b486b1ec61708248cb388745fc607278) +Signed-off-by: Han Gao +--- + arch/riscv/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig +index fc2725cbca18..140c12d4ab15 100644 +--- a/arch/riscv/configs/defconfig ++++ b/arch/riscv/configs/defconfig +@@ -30,6 +30,7 @@ CONFIG_ARCH_SPACEMIT=y + CONFIG_SOC_STARFIVE=y + CONFIG_ARCH_SUNXI=y + CONFIG_ARCH_THEAD=y ++CONFIG_ARCH_ULTRARISC=y + CONFIG_ARCH_VIRT=y + CONFIG_ARCH_CANAAN=y + CONFIG_SMP=y +-- +2.53.0 + diff --git a/SPECS/linux-lts/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch deleted file mode 100644 index 8f80489e78..0000000000 --- a/SPECS/linux-lts/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 90bc96384294bf251a26f5f518765309821b8cd2 Mon Sep 17 00:00:00 2001 -From: Xiaoguang Xing -Date: Mon, 22 Jan 2024 10:31:30 +0800 -Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean - with flush - -FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 - -Signed-off-by: Xiaoguang Xing -Signed-off-by: Han Gao ---- - arch/riscv/errata/thead/errata.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index fbe46f2fa8fb..9be8c45f4531 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, - * 0000000 11001 00000 000 00000 0001011 - */ - #define THEAD_INVAL_A0 ".long 0x02a5000b" --#define THEAD_CLEAN_A0 ".long 0x0295000b" -+#define THEAD_CLEAN_A0 ".long 0x02b5000b" - #define THEAD_FLUSH_A0 ".long 0x02b5000b" - #define THEAD_SYNC_S ".long 0x0190000b" - --- -2.53.0 - diff --git a/SPECS/linux-lts/0445-UPSTREAM-selftests-rseq-Fix-a-building-error-for-ris.patch b/SPECS/linux-lts/0445-UPSTREAM-selftests-rseq-Fix-a-building-error-for-ris.patch new file mode 100644 index 0000000000..49f1f4693c --- /dev/null +++ b/SPECS/linux-lts/0445-UPSTREAM-selftests-rseq-Fix-a-building-error-for-ris.patch @@ -0,0 +1,51 @@ +From 2a5a5569ecca5b121c27b2e52e2167399ac07557 Mon Sep 17 00:00:00 2001 +From: Hui Wang +Date: Tue, 7 Jul 2026 16:23:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: selftests/rseq: Fix a building error for riscv + arch + +RISC-V rseq selftests include asm/fence.h from tools/arch/riscv, +but the rseq Makefile only adds tools/include in the CFLAGS, this +results in the building failure both for native and cross build: + + In file included from rseq.h:131, + from rseq.c:37: + rseq-riscv.h:11:10: fatal error: asm/fence.h: No such file or directory + +To fix it, add the matching tools/arch/$(ARCH)/include path in the +CFLAGS and derive ARCH from SUBARCH for standalone native builds where +ARCH is not set. + +Fixes: c92786e179e0 ("KVM: riscv: selftests: Use the existing RISCV_FENCE macro in `rseq-riscv.h`") +Cc: stable@vger.kernel.org +Signed-off-by: Hui Wang +Link: https://patch.msgid.link/20260707082348.36896-1-hui.wang@canonical.com +Signed-off-by: Paul Walmsley +(cherry picked from commit a2ac823d8a228e392bc6a79ea63b550ab84a55b2) +Signed-off-by: Han Gao +--- + tools/testing/selftests/rseq/Makefile | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/tools/testing/selftests/rseq/Makefile b/tools/testing/selftests/rseq/Makefile +index 0d0a5fae5954..ee4325874bae 100644 +--- a/tools/testing/selftests/rseq/Makefile ++++ b/tools/testing/selftests/rseq/Makefile +@@ -5,9 +5,13 @@ CLANG_FLAGS += -no-integrated-as + endif + + top_srcdir = ../../../.. ++include $(top_srcdir)/scripts/subarch.include ++ARCH ?= $(SUBARCH) ++LINUX_TOOL_ARCH_INCLUDE = $(top_srcdir)/tools/arch/$(ARCH)/include + + CFLAGS += -O2 -Wall -g -I./ $(KHDR_INCLUDES) -L$(OUTPUT) -Wl,-rpath=./ \ +- $(CLANG_FLAGS) -I$(top_srcdir)/tools/include ++ $(CLANG_FLAGS) -I$(top_srcdir)/tools/include \ ++ -I$(LINUX_TOOL_ARCH_INCLUDE) + LDLIBS += -lpthread -ldl + + # Own dependencies because we only want to build against 1st prerequisite, but +-- +2.53.0 + diff --git a/SPECS/linux-lts/0446-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux-lts/0446-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch new file mode 100644 index 0000000000..c168ebac21 --- /dev/null +++ b/SPECS/linux-lts/0446-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch @@ -0,0 +1,185 @@ +From dacfb03effe0f9ff79f2e310a9529323830e037e Mon Sep 17 00:00:00 2001 +From: "Guo Ren (Alibaba DAMO Academy)" +Date: Tue, 21 Apr 2026 10:31:40 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE + fixup + +The early version of XuanTie C910 core has a store merge buffer +delay problem. The store merge buffer could improve the store queue +performance by merging multi-store requests, but when there are not +continued store requests, the prior single store request would be +waiting in the store queue for a long time. That would cause +significant problems for communication between multi-cores. This +problem was found on sg2042 & th1520 platforms with the qspinlock +lock torture test. + +So appending a fence w.o could immediately flush the store merge +buffer and let other cores see the write result. + +This will apply the WRITE_ONCE errata to handle the non-standard +behavior via appending a fence w.o instruction for WRITE_ONCE(). + +This problem is only observed on the sg2042 hardware platform by +running the lock_torture test program for half an hour. The problem +was not found in the user space application, because interrupt can +break the livelock. + +Acked-by: Arnd Bergmann +Reviewed-by: Alexandre Ghiti +Reviewed-by: Leonardo Bras +Reviewed-by: Inochi Amaoto +Tested-by: Han Gao +Tested-by: Yao Zi +Cc: Chen Wang +Cc: Xiaoguang Xing +Cc: Paul Walmsley +Signed-off-by: Guo Ren (Alibaba DAMO Academy) +Link: https://lore.kernel.org/r/20260421143154.1590156-1-guoren@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig.errata | 17 ++++++++++ + arch/riscv/errata/thead/errata.c | 20 ++++++++++++ + arch/riscv/include/asm/errata_list_vendors.h | 3 +- + arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ + include/asm-generic/rwonce.h | 2 ++ + 5 files changed, 75 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/include/asm/rwonce.h + +diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata +index aca9b0cfcfec..ac64123433e7 100644 +--- a/arch/riscv/Kconfig.errata ++++ b/arch/riscv/Kconfig.errata +@@ -153,4 +153,21 @@ config ERRATA_THEAD_GHOSTWRITE + + If you don't know what to do here, say "Y". + ++config ERRATA_THEAD_WRITE_ONCE ++ bool "Apply T-Head WRITE_ONCE errata" ++ depends on ERRATA_THEAD ++ default y ++ help ++ The early version of T-Head C9xx cores of sg2042 & th1520 have a store ++ merge buffer delay problem. The store merge buffer could improve the ++ store queue performance by merging multi-store requests, but when there ++ are no continued store requests, the prior single store request would be ++ waiting in the store queue for a long time. That would cause signifi- ++ cant problems for communication between multi-cores. Appending a ++ fence w.o could immediately flush the store merge buffer and let other ++ cores see the write result. ++ ++ This will apply the WRITE_ONCE errata to handle the non-standard beh- ++ avior via appending a fence w.o instruction for WRITE_ONCE(). ++ + endmenu # "CPU errata selection" +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index 0b942183f708..fbe46f2fa8fb 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, + return true; + } + ++static bool errata_probe_write_once(unsigned int stage, ++ unsigned long arch_id, unsigned long impid) ++{ ++ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) ++ return false; ++ ++ /* target-c9xx cores report arch_id and impid as 0 */ ++ if (arch_id != 0 || impid != 0) ++ return false; ++ ++ if (stage == RISCV_ALTERNATIVES_BOOT || ++ stage == RISCV_ALTERNATIVES_MODULE) ++ return true; ++ ++ return false; ++} ++ + static u32 thead_errata_probe(unsigned int stage, + unsigned long archid, unsigned long impid) + { +@@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, + + errata_probe_ghostwrite(stage, archid, impid); + ++ if (errata_probe_write_once(stage, archid, impid)) ++ cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); ++ + return cpu_req_errata; + } + +diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h +index ec7eba373437..8fd7c36307e2 100644 +--- a/arch/riscv/include/asm/errata_list_vendors.h ++++ b/arch/riscv/include/asm/errata_list_vendors.h +@@ -18,7 +18,8 @@ + #define ERRATA_THEAD_MAE 0 + #define ERRATA_THEAD_PMU 1 + #define ERRATA_THEAD_GHOSTWRITE 2 +-#define ERRATA_THEAD_NUMBER 3 ++#define ERRATA_THEAD_WRITE_ONCE 3 ++#define ERRATA_THEAD_NUMBER 4 + #endif + + #ifdef CONFIG_ERRATA_MIPS +diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h +new file mode 100644 +index 000000000000..081793d4d772 +--- /dev/null ++++ b/arch/riscv/include/asm/rwonce.h +@@ -0,0 +1,34 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef __ASM_RWONCE_H ++#define __ASM_RWONCE_H ++ ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) ++ ++#define write_once_fence() \ ++do { \ ++ asm volatile(ALTERNATIVE( \ ++ "nop", \ ++ "fence w, o", \ ++ THEAD_VENDOR_ID, \ ++ ERRATA_THEAD_WRITE_ONCE, \ ++ CONFIG_ERRATA_THEAD_WRITE_ONCE) \ ++ : : : "memory"); \ ++} while (0) ++ ++#define __WRITE_ONCE(x, val) \ ++do { \ ++ *(volatile typeof(x) *)&(x) = (val); \ ++ write_once_fence(); \ ++} while (0) ++ ++#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ ++ ++#include ++ ++#endif /* __ASM_RWONCE_H */ +diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h +index 52b969c7cef9..4e2d941f15a1 100644 +--- a/include/asm-generic/rwonce.h ++++ b/include/asm-generic/rwonce.h +@@ -50,10 +50,12 @@ + __READ_ONCE(x); \ + }) + ++#ifndef __WRITE_ONCE + #define __WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) = (val); \ + } while (0) ++#endif + + #define WRITE_ONCE(x, val) \ + do { \ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux-lts/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch deleted file mode 100644 index 5ca806b352..0000000000 --- a/SPECS/linux-lts/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 283120c06a7de7f2b98715726a766cbef2459707 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 15:59:17 +0800 -Subject: [RUYI PATCH] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add - support for Ultrarisc DP1000 GMAC - -The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC -(version 5.10a). - -Add necessary compatible string for this device. - -Signed-off-by: Han Gao -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 1 + - .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ - 2 files changed, 90 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index eb36cb36a57a..a8a45b844335 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -113,6 +113,7 @@ properties: - - starfive,jh7110-dwmac - - tesla,fsd-ethqos - - thead,th1520-gmac -+ - ultrarisc,dp1000-gmac - - reg: - minItems: 1 -diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -new file mode 100644 -index 000000000000..ace5c4058cc9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Ultrarisc dp1000 glue layer -+ -+maintainers: -+ - Han Gao -+ -+select: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - ultrarisc,dp1000-gmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - const: ultrarisc,dp1000-gmac -+ - const: snps,dwmac-5.10a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC main clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ -+ dma-noncoherent: true -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0447-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux-lts/0447-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch new file mode 100644 index 0000000000..e00c8ebfe4 --- /dev/null +++ b/SPECS/linux-lts/0447-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch @@ -0,0 +1,54 @@ +From 20b11bd8885b81bc6e9498cecffb7048b7ecca08 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:56:57 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native + PCIe port services + +Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe +port service driver from probing specific devices. This provides a +per-device equivalent of the global pcie_ports=compat kernel parameter. + +Some platforms have PCIe root ports that break MSI delivery to downstream +devices when native port services (AER, PME, bwctrl, etc.) are active. +The existing pci_host_bridge native_* flags do not cover all services +(notably bwctrl), so a mechanism to skip port driver probing entirely +on a per-device basis is needed. + +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331175658.1015829-2-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/pcie/portdrv.c | 3 +++ + include/linux/pci.h | 2 ++ + 2 files changed, 5 insertions(+) + +diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c +index a0991da48213..315a8d9cb440 100644 +--- a/drivers/pci/pcie/portdrv.c ++++ b/drivers/pci/pcie/portdrv.c +@@ -684,6 +684,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { + static int pcie_portdrv_probe(struct pci_dev *dev, + const struct pci_device_id *id) + { ++ if (dev->dev_flags & PCI_DEV_FLAGS_NO_PORT_SERVICES) ++ return -ENODEV; ++ + int type = pci_pcie_type(dev); + int status; + +diff --git a/include/linux/pci.h b/include/linux/pci.h +index cdf67f5aa239..daf7f2363658 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -253,6 +253,8 @@ enum pci_dev_flags { + * integrated with the downstream devices and doesn't use real PCI. + */ + PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), ++ /* Do not use native PCIe port services (equivalent to pcie_ports=compat) */ ++ PCI_DEV_FLAGS_NO_PORT_SERVICES = (__force pci_dev_flags_t) (1 << 15), + }; + + enum pci_irq_reroute_variant { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux-lts/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch deleted file mode 100644 index 271d5db9ac..0000000000 --- a/SPECS/linux-lts/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 10d617cd5ad42153be1aa390de90e0cdd8376340 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 17:00:37 +0800 -Subject: [RUYI PATCH] REVYSR: net: stmmac: add support for dwmac 5.10a - -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -index b9218c07eb6b..a27b2bc177af 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { - { .compatible = "snps,dwmac-3.72a"}, - { .compatible = "snps,dwmac-4.00"}, - { .compatible = "snps,dwmac-4.10a"}, -+ { .compatible = "snps,dwmac-5.10a"}, - { .compatible = "snps,dwmac"}, - { .compatible = "snps,dwxgmac-2.10"}, - { .compatible = "snps,dwxgmac"}, --- -2.53.0 - diff --git a/SPECS/linux-lts/0448-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux-lts/0448-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch new file mode 100644 index 0000000000..6eaf9b9ecd --- /dev/null +++ b/SPECS/linux-lts/0448-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch @@ -0,0 +1,60 @@ +From e0f84e027e0c4bfad18d1f9f85e526228473219a Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:56:58 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services + on Sophgo SG2042 + +SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to +downstream devices when native port services are enabled. Devices under +an affected root port receive zero interrupts despite successful vector +allocation, causing driver timeouts (e.g. amdgpu fence fallback timer +expired on all rings). + +Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the +port service driver from probing, restoring correct MSI delivery. + +Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 12 ++++++++++++ + include/linux/pci_ids.h | 2 ++ + 2 files changed, 14 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 481e4186a5c1..28d23f8dfd60 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -6388,3 +6388,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); + #endif ++ ++/* ++ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to ++ * downstream devices when native PCIe port services are enabled. All ++ * services including bwctrl must be disabled, equivalent to pcie_ports=compat. ++ */ ++static void quirk_sg2042_no_port_services(struct pci_dev *dev) ++{ ++ pci_info(dev, "SG2042: disabling native PCIe port services\n"); ++ dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 2b6692a5005f..7c01548a6ddb 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2633,6 +2633,8 @@ + + #define PCI_VENDOR_ID_CXL 0x1e98 + ++#define PCI_VENDOR_ID_SOPHGO 0x1f1c ++ + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 + #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 + #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux-lts/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch deleted file mode 100644 index 9de39c75e0..0000000000 --- a/SPECS/linux-lts/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch +++ /dev/null @@ -1,578 +0,0 @@ -From 99ea7fd4bd1ccf2910170d8c84c997b33c948537 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 16 May 2025 11:12:26 +0800 -Subject: [RUYI PATCH] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 SoC - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/Makefile | 1 + - arch/riscv/boot/dts/ultrarisc/Makefile | 2 + - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ - 3 files changed, 539 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts - -diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile -index 3763d199c70a..297b30243037 100644 ---- a/arch/riscv/boot/dts/Makefile -+++ b/arch/riscv/boot/dts/Makefile -@@ -10,3 +10,4 @@ subdir-y += sophgo - subdir-y += spacemit - subdir-y += starfive - subdir-y += thead -+subdir-y += ultrarisc -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -new file mode 100644 -index 000000000000..c27f490e2b99 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-y += dp1000.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -new file mode 100644 -index 000000000000..3eb811f73aa8 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -0,0 +1,536 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "ultrarisc,dp1000"; -+ model = "ultrarisc,dp1000"; -+ -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+ -+ cpus { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ timebase-frequency = <10000000>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ reg = <0x00>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu0_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ reg = <0x1>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu1_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ reg = <0x2>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu2_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ reg = <0x3>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu3_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu4: cpu@4 { -+ device_type = "cpu"; -+ reg = <0x10>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu4_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu5: cpu@5 { -+ device_type = "cpu"; -+ reg = <0x11>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu5_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu6: cpu@6 { -+ device_type = "cpu"; -+ reg = <0x12>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ -+ clock-frequency = <2000000000>; -+ -+ cpu6_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu7: cpu@7 { -+ device_type = "cpu"; -+ reg = <0x13>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu7_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00 0x80000000 0x4 0x00000000>; -+ }; -+ -+ soc { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "simple-bus"; -+ ranges; -+ -+ clocks { -+ compatible = "simple-bus"; -+ u-boot,dm-pre-reloc; -+ device_clk: device_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <62500000>; -+ #clock-cells = <0>; -+ }; -+ csr_clk: csr_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <250000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ clint: clint@8000000 { -+ compatible = "riscv,clint0"; -+ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ reg = <0x00 0x8000000 0x00 0x100000>; -+ }; -+ -+ plic: plic@9000000 { -+ #interrupt-cells = <1>; -+ #address-cells = <0>; -+ phandle = <0x01>; -+ compatible = "ultrarisc,dp1000-plic"; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ reg = <0x00 0x9000000 0x00 0x4000000>; -+ riscv,max-priority = <0x07>; -+ riscv,ndev = <160>; -+ }; -+ -+ uart0: serial@20300000 { -+ interrupt-parent = <0x01>; -+ interrupts = <17>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20300000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart1: serial@20310000 { -+ interrupt-parent = <0x01>; -+ interrupts = <18>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20310000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart2: serial@20400000 { -+ interrupt-parent = <0x01>; -+ interrupts = <25>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20400000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart3: serial@20410000 { -+ interrupt-parent = <0x01>; -+ interrupts = <26>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20410000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ spi0: spi@20320000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20320000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <19>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; -+ }; -+ -+ spi1: spi@20420000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20420000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <27>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ }; -+ -+ i2c0: i2c@20330000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20330000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <20>; -+ }; -+ -+ i2c1: i2c@20340000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20340000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <21>; -+ }; -+ -+ i2c2: i2c@20430000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20430000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <28>; -+ }; -+ -+ i2c3: i2c@20440000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20440000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <29>; -+ }; -+ -+ wdt0: watchdog@20210000 { -+ compatible = "snps,dw-wdt"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20210000 0x0 0x100>; -+ interrupt-parent = <0x01>; -+ interrupts = <33>; -+ clocks = <&device_clk>; -+ }; -+ -+ timer0: timer@20220000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20220000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <35>; -+ status = "okay"; -+ }; -+ -+ timer1: timer@20230000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20230000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <36>; -+ status = "okay"; -+ }; -+ -+ gpio: gpio@20200000 { -+ compatible = "snps,dw-apb-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20200000 0x0 0x1000>; -+ clocks = <&csr_clk>, <&device_clk>; -+ clock-names = "bus", "db"; -+ status = "okay"; -+ -+ porta: gpio-port@0 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <16>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <0x01>; -+ interrupts = <34>; -+ }; -+ -+ portb: gpio-port@1 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portc: gpio-port@2 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portd: gpio-port@3 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <3>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ }; -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ phandle = <0x04>; -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ dmac: dma-controller@39000000 { -+ compatible = "snps,axi-dma-1.01a"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x39000000 0x0 0x400>; -+ clocks = <&device_clk>, <&device_clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <0x01>; -+ interrupts = <152>; -+ #dma-cells = <1>; -+ dma-channels = <8>; -+ snps,dma-masters = <1>; -+ snps,data-width = <4>; -+ snps,block-size = <512 512 512 512 512 512 512 512>; -+ snps,priority = <0 1 2 3 4 5 6 7>; -+ snps,axi-max-burst-len = <256>; -+ }; -+ -+ pcie_x16: pcie@21000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ -+ pcie_x4a: pcie@23000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, -+ <0x0 0x0 0x0 0x2 &plic 65>, -+ <0x0 0x0 0x0 0x3 &plic 66>, -+ <0x0 0x0 0x0 0x4 &plic 67>; -+ }; -+ -+ pcie_x4b: pcie@24000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, -+ <0x0 0x0 0x0 0x2 &plic 75>, -+ <0x0 0x0 0x0 0x3 &plic 76>, -+ <0x0 0x0 0x0 0x4 &plic 77>; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0449-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux-lts/0449-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch new file mode 100644 index 0000000000..5de83f4a30 --- /dev/null +++ b/SPECS/linux-lts/0449-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch @@ -0,0 +1,83 @@ +From 3b6fe729fdaddb25e1dd2b72d088b126141b2cfa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= +Date: Thu, 18 Sep 2025 13:58:56 -0700 +Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to + allow GPU BAR resize +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Resizing BAR to a larger size has to release upstream bridge windows in +order make the bridge windows larger as well (and to potential relocate +them into a larger free block within iomem space). Some GPUs have an +integrated PCI switch that has BAR0. The resource allocation assigns +space for that BAR0 as it does for any resource. + +An extra resource on a bridge will pin its upstream bridge window in +place which prevents BAR resize for anything beneath that bridge. + +Nothing in the pcieport driver provided by PCI core, which typically is +the driver bound to these bridges, requires that BAR0. Because of that, +releasing the extra BAR does not seem to have notable downsides but +comes with a clear upside. + +Therefore, release BAR0 of such switches using a quirk and clear its +flags to prevent any new invocation of the resource assignment +algorithm from assigning the resource again. + +Due to other siblings within the PCI hierarchy of all the devices +integrated into the GPU, some other devices may still have to be +manually removed before the resize is free of any bridge window pins. +Such siblings can be released through sysfs to unpin windows while +leaving access to GPU's sysfs entries required for initiating the +resize operation, whereas removing the topmost bridge this quirk +targets would result in removing the GPU device as well so no manual +workaround for this problem exists. + +Reported-by: Lucas De Marchi +Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ +Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ +Signed-off-by: Ilpo Järvinen +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Lucas De Marchi +Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com +Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 28d23f8dfd60..f0cd6c2a7827 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -6400,3 +6400,26 @@ static void quirk_sg2042_no_port_services(struct pci_dev *dev) + dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; + } + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); ++ ++/* ++ * PCI switches integrated into Intel Arc GPUs have BAR0 that prevents ++ * resizing the BARs of the GPU device due to that bridge BAR0 pinning the ++ * bridge window it's under in place. Nothing in pcieport requires that ++ * BAR0. ++ * ++ * Release and disable BAR0 permanently by clearing its flags to prevent ++ * anything from assigning it again. ++ */ ++static void pci_release_bar0(struct pci_dev *pdev) ++{ ++ struct resource *res = pci_resource_n(pdev, 0); ++ ++ if (!res->parent) ++ return; ++ ++ pci_release_resource(pdev, 0); ++ res->flags = 0; ++} ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa0, pci_release_bar0); ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa1, pci_release_bar0); ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0xe2ff, pci_release_bar0); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux-lts/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch deleted file mode 100644 index fad0cc8ffd..0000000000 --- a/SPECS/linux-lts/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,880 +0,0 @@ -From 709a5329d0c5e869292d0fb40e080d1e280adb51 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 17 Jan 2025 19:34:48 +0800 -Subject: [RUYI PATCH] RVCK: pinctrl: add pinctrl dirver for UltraRisc DP1000 - -support pinmux and pinconf for UltraRisc DP1000 SoC - -Signed-off-by: Jia Wang -Signed-off-by: Yanteng Si -FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade -Signed-off-by: Han Gao ---- - drivers/pinctrl/Kconfig | 1 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/ultrarisc/Kconfig | 20 + - drivers/pinctrl/ultrarisc/Makefile | 4 + - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ - .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ - 8 files changed, 794 insertions(+) - create mode 100644 drivers/pinctrl/ultrarisc/Kconfig - create mode 100644 drivers/pinctrl/ultrarisc/Makefile - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h - create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h - -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index 4f8507ebbdac..b4ba4fb72f10 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -712,5 +712,6 @@ source "drivers/pinctrl/ti/Kconfig" - source "drivers/pinctrl/uniphier/Kconfig" - source "drivers/pinctrl/visconti/Kconfig" - source "drivers/pinctrl/vt8500/Kconfig" -+source "drivers/pinctrl/ultrarisc/Kconfig" - - endif -diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index e0cfb9b7c99b..32f0d988e505 100644 ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -95,3 +95,4 @@ obj-y += ti/ - obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ - obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ - obj-$(CONFIG_ARCH_VT8500) += vt8500/ -+obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ -diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig -new file mode 100644 -index 000000000000..e4db80843bea ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Kconfig -@@ -0,0 +1,20 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config PINCTRL_ULTRARISC -+ bool -+ depends on OF -+ select PINMUX -+ select GENERIC_PINCTRL_GROUPS -+ select GENERIC_PINCONF -+ select GENERIC_PINMUX_FUNCTIONS -+ select GPIOLIB -+ select IRQ_DOMAIN_HIERARCHY -+ select MFD_SYSCON -+ -+config PINCTRL_ULTRARISC_DP1000 -+ tristate "Pinctrl driver of UltraRisc DP1000" -+ select PINCTRL_ULTRARISC -+ depends on OF && HAS_IOMEM -+ help -+ This driver configures the UltraRisc DP1000 SoC's pinctrl -+ subsystem. -diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile -new file mode 100644 -index 000000000000..5bf3f449d59b ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o -+obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o -\ No newline at end of file -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -new file mode 100644 -index 000000000000..217f671fe63a ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static const struct pinctrl_pin_desc ur_dp1000_pins[] = { -+ // PA -+ PINCTRL_PIN(0, "PA0"), -+ PINCTRL_PIN(1, "PA1"), -+ PINCTRL_PIN(2, "PA2"), -+ PINCTRL_PIN(3, "PA3"), -+ PINCTRL_PIN(4, "PA4"), -+ PINCTRL_PIN(5, "PA5"), -+ PINCTRL_PIN(6, "PA6"), -+ PINCTRL_PIN(7, "PA7"), -+ PINCTRL_PIN(8, "PA8"), -+ PINCTRL_PIN(9, "PA9"), -+ PINCTRL_PIN(10, "PA10"), -+ PINCTRL_PIN(11, "PA11"), -+ PINCTRL_PIN(12, "PA12"), -+ PINCTRL_PIN(13, "PA13"), -+ PINCTRL_PIN(14, "PA14"), -+ PINCTRL_PIN(15, "PA15"), -+ // PB -+ PINCTRL_PIN(16, "PB0"), -+ PINCTRL_PIN(17, "PB1"), -+ PINCTRL_PIN(18, "PB2"), -+ PINCTRL_PIN(19, "PB3"), -+ PINCTRL_PIN(20, "PB4"), -+ PINCTRL_PIN(21, "PB5"), -+ PINCTRL_PIN(22, "PB6"), -+ PINCTRL_PIN(23, "PB7"), -+ // PC -+ PINCTRL_PIN(24, "PC0"), -+ PINCTRL_PIN(25, "PC1"), -+ PINCTRL_PIN(26, "PC2"), -+ PINCTRL_PIN(27, "PC3"), -+ PINCTRL_PIN(28, "PC4"), -+ PINCTRL_PIN(29, "PC5"), -+ PINCTRL_PIN(30, "PC6"), -+ PINCTRL_PIN(31, "PC7"), -+ // PD -+ PINCTRL_PIN(32, "PD0"), -+ PINCTRL_PIN(33, "PD1"), -+ PINCTRL_PIN(34, "PD2"), -+ PINCTRL_PIN(35, "PD3"), -+ PINCTRL_PIN(36, "PD4"), -+ PINCTRL_PIN(37, "PD5"), -+ PINCTRL_PIN(38, "PD6"), -+ PINCTRL_PIN(39, "PD7"), -+ // LPC -+ PINCTRL_PIN(40, "LPC0"), -+ PINCTRL_PIN(41, "LPC1"), -+ PINCTRL_PIN(42, "LPC2"), -+ PINCTRL_PIN(43, "LPC3"), -+ PINCTRL_PIN(44, "LPC4"), -+ PINCTRL_PIN(45, "LPC5"), -+ PINCTRL_PIN(46, "LPC6"), -+ PINCTRL_PIN(47, "LPC7"), -+ PINCTRL_PIN(48, "LPC8"), -+ PINCTRL_PIN(49, "LPC9"), -+ PINCTRL_PIN(50, "LPC10"), -+ PINCTRL_PIN(51, "LPC11"), -+ PINCTRL_PIN(52, "LPC12"), -+}; -+ -+static struct ur_pinctrl_match_data ur_dp1000_match_data = { -+ .pins = ur_dp1000_pins, -+ .npins = ARRAY_SIZE(ur_dp1000_pins), -+ .offset = 0x2c0, -+ .ports = { -+ {"A", 16, 0x2c0, 0x310}, -+ {"B", 8, 0x2c4, 0x318}, -+ {"C", 8, 0x2c8, 0x31c}, -+ {"D", 8, 0x2cc, 0x320}, -+ {"LPC", 13, 0x2d0, 0x324}, -+ }, -+}; -+ -+enum ur_dp1000_port_list { -+ PORT_A = 0, -+ PORT_B, -+ PORT_C, -+ PORT_D, -+ PORT_LPC -+}; -+ -+ -+static const struct of_device_id ur_pinctrl_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); -+ -+static struct platform_driver ur_pinctrl_driver = { -+ .driver = { -+ .name = "ultrarisc-pinctrl-dp1000", -+ .of_match_table = ur_pinctrl_of_match, -+ }, -+ .probe = ur_pinctrl_probe, -+ .remove = ur_pinctrl_remove, -+}; -+ -+module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -new file mode 100644 -index 000000000000..667d59e0ac6e ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -0,0 +1,503 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) -+{ -+ int index = 0; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; -+ -+ for (int i = 0; i < pin_val->port; i++) -+ index += ur_match_data->ports[i].npins; -+ index += pin_val->pin; -+ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); -+ return index; -+} -+ -+static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, -+ const char *name, -+ enum pinctrl_map_type type, -+ struct device_node *np, -+ int **pins, -+ struct ur_pin_val **pin_val, -+ int *pin_num) -+{ -+ struct ur_pin_val *pin_vals; -+ int rows; -+ int ret = -EINVAL; -+ int *group_pins; -+ const char **pgnames; -+ -+ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); -+ rows = pinctrl_count_index_with_args(np, name); -+ if (rows < 0) { -+ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); -+ return rows; -+ } -+ -+ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); -+ if (!pin_vals) { -+ return -ENOMEM; -+ } -+ -+ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); -+ if (!group_pins) { -+ ret = -ENOMEM; -+ goto free_pin_vals; -+ } -+ -+ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); -+ if (!pgnames) { -+ ret = -ENOMEM; -+ goto free_pins; -+ } -+ -+ for (int i = 0; i < rows; i++) { -+ struct of_phandle_args pin_args; -+ -+ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); -+ if (ret) { -+ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); -+ goto free_pgnames; -+ } -+ -+ if (pin_args.args_count < 3) { -+ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", -+ pin_args.args_count, name, i, rows); -+ ret = -EINVAL; -+ goto free_pgnames; -+ } -+ pin_vals[i].port = pin_args.args[0]; -+ pin_vals[i].pin = pin_args.args[1]; -+ pin_vals[i].mode = pin_args.args[2]; -+ -+ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", -+ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); -+ -+ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); -+ -+ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add group %s failed\n", np->name); -+ goto free_pgnames; -+ } -+ -+ *pgnames = np->name; -+ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add function %s failed\n", np->name); -+ goto free_group; -+ } -+ -+ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); -+ -+ *pins = group_pins; -+ *pin_val = pin_vals; -+ *pin_num = rows; -+ -+ return 0; -+ -+free_group: -+ pinctrl_generic_remove_group(pctldev, ret); -+free_pgnames: -+ devm_kfree(pctldev->dev, pgnames); -+free_pins: -+ devm_kfree(pctldev->dev, group_pins); -+free_pin_vals: -+ devm_kfree(pctldev->dev, pin_vals); -+ return ret; -+} -+ -+static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin_vals; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, -+ np, &pins, &pin_vals, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); -+ return ret; -+ } -+ -+ map->type = PIN_MAP_TYPE_MUX_GROUP; -+ map->data.mux.group = np->name; -+ map->data.mux.function = np->name; -+ -+ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", -+ map->type, map->data.mux.group, map->data.mux.function); -+ -+ return 0; -+} -+ -+static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, -+ np, &pins, &pin, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); -+ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; -+ map->data.configs.group_or_pin = np->name; -+ map->data.configs.configs = (unsigned long *)pin; -+ map->data.configs.num_configs = pin_num; -+ -+ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", -+ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); -+ -+ return 0; -+} -+ -+static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map **map, -+ unsigned int *num_maps) -+{ -+ int ret; -+ bool mux_present = false, conf_present = false; -+ struct pinctrl_map *new_map; -+ unsigned int map_num = 0, prop_count = 0; -+ -+ //device_get_named_child_node(pctldev->dev, np->name); -+ if (of_property_present(np, PINMUX_PROP_NAME)) { -+ mux_present = true; -+ prop_count++; -+ } -+ if (of_property_present(np, PINCONF_PROP_NAME)) { -+ conf_present = true; -+ prop_count++; -+ } -+ -+ if (!prop_count) { -+ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); -+ return -EINVAL; -+ } -+ -+ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); -+ if (!new_map) -+ return -ENOMEM; -+ -+ *map = new_map; -+ if (mux_present) { -+ ret = ur_pinmux_to_map(pctldev, np, new_map); -+ if (!ret) { -+ new_map++; -+ map_num++; -+ } -+ } -+ if (conf_present) { -+ ret = ur_pinconf_to_map(pctldev, np, new_map); -+ if (!ret) -+ map_num++; -+ } -+ -+ if (!map_num) { -+ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); -+ goto free_map; -+ } -+ *num_maps = map_num; -+ -+ return 0; -+ -+free_map: -+ devm_kfree(pctldev->dev, new_map); -+ return ret; -+} -+ -+static void ur_dt_free_map(struct pinctrl_dev *pctldev, -+ struct pinctrl_map *map, unsigned int num_maps) -+{ -+ if (map) -+ devm_kfree(pctldev->dev, map); -+} -+ -+static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, -+ struct seq_file *s, unsigned int offset) -+{ -+ seq_printf(s, "%s", dev_name(pctldev->dev)); -+} -+ -+static const struct pinctrl_ops ur_pinctrl_ops = { -+ .get_groups_count = pinctrl_generic_get_group_count, -+ .get_group_name = pinctrl_generic_get_group_name, -+ .get_group_pins = pinctrl_generic_get_group_pins, -+ .dt_node_to_map = ur_dt_node_to_map, -+ .dt_free_map = ur_dt_free_map, -+ .pin_dbg_show = ur_pin_dbg_show, -+}; -+ -+static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ unsigned long flag; -+ //bool clear_mode = false; -+ void __iomem *reg; -+ u32 val; -+ const struct ur_port_desc *port; -+ -+ port = &pin_ctrl->match_data->ports[pin_vals->port]; -+ -+ reg = pin_ctrl->base + port->func_offset; -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); -+ val |= (pin_vals->mode << pin_vals->pin); -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ -+ return 0; -+} -+ -+static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, -+ unsigned int group_selector) -+{ -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_vals; -+ -+ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", -+ func_selector, group_selector); -+ ur_group = pinctrl_generic_get_group(pctldev, group_selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "get group %d failed\n", group_selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); -+ pin_vals = ur_group->data; -+ if (!pin_vals) { -+ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); -+ return -EINVAL; -+ } -+ -+ for (int i = 0; i < ur_group->grp.npins; i++) -+ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); -+ -+ return 0; -+} -+ -+static const struct pinmux_ops ur_pinmux_ops = { -+ .get_functions_count = pinmux_generic_get_function_count, -+ .get_function_name = pinmux_generic_get_function_name, -+ .get_function_groups = pinmux_generic_get_function_groups, -+ .set_mux = ur_set_mux, -+ .strict = true, -+}; -+ -+#define UR_CONF_BIT_PER_PIN (4) -+#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ const struct ur_port_desc *port_desc; -+ unsigned long flag; -+ void __iomem *reg; -+ u32 val, conf; -+ -+ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ reg = pin_ctrl->base + port_desc->conf_offset; -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; -+ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); -+ -+ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); -+ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); -+ val |= conf; -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); -+ -+ return 0; -+} -+ -+static int ur_pin_config_get(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); -+ // TODO: this is call by pinconf-generic -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_set(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -+ __func__, __LINE__, pin, num_configs); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", -+ __func__, __LINE__, selector, *config); -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", -+ __func__, __LINE__, selector, num_configs); -+ ur_group = pinctrl_generic_get_group(pctldev, selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static const struct pinconf_ops ur_pinconf_ops = { -+ .pin_config_get = ur_pin_config_get, -+ .pin_config_set = ur_pin_config_set, -+ .pin_config_group_get = ur_pin_config_group_get, -+ .pin_config_group_set = ur_pin_config_group_set, -+#ifdef CONFIG_GENERIC_PINCONF -+ .is_generic = true, -+#endif -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct pinctrl_desc *ur_pinctrl_desc; -+ const struct ur_pinctrl_match_data *pins_data; -+ struct ur_pinctrl *ur_pinctrl; -+ int ret; -+ -+ pins_data = of_device_get_match_data(&pdev->dev); -+ if (!pins_data) -+ return -ENODEV; -+ -+ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); -+ if (!ur_pinctrl_desc) { -+ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); -+ if (!ur_pinctrl) { -+ dev_err(&pdev->dev, "pinctrl alloc failed\n"); -+ ret = -ENOMEM; -+ goto free_pinctrl_desc; -+ } -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); -+ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ur_pinctrl->base)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pinctrl_desc; -+ } -+ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); -+ ur_pinctrl_desc->name = dev_name(&pdev->dev); -+ ur_pinctrl_desc->owner = THIS_MODULE; -+ ur_pinctrl_desc->pins = pins_data->pins; -+ ur_pinctrl_desc->npins = pins_data->npins; -+ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; -+ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; -+ ur_pinctrl_desc->confops = &ur_pinconf_ops; -+ -+ ur_pinctrl->dev = &pdev->dev; -+ ur_pinctrl->match_data = pins_data; -+ ur_pinctrl->pctl_desc = ur_pinctrl_desc; -+ raw_spin_lock_init(&ur_pinctrl->lock); -+ mutex_init(&ur_pinctrl->mutex); -+ -+ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, -+ ur_pinctrl, &ur_pinctrl->pctl_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "pinctrl register failed\n"); -+ goto free_pinctrl; -+ } -+ -+ platform_set_drvdata(pdev, ur_pinctrl); -+ -+ return pinctrl_enable(ur_pinctrl->pctl_dev); -+ -+free_pinctrl: -+ devm_kfree(&pdev->dev, ur_pinctrl); -+free_pinctrl_desc: -+ devm_kfree(&pdev->dev, ur_pinctrl_desc); -+ return ret; -+} -+ -+ -+void ur_pinctrl_remove(struct platform_device *pdev) -+{ -+ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -+ -+ if (ur_pinctrl->pctl_dev) -+ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); -+} -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -new file mode 100644 -index 000000000000..eec621bf8b05 ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __PINCTRL_ULTRARISC_H__ -+#define __PINCTRL_ULTRARISC_H__ -+ -+#include -+#include -+ -+#define PINMUX_PROP_NAME "pinctrl-pins" -+#define PINCONF_PROP_NAME "pinconf-pins" -+ -+struct ur_pin_conf { -+ u16 pull; -+ u16 drive; -+}; -+ -+struct ur_pin_val { -+ u32 port; -+ u32 pin; -+ union { -+ u32 mode; -+ u32 conf; -+ }; -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+#define UR_BIAS_MASK 0x0000000F -+#define UR_PULL_MASK 0x0C -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+#define UR_DRIVE_MASK 0x03 -+}; -+ -+struct ur_port_desc { -+ char *name; -+ u32 npins; -+ u32 func_offset; -+ u32 conf_offset; -+}; -+ -+struct ur_pinctrl_match_data { -+ const struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 offset; -+ //u32 conf_offset[]; -+ struct ur_port_desc ports[]; -+}; -+ -+ -+struct ur_pinctrl { -+ struct device *dev; -+ struct pinctrl_dev *pctl_dev; -+ struct pinctrl_desc *pctl_desc; -+ void __iomem *base; -+ unsigned int ngroups; -+ const char **grp_names; -+ unsigned int nbanks; -+ const struct ur_pinctrl_match_data *match_data; -+ struct regmap *regmap; -+ raw_spinlock_t lock; -+ struct mutex mutex; -+ struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 pkg; -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev); -+void ur_pinctrl_remove(struct platform_device *pdev); -+ -+#endif -diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -new file mode 100644 -index 000000000000..5bec446e2411 ---- /dev/null -+++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl header -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __UR_DP1000_PINCTRL_H__ -+#define __UR_DP1000_PINCTRL_H__ -+ -+#define UR_DP1000_IOMUX_A 0x0 -+#define UR_DP1000_IOMUX_B 0x1 -+#define UR_DP1000_IOMUX_C 0x2 -+#define UR_DP1000_IOMUX_D 0x3 -+#define UR_DP1000_IOMUX_LPC 0x4 -+ -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+/** -+ * port: 'A' 'B' 'C' -+ * Pin in the port -+ * pin: -+ * PA: 0 - 15 -+ * PB-PD: 0 - 7 -+ * func: -+ * UR_FUNC_DEF: default -+ * UR_FUNC0: func0 -+ * UR_FUNC1: func1 -+ */ -+#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) -+ -+/** -+ * Configure pull up/down resistor of the IO pin -+ * UR_PULL_DIS: disable pull-up and pull-down -+ * UR_PULL_UP: enable pull-up -+ * UR_PULL_DOWN: enable pull-down -+ */ -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+/** -+ * Configure drive strength of the IO pin -+ * UR_DRIVE_DEF: default value, reset value is 2 -+ * UR_DRIVE_0: 20mA -+ * UR_DRIVE_1: 27mA -+ * UR_DIRVE_2: 33mA -+ * UR_DRIVE_3: 40mA -+ */ -+#define UR_DRIVE_DEF 2 -+#define UR_DRIVE_0 0 -+#define UR_DRIVE_1 1 -+#define UR_DRIVE_2 2 -+#define UR_DRIVE_3 3 -+ -+/** -+ * Combine the pull-up/down resistor and drive strength -+ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN -+ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 -+ */ -+#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0450-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux-lts/0450-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch new file mode 100644 index 0000000000..5d8d7c38cb --- /dev/null +++ b/SPECS/linux-lts/0450-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch @@ -0,0 +1,63 @@ +From 5bedd31673a02d21556a205f46115eaa2aadc42f Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sat, 29 Jun 2024 13:22:46 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA + coherency status in ttm_device + +Currently TTM utilizes cached memory regardless of whether the device +have full DMA coherency (can snoop CPU cache). + +Save the device's DMA coherency status in struct ttm_device, to allow +further support of devices w/o snooping capability (the capability +missing on at least one part of the transmission between the CPU and the +device). + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20240629052247.2653363-2-uwu@icenowy.me +[ Han Gao: add conditional compilation for dma_coherent ] +Signed-off-by: Han Gao +--- + drivers/gpu/drm/ttm/ttm_device.c | 6 ++++++ + include/drm/ttm/ttm_device.h | 9 +++++++++ + 2 files changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c +index c3e2fcbdd2cc..1758d94b3d44 100644 +--- a/drivers/gpu/drm/ttm/ttm_device.c ++++ b/drivers/gpu/drm/ttm/ttm_device.c +@@ -246,6 +246,12 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func + list_add_tail(&bdev->device_list, &glob->device_list); + mutex_unlock(&ttm_global_mutex); + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ bdev->dma_coherent = dev->dma_coherent; ++#endif ++ + return 0; + } + EXPORT_SYMBOL(ttm_device_init); +diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h +index 592b5f802859..c2e61312a43a 100644 +--- a/include/drm/ttm/ttm_device.h ++++ b/include/drm/ttm/ttm_device.h +@@ -225,6 +225,15 @@ struct ttm_device { + */ + const struct ttm_device_funcs *funcs; + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /** ++ * @dma_coherent: if the device backed is dma-coherent. ++ */ ++ bool dma_coherent; ++#endif ++ + /** + * @sysman: Resource manager for the system domain. + * Access via ttm_manager_type. +-- +2.53.0 + diff --git a/SPECS/linux-lts/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux-lts/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch deleted file mode 100644 index 935589d38c..0000000000 --- a/SPECS/linux-lts/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,237 +0,0 @@ -From c3b99eaa70d3c031fe29c503b85abb31e02d50a4 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 16 Jun 2025 10:25:31 +0800 -Subject: [RUYI PATCH] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 - -The newly added dtsi/dts is used to describe the pinctrl -configuration of the UltraRisc DP1000-EVB mainboard. - -Do not involve functional changes. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ - 3 files changed, 194 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index c27f490e2b99..ef70e28e0b65 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,2 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb -+dtb-y += dp1000.dtb dp1000-evb-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -new file mode 100644 -index 000000000000..be898b6df6fb ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -0,0 +1,141 @@ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -new file mode 100644 -index 000000000000..5ec9a39e8c34 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -0,0 +1,52 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+#include "dp1000.dts" -+#include "dp1000-evb-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0451-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux-lts/0451-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch new file mode 100644 index 0000000000..8f765e4abb --- /dev/null +++ b/SPECS/linux-lts/0451-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch @@ -0,0 +1,125 @@ +From 1500e6d66b9678818ba5df1e067507906ddabc8c Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sat, 29 Jun 2024 13:22:47 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to + write_combined when snooping not available + +As we can now acquire the presence of the full DMA coherency (snooping +capability) from ttm_device, we can now map the CPU side memory as +write-combined when cached is requested and snooping is not avilable. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20240629052247.2653363-3-uwu@icenowy.me +[ Han Gao: add conditional compilation for dma coherent operations ] +[ Icenowy: omit single page ttm_cached optimization when non-coherent and handle linear io iter ] +Signed-off-by: Han Gao +--- + drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +++++++++++++ + drivers/gpu/drm/ttm/ttm_resource.c | 13 +++++++++++-- + drivers/gpu/drm/ttm/ttm_tt.c | 8 ++++++++ + include/drm/ttm/ttm_caching.h | 3 ++- + 4 files changed, 34 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c +index acbbca9d5c92..2a8777d1f2b8 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo_util.c ++++ b/drivers/gpu/drm/ttm/ttm_bo_util.c +@@ -307,6 +307,14 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res, + caching = res->bus.caching; + } + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bo->bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + return ttm_prot_from_caching(caching, tmp); + } + EXPORT_SYMBOL(ttm_io_prot); +@@ -360,6 +368,11 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, + return ret; + + if (num_pages == 1 && ttm->caching == ttm_cached && ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ bo->bdev->dma_coherent && ++#endif + !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { + /* + * We're mapping a single page, and the desired +diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c +index 2a05fbd07546..4f18a9a98f11 100644 +--- a/drivers/gpu/drm/ttm/ttm_resource.c ++++ b/drivers/gpu/drm/ttm/ttm_resource.c +@@ -830,8 +830,17 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, + struct ttm_device *bdev, + struct ttm_resource *mem) + { ++ enum ttm_caching caching = mem->bus.caching; + int ret; + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + ret = ttm_mem_io_reserve(bdev, mem); + if (ret) + goto out_err; +@@ -846,11 +855,11 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, + } else { + iter_io->needs_unmap = true; + memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); +- if (mem->bus.caching == ttm_write_combined) ++ if (caching == ttm_write_combined) + iosys_map_set_vaddr_iomem(&iter_io->dmap, + ioremap_wc(mem->bus.offset, + mem->size)); +- else if (mem->bus.caching == ttm_cached) ++ else if (caching == ttm_cached) + iosys_map_set_vaddr(&iter_io->dmap, + memremap(mem->bus.offset, mem->size, + MEMREMAP_WB | +diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c +index 506e257dfba8..8338deb3330f 100644 +--- a/drivers/gpu/drm/ttm/ttm_tt.c ++++ b/drivers/gpu/drm/ttm/ttm_tt.c +@@ -154,6 +154,14 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, + enum ttm_caching caching, + unsigned long extra_pages) + { ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bo->bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; + ttm->page_flags = page_flags; + ttm->dma_address = NULL; +diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h +index a18f43e93aba..f92d7911f50e 100644 +--- a/include/drm/ttm/ttm_caching.h ++++ b/include/drm/ttm/ttm_caching.h +@@ -47,7 +47,8 @@ enum ttm_caching { + + /** + * @ttm_cached: Fully cached like normal system memory, requires that +- * devices snoop the CPU cache on accesses. ++ * devices snoop the CPU cache on accesses. Downgraded to ++ * ttm_write_combined when the snooping capaiblity is missing. + */ + ttm_cached + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux-lts/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch deleted file mode 100644 index dfeb639386..0000000000 --- a/SPECS/linux-lts/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 6e08f5227680fcb9eef599c73c6a48dbba8d8f66 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 4 Sep 2025 16:31:30 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: add the dts of UltraRISC - dp1000-mo-v1 board - -adds the necessary device tree files for the UltraRISC -dp1000-mo-v1 board. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ - 3 files changed, 209 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index ef70e28e0b65..9eac56549340 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -new file mode 100644 -index 000000000000..e82fcf2901ab ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -new file mode 100644 -index 000000000000..a74714629566 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000.dts" -+#include "dp1000-mo-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@32 { -+ compatible = "whwave,sd3078"; -+ reg = <0x32>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0452-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux-lts/0452-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch new file mode 100644 index 0000000000..aa8d8fd112 --- /dev/null +++ b/SPECS/linux-lts/0452-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch @@ -0,0 +1,98 @@ +From 5c63322d4ad772fbd9ac2df51769aa8e554b790e Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:16 +0000 +Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP + table for TH1520 + +Add operating point table for CPU cores, and wire up clocks for CPU +nodes. + +This patch isn't intended for upstreaming but only for testing purpose, +since the PMIC driver for scaling CPU voltage isn't ready yet. Only +operating points whose voltage is satisified by Lichee Module 4A's PMIC +default, i.e. <= 1.5GHz, are enabled. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20251120131416.26236-8-ziyao@disroot.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 35 +++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 94932c51b7e3..f2abc6338458 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -38,6 +38,8 @@ c910_0: cpu@0 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -65,6 +67,8 @@ c910_1: cpu@1 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -92,6 +96,8 @@ c910_2: cpu@2 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -119,6 +125,8 @@ c910_3: cpu@3 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -137,6 +145,33 @@ l2_cache: l2-cache { + }; + }; + ++ cpu_opp: opp-table-cpu { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <600000>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <700000>; ++ }; ++ ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <800000>; ++ }; ++ ++/* ++ opp-1848000000 { ++ opp-hz = /bits/ 64 <1848000000>; ++ opp-microvolt = <1000000>; ++ }; ++ */ ++ }; ++ + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = +-- +2.53.0 + diff --git a/SPECS/linux-lts/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux-lts/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch deleted file mode 100644 index ee76518537..0000000000 --- a/SPECS/linux-lts/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch +++ /dev/null @@ -1,111 +0,0 @@ -From b9ce7c71ab1aae741d95ad74bd380256a79a7de3 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 9 Sep 2025 15:45:52 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to - board DTS - -The mmc0 node (mmc-spi-slot) is a board-level peripheral -specific to the UltraRISC DP1000 EVB V1.0, not part of the -base SoC. Move it from the SoC-level dp1000.dts to the -board-specific dp1000-evb-v1.dts to maintain proper device -tree hierarchy between SoC core and board-specific components. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 -Signed-off-by: Han Gao ---- - .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ - 3 files changed, 21 insertions(+), 19 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index be898b6df6fb..e82fcf2901ab 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -1,3 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ - #include - - / { -@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) - - uart0_pins: uart0_pins { - pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) - >; - - pinconf-pins = < -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 5ec9a39e8c34..34622a33e63b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - #include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" -@@ -27,6 +25,14 @@ &i2c3 { - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -+ -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; - }; - - &spi1 { -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 3eb811f73aa8..23a983d6a4c8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - /dts-v1/; - -@@ -261,13 +259,6 @@ spi0: spi@20320000 { - clock-names = "device_clk"; - num-cs = <3>; - spi-max-frequency = <62500000>; -- mmc0: mmc@0 { -- compatible = "mmc-spi-slot"; -- spi-max-frequency = <15625000>; -- reg = <0x00>; -- voltage-ranges = <3300 3300>; -- disable-wp; -- }; - }; - - spi1: spi@20420000 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0453-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux-lts/0453-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch new file mode 100644 index 0000000000..5d15847c7d --- /dev/null +++ b/SPECS/linux-lts/0453-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch @@ -0,0 +1,83 @@ +From d7a807a6da111df9d1768cea86661423eb39f79d Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:54 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate + Makefile + +A subsequent commit will add a new function `bindgen-option` to +`scripts/Kconfig.include`. The bindgen backend requires the `--target` +option for cross compiling, but variable `BINDGEN_TARGET` in +`rust/Makefile` cannot be exported to `scripts/Kconfig.include`. + +Therefore, move this variable to a separate new `Makefile.rust` file and +include it from `scripts/Makefile` to make the exported variable +available for use in Kconfig. Place the include in the `need-compiler` +branch to avoid including it in irrelevant make targets. + +Since the new file name is `Makefile.rust`, it matches an existing +MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS +file is needed. + +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-1-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + Makefile | 3 ++- + rust/Makefile | 8 -------- + scripts/Makefile.rust | 9 +++++++++ + 3 files changed, 11 insertions(+), 9 deletions(-) + create mode 100644 scripts/Makefile.rust + +diff --git a/Makefile b/Makefile +index 8ae52cf42da5..45c25959a2b1 100644 +--- a/Makefile ++++ b/Makefile +@@ -725,9 +725,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) + include $(srctree)/scripts/Makefile.clang + endif + ++ifdef need-compiler ++include $(srctree)/scripts/Makefile.rust + # Include this also for config targets because some architectures need + # cc-cross-prefix to determine CROSS_COMPILE. +-ifdef need-compiler + include $(srctree)/scripts/Makefile.compiler + endif + +diff --git a/rust/Makefile b/rust/Makefile +index d4618f646b05..c311d16e7e74 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -300,14 +300,6 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fzero-init-padding-bits=% -mno-fdpic \ + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference + +-# Derived from `scripts/Makefile.clang`. +-BINDGEN_TARGET_x86 := x86_64-linux-gnu +-BINDGEN_TARGET_arm64 := aarch64-linux-gnu +-BINDGEN_TARGET_arm := arm-linux-gnueabi +-BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf +-BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) +-BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) +- + # All warnings are inhibited since GCC builds are very experimental, + # many GCC warnings are not supported by Clang, they may only appear in + # some configurations, with new GCC versions, etc. +diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust +new file mode 100644 +index 000000000000..5c12b4b8c8b6 +--- /dev/null ++++ b/scripts/Makefile.rust +@@ -0,0 +1,9 @@ ++# Derived from `scripts/Makefile.clang`. ++BINDGEN_TARGET_x86 := x86_64-linux-gnu ++BINDGEN_TARGET_arm64 := aarch64-linux-gnu ++BINDGEN_TARGET_arm := arm-linux-gnueabi ++BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf ++BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) ++BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) ++ ++export BINDGEN_TARGET +-- +2.53.0 + diff --git a/SPECS/linux-lts/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux-lts/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch deleted file mode 100644 index 2e0d7ad5ce..0000000000 --- a/SPECS/linux-lts/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 2e69e921113ca412333654bea99e8cde384f3780 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 18 Sep 2025 10:44:01 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: plic: add plic early init supports - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - -------------------------------------------------- - -Add PLIC early init supports and remove invalid -timer nodes in dp1000.dts. - -Signed-off-by: Jia Wang -From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- - drivers/irqchip/irq-sifive-plic.c | 1 + - 2 files changed, 3 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 23a983d6a4c8..4a2dae602693 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -164,6 +164,7 @@ device_clk: device_clk { - clock-frequency = <62500000>; - #clock-cells = <0>; - }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { - interrupts = <33>; - clocks = <&device_clk>; - }; -- -- timer0: timer@20220000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20220000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <35>; -- status = "okay"; -- }; -- -- timer1: timer@20230000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20230000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <36>; -- status = "okay"; -- }; -- -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 70058871d2fb..007a4668f9e5 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, - } - - IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); -+IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); --- -2.53.0 - diff --git a/SPECS/linux-lts/0454-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux-lts/0454-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch new file mode 100644 index 0000000000..930937fa4d --- /dev/null +++ b/SPECS/linux-lts/0454-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch @@ -0,0 +1,61 @@ +From 0fb94e0dedf55feb6037f53cc79738321746b27c Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:55 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET + is undefined + +Generate a friendly fatal error if the target triplet is undefined for +bindgen, rather than having the compiler generate obscure error messages +during the build stage. + +`BINDGEN_TARGET` is actually defined in `scripts/Makefile.rust`, but the +file is included regardless of whether Rust is enabled, so perform this +check in `rust/Makefile` to avoid breaking targets that do not yet +support Rust builds. + +This piece of code is copied from `scripts/Makefile.clang`. + +Before this commit, error messages might look like: + +error: unknown argument: '-mno-riscv-attribute' +error: unsupported argument 'medany' to option '-mcmodel=' for target +'unknown' +error: unsupported option '-march=' for target '' +error: unsupported option '-mno-save-restore' for target '' +error: unknown target triple 'unknown' +panicked at bindgen/ir/context.rs:562:15: +libclang error; possible causes include: +- Invalid flag syntax +- Unrecognized flags +- Invalid flag arguments +- File I/O errors +- Host vs. target architecture mismatch + +Acked-by: Miguel Ojeda +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-2-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + rust/Makefile | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/rust/Makefile b/rust/Makefile +index c311d16e7e74..6d2d542a55e8 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -300,6 +300,12 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fzero-init-padding-bits=% -mno-fdpic \ + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference + ++# Because scripts/Makefile.rust is included regardless of whether Rust is enabled, ++# we perform this check here to avoid breaking targets that do not yet support Rust builds. ++ifeq ($(BINDGEN_TARGET),) ++$(error add '--target=' option to scripts/Makefile.rust) ++endif ++ + # All warnings are inhibited since GCC builds are very experimental, + # many GCC warnings are not supported by Clang, they may only appear in + # some configurations, with new GCC versions, etc. +-- +2.53.0 + diff --git a/SPECS/linux-lts/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux-lts/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch deleted file mode 100644 index 87e90bc15e..0000000000 --- a/SPECS/linux-lts/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch +++ /dev/null @@ -1,85 +0,0 @@ -From c95a87c3fe519649f8470396461cd19be68bb138 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 10 Nov 2025 16:11:12 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move chosen node from common - to board-specific DTS - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -This commit moves the chosen node configuration from the -common dp1000.dts file to the respective board-specific -DTS files. - -This change allows each board to specify its own console -configuration while keeping the common SoC definitions clean. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ - 3 files changed, 15 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34622a33e63b..34d024a083fc 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-evb-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index a74714629566..8c532e5b71a3 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-mo-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 4a2dae602693..128293c0af1f 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -10,12 +10,7 @@ / { - #size-cells = <0x02>; - compatible = "ultrarisc,dp1000"; - model = "ultrarisc,dp1000"; -- -- chosen { -- bootargs = "earlycon=sbi console=ttyS1,115200"; -- stdout-path = &uart1; -- }; -- -+ - cpus { - #address-cells = <0x01>; - #size-cells = <0x00>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0455-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux-lts/0455-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch new file mode 100644 index 0000000000..bf57eb698d --- /dev/null +++ b/SPECS/linux-lts/0455-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch @@ -0,0 +1,35 @@ +From 0a7fb712936e3739ca0aec162a654b3554e8de8d Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:56 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for + support of bindgen options + +Add a new `bindgen-backend-option` Kconfig function to test whether the +bindgen backend supports a given flag. + +A subsequent commit will use this function to test for RISC-V extension +flags. + +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-3-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + scripts/Kconfig.include | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include +index d42042b6c9e2..9954b8093fab 100644 +--- a/scripts/Kconfig.include ++++ b/scripts/Kconfig.include +@@ -78,3 +78,8 @@ rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) + # If you are testing for unstable features, consider testing RUSTC_VERSION + # instead, as features may have different completeness while available. + rustc-option = $(success,trap "rm -rf .tmp_$$" EXIT; mkdir .tmp_$$; $(RUSTC) $(1) --crate-type=rlib /dev/null --out-dir=.tmp_$$ -o .tmp_$$/tmp.rlib) ++ ++# $(bindgen-backend-option,) ++# Return y if bindgen backend supports , n otherwise ++# For now, the backend refers only to libclang, so more specifically, this function tests whether the given flag is recognized by the libclang used by bindgen. ++bindgen-backend-option = $(success,$(BINDGEN) /dev/null -- -x c --target=$(BINDGEN_TARGET) $(1)) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux-lts/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch deleted file mode 100644 index 47458b4dd9..0000000000 --- a/SPECS/linux-lts/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch +++ /dev/null @@ -1,677 +0,0 @@ -From efed87f8a357dd6937ae5011627de96daf2e7029 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 11 Nov 2025 17:03:37 +0800 -Subject: [RUYI PATCH] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device tree - files - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add gpio-ranges property to all gpio/portX nodes. -This property maps GPIO lines to pin controller pins, -ensuring proper GPIO pin allocation and management. - -Convert dp1000.dts to a common include file (dp1000.dtsi) and update -the board-specific DTS files to include it. This refactoring allows -for better code reuse across different DP1000-based boards (EVB, MO, -and Titan variants) while maintaining board-specific configurations. - -The changes include: -- Renaming dp1000.dts to dp1000.dtsi -- Updating board-specific DTS files to include the common .dtsi -- Adjusting Makefile to reflect these changes -- Updating pinctrl files for all board variants - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 - - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - - .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + - 6 files changed, 263 insertions(+), 277 deletions(-) - rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 9eac56549340..22c03b44b2f8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,4 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index e82fcf2901ab..e2c09d5bdb20 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34d024a083fc..46fe457b5f52 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -index e82fcf2901ab..85b013f66bbd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index 8c532e5b71a3..dc057cbaf59b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-mo-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -similarity index 96% -rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts -rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 128293c0af1f..a25e87e15553 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { - clocks = <&device_clk>; - }; - -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ }; -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -@@ -349,6 +360,7 @@ porta: gpio-port@0 { - #interrupt-cells = <2>; - interrupt-parent = <0x01>; - interrupts = <34>; -+ gpio-ranges = <&pmx0 0 0 16>; - }; - - portb: gpio-port@1 { -@@ -357,6 +369,7 @@ portb: gpio-port@1 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 16 0 8>; - }; - - portc: gpio-port@2 { -@@ -365,6 +378,7 @@ portc: gpio-port@2 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 24 0 8>; - }; - - portd: gpio-port@3 { -@@ -373,6 +387,7 @@ portd: gpio-port@3 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 32 0 8>; - }; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0456-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux-lts/0456-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch new file mode 100644 index 0000000000..5116c4be0a --- /dev/null +++ b/SPECS/linux-lts/0456-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch @@ -0,0 +1,183 @@ +From be97e5642f9d000785f845323dce45e5fc583bf8 Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:57 +0100 +Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, + re-enable gcc + rust builds + +Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC ++ Rust builds for RISC-V due to differences in extension handling +compared to LLVM. This commit enables GCC + Rust builds again. + +Add `bindgen-option` conditions for the availability of libclang to the +RISC-V extension Kconfig symbols that depend on the `cc-option` +function. + +For Zicsr/Zifencei special handling, since LLVM/Clang always enables +these two extensions, either don't pass them to `-march`, or pass them +explicitly and Rust bindgen libclang must recognize them. + +Clang does not support `-mno-riscv-attribute` flag, filter it out to +resolve error: unknown argument: '-mno-riscv-attribute'. + +Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen +libclang for RISC-V to resolve error: unsupported argument 'medany' to +option '-mcmodel=' for target 'unknown'. + +Update the documentation, GCC + Rust builds for RISC-V are now +maintained. + +Acked-by: Miguel Ojeda +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + Documentation/rust/arch-support.rst | 2 +- + arch/riscv/Kconfig | 35 ++++++++++++++++++++++++++++- + rust/Makefile | 3 ++- + scripts/Makefile.rust | 1 + + 4 files changed, 38 insertions(+), 3 deletions(-) + +diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst +index 6e6a515d0899..5282e0e174e8 100644 +--- a/Documentation/rust/arch-support.rst ++++ b/Documentation/rust/arch-support.rst +@@ -18,7 +18,7 @@ Architecture Level of support Constraints + ``arm`` Maintained ARMv7 Little Endian only. + ``arm64`` Maintained Little Endian only. + ``loongarch`` Maintained \- +-``riscv`` Maintained ``riscv64`` and LLVM/Clang only. ++``riscv`` Maintained ``riscv64`` only. + ``um`` Maintained \- + ``x86`` Maintained ``x86_64`` only. + ============= ================ ============================================== +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 12bebdbaaf9f..36112b662884 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -196,7 +196,7 @@ config RISCV + select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_RETHOOK if !XIP_KERNEL + select HAVE_RSEQ +- select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG ++ select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI + select HAVE_SAMPLE_FTRACE_DIRECT + select HAVE_SAMPLE_FTRACE_DIRECT_MULTI + select HAVE_STACKPROTECTOR +@@ -620,6 +620,8 @@ config TOOLCHAIN_HAS_V + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv) + depends on LD_IS_LLD || LD_VERSION >= 23800 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64imv) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32imv) + + config RISCV_ISA_V + bool "Vector extension support" +@@ -684,6 +686,8 @@ config TOOLCHAIN_HAS_ZABHA + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha) + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zabha) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zabha) + + config RISCV_ISA_ZABHA + bool "Zabha extension support for atomic byte/halfword operations" +@@ -702,6 +706,8 @@ config TOOLCHAIN_HAS_ZACAS + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas) + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zacas) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zacas) + + config RISCV_ISA_ZACAS + bool "Zacas extension support for atomic CAS" +@@ -720,6 +726,8 @@ config TOOLCHAIN_HAS_ZBB + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbb) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbb) + + # This symbol indicates that the toolchain supports all v1.0 vector crypto + # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once. +@@ -735,6 +743,8 @@ config TOOLCHAIN_HAS_ZBA + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zba) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zba) + + config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" +@@ -770,6 +780,8 @@ config TOOLCHAIN_HAS_ZBC + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbc) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbc) + + config RISCV_ISA_ZBC + bool "Zbc extension support for carry-less multiplication instructions" +@@ -793,6 +805,8 @@ config TOOLCHAIN_HAS_ZBKB + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbkb) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbkb) + + config RISCV_ISA_ZBKB + bool "Zbkb extension support for bit manipulation instructions" +@@ -880,6 +894,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC + versions of clang and GCC to be passed to GAS, which has the same result + as passing zicsr and zifencei to -march. + ++config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI ++ def_bool y ++ depends on !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zicsr_zifencei) ++ depends on !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zicsr_zifencei) ++ ++config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI ++ def_bool y ++ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 ++ depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI ++ help ++ LLVM/Clang >= 17.0.0 starts recognizing Zicsr/Zifencei in -march, passing ++ them to -march doesn't generate an error anymore, and passing them or not ++ doesn't have any real difference, it still follows ISA before version ++ 20190608 - Zicsr/Zifencei are included in base ISA. ++ ++ The current latest version of LLVM/Clang still does not require explicit ++ Zicsr/Zifencei to enable these two extensions, Clang just accepts them in ++ -march and then silently ignores them. ++ + config FPU + bool "FPU support" + default y +diff --git a/rust/Makefile b/rust/Makefile +index 6d2d542a55e8..046492426017 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -298,7 +298,8 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fno-inline-functions-called-once -fsanitize=bounds-strict \ + -fstrict-flex-arrays=% -fmin-function-alignment=% \ + -fzero-init-padding-bits=% -mno-fdpic \ +- --param=% --param asan-% -fno-isolate-erroneous-paths-dereference ++ --param=% --param asan-% -fno-isolate-erroneous-paths-dereference \ ++ -mno-riscv-attribute + + # Because scripts/Makefile.rust is included regardless of whether Rust is enabled, + # we perform this check here to avoid breaking targets that do not yet support Rust builds. +diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust +index 5c12b4b8c8b6..bfdad4a0a3ce 100644 +--- a/scripts/Makefile.rust ++++ b/scripts/Makefile.rust +@@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 := x86_64-linux-gnu + BINDGEN_TARGET_arm64 := aarch64-linux-gnu + BINDGEN_TARGET_arm := arm-linux-gnueabi + BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf ++BINDGEN_TARGET_riscv := riscv64-linux-gnu + BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) + BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux-lts/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch deleted file mode 100644 index ebf2263e4c..0000000000 --- a/SPECS/linux-lts/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch +++ /dev/null @@ -1,166 +0,0 @@ -From bae8242b84b2c9409608fced96e355aa782dfcd8 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Wed, 12 Nov 2025 15:43:27 +0800 -Subject: [RUYI PATCH] RVCK: riscv: pinctrl: ultrarisc: Implement pin - configuration support - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Update ur_pin_config_set() to use the new configuration handling logic. -This allows the driver to properly handle standard Linux kernel pin -configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, -PIN_CONFIG_BIAS_PULL_DOWN, etc. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- - 3 files changed, 77 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 217f671fe63a..6a7496a465d8 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { - .pins = ur_dp1000_pins, - .npins = ARRAY_SIZE(ur_dp1000_pins), - .offset = 0x2c0, -+ .num_ports = 5, - .ports = { - {"A", 16, 0x2c0, 0x310}, - {"B", 8, 0x2c4, 0x318}, -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index 667d59e0ac6e..edaeca881af7 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { - - #define UR_CONF_BIT_PER_PIN (4) - #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+ -+static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, -+ struct ur_pin_val *pin_val, u32 pin_num) -+{ -+ const struct ur_port_desc *port_desc; -+ -+ for (int i = 0; i < match_data->num_ports; i++) { -+ port_desc = &match_data->ports[i]; -+ if (pin_num < port_desc->npins) { -+ pin_val->port = i; -+ pin_val->pin = pin_num; -+ pin_val->conf = 0; -+ return 0; -+ } -+ pin_num -= port_desc->npins; -+ } -+ return -EINVAL; -+} -+ -+static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, -+ struct ur_pin_val *pin_vals, -+ unsigned long *config) -+{ -+ enum pin_config_param param = pinconf_to_config_param(*config); -+ u32 arg = pinconf_to_config_argument(*config); -+ -+ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", -+ __func__, __LINE__, param, arg); -+ -+ switch (param) { -+ case PIN_CONFIG_BIAS_DISABLE: -+ pin_vals->conf &= ~UR_BIAS_MASK; -+ break; -+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: -+ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); -+ break; -+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: -+ case PIN_CONFIG_BIAS_PULL_DOWN: -+ pin_vals->conf |= UR_PULL_DOWN; -+ break; -+ case PIN_CONFIG_BIAS_PULL_UP: -+ pin_vals->conf |= UR_PULL_UP; -+ break; -+ case PIN_CONFIG_DRIVE_PUSH_PULL: -+ case PIN_CONFIG_PERSIST_STATE: -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ return 0; -+} -+ - static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) - { - const struct ur_port_desc *port_desc; -@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v - u32 val, conf; - - port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", -+ pin_vals->port, pin_vals->pin, pin_vals->conf); - reg = pin_ctrl->base + port_desc->conf_offset; -- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", -+ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); - reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; - dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); - -@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, - unsigned long *configs, - unsigned int num_configs) - { -- struct ur_pin_val *pin_conf; -+ struct ur_pin_val pin_val; - struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ int ret; -+ -+ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid pin number %d\n", pin); -+ return ret; -+ } -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", -+ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); - -- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -- __func__, __LINE__, pin, num_configs); -- pin_conf = (struct ur_pin_val *)configs; - for (int i = 0; i < num_configs; i++) { -- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", -+ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_val); - } - return 0; - } -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -index eec621bf8b05..728b2111def0 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - u32 npins; - u32 offset; -- //u32 conf_offset[]; -+ u32 num_ports; - struct ur_port_desc ports[]; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0457-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux-lts/0457-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch new file mode 100644 index 0000000000..3f84a1dedd --- /dev/null +++ b/SPECS/linux-lts/0457-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch @@ -0,0 +1,45 @@ +From 9d4f7807566149c7cd345ebd0bf77f93a630d667 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 16:38:54 +0800 +Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as + dependencies + +REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on +MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' +does not always respect the parent's dependencies, so 'depends on' +is the safer and more correct choice. + +Since MFD_SPACEMIT_P1 already depends on I2C_K1, the dependency +in REGULATOR_SPACEMIT_P1 is now redundant. + +Additionally, the default value depends on MFD_SPACEMIT_P1 rather +than ARCH_SPACEMIT. + +Acked-by: Mark Brown +Acked-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-1-6fe19f460269@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/regulator/Kconfig | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig +index d84f3d054c59..3701d0fe3e06 100644 +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1455,9 +1455,8 @@ config REGULATOR_SLG51000 + config REGULATOR_SPACEMIT_P1 + tristate "SpacemiT P1 regulators" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on I2C +- select MFD_SPACEMIT_P1 +- default ARCH_SPACEMIT ++ depends on MFD_SPACEMIT_P1 ++ default m if MFD_SPACEMIT_P1 + help + Enable support for regulators implemented by the SpacemiT P1 + power controller. The P1 implements 6 high-efficiency buck +-- +2.53.0 + diff --git a/SPECS/linux-lts/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux-lts/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch deleted file mode 100644 index ca0081cabf..0000000000 --- a/SPECS/linux-lts/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch +++ /dev/null @@ -1,364 +0,0 @@ -From 90a72c61206582a7f4df5b88119e6602cbafc201 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 18 Nov 2025 13:48:49 +0800 -Subject: [RUYI PATCH] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V Titan - board based on UltraRISC DP1000 SoC - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan -board. The Titan board is designed by Milk-V and is based on the UltraRISC -DP1000 SoC. These device tree files provide the initial support for the -board, including pinctrl and basic peripheral configuration. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 + - .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ - 3 files changed, 313 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 22c03b44b2f8..df8efe1a3ed7 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -new file mode 100644 -index 000000000000..35429e539832 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart3_pins: uart3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 6 UR_FUNC0 -+ UR_DP1000_IOMUX_C 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ UR_DP1000_IOMUX_A 4 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ gpios_pin: gpios_pin { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF -+ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -new file mode 100644 -index 000000000000..2cbdfa2ad813 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000-titan-pinctrl.dtsi" -+#include -+#include -+#include -+#include -+ -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&portb 0 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "power-off"; -+ status = "okay"; -+ }; -+ -+ gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&portb 1 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "reset-system"; -+ status = "okay"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ key-wakeup { -+ label = "Wake-Up"; -+ gpios = <&porta 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ linux,input-type = ; -+ debounce-interval = <10>; -+ wakeup-source; -+ wakeup-event-action = ; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@68 { -+ compatible = "st,m41t11"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+}; -+ -+&porta { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpios_pin>; -+ -+ i2c1-mux-hog { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ /* LOW: DCDC(U6) connect MCU(EC) -+ * HIGH: DCDC(U6) connect CPU -+ */ -+ output-low; -+ line-name = "gpio-mux-dcdc"; -+ }; -+ -+ i2c3-mux-hog { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_LOW>; -+ /* LOW: CPU i2c3 connect nvme -+ * HIGH: CPU i2c3 connect pciex16 -+ */ -+ output-low; -+ line-name = "gpio-mux-i2c3"; -+ }; -+ -+ uart0-mux-hog { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ /* LOW: uart_debug connect BMC -+ * HIGH: uart_debug connect CPU -+ */ -+ output-high; -+ line-name = "gpio-mux-debug"; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0458-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux-lts/0458-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch new file mode 100644 index 0000000000..559cbb12bc --- /dev/null +++ b/SPECS/linux-lts/0458-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch @@ -0,0 +1,37 @@ +From 51a4c9295dc51a46adb40ccb9cdbc7934f3ae495 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 16:38:56 +0800 +Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when + MFD_SPACEMIT_P1 is enabled + +The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which +caused it to be built-in automatically whenever the PMIC support was +set to y. + +This is not always desirable, as the RTC function is not required on +all platforms using the SpacemiT P1 PMIC. + +Acked-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-3-6fe19f460269@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/rtc/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index b392e6d096ed..4fc77f6b8a72 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -410,7 +410,7 @@ config RTC_DRV_SPACEMIT_P1 + tristate "SpacemiT P1 RTC" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on MFD_SPACEMIT_P1 +- default MFD_SPACEMIT_P1 ++ default m if MFD_SPACEMIT_P1 + help + Enable support for the RTC function in the SpacemiT P1 PMIC. + This driver can also be built as a module, which will be called +-- +2.53.0 + diff --git a/SPECS/linux-lts/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux-lts/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch deleted file mode 100644 index 7b6568d84b..0000000000 --- a/SPECS/linux-lts/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch +++ /dev/null @@ -1,77 +0,0 @@ -From ad2ca89827235515c3cfea8822ac22544a6f79f1 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 23 Feb 2026 14:35:29 +0800 -Subject: [RUYI PATCH] REVYSR: pinctrl: ultrarisc: cleanup probe&remove - -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- - 2 files changed, 3 insertions(+), 20 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 6a7496a465d8..0ead138c9d1f 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { - .of_match_table = ur_pinctrl_of_match, - }, - .probe = ur_pinctrl_probe, -- .remove = ur_pinctrl_remove, - }; - - module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index edaeca881af7..cdd7160f3183 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); - if (!ur_pinctrl) { - dev_err(&pdev->dev, "pinctrl alloc failed\n"); -- ret = -ENOMEM; -- goto free_pinctrl_desc; -+ return -ENOMEM; - } - struct resource *res; - -@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ur_pinctrl->base)) { - dev_err(&pdev->dev, "get ioremap resource failed\n"); -- ret = -EINVAL; -- goto free_pinctrl_desc; -+ return -EINVAL; - } - dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); - ur_pinctrl_desc->name = dev_name(&pdev->dev); -@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl, &ur_pinctrl->pctl_dev); - if (ret) { - dev_err(&pdev->dev, "pinctrl register failed\n"); -- goto free_pinctrl; -+ return ret; - } - - platform_set_drvdata(pdev, ur_pinctrl); - - return pinctrl_enable(ur_pinctrl->pctl_dev); -- --free_pinctrl: -- devm_kfree(&pdev->dev, ur_pinctrl); --free_pinctrl_desc: -- devm_kfree(&pdev->dev, ur_pinctrl_desc); -- return ret; - } - -- --void ur_pinctrl_remove(struct platform_device *pdev) --{ -- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -- -- if (ur_pinctrl->pctl_dev) -- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); --} --- -2.53.0 - diff --git a/SPECS/linux-lts/0459-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux-lts/0459-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch new file mode 100644 index 0000000000..e92cce8ec3 --- /dev/null +++ b/SPECS/linux-lts/0459-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch @@ -0,0 +1,57 @@ +From fe76dddf31c17cfb0bcb998537c23161cc793091 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 17:24:21 +0800 +Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after + unmapping DMA + +In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA +before calling kfree() to deallocate the memory, instead of the other +way around. + +Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC") +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-4-0ab0122fdd14@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index 359b409f8203..48c80c075fdf 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -463,12 +463,12 @@ static void emac_free_tx_resources(struct emac_priv *priv) + + emac_clean_tx_desc_ring(priv); + +- kfree(tr->tx_desc_buf); +- tr->tx_desc_buf = NULL; +- + dma_free_coherent(dev, tr->total_size, tr->desc_addr, + tr->desc_dma_addr); + tr->desc_addr = NULL; ++ ++ kfree(tr->tx_desc_buf); ++ tr->tx_desc_buf = NULL; + } + + static void emac_free_rx_resources(struct emac_priv *priv) +@@ -478,12 +478,12 @@ static void emac_free_rx_resources(struct emac_priv *priv) + + emac_clean_rx_desc_ring(priv); + +- kfree(rr->rx_desc_buf); +- rr->rx_desc_buf = NULL; +- + dma_free_coherent(dev, rr->total_size, rr->desc_addr, + rr->desc_dma_addr); + rr->desc_addr = NULL; ++ ++ kfree(rr->rx_desc_buf); ++ rr->rx_desc_buf = NULL; + } + + static int emac_tx_clean_desc(struct emac_priv *priv) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux-lts/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch deleted file mode 100644 index 3ab0a8fab6..0000000000 --- a/SPECS/linux-lts/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 3a0ec292f418c3f0ec2630531aeab29eea263f22 Mon Sep 17 00:00:00 2001 -From: U2FsdGVkX1 -Date: Sun, 29 Mar 2026 15:31:14 +0000 -Subject: [RUYI PATCH] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie - for PCIe nodes - -Signed-off-by: U2FsdGVkX1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index a25e87e15553..78e0cda1fcb9 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { - }; - - pcie_x16: pcie@21000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { - }; - - pcie_x4a: pcie@23000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { - }; - - pcie_x4b: pcie@24000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0460-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux-lts/0460-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch new file mode 100644 index 0000000000..ed21dc9f9a --- /dev/null +++ b/SPECS/linux-lts/0460-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch @@ -0,0 +1,33 @@ +From 489d0a8540aa197ecba524f862ae9a022e756ad2 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Fri, 26 Jun 2026 16:10:23 +0800 +Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to + the allowlist + +Add the compatible string for supporting the generic +cpufreq driver on the SpacemiT K1 SoC. + +Signed-off-by: Shuwei Wu +Tested-by: Gong Shuai # OrangePi-RV2 +Link: https://lore.kernel.org/r/20260626-shadow-deps-v4-1-bba9831f2f1d@mailbox.org +Signed-off-by: Han Gao +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index 47dd76acd31e..8d37426273df 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -81,6 +81,8 @@ static const struct of_device_id allowlist[] __initconst = { + { .have_governor_per_policy = true, }, + }, + ++ { .compatible = "spacemit,k1", }, ++ + { .compatible = "st-ericsson,u8500", }, + { .compatible = "st-ericsson,u8540", }, + { .compatible = "st-ericsson,u9500", }, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux-lts/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch deleted file mode 100644 index 732de29759..0000000000 --- a/SPECS/linux-lts/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch +++ /dev/null @@ -1,450 +0,0 @@ -From 3091a1fa3451d492041d5cc22aeb46f67edaf469 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 13 Feb 2025 15:50:12 +0800 -Subject: [RUYI PATCH] ULTRARISC: hwmon: add corepvt driver of UltraRISC DP1000 - -From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 - -UltraRISC Corepvt driver supports cluster voltage -and core temperature detection - -Signed-off-by: Jia Wang -Signed-off-by: Han Gao ---- - drivers/hwmon/Kconfig | 9 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ - 3 files changed, 400 insertions(+) - create mode 100644 drivers/hwmon/corepvt-ultrarisc.c - -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 2a71b6e834b0..2a44030c7796 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 - To compile this driver as a module, choose M here: the module - will be called chipcap2. - -+config SENSORS_COREPVT_ULTRARISC -+ tristate "UltraRISC Core Voltage, Temperature sensor driver" -+ help -+ If you say yes here you get support for UltraRISC Core PVT sensor -+ embedded into the SoC. -+ -+ This driver can also be built as a module. If so, the module will be -+ called corepvt-ultrarisc. -+ - config SENSORS_CORSAIR_CPRO - tristate "Corsair Commander Pro controller" - depends on HID -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 73b2abdcc6dd..6cf5fac80b7b 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o - obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o - obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o - obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o -+obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o - obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o - obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o - obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o -diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c -new file mode 100644 -index 000000000000..3674eedefbda ---- /dev/null -+++ b/drivers/hwmon/corepvt-ultrarisc.c -@@ -0,0 +1,390 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Driver for UltraRISC Core PVT -+ * -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define COREPVT_CHL_OFFSET 0x1000 -+#define COREPVT_REG_CIR 0x0 -+#define COREPVT_REG_PSCR 0x04 -+#define COREPVT_REG_CFDR 0x08 -+#define COREPVT_REG_DOR 0x0C -+#define COREPVT_REG_ICR 0x10 -+#define COREPVT_REG_IER 0x14 -+#define COREPVT_REG_IMSR 0x18 -+#define COREPVT_REG_IRSR 0x1C -+ -+#define PVT_MAX_CHANNEL 64 -+#define PVT_TRIM_DEFAULT 0x7 -+ -+struct corepvt_channel_config { -+ const char *label; -+ u32 trim; -+}; -+ -+struct corepvt_cal_data { -+ u32 val_offset; -+ u32 val_lsb; -+}; -+ -+struct corepvt_data { -+ const struct hwmon_chip_info *chip_info; -+ u64 temp_chl_mask; -+ u64 vol_chl_mask; -+}; -+ -+struct corepvt_hwmon { -+ struct device *dev; -+ struct device *hwmon; -+ -+ void __iomem *regs; -+ int irq; -+ int clk_freq; -+ int channels; -+ const struct hwmon_chip_info *chip_info; -+ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; -+ const struct corepvt_data *pvt_data; -+ raw_spinlock_t lock; -+}; -+ -+#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ -+#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ -+#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ -+#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ -+ -+static int corepvt_read_vol(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the voltage channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; -+ -+ return 0; -+} -+ -+static int corepvt_read_temp(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the temperature channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; -+ -+ return 0; -+} -+ -+static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct corepvt_hwmon *pvt = drvdata; -+ -+ if (channel >= pvt->channels) -+ return 0; -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ case hwmon_in_label: -+ return 0444; -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_type: -+ case hwmon_temp_label: -+ return 0444; -+ } -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ return corepvt_read_vol(pvt, channel, val); -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_type: -+ *val = 1; -+ return 0; -+ case hwmon_temp_input: -+ return corepvt_read_temp(pvt, channel, val); -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return -ENODATA; -+} -+ -+static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, const char **str) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ u32 chl_offset = 0; -+ -+ switch (type) { -+ case hwmon_in: -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ break; -+ case hwmon_temp: -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ break; -+ default: -+ return -ENODATA; -+ break; -+ } -+ -+ *str = pvt->config[channel + chl_offset].label; -+ -+ return 0; -+} -+ -+/* -+ * corepvt init process: -+ * 1. config SETUP time, should be 10us, set PSCR register -+ * 2. config CLKIN, should be 4MHz, set CFDR register -+ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR -+ * 4. config TRIM and enable PVT, set CIR -+ */ -+static int corepvt_init(struct corepvt_hwmon *pvt) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ /* -+ * SETUP time 10us = 100KHz -+ * PSCR = CLK_FREQ / 100KHz -+ */ -+ u32 pscr_val = pvt->clk_freq / 100000; -+ /* -+ * CFDR = CLK_FREQ / 4MHz / 2 -+ */ -+ u32 cfdr_val = pvt->clk_freq / 8000000; -+ /* -+ * CIR: -+ * bit[0]: PU_VTDC, set 1 to enable pvt -+ * bit[5:2]: TRIM -+ */ -+ u32 cir_val; -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ for (int i = 0; i < pvt->channels; i++) { -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; -+ cir_val = (pvt->config[i].trim << 2) | 0x01; -+ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); -+ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); -+ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); -+ } -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ return 0; -+} -+ -+static const struct hwmon_ops corepvt_hwmon_ops = { -+ .is_visible = corepvt_is_visible, -+ .read = corepvt_read, -+ .read_string = corepvt_read_string, -+}; -+ -+static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) -+{ -+ struct device_node *child; -+ int ret; -+ u32 channel; -+ const char *label; -+ u32 trim; -+ -+ for_each_child_of_node(pdev->dev.of_node, child) { -+ if (!of_node_name_eq(child, "channel")) -+ continue; -+ -+ ret = of_property_read_u32(child, "reg", &channel); -+ if (ret) -+ goto node_put; -+ -+ ret = of_property_read_string(child, "label", &label); -+ if (ret) -+ goto node_put; -+ -+ if (of_property_present(child, "trim")) -+ of_property_read_u32(child, "trim", &trim); -+ else -+ trim = PVT_TRIM_DEFAULT; -+ -+ pvt->config[channel].label = label; -+ pvt->config[channel].trim = trim; -+ } -+ -+ return 0; -+ -+node_put: -+ of_node_put(child); -+ return ret; -+} -+ -+static int corepvt_probe(struct platform_device *pdev) -+{ -+ struct corepvt_hwmon *pvt; -+ const struct corepvt_data *pvt_data; -+ int ret; -+ -+ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); -+ if (!pvt) -+ return -ENOMEM; -+ -+ pvt->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(pvt->regs)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ if (device_property_present(&pdev->dev, "interrupts")) -+ pvt->irq = platform_get_irq(pdev, 0); -+ -+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); -+ if (ret) { -+ dev_err(&pdev->dev, "get clock-frequency failed\n"); -+ goto free_pvt; -+ } -+ -+ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); -+ if (ret) { -+ dev_err(&pdev->dev, "get channels failed\n"); -+ goto free_pvt; -+ } -+ -+ pvt_data = device_get_match_data(&pdev->dev); -+ if (!pvt_data) { -+ dev_err(&pdev->dev, "No chip info found\n"); -+ ret = -ENODATA; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ pvt->chip_info = pvt_data->chip_info; -+ pvt->pvt_data = pvt_data; -+ -+ if (pdev->dev.of_node) { -+ ret = corepvt_probe_channel_from_dt(pdev, pvt); -+ if (ret) -+ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); -+ } -+ -+ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", -+ pvt, pvt->chip_info, -+ NULL); -+ if (IS_ERR(pvt->hwmon)) { -+ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ raw_spin_lock_init(&pvt->lock); -+ -+ // Config and enable corepvt -+ corepvt_init(pvt); -+ -+ return 0; -+ -+free_pvt: -+ devm_kfree(&pdev->dev, pvt); -+ return ret; -+} -+ -+static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL), -+ HWMON_CHANNEL_INFO(in, -+ HWMON_I_INPUT | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_LABEL), -+ NULL -+}; -+ -+static const struct hwmon_chip_info ur_dp1000_chip_info = { -+ .ops = &corepvt_hwmon_ops, -+ .info = ur_dp1000_channel_info, -+}; -+ -+static struct corepvt_data ur_dp1000_pvt_data = { -+ .chip_info = &ur_dp1000_chip_info, -+ .temp_chl_mask = GENMASK_ULL(10, 0), -+ .vol_chl_mask = GENMASK_ULL(12, 11) -+}; -+ -+static const struct of_device_id corepvt_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, corepvt_of_match); -+ -+static struct platform_driver corepvt_driver = { -+ .probe = corepvt_probe, -+ .driver = { -+ .name = "corepvt-ultrarisc", -+ .of_match_table = corepvt_of_match -+ } -+}; -+module_platform_driver(corepvt_driver); -+ -+MODULE_AUTHOR("Jia Wang "); -+MODULE_DESCRIPTION("corepvt-ultrarisc driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0461-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux-lts/0461-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch new file mode 100644 index 0000000000..11317035e7 --- /dev/null +++ b/SPECS/linux-lts/0461-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch @@ -0,0 +1,267 @@ +From a6cef789e1aadc2510ae9cb9c4417da34582a866 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Fri, 26 Jun 2026 16:10:24 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 + SoC + +Add CPU clock properties and OPP tables for the two CPU clusters in the +SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU +supply is shared by both clusters. + +Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and +wiring the CPU nodes to the CPU regulator supply. + +Signed-off-by: Shuwei Wu +Tested-by: Andre Heider # k1-musepi-pro +Tested-by: Gong Shuai # OrangePi-RV2 +Link: https://lore.kernel.org/r/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- + arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ + 3 files changed, 147 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 72f77e9edd63..307a7e4a8943 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -4,6 +4,7 @@ + */ + + #include "k1.dtsi" ++#include "k1-opp.dtsi" + #include "k1-pinctrl.dtsi" + + / { +@@ -87,6 +88,38 @@ &combo_phy { + status = "okay"; + }; + ++&cpu_0 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_1 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_2 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_3 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_4 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_5 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_6 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_7 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ + &emmc { + bus-width = <8>; + mmc-hs400-1_8v; +@@ -202,7 +235,7 @@ pmic@41 { + dldoin2-supply = <&buck5>; + + regulators { +- buck1 { ++ buck1_0v9: buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi +new file mode 100644 +index 000000000000..4cebfcd87485 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/ { ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-614400000 { ++ opp-hz = /bits/ 64 <614400000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-819000000 { ++ opp-hz = /bits/ 64 <819000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1228800000 { ++ opp-hz = /bits/ 64 <1228800000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1600000000 { ++ opp-hz = /bits/ 64 <1600000000>; ++ opp-microvolt = <1050000 1050000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-614400000 { ++ opp-hz = /bits/ 64 <614400000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-819000000 { ++ opp-hz = /bits/ 64 <819000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1228800000 { ++ opp-hz = /bits/ 64 <1228800000>; ++ opp-microvolt = <950000 950000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1600000000 { ++ opp-hz = /bits/ 64 <1600000000>; ++ opp-microvolt = <1050000 1050000 1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++}; ++ ++&cpu_0 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_1 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_2 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_3 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_4 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_5 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_6 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_7 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 08a0f28d011f..4a359190f633 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -54,6 +54,7 @@ cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -84,6 +85,7 @@ cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -114,6 +116,7 @@ cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -144,6 +147,7 @@ cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -174,6 +178,7 @@ cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -204,6 +209,7 @@ cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -234,6 +240,7 @@ cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -264,6 +271,7 @@ cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +-- +2.53.0 + diff --git a/SPECS/linux-lts/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux-lts/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch deleted file mode 100644 index 0582b1d016..0000000000 --- a/SPECS/linux-lts/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +++ /dev/null @@ -1,732 +0,0 @@ -From 817a4331068207be97f31dbe87e3512e92b549de Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 12 Apr 2026 02:50:03 +0800 -Subject: [RUYI PATCH] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi - -FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- - 1 file changed, 489 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 78e0cda1fcb9..7b7016618dcd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -22,121 +22,491 @@ cpu0: cpu@0 { - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache0>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu0_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache0: l2-cache0 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu1: cpu@1 { - device_type = "cpu"; - reg = <0x1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache1>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu1_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache1: l2-cache1 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu2: cpu@2 { - device_type = "cpu"; - reg = <0x2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache2>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu2_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache2: l2-cache2 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu3: cpu@3 { - device_type = "cpu"; - reg = <0x3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache3>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu3_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache3: l2-cache3 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu4: cpu@4 { - device_type = "cpu"; - reg = <0x10>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache4>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu4_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache4: l2-cache4 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu5: cpu@5 { - device_type = "cpu"; - reg = <0x11>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache5>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu5_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache5: l2-cache5 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu6: cpu@6 { - device_type = "cpu"; - reg = <0x12>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; -- - clock-frequency = <2000000000>; -- -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache6>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu6_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache6: l2-cache6 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu7: cpu@7 { - device_type = "cpu"; - reg = <0x13>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache7>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu7_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache7: l2-cache7 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; -+ }; -+ -+ cpu-map { -+ cluster0: cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ core2 { -+ cpu = <&cpu2>; -+ }; -+ core3 { -+ cpu = <&cpu3>; -+ }; -+ -+ cluster0_l3: l3-cache0 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; -+ -+ cluster1: cluster1 { -+ core0 { -+ cpu = <&cpu4>; -+ }; -+ core1 { -+ cpu = <&cpu5>; -+ }; -+ core2 { -+ cpu = <&cpu6>; -+ }; -+ core3 { -+ cpu = <&cpu7>; -+ }; -+ cluster1_l3: l3-cache1 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; - }; - }; - -@@ -150,6 +520,20 @@ soc { - #size-cells = <0x02>; - compatible = "simple-bus"; - ranges; -+ -+ l4_cache: l4-cache { -+ /* L4 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 16MB -+ * shared by the SoC. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <4>; -+ cache-size = <0x1000000>; -+ cache-sets = <0x4000>; -+ cache-unified; -+ }; - - clocks { - compatible = "simple-bus"; -@@ -160,6 +544,12 @@ device_clk: device_clk { - #clock-cells = <0>; - }; - -+ timer_clk: timer_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+ #clock-cells = <0>; -+ }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -170,35 +560,102 @@ csr_clk: csr_clk { - clint: clint@8000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; - reg = <0x00 0x8000000 0x00 0x100000>; - }; -- -+ - plic: plic@9000000 { - #interrupt-cells = <1>; - #address-cells = <0>; -- phandle = <0x01>; -- compatible = "ultrarisc,dp1000-plic"; -+ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; - interrupt-controller; - interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; - reg = <0x00 0x9000000 0x00 0x4000000>; - riscv,max-priority = <0x07>; - riscv,ndev = <160>; - }; -- -+ -+ core_pvt: pvt@110D0000 { -+ compatible = "ultrarisc,dp1000-pvt"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00 0x110D0000 0x00 0x0000D000>; -+ clock-frequency = <250000000>; -+ channels = <13>; -+ -+ #thermal-sensor-cells = <1>; -+ channel@0 { -+ label = "Core temp0"; -+ reg = <0>; -+ }; -+ -+ channel@1 { -+ label = "Core temp1"; -+ reg = <1>; -+ }; -+ -+ channel@2 { -+ label = "Core temp2"; -+ reg = <2>; -+ }; -+ -+ channel@3 { -+ label = "Core temp3"; -+ reg = <3>; -+ }; -+ -+ channel@4 { -+ label = "Core temp4"; -+ reg = <4>; -+ }; -+ -+ channel@5 { -+ label = "Core temp5"; -+ reg = <5>; -+ }; -+ channel@6 { -+ label = "Core temp6"; -+ reg = <6>; -+ }; -+ channel@7 { -+ label = "Core temp7"; -+ reg = <7>; -+ }; -+ channel@8 { -+ label = "Core temp8"; -+ reg = <8>; -+ }; -+ channel@9 { -+ label = "Core temp9"; -+ reg = <9>; -+ }; -+ channel@10 { -+ label = "Core temp10"; -+ reg = <10>; -+ }; -+ channel@11 { -+ label = "Cluster0 voltage"; -+ reg = <11>; -+ }; -+ channel@12 { -+ label = "Cluster1 voltage"; -+ reg = <12>; -+ }; -+ }; -+ - uart0: serial@20300000 { - interrupt-parent = <0x01>; - interrupts = <17>; -@@ -244,7 +701,7 @@ uart3: serial@20410000 { - }; - - spi0: spi@20320000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -258,7 +715,7 @@ spi0: spi@20320000 { - }; - - spi1: spi@20420000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { - num-lanes = <16>; - ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -- max-link-speed = <4>; -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <16>; - interrupt-parent = <&plic>; -- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, - <0x0 0x0 0x0 0x2 &plic 45>, -@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <63>, <64>, <65>, <66>, <67>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, - <0x0 0x0 0x0 0x2 &plic 65>, -@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <73>, <74>, <75>, <76>, <77>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, - <0x0 0x0 0x0 0x2 &plic 75>, --- -2.53.0 - diff --git a/SPECS/linux-lts/0462-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux-lts/0462-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch new file mode 100644 index 0000000000..2c733ae413 --- /dev/null +++ b/SPECS/linux-lts/0462-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch @@ -0,0 +1,84 @@ +From 4108a2c32f1c17beab2e4fef0cc9a3c8837300e7 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Tue, 17 Mar 2026 16:48:06 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other + CPUs before reboot/shutdown + +Currently, the RISC-V implementation of machine_restart(), machine_halt(), +and machine_power_off() invokes the kernel teardown chains (e.g., +do_kernel_restart()) with local interrupts enabled and other CPUs still +running. + +This implementation fails to provide a deterministic execution environment +for registered handlers in the restart or power-off notifier chains. These +chains are intended to be executed in a strict atomic and single-threaded +context. + +Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increment +the preempt_count. If local interrupts remain enabled, the environment +is not guaranteed to be atomic. This can lead to a context misidentification +within generic kernel teardown code, causing it to incorrectly enter +non-atomic paths (such as attempting to acquire sleeping locks), which +results in fatal "scheduling while atomic" splats or system hangs. + +Additionally, stopping other CPUs ensures the primary CPU has exclusive +access to the hardware state during the final teardown phase, preventing +unpredictable interference from other active cores. + +Align RISC-V with other major architectures by disabling local interrupts +and stopping other CPUs at the beginning of the shutdown sequences. This +guarantees the architectural expectations of the kernel's restart and +power-off handlers are met. + +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Link: https://lore.kernel.org/all/abEP80FoCn4S4-WG@aurel32.net/ [1] +Link: https://lore.kernel.org/r/20260317-v7-0-rc1-rv-dis-int-before-restart-v2-1-0ecc85fbb7ff@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/kernel/reset.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c +index 912288572226..8c48466c50e9 100644 +--- a/arch/riscv/kernel/reset.c ++++ b/arch/riscv/kernel/reset.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + + static void default_power_off(void) + { +@@ -17,18 +18,27 @@ EXPORT_SYMBOL(pm_power_off); + + void machine_restart(char *cmd) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_restart(cmd); + while (1); + } + + void machine_halt(void) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_power_off(); + default_power_off(); + } + + void machine_power_off(void) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_power_off(); + default_power_off(); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch deleted file mode 100644 index f7231a5dd3..0000000000 --- a/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 360a4acac1e14c683370c4ffa8f3e85733ca0207 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 24 Jan 2026 08:48:53 +0800 -Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support - -FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 - -The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub -which fully USB2.0 protocol compliant and provides 4 ports. - -Signed-off-by: Yixun Lan -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ - 2 files changed, 56 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 61cbf924830b..ac965ec83f2c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ aux_vcc3v3: regulator-aux-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - }; - - &i2c8 { -@@ -255,3 +264,19 @@ &uart0 { - pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -+ -+&usb2_host { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ vdd-supply = <&aux_vcc3v3>; -+ }; -+}; -+ -+&usb2_phy { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index ed046714a7ac..1b86c872accb 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb2_host: usb@c0a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, -+ <&syscon_apmu RESET_APMU_USB2_VCC>, -+ <&syscon_apmu RESET_APMU_USB2_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ dr_mode = "host"; -+ maximum-speed = "high-speed"; -+ status = "disabled"; -+ }; -+ -+ usb2_phy: phy@c0a20000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0xc0a20000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0463-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux-lts/0463-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch new file mode 100644 index 0000000000..6d5912b805 --- /dev/null +++ b/SPECS/linux-lts/0463-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch @@ -0,0 +1,39 @@ +From 7d7f234e12191d9c9ec0b097efa23976191b35d9 Mon Sep 17 00:00:00 2001 +From: Felix Gu +Date: Sat, 21 Mar 2026 03:12:10 +0800 +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on + dw_hdmi_probe() return value + +The error check after calling dw_hdmi_probe() was incorrectly checking +the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. + +Fix this by checking the correct variable. + +Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") +Signed-off-by: Felix Gu +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260321-th1520-v1-1-ec877197770d@gmail.com +Signed-off-by: Han Gao +--- + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +index 389eead5f1c4..c9968ec1823c 100644 +--- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -136,8 +136,8 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) + plat_data->priv_data = hdmi; + + hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); +- if (IS_ERR(hdmi)) +- return PTR_ERR(hdmi); ++ if (IS_ERR(hdmi->dw_hdmi)) ++ return PTR_ERR(hdmi->dw_hdmi); + + platform_set_drvdata(pdev, hdmi); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch deleted file mode 100644 index 7871de10b3..0000000000 --- a/SPECS/linux-lts/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 8b65d5e0ae467754eccf77dddcd58ae11ea35cdd Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Mon, 5 Jan 2026 20:05:04 +0800 -Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is - not cacheable - -FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f - -Change-Id: I040d597ee246777767f7be747fa9202154524538 -[ Vivian: Rebase and move check into enter_vector_usercopy ] -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/uaccess.h | 5 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/riscv_v_helpers.c | 5 +++ - arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ - 4 files changed, 76 insertions(+) - create mode 100644 arch/riscv/lib/uaccess_cache_check.c - -diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h -index 6aef591a6bfc..b028208b05ec 100644 ---- a/arch/riscv/include/asm/uaccess.h -+++ b/arch/riscv/include/asm/uaccess.h -@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } - if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ - goto label; - -+/* Memory cacheability check for vector uaccess optimization */ -+#ifdef CONFIG_RISCV_ISA_V -+int is_cacheable_safe(const void *addr); -+#endif -+ - #else /* CONFIG_MMU */ - #include - #endif /* CONFIG_MMU */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 735d0b665536..43fe69db9803 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -14,6 +14,7 @@ endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) - lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o -+lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o - endif - lib-$(CONFIG_MMU) += uaccess.o - lib-$(CONFIG_64BIT) += tishift.o -diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c -index 7bbdfc6d4552..7ab2cea280f8 100644 ---- a/arch/riscv/lib/riscv_v_helpers.c -+++ b/arch/riscv/lib/riscv_v_helpers.c -@@ -8,6 +8,7 @@ - - #include - #include -+#include - - #ifdef CONFIG_MMU - #include -@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, - if (!may_use_simd()) - goto fallback; - -+ /* HACK */ -+ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) -+ goto fallback; -+ - kernel_vector_begin(); - remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : - __asm_vector_usercopy_sum_enabled(dst, src, n); -diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c -new file mode 100644 -index 000000000000..0b0996fa2d37 ---- /dev/null -+++ b/arch/riscv/lib/uaccess_cache_check.c -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Memory cacheability check for RISC-V uaccess optimization -+ * -+ * This file provides a C function that can be called from assembly -+ * to determine if a buffer is cacheable before using vector instructions. -+ */ -+ -+#include -+#include -+#include -+ -+/** -+ * is_cacheable_safe - Check if memory buffer is cacheable -+ * @addr: Virtual address to check (kernel or user space) -+ * -+ * Returns: 1 if cacheable, 0 if non-cacheable -+ * -+ * This function is designed to be called from assembly code in uaccess.S -+ * to determine if vector instructions are safe to use for memory copy. -+ * -+ * Non-cacheable memory (device IO, DMA coherent buffers) should not use -+ * vector instructions as they may cause cache coherency issues. -+ * -+ * Handles both kernel and user space addresses safely: -+ * - Kernel direct mapping: Always cacheable -+ * - Kernel vmalloc: Check VM flags -+ * - User space: Check page table (most are cacheable) -+ * - ioremap/DMA: Non-cacheable -+ */ -+int is_cacheable_safe(const void *addr) -+{ -+ unsigned long vaddr = (unsigned long)addr; -+ -+ /* Kernel direct mapped memory - always cacheable */ -+ if (virt_addr_valid(addr)) -+ return 1; -+ -+ if (vaddr < TASK_SIZE) { -+ /* -+ * User space address, Determine it as a cacheable buffer, -+ * maybe not safe!! -+ */ -+ return 1; -+ } -+ -+ /* Check if it's a vmalloc region (kernel virtual address) */ -+ if (is_vmalloc_addr(addr)) { -+ struct vm_struct *vm; -+ -+ vm = find_vm_area(addr); -+ if (!vm) -+ return 0; -+ -+ /* Exclude ioremap and DMA coherent buffers */ -+ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) -+ return 0; -+ -+ /* Normal vmalloc - cacheable */ -+ return 1; -+ } -+ -+ /* Unknown kernel region - assume non-cacheable for safety */ -+ return 0; -+} --- -2.53.0 - diff --git a/SPECS/linux-lts/0464-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux-lts/0464-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch new file mode 100644 index 0000000000..d11395b288 --- /dev/null +++ b/SPECS/linux-lts/0464-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch @@ -0,0 +1,43 @@ +From b3a415a826bf0b3679416bd4c7dd0547fafe05df Mon Sep 17 00:00:00 2001 +From: Felix Gu +Date: Sat, 21 Mar 2026 03:12:11 +0800 +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() + callback + +This driver stores struct th1520_hdmi * in platform drvdata, but +th1520_dw_hdmi_remove() was reading it back as struct dw_hdmi * +and passing it to dw_hdmi_remove(), so teardown runs on the wrong +pointer. + +Retrieve struct th1520_hdmi * from platform drvdata and pass +hdmi->dw_hdmi to dw_hdmi_remove(). + +Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") +Signed-off-by: Felix Gu +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260321-th1520-v1-2-ec877197770d@gmail.com +Signed-off-by: Han Gao +--- + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +index c9968ec1823c..6ec9003a8f3f 100644 +--- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -146,9 +146,9 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) + + static void th1520_dw_hdmi_remove(struct platform_device *pdev) + { +- struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ struct th1520_hdmi *hdmi = platform_get_drvdata(pdev); + +- dw_hdmi_remove(hdmi); ++ dw_hdmi_remove(hdmi->dw_hdmi); + } + + static const struct of_device_id th1520_dw_hdmi_of_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux-lts/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch deleted file mode 100644 index 2a03ed4e12..0000000000 --- a/SPECS/linux-lts/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 675808049c603e6935816557a160a1d7f6eb5495 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:01:58 +0800 -Subject: [RUYI PATCH] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb - phy support - -The USB3/PCIe comb PHY on the K3 is a complex PHY group that -can provide multiple phy for both PCIe and USB controller. -Its mux configuration is controlled by the APMU syscon device. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -new file mode 100644 -index 000000000000..eafc753b7e9b ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 PCIE/USB3 Comb PHY -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ const: spacemit,k3-combo-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 2 -+ description: -+ The first one is phy id, the second one is phy type. -+ -+ spacemit,apb-spare: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Phandle to APB SPARE system controller interface, used for -+ PHY calibration. -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle of APMU syscon -+ - description: configuration of the PHY lanes -+ description: | -+ Phandle to control PHY mux configuration. The configuration -+ is described as follows: -+ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode -+ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode -+ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode -+ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode -+ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode -+ -+ The bit[3:0] is only valid when bit 4 is 1. -+ -+required: -+ - compatible -+ - reg -+ - "#phy-cells" -+ - spacemit,apb-spare -+ - spacemit,apmu -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x81d00000 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&apb_spare>; -+ spacemit,apmu = <&apmu 0x00>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0465-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux-lts/0465-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch new file mode 100644 index 0000000000..7178b45152 --- /dev/null +++ b/SPECS/linux-lts/0465-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch @@ -0,0 +1,83 @@ +From 71f06799692814cdd5d371b34e71bb4ad361c7bb Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Tue, 31 Mar 2026 15:37:22 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for + systems with DRAM above 4GB + +On RISC-V platforms where the entire physical memory (DRAM) resides +above the 32-bit address space (i.e., above dma32_phys_limit), the +current SWIOTLB initialization logic fails. + +This patch addresses two interconnected issues on such platforms: + +1. Incorrect 32-bit DMA bounce assumption: +The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes +that a 32-bit DMA bounce buffer is required simply because the maximum +PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, +no memory exists below the limit to satisfy this allocation. Fix +this by adding a check to ensure `memblock_start_of_DRAM()` is actually +below the 32-bit limit before enforcing 32-bit SWIOTLB. + +2. kmalloc() bounce buffer allocation failure on non-coherent systems: +For non-coherent hardware, a bounce buffer is still mandatory for +cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. +Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating +from low memory, which fails completely when DRAM only exists in high +memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is +permitted to allocate this alignment buffer from high memory. + +With this patch, systems with non-coherent DMA and DRAM entirely above +4GB can successfully map the software IO TLB in high memory and boot +normally. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260331-fix-riscv-swiotlb-v1-1-74dd5e6be0f1@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 6533cc17825a..ac5bece70736 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -172,7 +172,9 @@ static void print_vm_layout(void) { } + + void __init arch_mm_preinit(void) + { +- bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit); ++ bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) && ++ memblock_start_of_DRAM() < dma32_phys_limit; ++ unsigned int swiotlb_flags = SWIOTLB_VERBOSE; + #ifdef CONFIG_FLATMEM + BUG_ON(!mem_map); + #endif /* CONFIG_FLATMEM */ +@@ -180,17 +182,21 @@ void __init arch_mm_preinit(void) + if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb && + dma_cache_alignment != 1) { + /* +- * If no bouncing needed for ZONE_DMA, allocate 1MB swiotlb +- * buffer per 1GB of RAM for kmalloc() bouncing on +- * non-coherent platforms. ++ * No 32-bit DMA bouncing needed (either all DRAM is within ++ * the 32-bit limit, or it all starts above it), but ++ * non-coherent hardware still requires cache-line-aligned ++ * bounce buffers for kmalloc(). Use SWIOTLB_ANY so that the ++ * buffer can be allocated from high memory when DRAM starts ++ * above dma32_phys_limit. Allocate ~1 MB per 1 GB of RAM. + */ + unsigned long size = + DIV_ROUND_UP(memblock_phys_mem_size(), 1024); + swiotlb_adjust_size(min(swiotlb_size_or_default(), size)); + swiotlb = true; ++ swiotlb_flags |= SWIOTLB_ANY; + } + +- swiotlb_init(swiotlb, SWIOTLB_VERBOSE); ++ swiotlb_init(swiotlb, swiotlb_flags); + + print_vm_layout(); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux-lts/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch deleted file mode 100644 index 4c1686add5..0000000000 --- a/SPECS/linux-lts/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +++ /dev/null @@ -1,730 +0,0 @@ -From 4ee622c1f03b3a5e9d6df7f54f612202f9462d8c Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:09:58 +0800 -Subject: [RUYI PATCH] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver for - Spacemit K3 - -The comb PHY on K3 requires to configure a syscon device for the -right mux configuration. And it requires calibration before any -usage. - -Add USB3/PCIe comb PHY driver for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/Kconfig | 16 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.h | 27 ++ - 5 files changed, 669 insertions(+) - create mode 100644 drivers/phy/spacemit/phy-k3-combo.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.h - -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -index 0136aee2e8a2..9a1e25592f25 100644 ---- a/drivers/phy/spacemit/Kconfig -+++ b/drivers/phy/spacemit/Kconfig -@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 - help - Enable this to support K1 USB 2.0 PHY driver. This driver takes care of - enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -+ -+config PHY_SPACEMIT_K3_COMMON_OPS -+ tristate -+ select MFD_SYSCON -+ select GENERIC_PHY -+ -+config PHY_SPACEMIT_K3_COMBO_PHY -+ tristate "SpacemiT K3 USB3/PCIe PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ select PHY_SPACEMIT_K3_COMMON_OPS -+ help -+ Enable this to support K3 USB3/PCIe combo PHY driver. This -+ driver takes care of enabling and clock setup and will be used -+ by K3 dwc3 driver. -+ If unsure, say N. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -index fec0b425a948..df9b609d066f 100644 ---- a/drivers/phy/spacemit/Makefile -+++ b/drivers/phy/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o -diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c -new file mode 100644 -index 000000000000..abd0aad18893 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-combo.c -@@ -0,0 +1,252 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver -+ * -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* -+ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs -+ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. -+ * -+ * PMUA_PCIE_SUBSYS_MGMT[4:0] -+ * -+ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A -+ * 1 : PHY lanes shared between PCIe or USB according to [3:0] -+ * -+ * All PHY matrix combinations according to [4:0]: -+ * -+ * 0x0X : PCIe-A X8 -+ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) -+ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) -+ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) -+ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) -+ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) -+ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) -+ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * -+ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. -+ */ -+#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 -+#define PU_MATRIX_CONF_MASK GENMASK(4, 0) -+ -+#define COMBPHY_MAX_SUBPHYS 6 -+ -+struct k3_combo_phy { -+ struct device *dev; -+ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; -+ void __iomem *base; -+ struct regmap *apb_spare; -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x0, 0x400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x100000, 0x100400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { -+ .lanes = 1, -+ .config = 0x14, -+ .mask = 0x14, -+ .offsets = { -+ 0x200000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { -+ .lanes = 1, -+ .config = 0x12, -+ .mask = 0x12, -+ .offsets = { -+ 0x300000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { -+ .lanes = 1, -+ .config = 0x11, -+ .mask = 0x11, -+ .offsets = { -+ 0x400000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { -+ .lanes = 1, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x500000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { -+ &k3_combphy_lane_group0, -+ &k3_combphy_lane_group1, -+ &k3_combphy_lane_group2, -+ &k3_combphy_lane_group3, -+ &k3_combphy_lane_group4, -+ &k3_combphy_lane_group5, -+}; -+ -+static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { -+ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; -+ struct k3_lane_group *lg = &phy->groups[i]; -+ const struct phy_ops *ops; -+ bool is_usb; -+ -+ is_usb = (data->mask & config) == data->config; -+ if (is_usb) -+ ops = &k3_usb3_phy_ops; -+ else -+ ops = &k3_pcie_phy_ops; -+ -+ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); -+ -+ lg->phy = devm_phy_create(phy->dev, NULL, ops); -+ if (IS_ERR(lg->phy)) -+ return PTR_ERR(lg->phy); -+ -+ lg->is_pcie = !is_usb; -+ lg->data = data; -+ lg->base = phy->base; -+ phy_set_drvdata(lg->phy, lg); -+ } -+ -+ return 0; -+} -+ -+static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) -+{ -+ if (config & ~PU_MATRIX_CONF_MASK) -+ return -EINVAL; -+ -+ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); -+} -+ -+static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k3_combo_phy *phy = dev_get_drvdata(dev); -+ struct k3_lane_group *lg; -+ -+ if (args->args_count != 2) { -+ dev_err(dev, "Invalid number of arguments\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { -+ dev_err(dev, "Invalid PHY id\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ lg = &phy->groups[args->args[0]]; -+ -+ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || -+ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { -+ dev_err(dev, "Invalid PHY mode\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return lg->phy; -+} -+ -+static int k3_combo_phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct phy_provider *provider; -+ struct k3_combo_phy *phy; -+ struct regmap *apmu; -+ u32 config = 0; -+ int ret; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(phy->base)) -+ return PTR_ERR(phy->base); -+ -+ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); -+ if (IS_ERR(phy->apb_spare)) -+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), -+ "Failed to fine APB SPARE syscon"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to find APMU syscon"); -+ -+ ret = k3_combo_phy_update_config(apmu, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to set lane configuration"); -+ -+ phy->dev = dev; -+ platform_set_drvdata(pdev, phy); -+ -+ ret = k3_phy_calibrate(phy->apb_spare); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to calibrate phy"); -+ -+ ret = k3_combo_phy_init_lanes(phy, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to init lanes"); -+ -+ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "Failed to register provider\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id k3_combo_phy_of_match[] = { -+ { .compatible = "spacemit,k3-combo-phy" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); -+ -+static struct platform_driver k3_combo_phy_driver = { -+ .probe = k3_combo_phy_probe, -+ .driver = { -+ .name = "spacemit,k3-combo-phy", -+ .of_match_table = k3_combo_phy_of_match, -+ }, -+}; -+module_platform_driver(k3_combo_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c -new file mode 100644 -index 000000000000..840524cbe533 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.c -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* PHY Registers */ -+#define PHY_VERSION 0x0 -+ -+#define PHY_RESET_CFG 0x04 -+ -+#define PHY_RESET_RXBUF_RST BIT(0) -+#define PHY_RESET_SOFT_RST_PCS BIT(1) -+#define PHY_RESET_SOFT_RST_AHB BIT(2) -+#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) -+ -+#define PHY_CLK_CFG 0x08 -+ -+#define PHY_CLK_PLL_READY BIT(0) -+#define PHY_CLK_TXCLK_INV BIT(2) -+#define PHY_CLK_RXCLK_EN BIT(3) -+#define PHY_CLK_TXCLK_EN BIT(4) -+#define PHY_CLK_PCLK_EN BIT(5) -+#define PHY_CLK_PIPE_PCLK_EN BIT(6) -+#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) -+#define PHY_CLK_REFCLK_24M 2 -+#define PHY_CLK_SW_INIT_DONE BIT(11) -+#define PHY_CLK_PU_SSC_OUT BIT(23) -+ -+#define PHY_MODE_CFG 0x0C -+ -+#define PHY_MODE_PCIE_INT_EN BIT(0) -+#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) -+#define PHY_MODE_LFPS_TPERIOD_USB 3 -+ -+#define PHY_PU_SEL 0x40 -+ -+#define PHY_PU_CFG_STATUS BIT(9) -+#define PHY_PU_OVRD_STATUS BIT(10) -+ -+#define PHY_PU_CK_REG 0x54 -+ -+#define PHY_PU_REFCLK_100 BIT(25) -+ -+#define PHY_PLL_REG1 0x58 -+ -+#define PHY_PLL_FREF_SEL GENMASK(15, 13) -+#define PHY_PLL_FREF_24M 0x1 -+#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) -+#define PHY_PLL_SSC_5000PPM 0xa -+#define PHY_PLL_SSC_MODE GENMASK(29, 28) -+#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 -+#define PHY_PLL_SSC_MODE_UP_SPREAD 1 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 -+ -+#define PHY_PLL_REG2 0x5c -+ -+#define PHY_PLL_SEL_REF100 BIT(21) -+ -+/* PHY RX Register Definitions */ -+#define PHY_RX_REG_A 0x60 -+ -+#define PHY_RX_REG0_RLOAD BIT(4) -+#define PHY_RX_REG1_RTERM GENMASK(11, 8) -+#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) -+#define PHY_RX_REG2_CSEL GENMASK(19, 16) -+#define PHY_RX_REG2_FORCE_CSEL BIT(20) -+#define PHY_RX_REG2_PSEL GENMASK(23, 21) -+#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) -+#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) -+#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) -+#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) -+ -+#define PHY_RX_REG_B 0x64 -+ -+#define PHY_RX_REGB_MASK GENMASK(23, 0) -+ -+#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) -+#define PHY_RX_REG4_ENVOS BIT(4) -+#define PHY_RX_REG4_RTERM_SEL BIT(5) -+#define PHY_RX_REG4_MANUAL_CFG BIT(7) -+#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) -+#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) -+#define PHY_RX_REG6_H1_REG GENMASK(19, 16) -+#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) -+#define PHY_RX_REG6_BYPASS_ADPT BIT(22) -+ -+#define PHY_ADPT_CFG0 0x140 -+#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) -+#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) -+ -+#define PHY_RXEQ_TIME 0xb4 -+#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) -+#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) -+#define PHY_RXEQ_TIME_AMP_SOC_650M 0 -+#define PHY_RXEQ_TIME_AMP_SOC_800M 1 -+#define PHY_RXEQ_TIME_AMP_SOC_870M 2 -+#define PHY_RXEQ_TIME_AMP_SOC_900M 3 -+#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) -+ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PHY_CLK_PLL_READY BIT(0) -+#define PCIE_INITAL_TIMER GENMASK(6, 3) -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define CFG_SW_PHY_INIT_DONE BIT(11) -+ -+/* Lane RX/TX configuration (per‑lane, at lane_base) */ -+#define PCIE_RX_REG1 0x050 -+#define PCIE_TX_REG1 0x064 -+ -+#define PCIE_PLL_TIMEOUT 500000 -+#define PCIE_POLL_DELAY 500 -+ -+static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) -+{ -+ struct phy *phy = lg->phy; -+ u32 val, tmp; -+ int ret; -+ -+ /* Do not wait CDR lock before sampling data */ -+ val = readl(base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); -+ writel(val, base + PHY_RESET_CFG); -+ -+ /* Power down 100MHz refclk buffer */ -+ val = readl(base + PHY_PU_CK_REG); -+ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); -+ writel(val, base + PHY_PU_CK_REG); -+ -+ /* Program PLL REG1 configure the SSC */ -+ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | -+ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | -+ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); -+ writel(val, base + PHY_PLL_REG1); -+ -+ /* Un-select 100MHz PLL reference */ -+ val = readl(base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); -+ writel(val, base + PHY_PLL_REG2); -+ -+ /* USB LFPS period configuration */ -+ val = readl(base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); -+ writel(val, base + PHY_MODE_CFG); -+ -+ /* Force AFE adaptation reset */ -+ val = readl(base + PHY_ADPT_CFG0); -+ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; -+ writel(val, base + PHY_ADPT_CFG0); -+ -+ /* Override driver amplitude value to 900m */ -+ val = readl(base + PHY_RXEQ_TIME); -+ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; -+ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); -+ writel(val, base + PHY_RXEQ_TIME); -+ -+ /* Configure RX parameters */ -+ val = PHY_RX_REG0_RLOAD | -+ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | -+ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | -+ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | -+ PHY_RX_REG2_FORCE_CSEL | -+ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | -+ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | -+ PHY_RX_REG3_SEL_CBOOST_CODE | -+ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | -+ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); -+ writel(val, base + PHY_RX_REG_A); -+ -+ val = readl(base + PHY_RX_REG_B); -+ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | -+ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | -+ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | -+ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); -+ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); -+ writel(val, base + PHY_RX_REG_B); -+ -+ /* -+ * Inform PHY that all PLL-related configuration is done. -+ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. -+ */ -+ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | -+ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | -+ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | -+ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; -+ writel(val, base + PHY_CLK_CFG); -+ -+ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), -+ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&phy->dev, "PHY PLL polling timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int k3_usb3phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ int ret, i; -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_usb3_phy_ops = { -+ .init = k3_usb3phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); -+ -+static int k3_pcie_phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ void __iomem *phy_base = lg->base + lg->data->offsets[0]; -+ u32 val; -+ int ret; -+ int i; -+ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, BIT(21)); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ val = readl(lane_base + PCIE_RX_REG1); -+ val = u32_replace_bits(val, 0, 0x3); -+ writel(val, lane_base + PCIE_RX_REG1); -+ } -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val |= BIT(20); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ writel(0x00006505, phy_base + PCIE_RX_REG1); -+ -+ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0, GENMASK(27, 24)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ -+ val = readl(lane_base + PHY_PU_SEL); -+ val = u32_replace_bits(val, 1, BIT(13)); -+ writel(val, lane_base + PHY_PU_SEL); -+ -+ /* disable en_sample_data_after_cdr_locked */ -+ val = readl(lane_base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, BIT(6)); -+ writel(val, lane_base + PHY_RESET_CFG); -+ -+ /* Dynamic Lock */ -+ val = readl(lane_base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, 1, BIT(2)); -+ writel(val, lane_base + PHY_MODE_CFG); -+ -+ val = FIELD_PREP(GENMASK(7, 0), 0x10) | -+ FIELD_PREP(GENMASK(15, 8), 0x78) | -+ FIELD_PREP(GENMASK(23, 16), 0x98) | -+ FIELD_PREP(GENMASK(31, 24), 0xdf); -+ writel(val, lane_base + PHY_RX_REG_A); -+ -+ val = readl(lane_base + PHY_RX_REG_B); -+ val &= ~PHY_RX_REGB_MASK; -+ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | -+ FIELD_PREP(GENMASK(15, 8), 0x88) | -+ FIELD_PREP(GENMASK(23, 16), 0x28); -+ writel(val, lane_base + PHY_RX_REG_B); -+ -+ /* Set init done */ -+ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); -+ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); -+ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); -+ } -+ -+ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, -+ PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_pcie_phy_ops = { -+ .init = k3_pcie_phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); -+ -+/* PHY rcal init requires APB_SPARE regmap access */ -+ -+#define APB_SPARE_PU_CAL 0x178 -+#define PU_CAL BIT(17) -+ -+#define APB_SPARE_RCAL_HSIO 0x17c -+#define APB_SPARE_PU_CAL_DONE BIT(8) -+#define RCAL_OVRD_PTRIM GENMASK(23, 20) -+#define RCAL_OVRD_NTRIM GENMASK(27, 24) -+#define RCAL_OVRD_PTRIM_EN BIT(28) -+#define RCAL_OVRD_NTRIM_EN BIT(29) -+#define RCAL_OVRD_STABLE_VAL BIT(30) -+#define RCAL_OVRD_STABLE_EN BIT(31) -+ -+#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) -+#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) -+ -+#define PU_CAL_TIMEOUT 2000000 -+ -+static DEFINE_MUTEX(calibrate_lock); -+ -+int k3_phy_calibrate(struct regmap *apb_spare) -+{ -+ unsigned int val = 0; -+ int ret; -+ -+ guard(mutex)(&calibrate_lock); -+ -+ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); -+ if (val & APB_SPARE_PU_CAL_DONE) -+ return 0; -+ -+ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, -+ PU_CAL); -+ -+ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, -+ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, -+ PU_CAL_TIMEOUT); -+ -+ if (ret) -+ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | -+ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | -+ RCAL_OVRD_STABLE_EN); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(k3_phy_calibrate); -+ -+MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h -new file mode 100644 -index 000000000000..49009c3c313a ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _PHY_K3_COMMON_H -+#define _PHY_K3_COMMON_H -+ -+#include -+ -+struct k3_phy_lane_group_data { -+ u32 lanes; -+ u8 config; -+ u8 mask; -+ u32 offsets[] __counted_by(lanes); -+}; -+ -+struct k3_lane_group { -+ const struct k3_phy_lane_group_data *data; -+ void __iomem *base; -+ struct phy *phy; -+ bool is_pcie; -+}; -+ -+extern const struct phy_ops k3_pcie_phy_ops; -+extern const struct phy_ops k3_usb3_phy_ops; -+ -+int k3_phy_calibrate(struct regmap *apb_spare); -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0466-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux-lts/0466-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch new file mode 100644 index 0000000000..9e78580517 --- /dev/null +++ b/SPECS/linux-lts/0466-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch @@ -0,0 +1,61 @@ +From e6e34cc6749f4fd4a9f8f59f3cbed84a538bb564 Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:08 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add + vcc5v0_sys regulator for Banana Pi F3 + +Define the system 5V fixed regulator (vcc5v0_sys) supplied by the +DC input. As per the schematics, vcc5v0_sys is the input power source +for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators +to correctly reference vcc5v0_sys as their parent (vin-supply). + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-2-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 307a7e4a8943..fbb4ff5e169f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -54,6 +54,16 @@ reg_dc_in: regulator-dc-in-12v { + regulator-always-on; + }; + ++ reg_vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; +@@ -70,6 +80,7 @@ regulator-usb3-vbus-5v { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; ++ vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +@@ -79,6 +90,7 @@ usb3_hub_5v: regulator-usb3-hub-5v { + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux-lts/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch deleted file mode 100644 index ce8ce857a9..0000000000 --- a/SPECS/linux-lts/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 448b7e9c38ae27c10f2aa343886ce7c2b8243f8d Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 27 Feb 2026 09:46:06 +0800 -Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: add USB controller and - USB phy support - -Add all USB device node to the Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ - 2 files changed, 55 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index ac965ec83f2c..acfbb5029c15 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -183,6 +183,11 @@ dldo7: dldo7 { - }; - }; - -+&combophy { -+ spacemit,apmu = <&syscon_apmu 0x11>; -+ status = "okay"; -+}; -+ - ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -@@ -280,3 +285,11 @@ hub@1 { - &usb2_phy { - status = "okay"; - }; -+ -+&usb3d_u2phy { -+ status = "okay"; -+}; -+ -+&usb3d { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 1b86c872accb..e73e6838f6b0 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - /dts-v1/; - -@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb3d: usb@81a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0x81a00000 0x0 0x10000>; -+ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, -+ <&syscon_apmu RESET_APMU_USB3_D_VCC>, -+ <&syscon_apmu RESET_APMU_USB3_D_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ phys = <&usb3d_u2phy>, -+ <&combophy 4 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,parkmode-disable-ss-quirk; -+ dr_mode = "host"; -+ status = "disabled"; -+ }; -+ -+ usb3d_u2phy: phy@81b00000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0x81b00000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combophy: phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x0 0x81d00000 0x0 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&pll>; -+ status = "disabled"; -+ }; -+ - usb2_host: usb@c0a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0xc0a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0467-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux-lts/0467-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch new file mode 100644 index 0000000000..983640a3a3 --- /dev/null +++ b/SPECS/linux-lts/0467-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch @@ -0,0 +1,59 @@ +From e520c42b3ece2562b8301a3c122559e0a95ad7ba Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:09 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update + USB regulator on onboard usb and lable + +Update the USB regulator labels to align with the board schematics and +power hierarchy. This change renames the regulator to reg_5v_vbus and +its name to 5V_VBUS. Additionally, it fixes the vdd-supply references +for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point +to the 5V_VBUS input source as per the board schematics. + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-3-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index fbb4ff5e169f..e97519a9a55e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -74,9 +74,9 @@ reg_vcc_4v: regulator-vcc-4v { + vin-supply = <®_dc_in>; + }; + +- regulator-usb3-vbus-5v { ++ reg_5v_vbus: regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; +- regulator-name = "USB30_VBUS"; ++ regulator-name = "5V_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; +@@ -408,7 +408,7 @@ &usb_dwc3 { + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; +- vdd-supply = <&usb3_hub_5v>; ++ vdd-supply = <®_5v_vbus>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +@@ -416,7 +416,7 @@ hub_2_0: hub@1 { + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; +- vdd-supply = <&usb3_hub_5v>; ++ vdd-supply = <®_5v_vbus>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch deleted file mode 100644 index 76aa9565cc..0000000000 --- a/SPECS/linux-lts/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +++ /dev/null @@ -1,261 +0,0 @@ -From 3e1379ca2b2ca099c8a0a6900f9be381e48213c6 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 24 Mar 2026 11:06:24 +0800 -Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add PCIe device node - -Add all PCIe device node for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ - 3 files changed, 212 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index acfbb5029c15..f24ada15f182 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -264,6 +264,35 @@ uboot@210000 { - }; - }; - -+&pcie0_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_0_cfg>; -+ phys = <&combophy 0 PHY_TYPE_PCIE>, -+ <&combophy 1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pcie2_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_cfg>; -+ phys = <&combophy 2 PHY_TYPE_PCIE>, -+ <&combophy 3 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <2>; -+ status = "okay"; -+}; -+ -+&pcie4_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie4_0_cfg>; -+ phys = <&combophy 5 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ num-lanes = <1>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 846d5e8cc783..5a817610101b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -710,4 +710,37 @@ uart0-0-pins { - drive-strength = <25>; - }; - }; -+ -+ pcie0_0_cfg: pcie0-0-cfg { -+ pcie0-0-pins { -+ pinmux = , /* pcie0 perst */ -+ ; /* pcie0 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ pcie2_0_cfg: pcie2-0-cfg { -+ pcie2-0-pins { -+ pinmux = , /* pcie2 perst */ -+ ; /* pcie2 clkreq */ -+ -+ drive-strength = <38>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ pcie4_0_cfg: pcie4-0-cfg { -+ pcie4-0-pins { -+ pinmux = , /* pcie4 perst */ -+ , /* pcie4 wake */ -+ ; /* pcie4 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index e73e6838f6b0..9552089c7c73 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ pcie0_rc: pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ status = "disabled"; -+ }; -+ -+ pcie1_rc: pcie@80400000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80400000 0x0 0x00001000>, -+ <0x0 0x80500000 0x0 0x00001000>, -+ <0x0 0x80700000 0x0 0x00003f20>, -+ <0x11 0x80000000 0x0 0x00010000>, -+ <0x0 0x82c00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, -+ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <1>; -+ spacemit,apmu = <&syscon_apmu 0x1d0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_rc: pcie@80800000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80800000 0x0 0x00001000>, -+ <0x0 0x80900000 0x0 0x00001000>, -+ <0x0 0x80b00000 0x0 0x00003f20>, -+ <0x12 0x00000000 0x0 0x00010000>, -+ <0x0 0x82d00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <2>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1c8>; -+ status = "disabled"; -+ }; -+ -+ pcie3_rc: pcie@80c00000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80c00000 0x0 0x00001000>, -+ <0x0 0x80d00000 0x0 0x00001000>, -+ <0x0 0x80f00000 0x0 0x00003f20>, -+ <0x12 0x80000000 0x0 0x00010000>, -+ <0x0 0x82a00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, -+ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, -+ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <3>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e0>; -+ status = "disabled"; -+ }; -+ -+ pcie4_rc: pcie@81000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x81000000 0x0 0x00001000>, -+ <0x0 0x81100000 0x0 0x00001000>, -+ <0x0 0x81300000 0x0 0x00003f20>, -+ <0x12 0xc0000000 0x0 0x00010000>, -+ <0x0 0x82b00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, -+ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, -+ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <4>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e8>; -+ status = "disabled"; -+ }; -+ - usb3d: usb@81a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0x81a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0468-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux-lts/0468-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch new file mode 100644 index 0000000000..7e2a884509 --- /dev/null +++ b/SPECS/linux-lts/0468-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch @@ -0,0 +1,52 @@ +From f02035a00fee5f965789e1fbb4d5ee0f8a71b08b Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:10 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct + USB hub power hierarchy +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to +ensure the USB 3.0 stack is properly powered as per the schematics. +In addition, align the USB hub regulator with the board schematics +by renaming it to VCC5V0_HUB and marking it as regulator-always-on +to maintain power stability. + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-4-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index e97519a9a55e..8d2c161f5b35 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -87,9 +87,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v { + + usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; +- regulator-name = "USB30_HUB"; ++ regulator-name = "VCC5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ regulator-always-on; + vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; +@@ -403,6 +404,7 @@ &usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; ++ vbus-supply = <&usb3_hub_5v>; + status = "okay"; + + hub_2_0: hub@1 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux-lts/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch deleted file mode 100644 index 9a9326a3e9..0000000000 --- a/SPECS/linux-lts/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 88fa19733f8dc09f9c51bf41ded9c4d68c722b88 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:28:15 +0800 -Subject: [RUYI PATCH] RUYI: PCI: add SpacemiT vendor id and its K3 device id - to pci_ids - -The SpacemiT K3 chip's root complex needs to be listed in the allowlist -of rtw89 driver to allow 36-bit DMA. - -Add the vendor and device IDs to pci_ids.h header file. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - include/linux/pci_ids.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 7c01548a6ddb..e5a5700f7c8c 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2643,6 +2643,9 @@ - #define PCI_VENDOR_ID_SUNIX 0x1fd4 - #define PCI_DEVICE_ID_SUNIX_1999 0x1999 - -+#define PCI_VENDOR_ID_SPACEMIT 0x201f -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 -+ - #define PCI_VENDOR_ID_HINT 0x3388 - #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 - --- -2.53.0 - diff --git a/SPECS/linux-lts/0469-FROMLIST-riscv-mm-Do-not-probe-satp-mode-limit-if-kn.patch b/SPECS/linux-lts/0469-FROMLIST-riscv-mm-Do-not-probe-satp-mode-limit-if-kn.patch new file mode 100644 index 0000000000..7a4d943883 --- /dev/null +++ b/SPECS/linux-lts/0469-FROMLIST-riscv-mm-Do-not-probe-satp-mode-limit-if-kn.patch @@ -0,0 +1,72 @@ +From e308a4d17d13dd8bd7022a103861970e8276e363 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 24 Apr 2026 11:03:26 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Do not probe satp mode limit if + known in FDT + +Some systems may only have memory at such a high address that an +identity mapping cannot be made in Sv48, or even Sv57. To avoid crashing +while probing satp mode support, trust the mmu-type property from FDT +and avoid probing if it is set. + +For example, if a CPU supports (up to) Sv57 but the SoC it is on only +has memory starting at 128 TiB, an identity mapping cannot be made in +Sv48. If the user specifies "no5lvl" on the command line, +set_satp_mode() will attempt to test Sv48 support and crash, since the +virtual address is too high. Instead, given the correct FDT CPU node +property mmu-type = "riscv,sv57", set_satp_mode() can pick the maximum +allowed mode from command line and FDT, namely Sv48, without probing. + +Handling of mmu-type "riscv,sv57" in set_satp_mode_from_fdt() is added +since it is now needed. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260424-riscv-mm-trust-fdt-mmu-type-v1-1-57f3313275d2@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/kernel/pi/fdt_early.c | 2 ++ + arch/riscv/mm/init.c | 7 ++++++- + 2 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/pi/fdt_early.c b/arch/riscv/kernel/pi/fdt_early.c +index a12ff8090f19..702253287560 100644 +--- a/arch/riscv/kernel/pi/fdt_early.c ++++ b/arch/riscv/kernel/pi/fdt_early.c +@@ -218,6 +218,8 @@ u64 set_satp_mode_from_fdt(uintptr_t dtb_pa) + return SATP_MODE_39; + else if (!strcmp(mmu_type, "riscv,sv48")) + return SATP_MODE_48; ++ else if (!strcmp(mmu_type, "riscv,sv57")) ++ return SATP_MODE_57; + break; + } + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index ac5bece70736..f10c37999f23 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -892,8 +892,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) + { + u64 identity_satp, hw_satp; + uintptr_t set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; ++ u64 satp_mode_limit_fdt = __pi_set_satp_mode_from_fdt(dtb_pa); + u64 satp_mode_limit = min_not_zero(__pi_set_satp_mode_from_cmdline(dtb_pa), +- __pi_set_satp_mode_from_fdt(dtb_pa)); ++ satp_mode_limit_fdt); + + kernel_map.page_offset = PAGE_OFFSET_L5; + +@@ -905,6 +906,10 @@ static __init void set_satp_mode(uintptr_t dtb_pa) + return; + } + ++ /* Skip probing if max SATP mode known from FDT */ ++ if (satp_mode_limit_fdt) ++ return; ++ + create_p4d_mapping(early_p4d, + set_satp_mode_pmd, (uintptr_t)early_pud, + P4D_SIZE, PAGE_TABLE); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux-lts/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch deleted file mode 100644 index e0b9eb8766..0000000000 --- a/SPECS/linux-lts/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e57bb71611315a5153d479c9e82b806ab76de1fb Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:29:46 +0800 -Subject: [RUYI PATCH] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA - allowlist - -The SpacemiT K3 platform has no system memory in the 32-bit address -space, and it's verified that the chip works well with 36-bit DMA of -RTL8852BE. - -Add it to the 36-bit DMA allowlist of rtw89_pci. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c -index 6be1849b0c4d..5058ebadb604 100644 ---- a/drivers/net/wireless/realtek/rtw89/pci.c -+++ b/drivers/net/wireless/realtek/rtw89/pci.c -@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) - if (bridge->device == 0x2806) - return true; - break; -+ case PCI_VENDOR_ID_SPACEMIT: -+ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) -+ return true; -+ break; - } - - return false; --- -2.53.0 - diff --git a/SPECS/linux-lts/0470-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux-lts/0470-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch new file mode 100644 index 0000000000..18cf83a357 --- /dev/null +++ b/SPECS/linux-lts/0470-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch @@ -0,0 +1,37 @@ +From ae4f71186edf3edcdff7559238bfbf06bf69cd51 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 18:31:44 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for + cross-DAI rate constraint + +On SpacemiT K3, multiple I2S controllers share the same physical BCLK +(c_bclk). Declare this clock via snd_soc_dai_set_bclk_clk() so the +ASoC core can automatically constrain hw_params when one controller is +already streaming. + +For K1, c_bclk is NULL (obtained via devm_clk_get_optional_enabled), +so this call is a no-op and behavior is unchanged. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-3-ede05a22f732@linux.spacemit.com +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 3df94b4ca5a5..1a02d7fcc7e1 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -323,6 +323,8 @@ static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai) + + spacemit_i2s_init(i2s); + ++ snd_soc_dai_set_bclk_clk(dai, i2s->c_bclk); ++ + return 0; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch deleted file mode 100644 index 00daab299c..0000000000 --- a/SPECS/linux-lts/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 50eb8f06ed16e79d0840e5c58220ae05cac7dbb1 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 19 May 2026 19:57:52 +0800 -Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on - SpacemiT K3 - -The dynamic speed switch functionality seems to be broken on SpacemiT -K3, and leads to frequent GPU crashes at least with Polaris GPUs. - -Disable dynamic speed switch on this platform. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index c22aea46efcd..b54f7cdd0ce8 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) - */ - static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) - { -+ struct pci_dev *parent = adev->pdev; -+ static const struct pci_device_id broken_devids[] = { -+ /* SpacemiT K3 */ -+ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, -+ PCI_DEVICE_ID_SPACEMIT_K3) }, -+ {} -+ }; -+ - #if IS_ENABLED(CONFIG_X86) - struct cpuinfo_x86 *c = &cpu_data(0); - -@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device - if (c->x86_vendor == X86_VENDOR_INTEL) - return false; - #endif -+ /* skip upstream/downstream switches internal to dGPU */ -+ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { -+ parent = pci_upstream_bridge(parent); -+ } -+ -+ if (!parent) -+ return true; -+ -+ if (pci_match_id(broken_devids, parent)) -+ return false; -+ - return true; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0471-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux-lts/0471-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch new file mode 100644 index 0000000000..7eeffa199a --- /dev/null +++ b/SPECS/linux-lts/0471-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch @@ -0,0 +1,65 @@ +From 1e205e57bed060dde731ccfde50d6a73f757ee3a Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:16:59 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC + subsys clock controller + +TH1520 has a subsystem clock controller called MISC_SUBSYS in its +manual, mainly controlling clocks for USB and MMC/SD in non-TEE +environment. + +Add device tree binding for it. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-2-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- + include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ + 2 files changed, 13 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +index 9d058c00ab3d..d46d13597466 100644 +--- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml ++++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +@@ -23,6 +23,7 @@ properties: + compatible: + enum: + - thead,th1520-clk-ap ++ - thead,th1520-clk-misc + - thead,th1520-clk-vo + + reg: +@@ -32,8 +33,8 @@ properties: + items: + - description: | + One input clock: +- - For "thead,th1520-clk-ap": the clock input must be the 24 MHz +- main oscillator. ++ - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clock ++ input must be the 24 MHz main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL +diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h +index 68b35cc61204..642c2a69a579 100644 +--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h ++++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h +@@ -128,4 +128,14 @@ + #define CLK_MIPIDSI1_PIXCLK 29 + #define CLK_HDMI_PIXCLK 30 + ++/* MISC clocks */ ++#define CLK_MISCSYS_ACLK 0 ++#define CLK_USB 1 ++#define CLK_USB_CTL_REF 2 ++#define CLK_USB_PHY_REF 3 ++#define CLK_USB_SUSPEND 4 ++#define CLK_EMMC 5 ++#define CLK_SDIO0 6 ++#define CLK_SDIO1 7 ++ + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux-lts/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch deleted file mode 100644 index daa05c9c8d..0000000000 --- a/SPECS/linux-lts/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +++ /dev/null @@ -1,50 +0,0 @@ -From c0f35dd9ad2ce894ee2fef94f5ac86216d03ef46 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Wed, 4 Feb 2026 08:54:40 +0800 -Subject: [RUYI PATCH] RVCK: driver: clk: k3: keep some system based clock - always on - -FROM: https://github.com/RVCK-Project/rvck/pull/213 - -community inclusion -category: bugfix -bugzilla: https://github.com/RVCK-Project/rvck/issues/212 - --------------------------------- - -The hdma clk is used by some component of CCI bus, it should -be keep always on, regardless of whether hdma enabled. - -The rcpu clk should be always on because it is running backround. - -Signed-off-by: Zhang Meng -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 03de04144963..6acde3b76b7b 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { - CCU_PARENT_HW(pll1_d6_409p6), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -- 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); - - static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { - CCU_PARENT_HW(pll1_d48_51p2_ap), -@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT - /* APMU clocks end */ - - /* DCIU clocks start */ --CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); - CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); - CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); - CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); --- -2.53.0 - diff --git a/SPECS/linux-lts/0472-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux-lts/0472-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch new file mode 100644 index 0000000000..f407d873df --- /dev/null +++ b/SPECS/linux-lts/0472-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch @@ -0,0 +1,124 @@ +From 1ea3a9e11199d508a404f6f72d8b455e39d612e1 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:00 +0800 +Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC + subsys clocks + +The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows +controlling of USB related clocks and MMC/SD controller AHB bus clocks. + +Add support for this clock controller, in order to enable USB support. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-3-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ + 1 file changed, 64 insertions(+) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index 3a6847f1c950..24f785f0b329 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", + static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, + 0x4, 0, 0); + ++static struct clk_fixed_factor usb_suspend_div_clk = { ++ .div = 24, ++ .mult = 1, ++ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", ++ osc_24m_clk, ++ &clk_fixed_factor_ops, ++ 0), ++}; ++ ++static const struct clk_parent_data usb_suspend_parents[] = { ++ { .hw = &usb_suspend_div_clk.hw }, ++}; ++ ++static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_pd, ++ 0x0, 0, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data miscsys_aclk_pd[] = { ++ { .hw = &miscsys_aclk.gate.hw }, ++}; ++ ++static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, ++ CLK_IS_CRITICAL); ++static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_clk, ++ 0x4, 1, 0); ++static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_clk, ++ 0x4, 2, 0); ++static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", ++ usb_suspend_parents, 0x4, 3, 0); ++static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, ++ 0); ++static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, ++ 0); ++static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, 0, ++ 0); ++ + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", + &gmac_pll_clk.common.hw, 10, 1, 0); + +@@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] = { + &hdmi_pixclk + }; + ++static struct ccu_gate *th1520_misc_gate_clks[] = { ++ &miscsys_aclk, ++ &usb_clk, ++ &usb_ctl_ref_clk, ++ &usb_phy_ref_clk, ++ &usb_suspend_clk, ++ &emmc_clk, ++ &sdio0_clk, ++ &sdio1_clk ++}; ++ + static const struct regmap_config th1520_clk_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +@@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platdata = { + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), + }; + ++static const struct th1520_plat_data th1520_misc_platdata = { ++ .th1520_gate_clks = th1520_misc_gate_clks, ++ ++ .nr_clks = CLK_SDIO1 + 1, ++ ++ .nr_gate_clks = ARRAY_SIZE(th1520_misc_gate_clks), ++}; ++ + /* + * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) + * when its parent, c910_clk, changes the rate. +@@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *pdev) + return ret; + } + ++ if (plat_data == &th1520_ap_platdata) { ++ ret = devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); ++ if (ret) ++ return ret; ++ } ++ + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); + if (ret) + return ret; +@@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = { + .compatible = "thead,th1520-clk-vo", + .data = &th1520_vo_platdata, + }, ++ { ++ .compatible = "thead,th1520-clk-misc", ++ .data = &th1520_misc_platdata, ++ }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, th1520_clk_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch deleted file mode 100644 index 5c6f644043..0000000000 --- a/SPECS/linux-lts/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch +++ /dev/null @@ -1,65 +0,0 @@ -From af2e3f98ce75fe961163f67f323465d95ce082d9 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 28 May 2026 14:18:23 +0800 -Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA - variant - -Add support for a testing variant of the SG2042 SDHCI controller without -PHY reset and without the "timer" clock. - -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c -index 90aa146a1be3..292940d9c45b 100644 ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -1664,6 +1664,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { - .platform_execute_tuning = th1520_execute_tuning, - }; - -+static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { -+ .set_clock = sdhci_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .set_uhs_signaling = dwcmshc_set_uhs_signaling, -+ .get_max_clock = dwcmshc_get_max_clock, -+ .reset = sdhci_reset, -+ .adma_write_desc = dwcmshc_adma_write_desc, -+ .platform_execute_tuning = th1520_execute_tuning, -+}; -+ - static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { - .set_clock = sdhci_eic7700_set_clock, - .get_max_clock = sdhci_pltfm_clk_get_max_clock, -@@ -1746,6 +1756,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { - .init = sg2042_init, - }; - -+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { -+ .pdata = { -+ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, -+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+ }, -+}; -+ - static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { - .pdata = { - .ops = &sdhci_dwcmshc_eic7700_ops, -@@ -1857,6 +1875,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { - .compatible = "sophgo,sg2042-dwcmshc", - .data = &sdhci_dwcmshc_sg2042_pdata, - }, -+ { -+ .compatible = "sophgo,sg2042-fpga-dwcmshc", -+ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, -+ }, - { - .compatible = "eswin,eic7700-dwcmshc", - .data = &sdhci_dwcmshc_eic7700_pdata, --- -2.53.0 - diff --git a/SPECS/linux-lts/0473-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux-lts/0473-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch new file mode 100644 index 0000000000..35188c6953 --- /dev/null +++ b/SPECS/linux-lts/0473-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch @@ -0,0 +1,74 @@ +From f975aa1c287cee3e6227d7bd60a2ff64c4fc607f Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:01 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for + MISC clock controller + +The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller +mainly controlling USB-related clocks (which isn't utilized yet) and +MMC/SD controllers' AHB bus clocks. + +Add the device tree node for it along with the missing bus clock +references for MMC/SD controllers. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-4-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ + 1 file changed, 13 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f2abc6338458..f54329861496 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -401,8 +401,8 @@ emmc: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -410,8 +410,8 @@ sdio0: mmc@ffe7090000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -419,8 +419,8 @@ sdio1: mmc@ffe70a0000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe70a0000 0x0 0x10000>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -579,6 +579,13 @@ rst_misc: reset-controller@ffec02c000 { + #reset-cells = <1>; + }; + ++ clk_misc: clock-controller@ffec02c100 { ++ compatible = "thead,th1520-clk-misc"; ++ reg = <0xff 0xec02c100 0x0 0x100>; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; ++ + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0474-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux-lts/0474-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch new file mode 100644 index 0000000000..ac2e734a54 --- /dev/null +++ b/SPECS/linux-lts/0474-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch @@ -0,0 +1,102 @@ +From 66f85ff8fbb353a1dfcb16a6755a232ccc2ba2f2 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:02 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head + TH1520 USB PHY + +The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom +glue logic configuring PHY parameters. + +Add a binding for it. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-5-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ + 1 file changed, 74 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml +new file mode 100644 +index 000000000000..37f5cfb95bad +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml +@@ -0,0 +1,74 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: T-Head TH1520 USB PHY ++ ++description: | ++ The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some ++ custom logic to configure PHY parameters. ++ ++maintainers: ++ - Icenowy Zheng ++ - Wei Fu ++ - Drew Fustini ++ ++properties: ++ compatible: ++ const: thead,th1520-usb-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ clocks: ++ items: ++ - description: PHY bus clock ++ - description: PHY reference clock ++ ++ clock-names: ++ items: ++ - const: bus ++ - const: ref ++ ++ resets: ++ items: ++ - description: PHY bus reset ++ - description: PHY reset ++ ++ reset-names: ++ items: ++ - const: bus ++ - const: phy ++ ++ avdd33-usb3-supply: ++ description: | ++ 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. ++ ++required: ++ - compatible ++ - "#phy-cells" ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - avdd33-usb3-supply ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@ec030000 { ++ compatible = "thead,th1520-usb-phy"; ++ reg = <0xec030000 0x10000>; ++ #phy-cells = <0>; ++ clocks = <&clk_misc 1>, <&clk_misc 3>; ++ clock-names = "bus", "ref"; ++ resets = <&rst_misc 6>, <&rst_misc 7>; ++ reset-names = "bus", "phy"; ++ avdd33-usb3-supply = <&avdd33_usb3>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0475-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux-lts/0475-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch new file mode 100644 index 0000000000..df0e716d5e --- /dev/null +++ b/SPECS/linux-lts/0475-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch @@ -0,0 +1,281 @@ +From 3fd89dbf05c5808ca796f284fdfa9e52b806e90e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:03 +0800 +Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY + +The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with +some PHY parameters exported as another system controller along with it. + +As a few PHY parameters' default value isn't ready to work, add a driver +configuring them before letting the PHY run, in addition to +clock/reset/regulator management. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-6-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/thead/Kconfig | 12 ++ + drivers/phy/thead/Makefile | 2 + + drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ + 5 files changed, 213 insertions(+) + create mode 100644 drivers/phy/thead/Kconfig + create mode 100644 drivers/phy/thead/Makefile + create mode 100644 drivers/phy/thead/phy-th1520-usb.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index c39b40876177..d775ac20fafd 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -128,6 +128,7 @@ source "drivers/phy/st/Kconfig" + source "drivers/phy/starfive/Kconfig" + source "drivers/phy/sunplus/Kconfig" + source "drivers/phy/tegra/Kconfig" ++source "drivers/phy/thead/Kconfig" + source "drivers/phy/ti/Kconfig" + source "drivers/phy/intel/Kconfig" + source "drivers/phy/xilinx/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index e1aea28dbf6b..2577882c9647 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -41,5 +41,6 @@ obj-y += allwinner/ \ + starfive/ \ + sunplus/ \ + tegra/ \ ++ thead/ \ + ti/ \ + xilinx/ +diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig +new file mode 100644 +index 000000000000..14012db5973c +--- /dev/null ++++ b/drivers/phy/thead/Kconfig +@@ -0,0 +1,12 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config PHY_TH1520_USB ++ tristate "USB PHY driver for T-Head TH1520 SoC" ++ depends on ARCH_THEAD || COMPILE_TEST ++ depends on COMMON_CLK ++ depends on HAS_IOMEM ++ depends on OF ++ depends on RESET_CONTROLLER ++ select GENERIC_PHY ++ default ARCH_THEAD ++ help ++ Enable support for the USB PHY on the T-Head TH1520 SoC. +diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile +new file mode 100644 +index 000000000000..5b459bc7004b +--- /dev/null ++++ b/drivers/phy/thead/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_TH1520_USB) += phy-th1520-usb.o +diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1520-usb.c +new file mode 100644 +index 000000000000..c87bd779bbb7 +--- /dev/null ++++ b/drivers/phy/thead/phy-th1520-usb.c +@@ -0,0 +1,197 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) ++ * ++ * Authors: ++ * Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define USB_SYSCON_OFFSET 0xf000 ++ ++/* All the below registers are in the USB syscon region */ ++#define USB_CLK_GATE_STS 0x0 ++#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 ++#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 ++#define USB_GPIO 0xc ++#define USB_DEBUG_STS0 0x10 ++#define USB_DEBUG_STS1 0x14 ++#define USB_DEBUG_STS2 0x18 ++#define USBCTL_CLK_CTRL0 0x1c ++#define USBPHY_CLK_CTRL1 0x20 ++#define USBPHY_TEST_CTRL0 0x24 ++#define USBPHY_TEST_CTRL1 0x28 ++#define USBPHY_TEST_CTRL2 0x2c ++#define USBPHY_TEST_CTRL3 0x30 ++#define USB_SSP_EN 0x34 ++#define USB_HADDR_SEL 0x38 ++#define USB_SYS 0x3c ++#define USB_HOST_STATUS 0x40 ++#define USB_HOST_CTRL 0x44 ++#define USBPHY_HOST_CTRL 0x48 ++#define USBPHY_HOST_STATUS 0x4c ++#define USB_TEST_REG0 0x50 ++#define USB_TEST_REG1 0x54 ++#define USB_TEST_REG2 0x58 ++#define USB_TEST_REG3 0x5c ++ ++#define USB_SYS_COMMONONN BIT(0) ++ ++#define USB_SSP_EN_REF_SSP_EN BIT(0) ++ ++struct th1520_usb_phy { ++ struct platform_device *pdev; ++ struct phy *phy; ++ struct regmap *regmap; ++ struct clk *ref_clk; ++ struct reset_control *phy_reset; ++}; ++ ++static int th1520_usb_phy_init(struct phy *phy) ++{ ++ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = clk_prepare_enable(th1520_phy->ref_clk); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_assert(th1520_phy->phy_reset); ++ if (ret) ++ goto err_disable_clk; ++ ++ /* ++ * Do some initial PHY setup: ++ * - Set COMMONONN to allow the PHY to automatically power down. ++ * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed ++ * PHY clock PLL. ++ */ ++ regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); ++ regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); ++ ++ ret = reset_control_deassert(th1520_phy->phy_reset); ++ if (ret) ++ goto err_disable_clk; ++ ++ udelay(10); ++ ++ return 0; ++ ++err_disable_clk: ++ clk_disable_unprepare(th1520_phy->ref_clk); ++ return ret; ++} ++ ++static int th1520_usb_phy_exit(struct phy *phy) ++{ ++ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = reset_control_assert(th1520_phy->phy_reset); ++ if (ret) ++ return ret; ++ ++ clk_disable_unprepare(th1520_phy->ref_clk); ++ ++ return 0; ++} ++ ++static const struct phy_ops th1520_usb_phy_ops = { ++ .init = th1520_usb_phy_init, ++ .exit = th1520_usb_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct regmap_config phy_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = USB_TEST_REG3, ++}; ++ ++static int th1520_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct th1520_usb_phy *th1520_phy; ++ struct reset_control *bus_reset; ++ void __iomem *base; ++ int ret; ++ ++ th1520_phy = devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); ++ if (!th1520_phy) ++ return -ENOMEM; ++ ++ th1520_phy->pdev = pdev; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ th1520_phy->ref_clk = devm_clk_get(dev, "ref"); ++ if (IS_ERR(th1520_phy->ref_clk)) ++ return PTR_ERR(th1520_phy->ref_clk); ++ ++ /* De-assert the bus reset and leave it that way */ ++ bus_reset = devm_reset_control_get_exclusive_deasserted(dev, "bus"); ++ if (IS_ERR(bus_reset)) ++ return PTR_ERR(bus_reset); ++ ++ th1520_phy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); ++ if (IS_ERR(th1520_phy->phy_reset)) ++ return PTR_ERR(th1520_phy->phy_reset); ++ ++ /* ++ * Schematics of several boards (Lichee Module 4A/Milk-V Meles) ++ * describe this power rail as always-on. ++ */ ++ ret = devm_regulator_get_enable(dev, "avdd33-usb3"); ++ if (ret) ++ return ret; ++ ++ th1520_phy->regmap = devm_regmap_init_mmio_clk(dev, "bus", ++ base + USB_SYSCON_OFFSET, ++ &phy_regmap_config); ++ if (IS_ERR(th1520_phy->regmap)) ++ return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), ++ "Failed to init regmap\n"); ++ ++ th1520_phy->phy = devm_phy_create(dev, dev->of_node, &th1520_usb_phy_ops); ++ if (IS_ERR(th1520_phy->phy)) { ++ dev_err(dev, "failed to create PHY\n"); ++ return PTR_ERR(th1520_phy->phy); ++ } ++ ++ phy_set_drvdata(th1520_phy->phy, th1520_phy); ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id th1520_usb_phy_of_table[] = { ++ { .compatible = "thead,th1520-usb-phy" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); ++ ++static struct platform_driver th1520_usb_phy_driver = { ++ .driver = { ++ .name = "th1520-usb-phy", ++ .of_match_table = th1520_usb_phy_of_table, ++ }, ++ .probe = th1520_usb_phy_probe, ++}; ++ ++module_platform_driver(th1520_usb_phy_driver); ++ ++MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0476-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux-lts/0476-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch new file mode 100644 index 0000000000..5639deb1e0 --- /dev/null +++ b/SPECS/linux-lts/0476-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch @@ -0,0 +1,68 @@ +From a909ed185ec695980b1d7077fcc0a623041b5e71 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:04 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB + +The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 +Dual Role Device controller in addition to a USB2+USB3 combo PHY based +on Synopsys USB3.0 FemtoPHY. + +Add device tree nodes for them. The USB controller is quite generic, new +and properly configured during silicon design, but the PHY is a little +quirky. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-7-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f54329861496..f6049dadc3d3 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -351,6 +351,20 @@ uart0: serial@ffe7014000 { + status = "disabled"; + }; + ++ usb: usb@ffe7040000 { ++ compatible = "snps,dwc3"; ++ reg = <0xff 0xe7040000 0x0 0x10000>; ++ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_misc CLK_USB>, ++ <&clk_misc CLK_USB_CTL_REF>, ++ <&clk_misc CLK_USB_SUSPEND>; ++ clock-names = "bus_early", "ref", "suspend"; ++ resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>; ++ phys = <&usb_phy>; ++ phy-names = "usb3-phy"; ++ status = "disabled"; ++ }; ++ + gmac1: ethernet@ffe7060000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; +@@ -586,6 +600,19 @@ clk_misc: clock-controller@ffec02c100 { + #clock-cells = <1>; + }; + ++ usb_phy: phy@ffec030000 { ++ compatible = "thead,th1520-usb-phy"; ++ reg = <0xff 0xec030000 0x0 0x10000>; ++ clocks = <&clk_misc CLK_USB>, ++ <&clk_misc CLK_USB_PHY_REF>; ++ clock-names = "bus", "ref"; ++ resets = <&rst_misc TH1520_RESET_ID_USB3_APB>, ++ <&rst_misc TH1520_RESET_ID_USB3_PHY>; ++ reset-names = "bus", "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0477-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux-lts/0477-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch new file mode 100644 index 0000000000..50054349a0 --- /dev/null +++ b/SPECS/linux-lts/0477-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch @@ -0,0 +1,48 @@ +From df0426871c47577b198bcc8cff14405a4b5a2e4e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:06 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports + property + +As a USB hub device, VL817 can surely be connected to external USB +connectors. The binding for such connectors connection is already +described in the generic usb-hub.yaml binding with ports subnode, but +it's not yet allowed in the VL817 binding. + +Switch the reference binding from usb-device.yaml to usb-hub.yaml (which +recursively references usb-device.yaml and contains definition for ports +subnode) and allow ports subnode in VL817 binding. + +Cc: Anand Moon +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-9-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +index c815010ba9c2..7387f4fae54d 100644 +--- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml ++++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +@@ -10,7 +10,7 @@ maintainers: + - Anand Moon + + allOf: +- - $ref: usb-device.yaml# ++ - $ref: usb-hub.yaml# + + properties: + compatible: +@@ -34,6 +34,8 @@ properties: + description: + phandle to the peer hub on the controller. + ++ ports: true ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts/0478-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux-lts/0478-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch new file mode 100644 index 0000000000..3d307a7d12 --- /dev/null +++ b/SPECS/linux-lts/0478-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch @@ -0,0 +1,66 @@ +From 1462dae45364f55b5bd2abc1fe3843cd79e6d08e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:07 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes + +Although "D" and "H" are earlier in the alphabet than "P", the DPU and +HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. + +Sort the nodes in this device tree. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-10-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index af6f25ebbf60..834ee72a77ee 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -117,6 +117,20 @@ i2c-pins { + }; + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -179,20 +193,6 @@ &sdio1 { + status = "okay"; + }; + +-&dpu { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out_port { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0479-BACKPORT-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nod.patch b/SPECS/linux-lts/0479-BACKPORT-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nod.patch new file mode 100644 index 0000000000..08c762a841 --- /dev/null +++ b/SPECS/linux-lts/0479-BACKPORT-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nod.patch @@ -0,0 +1,111 @@ +From 999615d8e829b7e54b7f592523530f707b09a765 Mon Sep 17 00:00:00 2001 +From: Thomas Bonnefille +Date: Thu, 7 May 2026 16:17:08 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: riscv: dts: thead: Add TH1520 I2C + nodes + +Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. + +Signed-off-by: Thomas Bonnefille +Reviewed-by: Drew Fustini +[Icenowy: rebase on top of v7.1-rc2] +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-11-zhengxingda@iscas.ac.cn +[Han Gao: i2c1 node has been merged, so drop it from origin patch] +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f6049dadc3d3..aa757ddd6046 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -460,6 +460,16 @@ uart3: serial@ffe7f04000 { + status = "disabled"; + }; + ++ i2c0: i2c@ffe7f20000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f20000 0x0 0x4000>; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2c1: i2c@ffe7f24000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; +@@ -471,6 +481,16 @@ i2c1: i2c@ffe7f24000 { + status = "disabled"; + }; + ++ i2c4: i2c@ffe7f28000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f28000 0x0 0x4000>; ++ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C4>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; +@@ -569,6 +589,16 @@ padctrl0_apsys: pinctrl@ffec007000 { + thead,pad-group = <3>; + }; + ++ i2c2: i2c@ffec00c000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xec00c000 0x0 0x4000>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; +@@ -580,6 +610,16 @@ uart2: serial@ffec010000 { + status = "disabled"; + }; + ++ i2c3: i2c@ffec014000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xec014000 0x0 0x4000>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C3>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + pwm: pwm@ffec01c000 { + compatible = "thead,th1520-pwm"; + reg = <0xff 0xec01c000 0x0 0x4000>; +@@ -805,6 +845,16 @@ uart5: serial@fff7f0c000 { + status = "disabled"; + }; + ++ i2c5: i2c@fff7f2c000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xf7f2c000 0x0 0x4000>; ++ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C5>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0480-BACKPORT-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-I.patch b/SPECS/linux-lts/0480-BACKPORT-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-I.patch new file mode 100644 index 0000000000..d1f85614e9 --- /dev/null +++ b/SPECS/linux-lts/0480-BACKPORT-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-I.patch @@ -0,0 +1,189 @@ +From 7d0c40ab6d9603c045e3ec1c534a923b54c228af Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Thu, 7 May 2026 16:17:09 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: riscv: dts: thead: Add Lichee Pi 4A + IO expansions + +Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the +I2C0/1/3 busses. + +Add device tree nodes for them. + +Signed-off-by: Emil Renner Berthing +[Icenowy: added commit description] +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-12-zhengxingda@iscas.ac.cn +[Han Gao: Remove the upstream i2c1 node + and set the i2c1 clock frequency to the mainline value. ] +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 125 ++++++++++++++++-- + 1 file changed, 111 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 834ee72a77ee..76c211ffdbf9 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -17,6 +17,9 @@ aliases { + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &aogpio; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; +@@ -131,6 +134,76 @@ hdmi_out_con: endpoint { + }; + }; + ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp1: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "cam0_dvdd12", ++ "cam0_avdd28", ++ "cam0_dovdd18"; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <400000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp2: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "", ++ "cam0_reset", ++ "cam1_reset", ++ "cam2_reset", ++ "wl_host_wake", ++ "bt_resetn", ++ "", ++ "bt_host_wake"; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp3: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "tp0_rst", ++ "", ++ "", ++ "vcc5v_usb", ++ "vdd28_tp0", ++ "vdd33_lcd0", ++ "vdd18_lcd0", ++ "lcd0_reset"; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -144,6 +217,18 @@ pwm1-pins { + }; + }; + ++ i2c3_pins: i2c3-0 { ++ i2c-pins { ++ pins = "I2C3_SCL", "I2C3_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++ + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; +@@ -167,20 +252,6 @@ rx-pins { + }; + }; + +-&i2c1 { +- clock-frequency = <400000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c1_pins>; +- status = "okay"; +- +- ioexp2: gpio@18 { +- compatible = "nxp,pca9557"; +- reg = <0x18>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +-}; +- + &sdio1 { + #address-cells = <1>; + #size-cells = <0>; +@@ -193,6 +264,32 @@ &sdio1 { + status = "okay"; + }; + ++&padctrl1_apsys { ++ i2c0_pins: i2c0-0 { ++ i2c-pins { ++ pins = "I2C0_SCL", "I2C0_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-0 { ++ i2c-pins { ++ pins = "I2C1_SCL", "I2C1_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0481-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux-lts/0481-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch new file mode 100644 index 0000000000..5fa7f15e44 --- /dev/null +++ b/SPECS/linux-lts/0481-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch @@ -0,0 +1,298 @@ +From fc84999cabbda71a6f64d0b05b52714597ab9717 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:10 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee + Pi 4A + +The Lichee Pi 4A board features an onboard VIA VL817 hub connected to +the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as +downstream. + +Enable SoC USB3 and the hub on Lichee Pi 4A. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-13-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 230 ++++++++++++++++++ + 2 files changed, 245 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +index 8e76b63e0100..bfda5a6b56b8 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +@@ -20,6 +20,16 @@ memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; ++ ++ /* TODO: Switch to AON regulator when it's available. */ ++ avdd33_usb3: regulator-avdd33-usb3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AVDD33_USB3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ /* Marked as always on on the schematics */ ++ regulator-always-on; ++ }; + }; + + &osc { +@@ -202,3 +212,8 @@ &sdio0 { + max-frequency = <198000000>; + status = "okay"; + }; ++ ++&usb_phy { ++ avdd33-usb3-supply = <&avdd33_usb3>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 76c211ffdbf9..da3425a44f63 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -104,6 +104,141 @@ fan: pwm-fan { + cooling-levels = <0 66 196 255>; + }; + ++ hub_5v: regulator-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "HUB_5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&ioexp3 3 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc5v_usb: regulator-vcc5v-usb { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V_USB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* ++ * Workaround for Linux currently being not able to power on ++ * Vbus for USB Type-A connectors. ++ */ ++ regulator-always-on; ++ }; ++ ++ connector-usb-a-1 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_1_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port1_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_1_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port1_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-2 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_2_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port2_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_2_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port2_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-3 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_3_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port3_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_3_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port3_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-4 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_4_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port4_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_4_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port4_ep>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&aogpio { ++ /* Route USB2 to the onboard hub for normal operation */ ++ sel-usb-hub-hog { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; + }; + + &padctrl1_apsys { +@@ -295,3 +430,98 @@ &uart0 { + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&usb { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_hs: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <1>; ++ peer-hub = <&hub_ss>; ++ vdd-supply = <&hub_5v>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ hub_hs_port1_ep: endpoint { ++ remote-endpoint = <&usb_a_1_hs_ep>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ hub_hs_port2_ep: endpoint { ++ remote-endpoint = <&usb_a_2_hs_ep>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ hub_hs_port3_ep: endpoint { ++ remote-endpoint = <&usb_a_3_hs_ep>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ hub_hs_port4_ep: endpoint { ++ remote-endpoint = <&usb_a_4_hs_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ hub_ss: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <2>; ++ peer-hub = <&hub_hs>; ++ vdd-supply = <&hub_5v>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ hub_ss_port1_ep: endpoint { ++ remote-endpoint = <&usb_a_1_ss_ep>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ hub_ss_port2_ep: endpoint { ++ remote-endpoint = <&usb_a_2_ss_ep>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ hub_ss_port3_ep: endpoint { ++ remote-endpoint = <&usb_a_3_ss_ep>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ hub_ss_port4_ep: endpoint { ++ remote-endpoint = <&usb_a_4_ss_ep>; ++ }; ++ }; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0482-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux-lts/0482-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch new file mode 100644 index 0000000000..3c624e3928 --- /dev/null +++ b/SPECS/linux-lts/0482-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch @@ -0,0 +1,318 @@ +From 5da3180c2d8a66742b63158bf1717c6352af5d7c Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 8 May 2026 15:25:24 +0800 +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for + accurate SCL frequency + +The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for +master mode operations is determined by the ILCR (I2C Load Count Register). +Previously, the driver relied on the hardware's reset default +values for this register. + +The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL +frequencies lower than intended. For example, with the default +31.5 MHz input clock, these default settings result in an SCL +frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, +and approximately 338 kHz (fast mode) when targeting 400 kHz. +These frequencies are below the 100 kHz/400 kHz nominal speeds. + +This patch integrates the SCL frequency management into +the Common Clock Framework (CCF). Specifically, the ILCR register, +which acts as a frequency divider for the SCL clock, is now registered +as a managed clock (scl_clk) within the CCF. + +The actual hardware timing formulas are: +- standard mode: SCL = FCLK / (2 * SLV + 8) +- fast mode: SCL = FCLK / (2 * FLV + 10) + +These formulas are only valid when the IWCR (Wait Count Register) is +programmed to 0x142A, a value specified by the I2C IP designer. The +driver now initializes IWCR to this value during controller init. + +Reviewed-by: Yixun Lan +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/i2c/busses/Kconfig | 2 +- + drivers/i2c/busses/i2c-k1.c | 174 ++++++++++++++++++++++++++++++++++-- + 2 files changed, 167 insertions(+), 9 deletions(-) + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index e60faac4e337..456cced004b2 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -798,7 +798,7 @@ config I2C_JZ4780 + config I2C_K1 + tristate "SpacemiT K1 I2C adapter" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on OF ++ depends on OF && COMMON_CLK + default ARCH_SPACEMIT + help + This option enables support for the I2C interface on the SpacemiT K1 +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 9152cf436bea..c6fe2052e479 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -4,7 +4,9 @@ + */ + + #include ++#include + #include ++#include + #include + #include + #include +@@ -17,6 +19,8 @@ + #define SPACEMIT_ISR 0x4 /* Status register */ + #define SPACEMIT_IDBR 0xc /* Data buffer register */ + #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ ++#define SPACEMIT_ILCR 0x10 /* Load Count Register */ ++#define SPACEMIT_IWCR 0x14 /* Wait Count Register */ + #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ + + /* SPACEMIT_ICR register fields */ +@@ -88,6 +92,19 @@ + #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ + #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ + ++#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0) ++#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9) ++ ++/* SPACEMIT_IWCR register fields */ ++#define SPACEMIT_WCR_COUNT GENMASK(4, 0) ++#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5) ++#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10) ++ ++/* Required by I2C IP for correct SCL timing */ ++#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \ ++ FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \ ++ FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5)) ++ + /* i2c bus recover timeout: us */ + #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 + +@@ -109,11 +126,20 @@ enum spacemit_i2c_state { + SPACEMIT_STATE_WRITE, + }; + ++enum spacemit_i2c_mode { ++ SPACEMIT_MODE_STANDARD, ++ SPACEMIT_MODE_FAST ++}; ++ + /* i2c-spacemit driver's main struct */ + struct spacemit_i2c_dev { + struct device *dev; + struct i2c_adapter adapt; + ++ struct clk_hw scl_clk_hw; ++ struct clk *scl_clk; ++ enum spacemit_i2c_mode mode; ++ + /* hardware resources */ + void __iomem *base; + int irq; +@@ -135,6 +161,85 @@ struct spacemit_i2c_dev { + u32 status; + }; + ++static void spacemit_i2c_scl_clk_disable_unprepare(void *data) ++{ ++ clk_disable_unprepare(data); ++} ++ ++/* ++ * Calculate the ILCR divider value (lv) from the target SCL rate. ++ * ++ * Hardware timing formulas: ++ * - standard mode: SCL = FCLK / (2 * SLV + 8) ++ * - fast mode: SCL = FCLK / (2 * FLV + 10) ++ */ ++static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c, ++ unsigned long parent_rate, ++ unsigned long target_rate) ++{ ++ u32 offset, denom; ++ ++ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; ++ denom = DIV_ROUND_CLOSEST(parent_rate, target_rate); ++ ++ return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2); ++} ++ ++static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lv, lcr, mask; ++ ++ lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate); ++ ++ mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ? ++ SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK; ++ ++ lcr = readl(i2c->base + SPACEMIT_ILCR); ++ lcr &= ~mask; ++ lcr |= field_prep(mask, lv); ++ writel(lcr, i2c->base + SPACEMIT_ILCR); ++ ++ return 0; ++} ++ ++static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lv, offset; ++ ++ lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate); ++ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; ++ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset); ++ ++ return 0; ++} ++ ++static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lcr, lv = 0; ++ ++ lcr = readl(i2c->base + SPACEMIT_ILCR); ++ ++ if (i2c->mode == SPACEMIT_MODE_STANDARD) { ++ lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr); ++ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8); ++ } ++ ++ lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr); ++ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10); ++} ++ ++static const struct clk_ops spacemit_i2c_clk_ops = { ++ .set_rate = spacemit_i2c_clk_set_rate, ++ .determine_rate = spacemit_i2c_clk_determine_rate, ++ .recalc_rate = spacemit_i2c_clk_recalc_rate, ++}; ++ + static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) + { + u32 val; +@@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_ICR); + } + ++static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c) ++{ ++ struct clk_init_data init = {}; ++ char name[64]; ++ int ret; ++ ++ ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev)); ++ if (ret >= ARRAY_SIZE(name)) ++ dev_warn(i2c->dev, "scl clock name truncated"); ++ ++ init.name = name; ++ init.ops = &spacemit_i2c_clk_ops; ++ init.parent_data = (struct clk_parent_data[]) { ++ { .fw_name = "func" }, ++ }; ++ init.num_parents = 1; ++ ++ i2c->scl_clk_hw.init = &init; ++ ++ return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw); ++} ++ + static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) + { + writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); +@@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + val |= SPACEMIT_CR_MSDIE; + } + +- if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) ++ if (i2c->mode == SPACEMIT_MODE_FAST) + val |= SPACEMIT_CR_MODE_FAST; + + /* disable response to general call */ +@@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_IRCR); + + spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); ++ ++ /* ++ * Initialize IWCR to the value specified by the I2C IP designer. ++ * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard ++ * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when ++ * IWCR contains this specific value. ++ */ ++ writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR); + } + + static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) +@@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); + + /* For now, this driver doesn't support high-speed. */ +- if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { +- dev_warn(dev, "unsupported clock frequency %u; using %u\n", +- i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); ++ if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && ++ i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { ++ i2c->mode = SPACEMIT_MODE_FAST; ++ } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { ++ i2c->mode = SPACEMIT_MODE_STANDARD; ++ } else { ++ dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); ++ i2c->mode = SPACEMIT_MODE_FAST; + i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; +- } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { +- dev_warn(dev, "unsupported clock frequency %u; using %u\n", +- i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); +- i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; + } + + i2c->dev = &pdev->dev; +@@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); + ++ ret = spacemit_i2c_register_scl_clk(i2c); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register scl clock\n"); ++ ++ i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl"); ++ if (IS_ERR(i2c->scl_clk)) ++ return dev_err_probe(dev, PTR_ERR(i2c->scl_clk), ++ "failed to get scl clock\n"); ++ + clk = devm_clk_get_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); +@@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + return dev_err_probe(dev, PTR_ERR(rst), + "failed to acquire deasserted reset\n"); + ++ ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to set rate for SCL clock"); ++ ++ ret = clk_prepare_enable(i2c->scl_clk); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to prepare and enable clock"); ++ ++ ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare, ++ i2c->scl_clk); ++ if (ret) ++ return ret; ++ + spacemit_i2c_reset(i2c); + + i2c_set_adapdata(&i2c->adapt, i2c); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0483-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux-lts/0483-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch new file mode 100644 index 0000000000..497fbf65d0 --- /dev/null +++ b/SPECS/linux-lts/0483-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch @@ -0,0 +1,45 @@ +From f68f6e52d9807e19c5662a3a3a157ddcee8d1098 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 8 May 2026 15:25:25 +0800 +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when + clock-frequency property is absent + +The clock-frequency property is optional according to the DT binding. +Do not emit a warning when the property is missing and fall back to the +default frequency instead. + +Reviewed-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index c6fe2052e479..7cf5c05a20d2 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -833,9 +833,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (!i2c) + return -ENOMEM; + +- ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); +- if (ret && ret != -EINVAL) +- dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); ++ of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); + + /* For now, this driver doesn't support high-speed. */ + if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && +@@ -844,7 +842,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { + i2c->mode = SPACEMIT_MODE_STANDARD; + } else { +- dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); ++ dev_info(dev, "clock-frequency not set or out of range, using fast mode\n"); + i2c->mode = SPACEMIT_MODE_FAST; + i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0484-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux-lts/0484-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch new file mode 100644 index 0000000000..b4ce439eb6 --- /dev/null +++ b/SPECS/linux-lts/0484-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch @@ -0,0 +1,102 @@ +From fd0b7e4ebbd77c9d9180ee860c936e95844e4a2c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:21 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support + +To reuse the K1 PCIe driver logic for K3 PCIe controller, add device +data to handle the K1 specific logic and make room for the incoming +logic for K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 30 ++++++++++++++++--- + 1 file changed, 26 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index be20a520255b..f6ae8ff3589a 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -49,8 +49,17 @@ + #define PCIE_CONTROL_LOGIC 0x0004 + #define PCIE_SOFT_RESET BIT(0) + ++struct k1_pcie; ++ ++struct k1_pcie_device_data { ++ const struct dw_pcie_host_ops *host_ops; ++ const struct dw_pcie_ops *ops; ++ int (*parse_port)(struct k1_pcie *k1); ++}; ++ + struct k1_pcie { + struct dw_pcie pci; ++ const struct k1_pcie_device_data *data; + struct phy *phy; + void __iomem *link; + struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ +@@ -278,14 +287,21 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + + static int k1_pcie_probe(struct platform_device *pdev) + { ++ const struct k1_pcie_device_data *data; + struct device *dev = &pdev->dev; + struct k1_pcie *k1; + int ret; + ++ data = device_get_match_data(dev); ++ if (!data) ++ return -ENODEV; ++ + k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); + if (!k1) + return -ENOMEM; + ++ k1->data = data; ++ + k1->pmu = syscon_regmap_lookup_by_phandle_args(dev_of_node(dev), + SYSCON_APMU, 1, + &k1->pmu_off); +@@ -299,11 +315,11 @@ static int k1_pcie_probe(struct platform_device *pdev) + "failed to map \"link\" registers\n"); + + k1->pci.dev = dev; +- k1->pci.ops = &k1_pcie_ops; ++ k1->pci.ops = data->ops; + k1->pci.pp.num_vectors = MAX_MSI_IRQS; + dw_pcie_cap_set(&k1->pci, REQ_RES); + +- k1->pci.pp.ops = &k1_pcie_host_ops; ++ k1->pci.pp.ops = data->host_ops; + + /* Hold the PHY in reset until we start the link */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, +@@ -320,7 +336,7 @@ static int k1_pcie_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, k1); + +- ret = k1_pcie_parse_port(k1); ++ ret = data->parse_port(k1); + if (ret) + return dev_err_probe(dev, ret, "failed to parse root port\n"); + +@@ -338,8 +354,14 @@ static void k1_pcie_remove(struct platform_device *pdev) + dw_pcie_host_deinit(&k1->pci.pp); + } + ++static const struct k1_pcie_device_data k1_pcie_device_data = { ++ .host_ops = &k1_pcie_host_ops, ++ .ops = &k1_pcie_ops, ++ .parse_port = k1_pcie_parse_port, ++}; ++ + static const struct of_device_id k1_pcie_of_match_table[] = { +- { .compatible = "spacemit,k1-pcie", }, ++ { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, + { } + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0485-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux-lts/0485-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch new file mode 100644 index 0000000000..9583f0fd23 --- /dev/null +++ b/SPECS/linux-lts/0485-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch @@ -0,0 +1,155 @@ +From 7851cfa52f4968dd95e9c120403957785bd51bac Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:22 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles + support + +The PCIe controller on Spacemit K3 may use multiple PHYs at the +same time. The feature is not support by the current driver. +So extend the PHY definition to support multiple PHY handles. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 70 ++++++++++++++++--- + 1 file changed, 59 insertions(+), 11 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index f6ae8ff3589a..e22ecbd09579 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -55,12 +55,14 @@ struct k1_pcie_device_data { + const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ops *ops; + int (*parse_port)(struct k1_pcie *k1); ++ unsigned int max_phy_count; + }; + + struct k1_pcie { + struct dw_pcie pci; + const struct k1_pcie_device_data *data; +- struct phy *phy; ++ struct phy **phy; ++ unsigned int phy_count; + void __iomem *link; + struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ + u32 pmu_off; +@@ -119,6 +121,54 @@ static void k1_pcie_disable_resources(struct k1_pcie *k1) + clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); + } + ++static int k1_pcie_get_phy_handle(struct k1_pcie *k1, struct device_node *node) ++{ ++ const struct k1_pcie_device_data *data = k1->data; ++ struct device *dev = k1->pci.dev; ++ unsigned int i; ++ ++ k1->phy = devm_kmalloc_array(dev, data->max_phy_count, ++ sizeof(*k1->phy), GFP_KERNEL); ++ if (!k1->phy) ++ return -ENOMEM; ++ ++ for (i = 0; i < data->max_phy_count; i++) { ++ k1->phy[i] = devm_of_phy_get_by_index(dev, node, i); ++ if (IS_ERR(k1->phy[i])) { ++ if (PTR_ERR(k1->phy[i]) == -ENODEV) ++ break; ++ ++ return PTR_ERR(k1->phy[i]); ++ } ++ } ++ ++ k1->phy_count = i; ++ if (k1->phy_count == 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int k1_pcie_enable_phy(struct k1_pcie *k1) ++{ ++ unsigned int i; ++ int ret; ++ ++ for (i = 0; i < k1->phy_count; i++) { ++ ret = phy_init(k1->phy[i]); ++ if (ret) ++ goto err_phy; ++ } ++ ++ return 0; ++ ++err_phy: ++ while (i--) ++ phy_exit(k1->phy[i]); ++ ++ return ret; ++} ++ + /* FIXME: Disable ASPM L1 to avoid errors reported on some NVMe drives */ + static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) + { +@@ -174,7 +224,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) + */ + regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); + +- ret = phy_init(k1->phy); ++ ret = k1_pcie_enable_phy(k1); + if (ret) { + k1_pcie_disable_resources(k1); + +@@ -194,12 +244,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct k1_pcie *k1 = to_k1_pcie(pci); ++ int i; + + /* Assert fundamental reset (drive PERST# low) */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + PCIE_RC_PERST); + +- phy_exit(k1->phy); ++ for (i = 0; i < k1->phy_count; i++) ++ phy_exit(k1->phy[i]); + + k1_pcie_disable_resources(k1); + } +@@ -266,23 +318,18 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + { + struct device *dev = k1->pci.dev; + struct device_node *root_port; +- struct phy *phy; ++ int ret; + + /* We assume only one root port */ + root_port = of_get_next_available_child(dev_of_node(dev), NULL); + if (!root_port) + return -EINVAL; + +- phy = devm_of_phy_get(dev, root_port, NULL); ++ ret = k1_pcie_get_phy_handle(k1, root_port); + + of_node_put(root_port); + +- if (IS_ERR(phy)) +- return PTR_ERR(phy); +- +- k1->phy = phy; +- +- return 0; ++ return ret; + } + + static int k1_pcie_probe(struct platform_device *pdev) +@@ -358,6 +405,7 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .host_ops = &k1_pcie_host_ops, + .ops = &k1_pcie_ops, + .parse_port = k1_pcie_parse_port, ++ .max_phy_count = 1, + }; + + static const struct of_device_id k1_pcie_of_match_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0486-FROMLIST-PCI-spacemit-k1-Add-device-id-update-helper.patch b/SPECS/linux-lts/0486-FROMLIST-PCI-spacemit-k1-Add-device-id-update-helper.patch new file mode 100644 index 0000000000..0b8258558c --- /dev/null +++ b/SPECS/linux-lts/0486-FROMLIST-PCI-spacemit-k1-Add-device-id-update-helper.patch @@ -0,0 +1,67 @@ +From 1ceddcb346dade0ca601ead0c65044ffd409b988 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:23 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device id update helper + +Both K1 and K3 needs to set vendor id and device id, add a helper function +to simplify this. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-4-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index e22ecbd09579..31aac056b68e 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -56,6 +56,7 @@ struct k1_pcie_device_data { + const struct dw_pcie_ops *ops; + int (*parse_port)(struct k1_pcie *k1); + unsigned int max_phy_count; ++ unsigned int device_id; + }; + + struct k1_pcie { +@@ -186,6 +187,16 @@ static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) + dw_pcie_dbi_ro_wr_dis(pci); + } + ++static void k1_pcie_set_device_id(struct k1_pcie *k1) ++{ ++ struct dw_pcie *pci = &k1->pci; ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); ++ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, k1->data->device_id); ++ dw_pcie_dbi_ro_wr_dis(pci); ++} ++ + static int k1_pcie_init(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); +@@ -201,10 +212,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) + return ret; + + /* Set the PCI vendor and device ID */ +- dw_pcie_dbi_ro_wr_en(pci); +- dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); +- dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K1); +- dw_pcie_dbi_ro_wr_dis(pci); ++ k1_pcie_set_device_id(k1); + + /* + * Start by asserting fundamental reset (drive PERST# low). The +@@ -406,6 +414,7 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .ops = &k1_pcie_ops, + .parse_port = k1_pcie_parse_port, + .max_phy_count = 1, ++ .device_id = PCI_DEVICE_ID_SPACEMIT_K1, + }; + + static const struct of_device_id k1_pcie_of_match_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0487-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux-lts/0487-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch new file mode 100644 index 0000000000..d2a3059f97 --- /dev/null +++ b/SPECS/linux-lts/0487-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch @@ -0,0 +1,42 @@ +From a9276d0da521588ea063c1d7e3e66f14c971fd73 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:24 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent + for MSI handle check + +The IMSIC device on RISC-V based system does not require ID +remapping for MSI. So this device only needs "msi-parent" +property for IMSIC-based SoC, and the "msi-map" is not a +necessary property. + +Add new condition for MSI handling on IMSIC based SoC. + +Signed-off-by: Inochi Amaoto +Acked-by: Rob Herring (Arm) +Link: https://lore.kernel.org/r/20260709040027.958400-5-inochiama@gmail.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +index b3216141881c..91bbbc8924f6 100644 +--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml ++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +@@ -27,8 +27,11 @@ allOf: + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + - if: + not: +- required: +- - msi-map ++ anyOf: ++ - required: ++ - msi-map ++ - required: ++ - msi-parent + then: + properties: + interrupt-names: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0488-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux-lts/0488-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch new file mode 100644 index 0000000000..4276f26d42 --- /dev/null +++ b/SPECS/linux-lts/0488-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch @@ -0,0 +1,123 @@ +From 12732c2c8ac64d1c18abbee127dd9dca49efd4a2 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:25 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit + K3 PCIe host controller + +Add binding support for the PCIe controller on the SpacemiT K3 SoC. +This controller is almost a standard Synopsys DesignWare PCIe IP, +with some extra link and reset state control. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-6-inochiama@gmail.com +Signed-off-by: Han Gao +--- + .../bindings/pci/spacemit,k1-pcie-host.yaml | 50 ++++++++++++++++--- + 1 file changed, 43 insertions(+), 7 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml +index c4c00b5fcdc0..54817d6fd9af 100644 +--- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml ++++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml +@@ -14,26 +14,29 @@ description: > + PCIe IP. The controller uses the DesignWare built-in MSI interrupt + controller, and supports 256 MSIs. + +-allOf: +- - $ref: /schemas/pci/snps,dw-pcie.yaml# +- + properties: + compatible: +- const: spacemit,k1-pcie ++ enum: ++ - spacemit,k1-pcie ++ - spacemit,k3-pcie + + reg: ++ minItems: 4 + items: + - description: DesignWare PCIe registers + - description: ATU address space + - description: PCIe configuration space + - description: Link control registers ++ - description: Data Bus Interface (DBI) shadow registers. + + reg-names: ++ minItems: 4 + items: + - const: dbi + - const: atu + - const: config + - const: link ++ - const: dbi2 + + clocks: + items: +@@ -66,6 +69,8 @@ properties: + interrupt-names: + const: msi + ++ msi-parent: true ++ + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: +@@ -84,7 +89,8 @@ patternProperties: + + properties: + phys: +- maxItems: 1 ++ minItems: 1 ++ maxItems: 6 + + vpcie3v3-supply: + description: +@@ -96,13 +102,43 @@ patternProperties: + + unevaluatedProperties: false + ++allOf: ++ - $ref: /schemas/pci/snps,dw-pcie.yaml# ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k1-pcie ++ then: ++ properties: ++ reg: ++ maxItems: 4 ++ ++ reg-names: ++ maxItems: 4 ++ ++ patternProperties: ++ '^pcie@': ++ properties: ++ phys: ++ maxItems: 1 ++ ++ required: ++ - interrupts ++ - interrupt-names ++ else: ++ properties: ++ reg: ++ minItems: 5 ++ ++ reg-names: ++ minItems: 5 ++ + required: + - clocks + - clock-names + - resets + - reset-names +- - interrupts +- - interrupt-names + - spacemit,apmu + + unevaluatedProperties: false +-- +2.53.0 + diff --git a/SPECS/linux-lts/0489-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux-lts/0489-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch new file mode 100644 index 0000000000..89e72f0baf --- /dev/null +++ b/SPECS/linux-lts/0489-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch @@ -0,0 +1,215 @@ +From 2a6036e000e9f2ba727072be0a8d992a502938ec Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:00:26 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host + controller support + +The PCIe controller on Spacemit K3 is almost a standard Synopsys +DesignWare PCIe IP with extra link and reset control. Unlike +the PCIe controller on K1, this controller supports external MSI +interrupt controller and can use multiple PHYs at the same time. + +Add driver to support PCIe controller on Spacemit K3 PCIe. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040027.958400-7-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/Kconfig | 4 +- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 126 ++++++++++++++++++ + 2 files changed, 128 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index af024a18621d..a1d7192e705f 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -417,7 +417,7 @@ config PCIE_SOPHGO_DW + Sophgo SoCs. + + config PCIE_SPACEMIT_K1 +- tristate "SpacemiT K1 PCIe controller (host mode)" ++ tristate "SpacemiT PCIe controller (host mode)" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on HAS_IOMEM + select PCIE_DW_HOST +@@ -425,7 +425,7 @@ config PCIE_SPACEMIT_K1 + default ARCH_SPACEMIT + help + Enables support for the DesignWare based PCIe controller in +- the SpacemiT K1 SoC operating in host mode. Three controllers ++ the SpacemiT SoC operating in host mode. Three controllers + are available on the K1 SoC; the first of these shares a PHY + with a USB 3.0 host controller (one or the other can be used). + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 31aac056b68e..680acc93f539 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -23,6 +23,7 @@ + + #define PCI_VENDOR_ID_SPACEMIT 0x201f + #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 + + /* Offsets and field definitions for link management registers */ + #define K1_PHY_AHB_IRQ_EN 0x0000 +@@ -32,8 +33,18 @@ + #define SMLH_LINK_UP BIT(1) + #define RDLH_LINK_UP BIT(12) + ++#define INTR_STATUS 0x0010 ++ + #define INTR_ENABLE 0x0014 + #define MSI_CTRL_INT BIT(11) ++#define RDLH_LINK_UP_INT BIT(20) ++ ++#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 ++ ++#define K3_ADDR_INTR_STATUS1 0x0018 ++ ++#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) ++#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf + + /* Some controls require APMU regmap access */ + #define SYSCON_APMU "spacemit,apmu" +@@ -48,6 +59,9 @@ + + #define PCIE_CONTROL_LOGIC 0x0004 + #define PCIE_SOFT_RESET BIT(0) ++#define PCIE_PERSTN_OE BIT(24) ++#define PCIE_PERSTN_OUT BIT(25) ++#define PCIE_IGNORE_PERSTN BIT(31) + + struct k1_pcie; + +@@ -340,6 +354,109 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + return ret; + } + ++static int k3_pcie_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct k1_pcie *k1 = to_k1_pcie(pci); ++ u32 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; ++ u32 val; ++ int ret; ++ ++ regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); ++ ++ k1_pcie_toggle_soft_reset(k1); ++ ++ ret = k1_pcie_enable_resources(k1); ++ if (ret) ++ return ret; ++ ++ regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); ++ regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); ++ ++ ret = k1_pcie_enable_phy(k1); ++ if (ret) { ++ k1_pcie_disable_resources(k1); ++ return ret; ++ } ++ ++ /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ ++ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, ++ PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); ++ usleep_range(1000, 2000); ++ regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); ++ ++ msleep(PCIE_T_PVPERL_MS); ++ ++ /* ++ * Put the controller in root complex mode, and indicate that ++ * Vaux (3.3v) is present. ++ */ ++ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, ++ PCIE_PERSTN_OUT | PCIE_PERSTN_OE); ++ ++ val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); ++ val = u32_replace_bits(val, BIT(7), ++ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); ++ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); ++ ++ k1_pcie_set_device_id(k1); ++ ++ /* Finally, as a workaround, disable ASPM L1 */ ++ k1_pcie_disable_aspm_l1(k1); ++ ++ return 0; ++} ++ ++static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ u32 val; ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ ++ val = dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); ++ val = u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, ++ K3_CACHE_MSTR_AWCACHE_MODE); ++ dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); ++ ++ dw_pcie_dbi_ro_wr_dis(pci); ++ ++ return 0; ++} ++ ++static const struct dw_pcie_host_ops k3_pcie_host_ops = { ++ .init = k3_pcie_init, ++ .deinit = k1_pcie_deinit, ++ .msi_init = k3_pcie_msi_host_init, ++}; ++ ++static const struct dw_pcie_ops k3_pcie_ops = { ++ .link_up = k1_pcie_link_up, ++ .start_link = k1_pcie_start_link, ++ .stop_link = k1_pcie_stop_link, ++}; ++ ++static void k3_pcie_clear_irq_status(struct k1_pcie *k1, ++ u32 *status0, u32 *status1, u32 *status2) ++{ ++ *status0 = readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); ++ *status1 = readl_relaxed(k1->link + INTR_STATUS); ++ *status2 = readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); ++ ++ writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); ++ writel_relaxed(*status1, k1->link + INTR_STATUS); ++ writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); ++} ++ ++static int k3_pcie_parse_port(struct k1_pcie *k1) ++{ ++ u32 status0, status1, status2; ++ ++ k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); ++ ++ return k1_pcie_parse_port(k1); ++} ++ + static int k1_pcie_probe(struct platform_device *pdev) + { + const struct k1_pcie_device_data *data; +@@ -417,8 +534,17 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .device_id = PCI_DEVICE_ID_SPACEMIT_K1, + }; + ++static const struct k1_pcie_device_data k3_pcie_device_data = { ++ .host_ops = &k3_pcie_host_ops, ++ .ops = &k3_pcie_ops, ++ .parse_port = k3_pcie_parse_port, ++ .max_phy_count = 6, ++ .device_id = PCI_DEVICE_ID_SPACEMIT_K3, ++}; ++ + static const struct of_device_id k1_pcie_of_match_table[] = { + { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, ++ { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, + { } + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0490-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux-lts/0490-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch new file mode 100644 index 0000000000..11295a44f1 --- /dev/null +++ b/SPECS/linux-lts/0490-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch @@ -0,0 +1,37 @@ +From 3748a5c47c8c95ff1013a6db12e90030fea6d4bf Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 02:58:36 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock + +According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus +clock enable bit was wrongly swapped, the correct one should be: + +Register : APMU_USB_CLK_RES_CTRL +bit[1] : usb2_port_bus_clk_en +bit[0] : usb2_port_ahb_rstn + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Junzhong Pan +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index cb0c4277f72a..03de04144963 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -777,7 +777,7 @@ static const struct clk_parent_data sdh2_parents[] = { + CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, + BIT(11), 5, 3, BIT(4), 0); + +-CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); + CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); + CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); + CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0491-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux-lts/0491-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch new file mode 100644 index 0000000000..23a19eb2ae --- /dev/null +++ b/SPECS/linux-lts/0491-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch @@ -0,0 +1,37 @@ +From 22ec86aedc922b5afebd7f4c23b120545a563e69 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 02:58:37 +0000 +Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset + +According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus +clock enable bit was wrongly swapped, the correct one should be: + +Register : APMU_USB_CLK_RES_CTRL +bit[1] : usb2_port_bus_clk_en +bit[0] : usb2_port_ahb_rstn + +Fixes: a0e0c2f8c5f3 ("reset: spacemit: k3: Decouple composite reset lines") +Reported-by: Junzhong Pan +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/reset-spacemit-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +index 9841f5e057b2..2e87f320cf11 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k3.c ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), +- [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), + [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), + [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0492-FROMLIST-riscv-dts-spacemit-k3-Add-QSPI-support-for-.patch b/SPECS/linux-lts/0492-FROMLIST-riscv-dts-spacemit-k3-Add-QSPI-support-for-.patch new file mode 100644 index 0000000000..791c58d538 --- /dev/null +++ b/SPECS/linux-lts/0492-FROMLIST-riscv-dts-spacemit-k3-Add-QSPI-support-for-.patch @@ -0,0 +1,152 @@ +From 73238d89a2b005bcbf2fa0eef726acd61a0962cd Mon Sep 17 00:00:00 2001 +From: Zhengyu He +Date: Sat, 11 Jul 2026 09:38:52 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add QSPI support for + Pico-ITX board + +Enable QSPI with proper pinmux on the Pico-ITX board, and describe the +NOR flash wired to it. + +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Cody Kang +Signed-off-by: Zhengyu He +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 56 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 ++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ + 3 files changed, 94 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index b89c1521e664..fd2b154f275a 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -200,6 +200,62 @@ phy0: phy@1 { + }; + }; + ++&qspi_cfg { ++ qspi-pins { ++ power-source = <1800>; ++ }; ++ ++ qspi-cs0-pins { ++ power-source = <1800>; ++ }; ++}; ++ ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x20000>; ++ }; ++ ++ fsbl@20000 { ++ reg = <0x20000 0x80000>; ++ }; ++ ++ env@a0000 { ++ reg = <0xa0000 0x10000>; ++ }; ++ ++ esos@b0000 { ++ reg = <0xb0000 0x100000>; ++ }; ++ ++ opensbi@1b0000 { ++ reg = <0x1b0000 0x60000>; ++ }; ++ ++ uboot@210000 { ++ reg = <0x210000 0x5f0000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 3ee1471f3798..846d5e8cc783 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -679,6 +679,27 @@ pwm19-2-pins { + }; + }; + ++ /omit-if-no-ref/ ++ qspi_cfg: qspi-cfg { ++ qspi-pins { ++ pinmux = , /* qspi dat0 */ ++ , /* qspi dat1 */ ++ , /* qspi dat2 */ ++ , /* qspi dat3 */ ++ ; /* qspi clk */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ }; ++ ++ qspi-cs0-pins { ++ pinmux = ; /* qspi cs0 */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 19fc9b49668e..9a49dd8032bf 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1099,6 +1099,23 @@ pll: clock-controller@d4090000 { + #clock-cells = <1>; + }; + ++ qspi: spi@d420c000 { ++ compatible = "spacemit,k3-qspi", ++ "spacemit,k1-qspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0xd420c000 0x0 0x1000>, ++ <0x0 0xb8000000 0x0 0xc00000>; ++ reg-names = "QuadSPI", "QuadSPI-memory"; ++ clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, ++ <&syscon_apmu CLK_APMU_QSPI>; ++ clock-names = "qspi_en", "qspi"; ++ resets = <&syscon_apmu RESET_APMU_QSPI>, ++ <&syscon_apmu RESET_APMU_QSPI_BUS>; ++ interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0493-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0493-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..4a4aae87e2 --- /dev/null +++ b/SPECS/linux-lts/0493-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,35 @@ +From 507ebca60d2727433d5db92f854fa3e28688b729 Mon Sep 17 00:00:00 2001 +From: Jennifer Berringer +Date: Wed, 20 May 2026 07:11:50 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + OrangePi RV2 + +Set the baud rate to 115200, matching what is used by U-Boot on this +platform so that the console is usable even when console options are not +specified in cmdline. + +Fixes: bab8dea259100 ("riscv: dts: spacemit: Add OrangePi RV2 board device tree") +Signed-off-by: Jennifer Berringer +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260520111150.3300707-1-jberring@redhat.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 7c49bce427f3..07dbd292eee3 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -22,7 +22,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + pcie_vcc3v3: regulator-pcie-vcc3v3 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0494-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux-lts/0494-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch new file mode 100644 index 0000000000..55e80852a8 --- /dev/null +++ b/SPECS/linux-lts/0494-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch @@ -0,0 +1,75 @@ +From e89f6522eb0ab0e4bab06940c306db21bd715065 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 2 Jun 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi + R2S + +Enable the two RTL8125 network controllers and corresponding +PHYs connected via the PCIe controllers on the OrangePi R2S. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index b13a8d6a2670..919e5b451109 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -23,6 +23,14 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; +@@ -228,6 +236,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0495-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-cpu-sc.patch b/SPECS/linux-lts/0495-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-cpu-sc.patch new file mode 100644 index 0000000000..361f3f6f13 --- /dev/null +++ b/SPECS/linux-lts/0495-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-cpu-sc.patch @@ -0,0 +1,79 @@ +From 87828fa45efba06d39fec25170189b42e8678691 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Sun, 14 Jun 2026 14:28:11 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add cpu + scaling + +Enable CPU DVFS by including the OPP table and wiring the CPU nodes to the +CPU regulator supply. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260614122812.2287506-1-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 0d809e4ad3b1..1b425011f123 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -9,6 +9,7 @@ + + #include "k1.dtsi" + #include "k1-pinctrl.dtsi" ++#include "k1-opp.dtsi" + + / { + model = "SpacemiT MusePi Pro"; +@@ -99,6 +100,38 @@ &combo_phy { + status = "okay"; + }; + ++&cpu_0 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_1 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_2 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_3 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_4 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_5 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_6 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ ++&cpu_7 { ++ cpu-supply = <&buck1_0v9>; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -178,7 +211,7 @@ pmic@41 { + dldoin2-supply = <&buck5>; + + regulators { +- buck1 { ++ buck1_0v9: buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0496-FROMLIST-riscv-dts-spacemit-k3-Enable-SD-card-suppor.patch b/SPECS/linux-lts/0496-FROMLIST-riscv-dts-spacemit-k3-Enable-SD-card-suppor.patch new file mode 100644 index 0000000000..68ec8b1206 --- /dev/null +++ b/SPECS/linux-lts/0496-FROMLIST-riscv-dts-spacemit-k3-Enable-SD-card-suppor.patch @@ -0,0 +1,126 @@ +From 0e224d82edfb1ad6ef17f3f40dd9946fe77817dc Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 10 Jun 2026 12:34:32 +0000 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Enable SD card + support + +Add the device tree node of SDHCI-0 controller which found on CoM260-IFX +board, it's currenty used for Micro SD card slot, and one GPIO pin is +configured as card insertion/removal detection pin, the slot use 4-bit +data bus, and up support to SDR104 speed mode. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260610-07-k3-enable-sd-v1-1-196ae29bd091@kernel.org +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 18 ++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 44 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 13 ++++++ + 3 files changed, 75 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +index 238bb03d0e9e..e7f76cd24b90 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -19,3 +19,21 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default","uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K3_GPIO(4) GPIO_ACTIVE_HIGH>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&aldo4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 846d5e8cc783..ee53ab2e7267 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -710,4 +710,48 @@ uart0-0-pins { + drive-strength = <25>; + }; + }; ++ ++ mmc1_cfg: mmc1-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1 dat3 */ ++ , /* mmc1 dat2 */ ++ , /* mmc1 dat1 */ ++ , /* mmc1 dat0 */ ++ ; /* mmc1 cmd */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ power-source = <3300>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1 clk */ ++ ++ bias-pull-down; ++ drive-strength = <25>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ mmc1_uhs_cfg: mmc1-uhs-cfg { ++ mmc1-uhs-data-cmd-pins { ++ pinmux = , /* mmc1 dat3 */ ++ , /* mmc1 dat2 */ ++ , /* mmc1 dat1 */ ++ , /* mmc1 dat0 */ ++ ; /* mmc1 cmd */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ power-source = <1800>; ++ }; ++ ++ mmc1-uhs-clk-pins { ++ pinmux = ; /* mmc1 clk */ ++ ++ bias-pull-down; ++ drive-strength = <21>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 9a49dd8032bf..fc46e34465e4 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1116,6 +1116,19 @@ qspi: spi@d420c000 { + status = "disabled"; + }; + ++ sdhci0: mmc@d4280000 { ++ compatible = "spacemit,k3-sdhci"; ++ reg = <0x0 0xd4280000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_SDH_AXI>, ++ <&syscon_apmu CLK_APMU_SDH0>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_APMU_SDH_AXI>, ++ <&syscon_apmu RESET_APMU_SDH0>; ++ reset-names = "axi", "sdh"; ++ interrupts = <99 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0497-FROMLIST-ACPI-tables-Add-missing-include-asm-fixmap..patch b/SPECS/linux-lts/0497-FROMLIST-ACPI-tables-Add-missing-include-asm-fixmap..patch new file mode 100644 index 0000000000..63da94638c --- /dev/null +++ b/SPECS/linux-lts/0497-FROMLIST-ACPI-tables-Add-missing-include-asm-fixmap..patch @@ -0,0 +1,33 @@ +From ecc87e849e81a2541048869d3c89f519e46ebe40 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 16 Jun 2026 21:51:31 +0800 +Subject: [RUYI PATCH] FROMLIST: ACPI: tables: Add missing #include + + +drivers/acpi/tables.c uses NR_FIX_BTMAPS without including +. This isn't a problem for existing archs, but would be +when ARCH_HAS_ACPI_TABLE_UPGRADE is enabled for RISC-V. Add the missing +include. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260616-riscv-acpi-table-upgrade-v1-1-45902d2dedf9@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/acpi/tables.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c +index 57fc8bc56166..c127da7fa32a 100644 +--- a/drivers/acpi/tables.c ++++ b/drivers/acpi/tables.c +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + #include "internal.h" + + #ifdef CONFIG_ACPI_CUSTOM_DSDT +-- +2.53.0 + diff --git a/SPECS/linux-lts/0498-FROMLIST-riscv-acpi-Enable-ARCH_HAS_ACPI_TABLE_UPGRA.patch b/SPECS/linux-lts/0498-FROMLIST-riscv-acpi-Enable-ARCH_HAS_ACPI_TABLE_UPGRA.patch new file mode 100644 index 0000000000..2a443a53d1 --- /dev/null +++ b/SPECS/linux-lts/0498-FROMLIST-riscv-acpi-Enable-ARCH_HAS_ACPI_TABLE_UPGRA.patch @@ -0,0 +1,75 @@ +From 8b2fd77b8c90c505e59b00a3437419a7b0a81dd2 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 16 Jun 2026 21:51:32 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: acpi: Enable + ARCH_HAS_ACPI_TABLE_UPGRADE + +Implement the various required hooks and enable +ARCH_HAS_ACPI_TABLE_UPGRADE to allow use for ACPI_TABLE_UPGRADE, which +is useful for debugging ACPI table problems. + +The implementation is based on arm64's of the same feature due to the +similarities of the requirements of the two platforms. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260616-riscv-acpi-table-upgrade-v1-2-45902d2dedf9@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 1 + + arch/riscv/include/asm/acpi.h | 2 ++ + arch/riscv/kernel/acpi.c | 5 +++++ + arch/riscv/kernel/setup.c | 2 ++ + 4 files changed, 10 insertions(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 36112b662884..afdd6f6a05f6 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -24,6 +24,7 @@ config RISCV + select ARCH_ENABLE_MEMORY_HOTREMOVE if MEMORY_HOTPLUG + select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 + select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE ++ select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI + select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CC_CAN_LINK + select ARCH_HAS_CURRENT_STACK_POINTER +diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h +index 6e13695120bc..b0c1f2669335 100644 +--- a/arch/riscv/include/asm/acpi.h ++++ b/arch/riscv/include/asm/acpi.h +@@ -96,4 +96,6 @@ void acpi_map_cpus_to_nodes(void); + static inline void acpi_map_cpus_to_nodes(void) { } + #endif /* CONFIG_ACPI_NUMA */ + ++#define ACPI_TABLE_UPGRADE_MAX_PHYS MEMBLOCK_ALLOC_ACCESSIBLE ++ + #endif /*_ASM_ACPI_H*/ +diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c +index ff681db9f4f1..a9b1d50b0bdd 100644 +--- a/arch/riscv/kernel/acpi.c ++++ b/arch/riscv/kernel/acpi.c +@@ -337,3 +337,8 @@ int raw_pci_write(unsigned int domain, unsigned int bus, + } + + #endif /* CONFIG_PCI */ ++ ++void __init arch_reserve_mem_area(acpi_physical_address addr, size_t size) ++{ ++ memblock_mark_nomap(addr, size); ++} +diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c +index 13b27a078912..36812b984395 100644 +--- a/arch/riscv/kernel/setup.c ++++ b/arch/riscv/kernel/setup.c +@@ -325,6 +325,8 @@ void __init setup_arch(char **cmdline_p) + efi_init(); + paging_init(); + ++ acpi_table_upgrade(); ++ + /* Parse the ACPI tables for possible boot-time configuration */ + acpi_boot_table_init(); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0499-FROMLIST-RISC-V-Add-common-csr_read_num-and-csr_writ.patch b/SPECS/linux-lts/0499-FROMLIST-RISC-V-Add-common-csr_read_num-and-csr_writ.patch new file mode 100644 index 0000000000..78ed4b6bb2 --- /dev/null +++ b/SPECS/linux-lts/0499-FROMLIST-RISC-V-Add-common-csr_read_num-and-csr_writ.patch @@ -0,0 +1,349 @@ +From 86bb04caa022348523df07728b024482dc38554e Mon Sep 17 00:00:00 2001 +From: Anup Patel +Date: Wed, 4 Feb 2026 21:23:09 +0530 +Subject: [RUYI PATCH] FROMLIST: RISC-V: Add common csr_read_num() and + csr_write_num() functions + +In RISC-V, there is no CSR read/write instruction which takes CSR +number via register so add common csr_read_num() and csr_write_num() +functions which allow accessing certain CSRs by passing CSR number +as parameter. These common functions will be first used by the +ACPI CPPC driver and RISC-V PMU driver. + +Also, the RISC-V ACPI FFH specification allows arbitrary CSR number +as CPPC register and the RISC-V SBI specification allows arbitrary +CSR number as PMU hardware counter. This means ACPI CPPC driver and +RISC-V PMU driver no longer need to do sanity checks on CSR number +which are now done by the common csr_read_num() and csr_write_num() +functions. + +Signed-off-by: Anup Patel +Reviewed-by: Sunil V L +Reviewed-by: Andrew Jones +Reviewed-by: Atish Patra +Reviewed-by: Nutty Liu +Link: https://lore.kernel.org/r/20260204155309.763597-2-anup.patel@oss.qualcomm.com +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/csr.h | 3 + + arch/riscv/kernel/Makefile | 1 + + arch/riscv/kernel/csr.c | 165 +++++++++++++++++++++++++++++++++++ + drivers/acpi/riscv/cppc.c | 17 ++-- + drivers/perf/riscv_pmu.c | 54 ++---------- + 5 files changed, 184 insertions(+), 56 deletions(-) + create mode 100644 arch/riscv/kernel/csr.c + +diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h +index 4a37a98398ad..543a3364f11d 100644 +--- a/arch/riscv/include/asm/csr.h ++++ b/arch/riscv/include/asm/csr.h +@@ -575,6 +575,9 @@ + : "memory"); \ + }) + ++unsigned long csr_read_num(unsigned long csr_num, int *out_err); ++void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err); ++ + #endif /* __ASSEMBLER__ */ + + #endif /* _ASM_RISCV_CSR_H */ +diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile +index a01f6439d62b..0b9008a6f4e0 100644 +--- a/arch/riscv/kernel/Makefile ++++ b/arch/riscv/kernel/Makefile +@@ -51,6 +51,7 @@ obj-y += soc.o + obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o + obj-y += cpu.o + obj-y += cpufeature.o ++obj-y += csr.o + obj-y += entry.o + obj-y += irq.o + obj-y += process.o +diff --git a/arch/riscv/kernel/csr.c b/arch/riscv/kernel/csr.c +new file mode 100644 +index 000000000000..e96b129c1a99 +--- /dev/null ++++ b/arch/riscv/kernel/csr.c +@@ -0,0 +1,165 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2025 Ventana Micro Systems Inc. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define CSR_CUSTOM0_U_RW_BASE 0x800 ++#define CSR_CUSTOM0_U_RW_COUNT 0x100 ++ ++#define CSR_CUSTOM1_U_RO_BASE 0xCC0 ++#define CSR_CUSTOM1_U_RO_COUNT 0x040 ++ ++#define CSR_CUSTOM2_S_RW_BASE 0x5C0 ++#define CSR_CUSTOM2_S_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM3_S_RW_BASE 0x9C0 ++#define CSR_CUSTOM3_S_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM4_S_RO_BASE 0xDC0 ++#define CSR_CUSTOM4_S_RO_COUNT 0x040 ++ ++#define CSR_CUSTOM5_HS_RW_BASE 0x6C0 ++#define CSR_CUSTOM5_HS_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM6_HS_RW_BASE 0xAC0 ++#define CSR_CUSTOM6_HS_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM7_HS_RO_BASE 0xEC0 ++#define CSR_CUSTOM7_HS_RO_COUNT 0x040 ++ ++#define CSR_CUSTOM8_M_RW_BASE 0x7C0 ++#define CSR_CUSTOM8_M_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM9_M_RW_BASE 0xBC0 ++#define CSR_CUSTOM9_M_RW_COUNT 0x040 ++ ++#define CSR_CUSTOM10_M_RO_BASE 0xFC0 ++#define CSR_CUSTOM10_M_RO_COUNT 0x040 ++ ++unsigned long csr_read_num(unsigned long csr_num, int *out_err) ++{ ++#define switchcase_csr_read(__csr_num) \ ++ case (__csr_num): \ ++ return csr_read(__csr_num) ++#define switchcase_csr_read_2(__csr_num) \ ++ switchcase_csr_read(__csr_num + 0); \ ++ switchcase_csr_read(__csr_num + 1) ++#define switchcase_csr_read_4(__csr_num) \ ++ switchcase_csr_read_2(__csr_num + 0); \ ++ switchcase_csr_read_2(__csr_num + 2) ++#define switchcase_csr_read_8(__csr_num) \ ++ switchcase_csr_read_4(__csr_num + 0); \ ++ switchcase_csr_read_4(__csr_num + 4) ++#define switchcase_csr_read_16(__csr_num) \ ++ switchcase_csr_read_8(__csr_num + 0); \ ++ switchcase_csr_read_8(__csr_num + 8) ++#define switchcase_csr_read_32(__csr_num) \ ++ switchcase_csr_read_16(__csr_num + 0); \ ++ switchcase_csr_read_16(__csr_num + 16) ++#define switchcase_csr_read_64(__csr_num) \ ++ switchcase_csr_read_32(__csr_num + 0); \ ++ switchcase_csr_read_32(__csr_num + 32) ++#define switchcase_csr_read_128(__csr_num) \ ++ switchcase_csr_read_64(__csr_num + 0); \ ++ switchcase_csr_read_64(__csr_num + 64) ++#define switchcase_csr_read_256(__csr_num) \ ++ switchcase_csr_read_128(__csr_num + 0); \ ++ switchcase_csr_read_128(__csr_num + 128) ++ ++ *out_err = 0; ++ switch (csr_num) { ++ switchcase_csr_read_32(CSR_CYCLE); ++ switchcase_csr_read_32(CSR_CYCLEH); ++ switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE); ++#ifdef CONFIG_RISCV_M_MODE ++ switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE); ++ switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE); ++#endif ++ default: ++ *out_err = -EINVAL; ++ break; ++ } ++ ++ return 0; ++#undef switchcase_csr_read_256 ++#undef switchcase_csr_read_128 ++#undef switchcase_csr_read_64 ++#undef switchcase_csr_read_32 ++#undef switchcase_csr_read_16 ++#undef switchcase_csr_read_8 ++#undef switchcase_csr_read_4 ++#undef switchcase_csr_read_2 ++#undef switchcase_csr_read ++} ++EXPORT_SYMBOL_GPL(csr_read_num); ++ ++void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err) ++{ ++#define switchcase_csr_write(__csr_num, __val) \ ++ case (__csr_num): \ ++ csr_write(__csr_num, __val); \ ++ break ++#define switchcase_csr_write_2(__csr_num, __val) \ ++ switchcase_csr_write(__csr_num + 0, __val); \ ++ switchcase_csr_write(__csr_num + 1, __val) ++#define switchcase_csr_write_4(__csr_num, __val) \ ++ switchcase_csr_write_2(__csr_num + 0, __val); \ ++ switchcase_csr_write_2(__csr_num + 2, __val) ++#define switchcase_csr_write_8(__csr_num, __val) \ ++ switchcase_csr_write_4(__csr_num + 0, __val); \ ++ switchcase_csr_write_4(__csr_num + 4, __val) ++#define switchcase_csr_write_16(__csr_num, __val) \ ++ switchcase_csr_write_8(__csr_num + 0, __val); \ ++ switchcase_csr_write_8(__csr_num + 8, __val) ++#define switchcase_csr_write_32(__csr_num, __val) \ ++ switchcase_csr_write_16(__csr_num + 0, __val); \ ++ switchcase_csr_write_16(__csr_num + 16, __val) ++#define switchcase_csr_write_64(__csr_num, __val) \ ++ switchcase_csr_write_32(__csr_num + 0, __val); \ ++ switchcase_csr_write_32(__csr_num + 32, __val) ++#define switchcase_csr_write_128(__csr_num, __val) \ ++ switchcase_csr_write_64(__csr_num + 0, __val); \ ++ switchcase_csr_write_64(__csr_num + 64, __val) ++#define switchcase_csr_write_256(__csr_num, __val) \ ++ switchcase_csr_write_128(__csr_num + 0, __val); \ ++ switchcase_csr_write_128(__csr_num + 128, __val) ++ ++ *out_err = 0; ++ switch (csr_num) { ++ switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val); ++#ifdef CONFIG_RISCV_M_MODE ++ switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val); ++ switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val); ++#endif ++ default: ++ *out_err = -EINVAL; ++ break; ++ } ++#undef switchcase_csr_write_256 ++#undef switchcase_csr_write_128 ++#undef switchcase_csr_write_64 ++#undef switchcase_csr_write_32 ++#undef switchcase_csr_write_16 ++#undef switchcase_csr_write_8 ++#undef switchcase_csr_write_4 ++#undef switchcase_csr_write_2 ++#undef switchcase_csr_write ++} ++EXPORT_SYMBOL_GPL(csr_write_num); +diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c +index 42c1a9052470..fe491937ed25 100644 +--- a/drivers/acpi/riscv/cppc.c ++++ b/drivers/acpi/riscv/cppc.c +@@ -65,24 +65,19 @@ static void sbi_cppc_write(void *write_data) + static void cppc_ffh_csr_read(void *read_data) + { + struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data; ++ int err; + +- switch (data->reg) { +- /* Support only TIME CSR for now */ +- case CSR_TIME: +- data->ret.value = csr_read(CSR_TIME); +- data->ret.error = 0; +- break; +- default: +- data->ret.error = -EINVAL; +- break; +- } ++ data->ret.value = csr_read_num(data->reg, &err); ++ data->ret.error = err; + } + + static void cppc_ffh_csr_write(void *write_data) + { + struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data; ++ int err; + +- data->ret.error = -EINVAL; ++ csr_write_num(data->reg, data->val, &err); ++ data->ret.error = err; + } + + /* +diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c +index 7644147d50b4..b41f353ba964 100644 +--- a/drivers/perf/riscv_pmu.c ++++ b/drivers/perf/riscv_pmu.c +@@ -16,6 +16,7 @@ + #include + #include + ++#include + #include + + static bool riscv_perf_user_access(struct perf_event *event) +@@ -88,58 +89,21 @@ void arch_perf_update_userpage(struct perf_event *event, + userpg->cap_user_time_short = 1; + } + +-static unsigned long csr_read_num(int csr_num) +-{ +-#define switchcase_csr_read(__csr_num, __val) {\ +- case __csr_num: \ +- __val = csr_read(__csr_num); \ +- break; } +-#define switchcase_csr_read_2(__csr_num, __val) {\ +- switchcase_csr_read(__csr_num + 0, __val) \ +- switchcase_csr_read(__csr_num + 1, __val)} +-#define switchcase_csr_read_4(__csr_num, __val) {\ +- switchcase_csr_read_2(__csr_num + 0, __val) \ +- switchcase_csr_read_2(__csr_num + 2, __val)} +-#define switchcase_csr_read_8(__csr_num, __val) {\ +- switchcase_csr_read_4(__csr_num + 0, __val) \ +- switchcase_csr_read_4(__csr_num + 4, __val)} +-#define switchcase_csr_read_16(__csr_num, __val) {\ +- switchcase_csr_read_8(__csr_num + 0, __val) \ +- switchcase_csr_read_8(__csr_num + 8, __val)} +-#define switchcase_csr_read_32(__csr_num, __val) {\ +- switchcase_csr_read_16(__csr_num + 0, __val) \ +- switchcase_csr_read_16(__csr_num + 16, __val)} +- +- unsigned long ret = 0; +- +- switch (csr_num) { +- switchcase_csr_read_32(CSR_CYCLE, ret) +- switchcase_csr_read_32(CSR_CYCLEH, ret) +- default : +- break; +- } +- +- return ret; +-#undef switchcase_csr_read_32 +-#undef switchcase_csr_read_16 +-#undef switchcase_csr_read_8 +-#undef switchcase_csr_read_4 +-#undef switchcase_csr_read_2 +-#undef switchcase_csr_read +-} +- + /* + * Read the CSR of a corresponding counter. + */ + unsigned long riscv_pmu_ctr_read_csr(unsigned long csr) + { +- if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H || +- (csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) { +- pr_err("Invalid performance counter csr %lx\n", csr); +- return -EINVAL; ++ unsigned long val; ++ int rc; ++ ++ val = csr_read_num(csr, &rc); ++ if (rc) { ++ pr_err("Failed to read performance counter csr %lx (error %d)\n", csr, rc); ++ return rc; + } + +- return csr_read_num(csr); ++ return val; + } + + u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0500-FROMLIST-ACPI-RISC-V-Fix-false-warning-in-cppc_read_.patch b/SPECS/linux-lts/0500-FROMLIST-ACPI-RISC-V-Fix-false-warning-in-cppc_read_.patch new file mode 100644 index 0000000000..3e85fd102d --- /dev/null +++ b/SPECS/linux-lts/0500-FROMLIST-ACPI-RISC-V-Fix-false-warning-in-cppc_read_.patch @@ -0,0 +1,70 @@ +From be85392e7c5d19687473ddf28227aa6780bec969 Mon Sep 17 00:00:00 2001 +From: Wang Yechao +Date: Tue, 9 Jun 2026 19:28:56 +0800 +Subject: [RUYI PATCH] FROMLIST: ACPI: RISC-V: Fix false warning in + cppc_read_ffh() for same-CPU reads + +Commit 997c021abc6e ("cpufreq: CPPC: Update FIE arch_freq_scale in +ticks for non-PCC regs") changed the CPPC Frequency Invariance Engine +to read AMU counters directly from the scheduler tick for non-PCC +register spaces (like FFH), instead of deferring to a kthread. This +means cppc_read_ffh() is now called with IRQs disabled from the tick +handler, triggering the warning. + +This is the same fix as commit df6e4ab654dc ("arm64: topology: Fix +false warning in counters_read_on_cpu() for same-CPU reads"). + +Fixes: 997c021abc6e ("cpufreq: CPPC: Update FIE arch_freq_scale in ticks for non-PCC regs") +Signed-off-by: Wang Yechao +Link: https://lore.kernel.org/r/20260609192856874Y8AaPpKL5TnmbgiWI8DI3@zte.com.cn +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/cppc.c | 19 ++++++++++++++----- + 1 file changed, 14 insertions(+), 5 deletions(-) + +diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c +index fe491937ed25..41c23db0223a 100644 +--- a/drivers/acpi/riscv/cppc.c ++++ b/drivers/acpi/riscv/cppc.c +@@ -93,16 +93,19 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val) + { + struct sbi_cppc_data data; + +- if (WARN_ON_ONCE(irqs_disabled())) +- return -EPERM; +- + if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) { + if (!cppc_ext_present) + return -EINVAL; + + data.reg = FFH_CPPC_SBI_REG(reg->address); + +- smp_call_function_single(cpu, sbi_cppc_read, &data, 1); ++ if (irqs_disabled()) { ++ if (WARN_ON_ONCE(cpu != smp_processor_id())) ++ return -EPERM; ++ sbi_cppc_read(&data); ++ } else { ++ smp_call_function_single(cpu, sbi_cppc_read, &data, 1); ++ } + + *val = data.ret.value; + +@@ -110,7 +113,13 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val) + } else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) { + data.reg = FFH_CPPC_CSR_NUM(reg->address); + +- smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1); ++ if (irqs_disabled()) { ++ if (WARN_ON_ONCE(cpu != smp_processor_id())) ++ return -EPERM; ++ cppc_ffh_csr_read(&data); ++ } else { ++ smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1); ++ } + + *val = data.ret.value; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0501-FROMLIST-riscv-unaligned-stop-using-kthread-for-chec.patch b/SPECS/linux-lts/0501-FROMLIST-riscv-unaligned-stop-using-kthread-for-chec.patch new file mode 100644 index 0000000000..4d90c36fc8 --- /dev/null +++ b/SPECS/linux-lts/0501-FROMLIST-riscv-unaligned-stop-using-kthread-for-chec.patch @@ -0,0 +1,95 @@ +From b97a141de17eb9d0d6e48338e2f159e1556ac301 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Wed, 17 Jun 2026 05:38:24 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: unaligned: stop using kthread for + check_vector_unaligned_access() + +A kthread is used to run check_vector_unaligned_access() to optimize boot +time, allowing the kernel to continue booting without waiting for the +unaligned vector speed probe to finish. + +However, this asynchronous approach introduces several complications. +First, the kthread may not complete before a user reads vDSO data, +resulting in incorrect values. This was previously addressed by +commit 5d15d2ad36b0 ("riscv: hwprobe: Fix stale vDSO data for +late-initialized keys at boot"), which added complex synchronization +between the kthread and vDSO reads. + +Second, it was discovered that the kthread may not finish before +vec_check_unaligned_access_speed_all_cpus() (marked with __init) is freed, +triggering a page fault. + +These issues raise the question of whether the kthread is worth the added +complexity. A past boot time regression report was actually unrelated to +synchronous probing; it was caused by the probe running serially. Since +switching to a parallel probe, no further complaints have been made. +Furthermore, the unaligned scalar access speed probe takes the same amount +of time, runs synchronously, and has caused no issues. + +Testing shows no noticeable boot time slowdown when running the vector +probe synchronously (0.464474s with kthread vs. 0.457991s without). + +Remove the kthread usage and run the probe synchronously. This simplifies +the boot flow and allows for the revert of commit 5d15d2ad36b0 ("riscv: +hwprobe: Fix stale vDSO data for late-initialized keys at boot") + +Reported-by: Anirudh Srinivasan +Closes: https://lore.kernel.org/linux-riscv/20260612-vec_unaligned_drop_init-v1-1-df969210ae34@oss.tenstorrent.com/ +Fixes: a00e022be531 ("riscv: Annotate unaligned access init functions") +Cc: stable@vger.kernel.org +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/1c378963f27c5960e8a57c50b8b444d30954cb54.1781666867.git.namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/kernel/unaligned_access_speed.c | 19 ++----------------- + 1 file changed, 2 insertions(+), 17 deletions(-) + +diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c +index 5e224cc48c62..e779fd703730 100644 +--- a/arch/riscv/kernel/unaligned_access_speed.c ++++ b/arch/riscv/kernel/unaligned_access_speed.c +@@ -6,7 +6,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -364,18 +363,9 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus + __free_pages(page, MISALIGNED_BUFFER_ORDER); + } + +-/* Measure unaligned access speed on all CPUs present at boot in parallel. */ +-static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +-{ +- schedule_on_each_cpu(check_vector_unaligned_access); +- riscv_hwprobe_complete_async_probe(); +- +- return 0; +-} + #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ +-static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) ++static void check_vector_unaligned_access(struct work_struct *work __always_unused) + { +- return 0; + } + #endif + +@@ -463,12 +453,7 @@ static int __init check_unaligned_access_all_cpus(void) + per_cpu(vector_misaligned_access, cpu) = unaligned_vector_speed_param; + } else if (!check_vector_unaligned_access_emulated_all_cpus() && + IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { +- riscv_hwprobe_register_async_probe(); +- if (IS_ERR(kthread_run(vec_check_unaligned_access_speed_all_cpus, +- NULL, "vec_check_unaligned_access_speed_all_cpus"))) { +- pr_warn("Failed to create vec_unalign_check kthread\n"); +- riscv_hwprobe_complete_async_probe(); +- } ++ schedule_on_each_cpu(check_vector_unaligned_access); + } + + /* +-- +2.53.0 + diff --git a/SPECS/linux-lts/0502-FROMLIST-Revert-riscv-hwprobe-Fix-stale-vDSO-data-fo.patch b/SPECS/linux-lts/0502-FROMLIST-Revert-riscv-hwprobe-Fix-stale-vDSO-data-fo.patch new file mode 100644 index 0000000000..ec92abed56 --- /dev/null +++ b/SPECS/linux-lts/0502-FROMLIST-Revert-riscv-hwprobe-Fix-stale-vDSO-data-fo.patch @@ -0,0 +1,182 @@ +From e4de9fc60f2d44feef3bf2f2e15fda93f6da4ab7 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Wed, 17 Jun 2026 05:38:25 +0200 +Subject: [RUYI PATCH] FROMLIST: Revert "riscv: hwprobe: Fix stale vDSO data + for late-initialized keys at boot" + +This reverts commit 5d15d2ad36b0 ("riscv: hwprobe: Fix stale vDSO data for +late-initialized keys at boot"). The commit ensures synchronization between +the unaligned vector access speed probe kthread and vDSO data read. But now +that the kthread has been removed, this commit can be reverted. + +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/50ca78a649faf53f8941bc94c9cf8268b3644d38.1781666867.git.namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/hwprobe.h | 7 --- + arch/riscv/include/asm/vdso/arch_data.h | 6 --- + arch/riscv/kernel/sys_hwprobe.c | 70 +++++-------------------- + arch/riscv/kernel/vdso/hwprobe.c | 2 +- + 4 files changed, 13 insertions(+), 72 deletions(-) + +diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h +index 58f8dda73259..948d2b34e94e 100644 +--- a/arch/riscv/include/asm/hwprobe.h ++++ b/arch/riscv/include/asm/hwprobe.h +@@ -42,11 +42,4 @@ static inline bool riscv_hwprobe_pair_cmp(struct riscv_hwprobe *pair, + return pair->value == other_pair->value; + } + +-#ifdef CONFIG_MMU +-void riscv_hwprobe_register_async_probe(void); +-void riscv_hwprobe_complete_async_probe(void); +-#else +-static inline void riscv_hwprobe_register_async_probe(void) {} +-static inline void riscv_hwprobe_complete_async_probe(void) {} +-#endif + #endif +diff --git a/arch/riscv/include/asm/vdso/arch_data.h b/arch/riscv/include/asm/vdso/arch_data.h +index 88b37af55175..da57a3786f7a 100644 +--- a/arch/riscv/include/asm/vdso/arch_data.h ++++ b/arch/riscv/include/asm/vdso/arch_data.h +@@ -12,12 +12,6 @@ struct vdso_arch_data { + + /* Boolean indicating all CPUs have the same static hwprobe values. */ + __u8 homogeneous_cpus; +- +- /* +- * A gate to check and see if the hwprobe data is actually ready, as +- * probing is deferred to avoid boot slowdowns. +- */ +- __u8 ready; + }; + + #endif /* __RISCV_ASM_VDSO_ARCH_DATA_H */ +diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c +index 199d13f86f31..ded80da10678 100644 +--- a/arch/riscv/kernel/sys_hwprobe.c ++++ b/arch/riscv/kernel/sys_hwprobe.c +@@ -5,9 +5,6 @@ + * more details. + */ + #include +-#include +-#include +-#include + #include + #include + #include +@@ -463,32 +460,28 @@ static int hwprobe_get_cpus(struct riscv_hwprobe __user *pairs, + return 0; + } + +-#ifdef CONFIG_MMU +- +-static DECLARE_COMPLETION(boot_probes_done); +-static atomic_t pending_boot_probes = ATOMIC_INIT(1); +- +-void riscv_hwprobe_register_async_probe(void) ++static int do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, ++ size_t pair_count, size_t cpusetsize, ++ unsigned long __user *cpus_user, ++ unsigned int flags) + { +- atomic_inc(&pending_boot_probes); +-} ++ if (flags & RISCV_HWPROBE_WHICH_CPUS) ++ return hwprobe_get_cpus(pairs, pair_count, cpusetsize, ++ cpus_user, flags); + +-void riscv_hwprobe_complete_async_probe(void) +-{ +- if (atomic_dec_and_test(&pending_boot_probes)) +- complete(&boot_probes_done); ++ return hwprobe_get_values(pairs, pair_count, cpusetsize, ++ cpus_user, flags); + } + +-static int complete_hwprobe_vdso_data(void) ++#ifdef CONFIG_MMU ++ ++static int __init init_hwprobe_vdso_data(void) + { + struct vdso_arch_data *avd = vdso_k_arch_data; + u64 id_bitsmash = 0; + struct riscv_hwprobe pair; + int key; + +- if (unlikely(!atomic_dec_and_test(&pending_boot_probes))) +- wait_for_completion(&boot_probes_done); +- + /* + * Initialize vDSO data with the answers for the "all CPUs" case, to + * save a syscall in the common case. +@@ -516,52 +509,13 @@ static int complete_hwprobe_vdso_data(void) + * vDSO should defer to the kernel for exotic cpu masks. + */ + avd->homogeneous_cpus = id_bitsmash != 0 && id_bitsmash != -1; +- +- /* +- * Make sure all the VDSO values are visible before we look at them. +- * This pairs with the implicit "no speculativly visible accesses" +- * barrier in the VDSO hwprobe code. +- */ +- smp_wmb(); +- avd->ready = true; +- return 0; +-} +- +-static int __init init_hwprobe_vdso_data(void) +-{ +- struct vdso_arch_data *avd = vdso_k_arch_data; +- +- /* +- * Prevent the vDSO cached values from being used, as they're not ready +- * yet. +- */ +- avd->ready = false; + return 0; + } + + arch_initcall_sync(init_hwprobe_vdso_data); + +-#else +- +-static int complete_hwprobe_vdso_data(void) { return 0; } +- + #endif /* CONFIG_MMU */ + +-static int do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, +- size_t pair_count, size_t cpusetsize, +- unsigned long __user *cpus_user, +- unsigned int flags) +-{ +- DO_ONCE_SLEEPABLE(complete_hwprobe_vdso_data); +- +- if (flags & RISCV_HWPROBE_WHICH_CPUS) +- return hwprobe_get_cpus(pairs, pair_count, cpusetsize, +- cpus_user, flags); +- +- return hwprobe_get_values(pairs, pair_count, cpusetsize, +- cpus_user, flags); +-} +- + SYSCALL_DEFINE5(riscv_hwprobe, struct riscv_hwprobe __user *, pairs, + size_t, pair_count, size_t, cpusetsize, unsigned long __user *, + cpus, unsigned int, flags) +diff --git a/arch/riscv/kernel/vdso/hwprobe.c b/arch/riscv/kernel/vdso/hwprobe.c +index 8f45500d0a6e..2ddeba6c68dd 100644 +--- a/arch/riscv/kernel/vdso/hwprobe.c ++++ b/arch/riscv/kernel/vdso/hwprobe.c +@@ -27,7 +27,7 @@ static int riscv_vdso_get_values(struct riscv_hwprobe *pairs, size_t pair_count, + * homogeneous, then this function can handle requests for arbitrary + * masks. + */ +- if (flags != 0 || (!all_cpus && !avd->homogeneous_cpus) || unlikely(!avd->ready)) ++ if ((flags != 0) || (!all_cpus && !avd->homogeneous_cpus)) + return riscv_hwprobe(pairs, pair_count, cpusetsize, cpus, flags); + + /* This is something we can handle, fill out the pairs. */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0503-FROMLIST-riscv-uaccess-Add-a-fast-path-for-small-ali.patch b/SPECS/linux-lts/0503-FROMLIST-riscv-uaccess-Add-a-fast-path-for-small-ali.patch new file mode 100644 index 0000000000..623bca7113 --- /dev/null +++ b/SPECS/linux-lts/0503-FROMLIST-riscv-uaccess-Add-a-fast-path-for-small-ali.patch @@ -0,0 +1,79 @@ +From e7d6a964039535c0d255b5f04106a0146360db63 Mon Sep 17 00:00:00 2001 +From: Yunhui Cui +Date: Tue, 23 Jun 2026 16:35:51 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: uaccess: Add a fast path for small + aligned copies + +The scalar user copy routine currently enters the word-copy path only +for copies of at least 9 * SZREG - 1 bytes. On RV64 this is 71 bytes, +so common 32-byte and 64-byte aligned user/kernel copies fall back to +byte-by-byte copying. + +Add a small-copy word path for copies below that threshold when both +source and destination are SZREG-aligned. Unaligned and sub-word copies +keep using the existing byte-copy path, and larger copies keep using the +existing large-copy paths. + +This is a generic usercopy improvement. One common case is Linux AIO: +io_getevents() copies 32-byte struct io_event objects to userspace, and +io_submit() copies 64-byte struct iocb objects from userspace. + +fio libaio randrw three-run averages improved: + + baseline: read 560k IOPS, write 240k IOPS, sys 68.60% + this patch: read 593k IOPS, write 254k IOPS, sys 69.03% + +This is about +5.8% read IOPS and +5.5% write IOPS. + +lmbench bw_pipe with small messages was also improved: + + bw_pipe -m -M 16m -W 1 -N 5 + + size baseline MB/s this patch MB/s change + 32 62.52 74.54 +19.2% + 64 122.57 155.31 +26.7% + +Signed-off-by: Yunhui Cui +Link: https://lore.kernel.org/r/20260623083551.86021-1-cuiyunhui@bytedance.com +Signed-off-by: Han Gao +--- + arch/riscv/lib/uaccess.S | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S +index 4efea1b3326c..2d78007f10d0 100644 +--- a/arch/riscv/lib/uaccess.S ++++ b/arch/riscv/lib/uaccess.S +@@ -70,12 +70,27 @@ SYM_FUNC_START(fallback_scalar_usercopy_sum_enabled) + add t0, a0, a2 + + /* +- * Use byte copy only if too small. +- * SZREG holds 4 for RV32 and 8 for RV64 ++ * For small copies below the large-copy threshold, use word-copy if ++ * both src and dst are naturally aligned. Unaligned or sub-word copies ++ * are left to the byte-copy tail. + */ + li a3, 9*SZREG-1 /* size must >= (word_copy stride + SZREG-1) */ ++ bgeu a2, a3, .Llarge_copy_user ++ li a3, SZREG + bltu a2, a3, .Lbyte_copy_tail ++ or a3, a0, a1 ++ andi a3, a3, SZREG-1 ++ bnez a3, .Lbyte_copy_tail ++ andi t1, t0, ~(SZREG-1) ++5: ++ fixup REG_L a5, 0(a1), 10f ++ addi a1, a1, SZREG ++ fixup REG_S a5, 0(a0), 10f ++ addi a0, a0, SZREG ++ bltu a0, t1, 5b ++ j .Lbyte_copy_tail + ++.Llarge_copy_user: + /* + * Copy first bytes until dst is aligned to word boundary. + * a0 - start of dst +-- +2.53.0 + diff --git a/SPECS/linux-lts/0504-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0504-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..82dfdd5e6e --- /dev/null +++ b/SPECS/linux-lts/0504-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,35 @@ +From 10909b4ca532268892e712654aa65d5c1a32d141 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:45 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + K3 Pico-ITX board + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +Fixes: 7a6131804986 ("riscv: dts: spacemit: add K3 Pico-ITX board support") +Signed-off-by: Aurelien Jarno +Reviewed-by: Guodong Xu +Link: https://lore.kernel.org/r/20260623204431.498700-2-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index fd2b154f275a..7f2236104490 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -18,7 +18,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + memory@100000000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0505-FROMLIST-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch b/SPECS/linux-lts/0505-FROMLIST-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch new file mode 100644 index 0000000000..9f96a9df66 --- /dev/null +++ b/SPECS/linux-lts/0505-FROMLIST-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch @@ -0,0 +1,59 @@ +From 56ea79d330bdf3403632db83e4d2c9e97502472b Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:46 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable the i2c2 adapter + on K3 Pico-ITX board + +Define I2C2 pinctrl properties, and enable it on the K3 Pico-ITX board. +It will be used by the 24c02 eeprom. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-3-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 6 ++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 +++++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 7f2236104490..20848a5d2f9c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -43,6 +43,12 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + }; + }; + ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_1_cfg>; ++ status = "okay"; ++}; ++ + &i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index ee53ab2e7267..5b9045e01434 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -78,6 +78,17 @@ gmac1-phy-0-pins { + }; + }; + ++ /omit-if-no-ref/ ++ i2c2_1_cfg: i2c2-1-cfg { ++ i2c2-1-pins { ++ pinmux = , /* i2c2 scl */ ++ ; /* i2c2 sda */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0506-FROMLIST-riscv-dts-spacemit-add-24c02-eeprom-on-K3-P.patch b/SPECS/linux-lts/0506-FROMLIST-riscv-dts-spacemit-add-24c02-eeprom-on-K3-P.patch new file mode 100644 index 0000000000..2e935a2df0 --- /dev/null +++ b/SPECS/linux-lts/0506-FROMLIST-riscv-dts-spacemit-add-24c02-eeprom-on-K3-P.patch @@ -0,0 +1,65 @@ +From af4a9c8c6fd1ae4bd0153f3136b839aa54e274d5 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:47 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add 24c02 eeprom on K3 + Pico-ITX board + +The K3 Pico-ITX board includes a 24c02 eeprom, that stores the product +name, the part name, the MAC address of the network interfaces and the +board's serial number. These values are also exposed via an +onie,tlv-layout nvmem layout. + +The eeprom is marked as read-only since its contents are not supposed to +be modified. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-4-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 30 ++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 20848a5d2f9c..85dd87a4381e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -47,6 +47,36 @@ &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_cfg>; + status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <8>; ++ read-only; ++ size = <256>; ++ status = "okay"; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ mac-address { ++ #nvmem-cell-cells = <1>; ++ }; ++ ++ num-macs { ++ }; ++ ++ part-number { ++ }; ++ ++ product-name { ++ }; ++ ++ serial-number { ++ }; ++ ++ }; ++ }; + }; + + &i2c8 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0507-FROMLIST-riscv-dts-spacemit-add-i2c-aliases-on-K3-Pi.patch b/SPECS/linux-lts/0507-FROMLIST-riscv-dts-spacemit-add-i2c-aliases-on-K3-Pi.patch new file mode 100644 index 0000000000..f004f94324 --- /dev/null +++ b/SPECS/linux-lts/0507-FROMLIST-riscv-dts-spacemit-add-i2c-aliases-on-K3-Pi.patch @@ -0,0 +1,33 @@ +From 843267f7efa94a4497127b96b58f4b4b7460a459 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:48 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add i2c aliases on K3 + Pico-ITX board + +Add i2c aliases for i2c2 and i2c8 on K3 Pico-ITX board. This is useful +to keep a stable number for the /dev entries after loading the i2c-dev +module. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-5-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 85dd87a4381e..a07db9853ad8 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -14,6 +14,8 @@ / { + + aliases { + ethernet0 = ð0; ++ i2c2 = &i2c2; ++ i2c8 = &i2c8; + serial0 = &uart0; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0508-FROMLIST-riscv-dts-spacemit-improve-RTL8211F-PHY-con.patch b/SPECS/linux-lts/0508-FROMLIST-riscv-dts-spacemit-improve-RTL8211F-PHY-con.patch new file mode 100644 index 0000000000..045ad597bc --- /dev/null +++ b/SPECS/linux-lts/0508-FROMLIST-riscv-dts-spacemit-improve-RTL8211F-PHY-con.patch @@ -0,0 +1,36 @@ +From 6019cef4db7227082c278bbf6663364aa65fb0e4 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:43:49 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: improve RTL8211F PHY + configuration on K3 Pico-ITX board + +Vendor kernel enabled ALDPS (Advanced Link Down Power Saving) on the +RTL8211F PHY to save power when link down. + +Vendor kernel also disabled the 125MHz clkout clock signal, and indeed +the schematics confirms that it only goes to a test point (TP14), so +let's do the same. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204431.498700-6-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index a07db9853ad8..8b2a120b02d1 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -234,6 +234,8 @@ phy0: phy@1 { + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; ++ realtek,aldps-enable; ++ realtek,clkout-disable; + }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0509-FROMLIST-arch-riscv-vdso-remove-CFI-landing-pad-from.patch b/SPECS/linux-lts/0509-FROMLIST-arch-riscv-vdso-remove-CFI-landing-pad-from.patch new file mode 100644 index 0000000000..be88a3c33d --- /dev/null +++ b/SPECS/linux-lts/0509-FROMLIST-arch-riscv-vdso-remove-CFI-landing-pad-from.patch @@ -0,0 +1,52 @@ +From 60703b7dd0916fb50ad7c9a9a07ca3a4738c1741 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 23 Jun 2026 22:40:57 +0200 +Subject: [RUYI PATCH] FROMLIST: arch/riscv: vdso: remove CFI landing pad from + rt_sigreturn + +When CONFIG_RISCV_USER_CFI is enabled, the CFI version of the vDSO, has +a CFI landing pad instruction at the start of __vdso_rt_sigreturn. This +breaks libgcc's unwinding code which matches on the first two +instructions. Other unwinders that rely on similar instruction matching +may also be affected. + +Since __vdso_rt_sigreturn is reached as part of signal-return handling +rather than via an indirect call/jump from userspace, it does not need a +CFI landing pad. Remove it and restore the instruction sequence expected +by existing unwinding code. + +This matches what was done on arm64 in commit 9a964285572b ("arm64: +vdso: Don't prefix sigreturn trampoline with a BTI C instruction") for a +similar issue. + +Fixes: 37f57bd3faea ("arch/riscv: compile vdso with landing pad and shadow stack note") +Co-authored-by: Joel Stanley +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260623204058.498120-1-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/kernel/vdso/rt_sigreturn.S | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/kernel/vdso/rt_sigreturn.S b/arch/riscv/kernel/vdso/rt_sigreturn.S +index 3dc022aa8931..43e0c1607271 100644 +--- a/arch/riscv/kernel/vdso/rt_sigreturn.S ++++ b/arch/riscv/kernel/vdso/rt_sigreturn.S +@@ -6,6 +6,14 @@ + #include + #include + ++/* WARNING: Do NOT add a CFI landing pad at the start of this function. ++ * Unwinders such as libgcc identify the sigreturn trampoline by matching the ++ * instruction sequence. Adding a landing pad here would break unwinding from ++ * signal handlers. ++ * ++ * This trampoline is used only for signal return and not via an indirect ++ * call/jump from userspace, so adding CFI landing pad is unnecessary. ++ */ + .text + SYM_FUNC_START(__vdso_rt_sigreturn) + .cfi_startproc +-- +2.53.0 + diff --git a/SPECS/linux-lts/0510-FROMLIST-dt-bindings-vendor-prefixes-add-Rongda.patch b/SPECS/linux-lts/0510-FROMLIST-dt-bindings-vendor-prefixes-add-Rongda.patch new file mode 100644 index 0000000000..b46bdc466e --- /dev/null +++ b/SPECS/linux-lts/0510-FROMLIST-dt-bindings-vendor-prefixes-add-Rongda.patch @@ -0,0 +1,33 @@ +From d6a4700e9c8a801dd4c9c247fa9416bf6bdc2ca4 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:17:57 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: vendor-prefixes: add Rongda + +Add Shenzhen Rongda Computer Co., Ltd. to the vendor prefixes. + +Link: http://www.shenrongda.com/ + +Signed-off-by: Jia Wang +Link: http://www.shenrongda.com/ +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-1-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index d03f700d178e..4ba63daade2d 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -1355,6 +1355,8 @@ patternProperties: + description: Rockchip Electronics Co., Ltd. + "^rocktech,.*": + description: ROCKTECH DISPLAYS LIMITED ++ "^rongda,.*": ++ description: Shenzhen Rongda Computer Co., Ltd. + "^rohm,.*": + description: ROHM Semiconductor Co., Ltd + "^ronbo,.*": +-- +2.53.0 + diff --git a/SPECS/linux-lts/0511-FROMLIST-dt-bindings-riscv-cpus-Add-UltraRISC-CP100-.patch b/SPECS/linux-lts/0511-FROMLIST-dt-bindings-riscv-cpus-Add-UltraRISC-CP100-.patch new file mode 100644 index 0000000000..1c4d5dbc91 --- /dev/null +++ b/SPECS/linux-lts/0511-FROMLIST-dt-bindings-riscv-cpus-Add-UltraRISC-CP100-.patch @@ -0,0 +1,33 @@ +From e1f510725851ec21d732d9546f8faa3e98c53bce Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:17:58 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: cpus: Add UltraRISC CP100 + compatible + +Update Documentation for supporting UltraRISC CP100 based CPU. + +CP100 is used in UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-2-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml +index a86819565394..3fdd3571436d 100644 +--- a/Documentation/devicetree/bindings/riscv/cpus.yaml ++++ b/Documentation/devicetree/bindings/riscv/cpus.yaml +@@ -66,6 +66,7 @@ properties: + - thead,c908 + - thead,c910 + - thead,c920 ++ - ultrarisc,cp100 + - const: riscv + - items: + - enum: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0512-FROMLIST-dt-bindings-riscv-Add-UltraRISC-DP1000-bind.patch b/SPECS/linux-lts/0512-FROMLIST-dt-bindings-riscv-Add-UltraRISC-DP1000-bind.patch new file mode 100644 index 0000000000..f1bb7708cb --- /dev/null +++ b/SPECS/linux-lts/0512-FROMLIST-dt-bindings-riscv-Add-UltraRISC-DP1000-bind.patch @@ -0,0 +1,70 @@ +From 8edb9581c7e088b0f3cbf5fa05c58a74f2c5ca6c Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:17:59 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: Add UltraRISC DP1000 + bindings + +Add DT binding documentation for the UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-3-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/ultrarisc.yaml | 27 +++++++++++++++++++ + MAINTAINERS | 6 +++++ + 2 files changed, 33 insertions(+) + create mode 100644 Documentation/devicetree/bindings/riscv/ultrarisc.yaml + +diff --git a/Documentation/devicetree/bindings/riscv/ultrarisc.yaml b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml +new file mode 100644 +index 000000000000..d4421c2ef945 +--- /dev/null ++++ b/Documentation/devicetree/bindings/riscv/ultrarisc.yaml +@@ -0,0 +1,27 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: UltraRISC SoC-based boards ++ ++maintainers: ++ - Jia Wang ++ ++description: ++ UltraRISC DP1000 SoC-based boards ++ ++properties: ++ $nodename: ++ const: '/' ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - rongda,m0 ++ - milkv,titan ++ - const: ultrarisc,dp1000 ++ ++additionalProperties: true ++... +diff --git a/MAINTAINERS b/MAINTAINERS +index a3bc23926943..968133ea82e8 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -22249,6 +22249,12 @@ F: include/dt-bindings/power/thead,th1520-power.h + F: include/dt-bindings/reset/thead,th1520-reset.h + F: include/linux/firmware/thead/thead,th1520-aon.h + ++RISC-V ULTRARISC SoC SUPPORT ++M: Jia Wang ++L: linux-riscv@lists.infradead.org ++S: Maintained ++F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml ++ + RNBD BLOCK DRIVERS + M: Md. Haris Iqbal + M: Jack Wang +-- +2.53.0 + diff --git a/SPECS/linux-lts/0513-FROMLIST-riscv-dts-ultrarisc-Add-initial-device-tree.patch b/SPECS/linux-lts/0513-FROMLIST-riscv-dts-ultrarisc-Add-initial-device-tree.patch new file mode 100644 index 0000000000..de08316483 --- /dev/null +++ b/SPECS/linux-lts/0513-FROMLIST-riscv-dts-ultrarisc-Add-initial-device-tree.patch @@ -0,0 +1,900 @@ +From 8b23e4334dc19b856bff57963fb1a51a19141823 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:01 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: ultrarisc: Add initial device tree + for UltraRISC DP1000 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add the base device tree for the UltraRISC DP1000 SoC. It describes the +8×CP100 CPU cores and essential SoC peripherals including the interrupt +controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC and the DMA +controller. + +Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/ +Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/ + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/ +Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/ +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-5-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + MAINTAINERS | 1 + + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 851 ++++++++++++++++++++++ + 2 files changed, 852 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dtsi + +diff --git a/MAINTAINERS b/MAINTAINERS +index 968133ea82e8..d774f0f29f70 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -22254,6 +22254,7 @@ M: Jia Wang + L: linux-riscv@lists.infradead.org + S: Maintained + F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml ++F: arch/riscv/boot/dts/ultrarisc/ + + RNBD BLOCK DRIVERS + M: Md. Haris Iqbal +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +new file mode 100644 +index 000000000000..1aae53fc1a2b +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -0,0 +1,851 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ compatible = "ultrarisc,dp1000"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <10000000>; ++ ++ cpu0: cpu@0 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x0>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache0>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache0: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu1: cpu@1 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x1>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache1>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu1_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache1: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu2: cpu@2 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x2>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache2>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu2_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache2: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu3: cpu@3 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x3>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache3>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu3_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache3: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; ++ }; ++ ++ cpu4: cpu@4 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x10>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache4>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu4_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache4: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ cpu5: cpu@5 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x11>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache5>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu5_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache5: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ cpu6: cpu@6 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x12>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache6>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu6_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache6: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu7: cpu@7 { ++ compatible = "ultrarisc,cp100", "riscv"; ++ reg = <0x13>; ++ device_type = "cpu"; ++ riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", ++ "zba", "zbb", "zbc", "zbs", "zicntr", ++ "zicsr", "zifencei", "zihpm", "ziccif", ++ "ziccrse", "ziccamoa", "za64rs", "zicbom", ++ "zicbop", "zicboz", "zkt", "svade", ++ "ssccptr", "sstvecd", "sscounterenw", ++ "shcounterenw", "shtvala", "shvstvecd", ++ "shvsatpa", "svvptc"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache7>; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ ++ cpu7_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <0x01>; ++ }; ++ ++ l2_cache7: l2-cache { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0: cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ }; ++ ++ cluster1: cluster1 { ++ core0 { ++ cpu = <&cpu4>; ++ }; ++ ++ core1 { ++ cpu = <&cpu5>; ++ }; ++ ++ core2 { ++ cpu = <&cpu6>; ++ }; ++ ++ core3 { ++ cpu = <&cpu7>; ++ }; ++ }; ++ }; ++ ++ cluster0_l3: l3-cache0 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ ++ cluster1_l3: l3-cache1 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; ++ ++ clocks { ++ device_clk: device_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <62500000>; ++ #clock-cells = <0>; ++ }; ++ ++ timer_clk: timer_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ #clock-cells = <0>; ++ }; ++ ++ csr_clk: csr_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <250000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ l4_cache: l4-cache { ++ /* L4 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 16MB ++ * shared by the SoC. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <4>; ++ cache-size = <0x1000000>; ++ cache-sets = <0x4000>; ++ cache-unified; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x00 0x80000000 0x4 0x00000000>; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ ranges; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ++ clint: clint@8000000 { ++ compatible = "sifive,clint0", "riscv,clint0"; ++ reg = <0x00 0x8000000 0x00 0x100000>; ++ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ }; ++ ++ plic: plic@9000000 { ++ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; ++ reg = <0x00 0x9000000 0x00 0x4000000>; ++ #interrupt-cells = <1>; ++ #address-cells = <0>; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ riscv,ndev = <160>; ++ }; ++ ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #pinctrl-cells = <2>; ++ }; ++ ++ gpio: gpio@20200000 { ++ compatible = "snps,dw-apb-gpio"; ++ reg = <0x0 0x20200000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-names = "bus", "db"; ++ clocks = <&csr_clk>, <&device_clk>; ++ ++ gpio_a: gpio-port@0 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <16>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <&plic>; ++ interrupts = <34>; ++ gpio-ranges = <&pmx0 0 0 16>; ++ }; ++ ++ gpio_b: gpio-port@1 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <1>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 16 0 8>; ++ }; ++ ++ gpio_c: gpio-port@2 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 24 0 8>; ++ }; ++ ++ gpio_d: gpio-port@3 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <3>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 32 0 8>; ++ }; ++ }; ++ ++ uart0: serial@20300000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20300000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <17>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart1: serial@20310000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20310000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <18>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart2: serial@20400000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20400000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <25>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart3: serial@20410000 { ++ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; ++ reg = <0x00 0x20410000 0x00 0x10000>; ++ interrupt-parent = <&plic>; ++ interrupts = <26>; ++ clock-frequency = <62500000>; ++ reg-io-width = <0x04>; ++ reg-shift = <0x02>; ++ }; ++ ++ spi0: spi@20320000 { ++ compatible = "snps,dw-apb-ssi"; ++ reg = <0x0 0x20320000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <19>; ++ num-cs = <3>; ++ }; ++ ++ spi1: spi@20420000 { ++ compatible = "snps,dw-apb-ssi"; ++ reg = <0x0 0x20420000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <27>; ++ num-cs = <3>; ++ }; ++ ++ i2c0: i2c@20330000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20330000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <20>; ++ }; ++ ++ i2c1: i2c@20340000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20340000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <21>; ++ }; ++ ++ i2c2: i2c@20430000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20430000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <28>; ++ }; ++ ++ i2c3: i2c@20440000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x20440000 0x0 0x100>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <&plic>; ++ interrupts = <29>; ++ }; ++ ++ pcie_x16: pcie@21000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x21000000 0x0 0x01000000>, ++ <0x0 0x4fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ ++ pcie_x4a: pcie@23000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x23000000 0x0 0x01000000>, ++ <0x0 0x6fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <63>, <64>, <65>, <66>, <67>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, ++ <0x0 0x0 0x0 0x2 &plic 65>, ++ <0x0 0x0 0x0 0x3 &plic 66>, ++ <0x0 0x0 0x0 0x4 &plic 67>; ++ }; ++ ++ pcie_x4b: pcie@24000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x24000000 0x0 0x01000000>, ++ <0x0 0x7fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <73>, <74>, <75>, <76>, <77>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, ++ <0x0 0x0 0x0 0x2 &plic 75>, ++ <0x0 0x0 0x0 0x3 &plic 76>, ++ <0x0 0x0 0x0 0x4 &plic 77>; ++ }; ++ ++ ethernet: ethernet@38000000 { ++ compatible = "snps,dwmac", "snps,dwmac-5.10a"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ interrupt-parent = <&plic>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ local-mac-address = [ff ff ff ff ff ff]; ++ max-speed = <1000>; ++ phy-mode = "rgmii-id"; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ }; ++ ++ dmac: dma-controller@39000000 { ++ compatible = "snps,axi-dma-1.01a"; ++ reg = <0x0 0x39000000 0x0 0x400>; ++ clocks = <&device_clk>, <&device_clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ #dma-cells = <1>; ++ dma-channels = <8>; ++ interrupt-parent = <&plic>; ++ interrupts = <152>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <512 512 512 512 512 512 512 512>; ++ snps,priority = <0 1 2 3 4 5 6 7>; ++ snps,axi-max-burst-len = <256>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0514-FROMLIST-riscv-dts-ultrarisc-add-Rongda-M0-board-dev.patch b/SPECS/linux-lts/0514-FROMLIST-riscv-dts-ultrarisc-add-Rongda-M0-board-dev.patch new file mode 100644 index 0000000000..83a8b6fe7e --- /dev/null +++ b/SPECS/linux-lts/0514-FROMLIST-riscv-dts-ultrarisc-add-Rongda-M0-board-dev.patch @@ -0,0 +1,249 @@ +From 351dafdb70244bb991776985260367ade2579893 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:03 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: ultrarisc: add Rongda M0 board + device tree + +Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-7-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/Makefile | 1 + + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + + .../ultrarisc/dp1000-rongda-m0-pinctrl.dtsi | 85 ++++++++++++++ + .../boot/dts/ultrarisc/dp1000-rongda-m0.dts | 111 ++++++++++++++++++ + 4 files changed, 199 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts + +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index 3763d199c70a..297b30243037 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -10,3 +10,4 @@ subdir-y += sophgo + subdir-y += spacemit + subdir-y += starfive + subdir-y += thead ++subdir-y += ultrarisc +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +new file mode 100644 +index 000000000000..d01a770d3cba +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi +new file mode 100644 +index 000000000000..101b416b1079 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0-pins { ++ pins = "PA12", "PA13"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c1_pins: i2c1-pins { ++ pins = "PB6", "PB7"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c2_pins: i2c2-pins { ++ pins = "PC0", "PC1"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c3_pins: i2c3-pins { ++ pins = "PC2", "PC3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ pciex4a_link_pins: pciex4a-link-pins { ++ pins = "PC0"; ++ function = "func1"; ++ bias-pull-down; ++ drive-strength = <33>; ++ }; ++ ++ pciex4b_link_pins: pciex4b-link-pins { ++ pins = "PC1"; ++ function = "func1"; ++ bias-pull-down; ++ drive-strength = <33>; ++ }; ++ ++ spi0_pins: spi0-pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ spi1_pins: spi1-pins { ++ pins = "PA0", "PA1", "PA2", "PA3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart0_pins: uart0-pins { ++ pins = "PA8", "PA9"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart1_pins: uart1-pins { ++ pins = "PB4", "PB5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart2_pins: uart2-pins { ++ pins = "PC4", "PC5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts +new file mode 100644 +index 000000000000..6f72d60ad55e +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts +@@ -0,0 +1,111 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-rongda-m0-pinctrl.dtsi" ++#include ++ ++/ { ++ model = "Rongda M0 Board"; ++ compatible = "rongda,m0", "ultrarisc,dp1000"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio_b 0 GPIO_ACTIVE_HIGH>; ++ active-delay-ms = <100>; ++ ++ status = "disabled"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&gpio_b 1 GPIO_ACTIVE_HIGH>; ++ active-delay = <100>; ++ ++ status = "disabled"; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@32 { ++ compatible = "whwave,sd3078"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++ðernet { ++ phy-handle = <&phy0>; ++ /* ++ * YT8531 RGMII timing on this board requires no PHY internal delays. ++ * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX CRC ++ * errors and no usable traffic, so keep plain "rgmii" here. ++ */ ++ phy-mode = "rgmii"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy0: phy@0 { ++ reg = <0x00>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0515-FROMLIST-riscv-dts-ultrarisc-add-Milk-V-Titan-board-.patch b/SPECS/linux-lts/0515-FROMLIST-riscv-dts-ultrarisc-add-Milk-V-Titan-board-.patch new file mode 100644 index 0000000000..814ab91e9e --- /dev/null +++ b/SPECS/linux-lts/0515-FROMLIST-riscv-dts-ultrarisc-add-Milk-V-Titan-board-.patch @@ -0,0 +1,331 @@ +From 22c65ac67825963cc9cd853c1df59117ec1f96b1 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 15 May 2026 09:18:04 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: ultrarisc: add Milk-V Titan board + device tree + +Milk-V Titan is an ITX motherboard based on the UltraRISC DP1000 SoC. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260515-ultrarisc-pinctrl-v1-8-bf559589ea8a@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 + + .../ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 107 ++++++++++ + .../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 182 ++++++++++++++++++ + 3 files changed, 290 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index d01a770d3cba..9c27256a2f67 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi +new file mode 100644 +index 000000000000..053206190ec7 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi +@@ -0,0 +1,107 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0-pins { ++ pins = "PA12", "PA13"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c1_pins: i2c1-pins { ++ pins = "PB6", "PB7"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c2_pins: i2c2-pins { ++ pins = "PC0", "PC1"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ i2c3_pins: i2c3-pins { ++ pins = "PC2", "PC3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ io_pins: io-pins { ++ pins = "PA10", "PA15", "PB0", "PB1", "PB2", "PD6", "PD7"; ++ function = "gpio"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ gpio_keys_pins: gpio-keys-pins { ++ pins = "PA4", "PA11", "PA14"; ++ function = "gpio"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ mux_dcdc_pins: mux-dcdc-pins { ++ pins = "PA5"; ++ function = "gpio"; ++ }; ++ ++ mux_i2c3_pins: mux-i2c3-pins { ++ pins = "PA6"; ++ function = "gpio"; ++ }; ++ ++ mux_uart0_pins: mux-uart0-pins { ++ pins = "PA7"; ++ function = "gpio"; ++ }; ++ ++ spi0_pins: spi0-pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ spi1_pins: spi1-pins { ++ pins = "PA0", "PA1", "PA2", "PA3"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart0_pins: uart0-pins { ++ pins = "PA8", "PA9"; ++ function = "func1"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart1_pins: uart1-pins { ++ pins = "PB4", "PB5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart2_pins: uart2-pins { ++ pins = "PC4", "PC5"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++ ++ uart3_pins: uart3-pins { ++ pins = "PC6", "PC7"; ++ function = "func0"; ++ bias-pull-up; ++ drive-strength = <33>; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts +new file mode 100644 +index 000000000000..21d85c03abe1 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts +@@ -0,0 +1,182 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-milkv-titan-pinctrl.dtsi" ++#include ++#include ++#include ++#include ++ ++/ { ++ model = "Milk-V Titan"; ++ compatible = "milkv,titan", "ultrarisc,dp1000"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio_b 0 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ ++ status = "disabled"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&gpio_b 1 GPIO_ACTIVE_LOW>; ++ active-delay = <100>; ++ ++ status = "disabled"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio_keys_pins>; ++ ++ key-wakeup-0 { ++ label = "Wake-Up"; ++ gpios = <&gpio_a 14 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ ++ key-wakeup-1 { ++ label = "Power"; ++ gpios = <&gpio_a 11 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ ++ key-wakeup-2 { ++ label = "Wake-Up-by-USB"; ++ gpios = <&gpio_a 4 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@68 { ++ compatible = "st,m41t11"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++}; ++ ++&gpio { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&io_pins &mux_dcdc_pins &mux_i2c3_pins &mux_uart0_pins>; ++}; ++ ++ðernet { ++ phy-handle = <&phy0>; ++ /* ++ * RTL8211F: board timing uses PHY strap delays; keep plain "rgmii". ++ * Enabling PHY internal delays via "rgmii-id" breaks Ethernet traffic. ++ */ ++ phy-mode = "rgmii"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy0: phy@0 { ++ reg = <0x00>; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ led@1 { ++ label = "eth-link"; ++ reg = <0x01>; ++ color = ; ++ function = LED_FUNCTION_INDICATOR; ++ default-state = "keep"; ++ linux,default-trigger = "netdev"; ++ }; ++ ++ led@2 { ++ label = "eth-activity"; ++ reg = <0x02>; ++ color = ; ++ function = LED_FUNCTION_ACTIVITY; ++ default-state = "keep"; ++ linux,default-trigger = "netdev"; ++ }; ++ }; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0516-FROMLIST-clocksource-drivers-timer-sun4i-Advertise-a.patch b/SPECS/linux-lts/0516-FROMLIST-clocksource-drivers-timer-sun4i-Advertise-a.patch new file mode 100644 index 0000000000..c77f6b3c78 --- /dev/null +++ b/SPECS/linux-lts/0516-FROMLIST-clocksource-drivers-timer-sun4i-Advertise-a.patch @@ -0,0 +1,52 @@ +From 129865db72315d91e800a756092f830f8ca3e15a Mon Sep 17 00:00:00 2001 +From: Felix Yan +Date: Thu, 25 Jun 2026 06:04:34 +0800 +Subject: [RUYI PATCH] FROMLIST: clocksource/drivers/timer-sun4i: Advertise a + real minimum delta + +sun4i_clkevt_next_event() compensates for the timer stop/start +synchronization delay by programming evt - TIMER_SYNC_TICKS into the +hardware interval register. The clockevent device currently advertises +TIMER_SYNC_TICKS as min_delta_ticks, so the clockevents core is allowed +to call set_next_event() with evt == TIMER_SYNC_TICKS. + +That programs a zero-tick interval. With oneshot/highres/nohz timer +operation this can leave the next event stuck, which was observed as a +boot hang on Allwinner D1 after the clockevents core started reusing +forced minimum-delta events. + +Advertise one extra tick instead, so the smallest event accepted by the +core still programs at least one hardware tick after the synchronization +compensation. + +Fixes: 12e1480bcb49 ("clocksource: sun4i: Report the minimum tick that we can program") +Cc: stable@vger.kernel.org +Reported-by: Indrek Kruusa +Closes: https://lore.kernel.org/linux-riscv/CA+fTLhgLmTY+exGujKf8OYYQvcEW5X5NJ_5sLq2AYL6zER2c0A@mail.gmail.com/ +Assisted-by: Codex:gpt-5.5 +Signed-off-by: Felix Yan +Acked-by: Jernej Skrabec +Tested-by: Indrek Kruusa +Link: https://lore.kernel.org/linux-riscv/CA+fTLhgLmTY+exGujKf8OYYQvcEW5X5NJ_5sLq2AYL6zER2c0A@mail.gmail.com/ +Link: https://lore.kernel.org/r/20260624220434.4183732-1-felixonmars@archlinux.org +Signed-off-by: Han Gao +--- + drivers/clocksource/timer-sun4i.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c +index 7bdcc60ad43c..c2d04ab7cf2d 100644 +--- a/drivers/clocksource/timer-sun4i.c ++++ b/drivers/clocksource/timer-sun4i.c +@@ -208,7 +208,7 @@ static int __init sun4i_timer_init(struct device_node *node) + sun4i_timer_clear_interrupt(timer_of_base(&to)); + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), +- TIMER_SYNC_TICKS, 0xffffffff); ++ TIMER_SYNC_TICKS + 1, 0xffffffff); + + /* Enable timer0 interrupt */ + val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0517-FROMLIST-riscv-dts-spacemit-Use-symbolic-PDMA-reques.patch b/SPECS/linux-lts/0517-FROMLIST-riscv-dts-spacemit-Use-symbolic-PDMA-reques.patch new file mode 100644 index 0000000000..861c8c75e5 --- /dev/null +++ b/SPECS/linux-lts/0517-FROMLIST-riscv-dts-spacemit-Use-symbolic-PDMA-reques.patch @@ -0,0 +1,111 @@ +From d322615922ba5ddf1ada2e5bbf9e9dc823068141 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 20 Jun 2026 01:07:48 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Use symbolic PDMA + request numbers on K1 + +The PDMA request numbers (DRQ) are fixed values specific to the SoC from +a hardware perspective. The detailed definition can be found in K1 User +Manual [1], Chapter 9.4.3 DMA Connectivity & Assignments. Add a DTS +header file to define the symbolic names for the DRQs of non-secure DMA +peripherals. + +Convert the K1 SPI3 node to these macros. + +Link: https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md [1] +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260620-b4-k1-pdma-req-macros-v4-1-3cf77d0bd0d6@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-pdma.h | 56 ++++++++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- + 2 files changed, 59 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k1-pdma.h + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pdma.h b/arch/riscv/boot/dts/spacemit/k1-pdma.h +new file mode 100644 +index 000000000000..7e5ad3d7111d +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k1-pdma.h +@@ -0,0 +1,56 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * DMA request number (DRQ) definitions for non-secure peripherals of ++ * the SpacemiT K1 PDMA. ++ * ++ * Copyright (c) 2026 Guodong Xu ++ */ ++ ++#ifndef _DTS_SPACEMIT_K1_PDMA_H ++#define _DTS_SPACEMIT_K1_PDMA_H ++ ++#define K1_PDMA_UART0_TX 3 ++#define K1_PDMA_UART0_RX 4 ++#define K1_PDMA_UART2_TX 5 ++#define K1_PDMA_UART2_RX 6 ++#define K1_PDMA_UART3_TX 7 ++#define K1_PDMA_UART3_RX 8 ++#define K1_PDMA_UART4_TX 9 ++#define K1_PDMA_UART4_RX 10 ++#define K1_PDMA_I2C0_TX 11 ++#define K1_PDMA_I2C0_RX 12 ++#define K1_PDMA_I2C1_TX 13 ++#define K1_PDMA_I2C1_RX 14 ++#define K1_PDMA_I2C2_TX 15 ++#define K1_PDMA_I2C2_RX 16 ++#define K1_PDMA_I2C4_TX 17 ++#define K1_PDMA_I2C4_RX 18 ++#define K1_PDMA_SPI3_TX 19 ++#define K1_PDMA_SPI3_RX 20 ++#define K1_PDMA_I2S0_TX 21 ++#define K1_PDMA_I2S0_RX 22 ++#define K1_PDMA_I2S1_TX 23 ++#define K1_PDMA_I2S1_RX 24 ++#define K1_PDMA_UART5_TX 25 ++#define K1_PDMA_UART5_RX 26 ++#define K1_PDMA_UART6_TX 27 ++#define K1_PDMA_UART6_RX 28 ++#define K1_PDMA_UART7_TX 29 ++#define K1_PDMA_UART7_RX 30 ++#define K1_PDMA_UART8_TX 31 ++#define K1_PDMA_UART8_RX 32 ++#define K1_PDMA_UART9_TX 33 ++#define K1_PDMA_UART9_RX 34 ++#define K1_PDMA_I2C5_TX 35 ++#define K1_PDMA_I2C5_RX 36 ++#define K1_PDMA_I2C6_TX 37 ++#define K1_PDMA_I2C6_RX 38 ++#define K1_PDMA_I2C7_TX 39 ++#define K1_PDMA_I2C7_RX 40 ++#define K1_PDMA_I2C8_TX 41 ++#define K1_PDMA_I2C8_RX 42 ++#define K1_PDMA_CAN0_RX 43 ++#define K1_PDMA_QSPI_RX 44 ++#define K1_PDMA_QSPI_TX 45 ++ ++#endif /* _DTS_SPACEMIT_K1_PDMA_H */ +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 4a359190f633..3fabfd34114b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -6,6 +6,8 @@ + #include + #include + ++#include "k1-pdma.h" ++ + /dts-v1/; + / { + #address-cells = <2>; +@@ -1102,7 +1104,7 @@ spi3: spi@d401c000 { + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_SSP3>; + interrupts = <55>; +- dmas = <&pdma 20>, <&pdma 19>; ++ dmas = <&pdma K1_PDMA_SPI3_RX>, <&pdma K1_PDMA_SPI3_TX>; + dma-names = "rx", "tx"; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0518-FROMLIST-riscv-mm-Fix-concurrency-in-mark_new_valid_.patch b/SPECS/linux-lts/0518-FROMLIST-riscv-mm-Fix-concurrency-in-mark_new_valid_.patch new file mode 100644 index 0000000000..257fde3cd4 --- /dev/null +++ b/SPECS/linux-lts/0518-FROMLIST-riscv-mm-Fix-concurrency-in-mark_new_valid_.patch @@ -0,0 +1,103 @@ +From 738cb2f8e77e629af7ad3ecb6327b64b0ab8d2cc Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 29 Jun 2026 17:25:45 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Fix concurrency in + mark_new_valid_map() + +Turns out, the concurrency concerns [1] were justified - BOSC reported a +spurious fault in KFENCE that still triggers despite previous fixes, +which KFENCE reports as a false-positive. + +Fix the concurrency problems in mark_new_valid_map(): + +- Add smp_wmb() before filling the bitmap, to make sure page table + writes are "received". +- Use WRITE_ONCE() to fill the bitmap. + +This fixes the KFENCE false positives in internal testing. + +Also update comments in the assembly exception handler code to match. + +Fixes: 26c171fc4853 ("riscv: mm: Use the bitmap API for new_valid_map_cpus") +Reported-by: Yaxing Guo +Suggested-by: David Hildenbrand (Arm) +Link: https://lore.kernel.org/linux-riscv/da19ffcf-8042-4f96-9c2d-649468dc6a0a@kernel.org/ # [1] +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260629-riscv-mm-new-valid-map-ordering-v1-1-60d8c10c6292@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 15 ++++++++++++++- + arch/riscv/kernel/entry.S | 11 ++++------- + 2 files changed, 18 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 8cfe59483a8f..1f191cf801a2 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -6,7 +6,9 @@ + #ifndef _ASM_RISCV_CACHEFLUSH_H + #define _ASM_RISCV_CACHEFLUSH_H + ++#include + #include ++#include + + static inline void local_flush_icache_all(void) + { +@@ -46,12 +48,23 @@ extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; + static inline void mark_new_valid_map(void) + { ++ /* ++ * Orders any previous page table writes before setting bits in ++ * new_valid_map_cpus. Pairs with the sfence.vma in ++ * new_valid_map_cpus_check. ++ */ ++ smp_wmb(); ++ + /* + * We don't care if concurrently a cpu resets this value since + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. ++ * ++ * Not memset() or bitmap_fill() to avoid any possible compiler ++ * shenanigans. + */ +- bitmap_fill(new_valid_map_cpus, NR_CPUS); ++ for (size_t i = 0; i < ARRAY_SIZE(new_valid_map_cpus); i++) ++ WRITE_ONCE(new_valid_map_cpus[i], -1UL); + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 5639031d1437..67d630acf330 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -76,6 +76,8 @@ + amoxor.d a0, a1, (a0) + + /* ++ * Pairs with the smp_wmb() in mark_new_valid_map() ++ * + * A sfence.vma is required here. Even if we had Svvptc, there's no + * guarantee that after returning we wouldn't just fault again. + */ +@@ -112,13 +114,8 @@ SYM_CODE_START(handle_exception) + /* + * The RISC-V kernel does not flush TLBs on all CPUS after each new + * vmalloc mapping or kfence_unprotect(), which may result in +- * exceptions: +- * +- * - if the uarch caches invalid entries, the new mapping would not be +- * observed by the page table walker and an invalidation is needed. +- * - if the uarch does not cache invalid entries, a reordered access +- * could "miss" the new mapping and traps: in that case, we only need +- * to retry the access, no sfence.vma is required. ++ * exceptions. In that case, we need to sfence.vma to "receive" the new ++ * mappings and retry, whether or not we have Svvptc. + */ + new_valid_map_cpus_check + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0519-FROMLIST-clk-spacemit-k3-fix-parent-clock-of-UFS-acl.patch b/SPECS/linux-lts/0519-FROMLIST-clk-spacemit-k3-fix-parent-clock-of-UFS-acl.patch new file mode 100644 index 0000000000..8f6d34d686 --- /dev/null +++ b/SPECS/linux-lts/0519-FROMLIST-clk-spacemit-k3-fix-parent-clock-of-UFS-acl.patch @@ -0,0 +1,44 @@ +From adc59ef4d17d4895bf576f3cf8aa3caf6889e7bf Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 12:52:45 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix parent clock of UFS + aclk + +According to SpacemiT updated clock docs, the previous UFS aclk parent +clock was wrong, the correct one is illustrated below, so fix it. + + --> pll1_d5_491p52 --\ + --> pll1_d6_409p6 --| + --> pll2_d6 --|--> div --> gate --> ufs_aclk + --> pll2_d5 --/ + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260630-06-clk-ufs-support-v1-1-cf7521d1d0fe@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 03de04144963..0702b6ecdbd2 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -926,11 +926,10 @@ CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 1 + 20, 3, BIT(16), 0); + + static const struct clk_parent_data ufs_aclk_parents[] = { +- CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), +- CCU_PARENT_HW(pll1_d4_614p4), +- CCU_PARENT_HW(pll1_d8_307p2), +- CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll2_d6), ++ CCU_PARENT_HW(pll2_d5), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), + 2, 3, BIT(1), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0520-FROMLIST-dt-bindings-soc-spacemit-k3-Add-clock-ID-fo.patch b/SPECS/linux-lts/0520-FROMLIST-dt-bindings-soc-spacemit-k3-Add-clock-ID-fo.patch new file mode 100644 index 0000000000..29062567d5 --- /dev/null +++ b/SPECS/linux-lts/0520-FROMLIST-dt-bindings-soc-spacemit-k3-Add-clock-ID-fo.patch @@ -0,0 +1,31 @@ +From b4f7041ac6bd1aadb453f13a9b30238794f3dac7 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 12:52:46 +0000 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add clock ID + for UFS refclk + +Add clock ID for the UFS refclk clock in SpacemiT K3 SoC. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260630-06-clk-ufs-support-v1-2-cf7521d1d0fe@kernel.org +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index dfae52547cda..69978ab0b29f 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -385,6 +385,7 @@ + #define CLK_APMU_PCIE_PORTC_DBI 91 + #define CLK_APMU_PCIE_PORTD_DBI 92 + #define CLK_APMU_PCIE_PORTE_DBI 93 ++#define CLK_APMU_UFS_REFCLK 94 + + /* DCIU clocks */ + #define CLK_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0521-FROMLIST-clk-spacemit-k3-Add-UFS-refclk-clock.patch b/SPECS/linux-lts/0521-FROMLIST-clk-spacemit-k3-Add-UFS-refclk-clock.patch new file mode 100644 index 0000000000..05cce2a6d8 --- /dev/null +++ b/SPECS/linux-lts/0521-FROMLIST-clk-spacemit-k3-Add-UFS-refclk-clock.patch @@ -0,0 +1,38 @@ +From aa8baac4138d0aba308fc3e443779253a7d48537 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 12:52:47 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add UFS refclk clock + +Add the UFS reference clock for SpacemiT K3 SoC. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260630-06-clk-ufs-support-v1-3-cf7521d1d0fe@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 0702b6ecdbd2..092446590e41 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -934,6 +934,8 @@ static const struct clk_parent_data ufs_aclk_parents[] = { + CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), + 2, 3, BIT(1), 0); + ++CCU_FACTOR_DEFINE(ufs_refclk, CCU_PARENT_HW(pll1_d64_38p4), 2, 1); ++ + static const struct clk_parent_data edp0_pclk_parents[] = { + CCU_PARENT_HW(lcd_pxclk), + CCU_PARENT_NAME(external_clk), +@@ -1391,6 +1393,7 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { + [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, + [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, + [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, ++ [CLK_APMU_UFS_REFCLK] = &ufs_refclk.common.hw, + [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, + [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, + [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0522-FROMLIST-riscv-Avoid-stack-access-when-CSR_SCRATCH-i.patch b/SPECS/linux-lts/0522-FROMLIST-riscv-Avoid-stack-access-when-CSR_SCRATCH-i.patch new file mode 100644 index 0000000000..7e11efaa4f --- /dev/null +++ b/SPECS/linux-lts/0522-FROMLIST-riscv-Avoid-stack-access-when-CSR_SCRATCH-i.patch @@ -0,0 +1,194 @@ +From 888cd2841311164193d9df6e0f99f4d5a3f63d79 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 30 Jun 2026 14:36:24 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: Avoid stack access when CSR_SCRATCH is + incorrect + +The kernel exception handler unconditionally relies on the value in +CSR_SCRATCH, whether it is 0 (meaning kernel mode) or the current +pointer (meaning user mode). Therefore, any exception that happens while +CSR_SCRATCH does not reflect the current privilege mode would be +irrecoverable. + +When VMAP_STACK=y, spurious-seeming page faults can happen while +accessing the stack if the processor has cached/still-in-pipeline +non-valid PTEs. Therefore, it is unsafe to access the stack on entry +before setting CSR_SCRATCH to 0, or on exit to user after setting +CSR_SCRATCH to current. + +Therefore, instead of using the stack, make some scratch space in +task_info for these fragile regions of code, and access them using +offsets from tp. The scratch space for mark_new_valid_map is not reused +because the page fault *can* nest in places where the scratch space is +needed. + +Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") +Reported-by: Yaxing Guo +Link: https://lore.kernel.org/linux-riscv/20260601084524.34584-1-guoyaxing@bosc.ac.cn/ +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260630-riscv-no-stack-when-wrong-scratch-v1-1-0f9b9cb5cf67@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/csr.h | 1 + + arch/riscv/include/asm/thread_info.h | 5 +++ + arch/riscv/kernel/asm-offsets.c | 2 + + arch/riscv/kernel/entry.S | 65 +++++++++++++++++++++------- + 4 files changed, 58 insertions(+), 15 deletions(-) + +diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h +index 543a3364f11d..3ca44349168b 100644 +--- a/arch/riscv/include/asm/csr.h ++++ b/arch/riscv/include/asm/csr.h +@@ -16,6 +16,7 @@ + #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ + #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ + #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ ++#define SR_MPP_SHIFT 11 + #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ + + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h +index 836d80dd2921..0a2767430d0a 100644 +--- a/arch/riscv/include/asm/thread_info.h ++++ b/arch/riscv/include/asm/thread_info.h +@@ -73,6 +73,11 @@ struct thread_info { + */ + unsigned long a0, a1, a2; + #endif ++ /* ++ * Used in ret_from_exception() and handle_exception() as scratch space ++ * when CSR_SCRATCH does not reflect the current privilege mode. ++ */ ++ unsigned long tp, t0; + }; + + #ifdef CONFIG_SHADOW_CALL_STACK +diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c +index 7d42d3b8a32a..63cb1d8e0b5e 100644 +--- a/arch/riscv/kernel/asm-offsets.c ++++ b/arch/riscv/kernel/asm-offsets.c +@@ -49,6 +49,8 @@ void asm_offsets(void) + OFFSET(TASK_TI_A1, task_struct, thread_info.a1); + OFFSET(TASK_TI_A2, task_struct, thread_info.a2); + #endif ++ OFFSET(TASK_TI_TP, task_struct, thread_info.tp); ++ OFFSET(TASK_TI_T0, task_struct, thread_info.t0); + + OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); + OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 67d630acf330..5a97f002bf1f 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -99,6 +99,8 @@ + + + SYM_CODE_START(handle_exception) ++ /* Caution: CSR_SCARTCH does not reflect privilege mode from now on. */ ++ + /* + * If coming from userspace, preserve the user thread pointer and load + * the kernel thread pointer. If we came from the kernel, the scratch +@@ -131,6 +133,19 @@ SYM_CODE_START(handle_exception) + #endif + + .Lsave_context: ++ REG_S t0, TASK_TI_T0(tp) ++ ++ /* ++ * Grab the saved TP, and also set the scratch register back to 0, so ++ * that if a recursive exception occurs, the exception vector knows it ++ * came from the kernel. ++ * ++ * Caution: CSR_SCARTCH does not reflect privilege mode before this. ++ */ ++ csrrw t0, CSR_SCRATCH, zero ++ REG_S t0, TASK_TI_TP(tp) ++ REG_L t0, TASK_TI_T0(tp) ++ + REG_S sp, TASK_TI_USER_SP(tp) + REG_L sp, TASK_TI_KERNEL_SP(tp) + addi sp, sp, -(PT_SIZE_ON_STACK) +@@ -153,7 +168,7 @@ SYM_CODE_START(handle_exception) + csrr s2, CSR_EPC + csrr s3, CSR_TVAL + csrr s4, CSR_CAUSE +- csrr s5, CSR_SCRATCH ++ REG_L s5, TASK_TI_TP(tp) + REG_S s0, PT_SP(sp) + REG_S s1, PT_STATUS(sp) + REG_S s2, PT_EPC(sp) +@@ -161,12 +176,6 @@ SYM_CODE_START(handle_exception) + REG_S s4, PT_CAUSE(sp) + REG_S s5, PT_TP(sp) + +- /* +- * Set the scratch register to 0, so that if a recursive exception +- * occurs, the exception vector knows it came from the kernel +- */ +- csrw CSR_SCRATCH, x0 +- + /* Load the global pointer */ + load_global_pointer + +@@ -234,11 +243,6 @@ SYM_CODE_START_NOALIGN(ret_from_exception) + /* Save the kernel shadow call stack pointer */ + scs_save_current + +- /* +- * Save TP into the scratch register , so we can find the kernel data +- * structures again. +- */ +- csrw CSR_SCRATCH, tp + 1: + #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE + move a0, sp +@@ -270,11 +274,42 @@ SYM_CODE_START_NOALIGN(ret_from_exception) + + REG_L x1, PT_RA(sp) + REG_L x3, PT_GP(sp) +- REG_L x4, PT_TP(sp) +- REG_L x5, PT_T0(sp) + restore_from_x6_to_x31 + +- REG_L x2, PT_SP(sp) ++ /* ++ * Stash t0 and tp in thread_info since we can't access the stack after ++ * switching CSR_SCRATCH. ++ */ ++ REG_L t0, PT_T0(sp) ++ REG_S t0, TASK_TI_T0(tp) ++ REG_L t0, PT_TP(sp) ++ REG_S t0, TASK_TI_TP(tp) ++ ++ REG_L sp, PT_SP(sp) ++ ++ /* If returning to user mode, set CSR_SCRATCH to tp, else 0 */ ++ csrr t0, CSR_STATUS ++#if defined(CONFIG_RISCV_M_MODE) ++ /* the MPP value is too large to be used as an immediate arg for andi */ ++ srli t0, t0, SR_MPP_SHIFT ++ andi t0, t0, SR_MPP >> SR_MPP_SHIFT ++ /* t0 = (mstatus & SR_MPP) >> SR_MPP_SHIFT */ ++#else ++ andi t0, t0, SR_SPP ++ /* t0 = sstatus & SR_SPP */ ++#endif ++ seqz t0, t0 ++ /* t0 = !(status & SR_PP) */ ++ neg t0, t0 ++ /* t0 = (status & SR_PP) ? 0 : -1 */ ++ and t0, t0, tp ++ /* t0 = (status & SR_PP) ? 0 : tp */ ++ csrw CSR_SCRATCH, t0 ++ ++ /* Caution: CSR_SCARTCH does not reflect privilege mode from now on. */ ++ ++ REG_L t0, TASK_TI_T0(tp) ++ REG_L tp, TASK_TI_TP(tp) + + #ifdef CONFIG_RISCV_M_MODE + mret +-- +2.53.0 + diff --git a/SPECS/linux-lts/0523-FROMLIST-clk-spacemit-k3-set-hdma-clock-as-critical.patch b/SPECS/linux-lts/0523-FROMLIST-clk-spacemit-k3-set-hdma-clock-as-critical.patch new file mode 100644 index 0000000000..e3075be78a --- /dev/null +++ b/SPECS/linux-lts/0523-FROMLIST-clk-spacemit-k3-set-hdma-clock-as-critical.patch @@ -0,0 +1,35 @@ +From 09ea1f8afcd909a41d34782732f100b787f25a8c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 08:53:19 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: set hdma clock as critical + +HDMA clock is responsible for the internal TCM access path of X100 RISC-V +core, so set the clock flag as critical to prevent it from being shut off, +otherwise the Linux system will hang. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Han Gao +Signed-off-by: Yixun Lan +Tested-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260630-06-clk-hdma-critial-v1-1-443c0ac88c5f@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 092446590e41..aca61ea76019 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -1027,7 +1027,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT + /* APMU clocks end */ + + /* DCIU clocks start */ +-CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); + CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); + CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); + CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0524-FROMLIST-clk-spacemit-k3-set-rcpu-clock-as-critical.patch b/SPECS/linux-lts/0524-FROMLIST-clk-spacemit-k3-set-rcpu-clock-as-critical.patch new file mode 100644 index 0000000000..cddf6384f8 --- /dev/null +++ b/SPECS/linux-lts/0524-FROMLIST-clk-spacemit-k3-set-rcpu-clock-as-critical.patch @@ -0,0 +1,36 @@ +From 90c9870addd82d973bf57ae773aee08cfc054c74 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 30 Jun 2026 08:53:20 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: set rcpu clock as critical + +The SpacemiT K3 SoC integrates two RT24 RISC-V little cores (os0_rcpu and +os1_rcpu), each running an independent ESOS instance responsible for +system power management and real-time task. The RCPU clock is required +in order to keep these cores functional, so set its clock as critical to +prevent it from being shut off. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Han Gao +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260630-06-clk-hdma-critial-v1-2-443c0ac88c5f@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index aca61ea76019..5d0e31f07d6d 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { + CCU_PARENT_HW(pll1_d6_409p6), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, +- 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); + + static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { + CCU_PARENT_HW(pll1_d48_51p2_ap), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0525-FROMLIST-scsi-ufs-spacemit-dt-bindings-Add-UFS-contr.patch b/SPECS/linux-lts/0525-FROMLIST-scsi-ufs-spacemit-dt-bindings-Add-UFS-contr.patch new file mode 100644 index 0000000000..b13f6e5e54 --- /dev/null +++ b/SPECS/linux-lts/0525-FROMLIST-scsi-ufs-spacemit-dt-bindings-Add-UFS-contr.patch @@ -0,0 +1,86 @@ +From 8a7c0fb3a48fb485653d9f1159654de66caf9b84 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 2 Jul 2026 02:31:35 +0000 +Subject: [RUYI PATCH] FROMLIST: scsi: ufs: spacemit: dt-bindings: Add UFS + controller for K3 SoC + +Document the compatible for UFS (Universal Flash Storage) Host Controller +which found in SpacemiT K3 SoC chip. Its features are listed below: + +- Compliant with MIPI UniPro v1.61 specification. +- Compliant with M-PHY v3.0 specification. +- Compliant with UFS HCI v2.1 specification. +- Supports up to 2 Tx and 2 Rx lanes, up to HS-GEAR3 5.8 Gbps per lane. +- Supports standard low-power hibernate to reduce power consumption. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260702-08-k3-ufs-support-v1-1-1a64a3ab128f@kernel.org +Signed-off-by: Han Gao +--- + .../bindings/ufs/spacemit,k3-ufshc.yaml | 54 +++++++++++++++++++ + 1 file changed, 54 insertions(+) + create mode 100644 Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml + +diff --git a/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml b/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml +new file mode 100644 +index 000000000000..e6cb6fb2496c +--- /dev/null ++++ b/Documentation/devicetree/bindings/ufs/spacemit,k3-ufshc.yaml +@@ -0,0 +1,54 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/ufs/spacemit,k3-ufshc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K3 SoC UFS Host Controller ++ ++maintainers: ++ - Yixun Lan ++ ++properties: ++ compatible: ++ const: spacemit,k3-ufshc ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: aclk ++ - const: ref_clk ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ ++allOf: ++ - $ref: ufs-common.yaml ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ufs@c0e00000 { ++ compatible = "spacemit,k3-ufshc"; ++ reg = <0xc0e00000 0x40000>; ++ clocks = <&syscon_apmu CLK_APMU_UFS_ACLK>, ++ <&syscon_apmu CLK_APMU_UFS_REFCLK>; ++ clock-names = "aclk", "ref_clk"; ++ resets = <&syscon_apmu RESET_APMU_UFS_ACLK>; ++ freq-table-hz = <491520000 491520000 19200000 19200000>; ++ lanes-per-direction = <2>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0526-FROMLIST-scsi-ufs-spacemit-k3-Add-UFS-Host-Controlle.patch b/SPECS/linux-lts/0526-FROMLIST-scsi-ufs-spacemit-k3-Add-UFS-Host-Controlle.patch new file mode 100644 index 0000000000..49c6e86246 --- /dev/null +++ b/SPECS/linux-lts/0526-FROMLIST-scsi-ufs-spacemit-k3-Add-UFS-Host-Controlle.patch @@ -0,0 +1,1093 @@ +From be8fda343078b7b8f8ee71dab4139785a03d9ace Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 2 Jul 2026 02:31:36 +0000 +Subject: [RUYI PATCH] FROMLIST: scsi: ufs: spacemit: k3: Add UFS Host + Controller driver + +SpacemiT K3 SoC consist of UFS (Universal Flash Storage) Host Controller +which has features compatible with JEDEC UFS 2.2, MIPI UniPro v1.61 and +M-PHY v3.0 standard. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260702-08-k3-ufs-support-v1-2-1a64a3ab128f@kernel.org +Signed-off-by: Han Gao +--- + drivers/ufs/host/Kconfig | 12 + + drivers/ufs/host/Makefile | 1 + + drivers/ufs/host/ufs-spacemit.c | 931 ++++++++++++++++++++++++++++++++ + drivers/ufs/host/ufs-spacemit.h | 90 +++ + 4 files changed, 1034 insertions(+) + create mode 100644 drivers/ufs/host/ufs-spacemit.c + create mode 100644 drivers/ufs/host/ufs-spacemit.h + +diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig +index 964ae70e7390..9b57772faf5f 100644 +--- a/drivers/ufs/host/Kconfig ++++ b/drivers/ufs/host/Kconfig +@@ -132,6 +132,18 @@ config SCSI_UFS_VARIABLE_SG_ENTRY_SIZE + bool + default y if SCSI_UFS_EXYNOS && SCSI_UFS_CRYPTO + ++config SCSI_UFS_SPACEMIT ++ tristate "SpacemiT UFS controller driver" ++ depends on SCSI_UFSHCD_PLATFORM && ARCH_SPACEMIT ++ help ++ This selects the SpacemiT specific additions to UFSHCD platform driver. ++ UFS host on SpacemiT needs some vendor specific configuration before ++ accessing the hardware which includes PHY configuration and vendor ++ specific registers. ++ ++ Select this if you have UFS controller on SpacemiT chipset. ++ If unsure, say N. ++ + config SCSI_UFS_SPRD + tristate "Unisoc specific hooks to UFS controller platform driver" + depends on SCSI_UFSHCD_PLATFORM && (ARCH_SPRD || COMPILE_TEST) +diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile +index 65d8bb23ab7b..151bf43dfba7 100644 +--- a/drivers/ufs/host/Makefile ++++ b/drivers/ufs/host/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o + obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o + obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o + obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o ++obj-$(CONFIG_SCSI_UFS_SPACEMIT) += ufs-spacemit.o + obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o + obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o + obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o +diff --git a/drivers/ufs/host/ufs-spacemit.c b/drivers/ufs/host/ufs-spacemit.c +new file mode 100644 +index 000000000000..be475f5566a8 +--- /dev/null ++++ b/drivers/ufs/host/ufs-spacemit.c +@@ -0,0 +1,931 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ufshcd-pltfrm.h" ++#include "ufs-spacemit.h" ++ ++/* PA Layer Gettable and settable M-PHY Specific Attributes */ ++#define PA_TXHSG1SYNCLENGTH 0x1552 ++#define PA_TXHSG1PREPARELENGTH 0x1553 ++#define PA_TXHSG2SYNCLENGTH 0x1554 ++#define PA_TXHSG2PREPARELENGTH 0x1555 ++#define PA_TXHSG3SYNCLENGTH 0x1556 ++#define PA_TXHSG3PREPARELENGTH 0x1557 ++#define PA_TXMK2EXTENSION 0x155A ++#define PA_PEERSCRAMBLING 0x155B ++#define PA_TXSKIP 0x155C ++#define PA_TXSKIPPERIOD 0x155D ++#define PA_PEER_TX_LCC_ENABLE 0x155F ++ ++#define PA_SCRAMBLING 0x1585 ++#define PA_MK2EXTENSIONGUARDBAND 0x15AB ++ ++/*special TX/RX Configuration Attributes*/ ++#define RX_LS_PRE_LEN_CAP 0x008D ++#define RX_LANE_HB8_BKDOOR_ATTR 0x00F4 ++#define RX_PWRM_CLOSURE_LEN_CAP 0x008E ++#define RX_MIN_STALL_CAP 0x0088 ++#define RX_LANE_SOF_BKDOOR_ATT 0x00F2 ++#define RX_GARBAGE_COUNT_OFFSET 0x00F2 ++ ++/*special analog reg*/ ++#define ANA_EQ_CTRL_REG_ATTR 0x00CD ++#define ANA_HSGEAR_CTRL_ATTR 0x00C1 ++ ++/* ++ * Keep UFS ACLK at a lower parent rate (409.6MHz) for stable init. ++ * This mirrors the "ufs-low-aclk-freq" change from the other environment. ++ */ ++#define UFS_ACLK_LOW_FREQ_HZ 409600000UL ++ ++/* PHY register magic values */ ++#define MPHY_PU_ALL 0x87f ++#define MPHY_PU_WITH_HB8_RESET 0xb7f ++#define MPHY_DEVICE_RESET_DEASSERT 0x101 ++#define MPHY_DEVICE_RESET_ASSERT 0x001 ++#define MPHY_PLL_LOCK_BIT BIT(31) ++#define MPHY_PLL_LOCK_TIMEOUT_US 10000 ++ ++/* FSM states */ ++#define FSM_STATE_HIBERN8 0x1 ++#define FSM_STATE_ACTIVE 0x3 ++#define FSM_STATE_LS_BURST 0x5 ++ ++struct ufs_reg_snapshot { ++ u32 reg_utrlba; ++ u32 reg_utrlbau; ++ u32 reg_utrmlba; ++ u32 reg_utrmlbau; ++ ++ u32 reg_sys1clk; ++ u32 reg_tx_symbol_clk; ++ u32 reg_retry_timer; ++ u32 reg_pa_link; ++ u32 reg_cfg1; ++}; ++ ++#define VENDOR_DUMP_BUF_SIZE 2048 ++#define VENDOR_MAX_OFFSET 0xE0 ++ ++static void ufs_spacemit_dump_host_regs(struct ufs_hba *hba) ++{ ++ int i, offset; ++ size_t len = 0; ++ u8 *buf; ++ u32 val; ++ u32 host_reg[] = { ++ (UFS_PHY_MNG_BASE + UFS_MPHY_RST_CTRL), ++ (UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL), ++ (UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL), ++ 0xFFF, ++ }; ++ ++ buf = kzalloc(VENDOR_DUMP_BUF_SIZE, GFP_ATOMIC); ++ if (!buf) ++ return; ++ ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "vendor specific registers:"); ++ ++ for (offset = 0xC0, i = 0; offset < VENDOR_MAX_OFFSET; offset += 4, i++) { ++ val = ufshcd_readl(hba, offset); ++ if (i % 4 == 0) ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n"); ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, " 0x%03x: 0x%08x ", ++ offset, val); ++ } ++ ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n mphy and atop registers:"); ++ ++ for (i = 0; host_reg[i] != 0xFFF; i++) { ++ val = ufshcd_readl(hba, host_reg[i]); ++ if (i % 4 == 0) ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n"); ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, " 0x%03x: 0x%08x ", ++ host_reg[i], val); ++ } ++ len += scnprintf(buf + len, VENDOR_DUMP_BUF_SIZE - len, "\n"); ++ ++ dev_warn(hba->dev, "%s", buf); ++ ++ kfree(buf); ++} ++ ++/* M-PHY FSM states */ ++#define MPHY_RX_FSM_STATE 0xC1 ++#define MPHY_TX_FSM_STATE 0x41 ++ ++static bool is_fsm_state_valid(u32 state) ++{ ++ return (state == FSM_STATE_ACTIVE || state == FSM_STATE_LS_BURST); ++} ++ ++static int ufs_spacemit_check_hibern8(struct ufs_hba *hba) ++{ ++ u32 tx_fsm_val_0 = 0; ++ u32 tx_fsm_val_1 = 0; ++ int retries = DIV_ROUND_UP(HBRN8_POLL_TOUT_MS * 1000, 100); ++ int err = 0; ++ ++ do { ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ &tx_fsm_val_0); ++ err |= ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ &tx_fsm_val_1); ++ if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && ++ tx_fsm_val_1 == TX_FSM_HIBERN8)) ++ break; ++ ++ usleep_range(100, 200); ++ } while (--retries > 0); ++ ++ if (!err && retries <= 0) { ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ &tx_fsm_val_0); ++ err |= ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, ++ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ &tx_fsm_val_1); ++ } ++ ++ if (err) { ++ dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", ++ __func__, err); ++ } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || ++ tx_fsm_val_1 != TX_FSM_HIBERN8) { ++ err = -ETIMEDOUT; ++ dev_err(hba->dev, ++ "%s: invalid TX_FSM_STATE, lane0 = %u, lane1 = %u\n", ++ __func__, tx_fsm_val_0, tx_fsm_val_1); ++ } ++ ++ return err; ++} ++ ++static void ufs_spacemit_dump_fsm_state(struct ufs_hba *hba) ++{ ++ u32 tx0_fsm_val, tx1_fsm_val, rx0_fsm_val, rx1_fsm_val; ++ int err; ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ &tx0_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ &tx1_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_RX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ &rx0_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ err = ufshcd_dme_get(hba, ++ UIC_ARG_MIB_SEL(MPHY_RX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ &rx1_fsm_val); ++ if (err) ++ return; ++ ++ usleep_range(100, 200); ++ ++ if (!is_fsm_state_valid(tx0_fsm_val) || !is_fsm_state_valid(tx1_fsm_val) || ++ !is_fsm_state_valid(rx0_fsm_val) || !is_fsm_state_valid(rx1_fsm_val)) { ++ dev_warn(hba->dev, "FSM state invalid - TX:[0x%x, 0x%x], RX:[0x%x, 0x%x]\n", ++ tx0_fsm_val, tx1_fsm_val, rx0_fsm_val, rx1_fsm_val); ++ } ++} ++ ++static int ufs_spacemit_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes) ++{ ++ int err; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes); ++ if (err) ++ dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n", __func__, err); ++ ++ return err; ++} ++ ++static u32 ufs_spacemit_get_sys1clk_1us(struct ufs_hba *hba) ++{ ++ struct ufs_clk_info *clki, *ufs_aclk = NULL; ++ struct list_head *head = &hba->clk_list_head; ++ unsigned long rate_hz = 0; ++ ++ if (!list_empty(head)) { ++ list_for_each_entry(clki, head, list) { ++ if (clki->name && !strcmp(clki->name, "aclk") && clki->clk) { ++ ufs_aclk = clki; ++ break; ++ } ++ } ++ } ++ ++ if (ufs_aclk && ufs_aclk->clk) ++ rate_hz = clk_get_rate(ufs_aclk->clk); ++ ++ if (!rate_hz) ++ return 0; ++ ++ return DIV_ROUND_CLOSEST(rate_hz, 1000000); ++} ++ ++static int ufs_spacemit_wait_mphy_pll_lock(struct ufs_hba *hba) ++{ ++ int timeout = MPHY_PLL_LOCK_TIMEOUT_US; ++ u32 val; ++ ++ while (timeout-- > 0) { ++ val = ufshcd_readl(hba, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ if (val & MPHY_PLL_LOCK_BIT) ++ return 0; ++ ++ udelay(1); ++ } ++ ++ dev_err(hba->dev, "M-PHY PLL lock timeout\n"); ++ return -ETIMEDOUT; ++} ++ ++/** ++ * ufs_spacemit_mphy_init ++ * @hba: host controller instance ++ */ ++static int ufs_spacemit_mphy_init(struct ufs_hba *hba) ++{ ++ int ret; ++ ++ /* reset all mphy logical */ ++ ufshcd_writel(hba, 0x003, UFS_PHY_MNG_BASE + 0x0); ++ mdelay(1); ++ ++ /* power up all */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + 0x4); ++ mdelay(1); ++ ++ /* asserted ana_rx_hb8_reset */ ++ ufshcd_writel(hba, 0xb7f, UFS_PHY_MNG_BASE + 0x4); ++ mdelay(1); ++ ++ /* deasserted ana_rx_hb8_reset */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + 0x4); ++ mdelay(1); ++ ++ /* deasserted ufs device reset & refer clk output enable */ ++ ufshcd_writel(hba, 0x101, UFS_PHY_MNG_BASE + 0xC); ++ mdelay(1); ++ ++ ret = ufs_spacemit_wait_mphy_pll_lock(hba); ++ if (ret < 0) ++ return ret; ++ ++ dev_dbg(hba->dev, "M-PHY PLL locked successfully\n"); ++ ++ ufshcd_writel(hba, 0x1, UFS_PHY_MNG_BASE + 0x08); ++ udelay(5); ++ ++ ufshcd_writel(hba, 0x40, UFS_ATOP_BASE + (0xC2 << 2)); ++ udelay(5); ++ ++ ufshcd_writel(hba, 0x0, UFS_PHY_MNG_BASE + 0x08); ++ ++ mdelay(2); ++ ++ dev_dbg(hba->dev, "M-PHY init completed\n"); ++ ++ return 0; ++} ++ ++static int ufs_spacemit_uniprov1p6_init(struct ufs_hba *hba) ++{ ++ /* PA_TXHSG1SYNCLENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1552), 0x4f); ++ ++ /* PA_TXHSG1PREPARELENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1553), 0xf); ++ ++ /* PA_TXHSG2SYNCLENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1554), 0x4f); ++ ++ /* PA_TXHSG2PREPARELENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1555), 0xf); ++ ++ /* PA_TXHSG3SYNCLENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x4f); ++ ++ /* PA_TXHSG3PREPARELENGTH */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1557), 0xf); ++ ++ /* PA_TXMK2EXTENSION */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155A), 0x0); ++ ++ /* PA_PEERSCRAMBLING */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155B), 0x1); ++ ++ /* PA_TXSKIP */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155C), 0x1); ++ ++ /* PA_TXSKIPPERIOD */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155D), 250); ++ ++ /* PA_LOCAL_TX_LCC_ENABLE */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0); ++ ++ /* PA_PEER_TX_LCC_ENABLE */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x155F), 0x0); ++ ++ /* PA_SCRAMBLING */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1585), 0x1); ++ ++ /* PA_GRANULARITY */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15AA), 0x1); ++ ++ /* PA_MK2EXTENSIONGUARDBAND */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15AB), 0x0); ++ ++ /* PA_STALLNOCONFIGTIME */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A3), 15); ++ ++ /* PA_TACTIVATE */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x64); ++ ++ /* PA_TXTRAILINGCLOCKS */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0x1564), 0x64); ++ ++ /* RX_LS_PREPARELEN_TIME RX0 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008D, 4), 0x0B); ++ ++ /* RX_LS_PREPARELEN_TIME RX1 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008D, 5), 0X0B); ++ ++ /* RX_HIBERNATE_BKEN RX0 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F4, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x9F); ++ ++ /* RX_HIBERNATE_BKEN RX1 */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F4, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x9F); ++ ++ /* PWM_BURST_closure_length */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008E, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 15); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008E, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 15); ++ ++ /* min_stall_not_config_time*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0088, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0xFF); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0088, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0xFF); ++ ++ /* TX HB8_TIME CAP */ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x64); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), 0x64); ++ ++ /*RX HB8_TIME CAP*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x64); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x64); ++ ++ /*TX EQ 3DB*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00CD, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x5); ++ ++ /*RX garbage cnt = 32 SI*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F2, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 0x9F); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x00F2, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), 0x9F); ++ ++ dev_info(hba->dev, "UniPro v1.6 init completed\n"); ++ ++ return 0; ++} ++ ++static void ufs_spacemit_set_dev_cap(struct ufs_host_params *host_params, u32 pwr_hs) ++{ ++ if (!host_params) ++ return; ++ ++ memset(host_params, 0, sizeof(struct ufs_host_params)); ++ host_params->tx_lanes = UFS_SPACEMIT_K3_LIMIT_NUM_LANES_TX; ++ host_params->rx_lanes = UFS_SPACEMIT_K3_LIMIT_NUM_LANES_RX; ++ host_params->hs_rx_gear = UFS_SPACEMIT_K3_LIMIT_HSGEAR_RX; ++ host_params->hs_tx_gear = UFS_SPACEMIT_K3_LIMIT_HSGEAR_TX; ++ host_params->pwm_rx_gear = UFS_SPACEMIT_K3_LIMIT_PWMGEAR_RX; ++ host_params->pwm_tx_gear = UFS_SPACEMIT_K3_LIMIT_PWMGEAR_TX; ++ host_params->rx_pwr_pwm = UFS_SPACEMIT_K3_LIMIT_RX_PWR_PWM; ++ host_params->tx_pwr_pwm = UFS_SPACEMIT_K3_LIMIT_TX_PWR_PWM; ++ host_params->rx_pwr_hs = pwr_hs; ++ host_params->tx_pwr_hs = pwr_hs; ++ host_params->hs_rate = UFS_SPACEMIT_K3_LIMIT_HS_RATE; ++ host_params->desired_working_mode = UFS_HS_MODE; ++} ++ ++static int ufs_spacemit_link_startup_pre_change(struct ufs_hba *hba) ++{ ++ u32 value, sys1clk_1us; ++ ++ ufs_spacemit_mphy_init(hba); ++ ++ ufs_spacemit_uniprov1p6_init(hba); ++ ++ /* config sysclk and tx symbol clk before link startup */ ++ value = UFS_MAX_LINKSTARTUP_TIMER; ++ ++ /* clear bit0~bit3, select b0 design */ ++ value &= ~0xf; ++ ++ ufshcd_writel(hba, value, UFS_PA_LINK_STARTUP_TIMER); ++ ++ sys1clk_1us = ufs_spacemit_get_sys1clk_1us(hba); ++ if (!sys1clk_1us) ++ sys1clk_1us = DIV_ROUND_CLOSEST(UFS_ACLK_LOW_FREQ_HZ, 1000000); ++ ufshcd_writel(hba, sys1clk_1us, UFS_SYS1CLK_1US); ++ ufshcd_writel(hba, UFS_TX_SYMBO_CLK, UFS_TX_SYMBOL_CLK_NS_US); ++ ++ dev_dbg(hba->dev, "REG_UFS_SYS1CLK_1US: 0x%x\n", ufshcd_readl(hba, UFS_SYS1CLK_1US)); ++ dev_dbg(hba->dev, "REG_UFS_TX_SYMBOL_CLK_NS_US: 0x%x\n", ++ ufshcd_readl(hba, UFS_TX_SYMBOL_CLK_NS_US)); ++ ++ return 0; ++} ++ ++static int ufs_spacemit_link_startup_post_change(struct ufs_hba *hba) ++{ ++ u32 tx_lanes; ++ ++ /* add 0xe8 make UFS2.1 run GEAR3 + 2Lane@409M */ ++ mdelay(5); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xe8, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x97); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xe8, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0xd7); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xe8, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0x17); ++ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), UFS_DL_AFC0REQTIMEOUTVAL_MAX); ++ ++ return ufs_spacemit_get_connected_tx_lanes(hba, &tx_lanes); ++} ++ ++static int ufs_spacemit_link_startup_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ switch (status) { ++ case PRE_CHANGE: ++ ufs_spacemit_link_startup_pre_change(hba); ++ break; ++ case POST_CHANGE: ++ ufs_spacemit_link_startup_post_change(hba); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int ufs_spacemit_negotiate_pwr_mode(struct ufs_hba *hba, ++ const struct ufs_pa_layer_attr *dev_max_params, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_host_params host_params; ++ int ret; ++ ++ ufs_spacemit_set_dev_cap(&host_params, FAST_MODE); ++ ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, ++ dev_req_params); ++ if (ret) { ++ dev_err(hba->dev, "Failed to negotiate power params: %d\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(hba->dev, ++ "Power mode config - gear_rx:%d, gear_tx:%d, lane_rx:%d, lane_tx:%d, pwr_rx:%d, pwr_tx:%d, hs_rate:%d\n", ++ dev_req_params->gear_rx, dev_req_params->gear_tx, dev_req_params->lane_rx, ++ dev_req_params->lane_tx, dev_req_params->pwr_rx, dev_req_params->pwr_tx, ++ dev_req_params->hs_rate); ++ ++ return ret; ++} ++ ++static int ufs_spacemit_pwr_change_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status, ++ struct ufs_pa_layer_attr *dev_req_params) ++{ ++ struct ufs_spacemit_host *host = ufshcd_get_variant(hba); ++ int ret = 0; ++ ++ if (!dev_req_params) { ++ dev_err(hba->dev, "Invalid Parameters\n"); ++ return -EINVAL; ++ } ++ ++ switch (status) { ++ case PRE_CHANGE: ++ break; ++ case POST_CHANGE: ++ /* cache the power mode parameters to use internally */ ++ memcpy(&host->dev_req_params, dev_req_params, sizeof(*dev_req_params)); ++ ret = ufs_spacemit_wait_mphy_pll_lock(hba); ++ if (ret < 0) ++ return ret; ++ ++ dev_dbg(hba->dev, "M-PHY PLL locked after power mode change\n"); ++ /*set ANA_HSGEAR_CTRL_ATTR back to default value*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(ANA_HSGEAR_CTRL_ATTR), 0x00); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static int ufs_spacemit_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) ++{ ++ int err; ++ u32 pa_vs_config_reg1; ++ ++ err = ufshcd_dme_get(hba, UIC_ARG_MIB(UFS_PA_VS_CONFIG_REG1), &pa_vs_config_reg1); ++ if (err) ++ return err; ++ ++ /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ ++ return ufshcd_dme_set(hba, UIC_ARG_MIB(UFS_PA_VS_CONFIG_REG1), ++ (pa_vs_config_reg1 | (1 << 12))); ++} ++ ++static int ufs_spacemit_apply_dev_quirks(struct ufs_hba *hba) ++{ ++ if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) ++ ufs_spacemit_quirk_host_pa_saveconfigtime(hba); ++ ++ if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) ++ hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; ++ ++ /*LCC_DISABLE*/ ++ mdelay(50); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LCC_ENABLE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 0); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LCC_ENABLE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), 0); ++ ++ /*TX_Min_ActivateTime*/ ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), ++ 0x0); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)), ++ 0x0); ++ mdelay(10); ++ ++ /*use backdoor reg to pre-set TX RATE/GEAR to let PLL lock before set_power_mode switch*/ ++ ufshcd_dme_set(hba, UIC_ARG_MIB(ANA_HSGEAR_CTRL_ATTR), 0x25); ++ mdelay(10); ++ ++ return ufs_spacemit_wait_mphy_pll_lock(hba); ++} ++ ++/** ++ * ufs_spacemit_advertise_quirks - advertise the known Spacemit UFS controller quirks ++ * @hba: host controller instance ++ * ++ * Spacemit UFS host controller might have some non standard behaviours (quirks) ++ * than what is specified by UFSHCI specification. Advertise all such ++ * quirks to standard UFS host controller driver so standard takes them into ++ * account. ++ */ ++static void ufs_spacemit_advertise_quirks(struct ufs_hba *hba) ++{ ++ hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; ++} ++ ++/** ++ * ufs_spacemit_fsm_dump_work - Deferred work to dump FSM state ++ * @work: work structure ++ * ++ * This function is called from a workqueue context (not interrupt context), ++ * allowing safe execution of blocking operations like ufshcd_dme_get(). ++ */ ++static void ufs_spacemit_fsm_dump_work(struct work_struct *work) ++{ ++ struct ufs_spacemit_host *host = container_of(work, struct ufs_spacemit_host, ++ fsm_dump_work); ++ struct ufs_hba *hba = host->hba; ++ ++ /* Safe to call blocking functions in workqueue context */ ++ if (ufshcd_is_link_active(hba)) ++ ufs_spacemit_dump_fsm_state(hba); ++} ++ ++/** ++ * ufs_spacemit_init - init phy and prepare clk ++ * @hba: host controller instance ++ */ ++static int ufs_spacemit_init(struct ufs_hba *hba) ++{ ++ int err = 0; ++ struct device *dev = hba->dev; ++ struct ufs_spacemit_host *host; ++ ++ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ host->rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(host->rst)) ++ return dev_err_probe(dev, PTR_ERR(host->rst), ++ "Failed to get reset control\n"); ++ ++ host->hba = hba; ++ ufshcd_set_variant(hba, host); ++ ufs_spacemit_advertise_quirks(hba); ++ ++ /* Initialize workqueue for deferred FSM state dump */ ++ INIT_WORK(&host->fsm_dump_work, ufs_spacemit_fsm_dump_work); ++ ++ err = ufshcd_vops_phy_initialization(host->hba); ++ return err; ++} ++ ++/** ++ * ufs_spacemit_device_reset - Toggle device reset line ++ * @hba: per-adapter instance ++ * ++ * Toggles the reset line to reset the attached UFS device. ++ * ++ * Returns: 0 on success ++ */ ++static int ufs_spacemit_device_reset(struct ufs_hba *hba) ++{ ++ /* Stop device ref_clk & asserted ufs device reset */ ++ ufshcd_writel(hba, 0x000, UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ mdelay(1); ++ ++ /* Enable device ref_clk & de-asserted ufs device reset */ ++ ufshcd_writel(hba, MPHY_DEVICE_RESET_DEASSERT, UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ mdelay(1); ++ ++ return 0; ++} ++ ++/** ++ * ufs_spacemit_event_notify - Handle UFS error events ++ * @hba: host controller instance ++ * @evt: event type ++ * @data: event-specific data ++ * ++ * Handles error events from UFS core, dumps registers immediately ++ * and schedules FSM state dump for later execution in workqueue context. ++ */ ++static void ufs_spacemit_event_notify(struct ufs_hba *hba, enum ufs_event_type evt, void *data) ++{ ++ struct ufs_spacemit_host *host = ufshcd_get_variant(hba); ++ bool dump_regs = false; ++ ++ switch (evt) { ++ case UFS_EVT_PA_ERR: ++ if (data) ++ dev_warn(hba->dev, "PA error event, INT errors:0x%x, PA_ERR_CODE:0x%x\n", ++ hba->errors, *(u32 *)data); ++ ++ dump_regs = true; ++ break; ++ ++ case UFS_EVT_DL_ERR: ++ if (data) ++ dev_warn(hba->dev, "DL error event, INT errors:0x%x, DL_ERR:0x%x\n", ++ hba->errors, *(u32 *)data); ++ ++ dump_regs = true; ++ break; ++ ++ case UFS_EVT_ABORT: ++ dev_warn(hba->dev, "Abort event, INT errors:0x%x\n", hba->errors); ++ break; ++ ++ default: ++ break; ++ } ++ ++ /* Dump registers if error occurred (safe in interrupt context) */ ++ if (hba->errors || dump_regs) ++ ufs_spacemit_dump_host_regs(hba); ++ ++ /* Schedule FSM state dump in workqueue context (not in interrupt context) */ ++ if (ufshcd_is_link_active(hba) && host) ++ queue_work(system_wq, &host->fsm_dump_work); ++} ++ ++/** ++ * ufs_spacemit_hibern8_notify - Handle hibernate enter/exit ++ * @hba: host controller instance ++ * @cmd: UIC command (HIBER_ENTER or HIBER_EXIT) ++ * @status: notification status ++ * ++ * Manages M-PHY power state during hibernate transitions. ++ */ ++static void ufs_spacemit_hibern8_notify(struct ufs_hba *hba, enum uic_cmd_dme cmd, ++ enum ufs_notify_change_status status) ++{ ++ int ret; ++ ++ dev_dbg(hba->dev, "Hibern8 notify: cmd=%d, status=%d\n", cmd, status); ++ if (status == PRE_CHANGE) { ++ if (cmd == UIC_CMD_DME_HIBER_EXIT) { ++ mdelay(1); ++ ++ /* Enable reference clock */ ++ ufshcd_writel(hba, MPHY_DEVICE_RESET_DEASSERT, ++ UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ mdelay(1); ++ ++ /* Power up all */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ mdelay(1); ++ ++ /* Assert ana_rx_hb8_reset */ ++ ufshcd_writel(hba, MPHY_PU_WITH_HB8_RESET, ++ UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ mdelay(1); ++ ++ /* Deassert ana_rx_hb8_reset */ ++ ufshcd_writel(hba, MPHY_PU_ALL, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ ++ ret = ufs_spacemit_wait_mphy_pll_lock(hba); ++ if (ret < 0) ++ return; ++ ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xdd), 0x57); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xe8), 0x57); ++ } ++ } ++ ++ if (status == PRE_CHANGE) { ++ if (cmd == UIC_CMD_DME_HIBER_ENTER) { ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x85); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x85); ++ } ++ } ++ ++ if (status == POST_CHANGE) { ++ if (cmd == UIC_CMD_DME_HIBER_ENTER) { ++ ufs_spacemit_check_hibern8(hba); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x84); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), ++ 0x80); ++ ufshcd_dme_set(hba, ++ UIC_ARG_MIB_SEL(0xf1, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(1)), ++ 0x80); ++ ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xdd), 0x57); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xdd), 0xd7); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xe8), 0x57); ++ mdelay(1); ++ ufshcd_dme_set(hba, UIC_ARG_MIB(0xe8), 0xd7); ++ mdelay(1); ++ ++ /* Power down M-PHY */ ++ ufshcd_writel(hba, 0x0, UFS_PHY_MNG_BASE + UFS_MPHY_PU_CTRL); ++ mdelay(1); ++ ++ /* Keep reference clock enabled, assert device reset */ ++ ufshcd_writel(hba, MPHY_DEVICE_RESET_ASSERT, ++ UFS_PHY_MNG_BASE + UFS_DEVICE_IO_CTRL); ++ } ++ } ++} ++ ++/** ++ * ufs_spacemit_hce_enable_notify - Configure HCE enable sequence ++ * @hba: host controller instance ++ * @status: notification status (PRE_CHANGE or POST_CHANGE) ++ * ++ * Configures host controller enable with proper sequencing. ++ * Handles crypto enable if supported. ++ * ++ * Returns: 0 on success ++ */ ++static int ufs_spacemit_hce_enable_notify(struct ufs_hba *hba, ++ enum ufs_notify_change_status status) ++{ ++ struct ufs_spacemit_host *host = ufshcd_get_variant(hba); ++ u32 enable_val, val; ++ ++ if (status == PRE_CHANGE) { ++ enable_val = CONTROLLER_ENABLE; ++ ++ if (hba->caps & UFSHCD_CAP_CRYPTO) ++ enable_val = CRYPTO_GENERAL_ENABLE | CONTROLLER_ENABLE; ++ ++ if (!host->first_hce_done) { ++ host->first_hce_done = true; ++ dev_dbg(hba->dev, "First HCE enable\n"); ++ } else { ++ val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); ++ if (val == enable_val) { ++ ufshcd_writel(hba, enable_val & (1 << CONTROLLER_ENABLE), ++ REG_CONTROLLER_ENABLE); ++ ++ while (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) == ++ (enable_val & (1 << CONTROLLER_ENABLE))) ++ ; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * struct ufs_hba_spacemit_vops - UFS Spacemit specific variant operations ++ * ++ * The variant operations configure the necessary controller and PHY ++ * handshake during initialization. ++ */ ++static const struct ufs_hba_variant_ops ufs_hba_spacemit_vops = { ++ .name = "ufshcd-spacemit", ++ .init = ufs_spacemit_init, ++ .link_startup_notify = ufs_spacemit_link_startup_notify, ++ .negotiate_pwr_mode = ufs_spacemit_negotiate_pwr_mode, ++ .pwr_change_notify = ufs_spacemit_pwr_change_notify, ++ .device_reset = ufs_spacemit_device_reset, ++ .event_notify = ufs_spacemit_event_notify, ++ .apply_dev_quirks = ufs_spacemit_apply_dev_quirks, ++ .hibern8_notify = ufs_spacemit_hibern8_notify, ++ .hce_enable_notify = ufs_spacemit_hce_enable_notify, ++}; ++ ++static const struct of_device_id ufs_spacemit_of_match[] = { ++ { .compatible = "spacemit,k3-ufshc" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, ufs_spacemit_of_match); ++ ++static int ufs_spacemit_probe(struct platform_device *pdev) ++{ ++ return ufshcd_pltfrm_init(pdev, &ufs_hba_spacemit_vops); ++} ++ ++static void ufs_spacemit_remove(struct platform_device *pdev) ++{ ++ ufshcd_pltfrm_remove(pdev); ++} ++ ++static struct platform_driver ufs_spacemit_pltform = { ++ .probe = ufs_spacemit_probe, ++ .remove = ufs_spacemit_remove, ++ .driver = { ++ .name = "ufshcd-spacemit", ++ .of_match_table = of_match_ptr(ufs_spacemit_of_match), ++ }, ++}; ++module_platform_driver(ufs_spacemit_pltform); ++ ++MODULE_DESCRIPTION("SpacemiT UFS Host Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/ufs/host/ufs-spacemit.h b/drivers/ufs/host/ufs-spacemit.h +new file mode 100644 +index 000000000000..6ae3c263a360 +--- /dev/null ++++ b/drivers/ufs/host/ufs-spacemit.h +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * SpacemiT UFS Host Controller driver ++ * ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ */ ++ ++#ifndef _UFS_SPACEMIT_H_ ++#define _UFS_SPACEMIT_H_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* Spacemit K3 UFS host controller vendor specific registers */ ++#define UFS_SYS1CLK_1US 0xC0 ++#define UFS_TX_SYMBOL_CLK_NS_US 0xC4 ++#define UFS_LOCAL_PORT_ID_REG 0xC8 ++#define UFS_PA_ERR_CODE 0xCC ++#define UFS_RETRY_TIMER_REG 0xD0 ++#define UFS_PA_LINK_STARTUP_TIMER 0xD8 ++#define UFS_CFG1 0xDC ++ ++/* MPHY control registers */ ++#define UFS_PHY_MNG_BASE 0x1B00 ++#define UFS_MPHY_RST_CTRL 0x0 ++#define UFS_MPHY_PU_CTRL 0x4 ++#define UFS_MPHY_BKDR_CTRL 0x8 ++#define UFS_DEVICE_IO_CTRL 0xC ++ ++/* ATOP base*/ ++#define UFS_ATOP_BASE 0x1C00 ++ ++#define UFS_SYSCLK 499 ++#define UFS_TX_SYMBO_CLK 0x800 ++#define UFS_MAX_LINKSTARTUP_TIMER 0xFFFFFFFF ++#define UFS_DL_AFC0REQTIMEOUTVAL_MAX 0xFFFF ++ ++#define MPHY_TX_FSM_STATE 0x41 ++#define TX_FSM_HIBERN8 0x1 ++#define HBRN8_POLL_TOUT_MS 100 ++#define DEFAULT_CLK_RATE_HZ 1000000 ++#define BUS_VECTOR_NAME_LEN 32 ++ ++#define UFS_HW_VER_MAJOR_SHFT 28 ++#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) ++#define UFS_HW_VER_MINOR_SHFT 16 ++#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) ++#define UFS_HW_VER_STEP_SHFT 0 ++#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) ++ ++#define UFS_SPACEMIT_K3_LIMIT_NUM_LANES_RX 2 ++#define UFS_SPACEMIT_K3_LIMIT_NUM_LANES_TX 2 ++#define UFS_SPACEMIT_K3_LIMIT_HSGEAR_RX UFS_HS_G3 ++#define UFS_SPACEMIT_K3_LIMIT_HSGEAR_TX UFS_HS_G3 ++#define UFS_SPACEMIT_K3_LIMIT_PWMGEAR_RX UFS_PWM_G4 ++#define UFS_SPACEMIT_K3_LIMIT_PWMGEAR_TX UFS_PWM_G4 ++#define UFS_SPACEMIT_K3_LIMIT_RX_PWR_PWM SLOW_MODE ++#define UFS_SPACEMIT_K3_LIMIT_TX_PWR_PWM SLOW_MODE ++#define UFS_SPACEMIT_K3_LIMIT_RX_PWR_HS FAST_MODE ++#define UFS_SPACEMIT_K3_LIMIT_TX_PWR_HS FAST_MODE ++#define UFS_SPACEMIT_K3_LIMIT_HS_RATE PA_HS_MODE_B ++#define UFS_SPACEMIT_K3_LIMIT_DESIRED_MODE 2 ++ ++#define UFS_PA_VS_CONFIG_REG1 0x9000 ++#define UFS_DME_VS_CORE_CLK_CTRL 0xD002 ++ ++#define UFS_HCLKDIV_REG 0xFC ++ ++struct ufs_spacemit_host { ++ struct ufs_hba *hba; ++ struct ufs_pa_layer_attr dev_req_params; ++ struct reset_control *rst; ++ u32 caps; ++ u32 lpm_qos; ++ u32 unipro_ver; ++ u32 remote_unipro_ver; ++ u8 prev_request_crypto; ++ ++ bool is_lane_clks_on; ++ bool first_init_done; ++ bool first_hce_done; ++ ++ /* Workqueue for deferred FSM state dump */ ++ struct work_struct fsm_dump_work; ++}; ++ ++#endif /* _UFS_SPACEMIT_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0527-FROMLIST-riscv-dts-spacemit-k3-Add-UFS-support.patch b/SPECS/linux-lts/0527-FROMLIST-riscv-dts-spacemit-k3-Add-UFS-support.patch new file mode 100644 index 0000000000..7cfae1033d --- /dev/null +++ b/SPECS/linux-lts/0527-FROMLIST-riscv-dts-spacemit-k3-Add-UFS-support.patch @@ -0,0 +1,67 @@ +From d5b71c210c3bcb18e2afe2d3940f43c56d2827bf Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 2 Jul 2026 02:31:37 +0000 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add UFS support + +Add UFS Host Controller support for SpacemiT K3 SoC, and enable +it both on both Pico-ITX and CoM260-IFX boards. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260702-08-k3-ufs-support-v1-3-1a64a3ab128f@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts | 4 ++++ + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 4 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 13 +++++++++++++ + 3 files changed, 21 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +index e7f76cd24b90..91bc8c0a2ed9 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -37,3 +37,7 @@ &sdhci0 { + sd-uhs-sdr104; + status = "okay"; + }; ++ ++&ufshc { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 8b2a120b02d1..c7ecb2f5cb4d 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -317,3 +317,7 @@ hub@1 { + &usb2_phy { + status = "okay"; + }; ++ ++&ufshc { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index fc46e34465e4..862e5698972e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1216,5 +1216,18 @@ maplic: interrupt-controller@f1800000 { + riscv,num-sources = <512>; + status = "reserved"; + }; ++ ++ ufshc: ufshc@c0e00000 { ++ compatible = "spacemit,k3-ufshc"; ++ reg = <0x0 0xc0e00000 0x0 0x40000>; ++ clocks = <&syscon_apmu CLK_APMU_UFS_ACLK>, ++ <&syscon_apmu CLK_APMU_UFS_REFCLK>; ++ clock-names = "aclk", "ref_clk"; ++ resets = <&syscon_apmu RESET_APMU_UFS_ACLK>; ++ interrupts = <135 IRQ_TYPE_LEVEL_HIGH>; ++ freq-table-hz = <491520000 491520000 19200000 19200000>; ++ lanes-per-direction = <2>; ++ status = "disabled"; ++ }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0528-FROMLIST-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-c.patch b/SPECS/linux-lts/0528-FROMLIST-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-c.patch new file mode 100644 index 0000000000..43c521362a --- /dev/null +++ b/SPECS/linux-lts/0528-FROMLIST-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-c.patch @@ -0,0 +1,95 @@ +From 761a9312a0023c41f12b4561170ecf1df809dc1d Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 3 Jul 2026 10:10:22 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: Add Spacemit K3 USB3/PCIe + comb phy support + +The USB3/PCIe comb PHY on the K3 is a complex PHY group that +can provide multiple phy for both PCIe and USB controller. +Its mux configuration is controlled by the APMU syscon device. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260703021024.495433-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k3-combo-phy.yaml | 68 +++++++++++++++++++ + 1 file changed, 68 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +new file mode 100644 +index 000000000000..ed820cf697b8 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +@@ -0,0 +1,68 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 PCIE/USB3 Comb PHY ++ ++maintainers: ++ - Inochi Amaoto ++ ++properties: ++ compatible: ++ const: spacemit,k3-combo-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 2 ++ description: ++ The first one is phy id, the second one is phy type. This ++ only supports types are PCIe and USB . ++ ++ spacemit,apb-spare: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to APB SPARE system controller interface, used for ++ PHY calibration. ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle of APMU syscon ++ - description: configuration of the PHY lanes ++ description: | ++ Phandle to control PHY mux configuration. The configuration ++ is described as follows: ++ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode ++ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode ++ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode ++ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode ++ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode ++ ++ The bit[3:0] is only valid when bit 4 is 1. ++ ++ This mux control does not affect the PHY for PCIe E, it is always ++ in PCIe mode. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ - spacemit,apb-spare ++ - spacemit,apmu ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x81d00000 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&apb_spare>; ++ spacemit,apmu = <&apmu 0x00>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0529-FROMLIST-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-.patch b/SPECS/linux-lts/0529-FROMLIST-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-.patch new file mode 100644 index 0000000000..a881ddffb1 --- /dev/null +++ b/SPECS/linux-lts/0529-FROMLIST-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-.patch @@ -0,0 +1,751 @@ +From 19a2632222f27e50adbb383893af270b0469c06a Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 3 Jul 2026 10:10:23 +0800 +Subject: [RUYI PATCH] FROMLIST: phy: spacemit: Add USB3/PCIe comb PHY driver + for Spacemit K3 + +The comb PHY on K3 requires to configure a syscon device for the +right mux configuration. And it requires calibration before any +usage. + +Add USB3/PCIe comb PHY driver for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260703021024.495433-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/Kconfig | 16 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k3-combo.c | 252 +++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.c | 391 +++++++++++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.h | 27 ++ + 5 files changed, 688 insertions(+) + create mode 100644 drivers/phy/spacemit/phy-k3-combo.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.h + +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 50b0005acf66..5fdf18fce499 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -23,3 +23,19 @@ config PHY_SPACEMIT_K1_USB2 + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. ++ ++config PHY_SPACEMIT_K3_COMMON_OPS ++ tristate ++ select MFD_SYSCON ++ select GENERIC_PHY ++ ++config PHY_SPACEMIT_K3_COMBO_PHY ++ tristate "SpacemiT K3 USB3/PCIe PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ select PHY_SPACEMIT_K3_COMMON_OPS ++ help ++ Enable this to support K3 USB3/PCIe combo PHY driver. This ++ driver takes care of enabling and clock setup and will be used ++ by K3 dwc3 driver. ++ If unsure, say N. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index a821a21d6142..f679c1851b4f 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,3 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o +diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c +new file mode 100644 +index 000000000000..0bc08bb6247a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-combo.c +@@ -0,0 +1,252 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * phy-k3-combo.c - SpacemiT K3 PCIe/USB3 Combo PHY Driver ++ * ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* ++ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs ++ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. ++ * ++ * PMUA_PCIE_SUBSYS_MGMT[4:0] ++ * ++ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A ++ * 1 : PHY lanes shared between PCIe or USB according to [3:0] ++ * ++ * All PHY matrix combinations according to [4:0]: ++ * ++ * 0x0X : PCIe-A X8 ++ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) ++ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) ++ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) ++ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) ++ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) ++ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) ++ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * ++ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. ++ */ ++#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 ++#define PU_MATRIX_CONF_MASK GENMASK(4, 0) ++ ++#define COMBPHY_MAX_SUBPHYS 6 ++ ++struct k3_combo_phy { ++ struct device *dev; ++ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; ++ void __iomem *base; ++ struct regmap *apb_spare; ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x0, 0x400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x100000, 0x100400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { ++ .lanes = 1, ++ .config = 0x14, ++ .mask = 0x14, ++ .offsets = { ++ 0x200000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { ++ .lanes = 1, ++ .config = 0x12, ++ .mask = 0x12, ++ .offsets = { ++ 0x300000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { ++ .lanes = 1, ++ .config = 0x11, ++ .mask = 0x11, ++ .offsets = { ++ 0x400000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { ++ .lanes = 1, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x500000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { ++ &k3_combphy_lane_group0, ++ &k3_combphy_lane_group1, ++ &k3_combphy_lane_group2, ++ &k3_combphy_lane_group3, ++ &k3_combphy_lane_group4, ++ &k3_combphy_lane_group5, ++}; ++ ++static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { ++ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; ++ struct k3_lane_group *lg = &phy->groups[i]; ++ const struct phy_ops *ops; ++ bool is_usb; ++ ++ is_usb = (data->mask & config) == data->config; ++ if (is_usb) ++ ops = &k3_usb3_phy_ops; ++ else ++ ops = &k3_pcie_phy_ops; ++ ++ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); ++ ++ lg->phy = devm_phy_create(phy->dev, NULL, ops); ++ if (IS_ERR(lg->phy)) ++ return PTR_ERR(lg->phy); ++ ++ lg->is_pcie = !is_usb; ++ lg->data = data; ++ lg->base = phy->base; ++ phy_set_drvdata(lg->phy, lg); ++ } ++ ++ return 0; ++} ++ ++static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) ++{ ++ if (config & ~PU_MATRIX_CONF_MASK) ++ return -EINVAL; ++ ++ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); ++} ++ ++static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k3_combo_phy *phy = dev_get_drvdata(dev); ++ struct k3_lane_group *lg; ++ ++ if (args->args_count != 2) { ++ dev_err(dev, "Invalid number of arguments\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { ++ dev_err(dev, "Invalid PHY id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ lg = &phy->groups[args->args[0]]; ++ ++ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || ++ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { ++ dev_err(dev, "Invalid PHY mode\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return lg->phy; ++} ++ ++static int k3_combo_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct phy_provider *provider; ++ struct k3_combo_phy *phy; ++ struct regmap *apmu; ++ u32 config = 0; ++ int ret; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->base)) ++ return PTR_ERR(phy->base); ++ ++ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); ++ if (IS_ERR(phy->apb_spare)) ++ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), ++ "Failed to find APB SPARE syscon"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to find APMU syscon"); ++ ++ ret = k3_combo_phy_update_config(apmu, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to set lane configuration"); ++ ++ phy->dev = dev; ++ platform_set_drvdata(pdev, phy); ++ ++ ret = k3_phy_calibrate(phy->apb_spare); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to calibrate phy"); ++ ++ ret = k3_combo_phy_init_lanes(phy, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to init lanes"); ++ ++ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "Failed to register provider\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id k3_combo_phy_of_match[] = { ++ { .compatible = "spacemit,k3-combo-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); ++ ++static struct platform_driver k3_combo_phy_driver = { ++ .probe = k3_combo_phy_probe, ++ .driver = { ++ .name = "spacemit,k3-combo-phy", ++ .of_match_table = k3_combo_phy_of_match, ++ }, ++}; ++module_platform_driver(k3_combo_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c +new file mode 100644 +index 000000000000..0b289e63db99 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.c +@@ -0,0 +1,391 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* PHY Registers */ ++#define PHY_VERSION 0x0 ++ ++#define PHY_RESET_CFG 0x04 ++ ++#define PHY_RESET_RXBUF_RST BIT(0) ++#define PHY_RESET_SOFT_RST_PCS BIT(1) ++#define PHY_RESET_SOFT_RST_AHB BIT(2) ++#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) ++ ++#define PHY_CLK_CFG 0x08 ++ ++#define PHY_CLK_PLL_READY BIT(0) ++#define PHY_CLK_TXCLK_INV BIT(2) ++#define PHY_CLK_RXCLK_EN BIT(3) ++#define PHY_CLK_TXCLK_EN BIT(4) ++#define PHY_CLK_PCLK_EN BIT(5) ++#define PHY_CLK_PIPE_PCLK_EN BIT(6) ++#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) ++#define PHY_CLK_REFCLK_24M 2 ++#define PHY_CLK_SW_INIT_DONE BIT(11) ++#define PHY_CLK_PU_SSC_OUT BIT(23) ++ ++#define PHY_MODE_CFG 0x0C ++ ++#define PHY_MODE_PCIE_INT_EN BIT(0) ++#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) ++#define PHY_MODE_LFPS_TPERIOD_USB 3 ++ ++#define PHY_PU_SEL 0x40 ++ ++#define PHY_PU_CFG_STATUS BIT(9) ++#define PHY_PU_OVRD_STATUS BIT(10) ++ ++#define PHY_PU_CK_REG 0x54 ++ ++#define PHY_PU_REFCLK_100 BIT(25) ++ ++#define PHY_PLL_REG1 0x58 ++ ++#define PHY_PLL_FREF_SEL GENMASK(15, 13) ++#define PHY_PLL_FREF_24M 0x1 ++#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) ++#define PHY_PLL_SSC_5000PPM 0xa ++#define PHY_PLL_SSC_MODE GENMASK(29, 28) ++#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 ++#define PHY_PLL_SSC_MODE_UP_SPREAD 1 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 ++ ++#define PHY_PLL_REG2 0x5c ++ ++#define PHY_PLL_SEL_REF100 BIT(21) ++ ++/* PHY RX Register Definitions */ ++#define PHY_RX_REG_A 0x60 ++ ++#define PHY_RX_REG0_MASK GENMASK(7, 0) ++#define PHY_RX_REG1_MASK GENMASK(15, 8) ++#define PHY_RX_REG2_MASK GENMASK(23, 16) ++#define PHY_RX_REG3_MASK GENMASK(31, 24) ++ ++#define PHY_RX_REG0_RLOAD BIT(4) ++#define PHY_RX_REG1_RTERM GENMASK(11, 8) ++#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) ++#define PHY_RX_REG2_CSEL GENMASK(19, 16) ++#define PHY_RX_REG2_FORCE_CSEL BIT(20) ++#define PHY_RX_REG2_PSEL GENMASK(23, 21) ++#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) ++#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) ++#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) ++#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) ++ ++#define PHY_RX_REG_B 0x64 ++ ++#define PHY_RX_REG4_MASK GENMASK(7, 0) ++#define PHY_RX_REG5_MASK GENMASK(15, 8) ++#define PHY_RX_REG6_MASK GENMASK(23, 16) ++ ++#define PHY_RX_REGB_MASK GENMASK(23, 0) ++ ++#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) ++#define PHY_RX_REG4_ENVOS BIT(4) ++#define PHY_RX_REG4_RTERM_SEL BIT(5) ++#define PHY_RX_REG4_MANUAL_CFG BIT(7) ++#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) ++#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) ++#define PHY_RX_REG6_H1_REG GENMASK(19, 16) ++#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) ++#define PHY_RX_REG6_BYPASS_ADPT BIT(22) ++ ++#define PHY_ADPT_CFG0 0x140 ++#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) ++#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) ++ ++#define PHY_RXEQ_TIME 0xb4 ++#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) ++#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) ++#define PHY_RXEQ_TIME_AMP_SOC_650M 0 ++#define PHY_RXEQ_TIME_AMP_SOC_800M 1 ++#define PHY_RXEQ_TIME_AMP_SOC_870M 2 ++#define PHY_RXEQ_TIME_AMP_SOC_900M 3 ++#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) ++ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PHY_CLK_PLL_READY BIT(0) ++#define PCIE_INITAL_TIMER GENMASK(6, 3) ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define CFG_SW_PHY_INIT_DONE BIT(11) ++ ++/* Lane RX/TX configuration (per‑lane, at lane_base) */ ++#define PCIE_RX_REG1 0x050 ++#define PCIE_RX_REFCLK_MODE GENMASK(1, 0) ++#define PCIE_RX_REFCLK_MODE_DRIVER 1 ++#define PCIE_RX_SEL_TRI_CODE BIT(2) ++#define PCIE_RX_LEGACY GENMASK(15, 8) ++#define PCIE_RX_LEGACY_DEFAULT 0x65 ++ ++#define PCIE_TX_REG1 0x064 ++ ++#define PCIE_PLL_TIMEOUT 500000 ++#define PCIE_POLL_DELAY 500 ++ ++static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) ++{ ++ struct phy *phy = lg->phy; ++ u32 val, tmp; ++ int ret; ++ ++ /* Do not wait CDR lock before sampling data */ ++ val = readl(base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); ++ writel(val, base + PHY_RESET_CFG); ++ ++ /* Power down 100MHz refclk buffer */ ++ val = readl(base + PHY_PU_CK_REG); ++ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); ++ writel(val, base + PHY_PU_CK_REG); ++ ++ /* Program PLL REG1 configure the SSC */ ++ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | ++ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | ++ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); ++ writel(val, base + PHY_PLL_REG1); ++ ++ /* Un-select 100MHz PLL reference */ ++ val = readl(base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); ++ writel(val, base + PHY_PLL_REG2); ++ ++ /* USB LFPS period configuration */ ++ val = readl(base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); ++ writel(val, base + PHY_MODE_CFG); ++ ++ /* Force AFE adaptation reset */ ++ val = readl(base + PHY_ADPT_CFG0); ++ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; ++ writel(val, base + PHY_ADPT_CFG0); ++ ++ /* Override driver amplitude value to 900m */ ++ val = readl(base + PHY_RXEQ_TIME); ++ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; ++ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); ++ writel(val, base + PHY_RXEQ_TIME); ++ ++ /* Configure RX parameters */ ++ val = PHY_RX_REG0_RLOAD | ++ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | ++ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | ++ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | ++ PHY_RX_REG2_FORCE_CSEL | ++ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | ++ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | ++ PHY_RX_REG3_SEL_CBOOST_CODE | ++ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | ++ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); ++ writel(val, base + PHY_RX_REG_A); ++ ++ val = readl(base + PHY_RX_REG_B); ++ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | ++ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | ++ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | ++ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); ++ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); ++ writel(val, base + PHY_RX_REG_B); ++ ++ /* ++ * Inform PHY that all PLL-related configuration is done. ++ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. ++ */ ++ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | ++ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | ++ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | ++ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; ++ writel(val, base + PHY_CLK_CFG); ++ ++ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), ++ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&phy->dev, "PHY PLL polling timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int k3_usb3phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ int ret, i; ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_usb3_phy_ops = { ++ .init = k3_usb3phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); ++ ++static int k3_pcie_phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ void __iomem *phy_base = lg->base + lg->data->offsets[0]; ++ u32 val; ++ int ret; ++ int i; ++ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, BIT(21)); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ val = readl(lane_base + PCIE_RX_REG1); ++ val = u32_replace_bits(val, 0, 0x3); ++ writel(val, lane_base + PCIE_RX_REG1); ++ } ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val |= BIT(20); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ /* The write is needed as clock requires renegotiation */ ++ val = FIELD_PREP(PCIE_RX_REFCLK_MODE, PCIE_RX_REFCLK_MODE_DRIVER) | ++ PCIE_RX_SEL_TRI_CODE | ++ FIELD_PREP(PCIE_RX_LEGACY, PCIE_RX_LEGACY_DEFAULT); ++ writel(val, phy_base + PCIE_RX_REG1); ++ ++ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0, GENMASK(27, 24)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ ++ val = readl(lane_base + PHY_PU_SEL); ++ val = u32_replace_bits(val, 1, BIT(13)); ++ writel(val, lane_base + PHY_PU_SEL); ++ ++ /* disable en_sample_data_after_cdr_locked */ ++ val = readl(lane_base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, BIT(6)); ++ writel(val, lane_base + PHY_RESET_CFG); ++ ++ /* Dynamic Lock */ ++ val = readl(lane_base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, 1, BIT(2)); ++ writel(val, lane_base + PHY_MODE_CFG); ++ ++ val = FIELD_PREP(PHY_RX_REG0_MASK, 0x10) | ++ FIELD_PREP(PHY_RX_REG1_MASK, 0x78) | ++ FIELD_PREP(PHY_RX_REG2_MASK, 0x98) | ++ FIELD_PREP(PHY_RX_REG3_MASK, 0xdf); ++ writel(val, lane_base + PHY_RX_REG_A); ++ ++ val = readl(lane_base + PHY_RX_REG_B); ++ val &= ~PHY_RX_REGB_MASK; ++ val |= FIELD_PREP(PHY_RX_REG4_MASK, 0xb4) | ++ FIELD_PREP(PHY_RX_REG5_MASK, 0x88) | ++ FIELD_PREP(PHY_RX_REG6_MASK, 0x28); ++ writel(val, lane_base + PHY_RX_REG_B); ++ ++ /* Set init done */ ++ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); ++ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); ++ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); ++ } ++ ++ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, ++ PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_pcie_phy_ops = { ++ .init = k3_pcie_phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); ++ ++/* PHY rcal init requires APB_SPARE regmap access */ ++ ++#define APB_SPARE_PU_CAL 0x178 ++#define PU_CAL BIT(17) ++ ++#define APB_SPARE_RCAL_HSIO 0x17c ++#define APB_SPARE_PU_CAL_DONE BIT(8) ++#define RCAL_OVRD_PTRIM GENMASK(23, 20) ++#define RCAL_OVRD_NTRIM GENMASK(27, 24) ++#define RCAL_OVRD_PTRIM_EN BIT(28) ++#define RCAL_OVRD_NTRIM_EN BIT(29) ++#define RCAL_OVRD_STABLE_VAL BIT(30) ++#define RCAL_OVRD_STABLE_EN BIT(31) ++ ++#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) ++#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) ++ ++#define PU_CAL_TIMEOUT 2000000 ++ ++static DEFINE_MUTEX(calibrate_lock); ++ ++int k3_phy_calibrate(struct regmap *apb_spare) ++{ ++ unsigned int val = 0; ++ int ret; ++ ++ guard(mutex)(&calibrate_lock); ++ ++ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); ++ if (val & APB_SPARE_PU_CAL_DONE) ++ return 0; ++ ++ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, ++ PU_CAL); ++ ++ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, ++ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, ++ PU_CAL_TIMEOUT); ++ ++ if (ret) ++ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | ++ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | ++ RCAL_OVRD_STABLE_EN); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(k3_phy_calibrate); ++ ++MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h +new file mode 100644 +index 000000000000..49009c3c313a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _PHY_K3_COMMON_H ++#define _PHY_K3_COMMON_H ++ ++#include ++ ++struct k3_phy_lane_group_data { ++ u32 lanes; ++ u8 config; ++ u8 mask; ++ u32 offsets[] __counted_by(lanes); ++}; ++ ++struct k3_lane_group { ++ const struct k3_phy_lane_group_data *data; ++ void __iomem *base; ++ struct phy *phy; ++ bool is_pcie; ++}; ++ ++extern const struct phy_ops k3_pcie_phy_ops; ++extern const struct phy_ops k3_usb3_phy_ops; ++ ++int k3_phy_calibrate(struct regmap *apb_spare); ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0530-FROMLIST-gpio-sifive-add-missing-MODULE_DEVICE_TABLE.patch b/SPECS/linux-lts/0530-FROMLIST-gpio-sifive-add-missing-MODULE_DEVICE_TABLE.patch new file mode 100644 index 0000000000..891cf34f03 --- /dev/null +++ b/SPECS/linux-lts/0530-FROMLIST-gpio-sifive-add-missing-MODULE_DEVICE_TABLE.patch @@ -0,0 +1,38 @@ +From b4b8c09ba9b89f134f5d2517191a1cdca3cc4916 Mon Sep 17 00:00:00 2001 +From: Pengpeng Hou +Date: Sat, 4 Jul 2026 20:22:30 +0800 +Subject: [RUYI PATCH] FROMLIST: gpio: sifive: add missing + MODULE_DEVICE_TABLE() + +The driver has an OF match table wired to .of_match_table, but does +not export the table with MODULE_DEVICE_TABLE(). + +Add the missing MODULE_DEVICE_TABLE(of, ...) entry so module alias +information is generated for OF based module autoloading. + +This is a source-level fix. It does not claim dynamic hardware +reproduction; the evidence is the driver-owned match table, its use by +the platform driver, and the missing module alias publication. + +Signed-off-by: Pengpeng Hou +Link: https://lore.kernel.org/r/20260704122230.75964-1-pengpeng@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-sifive.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c +index 94ef2efbd14f..e9a992cd4b9c 100644 +--- a/drivers/gpio/gpio-sifive.c ++++ b/drivers/gpio/gpio-sifive.c +@@ -260,6 +260,7 @@ static const struct of_device_id sifive_gpio_match[] = { + { .compatible = "sifive,fu540-c000-gpio" }, + { }, + }; ++MODULE_DEVICE_TABLE(of, sifive_gpio_match); + + static struct platform_driver sifive_gpio_driver = { + .probe = sifive_gpio_probe, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0531-FROMLIST-PCI-dwc-spacemit-add-missing-MODULE_DEVICE_.patch b/SPECS/linux-lts/0531-FROMLIST-PCI-dwc-spacemit-add-missing-MODULE_DEVICE_.patch new file mode 100644 index 0000000000..3e35d82f3e --- /dev/null +++ b/SPECS/linux-lts/0531-FROMLIST-PCI-dwc-spacemit-add-missing-MODULE_DEVICE_.patch @@ -0,0 +1,38 @@ +From 099f5123116f3b3a4f1b8f9cd14915ed44b718db Mon Sep 17 00:00:00 2001 +From: Pengpeng Hou +Date: Sat, 4 Jul 2026 20:25:38 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: dwc: spacemit: add missing + MODULE_DEVICE_TABLE() + +The driver has an OF match table wired to .of_match_table, but does +not export the table with MODULE_DEVICE_TABLE(). + +Add the missing MODULE_DEVICE_TABLE(of, ...) entry so module alias +information is generated for OF based module autoloading. + +This is a source-level fix. It does not claim dynamic hardware +reproduction; the evidence is the driver-owned match table, its use by +the platform driver, and the missing module alias publication. + +Signed-off-by: Pengpeng Hou +Link: https://lore.kernel.org/r/20260704122538.92830-1-pengpeng@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 680acc93f539..7502d66bd0d0 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -547,6 +547,7 @@ static const struct of_device_id k1_pcie_of_match_table[] = { + { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, + { } + }; ++MODULE_DEVICE_TABLE(of, k1_pcie_of_match_table); + + static struct platform_driver k1_pcie_driver = { + .probe = k1_pcie_probe, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0532-FROMLIST-riscv-stacktrace-Fix-NULL-task-pointer-in-f.patch b/SPECS/linux-lts/0532-FROMLIST-riscv-stacktrace-Fix-NULL-task-pointer-in-f.patch new file mode 100644 index 0000000000..5ef6a82df3 --- /dev/null +++ b/SPECS/linux-lts/0532-FROMLIST-riscv-stacktrace-Fix-NULL-task-pointer-in-f.patch @@ -0,0 +1,51 @@ +From 36246e7cbaca481c4c172427c4e9ab9f202f74c4 Mon Sep 17 00:00:00 2001 +From: Anmeng Zhang +Date: Wed, 8 Jul 2026 09:50:46 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: stacktrace: Fix NULL task pointer in + ftrace_graph_ret_addr() + +When dump_backtrace() is called with a NULL task argument, and the +call stack contains functions that are being traced, +walk_stackframe() eventually calls ftrace_graph_ret_addr() with the +NULL task pointer, which results in a NULL pointer dereference when +accessing task->curr_ret_stack. + +Fix this by assigning the task pointer to the current task in +walk_stackframe() when it is NULL, keeping the behavior consistent +with other architectures. + +Fixes: ecbf894165a2 ("riscv: Fix ftrace_graph_ret_addr() to use the correct task pointer") +Reviewed-by: Shengming Hu +Reviewed-by: Rui Gao +Reviewed-by: Luo Haiyang +Reviewed-by: Run Zhang +Signed-off-by: Anmeng Zhang +Link: https://lore.kernel.org/r/20260708095046716mVQlEvhyoXko9eueCxict@zte.com.cn +Signed-off-by: Han Gao +--- + arch/riscv/kernel/stacktrace.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c +index b41b6255751c..694c9c7fde4a 100644 +--- a/arch/riscv/kernel/stacktrace.c ++++ b/arch/riscv/kernel/stacktrace.c +@@ -52,11 +52,14 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, + int graph_idx = 0; + int level = 0; + ++ if (task == NULL) ++ task = current; ++ + if (regs) { + fp = frame_pointer(regs); + sp = user_stack_pointer(regs); + pc = instruction_pointer(regs); +- } else if (task == NULL || task == current) { ++ } else if (task == current) { + fp = (unsigned long)__builtin_frame_address(0); + sp = current_stack_pointer; + pc = (unsigned long)walk_stackframe; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0533-FROMLIST-riscv-ftrace-only-use-pre-function-NOPs-wit.patch b/SPECS/linux-lts/0533-FROMLIST-riscv-ftrace-only-use-pre-function-NOPs-wit.patch new file mode 100644 index 0000000000..ba10609430 --- /dev/null +++ b/SPECS/linux-lts/0533-FROMLIST-riscv-ftrace-only-use-pre-function-NOPs-wit.patch @@ -0,0 +1,62 @@ +From 9fc49a04adaf2bb83829be405656fa5d613d5a0c Mon Sep 17 00:00:00 2001 +From: Rui Qi +Date: Mon, 6 Jul 2026 20:35:54 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: only use pre-function NOPs with + call ops + +Commit c217157bcd1d ("riscv: Implement +HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS") changed CC_FLAGS_FTRACE to use +-fpatchable-function-entry=8,4 or -fpatchable-function-entry=4,2 +for all dynamic ftrace builds. That layout makes the compiler place an +8-byte area before the function entry, which is used as the per-callsite +ftrace_ops literal when CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS is enabled. + +RISC-V can still build with CONFIG_DYNAMIC_FTRACE=y and +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS=n, for example when +CONFIG_CFI_CLANG is enabled because HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS +is selected only when !CFI_CLANG. In that configuration +ftrace_call_adjust() does not skip the pre-function literal area and +only returns addr + MCOUNT_AUIPC_SIZE. With the pre-function layout, +that points into the pre-entry padding instead of the callsite jalr, so +dynamic ftrace records the wrong patch address. + +Use the pre-function literal layout only when call ops are enabled. +Otherwise keep the previous patchable-function-entry counts so the +recorded address matches ftrace_call_adjust() non-call-ops path. + +Fixes: c217157bcd1d ("riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS") +Cc: stable@vger.kernel.org +Signed-off-by: Rui Qi +Link: https://lore.kernel.org/r/20260706123554.455065-1-qirui.001@bytedance.com +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 775b5faa4b2e..2dbb6e3c78c9 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -14,11 +14,19 @@ endif + ifeq ($(CONFIG_DYNAMIC_FTRACE),y) + LDFLAGS_vmlinux += --no-relax + KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY ++ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS),y) + ifeq ($(CONFIG_RISCV_ISA_C),y) + CC_FLAGS_FTRACE := -fpatchable-function-entry=8,4 + else + CC_FLAGS_FTRACE := -fpatchable-function-entry=4,2 + endif ++else ++ifeq ($(CONFIG_RISCV_ISA_C),y) ++ CC_FLAGS_FTRACE := -fpatchable-function-entry=4 ++else ++ CC_FLAGS_FTRACE := -fpatchable-function-entry=2 ++endif ++endif + endif + + ifeq ($(CONFIG_CMODEL_MEDLOW),y) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0534-FROMLIST-riscv-vdso-Only-try-to-install-vDSO-when-pr.patch b/SPECS/linux-lts/0534-FROMLIST-riscv-vdso-Only-try-to-install-vDSO-when-pr.patch new file mode 100644 index 0000000000..5a02241193 --- /dev/null +++ b/SPECS/linux-lts/0534-FROMLIST-riscv-vdso-Only-try-to-install-vDSO-when-pr.patch @@ -0,0 +1,38 @@ +From 2b8b9475a2f3b59d8c0181d57e39de5dbb38f138 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Thu, 9 Jul 2026 08:49:00 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: vdso: Only try to install vDSO when + present +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +vdso.so.dbg is only built with CONFIG_MMU. + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202607090258.iSAUYlO1-lkp@intel.com/ +Fixes: f157d411a9eb ("riscv: add missing vdso_install target") +Fixes: 3edf39916977 ("vDSO, kbuild: Provide vDSO debug variants at runtime") +Signed-off-by: Thomas Weißschuh +Link: https://lore.kernel.org/r/20260709-riscv-install-vdso-v1-1-0ba4345419ca@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 2dbb6e3c78c9..1256e91714ef 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -172,7 +172,7 @@ vdso_prepare: prepare0 + endif + endif + +-vdso-install-y += arch/riscv/kernel/vdso/vdso.so.dbg ++vdso-install-$(CONFIG_MMU) += arch/riscv/kernel/vdso/vdso.so.dbg + vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg + + BOOT_TARGETS := Image Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zst Image.xz loader loader.bin xipImage vmlinuz.efi +-- +2.53.0 + diff --git a/SPECS/linux-lts/0535-FROMLIST-riscv-dts-spacemit-k3-add-USB-controller-an.patch b/SPECS/linux-lts/0535-FROMLIST-riscv-dts-spacemit-k3-add-USB-controller-an.patch new file mode 100644 index 0000000000..d1a7910ed0 --- /dev/null +++ b/SPECS/linux-lts/0535-FROMLIST-riscv-dts-spacemit-k3-add-USB-controller-an.patch @@ -0,0 +1,110 @@ +From 15cf4e848cdfd439dc8f1be567b3141aba5aa4dd Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:04:13 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add USB controller + and USB phy support + +Add all USB device node to the Spacemit K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040415.977784-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index c7ecb2f5cb4d..c418cd4fb7d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -220,6 +220,11 @@ dldo7: dldo7 { + }; + }; + ++&combophy { ++ spacemit,apmu = <&syscon_apmu 0x11>; ++ status = "okay"; ++}; ++ + ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; +@@ -318,6 +323,14 @@ &usb2_phy { + status = "okay"; + }; + ++&usb3d_u2phy { ++ status = "okay"; ++}; ++ ++&usb3d { ++ status = "okay"; ++}; ++ + &ufshc { + status = "okay"; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 862e5698972e..ef75a70c94a0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + /dts-v1/; + +@@ -438,6 +439,47 @@ soc: soc { + dma-noncoherent; + ranges; + ++ usb3d: usb@81a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81a00000 0x0 0x10000>; ++ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_D_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_D_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3d_u2phy>, ++ <&combophy 4 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3d_u2phy: phy@81b00000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81b00000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combophy: phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x0 0x81d00000 0x0 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&pll>; ++ status = "disabled"; ++ }; ++ + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0536-FROMLIST-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts/0536-FROMLIST-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch new file mode 100644 index 0000000000..fa574ac96c --- /dev/null +++ b/SPECS/linux-lts/0536-FROMLIST-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch @@ -0,0 +1,318 @@ +From 9f73b927d59d145d16de86b92fa0375f38c2e133 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 9 Jul 2026 12:04:14 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add PCIe device node + +Add all PCIe device node for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260709040415.977784-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 195 +++++++++++++++++++ + 3 files changed, 266 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index c418cd4fb7d6..cb51126bf4e4 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -301,6 +301,44 @@ uboot@210000 { + }; + }; + ++&pcie0_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_0_cfg>; ++ num-lanes = <4>; ++ status = "okay"; ++ ++ pcie@0 { ++ vpcie3v3-supply = <®_aux_vcc3v3>; ++ phys = <&combophy 0 PHY_TYPE_PCIE>, ++ <&combophy 1 PHY_TYPE_PCIE>; ++ }; ++}; ++ ++&pcie2_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_cfg>; ++ num-lanes = <2>; ++ status = "okay"; ++ ++ pcie@0 { ++ vpcie3v3-supply = <®_aux_vcc3v3>; ++ phys = <&combophy 2 PHY_TYPE_PCIE>, ++ <&combophy 3 PHY_TYPE_PCIE>; ++ }; ++}; ++ ++&pcie4_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie4_0_cfg>; ++ num-lanes = <1>; ++ status = "okay"; ++ ++ pcie@0 { ++ vpcie3v3-supply = <®_aux_vcc3v3>; ++ phys = <&combophy 5 PHY_TYPE_PCIE>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 5b9045e01434..746eb2ee1799 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -722,6 +722,39 @@ uart0-0-pins { + }; + }; + ++ pcie0_0_cfg: pcie0-0-cfg { ++ pcie0-0-pins { ++ pinmux = , /* pcie0 perst */ ++ ; /* pcie0 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ pcie2_0_cfg: pcie2-0-cfg { ++ pcie2-0-pins { ++ pinmux = , /* pcie2 perst */ ++ ; /* pcie2 clkreq */ ++ ++ drive-strength = <38>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ pcie4_0_cfg: pcie4-0-cfg { ++ pcie4-0-pins { ++ pinmux = , /* pcie4 perst */ ++ , /* pcie4 wake */ ++ ; /* pcie4 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ + mmc1_cfg: mmc1-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1 dat3 */ +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index ef75a70c94a0..d7beabc88d86 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -439,6 +439,201 @@ soc: soc { + dma-noncoherent; + ranges; + ++ pcie0_rc: pcie@80000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80000000 0x0 0x00001000>, ++ <0x0 0x80300000 0x0 0x00003f20>, ++ <0x11 0x00000000 0x0 0x00010000>, ++ <0x0 0x82900000 0x0 0x00001000>, ++ <0x0 0x80100000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ max-link-speed = <3>; ++ linux,pci-domain = <0>; ++ spacemit,apmu = <&syscon_apmu 0x1f0>; ++ status = "disabled"; ++ ++ pcie0_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie1_rc: pcie@80400000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80400000 0x0 0x00001000>, ++ <0x0 0x80700000 0x0 0x00003f20>, ++ <0x11 0x80000000 0x0 0x00010000>, ++ <0x0 0x82c00000 0x0 0x00001000>, ++ <0x0 0x80500000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, ++ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ max-link-speed = <3>; ++ linux,pci-domain = <1>; ++ spacemit,apmu = <&syscon_apmu 0x1d0>; ++ status = "disabled"; ++ ++ pcie1_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie2_rc: pcie@80800000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80800000 0x0 0x00001000>, ++ <0x0 0x80b00000 0x0 0x00003f20>, ++ <0x12 0x00000000 0x0 0x00010000>, ++ <0x0 0x82d00000 0x0 0x00001000>, ++ <0x0 0x80900000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <2>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1c8>; ++ status = "disabled"; ++ ++ pcie2_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie3_rc: pcie@80c00000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80c00000 0x0 0x00001000>, ++ <0x0 0x80f00000 0x0 0x00003f20>, ++ <0x12 0x80000000 0x0 0x00010000>, ++ <0x0 0x82a00000 0x0 0x00001000>, ++ <0x0 0x80d00000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, ++ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, ++ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e0>; ++ status = "disabled"; ++ ++ pcie3_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie4_rc: pcie@81000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x81000000 0x0 0x00001000>, ++ <0x0 0x81300000 0x0 0x00003f20>, ++ <0x12 0xc0000000 0x0 0x00010000>, ++ <0x0 0x82b00000 0x0 0x00001000>, ++ <0x0 0x81100000 0x0 0x00001000>; ++ reg-names = "dbi", "atu", "config", "link", "dbi2"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, ++ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, ++ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <4>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e8>; ++ status = "disabled"; ++ ++ pcie4_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0537-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch b/SPECS/linux-lts/0537-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch new file mode 100644 index 0000000000..f5c6df9f57 --- /dev/null +++ b/SPECS/linux-lts/0537-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch @@ -0,0 +1,35 @@ +From a188bbf049589da3b44ddaf65000884f2167e955 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 10 Jul 2026 14:33:12 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add enough deassert time + for the PHY on PICO ITX + +RTL8211F require at least 50ms deassert to guarantee the register +access, 10ms is only enough for the PHY reset. + +Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") +Signed-off-by: Inochi Amaoto +Tested-by: E Shattow +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260710063314.1030249-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index cb51126bf4e4..c412f7002011 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -238,7 +238,7 @@ phy0: phy@1 { + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; +- reset-deassert-us = <10000>; ++ reset-deassert-us = <50000>; + realtek,aldps-enable; + realtek,clkout-disable; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0538-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch b/SPECS/linux-lts/0538-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch new file mode 100644 index 0000000000..62f0422014 --- /dev/null +++ b/SPECS/linux-lts/0538-FROMLIST-riscv-dts-spacemit-Add-enough-deassert-time.patch @@ -0,0 +1,33 @@ +From 581d3a2a0e3383f2f9f006c11205d1c5d7d00c91 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 10 Jul 2026 14:33:13 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add enough deassert time + for the PHY on com260 board + +RTL8211F require at least 50ms deassert to guarantee the register +access, 10ms is only enough for the PHY reset. + +Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260710063314.1030249-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +index a38d7b738258..b704b537385c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +@@ -178,7 +178,7 @@ phy1: phy@1 { + reg = <1>; + reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; +- reset-deassert-us = <10000>; ++ reset-deassert-us = <50000>; + }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0539-FROMLIST-Failed-to-reinit-phy-of-spacemit-dwmac-when.patch b/SPECS/linux-lts/0539-FROMLIST-Failed-to-reinit-phy-of-spacemit-dwmac-when.patch new file mode 100644 index 0000000000..19b5cf5d50 --- /dev/null +++ b/SPECS/linux-lts/0539-FROMLIST-Failed-to-reinit-phy-of-spacemit-dwmac-when.patch @@ -0,0 +1,74 @@ +From d038896e5e76e45986dcd757f2aa2eb062d59aba Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 12 Jul 2026 12:52:33 +0800 +Subject: [RUYI PATCH] FROMLIST: Failed to reinit phy of spacemit-dwmac when + reset-gpio is present + +TL;DR: + +The DWMAC on Spacemit K3 is failled to register phy after the reload +the driver module (rmmod then insmod). Because the reset-gpio is +asserted while unloading the driver and is not desserted before reading +the c22 id, which leads to a fault. + +Description + +In a few days ago, E Shattow reports he has sufferred the a weird issue, +when unloading the spacemit-dwmac driver and then reloading it, he got +the following error: + +[ 60.713071] mdio_bus stmmac-0: MDIO device at address 1 is missing. + +This only occurs when reloading the driver but the first initialization +successed. After some function tracking, I found it is failed at reading +c22 id. The call graph is as the follows: + +stmmac_mdio_register + mdiobus_alloc + of_mdiobus_register + __of_mdiobus_register + __mdiobus_register + __of_mdiobus_parse_phys + of_mdiobus_child_is_phy + of_mdiobus_register_phy + fwnode_mdiobus_register_phy + get_phy_device + get_phy_c22_id + +By checking the difference between the initialization process and the +reloading process, I found the reset gpio is asserted in the function +mdiobus_unregister(). And there is no any function desserted this reset +gpio in the loading stage. And in the initialization process, the reset +goio is deasserted. + +This bug report is sent as I found it is hard to solve this problem +and ask for help to fix this issue as it is related to the framework +instead of a specific driver. + +The possible workaround I found is as the following, just use the phy +id in the compatible string (Confirmed by dlan): + +Tested-by: E Shattow +Link: https://lore.kernel.org/r/20260712045233.800748-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index c412f7002011..7327eb65593c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -234,7 +234,8 @@ ð0 { + + mdio { + phy0: phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; ++ compatible = "ethernet-phy-id001c.c916", ++ "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0540-FROMLIST-riscv-mm-Make-mark_new_valid_map-stuff-depe.patch b/SPECS/linux-lts/0540-FROMLIST-riscv-mm-Make-mark_new_valid_map-stuff-depe.patch new file mode 100644 index 0000000000..e5a2ec8689 --- /dev/null +++ b/SPECS/linux-lts/0540-FROMLIST-riscv-mm-Make-mark_new_valid_map-stuff-depe.patch @@ -0,0 +1,68 @@ +From 346dbf0541b3086cf6e288aa170f5d4cae692dff Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 13 Jul 2026 14:15:20 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Make mark_new_valid_map() stuff + depend on 64BIT && MMU + +None of the code relating to mark_new_valid_map() does anything useful +without CONFIG_64BIT=y && CONFIG_MMU=y, because the +new_valid_map_cpus_check code is only used if CONFIG_64BIT, and the +exception codes checked there can only happen with CONFIG_MMU=y. + +Therefore, make these conditional on CONFIG_64BIT=y && CONFIG_MMU=y to +simplify programming, since we do not have to handle CONFIG_MMU=n when +changing this code in the future. This also removes some unused code on +the entry path for CONFIG_MMU=n. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260713-mark-after-vmemmap-populate-v6-1-b945ceba29d4@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 2 +- + arch/riscv/kernel/entry.S | 2 +- + arch/riscv/mm/init.c | 2 ++ + 3 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 1f191cf801a2..939ac3b61ff2 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -42,7 +42,7 @@ do { \ + flush_icache_mm(vma->vm_mm, 0); \ + } while (0) + +-#ifdef CONFIG_64BIT ++#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) + /* This is accessed in assembly code. cpumask_var_t would be too complex. */ + extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 5a97f002bf1f..df3f720ad61f 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -112,7 +112,7 @@ SYM_CODE_START(handle_exception) + .Lrestore_kernel_tpsp: + csrr tp, CSR_SCRATCH + +-#ifdef CONFIG_64BIT ++#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) + /* + * The RISC-V kernel does not flush TLBs on all CPUS after each new + * vmalloc mapping or kfence_unprotect(), which may result in +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index f10c37999f23..715575f68c69 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,9 @@ + + #include "../kernel/head.h" + ++#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) + DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); ++#endif + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0541-FROMLIST-mm-sparse-vmemmap-flush_cache_vmap-after-ho.patch b/SPECS/linux-lts/0541-FROMLIST-mm-sparse-vmemmap-flush_cache_vmap-after-ho.patch new file mode 100644 index 0000000000..41989f347a --- /dev/null +++ b/SPECS/linux-lts/0541-FROMLIST-mm-sparse-vmemmap-flush_cache_vmap-after-ho.patch @@ -0,0 +1,65 @@ +From 0c338eb602e2a4922a7c4f5c6ddc9f58bf0fc53f Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 13 Jul 2026 14:15:21 +0800 +Subject: [RUYI PATCH] FROMLIST: mm/sparse-vmemmap: flush_cache_vmap() after + hotplugging vmemmap + +section_activate() does not flush TLB after populating new vmemmap +pages. On most architectures, this is okay. However it is a problem on +RISC-V since there the TLB caching non-present entries is permitted, +which causes spurious faults on some hardwares. + +This seems to be most easily reproduced with DEBUG_VM=y and +PAGE_POISONING=y, which causes these newly mapped struct pages to be +poisoned i.e. written to immediately after mapping. + +Extend the RISC-V flush_cache_vmap() to also handle the vmemmap range, +and call it after hotplugging vmemmap, which gets the possible spurious +fault handled in the exception handler. + +At least for now, the only other architecture with both +SPARSEMEM_VMEMMAP and flush_cache_vmap() is PowerPC, which has a similar +problem with newly valid PTEs. But there flush_cache_vmap() is just a +ptesync. So it should be safe to do this for generic code while having +minimal performance impact. + +Suggested-by: Muchun Song +Signed-off-by: Vivian Wang +Reviewed-by: Muchun Song +Link: https://lore.kernel.org/r/20260713-mark-after-vmemmap-populate-v6-2-b945ceba29d4@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 3 ++- + mm/sparse-vmemmap.c | 2 ++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 939ac3b61ff2..c6297a1d2645 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -69,7 +69,8 @@ static inline void mark_new_valid_map(void) + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) + { +- if (is_vmalloc_or_module_addr((void *)start)) ++ if (is_vmalloc_or_module_addr((void *)start) || ++ (start >= VMEMMAP_START && end <= VMEMMAP_END)) + mark_new_valid_map(); + } + #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) +diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c +index 37522d6cb398..c9328cc59f52 100644 +--- a/mm/sparse-vmemmap.c ++++ b/mm/sparse-vmemmap.c +@@ -578,6 +578,8 @@ struct page * __meminit __populate_section_memmap(unsigned long pfn, + if (r < 0) + return NULL; + ++ flush_cache_vmap(start, end); ++ + return pfn_to_page(pfn); + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0542-FROMLIST-riscv-mm-Move-dma_contiguous_reserve-after-.patch b/SPECS/linux-lts/0542-FROMLIST-riscv-mm-Move-dma_contiguous_reserve-after-.patch new file mode 100644 index 0000000000..7a0a505a97 --- /dev/null +++ b/SPECS/linux-lts/0542-FROMLIST-riscv-mm-Move-dma_contiguous_reserve-after-.patch @@ -0,0 +1,73 @@ +From f895bb784a54d2b918908ac5c9e04f01ae403ed5 Mon Sep 17 00:00:00 2001 +From: Eder Zulian +Date: Tue, 14 Jul 2026 20:56:48 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Move dma_contiguous_reserve() after + NUMA initialization + +Move the dma_contiguous_reserve() call from setup_bootmem() to +misc_mem_init(), placing it after arch_numa_init(). This ensures that +NUMA topology is initialized when reserving contiguous memory for DMA. + +Tested with CMA_SIZE_PERNUMA enabled and two NUMA nodes on QEMU: + +qemu-system-riscv64 \ + -machine virt \ + -nographic \ + -smp 2 -m 512M \ + -numa node,nodeid=0,cpus=0,memdev=m0 \ + -numa node,nodeid=1,cpus=1,memdev=m1 \ + -object memory-backend-ram,id=m0,size=256M \ + -object memory-backend-ram,id=m1,size=256M \ + -kernel arch/riscv/boot/Image \ + -append "console=ttyS0 earlycon loglevel=7 cma=16M" + +Unpatched kernel's log (one global CMA pool and no per-nodepools, 16 MiB +cma-reserved): + + [ 0.000000] cma: Reserved 16 MiB at 0x000000009ee00000 + ... + [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] + [ 0.000000] Initmem setup node 1 [mem 0x0000000090000000-0x000000009fffffff] + ... + [ 0.056397] smp: Brought up 2 nodes, 2 CPUs + [ 0.066135] Memory: 449288K/524288K available (12279K kernel code, 5980K rwdata, 6144K rodata, 2467K init, 482K bss, 54504K reserved, 16384K cma-reserved) + +Patched kernel's log (three CMA pools are created, 48 MiB total), + + [ 0.000000] cma: Reserved 16 MiB at 0x000000009ee00000 + [ 0.000000] cma: Reserved 16 MiB at 0x000000008ee00000 + [ 0.000000] cma: Reserved 16 MiB at 0x000000009de00000 + ... + [ 0.054251] smp: Brought up 2 nodes, 2 CPUs + [ 0.064082] Memory: 416520K/524288K available (12279K kernel code, 5980K rwdata, 6144K rodata, 2467K init, 482K bss, 54504K reserved, 49152K cma-reserved) + +Signed-off-by: Eder Zulian +Link: https://lore.kernel.org/r/20260714185648.1082483-1-ezulian@redhat.com +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 715575f68c69..6b5be15b941c 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -322,7 +322,6 @@ static void __init setup_bootmem(void) + if (!IS_ENABLED(CONFIG_BUILTIN_DTB)) + memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va)); + +- dma_contiguous_reserve(dma32_phys_limit); + if (IS_ENABLED(CONFIG_64BIT)) + hugetlb_cma_reserve(PUD_SHIFT - PAGE_SHIFT); + } +@@ -1472,6 +1471,7 @@ void __init misc_mem_init(void) + { + early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT); + arch_numa_init(); ++ dma_contiguous_reserve(dma32_phys_limit); + sparse_init(); + #ifdef CONFIG_SPARSEMEM_VMEMMAP + /* The entire VMEMMAP region has been populated. Flush TLB for this region */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0543-FROMLIST-dt-bindings-soc-spacemit-k3-add-i2s_sysclk-.patch b/SPECS/linux-lts/0543-FROMLIST-dt-bindings-soc-spacemit-k3-add-i2s_sysclk-.patch new file mode 100644 index 0000000000..bfd5438937 --- /dev/null +++ b/SPECS/linux-lts/0543-FROMLIST-dt-bindings-soc-spacemit-k3-add-i2s_sysclk-.patch @@ -0,0 +1,40 @@ +From fd4bdd7000033cfca5f88d4d2c727472ab1fb809 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 17 Jul 2026 00:26:01 -0700 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: add + i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs + +Add three new clock IDs to expose clocks introduced by the topology fix: +- CLK_MPMU_I2S_SYSCLK (51): the common i2s sysclk DDN at MPMU_ISCCR1 +- CLK_MPMU_I2S_BCLK_FACTOR (52): the implicit /2 factor feeding i2s_bclk +- CLK_MPMU_I2S1_SYSCLK_SRC (53): the dedicated i2s1 sysclk source mux + +CLK_MPMU_I2S1_SYSCLK keeps its existing ID (47) but will be repointed to +the real per-instance i2s1 clock in a subsequent patch. No in-tree user +references this ID so the semantic change is contained. + +Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support") +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260717-k3-clk-fix-i2s-v1-1-e95001a692ee@linux.spacemit.com +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index 69978ab0b29f..4f1099f5da1c 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -145,6 +145,9 @@ + #define CLK_MPMU_I2S3_SYSCLK 48 + #define CLK_MPMU_I2S4_SYSCLK 49 + #define CLK_MPMU_I2S5_SYSCLK 50 ++#define CLK_MPMU_I2S_SYSCLK 51 ++#define CLK_MPMU_I2S_BCLK_FACTOR 52 ++#define CLK_MPMU_I2S1_SYSCLK_SRC 53 + + /* APBC clocks */ + #define CLK_APBC_UART0 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0544-FROMLIST-clk-spacemit-k3-fix-i2s-clock-topology.patch b/SPECS/linux-lts/0544-FROMLIST-clk-spacemit-k3-fix-i2s-clock-topology.patch new file mode 100644 index 0000000000..21d74b826a --- /dev/null +++ b/SPECS/linux-lts/0544-FROMLIST-clk-spacemit-k3-fix-i2s-clock-topology.patch @@ -0,0 +1,115 @@ +From 65c0b62e10c2a882cc56375fff81db28f94cf8db Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 17 Jul 2026 00:26:02 -0700 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix i2s clock topology + +The K3 i2s clocks were modelled as a single path behind one MPMU +register: + + pll1_d96_25p6 / i2s_153p6_base + `-- i2s_sysclk_src (mux+gate, MPMU_ISCCR) + `-- i2s1_sysclk (DDN, MPMU_ISCCR) + |-- i2s_bclk (div+gate, MPMU_ISCCR) + `-- i2s2_sysclk (mux, parent 0) + +The hardware actually has two i2s clock control registers, ISCCR0 +(0x0040) and ISCCR1 (0x0044): ISCCR1 drives the common sysclk shared +by i2s0/2/3/4/5 and the common bclk, whose divider always implies a +fixed 1/2 factor in front, while ISCCR0 drives a dedicated path for +i2s1: + + pll1_d96_25p6 / i2s_153p6_base + |-- i2s_sysclk_src (mux+gate, MPMU_ISCCR1) + | `-- i2s_sysclk (DDN, MPMU_ISCCR1) + | |-- i2s_bclk_factor (fixed factor, /2) + | | `-- i2s_bclk (div+gate, MPMU_ISCCR1) + | `-- i2s2_sysclk (mux, parent 0) + `-- i2s1_sysclk_src (mux+gate, MPMU_ISCCR0) + `-- i2s1_sysclk (DDN, MPMU_ISCCR0) + +Because of this mismatch, i2s_bclk reported twice the real rate, and +the dedicated i2s1 clock path could not be described in DT at all. + +Model the tree as above: split the MPMU_ISCCR register macro into +MPMU_ISCCR0 and MPMU_ISCCR1 to match the hardware register names, +rename the common DDN to i2s_sysclk, insert the fixed 1/2 factor +i2s_bclk_factor in front of i2s_bclk, and add the i2s1_sysclk_src mux +and i2s1_sysclk DDN backed by MPMU_ISCCR0. CLK_MPMU_I2S1_SYSCLK now +refers to the dedicated i2s1 clock; no in-tree user references this +ID, so nothing is affected by the change of meaning. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260717-k3-clk-fix-i2s-v1-2-e95001a692ee@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 21 ++++++++++++++++----- + include/soc/spacemit/k3-syscon.h | 3 ++- + 2 files changed, 18 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 5d0e31f07d6d..5cb14349358a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -218,11 +218,19 @@ static const struct clk_parent_data i2s_sysclk_src_parents[] = { + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(i2s_153p6_base), + }; +-CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); ++CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR1, 30, 1, BIT(31), 0); + +-CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); ++CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR1, 0, 15, 15, 12, 1, 0); + +-CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0); ++CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1); ++/* ++ * Divider of i2s_bclk always implies a 1/2 factor, which is ++ * described by i2s_bclk_factor. ++ */ ++CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR1, 27, 2, BIT(29), 0); ++ ++CCU_MUX_GATE_DEFINE(i2s1_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR0, 30, 1, BIT(31), 0); ++CCU_DDN_DEFINE(i2s1_sysclk, i2s1_sysclk_src, MPMU_ISCCR0, 0, 15, 15, 12, 1, 0); + + static const struct clk_parent_data i2s_sysclk_parents[] = { + CCU_PARENT_HW(pll1_d4_614p4), +@@ -243,7 +251,7 @@ CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16 + CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); + + static const struct clk_parent_data i2s2_sysclk_parents[] = { +- CCU_PARENT_HW(i2s1_sysclk), ++ CCU_PARENT_HW(i2s_sysclk), + CCU_PARENT_HW(i2s2_sysclk_div), + }; + CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); +@@ -1162,8 +1170,11 @@ static struct clk_hw *k3_ccu_mpmu_hws[] = { + [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, + [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, + [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, +- [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, ++ [CLK_MPMU_I2S_SYSCLK] = &i2s_sysclk.common.hw, ++ [CLK_MPMU_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw, + [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK_SRC] = &i2s1_sysclk_src.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, + [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, + [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, + [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +index a68255dd641f..959d8d0786fe 100644 +--- a/include/soc/spacemit/k3-syscon.h ++++ b/include/soc/spacemit/k3-syscon.h +@@ -45,7 +45,8 @@ + #define POSR_PLL7_LOCK BIT(30) + #define POSR_PLL8_LOCK BIT(31) + #define MPMU_SUCCR 0x0014 +-#define MPMU_ISCCR 0x0044 ++#define MPMU_ISCCR0 0x0040 ++#define MPMU_ISCCR1 0x0044 + #define MPMU_WDTPCR 0x0200 + #define MPMU_RIPCCR 0x0210 + #define MPMU_ACGR 0x1024 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0545-FROMLIST-clk-spacemit-k3-fix-missing-2-factor-in-i2s.patch b/SPECS/linux-lts/0545-FROMLIST-clk-spacemit-k3-fix-missing-2-factor-in-i2s.patch new file mode 100644 index 0000000000..c204c1a71f --- /dev/null +++ b/SPECS/linux-lts/0545-FROMLIST-clk-spacemit-k3-fix-missing-2-factor-in-i2s.patch @@ -0,0 +1,46 @@ +From 98f95b9befc76bbe97a77e195f2379b1ff67b242 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 17 Jul 2026 00:26:03 -0700 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix missing /2 factor in + i2s sysclk dividers + +The i2s{0,2,3,4,5}_sysclk_div DDNs have an additional fixed 1/2 +divider in the hardware IP after the configurable divider, so the +real output rate is: + + rate = parent_rate * num / (den * 2) + +Set pre_div to 2 to account for it. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260717-k3-clk-fix-i2s-v1-3-e95001a692ee@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 5cb14349358a..972499084d3a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -244,11 +244,11 @@ CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, + CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); + CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); + +-CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); +-CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 2, 0); ++CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 2, 0); + + static const struct clk_parent_data i2s2_sysclk_parents[] = { + CCU_PARENT_HW(i2s_sysclk), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0546-FROMLIST-riscv-defconfig-enable-RFKILL-and-RFKILL_GP.patch b/SPECS/linux-lts/0546-FROMLIST-riscv-defconfig-enable-RFKILL-and-RFKILL_GP.patch new file mode 100644 index 0000000000..57b9331fbd --- /dev/null +++ b/SPECS/linux-lts/0546-FROMLIST-riscv-defconfig-enable-RFKILL-and-RFKILL_GP.patch @@ -0,0 +1,32 @@ +From 4b6155e2dea7292e4daa582ebea5a0a8c24f7e98 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:01 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: defconfig: enable RFKILL and + RFKILL_GPIO + +The SpacemiT K3 Pico-ITX requires RFKILL_GPIO to enable Bluetooth and +WLAN. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-2-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/configs/defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig +index 140c12d4ab15..d68b4ed087f7 100644 +--- a/arch/riscv/configs/defconfig ++++ b/arch/riscv/configs/defconfig +@@ -97,6 +97,8 @@ CONFIG_NET_CLS_CGROUP=m + CONFIG_NETLINK_DIAG=y + CONFIG_CGROUP_NET_PRIO=y + CONFIG_CAN=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_GPIO=m + CONFIG_NET_9P=y + CONFIG_NET_9P_VIRTIO=y + CONFIG_PCI=y +-- +2.53.0 + diff --git a/SPECS/linux-lts/0547-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-B.patch b/SPECS/linux-lts/0547-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-B.patch new file mode 100644 index 0000000000..4b550bd706 --- /dev/null +++ b/SPECS/linux-lts/0547-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-B.patch @@ -0,0 +1,40 @@ +From b6510b4dfc53a0394f8a382a793f34a3d57faa75 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:02 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add rfkill node for + Bluetooth on Pico-ITX board + +On the K3 PICO-ITX board, by default the GPIO pin that connects to the +RTL8852BE Bluetooth enable signal is driven low, resulting in +impossibility to use Bluetooth. Add a DT node to expose it as an RFKILL +device, which lets the Bluetooth driver or userspace toggle it as +required. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-3-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 7327eb65593c..df6b6201ecc2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -43,6 +43,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ rfkill-usb-bt { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-usb-bt"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio 0 30 GPIO_ACTIVE_HIGH>; ++ }; + }; + + &i2c2 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0548-FROMLIST-riscv-dts-spacemit-k3-add-USB3-B-and-C-cont.patch b/SPECS/linux-lts/0548-FROMLIST-riscv-dts-spacemit-k3-add-USB3-B-and-C-cont.patch new file mode 100644 index 0000000000..6f45293fbe --- /dev/null +++ b/SPECS/linux-lts/0548-FROMLIST-riscv-dts-spacemit-k3-add-USB3-B-and-C-cont.patch @@ -0,0 +1,131 @@ +From 9214c50c885eec7cf26576a52e6223328661f38f Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:03 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add USB3 B and C + controllers for Pico-ITX board + +The SpacemiT K3 has 4 USB3 controllers labelled A to D. + +On the K3 Pico-ITX board, the controllers B and C are used in USB 2 mode +only respectively for the M.2 B-Key slot and for the RTL8852BE Bluetooth +controller. + +Add the two controller nodes and the two corresponding USB2 PHY nodes +(the PCIe/USB3 combo PHY driver is not yet merged) and enable them on +the K3 Pico-ITX board. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-4-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 18 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 64 ++++++++++++++++++++ + 2 files changed, 82 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index df6b6201ecc2..e60d57b0891b 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -369,6 +369,24 @@ &usb2_phy { + status = "okay"; + }; + ++&usb3b { ++ maximum-speed = "high-speed"; ++ status = "okay"; ++}; ++ ++&usb3b_u2phy { ++ status = "okay"; ++}; ++ ++&usb3c { ++ maximum-speed = "high-speed"; ++ status = "okay"; ++}; ++ ++&usb3c_u2phy { ++ status = "okay"; ++}; ++ + &usb3d_u2phy { + status = "okay"; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index d7beabc88d86..ab3d71282da0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -634,6 +634,70 @@ pcie4_port: pcie@0 { + }; + }; + ++ usb3b: usb@81400000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81400000 0x0 0x10000>; ++ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_B_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_B_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_B_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3b_u2phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3b_u2phy: phy@81500000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81500000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usb3c: usb@81700000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81700000 0x0 0x10000>; ++ interrupts = <148 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_C_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_C_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_C_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3c_u2phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3c_u2phy: phy@81800000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81800000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0549-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-W.patch b/SPECS/linux-lts/0549-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-W.patch new file mode 100644 index 0000000000..130dac55f1 --- /dev/null +++ b/SPECS/linux-lts/0549-FROMLIST-riscv-dts-spacemit-k3-add-rfkill-node-for-W.patch @@ -0,0 +1,39 @@ +From 67d1a5fa2166dfbf9e09392ded5bfdc1e0dad09d Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 16 Jul 2026 23:19:04 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: add rfkill node for + WLAN on Pico-ITX board + +By default the GPIO pin that connects to the RTL8852BE WLAN enable +signal is driven low, resulting in impossibility to connect to any +network. Add a DT node to expose it as an RFKILL device, which lets the +WiFi driver or userspace toggle it as required. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260716213314.3027969-5-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index e60d57b0891b..9dd60d1acb34 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -44,6 +44,13 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-always-on; + }; + ++ rfkill-pcie-wlan { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-pcie-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio 1 3 GPIO_ACTIVE_HIGH>; ++ }; ++ + rfkill-usb-bt { + compatible = "rfkill-gpio"; + label = "rfkill-usb-bt"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0550-FROMLIST-riscv-require-vmemmap-for-NUMA-balancing.patch b/SPECS/linux-lts/0550-FROMLIST-riscv-require-vmemmap-for-NUMA-balancing.patch new file mode 100644 index 0000000000..370297dff6 --- /dev/null +++ b/SPECS/linux-lts/0550-FROMLIST-riscv-require-vmemmap-for-NUMA-balancing.patch @@ -0,0 +1,46 @@ +From 9cc01243978429e6a17c49ccfeaa9840edf79858 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 16 Jul 2026 14:47:10 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: require vmemmap for NUMA balancing + +RISC-V randconfig can enable NUMA balancing while selecting +SPARSEMEM_EXTREME without SPARSEMEM_VMEMMAP. In that layout, the +section and node fields can consume enough page flag bits that +LAST_CPUPID cannot fit in page->flags. + +The generic MM code then stores last_cpupid in struct page and emits +the "Unfortunate NUMA and NUMA Balancing config" warning from +mm/memory.c. + +NUMA balancing needs LAST_CPUPID storage, but this fallback grows +struct page for a configuration that randconfig can select +accidentally. Keep NUMA support available, but advertise RISC-V NUMA +balancing support only when SPARSEMEM_VMEMMAP is enabled, where the +page flag layout leaves room for LAST_CPUPID. + +This was originally seen with a RISC-V randconfig generated from +KCONFIG_SEED=550012. + +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260716-numa_kconfig-v1-1-b0cd6d29accb@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index afdd6f6a05f6..8832a62b356d 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -486,7 +486,7 @@ endchoice + config NUMA + bool "NUMA Memory Allocation and Scheduler Support" + depends on SMP && MMU +- select ARCH_SUPPORTS_NUMA_BALANCING ++ select ARCH_SUPPORTS_NUMA_BALANCING if SPARSEMEM_VMEMMAP + select GENERIC_ARCH_NUMA + select HAVE_SETUP_PER_CPU_AREA + select NEED_PER_CPU_EMBED_FIRST_CHUNK +-- +2.53.0 + diff --git a/SPECS/linux-lts/0551-FROMLIST-riscv-time-Add-missing-__iomem-in-get_cycle.patch b/SPECS/linux-lts/0551-FROMLIST-riscv-time-Add-missing-__iomem-in-get_cycle.patch new file mode 100644 index 0000000000..3b18eef6c5 --- /dev/null +++ b/SPECS/linux-lts/0551-FROMLIST-riscv-time-Add-missing-__iomem-in-get_cycle.patch @@ -0,0 +1,43 @@ +From 23a2e3ab76e9a1c0adc1d4d69cb0d5c722ac491d Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Thu, 16 Jul 2026 07:33:19 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: time: Add missing __iomem in + get_cycles() and get_cycles_hi() + +__iomem is missing while calling readl_relaxed() in get_cycles() and +get_cycles_hi() and sparse complains. + +Add __iomem to silence the sparse warnings. + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202607160619.14G8GHp5-lkp@intel.com/ +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/20260716053319.2178937-1-namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/timex.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h +index a06697846e69..d41acfb3959d 100644 +--- a/arch/riscv/include/asm/timex.h ++++ b/arch/riscv/include/asm/timex.h +@@ -22,13 +22,13 @@ static inline cycles_t get_cycles(void) + #else /* !CONFIG_64BIT */ + static inline u32 get_cycles(void) + { +- return readl_relaxed(((u32 *)clint_time_val)); ++ return readl_relaxed(((u32 __iomem *)clint_time_val)); + } + #define get_cycles get_cycles + + static inline u32 get_cycles_hi(void) + { +- return readl_relaxed(((u32 *)clint_time_val) + 1); ++ return readl_relaxed(((u32 __iomem *)clint_time_val) + 1); + } + #define get_cycles_hi get_cycles_hi + #endif /* CONFIG_64BIT */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0552-FROMLIST-PCI-Move-Spacemit-vendor-and-device-IDs-to-.patch b/SPECS/linux-lts/0552-FROMLIST-PCI-Move-Spacemit-vendor-and-device-IDs-to-.patch new file mode 100644 index 0000000000..e50431db47 --- /dev/null +++ b/SPECS/linux-lts/0552-FROMLIST-PCI-Move-Spacemit-vendor-and-device-IDs-to-.patch @@ -0,0 +1,54 @@ +From 64b66eb1e39719aab650752801d8e9f97f010c9a Mon Sep 17 00:00:00 2001 +From: Anirudh Srinivasan +Date: Thu, 16 Jul 2026 18:05:10 -0500 +Subject: [RUYI PATCH] FROMLIST: PCI: Move Spacemit vendor and device IDs to + linux/pci_ids.h + +Move the vendor and device ID for the existing Spacemit K1 PCIe Root +Complex to include/linux/pci_ids.h. Also add K3's Root Complex device ID +to this header. This is done so that these values can be referenced in +the rtw89 driver to enable 36-bit DMA ability in it for WiFi to function +on the K3 Pico ITX board. + +Acked-by: Bjorn Helgaas +Signed-off-by: Anirudh Srinivasan +Link: https://lore.kernel.org/r/20260716-rtw89-spacemit-k3-v2-1-392b577ebf75@oss.tenstorrent.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 4 ---- + include/linux/pci_ids.h | 4 ++++ + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 7502d66bd0d0..bf2ab5cb59ce 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -21,10 +21,6 @@ + + #include "pcie-designware.h" + +-#define PCI_VENDOR_ID_SPACEMIT 0x201f +-#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 +-#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 +- + /* Offsets and field definitions for link management registers */ + #define K1_PHY_AHB_IRQ_EN 0x0000 + #define PCIE_INTERRUPT_EN BIT(0) +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 7c01548a6ddb..26ac13010cb5 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2643,6 +2643,10 @@ + #define PCI_VENDOR_ID_SUNIX 0x1fd4 + #define PCI_DEVICE_ID_SUNIX_1999 0x1999 + ++#define PCI_VENDOR_ID_SPACEMIT 0x201f ++#define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 ++ + #define PCI_VENDOR_ID_HINT 0x3388 + #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0553-FROMLIST-wifi-rtw89-pci-enable-36-bit-DMA-on-spacemi.patch b/SPECS/linux-lts/0553-FROMLIST-wifi-rtw89-pci-enable-36-bit-DMA-on-spacemi.patch new file mode 100644 index 0000000000..d52003d2e0 --- /dev/null +++ b/SPECS/linux-lts/0553-FROMLIST-wifi-rtw89-pci-enable-36-bit-DMA-on-spacemi.patch @@ -0,0 +1,39 @@ +From d3fadb381f8e426840c03b032c474eb1535c31f5 Mon Sep 17 00:00:00 2001 +From: Anirudh Srinivasan +Date: Thu, 16 Jul 2026 18:05:11 -0500 +Subject: [RUYI PATCH] FROMLIST: wifi: rtw89: pci: enable 36-bit DMA on + spacemit K3 + +The Spacemit K3 Pico ITX Board has a RTL8852BE pcie card behind a PCIe +root port, but the SoC doesn't have any 32 bit DMA addreseses which the +rtw89 seems to use by default. Enable 36 bit DMA ability that the driver +has when this particular root port is detected so that the driver can +probe on this SoC. + +Tested-by: Aurelien Jarno +Acked-by: Ping-Ke Shih +Signed-off-by: Anirudh Srinivasan +Link: https://lore.kernel.org/r/20260716-rtw89-spacemit-k3-v2-2-392b577ebf75@oss.tenstorrent.com +Signed-off-by: Han Gao +--- + drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +index 6be1849b0c4d..5058ebadb604 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.c ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) + if (bridge->device == 0x2806) + return true; + break; ++ case PCI_VENDOR_ID_SPACEMIT: ++ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) ++ return true; ++ break; + } + + return false; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0554-FROMLIST-riscv-cmpxchg-Use-.option-arch-for-Zacas-an.patch b/SPECS/linux-lts/0554-FROMLIST-riscv-cmpxchg-Use-.option-arch-for-Zacas-an.patch new file mode 100644 index 0000000000..0f5c5a9158 --- /dev/null +++ b/SPECS/linux-lts/0554-FROMLIST-riscv-cmpxchg-Use-.option-arch-for-Zacas-an.patch @@ -0,0 +1,97 @@ +From 5cb1625f1dd1575c52963517c166d900063ac6fa Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 17 Jul 2026 20:40:06 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: cmpxchg: Use .option arch for Zacas and + Zabha + +Instead of adding these to -march globally, use .option arch to use +instructions from these extensions only in code paths where we know they +are available, like how it is done for most other extensions. +TOOLCHAIN_HAS_{ZACAS,ZABHA} already depend on AS_HAS_OPTION_ARCH, so +this is not a functionality regression even on older assemblers. + +Although the compiler is unlikely to generate atomics on its own accord, +this aligns handling of Zacas and Zabha with most other extensions and +improves consistency on how assembly code requiring extra extensions is +written in kernel code. + +This is analogous to the use of __LSE_PREAMBLE or .arch_extension lse in +arm64 code. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260717-riscv-no-zacas-zabha-in-march-v1-1-82b5b0799fb6@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 6 ------ + arch/riscv/include/asm/cmpxchg.h | 14 +++++++++++++- + 2 files changed, 13 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 1256e91714ef..478451141341 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -83,12 +83,6 @@ else + riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei + endif + +-# Check if the toolchain supports Zacas +-riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas +- +-# Check if the toolchain supports Zabha +-riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha +- + # Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by + # matching non-v and non-multi-letter extensions out with the filter ([^v_]*) + KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/') +diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h +index 122e1485d39a..e68263343403 100644 +--- a/arch/riscv/include/asm/cmpxchg.h ++++ b/arch/riscv/include/asm/cmpxchg.h +@@ -23,7 +23,10 @@ + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + __asm__ __volatile__ ( \ + prepend \ ++ " .option push\n" \ ++ " .option arch, +zabha\n" \ + " amoswap" swap_sfx " %0, %z2, %1\n" \ ++ " .option pop\n" \ + swap_append \ + : "=&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ +@@ -141,7 +144,10 @@ + \ + __asm__ __volatile__ ( \ + cas_prepend \ ++ " .option push\n" \ ++ " .option arch, +zacas, +zabha\n" \ + " amocas" cas_sfx " %0, %z2, %1\n" \ ++ " .option pop\n" \ + cas_append \ + : "+&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ +@@ -188,7 +194,10 @@ + \ + __asm__ __volatile__ ( \ + cas_prepend \ ++ " .option push\n" \ ++ " .option arch, +zacas\n" \ + " amocas" cas_sfx " %0, %z2, %1\n" \ ++ " .option pop\n" \ + cas_append \ + : "+&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ +@@ -340,7 +349,10 @@ union __u128_halves { + register unsigned long t4 asm ("t4") = __ho.high; \ + \ + __asm__ __volatile__ ( \ +- " amocas.q" cas_sfx " %0, %z3, %2" \ ++ " .option push\n" \ ++ " .option arch, +zacas\n" \ ++ " amocas.q" cas_sfx " %0, %z3, %2\n" \ ++ " .option pop\n" \ + : "+&r" (t3), "+&r" (t4), "+A" (*(p)) \ + : "rJ" (t1), "rJ" (t2) \ + : "memory"); \ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0555-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts/0555-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch new file mode 100644 index 0000000000..9919124010 --- /dev/null +++ b/SPECS/linux-lts/0555-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch @@ -0,0 +1,49 @@ +From ac7aa3430e8c8a4228ddd613179ea61f723a9574 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 24 Nov 2025 20:38:44 +0800 +Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support + +From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/Makefile | 1 + + .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ + 2 files changed, 19 insertions(+) + create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts + +diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile +index b55a17127c2b..281849e71ccb 100644 +--- a/arch/riscv/boot/dts/thead/Makefile ++++ b/arch/riscv/boot/dts/thead/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb ++dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +new file mode 100644 +index 000000000000..a3a991baf716 +--- /dev/null ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Han Gao ++ */ ++ ++/dts-v1/; ++ ++#include "th1520-lichee-pi-4a.dts" ++ ++/ { ++ model = "Sipeed Lichee Pi 4A 16G"; ++ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x00000000 0x4 0x00000000>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0556-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts/0556-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch new file mode 100644 index 0000000000..3fa38cb786 --- /dev/null +++ b/SPECS/linux-lts/0556-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch @@ -0,0 +1,28 @@ +From 057f072a9105eb987d4152d0c9488cc3495eaf18 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:16:15 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie + +Signed-off-by: Han Gao +[Icenowy: preserve the original compatible to allow Linux to match] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index aa757ddd6046..108205d5d4a6 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { + }; + + aon: aon { +- compatible = "thead,th1520-aon"; ++ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0557-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts/0557-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch new file mode 100644 index 0000000000..437e7fe52e --- /dev/null +++ b/SPECS/linux-lts/0557-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch @@ -0,0 +1,44 @@ +From af4d8f5cb53889a1c1486fef77dc3d7e6ebcbd4a Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:27:18 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r + +Signed-off-by: Han Gao +[Icenowy: remove the interrupt-controller property] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 108205d5d4a6..fdef5fb82b45 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -292,6 +292,24 @@ aon: aon { + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; + #power-domain-cells = <1>; ++ opensbi-mboxes = <&mbox_910r>; ++ status = "okay"; ++ }; ++ ++ mbox_910r: mbox@ffefc53000 { ++ compatible = "xuantie,th1520-mbox-r"; ++ reg = <0xff 0xefc53000 0x0 0x4000>, ++ <0xff 0xefc3f000 0x0 0x1000>, ++ <0xff 0xefc47000 0x0 0x1000>, ++ <0xff 0xefc4f000 0x0 0x1000>; ++ reg-names = "local_base", ++ "remote_icu0", ++ "remote_icu1", ++ "remote_icu2"; ++ clocks = <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ipg"; ++ icu_cpu_id = <3>; ++ #mbox-cells = <2>; + }; + + soc { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0558-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts/0558-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch new file mode 100644 index 0000000000..866a2cfc89 --- /dev/null +++ b/SPECS/linux-lts/0558-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch @@ -0,0 +1,84 @@ +From e2eb8f9600dd3a09b456111bd9cb4f7ed4c60d45 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:31 +0800 +Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller + +Sophgo SG2044 uses eFuses used to store factory-programmed data +such as ROM patch, public keys and other factory information. + +Signed-off-by: Inochi Amaoto +--- + .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml + +diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +new file mode 100644 +index 000000000000..d4bffe2724ac +--- /dev/null ++++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sophgo SoC eFuse-based NVMEM ++ ++description: ++ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, ++ public key and other factory information. ++ ++maintainers: ++ - Inochi Amaoto ++ ++allOf: ++ - $ref: nvmem.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - sophgo,sg2044-efuse ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ items: ++ - description: Core clock ++ - description: APB clock ++ ++ clock-names: ++ minItems: 1 ++ items: ++ - const: core ++ - const: apb ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ efuse@40000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x40000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk 0>, ++ <&clk 1>; ++ clock-names = "core", "apb"; ++ }; ++ ++... +-- +2.53.0 + diff --git a/SPECS/linux-lts/0559-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts/0559-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch new file mode 100644 index 0000000000..47c78a2e2a --- /dev/null +++ b/SPECS/linux-lts/0559-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch @@ -0,0 +1,241 @@ +From 3482c1d615fc8998a6fab569b8d8c1dc63c2dba0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:32 +0800 +Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver + +Sophgo SoCs such as SG2044 contain eFuses used to store +factory-programmed data. + +As for SG2044, HW automatically loads the eFuse content +into shadow registers which are organized as 32bit values +exposed as MMIO. + +Signed-off-by: Inochi Amaoto +--- + drivers/nvmem/Kconfig | 12 +++ + drivers/nvmem/Makefile | 2 + + drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 drivers/nvmem/sophgo-efuse.c + +diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig +index 11b098705ec6..42f46eb0462a 100644 +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR + This driver can also be built as a module. If so, the module + will be called nvmem-snvs-lpgpr. + ++config NVMEM_SOPHGO_EFUSE ++ tristate "Sophgo eFuse support" ++ depends on ARCH_SOPHGO || COMPILE_TEST ++ default ARCH_SOPHGO ++ help ++ Say y here to enable support for reading eFuses on Sophgo SoCs ++ such as the CV1800B. These are e.g. used to store factory programmed ++ calibration data required for the builtin ethernet PHY. ++ ++ This driver can also be built as a module. If so, the module will ++ be called nvmem-sophgo-efuse. ++ + config NVMEM_SPMI_SDAM + tristate "SPMI SDAM Support" + depends on SPMI +diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile +index 70a4464dcb1e..6cc324aaa757 100644 +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o + nvmem-sc27xx-efuse-y := sc27xx-efuse.o + obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o + nvmem_snvs_lpgpr-y := snvs_lpgpr.o ++obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o ++nvmem-sophgo-efuse-y := sophgo-efuse.o + obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o + nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o + obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o +diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c +new file mode 100644 +index 000000000000..5f90adaf8e4f +--- /dev/null ++++ b/drivers/nvmem/sophgo-efuse.c +@@ -0,0 +1,176 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Sophgo SoC eFuse driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SG2044_EFUSE_CONTENT_SIZE 0x400 ++ ++#define SG2044_EFUSE_MD 0x000 ++#define SG2044_EFUSE_ADR 0x004 ++#define SG2044_EFUSE_RD_DATA 0x00c ++ ++#define SG2044_EFUSE_MODE GENMASK(1, 0) ++#define SG2044_EFUSE_MODE_READ 2 ++ ++#define SG2044_EFUSE_BOOT_DONE BIT(7) ++#define SG2044_BOOT_TIMEOUT 10000 ++ ++#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) ++ ++#define SG2044_EFUSE_ALIGN 4 ++ ++struct sophgo_efuses { ++ void __iomem *base; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct mutex mutex; ++}; ++ ++static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) ++{ ++ u32 value; ++ ++ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, ++ 1, SG2044_BOOT_TIMEOUT); ++} ++ ++static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) ++{ ++ u32 val = readl(efuse->base + SG2044_EFUSE_MD); ++ ++ val &= ~SG2044_EFUSE_MODE; ++ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); ++ ++ writel(val, efuse->base + SG2044_EFUSE_MD); ++ ++ return sg2044_efuse_wait_mode(efuse); ++} ++ ++static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, ++ unsigned int offset, u32 *strip) ++{ ++ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); ++ int ret; ++ ++ guard(mutex)(&efuse->mutex); ++ ++ writel(val, efuse->base + SG2044_EFUSE_ADR); ++ ++ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); ++ if (ret < 0) ++ return ret; ++ ++ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); ++ ++ return 0; ++} ++ ++static int sg2044_efuses_read(void *context, unsigned int offset, void *val, ++ size_t bytes) ++{ ++ struct sophgo_efuses *efuse = context; ++ unsigned int start, start_offset, end, i; ++ u32 value; ++ u8 *buf; ++ int ret; ++ ++ start = rounddown(offset, SG2044_EFUSE_ALIGN); ++ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); ++ start_offset = offset - start; ++ ++ start /= SG2044_EFUSE_ALIGN; ++ end /= SG2044_EFUSE_ALIGN; ++ ++ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ (value & SG2044_EFUSE_BOOT_DONE), ++ 1, SG2044_BOOT_TIMEOUT); ++ if (ret < 0) ++ return ret; ++ ++ buf = kzalloc(end - start, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (i = start; i < end; i++) { ++ ret = sg2044_efuses_read_strip(efuse, i, &value); ++ if (ret) ++ goto failed; ++ ++ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); ++ } ++ ++ memcpy(val, buf + start_offset, bytes); ++ ++failed: ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int sophgo_efuses_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct sophgo_efuses *efuse; ++ struct nvmem_config config = { ++ .dev = &pdev->dev, ++ .add_legacy_fixed_of_cells = true, ++ .read_only = true, ++ .reg_read = sg2044_efuses_read, ++ .stride = 1, ++ .word_size = 1, ++ .name = "sophgo-efuse", ++ .id = NVMEM_DEVID_AUTO, ++ .root_only = true, ++ }; ++ ++ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); ++ if (!efuse) ++ return -ENOMEM; ++ ++ efuse->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(efuse->base)) ++ return PTR_ERR(efuse->base); ++ ++ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); ++ if (efuse->num_clks < 0) ++ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); ++ ++ config.priv = efuse; ++ config.size = SG2044_EFUSE_CONTENT_SIZE; ++ ++ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); ++} ++ ++static const struct of_device_id sophgo_efuses_of_match[] = { ++ { .compatible = "sophgo,sg2044-efuse", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); ++ ++static struct platform_driver sophgo_efuses_driver = { ++ .driver = { ++ .name = "sophgo_efuse", ++ .of_match_table = sophgo_efuses_of_match, ++ }, ++ .probe = sophgo_efuses_probe, ++}; ++ ++module_platform_driver(sophgo_efuses_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Sophgo efuse driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0560-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts/0560-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch new file mode 100644 index 0000000000..a57f9e3a3e --- /dev/null +++ b/SPECS/linux-lts/0560-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch @@ -0,0 +1,54 @@ +From e2679ad091eadd0d4c8e4e8bf0bbf36257b98c1c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 5 Dec 2024 13:24:13 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device + +Add eFUSE controller node for SG2044. + +Signed-off-by: Inochi Amaoto +--- + arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index fed3d9a384a0..1b506972d465 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -36,6 +36,10 @@ &emmc { + status = "okay"; + }; + ++&efuse0 { ++ status = "okay"; ++}; ++ + &gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 320c4d1d08e6..9577aae08f7f 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -408,6 +408,18 @@ sd: mmc@703000b000 { + status = "disabled"; + }; + ++ efuse0: efuse@7040000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x70 0x40000000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk CLK_GATE_EFUSE>, ++ <&clk CLK_GATE_APB_EFUSE>; ++ clock-names = "core", "apb"; ++ resets = <&rst RST_EFUSE0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@7040005000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40005000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0561-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts/0561-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch new file mode 100644 index 0000000000..246eb06539 --- /dev/null +++ b/SPECS/linux-lts/0561-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch @@ -0,0 +1,30 @@ +From 9bdc31cdfcf7352a39af835175692dad1e9875e3 Mon Sep 17 00:00:00 2001 +From: Xiaoguang Xing +Date: Mon, 22 Jan 2024 10:31:30 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean + with flush + +FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 + +Signed-off-by: Xiaoguang Xing +Signed-off-by: Han Gao +--- + arch/riscv/errata/thead/errata.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index fbe46f2fa8fb..9be8c45f4531 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, + * 0000000 11001 00000 000 00000 0001011 + */ + #define THEAD_INVAL_A0 ".long 0x02a5000b" +-#define THEAD_CLEAN_A0 ".long 0x0295000b" ++#define THEAD_CLEAN_A0 ".long 0x02b5000b" + #define THEAD_FLUSH_A0 ".long 0x02b5000b" + #define THEAD_SYNC_S ".long 0x0190000b" + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0562-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts/0562-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch new file mode 100644 index 0000000000..bf61df6a36 --- /dev/null +++ b/SPECS/linux-lts/0562-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch @@ -0,0 +1,102 @@ +From 6bf71169183a4dec0533a946b56929ef4c3eaf20 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 28 Dec 2025 23:02:15 +0800 +Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address + +FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 9577aae08f7f..f1377ee8e149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00000000 0x0 0x00001000>, + <0x6c 0x00300000 0x0 0x00004000>, +- <0x48 0x00000000 0x0 0x00001000>, ++ <0x50 0x00000000 0x0 0x00001000>, + <0x6c 0x000c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, + <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc0: interrupt-controller { +@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { + ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc1: interrupt-controller { +@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04000000 0x0 0x00001000>, + <0x6c 0x04300000 0x0 0x00004000>, +- <0x58 0x00000000 0x0 0x00001000>, ++ <0x7c 0x00000000 0x0 0x00001000>, + <0x6c 0x040c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, + <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, +- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc2: interrupt-controller { +@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04400000 0x0 0x00001000>, + <0x6c 0x04700000 0x0 0x00004000>, +- <0x50 0x00000000 0x0 0x00001000>, ++ <0x78 0x00000000 0x0 0x00001000>, + <0x6c 0x04780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, + <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, +- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, +- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc3: interrupt-controller { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0563-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts/0563-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch new file mode 100644 index 0000000000..ca3265badb --- /dev/null +++ b/SPECS/linux-lts/0563-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch @@ -0,0 +1,145 @@ +From 412ab5bced3838d09062ee243fa024c8075a6999 Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Mon, 5 Jan 2026 20:05:04 +0800 +Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is + not cacheable + +FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f + +Change-Id: I040d597ee246777767f7be747fa9202154524538 +[ Vivian: Rebase and move check into enter_vector_usercopy ] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/uaccess.h | 5 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/riscv_v_helpers.c | 5 +++ + arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ + 4 files changed, 76 insertions(+) + create mode 100644 arch/riscv/lib/uaccess_cache_check.c + +diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h +index 6aef591a6bfc..b028208b05ec 100644 +--- a/arch/riscv/include/asm/uaccess.h ++++ b/arch/riscv/include/asm/uaccess.h +@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } + if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ + goto label; + ++/* Memory cacheability check for vector uaccess optimization */ ++#ifdef CONFIG_RISCV_ISA_V ++int is_cacheable_safe(const void *addr); ++#endif ++ + #else /* CONFIG_MMU */ + #include + #endif /* CONFIG_MMU */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 735d0b665536..43fe69db9803 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -14,6 +14,7 @@ endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) + lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o ++lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o + endif + lib-$(CONFIG_MMU) += uaccess.o + lib-$(CONFIG_64BIT) += tishift.o +diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c +index 7bbdfc6d4552..7ab2cea280f8 100644 +--- a/arch/riscv/lib/riscv_v_helpers.c ++++ b/arch/riscv/lib/riscv_v_helpers.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + + #ifdef CONFIG_MMU + #include +@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, + if (!may_use_simd()) + goto fallback; + ++ /* HACK */ ++ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) ++ goto fallback; ++ + kernel_vector_begin(); + remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : + __asm_vector_usercopy_sum_enabled(dst, src, n); +diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c +new file mode 100644 +index 000000000000..0b0996fa2d37 +--- /dev/null ++++ b/arch/riscv/lib/uaccess_cache_check.c +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Memory cacheability check for RISC-V uaccess optimization ++ * ++ * This file provides a C function that can be called from assembly ++ * to determine if a buffer is cacheable before using vector instructions. ++ */ ++ ++#include ++#include ++#include ++ ++/** ++ * is_cacheable_safe - Check if memory buffer is cacheable ++ * @addr: Virtual address to check (kernel or user space) ++ * ++ * Returns: 1 if cacheable, 0 if non-cacheable ++ * ++ * This function is designed to be called from assembly code in uaccess.S ++ * to determine if vector instructions are safe to use for memory copy. ++ * ++ * Non-cacheable memory (device IO, DMA coherent buffers) should not use ++ * vector instructions as they may cause cache coherency issues. ++ * ++ * Handles both kernel and user space addresses safely: ++ * - Kernel direct mapping: Always cacheable ++ * - Kernel vmalloc: Check VM flags ++ * - User space: Check page table (most are cacheable) ++ * - ioremap/DMA: Non-cacheable ++ */ ++int is_cacheable_safe(const void *addr) ++{ ++ unsigned long vaddr = (unsigned long)addr; ++ ++ /* Kernel direct mapped memory - always cacheable */ ++ if (virt_addr_valid(addr)) ++ return 1; ++ ++ if (vaddr < TASK_SIZE) { ++ /* ++ * User space address, Determine it as a cacheable buffer, ++ * maybe not safe!! ++ */ ++ return 1; ++ } ++ ++ /* Check if it's a vmalloc region (kernel virtual address) */ ++ if (is_vmalloc_addr(addr)) { ++ struct vm_struct *vm; ++ ++ vm = find_vm_area(addr); ++ if (!vm) ++ return 0; ++ ++ /* Exclude ioremap and DMA coherent buffers */ ++ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) ++ return 0; ++ ++ /* Normal vmalloc - cacheable */ ++ return 1; ++ } ++ ++ /* Unknown kernel region - assume non-cacheable for safety */ ++ return 0; ++} +-- +2.53.0 + diff --git a/SPECS/linux-lts/0564-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts/0564-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch new file mode 100644 index 0000000000..af2c7896d5 --- /dev/null +++ b/SPECS/linux-lts/0564-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch @@ -0,0 +1,57 @@ +From 8e003247f1ea7a299ee88d58637eb93a70aff1b5 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 19 May 2026 19:57:52 +0800 +Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on + SpacemiT K3 + +The dynamic speed switch functionality seems to be broken on SpacemiT +K3, and leads to frequent GPU crashes at least with Polaris GPUs. + +Disable dynamic speed switch on this platform. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index c22aea46efcd..b54f7cdd0ce8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) + */ + static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) + { ++ struct pci_dev *parent = adev->pdev; ++ static const struct pci_device_id broken_devids[] = { ++ /* SpacemiT K3 */ ++ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, ++ PCI_DEVICE_ID_SPACEMIT_K3) }, ++ {} ++ }; ++ + #if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); + +@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device + if (c->x86_vendor == X86_VENDOR_INTEL) + return false; + #endif ++ /* skip upstream/downstream switches internal to dGPU */ ++ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { ++ parent = pci_upstream_bridge(parent); ++ } ++ ++ if (!parent) ++ return true; ++ ++ if (pci_match_id(broken_devids, parent)) ++ return false; ++ + return true; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0565-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts/0565-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch new file mode 100644 index 0000000000..9e11504188 --- /dev/null +++ b/SPECS/linux-lts/0565-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch @@ -0,0 +1,65 @@ +From f443eaed7912e8a966fc81edd153f42d28cd0043 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 28 May 2026 14:18:23 +0800 +Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA + variant + +Add support for a testing variant of the SG2042 SDHCI controller without +PHY reset and without the "timer" clock. + +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 90aa146a1be3..292940d9c45b 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1664,6 +1664,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { ++ .set_clock = sdhci_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = dwcmshc_set_uhs_signaling, ++ .get_max_clock = dwcmshc_get_max_clock, ++ .reset = sdhci_reset, ++ .adma_write_desc = dwcmshc_adma_write_desc, ++ .platform_execute_tuning = th1520_execute_tuning, ++}; ++ + static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_clock = sdhci_eic7700_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, +@@ -1746,6 +1756,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++ }, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_eic7700_ops, +@@ -1857,6 +1875,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "sophgo,sg2042-fpga-dwcmshc", ++ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, ++ }, + { + .compatible = "eswin,eic7700-dwcmshc", + .data = &sdhci_dwcmshc_eic7700_pdata, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0566-RUYI-riscv-dts-sophgo-sg2044-srd3-add-spifmc-node.patch b/SPECS/linux-lts/0566-RUYI-riscv-dts-sophgo-sg2044-srd3-add-spifmc-node.patch new file mode 100644 index 0000000000..00a52c24cf --- /dev/null +++ b/SPECS/linux-lts/0566-RUYI-riscv-dts-sophgo-sg2044-srd3-add-spifmc-node.patch @@ -0,0 +1,49 @@ +From d82d17cf8643eba9acc05af4e18863a62db99ef8 Mon Sep 17 00:00:00 2001 +From: Hangfan Li +Date: Fri, 3 Jul 2026 17:29:21 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: sophgo: sg2044: srd3: add spifmc node + +Signed-off-by: Hangfan Li +Signed-off-by: Han Gao +--- + .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index 1b506972d465..6003d92c50a7 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -113,6 +113,30 @@ &sd { + status = "okay"; + }; + ++&spifmc0 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <133000000>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++}; ++ ++&spifmc1 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <133000000>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ }; ++}; ++ + &uart0 { + /* for firmware */ + status = "reserved"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0567-RUYI-HACK-riscv-entry-nmi_exit-before-die.patch b/SPECS/linux-lts/0567-RUYI-HACK-riscv-entry-nmi_exit-before-die.patch new file mode 100644 index 0000000000..0575ade162 --- /dev/null +++ b/SPECS/linux-lts/0567-RUYI-HACK-riscv-entry-nmi_exit-before-die.patch @@ -0,0 +1,45 @@ +From 0cbaf29b9b337231c6c786852d96d9ecc6d9038d Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 7 Jul 2026 09:35:50 +0800 +Subject: [RUYI PATCH] RUYI: HACK: riscv: entry: nmi_exit() before die() + +Breakpoint exceptions are handled in_nmi() since they could be kernel +breakpoints. As such, nmi_exit() before die() to give the kernel a +chance to recover instead of having make_task_dead() generate a +full-machine panic. + +This is similar to how some exceptions are handled in powerpc. + +This is a bit of a hack. A better solution was being discussed [1] but +no concrete conclusion has been arrived to yet. + +Link: https://lore.kernel.org/linux-riscv/20230702025708.784106-1-guoren@kernel.org/ # [1] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/kernel/traps.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c +index 47afea4ff1a8..65172f072f37 100644 +--- a/arch/riscv/kernel/traps.c ++++ b/arch/riscv/kernel/traps.c +@@ -298,10 +298,13 @@ void handle_break(struct pt_regs *regs) + return; + #endif + else if (report_bug(regs->epc, regs) == BUG_TRAP_TYPE_WARN || +- handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) ++ handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) { + regs->epc += get_break_insn_length(regs->epc); +- else ++ } else { ++ /* Avoid a panic, since we're in_nmi(). */ ++ nmi_exit(); + die(regs, "Kernel BUG"); ++ } + } + + asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) +-- +2.53.0 + diff --git a/SPECS/linux-lts/config.riscv64 b/SPECS/linux-lts/config.riscv64 index 147cea1b83..6bf3a8a1e1 100644 --- a/SPECS/linux-lts/config.riscv64 +++ b/SPECS/linux-lts/config.riscv64 @@ -1,1856 +1,7207 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_KERNEL_UNCOMPRESSED=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BPF_SYSCALL=y -CONFIG_BPF_JIT=y -CONFIG_BPF_JIT_ALWAYS_ON=y -CONFIG_PREEMPT_DYNAMIC=y -CONFIG_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_PSI=y -CONFIG_PSI_DEFAULT_DISABLED=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=20 -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_MISC=y -CONFIG_NAMESPACES=y -CONFIG_USER_NS=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -CONFIG_DEBUG_PERF_USE_VMALLOC=y -CONFIG_PROFILING=y -CONFIG_RUST=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y +# CONFIG_ERRATA_THEAD_GHOSTWRITE is not set +# CONFIG_ERRATA_THEAD_WRITE_ONCE is not set +CONFIG_64BIT=y +# CONFIG_6LOWPAN is not set +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_9P_FS=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +# CONFIG_ACCESSIBILITY is not set +CONFIG_ACLINT_SSWI=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI=y +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +# CONFIG_ACPI_BGRT is not set +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_DEBUG=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_DOCK=y +# CONFIG_ACPI_EC is not set +CONFIG_ACPI_FAN=y +CONFIG_ACPI_FFH=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +# CONFIG_ACPI_HOTPLUG_MEMORY is not set +CONFIG_ACPI_I2C_OPREGION=y +# CONFIG_ACPI_IPMI is not set +CONFIG_ACPI_MCFG=y +CONFIG_ACPI_MDIO=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NHLT=y +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PPTT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ACPI_RIMT=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_TABLE_LIB=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_THERMAL_LIB=y +CONFIG_ACPI_VIDEO=m +# CONFIG_AD525X_DPOT is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIN1100_PHY is not set +# CONFIG_ADIN1110 is not set +# CONFIG_ADIN_PHY is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_KCM is not set +# CONFIG_AF_RXRPC is not set +CONFIG_AF_UNIX_OOB=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_DWC is not set +# CONFIG_AHCI_SUNXI is not set +CONFIG_AIO=y +# CONFIG_AIR_EN8811H_PHY is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_ALIM7101_WDT=m +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ALTERA_MSGDMA is not set +CONFIG_ALTERA_STAPL=m +# CONFIG_ALTERA_TSE is not set +CONFIG_ALX=m +# CONFIG_AL_FIC is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_AMD8111_ETH is not set +CONFIG_AMD_PHY=m +# CONFIG_AMD_QDMA is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMT is not set +CONFIG_ANDES_CUSTOM_PMU=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_ANDROID_BINDER_IPC_RUST is not set +# CONFIG_ANON_VMA_NAME is not set +CONFIG_APDS9802ALS=m +CONFIG_APERTURE_HELPERS=y +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_APPLICOM is not set +# CONFIG_AQTION is not set +CONFIG_AQUANTIA_PHY=m +# CONFIG_AR5523 is not set CONFIG_ARCH_ANDES=y +CONFIG_ARCH_CANAAN=y +CONFIG_ARCH_CC_CAN_LINK=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_ARCH_ESWIN=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_CC_CAN_LINK=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_ELF_CORE_EFLAGS=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD=y +CONFIG_ARCH_HAS_PTDUMP=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAS_UBSAN=y +CONFIG_ARCH_HAS_VDSO_ARCH_DATA=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECTS_KEXEC=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y CONFIG_ARCH_SPACEMIT=y -CONFIG_SOC_STARFIVE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_STARFIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_CFI=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_RT=y +CONFIG_ARCH_SUPPORTS_SCHED_MC=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_THEAD=y CONFIG_ARCH_ULTRARISC=y +CONFIG_ARCH_USERFLAGS="-march=rv64g -mabi=lp64d" +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_ARCH_VIRT=y -CONFIG_ARCH_CANAAN=y -CONFIG_ERRATA_MIPS=y -CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y -CONFIG_SMP=y -CONFIG_NR_CPUS=256 -CONFIG_NUMA=y -CONFIG_NODES_SHIFT=7 +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y +# CONFIG_ARCNET is not set +CONFIG_ARM_AMBA=y +# CONFIG_ARM_HISI_UNCORE_DEVFREQ is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set +# CONFIG_AS21XXX_PHY is not set +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASN1_ENCODER=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_ASYNC_XOR=m +CONFIG_AS_HAS_INSN=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_AS_HAS_OPTION_ARCH=y +CONFIG_AS_HAS_ULEB128=y +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24690 +CONFIG_AT803X_PHY=m +CONFIG_ATA=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=m +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=m +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATH10K=m +# CONFIG_ATH10K_AHB is not set +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +CONFIG_ATH10K_LEDS=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_TRACING is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH11K is not set +# CONFIG_ATH12K is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_AT_XDMAC is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUTOFS_FS=y +CONFIG_AUXDISPLAY=y +CONFIG_AUXILIARY_BUS=y +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_AX88796B_PHY=m +# CONFIG_B44 is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_BD6107 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=m +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +# CONFIG_BACKLIGHT_LED is not set +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_MP3309C is not set +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BALLOON_COMPACTION=y +# CONFIG_BAREUDP is not set +# CONFIG_BASE_SMALL is not set +CONFIG_BASIC_MODVERSIONS=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_CHAGALL is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_UG3105 is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA=m +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_NET_PHYPTP=m +# CONFIG_BCM_VK is not set +CONFIG_BE2ISCSI=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFQ_CGROUP_DEBUG is not set +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFS_FS is not set +# CONFIG_BIG_KEYS is not set +CONFIG_BINARY_PRINTF=y +CONFIG_BINDGEN_VERSION_TEXT="bindgen 0.72.1" +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +CONFIG_BLK_CGROUP=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_DM=m +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_RUST_NULL is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_DEV_ZONED_LOOP is not set +CONFIG_BLK_ICQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BLK_MQ_STACKING=y +CONFIG_BLK_PM=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +# CONFIG_BNGE is not set +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +# CONFIG_BNXT_HWMON is not set +CONFIG_BNXT_SRIOV=y +CONFIG_BONDING=m +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTTIME_TRACING=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BPF=y +CONFIG_BPF_EVENTS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPF_LSM is not set +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_STREAM_PARSER=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +CONFIG_BRIDGE=m +# CONFIG_BRIDGE_CFM is not set +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_BT is not set +CONFIG_BTREE=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +CONFIG_BTRFS_EXPERIMENTAL=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTT=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUG=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +CONFIG_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_BUILD_SALT="" +# CONFIG_C2PORT is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_CAIF=y +# CONFIG_CAIF_DEBUG is not set +# CONFIG_CAIF_DRIVERS is not set +CONFIG_CAIF_NETDEV=y +# CONFIG_CAIF_USB is not set +CONFIG_CAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_C_CAN_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +# CONFIG_CAN_ESD_USB is not set +# CONFIG_CAN_ETAS_ES58X is not set +# CONFIG_CAN_F81601 is not set +# CONFIG_CAN_F81604 is not set +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_GS_USB is not set +CONFIG_CAN_GW=m +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_ISOTP is not set +# CONFIG_CAN_J1939 is not set +CONFIG_CAN_KVASER_PCI=m +# CONFIG_CAN_KVASER_PCIEFD is not set +CONFIG_CAN_KVASER_USB=m +# CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# CONFIG_CAN_M_CAN is not set +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +# CONFIG_CAN_PEAK_PCIEFD is not set +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_RAW=m +# CONFIG_CAN_RCAR is not set +# CONFIG_CAN_RCAR_CANFD is not set +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SOFTING=m +# CONFIG_CAN_SUN4I is not set +# CONFIG_CAN_UCAN is not set +CONFIG_CAN_VCAN=m +# CONFIG_CAN_VXCAN is not set +# CONFIG_CARL9170 is not set +CONFIG_CAVIUM_PTP=y +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_ASSUME=y +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_IS_GCC=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (Debian 15.3.0-1) 15.3.0" +CONFIG_CDROM=y +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +# CONFIG_CGROUP_DMEM is not set +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_WRITEBACK=y +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_MAX8971 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_RT9467 is not set +# CONFIG_CHARGER_RT9471 is not set +# CONFIG_CHARGER_SBS is not set +CONFIG_CHARGER_SMB347=m +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_LIB=m +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +# CONFIG_CHELSIO_T4_DCB is not set +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_ST=m +CONFIG_CICADA_PHY=m +CONFIG_CIFS=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_COMPRESSION is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_SWN_UPCALL is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CLANG_VERSION=0 +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set +CONFIG_CLK_RENESAS=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +# CONFIG_CLK_SOPHGO_CV1800 is not set +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y +CONFIG_CLK_SOPHGO_SG2044=y +CONFIG_CLK_SOPHGO_SG2044_PLL=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7110_AON=m +CONFIG_CLK_STARFIVE_JH7110_ISP=m +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_STG=m +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=m +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_THEAD_TH1520_AP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLOSURES=y +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=19 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CNIC=m +# CONFIG_CODA_FS is not set +# CONFIG_COMEDI is not set +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_RPMI=y +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_VC3 is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_COMPAT is not set -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_PM_DEBUG=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_CONSOLE_POLL=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTEXT_TRACKING_USER=y +# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set +CONFIG_CONTIG_ALLOC=y +CONFIG_CORDIC=m +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_CORTINA_PHY is not set +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_CPUFREQ_DT_RUST is not set +# CONFIG_CPUFREQ_VIRT is not set +CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=m -CONFIG_ACPI=y -CONFIG_ACPI_TAD=m -CONFIG_ACPI_DOCK=y -CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_HED=y -CONFIG_ACPI_NFIT=m -CONFIG_ACPI_CONFIGFS=m -CONFIG_ACPI_PFRUT=m -CONFIG_ACPI_FFH=y -CONFIG_PMIC_OPREGION=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_GENDWARFKSYMS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_MODULE_SIG_SHA256=y -CONFIG_MODULE_COMPRESS=y -CONFIG_MODULE_COMPRESS_XZ=y -CONFIG_MODULE_DECOMPRESS=y -CONFIG_BLK_DEV_ZONED=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BLK_WBT=y -CONFIG_BLK_INLINE_ENCRYPTION=y -CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_KARMA_PARTITION=y -CONFIG_MQ_IOSCHED_KYBER=m -CONFIG_BINFMT_MISC=m -CONFIG_ZSWAP=y -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y -CONFIG_ZSMALLOC_STAT=y -CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_SLAB_FREELIST_HARDENED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y -CONFIG_MEMORY_HOTREMOVE=y -CONFIG_KSM=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y -CONFIG_CMA_SYSFS=y -CONFIG_CMA_AREAS=19 -CONFIG_IDLE_PAGE_TRACKING=y -CONFIG_ZONE_DEVICE=y -CONFIG_DEVICE_PRIVATE=y -CONFIG_USERFAULTFD=y -CONFIG_LRU_GEN=y -CONFIG_LRU_GEN_ENABLED=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set +# CONFIG_CRASH_DM_CRYPT is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_CRC32_ARCH=y +CONFIG_CRC64=y +CONFIG_CRC64_ARCH=y +CONFIG_CRC7=y +CONFIG_CRC8=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_OPTIMIZATIONS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_T10DIF_ARCH=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_BENCHMARK is not set +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DEV_ALLWINNER=y +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_QAT_420XX is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_SUN4I_SS is not set +# CONFIG_CRYPTO_DEV_SUN8I_CE is not set +# CONFIG_CRYPTO_DEV_SUN8I_SS is not set +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set +CONFIG_CRYPTO_ECHAINIV=m +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_HCTR2 is not set +CONFIG_CRYPTO_HKDF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_KRB5 is not set +# CONFIG_CRYPTO_KRB5ENC is not set +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_MD5=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_ARCH=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SHA512=y +CONFIG_CRYPTO_LIB_SM3=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4=y +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SELFTESTS is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_SM3_GENERIC=y +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_RNG=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=y +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +# CONFIG_CV1800_MBOX is not set +CONFIG_CXD2880_SPI_DRV=m +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=y +# CONFIG_CXL_FEATURES is not set +CONFIG_CXL_MEM=y +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=y +CONFIG_CXL_PMEM=m +# CONFIG_CXL_PMU is not set +CONFIG_CXL_PORT=y +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_SUSPEND=y +CONFIG_DA9063_WATCHDOG=m CONFIG_DAMON=y -CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_LRU_SORT=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_STAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX_DIAG=m -CONFIG_TLS_DEVICE=y -CONFIG_XFRM_USER=m -CONFIG_XFRM_INTERFACE=m -CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y -CONFIG_XDP_SOCKETS=y -CONFIG_XDP_SOCKETS_DIAG=m -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_NET_IPVTI=m -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_DIAG=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_BBR=m -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_GRE=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_NETLABEL=y -CONFIG_MPTCP=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE_NETFILTER=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_PROCFS=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NF_CT_NETLINK_HELPER=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_NAT=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NFT_FIB_INET=m -CONFIG_NFT_DUP_NETDEV=m -CONFIG_NFT_FWD_NETDEV=m -CONFIG_NFT_FIB_NETDEV=m -CONFIG_NETFILTER_XTABLES=y -CONFIG_NETFILTER_XT_SET=m -CONFIG_NETFILTER_XT_TARGET_AUDIT=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_SET=m -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_PE_SIP=m -CONFIG_NFT_DUP_IPV4=m -CONFIG_NFT_FIB_IPV4=m -CONFIG_NF_TABLES_ARP=y -CONFIG_NF_LOG_ARP=m -CONFIG_NF_LOG_IPV4=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_SCTP=m -CONFIG_TIPC=m -CONFIG_TIPC_MEDIA_IB=y -CONFIG_L2TP=m -CONFIG_L2TP_DEBUGFS=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_SCH_DEFAULT=y -CONFIG_DEFAULT_FQ_CODEL=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_DAMON_STAT_ENABLED_DEFAULT=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y CONFIG_DCB=y -CONFIG_OPENVSWITCH=m -CONFIG_VSOCKETS=m -CONFIG_VIRTIO_VSOCKETS=m -CONFIG_NETLINK_DIAG=y -CONFIG_NET_SWITCHDEV=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_STREAM_PARSER=y -CONFIG_NET_PKTGEN=m -CONFIG_NET_DROP_MONITOR=m -CONFIG_CAN=m -CONFIG_CFG80211=m -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_NET_9P=y -CONFIG_NET_9P_FD=m -CONFIG_NET_9P_VIRTIO=y -CONFIG_CAIF=y -CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -CONFIG_LWTUNNEL=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEAER_INJECT=m -CONFIG_PCIE_ECRC=y -CONFIG_PCIE_DPC=y -CONFIG_PCIE_PTM=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_STUB=m -CONFIG_PCI_PF_STUB=m -CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -CONFIG_VGA_ARB_MAX_GPUS=64 -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCIE_XILINX=y -CONFIG_PCIE_SG2042_HOST=m -CONFIG_PCIE_DW_PLAT_HOST=y -CONFIG_PCIE_DW_PLAT_EP=y -CONFIG_PCIE_FU740=y -CONFIG_PCIE_SOPHGO_DW=y -CONFIG_PCIE_ULTRARISC=m -CONFIG_PCIE_MICROCHIP_HOST=y -CONFIG_PCIE_STARFIVE_HOST=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_CXL_BUS=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NET_SMALL_RTNL is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_PERF_USE_VMALLOC=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_VFS is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_ZSTD=y +# CONFIG_DEFAULT_CODEL is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_FQ is not set +CONFIG_DEFAULT_FQ_CODEL=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_DEFAULT_NET_SCH="fq_codel" +# CONFIG_DEFAULT_PFIFO_FAST is not set +# CONFIG_DEFAULT_RENO is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SFQ is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DETECT_HUNG_TASK_BLOCKER=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVICE_MIGRATION=y +CONFIG_DEVICE_PRIVATE=y +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_COMPRESS=y -CONFIG_FW_LOADER_COMPRESS_ZSTD=y -# CONFIG_ALLOW_DEV_COREDUMP is not set -CONFIG_SIFIVE_CCACHE=y -CONFIG_CONNECTOR=y -CONFIG_SYSFB_SIMPLEFB=y -CONFIG_TH1520_AON_PROTOCOL=y -CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y -CONFIG_MTD=m -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_MAP_BANK_WIDTH_8=y -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_BLOCK2MTD=m -CONFIG_MTD_SPI_NOR=m -CONFIG_MTD_UBI=m -CONFIG_MTD_UBI_GLUEBI=m -CONFIG_OF_OVERLAY=y -CONFIG_BLK_DEV_NULL_BLK=m -CONFIG_ZRAM=m -CONFIG_ZRAM_MULTI_COMP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 -CONFIG_BLK_DEV_DRBD=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=m -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_ATA_OVER_ETH=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_RBD=m -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_MULTIPATH=y -CONFIG_NVME_HWMON=y -CONFIG_NVME_RDMA=m -CONFIG_NVME_FC=m -CONFIG_NVME_TCP=m -CONFIG_NVME_TCP_TLS=y -CONFIG_NVME_HOST_AUTH=y -CONFIG_NVME_TARGET=m -CONFIG_NVME_TARGET_PASSTHRU=y -CONFIG_NVME_TARGET_LOOP=m -CONFIG_NVME_TARGET_RDMA=m -CONFIG_NVME_TARGET_FC=m -CONFIG_NVME_TARGET_FCLOOP=m -CONFIG_NVME_TARGET_TCP=m -CONFIG_ENCLOSURE_SERVICES=m -CONFIG_APDS9802ALS=m -CONFIG_ISL29003=m -CONFIG_ISL29020=m -CONFIG_SENSORS_TSL2550=m -CONFIG_SENSORS_BH1770=m -CONFIG_SENSORS_APDS990X=m -CONFIG_SRAM=y -CONFIG_NTSYNC=m -CONFIG_EEPROM_MAX6875=m -CONFIG_SENSORS_LIS3_I2C=m -CONFIG_ALTERA_STAPL=m -CONFIG_MISC_RTSX_PCI=m -CONFIG_MISC_RTSX_USB=m -CONFIG_UACCE=m -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_ENCLOSURE=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SAS_ATA=y -CONFIG_ISCSI_TCP=m -CONFIG_SCSI_CXGB4_ISCSI=m -CONFIG_SCSI_BNX2_ISCSI=m -CONFIG_SCSI_BNX2X_FCOE=m -CONFIG_BE2ISCSI=m -CONFIG_SCSI_HPSA=m -CONFIG_SCSI_AACRAID=m -CONFIG_MEGARAID_SAS=m -CONFIG_SCSI_MPT2SAS=m -CONFIG_SCSI_SMARTPQI=m -CONFIG_LIBFC=m -CONFIG_LIBFCOE=m -CONFIG_FCOE=m -CONFIG_SCSI_IPR=m -CONFIG_SCSI_QLA_FC=m -CONFIG_SCSI_QLA_ISCSI=m -CONFIG_QEDI=m -CONFIG_QEDF=m -CONFIG_SCSI_LPFC=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_VIRTIO=y -CONFIG_SCSI_CHELSIO_FCOE=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=y -CONFIG_SCSI_DH_HP_SW=y -CONFIG_SCSI_DH_EMC=y -CONFIG_SCSI_DH_ALUA=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_ATA_PIIX=m -CONFIG_ATA_GENERIC=m -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_DEBUG=y -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_THIN_PROVISIONING=m +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +CONFIG_DEV_DAX_HMEM_DEVICES=y +CONFIG_DEV_DAX_KMEM=m +CONFIG_DEV_DAX_PMEM=m +# CONFIG_DIBS is not set +CONFIG_DIMLIB=y +# CONFIG_DLM is not set +# CONFIG_DM9051 is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMAPOOL_TEST is not set +# CONFIG_DMATEST is not set +CONFIG_DMA_ACPI=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_CMA=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_MAP_BENCHMARK=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_NONCOHERENT_MMAP=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_OF=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_SUN6I is not set +CONFIG_DMI=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DM_AUDIT=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_BUFIO=m CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +# CONFIG_DM_CLONE is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_DEBUG=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_DUST is not set +# CONFIG_DM_EBS is not set CONFIG_DM_ERA=m -CONFIG_DM_MIRROR=m +CONFIG_DM_FLAKEY=m +CONFIG_DM_INTEGRITY=m CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=m CONFIG_DM_MULTIPATH=m +# CONFIG_DM_MULTIPATH_HST is not set +# CONFIG_DM_MULTIPATH_IOA is not set CONFIG_DM_MULTIPATH_QL=m CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_DELAY=m -CONFIG_DM_UEVENT=y -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m +# CONFIG_DM_PCACHE is not set +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=m CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_DM_INTEGRITY=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +# CONFIG_DM_UNSTRIPED is not set CONFIG_DM_VDO=m -CONFIG_TARGET_CORE=m -CONFIG_TCM_IBLOCK=m -CONFIG_TCM_FILEIO=m -CONFIG_TCM_PSCSI=m -CONFIG_TCM_USER2=m -CONFIG_LOOPBACK_TARGET=m -CONFIG_TCM_FC=m -CONFIG_ISCSI_TARGET=m -CONFIG_ISCSI_TARGET_CXGB4=m -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -CONFIG_OVPN=m -CONFIG_EQUALIZER=m -CONFIG_NET_FC=y -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN=m -CONFIG_IPVTAP=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NLMON=m -CONFIG_NET_VRF=m -CONFIG_VSOCKMON=m -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_ADAPTEC is not set -# CONFIG_NET_VENDOR_AGERE is not set -# CONFIG_NET_VENDOR_ALTEON is not set -CONFIG_ENA_ETHERNET=m -CONFIG_ATL1=m -CONFIG_ATL1E=m -CONFIG_ATL1C=m -CONFIG_ALX=m -CONFIG_TIGON3=m -CONFIG_BNX2X=m -CONFIG_BNXT=m -CONFIG_BNXT_DCB=y -# CONFIG_BNXT_HWMON is not set -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=m -CONFIG_THUNDER_NIC_VF=m -CONFIG_CAVIUM_PTP=y -CONFIG_LIQUIDIO=m -CONFIG_LIQUIDIO_VF=m -CONFIG_CHELSIO_T4VF=m -CONFIG_CHELSIO_IPSEC_INLINE=m -CONFIG_CHELSIO_TLS_DEVICE=m -# CONFIG_NET_VENDOR_CISCO is not set -# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_FEC is not set +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +# CONFIG_DM_WRITECACHE is not set +CONFIG_DM_ZERO=m +# CONFIG_DM_ZONED is not set CONFIG_DNET=m -# CONFIG_NET_VENDOR_DEC is not set -# CONFIG_NET_VENDOR_DLINK is not set -# CONFIG_NET_VENDOR_EMULEX is not set -# CONFIG_NET_VENDOR_EZCHIP is not set -# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=y +CONFIG_DP83640_PHY=m +# CONFIG_DP83822_PHY is not set +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +# CONFIG_DP83869_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set +CONFIG_DPLL=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRM=y +# CONFIG_DRM_ACCEL is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ACP is not set +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_FP=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DRM_AMD_ISP is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BRIDGE_CONNECTOR=y +CONFIG_DRM_BUDDY=m +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_CLIENT=y +CONFIG_DRM_CLIENT_DEFAULT="fbdev" +CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y +CONFIG_DRM_CLIENT_LIB=y +# CONFIG_DRM_CLIENT_LOG is not set +CONFIG_DRM_CLIENT_SELECTION=y +CONFIG_DRM_CLIENT_SETUP=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_DP_TUNNEL=y +CONFIG_DRM_DISPLAY_DSC_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DW_HDMI=m +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +# CONFIG_DRM_DW_HDMI_CEC is not set +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_EXEC=m +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=y +# CONFIG_DRM_GM12U320 is not set +CONFIG_DRM_GPUSVM=m +CONFIG_DRM_GPUVM=m +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_ITE_IT6263 is not set +# CONFIG_DRM_ITE_IT6505 is not set +# CONFIG_DRM_ITE_IT66121 is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_KOMEDA is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LOGICVC is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MGAG200=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_CH7006=m +CONFIG_DRM_NOUVEAU_SIL164=m +# CONFIG_DRM_NOVA is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS=m +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TD4320 is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112B is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_HYDIS_HV101HD1 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_RENESAS_R61307 is not set +# CONFIG_DRM_PANEL_RENESAS_R69328 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_SUMMIT is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# CONFIG_DRM_PANIC is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_PIXPAPER is not set +# CONFIG_DRM_POWERVR is not set +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_SAMSUNG_DSIM is not set +CONFIG_DRM_SCHED=m +# CONFIG_DRM_SHMOBILE is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIL_SII8620 is not set +CONFIG_DRM_SIMPLEDRM=y +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_SOLOMON_SSD2825 is not set +# CONFIG_DRM_SSD130X is not set +# CONFIG_DRM_ST7571_I2C is not set +# CONFIG_DRM_ST7586 is not set +# CONFIG_DRM_ST7735R is not set +CONFIG_DRM_SUBALLOC_HELPER=m +# CONFIG_DRM_SUN4I is not set +CONFIG_DRM_SYSFB_HELPER=y +CONFIG_DRM_THEAD_TH1520_DW_HDMI=m +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TI_DLPC3433 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TDP158 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VERISILICON_DC=m +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_WAVESHARE_BRIDGE is not set +# CONFIG_DRM_WERROR is not set +CONFIG_DRM_XE=m +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_MEMIRQ is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_DP_TUNNEL=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_GPUSVM=y +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +CONFIG_DRM_XE_PAGEMAP=y +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +# CONFIG_DS1682 is not set +CONFIG_DST_CACHE=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY=m +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_DUMMY_IRQ is not set +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m +# CONFIG_DVB_AS102 is not set +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_CXD2099=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_CXD2880=m +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_DRXK=m +CONFIG_DVB_DS3000=m +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_EC100=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_L64781=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MB86A20S=m +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_MN88443X=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_MT312=m +CONFIG_DVB_MT352=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_MXL692=m +# CONFIG_DVB_NET is not set +CONFIG_DVB_NXT200X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +# CONFIG_DVB_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLL=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_S921=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_SP2=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0297=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_TC90522=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TS2020=m +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_ULE_DEBUG is not set +# CONFIG_DVB_USB_V2 is not set +CONFIG_DVB_VES1820=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_ZL10353=m +# CONFIG_DWC_PCIE_PMU is not set +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_RENESAS_GBETH=m +CONFIG_DWMAC_SOPHGO=m +CONFIG_DWMAC_SPACEMIT=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_SUN55I=m +CONFIG_DWMAC_SUN8I=m +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_THEAD=m +# CONFIG_DW_AXI_DMAC is not set +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC_PCI=m +# CONFIG_DW_EDMA is not set +CONFIG_DW_WATCHDOG=m +# CONFIG_DW_XDATA_PCIE is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_SIGFRAME=y +# CONFIG_E100 is not set CONFIG_E1000=m CONFIG_E1000E=y -CONFIG_IGB=m -CONFIG_IGBVF=m -CONFIG_IXGBE=m -CONFIG_IXGBE_DCB=y -CONFIG_IXGBEVF=m -CONFIG_I40E=m -CONFIG_I40EVF=m -CONFIG_ICE=m -CONFIG_FM10K=m -# CONFIG_NET_VENDOR_MARVELL is not set -CONFIG_MLX4_EN=m -# CONFIG_MLX4_CORE_GEN2 is not set -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_CORE_IPOIB=y -CONFIG_MLXSW_CORE=m -# CONFIG_MLXSW_SPECTRUM is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NI is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_NETERION is not set -CONFIG_NFP=m -# CONFIG_NET_VENDOR_NVIDIA is not set -CONFIG_ETHOC=m -# CONFIG_NET_VENDOR_PACKET_ENGINES is not set -CONFIG_QLA3XXX=m -CONFIG_NETXEN_NIC=m -CONFIG_QED=m -CONFIG_QEDE=m -# CONFIG_NET_VENDOR_BROCADE is not set -CONFIG_QCOM_EMAC=m -# CONFIG_NET_VENDOR_RDC is not set -CONFIG_8139CP=m -CONFIG_8139TOO=m -# CONFIG_8139TOO_PIO is not set -CONFIG_8139TOO_8129=y -CONFIG_R8169=y -# CONFIG_NET_VENDOR_RENESAS is not set -CONFIG_ROCKER=m -# CONFIG_NET_VENDOR_SAMSUNG is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SILAN is not set -# CONFIG_NET_VENDOR_SIS is not set -CONFIG_SFC=m +# CONFIG_ECRYPT_FS is not set +CONFIG_EDAC=y +# CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_ECS is not set +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_MEM_REPAIR is not set +# CONFIG_EDAC_SCRUB is not set +CONFIG_EDAC_SIFIVE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_M24LR is not set +CONFIG_EEPROM_MAX6875=m +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +# CONFIG_EFI_ZBOOT is not set +# CONFIG_EFS_FS is not set +CONFIG_ELFCORE=y +CONFIG_ELF_CORE=y +CONFIG_ENA_ETHERNET=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENERGY_MODEL is not set CONFIG_EPIC100=m -CONFIG_SMSC911X=m -CONFIG_SMSC9420=m -# CONFIG_NET_VENDOR_SOCIONEXT is not set -CONFIG_STMMAC_ETH=m -CONFIG_DWMAC_THEAD=m -CONFIG_DWMAC_INTEL_PLAT=m -CONFIG_STMMAC_PCI=m -# CONFIG_NET_VENDOR_SUN is not set -# CONFIG_NET_VENDOR_SYNOPSYS is not set -# CONFIG_NET_VENDOR_TEHUTI is not set -# CONFIG_NET_VENDOR_TI is not set -# CONFIG_NET_VENDOR_VIA is not set -CONFIG_NGBE=m -CONFIG_TXGBE=m -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_NET_VENDOR_XILINX is not set -CONFIG_AMD_PHY=m -CONFIG_AQUANTIA_PHY=m -CONFIG_BROADCOM_PHY=m -CONFIG_BCM87XX_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_ICPLUS_PHY=m -CONFIG_LXT_PHY=m -CONFIG_LSI_ET1011C_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MICREL_PHY=m -CONFIG_MICROSEMI_PHY=m -CONFIG_NATIONAL_PHY=m -CONFIG_AT803X_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_STE10XP=m -CONFIG_TERANETICS_PHY=m -CONFIG_DP83848_PHY=m -CONFIG_DP83867_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_PLATFORM=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_MDIO_BITBANG=m -CONFIG_MDIO_BCM_UNIMAC=m -CONFIG_MDIO_GPIO=m -CONFIG_MDIO_OCTEON=m -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=m -CONFIG_PPTP=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -# CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -# CONFIG_WLAN_VENDOR_ATMEL is not set -# CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_INTEL is not set -# CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set -# CONFIG_WLAN_VENDOR_MEDIATEK is not set -CONFIG_RT2X00=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT53XX=y -CONFIG_RTL8180=m -CONFIG_RTL8187=m -CONFIG_RTL8192CE=m -CONFIG_RTL8192SE=m -CONFIG_RTL8192DE=m -CONFIG_RTL8723AE=m -CONFIG_RTL8723BE=m -CONFIG_RTL8188EE=m -CONFIG_RTL8192EE=m -CONFIG_RTL8821AE=m -CONFIG_RTL8192CU=m -CONFIG_RTL8192DU=m -# CONFIG_RTLWIFI_DEBUG is not set -CONFIG_RTL8XXXU=m -CONFIG_RTW88=m -CONFIG_RTW88_8822BE=m -CONFIG_RTW88_8822BS=m -CONFIG_RTW88_8822BU=m -CONFIG_RTW88_8822CE=m -CONFIG_RTW88_8822CS=m -CONFIG_RTW88_8822CU=m -CONFIG_RTW88_8723DE=m -CONFIG_RTW88_8723DS=m -CONFIG_RTW88_8723CS=m -CONFIG_RTW88_8723DU=m -CONFIG_RTW88_8821CE=m -CONFIG_RTW88_8821CS=m -CONFIG_RTW88_8821CU=m -CONFIG_RTW88_8821AU=m -CONFIG_RTW88_8812AU=m -CONFIG_RTW88_8814AE=m -CONFIG_RTW88_8814AU=m -CONFIG_RTW89=m -CONFIG_RTW89_8851BE=m -CONFIG_RTW89_8851BU=m -CONFIG_RTW89_8852AE=m -CONFIG_RTW89_8852BE=m -CONFIG_RTW89_8852BU=m -CONFIG_RTW89_8852BTE=m -CONFIG_RTW89_8852CE=m -CONFIG_RTW89_8922AE=m -# CONFIG_WLAN_VENDOR_RSI is not set -# CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set -# CONFIG_WLAN_VENDOR_ZYDAS is not set -# CONFIG_WLAN_VENDOR_QUANTENNA is not set -CONFIG_WAN=y +CONFIG_EPOLL=y +CONFIG_EPROBE_EVENTS=y +CONFIG_EQUALIZER=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_BACKED_BY_FILE=y +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ACCEL is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +# CONFIG_EROFS_FS_ZIP_LZMA is not set +# CONFIG_EROFS_FS_ZIP_ZSTD is not set +CONFIG_ERRATA_ANDES=y +CONFIG_ERRATA_MIPS=y +CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_MAE=y +CONFIG_ERRATA_THEAD_PMU=y +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_EVENTFD=y +CONFIG_EVENT_TRACING=y +CONFIG_EVM=y +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +CONFIG_EVM_LOAD_X509=y +CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=y +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXTCON=y +# CONFIG_EXTCON_FSA9480 is not set +CONFIG_EXTCON_GPIO=m +# CONFIG_EXTCON_LC824206XA is not set +# CONFIG_EXTCON_MAX14526 is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTENDED_MODVERSIONS=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +# CONFIG_FARSYNC is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_FB=y +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_CARMINE is not set +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CIRRUS is not set +CONFIG_FB_CORE=y +# CONFIG_FB_CYBER2000 is not set +CONFIG_FB_DDC=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +# CONFIG_FB_KYRO is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_NEOMAGIC is not set +CONFIG_FB_NOTIFY=y +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_RADEON_I2C=y +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_SSD1307=m +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +CONFIG_FCOE=m +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +CONFIG_FHANDLE=y +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_FIRMWARE_TABLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FM10K=m +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_FPGA is not set +# CONFIG_FPROBE is not set +CONFIG_FPU=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMER is not set +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +# CONFIG_FSCACHE is not set +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_DAX is not set +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +# CONFIG_FS_VERITY is not set +# CONFIG_FTL is not set +CONFIG_FTRACE=y +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set +# CONFIG_FUEL_GAUGE_STC3117 is not set +# CONFIG_FUJITSU_ES is not set +CONFIG_FUNCTION_ALIGNMENT=8 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ALIGNMENT_8B=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FUNCTION_GRAPH_RETADDR is not set +# CONFIG_FUNCTION_GRAPH_RETVAL is not set +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_TRACE_ARGS=y +# CONFIG_FUN_ETH is not set +CONFIG_FUSE_FS=y +CONFIG_FUSE_IO_URING=y +CONFIG_FUSE_PASSTHROUGH=y +# CONFIG_FUSION is not set +CONFIG_FUTEX=y +CONFIG_FUTEX_MPOL=y +CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y +# CONFIG_FWCTL is not set +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_FW_UPLOAD=y +CONFIG_GACT_PROB=y +# CONFIG_GAMEPORT is not set +CONFIG_GARP=m +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_GCC_VERSION=150300 +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_GENDWARFKSYMS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_NUMA=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_ENTRY=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_SYSCALL=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_TRACER=y +CONFIG_GENEVE=m +# CONFIG_GENKSYMS is not set +# CONFIG_GENWQE is not set +CONFIG_GET_FREE_REGION=y +# CONFIG_GFS2_FS is not set +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GNSS is not set +CONFIG_GOLDFISH=y +# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH_TTY is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIOLIB_LEGACY=y +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +CONFIG_GPIO_ACPI=y +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_BT8XX is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +# CONFIG_GPIO_DS4520 is not set +CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_FXL6408 is not set +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=m +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPSSE is not set +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_POLARFIRE_SOC is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_SIM is not set +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +CONFIG_GPIO_SPACEMIT_K1=y +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SYSFS_LEGACY=y +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set +CONFIG_GPIO_WATCHDOG=m +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_GP_PCI1XXXX is not set +CONFIG_GRACE_PERIOD=y +# CONFIG_GREENASIA_FF is not set +# CONFIG_GREYBUS is not set +CONFIG_GROUP_SCHED_BANDWIDTH=y +CONFIG_GROUP_SCHED_WEIGHT=y +CONFIG_GRO_CELLS=y +# CONFIG_GTP is not set +CONFIG_GUEST_PERF_EVENTS=y +# CONFIG_GUP_TEST is not set +# CONFIG_HAMRADIO is not set +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_DEFAULT_ON=y +CONFIG_HARDIRQS_SW_RESEND=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_SECURITY_AUDIT=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_HAVE_ARCH_KFENCE=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_HAVE_ARCH_KSTACK_ERASE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_GRAPH_FUNC=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_TIF_BITS=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_GIGANTIC_FOLIOS=y +CONFIG_HAVE_GUP_FAST=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_UNCOMPRESSED=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KVM_DIRTY_RING=y +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_READONLY_MEM=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_TRUSTED_KEYS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HD44780 is not set CONFIG_HDLC=m -CONFIG_HDLC_RAW=m CONFIG_HDLC_CISCO=m CONFIG_HDLC_FR=m CONFIG_HDLC_PPP=m -CONFIG_USB4_NET=m -CONFIG_INPUT_SPARSEKMAP=m -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_EVDEV=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_MOUSE_PS2_ELANTECH=y -CONFIG_MOUSE_PS2_SENTELIC=y -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -CONFIG_MOUSE_CYAPA=m -CONFIG_MOUSE_VSXXXAA=m -CONFIG_MOUSE_SYNAPTICS_I2C=m -CONFIG_MOUSE_SYNAPTICS_USB=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_RMI4_I2C=m -CONFIG_RMI4_SPI=m -CONFIG_RMI4_SMB=m -CONFIG_SERIO_RAW=m -CONFIG_SERIO_ALTERA_PS2=m -CONFIG_SERIO_ARC_PS2=m -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_EARLYCON_RISCV_SBI=y -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_N_HDLC=m -CONFIG_N_GSM=m -CONFIG_TTY_PRINTK=m -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SSIF=m -CONFIG_IPMI_WATCHDOG=m -CONFIG_IPMI_POWEROFF=m +CONFIG_HDLC_RAW=m +# CONFIG_HDLC_RAW_ETH is not set +CONFIG_HDMI=y +CONFIG_HEADERS_INSTALL=y +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFS_FS is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_DEF_COMP="lzo" +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +# CONFIG_HIBMCGE is not set +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +CONFIG_HID_ACRUX=m +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_ALPS is not set +CONFIG_HID_APPLE=y +CONFIG_HID_APPLEIR=m +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BETOP_FF=m +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_BPF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CORSAIR=m +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=m +# CONFIG_HID_ELAN is not set +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EVISION is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=y +CONFIG_HID_GFRM=m +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_GOODIX_SPI is not set +# CONFIG_HID_GOOGLE_STADIA_FF is not set +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +# CONFIG_HID_HAPTIC is not set +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=y +# CONFIG_HID_JABRA is not set +CONFIG_HID_KENSINGTON=y +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +# CONFIG_HID_KYSONA is not set +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +# CONFIG_HID_MACALLY is not set +CONFIG_HID_MAGICMOUSE=y +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MCP2200 is not set +# CONFIG_HID_MCP2221 is not set +# CONFIG_HID_MEGAWORLD_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=m +# CONFIG_HID_NINTENDO is not set +# CONFIG_HID_NTI is not set +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_RETRODE is not set +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_SENSOR_HUB=m +# CONFIG_HID_SIGMAMICRO is not set +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +# CONFIG_HID_STEAM is not set +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +# CONFIG_HID_TOPRE is not set +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +# CONFIG_HID_U2FZERO is not set +CONFIG_HID_UCLOGIC=m +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_UNIVERSAL_PIDFF is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_VRC2 is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set +# CONFIG_HID_XIAOMI is not set +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_HMC6352 is not set +CONFIG_HMEM_REPORTING=y +CONFIG_HMM_MIRROR=y +# CONFIG_HOLTEK_FF is not set +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_OCTEONEP is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +# CONFIG_HPFS_FS is not set +# CONFIG_HP_ILO is not set +CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HT16K33 is not set +# CONFIG_HTE is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HVC_DRIVER=y +CONFIG_HWLAT_TRACER=y +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON_VID=m +CONFIG_HWSPINLOCK=y +# CONFIG_HWSPINLOCK_SUN6I is not set CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_JH7110 is not set CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y CONFIG_HW_RANDOM_VIRTIO=y -# CONFIG_DEVPORT is not set -CONFIG_TCG_TIS=y -CONFIG_TCG_TIS_SPI=y -CONFIG_TCG_TIS_I2C_ATMEL=m -CONFIG_TCG_TIS_I2C_INFINEON=m -CONFIG_TCG_TIS_I2C_NUVOTON=m -CONFIG_TCG_ATMEL=m -CONFIG_TCG_TIS_ST33ZP24_I2C=m -CONFIG_TCG_TIS_ST33ZP24_SPI=m +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=m +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +# CONFIG_I2C_AT91 is not set +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_CCGX_UCSI=m CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DIOLAN_U2C=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_CORE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +CONFIG_I2C_K1=m +# CONFIG_I2C_MICROCHIP_CORE is not set CONFIG_I2C_MUX=m -CONFIG_I2C_ARB_GPIO_CHALLENGE=m CONFIG_I2C_MUX_GPIO=m +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_MULE is not set CONFIG_I2C_MUX_PCA9541=m CONFIG_I2C_MUX_PCA954x=m CONFIG_I2C_MUX_PINCTRL=m -CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MV64XXX is not set CONFIG_I2C_NFORCE2=m -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_SLAVE=y -CONFIG_I2C_DESIGNWARE_PCI=m -CONFIG_I2C_GPIO=m -CONFIG_I2C_K1=m +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_NVIDIA_GPU is not set CONFIG_I2C_OCORES=m CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RIIC is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_RZV2M is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set CONFIG_I2C_SIMTEC=m -CONFIG_I2C_DIOLAN_U2C=m -CONFIG_I2C_TINY_USB=m -CONFIG_I2C_STUB=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=m -CONFIG_SPI=y -CONFIG_SPI_CADENCE=m -CONFIG_SPI_DESIGNWARE=y -CONFIG_SPI_DW_PCI=m -CONFIG_SPI_DW_MMIO=y -CONFIG_SPI_FSL_QUADSPI=m -CONFIG_SPI_SIFIVE=y -CONFIG_SPI_SG2044_NOR=m -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_GPIO=m -CONFIG_DP83640_PHY=m -CONFIG_PINCTRL_TH1520=y -CONFIG_PINCTRL_SOPHGO_SG2042=y -CONFIG_PINCTRL_SOPHGO_SG2044=y -CONFIG_PINCTRL_ULTRARISC_DP1000=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_CADENCE=m -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC_PLATFORM=m -CONFIG_GPIO_SIFIVE=y -CONFIG_GPIO_SPACEMIT_K1=y -CONFIG_GPIO_PCA953X=m -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_TH1520_AON=m -CONFIG_POWER_SEQUENCING=m -CONFIG_POWER_SEQUENCING_TH1520_GPU=m -CONFIG_CHARGER_SMB347=m -CONFIG_SENSORS_AD7314=m -CONFIG_SENSORS_AD7414=m -CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1025=m -CONFIG_SENSORS_ADM1026=m -CONFIG_SENSORS_ADM1029=m -CONFIG_SENSORS_ADM1031=m -CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_ADT7310=m -CONFIG_SENSORS_ADT7410=m -CONFIG_SENSORS_ADT7411=m -CONFIG_SENSORS_ADT7462=m -CONFIG_SENSORS_ADT7470=m -CONFIG_SENSORS_ADT7475=m -CONFIG_SENSORS_ASC7621=m -CONFIG_SENSORS_ATXP1=m -CONFIG_SENSORS_COREPVT_ULTRARISC=m -CONFIG_SENSORS_DS620=m -CONFIG_SENSORS_DS1621=m -CONFIG_SENSORS_F71805F=m -CONFIG_SENSORS_F71882FG=m -CONFIG_SENSORS_F75375S=m -CONFIG_SENSORS_GL518SM=m -CONFIG_SENSORS_GL520SM=m -CONFIG_SENSORS_G760A=m -CONFIG_SENSORS_G762=m -CONFIG_SENSORS_IBMAEM=m -CONFIG_SENSORS_IBMPEX=m -CONFIG_SENSORS_IT87=m -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_POWR1220=m -CONFIG_SENSORS_LINEAGE=m -CONFIG_SENSORS_LTC2945=m -CONFIG_SENSORS_LTC4151=m -CONFIG_SENSORS_LTC4215=m -CONFIG_SENSORS_LTC4222=m -CONFIG_SENSORS_LTC4245=m -CONFIG_SENSORS_LTC4260=m -CONFIG_SENSORS_LTC4261=m -CONFIG_SENSORS_MAX1111=m -CONFIG_SENSORS_MAX16065=m -CONFIG_SENSORS_MAX1619=m -CONFIG_SENSORS_MAX1668=m -CONFIG_SENSORS_MAX197=m -CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6650=m -CONFIG_SENSORS_MAX6697=m -CONFIG_SENSORS_MAX31790=m -CONFIG_SENSORS_MCP3021=m -CONFIG_SENSORS_MR75203=m -CONFIG_SENSORS_ADCXX=m -CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM70=m -CONFIG_SENSORS_LM73=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM77=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM80=m -CONFIG_SENSORS_LM83=m -CONFIG_SENSORS_LM85=m -CONFIG_SENSORS_LM87=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_LM92=m -CONFIG_SENSORS_LM93=m -CONFIG_SENSORS_LM95234=m -CONFIG_SENSORS_LM95241=m -CONFIG_SENSORS_LM95245=m -CONFIG_SENSORS_PC87360=m -CONFIG_SENSORS_PC87427=m -CONFIG_SENSORS_NCT6683=m -CONFIG_SENSORS_NCT7802=m -CONFIG_SENSORS_NCT7904=m -CONFIG_SENSORS_PCF8591=m -CONFIG_PMBUS=m -CONFIG_SENSORS_ADM1275=m -CONFIG_SENSORS_LM25066=m -CONFIG_SENSORS_LTC2978=m -CONFIG_SENSORS_LTC3815=m -CONFIG_SENSORS_MAX16064=m -CONFIG_SENSORS_MAX20751=m -CONFIG_SENSORS_MAX34440=m -CONFIG_SENSORS_MAX8688=m -CONFIG_SENSORS_TPS40422=m -CONFIG_SENSORS_UCD9000=m -CONFIG_SENSORS_UCD9200=m -CONFIG_SENSORS_ZL6100=m -CONFIG_SENSORS_PWM_FAN=y -CONFIG_SENSORS_SHT15=m -CONFIG_SENSORS_SHT21=m -CONFIG_SENSORS_SHTC1=m -CONFIG_SENSORS_SIS5595=m -CONFIG_SENSORS_DME1737=m -CONFIG_SENSORS_EMC1403=m -CONFIG_SENSORS_EMC6W201=m -CONFIG_SENSORS_SMSC47M1=m -CONFIG_SENSORS_SMSC47M192=m -CONFIG_SENSORS_SMSC47B397=m -CONFIG_SENSORS_SCH5627=m -CONFIG_SENSORS_SCH5636=m -CONFIG_SENSORS_SG2042_MCU=m -CONFIG_SENSORS_ADC128D818=m -CONFIG_SENSORS_ADS7828=m -CONFIG_SENSORS_ADS7871=m -CONFIG_SENSORS_AMC6821=m -CONFIG_SENSORS_INA209=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_TC74=m -CONFIG_SENSORS_THMC50=m -CONFIG_SENSORS_TMP102=m -CONFIG_SENSORS_TMP103=m -CONFIG_SENSORS_TMP401=m -CONFIG_SENSORS_TMP421=m -CONFIG_SENSORS_VIA686A=m -CONFIG_SENSORS_VT1211=m -CONFIG_SENSORS_VT8231=m -CONFIG_SENSORS_W83781D=m -CONFIG_SENSORS_W83791D=m -CONFIG_SENSORS_W83792D=m -CONFIG_SENSORS_W83793=m -CONFIG_SENSORS_W83795=m -CONFIG_SENSORS_W83L785TS=m -CONFIG_SENSORS_W83L786NG=m -CONFIG_SENSORS_W83627HF=m -CONFIG_SENSORS_W83627EHF=m -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_SPACEMIT_K1_TSENSOR=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_SYSFS=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_DA9063_WATCHDOG=m -CONFIG_GPIO_WATCHDOG=m -CONFIG_DW_WATCHDOG=m -CONFIG_ALIM7101_WDT=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_STUB=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VIRTIO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2C_ZHAOXIN is not set +# CONFIG_I3C is not set +CONFIG_I40E=m +CONFIG_I40EVF=m +# CONFIG_I40E_DCB is not set CONFIG_I6300ESB_WDT=m -CONFIG_PCIPCWATCHDOG=m -CONFIG_WDTPCI=m -CONFIG_USBPCWATCHDOG=m -CONFIG_BCMA=m -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_MFD_DA9063=m -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PWM=y -# CONFIG_MEDIA_CEC_SUPPORT is not set -CONFIG_MEDIA_SUPPORT=m -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -# CONFIG_DVB_NET is not set -# CONFIG_DVB_DYNAMIC_MINORS is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_AUXDISPLAY=y -CONFIG_DRM=y -CONFIG_DRM_LOAD_EDID_FIRMWARE=y -CONFIG_DRM_SIMPLEDRM=y -CONFIG_DRM_RADEON=m -CONFIG_DRM_RADEON_USERPTR=y -CONFIG_DRM_AMDGPU=m -CONFIG_DRM_AMDGPU_SI=y -CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMD_DC_SI=y -CONFIG_HSA_AMD=y -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_XE=m -CONFIG_DRM_UDL=m -CONFIG_DRM_AST=m -CONFIG_DRM_MGAG200=m -CONFIG_DRM_QXL=m -CONFIG_DRM_VIRTIO_GPU=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_THEAD_TH1520_DW_HDMI=m -CONFIG_DRM_BOCHS=m -CONFIG_DRM_CIRRUS_QEMU=m -CONFIG_DRM_VERISILICON_DC=m -CONFIG_FB=y -CONFIG_FB_EFI=y -CONFIG_FB_RADEON=y -CONFIG_FB_SSD1307=m -CONFIG_FB_TILEBLITTING=y -CONFIG_LCD_CLASS_DEVICE=m -CONFIG_LCD_PLATFORM=m -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_BACKLIGHT_GPIO=m -CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_ALOOP=m -CONFIG_SND_HDA_INTEL=m -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_SOC=m -CONFIG_SND_SOC_K1_I2S=m -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HIDRAW=y -CONFIG_UHID=m -CONFIG_HID_A4TECH=y -CONFIG_HID_ACRUX=m -CONFIG_HID_APPLE=y -CONFIG_HID_APPLEIR=m -CONFIG_HID_AUREAL=m -CONFIG_HID_BELKIN=y -CONFIG_HID_BETOP_FF=m -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CORSAIR=m -CONFIG_HID_CYPRESS=y -CONFIG_HID_DRAGONRISE=m -CONFIG_HID_ELECOM=m -CONFIG_HID_ELO=m -CONFIG_HID_EZKEY=y -CONFIG_HID_GEMBIRD=m -CONFIG_HID_GFRM=m -CONFIG_HID_HOLTEK=m -CONFIG_HID_GT683R=m -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_GYRATION=m -CONFIG_HID_ICADE=m -CONFIG_HID_ITE=y -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=y -CONFIG_HID_LCPOWER=m -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NTRIG=y -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_HID_PENMOUNT=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PLANTRONICS=m -CONFIG_HID_PRIMAX=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_SONY_FF=y -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_STEELSERIES=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_RMI=m -CONFIG_HID_GREENASIA=m -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_THINGM=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -CONFIG_HID_XINMO=m -CONFIG_HID_ZEROPLUS=m -CONFIG_HID_ZYDACRON=m -CONFIG_HID_SENSOR_HUB=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_I2C_HID_OF_ELAN=m -CONFIG_I2C_HID_OF_GOODIX=m -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_LED_TRIG=y -CONFIG_USB_ULPI_BUS=m -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=m -CONFIG_USB_MON=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_PRINTER=m -CONFIG_USB_TMC=m -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=y -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_DWC3=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_HSIC_USB3503=m -CONFIG_USB_CHAOSKEY=m -CONFIG_USB_ONBOARD_DEV=m -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_UCSI=m -CONFIG_TYPEC_DP_ALTMODE=m -CONFIG_USB_ROLE_SWITCH=y -CONFIG_MMC=y -CONFIG_PWRSEQ_EMMC=m -CONFIG_PWRSEQ_SIMPLE=m -CONFIG_SDIO_UART=m -CONFIG_MMC_CRYPTO=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PCI=m -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=m -CONFIG_MMC_SDHCI_OF_K1=m -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_TIFM_SD=m -CONFIG_MMC_SPI=y -CONFIG_MMC_CB710=m -CONFIG_MMC_VIA_SDMMC=m -CONFIG_MMC_DW=m -CONFIG_MMC_DW_BLUEFIELD=m -CONFIG_MMC_DW_PCI=m -CONFIG_MMC_VUB300=m -CONFIG_MMC_USHC=m -CONFIG_MMC_REALTEK_PCI=m -CONFIG_MMC_REALTEK_USB=m -CONFIG_MMC_CQHCI=y -CONFIG_MMC_TOSHIBA_PCI=m -CONFIG_MMC_MTK=m -CONFIG_MMC_SDHCI_XENON=m -CONFIG_MEMSTICK=m -CONFIG_MSPRO_BLOCK=m -CONFIG_MEMSTICK_TIFM_MS=m -CONFIG_MEMSTICK_JMICRON_38X=m -CONFIG_MEMSTICK_R592=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_CLASS_FLASH=m -CONFIG_LEDS_LM3530=m -CONFIG_LEDS_LP3944=m -CONFIG_LEDS_LT3593=m -CONFIG_LEDS_BLINKM=m -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_ONESHOT=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_IAVF=m +CONFIG_ICE=m +CONFIG_ICE_HWMON=y +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICPLUS_PHY=m +# CONFIG_ICS932S401 is not set +CONFIG_IDLE_PAGE_TRACKING=y +# CONFIG_IDPF is not set +# CONFIG_IEEE802154 is not set +CONFIG_IFB=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGB_HWMON=y +# CONFIG_IGC is not set +# CONFIG_IIO is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMA=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +# CONFIG_IMA_APPRAISE_MODSIG is not set +# CONFIG_IMA_APPRAISE_SIGNED_INIT is not set +# CONFIG_IMA_ARCH_POLICY is not set +# CONFIG_IMA_BLACKLIST_KEYRING is not set +CONFIG_IMA_DEFAULT_HASH="sha256" +# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set +CONFIG_IMA_DEFAULT_HASH_SHA256=y +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +# CONFIG_IMA_DEFAULT_HASH_SM3 is not set +CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" +# CONFIG_IMA_DISABLE_HTABLE is not set +# CONFIG_IMA_KEXEC is not set +# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set +CONFIG_IMA_LOAD_X509=y +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y +CONFIG_IMA_READ_POLICY=y +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_WRITE_POLICY is not set +CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_INET=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=m +# CONFIG_INET_PSP is not set +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_SCTP_DIAG=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_XFRM_TUNNEL=m CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_MAD=m -CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y CONFIG_INFINIBAND_BNXT_RE=m CONFIG_INFINIBAND_CXGB4=m -CONFIG_MLX4_INFINIBAND=m -CONFIG_MLX5_INFINIBAND=m -CONFIG_INFINIBAND_QEDR=m -CONFIG_RDMA_RXE=m +# CONFIG_INFINIBAND_EFA is not set +# CONFIG_INFINIBAND_ERDMA is not set CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB_CM=y # CONFIG_INFINIBAND_IPOIB_DEBUG is not set -CONFIG_INFINIBAND_SRP=m -CONFIG_INFINIBAND_SRPT=m CONFIG_INFINIBAND_ISER=m CONFIG_INFINIBAND_ISERT=m -CONFIG_EDAC=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_SYSTOHC is not set -CONFIG_RTC_DRV_ABB5ZES3=m -CONFIG_RTC_DRV_ABX80X=m -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_DS1374=m -CONFIG_RTC_DRV_DS1374_WDT=y -CONFIG_RTC_DRV_DS1672=m -CONFIG_RTC_DRV_MAX6900=m -CONFIG_RTC_DRV_RS5C372=m -CONFIG_RTC_DRV_ISL1208=m -CONFIG_RTC_DRV_ISL12022=m -CONFIG_RTC_DRV_X1205=m -CONFIG_RTC_DRV_PCF8523=m -CONFIG_RTC_DRV_PCF8563=m -CONFIG_RTC_DRV_PCF8583=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_M41T80_WDT=y -CONFIG_RTC_DRV_BQ32K=m -CONFIG_RTC_DRV_FM3130=m -CONFIG_RTC_DRV_RX8010=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RX8025=m -CONFIG_RTC_DRV_EM3027=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_M41T93=m -CONFIG_RTC_DRV_M41T94=m -CONFIG_RTC_DRV_DS1305=m -CONFIG_RTC_DRV_DS1343=m -CONFIG_RTC_DRV_DS1347=m -CONFIG_RTC_DRV_DS1390=m -CONFIG_RTC_DRV_R9701=m -CONFIG_RTC_DRV_RX4581=m -CONFIG_RTC_DRV_RS5C348=m -CONFIG_RTC_DRV_MAX6902=m -CONFIG_RTC_DRV_PCF2123=m -CONFIG_RTC_DRV_MCP795=m -CONFIG_RTC_DRV_DS3232=m -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_RV3029C2=m -# CONFIG_RTC_DRV_RV3029_HWMON is not set -CONFIG_RTC_DRV_DS1286=m -CONFIG_RTC_DRV_DS1511=m -CONFIG_RTC_DRV_DS1553=m -CONFIG_RTC_DRV_DS1685_FAMILY=m -CONFIG_RTC_DRV_DS1742=m -CONFIG_RTC_DRV_DS2404=m -CONFIG_RTC_DRV_DA9063=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_STK17TA8=m -CONFIG_RTC_DRV_M48T35=m -CONFIG_RTC_DRV_M48T59=m -CONFIG_RTC_DRV_MSM6242=m -CONFIG_RTC_DRV_RP5C01=m -CONFIG_DMADEVICES=y -CONFIG_QCOM_HIDMA_MGMT=m -CONFIG_QCOM_HIDMA=m -CONFIG_DW_DMAC=m -CONFIG_DW_DMAC_PCI=m -CONFIG_ASYNC_TX_DMA=y +# CONFIG_INFINIBAND_MTHCA is not set +# CONFIG_INFINIBAND_OCRDMA is not set +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_RTRS_CLIENT is not set +# CONFIG_INFINIBAND_RTRS_SERVER is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_VIRT_DMA=y +# CONFIG_INFTL is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_STACK_NONE=y +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_AW86927 is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_DA9063_ONKEY is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_IBM_PANEL is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_VIVALDIFMAP=y +# CONFIG_INPUT_YEALINK is not set +CONFIG_INTEGRITY=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_INTEGRITY_MACHINE_KEYRING is not set +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_TH is not set +# CONFIG_INTEL_XWAY_PHY is not set +CONFIG_INTERCONNECT=y +CONFIG_INTERVAL_TREE=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IONIC is not set +CONFIG_IOSCHED_BFQ=y +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IO_URING_MOCK_FILE is not set +CONFIG_IO_URING_ZCRX=y +CONFIG_IO_WQ=y +# CONFIG_IP5XXX_POWER is not set +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_MATCH_SRH is not set +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +# CONFIG_IPACK_BUS is not set +CONFIG_IPC_NS=y +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_IPMB is not set +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPV6=y +CONFIG_IPV6_GRE=m +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +# CONFIG_IPV6_SUBTREES is not set +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPVLAN=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVTAP=m +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +# CONFIG_IP_SET_HASH_IPMAC is not set +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +# CONFIG_IP_VS_MH is not set +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +# CONFIG_IP_VS_TWOS is not set +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IRQCHIP=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TCP=m +# CONFIG_ISDN is not set +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_ISO9660_FS=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_JH71XX_PMU=y +# CONFIG_JME is not set +CONFIG_JOLIET=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KARMA_PARTITION=y +# CONFIG_KASAN is not set +CONFIG_KCMP=y +# CONFIG_KCOV is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x0 +CONFIG_KDB_KEYBOARD=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_UNCOMPRESSED=y +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KERNFS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_ELF=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_KEY_DH_OPERATIONS is not set +CONFIG_KFENCE=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=100 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +CONFIG_KGDB_TESTS=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +CONFIG_KPROBES=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_KSM=y +# CONFIG_KUNIT is not set +CONFIG_KVFREE_RCU_BATCHED=y +CONFIG_KVM=m +CONFIG_KVM_COMMON=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_KVM_GENERIC_MMU_NOTIFIER=y +CONFIG_KVM_MMIO=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP_V3=y +# CONFIG_LAPB is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LCD2S is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_PARTITION is not set +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set +CONFIG_LD_IS_BFD=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_LD_VERSION=24690 +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_AW200XX is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_BLINKM=m +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3601X is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3697 is not set +CONFIG_LEDS_LP3944=m +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LP8864 is not set +CONFIG_LEDS_LT3593=m +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_ST1202 is not set +# CONFIG_LEDS_SY7802 is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_TPS6131X is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +CONFIG_LEDS_TRIGGER_ONESHOT=m +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +# CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LIBETH=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y +CONFIG_LIBIE=m +CONFIG_LIBIE_ADMINQ=m +CONFIG_LIBIE_FWLOG=m +CONFIG_LIBNVDIMM=m +CONFIG_LIBWX=m +CONFIG_LINEAR_RANGES=y +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_CORE=m +CONFIG_LIQUIDIO_VF=m +CONFIG_LIST_HARDENED=y +# CONFIG_LITEX_LITEETH is not set +# CONFIG_LITEX_SOC_CONTROLLER is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +CONFIG_LLD_VERSION=0 +# CONFIG_LMK04832 is not set +CONFIG_LOAD_UEFI_KEYS=y +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKD=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=20 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOOPBACK_TARGET=m +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +CONFIG_LRU_CACHE=m +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" +CONFIG_LSM_MMAP_MIN_ADDR=32768 +CONFIG_LTO_NONE=y +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_LXT_PHY=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211=m +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_HWSIM is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +# CONFIG_MAC_PARTITION is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +# CONFIG_MANAGER_SBS is not set +CONFIG_MARVELL_10G_PHY=m +# CONFIG_MARVELL_88Q2XXX_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +CONFIG_MARVELL_PHY=m +# CONFIG_MAX31827 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX6959 is not set +# CONFIG_MAXLINEAR_86110_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +CONFIG_MAX_SKB_FRAGS=17 +# CONFIG_MCB is not set +CONFIG_MCHP_CLK_MPFS=y +# CONFIG_MCHP_LAN966X_PCI is not set +# CONFIG_MCHP_SBI_IPC_MBOX is not set +# CONFIG_MCTP is not set +CONFIG_MD=y +CONFIG_MDIO=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_MVUSB is not set +CONFIG_MDIO_OCTEON=m +# CONFIG_MDIO_SUN4I is not set +CONFIG_MDIO_THUNDER=m +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP=y +CONFIG_MD_BITMAP_FILE=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_LLBITMAP is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MEDIATEK_GE_PHY is not set +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +CONFIG_MEGARAID_SAS=m +CONFIG_MEMBARRIER=y +CONFIG_MEMCG=y +# CONFIG_MEMCG_V1 is not set +CONFIG_MEMFD_CREATE=y +# CONFIG_MEMORY is not set +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMREGION=y +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +# CONFIG_MEMSTICK_REALTEK_USB is not set +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +# CONFIG_MEMTEST is not set +# CONFIG_MEM_ALLOC_PROFILING is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_ADP5585 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_AT91_USART is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_BQ257XX is not set +CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +CONFIG_MFD_DA9063=m +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_LS2K_BMC_CORE is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX5970 is not set +# CONFIG_MFD_MAX7360 is not set +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77705 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77759 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_NCT6694 is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_SEC_I2C is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMPRO is not set +CONFIG_MFD_SPACEMIT_P1=m +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_SUN4I_GPADC is not set +# CONFIG_MFD_SUN6I_PRCM is not set +# CONFIG_MFD_SY7636A is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE is not set +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set +CONFIG_MHP_MEMMAP_ON_MEMORY=y +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1S_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROSEMI_PHY=m +CONFIG_MIGRATION=y +CONFIG_MII=m +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_MIN_HEAP=y +# CONFIG_MISC_ALCOR_PCI is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISC_RP1 is not set +CONFIG_MISC_RTSX=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MLX4_CORE=m +# CONFIG_MLX4_CORE_GEN2 is not set +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_DPLL is not set +CONFIG_MLX5_EN_ARFS=y +# CONFIG_MLX5_EN_IPSEC is not set +CONFIG_MLX5_EN_RXNFC=y +# CONFIG_MLX5_EN_TLS is not set +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_HW_STEERING=y +CONFIG_MLX5_INFINIBAND=m +# CONFIG_MLX5_MACSEC is not set +CONFIG_MLX5_MPFS=y +# CONFIG_MLX5_SF is not set +CONFIG_MLX5_SW_STEERING=y +# CONFIG_MLX5_VFIO_PCI is not set +CONFIG_MLXFW=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +# CONFIG_MLXSW_SPECTRUM is not set +CONFIG_MMC=y +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=y +CONFIG_MMC_CRYPTO=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_BLUEFIELD=m +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_MTK=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_ACPI is not set +CONFIG_MMC_SDHCI_CADENCE=y +# CONFIG_MMC_SDHCI_F_SDH30 is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_OF_K1=m +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_UHS2=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHI is not set +# CONFIG_MMC_SH_MMCIF is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_SUNXI is not set +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_TOSHIBA_PCI=m +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMIOWB=y +CONFIG_MMP_PDMA=m +CONFIG_MMU=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MM_ID=y +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ALL=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_DECOMPRESS=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULE_SIG_HASH="sha256" +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_SHA1 is not set +CONFIG_MODULE_SIG_SHA256=y +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +# CONFIG_MOST is not set +# CONFIG_MOTORCOMM_PHY is not set +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXTET is not set +CONFIG_MPILIB=y +CONFIG_MPLS=y +# CONFIG_MPLS_ROUTING is not set +CONFIG_MPTCP=y +CONFIG_MPTCP_IPV6=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_MRP=m +# CONFIG_MSCC_OCELOT_SWITCH is not set +CONFIG_MSDOS_FS=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSE102X is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set +CONFIG_MTD=m +# CONFIG_MTD_ABSENT is not set +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +# CONFIG_MTD_BLOCK_RO is not set +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CMDLINE_PARTS=m +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD_INTEL_DG is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PHRAM is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_NVMEM is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTIUSER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MYRI10GE is not set +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +# CONFIG_NCN26000_PHY is not set +CONFIG_ND_BTT=m +CONFIG_ND_CLAIM=y +CONFIG_ND_PFN=m +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET=y +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVSIM is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XTABLES_LEGACY is not set +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_NETFILTER_XT_NAT is not set +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +# CONFIG_NETFILTER_XT_TARGET_HL is not set +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_MASQUERADE is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +# CONFIG_NETFS_DEBUG is not set +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETKIT is not set +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=y +CONFIG_NETPOLL=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETXEN_NIC=m +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +# CONFIG_NET_9P_RDMA is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_ACT_BPF=m +# CONFIG_NET_ACT_CONNMARK is not set +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_GACT=m +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_ACT_IFE is not set +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CORE=y +CONFIG_NET_CRC32C=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NET_DROP_MONITOR=m +# CONFIG_NET_DSA is not set +CONFIG_NET_EGRESS=y +CONFIG_NET_EMATCH=y +# CONFIG_NET_EMATCH_CANID is not set +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_FAILOVER=y +CONFIG_NET_FC=y +CONFIG_NET_FLOW_LIMIT=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_NET_HANDSHAKE=y +# CONFIG_NET_IFE is not set +CONFIG_NET_INGRESS=y +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_NET_NCSI is not set +CONFIG_NET_NS=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_REDIRECT=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_BPF is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_CBS is not set +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_DEFAULT=y +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_DUALPI2 is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_ETS is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_CODEL=m +# CONFIG_NET_SCH_FQ_PIE is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SHAPER=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_NET_VENDOR_AGERE is not set +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALLWINNER=y +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_SPACEMIT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +CONFIG_NET_VENDOR_VERTEXCOM=y +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_NET_VRF=m +CONFIG_NET_XGRESS=y +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_APP_FLOWER=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP_NET_IPSEC=y +CONFIG_NFSD=m +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_LEGACY_CLIENT_TRACKING=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_V4_2_INTER_SSC=y +# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_DEBUG=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_LOCALIO is not set +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_2=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_NFS_V4_SECURITY_LABEL=y +# CONFIG_NFTL is not set +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COMPAT_ARP=m +# CONFIG_NFT_CONNLIMIT is not set +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +# CONFIG_NFT_EXTHDR_DCCP is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +# CONFIG_NFT_OSF is not set +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +# CONFIG_NFT_REJECT_NETDEV is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_SYNPROXY is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_XFRM is not set +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_AMANDA=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NGBE=m +# CONFIG_NGBEVF is not set +# CONFIG_NIC7018_WDT is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +CONFIG_NLMON=m +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +CONFIG_NODES_SHIFT=7 +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_TRACER=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +# CONFIG_NOVA_CORE is not set +# CONFIG_NOZOMI is not set +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_PAGE_MAPCOUNT is not set +CONFIG_NR_CPUS=256 +# CONFIG_NSM is not set +# CONFIG_NTB is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS_FS=m +CONFIG_NTSYNC=m +# CONFIG_NULL_TTY is not set +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NUMA_EMU is not set +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NVDIMM_DAX=y +CONFIG_NVDIMM_KEYS=y +CONFIG_NVDIMM_PFN=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SOPHGO_EFUSE=m +# CONFIG_NVMEM_SUNXI_SID is not set +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_U_BOOT_ENV is not set +CONFIG_NVME_AUTH=y +CONFIG_NVME_CORE=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_KEYRING=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_AUTH is not set +# CONFIG_NVME_TARGET_DEBUGFS is not set +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_PASSTHRU=y +# CONFIG_NVME_TARGET_PCI_EPF is not set +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_TCP_TLS is not set +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NUMA=y +CONFIG_OF_OVERLAY=y +# CONFIG_OF_PARTITION is not set +CONFIG_OF_PMEM=m +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OID_REGISTRY=y +# CONFIG_OMFS_FS is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +# CONFIG_OPEN_DICE is not set +# CONFIG_ORANGEFS_FS is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OSNOISE_TRACER=y +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVMF_DEBUG_LOG is not set +CONFIG_OVPN=m +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_PAGE_COUNTER=y +# CONFIG_PAGE_EXTENSION is not set +CONFIG_PAGE_IDLE_FLAG=y +CONFIG_PAGE_MAPCOUNT=y +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_VERSION=131 +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARAVIRT is not set +# CONFIG_PARPORT is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ACPI is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +CONFIG_PATA_TIMINGS=y +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PC104 is not set +# CONFIG_PC300TOO is not set +CONFIG_PCC=y +# CONFIG_PCCARD is not set +CONFIG_PCI=y +# CONFIG_PCI200SYN is not set +CONFIG_PCIEAER=y +CONFIG_PCIEAER_CXL=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_CADENCE=m +CONFIG_PCIE_CADENCE_HOST=m +# CONFIG_PCIE_CADENCE_PLAT_EP is not set +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +CONFIG_PCIE_DPC=y +CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_DEBUGFS is not set +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_ECRC=y +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_FU740=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_PLDA_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_RCAR_EP is not set +# CONFIG_PCIE_RCAR_GEN4_EP is not set +# CONFIG_PCIE_RCAR_GEN4_HOST is not set +# CONFIG_PCIE_RCAR_HOST is not set +CONFIG_PCIE_SG2042_HOST=m +CONFIG_PCIE_SOPHGO_DW=y +CONFIG_PCIE_SPACEMIT_K1=y +CONFIG_PCIE_STARFIVE_HOST=y +# CONFIG_PCIE_THERMAL is not set +# CONFIG_PCIE_TPH is not set +CONFIG_PCIE_ULTRARISC=m +CONFIG_PCIE_XILINX=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_ATS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_DOE=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCI_ECAM=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +# CONFIG_PCI_ENDPOINT_MSI_DOORBELL is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_PCI_EPF_NTB is not set +# CONFIG_PCI_EPF_TEST is not set +# CONFIG_PCI_FTPCI100 is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI=y +# CONFIG_PCI_NPEM is not set +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_PASID=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTRL=y +CONFIG_PCI_PWRCTRL_SLOT=y +CONFIG_PCI_QUIRKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +# CONFIG_PCI_SW_SWITCHTEC is not set +# CONFIG_PCNET32 is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCS_RZN1_MIIC=m +CONFIG_PCS_XPCS=m +# CONFIG_PDC_ADMA is not set +# CONFIG_PDS_CORE is not set +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_PFCP is not set +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=5 +# CONFIG_PHANTOM is not set +# CONFIG_PHONET is not set +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_NXP_PTN3222 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_PACKAGE=m +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set +# CONFIG_PHY_RCAR_GEN2 is not set +# CONFIG_PHY_RCAR_GEN3_PCIE is not set +# CONFIG_PHY_RCAR_GEN3_USB2 is not set +# CONFIG_PHY_RCAR_GEN3_USB3 is not set +# CONFIG_PHY_SOPHGO_CV1800_USB2 is not set +CONFIG_PHY_SPACEMIT_K1_PCIE=y +CONFIG_PHY_SPACEMIT_K1_USB2=m +CONFIG_PHY_SPACEMIT_K3_COMBO_PHY=m +CONFIG_PHY_SPACEMIT_K3_COMMON_OPS=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_SUN4I_USB is not set +# CONFIG_PHY_SUN50I_USB3 is not set +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PHY_TH1520_USB=m +# CONFIG_PHY_TUSB1210 is not set +CONFIG_PID_NS=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_AW9523 is not set +# CONFIG_PINCTRL_CY8C95X0 is not set +# CONFIG_PINCTRL_EIC7700 is not set +# CONFIG_PINCTRL_K230 is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RENESAS=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_SOPHGO_COMMON=y +# CONFIG_PINCTRL_SOPHGO_CV1800B is not set +# CONFIG_PINCTRL_SOPHGO_CV1812H is not set +# CONFIG_PINCTRL_SOPHGO_SG2000 is not set +# CONFIG_PINCTRL_SOPHGO_SG2002 is not set +CONFIG_PINCTRL_SOPHGO_SG2042=y +CONFIG_PINCTRL_SOPHGO_SG2042_OPS=y +CONFIG_PINCTRL_SOPHGO_SG2044=y +CONFIG_PINCTRL_SPACEMIT_K1=y +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN55I_A523 is not set +# CONFIG_PINCTRL_SUN55I_A523_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_TH1520=y +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set +CONFIG_PLDMFW=y +# CONFIG_PLFXLC is not set +# CONFIG_PLX_DMA is not set +CONFIG_PM=y +CONFIG_PMBUS=m +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +CONFIG_PMIC_OPREGION=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_FLEXFILE_LAYOUT=y +CONFIG_PNP=y +CONFIG_PNPACPI=y +CONFIG_PNP_DEBUG_MESSAGES=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set +CONFIG_PORTABLE=y +# CONFIG_POSIX_AUX_CLOCKS is not set +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POSIX_TIMERS=y +# CONFIG_POWERCAP is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SPACEMIT_P1=m +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_TH1520_AON=m +CONFIG_POWER_SEQUENCING=m +# CONFIG_POWER_SEQUENCING_QCOM_WCN is not set +CONFIG_POWER_SEQUENCING_TH1520_GPU=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPP=m +CONFIG_PPPOE=m +CONFIG_PPPOE_HASH_BITS=4 +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS=y +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPS_GENERATOR is not set +CONFIG_PPTP=m +# CONFIG_PREEMPT is not set +CONFIG_PREEMPTION=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPT_LAZY is not set +CONFIG_PREEMPT_NONE=y +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +# CONFIG_PREEMPT_RT is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_PRIME_NUMBERS is not set +CONFIG_PRINTK=y +CONFIG_PRINTK_CALLER=y +# CONFIG_PRINTK_INDEX is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +# CONFIG_PROVE_LOCKING is not set +CONFIG_PSAMPLE=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTP_1588_CLOCK=y +# CONFIG_PTP_1588_CLOCK_FC3W is not set +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_INES is not set +# CONFIG_PTP_1588_CLOCK_MOCK is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +# CONFIG_PTP_NETC_V4_TIMER is not set +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +# CONFIG_PWM_ARGON_FAN_HAT is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set +# CONFIG_PWM_MC33XS2410 is not set +# CONFIG_PWM_MICROCHIP_CORE is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_PROVIDE_GPIO is not set +# CONFIG_PWM_PXA is not set +# CONFIG_PWM_RENESAS_RCAR is not set +# CONFIG_PWM_RENESAS_TPU is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_SOPHGO_SG2042=m +# CONFIG_PWM_SUN4I is not set +CONFIG_PWM_TH1520=m +# CONFIG_PWM_XILINX is not set +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA807X_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +CONFIG_QCOM_EMAC=m +CONFIG_QCOM_HIDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_NET_PHYLIB=m +# CONFIG_QCOM_PMIC_GLINK is not set +# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED_FCOE=y +CONFIG_QED_ISCSI=y +CONFIG_QED_LL2=y +CONFIG_QED_OOO=y +CONFIG_QED_RDMA=y +CONFIG_QED_SRIOV=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QLA3XXX=m +# CONFIG_QLCNIC is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QRTR is not set +CONFIG_QSEMI_PHY=m +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=y +CONFIG_R8169=y +CONFIG_RADIO_ADAPTERS=m +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RAPIDIO is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RCAR_DMAC is not set +# CONFIG_RCAR_GEN3_THERMAL is not set +# CONFIG_RCAR_THERMAL is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RC_CORE is not set +CONFIG_RDMA_RXE=m +# CONFIG_RDMA_SIW is not set +# CONFIG_RDS is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=y +# CONFIG_REALTEK_PHY_HWMON is not set +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=m +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ADP5055 is not set +# CONFIG_REGULATOR_AW37503 is not set +# CONFIG_REGULATOR_DA9063 is not set +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX20411 is not set +# CONFIG_REGULATOR_MAX77503 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MAX77838 is not set +# CONFIG_REGULATOR_MAX77857 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF0900 is not set +# CONFIG_REGULATOR_PF530X is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PF9453 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RAA215300 is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT4803 is not set +# CONFIG_REGULATOR_RT5133 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5739 is not set +# CONFIG_REGULATOR_RT5759 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTQ2208 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_SLG51000 is not set +CONFIG_REGULATOR_SPACEMIT_P1=m +CONFIG_REGULATOR_SUN20I=y +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC is not set +# CONFIG_REMOTE_TARGET is not set +# CONFIG_RENESAS_OSTM is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_RENESAS_RZAWDT is not set +# CONFIG_RENESAS_RZN1WDT is not set +# CONFIG_RENESAS_RZV2HWDT is not set +# CONFIG_RENESAS_USB_DMAC is not set +# CONFIG_RENESAS_WDT is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_RESET_K230=y +CONFIG_RESET_POLARFIRE_SOC=y +# CONFIG_RESET_RZV2H_USB2PHY is not set +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SPACEMIT_COMMON=y +CONFIG_RESET_SPACEMIT_K1=y +CONFIG_RESET_SPACEMIT_K3=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_SUNXI=y +CONFIG_RESET_TH1520=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set +CONFIG_RETHOOK=y +# CONFIG_RFD_FTL is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFS_ACCEL=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_APLIC=y +CONFIG_RISCV_APLIC_MSI=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_RISCV_COMBO_SPINLOCKS=y +CONFIG_RISCV_DMA_NONCOHERENT=y +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set +CONFIG_RISCV_IMSIC=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_IOMMU=y +CONFIG_RISCV_IOMMU_PCI=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SUPM=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_VENDOR_EXT=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y +CONFIG_RISCV_ISA_VENDOR_EXT_MIPS=y +CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y +CONFIG_RISCV_ISA_VENDOR_EXT_THEAD=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_V_PREEMPTIVE=y +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 +CONFIG_RISCV_ISA_XTHEADVECTOR=y +CONFIG_RISCV_ISA_ZABHA=y +CONFIG_RISCV_ISA_ZACAS=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y +CONFIG_RISCV_ISA_ZBKB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOP=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_MISALIGNED=y +CONFIG_RISCV_NONSTANDARD_CACHE_OPS=y +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS=y +CONFIG_RISCV_RPMI_SYSMSI=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_CPUIDLE=y +CONFIG_RISCV_SBI_MPXY_MBOX=y +# CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SCALAR_MISALIGNED=y +# CONFIG_RISCV_TICKET_SPINLOCKS is not set +CONFIG_RISCV_TIMER=y +CONFIG_RISCV_VECTOR_MISALIGNED=y +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +# CONFIG_RMI4_F1A is not set +# CONFIG_RMI4_F21 is not set +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +# CONFIG_RMI4_F55 is not set +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +# CONFIG_RMNET is not set +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_ROCKER=m +# CONFIG_ROMFS_FS is not set +CONFIG_ROOT_NFS=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set +# CONFIG_RPMB is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_NS=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_TTY is not set +CONFIG_RPMSG_VIRTIO=y +CONFIG_RPS=y +CONFIG_RSEQ=y +# CONFIG_RT2400PCI is not set +# CONFIG_RT2500PCI is not set +# CONFIG_RT2500USB is not set +# CONFIG_RT2800PCI is not set +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +# CONFIG_RT2800USB_RT3573 is not set +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +# CONFIG_RT2800USB_RT55XX is not set +# CONFIG_RT2800USB_UNKNOWN is not set +CONFIG_RT2800_LIB=m +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_USB=m +# CONFIG_RT61PCI is not set +# CONFIG_RT73USB is not set +# CONFIG_RTASE is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_DRV_ABB5ZES3=m +# CONFIG_RTC_DRV_ABEOZ9 is not set +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_CADENCE is not set +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685=y +CONFIG_RTC_DRV_DS1685_FAMILY=m +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +# CONFIG_RTC_DRV_FTRTC010 is not set +CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_ISL12026 is not set +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX31335 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +# CONFIG_RTC_DRV_MAX6916 is not set +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +# CONFIG_RTC_DRV_NCT3018Y is not set +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_POLARFIRE_SOC is not set +# CONFIG_RTC_DRV_R7301 is not set +CONFIG_RTC_DRV_R9701=m +# CONFIG_RTC_DRV_RENESAS_RTCA3 is not set +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3029C2=m +# CONFIG_RTC_DRV_RV3029_HWMON is not set +# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_RX4581=m +# CONFIG_RTC_DRV_RX6110 is not set +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +# CONFIG_RTC_DRV_RX8111 is not set +CONFIG_RTC_DRV_RX8581=m +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SD2405AL is not set +# CONFIG_RTC_DRV_SD3078 is not set +# CONFIG_RTC_DRV_SH is not set +CONFIG_RTC_DRV_SPACEMIT_P1=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_NVMEM=y +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192D_COMMON=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +# CONFIG_RTL8XXXU_UNTESTED is not set +CONFIG_RTLBTCOEXIST=m +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTL_CARDS=m +CONFIG_RTW88=m +CONFIG_RTW88_8703B=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8723X=m +CONFIG_RTW88_8812A=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_8814A=m +CONFIG_RTW88_8814AE=m +CONFIG_RTW88_8814AU=m +CONFIG_RTW88_8821A=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_88XXA=m +CONFIG_RTW88_CORE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW88_LEDS=y +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW89=m +CONFIG_RTW89_8851B=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BT=m +CONFIG_RTW89_8852BTE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852B_COMMON=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922A=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_CORE=m +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89_PCI=m +CONFIG_RTW89_USB=m +CONFIG_RT_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED_DEFAULT_DISABLED is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RUST=y +CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_FILE_AS_C_STR=y +CONFIG_RUSTC_HAS_FILE_WITH_NUL=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y +CONFIG_RUSTC_LLVM_VERSION=210108 +CONFIG_RUSTC_SUPPORTS_RISCV=y +CONFIG_RUSTC_VERSION=109500 +CONFIG_RUSTC_VERSION_TEXT="rustc 1.95.0 (59807616e 2026-04-14) (built from a source tarball)" +CONFIG_RUST_BINDGEN_HAS_ZICSR_ZIFENCEI=y +# CONFIG_RUST_BITMAP_HARDENED is not set +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +CONFIG_RUST_IS_AVAILABLE=y +CONFIG_RUST_OVERFLOW_CHECKS=y +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set +CONFIG_RUST_PWM_ABSTRACTIONS=y +# CONFIG_RV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_RZG2L_THERMAL is not set +# CONFIG_RZG3E_THERMAL is not set +CONFIG_SAMPLES=y +# CONFIG_SAMPLES_RUST is not set +# CONFIG_SAMPLE_ANDROID_BINDERFS is not set +# CONFIG_SAMPLE_AUXDISPLAY is not set +# CONFIG_SAMPLE_CGROUP is not set +# CONFIG_SAMPLE_CHECK_EXEC is not set +# CONFIG_SAMPLE_CONFIGFS is not set +# CONFIG_SAMPLE_CONNECTOR is not set +# CONFIG_SAMPLE_DAMON_MTIER is not set +# CONFIG_SAMPLE_DAMON_PRCL is not set +# CONFIG_SAMPLE_DAMON_WSSE is not set +# CONFIG_SAMPLE_FANOTIFY_ERROR is not set +# CONFIG_SAMPLE_FTRACE_DIRECT is not set +# CONFIG_SAMPLE_FTRACE_DIRECT_MULTI is not set +# CONFIG_SAMPLE_FTRACE_OPS is not set +# CONFIG_SAMPLE_HIDRAW is not set +# CONFIG_SAMPLE_HUNG_TASK is not set +# CONFIG_SAMPLE_KDB is not set +# CONFIG_SAMPLE_KFIFO is not set +# CONFIG_SAMPLE_KOBJECT is not set +# CONFIG_SAMPLE_KPROBES is not set +# CONFIG_SAMPLE_LANDLOCK is not set +# CONFIG_SAMPLE_PIDFD is not set +# CONFIG_SAMPLE_RPMSG_CLIENT is not set +# CONFIG_SAMPLE_SECCOMP is not set +# CONFIG_SAMPLE_TIMER is not set +# CONFIG_SAMPLE_TPS6594_PFSM is not set +# CONFIG_SAMPLE_TRACE_ARRAY is not set +# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set +# CONFIG_SAMPLE_TRACE_EVENTS is not set +# CONFIG_SAMPLE_TRACE_PRINTK is not set +# CONFIG_SAMPLE_TSM_MR is not set +# CONFIG_SAMPLE_UHID is not set +# CONFIG_SAMPLE_VFIO_MDEV_MBOCHS is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set +# CONFIG_SAMPLE_VFIO_MDEV_MTTY is not set +# CONFIG_SAMPLE_VFS is not set +# CONFIG_SAMPLE_WATCHDOG is not set +# CONFIG_SAMPLE_WATCH_QUEUE is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_DWC is not set +CONFIG_SATA_HOST=y +# CONFIG_SATA_INIC162X is not set +CONFIG_SATA_MOBILE_LPM_POLICY=0 +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_ZPODD is not set +CONFIG_SBITMAP=y +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CLASS_EXT is not set +CONFIG_SCHED_HRTICK=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MM_CID=y +# CONFIG_SCHED_PROXY_EXEC is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_SCHED_TRACER=y +CONFIG_SCREEN_INFO=y +CONFIG_SCSI=y +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +CONFIG_SCSI_AACRAID=m +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BNX2_ISCSI=m +# CONFIG_SCSI_BUSLOGIC is not set +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_CXGB3_ISCSI is not set +CONFIG_SCSI_CXGB4_ISCSI=m +# CONFIG_SCSI_DC395x is not set +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_ALUA=y +CONFIG_SCSI_DH_EMC=y +CONFIG_SCSI_DH_HP_SW=y +CONFIG_SCSI_DH_RDAC=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EFCT is not set +CONFIG_SCSI_ENCLOSURE=m +# CONFIG_SCSI_ESAS2R is not set +CONFIG_SCSI_FC_ATTRS=m +# CONFIG_SCSI_FDOMAIN_PCI is not set +CONFIG_SCSI_HPSA=m +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR_TRACE=y +# CONFIG_SCSI_IPS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPI3MR is not set +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SCSI_NETLINK=y +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +# CONFIG_SCSI_SNIC is not set +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +CONFIG_SCSI_UFSHCD=m +# CONFIG_SCSI_UFSHCD_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_BSG=y +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +CONFIG_SCSI_UFS_CRYPTO=y +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_HWMON=y +# CONFIG_SCSI_UFS_RENESAS is not set +CONFIG_SCSI_UFS_SPACEMIT=m +CONFIG_SCSI_VIRTIO=y +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y +CONFIG_SDIO_UART=m +# CONFIG_SDR_MAX2175 is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP_FILTER=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY_INFINIBAND=y +# CONFIG_SECURITY_IPE is not set +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +# CONFIG_SECURITY_SELINUX_DEBUG is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ACBEL_FSG032 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM1266 is not set +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +# CONFIG_SENSORS_ADP1050 is not set +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_AHT10 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set +CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_BEL_PFE is not set +CONFIG_SENSORS_BH1770=m +# CONFIG_SENSORS_BPA_RS600 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_CRPS is not set +# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set +CONFIG_SENSORS_DME1737=m +# CONFIG_SENSORS_DPS920AB is not set +# CONFIG_SENSORS_DRIVETEMP is not set +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +# CONFIG_SENSORS_FSP_3Y is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_HTU31 is not set +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_INA209=m +# CONFIG_SENSORS_INA233 is not set +# CONFIG_SENSORS_INA238 is not set +CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL28022 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM25066=m +# CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +# CONFIG_SENSORS_LT3074 is not set +# CONFIG_SENSORS_LT7182S is not set +CONFIG_SENSORS_LTC2945=m +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +# CONFIG_SENSORS_LTC4286 is not set +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX16601 is not set +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +# CONFIG_SENSORS_MAX6620 is not set +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX8688=m +# CONFIG_SENSORS_MC34VR500 is not set +CONFIG_SENSORS_MCP3021=m +# CONFIG_SENSORS_MP2856 is not set +# CONFIG_SENSORS_MP2869 is not set +# CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set +# CONFIG_SENSORS_MP29502 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set +# CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set +# CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set +# CONFIG_SENSORS_MPQ7932 is not set +# CONFIG_SENSORS_MPQ8785 is not set +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set +# CONFIG_SENSORS_NCT7363 is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +# CONFIG_SENSORS_PIM4328 is not set +# CONFIG_SENSORS_PLI1209BC is not set +# CONFIG_SENSORS_PM6764TR is not set +CONFIG_SENSORS_PMBUS=m +# CONFIG_SENSORS_POWERZ is not set +CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PT5161L is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_PXE1610 is not set +# CONFIG_SENSORS_Q54SJ108A2 is not set +# CONFIG_SENSORS_SBTSI is not set +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SCH56XX_COMMON=m +# CONFIG_SENSORS_SFCTEMP is not set +CONFIG_SENSORS_SG2042_MCU=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +# CONFIG_SENSORS_SPD5118 is not set +# CONFIG_SENSORS_STPDDC60 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_TC654 is not set +CONFIG_SENSORS_TC74=m +# CONFIG_SENSORS_TDA38640 is not set +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +# CONFIG_SENSORS_TMP108 is not set +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +# CONFIG_SENSORS_TMP464 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_TPS25990 is not set +CONFIG_SENSORS_TPS40422=m +# CONFIG_SENSORS_TPS53679 is not set +# CONFIG_SENSORS_TPS546D24 is not set +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +# CONFIG_SENSORS_W83773G is not set +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +# CONFIG_SENSORS_XDP710 is not set +# CONFIG_SENSORS_XDPE122 is not set +# CONFIG_SENSORS_XDPE152 is not set +# CONFIG_SENSORS_XGENE is not set +CONFIG_SENSORS_ZL6100=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +# CONFIG_SERIAL_8250_EM is not set +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PCI1XXXX is not set +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_ATMEL is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SPRD is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIO=y +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_GPIO_PS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_SUN4I_PS2 is not set +CONFIG_SFC=m +# CONFIG_SFC_FALCON is not set +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_SFC_SRIOV=y +CONFIG_SFP=m +# CONFIG_SF_PDMA is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SIGNALFD=y +CONFIG_SIGNATURE=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIOX is not set +CONFIG_SKB_DECRYPTED=y +CONFIG_SKB_EXTENSIONS=y +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_OBJ_EXT=y +CONFIG_SLHC=m +# CONFIG_SLICOSS is not set +# CONFIG_SLIMBUS is not set +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_SLIP_SMART=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_SMBFS=m +# CONFIG_SMB_SERVER is not set +CONFIG_SMP=y +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_SM_FTL is not set +CONFIG_SND=m +# CONFIG_SND_AD1889 is not set +CONFIG_SND_ALOOP=m +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CTL_FAST_LOOKUP=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +CONFIG_SND_HDA=m +# CONFIG_SND_HDA_ACPI is not set +# CONFIG_SND_HDA_CODEC_ANALOG is not set +# CONFIG_SND_HDA_CODEC_CA0110 is not set +# CONFIG_SND_HDA_CODEC_CA0132 is not set +# CONFIG_SND_HDA_CODEC_CIRRUS is not set +# CONFIG_SND_HDA_CODEC_CM9825 is not set +# CONFIG_SND_HDA_CODEC_CMEDIA is not set +# CONFIG_SND_HDA_CODEC_CONEXANT is not set +# CONFIG_SND_HDA_CODEC_HDMI is not set +# CONFIG_SND_HDA_CODEC_REALTEK is not set +# CONFIG_SND_HDA_CODEC_SENARYTECH is not set +# CONFIG_SND_HDA_CODEC_SI3054 is not set +# CONFIG_SND_HDA_CODEC_SIGMATEL is not set +# CONFIG_SND_HDA_CODEC_VIA is not set +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_CORE=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# CONFIG_SND_HDA_GENERIC is not set +# CONFIG_SND_HDA_HWDEP is not set +CONFIG_SND_HDA_I915=y +# CONFIG_SND_HDA_INPUT_BEEP is not set +CONFIG_SND_HDA_INTEL=m +# CONFIG_SND_HDA_PATCH_LOADER is not set +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDA_RECONFIG is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_SPI is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_HWDEP=m +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OSSEMUL is not set +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +CONFIG_SND_PCM=m +# CONFIG_SND_PCMTEST is not set +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCXHR is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_RAWMIDI=m +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +CONFIG_SND_SOC=m +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1373 is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_ADI_AXI_I2S is not set +# CONFIG_SND_SOC_ADI_AXI_SPDIF is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_SOC_AW8738 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88081 is not set +# CONFIG_SND_SOC_AW88166 is not set +# CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88399 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CHV3_CODEC is not set +# CONFIG_SND_SOC_CHV3_I2S is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L45_I2C is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS35L56_I2C is not set +# CONFIG_SND_SOC_CS35L56_SPI is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L83 is not set +# CONFIG_SND_SOC_CS42L84 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS48L32 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8323 is not set +# CONFIG_SND_SOC_ES8326 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_ES8375 is not set +# CONFIG_SND_SOC_ES8389 is not set +# CONFIG_SND_SOC_FS210X is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_IDT821034 is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_JH7110_PWMDAC is not set +# CONFIG_SND_SOC_JH7110_TDM is not set +CONFIG_SND_SOC_K1_I2S=m +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98388 is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX98396 is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX98520 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MIKROE_PROTO is not set +# CONFIG_SND_SOC_MSIOF is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8325 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_NTP8835 is not set +# CONFIG_SND_SOC_NTP8918 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1754 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_RCAR is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RT9123 is not set +# CONFIG_SND_SOC_RT9123P is not set +# CONFIG_SND_SOC_RTQ9124 is not set +# CONFIG_SND_SOC_RTQ9128 is not set +CONFIG_SND_SOC_SDCA_OPTIONAL=m +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SH4_FSI is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SMA1303 is not set +# CONFIG_SND_SOC_SMA1307 is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM3515 is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set +# CONFIG_SND_SOC_TAS2781_I2C is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS5805M is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_UDA1342 is not set +# CONFIG_SND_SOC_USB is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731_I2C is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8940 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SOC_ZL38060 is not set +CONFIG_SND_SPI=y +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SND_SUPPORT_OLD_API=y +# CONFIG_SND_TEST_COMPONENT is not set +CONFIG_SND_TIMER=m +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_UTIMER is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTIO is not set +# CONFIG_SND_VIRTUOSO is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_SOC_BUS=y +CONFIG_SOC_RENESAS=y +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_TI is not set +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM is not set +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONY_FF=y +# CONFIG_SOPHGO_CV1800B_DMAMUX is not set +# CONFIG_SOPHGO_CV1800_RTCSYS is not set +CONFIG_SOPHGO_SG2042_MSI=y +CONFIG_SOPHGO_SG2044_TOPSYS=y +CONFIG_SOUND=m +# CONFIG_SOUNDWIRE is not set +CONFIG_SPACEMIT_CCU=y +CONFIG_SPACEMIT_K1_CCU=y +CONFIG_SPACEMIT_K1_EMAC=m +CONFIG_SPACEMIT_K1_TSENSOR=m +CONFIG_SPACEMIT_K3_CCU=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_ATMEL is not set +# CONFIG_SPI_AX88796C is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_CADENCE=m +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_DESIGNWARE=y +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_FSL_QUADSPI=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_POLARFIRE_SOC is not set +# CONFIG_SPI_RSPI is not set +# CONFIG_SPI_RZV2H_RSPI is not set +# CONFIG_SPI_RZV2M_CSI is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SG2044_NOR=m +# CONFIG_SPI_SH_HSPI is not set +# CONFIG_SPI_SH_MSIOF is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI_SN_F_OSPI is not set +CONFIG_SPI_SPACEMIT_K1=m +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_VIRTIO is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +# CONFIG_SPMI is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_ZSTD is not set +CONFIG_SRAM=y +# CONFIG_SSB is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSFDC is not set +# CONFIG_SSIF_IPMI_BMC is not set +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_STACK_TRACER=y +# CONFIG_STAGING is not set +CONFIG_STANDALONE=y +CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set +# CONFIG_STARFIVE_STARLINK_PMU is not set +CONFIG_STARFIVE_WATCHDOG=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +# CONFIG_STM is not set +CONFIG_STMMAC_ETH=m +CONFIG_STMMAC_PCI=m +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STP=m +CONFIG_STREAM_PARSER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN20I_PPU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +# CONFIG_SUN50I_DE2_BUS is not set +# CONFIG_SUN50I_H6_PRCM_PPU is not set +# CONFIG_SUN50I_IOMMU is not set +CONFIG_SUN55I_PCK600=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUNRPC=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_DEBUG=y +# CONFIG_SUNRPC_DEBUG_TRACE is not set +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +# CONFIG_SUNXI_WATCHDOG is not set +# CONFIG_SUN_PARTITION is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SWPHY=y +# CONFIG_SW_SYNC is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYN_COOKIES=y +# CONFIG_SYSCON_REBOOT_MODE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +CONFIG_SYSFB_SIMPLEFB=y +CONFIG_SYSFS=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set +CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_REVOCATION_KEYS="" +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_TAP=m +CONFIG_TARGET_CORE=m +CONFIG_TASKSTATS=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_CORE=y +# CONFIG_TCG_TIS_I2C is not set +CONFIG_TCG_TIS_I2C_ATMEL=m +# CONFIG_TCG_TIS_I2C_CR50 is not set +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI=y +# CONFIG_TCG_TIS_SPI_CR50 is not set +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_TCG_TPM=y +# CONFIG_TCG_TPM2_HMAC is not set +# CONFIG_TCG_VTPM_PROXY is not set +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +# CONFIG_TCM_QLA2XXX is not set +CONFIG_TCM_USER2=m +# CONFIG_TCP_AO is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +# CONFIG_TCP_CONG_CDG is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +CONFIG_TCP_SIGPOOL=y +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_TEST_LOCKUP is not set +# CONFIG_TEST_POWER is not set +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TH1520_AON_PROTOCOL=y +CONFIG_TH1520_PM_DOMAINS=m +CONFIG_THEAD_TH1520_MBOX=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_CORE_TESTING is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +# CONFIG_THERMAL_NETLINK is not set +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SIZE_ORDER=2 +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_THUNDER_NIC_VF=m +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIMERFD=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TIME_NS=y +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_SHARP_MEMORY is not set +CONFIG_TIPC=m +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_TI_FPC202 is not set +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_XATTR=y +CONFIG_TOOLCHAIN_HAS_V=y +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO=y +CONFIG_TOOLCHAIN_HAS_ZABHA=y +CONFIG_TOOLCHAIN_HAS_ZACAS=y +CONFIG_TOOLCHAIN_HAS_ZBA=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_TOOLCHAIN_HAS_ZBC=y +CONFIG_TOOLCHAIN_HAS_ZBKB=y +CONFIG_TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y +CONFIG_TRACEPOINTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_GPU_MEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_TRUSTED_KEYS=y +CONFIG_TRUSTED_KEYS_TPM=y +# CONFIG_TSNEP is not set +CONFIG_TTY=y +CONFIG_TTY_PRINTK=m +CONFIG_TTY_PRINTK_LEVEL=6 +CONFIG_TUN=m +CONFIG_TUNE_GENERIC=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_TXGBE=m +# CONFIG_TXGBEVF is not set +CONFIG_TYPEC=m +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_DP_ALTMODE=m +# CONFIG_TYPEC_FUSB302 is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_IT5205 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_PS883X is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set +# CONFIG_TYPEC_MUX_TUSB1046 is not set +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TBT_ALTMODE is not set +CONFIG_TYPEC_TCPCI=m +# CONFIG_TYPEC_TCPCI_MAXIM is not set +CONFIG_TYPEC_TCPM=m +# CONFIG_TYPEC_TPS6598X is not set +CONFIG_TYPEC_UCSI=m +# CONFIG_TYPEC_WUSB3801 is not set +CONFIG_UACCE=m +# CONFIG_UAPI_HEADER_TEST is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_UBSAN is not set +# CONFIG_UCLAMP_TASK is not set +CONFIG_UCS2_STRING=y +# CONFIG_UCSI_ACPI is not set +# CONFIG_UCSI_CCG is not set +# CONFIG_UCSI_STM32G0 is not set +CONFIG_UDF_FS=m +# CONFIG_UDMABUF is not set +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UFS_FS is not set +CONFIG_UHID=m +CONFIG_UIO=m +CONFIG_UIO_AEC=m CONFIG_UIO_CIF=m +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +CONFIG_UIO_PCI_GENERIC=m CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_AEC=m CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNION_FIND=y +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX_DIAG=m +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y +CONFIG_USB=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +CONFIG_USB4_NET=m +# CONFIG_USBIP_CORE is not set +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +# CONFIG_USB_AIRSPY is not set +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_BELKIN=y +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_CATC=m +# CONFIG_USB_CDNS_SUPPORT is not set +CONFIG_USB_CHAOSKEY=m +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_COMMON=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DWC2 is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_GENERIC_PLAT=m +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_PCI=m +# CONFIG_USB_DWC3_ULPI is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_HSIC_USB3503=m +# CONFIG_USB_HSIC_USB4604 is not set +CONFIG_USB_HSO=m +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_IPHETH=m +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1760 is not set +CONFIG_USB_KAWETH=m +CONFIG_USB_KC2190=y +# CONFIG_USB_KEENE is not set +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_LJCA is not set +# CONFIG_USB_MA901 is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y +# CONFIG_USB_MR800 is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_ONBOARD_DEV=m +# CONFIG_USB_ONBOARD_DEV_USB5744 is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set +CONFIG_USB_PEGASUS=m +CONFIG_USB_PRINTER=m +# CONFIG_USB_PWC is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +# CONFIG_USB_S2255 is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +# CONFIG_USB_SERIAL_UPD78F0730 is not set +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_WWAN=m +# CONFIG_USB_SERIAL_XR is not set +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEST is not set +CONFIG_USB_TMC=m +# CONFIG_USB_TRANCEVIBRATOR is not set +CONFIG_USB_UAS=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_USBNET=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_XHCI_RCAR=y +# CONFIG_USB_XHCI_SIDEBAND is not set +# CONFIG_USB_YUREX is not set +CONFIG_USERFAULTFD=y +# CONFIG_USERIO is not set +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USER_NS=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_UTS_NS=y +CONFIG_UVC_COMMON=m +CONFIG_V4L2_ASYNC=m +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L2_FWNODE=m +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +CONFIG_VALIDATE_FS_PARSER=y +# CONFIG_VCPU_STALL_DETECTOR is not set +# CONFIG_VDPA is not set +CONFIG_VDSO_GETRANDOM=y +CONFIG_VETH=m +CONFIG_VFAT_FS=y CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +CONFIG_VFIO_GROUP=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI=m -CONFIG_VIRT_DRIVERS=y -CONFIG_VIRTIO_PCI=y +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=64 +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST_VSOCK=m +CONFIG_VIDEO=y +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_ALVIUM_CSI2 is not set +# CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +# CONFIG_VIDEO_CADENCE_CSI2TX is not set +CONFIG_VIDEO_CAMERA_LENS=y +CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_DEV=m +# CONFIG_VIDEO_DS90UB913 is not set +# CONFIG_VIDEO_DS90UB953 is not set +# CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9719 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_ET8EK8 is not set +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC0310 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_HI846 is not set +# CONFIG_VIDEO_HI847 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX296 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_IMX415 is not set +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# CONFIG_VIDEO_LT6911UXE is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_OG01A1B is not set +# CONFIG_VIDEO_OG0VE1B is not set +# CONFIG_VIDEO_OV01A10 is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV02C10 is not set +# CONFIG_VIDEO_OV02E10 is not set +# CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV08X40 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_OV13B10 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV2735 is not set +# CONFIG_VIDEO_OV2740 is not set +# CONFIG_VIDEO_OV4689 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV6211 is not set +# CONFIG_VIDEO_OV64A40 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8858 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_RP1_CFE is not set +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_STK1160 is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THP7312 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VD55G1 is not set +# CONFIG_VIDEO_VD56G3 is not set +# CONFIG_VIDEO_VGXY61 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VIRTIO_FS=y CONFIG_VIRTIO_INPUT=y +# CONFIG_VIRTIO_MEM is not set +CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +# CONFIG_VIRTIO_PMEM is not set CONFIG_VIRTIO_RTC=m -CONFIG_VHOST_NET=m -CONFIG_VHOST_SCSI=m -CONFIG_VHOST_VSOCK=m -CONFIG_CLK_SOPHGO_SG2042_PLL=y -CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y -CONFIG_CLK_SOPHGO_SG2042_RPGATE=y -CONFIG_CLK_SOPHGO_SG2044=y -CONFIG_CLK_SOPHGO_SG2044_PLL=y -CONFIG_SPACEMIT_K1_CCU=y -CONFIG_SPACEMIT_K3_CCU=y -CONFIG_HWSPINLOCK=y -CONFIG_THEAD_TH1520_MBOX=y -CONFIG_IOMMU_DEFAULT_DMA_LAZY=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_CTRL=y -CONFIG_RPMSG_VIRTIO=y -CONFIG_SOPHGO_SG2044_TOPSYS=y -CONFIG_TH1520_PM_DOMAINS=m -CONFIG_EXTCON=y -CONFIG_EXTCON_GPIO=m -CONFIG_PWM=y -CONFIG_PWM_SIFIVE=m -CONFIG_PWM_SOPHGO_SG2042=m -CONFIG_PWM_TH1520=m -CONFIG_ACLINT_SSWI=y -CONFIG_SOPHGO_SG2042_MSI=y -CONFIG_RESET_TH1520=m -CONFIG_PHY_SPACEMIT_K1_USB2=m -CONFIG_PHY_SPACEMIT_K3_COMBO_PHY=m -CONFIG_USB4=m -CONFIG_DAX=y -CONFIG_DEV_DAX=m -CONFIG_NVMEM_SOPHGO_EFUSE=m -CONFIG_INTERCONNECT=y -CONFIG_VALIDATE_FS_PARSER=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y +CONFIG_VIRTIO_RTC_CLASS=y +CONFIG_VIRTIO_RTC_PTP=y +# CONFIG_VIRTIO_VFIO_PCI is not set +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_VIRTUALIZATION=y +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_VIRT_DRIVERS=y +# CONFIG_VIRT_WIFI is not set +CONFIG_VIRT_XFER_TO_GUEST_WORK=y +CONFIG_VITESSE_PHY=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_PFN=y +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_VMXNET3 is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKMON=m +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VXFS_FS is not set +CONFIG_VXLAN=m +# CONFIG_W1 is not set +CONFIG_WAN=y +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_WANXL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +# CONFIG_WATCH_QUEUE is not set +# CONFIG_WCN36XX is not set +# CONFIG_WDAT_WDT is not set +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +# CONFIG_WFX is not set +# CONFIG_WIL6210 is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIRELESS=y +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WPCM450_SOC is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WQ_WATCHDOG=y +# CONFIG_WWAN is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_X25 is not set +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_XARRAY_MULTI=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XFRM=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_IPCOMP=m +# CONFIG_XFRM_IPTFS is not set +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_USER=m +CONFIG_XFS_BTREE_IN_MEM=y +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_DRAIN_INTENTS=y CONFIG_XFS_FS=y -CONFIG_XFS_QUOTA=y +CONFIG_XFS_LIVE_HOOKS=y +CONFIG_XFS_MEMORY_BUFS=y +CONFIG_XFS_ONLINE_REPAIR=y +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_XFS_ONLINE_SCRUB_STATS=y CONFIG_XFS_POSIX_ACL=y -CONFIG_OCFS2_FS=m -# CONFIG_OCFS2_FS_STATS is not set -# CONFIG_OCFS2_DEBUG_MASKLOG is not set -CONFIG_BTRFS_FS=y -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_BTRFS_EXPERIMENTAL=y -CONFIG_F2FS_FS=m -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_FS_COMPRESSION=y -CONFIG_F2FS_UNFAIR_RWSEM=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_QFMT_V2=y -CONFIG_AUTOFS_FS=y -CONFIG_FUSE_FS=y -CONFIG_CUSE=m -CONFIG_VIRTIO_FS=y -CONFIG_OVERLAY_FS=m -CONFIG_NETFS_STATS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +# CONFIG_XFS_SUPPORT_ASCII_CI is not set +# CONFIG_XFS_SUPPORT_V4 is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_XILINX_INTC is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_VCU is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_XDMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_RISCV=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_XZ_DEC_X86=y +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZERO_CALL_USED_REGS is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -CONFIG_EXFAT_FS=y -CONFIG_NTFS3_LZX_XPRESS=y -CONFIG_NTFS3_FS_POSIX_ACL=y -CONFIG_NTFS_FS=m -CONFIG_PROC_KCORE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_EFIVAR_FS=y -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_PSTORE=y -CONFIG_PSTORE_RAM=m -CONFIG_EROFS_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V2=m -CONFIG_NFS_V3=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set -# CONFIG_NFS_V4_2_READ_PLUS is not set -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_BLOCKLAYOUT=y -CONFIG_NFSD_SCSILAYOUT=y -CONFIG_NFSD_FLEXFILELAYOUT=y -CONFIG_NFSD_V4_2_INTER_SSC=y -CONFIG_NFSD_V4_SECURITY_LABEL=y -CONFIG_RPCSEC_GSS_KRB5=m -CONFIG_SUNRPC_DEBUG=y -CONFIG_CEPH_FS=m -CONFIG_CEPH_FS_POSIX_ACL=y -CONFIG_CIFS=m -# CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_9P_FS=y -CONFIG_9P_FS_POSIX_ACL=y -CONFIG_9P_FS_SECURITY=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_NLS_UTF8=m -CONFIG_PERSISTENT_KEYRINGS=y -CONFIG_TRUSTED_KEYS=y -CONFIG_SECURITY=y -CONFIG_SECURITY_INFINIBAND=y -CONFIG_SECURITY_NETWORK_XFRM=y -CONFIG_LSM_MMAP_MIN_ADDR=32768 -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_APPARMOR=y -CONFIG_SECURITY_YAMA=y -CONFIG_SECURITY_LOCKDOWN_LSM=y -CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y -CONFIG_SECURITY_LANDLOCK=y -CONFIG_INTEGRITY_SIGNATURE=y -CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y -CONFIG_INTEGRITY_PLATFORM_KEYRING=y -CONFIG_IMA=y -CONFIG_IMA_DEFAULT_HASH_SHA256=y -CONFIG_IMA_READ_POLICY=y -CONFIG_IMA_APPRAISE=y -CONFIG_IMA_LOAD_X509=y -CONFIG_EVM=y -CONFIG_EVM_LOAD_X509=y -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" -CONFIG_INIT_STACK_NONE=y -CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y -CONFIG_FORTIFY_SOURCE=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_LIST_HARDENED=y -CONFIG_CRYPTO_USER=m -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_PCRYPT=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_ECDH=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_SM4_GENERIC=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SM3_GENERIC=y -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_CRC32=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZ4HC=m -CONFIG_CRYPTO_ZSTD=y -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_USER_API_SKCIPHER=y -CONFIG_CRYPTO_USER_API_RNG=y -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_CRYPTO_DEV_CHELSIO=m -CONFIG_CRYPTO_DEV_VIRTIO=y -CONFIG_SIGNED_PE_FILE_VERIFICATION=y -CONFIG_SECONDARY_TRUSTED_KEYRING=y -CONFIG_SYSTEM_BLACKLIST_KEYRING=y -CONFIG_SYSTEM_REVOCATION_LIST=y -CONFIG_CORDIC=m -CONFIG_CMA_SIZE_MBYTES=256 -CONFIG_DMA_MAP_BENCHMARK=y -CONFIG_PRINTK_TIME=y -CONFIG_PRINTK_CALLER=y -CONFIG_BOOT_PRINTK_DELAY=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_HEADERS_INSTALL=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_KGDB=y -CONFIG_KGDB_TESTS=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x0 -CONFIG_KDB_KEYBOARD=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_SOFTLOCKUP_DETECTOR=y -CONFIG_WQ_WATCHDOG=y -CONFIG_SCHEDSTATS=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_RCU_CPU_STALL_TIMEOUT=60 -# CONFIG_RCU_TRACE is not set -CONFIG_BOOTTIME_TRACING=y -CONFIG_FUNCTION_PROFILER=y -CONFIG_STACK_TRACER=y -CONFIG_SCHED_TRACER=y -CONFIG_HWLAT_TRACER=y -CONFIG_TIMERLAT_TRACER=y -CONFIG_FTRACE_SYSCALLS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_SYNTH_EVENTS=y -CONFIG_RING_BUFFER_BENCHMARK=m -CONFIG_SAMPLES=y -CONFIG_IO_STRICT_DEVMEM=y -# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_ZL3073X_I2C is not set +# CONFIG_ZL3073X_SPI is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZONEFS_FS is not set +CONFIG_ZONE_DEVICE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZRAM=m +# CONFIG_ZRAM_BACKEND_842 is not set +# CONFIG_ZRAM_BACKEND_DEFLATE is not set +CONFIG_ZRAM_BACKEND_FORCE_LZO=y +# CONFIG_ZRAM_BACKEND_LZ4 is not set +# CONFIG_ZRAM_BACKEND_LZ4HC is not set +CONFIG_ZRAM_BACKEND_LZO=y +# CONFIG_ZRAM_BACKEND_ZSTD is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC=y +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +CONFIG_ZSMALLOC_STAT=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lz4" +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set diff --git a/SPECS/linux-lts/config.riscv64-rva20 b/SPECS/linux-lts/config.riscv64-rva20 new file mode 100644 index 0000000000..8376eaad74 --- /dev/null +++ b/SPECS/linux-lts/config.riscv64-rva20 @@ -0,0 +1,7207 @@ +CONFIG_ERRATA_THEAD_GHOSTWRITE=y +CONFIG_ERRATA_THEAD_WRITE_ONCE=y +CONFIG_64BIT=y +# CONFIG_6LOWPAN is not set +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_9P_FS=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +# CONFIG_ACCESSIBILITY is not set +CONFIG_ACLINT_SSWI=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI=y +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +# CONFIG_ACPI_BGRT is not set +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_DEBUG=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_DOCK=y +# CONFIG_ACPI_EC is not set +CONFIG_ACPI_FAN=y +CONFIG_ACPI_FFH=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +# CONFIG_ACPI_HOTPLUG_MEMORY is not set +CONFIG_ACPI_I2C_OPREGION=y +# CONFIG_ACPI_IPMI is not set +CONFIG_ACPI_MCFG=y +CONFIG_ACPI_MDIO=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NHLT=y +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PPTT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ACPI_RIMT=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_TABLE_LIB=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_THERMAL_LIB=y +CONFIG_ACPI_VIDEO=m +# CONFIG_AD525X_DPOT is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIN1100_PHY is not set +# CONFIG_ADIN1110 is not set +# CONFIG_ADIN_PHY is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_KCM is not set +# CONFIG_AF_RXRPC is not set +CONFIG_AF_UNIX_OOB=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_DWC is not set +# CONFIG_AHCI_SUNXI is not set +CONFIG_AIO=y +# CONFIG_AIR_EN8811H_PHY is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_ALIM7101_WDT=m +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ALTERA_MSGDMA is not set +CONFIG_ALTERA_STAPL=m +# CONFIG_ALTERA_TSE is not set +CONFIG_ALX=m +# CONFIG_AL_FIC is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_AMD8111_ETH is not set +CONFIG_AMD_PHY=m +# CONFIG_AMD_QDMA is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMT is not set +CONFIG_ANDES_CUSTOM_PMU=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_ANDROID_BINDER_IPC_RUST is not set +# CONFIG_ANON_VMA_NAME is not set +CONFIG_APDS9802ALS=m +CONFIG_APERTURE_HELPERS=y +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_APPLICOM is not set +# CONFIG_AQTION is not set +CONFIG_AQUANTIA_PHY=m +# CONFIG_AR5523 is not set +CONFIG_ARCH_ANDES=y +CONFIG_ARCH_CANAAN=y +CONFIG_ARCH_CC_CAN_LINK=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_ARCH_ESWIN=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +CONFIG_ARCH_HAS_CC_CAN_LINK=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_ELF_CORE_EFLAGS=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD=y +CONFIG_ARCH_HAS_PTDUMP=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAS_UBSAN=y +CONFIG_ARCH_HAS_VDSO_ARCH_DATA=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECTS_KEXEC=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SIFIVE=y +CONFIG_ARCH_SOPHGO=y +CONFIG_ARCH_SPACEMIT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_STARFIVE=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_CFI=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_RT=y +CONFIG_ARCH_SUPPORTS_SCHED_MC=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_THEAD=y +CONFIG_ARCH_ULTRARISC=y +CONFIG_ARCH_USERFLAGS="-march=rv64g -mabi=lp64d" +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +CONFIG_ARCH_VIRT=y +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y +# CONFIG_ARCNET is not set +CONFIG_ARM_AMBA=y +# CONFIG_ARM_HISI_UNCORE_DEVFREQ is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set +# CONFIG_AS21XXX_PHY is not set +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASN1_ENCODER=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_ASYNC_XOR=m +CONFIG_AS_HAS_INSN=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_AS_HAS_OPTION_ARCH=y +CONFIG_AS_HAS_ULEB128=y +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24690 +CONFIG_AT803X_PHY=m +CONFIG_ATA=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=m +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=m +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATH10K=m +# CONFIG_ATH10K_AHB is not set +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +CONFIG_ATH10K_LEDS=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_TRACING is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH11K is not set +# CONFIG_ATH12K is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_AT_XDMAC is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUTOFS_FS=y +CONFIG_AUXDISPLAY=y +CONFIG_AUXILIARY_BUS=y +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_AX88796B_PHY=m +# CONFIG_B44 is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_BD6107 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=m +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +# CONFIG_BACKLIGHT_LED is not set +# CONFIG_BACKLIGHT_LM3509 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_MP3309C is not set +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BALLOON_COMPACTION=y +# CONFIG_BAREUDP is not set +# CONFIG_BASE_SMALL is not set +CONFIG_BASIC_MODVERSIONS=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_CHAGALL is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_UG3105 is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA=m +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_NET_PHYPTP=m +# CONFIG_BCM_VK is not set +CONFIG_BE2ISCSI=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFQ_CGROUP_DEBUG is not set +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFS_FS is not set +# CONFIG_BIG_KEYS is not set +CONFIG_BINARY_PRINTF=y +CONFIG_BINDGEN_VERSION_TEXT="bindgen 0.72.1" +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +CONFIG_BLK_CGROUP=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_DM=m +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_RUST_NULL is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_DEV_ZONED_LOOP is not set +CONFIG_BLK_ICQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BLK_MQ_STACKING=y +CONFIG_BLK_PM=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +# CONFIG_BNGE is not set +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +# CONFIG_BNXT_HWMON is not set +CONFIG_BNXT_SRIOV=y +CONFIG_BONDING=m +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTTIME_TRACING=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BPF=y +CONFIG_BPF_EVENTS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPF_LSM is not set +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_STREAM_PARSER=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +CONFIG_BRIDGE=m +# CONFIG_BRIDGE_CFM is not set +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_BT is not set +CONFIG_BTREE=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +CONFIG_BTRFS_EXPERIMENTAL=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTT=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUG=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +CONFIG_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_BUILD_SALT="" +# CONFIG_C2PORT is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_CAIF=y +# CONFIG_CAIF_DEBUG is not set +# CONFIG_CAIF_DRIVERS is not set +CONFIG_CAIF_NETDEV=y +# CONFIG_CAIF_USB is not set +CONFIG_CAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_C_CAN_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +# CONFIG_CAN_ESD_USB is not set +# CONFIG_CAN_ETAS_ES58X is not set +# CONFIG_CAN_F81601 is not set +# CONFIG_CAN_F81604 is not set +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_GS_USB is not set +CONFIG_CAN_GW=m +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_ISOTP is not set +# CONFIG_CAN_J1939 is not set +CONFIG_CAN_KVASER_PCI=m +# CONFIG_CAN_KVASER_PCIEFD is not set +CONFIG_CAN_KVASER_USB=m +# CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# CONFIG_CAN_M_CAN is not set +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +# CONFIG_CAN_PEAK_PCIEFD is not set +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_RAW=m +# CONFIG_CAN_RCAR is not set +# CONFIG_CAN_RCAR_CANFD is not set +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SOFTING=m +# CONFIG_CAN_SUN4I is not set +# CONFIG_CAN_UCAN is not set +CONFIG_CAN_VCAN=m +# CONFIG_CAN_VXCAN is not set +# CONFIG_CARL9170 is not set +CONFIG_CAVIUM_PTP=y +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_ASSUME=y +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_IS_GCC=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (Debian 15.3.0-1) 15.3.0" +CONFIG_CDROM=y +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +# CONFIG_CGROUP_DMEM is not set +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_WRITEBACK=y +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_MAX8971 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_RT9467 is not set +# CONFIG_CHARGER_RT9471 is not set +# CONFIG_CHARGER_SBS is not set +CONFIG_CHARGER_SMB347=m +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_LIB=m +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +# CONFIG_CHELSIO_T4_DCB is not set +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_ST=m +CONFIG_CICADA_PHY=m +CONFIG_CIFS=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_COMPRESSION is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_SWN_UPCALL is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CLANG_VERSION=0 +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set +CONFIG_CLK_RENESAS=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +# CONFIG_CLK_SOPHGO_CV1800 is not set +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y +CONFIG_CLK_SOPHGO_SG2044=y +CONFIG_CLK_SOPHGO_SG2044_PLL=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7110_AON=m +CONFIG_CLK_STARFIVE_JH7110_ISP=m +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_STG=m +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=m +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_THEAD_TH1520_AP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLOSURES=y +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=19 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=256 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CNIC=m +# CONFIG_CODA_FS is not set +# CONFIG_COMEDI is not set +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_RPMI=y +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_VC3 is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT is not set +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_CONSOLE_POLL=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTEXT_TRACKING_USER=y +# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set +CONFIG_CONTIG_ALLOC=y +CONFIG_CORDIC=m +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_CORTINA_PHY is not set +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_CPUFREQ_DT_RUST is not set +# CONFIG_CPUFREQ_VIRT is not set +CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set +# CONFIG_CRASH_DM_CRYPT is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_CRC32_ARCH=y +CONFIG_CRC64=y +CONFIG_CRC64_ARCH=y +CONFIG_CRC7=y +CONFIG_CRC8=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_OPTIMIZATIONS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_T10DIF_ARCH=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_BENCHMARK is not set +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DEV_ALLWINNER=y +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_QAT_420XX is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_SUN4I_SS is not set +# CONFIG_CRYPTO_DEV_SUN8I_CE is not set +# CONFIG_CRYPTO_DEV_SUN8I_SS is not set +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set +CONFIG_CRYPTO_ECHAINIV=m +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_ENGINE=y +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_HCTR2 is not set +CONFIG_CRYPTO_HKDF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_KRB5 is not set +# CONFIG_CRYPTO_KRB5ENC is not set +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_MD5=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_ARCH=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SHA512=y +CONFIG_CRYPTO_LIB_SM3=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4=y +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SELFTESTS is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_SM3_GENERIC=y +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_RNG=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=y +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +# CONFIG_CV1800_MBOX is not set +CONFIG_CXD2880_SPI_DRV=m +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=y +# CONFIG_CXL_FEATURES is not set +CONFIG_CXL_MEM=y +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=y +CONFIG_CXL_PMEM=m +# CONFIG_CXL_PMU is not set +CONFIG_CXL_PORT=y +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_SUSPEND=y +CONFIG_DA9063_WATCHDOG=m +CONFIG_DAMON=y +CONFIG_DAMON_LRU_SORT=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_STAT=y +CONFIG_DAMON_STAT_ENABLED_DEFAULT=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y +CONFIG_DCB=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NET_SMALL_RTNL is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_PERF_USE_VMALLOC=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_VFS is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_ZSTD=y +# CONFIG_DEFAULT_CODEL is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_FQ is not set +CONFIG_DEFAULT_FQ_CODEL=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_DEFAULT_NET_SCH="fq_codel" +# CONFIG_DEFAULT_PFIFO_FAST is not set +# CONFIG_DEFAULT_RENO is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SFQ is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DETECT_HUNG_TASK_BLOCKER=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVICE_MIGRATION=y +CONFIG_DEVICE_PRIVATE=y +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +CONFIG_DEV_DAX_HMEM_DEVICES=y +CONFIG_DEV_DAX_KMEM=m +CONFIG_DEV_DAX_PMEM=m +# CONFIG_DIBS is not set +CONFIG_DIMLIB=y +# CONFIG_DLM is not set +# CONFIG_DM9051 is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMAPOOL_TEST is not set +# CONFIG_DMATEST is not set +CONFIG_DMA_ACPI=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_CMA=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_MAP_BENCHMARK=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_NONCOHERENT_MMAP=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_OF=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_SUN6I is not set +CONFIG_DMI=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DM_AUDIT=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_BUFIO=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +# CONFIG_DM_CLONE is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_DEBUG=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_DELAY=m +# CONFIG_DM_DUST is not set +# CONFIG_DM_EBS is not set +CONFIG_DM_ERA=m +CONFIG_DM_FLAKEY=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=m +CONFIG_DM_MULTIPATH=m +# CONFIG_DM_MULTIPATH_HST is not set +# CONFIG_DM_MULTIPATH_IOA is not set +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_PCACHE is not set +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_SWITCH=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_VDO=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_FEC is not set +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +# CONFIG_DM_WRITECACHE is not set +CONFIG_DM_ZERO=m +# CONFIG_DM_ZONED is not set +CONFIG_DNET=m +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=y +CONFIG_DP83640_PHY=m +# CONFIG_DP83822_PHY is not set +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +# CONFIG_DP83869_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set +CONFIG_DPLL=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRM=y +# CONFIG_DRM_ACCEL is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ACP is not set +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_FP=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DRM_AMD_ISP is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BRIDGE_CONNECTOR=y +CONFIG_DRM_BUDDY=m +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_CLIENT=y +CONFIG_DRM_CLIENT_DEFAULT="fbdev" +CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y +CONFIG_DRM_CLIENT_LIB=y +# CONFIG_DRM_CLIENT_LOG is not set +CONFIG_DRM_CLIENT_SELECTION=y +CONFIG_DRM_CLIENT_SETUP=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_DP_TUNNEL=y +CONFIG_DRM_DISPLAY_DSC_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DW_HDMI=m +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +# CONFIG_DRM_DW_HDMI_CEC is not set +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_EXEC=m +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=y +# CONFIG_DRM_GM12U320 is not set +CONFIG_DRM_GPUSVM=m +CONFIG_DRM_GPUVM=m +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_ITE_IT6263 is not set +# CONFIG_DRM_ITE_IT6505 is not set +# CONFIG_DRM_ITE_IT66121 is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_KOMEDA is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LOGICVC is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MGAG200=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_CH7006=m +CONFIG_DRM_NOUVEAU_SIL164=m +# CONFIG_DRM_NOVA is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS=m +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TD4320 is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112B is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_HYDIS_HV101HD1 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set +# CONFIG_DRM_PANEL_RENESAS_R61307 is not set +# CONFIG_DRM_PANEL_RENESAS_R69328 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_SUMMIT is not set +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# CONFIG_DRM_PANIC is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_PIXPAPER is not set +# CONFIG_DRM_POWERVR is not set +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_SAMSUNG_DSIM is not set +CONFIG_DRM_SCHED=m +# CONFIG_DRM_SHMOBILE is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIL_SII8620 is not set +CONFIG_DRM_SIMPLEDRM=y +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_SOLOMON_SSD2825 is not set +# CONFIG_DRM_SSD130X is not set +# CONFIG_DRM_ST7571_I2C is not set +# CONFIG_DRM_ST7586 is not set +# CONFIG_DRM_ST7735R is not set +CONFIG_DRM_SUBALLOC_HELPER=m +# CONFIG_DRM_SUN4I is not set +CONFIG_DRM_SYSFB_HELPER=y +CONFIG_DRM_THEAD_TH1520_DW_HDMI=m +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TI_DLPC3433 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TDP158 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VERISILICON_DC=m +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_WAVESHARE_BRIDGE is not set +# CONFIG_DRM_WERROR is not set +CONFIG_DRM_XE=m +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_MEMIRQ is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_DP_TUNNEL=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_GPUSVM=y +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +CONFIG_DRM_XE_PAGEMAP=y +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +# CONFIG_DS1682 is not set +CONFIG_DST_CACHE=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY=m +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_DUMMY_IRQ is not set +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m +# CONFIG_DVB_AS102 is not set +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_CXD2099=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_CXD2880=m +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_DRXK=m +CONFIG_DVB_DS3000=m +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_EC100=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_L64781=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MB86A20S=m +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_MN88443X=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_MT312=m +CONFIG_DVB_MT352=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_MXL692=m +# CONFIG_DVB_NET is not set +CONFIG_DVB_NXT200X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +# CONFIG_DVB_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLL=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_S921=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_SP2=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0297=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_TC90522=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TS2020=m +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_ULE_DEBUG is not set +# CONFIG_DVB_USB_V2 is not set +CONFIG_DVB_VES1820=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_ZL10353=m +# CONFIG_DWC_PCIE_PMU is not set +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_RENESAS_GBETH=m +CONFIG_DWMAC_SOPHGO=m +CONFIG_DWMAC_SPACEMIT=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_SUN55I=m +CONFIG_DWMAC_SUN8I=m +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_THEAD=m +# CONFIG_DW_AXI_DMAC is not set +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC_PCI=m +# CONFIG_DW_EDMA is not set +CONFIG_DW_WATCHDOG=m +# CONFIG_DW_XDATA_PCIE is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_SIGFRAME=y +# CONFIG_E100 is not set +CONFIG_E1000=m +CONFIG_E1000E=y +# CONFIG_ECRYPT_FS is not set +CONFIG_EDAC=y +# CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_ECS is not set +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_MEM_REPAIR is not set +# CONFIG_EDAC_SCRUB is not set +CONFIG_EDAC_SIFIVE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_M24LR is not set +CONFIG_EEPROM_MAX6875=m +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +# CONFIG_EFI_ZBOOT is not set +# CONFIG_EFS_FS is not set +CONFIG_ELFCORE=y +CONFIG_ELF_CORE=y +CONFIG_ENA_ETHERNET=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_EPIC100=m +CONFIG_EPOLL=y +CONFIG_EPROBE_EVENTS=y +CONFIG_EQUALIZER=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_BACKED_BY_FILE=y +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ACCEL is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +# CONFIG_EROFS_FS_ZIP_LZMA is not set +# CONFIG_EROFS_FS_ZIP_ZSTD is not set +CONFIG_ERRATA_ANDES=y +CONFIG_ERRATA_MIPS=y +CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_MAE=y +CONFIG_ERRATA_THEAD_PMU=y +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_EVENTFD=y +CONFIG_EVENT_TRACING=y +CONFIG_EVM=y +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +CONFIG_EVM_LOAD_X509=y +CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=y +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXTCON=y +# CONFIG_EXTCON_FSA9480 is not set +CONFIG_EXTCON_GPIO=m +# CONFIG_EXTCON_LC824206XA is not set +# CONFIG_EXTCON_MAX14526 is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTENDED_MODVERSIONS=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +# CONFIG_FARSYNC is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_FB=y +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_CARMINE is not set +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CIRRUS is not set +CONFIG_FB_CORE=y +# CONFIG_FB_CYBER2000 is not set +CONFIG_FB_DDC=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +# CONFIG_FB_KYRO is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_NEOMAGIC is not set +CONFIG_FB_NOTIFY=y +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_RADEON=y +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_RADEON_I2C=y +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_SSD1307=m +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +CONFIG_FCOE=m +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +CONFIG_FHANDLE=y +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_FIRMWARE_TABLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FM10K=m +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_FPGA is not set +# CONFIG_FPROBE is not set +CONFIG_FPU=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMER is not set +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FREEZER=y +# CONFIG_FSCACHE is not set +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_DAX is not set +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +# CONFIG_FS_VERITY is not set +# CONFIG_FTL is not set +CONFIG_FTRACE=y +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set +# CONFIG_FUEL_GAUGE_STC3117 is not set +# CONFIG_FUJITSU_ES is not set +CONFIG_FUNCTION_ALIGNMENT=8 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ALIGNMENT_8B=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FUNCTION_GRAPH_RETADDR is not set +# CONFIG_FUNCTION_GRAPH_RETVAL is not set +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_TRACE_ARGS=y +# CONFIG_FUN_ETH is not set +CONFIG_FUSE_FS=y +CONFIG_FUSE_IO_URING=y +CONFIG_FUSE_PASSTHROUGH=y +# CONFIG_FUSION is not set +CONFIG_FUTEX=y +CONFIG_FUTEX_MPOL=y +CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y +# CONFIG_FWCTL is not set +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_FW_UPLOAD=y +CONFIG_GACT_PROB=y +# CONFIG_GAMEPORT is not set +CONFIG_GARP=m +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_GCC_VERSION=150300 +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_GENDWARFKSYMS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_NUMA=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_ENTRY=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_SYSCALL=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_TRACER=y +CONFIG_GENEVE=m +# CONFIG_GENKSYMS is not set +# CONFIG_GENWQE is not set +CONFIG_GET_FREE_REGION=y +# CONFIG_GFS2_FS is not set +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GNSS is not set +CONFIG_GOLDFISH=y +# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH_TTY is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIOLIB_LEGACY=y +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +CONFIG_GPIO_ACPI=y +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_BT8XX is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +# CONFIG_GPIO_DS4520 is not set +CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_FXL6408 is not set +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=m +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPSSE is not set +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_POLARFIRE_SOC is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_SIM is not set +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +CONFIG_GPIO_SPACEMIT_K1=y +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SYSFS_LEGACY=y +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set +CONFIG_GPIO_WATCHDOG=m +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_GP_PCI1XXXX is not set +CONFIG_GRACE_PERIOD=y +# CONFIG_GREENASIA_FF is not set +# CONFIG_GREYBUS is not set +CONFIG_GROUP_SCHED_BANDWIDTH=y +CONFIG_GROUP_SCHED_WEIGHT=y +CONFIG_GRO_CELLS=y +# CONFIG_GTP is not set +CONFIG_GUEST_PERF_EVENTS=y +# CONFIG_GUP_TEST is not set +# CONFIG_HAMRADIO is not set +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_DEFAULT_ON=y +CONFIG_HARDIRQS_SW_RESEND=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_SECURITY_AUDIT=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_HAVE_ARCH_KFENCE=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_HAVE_ARCH_KSTACK_ERASE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_FTRACE_GRAPH_FUNC=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_TIF_BITS=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_GIGANTIC_FOLIOS=y +CONFIG_HAVE_GUP_FAST=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_UNCOMPRESSED=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KVM_DIRTY_RING=y +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_READONLY_MEM=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_TRUSTED_KEYS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HD44780 is not set +CONFIG_HDLC=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_RAW=m +# CONFIG_HDLC_RAW_ETH is not set +CONFIG_HDMI=y +CONFIG_HEADERS_INSTALL=y +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFS_FS is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_DEF_COMP="lzo" +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +# CONFIG_HIBMCGE is not set +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +CONFIG_HID_ACRUX=m +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_ALPS is not set +CONFIG_HID_APPLE=y +CONFIG_HID_APPLEIR=m +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BETOP_FF=m +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_BPF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CORSAIR=m +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=m +# CONFIG_HID_ELAN is not set +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EVISION is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=y +CONFIG_HID_GFRM=m +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_GOODIX_SPI is not set +# CONFIG_HID_GOOGLE_STADIA_FF is not set +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +# CONFIG_HID_HAPTIC is not set +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=y +# CONFIG_HID_JABRA is not set +CONFIG_HID_KENSINGTON=y +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +# CONFIG_HID_KYSONA is not set +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +# CONFIG_HID_MACALLY is not set +CONFIG_HID_MAGICMOUSE=y +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MCP2200 is not set +# CONFIG_HID_MCP2221 is not set +# CONFIG_HID_MEGAWORLD_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=m +# CONFIG_HID_NINTENDO is not set +# CONFIG_HID_NTI is not set +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_RETRODE is not set +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_SENSOR_HUB=m +# CONFIG_HID_SIGMAMICRO is not set +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +# CONFIG_HID_STEAM is not set +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +# CONFIG_HID_TOPRE is not set +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +# CONFIG_HID_U2FZERO is not set +CONFIG_HID_UCLOGIC=m +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_UNIVERSAL_PIDFF is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_VRC2 is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set +# CONFIG_HID_XIAOMI is not set +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_HMC6352 is not set +CONFIG_HMEM_REPORTING=y +CONFIG_HMM_MIRROR=y +# CONFIG_HOLTEK_FF is not set +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_OCTEONEP is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +# CONFIG_HPFS_FS is not set +# CONFIG_HP_ILO is not set +CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HT16K33 is not set +# CONFIG_HTE is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HVC_DRIVER=y +CONFIG_HWLAT_TRACER=y +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON_VID=m +CONFIG_HWSPINLOCK=y +# CONFIG_HWSPINLOCK_SUN6I is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_JH7110 is not set +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=m +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +# CONFIG_I2C_AT91 is not set +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DIOLAN_U2C=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_CORE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +CONFIG_I2C_K1=m +# CONFIG_I2C_MICROCHIP_CORE is not set +CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_GPIO=m +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_MULE is not set +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MV64XXX is not set +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_NVIDIA_GPU is not set +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RIIC is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_RZV2M is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_STUB=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VIRTIO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2C_ZHAOXIN is not set +# CONFIG_I3C is not set +CONFIG_I40E=m +CONFIG_I40EVF=m +# CONFIG_I40E_DCB is not set +CONFIG_I6300ESB_WDT=m +CONFIG_IAVF=m +CONFIG_ICE=m +CONFIG_ICE_HWMON=y +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICPLUS_PHY=m +# CONFIG_ICS932S401 is not set +CONFIG_IDLE_PAGE_TRACKING=y +# CONFIG_IDPF is not set +# CONFIG_IEEE802154 is not set +CONFIG_IFB=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGB_HWMON=y +# CONFIG_IGC is not set +# CONFIG_IIO is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMA=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +# CONFIG_IMA_APPRAISE_MODSIG is not set +# CONFIG_IMA_APPRAISE_SIGNED_INIT is not set +# CONFIG_IMA_ARCH_POLICY is not set +# CONFIG_IMA_BLACKLIST_KEYRING is not set +CONFIG_IMA_DEFAULT_HASH="sha256" +# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set +CONFIG_IMA_DEFAULT_HASH_SHA256=y +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +# CONFIG_IMA_DEFAULT_HASH_SM3 is not set +CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" +# CONFIG_IMA_DISABLE_HTABLE is not set +# CONFIG_IMA_KEXEC is not set +# CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY is not set +CONFIG_IMA_LOAD_X509=y +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y +CONFIG_IMA_READ_POLICY=y +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_WRITE_POLICY is not set +CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_INET=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=m +# CONFIG_INET_PSP is not set +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_SCTP_DIAG=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +# CONFIG_INFINIBAND_EFA is not set +# CONFIG_INFINIBAND_ERDMA is not set +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +# CONFIG_INFINIBAND_MTHCA is not set +# CONFIG_INFINIBAND_OCRDMA is not set +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_RTRS_CLIENT is not set +# CONFIG_INFINIBAND_RTRS_SERVER is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_VIRT_DMA=y +# CONFIG_INFTL is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_STACK_NONE=y +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_AW86927 is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_DA9063_ONKEY is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_IBM_PANEL is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +CONFIG_INPUT_SPARSEKMAP=m +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_VIVALDIFMAP=y +# CONFIG_INPUT_YEALINK is not set +CONFIG_INTEGRITY=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_INTEGRITY_MACHINE_KEYRING is not set +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_TH is not set +# CONFIG_INTEL_XWAY_PHY is not set +CONFIG_INTERCONNECT=y +CONFIG_INTERVAL_TREE=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IONIC is not set +CONFIG_IOSCHED_BFQ=y +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IO_URING_MOCK_FILE is not set +CONFIG_IO_URING_ZCRX=y +CONFIG_IO_WQ=y +# CONFIG_IP5XXX_POWER is not set +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_MATCH_SRH is not set +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +# CONFIG_IPACK_BUS is not set +CONFIG_IPC_NS=y +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_IPMB is not set +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPV6=y +CONFIG_IPV6_GRE=m +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +# CONFIG_IPV6_SUBTREES is not set +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPVLAN=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVTAP=m +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +# CONFIG_IP_SET_HASH_IPMAC is not set +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +# CONFIG_IP_VS_MH is not set +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +# CONFIG_IP_VS_TWOS is not set +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IRQCHIP=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TCP=m +# CONFIG_ISDN is not set +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_ISO9660_FS=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_JH71XX_PMU=y +# CONFIG_JME is not set +CONFIG_JOLIET=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KARMA_PARTITION=y +# CONFIG_KASAN is not set +CONFIG_KCMP=y +# CONFIG_KCOV is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x0 +CONFIG_KDB_KEYBOARD=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_UNCOMPRESSED=y +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KERNFS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_ELF=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_KEY_DH_OPERATIONS is not set +CONFIG_KFENCE=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=100 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +CONFIG_KGDB_TESTS=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +CONFIG_KPROBES=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_KSM=y +# CONFIG_KUNIT is not set +CONFIG_KVFREE_RCU_BATCHED=y +CONFIG_KVM=m +CONFIG_KVM_COMMON=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_KVM_GENERIC_MMU_NOTIFIER=y +CONFIG_KVM_MMIO=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP_V3=y +# CONFIG_LAPB is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LCD2S is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_PARTITION is not set +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set +CONFIG_LD_IS_BFD=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_LD_VERSION=24690 +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AS3645A is not set +# CONFIG_LEDS_AW200XX is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_BLINKM=m +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3530=m +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3601X is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3697 is not set +CONFIG_LEDS_LP3944=m +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LP8864 is not set +CONFIG_LEDS_LT3593=m +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_ST1202 is not set +# CONFIG_LEDS_SY7802 is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_TPS6131X is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +CONFIG_LEDS_TRIGGER_ONESHOT=m +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +# CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LIBETH=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y +CONFIG_LIBIE=m +CONFIG_LIBIE_ADMINQ=m +CONFIG_LIBIE_FWLOG=m +CONFIG_LIBNVDIMM=m +CONFIG_LIBWX=m +CONFIG_LINEAR_RANGES=y +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_CORE=m +CONFIG_LIQUIDIO_VF=m +CONFIG_LIST_HARDENED=y +# CONFIG_LITEX_LITEETH is not set +# CONFIG_LITEX_SOC_CONTROLLER is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +CONFIG_LLD_VERSION=0 +# CONFIG_LMK04832 is not set +CONFIG_LOAD_UEFI_KEYS=y +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKD=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=20 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOOPBACK_TARGET=m +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +CONFIG_LRU_CACHE=m +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" +CONFIG_LSM_MMAP_MIN_ADDR=32768 +CONFIG_LTO_NONE=y +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_LXT_PHY=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211=m +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_HWSIM is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +# CONFIG_MAC_PARTITION is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +# CONFIG_MANAGER_SBS is not set +CONFIG_MARVELL_10G_PHY=m +# CONFIG_MARVELL_88Q2XXX_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +CONFIG_MARVELL_PHY=m +# CONFIG_MAX31827 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX6959 is not set +# CONFIG_MAXLINEAR_86110_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +CONFIG_MAX_SKB_FRAGS=17 +# CONFIG_MCB is not set +CONFIG_MCHP_CLK_MPFS=y +# CONFIG_MCHP_LAN966X_PCI is not set +# CONFIG_MCHP_SBI_IPC_MBOX is not set +# CONFIG_MCTP is not set +CONFIG_MD=y +CONFIG_MDIO=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_MVUSB is not set +CONFIG_MDIO_OCTEON=m +# CONFIG_MDIO_SUN4I is not set +CONFIG_MDIO_THUNDER=m +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP=y +CONFIG_MD_BITMAP_FILE=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_LLBITMAP is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MEDIATEK_GE_PHY is not set +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +CONFIG_MEGARAID_SAS=m +CONFIG_MEMBARRIER=y +CONFIG_MEMCG=y +# CONFIG_MEMCG_V1 is not set +CONFIG_MEMFD_CREATE=y +# CONFIG_MEMORY is not set +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMREGION=y +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +# CONFIG_MEMSTICK_REALTEK_USB is not set +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +# CONFIG_MEMTEST is not set +# CONFIG_MEM_ALLOC_PROFILING is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_ADP5585 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_AT91_USART is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_BQ257XX is not set +CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +CONFIG_MFD_DA9063=m +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_LS2K_BMC_CORE is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX5970 is not set +# CONFIG_MFD_MAX7360 is not set +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77705 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77759 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_NCT6694 is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_SEC_I2C is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMPRO is not set +CONFIG_MFD_SPACEMIT_P1=m +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_SUN4I_GPADC is not set +# CONFIG_MFD_SUN6I_PRCM is not set +# CONFIG_MFD_SY7636A is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE is not set +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set +CONFIG_MHP_MEMMAP_ON_MEMORY=y +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1S_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROSEMI_PHY=m +CONFIG_MIGRATION=y +CONFIG_MII=m +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_MIN_HEAP=y +# CONFIG_MISC_ALCOR_PCI is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISC_RP1 is not set +CONFIG_MISC_RTSX=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MLX4_CORE=m +# CONFIG_MLX4_CORE_GEN2 is not set +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_DPLL is not set +CONFIG_MLX5_EN_ARFS=y +# CONFIG_MLX5_EN_IPSEC is not set +CONFIG_MLX5_EN_RXNFC=y +# CONFIG_MLX5_EN_TLS is not set +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_HW_STEERING=y +CONFIG_MLX5_INFINIBAND=m +# CONFIG_MLX5_MACSEC is not set +CONFIG_MLX5_MPFS=y +# CONFIG_MLX5_SF is not set +CONFIG_MLX5_SW_STEERING=y +# CONFIG_MLX5_VFIO_PCI is not set +CONFIG_MLXFW=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +# CONFIG_MLXSW_SPECTRUM is not set +CONFIG_MMC=y +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=y +CONFIG_MMC_CRYPTO=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_BLUEFIELD=m +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_MTK=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_ACPI is not set +CONFIG_MMC_SDHCI_CADENCE=y +# CONFIG_MMC_SDHCI_F_SDH30 is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_OF_K1=m +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_UHS2=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHI is not set +# CONFIG_MMC_SH_MMCIF is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_SUNXI is not set +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_TOSHIBA_PCI=m +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMIOWB=y +CONFIG_MMP_PDMA=m +CONFIG_MMU=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MM_ID=y +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ALL=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_DECOMPRESS=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULE_SIG_HASH="sha256" +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_SHA1 is not set +CONFIG_MODULE_SIG_SHA256=y +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +# CONFIG_MOST is not set +# CONFIG_MOTORCOMM_PHY is not set +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXTET is not set +CONFIG_MPILIB=y +CONFIG_MPLS=y +# CONFIG_MPLS_ROUTING is not set +CONFIG_MPTCP=y +CONFIG_MPTCP_IPV6=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_MRP=m +# CONFIG_MSCC_OCELOT_SWITCH is not set +CONFIG_MSDOS_FS=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSE102X is not set +CONFIG_MSPRO_BLOCK=m +# CONFIG_MS_BLOCK is not set +CONFIG_MTD=m +# CONFIG_MTD_ABSENT is not set +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +# CONFIG_MTD_BLOCK_RO is not set +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CMDLINE_PARTS=m +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD_INTEL_DG is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PHRAM is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_NVMEM is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTIUSER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MYRI10GE is not set +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +# CONFIG_NCN26000_PHY is not set +CONFIG_ND_BTT=m +CONFIG_ND_CLAIM=y +CONFIG_ND_PFN=m +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET=y +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVSIM is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XTABLES_LEGACY is not set +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_NETFILTER_XT_NAT is not set +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +# CONFIG_NETFILTER_XT_TARGET_CT is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=m +# CONFIG_NETFILTER_XT_TARGET_HL is not set +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_MASQUERADE is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +# CONFIG_NETFS_DEBUG is not set +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETKIT is not set +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=y +CONFIG_NETPOLL=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETXEN_NIC=m +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +# CONFIG_NET_9P_RDMA is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_ACT_BPF=m +# CONFIG_NET_ACT_CONNMARK is not set +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_GACT=m +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_ACT_IFE is not set +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CORE=y +CONFIG_NET_CRC32C=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NET_DROP_MONITOR=m +# CONFIG_NET_DSA is not set +CONFIG_NET_EGRESS=y +CONFIG_NET_EMATCH=y +# CONFIG_NET_EMATCH_CANID is not set +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_FAILOVER=y +CONFIG_NET_FC=y +CONFIG_NET_FLOW_LIMIT=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_NET_HANDSHAKE=y +# CONFIG_NET_IFE is not set +CONFIG_NET_INGRESS=y +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_NET_NCSI is not set +CONFIG_NET_NS=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_REDIRECT=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_BPF is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_CBS is not set +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_DEFAULT=y +CONFIG_NET_SCH_DRR=m +# CONFIG_NET_SCH_DUALPI2 is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_ETS is not set +CONFIG_NET_SCH_FIFO=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_CODEL=m +# CONFIG_NET_SCH_FQ_PIE is not set +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SHAPER=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_NET_VENDOR_AGERE is not set +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALLWINNER=y +# CONFIG_NET_VENDOR_ALTEON is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_SPACEMIT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +CONFIG_NET_VENDOR_VERTEXCOM=y +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_NET_VRF=m +CONFIG_NET_XGRESS=y +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_APP_FLOWER=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP_NET_IPSEC=y +CONFIG_NFSD=m +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_LEGACY_CLIENT_TRACKING=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_V4_2_INTER_SSC=y +# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_DEBUG=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_LOCALIO is not set +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_2=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_NFS_V4_SECURITY_LABEL=y +# CONFIG_NFTL is not set +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COMPAT_ARP=m +# CONFIG_NFT_CONNLIMIT is not set +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +# CONFIG_NFT_EXTHDR_DCCP is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +# CONFIG_NFT_OSF is not set +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +# CONFIG_NFT_REJECT_NETDEV is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_SYNPROXY is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_XFRM is not set +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_AMANDA=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NGBE=m +# CONFIG_NGBEVF is not set +# CONFIG_NIC7018_WDT is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +CONFIG_NLMON=m +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +CONFIG_NODES_SHIFT=7 +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_TRACER=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +# CONFIG_NOVA_CORE is not set +# CONFIG_NOZOMI is not set +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_PAGE_MAPCOUNT is not set +CONFIG_NR_CPUS=256 +# CONFIG_NSM is not set +# CONFIG_NTB is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS_FS=m +CONFIG_NTSYNC=m +# CONFIG_NULL_TTY is not set +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NUMA_EMU is not set +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NVDIMM_DAX=y +CONFIG_NVDIMM_KEYS=y +CONFIG_NVDIMM_PFN=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SOPHGO_EFUSE=m +# CONFIG_NVMEM_SUNXI_SID is not set +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_U_BOOT_ENV is not set +CONFIG_NVME_AUTH=y +CONFIG_NVME_CORE=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_KEYRING=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_AUTH is not set +# CONFIG_NVME_TARGET_DEBUGFS is not set +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_PASSTHRU=y +# CONFIG_NVME_TARGET_PCI_EPF is not set +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_TCP_TLS is not set +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NUMA=y +CONFIG_OF_OVERLAY=y +# CONFIG_OF_PARTITION is not set +CONFIG_OF_PMEM=m +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OID_REGISTRY=y +# CONFIG_OMFS_FS is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +# CONFIG_OPEN_DICE is not set +# CONFIG_ORANGEFS_FS is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OSNOISE_TRACER=y +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVMF_DEBUG_LOG is not set +CONFIG_OVPN=m +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_PAGE_COUNTER=y +# CONFIG_PAGE_EXTENSION is not set +CONFIG_PAGE_IDLE_FLAG=y +CONFIG_PAGE_MAPCOUNT=y +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_VERSION=131 +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARAVIRT is not set +# CONFIG_PARPORT is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ACPI is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +CONFIG_PATA_TIMINGS=y +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PC104 is not set +# CONFIG_PC300TOO is not set +CONFIG_PCC=y +# CONFIG_PCCARD is not set +CONFIG_PCI=y +# CONFIG_PCI200SYN is not set +CONFIG_PCIEAER=y +CONFIG_PCIEAER_CXL=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_CADENCE=m +CONFIG_PCIE_CADENCE_HOST=m +# CONFIG_PCIE_CADENCE_PLAT_EP is not set +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +CONFIG_PCIE_DPC=y +CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_DEBUGFS is not set +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_ECRC=y +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_FU740=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_PLDA_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_RCAR_EP is not set +# CONFIG_PCIE_RCAR_GEN4_EP is not set +# CONFIG_PCIE_RCAR_GEN4_HOST is not set +# CONFIG_PCIE_RCAR_HOST is not set +CONFIG_PCIE_SG2042_HOST=m +CONFIG_PCIE_SOPHGO_DW=y +CONFIG_PCIE_SPACEMIT_K1=y +CONFIG_PCIE_STARFIVE_HOST=y +# CONFIG_PCIE_THERMAL is not set +# CONFIG_PCIE_TPH is not set +CONFIG_PCIE_ULTRARISC=m +CONFIG_PCIE_XILINX=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_ATS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_DOE=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCI_ECAM=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +# CONFIG_PCI_ENDPOINT_MSI_DOORBELL is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_PCI_EPF_NTB is not set +# CONFIG_PCI_EPF_TEST is not set +# CONFIG_PCI_FTPCI100 is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI=y +# CONFIG_PCI_NPEM is not set +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_PASID=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTRL=y +CONFIG_PCI_PWRCTRL_SLOT=y +CONFIG_PCI_QUIRKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +# CONFIG_PCI_SW_SWITCHTEC is not set +# CONFIG_PCNET32 is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCS_RZN1_MIIC=m +CONFIG_PCS_XPCS=m +# CONFIG_PDC_ADMA is not set +# CONFIG_PDS_CORE is not set +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_PFCP is not set +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=5 +# CONFIG_PHANTOM is not set +# CONFIG_PHONET is not set +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_NXP_PTN3222 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_PACKAGE=m +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set +# CONFIG_PHY_RCAR_GEN2 is not set +# CONFIG_PHY_RCAR_GEN3_PCIE is not set +# CONFIG_PHY_RCAR_GEN3_USB2 is not set +# CONFIG_PHY_RCAR_GEN3_USB3 is not set +# CONFIG_PHY_SOPHGO_CV1800_USB2 is not set +CONFIG_PHY_SPACEMIT_K1_PCIE=y +CONFIG_PHY_SPACEMIT_K1_USB2=m +CONFIG_PHY_SPACEMIT_K3_COMBO_PHY=m +CONFIG_PHY_SPACEMIT_K3_COMMON_OPS=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_SUN4I_USB is not set +# CONFIG_PHY_SUN50I_USB3 is not set +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +# CONFIG_PHY_SUN9I_USB is not set +CONFIG_PHY_TH1520_USB=m +# CONFIG_PHY_TUSB1210 is not set +CONFIG_PID_NS=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_AW9523 is not set +# CONFIG_PINCTRL_CY8C95X0 is not set +# CONFIG_PINCTRL_EIC7700 is not set +# CONFIG_PINCTRL_K230 is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RENESAS=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_SOPHGO_COMMON=y +# CONFIG_PINCTRL_SOPHGO_CV1800B is not set +# CONFIG_PINCTRL_SOPHGO_CV1812H is not set +# CONFIG_PINCTRL_SOPHGO_SG2000 is not set +# CONFIG_PINCTRL_SOPHGO_SG2002 is not set +CONFIG_PINCTRL_SOPHGO_SG2042=y +CONFIG_PINCTRL_SOPHGO_SG2042_OPS=y +CONFIG_PINCTRL_SOPHGO_SG2044=y +CONFIG_PINCTRL_SPACEMIT_K1=y +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SUN4I_A10 is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN55I_A523 is not set +# CONFIG_PINCTRL_SUN55I_A523_R is not set +# CONFIG_PINCTRL_SUN5I is not set +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_SUNXI=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_TH1520=y +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set +CONFIG_PLDMFW=y +# CONFIG_PLFXLC is not set +# CONFIG_PLX_DMA is not set +CONFIG_PM=y +CONFIG_PMBUS=m +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +CONFIG_PMIC_OPREGION=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_FLEXFILE_LAYOUT=y +CONFIG_PNP=y +CONFIG_PNPACPI=y +CONFIG_PNP_DEBUG_MESSAGES=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set +CONFIG_PORTABLE=y +# CONFIG_POSIX_AUX_CLOCKS is not set +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POSIX_TIMERS=y +# CONFIG_POWERCAP is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SPACEMIT_P1=m +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_TH1520_AON=m +CONFIG_POWER_SEQUENCING=m +# CONFIG_POWER_SEQUENCING_QCOM_WCN is not set +CONFIG_POWER_SEQUENCING_TH1520_GPU=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPP=m +CONFIG_PPPOE=m +CONFIG_PPPOE_HASH_BITS=4 +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS=y +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPS_GENERATOR is not set +CONFIG_PPTP=m +# CONFIG_PREEMPT is not set +CONFIG_PREEMPTION=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPT_LAZY is not set +CONFIG_PREEMPT_NONE=y +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +# CONFIG_PREEMPT_RT is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_PRIME_NUMBERS is not set +CONFIG_PRINTK=y +CONFIG_PRINTK_CALLER=y +# CONFIG_PRINTK_INDEX is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +# CONFIG_PROVE_LOCKING is not set +CONFIG_PSAMPLE=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTP_1588_CLOCK=y +# CONFIG_PTP_1588_CLOCK_FC3W is not set +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_INES is not set +# CONFIG_PTP_1588_CLOCK_MOCK is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +# CONFIG_PTP_NETC_V4_TIMER is not set +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +# CONFIG_PWM_ARGON_FAN_HAT is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set +# CONFIG_PWM_MC33XS2410 is not set +# CONFIG_PWM_MICROCHIP_CORE is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_PROVIDE_GPIO is not set +# CONFIG_PWM_PXA is not set +# CONFIG_PWM_RENESAS_RCAR is not set +# CONFIG_PWM_RENESAS_TPU is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_SOPHGO_SG2042=m +# CONFIG_PWM_SUN4I is not set +CONFIG_PWM_TH1520=m +# CONFIG_PWM_XILINX is not set +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA807X_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +CONFIG_QCOM_EMAC=m +CONFIG_QCOM_HIDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_NET_PHYLIB=m +# CONFIG_QCOM_PMIC_GLINK is not set +# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED_FCOE=y +CONFIG_QED_ISCSI=y +CONFIG_QED_LL2=y +CONFIG_QED_OOO=y +CONFIG_QED_RDMA=y +CONFIG_QED_SRIOV=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QLA3XXX=m +# CONFIG_QLCNIC is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QRTR is not set +CONFIG_QSEMI_PHY=m +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=y +CONFIG_R8169=y +CONFIG_RADIO_ADAPTERS=m +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RAPIDIO is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RCAR_DMAC is not set +# CONFIG_RCAR_GEN3_THERMAL is not set +# CONFIG_RCAR_THERMAL is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RC_CORE is not set +CONFIG_RDMA_RXE=m +# CONFIG_RDMA_SIW is not set +# CONFIG_RDS is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=y +# CONFIG_REALTEK_PHY_HWMON is not set +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=m +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ADP5055 is not set +# CONFIG_REGULATOR_AW37503 is not set +# CONFIG_REGULATOR_DA9063 is not set +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX20411 is not set +# CONFIG_REGULATOR_MAX77503 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MAX77838 is not set +# CONFIG_REGULATOR_MAX77857 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF0900 is not set +# CONFIG_REGULATOR_PF530X is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PF9453 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RAA215300 is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT4803 is not set +# CONFIG_REGULATOR_RT5133 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5739 is not set +# CONFIG_REGULATOR_RT5759 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTQ2208 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_SLG51000 is not set +CONFIG_REGULATOR_SPACEMIT_P1=m +CONFIG_REGULATOR_SUN20I=y +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC is not set +# CONFIG_REMOTE_TARGET is not set +# CONFIG_RENESAS_OSTM is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_RENESAS_RZAWDT is not set +# CONFIG_RENESAS_RZN1WDT is not set +# CONFIG_RENESAS_RZV2HWDT is not set +# CONFIG_RENESAS_USB_DMAC is not set +# CONFIG_RENESAS_WDT is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_RESET_K230=y +CONFIG_RESET_POLARFIRE_SOC=y +# CONFIG_RESET_RZV2H_USB2PHY is not set +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SPACEMIT_COMMON=y +CONFIG_RESET_SPACEMIT_K1=y +CONFIG_RESET_SPACEMIT_K3=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_SUNXI=y +CONFIG_RESET_TH1520=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set +CONFIG_RETHOOK=y +# CONFIG_RFD_FTL is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFS_ACCEL=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RISCV=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_APLIC=y +CONFIG_RISCV_APLIC_MSI=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_RISCV_COMBO_SPINLOCKS=y +CONFIG_RISCV_DMA_NONCOHERENT=y +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set +CONFIG_RISCV_IMSIC=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_IOMMU=y +CONFIG_RISCV_IOMMU_PCI=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SUPM=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_VENDOR_EXT=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y +CONFIG_RISCV_ISA_VENDOR_EXT_MIPS=y +CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y +CONFIG_RISCV_ISA_VENDOR_EXT_THEAD=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_V_PREEMPTIVE=y +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 +CONFIG_RISCV_ISA_XTHEADVECTOR=y +CONFIG_RISCV_ISA_ZABHA=y +CONFIG_RISCV_ISA_ZACAS=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y +CONFIG_RISCV_ISA_ZBKB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOP=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_MISALIGNED=y +CONFIG_RISCV_NONSTANDARD_CACHE_OPS=y +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS=y +CONFIG_RISCV_RPMI_SYSMSI=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_CPUIDLE=y +CONFIG_RISCV_SBI_MPXY_MBOX=y +# CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SCALAR_MISALIGNED=y +# CONFIG_RISCV_TICKET_SPINLOCKS is not set +CONFIG_RISCV_TIMER=y +CONFIG_RISCV_VECTOR_MISALIGNED=y +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +# CONFIG_RMI4_F1A is not set +# CONFIG_RMI4_F21 is not set +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +# CONFIG_RMI4_F55 is not set +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +# CONFIG_RMNET is not set +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_ROCKER=m +# CONFIG_ROMFS_FS is not set +CONFIG_ROOT_NFS=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set +# CONFIG_RPMB is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_NS=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_TTY is not set +CONFIG_RPMSG_VIRTIO=y +CONFIG_RPS=y +CONFIG_RSEQ=y +# CONFIG_RT2400PCI is not set +# CONFIG_RT2500PCI is not set +# CONFIG_RT2500USB is not set +# CONFIG_RT2800PCI is not set +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +# CONFIG_RT2800USB_RT3573 is not set +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +# CONFIG_RT2800USB_RT55XX is not set +# CONFIG_RT2800USB_UNKNOWN is not set +CONFIG_RT2800_LIB=m +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_USB=m +# CONFIG_RT61PCI is not set +# CONFIG_RT73USB is not set +# CONFIG_RTASE is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_DRV_ABB5ZES3=m +# CONFIG_RTC_DRV_ABEOZ9 is not set +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_CADENCE is not set +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685=y +CONFIG_RTC_DRV_DS1685_FAMILY=m +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +# CONFIG_RTC_DRV_FTRTC010 is not set +CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_ISL12022=m +# CONFIG_RTC_DRV_ISL12026 is not set +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX31335 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +# CONFIG_RTC_DRV_MAX6916 is not set +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +# CONFIG_RTC_DRV_NCT3018Y is not set +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_POLARFIRE_SOC is not set +# CONFIG_RTC_DRV_R7301 is not set +CONFIG_RTC_DRV_R9701=m +# CONFIG_RTC_DRV_RENESAS_RTCA3 is not set +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3029C2=m +# CONFIG_RTC_DRV_RV3029_HWMON is not set +# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_RX4581=m +# CONFIG_RTC_DRV_RX6110 is not set +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +# CONFIG_RTC_DRV_RX8111 is not set +CONFIG_RTC_DRV_RX8581=m +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SD2405AL is not set +# CONFIG_RTC_DRV_SD3078 is not set +# CONFIG_RTC_DRV_SH is not set +CONFIG_RTC_DRV_SPACEMIT_P1=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_NVMEM=y +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192D_COMMON=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +# CONFIG_RTL8XXXU_UNTESTED is not set +CONFIG_RTLBTCOEXIST=m +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTL_CARDS=m +CONFIG_RTW88=m +CONFIG_RTW88_8703B=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8723X=m +CONFIG_RTW88_8812A=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_8814A=m +CONFIG_RTW88_8814AE=m +CONFIG_RTW88_8814AU=m +CONFIG_RTW88_8821A=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_88XXA=m +CONFIG_RTW88_CORE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW88_LEDS=y +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW89=m +CONFIG_RTW89_8851B=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BT=m +CONFIG_RTW89_8852BTE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852B_COMMON=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922A=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_CORE=m +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89_PCI=m +CONFIG_RTW89_USB=m +CONFIG_RT_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED_DEFAULT_DISABLED is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RUST=y +CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_FILE_AS_C_STR=y +CONFIG_RUSTC_HAS_FILE_WITH_NUL=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y +CONFIG_RUSTC_LLVM_VERSION=210108 +CONFIG_RUSTC_SUPPORTS_RISCV=y +CONFIG_RUSTC_VERSION=109500 +CONFIG_RUSTC_VERSION_TEXT="rustc 1.95.0 (59807616e 2026-04-14) (built from a source tarball)" +CONFIG_RUST_BINDGEN_HAS_ZICSR_ZIFENCEI=y +# CONFIG_RUST_BITMAP_HARDENED is not set +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +CONFIG_RUST_IS_AVAILABLE=y +CONFIG_RUST_OVERFLOW_CHECKS=y +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set +CONFIG_RUST_PWM_ABSTRACTIONS=y +# CONFIG_RV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +# CONFIG_RZG2L_THERMAL is not set +# CONFIG_RZG3E_THERMAL is not set +CONFIG_SAMPLES=y +# CONFIG_SAMPLES_RUST is not set +# CONFIG_SAMPLE_ANDROID_BINDERFS is not set +# CONFIG_SAMPLE_AUXDISPLAY is not set +# CONFIG_SAMPLE_CGROUP is not set +# CONFIG_SAMPLE_CHECK_EXEC is not set +# CONFIG_SAMPLE_CONFIGFS is not set +# CONFIG_SAMPLE_CONNECTOR is not set +# CONFIG_SAMPLE_DAMON_MTIER is not set +# CONFIG_SAMPLE_DAMON_PRCL is not set +# CONFIG_SAMPLE_DAMON_WSSE is not set +# CONFIG_SAMPLE_FANOTIFY_ERROR is not set +# CONFIG_SAMPLE_FTRACE_DIRECT is not set +# CONFIG_SAMPLE_FTRACE_DIRECT_MULTI is not set +# CONFIG_SAMPLE_FTRACE_OPS is not set +# CONFIG_SAMPLE_HIDRAW is not set +# CONFIG_SAMPLE_HUNG_TASK is not set +# CONFIG_SAMPLE_KDB is not set +# CONFIG_SAMPLE_KFIFO is not set +# CONFIG_SAMPLE_KOBJECT is not set +# CONFIG_SAMPLE_KPROBES is not set +# CONFIG_SAMPLE_LANDLOCK is not set +# CONFIG_SAMPLE_PIDFD is not set +# CONFIG_SAMPLE_RPMSG_CLIENT is not set +# CONFIG_SAMPLE_SECCOMP is not set +# CONFIG_SAMPLE_TIMER is not set +# CONFIG_SAMPLE_TPS6594_PFSM is not set +# CONFIG_SAMPLE_TRACE_ARRAY is not set +# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set +# CONFIG_SAMPLE_TRACE_EVENTS is not set +# CONFIG_SAMPLE_TRACE_PRINTK is not set +# CONFIG_SAMPLE_TSM_MR is not set +# CONFIG_SAMPLE_UHID is not set +# CONFIG_SAMPLE_VFIO_MDEV_MBOCHS is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set +# CONFIG_SAMPLE_VFIO_MDEV_MTTY is not set +# CONFIG_SAMPLE_VFS is not set +# CONFIG_SAMPLE_WATCHDOG is not set +# CONFIG_SAMPLE_WATCH_QUEUE is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_DWC is not set +CONFIG_SATA_HOST=y +# CONFIG_SATA_INIC162X is not set +CONFIG_SATA_MOBILE_LPM_POLICY=0 +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_ZPODD is not set +CONFIG_SBITMAP=y +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CLASS_EXT is not set +CONFIG_SCHED_HRTICK=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MM_CID=y +# CONFIG_SCHED_PROXY_EXEC is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_SCHED_TRACER=y +CONFIG_SCREEN_INFO=y +CONFIG_SCSI=y +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +CONFIG_SCSI_AACRAID=m +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BNX2_ISCSI=m +# CONFIG_SCSI_BUSLOGIC is not set +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_CXGB3_ISCSI is not set +CONFIG_SCSI_CXGB4_ISCSI=m +# CONFIG_SCSI_DC395x is not set +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_ALUA=y +CONFIG_SCSI_DH_EMC=y +CONFIG_SCSI_DH_HP_SW=y +CONFIG_SCSI_DH_RDAC=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_EFCT is not set +CONFIG_SCSI_ENCLOSURE=m +# CONFIG_SCSI_ESAS2R is not set +CONFIG_SCSI_FC_ATTRS=m +# CONFIG_SCSI_FDOMAIN_PCI is not set +CONFIG_SCSI_HPSA=m +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR_TRACE=y +# CONFIG_SCSI_IPS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPI3MR is not set +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SCSI_NETLINK=y +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +# CONFIG_SCSI_QLOGIC_1280 is not set +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +# CONFIG_SCSI_SNIC is not set +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +CONFIG_SCSI_UFSHCD=m +# CONFIG_SCSI_UFSHCD_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_BSG=y +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +CONFIG_SCSI_UFS_CRYPTO=y +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_HWMON=y +# CONFIG_SCSI_UFS_RENESAS is not set +CONFIG_SCSI_UFS_SPACEMIT=m +CONFIG_SCSI_VIRTIO=y +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y +CONFIG_SDIO_UART=m +# CONFIG_SDR_MAX2175 is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP_FILTER=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY_INFINIBAND=y +# CONFIG_SECURITY_IPE is not set +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +# CONFIG_SECURITY_SELINUX_DEBUG is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ACBEL_FSG032 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM1266 is not set +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +# CONFIG_SENSORS_ADP1050 is not set +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_AHT10 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set +CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_BEL_PFE is not set +CONFIG_SENSORS_BH1770=m +# CONFIG_SENSORS_BPA_RS600 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_CRPS is not set +# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set +CONFIG_SENSORS_DME1737=m +# CONFIG_SENSORS_DPS920AB is not set +# CONFIG_SENSORS_DRIVETEMP is not set +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +# CONFIG_SENSORS_FSP_3Y is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_HTU31 is not set +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_INA209=m +# CONFIG_SENSORS_INA233 is not set +# CONFIG_SENSORS_INA238 is not set +CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL28022 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM25066=m +# CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +# CONFIG_SENSORS_LT3074 is not set +# CONFIG_SENSORS_LT7182S is not set +CONFIG_SENSORS_LTC2945=m +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +# CONFIG_SENSORS_LTC4286 is not set +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX16601 is not set +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +# CONFIG_SENSORS_MAX6620 is not set +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX8688=m +# CONFIG_SENSORS_MC34VR500 is not set +CONFIG_SENSORS_MCP3021=m +# CONFIG_SENSORS_MP2856 is not set +# CONFIG_SENSORS_MP2869 is not set +# CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set +# CONFIG_SENSORS_MP29502 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set +# CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set +# CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set +# CONFIG_SENSORS_MPQ7932 is not set +# CONFIG_SENSORS_MPQ8785 is not set +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set +# CONFIG_SENSORS_NCT7363 is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +# CONFIG_SENSORS_PIM4328 is not set +# CONFIG_SENSORS_PLI1209BC is not set +# CONFIG_SENSORS_PM6764TR is not set +CONFIG_SENSORS_PMBUS=m +# CONFIG_SENSORS_POWERZ is not set +CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PT5161L is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_PXE1610 is not set +# CONFIG_SENSORS_Q54SJ108A2 is not set +# CONFIG_SENSORS_SBTSI is not set +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SCH56XX_COMMON=m +# CONFIG_SENSORS_SFCTEMP is not set +CONFIG_SENSORS_SG2042_MCU=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +# CONFIG_SENSORS_SPD5118 is not set +# CONFIG_SENSORS_STPDDC60 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_TC654 is not set +CONFIG_SENSORS_TC74=m +# CONFIG_SENSORS_TDA38640 is not set +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +# CONFIG_SENSORS_TMP108 is not set +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +# CONFIG_SENSORS_TMP464 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_TPS25990 is not set +CONFIG_SENSORS_TPS40422=m +# CONFIG_SENSORS_TPS53679 is not set +# CONFIG_SENSORS_TPS546D24 is not set +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +# CONFIG_SENSORS_W83773G is not set +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +# CONFIG_SENSORS_XDP710 is not set +# CONFIG_SENSORS_XDPE122 is not set +# CONFIG_SENSORS_XDPE152 is not set +# CONFIG_SENSORS_XGENE is not set +CONFIG_SENSORS_ZL6100=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +# CONFIG_SERIAL_8250_EM is not set +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PCI1XXXX is not set +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_ATMEL is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SPRD is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIO=y +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_GPIO_PS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_SUN4I_PS2 is not set +CONFIG_SFC=m +# CONFIG_SFC_FALCON is not set +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_SFC_SRIOV=y +CONFIG_SFP=m +# CONFIG_SF_PDMA is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SIGNALFD=y +CONFIG_SIGNATURE=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIOX is not set +CONFIG_SKB_DECRYPTED=y +CONFIG_SKB_EXTENSIONS=y +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_OBJ_EXT=y +CONFIG_SLHC=m +# CONFIG_SLICOSS is not set +# CONFIG_SLIMBUS is not set +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_SLIP_SMART=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_SMBFS=m +# CONFIG_SMB_SERVER is not set +CONFIG_SMP=y +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_SM_FTL is not set +CONFIG_SND=m +# CONFIG_SND_AD1889 is not set +CONFIG_SND_ALOOP=m +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CTL_FAST_LOOKUP=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +CONFIG_SND_HDA=m +# CONFIG_SND_HDA_ACPI is not set +# CONFIG_SND_HDA_CODEC_ANALOG is not set +# CONFIG_SND_HDA_CODEC_CA0110 is not set +# CONFIG_SND_HDA_CODEC_CA0132 is not set +# CONFIG_SND_HDA_CODEC_CIRRUS is not set +# CONFIG_SND_HDA_CODEC_CM9825 is not set +# CONFIG_SND_HDA_CODEC_CMEDIA is not set +# CONFIG_SND_HDA_CODEC_CONEXANT is not set +# CONFIG_SND_HDA_CODEC_HDMI is not set +# CONFIG_SND_HDA_CODEC_REALTEK is not set +# CONFIG_SND_HDA_CODEC_SENARYTECH is not set +# CONFIG_SND_HDA_CODEC_SI3054 is not set +# CONFIG_SND_HDA_CODEC_SIGMATEL is not set +# CONFIG_SND_HDA_CODEC_VIA is not set +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_CORE=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# CONFIG_SND_HDA_GENERIC is not set +# CONFIG_SND_HDA_HWDEP is not set +CONFIG_SND_HDA_I915=y +# CONFIG_SND_HDA_INPUT_BEEP is not set +CONFIG_SND_HDA_INTEL=m +# CONFIG_SND_HDA_PATCH_LOADER is not set +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDA_RECONFIG is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_SPI is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_HWDEP=m +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OSSEMUL is not set +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +CONFIG_SND_PCM=m +# CONFIG_SND_PCMTEST is not set +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCXHR is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_RAWMIDI=m +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +CONFIG_SND_SOC=m +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1373 is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_ADI_AXI_I2S is not set +# CONFIG_SND_SOC_ADI_AXI_SPDIF is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_SOC_AW8738 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88081 is not set +# CONFIG_SND_SOC_AW88166 is not set +# CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88399 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CHV3_CODEC is not set +# CONFIG_SND_SOC_CHV3_I2S is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L45_I2C is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS35L56_I2C is not set +# CONFIG_SND_SOC_CS35L56_SPI is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L83 is not set +# CONFIG_SND_SOC_CS42L84 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS48L32 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8323 is not set +# CONFIG_SND_SOC_ES8326 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_ES8375 is not set +# CONFIG_SND_SOC_ES8389 is not set +# CONFIG_SND_SOC_FS210X is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_IDT821034 is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_JH7110_PWMDAC is not set +# CONFIG_SND_SOC_JH7110_TDM is not set +CONFIG_SND_SOC_K1_I2S=m +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98388 is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX98396 is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX98520 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MIKROE_PROTO is not set +# CONFIG_SND_SOC_MSIOF is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8325 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_NTP8835 is not set +# CONFIG_SND_SOC_NTP8918 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1754 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_RCAR is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RT9123 is not set +# CONFIG_SND_SOC_RT9123P is not set +# CONFIG_SND_SOC_RTQ9124 is not set +# CONFIG_SND_SOC_RTQ9128 is not set +CONFIG_SND_SOC_SDCA_OPTIONAL=m +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SH4_FSI is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SMA1303 is not set +# CONFIG_SND_SOC_SMA1307 is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM3515 is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set +# CONFIG_SND_SOC_TAS2781_I2C is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS5805M is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_UDA1342 is not set +# CONFIG_SND_SOC_USB is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731_I2C is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8940 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SOC_ZL38060 is not set +CONFIG_SND_SPI=y +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_DMIC is not set +CONFIG_SND_SUPPORT_OLD_API=y +# CONFIG_SND_TEST_COMPONENT is not set +CONFIG_SND_TIMER=m +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_UTIMER is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTIO is not set +# CONFIG_SND_VIRTUOSO is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_SOC_BUS=y +CONFIG_SOC_RENESAS=y +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_TI is not set +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM is not set +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONY_FF=y +# CONFIG_SOPHGO_CV1800B_DMAMUX is not set +# CONFIG_SOPHGO_CV1800_RTCSYS is not set +CONFIG_SOPHGO_SG2042_MSI=y +CONFIG_SOPHGO_SG2044_TOPSYS=y +CONFIG_SOUND=m +# CONFIG_SOUNDWIRE is not set +CONFIG_SPACEMIT_CCU=y +CONFIG_SPACEMIT_K1_CCU=y +CONFIG_SPACEMIT_K1_EMAC=m +CONFIG_SPACEMIT_K1_TSENSOR=m +CONFIG_SPACEMIT_K3_CCU=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_ATMEL is not set +# CONFIG_SPI_AX88796C is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_CADENCE=m +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_DESIGNWARE=y +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_FSL_QUADSPI=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_POLARFIRE_SOC is not set +# CONFIG_SPI_RSPI is not set +# CONFIG_SPI_RZV2H_RSPI is not set +# CONFIG_SPI_RZV2M_CSI is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SG2044_NOR=m +# CONFIG_SPI_SH_HSPI is not set +# CONFIG_SPI_SH_MSIOF is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI_SN_F_OSPI is not set +CONFIG_SPI_SPACEMIT_K1=m +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_VIRTIO is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +# CONFIG_SPMI is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_ZSTD is not set +CONFIG_SRAM=y +# CONFIG_SSB is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSFDC is not set +# CONFIG_SSIF_IPMI_BMC is not set +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_STACK_TRACER=y +# CONFIG_STAGING is not set +CONFIG_STANDALONE=y +CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set +# CONFIG_STARFIVE_STARLINK_PMU is not set +CONFIG_STARFIVE_WATCHDOG=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +# CONFIG_STM is not set +CONFIG_STMMAC_ETH=m +CONFIG_STMMAC_PCI=m +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STP=m +CONFIG_STREAM_PARSER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +CONFIG_SUN20I_PPU=y +# CONFIG_SUN4I_EMAC is not set +CONFIG_SUN4I_TIMER=y +# CONFIG_SUN50I_DE2_BUS is not set +# CONFIG_SUN50I_H6_PRCM_PPU is not set +# CONFIG_SUN50I_IOMMU is not set +CONFIG_SUN55I_PCK600=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_THERMAL is not set +CONFIG_SUNRPC=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_DEBUG=y +# CONFIG_SUNRPC_DEBUG_TRACE is not set +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUNXI_CCU=y +# CONFIG_SUNXI_RSB is not set +CONFIG_SUNXI_SRAM=y +# CONFIG_SUNXI_WATCHDOG is not set +# CONFIG_SUN_PARTITION is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SWPHY=y +# CONFIG_SW_SYNC is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYN_COOKIES=y +# CONFIG_SYSCON_REBOOT_MODE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +CONFIG_SYSFB_SIMPLEFB=y +CONFIG_SYSFS=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set +CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_REVOCATION_KEYS="" +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_TAP=m +CONFIG_TARGET_CORE=m +CONFIG_TASKSTATS=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_CORE=y +# CONFIG_TCG_TIS_I2C is not set +CONFIG_TCG_TIS_I2C_ATMEL=m +# CONFIG_TCG_TIS_I2C_CR50 is not set +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI=y +# CONFIG_TCG_TIS_SPI_CR50 is not set +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_TCG_TPM=y +# CONFIG_TCG_TPM2_HMAC is not set +# CONFIG_TCG_VTPM_PROXY is not set +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +# CONFIG_TCM_QLA2XXX is not set +CONFIG_TCM_USER2=m +# CONFIG_TCP_AO is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +# CONFIG_TCP_CONG_CDG is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +CONFIG_TCP_SIGPOOL=y +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_TEST_LOCKUP is not set +# CONFIG_TEST_POWER is not set +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TH1520_AON_PROTOCOL=y +CONFIG_TH1520_PM_DOMAINS=m +CONFIG_THEAD_TH1520_MBOX=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_CORE_TESTING is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +# CONFIG_THERMAL_NETLINK is not set +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THREAD_SIZE_ORDER=2 +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_THUNDER_NIC_VF=m +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIMERFD=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TIME_NS=y +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_SHARP_MEMORY is not set +CONFIG_TIPC=m +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_TI_FPC202 is not set +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_XATTR=y +CONFIG_TOOLCHAIN_HAS_V=y +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO=y +CONFIG_TOOLCHAIN_HAS_ZABHA=y +CONFIG_TOOLCHAIN_HAS_ZACAS=y +CONFIG_TOOLCHAIN_HAS_ZBA=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_TOOLCHAIN_HAS_ZBC=y +CONFIG_TOOLCHAIN_HAS_ZBKB=y +CONFIG_TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y +CONFIG_TRACEPOINTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_GPU_MEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_TRUSTED_KEYS=y +CONFIG_TRUSTED_KEYS_TPM=y +# CONFIG_TSNEP is not set +CONFIG_TTY=y +CONFIG_TTY_PRINTK=m +CONFIG_TTY_PRINTK_LEVEL=6 +CONFIG_TUN=m +CONFIG_TUNE_GENERIC=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_TXGBE=m +# CONFIG_TXGBEVF is not set +CONFIG_TYPEC=m +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_DP_ALTMODE=m +# CONFIG_TYPEC_FUSB302 is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_IT5205 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_PS883X is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set +# CONFIG_TYPEC_MUX_TUSB1046 is not set +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TBT_ALTMODE is not set +CONFIG_TYPEC_TCPCI=m +# CONFIG_TYPEC_TCPCI_MAXIM is not set +CONFIG_TYPEC_TCPM=m +# CONFIG_TYPEC_TPS6598X is not set +CONFIG_TYPEC_UCSI=m +# CONFIG_TYPEC_WUSB3801 is not set +CONFIG_UACCE=m +# CONFIG_UAPI_HEADER_TEST is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_UBSAN is not set +# CONFIG_UCLAMP_TASK is not set +CONFIG_UCS2_STRING=y +# CONFIG_UCSI_ACPI is not set +# CONFIG_UCSI_CCG is not set +# CONFIG_UCSI_STM32G0 is not set +CONFIG_UDF_FS=m +# CONFIG_UDMABUF is not set +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UFS_FS is not set +CONFIG_UHID=m +CONFIG_UIO=m +CONFIG_UIO_AEC=m +CONFIG_UIO_CIF=m +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_SERCOS3=m +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNION_FIND=y +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX_DIAG=m +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y +CONFIG_USB=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +CONFIG_USB4_NET=m +# CONFIG_USBIP_CORE is not set +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +# CONFIG_USB_AIRSPY is not set +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_BELKIN=y +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_CATC=m +# CONFIG_USB_CDNS_SUPPORT is not set +CONFIG_USB_CHAOSKEY=m +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_COMMON=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DWC2 is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_GENERIC_PLAT=m +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_PCI=m +# CONFIG_USB_DWC3_ULPI is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_HSIC_USB3503=m +# CONFIG_USB_HSIC_USB4604 is not set +CONFIG_USB_HSO=m +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_IPHETH=m +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1760 is not set +CONFIG_USB_KAWETH=m +CONFIG_USB_KC2190=y +# CONFIG_USB_KEENE is not set +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_LJCA is not set +# CONFIG_USB_MA901 is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y +# CONFIG_USB_MR800 is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_ONBOARD_DEV=m +# CONFIG_USB_ONBOARD_DEV_USB5744 is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set +CONFIG_USB_PEGASUS=m +CONFIG_USB_PRINTER=m +# CONFIG_USB_PWC is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +# CONFIG_USB_S2255 is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +# CONFIG_USB_SERIAL_UPD78F0730 is not set +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_WWAN=m +# CONFIG_USB_SERIAL_XR is not set +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEST is not set +CONFIG_USB_TMC=m +# CONFIG_USB_TRANCEVIBRATOR is not set +CONFIG_USB_UAS=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_USBNET=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_XHCI_RCAR=y +# CONFIG_USB_XHCI_SIDEBAND is not set +# CONFIG_USB_YUREX is not set +CONFIG_USERFAULTFD=y +# CONFIG_USERIO is not set +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USER_NS=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_UTS_NS=y +CONFIG_UVC_COMMON=m +CONFIG_V4L2_ASYNC=m +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L2_FWNODE=m +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +CONFIG_VALIDATE_FS_PARSER=y +# CONFIG_VCPU_STALL_DETECTOR is not set +# CONFIG_VDPA is not set +CONFIG_VDSO_GETRANDOM=y +CONFIG_VETH=m +CONFIG_VFAT_FS=y +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +CONFIG_VFIO_GROUP=y +CONFIG_VFIO_NOIOMMU=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=64 +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST_VSOCK=m +CONFIG_VIDEO=y +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_ALVIUM_CSI2 is not set +# CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +# CONFIG_VIDEO_CADENCE_CSI2TX is not set +CONFIG_VIDEO_CAMERA_LENS=y +CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX25840 is not set +CONFIG_VIDEO_DEV=m +# CONFIG_VIDEO_DS90UB913 is not set +# CONFIG_VIDEO_DS90UB953 is not set +# CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9719 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_ET8EK8 is not set +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC0310 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_HI846 is not set +# CONFIG_VIDEO_HI847 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX296 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_IMX415 is not set +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# CONFIG_VIDEO_LT6911UXE is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_OG01A1B is not set +# CONFIG_VIDEO_OG0VE1B is not set +# CONFIG_VIDEO_OV01A10 is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV02C10 is not set +# CONFIG_VIDEO_OV02E10 is not set +# CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV08X40 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_OV13B10 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV2735 is not set +# CONFIG_VIDEO_OV2740 is not set +# CONFIG_VIDEO_OV4689 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV6211 is not set +# CONFIG_VIDEO_OV64A40 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8858 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV9734 is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_RP1_CFE is not set +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_STK1160 is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THP7312 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VD55G1 is not set +# CONFIG_VIDEO_VD56G3 is not set +# CONFIG_VIDEO_VGXY61 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VIRTIO_FS=y +CONFIG_VIRTIO_INPUT=y +# CONFIG_VIRTIO_MEM is not set +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +# CONFIG_VIRTIO_PMEM is not set +CONFIG_VIRTIO_RTC=m +CONFIG_VIRTIO_RTC_CLASS=y +CONFIG_VIRTIO_RTC_PTP=y +# CONFIG_VIRTIO_VFIO_PCI is not set +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_VIRTUALIZATION=y +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_VIRT_DRIVERS=y +# CONFIG_VIRT_WIFI is not set +CONFIG_VIRT_XFER_TO_GUEST_WORK=y +CONFIG_VITESSE_PHY=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_PFN=y +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_VMXNET3 is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKMON=m +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VXFS_FS is not set +CONFIG_VXLAN=m +# CONFIG_W1 is not set +CONFIG_WAN=y +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_WANXL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +# CONFIG_WATCH_QUEUE is not set +# CONFIG_WCN36XX is not set +# CONFIG_WDAT_WDT is not set +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +# CONFIG_WFX is not set +# CONFIG_WIL6210 is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIRELESS=y +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WPCM450_SOC is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WQ_WATCHDOG=y +# CONFIG_WWAN is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_X25 is not set +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_XARRAY_MULTI=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XFRM=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_IPCOMP=m +# CONFIG_XFRM_IPTFS is not set +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_USER=m +CONFIG_XFS_BTREE_IN_MEM=y +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_DRAIN_INTENTS=y +CONFIG_XFS_FS=y +CONFIG_XFS_LIVE_HOOKS=y +CONFIG_XFS_MEMORY_BUFS=y +CONFIG_XFS_ONLINE_REPAIR=y +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_XFS_ONLINE_SCRUB_STATS=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +# CONFIG_XFS_SUPPORT_ASCII_CI is not set +# CONFIG_XFS_SUPPORT_V4 is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_XILINX_INTC is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_VCU is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_XDMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_RISCV=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_XZ_DEC_X86=y +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZERO_CALL_USED_REGS is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +CONFIG_ZISOFS=y +# CONFIG_ZL3073X_I2C is not set +# CONFIG_ZL3073X_SPI is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZONEFS_FS is not set +CONFIG_ZONE_DEVICE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZRAM=m +# CONFIG_ZRAM_BACKEND_842 is not set +# CONFIG_ZRAM_BACKEND_DEFLATE is not set +CONFIG_ZRAM_BACKEND_FORCE_LZO=y +# CONFIG_ZRAM_BACKEND_LZ4 is not set +# CONFIG_ZRAM_BACKEND_LZ4HC is not set +CONFIG_ZRAM_BACKEND_LZO=y +# CONFIG_ZRAM_BACKEND_ZSTD is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC=y +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +CONFIG_ZSMALLOC_STAT=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lz4" +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set diff --git a/SPECS/linux-lts/config.x86_64 b/SPECS/linux-lts/config.x86_64 index d18be35c7e..c228f70942 100644 --- a/SPECS/linux-lts/config.x86_64 +++ b/SPECS/linux-lts/config.x86_64 @@ -1,4826 +1,2712 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_WATCH_QUEUE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 -CONFIG_BPF_JIT=y -CONFIG_BPF_JIT_ALWAYS_ON=y -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_SCHED_CORE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_PSI=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_NUMA_BALANCING=y -CONFIG_MEMCG=y -CONFIG_MEMCG_V1=y -CONFIG_BLK_CGROUP=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_DMEM=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_MISC=y -CONFIG_NAMESPACES=y -CONFIG_USER_NS=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BOOT_CONFIG=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -CONFIG_PROFILING=y -CONFIG_KEXEC=y -CONFIG_KEXEC_JUMP=y -CONFIG_KEXEC_HANDOVER=y -CONFIG_SMP=y -CONFIG_X86_NUMACHIP=y -CONFIG_X86_INTEL_LPSS=y -CONFIG_X86_AMD_PLATFORM_DEVICE=y -CONFIG_IOSF_MBI_DEBUG=y -CONFIG_HYPERVISOR_GUEST=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_XEN=y -CONFIG_XEN_PVH=y -CONFIG_JAILHOUSE_GUEST=y -CONFIG_INTEL_TDX_GUEST=y -CONFIG_PROCESSOR_SELECT=y -CONFIG_GART_IOMMU=y -CONFIG_NR_CPUS=256 -CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_PERF_EVENTS_AMD_POWER=m -CONFIG_PERF_EVENTS_AMD_UNCORE=m -CONFIG_PERF_EVENTS_AMD_BRS=y -CONFIG_X86_MSR=m -CONFIG_X86_CPUID=m -CONFIG_NUMA=y -CONFIG_ARCH_MEMORY_PROBE=y -CONFIG_X86_PMEM_LEGACY=y -CONFIG_X86_CHECK_BIOS_CORRUPTION=y -CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 -CONFIG_X86_SGX=y -CONFIG_EFI=y -CONFIG_EFI_STUB=y -CONFIG_EFI_MIXED=y -CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_LEGACY_VSYSCALL_NONE=y -CONFIG_LIVEPATCH=y -CONFIG_HIBERNATION=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_DEBUG=y -CONFIG_PM_ADVANCED_DEBUG=y -CONFIG_PM_TRACE_RTC=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ACPI_FPDT=y -CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_60XX_WDT=m +CONFIG_64BIT=y +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6PACK=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_842_COMPRESS=m +CONFIG_842_DECOMPRESS=m +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +CONFIG_ABP060MG=m +CONFIG_AC97_BUS=m +CONFIG_ACCESSIBILITY=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_ACERHDF=m +CONFIG_ACER_WIRELESS=m +CONFIG_ACER_WMI=m +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI=y CONFIG_ACPI_AC=m -CONFIG_ACPI_BATTERY=m -CONFIG_ACPI_TAD=m -CONFIG_ACPI_DOCK=y -CONFIG_ACPI_IPMI=m -CONFIG_ACPI_PROCESSOR_AGGREGATOR=m -# CONFIG_ACPI_DEBUG is not set -CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_HOTPLUG_MEMORY=y -CONFIG_ACPI_SBS=m -CONFIG_ACPI_BGRT=y -CONFIG_ACPI_NFIT=m +CONFIG_ACPI_ADXL=y +CONFIG_ACPI_ALS=m CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_EINJ_CXL=y +# CONFIG_ACPI_APEI_ERST_DEBUG is not set CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_BATTERY=m +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CMPC=m +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_CUSTOM_DSDT_FILE="" +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_DOCK=y CONFIG_ACPI_DPTF=y +CONFIG_ACPI_EC=y +CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_EXTLOG=m -CONFIG_ACPI_CONFIGFS=m -CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_FAN=y CONFIG_ACPI_FFH=y -CONFIG_TPS68470_PMIC_OPREGION=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_X86_PCC_CPUFREQ=y -CONFIG_X86_ACPI_CPUFREQ=y -CONFIG_X86_POWERNOW_K8=y -CONFIG_X86_AMD_FREQ_SENSITIVITY=m -CONFIG_X86_SPEEDSTEP_CENTRINO=y -CONFIG_X86_P4_CLOCKMOD=m -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_HALTPOLL_CPUIDLE=m -CONFIG_INTEL_IDLE=y -CONFIG_IA32_EMULATION=y -CONFIG_X86_X32_ABI=y -CONFIG_KVM=m -CONFIG_KVM_WERROR=y -CONFIG_KVM_INTEL=m -CONFIG_X86_SGX_KVM=y -CONFIG_KVM_AMD=m -CONFIG_KVM_XEN=y -CONFIG_JUMP_LABEL=y -CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_MODULE_COMPRESS=y -CONFIG_MODULE_COMPRESS_ZSTD=y -CONFIG_MODULE_DECOMPRESS=y -CONFIG_BLK_DEV_ZONED=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BLK_WBT=y -CONFIG_BLK_CGROUP_FC_APPID=y -CONFIG_BLK_CGROUP_IOCOST=y -CONFIG_BLK_CGROUP_IOPRIO=y -CONFIG_BLK_INLINE_ENCRYPTION=y -CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_AIX_PARTITION=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_KARMA_PARTITION=y -CONFIG_SYSV68_PARTITION=y -CONFIG_CMDLINE_PARTITION=y -CONFIG_MQ_IOSCHED_KYBER=m -# CONFIG_BFQ_GROUP_IOSCHED is not set -CONFIG_BINFMT_MISC=m -CONFIG_ZSWAP=y -CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_SLAB_FREELIST_HARDENED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTREMOVE=y -CONFIG_KSM=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_MEMORY_FAILURE=y -CONFIG_HWPOISON_INJECT=m -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CMA_SYSFS=y -CONFIG_CMA_AREAS=7 -CONFIG_MEM_SOFT_DIRTY=y -CONFIG_IDLE_PAGE_TRACKING=y -CONFIG_ZONE_DEVICE=y -CONFIG_ANON_VMA_NAME=y -CONFIG_USERFAULTFD=y -CONFIG_LRU_GEN=y -CONFIG_DAMON=y -CONFIG_DAMON_RECLAIM=y -CONFIG_DAMON_LRU_SORT=y -CONFIG_DAMON_STAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX_DIAG=m -CONFIG_XFRM_USER=m -CONFIG_XFRM_USER_COMPAT=m -CONFIG_XFRM_INTERFACE=m -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=m -CONFIG_XDP_SOCKETS=y -CONFIG_XDP_SOCKETS_DIAG=m -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_NET_IPVTI=m -CONFIG_NET_FOU_IP_TUNNELS=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_DIAG=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_CDG=m -CONFIG_TCP_CONG_BBR=m -CONFIG_TCP_AO=y -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_ILA=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_GRE=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_MPTCP=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE_NETFILTER=m -CONFIG_NETFILTER_NETLINK_HOOK=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NF_CT_NETLINK_HELPER=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_CONNLIMIT=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_NAT=m -CONFIG_NFT_TUNNEL=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NFT_FIB_INET=m -CONFIG_NFT_XFRM=m -CONFIG_NFT_SOCKET=m -CONFIG_NFT_OSF=m -CONFIG_NFT_TPROXY=m -CONFIG_NFT_SYNPROXY=m -CONFIG_NFT_DUP_NETDEV=m -CONFIG_NFT_FWD_NETDEV=m -CONFIG_NFT_FIB_NETDEV=m -CONFIG_NFT_REJECT_NETDEV=m -CONFIG_NF_FLOW_TABLE_INET=m -CONFIG_NF_FLOW_TABLE=m -CONFIG_NF_FLOW_TABLE_PROCFS=y -CONFIG_NETFILTER_XTABLES_COMPAT=y -CONFIG_NETFILTER_XTABLES_LEGACY=y -CONFIG_NETFILTER_XT_SET=m -CONFIG_NETFILTER_XT_TARGET_AUDIT=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_CT=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_SET=m -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_IPMAC=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_MH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_TWOS=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_PE_SIP=m -CONFIG_NFT_DUP_IPV4=m -CONFIG_NFT_FIB_IPV4=m -CONFIG_NF_TABLES_ARP=y -CONFIG_NF_LOG_ARP=m -CONFIG_NF_LOG_IPV4=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_SECURITY=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_SECURITY=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_META=m -CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_CONNTRACK_BRIDGE=m -CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_SCTP=m -CONFIG_RDS=m -CONFIG_RDS_RDMA=m -CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_TIPC_MEDIA_IB=y -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_L2TP=m -CONFIG_L2TP_DEBUGFS=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_BRIDGE_MRP=y -CONFIG_BRIDGE_CFM=y -CONFIG_NET_DSA=m -CONFIG_NET_DSA_TAG_RTL4_A=m -CONFIG_NET_DSA_TAG_RTL8_4=m -CONFIG_NET_DSA_TAG_RZN1_A5PSW=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_6LOWPAN=m -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m -CONFIG_IEEE802154=m -CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y -CONFIG_IEEE802154_6LOWPAN=m -CONFIG_MAC802154=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_SKBPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_CAKE=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_FQ_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_SCH_ETS=m -CONFIG_NET_SCH_DUALPI2=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_CANID=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_EMATCH_IPT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_MPLS=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_CONNMARK=m -CONFIG_NET_ACT_CTINFO=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_IFE=m -CONFIG_NET_ACT_TUNNEL_KEY=m -CONFIG_NET_ACT_CT=m -CONFIG_NET_ACT_GATE=m -CONFIG_NET_IFE_SKBMARK=m -CONFIG_NET_IFE_SKBPRIO=m -CONFIG_NET_IFE_SKBTCINDEX=m -CONFIG_DNS_RESOLVER=y -CONFIG_BATMAN_ADV=m -# CONFIG_BATMAN_ADV_BATMAN_V is not set -CONFIG_OPENVSWITCH=m -CONFIG_VSOCKETS=m -CONFIG_VMWARE_VMCI_VSOCKETS=m -CONFIG_VIRTIO_VSOCKETS=m -CONFIG_NETLINK_DIAG=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m -CONFIG_HSR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_NET_NCSI=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_NET_PKTGEN=m -CONFIG_NET_DROP_MONITOR=m -CONFIG_HAMRADIO=y -CONFIG_AX25=m -CONFIG_NETROM=m -CONFIG_ROSE=m -CONFIG_MKISS=m -CONFIG_6PACK=m -CONFIG_BPQETHER=m -CONFIG_BAYCOM_SER_FDX=m -CONFIG_BAYCOM_SER_HDX=m -CONFIG_BAYCOM_PAR=m -CONFIG_YAM=m -CONFIG_CAN=m -CONFIG_CAN_J1939=m -CONFIG_CAN_ISOTP=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_6LOWPAN=m -CONFIG_BT_MSFTEXT=y -CONFIG_BT_AOSPEXT=y -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTUSB_MTK=y -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_NOKIA=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_INTEL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_RTL=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_AG6XX=y -CONFIG_BT_HCIUART_MRVL=y -CONFIG_BT_HCIUART_AML=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBCM4377=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIDTL1=m -CONFIG_BT_HCIBT3C=m -CONFIG_BT_HCIBLUECARD=m -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -CONFIG_BT_ATH3K=m -CONFIG_BT_MTKSDIO=m -CONFIG_BT_MTKUART=m -CONFIG_BT_VIRTIO=m -CONFIG_BT_NXPUART=m -CONFIG_BT_INTEL_PCIE=m -CONFIG_AF_RXRPC_IPV6=y -CONFIG_RXGK=y -CONFIG_AF_KCM=m -CONFIG_MCTP=y -CONFIG_CFG80211=m -CONFIG_CFG80211_DEBUGFS=y -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=m -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_DEBUGFS=y -CONFIG_MAC80211_MESSAGE_TRACING=y -CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_NET_9P=m -CONFIG_NET_9P_VIRTIO=m -CONFIG_NET_9P_XEN=m -CONFIG_NET_9P_USBG=m -CONFIG_NET_9P_RDMA=m -CONFIG_CAIF=m -CONFIG_CAIF_USB=m -CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -CONFIG_NFC=m -CONFIG_NFC_DIGITAL=m -CONFIG_NFC_NCI=m -CONFIG_NFC_NCI_SPI=m -CONFIG_NFC_NCI_UART=m -CONFIG_NFC_HCI=m -CONFIG_NFC_SHDLC=y -CONFIG_NFC_TRF7970A=m -CONFIG_NFC_MEI_PHY=m -CONFIG_NFC_SIM=m -CONFIG_NFC_PORT100=m -CONFIG_NFC_VIRTUAL_NCI=m -CONFIG_NFC_FDP=m -CONFIG_NFC_FDP_I2C=m -CONFIG_NFC_PN544_I2C=m -CONFIG_NFC_PN544_MEI=m -CONFIG_NFC_PN533_USB=m -CONFIG_NFC_PN533_I2C=m -CONFIG_NFC_PN532_UART=m -CONFIG_NFC_MICROREAD_I2C=m -CONFIG_NFC_MICROREAD_MEI=m -CONFIG_NFC_MRVL_USB=m -CONFIG_NFC_MRVL_UART=m -CONFIG_NFC_MRVL_I2C=m -CONFIG_NFC_MRVL_SPI=m -CONFIG_NFC_ST21NFCA_I2C=m -CONFIG_NFC_ST_NCI_I2C=m -CONFIG_NFC_ST_NCI_SPI=m -CONFIG_NFC_NXP_NCI=m -CONFIG_NFC_NXP_NCI_I2C=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_NFC_S3FWRN82_UART=m -CONFIG_NFC_ST95HF=m -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIE_DPC=y -CONFIG_PCIE_PTM=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_STUB=m -CONFIG_XEN_PCIDEV_FRONTEND=m -CONFIG_PCI_NPEM=y -CONFIG_PCIE_TPH=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_HOTPLUG_PCI_ACPI_IBM=m -CONFIG_HOTPLUG_PCI_CPCI=y -CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m -CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m -CONFIG_HOTPLUG_PCI_OCTEONEP=y -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_VMD=m -CONFIG_PCI_PWRCTRL_SLOT=m -CONFIG_CXL_BUS=m -CONFIG_PCCARD=m -CONFIG_YENTA=m -CONFIG_PD6729=m -CONFIG_I82092=m -CONFIG_RAPIDIO=y -CONFIG_RAPIDIO_TSI721=m -CONFIG_RAPIDIO_DMA_ENGINE=y -CONFIG_RAPIDIO_ENUM_BASIC=m -CONFIG_RAPIDIO_CHMAN=m -CONFIG_RAPIDIO_MPORT_CDEV=m -CONFIG_RAPIDIO_CPS_XX=m -CONFIG_RAPIDIO_CPS_GEN2=m -CONFIG_RAPIDIO_RXS_GEN3=m -CONFIG_UEVENT_HELPER=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DEVTMPFS_SAFE=y -# CONFIG_STANDALONE is not set -CONFIG_FW_LOADER_COMPRESS=y -CONFIG_FW_LOADER_COMPRESS_ZSTD=y -CONFIG_MHI_BUS_PCI_GENERIC=m -CONFIG_MHI_BUS_EP=m -CONFIG_CONNECTOR=y -CONFIG_EDD=y -CONFIG_EDD_OFF=y -CONFIG_DMI_SYSFS=m -CONFIG_ISCSI_IBFT=m -CONFIG_FW_CFG_SYSFS=m -CONFIG_EFI_VARS_PSTORE=m -CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y -CONFIG_EFI_BOOTLOADER_CONTROL=m -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_FWCTL=y -CONFIG_FWCTL_MLX5=m -CONFIG_FWCTL_PDS=m -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_GNSS_SIRF_SERIAL=m -CONFIG_GNSS_UBX_SERIAL=m -CONFIG_GNSS_USB=m -CONFIG_MTD=m -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_REDBOOT_PARTS=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_BLOCK_RO=m -CONFIG_FTL=m -CONFIG_NFTL=m -CONFIG_NFTL_RW=y -CONFIG_INFTL=m -CONFIG_RFD_FTL=m -CONFIG_SSFDC=m -CONFIG_SM_FTL=m -CONFIG_MTD_OOPS=m -CONFIG_MTD_SWAP=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_ROM=m -CONFIG_MTD_ABSENT=m -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_PHYSMAP_GPIO_ADDR=y -CONFIG_MTD_SBC_GXX=m -CONFIG_MTD_AMD76XROM=m -CONFIG_MTD_ICHXROM=m -CONFIG_MTD_ESB2ROM=m -CONFIG_MTD_CK804XROM=m -CONFIG_MTD_SCB2_FLASH=m -CONFIG_MTD_NETtel=m -CONFIG_MTD_L440GX=m -CONFIG_MTD_PCI=m -CONFIG_MTD_PCMCIA=m -CONFIG_MTD_PLATRAM=m -CONFIG_MTD_PMC551=m -CONFIG_MTD_DATAFLASH=m -CONFIG_MTD_DATAFLASH_OTP=y -CONFIG_MTD_MCHP23K256=m -CONFIG_MTD_MCHP48L640=m -CONFIG_MTD_SST25L=m -CONFIG_MTD_SLRAM=m -CONFIG_MTD_PHRAM=m -CONFIG_MTD_MTDRAM=m -CONFIG_MTD_BLOCK2MTD=m -CONFIG_MTD_INTEL_DG=m -CONFIG_MTD_DOCG3=m -CONFIG_MTD_ONENAND=m -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_ONENAND_GENERIC=m -CONFIG_MTD_ONENAND_2X_PROGRAM=y -CONFIG_MTD_RAW_NAND=m -CONFIG_MTD_NAND_DENALI_PCI=m -CONFIG_MTD_NAND_CAFE=m -CONFIG_MTD_NAND_MXIC=m -CONFIG_MTD_NAND_GPIO=m -CONFIG_MTD_NAND_PLATFORM=m -CONFIG_MTD_NAND_ARASAN=m -CONFIG_MTD_NAND_NANDSIM=m -CONFIG_MTD_NAND_RICOH=m -CONFIG_MTD_NAND_DISKONCHIP=m -CONFIG_MTD_SPI_NAND=m -CONFIG_MTD_LPDDR=m -CONFIG_MTD_UBI=m -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_GLUEBI=m -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_HYPERBUS=m -CONFIG_PARPORT=m -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_SERIAL=m -CONFIG_PARPORT_PC_FIFO=y -CONFIG_PARPORT_PC_PCMCIA=m -CONFIG_PARPORT_1284=y -# CONFIG_PNP_DEBUG_MESSAGES is not set -CONFIG_BLK_DEV_NULL_BLK=m -CONFIG_BLK_DEV_FD=m -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m -CONFIG_ZRAM=m -CONFIG_ZRAM_BACKEND_LZ4=y -CONFIG_ZRAM_BACKEND_LZ4HC=y -CONFIG_ZRAM_BACKEND_ZSTD=y -CONFIG_ZRAM_BACKEND_DEFLATE=y -CONFIG_ZRAM_BACKEND_842=y -CONFIG_ZRAM_BACKEND_LZO=y -CONFIG_ZRAM_MULTI_COMP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_DRBD=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_ATA_OVER_ETH=m -CONFIG_XEN_BLKDEV_BACKEND=m -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_RBD=m -CONFIG_BLK_DEV_RNBD_CLIENT=m -CONFIG_BLK_DEV_RNBD_SERVER=m -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_HWMON=y -CONFIG_NVME_RDMA=m -CONFIG_NVME_FC=m -CONFIG_NVME_TCP=m -CONFIG_NVME_TCP_TLS=y -CONFIG_NVME_HOST_AUTH=y -CONFIG_NVME_TARGET=m -CONFIG_NVME_TARGET_DEBUGFS=y -CONFIG_NVME_TARGET_LOOP=m -CONFIG_NVME_TARGET_RDMA=m -CONFIG_NVME_TARGET_FC=m -CONFIG_NVME_TARGET_FCLOOP=m -CONFIG_NVME_TARGET_TCP=m -CONFIG_NVME_TARGET_TCP_TLS=y -CONFIG_AD525X_DPOT=m -CONFIG_AD525X_DPOT_I2C=m -CONFIG_AD525X_DPOT_SPI=m -CONFIG_DUMMY_IRQ=m -CONFIG_IBM_ASM=m -CONFIG_PHANTOM=m -CONFIG_RPMB=m -CONFIG_TI_FPC202=m -CONFIG_ICS932S401=m -CONFIG_ENCLOSURE_SERVICES=m -CONFIG_SMPRO_ERRMON=m -CONFIG_SMPRO_MISC=m -CONFIG_HP_ILO=m -CONFIG_APDS9802ALS=m -CONFIG_ISL29003=m -CONFIG_ISL29020=m -CONFIG_SENSORS_TSL2550=m -CONFIG_SENSORS_BH1770=m -CONFIG_SENSORS_APDS990X=m -CONFIG_HMC6352=m -CONFIG_DS1682=m -CONFIG_VMWARE_BALLOON=m -CONFIG_LATTICE_ECP3_CONFIG=m -CONFIG_SRAM=y -CONFIG_DW_XDATA_PCIE=m -CONFIG_XILINX_SDFEC=m -CONFIG_NTSYNC=m -CONFIG_NSM=m -CONFIG_C2PORT=m -CONFIG_C2PORT_DURAMAR_2150=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_EEPROM_MAX6875=m -CONFIG_EEPROM_93XX46=m -CONFIG_EEPROM_IDT_89HPESX=m -CONFIG_EEPROM_EE1004=m -CONFIG_SENSORS_LIS3_I2C=m -CONFIG_INTEL_MEI=m -CONFIG_INTEL_MEI_GSC=m -CONFIG_INTEL_MEI_VSC_HW=m -CONFIG_INTEL_MEI_VSC=m -CONFIG_INTEL_MEI_GSC_PROXY=m -CONFIG_VMWARE_VMCI=m -CONFIG_GENWQE=m -CONFIG_BCM_VK=m -CONFIG_BCM_VK_TTY=y -CONFIG_MISC_ALCOR_PCI=m -CONFIG_MISC_RTSX_PCI=m -CONFIG_MISC_RTSX_USB=m -CONFIG_UACCE=m -CONFIG_PVPANIC=y -CONFIG_PVPANIC_MMIO=m -CONFIG_PVPANIC_PCI=m -CONFIG_GP_PCI1XXXX=m -CONFIG_KEBA_CP500=m -CONFIG_KEBA_LAN9252=m -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_ENCLOSURE=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_SAS_ATA=y -CONFIG_ISCSI_TCP=m -CONFIG_SCSI_CXGB3_ISCSI=m -CONFIG_SCSI_CXGB4_ISCSI=m -CONFIG_SCSI_BNX2_ISCSI=m -CONFIG_SCSI_BNX2X_FCOE=m -CONFIG_BE2ISCSI=m -CONFIG_BLK_DEV_3W_XXXX_RAID=m -CONFIG_SCSI_HPSA=m -CONFIG_SCSI_3W_9XXX=m -CONFIG_SCSI_3W_SAS=m -CONFIG_SCSI_ACARD=m -CONFIG_SCSI_AACRAID=m -CONFIG_SCSI_AIC7XXX=m -CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 -# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -CONFIG_SCSI_AIC79XX=m -# CONFIG_AIC79XX_DEBUG_ENABLE is not set -CONFIG_SCSI_AIC94XX=m -# CONFIG_AIC94XX_DEBUG is not set -CONFIG_SCSI_MVSAS=m -# CONFIG_SCSI_MVSAS_DEBUG is not set -CONFIG_SCSI_MVUMI=m -CONFIG_SCSI_ADVANSYS=m -CONFIG_SCSI_ARCMSR=m -CONFIG_SCSI_ESAS2R=m -CONFIG_MEGARAID_NEWGEN=y -CONFIG_MEGARAID_MM=m -CONFIG_MEGARAID_MAILBOX=m -CONFIG_MEGARAID_LEGACY=m -CONFIG_MEGARAID_SAS=m -CONFIG_SCSI_MPT2SAS=m -CONFIG_SCSI_MPI3MR=m -CONFIG_SCSI_SMARTPQI=m -CONFIG_SCSI_HPTIOP=m -CONFIG_SCSI_BUSLOGIC=m -CONFIG_SCSI_FLASHPOINT=y -CONFIG_SCSI_MYRB=m -CONFIG_SCSI_MYRS=m -CONFIG_VMWARE_PVSCSI=m -CONFIG_XEN_SCSI_FRONTEND=m -CONFIG_LIBFC=m -CONFIG_LIBFCOE=m -CONFIG_FCOE=m -CONFIG_FCOE_FNIC=m -CONFIG_SCSI_SNIC=m -CONFIG_SCSI_DMX3191D=m -CONFIG_SCSI_FDOMAIN_PCI=m -CONFIG_SCSI_ISCI=m -CONFIG_SCSI_IPS=m -CONFIG_SCSI_INITIO=m -CONFIG_SCSI_INIA100=m -CONFIG_SCSI_PPA=m -CONFIG_SCSI_IMM=m -CONFIG_SCSI_STEX=m -CONFIG_SCSI_SYM53C8XX_2=m -CONFIG_SCSI_IPR=m -CONFIG_SCSI_QLOGIC_1280=m -CONFIG_SCSI_QLA_FC=m -CONFIG_TCM_QLA2XXX=m -CONFIG_SCSI_QLA_ISCSI=m -CONFIG_QEDI=m -CONFIG_QEDF=m -CONFIG_SCSI_LPFC=m -CONFIG_SCSI_EFCT=m -CONFIG_SCSI_DC395x=m -CONFIG_SCSI_AM53C974=m -CONFIG_SCSI_WD719X=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_PMCRAID=m -CONFIG_SCSI_PM8001=m -CONFIG_SCSI_BFA_FC=m -CONFIG_SCSI_VIRTIO=m -CONFIG_SCSI_CHELSIO_FCOE=m -CONFIG_SCSI_LOWLEVEL_PCMCIA=y -CONFIG_PCMCIA_AHA152X=m -CONFIG_PCMCIA_FDOMAIN=m -CONFIG_PCMCIA_QLOGIC=m -CONFIG_PCMCIA_SYM53C500=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=m -CONFIG_SCSI_DH_HP_SW=m -CONFIG_SCSI_DH_EMC=m -CONFIG_SCSI_DH_ALUA=m -CONFIG_ATA=y -CONFIG_SATA_ZPODD=y -CONFIG_SATA_AHCI=m -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=m -CONFIG_AHCI_DWC=m -CONFIG_SATA_INIC162X=m -CONFIG_SATA_ACARD_AHCI=m -CONFIG_SATA_SIL24=m -CONFIG_PDC_ADMA=m -CONFIG_SATA_QSTOR=m -CONFIG_SATA_SX4=m -CONFIG_ATA_PIIX=y -CONFIG_SATA_DWC=m -CONFIG_SATA_MV=m -CONFIG_SATA_NV=m -CONFIG_SATA_PROMISE=m -CONFIG_SATA_SIL=m -CONFIG_SATA_SIS=m -CONFIG_SATA_SVW=m -CONFIG_SATA_ULI=m -CONFIG_SATA_VIA=m -CONFIG_SATA_VITESSE=m -CONFIG_PATA_ALI=m -CONFIG_PATA_AMD=m -CONFIG_PATA_ARTOP=m -CONFIG_PATA_ATIIXP=m -CONFIG_PATA_ATP867X=m -CONFIG_PATA_CMD64X=m -CONFIG_PATA_CYPRESS=m -CONFIG_PATA_EFAR=m -CONFIG_PATA_HPT366=m -CONFIG_PATA_HPT37X=m -CONFIG_PATA_HPT3X2N=m -CONFIG_PATA_HPT3X3=m -CONFIG_PATA_IT8213=m -CONFIG_PATA_IT821X=m -CONFIG_PATA_JMICRON=m -CONFIG_PATA_MARVELL=m -CONFIG_PATA_NETCELL=m -CONFIG_PATA_NINJA32=m -CONFIG_PATA_NS87415=m -CONFIG_PATA_OLDPIIX=m -CONFIG_PATA_OPTIDMA=m -CONFIG_PATA_PDC2027X=m -CONFIG_PATA_PDC_OLD=m -CONFIG_PATA_RADISYS=m -CONFIG_PATA_RDC=m -CONFIG_PATA_SCH=m -CONFIG_PATA_SERVERWORKS=m -CONFIG_PATA_SIL680=m -CONFIG_PATA_SIS=y -CONFIG_PATA_TOSHIBA=m -CONFIG_PATA_TRIFLEX=m -CONFIG_PATA_VIA=m -CONFIG_PATA_WINBOND=m -CONFIG_PATA_CMD640_PCI=m -CONFIG_PATA_MPIIX=m -CONFIG_PATA_NS87410=m -CONFIG_PATA_OPTI=m -CONFIG_PATA_PCMCIA=m -CONFIG_PATA_RZ1000=m -CONFIG_PATA_PARPORT=m -CONFIG_PATA_PARPORT_ATEN=m -CONFIG_PATA_PARPORT_BPCK=m -CONFIG_PATA_PARPORT_BPCK6=m -CONFIG_PATA_PARPORT_COMM=m -CONFIG_PATA_PARPORT_DSTR=m -CONFIG_PATA_PARPORT_FIT2=m -CONFIG_PATA_PARPORT_FIT3=m -CONFIG_PATA_PARPORT_EPAT=m -CONFIG_PATA_PARPORT_EPATC8=y -CONFIG_PATA_PARPORT_EPIA=m -CONFIG_PATA_PARPORT_FRIQ=m -CONFIG_PATA_PARPORT_FRPW=m -CONFIG_PATA_PARPORT_KBIC=m -CONFIG_PATA_PARPORT_KTTI=m -CONFIG_PATA_PARPORT_ON20=m -CONFIG_PATA_PARPORT_ON26=m -CONFIG_PATA_ACPI=m -CONFIG_ATA_GENERIC=y -CONFIG_PATA_LEGACY=m -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_LINEAR=m -CONFIG_MD_CLUSTER=m -CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=y -CONFIG_DM_UNSTRIPED=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_THIN_PROVISIONING=m -CONFIG_DM_CACHE=m -CONFIG_DM_WRITECACHE=m -CONFIG_DM_ERA=m -CONFIG_DM_CLONE=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_MULTIPATH_HST=m -CONFIG_DM_MULTIPATH_IOA=m -CONFIG_DM_DELAY=m -CONFIG_DM_DUST=m -CONFIG_DM_UEVENT=y -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m -CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y -CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_DM_INTEGRITY=m -CONFIG_DM_ZONED=m -CONFIG_DM_VDO=m -CONFIG_TARGET_CORE=m -CONFIG_TCM_IBLOCK=m -CONFIG_TCM_FILEIO=m -CONFIG_TCM_PSCSI=m -CONFIG_TCM_USER2=m -CONFIG_LOOPBACK_TARGET=m -CONFIG_TCM_FC=m -CONFIG_ISCSI_TARGET=m -CONFIG_ISCSI_TARGET_CXGB4=m -CONFIG_SBP_TARGET=m -CONFIG_REMOTE_TARGET=m -CONFIG_FUSION=y -CONFIG_FUSION_SPI=m -CONFIG_FUSION_FC=m -CONFIG_FUSION_SAS=m -CONFIG_FUSION_CTL=m -CONFIG_FUSION_LAN=m -CONFIG_FUSION_LOGGING=y -CONFIG_FIREWIRE=m -CONFIG_FIREWIRE_OHCI=m -CONFIG_FIREWIRE_SBP2=m -CONFIG_FIREWIRE_NET=m -CONFIG_FIREWIRE_NOSY=m -CONFIG_MACINTOSH_DRIVERS=y -CONFIG_MAC_EMUMOUSEBTN=m -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -CONFIG_OVPN=y -CONFIG_EQUALIZER=m -CONFIG_NET_FC=y -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN=m -CONFIG_IPVTAP=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_BAREUDP=m -CONFIG_GTP=m -CONFIG_PFCP=m -CONFIG_AMT=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NTB_NETDEV=m -CONFIG_RIONET=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_NLMON=m -CONFIG_NET_VRF=m -CONFIG_VSOCKMON=m -CONFIG_MHI_NET=m -CONFIG_ARCNET=m -CONFIG_ARCNET_1201=m -CONFIG_ARCNET_1051=m -CONFIG_ARCNET_RAW=m -CONFIG_ARCNET_CAP=m -CONFIG_ARCNET_COM90xx=m -CONFIG_ARCNET_COM90xxIO=m -CONFIG_ARCNET_RIM_I=m -CONFIG_ARCNET_COM20020=m -CONFIG_ARCNET_COM20020_PCI=m -CONFIG_ARCNET_COM20020_CS=m -CONFIG_ATM_DUMMY=m -CONFIG_ATM_TCP=m -CONFIG_ATM_LANAI=m -CONFIG_ATM_ENI=m -CONFIG_ATM_NICSTAR=m -CONFIG_ATM_IDT77252=m -CONFIG_ATM_IA=m -CONFIG_ATM_FORE200E=m -CONFIG_ATM_HE=m -CONFIG_ATM_HE_USE_SUNI=y -CONFIG_ATM_SOLOS=m -CONFIG_CAIF_DRIVERS=y -CONFIG_CAIF_TTY=m -CONFIG_CAIF_VIRTIO=m -CONFIG_B53_SPI_DRIVER=m -CONFIG_B53_MDIO_DRIVER=m -CONFIG_B53_MMAP_DRIVER=m -CONFIG_B53_SRAB_DRIVER=m -CONFIG_B53_SERDES=m -CONFIG_NET_DSA_BCM_SF2=m -CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m -CONFIG_NET_DSA_LANTIQ_GSWIP=m -CONFIG_NET_DSA_MT7530=m -CONFIG_NET_DSA_MV88E6060=m -CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m -CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m -CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y -CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m -CONFIG_NET_DSA_MV88E6XXX=m -CONFIG_NET_DSA_MV88E6XXX_PTP=y -CONFIG_NET_DSA_MSCC_OCELOT_EXT=m -CONFIG_NET_DSA_MSCC_SEVILLE=m -CONFIG_NET_DSA_AR9331=m -CONFIG_NET_DSA_QCA8K=m -CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y -CONFIG_NET_DSA_SJA1105=m -CONFIG_NET_DSA_SJA1105_PTP=y -CONFIG_NET_DSA_XRS700X_I2C=m -CONFIG_NET_DSA_XRS700X_MDIO=m -CONFIG_NET_DSA_REALTEK=m -CONFIG_NET_DSA_SMSC_LAN9303_I2C=m -CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m -CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m -CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m -CONFIG_PCMCIA_3C574=m -CONFIG_PCMCIA_3C589=m -CONFIG_VORTEX=m -CONFIG_TYPHOON=m -CONFIG_ADAPTEC_STARFIRE=m -CONFIG_ET131X=m -CONFIG_SLICOSS=m -CONFIG_ACENIC=m -CONFIG_ALTERA_TSE=m -CONFIG_ENA_ETHERNET=m -CONFIG_AMD8111_ETH=m -CONFIG_PCNET32=m -CONFIG_PCMCIA_NMCLAN=m -CONFIG_AMD_XGBE=m -CONFIG_PDS_CORE=m -CONFIG_AQTION=m -CONFIG_SPI_AX88796C=m -CONFIG_SPI_AX88796C_COMPRESSION=y -CONFIG_ATL2=m -CONFIG_ATL1=m -CONFIG_ATL1E=m -CONFIG_ATL1C=m -CONFIG_ALX=m -CONFIG_CX_ECAT=m -CONFIG_B44=m -CONFIG_BCMGENET=m -CONFIG_TIGON3=m -CONFIG_BNX2X=m -CONFIG_BNXT=m -CONFIG_BNGE=y -CONFIG_MACB=m -CONFIG_MACB_PCI=m -CONFIG_THUNDER_NIC_PF=m -CONFIG_THUNDER_NIC_VF=m -CONFIG_LIQUIDIO=m -CONFIG_LIQUIDIO_VF=m -CONFIG_CHELSIO_T1=m -CONFIG_CHELSIO_T1_1G=y -CONFIG_CHELSIO_T4_DCB=y -CONFIG_CHELSIO_T4_FCOE=y -CONFIG_CHELSIO_T4VF=m -# CONFIG_NET_VENDOR_CORTINA is not set -CONFIG_DM9051=m -CONFIG_DNET=m -CONFIG_NET_TULIP=y -CONFIG_DE2104X=m -CONFIG_TULIP=m -CONFIG_WINBOND_840=m -CONFIG_DM9102=m -CONFIG_ULI526X=m -CONFIG_PCMCIA_XIRCOM=m -CONFIG_DL2K=m -CONFIG_TSNEP=m -CONFIG_PCMCIA_FMVJ18X=m -CONFIG_FUN_ETH=m -CONFIG_GVE=m -CONFIG_HIBMCGE=m -CONFIG_HINIC=m -CONFIG_HINIC3=m -CONFIG_E100=m -CONFIG_E1000=m -CONFIG_E1000E=m -CONFIG_IGB=m -CONFIG_IGBVF=m -CONFIG_IXGBE=m -CONFIG_IXGBE_DCB=y -CONFIG_IXGBEVF=m -CONFIG_I40E=m -CONFIG_I40E_DCB=y -CONFIG_I40EVF=m -CONFIG_ICE=m -CONFIG_FM10K=m -CONFIG_IGC=m -CONFIG_IDPF=m -CONFIG_JME=m -CONFIG_ADIN1110=m -CONFIG_MVMDIO=m -CONFIG_SKGE=m -CONFIG_SKGE_GENESIS=y -CONFIG_SKY2=m -CONFIG_OCTEON_EP=m -CONFIG_PRESTERA=m -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_EN_IPSEC=y -CONFIG_MLX5_SF=y -CONFIG_MLX5_DPLL=m -CONFIG_MLXSW_CORE=m -CONFIG_FBNIC=m -CONFIG_KS8842=m -CONFIG_KS8851=m -CONFIG_KS8851_MLL=m -CONFIG_KSZ884X_PCI=m -CONFIG_ENC28J60=m -CONFIG_ENCX24J600=m -CONFIG_LAN743X=m -CONFIG_LAN865X=m -CONFIG_VCAP=y -CONFIG_MYRI10GE=m -CONFIG_FEALNX=m -CONFIG_NI_XGE_MANAGEMENT_ENET=m -CONFIG_NATSEMI=m -CONFIG_NS83820=m -CONFIG_S2IO=m -CONFIG_NFP=m -# CONFIG_NFP_APP_FLOWER is not set -CONFIG_PCMCIA_AXNET=m -CONFIG_NE2K_PCI=m -CONFIG_PCMCIA_PCNET=m -CONFIG_FORCEDETH=m -CONFIG_ETHOC=m -CONFIG_HAMACHI=m -CONFIG_YELLOWFIN=m -CONFIG_IONIC=m -CONFIG_QLA3XXX=m -CONFIG_QLCNIC=m -CONFIG_NETXEN_NIC=m -CONFIG_QED=m -CONFIG_QEDE=m -CONFIG_BNA=m -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_R6040=m -CONFIG_ATP=m -CONFIG_8139CP=m -CONFIG_8139TOO=m -CONFIG_8139TOO_8129=y -CONFIG_R8169=m -CONFIG_R8169_LEDS=y -CONFIG_RTASE=m -CONFIG_ROCKER=m -CONFIG_SXGBE_ETH=m -CONFIG_SC92031=m -CONFIG_SIS900=m -CONFIG_SIS190=m -CONFIG_SFC=m -CONFIG_SFC_FALCON=m -CONFIG_SFC_SIENA=m -CONFIG_SFC_SIENA_SRIOV=y -CONFIG_PCMCIA_SMC91C92=m -CONFIG_EPIC100=m -CONFIG_SMSC911X=m -CONFIG_SMSC9420=m -# CONFIG_NET_VENDOR_SOCIONEXT is not set -CONFIG_STMMAC_ETH=m -CONFIG_HAPPYMEAL=m -CONFIG_SUNGEM=m -CONFIG_CASSINI=m -CONFIG_NIU=m -CONFIG_DWC_XLGMAC=m -CONFIG_DWC_XLGMAC_PCI=m -CONFIG_TEHUTI=m -CONFIG_TEHUTI_TN40=m -CONFIG_TLAN=m -CONFIG_MSE102X=m -CONFIG_VIA_RHINE=m -CONFIG_VIA_RHINE_MMIO=y -CONFIG_VIA_VELOCITY=m -CONFIG_NGBE=m -CONFIG_TXGBE=m -CONFIG_TXGBEVF=m -CONFIG_NGBEVF=m -CONFIG_WIZNET_W5100=m -CONFIG_WIZNET_W5300=m -CONFIG_XILINX_EMACLITE=m -CONFIG_XILINX_AXI_EMAC=m -CONFIG_XILINX_LL_TEMAC=m -CONFIG_PCMCIA_XIRC2PS=m -CONFIG_FDDI=y -CONFIG_DEFXX=m -CONFIG_SKFP=m -CONFIG_PHYLIB=y -CONFIG_AS21XXX_PHY=m -CONFIG_AIR_EN8811H_PHY=m -CONFIG_AMD_PHY=m -CONFIG_ADIN_PHY=m -CONFIG_ADIN1100_PHY=m -CONFIG_AQUANTIA_PHY=m -CONFIG_BROADCOM_PHY=m -CONFIG_BCM54140_PHY=m -CONFIG_BCM84881_PHY=m -CONFIG_BCM87XX_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_CORTINA_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_ICPLUS_PHY=m -CONFIG_LXT_PHY=m -CONFIG_INTEL_XWAY_PHY=m -CONFIG_LSI_ET1011C_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_88Q2XXX_PHY=m -CONFIG_MARVELL_88X2222_PHY=m -CONFIG_MAXLINEAR_GPHY=m -CONFIG_MAXLINEAR_86110_PHY=m -CONFIG_MICROCHIP_T1S_PHY=m -CONFIG_MICROCHIP_T1_PHY=m -CONFIG_MICROSEMI_PHY=m -CONFIG_NATIONAL_PHY=m -CONFIG_NXP_CBTX_PHY=m -CONFIG_NXP_C45_TJA11XX_PHY=m -CONFIG_NXP_TJA11XX_PHY=m -CONFIG_NCN26000_PHY=m -CONFIG_AT803X_PHY=m -CONFIG_QCA83XX_PHY=m -CONFIG_QCA808X_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_REALTEK_PHY_HWMON=y -CONFIG_RENESAS_PHY=m -CONFIG_ROCKCHIP_PHY=m -CONFIG_STE10XP=m -CONFIG_TERANETICS_PHY=m -CONFIG_DP83822_PHY=m -CONFIG_DP83TC811_PHY=m -CONFIG_DP83848_PHY=m -CONFIG_DP83867_PHY=m -CONFIG_DP83869_PHY=m -CONFIG_DP83TD510_PHY=m -CONFIG_DP83TG720_PHY=m -CONFIG_XILINX_GMII2RGMII=m -CONFIG_PSE_CONTROLLER=y -CONFIG_PSE_REGULATOR=m -CONFIG_PSE_PD692X0=m -CONFIG_PSE_TPS23881=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_CAN327=m -CONFIG_CAN_JANZ_ICAN3=m -CONFIG_CAN_KVASER_PCIEFD=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_PLATFORM=m -CONFIG_CAN_CTUCANFD_PCI=m -CONFIG_CAN_IFI_CANFD=m -CONFIG_CAN_M_CAN=m -CONFIG_CAN_M_CAN_PCI=m -CONFIG_CAN_M_CAN_PLATFORM=m -CONFIG_CAN_M_CAN_TCAN4X5X=m -CONFIG_CAN_PEAK_PCIEFD=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_EMS_PCMCIA=m -CONFIG_CAN_F81601=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PEAK_PCMCIA=m -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m -CONFIG_CAN_SOFTING_CS=m -CONFIG_CAN_HI311X=m -CONFIG_CAN_MCP251X=m -CONFIG_CAN_MCP251XFD=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB=m -CONFIG_CAN_ETAS_ES58X=m -CONFIG_CAN_F81604=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -CONFIG_MCTP_SERIAL=m -CONFIG_MCTP_TRANSPORT_I2C=m -CONFIG_MCTP_TRANSPORT_USB=m -CONFIG_MDIO_GPIO=m -CONFIG_MDIO_MVUSB=m -CONFIG_PLIP=m -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOATM=m -CONFIG_PPPOE=m -CONFIG_PPTP=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_USB_NET_DRIVERS=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_CDC_PHONET=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -CONFIG_USB_NET_AQC111=m -CONFIG_ADM8211=m -CONFIG_ATH5K=m -CONFIG_ATH9K=m -CONFIG_ATH9K_AHB=y -CONFIG_ATH9K_DEBUGFS=y -CONFIG_ATH9K_STATION_STATISTICS=y -CONFIG_ATH9K_WOW=y -CONFIG_ATH9K_CHANNEL_CONTEXT=y -CONFIG_ATH9K_PCI_NO_EEPROM=m -CONFIG_ATH9K_HTC=m -CONFIG_ATH9K_HTC_DEBUGFS=y -CONFIG_ATH9K_HWRNG=y -CONFIG_CARL9170=m -CONFIG_CARL9170_HWRNG=y -CONFIG_ATH6KL=m -CONFIG_ATH6KL_SDIO=m -CONFIG_ATH6KL_USB=m -CONFIG_AR5523=m -CONFIG_WIL6210=m -CONFIG_WIL6210_TRACING=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_SDIO=m -CONFIG_ATH10K_USB=m -CONFIG_ATH10K_DEBUGFS=y -CONFIG_ATH10K_TRACING=y -CONFIG_WCN36XX=m -CONFIG_ATH11K=m -CONFIG_ATH11K_PCI=m -CONFIG_ATH12K=m -CONFIG_AT76C50X_USB=m -CONFIG_B43=m -CONFIG_B43LEGACY=m -# CONFIG_B43LEGACY_DEBUG is not set -CONFIG_BRCMSMAC=m -CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_USB=y -CONFIG_BRCMFMAC_PCIE=y -CONFIG_BRCM_TRACING=y -CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -CONFIG_IWL4965=m -CONFIG_IWL3945=m -CONFIG_IWLEGACY_DEBUGFS=y -CONFIG_IWLWIFI=m -CONFIG_IWLDVM=m -CONFIG_IWLMVM=m -CONFIG_IWLMLD=m -CONFIG_IWLWIFI_DEBUGFS=y -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -CONFIG_P54_PCI=m -CONFIG_P54_SPI=m -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -CONFIG_LIBERTAS_MESH=y -CONFIG_LIBERTAS_THINFIRM=m -CONFIG_LIBERTAS_THINFIRM_USB=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_MWIFIEX_USB=m -CONFIG_MWL8K=m -CONFIG_MT7601U=m -CONFIG_MT76x2U=m -CONFIG_MT7921E=m -CONFIG_MT7925E=m -CONFIG_MT7925U=m -CONFIG_WILC1000_SDIO=m -CONFIG_WILC1000_SPI=m -CONFIG_PLFXLC=m -CONFIG_RT2X00=m -CONFIG_RT2400PCI=m -CONFIG_RT2500PCI=m -CONFIG_RT61PCI=m -CONFIG_RT2800PCI=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT3573=y -CONFIG_RT2800USB_RT53XX=y -CONFIG_RT2800USB_RT55XX=y -CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RTL8180=m -CONFIG_RTL8187=m -CONFIG_RTL8192CE=m -CONFIG_RTL8192SE=m -CONFIG_RTL8192DE=m -CONFIG_RTL8723AE=m -CONFIG_RTL8723BE=m -CONFIG_RTL8188EE=m -CONFIG_RTL8192EE=m -CONFIG_RTL8821AE=m -CONFIG_RTL8192CU=m -CONFIG_RTL8192DU=m -# CONFIG_RTLWIFI_DEBUG is not set -CONFIG_RTL8XXXU=m -CONFIG_RTL8XXXU_UNTESTED=y -CONFIG_RTW88=m -CONFIG_RTW88_8822BE=m -CONFIG_RTW88_8822BS=m -CONFIG_RTW88_8822BU=m -CONFIG_RTW88_8822CE=m -CONFIG_RTW88_8822CS=m -CONFIG_RTW88_8822CU=m -CONFIG_RTW88_8723DE=m -CONFIG_RTW88_8723DS=m -CONFIG_RTW88_8723CS=m -CONFIG_RTW88_8723DU=m -CONFIG_RTW88_8821CE=m -CONFIG_RTW88_8821CS=m -CONFIG_RTW88_8821CU=m -CONFIG_RTW88_8821AU=m -CONFIG_RTW88_8812AU=m -CONFIG_RTW88_8814AE=m -CONFIG_RTW88_8814AU=m -CONFIG_RTW89=m -CONFIG_RTW89_8851BE=m -CONFIG_RTW89_8851BU=m -CONFIG_RTW89_8852AE=m -CONFIG_RTW89_8852BE=m -CONFIG_RTW89_8852BU=m -CONFIG_RTW89_8852BTE=m -CONFIG_RTW89_8852CE=m -CONFIG_RTW89_8922AE=m -CONFIG_RSI_91X=m -# CONFIG_RSI_DEBUGFS is not set -CONFIG_WFX=m -CONFIG_CW1200=m -CONFIG_CW1200_WLAN_SDIO=m -CONFIG_CW1200_WLAN_SPI=m -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL12XX=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_ZD1211RW=m -CONFIG_QTNFMAC_PCIE=m -CONFIG_MAC80211_HWSIM=m -CONFIG_VIRT_WIFI=m -CONFIG_WAN=y -CONFIG_HDLC=m -CONFIG_HDLC_RAW=m -CONFIG_HDLC_RAW_ETH=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_X25=m -CONFIG_FRAMER=m -CONFIG_PCI200SYN=m -CONFIG_WANXL=m -CONFIG_PC300TOO=m -CONFIG_FARSYNC=m -CONFIG_LAPBETHER=m -CONFIG_IEEE802154_FAKELB=m -CONFIG_IEEE802154_AT86RF230=m -CONFIG_IEEE802154_MRF24J40=m -CONFIG_IEEE802154_CC2520=m -CONFIG_IEEE802154_ATUSB=m -CONFIG_IEEE802154_ADF7242=m -CONFIG_IEEE802154_CA8210=m -CONFIG_IEEE802154_MCR20A=m -CONFIG_WWAN=y -# CONFIG_WWAN_DEBUGFS is not set -CONFIG_MHI_WWAN_CTRL=m -CONFIG_MHI_WWAN_MBIM=m -CONFIG_RPMSG_WWAN_CTRL=m -CONFIG_IOSM=m -CONFIG_MTK_T7XX=m -CONFIG_XEN_NETDEV_BACKEND=m -CONFIG_VMXNET3=m -CONFIG_FUJITSU_ES=m -CONFIG_USB4_NET=m -CONFIG_NETDEVSIM=m -CONFIG_ISDN=y -CONFIG_MISDN=m -CONFIG_MISDN_DSP=m -CONFIG_MISDN_L1OIP=m -CONFIG_MISDN_HFCPCI=m -CONFIG_MISDN_HFCMULTI=m -CONFIG_MISDN_HFCUSB=m -CONFIG_MISDN_AVMFRITZ=m -CONFIG_MISDN_SPEEDFAX=m -CONFIG_MISDN_INFINEON=m -CONFIG_MISDN_W6692=m -CONFIG_MISDN_NETJET=m -CONFIG_INPUT_LEDS=m -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_ADP5520=m -CONFIG_KEYBOARD_ADP5588=m -CONFIG_KEYBOARD_APPLESPI=m -CONFIG_KEYBOARD_QT1050=m -CONFIG_KEYBOARD_QT1070=m -CONFIG_KEYBOARD_QT2160=m -CONFIG_KEYBOARD_DLINK_DIR685=m -CONFIG_KEYBOARD_LKKBD=m -CONFIG_KEYBOARD_GPIO=m -CONFIG_KEYBOARD_TCA8418=m -CONFIG_KEYBOARD_MATRIX=m -CONFIG_KEYBOARD_LM8323=m -CONFIG_KEYBOARD_LM8333=m -CONFIG_KEYBOARD_MAX7359=m -CONFIG_KEYBOARD_MPR121=m -CONFIG_KEYBOARD_NEWTON=m -CONFIG_KEYBOARD_OPENCORES=m -CONFIG_KEYBOARD_PINEPHONE=m -CONFIG_KEYBOARD_SAMSUNG=m -CONFIG_KEYBOARD_STOWAWAY=m -CONFIG_KEYBOARD_SUNKBD=m -CONFIG_KEYBOARD_IQS62X=m -CONFIG_KEYBOARD_TM2_TOUCHKEY=m -CONFIG_KEYBOARD_TWL4030=m -CONFIG_KEYBOARD_XTKBD=m -CONFIG_KEYBOARD_CROS_EC=m -CONFIG_KEYBOARD_MTK_PMIC=m -CONFIG_KEYBOARD_CYPRESS_SF=m -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_PS2_ELANTECH=y -CONFIG_MOUSE_PS2_SENTELIC=y -CONFIG_MOUSE_PS2_TOUCHKIT=y -CONFIG_MOUSE_PS2_VMMOUSE=y -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -CONFIG_MOUSE_CYAPA=m -CONFIG_MOUSE_ELAN_I2C=m -CONFIG_MOUSE_ELAN_I2C_SMBUS=y -CONFIG_MOUSE_VSXXXAA=m -CONFIG_MOUSE_GPIO=m -CONFIG_MOUSE_SYNAPTICS_I2C=m -CONFIG_MOUSE_SYNAPTICS_USB=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADC=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=m -CONFIG_JOYSTICK_IFORCE_232=m -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_DB9=m -CONFIG_JOYSTICK_GAMECON=m -CONFIG_JOYSTICK_TURBOGRAFX=m -CONFIG_JOYSTICK_AS5011=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y -CONFIG_JOYSTICK_WALKERA0701=m -CONFIG_JOYSTICK_PSXPAD_SPI=m -CONFIG_JOYSTICK_PXRC=m -CONFIG_JOYSTICK_QWIIC=m -CONFIG_JOYSTICK_FSIA6B=m -CONFIG_JOYSTICK_SENSEHAT=m -CONFIG_JOYSTICK_SEESAW=m -CONFIG_INPUT_TABLET=y -CONFIG_TABLET_USB_ACECAD=m -CONFIG_TABLET_USB_AIPTEK=m -CONFIG_TABLET_USB_HANWANG=m -CONFIG_TABLET_USB_KBTAB=m -CONFIG_TABLET_USB_PEGASUS=m -CONFIG_TABLET_SERIAL_WACOM4=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_88PM860X=m -CONFIG_TOUCHSCREEN_ADS7846=m -CONFIG_TOUCHSCREEN_AD7877=m -CONFIG_TOUCHSCREEN_AD7879=m -CONFIG_TOUCHSCREEN_AD7879_I2C=m -CONFIG_TOUCHSCREEN_AD7879_SPI=m -CONFIG_TOUCHSCREEN_ADC=m -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_TOUCHSCREEN_AUO_PIXCIR=m -CONFIG_TOUCHSCREEN_BU21013=m -CONFIG_TOUCHSCREEN_BU21029=m -CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m -CONFIG_TOUCHSCREEN_CY8CTMA140=m -CONFIG_TOUCHSCREEN_CY8CTMG110=m -CONFIG_TOUCHSCREEN_CYTTSP_CORE=m -CONFIG_TOUCHSCREEN_CYTTSP_I2C=m -CONFIG_TOUCHSCREEN_CYTTSP_SPI=m -CONFIG_TOUCHSCREEN_CYTTSP5=m -CONFIG_TOUCHSCREEN_DA9034=m -CONFIG_TOUCHSCREEN_DA9052=m -CONFIG_TOUCHSCREEN_DYNAPRO=m -CONFIG_TOUCHSCREEN_HAMPSHIRE=m -CONFIG_TOUCHSCREEN_EETI=m -CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m -CONFIG_TOUCHSCREEN_EXC3000=m -CONFIG_TOUCHSCREEN_FUJITSU=m -CONFIG_TOUCHSCREEN_GOODIX=m -CONFIG_TOUCHSCREEN_HIDEEP=m -CONFIG_TOUCHSCREEN_HYCON_HY46XX=m -CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m -CONFIG_TOUCHSCREEN_ILI210X=m -CONFIG_TOUCHSCREEN_ILITEK=m -CONFIG_TOUCHSCREEN_S6SY761=m -CONFIG_TOUCHSCREEN_GUNZE=m -CONFIG_TOUCHSCREEN_EKTF2127=m -CONFIG_TOUCHSCREEN_ELAN=m -CONFIG_TOUCHSCREEN_ELO=m -CONFIG_TOUCHSCREEN_WACOM_W8001=m -CONFIG_TOUCHSCREEN_WACOM_I2C=m -CONFIG_TOUCHSCREEN_MAX11801=m -CONFIG_TOUCHSCREEN_MMS114=m -CONFIG_TOUCHSCREEN_MELFAS_MIP4=m -CONFIG_TOUCHSCREEN_MSG2638=m -CONFIG_TOUCHSCREEN_MTOUCH=m -CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m -CONFIG_TOUCHSCREEN_IMAGIS=m -CONFIG_TOUCHSCREEN_INEXIO=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -CONFIG_TOUCHSCREEN_PIXCIR=m -CONFIG_TOUCHSCREEN_WDT87XX_I2C=m -CONFIG_TOUCHSCREEN_WM831X=m -CONFIG_TOUCHSCREEN_WM97XX=m -CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -CONFIG_TOUCHSCREEN_MC13783=m -CONFIG_TOUCHSCREEN_TOUCHIT213=m -CONFIG_TOUCHSCREEN_TSC_SERIO=m -CONFIG_TOUCHSCREEN_TSC2004=m -CONFIG_TOUCHSCREEN_TSC2005=m -CONFIG_TOUCHSCREEN_TSC2007=m -CONFIG_TOUCHSCREEN_PCAP=m -CONFIG_TOUCHSCREEN_RM_TS=m -CONFIG_TOUCHSCREEN_SILEAD=m -CONFIG_TOUCHSCREEN_SIS_I2C=m -CONFIG_TOUCHSCREEN_ST1232=m -CONFIG_TOUCHSCREEN_STMFTS=m -CONFIG_TOUCHSCREEN_SUR40=m -CONFIG_TOUCHSCREEN_SURFACE3_SPI=m -CONFIG_TOUCHSCREEN_SX8654=m -CONFIG_TOUCHSCREEN_TPS6507X=m -CONFIG_TOUCHSCREEN_ZET6223=m -CONFIG_TOUCHSCREEN_ZFORCE=m -CONFIG_TOUCHSCREEN_COLIBRI_VF50=m -CONFIG_TOUCHSCREEN_ROHM_BU21023=m -CONFIG_TOUCHSCREEN_IQS5XX=m -CONFIG_TOUCHSCREEN_IQS7211=m -CONFIG_TOUCHSCREEN_ZINITIX=m -CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_88PM860X_ONKEY=m -CONFIG_INPUT_88PM80X_ONKEY=m -CONFIG_INPUT_AD714X=m -CONFIG_INPUT_ARIZONA_HAPTICS=m -CONFIG_INPUT_ATC260X_ONKEY=m -CONFIG_INPUT_BMA150=m -CONFIG_INPUT_CS40L50_VIBRA=m -CONFIG_INPUT_E3X0_BUTTON=m -CONFIG_INPUT_PCSPKR=m -CONFIG_INPUT_MAX77693_HAPTIC=m -CONFIG_INPUT_MAX8925_ONKEY=m -CONFIG_INPUT_MAX8997_HAPTIC=m -CONFIG_INPUT_MC13783_PWRBUTTON=m -CONFIG_INPUT_MMA8450=m -CONFIG_INPUT_APANEL=m -CONFIG_INPUT_GPIO_BEEPER=m -CONFIG_INPUT_GPIO_DECODER=m -CONFIG_INPUT_GPIO_VIBRA=m -CONFIG_INPUT_ATLAS_BTNS=m -CONFIG_INPUT_ATI_REMOTE2=m -CONFIG_INPUT_KEYSPAN_REMOTE=m -CONFIG_INPUT_KXTJ9=m -CONFIG_INPUT_POWERMATE=m -CONFIG_INPUT_YEALINK=m -CONFIG_INPUT_CM109=m -CONFIG_INPUT_REGULATOR_HAPTIC=m -CONFIG_INPUT_RETU_PWRBUTTON=m -CONFIG_INPUT_AXP20X_PEK=m -CONFIG_INPUT_TWL4030_PWRBUTTON=m -CONFIG_INPUT_TWL4030_VIBRA=m -CONFIG_INPUT_TWL6040_VIBRA=m -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_PALMAS_PWRBUTTON=m -CONFIG_INPUT_PCF8574=m -CONFIG_INPUT_PWM_BEEPER=m -CONFIG_INPUT_PWM_VIBRA=m -CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -CONFIG_INPUT_DA7280_HAPTICS=m -CONFIG_INPUT_DA9052_ONKEY=m -CONFIG_INPUT_DA9055_ONKEY=m -CONFIG_INPUT_DA9063_ONKEY=m -CONFIG_INPUT_WM831X_ON=m -CONFIG_INPUT_PCAP=m -CONFIG_INPUT_ADXL34X=m -CONFIG_INPUT_IBM_PANEL=m -CONFIG_INPUT_IMS_PCU=m -CONFIG_INPUT_IQS269A=m -CONFIG_INPUT_IQS626A=m -CONFIG_INPUT_IQS7222=m -CONFIG_INPUT_CMA3000=m -CONFIG_INPUT_CMA3000_I2C=m -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m -CONFIG_INPUT_IDEAPAD_SLIDEBAR=m -CONFIG_INPUT_SOC_BUTTON_ARRAY=m -CONFIG_INPUT_DRV260X_HAPTICS=m -CONFIG_INPUT_DRV2665_HAPTICS=m -CONFIG_INPUT_DRV2667_HAPTICS=m -CONFIG_INPUT_QNAP_MCU=m -CONFIG_INPUT_RAVE_SP_PWRBUTTON=m -CONFIG_INPUT_RT5120_PWRKEY=m -CONFIG_RMI4_I2C=m -CONFIG_RMI4_SPI=m -CONFIG_RMI4_SMB=m -CONFIG_RMI4_F1A=y -CONFIG_RMI4_F21=y -CONFIG_RMI4_F55=y -CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_CT82C710=m -CONFIG_SERIO_PARKBD=m -CONFIG_SERIO_PCIPS2=m -CONFIG_SERIO_RAW=m -CONFIG_SERIO_ALTERA_PS2=m -CONFIG_SERIO_PS2MULT=m -CONFIG_SERIO_ARC_PS2=m -CONFIG_SERIO_GPIO_PS2=m -CONFIG_USERIO=m -CONFIG_GAMEPORT_EMU10K1=m -CONFIG_GAMEPORT_FM801=m -CONFIG_LEGACY_PTY_COUNT=0 -# CONFIG_LEGACY_TIOCSTI is not set -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXAR=m -CONFIG_SERIAL_8250_CS=m -CONFIG_SERIAL_8250_MEN_MCB=m -CONFIG_SERIAL_8250_NR_UARTS=48 -CONFIG_SERIAL_8250_RUNTIME_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_PCI1XXXX=m -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DFL=m -CONFIG_SERIAL_8250_DW=m -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_8250_LPSS=m -CONFIG_SERIAL_8250_MID=m -CONFIG_SERIAL_8250_PERICOM=m -CONFIG_SERIAL_8250_NI=m -CONFIG_SERIAL_MAX3100=m -CONFIG_SERIAL_MAX310X=y -CONFIG_SERIAL_UARTLITE=m -CONFIG_SERIAL_JSM=m -CONFIG_SERIAL_LANTIQ=m -CONFIG_SERIAL_SCCNXP=y -CONFIG_SERIAL_SCCNXP_CONSOLE=y -CONFIG_SERIAL_SC16IS7XX=m -CONFIG_SERIAL_ALTERA_JTAGUART=m -CONFIG_SERIAL_ALTERA_UART=m -CONFIG_SERIAL_ARC=m -CONFIG_SERIAL_RP2=m -CONFIG_SERIAL_FSL_LPUART=m -CONFIG_SERIAL_FSL_LINFLEXUART=m -CONFIG_SERIAL_MEN_Z135=m -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_MOXA_INTELLIO=m -CONFIG_MOXA_SMARTIO=m -CONFIG_N_HDLC=m -CONFIG_IPWIRELESS=m -CONFIG_N_GSM=m -CONFIG_NOZOMI=m -CONFIG_NULL_TTY=m -CONFIG_RPMSG_TTY=m -CONFIG_SERIAL_DEV_BUS=y -CONFIG_TTY_PRINTK=y -CONFIG_PRINTER=m -CONFIG_PPDEV=m -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SSIF=m -CONFIG_IPMI_IPMB=m -CONFIG_IPMI_WATCHDOG=m -CONFIG_IPMI_POWEROFF=m -CONFIG_SSIF_IPMI_BMC=m -CONFIG_IPMB_DEVICE_INTERFACE=m -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=m -CONFIG_HW_RANDOM_INTEL=m -CONFIG_HW_RANDOM_AMD=m -CONFIG_HW_RANDOM_BA431=m -CONFIG_HW_RANDOM_VIA=m -CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_HW_RANDOM_XIPHERA=m -CONFIG_APPLICOM=m -CONFIG_MWAVE=m -CONFIG_HPET=y -CONFIG_HANGCHECK_TIMER=m -CONFIG_TCG_TPM2_HMAC=y -CONFIG_TCG_TIS_SPI=m -CONFIG_TCG_TIS_I2C=m -CONFIG_TCG_TIS_I2C_ATMEL=m -CONFIG_TCG_TIS_I2C_INFINEON=m -CONFIG_TCG_TIS_I2C_NUVOTON=m -CONFIG_TCG_NSC=m -CONFIG_TCG_ATMEL=m -CONFIG_TCG_INFINEON=m -CONFIG_TCG_XEN=m -CONFIG_TCG_VTPM_PROXY=m -CONFIG_TCG_TIS_ST33ZP24_I2C=m -CONFIG_TCG_TIS_ST33ZP24_SPI=m -CONFIG_TELCLOCK=m -CONFIG_XILLYBUS=m -CONFIG_XILLYBUS_PCIE=m -CONFIG_XILLYUSB=m -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX_GPIO=m -CONFIG_I2C_MUX_LTC4306=m -CONFIG_I2C_MUX_PCA9541=m -CONFIG_I2C_MUX_PCA954x=m -CONFIG_I2C_MUX_REG=m -CONFIG_I2C_MUX_MLXCPLD=m -CONFIG_I2C_ALI1535=m -CONFIG_I2C_ALI1563=m -CONFIG_I2C_ALI15X3=m -CONFIG_I2C_AMD756=m -CONFIG_I2C_AMD8111=m -CONFIG_I2C_AMD_MP2=m -CONFIG_I2C_AMD_ASF=m -CONFIG_I2C_I801=m -CONFIG_I2C_ISCH=m -CONFIG_I2C_ISMT=m -CONFIG_I2C_PIIX4=m -CONFIG_I2C_CHT_WC=m -CONFIG_I2C_NFORCE2=m -CONFIG_I2C_NVIDIA_GPU=m -CONFIG_I2C_SIS5595=m -CONFIG_I2C_SIS630=m -CONFIG_I2C_SIS96X=m -CONFIG_I2C_VIA=m -CONFIG_I2C_VIAPRO=m -CONFIG_I2C_ZHAOXIN=m -CONFIG_I2C_SCMI=m -CONFIG_I2C_CBUS_GPIO=m -CONFIG_I2C_CGBC=m -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_AMDISP=m -CONFIG_I2C_DESIGNWARE_BAYTRAIL=y -CONFIG_I2C_DESIGNWARE_PCI=m -CONFIG_I2C_EMEV2=m -CONFIG_I2C_GPIO=m -CONFIG_I2C_KEBA=m -CONFIG_I2C_KEMPLD=m -CONFIG_I2C_OCORES=m -CONFIG_I2C_PCA_PLATFORM=m -CONFIG_I2C_SIMTEC=m -CONFIG_I2C_DIOLAN_U2C=m -CONFIG_I2C_DLN2=m -CONFIG_I2C_CP2615=m -CONFIG_I2C_PARPORT=m -CONFIG_I2C_PCI1XXXX=m -CONFIG_I2C_ROBOTFUZZ_OSIF=m -CONFIG_I2C_TAOS_EVM=m -CONFIG_I2C_TINY_USB=m -CONFIG_I2C_VIPERBOARD=m -CONFIG_I2C_MLXCPLD=m -CONFIG_I2C_VIRTIO=m -CONFIG_I2C_STUB=m -CONFIG_I2C_SLAVE_EEPROM=m -CONFIG_I3C=m -CONFIG_CDNS_I3C_MASTER=m -CONFIG_DW_I3C_MASTER=m -CONFIG_SVC_I3C_MASTER=m -CONFIG_SPI=y -CONFIG_SPI_ALTERA=m -CONFIG_SPI_ALTERA_DFL=m -CONFIG_SPI_AXI_SPI_ENGINE=m -CONFIG_SPI_BUTTERFLY=m -CONFIG_SPI_CADENCE=m -CONFIG_SPI_CH341=m -CONFIG_SPI_DESIGNWARE=m -CONFIG_SPI_DW_PCI=m -CONFIG_SPI_DW_MMIO=m -CONFIG_SPI_DLN2=m -CONFIG_SPI_GPIO=m -CONFIG_SPI_KSPI2=m -CONFIG_SPI_LM70_LLP=m -CONFIG_SPI_MICROCHIP_CORE_QSPI=m -CONFIG_SPI_LANTIQ_SSC=m -CONFIG_SPI_OC_TINY=m -CONFIG_SPI_PCI1XXXX=m -CONFIG_SPI_SC18IS602=m -CONFIG_SPI_SIFIVE=m -CONFIG_SPI_MXIC=m -CONFIG_SPI_XCOMM=m -CONFIG_SPI_ZYNQMP_GQSPI=m -CONFIG_SPI_AMD=m -CONFIG_SPI_MUX=m -CONFIG_SPI_SPIDEV=m -CONFIG_SPI_TLE62X0=m -CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m -CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m -CONFIG_SPMI=m -CONFIG_HSI=m -CONFIG_HSI_CHAR=m -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_PARPORT=m -CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PPS_GENERATOR=m -CONFIG_PPS_GENERATOR_TIO=m -CONFIG_PTP_1588_CLOCK=m -CONFIG_PTP_1588_CLOCK_IDT82P33=m -CONFIG_PTP_1588_CLOCK_IDTCM=m -CONFIG_PTP_1588_CLOCK_OCP=m -CONFIG_PTP_DFL_TOD=m -CONFIG_ZL3073X_I2C=m -CONFIG_ZL3073X_SPI=m -CONFIG_PINCTRL_AMD=y -CONFIG_PINCTRL_AMDISP=m -CONFIG_PINCTRL_CY8C95X0=m -CONFIG_PINCTRL_MCP23S08=m -CONFIG_PINCTRL_SX150X=y -CONFIG_PINCTRL_BAYTRAIL=y -CONFIG_PINCTRL_CHERRYVIEW=y -CONFIG_PINCTRL_LYNXPOINT=m -CONFIG_PINCTRL_INTEL_PLATFORM=m -CONFIG_PINCTRL_ALDERLAKE=m -CONFIG_PINCTRL_BROXTON=m -CONFIG_PINCTRL_CANNONLAKE=m -CONFIG_PINCTRL_CEDARFORK=m -CONFIG_PINCTRL_DENVERTON=m -CONFIG_PINCTRL_ELKHARTLAKE=m -CONFIG_PINCTRL_EMMITSBURG=m -CONFIG_PINCTRL_GEMINILAKE=m -CONFIG_PINCTRL_ICELAKE=m -CONFIG_PINCTRL_JASPERLAKE=m -CONFIG_PINCTRL_LAKEFIELD=m -CONFIG_PINCTRL_LEWISBURG=m -CONFIG_PINCTRL_METEORLAKE=m -CONFIG_PINCTRL_METEORPOINT=m -CONFIG_PINCTRL_SUNRISEPOINT=m -CONFIG_PINCTRL_TIGERLAKE=m -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_AMDPT=m -CONFIG_GPIO_DWAPB=m -CONFIG_GPIO_EXAR=m -CONFIG_GPIO_GENERIC_PLATFORM=m -CONFIG_GPIO_GRANITERAPIDS=m -CONFIG_GPIO_ICH=m -CONFIG_GPIO_MB86S7X=m -CONFIG_GPIO_MENZ127=m -CONFIG_GPIO_POLARFIRE_SOC=y -CONFIG_GPIO_XILINX=m -CONFIG_GPIO_VX855=m -CONFIG_GPIO_F7188X=m -CONFIG_GPIO_IT87=m -CONFIG_GPIO_SCH=m -CONFIG_GPIO_SCH311X=m -CONFIG_GPIO_WINBOND=m -CONFIG_GPIO_WS16C48=m -CONFIG_GPIO_FXL6408=m -CONFIG_GPIO_DS4520=m -CONFIG_GPIO_MAX7300=m -CONFIG_GPIO_MAX732X=m -CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_PCA9570=m -CONFIG_GPIO_PCF857X=m -CONFIG_GPIO_TPIC2810=m -CONFIG_GPIO_ADP5520=m -CONFIG_GPIO_ARIZONA=m -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_CGBC=m -CONFIG_GPIO_CRYSTAL_COVE=m -CONFIG_GPIO_DA9052=m -CONFIG_GPIO_DA9055=m -CONFIG_GPIO_DLN2=m -CONFIG_GPIO_ELKHARTLAKE=m -CONFIG_GPIO_JANZ_TTL=m -CONFIG_GPIO_KEMPLD=m -CONFIG_GPIO_LP3943=m -CONFIG_GPIO_LP873X=m -CONFIG_GPIO_MADERA=m -CONFIG_GPIO_PALMAS=y -CONFIG_GPIO_RC5T583=y -CONFIG_GPIO_TPS65086=m -CONFIG_GPIO_TPS6586X=y -CONFIG_GPIO_TPS65910=y -CONFIG_GPIO_TPS65912=m -CONFIG_GPIO_TPS68470=m -CONFIG_GPIO_TQMX86=m -CONFIG_GPIO_TWL4030=m -CONFIG_GPIO_TWL6040=m -CONFIG_GPIO_WHISKEY_COVE=m -CONFIG_GPIO_WM831X=m -CONFIG_GPIO_WM8350=m -CONFIG_GPIO_WM8994=m -CONFIG_GPIO_AMD8111=m -CONFIG_GPIO_ML_IOH=m -CONFIG_GPIO_PCI_IDIO_16=m -CONFIG_GPIO_PCIE_IDIO_24=m -CONFIG_GPIO_RDC321X=m -CONFIG_GPIO_74X164=m -CONFIG_GPIO_MAX3191X=m -CONFIG_GPIO_MAX7301=m -CONFIG_GPIO_MC33880=m -CONFIG_GPIO_PISOSR=m -CONFIG_GPIO_XRA1403=m -CONFIG_GPIO_VIPERBOARD=m -CONFIG_GPIO_MPSSE=m -CONFIG_GPIO_AGGREGATOR=m -CONFIG_GPIO_LATCH=m -CONFIG_GPIO_VIRTIO=m -CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER=m -CONFIG_GPIO_VIRTUSER=m -CONFIG_W1_MASTER_AMD_AXI=m -CONFIG_W1_MASTER_MATROX=m -CONFIG_W1_MASTER_DS2490=m -CONFIG_W1_MASTER_DS2482=m -CONFIG_W1_MASTER_GPIO=m -CONFIG_W1_MASTER_SGI=m -CONFIG_W1_SLAVE_THERM=m -CONFIG_W1_SLAVE_SMEM=m -CONFIG_W1_SLAVE_DS2405=m -CONFIG_W1_SLAVE_DS2408=m -CONFIG_W1_SLAVE_DS2413=m -CONFIG_W1_SLAVE_DS2406=m -CONFIG_W1_SLAVE_DS2423=m -CONFIG_W1_SLAVE_DS2805=m -CONFIG_W1_SLAVE_DS2430=m -CONFIG_W1_SLAVE_DS2431=m -CONFIG_W1_SLAVE_DS2433=m -CONFIG_W1_SLAVE_DS2438=m -CONFIG_W1_SLAVE_DS250X=m -CONFIG_W1_SLAVE_DS28E04=m -CONFIG_W1_SLAVE_DS28E17=m -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_ATC260X=m -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_TPS65086=y -CONFIG_POWER_SEQUENCING=m -CONFIG_GENERIC_ADC_BATTERY=m -CONFIG_IP5XXX_POWER=m -CONFIG_MAX8925_POWER=m -CONFIG_WM831X_BACKUP=m -CONFIG_WM831X_POWER=m -CONFIG_WM8350_POWER=m -CONFIG_TEST_POWER=m -CONFIG_BATTERY_88PM860X=m -CONFIG_CHARGER_ADP5061=m -CONFIG_BATTERY_CHAGALL=m -CONFIG_BATTERY_CW2015=m -CONFIG_BATTERY_DS2760=m -CONFIG_BATTERY_DS2780=m -CONFIG_BATTERY_DS2781=m -CONFIG_BATTERY_DS2782=m -CONFIG_BATTERY_SBS=m -CONFIG_CHARGER_SBS=m -CONFIG_MANAGER_SBS=m -CONFIG_BATTERY_BQ27XXX=m -CONFIG_BATTERY_DA9030=m -CONFIG_BATTERY_DA9052=m -CONFIG_CHARGER_DA9150=m -CONFIG_BATTERY_DA9150=m -CONFIG_CHARGER_AXP20X=m -CONFIG_BATTERY_AXP20X=m -CONFIG_AXP20X_POWER=m -CONFIG_AXP288_CHARGER=m -CONFIG_AXP288_FUEL_GAUGE=m -CONFIG_BATTERY_MAX17040=m -CONFIG_BATTERY_MAX17042=m -CONFIG_BATTERY_MAX1720X=m -CONFIG_BATTERY_MAX1721X=m -CONFIG_BATTERY_TWL4030_MADC=m -CONFIG_CHARGER_88PM860X=m -CONFIG_BATTERY_RX51=m -CONFIG_CHARGER_ISP1704=m -CONFIG_CHARGER_MAX8903=m -CONFIG_CHARGER_TWL4030=m -CONFIG_CHARGER_TWL6030=m -CONFIG_CHARGER_LP8727=m -CONFIG_CHARGER_LP8788=m -CONFIG_CHARGER_GPIO=m -CONFIG_CHARGER_MANAGER=y -CONFIG_CHARGER_LT3651=m -CONFIG_CHARGER_LTC4162L=m -CONFIG_CHARGER_MAX14577=m -CONFIG_CHARGER_MAX77693=m -CONFIG_CHARGER_MAX77705=m -CONFIG_CHARGER_MAX77976=m -CONFIG_CHARGER_MAX8971=m -CONFIG_CHARGER_MAX8997=m -CONFIG_CHARGER_MAX8998=m -CONFIG_CHARGER_MP2629=m -CONFIG_CHARGER_MT6360=m -CONFIG_CHARGER_MT6370=m -CONFIG_CHARGER_BQ2415X=m -CONFIG_CHARGER_BQ24190=m -CONFIG_CHARGER_BQ24257=m -CONFIG_CHARGER_BQ24735=m -CONFIG_CHARGER_BQ2515X=m -CONFIG_CHARGER_BQ25890=m -CONFIG_CHARGER_BQ25980=m -CONFIG_CHARGER_BQ256XX=m -CONFIG_CHARGER_SMB347=m -CONFIG_CHARGER_TPS65090=m -CONFIG_BATTERY_GAUGE_LTC2941=m -CONFIG_BATTERY_GOLDFISH=m -CONFIG_BATTERY_RT5033=m -CONFIG_CHARGER_RT5033=m -CONFIG_CHARGER_RT9455=m -CONFIG_CHARGER_RT9467=m -CONFIG_CHARGER_RT9471=m -CONFIG_CHARGER_CROS_USBPD=m -CONFIG_FUEL_GAUGE_STC3117=m -CONFIG_CHARGER_BD99954=m -CONFIG_CHARGER_WILCO=m -CONFIG_BATTERY_SURFACE=m -CONFIG_CHARGER_SURFACE=m -CONFIG_BATTERY_UG3105=m -CONFIG_FUEL_GAUGE_MM8013=m -CONFIG_SENSORS_ABITUGURU=m -CONFIG_SENSORS_ABITUGURU3=m -CONFIG_SENSORS_SMPRO=m -CONFIG_SENSORS_AD7314=m -CONFIG_SENSORS_AD7414=m -CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1025=m -CONFIG_SENSORS_ADM1026=m -CONFIG_SENSORS_ADM1029=m -CONFIG_SENSORS_ADM1031=m -CONFIG_SENSORS_ADM1177=m -CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_ADT7310=m -CONFIG_SENSORS_ADT7410=m -CONFIG_SENSORS_ADT7411=m -CONFIG_SENSORS_ADT7462=m -CONFIG_SENSORS_ADT7470=m -CONFIG_SENSORS_ADT7475=m -CONFIG_SENSORS_AHT10=m -CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m -CONFIG_SENSORS_AS370=m -CONFIG_SENSORS_ASC7621=m -CONFIG_SENSORS_AXI_FAN_CONTROL=m -CONFIG_SENSORS_K8TEMP=m -CONFIG_SENSORS_K10TEMP=m -CONFIG_SENSORS_KBATT=m -CONFIG_SENSORS_KFAN=m -CONFIG_SENSORS_FAM15H_POWER=m -CONFIG_SENSORS_APPLESMC=m -CONFIG_SENSORS_ASB100=m -CONFIG_SENSORS_ATXP1=m -CONFIG_SENSORS_CGBC=m -CONFIG_SENSORS_CORSAIR_CPRO=m -CONFIG_SENSORS_CORSAIR_PSU=m -CONFIG_SENSORS_DRIVETEMP=y -CONFIG_SENSORS_DS620=m -CONFIG_SENSORS_DS1621=m -CONFIG_SENSORS_DELL_SMM=m -CONFIG_SENSORS_DA9052_ADC=m -CONFIG_SENSORS_DA9055=m -CONFIG_SENSORS_I5K_AMB=m -CONFIG_SENSORS_F71805F=m -CONFIG_SENSORS_F71882FG=m -CONFIG_SENSORS_F75375S=m -CONFIG_SENSORS_MC13783_ADC=m -CONFIG_SENSORS_FSCHMD=m -CONFIG_SENSORS_FTSTEUTATES=m -CONFIG_SENSORS_GIGABYTE_WATERFORCE=m -CONFIG_SENSORS_GL518SM=m -CONFIG_SENSORS_GL520SM=m -CONFIG_SENSORS_G760A=m -CONFIG_SENSORS_G762=m -CONFIG_SENSORS_HIH6130=m -CONFIG_SENSORS_HS3001=m -CONFIG_SENSORS_HTU31=m -CONFIG_SENSORS_IBMAEM=m -CONFIG_SENSORS_IBMPEX=m -CONFIG_SENSORS_IIO_HWMON=m -CONFIG_SENSORS_I5500=m -CONFIG_SENSORS_CORETEMP=m -CONFIG_SENSORS_ISL28022=m -CONFIG_SENSORS_IT87=m -CONFIG_SENSORS_JC42=m -CONFIG_SENSORS_POWERZ=m -CONFIG_SENSORS_POWR1220=m -CONFIG_SENSORS_LENOVO_EC=m -CONFIG_SENSORS_LINEAGE=m -CONFIG_SENSORS_LTC2945=m -CONFIG_SENSORS_LTC2947_I2C=m -CONFIG_SENSORS_LTC2947_SPI=m -CONFIG_SENSORS_LTC2990=m -CONFIG_SENSORS_LTC2991=m -CONFIG_SENSORS_LTC2992=m -CONFIG_SENSORS_LTC4151=m -CONFIG_SENSORS_LTC4215=m -CONFIG_SENSORS_LTC4222=m -CONFIG_SENSORS_LTC4245=m -CONFIG_SENSORS_LTC4260=m -CONFIG_SENSORS_LTC4261=m -CONFIG_SENSORS_MAX1111=m -CONFIG_SENSORS_MAX127=m -CONFIG_SENSORS_MAX16065=m -CONFIG_SENSORS_MAX1619=m -CONFIG_SENSORS_MAX1668=m -CONFIG_SENSORS_MAX197=m -CONFIG_SENSORS_MAX31722=m -CONFIG_SENSORS_MAX31730=m -CONFIG_SENSORS_MAX31760=m -CONFIG_MAX31827=m -CONFIG_SENSORS_MAX6620=m -CONFIG_SENSORS_MAX6621=m -CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6650=m -CONFIG_SENSORS_MAX6697=m -CONFIG_SENSORS_MAX31790=m -CONFIG_SENSORS_MAX77705=m -CONFIG_SENSORS_MC34VR500=m -CONFIG_SENSORS_MCP3021=m -CONFIG_SENSORS_TC654=m -CONFIG_SENSORS_TPS23861=m -CONFIG_SENSORS_MENF21BMC_HWMON=m -CONFIG_SENSORS_MR75203=m -CONFIG_SENSORS_ADCXX=m -CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM70=m -CONFIG_SENSORS_LM73=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM77=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM80=m -CONFIG_SENSORS_LM83=m -CONFIG_SENSORS_LM85=m -CONFIG_SENSORS_LM87=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_LM92=m -CONFIG_SENSORS_LM93=m -CONFIG_SENSORS_LM95234=m -CONFIG_SENSORS_LM95241=m -CONFIG_SENSORS_LM95245=m -CONFIG_SENSORS_PC87360=m -CONFIG_SENSORS_PC87427=m -CONFIG_SENSORS_NTC_THERMISTOR=m -CONFIG_SENSORS_NCT6683=m -CONFIG_SENSORS_NCT6775=m -CONFIG_SENSORS_NCT6775_I2C=m -CONFIG_SENSORS_NCT7363=m -CONFIG_SENSORS_NCT7802=m -CONFIG_SENSORS_NCT7904=m -CONFIG_SENSORS_NPCM7XX=m -CONFIG_SENSORS_NZXT_KRAKEN2=m -CONFIG_SENSORS_NZXT_SMART2=m -CONFIG_SENSORS_OCC_P8_I2C=m -CONFIG_SENSORS_PCF8591=m -CONFIG_PMBUS=m -CONFIG_SENSORS_ACBEL_FSG032=m -CONFIG_SENSORS_ADM1266=m -CONFIG_SENSORS_ADM1275=m -CONFIG_SENSORS_ADP1050=m -CONFIG_SENSORS_BEL_PFE=m -CONFIG_SENSORS_BPA_RS600=m -CONFIG_SENSORS_CRPS=m -CONFIG_SENSORS_DELTA_AHE50DC_FAN=m -CONFIG_SENSORS_FSP_3Y=m -CONFIG_SENSORS_IBM_CFFPS=m -CONFIG_SENSORS_DPS920AB=m -CONFIG_SENSORS_INA233=m -CONFIG_SENSORS_INSPUR_IPSPS=m -CONFIG_SENSORS_IR35221=m -CONFIG_SENSORS_IR36021=m -CONFIG_SENSORS_IR38064=m -CONFIG_SENSORS_IR38064_REGULATOR=y -CONFIG_SENSORS_IRPS5401=m -CONFIG_SENSORS_ISL68137=m -CONFIG_SENSORS_LM25066=m -CONFIG_SENSORS_LM25066_REGULATOR=y -CONFIG_SENSORS_LT3074=m -CONFIG_SENSORS_LT3074_REGULATOR=m -CONFIG_SENSORS_LT7182S=m -CONFIG_SENSORS_LTC2978=m -CONFIG_SENSORS_LTC2978_REGULATOR=y -CONFIG_SENSORS_LTC3815=m -CONFIG_SENSORS_LTC4286=y -CONFIG_SENSORS_MAX15301=m -CONFIG_SENSORS_MAX16064=m -CONFIG_SENSORS_MAX16601=m -CONFIG_SENSORS_MAX20730=m -CONFIG_SENSORS_MAX20751=m -CONFIG_SENSORS_MAX31785=m -CONFIG_SENSORS_MAX34440=m -CONFIG_SENSORS_MAX8688=m -CONFIG_SENSORS_MP2856=m -CONFIG_SENSORS_MP2888=m -CONFIG_SENSORS_MP2891=m -CONFIG_SENSORS_MP2975=m -CONFIG_SENSORS_MP2993=m -CONFIG_SENSORS_MP2975_REGULATOR=y -CONFIG_SENSORS_MP5023=m -CONFIG_SENSORS_MP5920=m -CONFIG_SENSORS_MP5990=m -CONFIG_SENSORS_MP9941=m -CONFIG_SENSORS_MPQ7932_REGULATOR=y -CONFIG_SENSORS_MPQ7932=m -CONFIG_SENSORS_PIM4328=m -CONFIG_SENSORS_PLI1209BC=m -CONFIG_SENSORS_PLI1209BC_REGULATOR=y -CONFIG_SENSORS_PM6764TR=m -CONFIG_SENSORS_PXE1610=m -CONFIG_SENSORS_Q54SJ108A2=m -CONFIG_SENSORS_STPDDC60=m -CONFIG_SENSORS_TDA38640=m -CONFIG_SENSORS_TDA38640_REGULATOR=y -CONFIG_SENSORS_TPS25990=m -CONFIG_SENSORS_TPS40422=m -CONFIG_SENSORS_TPS53679=m -CONFIG_SENSORS_TPS546D24=m -CONFIG_SENSORS_UCD9000=m -CONFIG_SENSORS_UCD9200=m -CONFIG_SENSORS_XDP710=m -CONFIG_SENSORS_XDPE152=m -CONFIG_SENSORS_XDPE122=m -CONFIG_SENSORS_XDPE122_REGULATOR=y -CONFIG_SENSORS_ZL6100=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_QNAP_MCU_HWMON=m -CONFIG_SENSORS_SBTSI=m -CONFIG_SENSORS_SHT15=m -CONFIG_SENSORS_SHT21=m -CONFIG_SENSORS_SHT3x=m -CONFIG_SENSORS_SHT4x=m -CONFIG_SENSORS_SHTC1=m -CONFIG_SENSORS_SIS5595=m -CONFIG_SENSORS_SY7636A=m -CONFIG_SENSORS_DME1737=m -CONFIG_SENSORS_EMC1403=m -CONFIG_SENSORS_EMC2103=m -CONFIG_SENSORS_EMC2305=m -CONFIG_SENSORS_EMC6W201=m -CONFIG_SENSORS_SMSC47M1=m -CONFIG_SENSORS_SMSC47M192=m -CONFIG_SENSORS_SMSC47B397=m -CONFIG_SENSORS_SCH5627=m -CONFIG_SENSORS_SCH5636=m -CONFIG_SENSORS_STTS751=m -CONFIG_SENSORS_SURFACE_TEMP=m -CONFIG_SENSORS_ADC128D818=m -CONFIG_SENSORS_ADS7828=m -CONFIG_SENSORS_ADS7871=m -CONFIG_SENSORS_AMC6821=m -CONFIG_SENSORS_INA209=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA238=m -CONFIG_SENSORS_INA3221=m -CONFIG_SENSORS_SPD5118=m -CONFIG_SENSORS_SPD5118_DETECT=y -CONFIG_SENSORS_TC74=m -CONFIG_SENSORS_THMC50=m -CONFIG_SENSORS_TMP102=m -CONFIG_SENSORS_TMP103=m -CONFIG_SENSORS_TMP108=m -CONFIG_SENSORS_TMP401=m -CONFIG_SENSORS_TMP421=m -CONFIG_SENSORS_TMP464=m -CONFIG_SENSORS_TMP513=m -CONFIG_SENSORS_VIA_CPUTEMP=m -CONFIG_SENSORS_VIA686A=m -CONFIG_SENSORS_VT1211=m -CONFIG_SENSORS_VT8231=m -CONFIG_SENSORS_W83773G=m -CONFIG_SENSORS_W83781D=m -CONFIG_SENSORS_W83791D=m -CONFIG_SENSORS_W83792D=m -CONFIG_SENSORS_W83793=m -CONFIG_SENSORS_W83795=m -CONFIG_SENSORS_W83L785TS=m -CONFIG_SENSORS_W83L786NG=m -CONFIG_SENSORS_W83627HF=m -CONFIG_SENSORS_W83627EHF=m -CONFIG_SENSORS_WM831X=m -CONFIG_SENSORS_WM8350=m -CONFIG_SENSORS_XGENE=m -CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m -CONFIG_SENSORS_ACPI_POWER=m -CONFIG_SENSORS_ATK0110=m -CONFIG_SENSORS_ASUS_WMI=m -CONFIG_SENSORS_ASUS_EC=m -CONFIG_SENSORS_HP_WMI=m -CONFIG_THERMAL_DEBUGFS=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_PCIE_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_INTEL_POWERCLAMP=m -CONFIG_INTEL_SOC_DTS_THERMAL=m -CONFIG_INT340X_THERMAL=m -CONFIG_INT3406_THERMAL=m -CONFIG_INTEL_BXT_PMIC_THERMAL=m -CONFIG_INTEL_PCH_THERMAL=m -CONFIG_INTEL_TCC_COOLING=m -CONFIG_INTEL_HFI_THERMAL=y -CONFIG_GENERIC_ADC_THERMAL=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_SYSFS=y -CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_DA9052_WATCHDOG=m -CONFIG_DA9055_WATCHDOG=m -CONFIG_DA9063_WATCHDOG=m -CONFIG_DA9062_WATCHDOG=m -CONFIG_LENOVO_SE10_WDT=m -CONFIG_LENOVO_SE30_WDT=m -CONFIG_MENF21BMC_WATCHDOG=m -CONFIG_MENZ069_WATCHDOG=m -CONFIG_WDAT_WDT=m -CONFIG_WM831X_WATCHDOG=m -CONFIG_WM8350_WATCHDOG=m -CONFIG_XILINX_WATCHDOG=m -CONFIG_ZIIRAVE_WATCHDOG=m -CONFIG_RAVE_SP_WATCHDOG=m -CONFIG_CADENCE_WATCHDOG=m -CONFIG_DW_WATCHDOG=m -CONFIG_TWL4030_WATCHDOG=m -CONFIG_MAX63XX_WATCHDOG=m -CONFIG_RETU_WATCHDOG=m -CONFIG_ACQUIRE_WDT=m -CONFIG_ADVANTECH_WDT=m -CONFIG_ADVANTECH_EC_WDT=m -CONFIG_ALIM1535_WDT=m -CONFIG_ALIM7101_WDT=m -CONFIG_EBC_C384_WDT=m -CONFIG_EXAR_WDT=m -CONFIG_F71808E_WDT=m -CONFIG_SP5100_TCO=m -CONFIG_SBC_FITPC2_WATCHDOG=m -CONFIG_EUROTECH_WDT=m -CONFIG_IB700_WDT=m -CONFIG_IBMASR=m -CONFIG_WAFER_WDT=m -CONFIG_I6300ESB_WDT=m -CONFIG_IE6XX_WDT=m -CONFIG_INTEL_OC_WATCHDOG=m -CONFIG_ITCO_WDT=m -CONFIG_ITCO_VENDOR_SUPPORT=y -CONFIG_IT8712F_WDT=m -CONFIG_IT87_WDT=m -CONFIG_HP_WATCHDOG=m -CONFIG_KEMPLD_WDT=m -CONFIG_SC1200_WDT=m -CONFIG_PC87413_WDT=m -CONFIG_NV_TCO=m -CONFIG_60XX_WDT=m -CONFIG_SMSC_SCH311X_WDT=m -CONFIG_SMSC37B787_WDT=m -CONFIG_TQMX86_WDT=m -CONFIG_VIA_WDT=m -CONFIG_W83627HF_WDT=m -CONFIG_W83877F_WDT=m -CONFIG_W83977F_WDT=m -CONFIG_MACHZ_WDT=m -CONFIG_SBC_EPX_C3_WATCHDOG=m -CONFIG_INTEL_MEI_WDT=m -CONFIG_NI903X_WDT=m -CONFIG_NIC7018_WDT=m -CONFIG_MEN_A21_WDT=m -CONFIG_XEN_WDT=m -CONFIG_PCIPCWATCHDOG=m -CONFIG_WDTPCI=m -CONFIG_USBPCWATCHDOG=m -CONFIG_SSB_SDIOHOST=y -CONFIG_SSB_DRIVER_GPIO=y -CONFIG_BCMA_HOST_SOC=y -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_MFD_AS3711=y -CONFIG_MFD_SMPRO=m -CONFIG_PMIC_ADP5520=y -CONFIG_MFD_AAT2870_CORE=y -CONFIG_MFD_BCM590XX=m -CONFIG_MFD_BD9571MWV=m -CONFIG_MFD_AXP20X_I2C=m -CONFIG_MFD_CGBC=m -CONFIG_MFD_CS40L50_I2C=m -CONFIG_MFD_CS40L50_SPI=m -CONFIG_MFD_CS42L43_I2C=m -CONFIG_MFD_MADERA=m -CONFIG_MFD_MADERA_I2C=m -CONFIG_MFD_MADERA_SPI=m -CONFIG_PMIC_DA903X=y -CONFIG_MFD_DA9052_SPI=y -CONFIG_MFD_DA9052_I2C=y -CONFIG_MFD_DA9055=y -CONFIG_MFD_DA9062=m -CONFIG_MFD_DA9063=y -CONFIG_MFD_DA9150=m -CONFIG_MFD_DLN2=m -CONFIG_MFD_MC13XXX_SPI=m -CONFIG_MFD_MC13XXX_I2C=m -CONFIG_MFD_MP2629=m -CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m -CONFIG_LPC_ICH=m -CONFIG_INTEL_SOC_PMIC=y -CONFIG_INTEL_SOC_PMIC_BXTWC=m -CONFIG_INTEL_SOC_PMIC_CHTWC=y -CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m -CONFIG_INTEL_SOC_PMIC_MRFLD=m -CONFIG_MFD_INTEL_LPSS_ACPI=m -CONFIG_MFD_INTEL_LPSS_PCI=m -CONFIG_MFD_INTEL_PMC_BXT=m -CONFIG_MFD_IQS62X=m -CONFIG_MFD_JANZ_CMODIO=m -CONFIG_MFD_KEMPLD=m -CONFIG_MFD_88PM800=m -CONFIG_MFD_88PM805=m -CONFIG_MFD_88PM860X=y -CONFIG_MFD_MAX14577=y -CONFIG_MFD_MAX77541=m -CONFIG_MFD_MAX77693=y -CONFIG_MFD_MAX77705=m -CONFIG_MFD_MAX77843=y -CONFIG_MFD_MAX8907=m -CONFIG_MFD_MAX8925=y -CONFIG_MFD_MAX8997=y -CONFIG_MFD_MAX8998=y -CONFIG_MFD_MT6360=m -CONFIG_MFD_MT6370=m -CONFIG_MFD_MT6397=m -CONFIG_MFD_MENF21BMC=m -CONFIG_EZX_PCAP=y -CONFIG_MFD_VIPERBOARD=m -CONFIG_MFD_RETU=m -CONFIG_MFD_SY7636A=m -CONFIG_MFD_RT4831=m -CONFIG_MFD_RT5033=m -CONFIG_MFD_RT5120=m -CONFIG_MFD_RC5T583=y -CONFIG_MFD_SI476X_CORE=m -CONFIG_MFD_SM501=m -CONFIG_MFD_SM501_GPIO=y -CONFIG_MFD_SKY81452=m -CONFIG_MFD_LP3943=m -CONFIG_MFD_LP8788=y -CONFIG_MFD_TI_LMU=m -CONFIG_MFD_PALMAS=y -CONFIG_TPS6105X=m -CONFIG_TPS65010=m -CONFIG_TPS6507X=m -CONFIG_MFD_TPS65086=m -CONFIG_MFD_TPS65090=y -CONFIG_MFD_TI_LP873X=m -CONFIG_MFD_TPS6586X=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_TPS65912_I2C=y -CONFIG_MFD_TPS65912_SPI=y -CONFIG_MFD_TPS6594_I2C=y -CONFIG_MFD_TPS6594_SPI=y -CONFIG_TWL4030_CORE=y -CONFIG_TWL6040_CORE=y -CONFIG_MFD_WL1273_CORE=m -CONFIG_MFD_LM3533=m -CONFIG_MFD_TQMX86=m -CONFIG_MFD_ARIZONA_I2C=m -CONFIG_MFD_ARIZONA_SPI=m -CONFIG_MFD_CS47L24=y -CONFIG_MFD_WM5102=y -CONFIG_MFD_WM5110=y -CONFIG_MFD_WM8997=y -CONFIG_MFD_WM8998=y -CONFIG_MFD_WM8400=y -CONFIG_MFD_WM831X_I2C=y -CONFIG_MFD_WM831X_SPI=y -CONFIG_MFD_WM8350_I2C=y -CONFIG_MFD_WM8994=m -CONFIG_MFD_ATC260X_I2C=m -CONFIG_RAVE_SP_CORE=m -CONFIG_MFD_INTEL_M10_BMC_SPI=m -CONFIG_MFD_INTEL_M10_BMC_PMCI=m -CONFIG_MFD_QNAP_MCU=m -CONFIG_MFD_UPBOARD_FPGA=m -CONFIG_REGULATOR_VIRTUAL_CONSUMER=m -CONFIG_REGULATOR_USERSPACE_CONSUMER=m -CONFIG_REGULATOR_88PG86X=m -CONFIG_REGULATOR_88PM800=m -CONFIG_REGULATOR_88PM8607=m -CONFIG_REGULATOR_ACT8865=m -CONFIG_REGULATOR_AD5398=m -CONFIG_REGULATOR_ADP5055=m -CONFIG_REGULATOR_AAT2870=m -CONFIG_REGULATOR_ARIZONA_LDO1=m -CONFIG_REGULATOR_ARIZONA_MICSUPP=m -CONFIG_REGULATOR_AS3711=m -CONFIG_REGULATOR_ATC260X=m -CONFIG_REGULATOR_AW37503=m -CONFIG_REGULATOR_AXP20X=m -CONFIG_REGULATOR_BCM590XX=m -CONFIG_REGULATOR_BD9571MWV=m -CONFIG_REGULATOR_DA903X=m -CONFIG_REGULATOR_DA9052=m -CONFIG_REGULATOR_DA9055=m -CONFIG_REGULATOR_DA9062=m -CONFIG_REGULATOR_DA9210=m -CONFIG_REGULATOR_DA9211=m -CONFIG_REGULATOR_FAN53555=m -CONFIG_REGULATOR_GPIO=m -CONFIG_REGULATOR_ISL9305=m -CONFIG_REGULATOR_ISL6271A=m -CONFIG_REGULATOR_LM363X=m -CONFIG_REGULATOR_LP3971=m -CONFIG_REGULATOR_LP3972=m -CONFIG_REGULATOR_LP872X=m -CONFIG_REGULATOR_LP8755=m -CONFIG_REGULATOR_LP8788=m -CONFIG_REGULATOR_LTC3589=m -CONFIG_REGULATOR_LTC3676=m -CONFIG_REGULATOR_MAX14577=m -CONFIG_REGULATOR_MAX1586=m -CONFIG_REGULATOR_MAX77503=m -CONFIG_REGULATOR_MAX77541=m -CONFIG_REGULATOR_MAX77857=m -CONFIG_REGULATOR_MAX8649=m -CONFIG_REGULATOR_MAX8660=m -CONFIG_REGULATOR_MAX8893=m -CONFIG_REGULATOR_MAX8907=m -CONFIG_REGULATOR_MAX8925=m -CONFIG_REGULATOR_MAX8952=m -CONFIG_REGULATOR_MAX8997=m -CONFIG_REGULATOR_MAX8998=m -CONFIG_REGULATOR_MAX20086=m -CONFIG_REGULATOR_MAX20411=m -CONFIG_REGULATOR_MAX77693=m -CONFIG_REGULATOR_MAX77826=m -CONFIG_REGULATOR_MC13783=m -CONFIG_REGULATOR_MC13892=m -CONFIG_REGULATOR_MP8859=m -CONFIG_REGULATOR_MT6311=m -CONFIG_REGULATOR_MT6315=m -CONFIG_REGULATOR_MT6323=m -CONFIG_REGULATOR_MT6331=m -CONFIG_REGULATOR_MT6332=m -CONFIG_REGULATOR_MT6357=m -CONFIG_REGULATOR_MT6358=m -CONFIG_REGULATOR_MT6359=m -CONFIG_REGULATOR_MT6360=m -CONFIG_REGULATOR_MT6370=m -CONFIG_REGULATOR_MT6397=m -CONFIG_REGULATOR_PALMAS=m -CONFIG_REGULATOR_PCA9450=m -CONFIG_REGULATOR_PF9453=m -CONFIG_REGULATOR_PCAP=m -CONFIG_REGULATOR_PV88060=m -CONFIG_REGULATOR_PV88080=m -CONFIG_REGULATOR_PV88090=m -CONFIG_REGULATOR_PWM=m -CONFIG_REGULATOR_QCOM_SPMI=m -CONFIG_REGULATOR_QCOM_USB_VBUS=m -CONFIG_REGULATOR_RAA215300=m -CONFIG_REGULATOR_RC5T583=m -CONFIG_REGULATOR_RT4801=m -CONFIG_REGULATOR_RT4803=m -CONFIG_REGULATOR_RT4831=m -CONFIG_REGULATOR_RT5033=m -CONFIG_REGULATOR_RT5120=m -CONFIG_REGULATOR_RT5190A=m -CONFIG_REGULATOR_RT5739=m -CONFIG_REGULATOR_RT5759=m -CONFIG_REGULATOR_RT6160=m -CONFIG_REGULATOR_RT6190=m -CONFIG_REGULATOR_RT6245=m -CONFIG_REGULATOR_RTQ2134=m -CONFIG_REGULATOR_RTMV20=m -CONFIG_REGULATOR_RTQ6752=m -CONFIG_REGULATOR_RTQ2208=m -CONFIG_REGULATOR_SKY81452=m -CONFIG_REGULATOR_SLG51000=m -CONFIG_REGULATOR_SY7636A=m -CONFIG_REGULATOR_TPS51632=m -CONFIG_REGULATOR_TPS62360=m -CONFIG_REGULATOR_TPS65023=m -CONFIG_REGULATOR_TPS6507X=m -CONFIG_REGULATOR_TPS65086=m -CONFIG_REGULATOR_TPS65090=m -CONFIG_REGULATOR_TPS65132=m -CONFIG_REGULATOR_TPS6524X=m -CONFIG_REGULATOR_TPS6586X=m -CONFIG_REGULATOR_TPS65910=m -CONFIG_REGULATOR_TPS65912=m -CONFIG_REGULATOR_TPS68470=m -CONFIG_REGULATOR_TWL4030=m -CONFIG_REGULATOR_WM831X=m -CONFIG_REGULATOR_WM8350=m -CONFIG_REGULATOR_WM8400=m -CONFIG_REGULATOR_WM8994=m -CONFIG_REGULATOR_QCOM_LABIBB=m -CONFIG_RC_CORE=m -CONFIG_LIRC=y -CONFIG_RC_DECODERS=y -CONFIG_IR_IMON_DECODER=m -CONFIG_IR_JVC_DECODER=m -CONFIG_IR_MCE_KBD_DECODER=m -CONFIG_IR_NEC_DECODER=m -CONFIG_IR_RC5_DECODER=m -CONFIG_IR_RC6_DECODER=m -CONFIG_IR_RCMM_DECODER=m -CONFIG_IR_SANYO_DECODER=m -CONFIG_IR_SHARP_DECODER=m -CONFIG_IR_SONY_DECODER=m -CONFIG_IR_XMP_DECODER=m -CONFIG_RC_DEVICES=y -CONFIG_IR_ENE=m -CONFIG_IR_FINTEK=m -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_IMON=m -CONFIG_IR_IMON_RAW=m -CONFIG_IR_ITE_CIR=m -CONFIG_IR_MCEUSB=m -CONFIG_IR_NUVOTON=m -CONFIG_IR_REDRAT3=m -CONFIG_IR_SERIAL=m -CONFIG_IR_SERIAL_TRANSMITTER=y -CONFIG_IR_STREAMZAP=m -CONFIG_IR_TOY=m -CONFIG_IR_TTUSBIR=m -CONFIG_IR_WINBOND_CIR=m -CONFIG_RC_ATI_REMOTE=m -CONFIG_RC_LOOPBACK=m -CONFIG_RC_XBOX_DVD=m -CONFIG_MEDIA_CEC_RC=y -CONFIG_CEC_CH7322=m -CONFIG_CEC_CROS_EC=m -CONFIG_CEC_GPIO=m -CONFIG_CEC_SECO=m -CONFIG_CEC_SECO_RC=y -CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC=m -CONFIG_USB_PULSE8_CEC=m -CONFIG_USB_RAINSHADOW_CEC=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y -CONFIG_V4L2_FLASH_LED_CLASS=m -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_GSPCA=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_GL860=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_PWC=m -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m -CONFIG_USB_VIDEO_CLASS=m -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_GO7007_USB=m -CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_STK1160=m -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_AU0828_RC=y -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_DVB_AS102=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_DVB_USB=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_CXUSB_ANALOG=y -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_VP7045=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -CONFIG_MEDIA_PCI_SUPPORT=y -CONFIG_VIDEO_MGB4=m -CONFIG_VIDEO_SOLO6X10=m -CONFIG_VIDEO_TW5864=m -CONFIG_VIDEO_TW68=m -CONFIG_VIDEO_TW686X=m -CONFIG_VIDEO_DT3155=m -CONFIG_VIDEO_IVTV=m -CONFIG_VIDEO_IVTV_ALSA=m -CONFIG_VIDEO_FB_IVTV=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_MXB=m -CONFIG_VIDEO_BT848=m -CONFIG_DVB_BT8XX=m -CONFIG_VIDEO_COBALT=m -CONFIG_VIDEO_CX18=m -CONFIG_VIDEO_CX18_ALSA=m -CONFIG_VIDEO_CX23885=m -CONFIG_MEDIA_ALTERA_CI=m -CONFIG_VIDEO_CX25821=m -CONFIG_VIDEO_CX25821_ALSA=m -CONFIG_VIDEO_CX88=m -CONFIG_VIDEO_CX88_ALSA=m -CONFIG_VIDEO_CX88_BLACKBIRD=m -CONFIG_VIDEO_CX88_DVB=m -CONFIG_VIDEO_SAA7134=m -CONFIG_VIDEO_SAA7134_ALSA=m -CONFIG_VIDEO_SAA7134_DVB=m -CONFIG_VIDEO_SAA7134_GO7007=m -CONFIG_VIDEO_SAA7164=m -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -CONFIG_DVB_DDBRIDGE=m -CONFIG_DVB_DM1105=m -CONFIG_MANTIS_CORE=m -CONFIG_DVB_MANTIS=m -CONFIG_DVB_HOPPER=m -CONFIG_DVB_NETUP_UNIDVB=m -CONFIG_DVB_NGENE=m -CONFIG_DVB_PLUTO2=m -CONFIG_DVB_PT1=m -CONFIG_DVB_PT3=m -CONFIG_DVB_SMIPCIE=m -CONFIG_DVB_BUDGET_CORE=m -CONFIG_DVB_BUDGET=m -CONFIG_DVB_BUDGET_CI=m -CONFIG_DVB_BUDGET_AV=m -CONFIG_VIDEO_IPU3_CIO2=m -CONFIG_VIDEO_INTEL_IPU6=m -CONFIG_INTEL_VSC=m -CONFIG_IPU_BRIDGE=m -CONFIG_RADIO_MAXIRADIO=m -CONFIG_RADIO_SAA7706H=m -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_RADIO_SI4713=m -CONFIG_RADIO_SI476X=m -CONFIG_RADIO_TEA5764=m -CONFIG_RADIO_TEF6862=m -CONFIG_USB_DSBR=m -CONFIG_USB_KEENE=m -CONFIG_USB_MA901=m -CONFIG_USB_MR800=m -CONFIG_USB_RAREMONO=m -CONFIG_RADIO_SI470X=m -CONFIG_USB_SI470X=m -CONFIG_I2C_SI470X=m -CONFIG_USB_SI4713=m -CONFIG_PLATFORM_SI4713=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_DVB_PLATFORM_DRIVERS=y -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m -CONFIG_VIDEO_CADENCE_CSI2RX=m -CONFIG_VIDEO_CADENCE_CSI2TX=m -CONFIG_VIDEO_CAFE_CCIC=m -CONFIG_VIDEO_RP1_CFE=m -CONFIG_VIDEO_VIA_CAMERA=m -CONFIG_SMS_SDIO_DRV=m -CONFIG_V4L_TEST_DRIVERS=y -CONFIG_VIDEO_VIM2M=m -CONFIG_VIDEO_VICODEC=m -CONFIG_VIDEO_VIVID=m -CONFIG_VIDEO_VIVID_CEC=y -# CONFIG_VIDEO_VIVID_OSD is not set -CONFIG_DVB_FIREDTV=m -CONFIG_SMS_SIANO_DEBUGFS=y -CONFIG_VIDEO_ALVIUM_CSI2=m -CONFIG_VIDEO_AR0521=m -CONFIG_VIDEO_GC0308=m -CONFIG_VIDEO_GC05A2=m -CONFIG_VIDEO_GC08A3=m -CONFIG_VIDEO_GC2145=m -CONFIG_VIDEO_HI556=m -CONFIG_VIDEO_HI846=m -CONFIG_VIDEO_HI847=m -CONFIG_VIDEO_IMX208=m -CONFIG_VIDEO_IMX214=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_IMX258=m -CONFIG_VIDEO_IMX274=m -CONFIG_VIDEO_IMX283=m -CONFIG_VIDEO_IMX290=m -CONFIG_VIDEO_IMX296=m -CONFIG_VIDEO_IMX319=m -CONFIG_VIDEO_IMX355=m -CONFIG_VIDEO_MT9M001=m -CONFIG_VIDEO_MT9M111=m -CONFIG_VIDEO_MT9M114=m -CONFIG_VIDEO_MT9P031=m -CONFIG_VIDEO_MT9T112=m -CONFIG_VIDEO_MT9V111=m -CONFIG_VIDEO_OG01A1B=m -CONFIG_VIDEO_OV01A10=m -CONFIG_VIDEO_OV02A10=m -CONFIG_VIDEO_OV02E10=m -CONFIG_VIDEO_OV02C10=m -CONFIG_VIDEO_OV08D10=m -CONFIG_VIDEO_OV08X40=m -CONFIG_VIDEO_OV13858=m -CONFIG_VIDEO_OV13B10=m -CONFIG_VIDEO_OV2659=m -CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV2685=m -CONFIG_VIDEO_OV2740=m -CONFIG_VIDEO_OV4689=m -CONFIG_VIDEO_OV5647=m -CONFIG_VIDEO_OV5648=m -CONFIG_VIDEO_OV5670=m -CONFIG_VIDEO_OV5675=m -CONFIG_VIDEO_OV5693=m -CONFIG_VIDEO_OV5695=m -CONFIG_VIDEO_OV64A40=m -CONFIG_VIDEO_OV7251=m -CONFIG_VIDEO_OV772X=m -CONFIG_VIDEO_OV7740=m -CONFIG_VIDEO_OV8856=m -CONFIG_VIDEO_OV8858=m -CONFIG_VIDEO_OV8865=m -CONFIG_VIDEO_OV9640=m -CONFIG_VIDEO_OV9650=m -CONFIG_VIDEO_OV9734=m -CONFIG_VIDEO_RDACM20=m -CONFIG_VIDEO_RDACM21=m -CONFIG_VIDEO_RJ54N1=m -CONFIG_VIDEO_S5C73M3=m -CONFIG_VIDEO_S5K5BAF=m -CONFIG_VIDEO_S5K6A3=m -CONFIG_VIDEO_VD55G1=m -CONFIG_VIDEO_VD56G3=m -CONFIG_VIDEO_CCS=m -CONFIG_VIDEO_ET8EK8=m -CONFIG_VIDEO_THP7312=m -CONFIG_VIDEO_AD5820=m -CONFIG_VIDEO_AK7375=m -CONFIG_VIDEO_DW9714=m -CONFIG_VIDEO_DW9719=m -CONFIG_VIDEO_DW9768=m -CONFIG_VIDEO_DW9807_VCM=m -CONFIG_VIDEO_ADP1653=m -CONFIG_VIDEO_LM3560=m -CONFIG_VIDEO_LM3646=m -CONFIG_VIDEO_TDA1997X=m -CONFIG_VIDEO_TLV320AIC23B=m -CONFIG_VIDEO_ADV7180=m -CONFIG_VIDEO_ADV7183=m -CONFIG_VIDEO_ADV7604_CEC=y -CONFIG_VIDEO_ADV7842_CEC=y -CONFIG_VIDEO_BT819=m -CONFIG_VIDEO_BT856=m -CONFIG_VIDEO_BT866=m -CONFIG_VIDEO_LT6911UXE=m -CONFIG_VIDEO_KS0127=m -CONFIG_VIDEO_ML86V7667=m -CONFIG_VIDEO_SAA7110=m -CONFIG_VIDEO_TC358743=m -CONFIG_VIDEO_TC358743_CEC=y -CONFIG_VIDEO_TC358746=m -CONFIG_VIDEO_TVP514X=m -CONFIG_VIDEO_TVP7002=m -CONFIG_VIDEO_TW9900=m -CONFIG_VIDEO_TW9910=m -CONFIG_VIDEO_VPX3220=m -CONFIG_VIDEO_ADV7170=m -CONFIG_VIDEO_ADV7175=m -CONFIG_VIDEO_ADV7343=m -CONFIG_VIDEO_ADV7393=m -CONFIG_VIDEO_ADV7511_CEC=y -CONFIG_VIDEO_AK881X=m -CONFIG_VIDEO_SAA7185=m -CONFIG_VIDEO_THS8200=m -CONFIG_SDR_MAX2175=m -CONFIG_VIDEO_I2C=m -CONFIG_VIDEO_ST_MIPID02=m -CONFIG_VIDEO_THS7303=m -CONFIG_VIDEO_MAX96717=m -CONFIG_CXD2880_SPI_DRV=m -CONFIG_VIDEO_GS1662=m -CONFIG_DVB_DIB9000=m -CONFIG_DVB_S5H1432=m -CONFIG_DVB_CXD2880=m -CONFIG_DVB_MN88443X=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DVB_LNBH29=m -CONFIG_DVB_DUMMY_FE=m -CONFIG_HD44780=m -CONFIG_LCD2S=m -CONFIG_KS0108=m -CONFIG_CFAG12864B=m -CONFIG_IMG_ASCII_LCD=m -CONFIG_HT16K33=m -CONFIG_PANEL=m -CONFIG_AGP=y -CONFIG_AGP_AMD64=y -CONFIG_AGP_INTEL=y -CONFIG_AGP_SIS=m -CONFIG_AGP_VIA=y -CONFIG_VGA_SWITCHEROO=y -CONFIG_DRM=m -CONFIG_DRM_PANIC=y -CONFIG_DRM_CLIENT_LOG=y -CONFIG_DRM_LOAD_EDID_FIRMWARE=y -CONFIG_DRM_DISPLAY_DP_AUX_CEC=y -CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y -CONFIG_DRM_EFIDRM=m -CONFIG_DRM_VESADRM=m -CONFIG_DRM_RADEON=m -CONFIG_DRM_AMDGPU=m -CONFIG_DRM_AMDGPU_SI=y -CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMD_ISP=y -CONFIG_DRM_AMD_SECURE_DISPLAY=y -CONFIG_HSA_AMD=y -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_I915=m -CONFIG_DRM_I915_GVT_KVMGT=m -CONFIG_DRM_XE=m -CONFIG_DRM_VGEM=m -CONFIG_DRM_VMWGFX=m -CONFIG_DRM_GMA500=m -CONFIG_DRM_UDL=m -CONFIG_DRM_AST=m -CONFIG_DRM_QXL=m -CONFIG_DRM_VIRTIO_GPU=m -CONFIG_DRM_PANEL_AUO_A030JTN01=m -CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m -CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_ANALOGIX_ANX78XX=m -CONFIG_DRM_HISI_HIBMC=m -CONFIG_DRM_APPLETBDRM=m -CONFIG_DRM_BOCHS=m -CONFIG_DRM_CIRRUS_QEMU=m -CONFIG_DRM_GM12U320=m -CONFIG_DRM_PANEL_MIPI_DBI=m -CONFIG_TINYDRM_HX8357D=m -CONFIG_TINYDRM_ILI9163=m -CONFIG_TINYDRM_ILI9225=m -CONFIG_TINYDRM_ILI9341=m -CONFIG_TINYDRM_ILI9486=m -CONFIG_TINYDRM_MI0283QT=m -CONFIG_TINYDRM_REPAPER=m -CONFIG_TINYDRM_SHARP_MEMORY=m -CONFIG_DRM_XEN_FRONTEND=m -CONFIG_DRM_VBOXVIDEO=m -CONFIG_DRM_GUD=m -CONFIG_DRM_ST7571_I2C=m -CONFIG_DRM_ST7586=m -CONFIG_DRM_ST7735R=m -CONFIG_DRM_SSD130X=m -CONFIG_DRM_SSD130X_I2C=m -CONFIG_DRM_SSD130X_SPI=m -CONFIG_FB=y -CONFIG_FB_CIRRUS=m -CONFIG_FB_PM2=m -CONFIG_FB_PM2_FIFO_DISCONNECT=y -CONFIG_FB_CYBER2000=m -CONFIG_FB_ARC=m -CONFIG_FB_ASILIANT=y -CONFIG_FB_IMSTT=y -CONFIG_FB_VGA16=m -CONFIG_FB_UVESA=m -CONFIG_FB_VESA=y -CONFIG_FB_EFI=y -CONFIG_FB_N411=m -CONFIG_FB_HGA=m -CONFIG_FB_OPENCORES=m -CONFIG_FB_S1D13XXX=m -CONFIG_FB_RIVA=m -CONFIG_FB_RIVA_I2C=y -CONFIG_FB_I740=m -CONFIG_FB_MATROX=m -CONFIG_FB_MATROX_MILLENIUM=y -CONFIG_FB_MATROX_MYSTIQUE=y -CONFIG_FB_MATROX_G=y -CONFIG_FB_MATROX_I2C=m -CONFIG_FB_MATROX_MAVEN=m -CONFIG_FB_RADEON=m -CONFIG_FB_ATY128=m -CONFIG_FB_ATY=m -CONFIG_FB_ATY_CT=y -CONFIG_FB_ATY_GX=y -CONFIG_FB_S3=m -CONFIG_FB_SAVAGE=m -CONFIG_FB_SAVAGE_I2C=y -CONFIG_FB_SIS=m -CONFIG_FB_SIS_300=y -CONFIG_FB_SIS_315=y -CONFIG_FB_VIA=m -CONFIG_FB_VIA_X_COMPATIBILITY=y -CONFIG_FB_NEOMAGIC=m -CONFIG_FB_KYRO=m -CONFIG_FB_3DFX=m -# CONFIG_FB_3DFX_I2C is not set -CONFIG_FB_VOODOO1=m -CONFIG_FB_VT8623=m -CONFIG_FB_TRIDENT=m -CONFIG_FB_ARK=m -CONFIG_FB_PM3=m -CONFIG_FB_CARMINE=m -CONFIG_FB_SM501=m -CONFIG_FB_SMSCUFX=m -CONFIG_FB_UDL=m -CONFIG_FB_IBM_GXT4500=m -CONFIG_XEN_FBDEV_FRONTEND=m -CONFIG_FB_METRONOME=m -CONFIG_FB_MB862XX=m -CONFIG_FB_SIMPLE=y -CONFIG_FB_SSD1307=m -CONFIG_FB_SM712=m -CONFIG_LCD_CLASS_DEVICE=m -CONFIG_LCD_L4F00242T03=m -CONFIG_LCD_LMS283GF05=m -CONFIG_LCD_LTV350QV=m -CONFIG_LCD_ILI922X=m -CONFIG_LCD_TDO24M=m -CONFIG_LCD_VGG2432A4=m -CONFIG_LCD_PLATFORM=m -CONFIG_LCD_AMS369FG06=m -CONFIG_LCD_LMS501KF03=m -CONFIG_LCD_HX8357=m -CONFIG_LCD_OTM3225A=m -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_KTD253=m -CONFIG_BACKLIGHT_KTZ8866=m -CONFIG_BACKLIGHT_LM3533=m -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_DA903X=m -CONFIG_BACKLIGHT_DA9052=m -CONFIG_BACKLIGHT_MAX8925=m -CONFIG_BACKLIGHT_MT6370=m -CONFIG_BACKLIGHT_APPLE=m -CONFIG_BACKLIGHT_QCOM_WLED=m -CONFIG_BACKLIGHT_RT4831=m -CONFIG_BACKLIGHT_SAHARA=m -CONFIG_BACKLIGHT_WM831X=m -CONFIG_BACKLIGHT_ADP5520=m -CONFIG_BACKLIGHT_ADP8860=m -CONFIG_BACKLIGHT_ADP8870=m -CONFIG_BACKLIGHT_88PM860X=m -CONFIG_BACKLIGHT_AAT2870=m -CONFIG_BACKLIGHT_LM3509=m -CONFIG_BACKLIGHT_LM3630A=m -CONFIG_BACKLIGHT_LM3639=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_BACKLIGHT_LP8788=m -CONFIG_BACKLIGHT_MP3309C=m -CONFIG_BACKLIGHT_PANDORA=m -CONFIG_BACKLIGHT_SKY81452=m -CONFIG_BACKLIGHT_AS3711=m -CONFIG_BACKLIGHT_GPIO=m -CONFIG_BACKLIGHT_LV5207LP=m -CONFIG_BACKLIGHT_BD6107=m -CONFIG_BACKLIGHT_ARCXCNN=m -CONFIG_BACKLIGHT_RAVE_SP=m -CONFIG_FIRMWARE_EDID=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -CONFIG_DRM_ACCEL=y -CONFIG_DRM_ACCEL_AMDXDNA=m -CONFIG_DRM_ACCEL_HABANALABS=m -CONFIG_DRM_ACCEL_IVPU=m -CONFIG_DRM_ACCEL_QAIC=m -CONFIG_SOUND=m -# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set -CONFIG_SND=m -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_HRTIMER=m -CONFIG_SND_CTL_INPUT_VALIDATION=y -CONFIG_SND_UTIMER=y -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_DUMMY=m -CONFIG_SND_ALOOP=m -CONFIG_SND_VIRMIDI=m -CONFIG_SND_MTPAV=m -CONFIG_SND_MTS64=m -CONFIG_SND_SERIAL_U16550=m -CONFIG_SND_MPU401=m -CONFIG_SND_PORTMAN2X4=m -CONFIG_SND_AC97_POWER_SAVE=y -CONFIG_SND_AD1889=m -CONFIG_SND_ALS300=m -CONFIG_SND_ALS4000=m -CONFIG_SND_ALI5451=m -CONFIG_SND_ASIHPI=m -CONFIG_SND_ATIIXP=m -CONFIG_SND_ATIIXP_MODEM=m -CONFIG_SND_AU8810=m -CONFIG_SND_AU8820=m -CONFIG_SND_AU8830=m -CONFIG_SND_AW2=m -CONFIG_SND_AZT3328=m -CONFIG_SND_BT87X=m -CONFIG_SND_CA0106=m -CONFIG_SND_CMIPCI=m -CONFIG_SND_OXYGEN=m -CONFIG_SND_CS4281=m -CONFIG_SND_CS46XX=m -CONFIG_SND_CTXFI=m -CONFIG_SND_DARLA20=m -CONFIG_SND_GINA20=m -CONFIG_SND_LAYLA20=m -CONFIG_SND_DARLA24=m -CONFIG_SND_GINA24=m -CONFIG_SND_LAYLA24=m -CONFIG_SND_MONA=m -CONFIG_SND_MIA=m -CONFIG_SND_ECHO3G=m -CONFIG_SND_INDIGO=m -CONFIG_SND_INDIGOIO=m -CONFIG_SND_INDIGODJ=m -CONFIG_SND_INDIGOIOX=m -CONFIG_SND_INDIGODJX=m -CONFIG_SND_EMU10K1=m -CONFIG_SND_EMU10K1X=m -CONFIG_SND_ENS1370=m -CONFIG_SND_ENS1371=m -CONFIG_SND_ES1938=m -CONFIG_SND_ES1968=m -CONFIG_SND_ES1968_INPUT=y -CONFIG_SND_ES1968_RADIO=y -CONFIG_SND_FM801=m -CONFIG_SND_FM801_TEA575X_BOOL=y -CONFIG_SND_HDSP=m -CONFIG_SND_HDSPM=m -CONFIG_SND_ICE1712=m -CONFIG_SND_ICE1724=m -CONFIG_SND_INTEL8X0=m -CONFIG_SND_INTEL8X0M=m -CONFIG_SND_KORG1212=m -CONFIG_SND_LOLA=m -CONFIG_SND_LX6464ES=m -CONFIG_SND_MAESTRO3=m -CONFIG_SND_MAESTRO3_INPUT=y -CONFIG_SND_MIXART=m -CONFIG_SND_NM256=m -CONFIG_SND_PCXHR=m -CONFIG_SND_RIPTIDE=m -CONFIG_SND_RME32=m -CONFIG_SND_RME96=m -CONFIG_SND_RME9652=m -CONFIG_SND_SONICVIBES=m -CONFIG_SND_TRIDENT=m -CONFIG_SND_VIA82XX=m -CONFIG_SND_VIA82XX_MODEM=m -CONFIG_SND_VIRTUOSO=m -CONFIG_SND_VX222=m -CONFIG_SND_YMFPCI=m -CONFIG_SND_HDA_HWDEP=y -CONFIG_SND_HDA_INPUT_BEEP=y -CONFIG_SND_HDA_INPUT_BEEP_MODE=0 -CONFIG_SND_HDA_PATCH_LOADER=y -CONFIG_SND_HDA_INTEL=m -CONFIG_SND_HDA_ACPI=m -CONFIG_SND_HDA_CODEC_ANALOG=m -CONFIG_SND_HDA_CODEC_SIGMATEL=m -CONFIG_SND_HDA_CODEC_VIA=m -CONFIG_SND_HDA_CODEC_CONEXANT=m -CONFIG_SND_HDA_CODEC_SENARYTECH=m -CONFIG_SND_HDA_CODEC_CA0110=m -CONFIG_SND_HDA_CODEC_CA0132=m -CONFIG_SND_HDA_CODEC_CMEDIA=m -CONFIG_SND_HDA_CODEC_CM9825=m -CONFIG_SND_HDA_CODEC_SI3054=m -CONFIG_SND_HDA_CODEC_REALTEK=m -CONFIG_SND_HDA_CODEC_CIRRUS=m -CONFIG_SND_HDA_CODEC_CS8409=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y -CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m -CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m -CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m -CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m -CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m -CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m -CONFIG_SND_INTEL_BYT_PREFER_SOF=y -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_AUDIO_MIDI_V2=y -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_USX2Y=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_USB_US122L=m -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_AUDIO_QMI=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m -CONFIG_SND_DICE=m -CONFIG_SND_OXFW=m -CONFIG_SND_ISIGHT=m -CONFIG_SND_FIREWORKS=m -CONFIG_SND_BEBOB=m -CONFIG_SND_FIREWIRE_DIGI00X=m -CONFIG_SND_FIREWIRE_TASCAM=m -CONFIG_SND_FIREWIRE_MOTU=m -CONFIG_SND_FIREFACE=m -CONFIG_SND_VXPOCKET=m -CONFIG_SND_PDAUDIOCF=m -CONFIG_SND_SOC=m -CONFIG_SND_SOC_USB=m -CONFIG_SND_SOC_ADI_AXI_I2S=m -CONFIG_SND_SOC_ADI_AXI_SPDIF=m -CONFIG_SND_SOC_AMD_ACP=m -CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m -CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m -CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m -CONFIG_SND_SOC_AMD_ACP3x=m -CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m -CONFIG_SND_SOC_AMD_RENOIR=m -CONFIG_SND_SOC_AMD_RENOIR_MACH=m -CONFIG_SND_SOC_AMD_ACP5x=m -CONFIG_SND_SOC_AMD_VANGOGH_MACH=m -CONFIG_SND_SOC_AMD_ACP6x=m -CONFIG_SND_SOC_AMD_YC_MACH=m -CONFIG_SND_SOC_AMD_ACP_COMMON=m -CONFIG_SND_SOC_AMD_ACP_PCI=m -CONFIG_SND_AMD_ASOC_RENOIR=m -CONFIG_SND_AMD_ASOC_REMBRANDT=m -CONFIG_SND_AMD_ASOC_ACP63=m -CONFIG_SND_AMD_ASOC_ACP70=m -CONFIG_SND_SOC_AMD_LEGACY_MACH=m -CONFIG_SND_SOC_AMD_SOF_MACH=m -CONFIG_SND_SOC_AMD_SOF_SDW_MACH=m -CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH=m -CONFIG_SND_SOC_AMD_RPL_ACP6x=m -CONFIG_SND_SOC_AMD_PS=m -CONFIG_SND_SOC_AMD_PS_MACH=m -CONFIG_SND_BCM63XX_I2S_WHISTLER=m -CONFIG_SND_DESIGNWARE_I2S=m -CONFIG_SND_SOC_FSL_ASRC=m -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_FSL_MQS=m -CONFIG_SND_SOC_FSL_AUDMIX=m -CONFIG_SND_SOC_FSL_SSI=m -CONFIG_SND_SOC_FSL_SPDIF=m -CONFIG_SND_SOC_FSL_ESAI=m -CONFIG_SND_SOC_FSL_MICFIL=m -CONFIG_SND_SOC_FSL_EASRC=m -CONFIG_SND_SOC_FSL_XCVR=m -CONFIG_SND_SOC_IMX_AUDMUX=m -CONFIG_SND_SOC_CHV3_I2S=m -CONFIG_SND_I2S_HI6210_I2S=m -CONFIG_SND_SOC_INTEL_CATPT=m -CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m -CONFIG_SND_SOC_INTEL_AVS=m -CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m -CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m -CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336=m -CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m -CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m -CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=m -CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m -CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m -CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m -CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A=m -CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663=m -CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m -CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m -CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y -CONFIG_SND_SOC_INTEL_HASWELL_MACH=m -CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m -CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m -CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m -CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m -CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m -CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m -CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m -CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m -CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m -CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m -CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m -CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m -CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m -CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m -CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m -CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m -CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m -CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m -CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m -CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m -CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=m -CONFIG_SND_SOC_MTK_BTCVSD=m -CONFIG_SND_SOC_XILINX_I2S=m -CONFIG_SND_SOC_XTFPGA_I2S=m -CONFIG_SND_SOC_SOF_TOPLEVEL=y -CONFIG_SND_SOC_SOF_PCI=m -CONFIG_SND_SOC_SOF_ACPI=m -CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m -CONFIG_SND_SOC_SOF_AMD_RENOIR=m -CONFIG_SND_SOC_SOF_AMD_VANGOGH=m -CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m -CONFIG_SND_SOC_SOF_AMD_ACP63=m -CONFIG_SND_SOC_SOF_AMD_ACP70=m -CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y -CONFIG_SND_SOC_SOF_HDA_LINK=y -CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y -CONFIG_SND_SOC_AC97_CODEC=m -CONFIG_SND_SOC_ADAU1372_I2C=m -CONFIG_SND_SOC_ADAU1372_SPI=m -CONFIG_SND_SOC_ADAU1373=m -CONFIG_SND_SOC_ADAU1701=m -CONFIG_SND_SOC_ADAU1761_I2C=m -CONFIG_SND_SOC_ADAU1761_SPI=m -CONFIG_SND_SOC_ADAU7118_HW=m -CONFIG_SND_SOC_ADAU7118_I2C=m -CONFIG_SND_SOC_AK4104=m -CONFIG_SND_SOC_AK4118=m -CONFIG_SND_SOC_AK4375=m -CONFIG_SND_SOC_AK4458=m -CONFIG_SND_SOC_AK4554=m -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_AK4619=m -CONFIG_SND_SOC_AK4642=m -CONFIG_SND_SOC_AK5386=m -CONFIG_SND_SOC_AK5558=m -CONFIG_SND_SOC_ALC5623=m -CONFIG_SND_SOC_AUDIO_IIO_AUX=m -CONFIG_SND_SOC_AW8738=m -CONFIG_SND_SOC_AW88395=m -CONFIG_SND_SOC_AW88166=m -CONFIG_SND_SOC_AW88261=m -CONFIG_SND_SOC_AW88081=m -CONFIG_SND_SOC_AW87390=m -CONFIG_SND_SOC_AW88399=m -CONFIG_SND_SOC_BD28623=m -CONFIG_SND_SOC_BT_SCO=m -CONFIG_SND_SOC_CHV3_CODEC=m -CONFIG_SND_SOC_CS35L32=m -CONFIG_SND_SOC_CS35L33=m -CONFIG_SND_SOC_CS35L34=m -CONFIG_SND_SOC_CS35L35=m -CONFIG_SND_SOC_CS35L36=m -CONFIG_SND_SOC_CS35L45_SPI=m -CONFIG_SND_SOC_CS35L45_I2C=m -CONFIG_SND_SOC_CS35L56_I2C=m -CONFIG_SND_SOC_CS40L50=m -CONFIG_SND_SOC_CS42L51_I2C=m -CONFIG_SND_SOC_CS42L52=m -CONFIG_SND_SOC_CS42L56=m -CONFIG_SND_SOC_CS42L73=m -CONFIG_SND_SOC_CS42L83=m -CONFIG_SND_SOC_CS42L84=m -CONFIG_SND_SOC_CS4234=m -CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4270=m -CONFIG_SND_SOC_CS4271_I2C=m -CONFIG_SND_SOC_CS4271_SPI=m -CONFIG_SND_SOC_CS42XX8_I2C=m -CONFIG_SND_SOC_CS43130=m -CONFIG_SND_SOC_CS4341=m -CONFIG_SND_SOC_CS4349=m -CONFIG_SND_SOC_CS48L32=m -CONFIG_SND_SOC_CS53L30=m -CONFIG_SND_SOC_CS530X_I2C=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_ES8311=m -CONFIG_SND_SOC_ES8323=m -CONFIG_SND_SOC_ES8328_I2C=m -CONFIG_SND_SOC_ES8328_SPI=m -CONFIG_SND_SOC_ES8375=m -CONFIG_SND_SOC_ES8389=m -CONFIG_SND_SOC_GTM601=m -CONFIG_SND_SOC_ICS43432=m -CONFIG_SND_SOC_IDT821034=m -CONFIG_SND_SOC_MAX98088=m -CONFIG_SND_SOC_MAX98504=m -CONFIG_SND_SOC_MAX9867=m -CONFIG_SND_SOC_MAX98520=m -CONFIG_SND_SOC_MAX98396=m -CONFIG_SND_SOC_MAX9860=m -CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -CONFIG_SND_SOC_PCM1681=m -CONFIG_SND_SOC_PCM1789_I2C=m -CONFIG_SND_SOC_PCM179X_I2C=m -CONFIG_SND_SOC_PCM179X_SPI=m -CONFIG_SND_SOC_PCM186X_I2C=m -CONFIG_SND_SOC_PCM186X_SPI=m -CONFIG_SND_SOC_PCM3060_I2C=m -CONFIG_SND_SOC_PCM3060_SPI=m -CONFIG_SND_SOC_PCM3168A_SPI=m -CONFIG_SND_SOC_PCM5102A=m -CONFIG_SND_SOC_PCM512x_SPI=m -CONFIG_SND_SOC_PCM6240=m -CONFIG_SND_SOC_PEB2466=m -CONFIG_SND_SOC_RT1017_SDCA_SDW=m -CONFIG_SND_SOC_RT5616=m -CONFIG_SND_SOC_RT5631=m -CONFIG_SND_SOC_RT5659=m -CONFIG_SND_SOC_RT9120=m -CONFIG_SND_SOC_RT9123=m -CONFIG_SND_SOC_RT9123P=m -CONFIG_SND_SOC_RTQ9124=m -CONFIG_SND_SOC_RTQ9128=m -CONFIG_SND_SOC_SGTL5000=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SIMPLE_MUX=m -CONFIG_SND_SOC_SMA1303=m -CONFIG_SND_SOC_SMA1307=m -CONFIG_SND_SOC_SPDIF=m -CONFIG_SND_SOC_SRC4XXX_I2C=m -CONFIG_SND_SOC_SSM2305=m -CONFIG_SND_SOC_SSM2518=m -CONFIG_SND_SOC_SSM2602_SPI=m -CONFIG_SND_SOC_SSM2602_I2C=m -CONFIG_SND_SOC_STA32X=m -CONFIG_SND_SOC_STA350=m -CONFIG_SND_SOC_STI_SAS=m -CONFIG_SND_SOC_TAS2552=m -CONFIG_SND_SOC_TAS2562=m -CONFIG_SND_SOC_TAS2764=m -CONFIG_SND_SOC_TAS2770=m -CONFIG_SND_SOC_TAS2780=m -CONFIG_SND_SOC_TAS2781_I2C=m -CONFIG_SND_SOC_TAS5086=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_TAS5720=m -CONFIG_SND_SOC_TAS5805M=m -CONFIG_SND_SOC_TAS6424=m -CONFIG_SND_SOC_TDA7419=m -CONFIG_SND_SOC_TFA9879=m -CONFIG_SND_SOC_TFA989X=m -CONFIG_SND_SOC_TLV320ADC3XXX=m -CONFIG_SND_SOC_TLV320AIC23_I2C=m -CONFIG_SND_SOC_TLV320AIC23_SPI=m -CONFIG_SND_SOC_TLV320AIC31XX=m -CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -CONFIG_SND_SOC_TLV320AIC32X4_SPI=m -CONFIG_SND_SOC_TLV320AIC3X_I2C=m -CONFIG_SND_SOC_TLV320AIC3X_SPI=m -CONFIG_SND_SOC_TLV320ADCX140=m -CONFIG_SND_SOC_TSCS42XX=m -CONFIG_SND_SOC_TSCS454=m -CONFIG_SND_SOC_UDA1334=m -CONFIG_SND_SOC_UDA1342=m -CONFIG_SND_SOC_WCD937X_SDW=m -CONFIG_SND_SOC_WCD938X_SDW=m -CONFIG_SND_SOC_WM8510=m -CONFIG_SND_SOC_WM8523=m -CONFIG_SND_SOC_WM8524=m -CONFIG_SND_SOC_WM8580=m -CONFIG_SND_SOC_WM8711=m -CONFIG_SND_SOC_WM8728=m -CONFIG_SND_SOC_WM8731_I2C=m -CONFIG_SND_SOC_WM8731_SPI=m -CONFIG_SND_SOC_WM8737=m -CONFIG_SND_SOC_WM8741=m -CONFIG_SND_SOC_WM8750=m -CONFIG_SND_SOC_WM8753=m -CONFIG_SND_SOC_WM8770=m -CONFIG_SND_SOC_WM8776=m -CONFIG_SND_SOC_WM8782=m -CONFIG_SND_SOC_WM8804_SPI=m -CONFIG_SND_SOC_WM8903=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WM8940=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8961=m -CONFIG_SND_SOC_WM8962=m -CONFIG_SND_SOC_WM8974=m -CONFIG_SND_SOC_WM8978=m -CONFIG_SND_SOC_WM8985=m -CONFIG_SND_SOC_WM8998=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SOC_WSA883X=m -CONFIG_SND_SOC_WSA884X=m -CONFIG_SND_SOC_ZL38060=m -CONFIG_SND_SOC_MAX9759=m -CONFIG_SND_SOC_MT6351=m -CONFIG_SND_SOC_MT6357=m -CONFIG_SND_SOC_MT6358=m -CONFIG_SND_SOC_MT6660=m -CONFIG_SND_SOC_NAU8540=m -CONFIG_SND_SOC_NAU8810=m -CONFIG_SND_SOC_NAU8822=m -CONFIG_SND_SOC_NTP8918=m -CONFIG_SND_SOC_NTP8835=m -CONFIG_SND_SOC_TPA6130A2=m -CONFIG_SND_SOC_LPASS_WSA_MACRO=m -CONFIG_SND_SOC_LPASS_VA_MACRO=m -CONFIG_SND_SOC_LPASS_RX_MACRO=m -CONFIG_SND_SOC_LPASS_TX_MACRO=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_HDMI_LPE_AUDIO=m -CONFIG_SND_XEN_FRONTEND=m -CONFIG_SND_VIRTIO=m -CONFIG_HID=m -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HIDRAW=y -CONFIG_UHID=m -CONFIG_HID_A4TECH=m -CONFIG_HID_ACCUTOUCH=m -CONFIG_HID_ACRUX=m -CONFIG_HID_ACRUX_FF=y -CONFIG_HID_APPLE=m -CONFIG_HID_APPLEIR=m -CONFIG_HID_APPLETB_KBD=m -CONFIG_HID_ASUS=m -CONFIG_HID_AUREAL=m -CONFIG_HID_BELKIN=m -CONFIG_HID_BETOP_FF=m -CONFIG_HID_BIGBEN_FF=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CORSAIR=m -CONFIG_HID_COUGAR=m -CONFIG_HID_MACALLY=m -CONFIG_HID_PRODIKEYS=m -CONFIG_HID_CMEDIA=m -CONFIG_HID_CP2112=m -CONFIG_HID_CREATIVE_SB0540=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DRAGONRISE=m -CONFIG_DRAGONRISE_FF=y -CONFIG_HID_EMS_FF=m -CONFIG_HID_ELAN=m -CONFIG_HID_ELECOM=m -CONFIG_HID_ELO=m -CONFIG_HID_EVISION=m -CONFIG_HID_EZKEY=m -CONFIG_HID_FT260=m -CONFIG_HID_GEMBIRD=m -CONFIG_HID_GFRM=m -CONFIG_HID_GLORIOUS=m -CONFIG_HID_HOLTEK=m -CONFIG_HOLTEK_FF=y -CONFIG_HID_GOODIX_SPI=m -CONFIG_HID_GOOGLE_HAMMER=m -CONFIG_HID_GOOGLE_STADIA_FF=m -CONFIG_HID_VIVALDI=m -CONFIG_HID_GT683R=m -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_KYSONA=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_VIEWSONIC=m -CONFIG_HID_VRC2=m -CONFIG_HID_XIAOMI=m -CONFIG_HID_GYRATION=m -CONFIG_HID_ICADE=m -CONFIG_HID_ITE=m -CONFIG_HID_JABRA=m -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LCPOWER=m -CONFIG_HID_LENOVO=m -CONFIG_HID_LETSKETCH=m -CONFIG_HID_LOGITECH=m -CONFIG_HID_LOGITECH_DJ=m -CONFIG_LOGITECH_FF=y -CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_LOGIG940_FF=y -CONFIG_HID_MAGICMOUSE=m -CONFIG_HID_MALTRON=m -CONFIG_HID_MAYFLASH=m -CONFIG_HID_MEGAWORLD_FF=m -CONFIG_HID_REDRAGON=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NINTENDO=m -CONFIG_NINTENDO_FF=y -CONFIG_HID_NTI=m -CONFIG_HID_NTRIG=m -CONFIG_HID_NVIDIA_SHIELD=m -CONFIG_NVIDIA_SHIELD_FF=y -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_PANTHERLORD_FF=y -CONFIG_HID_PENMOUNT=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PICOLCD_FB=y -CONFIG_HID_PICOLCD_BACKLIGHT=y -CONFIG_HID_PICOLCD_LCD=y -CONFIG_HID_PICOLCD_LEDS=y -CONFIG_HID_PICOLCD_CIR=y -CONFIG_HID_PLANTRONICS=m -CONFIG_HID_PLAYSTATION=m -CONFIG_PLAYSTATION_FF=y -CONFIG_HID_PXRC=m -CONFIG_HID_RAZER=m -CONFIG_HID_PRIMAX=m -CONFIG_HID_RETRODE=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SEMITEK=m -CONFIG_HID_SIGMAMICRO=m -CONFIG_HID_SONY=m -CONFIG_SONY_FF=y -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_STEAM=m -CONFIG_STEAM_FF=y -CONFIG_HID_STEELSERIES=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_RMI=m -CONFIG_HID_GREENASIA=m -CONFIG_GREENASIA_FF=y -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_SMARTJOYPLUS_FF=y -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_TOPRE=m -CONFIG_HID_THINGM=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_THRUSTMASTER_FF=y -CONFIG_HID_UDRAW_PS3=m -CONFIG_HID_U2FZERO=m -CONFIG_HID_UNIVERSAL_PIDFF=m -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -CONFIG_HID_WINWING=m -CONFIG_HID_XINMO=m -CONFIG_HID_ZEROPLUS=m -CONFIG_ZEROPLUS_FF=y -CONFIG_HID_ZYDACRON=m -CONFIG_HID_SENSOR_HUB=m -CONFIG_HID_SENSOR_CUSTOM_SENSOR=m -CONFIG_HID_ALPS=m -CONFIG_HID_MCP2200=m -CONFIG_HID_MCP2221=m -CONFIG_I2C_HID_ACPI=m -CONFIG_I2C_HID_OF=m -CONFIG_INTEL_ISH_HID=m -CONFIG_AMD_SFH_HID=m -CONFIG_SURFACE_HID=m -CONFIG_SURFACE_KBD=m -CONFIG_INTEL_THC_HID=m -CONFIG_INTEL_QUICKSPI=m -CONFIG_INTEL_QUICKI2C=m -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_KBD=m -CONFIG_USB_MOUSE=m -CONFIG_USB_LED_TRIG=y -CONFIG_USB_CONN_GPIO=m -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=m -CONFIG_USB_MON=m -CONFIG_USB_C67X00_HCD=m -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_SIDEBAND=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OXU210HP_HCD=m -CONFIG_USB_ISP116X_HCD=m -CONFIG_USB_MAX3421_HCD=m -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_SL811_HCD=m -CONFIG_USB_SL811_HCD_ISO=y -CONFIG_USB_SL811_CS=m -CONFIG_USB_R8A66597_HCD=m -CONFIG_USB_HCD_BCMA=m -CONFIG_USB_HCD_SSB=m -CONFIG_USB_XEN_HCD=m -CONFIG_USB_PRINTER=m -CONFIG_USB_TMC=m -CONFIG_USB_STORAGE=m -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USBIP_CORE=m -CONFIG_USBIP_VHCI_HCD=m -CONFIG_USBIP_HOST=m -CONFIG_USBIP_VUDC=m -CONFIG_USB_CDNS_SUPPORT=m -CONFIG_USB_CDNS3=m -CONFIG_USB_CDNSP_PCI=m -CONFIG_USB_CDNSP_GADGET=y -CONFIG_USB_CDNSP_HOST=y -CONFIG_USB_MUSB_HDRC=m -CONFIG_MUSB_PIO_ONLY=y -CONFIG_USB_DWC3=m -CONFIG_USB_DWC3_ULPI=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_PCI=m -CONFIG_USB_CHIPIDEA=m -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_F81232=m -CONFIG_USB_SERIAL_F8153X=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_METRO=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7715_PARPORT=y -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MXUPORT=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_WISHBONE=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_XR=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_USS720=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_APPLE_MFI_FASTCHARGE=m -CONFIG_USB_LJCA=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_YUREX=m -CONFIG_USB_HUB_USB251XB=m -CONFIG_USB_HSIC_USB3503=m -CONFIG_USB_HSIC_USB4604=m -CONFIG_USB_LINK_LAYER_TEST=m -CONFIG_USB_CHAOSKEY=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GPIO_VBUS=m -CONFIG_TAHVO_USB=m -CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y -CONFIG_USB_ISP1301=m -CONFIG_USB_GADGET=m -CONFIG_USB_GR_UDC=m -CONFIG_USB_R8A66597=m -CONFIG_USB_PXA27X=m -CONFIG_USB_BDC_UDC=m -CONFIG_USB_AMD5536UDC=m -CONFIG_USB_NET2280=m -CONFIG_USB_GOKU=m -CONFIG_USB_EG20T=m -CONFIG_USB_MAX3420_UDC=m -CONFIG_USB_CDNS2_UDC=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_PHONET=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_MIDI2=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m -CONFIG_GADGET_UAC1=y -CONFIG_USB_ETH=m -CONFIG_USB_ETH_EEM=y -CONFIG_USB_G_NCM=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_FUNCTIONFS_ETH=y -CONFIG_USB_FUNCTIONFS_RNDIS=y -CONFIG_USB_FUNCTIONFS_GENERIC=y -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_GADGET_TARGET=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_NOKIA=m -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_HID=m -CONFIG_USB_G_DBGP=m -CONFIG_USB_G_WEBCAM=m -CONFIG_USB_RAW_GADGET=m -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_TCPCI=m -CONFIG_TYPEC_RT1711H=m -CONFIG_TYPEC_MT6360=m -CONFIG_TYPEC_TCPCI_MT6370=m -CONFIG_TYPEC_TCPCI_MAXIM=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_UCSI=m -CONFIG_UCSI_CCG=m -CONFIG_UCSI_ACPI=m -CONFIG_UCSI_STM32G0=m -CONFIG_TYPEC_TPS6598X=m -CONFIG_TYPEC_ANX7411=m -CONFIG_TYPEC_RT1719=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_TYPEC_STUSB160X=m -CONFIG_TYPEC_WUSB3801=m -CONFIG_TYPEC_MUX_FSA4480=m -CONFIG_TYPEC_MUX_GPIO_SBU=m -CONFIG_TYPEC_MUX_PI3USB30532=m -CONFIG_TYPEC_MUX_INTEL_PMC=m -CONFIG_TYPEC_MUX_NB7VPQ904M=m -CONFIG_TYPEC_MUX_PS883X=m -CONFIG_TYPEC_MUX_PTN36502=m -CONFIG_TYPEC_MUX_TUSB1046=m -CONFIG_TYPEC_MUX_WCD939X_USBSS=m -CONFIG_TYPEC_DP_ALTMODE=m -CONFIG_TYPEC_NVIDIA_ALTMODE=m -CONFIG_TYPEC_TBT_ALTMODE=m -CONFIG_USB_ROLES_INTEL_XHCI=m -CONFIG_MMC=y -CONFIG_SDIO_UART=m -CONFIG_MMC_CRYPTO=y -CONFIG_MMC_SDHCI=m -CONFIG_MMC_SDHCI_PCI=m -CONFIG_MMC_SDHCI_ACPI=m -CONFIG_MMC_SDHCI_PLTFM=m -CONFIG_MMC_SDHCI_F_SDH30=m -CONFIG_MMC_WBSD=m -CONFIG_MMC_ALCOR=m -CONFIG_MMC_TIFM_SD=m -CONFIG_MMC_SPI=m -CONFIG_MMC_SDRICOH_CS=m -CONFIG_MMC_CB710=m -CONFIG_MMC_VIA_SDMMC=m -CONFIG_MMC_VUB300=m -CONFIG_MMC_USHC=m -CONFIG_MMC_USDHI6ROL0=m -CONFIG_MMC_REALTEK_PCI=m -CONFIG_MMC_REALTEK_USB=m -CONFIG_MMC_TOSHIBA_PCI=m -CONFIG_MMC_MTK=m -CONFIG_MMC_SDHCI_XENON=m -CONFIG_SCSI_UFSHCD=m -CONFIG_SCSI_UFS_CRYPTO=y -CONFIG_SCSI_UFS_HWMON=y -CONFIG_SCSI_UFSHCD_PCI=m -CONFIG_SCSI_UFSHCD_PLATFORM=m -CONFIG_SCSI_UFS_CDNS_PLATFORM=m -CONFIG_MEMSTICK=m -CONFIG_MSPRO_BLOCK=m -CONFIG_MS_BLOCK=m -CONFIG_MEMSTICK_TIFM_MS=m -CONFIG_MEMSTICK_JMICRON_38X=m -CONFIG_MEMSTICK_R592=m -CONFIG_MEMSTICK_REALTEK_USB=m -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_CLASS_FLASH=m -CONFIG_LEDS_CLASS_MULTICOLOR=m -CONFIG_LEDS_88PM860X=m -CONFIG_LEDS_APU=m -CONFIG_LEDS_AW200XX=m -CONFIG_LEDS_CHT_WCOVE=m -CONFIG_LEDS_LM3530=m -CONFIG_LEDS_LM3532=m -CONFIG_LEDS_LM3533=m -CONFIG_LEDS_LM3642=m -CONFIG_LEDS_MT6323=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_LP3944=m -CONFIG_LEDS_LP3952=m -CONFIG_LEDS_LP50XX=m -CONFIG_LEDS_LP8788=m -CONFIG_LEDS_PCA955X=m -CONFIG_LEDS_PCA963X=m -CONFIG_LEDS_PCA995X=m -CONFIG_LEDS_QNAP_MCU=m -CONFIG_LEDS_WM831X_STATUS=m -CONFIG_LEDS_WM8350=m -CONFIG_LEDS_DA903X=m -CONFIG_LEDS_DA9052=m -CONFIG_LEDS_DAC124S085=m -CONFIG_LEDS_PWM=m -CONFIG_LEDS_REGULATOR=m -CONFIG_LEDS_BD2606MVV=m -CONFIG_LEDS_BD2802=m -CONFIG_LEDS_INTEL_SS4200=m -CONFIG_LEDS_LT3593=m -CONFIG_LEDS_ADP5520=m -CONFIG_LEDS_MC13783=m -CONFIG_LEDS_TCA6507=m -CONFIG_LEDS_TLC591XX=m -CONFIG_LEDS_MAX77705=m -CONFIG_LEDS_MAX8997=m -CONFIG_LEDS_LM355x=m -CONFIG_LEDS_MENF21BMC=m -CONFIG_LEDS_IS31FL319X=m -CONFIG_LEDS_UPBOARD=m -CONFIG_LEDS_BLINKM=m -CONFIG_LEDS_BLINKM_MULTICOLOR=y -CONFIG_LEDS_MLXCPLD=m -CONFIG_LEDS_MLXREG=m -CONFIG_LEDS_USER=m -CONFIG_LEDS_NIC78BX=m -CONFIG_LEDS_SPI_BYTE=m -CONFIG_LEDS_LM36274=m -CONFIG_LEDS_AS3645A=m -CONFIG_LEDS_LM3601X=m -CONFIG_LEDS_MT6370_FLASH=m -CONFIG_LEDS_SGM3140=m -CONFIG_LEDS_KTD202X=m -CONFIG_LEDS_PWM_MULTICOLOR=m -CONFIG_LEDS_MT6370_RGB=m -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_ONESHOT=m -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEDS_TRIGGER_NETDEV=m -CONFIG_LEDS_TRIGGER_PATTERN=m -CONFIG_LEDS_TRIGGER_TTY=m -CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m -CONFIG_ACCESSIBILITY=y -CONFIG_A11Y_BRAILLE_CONSOLE=y -CONFIG_SPEAKUP=m -CONFIG_SPEAKUP_SYNTH_SOFT=m -CONFIG_INFINIBAND=m -CONFIG_INFINIBAND_USER_MAD=m -CONFIG_INFINIBAND_USER_ACCESS=m -CONFIG_INFINIBAND_BNXT_RE=m -CONFIG_INFINIBAND_CXGB4=m -CONFIG_INFINIBAND_EFA=m -CONFIG_INFINIBAND_ERDMA=m -CONFIG_INFINIBAND_HFI1=m -CONFIG_INFINIBAND_IRDMA=m -CONFIG_MLX4_INFINIBAND=m -CONFIG_MLX5_INFINIBAND=m -CONFIG_INFINIBAND_MTHCA=m -# CONFIG_INFINIBAND_MTHCA_DEBUG is not set -CONFIG_INFINIBAND_OCRDMA=m -CONFIG_INFINIBAND_QEDR=m -CONFIG_INFINIBAND_USNIC=m -CONFIG_INFINIBAND_VMWARE_PVRDMA=m -CONFIG_INFINIBAND_RDMAVT=m -CONFIG_RDMA_RXE=m -CONFIG_RDMA_SIW=m -CONFIG_INFINIBAND_IPOIB=m -CONFIG_INFINIBAND_IPOIB_CM=y -# CONFIG_INFINIBAND_IPOIB_DEBUG is not set -CONFIG_INFINIBAND_SRP=m -CONFIG_INFINIBAND_SRPT=m -CONFIG_INFINIBAND_ISER=m -CONFIG_INFINIBAND_ISERT=m -CONFIG_INFINIBAND_RTRS_CLIENT=m -CONFIG_INFINIBAND_RTRS_SERVER=m -CONFIG_INFINIBAND_OPA_VNIC=m -CONFIG_EDAC=y -# CONFIG_EDAC_LEGACY_SYSFS is not set -CONFIG_EDAC_DECODE_MCE=m -CONFIG_EDAC_GHES=y -CONFIG_EDAC_SCRUB=y -CONFIG_EDAC_ECS=y -CONFIG_EDAC_MEM_REPAIR=y -CONFIG_EDAC_AMD64=m -CONFIG_EDAC_E752X=m -CONFIG_EDAC_I82975X=m -CONFIG_EDAC_I3000=m -CONFIG_EDAC_I3200=m -CONFIG_EDAC_IE31200=m -CONFIG_EDAC_X38=m -CONFIG_EDAC_I5400=m -CONFIG_EDAC_I7CORE=m -CONFIG_EDAC_I5100=m -CONFIG_EDAC_I7300=m -CONFIG_EDAC_SBRIDGE=m -CONFIG_EDAC_SKX=m -CONFIG_EDAC_I10NM=m -CONFIG_EDAC_PND2=m -CONFIG_EDAC_IGEN6=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_88PM860X=m -CONFIG_RTC_DRV_88PM80X=m -CONFIG_RTC_DRV_ABB5ZES3=m -CONFIG_RTC_DRV_ABEOZ9=m -CONFIG_RTC_DRV_ABX80X=m -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_DS1374=m -CONFIG_RTC_DRV_DS1374_WDT=y -CONFIG_RTC_DRV_DS1672=m -CONFIG_RTC_DRV_LP8788=m -CONFIG_RTC_DRV_MAX6900=m -CONFIG_RTC_DRV_MAX8907=m -CONFIG_RTC_DRV_MAX8925=m -CONFIG_RTC_DRV_MAX8998=m -CONFIG_RTC_DRV_MAX8997=m -CONFIG_RTC_DRV_MAX31335=m -CONFIG_RTC_DRV_RS5C372=m -CONFIG_RTC_DRV_ISL1208=m -CONFIG_RTC_DRV_ISL12022=m -CONFIG_RTC_DRV_X1205=m -CONFIG_RTC_DRV_PCF8523=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_PCF8563=m -CONFIG_RTC_DRV_PCF8583=m -CONFIG_RTC_DRV_M41T80=m -CONFIG_RTC_DRV_M41T80_WDT=y -CONFIG_RTC_DRV_BQ32K=m -CONFIG_RTC_DRV_PALMAS=m -CONFIG_RTC_DRV_TPS6586X=m -CONFIG_RTC_DRV_TPS6594=m -CONFIG_RTC_DRV_TPS65910=m -CONFIG_RTC_DRV_RC5T583=m -CONFIG_RTC_DRV_S35390A=m -CONFIG_RTC_DRV_FM3130=m -CONFIG_RTC_DRV_RX8010=m -CONFIG_RTC_DRV_RX8111=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RX8025=m -CONFIG_RTC_DRV_EM3027=m -CONFIG_RTC_DRV_RV3028=m -CONFIG_RTC_DRV_RV3032=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_SD2405AL=m -CONFIG_RTC_DRV_SD3078=m -CONFIG_RTC_DRV_M41T93=m -CONFIG_RTC_DRV_M41T94=m -CONFIG_RTC_DRV_DS1302=m -CONFIG_RTC_DRV_DS1305=m -CONFIG_RTC_DRV_DS1343=m -CONFIG_RTC_DRV_DS1347=m -CONFIG_RTC_DRV_DS1390=m -CONFIG_RTC_DRV_MAX6916=m -CONFIG_RTC_DRV_R9701=m -CONFIG_RTC_DRV_RX4581=m -CONFIG_RTC_DRV_RS5C348=m -CONFIG_RTC_DRV_MAX6902=m -CONFIG_RTC_DRV_PCF2123=m -CONFIG_RTC_DRV_MCP795=m -CONFIG_RTC_DRV_DS3232=m -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_PCF85063=m -CONFIG_RTC_DRV_RV3029C2=m -CONFIG_RTC_DRV_RX6110=m -CONFIG_RTC_DRV_DS1286=m -CONFIG_RTC_DRV_DS1511=m -CONFIG_RTC_DRV_DS1553=m -CONFIG_RTC_DRV_DS1685_FAMILY=m -CONFIG_RTC_DRV_DS1742=m -CONFIG_RTC_DRV_DS2404=m -CONFIG_RTC_DRV_DA9052=m -CONFIG_RTC_DRV_DA9055=m -CONFIG_RTC_DRV_DA9063=m -CONFIG_RTC_DRV_STK17TA8=m -CONFIG_RTC_DRV_M48T86=m -CONFIG_RTC_DRV_M48T35=m -CONFIG_RTC_DRV_M48T59=m -CONFIG_RTC_DRV_MSM6242=m -CONFIG_RTC_DRV_RP5C01=m -CONFIG_RTC_DRV_WM831X=m -CONFIG_RTC_DRV_WM8350=m -CONFIG_RTC_DRV_CROS_EC=m -CONFIG_RTC_DRV_FTRTC010=m -CONFIG_RTC_DRV_PCAP=m -CONFIG_RTC_DRV_MC13XXX=m -CONFIG_RTC_DRV_MT6397=m -CONFIG_RTC_DRV_GOLDFISH=m -CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_ACPI_FPDT=y +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_IPMI=m +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_MADT_WAKEUP=y +CONFIG_ACPI_MDIO=y +CONFIG_ACPI_MRRM=y +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NHLT=y +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PLATFORM_PROFILE=m +CONFIG_ACPI_PRMT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_QUICKSTART=m +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_SLEEP=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +CONFIG_ACPI_TABLE_LIB=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_THERMAL_LIB=y +CONFIG_ACPI_THERMAL_REL=m +CONFIG_ACPI_TOSHIBA=m +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_VIOT=y +CONFIG_ACPI_WATCHDOG=y +CONFIG_ACPI_WMI=m +# CONFIG_ACPI_WMI_LEGACY_DEVICE_NAMES is not set +CONFIG_ACQUIRE_WDT=m +# CONFIG_ACRN_GUEST is not set +CONFIG_AD2S1200=m +CONFIG_AD2S1210=m +CONFIG_AD2S90=m +CONFIG_AD3530R=m +CONFIG_AD3552R=m +CONFIG_AD3552R_HS=m +CONFIG_AD3552R_LIB=m +CONFIG_AD4000=m +CONFIG_AD4030=m +CONFIG_AD4080=m +CONFIG_AD4130=m +CONFIG_AD4170_4=m +CONFIG_AD4695=m +CONFIG_AD4851=m +CONFIG_AD5064=m +CONFIG_AD5110=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m +CONFIG_AD5272=m +CONFIG_AD5360=m +CONFIG_AD5380=m +CONFIG_AD5421=m +CONFIG_AD5446=m +CONFIG_AD5449=m +CONFIG_AD5504=m +CONFIG_AD5592R=m +CONFIG_AD5592R_BASE=m +CONFIG_AD5593R=m +CONFIG_AD5624R_SPI=m +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +CONFIG_AD5755=m +CONFIG_AD5758=m +CONFIG_AD5761=m +CONFIG_AD5764=m +CONFIG_AD5766=m +CONFIG_AD5770R=m +CONFIG_AD5791=m +CONFIG_AD5933=m +CONFIG_AD7091R=m +CONFIG_AD7091R5=m +CONFIG_AD7091R8=m +CONFIG_AD7124=m +CONFIG_AD7150=m +CONFIG_AD7173=m +CONFIG_AD7191=m +CONFIG_AD7192=m +CONFIG_AD7266=m +CONFIG_AD7280=m +CONFIG_AD7291=m +CONFIG_AD7292=m +CONFIG_AD7293=m +CONFIG_AD7298=m +CONFIG_AD7303=m +CONFIG_AD7380=m +CONFIG_AD7405=m +CONFIG_AD74115=m +CONFIG_AD74413R=m +CONFIG_AD7476=m +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7625=m +CONFIG_AD7746=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +CONFIG_AD7779=m +CONFIG_AD7780=m +CONFIG_AD7791=m +CONFIG_AD7793=m +CONFIG_AD7816=m +CONFIG_AD7887=m +CONFIG_AD7923=m +CONFIG_AD7944=m +CONFIG_AD7949=m +CONFIG_AD799X=m +CONFIG_AD8366=m +CONFIG_AD8460=m +CONFIG_AD8801=m +# CONFIG_AD9467 is not set +CONFIG_AD9523=m +CONFIG_AD9739A=m +CONFIG_AD9832=m +CONFIG_AD9834=m +CONFIG_ADA4250=m +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_ADC_BATTERY_HELPER=m +# CONFIG_ADE9000 is not set +CONFIG_ADF4350=m +CONFIG_ADF4371=m +CONFIG_ADF4377=m +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_ADIN1100_PHY=m +CONFIG_ADIN1110=m +CONFIG_ADIN_PHY=m +CONFIG_ADIS16080=m +CONFIG_ADIS16130=m +CONFIG_ADIS16136=m +CONFIG_ADIS16201=m +CONFIG_ADIS16203=m +CONFIG_ADIS16209=m +CONFIG_ADIS16260=m +CONFIG_ADIS16400=m +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +CONFIG_ADIS16480=m +CONFIG_ADIS16550=m +# CONFIG_ADI_I3C_MASTER is not set +CONFIG_ADJD_S311=m +CONFIG_ADM8211=m +# CONFIG_ADMFM2000 is not set +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +CONFIG_ADMV8818=m +CONFIG_ADRF6780=m +CONFIG_ADT7316=m +CONFIG_ADT7316_I2C=m +CONFIG_ADT7316_SPI=m +CONFIG_ADUX1020=m +CONFIG_ADVANTECH_EC_WDT=m +CONFIG_ADVANTECH_WDT=m +CONFIG_ADVISE_SYSCALLS=y +CONFIG_ADV_SWBUTTON=m +CONFIG_ADXL313=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL372=m +CONFIG_ADXL372_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL380=m +CONFIG_ADXL380_I2C=m +CONFIG_ADXL380_SPI=m +CONFIG_ADXRS290=m +CONFIG_ADXRS450=m +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_AFFS_FS=m +# CONFIG_AFS_DEBUG is not set +# CONFIG_AFS_DEBUG_CURSOR is not set +CONFIG_AFS_FS=m +CONFIG_AFS_FSCACHE=y +CONFIG_AF_KCM=m +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +CONFIG_AF_RXRPC_IPV6=y +CONFIG_AF_UNIX_OOB=y +CONFIG_AGP=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +CONFIG_AGP_SIS=m +CONFIG_AGP_VIA=y +CONFIG_AHCI_DWC=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_AIC7XXX_RESET_DELAY_MS=5000 +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_AIO=y +CONFIG_AIR_EN8811H_PHY=m +CONFIG_AIX_PARTITION=y +CONFIG_AK09911=m +CONFIG_AK8974=m +CONFIG_AK8975=m +CONFIG_AL3000A=m +CONFIG_AL3010=m +CONFIG_AL3320A=m +CONFIG_ALIBABA_ENI_VDPA=m +CONFIG_ALIENWARE_WMI=m +CONFIG_ALIENWARE_WMI_LEGACY=y +CONFIG_ALIENWARE_WMI_WMAX=y +CONFIG_ALIM1535_WDT=m +CONFIG_ALIM7101_WDT=m +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_ALS31300=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_ALTERA_MBOX=m +CONFIG_ALTERA_MSGDMA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_STAPL=m +CONFIG_ALTERA_TSE=m +CONFIG_ALX=m +CONFIG_AM2315=m +CONFIG_AMD8111_ETH=m +CONFIG_AMDTEE=m +CONFIG_AMD_3D_VCACHE=m +CONFIG_AMD_AE4DMA=m +CONFIG_AMD_ATL=m +CONFIG_AMD_ATL_PRM=y +CONFIG_AMD_HFI=y +CONFIG_AMD_HSMP=y +CONFIG_AMD_HSMP_ACPI=y +CONFIG_AMD_HSMP_PLAT=m +CONFIG_AMD_IOMMU=y +CONFIG_AMD_ISP_PLATFORM=m +# CONFIG_AMD_MEM_ENCRYPT is not set +CONFIG_AMD_MP2_STB=y +CONFIG_AMD_NB=y +CONFIG_AMD_NODE=y +CONFIG_AMD_NUMA=y +CONFIG_AMD_PHY=m +CONFIG_AMD_PMC=m +CONFIG_AMD_PMF=m +# CONFIG_AMD_PMF_DEBUG is not set +CONFIG_AMD_PTDMA=m +CONFIG_AMD_QDMA=m +CONFIG_AMD_SFH_HID=m +CONFIG_AMD_WBRF=y +CONFIG_AMD_XGBE=m +# CONFIG_AMD_XGBE_DCB is not set +CONFIG_AMD_XGBE_HAVE_ECC=y +CONFIG_AMIGA_PARTITION=y +CONFIG_AMILO_RFKILL=m +CONFIG_AMT=m +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANON_VMA_NAME=y +CONFIG_AOSONG_AGS02MA=m +CONFIG_APDS9160=m +CONFIG_APDS9300=m +CONFIG_APDS9306=m +CONFIG_APDS9802ALS=m +CONFIG_APDS9960=m +CONFIG_APERTURE_HELPERS=y +CONFIG_APPLE_GMUX=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_APPLE_PROPERTIES=y +CONFIG_APPLICOM=m +CONFIG_AQTION=m +CONFIG_AQUANTIA_PHY=m +CONFIG_AR5523=m +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_CONFIGURES_CPU_MITIGATIONS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_CC_PLATFORM=y +CONFIG_ARCH_HAS_COPY_MC=y +CONFIG_ARCH_HAS_CPU_ATTACK_VECTORS=y +CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y +CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y +CONFIG_ARCH_HAS_CPU_PASID=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_ARCH_HAS_DMA_OPS=y +CONFIG_ARCH_HAS_EARLY_DEBUG=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_EXECMEM_ROX=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y +CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y +CONFIG_ARCH_HAS_PKEYS=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_PREEMPT_LAZY=y +CONFIG_ARCH_HAS_PTDUMP=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_UBSAN=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +CONFIG_ARCH_HAVE_EXTRA_ELF_NOTES=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_PKEY_BITS=4 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_AUTOFDO_CLANG=y +CONFIG_ARCH_SUPPORTS_CFI=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_SUPPORTS_CRASH_HOTPLUG=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER=y +CONFIG_ARCH_SUPPORTS_KEXEC_JUMP=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y +CONFIG_ARCH_SUPPORTS_KEXEC_SIG_FORCE=y +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_PROPELLER_CLANG=y +CONFIG_ARCH_SUPPORTS_PT_RECLAIM=y +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP=y +CONFIG_ARCH_SUPPORTS_RT=y +CONFIG_ARCH_SUPPORTS_SCHED_CLUSTER=y +CONFIG_ARCH_SUPPORTS_SCHED_MC=y +CONFIG_ARCH_SUPPORTS_SCHED_SMT=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_USES_PG_ARCH_2=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_HUGETLB_VMEMMAP_PREINIT=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_IRQS_OFF_ACTIVATE_MM=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_ARCNET=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM20020=m +CONFIG_ARCNET_COM20020_CS=m +CONFIG_ARCNET_COM20020_PCI=m +CONFIG_ARCNET_COM90xx=m +CONFIG_ARCNET_COM90xxIO=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_RIM_I=m +CONFIG_AS21XXX_PHY=m +CONFIG_AS3935=m +CONFIG_AS73211=m +CONFIG_ASM_MODVERSIONS=y +CONFIG_ASN1=y +CONFIG_ASN1_ENCODER=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASUS_LAPTOP=m +CONFIG_ASUS_NB_WMI=m +CONFIG_ASUS_TF103C_DOCK=m +CONFIG_ASUS_WIRELESS=m +CONFIG_ASUS_WMI=m +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_KERNEL_PGTABLE_FREE=y +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_ASYNC_XOR=m +CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24690 +CONFIG_AS_WRUSS=y +CONFIG_AT76C50X_USB=m +CONFIG_AT803X_PHY=m +CONFIG_ATA=y +CONFIG_ATALK=m +CONFIG_ATARI_PARTITION=y +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=y +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=y +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_DEBUG is not set +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_LEDS=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_SDIO=m +# CONFIG_ATH10K_SPECTRAL is not set +CONFIG_ATH10K_TRACING=y +CONFIG_ATH10K_USB=m +CONFIG_ATH11K=m +# CONFIG_ATH11K_DEBUG is not set +# CONFIG_ATH11K_DEBUGFS is not set +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH12K=m +# CONFIG_ATH12K_COREDUMP is not set +# CONFIG_ATH12K_DEBUG is not set +# CONFIG_ATH12K_DEBUGFS is not set +# CONFIG_ATH12K_TRACING is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +CONFIG_ATH5K_PCI=y +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH6KL=m +# CONFIG_ATH6KL_DEBUG is not set +CONFIG_ATH6KL_SDIO=m +# CONFIG_ATH6KL_TRACING is not set +CONFIG_ATH6KL_USB=m +CONFIG_ATH9K=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_COMMON_DEBUG=y +# CONFIG_ATH9K_COMMON_SPECTRAL is not set +CONFIG_ATH9K_DEBUGFS=y +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_HTC_DEBUGFS=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_HWRNG=y +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_STATION_STATISTICS=y +CONFIG_ATH9K_WOW=y +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATL1=m +CONFIG_ATL1C=m +CONFIG_ATL1E=m +CONFIG_ATL2=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATM=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +# CONFIG_ATM_ENI_TUNE_BURST is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_FORE200E_TX_RETRY=16 +# CONFIG_ATM_FORE200E_USE_TASKLET is not set +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_LANAI=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +CONFIG_ATM_SOLOS=m +CONFIG_ATM_TCP=m +# CONFIG_ATOMIC64_SELFTEST is not set +CONFIG_ATP=m +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_ARCH=y +CONFIG_AUTOFS_FS=m +CONFIG_AUXDISPLAY=y +CONFIG_AUXILIARY_BUS=y +CONFIG_AW96103=m +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_AX88796B_PHY=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP20X_POWER=m +CONFIG_AXP288_ADC=m +CONFIG_AXP288_CHARGER=m +CONFIG_AXP288_FUEL_GAUGE=m +CONFIG_B43=m +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +CONFIG_B43LEGACY_HWRNG=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PIO=y +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_B43_BCMA=y +CONFIG_B43_BCMA_PIO=y +# CONFIG_B43_BUSES_BCMA is not set +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_SSB is not set +# CONFIG_B43_DEBUG is not set +CONFIG_B43_HWRNG=y +CONFIG_B43_LEDS=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PIO=y +# CONFIG_B43_SDIO is not set +CONFIG_B43_SSB=y +CONFIG_B44=m +CONFIG_B44_PCI=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B53=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_BACKLIGHT_88PM860X=m +CONFIG_BACKLIGHT_AAT2870=m +CONFIG_BACKLIGHT_ADP5520=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_APPLE=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_AS3711=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_DA903X=m +CONFIG_BACKLIGHT_DA9052=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_KTD253=m +# CONFIG_BACKLIGHT_KTD2801 is not set +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LM3509=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_LP8788=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_MAX8925=m +CONFIG_BACKLIGHT_MP3309C=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_PANDORA=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RAVE_SP=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_SAHARA=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_WM831X=m +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BALLOON_COMPACTION=y +CONFIG_BARCO_P50_GPIO=m +CONFIG_BAREUDP=m +# CONFIG_BASE_SMALL is not set +CONFIG_BASIC_MODVERSIONS=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV_MCAST=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_BATTERY_88PM860X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_BATTERY_BQ27XXX=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_BATTERY_BQ27XXX_HDQ=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_CHAGALL=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DA9030=m +CONFIG_BATTERY_DA9052=m +CONFIG_BATTERY_DA9150=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_GAUGE_LTC2941=m +CONFIG_BATTERY_GOLDFISH=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_BATTERY_RT5033=m +CONFIG_BATTERY_RX51=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_SURFACE=m +CONFIG_BATTERY_TWL4030_MADC=m +CONFIG_BATTERY_UG3105=m +CONFIG_BAYCOM_PAR=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_DEBUG is not set +CONFIG_BCH=m +CONFIG_BCH_CONST_M=14 +CONFIG_BCH_CONST_PARAMS=y +CONFIG_BCH_CONST_T=4 +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMGENET=m +CONFIG_BCM_KONA_USB2_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_BD79703=m +CONFIG_BE2ISCSI=m +CONFIG_BE2NET=m +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +# CONFIG_BEFS_DEBUG is not set +CONFIG_BEFS_FS=m +# CONFIG_BFQ_GROUP_IOSCHED is not set +CONFIG_BFS_FS=m +CONFIG_BH1745=m +CONFIG_BH1750=m +CONFIG_BH1780=m +# CONFIG_BHYVE_GUEST is not set +# CONFIG_BIG_KEYS is not set +CONFIG_BINARY_PRINTF=y +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +CONFIG_BLK_CGROUP=y +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +# CONFIG_BLK_CGROUP_IOLATENCY is not set +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_DM=y +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_DEV_FD_RAWCMD is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_DEV_ZONED_LOOP is not set +CONFIG_BLK_ICQ=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BLK_MQ_STACKING=y +CONFIG_BLK_PM=y +CONFIG_BLK_RQ_ALLOC_TIME=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMC150_MAGN=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_BMG160=m +CONFIG_BMG160_I2C=m +CONFIG_BMG160_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_I2C=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BMI270=m +CONFIG_BMI270_I2C=m +CONFIG_BMI270_SPI=m +CONFIG_BMI323=m +CONFIG_BMI323_I2C=m +CONFIG_BMI323_SPI=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_BNA=m +CONFIG_BNGE=y +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT=m +# CONFIG_BNXT_DCB is not set +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_HWMON=y +CONFIG_BNXT_SRIOV=y +CONFIG_BOARD_TPCI200=m +CONFIG_BONDING=m +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +# CONFIG_BOOTTIME_TRACING is not set +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BOOT_VESA_SUPPORT=y +CONFIG_BOSCH_BNO055=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BPF=y +CONFIG_BPF_EVENTS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPF_LSM is not set +# CONFIG_BPF_PRELOAD is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BPQETHER=m +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMDBG is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMSMAC=m +CONFIG_BRCMSMAC_LEDS=y +CONFIG_BRCMUTIL=m +CONFIG_BRCM_TRACING=y +CONFIG_BRIDGE=m +CONFIG_BRIDGE_CFM=y +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCAST_TLB_FLUSH=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BT=m +CONFIG_BTREE=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_EXPERIMENTAL is not set +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTT=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_AOSPEXT=y +CONFIG_BT_ATH3K=m +CONFIG_BT_BCM=m +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_BREDR=y +CONFIG_BT_DEBUGFS=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIBTUSB=m +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_AML=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIVHCI=m +CONFIG_BT_HIDP=m +CONFIG_BT_INTEL=m +CONFIG_BT_INTEL_PCIE=m +CONFIG_BT_LE=y +# CONFIG_BT_LEDS is not set +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_MSFTEXT=y +CONFIG_BT_MTK=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_NXPUART=m +CONFIG_BT_QCA=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_RTL=m +# CONFIG_BT_SELFTEST is not set +CONFIG_BT_VIRTIO=m +CONFIG_BUFFER_HEAD=y +CONFIG_BUG=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +CONFIG_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_BUILD_SALT="" +CONFIG_C2PORT=m +CONFIG_C2PORT_DURAMAR_2150=m +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +CONFIG_CACHESTAT_SYSCALL=y +CONFIG_CADENCE_WATCHDOG=m +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_DRIVERS=y +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_TTY=m +CONFIG_CAIF_USB=m +CONFIG_CAIF_VIRTIO=m +CONFIG_CALL_PADDING=y +CONFIG_CALL_THUNKS=y +# CONFIG_CALL_THUNKS_DEBUG is not set +CONFIG_CAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_CAN327=m +CONFIG_CAN_CC770=m +# CONFIG_CAN_CC770_ISA is not set +CONFIG_CAN_CC770_PLATFORM=m +CONFIG_CAN_CTUCANFD=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_C_CAN_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_F81601=m +CONFIG_CAN_F81604=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_GW=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_J1939=m +CONFIG_CAN_JANZ_ICAN3=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_RAW=m +CONFIG_CAN_RX_OFFLOAD=y +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m +CONFIG_CAN_UCAN=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CARDBUS=y +CONFIG_CARL9170=m +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_HWRNG=y +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170_WPC=y +# CONFIG_CARMINE_DRAM_CUSTOM is not set +CONFIG_CASSINI=m +CONFIG_CAVIUM_PTP=m +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y +CONFIG_CC10001_ADC=m +CONFIG_CCS811=m +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_ASSUME=y +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_COUNTED_BY=y +CONFIG_CC_HAS_ENTRY_PADDING=y +CONFIG_CC_HAS_IBT=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_KASAN_SW_TAGS=y +CONFIG_CC_HAS_MARCH_NATIVE=y +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y +CONFIG_CC_HAS_NAMED_AS=y +CONFIG_CC_HAS_NAMED_AS_FIXED_SANITIZERS=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_CC_HAS_RETURN_THUNK=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_SLS=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_IS_GCC=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_CC_VERSION_TEXT="gcc (Debian 15.3.0-1) 15.3.0" +CONFIG_CDNS_I3C_MASTER=m +CONFIG_CDROM=y +CONFIG_CEC_CH7322=m +CONFIG_CEC_CORE=m +CONFIG_CEC_CROS_EC=m +CONFIG_CEC_GPIO=m +CONFIG_CEC_NOTIFIER=y +CONFIG_CEC_NXP_TDA9950=m +CONFIG_CEC_PIN=y +# CONFIG_CEC_PIN_ERROR_INJ is not set +CONFIG_CEC_SECO=m +CONFIG_CEC_SECO_RC=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_CFAG12864B=m +CONFIG_CFAG12864B_RATE=20 +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_CGBC_WDT is not set +CONFIG_CGROUPS=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_DMEM=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CHARGER_88PM860X=m +CONFIG_CHARGER_ADP5061=m +CONFIG_CHARGER_AXP20X=m +CONFIG_CHARGER_BD99954=m +CONFIG_CHARGER_BQ2415X=m +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_CROS_CONTROL=m +CONFIG_CHARGER_CROS_PCHG=m +CONFIG_CHARGER_CROS_USBPD=m +CONFIG_CHARGER_DA9150=m +CONFIG_CHARGER_GPIO=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_LP8788=m +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_MANAGER=y +CONFIG_CHARGER_MAX14577=m +CONFIG_CHARGER_MAX77693=m +CONFIG_CHARGER_MAX77705=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_MAX8971=m +CONFIG_CHARGER_MAX8997=m +CONFIG_CHARGER_MAX8998=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6360=m +CONFIG_CHARGER_MT6370=m +CONFIG_CHARGER_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +CONFIG_CHARGER_SBS=m +CONFIG_CHARGER_SMB347=m +CONFIG_CHARGER_SURFACE=m +CONFIG_CHARGER_TPS65090=m +CONFIG_CHARGER_TWL4030=m +CONFIG_CHARGER_TWL6030=m +CONFIG_CHARGER_WILCO=m +CONFIG_CHARLCD=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CHELSIO_INLINE_CRYPTO=y +# CONFIG_CHELSIO_IPSEC_INLINE is not set +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHROMEOS_ACPI=m +CONFIG_CHROMEOS_LAPTOP=m +CONFIG_CHROMEOS_PRIVACY_SCREEN=m +CONFIG_CHROMEOS_PSTORE=m +CONFIG_CHROMEOS_TBMC=m +CONFIG_CHROME_PLATFORMS=y +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_ST=m +CONFIG_CICADA_PHY=m +CONFIG_CIFS=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_COMPRESSION is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CLANG_VERSION=0 +CONFIG_CLKBLD_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_CLK_TWL=m +CONFIG_CLK_TWL6040=m +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLOSURES=y +CONFIG_CLS_U32_MARK=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLZ_TAB=y +CONFIG_CM32181=m +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +CONFIG_CM36651=m +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=0 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMA_SYSFS=y +# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_CNIC=m +CONFIG_CODA_FS=m +CONFIG_CODE_TAGGING=y +CONFIG_COMEDI=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_PCI=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_ADDI_APCI_1032=m +CONFIG_COMEDI_ADDI_APCI_1500=m +CONFIG_COMEDI_ADDI_APCI_1516=m +CONFIG_COMEDI_ADDI_APCI_1564=m +CONFIG_COMEDI_ADDI_APCI_16XX=m +CONFIG_COMEDI_ADDI_APCI_2032=m +CONFIG_COMEDI_ADDI_APCI_2200=m +CONFIG_COMEDI_ADDI_APCI_3120=m +CONFIG_COMEDI_ADDI_APCI_3501=m +CONFIG_COMEDI_ADDI_APCI_3XXX=m +CONFIG_COMEDI_ADDI_WATCHDOG=m +CONFIG_COMEDI_ADL_PCI6208=m +# CONFIG_COMEDI_ADL_PCI7250 is not set +CONFIG_COMEDI_ADL_PCI7X3X=m +CONFIG_COMEDI_ADL_PCI8164=m +CONFIG_COMEDI_ADL_PCI9111=m +CONFIG_COMEDI_ADL_PCI9118=m +CONFIG_COMEDI_ADV_PCI1710=m +CONFIG_COMEDI_ADV_PCI1720=m +CONFIG_COMEDI_ADV_PCI1723=m +CONFIG_COMEDI_ADV_PCI1724=m +CONFIG_COMEDI_ADV_PCI1760=m +CONFIG_COMEDI_ADV_PCI_DIO=m +CONFIG_COMEDI_AMPLC_DIO200=m +CONFIG_COMEDI_AMPLC_DIO200_PCI=m +CONFIG_COMEDI_AMPLC_PC236=m +CONFIG_COMEDI_AMPLC_PC236_PCI=m +CONFIG_COMEDI_AMPLC_PC263_PCI=m +CONFIG_COMEDI_AMPLC_PCI224=m +CONFIG_COMEDI_AMPLC_PCI230=m +CONFIG_COMEDI_BOND=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_CB_PCIDAS=m +CONFIG_COMEDI_CB_PCIDAS64=m +CONFIG_COMEDI_CB_PCIDDA=m +CONFIG_COMEDI_CB_PCIMDAS=m +CONFIG_COMEDI_CB_PCIMDDA=m +CONFIG_COMEDI_CONTEC_PCI_DIO=m +CONFIG_COMEDI_DAQBOARD2000=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_DAS08_PCI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DT3000=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_DYNA_PCI10XX=m +CONFIG_COMEDI_GSC_HPDI=m +CONFIG_COMEDI_ICP_MULTI=m +CONFIG_COMEDI_JR3_PCI=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_KE_COUNTER=m +CONFIG_COMEDI_ME4000=m +CONFIG_COMEDI_ME_DAQ=m +CONFIG_COMEDI_MF6X4=m +CONFIG_COMEDI_MISC_DRIVERS=y +CONFIG_COMEDI_MITE=m +CONFIG_COMEDI_NI_6527=m +CONFIG_COMEDI_NI_65XX=m +CONFIG_COMEDI_NI_660X=m +CONFIG_COMEDI_NI_670X=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_LABPC_PCI=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_NI_PCIDIO=m +CONFIG_COMEDI_NI_PCIMIO=m +CONFIG_COMEDI_NI_ROUTING=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_TIOCMD=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_PARPORT=m +CONFIG_COMEDI_PCI_DRIVERS=m +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_RTD520=m +CONFIG_COMEDI_S626=m +CONFIG_COMEDI_TEST=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_PALMAS=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_SI5341=m +CONFIG_COMMON_CLK_SI5351=m +CONFIG_COMMON_CLK_SI544=m +CONFIG_COMMON_CLK_TPS68470=m +CONFIG_COMMON_CLK_WM831X=m +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAL_LAPTOP=m +CONFIG_COMPAT=y +CONFIG_COMPAT_32=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_COMPAT_BRK is not set +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_COMPAT_OLD_SIGACTION=y +# CONFIG_COMPAT_VDSO is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=m +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_CONSOLE_POLL=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CORDIC=m +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CORTINA_PHY=m +CONFIG_COUNTER=m +# CONFIG_CPA_DEBUG is not set +CONFIG_CPUFREQ_ARCH_CUR_FREQ=y +CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_HALTPOLL=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set +# CONFIG_CRASH_DM_CRYPT is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_HOTPLUG=y +CONFIG_CRASH_MAX_MEMORY_RANGES=8192 +CONFIG_CRASH_RESERVE=y +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_CRC32_ARCH=y +CONFIG_CRC64=y +CONFIG_CRC64_ARCH=y +CONFIG_CRC7=m +CONFIG_CRC8=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC_OPTIMIZATIONS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_T10DIF_ARCH=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CROS_EC=m +CONFIG_CROS_EC_CHARDEV=m +CONFIG_CROS_EC_DEBUGFS=m +CONFIG_CROS_EC_I2C=m +CONFIG_CROS_EC_ISHTP=m +CONFIG_CROS_EC_LIGHTBAR=m +CONFIG_CROS_EC_LPC=m +CONFIG_CROS_EC_MKBP_PROXIMITY=m +CONFIG_CROS_EC_PROTO=m +CONFIG_CROS_EC_SENSORHUB=m +CONFIG_CROS_EC_SPI=m +CONFIG_CROS_EC_SYSFS=m +CONFIG_CROS_EC_TYPEC=m +CONFIG_CROS_EC_TYPEC_ALTMODES=y +CONFIG_CROS_EC_UART=m +CONFIG_CROS_EC_UCSI=m +# CONFIG_CROS_EC_WATCHDOG is not set +CONFIG_CROS_HPS_I2C=m +CONFIG_CROS_KBD_LED_BACKLIGHT=m +CONFIG_CROS_TYPEC_SWITCH=m +CONFIG_CROS_USBPD_LOGGER=m +CONFIG_CROS_USBPD_NOTIFY=m +CONFIG_CRYPTO=y +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_NI_INTEL=m +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_ARIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_BENCHMARK is not set +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_BLOWFISH_X86_64=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_CAMELLIA_X86_64=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST5_AVX_X86_64=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CAST6_AVX_X86_64=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CHACHA20=y +CONFIG_CRYPTO_CHACHA20POLY1305=y +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_DES3_EDE_X86_64=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CRYPTO_DEV_CCP_CRYPTO=m +CONFIG_CRYPTO_DEV_CCP_DD=m +# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_IAA_CRYPTO=m +# CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS is not set +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_PADLOCK=y +CONFIG_CRYPTO_DEV_PADLOCK_AES=m +CONFIG_CRYPTO_DEV_PADLOCK_SHA=m +CONFIG_CRYPTO_DEV_QAT=m +CONFIG_CRYPTO_DEV_QAT_420XX=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_6XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +# CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION is not set +CONFIG_CRYPTO_DEV_SAFEXCEL=m +CONFIG_CRYPTO_DEV_SP_CCP=y +CONFIG_CRYPTO_DEV_SP_PSP=y +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_ENGINE=m +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_HKDF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KDF800108_CTR=y +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KRB5=m +CONFIG_CRYPTO_KRB5ENC=m +# CONFIG_CRYPTO_KRB5_SELFTESTS is not set +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_AESCFB=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_ARCH=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA_ARCH=y +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_ARCH=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_MD5=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_ARCH=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA1_ARCH=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_SHA256_ARCH=y +CONFIG_CRYPTO_LIB_SHA512=y +CONFIG_CRYPTO_LIB_SHA512_ARCH=y +CONFIG_CRYPTO_LIB_SM3=m +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NHPOLY1305=m +CONFIG_CRYPTO_NHPOLY1305_AVX2=m +CONFIG_CRYPTO_NHPOLY1305_SSE2=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SELFTESTS is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX_X86_64=m +CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIG=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_SM3_AVX_X86_64=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_TWOFISH_X86_64=m +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_ZSTD=m +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_CXD2880_SPI_DRV=m +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=m +# CONFIG_CXL_FEATURES is not set +CONFIG_CXL_MCE=y +CONFIG_CXL_MEM=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=m +CONFIG_CXL_PMEM=m +CONFIG_CXL_PMU=m +CONFIG_CXL_PORT=m +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_SUSPEND=y +CONFIG_CX_ECAT=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_D3323AA=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DA9052_WATCHDOG=m +CONFIG_DA9055_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=m +CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9150_GPADC=m +CONFIG_DAMON=y +CONFIG_DAMON_LRU_SORT=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_STAT=y +CONFIG_DAMON_STAT_ENABLED_DEFAULT=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DASHARO_ACPI=m +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y +CONFIG_DCA=m +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DCB=y +CONFIG_DCDBAS=m +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_DEBUG_MISC=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NET_SMALL_RTNL is not set +# CONFIG_DEBUG_NMI_SELFTEST is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_TLBFLUSH is not set +# CONFIG_DEBUG_VFS is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DEFXX=m +CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m +CONFIG_DELL_RBTN=m +CONFIG_DELL_RBU=m +CONFIG_DELL_SMBIOS=m +CONFIG_DELL_SMBIOS_SMM=y +CONFIG_DELL_SMBIOS_WMI=y +CONFIG_DELL_SMO8800=m +CONFIG_DELL_UART_BACKLIGHT=m +CONFIG_DELL_WMI=m +CONFIG_DELL_WMI_AIO=m +CONFIG_DELL_WMI_DDV=m +CONFIG_DELL_WMI_DESCRIPTOR=m +CONFIG_DELL_WMI_LED=m +CONFIG_DELL_WMI_PRIVACY=y +CONFIG_DELL_WMI_SYSMAN=m +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DETECT_HUNG_TASK_BLOCKER is not set +CONFIG_DEVFREQ_GOV_PASSIVE=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_DEVICE_MIGRATION=y +# CONFIG_DEVICE_PRIVATE is not set +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_DEV_COREDUMP=y +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +CONFIG_DEV_DAX_HMEM_DEVICES=y +CONFIG_DEV_DAX_KMEM=m +CONFIG_DEV_DAX_PMEM=m +CONFIG_DEV_SYNC_PROBE=m +CONFIG_DHT11=m +# CONFIG_DIBS is not set +CONFIG_DIMLIB=y +CONFIG_DL2K=m +CONFIG_DLHL60D=m +CONFIG_DLM=m +# CONFIG_DLM_DEBUG is not set +CONFIG_DLN2_ADC=m +CONFIG_DM9051=m +CONFIG_DM9102=m +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set CONFIG_DMADEVICES=y -CONFIG_ALTERA_MSGDMA=m -CONFIG_INTEL_IDMA64=m -CONFIG_INTEL_IDXD=m -CONFIG_INTEL_IDXD_SVM=y -CONFIG_INTEL_IDXD_PERFMON=y -CONFIG_INTEL_IOATDMA=m -CONFIG_PLX_DMA=m -CONFIG_XILINX_DMA=m -CONFIG_AMD_AE4DMA=m -CONFIG_AMD_PTDMA=m -CONFIG_AMD_QDMA=m -CONFIG_QCOM_HIDMA_MGMT=m -CONFIG_QCOM_HIDMA=m +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMAPOOL_TEST is not set +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_DMAR_TABLE=y +# CONFIG_DMATEST is not set +CONFIG_DMA_ACPI=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +# CONFIG_DMA_FENCE_TRACE is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_DMA_NEED_SYNC=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_OPS_HELPERS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMI=y +CONFIG_DMIID=y +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +CONFIG_DMI_SYSFS=m +CONFIG_DM_AUDIT=y +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_BUFIO=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_CLONE=m +CONFIG_DM_CRYPT=m +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +# CONFIG_DM_EBS is not set +CONFIG_DM_ERA=m +CONFIG_DM_FLAKEY=m +# CONFIG_DM_INIT is not set +CONFIG_DM_INTEGRITY=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_PCACHE is not set +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_SWITCH=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_VDO=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_FEC is not set +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ZERO=m +CONFIG_DM_ZONED=m +CONFIG_DNET=m +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=y +CONFIG_DP83822_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83TD510_PHY=m +CONFIG_DP83TG720_PHY=m +CONFIG_DPLL=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DPOT_DAC=m +CONFIG_DPS310=m +CONFIG_DPTF_PCH_FIVR=m +CONFIG_DPTF_POWER=m +CONFIG_DQL=y +CONFIG_DRAGONRISE_FF=y +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRM=m +CONFIG_DRM_ACCEL=y +CONFIG_DRM_ACCEL_AMDXDNA=m +CONFIG_DRM_ACCEL_HABANALABS=m +CONFIG_DRM_ACCEL_IVPU=m +# CONFIG_DRM_ACCEL_IVPU_DEBUG is not set +CONFIG_DRM_ACCEL_QAIC=m +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ACP is not set +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_FP=y +# CONFIG_DRM_AMD_DC_SI is not set +CONFIG_DRM_AMD_ISP=y +CONFIG_DRM_AMD_SECURE_DISPLAY=y +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_APPLETBDRM=m +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_BUDDY=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_CLIENT=y +CONFIG_DRM_CLIENT_DEFAULT="fbdev" +CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y +# CONFIG_DRM_CLIENT_DEFAULT_LOG is not set +CONFIG_DRM_CLIENT_LIB=m +CONFIG_DRM_CLIENT_LOG=y +CONFIG_DRM_CLIENT_SELECTION=m +CONFIG_DRM_CLIENT_SETUP=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_DISPLAY_DP_AUX_CEC=y +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_DP_TUNNEL=y +CONFIG_DRM_DISPLAY_DSC_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DRAW=y +CONFIG_DRM_EFIDRM=m +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_EXEC=m +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_GMA500=m +CONFIG_DRM_GPUSVM=m +CONFIG_DRM_GPUVM=m +CONFIG_DRM_GUD=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I915=m +CONFIG_DRM_I915_CAPTURE_ERROR=y +CONFIG_DRM_I915_COMPRESS_ERROR=y +# CONFIG_DRM_I915_DEBUG is not set +# CONFIG_DRM_I915_DEBUG_GUC is not set +# CONFIG_DRM_I915_DEBUG_MMIO is not set +# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set +# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set +# CONFIG_DRM_I915_DEBUG_WAKEREF is not set +CONFIG_DRM_I915_DP_TUNNEL=y +CONFIG_DRM_I915_FENCE_TIMEOUT=10000 +CONFIG_DRM_I915_FORCE_PROBE="" +CONFIG_DRM_I915_GVT=y +CONFIG_DRM_I915_GVT_KVMGT=m +CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 +# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set +CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 +CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 +CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set +CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 +# CONFIG_DRM_I915_SELFTEST is not set +CONFIG_DRM_I915_STOP_TIMEOUT=100 +# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set +# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set +CONFIG_DRM_I915_TIMESLICE_DURATION=1 +CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 +CONFIG_DRM_I915_USERPTR=y +# CONFIG_DRM_I915_WERROR is not set +CONFIG_DRM_KMS_HELPER=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_MGAG200 is not set +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_CH7006=m +CONFIG_DRM_NOUVEAU_SIL164=m +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_AUO_A030JTN01=m +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS=m +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANIC=y +CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000 +# CONFIG_DRM_PANIC_DEBUG is not set +CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xffffff +CONFIG_DRM_PANIC_SCREEN="user" +# CONFIG_DRM_PIXPAPER is not set +CONFIG_DRM_PRIVACY_SCREEN=y +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +# CONFIG_DRM_RADEON_USERPTR is not set +CONFIG_DRM_SCHED=m +# CONFIG_DRM_SIMPLEDRM is not set +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +CONFIG_DRM_ST7571_I2C=m +CONFIG_DRM_ST7586=m +CONFIG_DRM_ST7735R=m +CONFIG_DRM_SUBALLOC_HELPER=m +CONFIG_DRM_SYSFB_HELPER=m +CONFIG_DRM_TTM=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_UDL=m +CONFIG_DRM_VBOXVIDEO=m +CONFIG_DRM_VESADRM=m +CONFIG_DRM_VGEM=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +# CONFIG_DRM_VKMS is not set +CONFIG_DRM_VMWGFX=m +# CONFIG_DRM_VMWGFX_MKSSTATS is not set +CONFIG_DRM_VRAM_HELPER=m +# CONFIG_DRM_WERROR is not set +CONFIG_DRM_XE=m +CONFIG_DRM_XEN=y +CONFIG_DRM_XEN_FRONTEND=m +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_MEMIRQ is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_DP_TUNNEL=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +CONFIG_DS1682=m +CONFIG_DS1803=m +CONFIG_DS4424=m +CONFIG_DST_CACHE=y +CONFIG_DUMMY=m +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_DUMMY_IRQ=m +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_AS102=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_BT8XX=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_CXD2099=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_CXD2880=m +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DM1105=m +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_DRXK=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_DUMMY_FE=m +CONFIG_DVB_DYNAMIC_MINORS=y +CONFIG_DVB_EC100=m +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_L64781=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MB86A20S=m +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_MN88443X=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_MT312=m +CONFIG_DVB_MT352=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_MXL692=m +CONFIG_DVB_NET=y +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_DVB_PLL=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_S921=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_SP2=m +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0297=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_TC90522=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TS2020=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_ULE_DEBUG is not set +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_VES1820=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_ZL10353=m +CONFIG_DWC_PCIE_PMU=m +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL=m CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC_PCI=m CONFIG_DW_EDMA=m CONFIG_DW_EDMA_PCIE=m -CONFIG_SF_PDMA=m -CONFIG_INTEL_LDMA=y -CONFIG_ASYNC_TX_DMA=y -CONFIG_UIO_CIF=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_AEC=m -CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_UIO_NETX=m -CONFIG_UIO_MF624=m -CONFIG_UIO_DFL=m -CONFIG_VFIO=m -CONFIG_VFIO_NOIOMMU=y -CONFIG_VFIO_PCI=m -CONFIG_VFIO_PCI_VGA=y -CONFIG_MLX5_VFIO_PCI=m -CONFIG_PDS_VFIO_PCI=m -CONFIG_VIRTIO_VFIO_PCI=m -CONFIG_QAT_VFIO_PCI=m -CONFIG_VIRT_DRIVERS=y -CONFIG_VBOXGUEST=m -CONFIG_NITRO_ENCLAVES=m -CONFIG_EFI_SECRET=m -CONFIG_TDX_GUEST_DRIVER=m -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_VDPA=m -CONFIG_VIRTIO_PMEM=m -CONFIG_VIRTIO_BALLOON=m -CONFIG_VIRTIO_MEM=m -CONFIG_VIRTIO_INPUT=m -CONFIG_VIRTIO_MMIO=m -CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y -CONFIG_VIRTIO_DEBUG=y -CONFIG_VIRTIO_RTC=m -CONFIG_VDPA=m -CONFIG_VDPA_USER=m -CONFIG_IFCVF=m -CONFIG_MLX5_VDPA_NET=m -CONFIG_VP_VDPA=m -CONFIG_ALIBABA_ENI_VDPA=m -CONFIG_SNET_VDPA=m -CONFIG_PDS_VDPA=m -CONFIG_OCTEONEP_VDPA=m -CONFIG_VHOST_NET=m -CONFIG_VHOST_SCSI=m -CONFIG_VHOST_VSOCK=m -CONFIG_VHOST_VDPA=m -CONFIG_XEN_DEV_EVTCHN=m -CONFIG_XENFS=m -CONFIG_XEN_PVCALLS_FRONTEND=m -CONFIG_XEN_SCSI_BACKEND=m -CONFIG_XEN_PRIVCMD_EVENTFD=y -CONFIG_XEN_ACPI_PROCESSOR=y -CONFIG_XEN_MCE_LOG=y -CONFIG_XEN_VIRTIO=y -CONFIG_COMEDI=m -CONFIG_COMEDI_MISC_DRIVERS=y -CONFIG_COMEDI_BOND=m -CONFIG_COMEDI_TEST=m -CONFIG_COMEDI_PARPORT=m -CONFIG_COMEDI_PCI_DRIVERS=m -CONFIG_COMEDI_8255_PCI=m -CONFIG_COMEDI_ADDI_APCI_1032=m -CONFIG_COMEDI_ADDI_APCI_1500=m -CONFIG_COMEDI_ADDI_APCI_1516=m -CONFIG_COMEDI_ADDI_APCI_1564=m -CONFIG_COMEDI_ADDI_APCI_16XX=m -CONFIG_COMEDI_ADDI_APCI_2032=m -CONFIG_COMEDI_ADDI_APCI_2200=m -CONFIG_COMEDI_ADDI_APCI_3120=m -CONFIG_COMEDI_ADDI_APCI_3501=m -CONFIG_COMEDI_ADDI_APCI_3XXX=m -CONFIG_COMEDI_ADL_PCI6208=m -CONFIG_COMEDI_ADL_PCI7X3X=m -CONFIG_COMEDI_ADL_PCI8164=m -CONFIG_COMEDI_ADL_PCI9111=m -CONFIG_COMEDI_ADL_PCI9118=m -CONFIG_COMEDI_ADV_PCI1710=m -CONFIG_COMEDI_ADV_PCI1720=m -CONFIG_COMEDI_ADV_PCI1723=m -CONFIG_COMEDI_ADV_PCI1724=m -CONFIG_COMEDI_ADV_PCI1760=m -CONFIG_COMEDI_ADV_PCI_DIO=m -CONFIG_COMEDI_AMPLC_DIO200_PCI=m -CONFIG_COMEDI_AMPLC_PC236_PCI=m -CONFIG_COMEDI_AMPLC_PC263_PCI=m -CONFIG_COMEDI_AMPLC_PCI224=m -CONFIG_COMEDI_AMPLC_PCI230=m -CONFIG_COMEDI_CONTEC_PCI_DIO=m -CONFIG_COMEDI_DAS08_PCI=m -CONFIG_COMEDI_DT3000=m -CONFIG_COMEDI_DYNA_PCI10XX=m -CONFIG_COMEDI_GSC_HPDI=m -CONFIG_COMEDI_MF6X4=m -CONFIG_COMEDI_ICP_MULTI=m -CONFIG_COMEDI_DAQBOARD2000=m -CONFIG_COMEDI_JR3_PCI=m -CONFIG_COMEDI_KE_COUNTER=m -CONFIG_COMEDI_CB_PCIDAS64=m -CONFIG_COMEDI_CB_PCIDAS=m -CONFIG_COMEDI_CB_PCIDDA=m -CONFIG_COMEDI_CB_PCIMDAS=m -CONFIG_COMEDI_CB_PCIMDDA=m -CONFIG_COMEDI_ME4000=m -CONFIG_COMEDI_ME_DAQ=m -CONFIG_COMEDI_NI_6527=m -CONFIG_COMEDI_NI_65XX=m -CONFIG_COMEDI_NI_660X=m -CONFIG_COMEDI_NI_670X=m -CONFIG_COMEDI_NI_LABPC_PCI=m -CONFIG_COMEDI_NI_PCIDIO=m -CONFIG_COMEDI_NI_PCIMIO=m -CONFIG_COMEDI_RTD520=m -CONFIG_COMEDI_S626=m -CONFIG_COMEDI_PCMCIA_DRIVERS=m -CONFIG_COMEDI_CB_DAS16_CS=m -CONFIG_COMEDI_DAS08_CS=m -CONFIG_COMEDI_NI_DAQ_700_CS=m -CONFIG_COMEDI_NI_DAQ_DIO24_CS=m -CONFIG_COMEDI_NI_LABPC_CS=m -CONFIG_COMEDI_NI_MIO_CS=m -CONFIG_COMEDI_QUATECH_DAQP_CS=m -CONFIG_COMEDI_USB_DRIVERS=m -CONFIG_COMEDI_DT9812=m -CONFIG_COMEDI_NI_USB6501=m -CONFIG_COMEDI_USBDUX=m -CONFIG_COMEDI_USBDUXFAST=m -CONFIG_COMEDI_USBDUXSIGMA=m -CONFIG_COMEDI_VMK80XX=m -CONFIG_COMEDI_8255_SA=m -CONFIG_STAGING=y -CONFIG_RTL8723BS=m -CONFIG_ADIS16203=m -CONFIG_AD7816=m -CONFIG_ADT7316=m -CONFIG_ADT7316_I2C=m -CONFIG_AD9832=m -CONFIG_AD9834=m -CONFIG_AD5933=m +CONFIG_DW_I3C_MASTER=m +CONFIG_DW_WATCHDOG=m +CONFIG_DW_XDATA_PCIE=m +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_DYNAMIC_PHYSICAL_MASK=y +CONFIG_DYNAMIC_SIGFRAME=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_E1000E_HWTS=y +CONFIG_EARLY_PRINTK=y +CONFIG_EARLY_PRINTK_DBGP=y +CONFIG_EARLY_PRINTK_USB=y +# CONFIG_EARLY_PRINTK_USB_XDBC is not set +CONFIG_EBC_C384_WDT=m +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_EDAC=y +CONFIG_EDAC_AMD64=m +CONFIG_EDAC_ATOMIC_SCRUB=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_DECODE_MCE=m +CONFIG_EDAC_E752X=m +CONFIG_EDAC_ECS=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_I10NM=m +CONFIG_EDAC_I3000=m +CONFIG_EDAC_I3200=m +CONFIG_EDAC_I5100=m +CONFIG_EDAC_I5400=m +CONFIG_EDAC_I7300=m +CONFIG_EDAC_I7CORE=m +CONFIG_EDAC_I82975X=m +CONFIG_EDAC_IE31200=m +CONFIG_EDAC_IGEN6=m +# CONFIG_EDAC_LEGACY_SYSFS is not set +CONFIG_EDAC_MEM_REPAIR=y +CONFIG_EDAC_PND2=m +CONFIG_EDAC_SBRIDGE=m +CONFIG_EDAC_SCRUB=y +CONFIG_EDAC_SKX=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC_X38=m +CONFIG_EDD=y +CONFIG_EDD_OFF=y +CONFIG_EEEPC_LAPTOP=m +CONFIG_EEEPC_WMI=m +CONFIG_EEPROM_93CX6=m +CONFIG_EEPROM_93XX46=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_EEPROM_EE1004=m +CONFIG_EEPROM_IDT_89HPESX=m +# CONFIG_EEPROM_M24LR is not set +CONFIG_EEPROM_MAX6875=m +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +CONFIG_EFI_BOOTLOADER_CONTROL=m +# CONFIG_EFI_CAPSULE_LOADER is not set +CONFIG_EFI_COCO_SECRET=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +CONFIG_EFI_DEV_PATH_PARSER=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_DXE_MEM_ATTRIBUTES=y +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_HANDOVER_PROTOCOL=y +CONFIG_EFI_MIXED=y +CONFIG_EFI_PARTITION=y +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_EFI_RCI2_TABLE is not set +CONFIG_EFI_RUNTIME_MAP=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_SBAT_FILE="" +CONFIG_EFI_SECRET=m +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_VARS_PSTORE=m +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFS_FS=m +CONFIG_ELFCORE=y +CONFIG_ELF_CORE=y +CONFIG_ENA_ETHERNET=m +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +CONFIG_ENCX24J600=m +# CONFIG_ENERGY_MODEL is not set +CONFIG_ENIC=m +CONFIG_ENS160=m +CONFIG_ENS160_I2C=m +CONFIG_ENS160_SPI=m +CONFIG_ENS210=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_EPIC100=m +CONFIG_EPOLL=y +CONFIG_EPROBE_EVENTS=y +CONFIG_EQUALIZER=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_BACKED_BY_FILE=y +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_ONDEMAND is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +# CONFIG_EROFS_FS_ZIP is not set +CONFIG_ET131X=m +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +CONFIG_EUROTECH_WDT=m +CONFIG_EVENTFD=y +CONFIG_EVENT_TRACING=y +CONFIG_EVM=y +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +CONFIG_EVM_EXTRA_SMACK_XATTRS=y +# CONFIG_EVM_LOAD_X509 is not set +CONFIG_EXAR_WDT=m +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXECMEM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=m +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXTCON=y +CONFIG_EXTCON_ADC_JACK=m +CONFIG_EXTCON_AXP288=m +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_INTEL_CHT_WC=m +CONFIG_EXTCON_INTEL_INT3496=m +CONFIG_EXTCON_INTEL_MRFLD=m +CONFIG_EXTCON_LC824206XA=m +# CONFIG_EXTCON_MAX14526 is not set +CONFIG_EXTCON_MAX14577=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_MAX77693=m +CONFIG_EXTCON_MAX77843=m +CONFIG_EXTCON_MAX8997=m +CONFIG_EXTCON_PALMAS=m +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_RT8973A=m +CONFIG_EXTCON_SM5502=m +CONFIG_EXTCON_USBC_CROS_EC=m +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_EXTCON_USB_GPIO=m +# CONFIG_EXTENDED_MODVERSIONS is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_EZX_PCAP=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +# CONFIG_F2FS_IOSTAT is not set +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_F71808E_WDT=m +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_FARSYNC=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_FB=y +CONFIG_FBNIC=m +CONFIG_FB_3DFX=m +# CONFIG_FB_3DFX_ACCEL is not set +# CONFIG_FB_3DFX_I2C is not set +CONFIG_FB_ARC=m +CONFIG_FB_ARK=m +CONFIG_FB_ASILIANT=y +CONFIG_FB_ATY=m +CONFIG_FB_ATY128=m +CONFIG_FB_ATY128_BACKLIGHT=y +CONFIG_FB_ATY_BACKLIGHT=y +CONFIG_FB_ATY_CT=y +# CONFIG_FB_ATY_GENERIC_LCD is not set +CONFIG_FB_ATY_GX=y +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_CARMINE=m +CONFIG_FB_CARMINE_DRAM_EVAL=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y +CONFIG_FB_CIRRUS=m +CONFIG_FB_CORE=y +CONFIG_FB_CYBER2000=m +CONFIG_FB_CYBER2000_DDC=y +CONFIG_FB_DDC=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_DMAMEM_HELPERS=y +CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_HECUBA=m +CONFIG_FB_HGA=m +CONFIG_FB_I740=m +CONFIG_FB_IBM_GXT4500=m +CONFIG_FB_IMSTT=y +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_IOMEM_HELPERS=y +CONFIG_FB_KYRO=m +CONFIG_FB_MATROX=m +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_I2C=y +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_METRONOME=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_N411=m +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_NOTIFY=y +# CONFIG_FB_NVIDIA is not set +CONFIG_FB_OPENCORES=m +CONFIG_FB_PM2=m +CONFIG_FB_PM2_FIFO_DISCONNECT=y +CONFIG_FB_PM3=m +CONFIG_FB_RADEON=m +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +CONFIG_FB_RADEON_I2C=y +CONFIG_FB_RIVA=m +CONFIG_FB_RIVA_BACKLIGHT=y +# CONFIG_FB_RIVA_DEBUG is not set +CONFIG_FB_RIVA_I2C=y +CONFIG_FB_S1D13XXX=m +CONFIG_FB_S3=m +CONFIG_FB_S3_DDC=y +CONFIG_FB_SAVAGE=m +# CONFIG_FB_SAVAGE_ACCEL is not set +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SIS=m +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +CONFIG_FB_SM501=m +CONFIG_FB_SM712=m CONFIG_FB_SM750=m -CONFIG_STAGING_MEDIA=y -CONFIG_INTEL_ATOMISP=y -CONFIG_DVB_AV7110=m -CONFIG_VIDEO_IPU3_IMGU=m -CONFIG_VIDEO_INTEL_IPU7=m +CONFIG_FB_SMSCUFX=m +CONFIG_FB_SSD1307=m +CONFIG_FB_SVGALIB=m +CONFIG_FB_SYSMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_IMAGEBLIT=y CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m @@ -4853,1140 +2739,7927 @@ CONFIG_FB_TFT_TLS8204=m CONFIG_FB_TFT_UC1611=m CONFIG_FB_TFT_UC1701=m CONFIG_FB_TFT_UPD161704=m +CONFIG_FB_TILEBLITTING=y +CONFIG_FB_TRIDENT=m +CONFIG_FB_UDL=m +CONFIG_FB_UVESA=m +CONFIG_FB_VESA=y +CONFIG_FB_VGA16=m +CONFIG_FB_VIA=m +# CONFIG_FB_VIA_DIRECT_PROCFS is not set +CONFIG_FB_VIA_X_COMPATIBILITY=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_VOODOO1=m +CONFIG_FB_VT8623=m +CONFIG_FCOE=m +CONFIG_FCOE_FNIC=m +CONFIG_FDDI=y +CONFIG_FEALNX=m +CONFIG_FHANDLE=y +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_FIND_NORMAL_PAGE=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIRMWARE_EDID=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_FIRMWARE_TABLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FM10K=m +CONFIG_FONTS=y +# CONFIG_FONT_10x18 is not set +CONFIG_FONT_6x10=y +# CONFIG_FONT_6x11 is not set +CONFIG_FONT_6x8=y +# CONFIG_FONT_7x14 is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_SUN8x16 is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONT_TER16x32=y +CONFIG_FORCEDETH=m +CONFIG_FORTIFY_SOURCE=y +CONFIG_FPGA=m +CONFIG_FPGA_BRIDGE=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +CONFIG_FPGA_MGR_XILINX_CORE=m +CONFIG_FPGA_MGR_XILINX_SELECTMAP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_REGION=m +CONFIG_FPROBE=y +CONFIG_FPROBE_EVENTS=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMER=m +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=1024 +CONFIG_FREEZER=y +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSNOTIFY=y +CONFIG_FS_DAX=y +CONFIG_FS_DAX_PMD=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +# CONFIG_FS_ENCRYPTION_INLINE_CRYPT is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FS_STACK=y +CONFIG_FS_VERITY=y +# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set +CONFIG_FTL=m +CONFIG_FTRACE=y +CONFIG_FTRACE_MCOUNT_USE_CC=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +CONFIG_FUEL_GAUGE_MM8013=m +CONFIG_FUEL_GAUGE_STC3117=m +CONFIG_FUJITSU_ES=m +CONFIG_FUJITSU_LAPTOP=m +CONFIG_FUJITSU_TABLET=m +CONFIG_FUNCTION_ALIGNMENT=16 +CONFIG_FUNCTION_ALIGNMENT_16B=y +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FUNCTION_GRAPH_RETADDR is not set +# CONFIG_FUNCTION_GRAPH_RETVAL is not set +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PADDING_BYTES=16 +CONFIG_FUNCTION_PADDING_CFI=11 +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_TRACE_ARGS=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m +CONFIG_FUSE_DAX=y +CONFIG_FUSE_FS=m +CONFIG_FUSE_IO_URING=y +CONFIG_FUSE_PASSTHROUGH=y +CONFIG_FUSION=y +CONFIG_FUSION_CTL=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_SAS=m +CONFIG_FUSION_SPI=m +CONFIG_FUTEX=y +CONFIG_FUTEX_MPOL=y +CONFIG_FUTEX_PI=y +CONFIG_FUTEX_PRIVATE_HASH=y +CONFIG_FWCTL=y +CONFIG_FWCTL_MLX5=m +CONFIG_FWCTL_PDS=m +CONFIG_FWNODE_MDIO=y +CONFIG_FW_ATTR_CLASS=m +CONFIG_FW_CACHE=y +CONFIG_FW_CFG_SYSFS=m +# CONFIG_FW_CFG_SYSFS_CMDLINE is not set +CONFIG_FW_CS_DSP=m +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_UPLOAD=y +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_GACT_PROB=y +CONFIG_GADGET_UAC1=y +# CONFIG_GADGET_UAC1_LEGACY is not set +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_GARP=m +CONFIG_GART_IOMMU=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_GCC_VERSION=150300 +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_GEHC_PMC_ADC=m +# CONFIG_GENDWARFKSYMS is not set +CONFIG_GENERIC_ADC_BATTERY=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_ENTRY=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_SYSCALL=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_TRACER=y +CONFIG_GENERIC_VDSO_OVERFLOW_PROTECT=y +CONFIG_GENEVE=m +CONFIG_GENKSYMS=y +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_GET_FREE_REGION=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_GIGABYTE_WMI=m +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +# CONFIG_GOLDFISH is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GP2AP002=m +CONFIG_GP2AP020A00F=m +CONFIG_GPD_POCKET_FAN=m +CONFIG_GPIB=m +CONFIG_GPIB_AGILENT_82350B=m +CONFIG_GPIB_AGILENT_82357A=m +CONFIG_GPIB_CB7210=m +CONFIG_GPIB_CEC_PCI=m +CONFIG_GPIB_COMMON=m +CONFIG_GPIB_INES=m +CONFIG_GPIB_LPVO=m +CONFIG_GPIB_NEC7210=m +CONFIG_GPIB_NI_PCI_ISA=m +CONFIG_GPIB_NI_USB=m +CONFIG_GPIB_PCMCIA=y +CONFIG_GPIB_TMS9914=m +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIOLIB_LEGACY=y +CONFIG_GPIO_74X164=m +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_ADP5520=m +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_AMD8111=m +CONFIG_GPIO_AMDPT=m +CONFIG_GPIO_AMD_FCH=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_CGBC=m +# CONFIG_GPIO_CROS_EC is not set +CONFIG_GPIO_CRYSTAL_COVE=m +CONFIG_GPIO_DA9052=m +CONFIG_GPIO_DA9055=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_DS4520=m +CONFIG_GPIO_DWAPB=m +CONFIG_GPIO_ELKHARTLAKE=m +CONFIG_GPIO_EXAR=m +CONFIG_GPIO_F7188X=m +CONFIG_GPIO_FXL6408=m +CONFIG_GPIO_GENERIC=m +CONFIG_GPIO_GENERIC_PLATFORM=m +CONFIG_GPIO_GRANITERAPIDS=m +CONFIG_GPIO_ICH=m +CONFIG_GPIO_IDIO_16=m +CONFIG_GPIO_IT87=m +CONFIG_GPIO_JANZ_TTL=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LATCH=m +CONFIG_GPIO_LJCA=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX3191X=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MAX730X=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_MC33880=m +CONFIG_GPIO_MENZ127=m +CONFIG_GPIO_ML_IOH=m +# CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_MPSSE=m +CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_PCIE_IDIO_24=m +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_POLARFIRE_SOC=y +CONFIG_GPIO_RC5T583=y +CONFIG_GPIO_RDC321X=m +CONFIG_GPIO_REGMAP=m +CONFIG_GPIO_SCH=m +CONFIG_GPIO_SCH311X=m +# CONFIG_GPIO_SIM is not set +CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SYSFS_LEGACY=y +CONFIG_GPIO_TANGIER=m +CONFIG_GPIO_TPIC2810=m +CONFIG_GPIO_TPS65086=m +CONFIG_GPIO_TPS6586X=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TPS65912=m +CONFIG_GPIO_TPS68470=m +CONFIG_GPIO_TQMX86=m +CONFIG_GPIO_TWL4030=m +CONFIG_GPIO_TWL6040=m +CONFIG_GPIO_VIPERBOARD=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m +CONFIG_GPIO_VX855=m +CONFIG_GPIO_WHISKEY_COVE=m +CONFIG_GPIO_WINBOND=m +CONFIG_GPIO_WM831X=m +CONFIG_GPIO_WM8350=m +CONFIG_GPIO_WM8994=m +CONFIG_GPIO_WS16C48=m +CONFIG_GPIO_XILINX=m +CONFIG_GPIO_XRA1403=m +CONFIG_GP_PCI1XXXX=m +CONFIG_GRACE_PERIOD=m +CONFIG_GREENASIA_FF=y +# CONFIG_GREYBUS is not set +CONFIG_GROUP_SCHED_BANDWIDTH=y +CONFIG_GROUP_SCHED_WEIGHT=y +CONFIG_GRO_CELLS=y +CONFIG_GTP=m +CONFIG_GUEST_PERF_EVENTS=y +# CONFIG_GUP_TEST is not set +CONFIG_GVE=m +CONFIG_HALTPOLL_CPUIDLE=m +CONFIG_HAMACHI=m +CONFIG_HAMRADIO=y +CONFIG_HANGCHECK_TIMER=m +CONFIG_HAPPYMEAL=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_DEFAULT_ON=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_HARDLOCKUP_DETECTOR_ARCH is not set +# CONFIG_HARDLOCKUP_DETECTOR_BUDDY is not set +CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER=y +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +# CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_SECURITY_AUDIT=y +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_HAVE_ARCH_KCSAN=y +CONFIG_HAVE_ARCH_KFENCE=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KMSAN=y +CONFIG_HAVE_ARCH_KSTACK_ERASE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_HAVE_ARCH_NODE_DEV_GROUP=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +CONFIG_HAVE_ARCH_USERFAULTFD_WP=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_HAVE_CALL_THUNKS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_FTRACE_GRAPH_FUNC=y +CONFIG_HAVE_FTRACE_REGS_HAVING_PT_REGS=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_TIF_BITS=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_GIGANTIC_FOLIOS=y +CONFIG_HAVE_GUP_FAST=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IMA_KEXEC=y +CONFIG_HAVE_INTEL_TXT=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_JUMP_LABEL_HACK=y +CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KVM_ARCH_GMEM_INVALIDATE=y +CONFIG_HAVE_KVM_ARCH_GMEM_POPULATE=y +CONFIG_HAVE_KVM_ARCH_GMEM_PREPARE=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_HAVE_KVM_DIRTY_RING=y +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y +CONFIG_HAVE_KVM_DIRTY_RING_TSO=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQ_BYPASS=m +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_NO_POLL=y +CONFIG_HAVE_KVM_PFNCACHE=y +CONFIG_HAVE_KVM_PM_NOTIFIER=y +CONFIG_HAVE_KVM_READONLY_MEM=y +CONFIG_HAVE_LIVEPATCH=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_NOINSTR_HACK=y +CONFIG_HAVE_NOINSTR_VALIDATION=y +CONFIG_HAVE_OBJTOOL=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y +CONFIG_HAVE_OBJTOOL_NOP_MCOUNT=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_HAVE_PCI=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_TRUSTED_KEYS=y +CONFIG_HAVE_UACCESS_VALIDATION=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y +CONFIG_HAVE_UNWIND_USER_FP=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HD44780=m +CONFIG_HD44780_COMMON=m +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HDC3020=m +CONFIG_HDLC=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_X25=m +CONFIG_HDMI=y +CONFIG_HDMI_LPE_AUDIO=m +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_HFI1_DEBUG_SDMA_ORDER is not set +CONFIG_HFSPLUS_FS=m +CONFIG_HFS_FS=m +CONFIG_HI8435=m +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_DEF_COMP="lzo" +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HIBMCGE=m +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_ALPS=m +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_APPLETB_BL=m +CONFIG_HID_APPLETB_KBD=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +# CONFIG_HID_BPF is not set +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_GOODIX_SPI=m +CONFIG_HID_GOOGLE_HAMMER=m +CONFIG_HID_GOOGLE_STADIA_FF=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +# CONFIG_HID_HAPTIC is not set +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_KYSONA=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_HID_MACALLY=m +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MCP2200=m +CONFIG_HID_MCP2221=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_NVIDIA_SHIELD=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_RETRODE=m +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_HID_SENSOR_PRESS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_HID_SENSOR_TEMP=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +CONFIG_HID_TOPRE=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_UNIVERSAL_PIDFF=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_VIVALDI_COMMON=m +CONFIG_HID_VRC2=m +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WINWING=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +CONFIG_HINIC=m +CONFIG_HINIC3=m +# CONFIG_HIPPI is not set +# CONFIG_HIST_TRIGGERS is not set +CONFIG_HMC425=m +CONFIG_HMC6352=m +CONFIG_HMEM_REPORTING=y +CONFIG_HMM_MIRROR=y +CONFIG_HOLTEK_FF=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CORE_SYNC_FULL=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PARALLEL=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_HOTPLUG_PCI_ACPI_IBM=m +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m +CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m +CONFIG_HOTPLUG_PCI_OCTEONEP=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_HOTPLUG_SMT=y +CONFIG_HOTPLUG_SPLIT_STARTUP=y +CONFIG_HP03=m +CONFIG_HP206C=m +CONFIG_HPET=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_HPET_MMAP=y +CONFIG_HPET_MMAP_DEFAULT=y +CONFIG_HPET_TIMER=y +CONFIG_HPFS_FS=m +CONFIG_HPWDT_NMI_DECODING=y +CONFIG_HP_ACCEL=m +CONFIG_HP_BIOSCFG=m +CONFIG_HP_ILO=m +CONFIG_HP_WATCHDOG=m +CONFIG_HP_WMI=m +CONFIG_HSA_AMD=y +CONFIG_HSC030PA=m +CONFIG_HSC030PA_I2C=m +CONFIG_HSC030PA_SPI=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y +CONFIG_HSI_CHAR=m +CONFIG_HSR=m +CONFIG_HSU_DMA=m +CONFIG_HT16K33=m +CONFIG_HTE=y +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +CONFIG_HUAWEI_WMI=m +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y +# CONFIG_HWLAT_TRACER is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON_VID=m +CONFIG_HWPOISON_INJECT=m +# CONFIG_HWSPINLOCK is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_AMD=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_INTEL=m +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_HW_RANDOM_VIA=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HX711=m +CONFIG_HX9023S=m +# CONFIG_HYPERV is not set +CONFIG_HYPERVISOR_GUEST=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_AMD_ASF=m +CONFIG_I2C_AMD_MP2=m +CONFIG_I2C_ATR=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_CGBC=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CHT_WC=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_CROS_EC_TUNNEL=m +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +CONFIG_I2C_DESIGNWARE_AMDISP=m +CONFIG_I2C_DESIGNWARE_BAYTRAIL=y +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_EMEV2=m +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID=m +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_CORE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_I801=m +CONFIG_I2C_I801_MUX=y +CONFIG_I2C_ISCH=m +CONFIG_I2C_ISMT=m +CONFIG_I2C_KEBA=m +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_LJCA=m +CONFIG_I2C_MLXCPLD=m +CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_SCMI=m +CONFIG_I2C_SI470X=m +CONFIG_I2C_SI4713=m +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_SMBUS=m +CONFIG_I2C_STUB=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m +CONFIG_I2C_VIPERBOARD=m +CONFIG_I2C_VIRTIO=m +CONFIG_I2C_XILINX=m +CONFIG_I2C_ZHAOXIN=m +CONFIG_I3C=m +CONFIG_I40E=m +CONFIG_I40EVF=m +CONFIG_I40E_DCB=y +CONFIG_I6300ESB_WDT=m +CONFIG_I82092=m +CONFIG_I8253_LOCK=y +# CONFIG_I8K is not set +CONFIG_IA32_EMULATION=y +# CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set +CONFIG_IA32_FEAT_CTL=y +CONFIG_IAQCORE=m +CONFIG_IAVF=m +CONFIG_IB700_WDT=m +CONFIG_IBMASR=m +CONFIG_IBM_ASM=m +CONFIG_IBM_RTL=m +CONFIG_ICE=m +CONFIG_ICE_HWMON=y +CONFIG_ICE_HWTS=y +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICP10100=m +CONFIG_ICPLUS_PHY=m +CONFIG_ICS932S401=m +CONFIG_IDEAPAD_LAPTOP=m +CONFIG_IDLE_INJECT=y +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set +CONFIG_IE6XX_WDT=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_CA8210=m +# CONFIG_IEEE802154_CA8210_DEBUGFS is not set +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_HWSIM is not set +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IFB=m +CONFIG_IFCVF=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGB_DCA=y +CONFIG_IGB_HWMON=y +CONFIG_IGC=m +CONFIG_IGC_LEDS=y +CONFIG_IIO=m +CONFIG_IIO_ADC_HELPER=m +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y +CONFIG_IIO_BACKEND=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m +CONFIG_IIO_CROS_EC_ACTIVITY=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m +CONFIG_IIO_GTS_HELPER=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_INV_SENSORS_TIMESTAMP=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_KX022A=m +CONFIG_IIO_KX022A_I2C=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO_MS_SENSORS_I2C=m +CONFIG_IIO_MUX=m +CONFIG_IIO_RESCALE=m +CONFIG_IIO_SIMPLE_DUMMY=m +# CONFIG_IIO_SIMPLE_DUMMY_BUFFER is not set +# CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set +CONFIG_IIO_SSP_SENSORHUB=m +CONFIG_IIO_SSP_SENSORS_COMMONS=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_ST_GYRO_I2C_3AXIS=m +CONFIG_IIO_ST_GYRO_SPI_3AXIS=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM9DS0=m +CONFIG_IIO_ST_LSM9DS0_I2C=m +CONFIG_IIO_ST_LSM9DS0_SPI=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_IMA=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +# CONFIG_IMA_APPRAISE_MODSIG is not set +# CONFIG_IMA_ARCH_POLICY is not set +# CONFIG_IMA_BLACKLIST_KEYRING is not set +CONFIG_IMA_DEFAULT_HASH="sha1" +CONFIG_IMA_DEFAULT_HASH_SHA1=y +# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" +CONFIG_IMA_DISABLE_HTABLE=y +CONFIG_IMA_KEXEC=y +CONFIG_IMA_KEXEC_EXTRA_MEMORY_KB=0 +# CONFIG_IMA_LOAD_X509 is not set +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y +# CONFIG_IMA_READ_POLICY is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_WRITE_POLICY is not set +CONFIG_IMG_ASCII_LCD=m +CONFIG_INA2XX_ADC=m +CONFIG_INET=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=m +# CONFIG_INET_PSP is not set +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_SCTP_DIAG=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_XFRM_TUNNEL=m +# CONFIG_INFINEON_TLV493D is not set +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_HFI1=m +# CONFIG_INFINIBAND_IONIC is not set +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set +CONFIG_INFINIBAND_IRDMA=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_MTHCA=m +# CONFIG_INFINIBAND_MTHCA_DEBUG is not set +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_OPA_VNIC=m +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_RDMAVT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_USNIC=m +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_VMWARE_PVRDMA=m +CONFIG_INFTL=m +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INIT_STACK_ALL_PATTERN is not set +CONFIG_INIT_STACK_ALL_ZERO=y +# CONFIG_INIT_STACK_NONE is not set +CONFIG_INOTIFY_USER=y +CONFIG_INPUT=y +CONFIG_INPUT_88PM80X_ONKEY=m +CONFIG_INPUT_88PM860X_ONKEY=m +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +CONFIG_INPUT_AD714X_SPI=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_APANEL=m +CONFIG_INPUT_ARIZONA_HAPTICS=m +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_ATLAS_BTNS=m +# CONFIG_INPUT_AW86927 is not set +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_CS40L50_VIBRA=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_DA9052_ONKEY=m +CONFIG_INPUT_DA9055_ONKEY=m +CONFIG_INPUT_DA9063_ONKEY=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_GPIO_BEEPER=m +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IDEAPAD_SLIDEBAR=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_LEDS=m +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_MAX77693_HAPTIC=m +CONFIG_INPUT_MAX8925_ONKEY=m +CONFIG_INPUT_MAX8997_HAPTIC=m +CONFIG_INPUT_MC13783_PWRBUTTON=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_PALMAS_PWRBUTTON=m +CONFIG_INPUT_PCAP=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PCSPKR=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_QNAP_MCU=m +CONFIG_INPUT_RAVE_SP_PWRBUTTON=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_RETU_PWRBUTTON=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_SOC_BUTTON_ARRAY=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_TABLET=y +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_INPUT_TPS6594_PWRBUTTON is not set +CONFIG_INPUT_TWL4030_PWRBUTTON=m +CONFIG_INPUT_TWL4030_VIBRA=m +CONFIG_INPUT_TWL6040_VIBRA=m +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_VIVALDIFMAP=y +CONFIG_INPUT_WM831X_ON=m +CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m +CONFIG_INPUT_YEALINK=m +CONFIG_INSPUR_PLATFORM_PROFILE=m +CONFIG_INSTRUCTION_DECODER=y +CONFIG_INT3406_THERMAL=m +CONFIG_INT340X_THERMAL=m +CONFIG_INTEGRITY=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +CONFIG_INTEL_ATOMISP=y +CONFIG_INTEL_ATOMISP2_LED=m +CONFIG_INTEL_ATOMISP2_PDX86=y +CONFIG_INTEL_BXTWC_PMIC_TMU=m +CONFIG_INTEL_BXT_PMIC_THERMAL=m +CONFIG_INTEL_BYTCRC_PWRSRC=m +CONFIG_INTEL_CHTDC_TI_PWRBTN=m +CONFIG_INTEL_CHTWC_INT33FE=m +# CONFIG_INTEL_DC_TI_ADC is not set +CONFIG_INTEL_GTT=y +CONFIG_INTEL_HFI_THERMAL=y +CONFIG_INTEL_HID_EVENT=m +CONFIG_INTEL_IDLE=y +CONFIG_INTEL_IDMA64=m +CONFIG_INTEL_IDXD=m +CONFIG_INTEL_IDXD_BUS=m +# CONFIG_INTEL_IDXD_COMPAT is not set +CONFIG_INTEL_IDXD_PERFMON=y +CONFIG_INTEL_IDXD_SVM=y +CONFIG_INTEL_IFS=m +CONFIG_INTEL_INT0002_VGPIO=m +CONFIG_INTEL_IOATDMA=m +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_PERF_EVENTS is not set +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set +CONFIG_INTEL_IOMMU_SVM=y +CONFIG_INTEL_IPS=m +CONFIG_INTEL_ISHTP_ECLITE=m +# CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set +CONFIG_INTEL_ISH_HID=m +CONFIG_INTEL_LDMA=y +CONFIG_INTEL_MEI=m +CONFIG_INTEL_MEI_GSC=m +CONFIG_INTEL_MEI_GSC_PROXY=m +# CONFIG_INTEL_MEI_HDCP is not set +# CONFIG_INTEL_MEI_LB is not set +CONFIG_INTEL_MEI_ME=m +# CONFIG_INTEL_MEI_PXP is not set +# CONFIG_INTEL_MEI_TXE is not set +CONFIG_INTEL_MEI_VSC=m +CONFIG_INTEL_MEI_VSC_HW=m +CONFIG_INTEL_MEI_WDT=m +CONFIG_INTEL_MRFLD_ADC=m +CONFIG_INTEL_MRFLD_PWRBTN=m +CONFIG_INTEL_OAKTRAIL=m +CONFIG_INTEL_OC_WATCHDOG=m +CONFIG_INTEL_PCH_THERMAL=m +CONFIG_INTEL_PLR_TPMI=m +CONFIG_INTEL_PMC_CORE=m +CONFIG_INTEL_PMC_SSRAM_TELEMETRY=m +CONFIG_INTEL_PMT_CLASS=m +CONFIG_INTEL_PMT_CRASHLOG=m +CONFIG_INTEL_PMT_DISCOVERY=m +CONFIG_INTEL_PMT_TELEMETRY=m +CONFIG_INTEL_POWERCLAMP=m +CONFIG_INTEL_PUNIT_IPC=m +CONFIG_INTEL_QEP=m +CONFIG_INTEL_QUICKI2C=m +CONFIG_INTEL_QUICKSPI=m +CONFIG_INTEL_RAPL=m +CONFIG_INTEL_RAPL_CORE=m +CONFIG_INTEL_RAPL_TPMI=m +CONFIG_INTEL_RST=m +CONFIG_INTEL_SAR_INT1092=m +CONFIG_INTEL_SCU=y +CONFIG_INTEL_SCU_IPC=y +CONFIG_INTEL_SCU_IPC_UTIL=m +CONFIG_INTEL_SCU_PCI=y +CONFIG_INTEL_SCU_PLATFORM=m +CONFIG_INTEL_SDSI=m +CONFIG_INTEL_SKL_INT3472=m +CONFIG_INTEL_SMARTCONNECT=m +CONFIG_INTEL_SOC_DTS_IOSF_CORE=m +CONFIG_INTEL_SOC_DTS_THERMAL=m +CONFIG_INTEL_SOC_PMIC=y +CONFIG_INTEL_SOC_PMIC_BXTWC=m +CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m +CONFIG_INTEL_SOC_PMIC_CHTWC=y +CONFIG_INTEL_SOC_PMIC_MRFLD=m +CONFIG_INTEL_SPEED_SELECT_INTERFACE=m +CONFIG_INTEL_SPEED_SELECT_TPMI=m +CONFIG_INTEL_TCC=y +CONFIG_INTEL_TCC_COOLING=m +CONFIG_INTEL_TDX_GUEST=y +# CONFIG_INTEL_TDX_HOST is not set +CONFIG_INTEL_TELEMETRY=m +CONFIG_INTEL_TH=m +CONFIG_INTEL_THC_HID=m +CONFIG_INTEL_TH_ACPI=m +# CONFIG_INTEL_TH_DEBUG is not set +CONFIG_INTEL_TH_GTH=m +CONFIG_INTEL_TH_MSU=m +CONFIG_INTEL_TH_PCI=m +CONFIG_INTEL_TH_PTI=m +CONFIG_INTEL_TH_STH=m +CONFIG_INTEL_TPMI=m +CONFIG_INTEL_TPMI_POWER_DOMAINS=m +# CONFIG_INTEL_TURBO_MAX_3 is not set +CONFIG_INTEL_TXT=y +CONFIG_INTEL_UNCORE_FREQ_CONTROL=m +CONFIG_INTEL_UNCORE_FREQ_CONTROL_TPMI=m +CONFIG_INTEL_VBTN=m +CONFIG_INTEL_VSC=m +CONFIG_INTEL_VSEC=m +CONFIG_INTEL_WMI=y +CONFIG_INTEL_WMI_SBL_FW_UPDATE=m +CONFIG_INTEL_WMI_THUNDERBOLT=m +CONFIG_INTEL_XWAY_PHY=m +# CONFIG_INTERCONNECT is not set +CONFIG_INTERRUPT_CNT=m +CONFIG_INTERVAL_TREE=y +CONFIG_INTERVAL_TREE_TEST=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_SPI=m +# CONFIG_IOMMUFD is not set +CONFIG_IOMMUFD_DRIVER=y +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUG is not set +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_HELPER=y +CONFIG_IOMMU_IOPF=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_MM_DATA=y +CONFIG_IOMMU_SUPPORT=y +CONFIG_IOMMU_SVA=y +CONFIG_IONIC=m +CONFIG_IOSCHED_BFQ=m +CONFIG_IOSF_MBI=y +CONFIG_IOSF_MBI_DEBUG=y +CONFIG_IOSM=m +# CONFIG_IO_DELAY_0X80 is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_IO_DELAY_UDELAY is not set +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IO_URING_MOCK_FILE is not set +CONFIG_IO_URING_ZCRX=y +CONFIG_IO_WQ=y +CONFIG_IP5XXX_POWER=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_IPTABLES_LEGACY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IPACK_BUS=m +CONFIG_IPC_NS=y +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_DMI_DECODE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_IPMB=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPU_BRIDGE=m +CONFIG_IPV6=y +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_ILA=m +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPVLAN=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVTAP=m +CONFIG_IPW2100=m +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2200=m +# CONFIG_IPW2200_DEBUG is not set +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPWIRELESS=m +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_COMMON=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_IPTABLES_LEGACY=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_VS=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +CONFIG_IP_VS_TWOS=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IQS620AT_TEMP=m +CONFIG_IQS621_ALS=m +CONFIG_IQS624_POS=m +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_REMAP=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_IRQ_WORK=y +CONFIG_IRSD200=m +CONFIG_IR_ENE=m +CONFIG_IR_FINTEK=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_XMP_DECODER=m +# CONFIG_ISA_BUS is not set +CONFIG_ISA_BUS_API=y +CONFIG_ISA_DMA_API=y +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ISCSI_IBFT=m +CONFIG_ISCSI_IBFT_FIND=y +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TCP=m +CONFIG_ISDN=y +CONFIG_ISDN_CAPI=y +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_ISL29125=m +CONFIG_ISL29501=m +CONFIG_ISL76682=m +CONFIG_ISO9660_FS=m +CONFIG_IT8712F_WDT=m +CONFIG_IT87_WDT=m +CONFIG_ITCO_VENDOR_SUPPORT=y +CONFIG_ITCO_WDT=m +CONFIG_ITG3200=m +CONFIG_IWL3945=m +CONFIG_IWL4965=m +CONFIG_IWLDVM=m +CONFIG_IWLEGACY=m +# CONFIG_IWLEGACY_DEBUG is not set +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLMLD=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI=m +# CONFIG_IWLWIFI_DEBUG is not set +CONFIG_IWLWIFI_DEBUGFS=y +CONFIG_IWLWIFI_DEVICE_TRACING=y +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLWIFI_OPMODE_MODULAR=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBE_DCA=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_JAILHOUSE_GUEST=y +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_JFFS2_CMODE_FAVOURLZO=y +# CONFIG_JFFS2_CMODE_NONE is not set +# CONFIG_JFFS2_CMODE_PRIORITY is not set +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_JME=m +CONFIG_JOLIET=y +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +# CONFIG_JOYSTICK_PSXPAD_SPI_FF is not set +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_SEESAW=m +CONFIG_JOYSTICK_SENSEHAT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JSA1212=m +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KARMA_PARTITION=y +# CONFIG_KASAN is not set +CONFIG_KCMP=y +# CONFIG_KCOV is not set +# CONFIG_KCSAN is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m +CONFIG_KEBA_LAN9252=m +CONFIG_KEMPLD_WDT=m +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KERNFS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_HANDOVER=y +# CONFIG_KEXEC_HANDOVER_DEBUG is not set +CONFIG_KEXEC_HANDOVER_DEBUGFS=y +CONFIG_KEXEC_JUMP=y +# CONFIG_KEXEC_SIG is not set +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_ADP5520=m +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_APPLESPI=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_CROS_EC=m +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_KEYBOARD_DLINK_DIR685=m +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_IQS62X=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_MTK_PMIC=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_TWL4030=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYS=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_KFENCE=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=0 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KMX61=m +CONFIG_KPROBES=y +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_KS0108=m +CONFIG_KS0108_DELAY=2 +CONFIG_KS0108_PORT=0x378 +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSM=y +CONFIG_KSZ884X_PCI=m +# CONFIG_KUNIT is not set +CONFIG_KVFREE_RCU_BATCHED=y +CONFIG_KVM=m +CONFIG_KVM_AMD=m +CONFIG_KVM_AMD_SEV=y +CONFIG_KVM_ASYNC_PF=y +CONFIG_KVM_COMMON=y +CONFIG_KVM_COMPAT=y +CONFIG_KVM_ELIDE_TLB_FLUSH_IF_YOUNG=y +CONFIG_KVM_EXTERNAL_WRITE_TRACKING=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES=y +CONFIG_KVM_GENERIC_MMU_NOTIFIER=y +CONFIG_KVM_GENERIC_PRE_FAULT_MEMORY=y +CONFIG_KVM_GUEST=y +CONFIG_KVM_GUEST_MEMFD=y +CONFIG_KVM_HYPERV=y +CONFIG_KVM_INTEL=m +# CONFIG_KVM_INTEL_PROVE_VE is not set +CONFIG_KVM_IOAPIC=y +CONFIG_KVM_MAX_NR_VCPUS=1024 +CONFIG_KVM_MMIO=y +CONFIG_KVM_MMU_LOCKLESS_AGING=y +# CONFIG_KVM_PROVE_MMU is not set +CONFIG_KVM_SMM=y +# CONFIG_KVM_SW_PROTECTED_VM is not set +CONFIG_KVM_VFIO=y +CONFIG_KVM_WERROR=y +CONFIG_KVM_X86=m +CONFIG_KVM_XEN=y +CONFIG_KXCJK1013=m +CONFIG_KXSD9=m +CONFIG_KXSD9_I2C=m +CONFIG_KXSD9_SPI=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +CONFIG_LAN865X=m +CONFIG_LAPB=m +CONFIG_LAPBETHER=m +# CONFIG_LATENCYTOP is not set +CONFIG_LATTICE_ECP3_CONFIG=m +CONFIG_LCD2S=m +CONFIG_LCD_AMS369FG06=m +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_HX8357=m +CONFIG_LCD_ILI922X=m +CONFIG_LCD_ILI9320=m +CONFIG_LCD_L4F00242T03=m +CONFIG_LCD_LMS283GF05=m +CONFIG_LCD_LMS501KF03=m +CONFIG_LCD_LTV350QV=m +CONFIG_LCD_OTM3225A=m +CONFIG_LCD_PLATFORM=m +CONFIG_LCD_TDO24M=m +CONFIG_LCD_VGG2432A4=m +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_DEBUG is not set +CONFIG_LDM_PARTITION=y +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y +CONFIG_LD_IS_BFD=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_LD_VERSION=24690 +CONFIG_LEDS_88PM860X=m +CONFIG_LEDS_ADP5520=m +CONFIG_LEDS_APU=m +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_AW200XX=m +CONFIG_LEDS_BD2606MVV=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_BLINKM_MULTICOLOR=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CHT_WCOVE=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_CROS_EC=m +CONFIG_LEDS_DA903X=m +CONFIG_LEDS_DA9052=m +CONFIG_LEDS_DAC124S085=m +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_INTEL_SS4200=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_KTD202X=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_LM36274=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP8788=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_MAX77705=m +CONFIG_LEDS_MAX8997=m +CONFIG_LEDS_MC13783=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_MLXCPLD=m +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_MT6323=m +CONFIG_LEDS_MT6370_FLASH=m +CONFIG_LEDS_MT6370_RGB=m +CONFIG_LEDS_NIC78BX=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_PCA955X=m +# CONFIG_LEDS_PCA955X_GPIO is not set +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QNAP_MCU=m +CONFIG_LEDS_REGULATOR=m +# CONFIG_LEDS_RT8515 is not set +CONFIG_LEDS_SGM3140=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_APOLLOLAKE=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_ELKHARTLAKE=m +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_F7188X=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TCA6507=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_TLC591XX=m +CONFIG_LEDS_TPS6105X=m +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m +# CONFIG_LEDS_TRIGGER_MTD is not set +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_LEDS_UPBOARD=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_WM831X_STATUS=m +CONFIG_LEDS_WM8350=m +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_LEGACY_VSYSCALL_NONE=y +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +CONFIG_LENOVO_SE10_WDT=m +CONFIG_LENOVO_SE30_WDT=m +CONFIG_LENOVO_WMI_CAMERA=m +CONFIG_LENOVO_WMI_DATA01=m +CONFIG_LENOVO_WMI_EVENTS=m +CONFIG_LENOVO_WMI_GAMEZONE=m +CONFIG_LENOVO_WMI_HELPERS=m +CONFIG_LENOVO_WMI_HOTKEY_UTILITIES=m +CONFIG_LENOVO_WMI_TUNING=m +CONFIG_LENOVO_YMC=m +CONFIG_LG_LAPTOP=m +CONFIG_LIBERTAS=m +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBETH=m +CONFIG_LIBETH_XDP=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBFDT=y +CONFIG_LIBIE=m +CONFIG_LIBIE_ADMINQ=m +CONFIG_LIBIE_FWLOG=m +CONFIG_LIBIPW=m +# CONFIG_LIBIPW_DEBUG is not set +CONFIG_LIBNVDIMM=y +CONFIG_LIBWX=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_LINEAR_RANGES=y +CONFIG_LINEDISP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_CORE=m +CONFIG_LIQUIDIO_VF=m +CONFIG_LIRC=y +# CONFIG_LIST_HARDENED is not set +CONFIG_LIVEPATCH=y +# CONFIG_LKDTM is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_LLD_VERSION=0 +CONFIG_LMK04832=m +CONFIG_LMP91000=m +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKD=m +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_TORTURE_TEST=m +CONFIG_LOGIG940_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOOPBACK_TARGET=m +CONFIG_LP8788_ADC=m +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +# CONFIG_LP_CONSOLE is not set +CONFIG_LRU_CACHE=m +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo" +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_LTC1660=m +CONFIG_LTC2309=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +CONFIG_LTC2632=m +CONFIG_LTC2664=m +CONFIG_LTC2688=m +CONFIG_LTC2983=m +CONFIG_LTO_NONE=y +CONFIG_LTR390=m +CONFIG_LTR501=m +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_LXT_PHY=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_M62332=m +CONFIG_MAC80211=m +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_HWSIM=m +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MAC802154=m +CONFIG_MACB=m +CONFIG_MACB_PCI=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACHZ_WDT=m +CONFIG_MACINTOSH_DRIVERS=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_MAC_EMUMOUSEBTN=m +CONFIG_MAC_PARTITION=y +CONFIG_MADERA_IRQ=m +CONFIG_MAG3110=m +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAILBOX=y +CONFIG_MANAGER_SBS=m +CONFIG_MANTIS_CORE=m +CONFIG_MAPPING_DIRTY_HELPERS=y +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88Q2XXX_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MAX1027=m +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +CONFIG_MAX30208=m +CONFIG_MAX31827=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_MAX34408=m +CONFIG_MAX44000=m +CONFIG_MAX44009=m +CONFIG_MAX517=m +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MAX5522=m +CONFIG_MAX5821=m +CONFIG_MAX63XX_WATCHDOG=m +# CONFIG_MAX6959 is not set +CONFIG_MAX77541_ADC=m +CONFIG_MAX8925_POWER=m +CONFIG_MAX9611=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAXLINEAR_86110_PHY=m +CONFIG_MAXLINEAR_GPHY=m +# CONFIG_MAXSMP is not set +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_MB1232=m +CONFIG_MC3230=m +CONFIG_MCB=m +CONFIG_MCB_LPC=m +CONFIG_MCB_PCI=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_MCP3564=m +CONFIG_MCP3911=m +CONFIG_MCP4018=m +CONFIG_MCP41010=m +CONFIG_MCP4131=m +CONFIG_MCP4531=m +CONFIG_MCP4725=m +CONFIG_MCP4728=m +CONFIG_MCP4821=m +CONFIG_MCP4922=m +CONFIG_MCP9600=m +CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +# CONFIG_MCTP_TRANSPORT_I3C is not set +CONFIG_MCTP_TRANSPORT_USB=m +CONFIG_MD=y +CONFIG_MDIO=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BUS=y +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_REGMAP=m +CONFIG_MDIO_THUNDER=m +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP=y +CONFIG_MD_BITMAP_FILE=y +CONFIG_MD_CLUSTER=m +CONFIG_MD_LINEAR=m +# CONFIG_MD_LLBITMAP is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MEDIATEK_GE_PHY=m +# CONFIG_MEDIATEK_GE_SOC_PHY is not set +CONFIG_MEDIATEK_MT6359_AUXADC=m +# CONFIG_MEDIATEK_MT6360_ADC is not set +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_COMMON_OPTIONS=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_MEEGOPAD_ANX7428=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_SAS=m +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_MEMBARRIER=y +CONFIG_MEMBLOCK_KHO_SCRATCH=y +CONFIG_MEMCG=y +CONFIG_MEMCG_V1=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MEMORY_FAILURE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m +CONFIG_MEMREGION=y +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MEMTEST=y +CONFIG_MEM_ALLOC_PROFILING=y +CONFIG_MEM_ALLOC_PROFILING_DEBUG=y +CONFIG_MEM_ALLOC_PROFILING_ENABLED_BY_DEFAULT=y +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_MENF21BMC_WATCHDOG=m +CONFIG_MENZ069_WATCHDOG=m +CONFIG_MEN_A21_WDT=m +CONFIG_MEN_Z188_ADC=m +CONFIG_MERAKI_MX100=m +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_MFD_88PM800=m +CONFIG_MFD_88PM805=m +CONFIG_MFD_88PM860X=y +CONFIG_MFD_AAT2870_CORE=y +CONFIG_MFD_ARIZONA=m +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_AS3711=y +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_BCM590XX=m +CONFIG_MFD_BD9571MWV=m +# CONFIG_MFD_BQ257XX is not set +CONFIG_MFD_CGBC=m +CONFIG_MFD_CORE=y +CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_CORE=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m +CONFIG_MFD_CS42L43=m +CONFIG_MFD_CS42L43_I2C=m +CONFIG_MFD_CS42L43_SDW=m +# CONFIG_MFD_CS47L15 is not set +CONFIG_MFD_CS47L24=y +# CONFIG_MFD_CS47L35 is not set +# CONFIG_MFD_CS47L85 is not set +# CONFIG_MFD_CS47L90 is not set +# CONFIG_MFD_CS47L92 is not set +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9052_SPI=y +CONFIG_MFD_DA9055=y +CONFIG_MFD_DA9062=m +CONFIG_MFD_DA9063=y +CONFIG_MFD_DA9150=m +CONFIG_MFD_DLN2=m +CONFIG_MFD_INTEL_LPSS=m +CONFIG_MFD_INTEL_LPSS_ACPI=m +CONFIG_MFD_INTEL_LPSS_PCI=m +CONFIG_MFD_INTEL_M10_BMC_CORE=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +CONFIG_MFD_INTEL_PMC_BXT=m +CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m +CONFIG_MFD_IQS62X=m +CONFIG_MFD_JANZ_CMODIO=m +CONFIG_MFD_KEMPLD=m +CONFIG_MFD_LM3533=m +CONFIG_MFD_LP3943=m +CONFIG_MFD_LP8788=y +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_MAX14577=y +# CONFIG_MFD_MAX7360 is not set +CONFIG_MFD_MAX77541=m +CONFIG_MFD_MAX77693=y +CONFIG_MFD_MAX77705=m +CONFIG_MFD_MAX77843=y +CONFIG_MFD_MAX8907=m +CONFIG_MFD_MAX8925=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_MAX8998=y +CONFIG_MFD_MC13XXX=m +CONFIG_MFD_MC13XXX_I2C=m +CONFIG_MFD_MC13XXX_SPI=m +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_MP2629=m +CONFIG_MFD_MT6360=m +CONFIG_MFD_MT6370=m +CONFIG_MFD_MT6397=m +# CONFIG_MFD_NCT6694 is not set +CONFIG_MFD_OCELOT=m +CONFIG_MFD_PALMAS=y +CONFIG_MFD_QNAP_MCU=m +CONFIG_MFD_RC5T583=y +CONFIG_MFD_RDC321X=m +CONFIG_MFD_RETU=m +CONFIG_MFD_RT4831=m +CONFIG_MFD_RT5033=m +CONFIG_MFD_RT5120=m +CONFIG_MFD_SI476X_CORE=m +CONFIG_MFD_SIMPLE_MFD_I2C=m +CONFIG_MFD_SKY81452=m +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_SMPRO=m +CONFIG_MFD_SY7636A=m +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_LMU=m +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TPS65086=m +CONFIG_MFD_TPS65090=y +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_TPS65912=y +CONFIG_MFD_TPS65912_I2C=y +CONFIG_MFD_TPS65912_SPI=y +CONFIG_MFD_TPS6594=y +CONFIG_MFD_TPS6594_I2C=y +CONFIG_MFD_TPS6594_SPI=y +CONFIG_MFD_TQMX86=m +CONFIG_MFD_TWL4030_AUDIO=y +CONFIG_MFD_UPBOARD_FPGA=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_VX855=m +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_WM5102=y +CONFIG_MFD_WM5110=y +CONFIG_MFD_WM831X=y +CONFIG_MFD_WM831X_I2C=y +CONFIG_MFD_WM831X_SPI=y +CONFIG_MFD_WM8350=y +CONFIG_MFD_WM8350_I2C=y +CONFIG_MFD_WM8400=y +CONFIG_MFD_WM8994=m +CONFIG_MFD_WM8997=y +CONFIG_MFD_WM8998=y +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_EP=m +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_NET=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE=y +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set +# CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set +CONFIG_MHP_MEMMAP_ON_MEMORY=y +CONFIG_MHZ19B=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROCODE=y +# CONFIG_MICROCODE_DBG is not set +# CONFIG_MICROCODE_LATE_LOADING is not set +CONFIG_MICROSEMI_PHY=m +CONFIG_MIGRATION=y +CONFIG_MII=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_SUBPARTITION=y +CONFIG_MIN_HEAP=y +# CONFIG_MIPI_I3C_HCI is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_FILESYSTEMS=y +CONFIG_MISC_RTSX=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MISDN=m +CONFIG_MISDN_AVMFRITZ=m +CONFIG_MISDN_DSP=m +CONFIG_MISDN_HDLC=m +CONFIG_MISDN_HFCMULTI=m +CONFIG_MISDN_HFCPCI=m +CONFIG_MISDN_HFCUSB=m +CONFIG_MISDN_INFINEON=m +CONFIG_MISDN_IPAC=m +CONFIG_MISDN_ISAR=m +CONFIG_MISDN_L1OIP=m +CONFIG_MISDN_NETJET=m +CONFIG_MISDN_SPEEDFAX=m +CONFIG_MISDN_W6692=m +CONFIG_MITIGATION_CALL_DEPTH_TRACKING=y +CONFIG_MITIGATION_GDS=y +CONFIG_MITIGATION_IBPB_ENTRY=y +CONFIG_MITIGATION_IBRS_ENTRY=y +CONFIG_MITIGATION_ITS=y +CONFIG_MITIGATION_L1TF=y +CONFIG_MITIGATION_MDS=y +CONFIG_MITIGATION_MMIO_STALE_DATA=y +CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=y +CONFIG_MITIGATION_RETBLEED=y +CONFIG_MITIGATION_RETHUNK=y +CONFIG_MITIGATION_RETPOLINE=y +CONFIG_MITIGATION_RFDS=y +# CONFIG_MITIGATION_SLS is not set +CONFIG_MITIGATION_SPECTRE_BHI=y +CONFIG_MITIGATION_SPECTRE_V1=y +CONFIG_MITIGATION_SPECTRE_V2=y +CONFIG_MITIGATION_SRBDS=y +CONFIG_MITIGATION_SRSO=y +CONFIG_MITIGATION_SSB=y +CONFIG_MITIGATION_TAA=y +CONFIG_MITIGATION_TSA=y +CONFIG_MITIGATION_UNRET_ENTRY=y +CONFIG_MITIGATION_VMSCAPE=y +CONFIG_MKISS=m +CONFIG_MLX4_CORE=m +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_EN_DCB=y +# CONFIG_MLX5_CORE_IPOIB is not set +CONFIG_MLX5_DPLL=m +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA is not set +CONFIG_MLX5_HW_STEERING=y +CONFIG_MLX5_INFINIBAND=m +# CONFIG_MLX5_MACSEC is not set +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_MLX5_VFIO_PCI=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +CONFIG_MLX90635=m +CONFIG_MLXFW=m +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +CONFIG_MMA8452=m +CONFIG_MMA9551=m +CONFIG_MMA9551_CORE=m +CONFIG_MMA9553=m +CONFIG_MMC=y +CONFIG_MMC35240=m +CONFIG_MMCONF_FAM10H=y +CONFIG_MMC_ALCOR=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_CRYPTO=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_HSQ=m +CONFIG_MMC_MTK=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_ACPI=m +CONFIG_MMC_SDHCI_F_SDH30=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_UHS2=m +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_SPI=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_WBSD=m +CONFIG_MMIOTRACE=y +# CONFIG_MMIOTRACE_TEST is not set +CONFIG_MMU=y +CONFIG_MMU_GATHER_MERGE_VMAS=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_MM_ID=y +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES=y +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_ALL=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +CONFIG_MODULE_COMPRESS_ZSTD=y +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_DECOMPRESS=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +CONFIG_MOST=m +CONFIG_MOST_CDEV=m CONFIG_MOST_COMPONENTS=m CONFIG_MOST_NET=m +CONFIG_MOST_SND=m +CONFIG_MOST_USB_HDM=m CONFIG_MOST_VIDEO=m -CONFIG_VME_BUS=y -CONFIG_VME_TSI148=m -CONFIG_VME_USER=m -CONFIG_GPIB=m -CONFIG_GPIB_AGILENT_82350B=m -CONFIG_GPIB_AGILENT_82357A=m -CONFIG_GPIB_CEC_PCI=m -CONFIG_GPIB_NI_PCI_ISA=m -CONFIG_GPIB_CB7210=m -CONFIG_GPIB_NI_USB=m -CONFIG_GPIB_INES=m -CONFIG_GPIB_LPVO=m -CONFIG_CHROME_PLATFORMS=y -CONFIG_CHROMEOS_ACPI=m -CONFIG_CHROMEOS_LAPTOP=m -CONFIG_CHROMEOS_PSTORE=m -CONFIG_CHROMEOS_TBMC=m -CONFIG_CROS_EC=m -CONFIG_CROS_EC_I2C=m -CONFIG_CROS_EC_ISHTP=m -CONFIG_CROS_EC_SPI=m -CONFIG_CROS_EC_UART=m -CONFIG_CROS_EC_LPC=m -CONFIG_CROS_KBD_LED_BACKLIGHT=m -CONFIG_CROS_HPS_I2C=m -CONFIG_CHROMEOS_PRIVACY_SCREEN=m -CONFIG_WILCO_EC=m -CONFIG_WILCO_EC_EVENTS=m -CONFIG_WILCO_EC_TELEMETRY=m -CONFIG_SURFACE3_WMI=m -CONFIG_SURFACE_3_POWER_OPREGION=m -CONFIG_SURFACE_ACPI_NOTIFY=m -CONFIG_SURFACE_AGGREGATOR_HUB=m -CONFIG_SURFACE_AGGREGATOR_REGISTRY=m -CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m -CONFIG_SURFACE_DTX=m -CONFIG_SURFACE_GPE=m -CONFIG_SURFACE_HOTPLUG=m -CONFIG_SURFACE_PLATFORM_PROFILE=m -CONFIG_SURFACE_PRO3_BUTTON=m -CONFIG_SURFACE_AGGREGATOR=m -CONFIG_HUAWEI_WMI=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_VMMOUSE=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_MP2629_ADC=m +CONFIG_MPILIB=y +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +CONFIG_MPL3115=m +CONFIG_MPLS=y +CONFIG_MPLS_IPTUNNEL=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPRLS0025PA=m +CONFIG_MPRLS0025PA_I2C=m +CONFIG_MPRLS0025PA_SPI=m +CONFIG_MPTCP=y +CONFIG_MPTCP_IPV6=y +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_MRP=m +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_MS5611_SPI=m +CONFIG_MS5637=m +CONFIG_MSA311=m +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSDOS_FS=m +CONFIG_MSDOS_PARTITION=y +CONFIG_MSE102X=m +CONFIG_MSI_EC=m +CONFIG_MSI_LAPTOP=m +CONFIG_MSI_WMI=m +CONFIG_MSI_WMI_PLATFORM=m +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m +CONFIG_MT7601U=m +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7663U is not set +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +# CONFIG_MT76x0E is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x2E is not set +CONFIG_MT76x2U=m +CONFIG_MT76x2_COMMON=m +# CONFIG_MT7915E is not set +CONFIG_MT7921E=m +# CONFIG_MT7921S is not set +# CONFIG_MT7921U is not set +CONFIG_MT7921_COMMON=m +CONFIG_MT7925E=m +CONFIG_MT7925U=m +CONFIG_MT7925_COMMON=m +CONFIG_MT792x_LIB=m +CONFIG_MT792x_USB=m +# CONFIG_MT7996E is not set +CONFIG_MTD=m +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTD_ABSENT=m +CONFIG_MTD_AMD76XROM=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_MTD_CFI=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_CK804XROM=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_DATAFLASH_OTP=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_DOCG3=m +CONFIG_MTD_ESB2ROM=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_HYPERBUS=m +CONFIG_MTD_ICHXROM=m +CONFIG_MTD_INTEL_DG=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_L440GX=m +CONFIG_MTD_LPDDR=m +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_NAND_DENALI=m +CONFIG_MTD_NAND_DENALI_PCI=m +CONFIG_MTD_NAND_DISKONCHIP=m +# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 +# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MXIC=y +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NETtel=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_ONENAND_GENERIC=m +# CONFIG_MTD_ONENAND_OTP is not set +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_OOPS=m +# CONFIG_MTD_PARTITIONED_MASTER is not set +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_PHRAM=m +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PLATRAM=m +CONFIG_MTD_PMC551=m +# CONFIG_MTD_PMC551_BUGFIX is not set +# CONFIG_MTD_PMC551_DEBUG is not set +CONFIG_MTD_QINFO_PROBE=m +CONFIG_MTD_RAM=m +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +CONFIG_MTD_REDBOOT_PARTS=m +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +CONFIG_MTD_ROM=m +CONFIG_MTD_SBC_GXX=m +CONFIG_MTD_SCB2_FLASH=m +CONFIG_MTD_SLRAM=m +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SST25L=m +CONFIG_MTD_SWAP=m +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=m +# CONFIG_MTD_UBI_NVMEM is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTK_NET_PHYLIB=m +CONFIG_MTK_T7XX=m +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_MULTIPLEXER=m +CONFIG_MULTIUSER=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MVMDIO=m +CONFIG_MWAVE=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_MXM_WMI=m +CONFIG_MYRI10GE=m +CONFIG_MYRI10GE_DCA=y +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +CONFIG_NATSEMI=m +CONFIG_NAU7802=m +CONFIG_NCN26000_PHY=m +# CONFIG_NCSI_OEM_CMD_GET_MAC is not set +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_NCT7201=m +CONFIG_ND_BTT=m +CONFIG_ND_CLAIM=y +CONFIG_ND_PFN=m +CONFIG_NE2K_PCI=m +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_NEED_SG_DMA_FLAGS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_TASKS_RCU=y +CONFIG_NET=y +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETDEVICES=y +CONFIG_NETDEVSIM=m +CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y +CONFIG_NETFILTER_XTABLES_LEGACY=y +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFS_DEBUG=y +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=m +# CONFIG_NETKIT is not set +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=m +CONFIG_NETPOLL=y +CONFIG_NETROM=m +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETXEN_NIC=m +CONFIG_NET_9P=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_RDMA=m +CONFIG_NET_9P_USBG=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CLS=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CORE=y +CONFIG_NET_CRC32C=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEVMEM=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NET_DROP_MONITOR=m +CONFIG_NET_DSA=m +CONFIG_NET_DSA_AR9331=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +# CONFIG_NET_DSA_KS8995 is not set +CONFIG_NET_DSA_LANTIQ_GSWIP=m +# CONFIG_NET_DSA_LOOP is not set +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=m +CONFIG_NET_DSA_MSCC_OCELOT_EXT=m +CONFIG_NET_DSA_MSCC_SEVILLE=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MT7530_MDIO=m +CONFIG_NET_DSA_MT7530_MMIO=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_LEDS=y +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +# CONFIG_NET_DSA_SJA1105_TAS is not set +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_NONE=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +CONFIG_NET_DSA_TAG_RZN1_A5PSW=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_VSC73XX_8021Q=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_EGRESS=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_FAILOVER=y +CONFIG_NET_FC=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_NET_HANDSHAKE=y +CONFIG_NET_IEEE8021Q_HELPERS=y +CONFIG_NET_IFE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_INGRESS=y +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_MPLS_GSO=m +CONFIG_NET_NCSI=y +CONFIG_NET_NS=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_REDIRECT=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_BPF is not set +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +# CONFIG_NET_SCH_DEFAULT is not set +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_DUALPI2=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_SCH_FIFO=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SHAPER=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TULIP=y +CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_ADI=y +CONFIG_NET_VENDOR_AGERE=y +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_ENGLEDER=y +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NETERION=y +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NET_VENDOR_NI=y +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_NET_VENDOR_VIA=y +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_NET_VRF=m +CONFIG_NET_XGRESS=y +CONFIG_NEW_LEDS=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_FDP=m +CONFIG_NFC_FDP_I2C=m +CONFIG_NFC_HCI=m +CONFIG_NFC_MEI_PHY=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MICROREAD_MEI=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_MRVL_SPI=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN544_MEI=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_SIM=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST95HF=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_APP_ABM_NIC=y +# CONFIG_NFP_APP_FLOWER is not set +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP_NET_IPSEC=y +CONFIG_NFSD=m +# CONFIG_NFSD_BLOCKLAYOUT is not set +# CONFIG_NFSD_FLEXFILELAYOUT is not set +# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set +# CONFIG_NFSD_SCSILAYOUT is not set +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +# CONFIG_NFSD_V4_2_INTER_SSC is not set +# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_COMMON_LOCALIO_SUPPORT=m +CONFIG_NFS_DEBUG=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFS_FS=m +CONFIG_NFS_FSCACHE=y +CONFIG_NFS_LOCALIO=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_NFS_V4_2=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COMPAT_ARP=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +# CONFIG_NFT_EXTHDR_DCCP is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_OSF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_XFRM=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CONNTRACK_PPTP=m +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE_PROCFS=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NGBE=m +CONFIG_NGBEVF=m +CONFIG_NI903X_WDT=m +CONFIG_NIC7018_WDT=m +CONFIG_NILFS2_FS=m +CONFIG_NINTENDO_FF=y +CONFIG_NITRO_ENCLAVES=m +CONFIG_NIU=m +CONFIG_NI_XGE_MANAGEMENT_ENET=m +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +CONFIG_NLMON=m +CONFIG_NLS=y +CONFIG_NLS_ASCII=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +# CONFIG_NMI_CHECK_CPU is not set +CONFIG_NOA1305=m +CONFIG_NODES_SHIFT=6 +CONFIG_NOP_TRACER=y +CONFIG_NOP_USB_XCEIV=m +CONFIG_NOTIFIER_ERROR_INJECTION=m +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_NOZOMI=m +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_PAGE_MAPCOUNT is not set +CONFIG_NR_CPUS=256 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NS83820=m +CONFIG_NSM=m +CONFIG_NTB=m +CONFIG_NTB_AMD=m +CONFIG_NTB_EPF=m +CONFIG_NTB_IDT=m +CONFIG_NTB_INTEL=m +CONFIG_NTB_MSI=y +CONFIG_NTB_MSI_TEST=m +CONFIG_NTB_NETDEV=m +CONFIG_NTB_PERF=m +CONFIG_NTB_PINGPONG=m +CONFIG_NTB_SWITCHTEC=m +CONFIG_NTB_TOOL=m +CONFIG_NTB_TRANSPORT=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_FS_POSIX_ACL is not set +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS_FS=m +CONFIG_NTSYNC=m +CONFIG_NULL_TTY=m +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NUMA_EMU is not set +CONFIG_NUMA_KEEP_MEMINFO=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NVDIMM_DAX=y +CONFIG_NVDIMM_KEYS=y +CONFIG_NVDIMM_PFN=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_NVIDIA_SHIELD_FF=y CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m -CONFIG_XIAOMI_WMI=m -CONFIG_GIGABYTE_WMI=m -CONFIG_ACERHDF=m -CONFIG_ACER_WIRELESS=m -CONFIG_ACER_WMI=m -CONFIG_AMD_HSMP_ACPI=y -CONFIG_AMD_HSMP_PLAT=m -CONFIG_AMD_PMF=m -CONFIG_AMD_PMC=m -CONFIG_AMD_HFI=y -CONFIG_AMD_3D_VCACHE=m -CONFIG_AMD_WBRF=y -CONFIG_AMD_ISP_PLATFORM=m -CONFIG_ADV_SWBUTTON=m -CONFIG_APPLE_GMUX=m -CONFIG_ASUS_LAPTOP=m -CONFIG_ASUS_WIRELESS=m -CONFIG_ASUS_WMI=m -CONFIG_ASUS_NB_WMI=m -CONFIG_ASUS_TF103C_DOCK=m -CONFIG_MERAKI_MX100=m -CONFIG_EEEPC_LAPTOP=m -CONFIG_EEEPC_WMI=m -CONFIG_X86_PLATFORM_DRIVERS_DELL=y -CONFIG_DELL_UART_BACKLIGHT=m -CONFIG_DELL_WMI_PRIVACY=y -CONFIG_AMILO_RFKILL=m -CONFIG_FUJITSU_LAPTOP=m -CONFIG_FUJITSU_TABLET=m -CONFIG_GPD_POCKET_FAN=m -CONFIG_X86_PLATFORM_DRIVERS_HP=y -CONFIG_WIRELESS_HOTKEY=m -CONFIG_IBM_RTL=m -CONFIG_SENSORS_HDAPS=m -CONFIG_INTEL_ATOMISP2_LED=m -CONFIG_INTEL_IFS=m -CONFIG_INTEL_SAR_INT1092=m -CONFIG_INTEL_SKL_INT3472=m -CONFIG_INTEL_PMC_CORE=m -CONFIG_INTEL_PMT_TELEMETRY=m -CONFIG_INTEL_PMT_CRASHLOG=m -CONFIG_INTEL_SPEED_SELECT_INTERFACE=m -CONFIG_INTEL_TELEMETRY=m -CONFIG_INTEL_WMI_SBL_FW_UPDATE=m -CONFIG_INTEL_WMI_THUNDERBOLT=m -CONFIG_INTEL_UNCORE_FREQ_CONTROL=m -CONFIG_INTEL_HID_EVENT=m -CONFIG_INTEL_VBTN=m -CONFIG_INTEL_INT0002_VGPIO=m -CONFIG_INTEL_OAKTRAIL=m -CONFIG_INTEL_BXTWC_PMIC_TMU=m -CONFIG_INTEL_BYTCRC_PWRSRC=m -CONFIG_INTEL_CHTDC_TI_PWRBTN=m -CONFIG_INTEL_CHTWC_INT33FE=m -CONFIG_INTEL_ISHTP_ECLITE=m -CONFIG_INTEL_MRFLD_PWRBTN=m -CONFIG_INTEL_PUNIT_IPC=m -CONFIG_INTEL_RST=m -CONFIG_INTEL_SDSI=m -CONFIG_INTEL_SMARTCONNECT=m -CONFIG_INTEL_TPMI=m -CONFIG_INTEL_PLR_TPMI=m -CONFIG_INTEL_VSEC=m -CONFIG_LENOVO_WMI_HOTKEY_UTILITIES=m -CONFIG_LENOVO_WMI_CAMERA=m -CONFIG_LENOVO_YMC=m -CONFIG_THINKPAD_ACPI=m -CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y -CONFIG_THINKPAD_LMI=m -CONFIG_YOGABOOK=m -CONFIG_YT2_1380=m -CONFIG_LENOVO_WMI_GAMEZONE=m -CONFIG_ACPI_QUICKSTART=m -CONFIG_MEEGOPAD_ANX7428=m -CONFIG_MSI_EC=m -CONFIG_MSI_LAPTOP=m -CONFIG_MSI_WMI=m -CONFIG_MSI_WMI_PLATFORM=m +CONFIG_NVMEM=y +# CONFIG_NVMEM_LAYOUTS is not set +CONFIG_NVMEM_RAVE_SP_EEPROM=m +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_SYSFS=y +CONFIG_NVME_AUTH=y +CONFIG_NVME_CORE=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_KEYRING=y +# CONFIG_NVME_MULTIPATH is not set +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET=m +# CONFIG_NVME_TARGET_AUTH is not set +CONFIG_NVME_TARGET_DEBUGFS=y +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_LOOP=m +# CONFIG_NVME_TARGET_PASSTHRU is not set +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_TCP_TLS=y +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +CONFIG_NVRAM=m +CONFIG_NV_TCO=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_CBTX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +CONFIG_OA_TC6=m +CONFIG_OBJAGG=m +CONFIG_OBJTOOL=y +# CONFIG_OBJTOOL_WERROR is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_OCFS2_DEBUG_MASKLOG=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCTEONEP_VDPA=m +CONFIG_OCTEON_EP=m +# CONFIG_OCTEON_EP_VF is not set +# CONFIG_OF is not set +CONFIG_OID_REGISTRY=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OMFS_FS=m +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPEN_ALLIANCE_HELPERS=y +CONFIG_OPT3001=m +CONFIG_OPT4001=m +CONFIG_OPT4060=m +CONFIG_OPTPROBES=y +CONFIG_ORANGEFS_FS=m +CONFIG_OSF_PARTITION=y +# CONFIG_OSNOISE_TRACER is not set +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVMF_DEBUG_LOG is not set +CONFIG_OVPN=y +CONFIG_OXP_EC=m +CONFIG_P2SB=y +CONFIG_P54_COMMON=m +CONFIG_P54_LEDS=y +CONFIG_P54_PCI=m +CONFIG_P54_SPI=m +# CONFIG_P54_SPI_DEFAULT_EEPROM is not set +CONFIG_P54_USB=m +CONFIG_PA12203001=m +CONFIG_PAC1921=m +# CONFIG_PAC1934 is not set +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_PACKING=y +CONFIG_PADATA=y +CONFIG_PAGE_BLOCK_MAX_ORDER=10 +CONFIG_PAGE_COUNTER=y +CONFIG_PAGE_EXTENSION=y +CONFIG_PAGE_IDLE_FLAG=y +CONFIG_PAGE_MAPCOUNT=y +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SHIFT=12 +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_VERSION=131 +CONFIG_PALMAS_GPADC=m +CONFIG_PANASONIC_LAPTOP=m +CONFIG_PANEL=m +# CONFIG_PANEL_CHANGE_MESSAGE is not set +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PANTHERLORD_FF=y +CONFIG_PARAVIRT=y +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_PARAVIRT_DEBUG is not set +CONFIG_PARAVIRT_SPINLOCKS=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_PARAVIRT_XXL=y +CONFIG_PARMAN=m +CONFIG_PARPORT=m +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_PARPORT_PANEL=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_PC_FIFO=y +CONFIG_PARPORT_PC_PCMCIA=m +# CONFIG_PARPORT_PC_SUPERIO is not set +CONFIG_PARPORT_SERIAL=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_PATA_ACPI=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_LEGACY=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PARPORT=m +CONFIG_PATA_PARPORT_ATEN=m +CONFIG_PATA_PARPORT_BPCK=m +CONFIG_PATA_PARPORT_BPCK6=m +CONFIG_PATA_PARPORT_COMM=m +CONFIG_PATA_PARPORT_DSTR=m +CONFIG_PATA_PARPORT_EPAT=m +CONFIG_PATA_PARPORT_EPATC8=y +CONFIG_PATA_PARPORT_EPIA=m +CONFIG_PATA_PARPORT_FIT2=m +CONFIG_PATA_PARPORT_FIT3=m +CONFIG_PATA_PARPORT_FRIQ=m +CONFIG_PATA_PARPORT_FRPW=m +CONFIG_PATA_PARPORT_KBIC=m +CONFIG_PATA_PARPORT_KTTI=m +CONFIG_PATA_PARPORT_ON20=m +CONFIG_PATA_PARPORT_ON26=m +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_RZ1000=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=y +CONFIG_PATA_TIMINGS=y +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +# CONFIG_PC104 is not set +CONFIG_PC300TOO=m +CONFIG_PC87413_WDT=m +CONFIG_PCC=y +CONFIG_PCCARD=m +CONFIG_PCCARD_NONSTATIC=y CONFIG_PCENGINES_APU2=m +CONFIG_PCI=y +CONFIG_PCI200SYN=m +CONFIG_PCIEAER=y +CONFIG_PCIEAER_CXL=y +# CONFIG_PCIEAER_INJECT is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_DPC=y +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +CONFIG_PCIE_THERMAL=y +CONFIG_PCIE_TPH=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_ATS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_DIRECT=y +CONFIG_PCI_DOE=y +CONFIG_PCI_DOMAINS=y +# CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +CONFIG_PCI_LOCKLESS_CONFIG=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MMCONFIG=y +CONFIG_PCI_MSI=y +CONFIG_PCI_NPEM=y +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_PASID=y +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTRL=m +CONFIG_PCI_PWRCTRL_SLOT=m +CONFIG_PCI_QUIRKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +CONFIG_PCI_SW_SWITCHTEC=m +CONFIG_PCI_XEN=y +CONFIG_PCMCIA=m +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_AXNET=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PCMCIA_PCNET=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SMC91C92=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_PCNET32=m +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PCS_LYNX=m +CONFIG_PCS_MTK_LYNXI=m +CONFIG_PCS_XPCS=m +CONFIG_PD6729=m +CONFIG_PDC_ADMA=m +CONFIG_PDS_CORE=m +CONFIG_PDS_VDPA=m +CONFIG_PDS_VFIO_PCI=m +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_PERCPU_TEST=m +CONFIG_PERF_EVENTS=y +CONFIG_PERF_EVENTS_AMD_BRS=y +CONFIG_PERF_EVENTS_AMD_POWER=m +CONFIG_PERF_EVENTS_AMD_UNCORE=m +CONFIG_PERF_EVENTS_INTEL_CSTATE=y +CONFIG_PERF_EVENTS_INTEL_RAPL=y +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +CONFIG_PFCP=m +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_PHANTOM=m +CONFIG_PHONET=m +CONFIG_PHYLIB=y +CONFIG_PHYLINK=m +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_INTEL_LGM_EMMC=m +CONFIG_PHY_PACKAGE=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_PHY_TUSB1210=m +CONFIG_PID_NS=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ALDERLAKE=m +CONFIG_PINCTRL_AMD=y +CONFIG_PINCTRL_AMDISP=m +CONFIG_PINCTRL_BAYTRAIL=y +CONFIG_PINCTRL_BROXTON=m +CONFIG_PINCTRL_CANNONLAKE=m +CONFIG_PINCTRL_CEDARFORK=m +CONFIG_PINCTRL_CHERRYVIEW=y +# CONFIG_PINCTRL_CS42L43 is not set +CONFIG_PINCTRL_CY8C95X0=m +# CONFIG_PINCTRL_DA9062 is not set +CONFIG_PINCTRL_DENVERTON=m +CONFIG_PINCTRL_ELKHARTLAKE=m +CONFIG_PINCTRL_EMMITSBURG=m +CONFIG_PINCTRL_GEMINILAKE=m +CONFIG_PINCTRL_ICELAKE=m +CONFIG_PINCTRL_INTEL=y +CONFIG_PINCTRL_INTEL_PLATFORM=m +CONFIG_PINCTRL_JASPERLAKE=m +CONFIG_PINCTRL_LAKEFIELD=m +CONFIG_PINCTRL_LEWISBURG=m +CONFIG_PINCTRL_LYNXPOINT=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_METEORLAKE=m +CONFIG_PINCTRL_METEORPOINT=m +CONFIG_PINCTRL_SUNRISEPOINT=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_TIGERLAKE=m +# CONFIG_PINCTRL_UPBOARD is not set +CONFIG_PING=m +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PLATFORM_SI4713=m +CONFIG_PLAYSTATION_FF=y +CONFIG_PLDMFW=y +CONFIG_PLFXLC=m +CONFIG_PLIP=m +CONFIG_PLX_DMA=m +CONFIG_PM=y +CONFIG_PMBUS=m +CONFIG_PMIC_ADP5520=y +CONFIG_PMIC_DA903X=y +CONFIG_PMIC_DA9052=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_PMS7003=m +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_NOTIFIER_ERROR_INJECT=m +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_PNP=y +CONFIG_PNPACPI=y +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_POLYNOMIAL=m CONFIG_PORTWELL_EC=m -CONFIG_BARCO_P50_GPIO=m -CONFIG_SAMSUNG_GALAXYBOOK=m -CONFIG_SAMSUNG_LAPTOP=m -CONFIG_SAMSUNG_Q10=m -CONFIG_ACPI_TOSHIBA=m -CONFIG_TOSHIBA_BT_RFKILL=m -CONFIG_TOSHIBA_HAPS=m -CONFIG_TOSHIBA_WMI=m -CONFIG_ACPI_CMPC=m -CONFIG_COMPAL_LAPTOP=m -CONFIG_LG_LAPTOP=m -CONFIG_PANASONIC_LAPTOP=m -CONFIG_SONY_LAPTOP=m -CONFIG_SONYPI_COMPAT=y -CONFIG_SYSTEM76_ACPI=m -CONFIG_TOPSTAR_LAPTOP=m -CONFIG_INSPUR_PLATFORM_PROFILE=m -CONFIG_DASHARO_ACPI=m -CONFIG_INTEL_IPS=m -CONFIG_INTEL_SCU_PCI=y -CONFIG_INTEL_SCU_PLATFORM=m -CONFIG_INTEL_SCU_IPC_UTIL=m -CONFIG_SIEMENS_SIMATIC_IPC=m -CONFIG_SILICOM_PLATFORM=m -CONFIG_WINMATE_FM07_KEYS=m -CONFIG_SEL3350_PLATFORM=m -CONFIG_OXP_EC=m -CONFIG_TUXEDO_NB04_WMI_AB=m -CONFIG_COMMON_CLK_WM831X=m -CONFIG_LMK04832=m -CONFIG_COMMON_CLK_MAX9485=m -CONFIG_COMMON_CLK_SI5341=m -CONFIG_COMMON_CLK_SI5351=m -CONFIG_COMMON_CLK_SI544=m -CONFIG_COMMON_CLK_CDCE706=m -CONFIG_COMMON_CLK_TPS68470=m -CONFIG_COMMON_CLK_CS2000_CP=m -CONFIG_CLK_TWL=m -CONFIG_CLK_TWL6040=m -CONFIG_COMMON_CLK_PALMAS=m -CONFIG_COMMON_CLK_PWM=m -CONFIG_XILINX_VCU=m -CONFIG_ALTERA_MBOX=m -CONFIG_AMD_IOMMU=y -CONFIG_INTEL_IOMMU=y -CONFIG_INTEL_IOMMU_SVM=y -# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set -# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set -# CONFIG_INTEL_IOMMU_PERF_EVENTS is not set -CONFIG_IRQ_REMAP=y -CONFIG_VIRTIO_IOMMU=m -CONFIG_RPMSG_QCOM_GLINK_RPM=m -CONFIG_RPMSG_VIRTIO=m -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_AMD=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_WPCM450_SOC=m +# CONFIG_POSIX_AUX_CLOCKS is not set +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POSIX_TIMERS=y +CONFIG_POWERCAP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +# CONFIG_POWER_RESET_MT6323 is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_TPS65086=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPDEV=m +CONFIG_PPP=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOE_HASH_BITS=4 +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS=m +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +# CONFIG_PPS_DEBUG is not set +CONFIG_PPS_GENERATOR=m +# CONFIG_PPS_GENERATOR_DUMMY is not set +CONFIG_PPS_GENERATOR_TIO=m +CONFIG_PPTP=m +# CONFIG_PREEMPT is not set +CONFIG_PREEMPTION=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPT_LAZY is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PREEMPT_RCU=y +# CONFIG_PREEMPT_RT is not set +# CONFIG_PREEMPT_TRACER is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREFIX_SYMBOLS=y +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRIME_NUMBERS=m +CONFIG_PRINTER=m +CONFIG_PRINTK=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_PRINTK_INDEX is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_MEM_ALWAYS_FORCE=y +# CONFIG_PROC_MEM_FORCE_PTRACE is not set +# CONFIG_PROC_MEM_NO_FORCE is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_THERMAL_MMIO_RAPL=m +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +CONFIG_PSAMPLE=m +CONFIG_PSE_CONTROLLER=y +CONFIG_PSE_PD692X0=m +CONFIG_PSE_REGULATOR=m +# CONFIG_PSE_SI3474 is not set +CONFIG_PSE_TPS23881=m +CONFIG_PSI=y +# CONFIG_PSI_DEFAULT_DISABLED is not set +CONFIG_PSTORE=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTE_MARKER_UFFD_WP=y +CONFIG_PTP_1588_CLOCK=m +# CONFIG_PTP_1588_CLOCK_FC3W is not set +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_KVM=m +# CONFIG_PTP_1588_CLOCK_MOCK is not set +CONFIG_PTP_1588_CLOCK_OCP=m +CONFIG_PTP_1588_CLOCK_OPTIONAL=m +CONFIG_PTP_1588_CLOCK_VMCLOCK=m +# CONFIG_PTP_1588_CLOCK_VMW is not set +CONFIG_PTP_DFL_TOD=m +# CONFIG_PTP_NETC_V4_TIMER is not set +CONFIG_PT_RECLAIM=y +CONFIG_PUNIT_ATOM_DEBUG=m +CONFIG_PVH=y +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_PWM=y +CONFIG_PWM_CLK=m +CONFIG_PWM_CRC=y +CONFIG_PWM_CROS_EC=m +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_DWC=m +CONFIG_PWM_DWC_CORE=m +CONFIG_PWM_GPIO=m +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_LPSS=m +CONFIG_PWM_LPSS_PCI=m +CONFIG_PWM_LPSS_PLATFORM=m +CONFIG_PWM_PCA9685=m +# CONFIG_PWM_PROVIDE_GPIO is not set +CONFIG_PWM_TWL=m +CONFIG_PWM_TWL_LED=m +CONFIG_QAT_VFIO_PCI=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m +CONFIG_QCOM_EMAC=m +CONFIG_QCOM_HIDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_NET_PHYLIB=m +# CONFIG_QCOM_PBS is not set CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m -CONFIG_SOC_TI=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -CONFIG_DEVFREQ_GOV_PASSIVE=m -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_EXTCON_ADC_JACK=m -CONFIG_EXTCON_AXP288=m -CONFIG_EXTCON_FSA9480=m -CONFIG_EXTCON_GPIO=m -CONFIG_EXTCON_INTEL_INT3496=m -CONFIG_EXTCON_INTEL_CHT_WC=m -CONFIG_EXTCON_INTEL_MRFLD=m -CONFIG_EXTCON_LC824206XA=m -CONFIG_EXTCON_MAX14577=m -CONFIG_EXTCON_MAX3355=m -CONFIG_EXTCON_MAX77693=m -CONFIG_EXTCON_MAX77843=m -CONFIG_EXTCON_MAX8997=m -CONFIG_EXTCON_PALMAS=m -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_RT8973A=m -CONFIG_EXTCON_SM5502=m -CONFIG_EXTCON_USB_GPIO=m -CONFIG_EXTCON_USBC_CROS_EC=m -CONFIG_EXTCON_USBC_TUSB320=m -CONFIG_MEMORY=y -CONFIG_FPGA_DFL_EMIF=m -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_ADIS16201=m -CONFIG_ADIS16209=m -CONFIG_ADXL313_I2C=m -CONFIG_ADXL313_SPI=m -CONFIG_ADXL355_I2C=m -CONFIG_ADXL355_SPI=m -CONFIG_ADXL367_SPI=m -CONFIG_ADXL367_I2C=m -CONFIG_ADXL372_SPI=m -CONFIG_ADXL372_I2C=m -CONFIG_ADXL380_SPI=m -CONFIG_ADXL380_I2C=m -CONFIG_BMA220=m -CONFIG_BMA400=m -CONFIG_BMC150_ACCEL=m -CONFIG_BMI088_ACCEL=m -CONFIG_DA280=m -CONFIG_DA311=m -CONFIG_DMARD06=m -CONFIG_DMARD09=m -CONFIG_DMARD10=m -CONFIG_FXLS8962AF_I2C=m -CONFIG_FXLS8962AF_SPI=m -CONFIG_HID_SENSOR_ACCEL_3D=m -CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m -CONFIG_IIO_KX022A_SPI=m -CONFIG_IIO_KX022A_I2C=m -CONFIG_KXSD9=m -CONFIG_KXCJK1013=m -CONFIG_MC3230=m -CONFIG_MMA7455_I2C=m -CONFIG_MMA7455_SPI=m -CONFIG_MMA7660=m -CONFIG_MMA8452=m -CONFIG_MMA9551=m -CONFIG_MMA9553=m -CONFIG_MSA311=m -CONFIG_MXC4005=m -CONFIG_MXC6255=m -CONFIG_SCA3000=m -CONFIG_SCA3300=m -CONFIG_STK8312=m -CONFIG_STK8BA50=m -CONFIG_AD4000=m -CONFIG_AD4030=m -CONFIG_AD4080=m -CONFIG_AD4130=m -CONFIG_AD4170_4=m -CONFIG_AD4695=m -CONFIG_AD4851=m -CONFIG_AD7091R5=m -CONFIG_AD7091R8=m -CONFIG_AD7124=m -CONFIG_AD7173=m -CONFIG_AD7191=m -CONFIG_AD7192=m -CONFIG_AD7266=m -CONFIG_AD7280=m -CONFIG_AD7291=m -CONFIG_AD7292=m -CONFIG_AD7298=m -CONFIG_AD7380=m -CONFIG_AD7405=m -CONFIG_AD7476=m -CONFIG_AD7606_IFACE_PARALLEL=m -CONFIG_AD7606_IFACE_SPI=m -CONFIG_AD7625=m -CONFIG_AD7766=m -CONFIG_AD7768_1=m -CONFIG_AD7779=m -CONFIG_AD7780=m -CONFIG_AD7791=m -CONFIG_AD7793=m -CONFIG_AD7887=m -CONFIG_AD7923=m -CONFIG_AD7944=m -CONFIG_AD7949=m -CONFIG_AD799X=m -CONFIG_AXP20X_ADC=m -CONFIG_AXP288_ADC=m -CONFIG_CC10001_ADC=m -CONFIG_DA9150_GPADC=m -CONFIG_DLN2_ADC=m -CONFIG_ENVELOPE_DETECTOR=m -CONFIG_GEHC_PMC_ADC=m -CONFIG_HI8435=m -CONFIG_HX711=m -CONFIG_INA2XX_ADC=m -CONFIG_INTEL_MRFLD_ADC=m -CONFIG_LP8788_ADC=m -CONFIG_LTC2309=m -CONFIG_LTC2471=m -CONFIG_LTC2485=m -CONFIG_LTC2496=m -CONFIG_LTC2497=m -CONFIG_MAX1027=m -CONFIG_MAX11100=m -CONFIG_MAX1118=m -CONFIG_MAX11205=m -CONFIG_MAX11410=m -CONFIG_MAX1241=m -CONFIG_MAX1363=m -CONFIG_MAX34408=m -CONFIG_MAX77541_ADC=m -CONFIG_MAX9611=m -CONFIG_MCP320X=m -CONFIG_MCP3422=m -CONFIG_MCP3564=m -CONFIG_MCP3911=m -CONFIG_MEDIATEK_MT6359_AUXADC=m -CONFIG_MEDIATEK_MT6370_ADC=m -CONFIG_MEN_Z188_ADC=m -CONFIG_MP2629_ADC=m -CONFIG_NAU7802=m -CONFIG_NCT7201=m -CONFIG_PAC1921=m -CONFIG_PALMAS_GPADC=m +CONFIG_QCOM_QMI_HELPERS=m +CONFIG_QCOM_SPMI_ADC5=m CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROHM_BD79124=m +CONFIG_QCOM_VADC_COMMON=m +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED_FCOE=y +CONFIG_QED_ISCSI=y +CONFIG_QED_LL2=y +CONFIG_QED_OOO=y +CONFIG_QED_RDMA=y +CONFIG_QED_SRIOV=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_QLCNIC_SRIOV=y +CONFIG_QNX4FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_QNX6FS_FS=m +CONFIG_QRTR=m +CONFIG_QRTR_MHI=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QSEMI_PHY=m +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA_TREE=m +CONFIG_R6040=m +CONFIG_R8169=m +CONFIG_R8169_LEDS=y +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI470X=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_SI476X=m +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_CPS_XX=m +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAS=y +# CONFIG_RAS_CEC is not set +CONFIG_RAS_FMPM=m +CONFIG_RATIONAL=y +CONFIG_RAVE_SP_CORE=m +CONFIG_RAVE_SP_WATCHDOG=m +# CONFIG_RBTREE_TEST is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_RC_LOOPBACK=m +CONFIG_RC_MAP=m +CONFIG_RC_XBOX_DVD=m +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_RDS=m +# CONFIG_RDS_DEBUG is not set +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=m +CONFIG_REALTEK_PHY_HWMON=y +# CONFIG_REDMI_WMI is not set +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_ENC8=y +# CONFIG_REED_SOLOMON_TEST is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SCCB=m +CONFIG_REGMAP_SOUNDWIRE=m +CONFIG_REGMAP_SOUNDWIRE_MBQ=m +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_88PG86X=m +CONFIG_REGULATOR_88PM800=m +CONFIG_REGULATOR_88PM8607=m +CONFIG_REGULATOR_AAT2870=m +CONFIG_REGULATOR_ACT8865=m +CONFIG_REGULATOR_AD5398=m +CONFIG_REGULATOR_ADP5055=m +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_AS3711=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AW37503=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BCM590XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_DA903X=m +CONFIG_REGULATOR_DA9052=m +CONFIG_REGULATOR_DA9055=m +CONFIG_REGULATOR_DA9062=m +CONFIG_REGULATOR_DA9210=m +CONFIG_REGULATOR_DA9211=m +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FIXED_VOLTAGE=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_ISL6271A=m +CONFIG_REGULATOR_ISL9305=m +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LP3971=m +CONFIG_REGULATOR_LP3972=m +CONFIG_REGULATOR_LP872X=m +CONFIG_REGULATOR_LP8755=m +CONFIG_REGULATOR_LP8788=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +CONFIG_REGULATOR_MAX14577=m +CONFIG_REGULATOR_MAX1586=m +CONFIG_REGULATOR_MAX20086=m +CONFIG_REGULATOR_MAX20411=m +CONFIG_REGULATOR_MAX77503=m +CONFIG_REGULATOR_MAX77541=m +CONFIG_REGULATOR_MAX77693=m +CONFIG_REGULATOR_MAX77826=m +# CONFIG_REGULATOR_MAX77838 is not set +CONFIG_REGULATOR_MAX77857=m +CONFIG_REGULATOR_MAX8649=m +CONFIG_REGULATOR_MAX8660=m +CONFIG_REGULATOR_MAX8893=m +CONFIG_REGULATOR_MAX8907=m +CONFIG_REGULATOR_MAX8925=m +CONFIG_REGULATOR_MAX8952=m +CONFIG_REGULATOR_MAX8997=m +CONFIG_REGULATOR_MAX8998=m +CONFIG_REGULATOR_MC13783=m +CONFIG_REGULATOR_MC13892=m +CONFIG_REGULATOR_MC13XXX_CORE=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MT6311=m +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6323=m +CONFIG_REGULATOR_MT6331=m +CONFIG_REGULATOR_MT6332=m +CONFIG_REGULATOR_MT6357=m +CONFIG_REGULATOR_MT6358=m +CONFIG_REGULATOR_MT6359=m +CONFIG_REGULATOR_MT6360=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_MT6397=m +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +CONFIG_REGULATOR_PALMAS=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PCAP=m +# CONFIG_REGULATOR_PF0900 is not set +CONFIG_REGULATOR_PF9453=m +CONFIG_REGULATOR_PV88060=m +CONFIG_REGULATOR_PV88080=m +CONFIG_REGULATOR_PV88090=m +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RAA215300=m +CONFIG_REGULATOR_RC5T583=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5033=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTQ2208=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_TPS51632=m +CONFIG_REGULATOR_TPS6105X=m +CONFIG_REGULATOR_TPS62360=m +CONFIG_REGULATOR_TPS65023=m +CONFIG_REGULATOR_TPS6507X=m +CONFIG_REGULATOR_TPS65086=m +CONFIG_REGULATOR_TPS65090=m +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS6524X=m +CONFIG_REGULATOR_TPS6586X=m +CONFIG_REGULATOR_TPS65910=m +CONFIG_REGULATOR_TPS65912=m +CONFIG_REGULATOR_TPS68470=m +CONFIG_REGULATOR_TWL4030=m +CONFIG_REGULATOR_USERSPACE_CONSUMER=m +CONFIG_REGULATOR_VIRTUAL_CONSUMER=m +CONFIG_REGULATOR_WM831X=m +CONFIG_REGULATOR_WM8350=m +CONFIG_REGULATOR_WM8400=m +CONFIG_REGULATOR_WM8994=m +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC is not set +CONFIG_REMOTE_TARGET=m +CONFIG_RENESAS_PHY=m +CONFIG_RESET_ATTACK_MITIGATION=y +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_RETHOOK=y +CONFIG_RETU_WATCHDOG=m +CONFIG_RFD77402=m +CONFIG_RFD_FTL=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFS_ACCEL=y CONFIG_RICHTEK_RTQ6056=m -CONFIG_SD_ADC_MODULATOR=m -CONFIG_TI_ADC081C=m -CONFIG_TI_ADC0832=m -CONFIG_TI_ADC084S021=m -CONFIG_TI_ADC108S102=m -CONFIG_TI_ADC12138=m -CONFIG_TI_ADC128S052=m -CONFIG_TI_ADC161S626=m -CONFIG_TI_ADS1015=m -CONFIG_TI_ADS1100=m -CONFIG_TI_ADS1119=m -CONFIG_TI_ADS124S08=m -CONFIG_TI_ADS131E08=m -CONFIG_TI_ADS7138=m -CONFIG_TI_ADS7924=m -CONFIG_TI_ADS7950=m -CONFIG_TI_ADS8344=m -CONFIG_TI_ADS8688=m -CONFIG_TI_LMP92064=m -CONFIG_TI_TLC4541=m -CONFIG_TI_TSC2046=m -CONFIG_TWL4030_MADC=m -CONFIG_TWL6030_GPADC=m -CONFIG_VF610_ADC=m -CONFIG_VIPERBOARD_ADC=m -CONFIG_XILINX_XADC=m -CONFIG_AD74115=m -CONFIG_AD74413R=m -CONFIG_IIO_RESCALE=m -CONFIG_AD8366=m -CONFIG_ADA4250=m -CONFIG_HMC425=m -CONFIG_AD7150=m -CONFIG_AD7746=m -CONFIG_AOSONG_AGS02MA=m -CONFIG_ATLAS_PH_SENSOR=m -CONFIG_ATLAS_EZO_SENSOR=m -CONFIG_BME680=m -CONFIG_CCS811=m -CONFIG_ENS160=m -CONFIG_IAQCORE=m -CONFIG_MHZ19B=m -CONFIG_PMS7003=m +CONFIG_RING_BUFFER=y +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RIONET=m +CONFIG_RIONET_RX_SIZE=128 +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F1A=y +CONFIG_RMI4_F21=y +CONFIG_RMI4_F30=y +# CONFIG_RMI4_F34 is not set +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +CONFIG_RMI4_F55=y +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +CONFIG_RMNET=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_ROCKER=m +# CONFIG_ROHM_BD79112 is not set +CONFIG_ROHM_BD79124=m +CONFIG_ROHM_BM1390=m +CONFIG_ROHM_BU27034=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROSE=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +CONFIG_RPMB=m +CONFIG_RPMSG=m +# CONFIG_RPMSG_CHAR is not set +# CONFIG_RPMSG_CTRL is not set +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_TTY=m +CONFIG_RPMSG_VIRTIO=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_RPR0521=m +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RSI_91X=m +CONFIG_RSI_COEX=y +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT2500USB=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00=m +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_CRYPTO=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_LEDS=y +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT61PCI=m +CONFIG_RT73USB=m +CONFIG_RTASE=m +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_DRV_88PM80X=m +CONFIG_RTC_DRV_88PM860X=m +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_CROS_EC=m +CONFIG_RTC_DRV_DA9052=m +CONFIG_RTC_DRV_DA9055=m +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1307=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685=y +CONFIG_RTC_DRV_DS1685_FAMILY=m +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_GOLDFISH=m +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_LP8788=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_M48T86=m +CONFIG_RTC_DRV_MAX31335=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_MAX8907=m +CONFIG_RTC_DRV_MAX8925=m +CONFIG_RTC_DRV_MAX8997=m +CONFIG_RTC_DRV_MAX8998=m +CONFIG_RTC_DRV_MC13XXX=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_MT6397=m +CONFIG_RTC_DRV_PALMAS=m +CONFIG_RTC_DRV_PCAP=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RC5T583=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RV3029_HWMON=y +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RX6110=m +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_RX8111=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_SD2405AL=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_TPS6586X=m +CONFIG_RTC_DRV_TPS65910=m +CONFIG_RTC_DRV_TPS6594=m +CONFIG_RTC_DRV_WILCO_EC=m +CONFIG_RTC_DRV_WM831X=m +CONFIG_RTC_DRV_WM8350=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_NVMEM=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192D_COMMON=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723BS=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTLBTCOEXIST=m +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTL_CARDS=m +CONFIG_RTW88=m +CONFIG_RTW88_8703B=m +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8723X=m +CONFIG_RTW88_8812A=m +CONFIG_RTW88_8812AU=m +CONFIG_RTW88_8814A=m +CONFIG_RTW88_8814AE=m +CONFIG_RTW88_8814AU=m +CONFIG_RTW88_8821A=m +CONFIG_RTW88_8821AU=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_88XXA=m +CONFIG_RTW88_CORE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW88_LEDS=y +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW89=m +CONFIG_RTW89_8851B=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BT=m +CONFIG_RTW89_8852BTE=m +CONFIG_RTW89_8852BU=m +CONFIG_RTW89_8852B_COMMON=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922A=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_CORE=m +# CONFIG_RTW89_DEBUGFS is not set +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89_PCI=m +CONFIG_RTW89_USB=m +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_RT_MUTEXES=y +CONFIG_RUNTIME_TESTING_MENU=y +CONFIG_RUSTC_HAS_COERCE_POINTEE=y +CONFIG_RUSTC_HAS_FILE_AS_C_STR=y +CONFIG_RUSTC_HAS_FILE_WITH_NUL=y +CONFIG_RUSTC_HAS_SPAN_FILE=y +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES=y +CONFIG_RUSTC_LLVM_VERSION=210108 +CONFIG_RUSTC_VERSION=109500 +CONFIG_RUST_IS_AVAILABLE=y +# CONFIG_RV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RXGK=y +# CONFIG_RXKAD is not set +# CONFIG_RXPERF is not set +CONFIG_S2IO=m +# CONFIG_SAMPLES is not set +CONFIG_SAMSUNG_GALAXYBOOK=m +CONFIG_SAMSUNG_LAPTOP=m +CONFIG_SAMSUNG_Q10=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_SATA_DWC=m +# CONFIG_SATA_DWC_OLD_DMA is not set +CONFIG_SATA_HOST=y +CONFIG_SATA_INIC162X=m +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PMP=y +CONFIG_SATA_PROMISE=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_SX4=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_SATA_ZPODD=y +CONFIG_SBC_EPX_C3_WATCHDOG=m +CONFIG_SBC_FITPC2_WATCHDOG=m +CONFIG_SBITMAP=y +CONFIG_SBP_TARGET=m +CONFIG_SC1200_WDT=m +CONFIG_SC92031=m +CONFIG_SCA3000=m +CONFIG_SCA3300=m CONFIG_SCD30_CORE=m CONFIG_SCD30_I2C=m CONFIG_SCD30_SERIAL=m CONFIG_SCD4X=m -CONFIG_SEN0322=m -CONFIG_SENSIRION_SGP30=m -CONFIG_SENSIRION_SGP40=m -CONFIG_SPS30_I2C=m -CONFIG_SPS30_SERIAL=m -CONFIG_SENSEAIR_SUNRISE_CO2=m -CONFIG_VZ89X=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m -CONFIG_IIO_CROS_EC_ACTIVITY=m -CONFIG_IIO_SSP_SENSORS_COMMONS=m -CONFIG_IIO_SSP_SENSORHUB=m -CONFIG_AD3530R=m -CONFIG_AD3552R_HS=m -CONFIG_AD3552R=m -CONFIG_AD5064=m -CONFIG_AD5360=m -CONFIG_AD5380=m -CONFIG_AD5421=m -CONFIG_AD5446=m -CONFIG_AD5449=m -CONFIG_AD5592R=m -CONFIG_AD5593R=m -CONFIG_AD5504=m -CONFIG_AD5624R_SPI=m -CONFIG_AD9739A=m -CONFIG_LTC2688=m -CONFIG_AD5686_SPI=m -CONFIG_AD5696_I2C=m -CONFIG_AD5755=m -CONFIG_AD5758=m -CONFIG_AD5761=m -CONFIG_AD5764=m -CONFIG_AD5766=m -CONFIG_AD5770R=m -CONFIG_AD5791=m -CONFIG_AD7293=m -CONFIG_AD7303=m -CONFIG_AD8460=m -CONFIG_AD8801=m -CONFIG_BD79703=m -CONFIG_DPOT_DAC=m -CONFIG_DS4424=m -CONFIG_LTC1660=m -CONFIG_LTC2632=m -CONFIG_LTC2664=m -CONFIG_M62332=m -CONFIG_MAX517=m -CONFIG_MAX5522=m -CONFIG_MAX5821=m -CONFIG_MCP4725=m -CONFIG_MCP4728=m -CONFIG_MCP4821=m -CONFIG_MCP4922=m -CONFIG_TI_DAC082S085=m -CONFIG_TI_DAC5571=m -CONFIG_TI_DAC7311=m -CONFIG_TI_DAC7612=m -CONFIG_VF610_DAC=m -CONFIG_IIO_SIMPLE_DUMMY=m -CONFIG_ADMV8818=m -CONFIG_AD9523=m -CONFIG_ADF4350=m -CONFIG_ADF4371=m -CONFIG_ADF4377=m -CONFIG_ADMV1013=m -CONFIG_ADMV1014=m -CONFIG_ADMV4420=m -CONFIG_ADRF6780=m -CONFIG_ADIS16080=m -CONFIG_ADIS16130=m -CONFIG_ADIS16136=m -CONFIG_ADIS16260=m -CONFIG_ADXRS290=m -CONFIG_ADXRS450=m -CONFIG_BMG160=m -CONFIG_FXAS21002C=m -CONFIG_HID_SENSOR_GYRO_3D=m -CONFIG_MPU3050_I2C=m -CONFIG_IIO_ST_GYRO_3AXIS=m -CONFIG_ITG3200=m -CONFIG_AFE4403=m -CONFIG_AFE4404=m -CONFIG_MAX30100=m -CONFIG_MAX30102=m -CONFIG_AM2315=m -CONFIG_DHT11=m -CONFIG_ENS210=m -CONFIG_HDC100X=m -CONFIG_HDC2010=m -CONFIG_HDC3020=m -CONFIG_HID_SENSOR_HUMIDITY=m -CONFIG_HTS221=m -CONFIG_HTU21=m -CONFIG_SI7005=m -CONFIG_SI7020=m -CONFIG_ADIS16400=m -CONFIG_ADIS16460=m -CONFIG_ADIS16475=m -CONFIG_ADIS16480=m -CONFIG_ADIS16550=m -CONFIG_BMI160_I2C=m -CONFIG_BMI160_SPI=m -CONFIG_BMI270_I2C=m -CONFIG_BMI270_SPI=m -CONFIG_BMI323_I2C=m -CONFIG_BMI323_SPI=m -CONFIG_BOSCH_BNO055_SERIAL=m -CONFIG_BOSCH_BNO055_I2C=m -CONFIG_FXOS8700_I2C=m -CONFIG_FXOS8700_SPI=m -CONFIG_KMX61=m -CONFIG_INV_ICM42600_I2C=m -CONFIG_INV_ICM42600_SPI=m -CONFIG_INV_MPU6050_I2C=m -CONFIG_INV_MPU6050_SPI=m -CONFIG_SMI240=m -CONFIG_IIO_ST_LSM6DSX=m -CONFIG_IIO_ST_LSM9DS0=m -CONFIG_ACPI_ALS=m -CONFIG_ADJD_S311=m -CONFIG_ADUX1020=m -CONFIG_AL3000A=m -CONFIG_AL3010=m -CONFIG_AL3320A=m -CONFIG_APDS9160=m -CONFIG_APDS9300=m -CONFIG_APDS9306=m -CONFIG_APDS9960=m -CONFIG_AS73211=m -CONFIG_BH1745=m -CONFIG_BH1750=m -CONFIG_BH1780=m -CONFIG_CM32181=m -CONFIG_CM3232=m -CONFIG_CM3323=m -CONFIG_CM3605=m -CONFIG_CM36651=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_GP2AP002=m -CONFIG_GP2AP020A00F=m -CONFIG_IQS621_ALS=m +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CLASS_EXT is not set +CONFIG_SCHED_CLUSTER=y +CONFIG_SCHED_CORE=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_SCHED_MM_CID=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCHED_PROXY_EXEC is not set +CONFIG_SCHED_SMT=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_SCHED_TRACER=y +CONFIG_SCREEN_INFO=y +CONFIG_SCSI=y +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_AIC79XX=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_SCSI_AIC94XX=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DMA=y +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_ESAS2R=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_FLASHPOINT=y +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_IMM=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPS=m +CONFIG_SCSI_ISCI=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_IZIP_SLOW_CTR is not set +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_MOD=y +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +# CONFIG_SCSI_MVSAS_TASKLET is not set +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PPA=m +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PCI=m +CONFIG_SCSI_UFSHCD_PLATFORM=m +# CONFIG_SCSI_UFS_BSG is not set +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +CONFIG_SCSI_UFS_CRYPTO=y +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_WD719X=m +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y +CONFIG_SDIO_UART=m +# CONFIG_SDMA_VERBOSITY is not set +CONFIG_SDP500=m +CONFIG_SDR_MAX2175=m +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_SD_ADC_MODULATOR=m +CONFIG_SECCOMP=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +CONFIG_SECURITY_DMESG_RESTRICT=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_IPE is not set +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DEBUG=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SMACK=y +# CONFIG_SECURITY_SMACK_APPEND_SIGNALS is not set +# CONFIG_SECURITY_SMACK_BRINGUP is not set +CONFIG_SECURITY_SMACK_NETFILTER=y +CONFIG_SECURITY_TOMOYO=y +CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init" +# CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set +CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048 +CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024 +# CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER is not set +CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init" +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +CONFIG_SEL3350_PLATFORM=m +CONFIG_SEN0322=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SENSIRION_SGP40=m +CONFIG_SENSORS_ABITUGURU=m +CONFIG_SENSORS_ABITUGURU3=m +CONFIG_SENSORS_ACBEL_FSG032=m +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADP1050=m +# CONFIG_SENSORS_ADP1050_REGULATOR is not set +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ADT7X10=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +CONFIG_SENSORS_APPLESMC=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASB100=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ASUS_EC=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set +CONFIG_SENSORS_ASUS_WMI=m +CONFIG_SENSORS_ATK0110=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_CGBC=m +# CONFIG_SENSORS_CHIPCAP2 is not set +CONFIG_SENSORS_CORETEMP=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m +CONFIG_SENSORS_CRPS=m +CONFIG_SENSORS_DA9052_ADC=m +CONFIG_SENSORS_DA9055=m +CONFIG_SENSORS_DELL_SMM=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_DRIVETEMP=y +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FAM15H_POWER=m +CONFIG_SENSORS_FSCHMD=m +CONFIG_SENSORS_FSP_3Y=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GIGABYTE_WATERFORCE=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPD is not set +CONFIG_SENSORS_HDAPS=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_HMC5843=m +CONFIG_SENSORS_HMC5843_I2C=m +CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_SENSORS_HP_WMI=m +CONFIG_SENSORS_HS3001=m +CONFIG_SENSORS_HTU31=m +CONFIG_SENSORS_I5500=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IBM_CFFPS=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA233=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +CONFIG_SENSORS_IR38064_REGULATOR=y +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL28022=m CONFIG_SENSORS_ISL29018=m CONFIG_SENSORS_ISL29028=m -CONFIG_ISL29125=m -CONFIG_ISL76682=m -CONFIG_HID_SENSOR_ALS=m -CONFIG_HID_SENSOR_PROX=m -CONFIG_JSA1212=m -CONFIG_ROHM_BU27034=m -CONFIG_RPR0521=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_SENSORS_K8TEMP=m +CONFIG_SENSORS_KBATT=m +CONFIG_SENSORS_KFAN=m +CONFIG_SENSORS_LENOVO_EC=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y CONFIG_SENSORS_LM3533=m -CONFIG_LTR390=m -CONFIG_LTR501=m -CONFIG_LTRF216A=m -CONFIG_LV0104CS=m -CONFIG_MAX44000=m -CONFIG_MAX44009=m -CONFIG_NOA1305=m -CONFIG_OPT3001=m -CONFIG_OPT4001=m -CONFIG_OPT4060=m -CONFIG_PA12203001=m -CONFIG_SI1133=m -CONFIG_SI1145=m -CONFIG_STK3310=m -CONFIG_ST_UVIS25=m -CONFIG_TCS3414=m -CONFIG_TCS3472=m -CONFIG_SENSORS_TSL2563=m -CONFIG_TSL2583=m -CONFIG_TSL2591=m -CONFIG_TSL2772=m -CONFIG_TSL4531=m -CONFIG_US5182D=m -CONFIG_VCNL4000=m -CONFIG_VCNL4035=m -CONFIG_VEML3235=m -CONFIG_VEML6030=m -CONFIG_VEML6040=m -CONFIG_VEML6070=m -CONFIG_VEML6075=m -CONFIG_VL6180=m -CONFIG_ZOPT2201=m -CONFIG_AK8974=m -CONFIG_AK09911=m -CONFIG_ALS31300=m -CONFIG_BMC150_MAGN_I2C=m -CONFIG_BMC150_MAGN_SPI=m -CONFIG_MAG3110=m -CONFIG_HID_SENSOR_MAGNETOMETER_3D=m -CONFIG_MMC35240=m -CONFIG_SENSORS_HMC5843_I2C=m -CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_LT3074=m +CONFIG_SENSORS_LT3074_REGULATOR=m +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC2978_REGULATOR=y +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2991=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +CONFIG_SENSORS_LTC4286=y +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX77705=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MC13783_ADC=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_MENF21BMC_HWMON=m +CONFIG_SENSORS_MP2856=m +# CONFIG_SENSORS_MP2869 is not set +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +# CONFIG_SENSORS_MP29502 is not set +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m +CONFIG_SENSORS_MP5990=m +CONFIG_SENSORS_MP9941=m +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +# CONFIG_SENSORS_MPQ8785 is not set +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT6775_CORE=m +CONFIG_SENSORS_NCT6775_I2C=m +CONFIG_SENSORS_NCT7363=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_OCC=m +CONFIG_SENSORS_OCC_P8_I2C=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_POWERZ=m +CONFIG_SENSORS_POWR1220=m +# CONFIG_SENSORS_PT5161L is not set +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_QNAP_MCU_HWMON=m +CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m CONFIG_SENSORS_RM3100_SPI=m -CONFIG_SI7210=m -CONFIG_YAMAHA_YAS530=m -CONFIG_IIO_MUX=m -CONFIG_HID_SENSOR_INCLINOMETER_3D=m -CONFIG_HID_SENSOR_DEVICE_ROTATION=m -CONFIG_IIO_HRTIMER_TRIGGER=m -CONFIG_IIO_INTERRUPT_TRIGGER=m -CONFIG_IIO_TIGHTLOOP_TRIGGER=m -CONFIG_IIO_SYSFS_TRIGGER=m -CONFIG_IQS624_POS=m -CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m -CONFIG_AD5110=m -CONFIG_AD5272=m -CONFIG_DS1803=m -CONFIG_MAX5432=m -CONFIG_MAX5481=m -CONFIG_MAX5487=m -CONFIG_MCP4018=m -CONFIG_MCP4131=m -CONFIG_MCP4531=m -CONFIG_MCP41010=m -CONFIG_TPL0102=m -CONFIG_X9250=m -CONFIG_LMP91000=m -CONFIG_ABP060MG=m -CONFIG_ROHM_BM1390=m -CONFIG_BMP280=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_DLHL60D=m -CONFIG_DPS310=m -CONFIG_HID_SENSOR_PRESS=m -CONFIG_HP03=m -CONFIG_HSC030PA=m -CONFIG_ICP10100=m -CONFIG_MPL115_I2C=m -CONFIG_MPL115_SPI=m -CONFIG_MPL3115=m -CONFIG_MPRLS0025PA=m -CONFIG_MS5611=m -CONFIG_MS5611_I2C=m -CONFIG_MS5611_SPI=m -CONFIG_MS5637=m -CONFIG_SDP500=m -CONFIG_IIO_ST_PRESS=m -CONFIG_T5403=m -CONFIG_HP206C=m -CONFIG_ZPA2326=m -CONFIG_AS3935=m -CONFIG_CROS_EC_MKBP_PROXIMITY=m -CONFIG_D3323AA=m -CONFIG_HX9023S=m -CONFIG_IRSD200=m -CONFIG_ISL29501=m -CONFIG_LIDAR_LITE_V2=m -CONFIG_MB1232=m -CONFIG_PING=m -CONFIG_RFD77402=m -CONFIG_SRF04=m -CONFIG_SX9310=m -CONFIG_SX9324=m -CONFIG_SX9360=m -CONFIG_SX9500=m -CONFIG_SRF08=m -CONFIG_VCNL3020=m -CONFIG_VL53L0X_I2C=m -CONFIG_AW96103=m -CONFIG_AD2S90=m -CONFIG_AD2S1200=m -CONFIG_AD2S1210=m -CONFIG_IQS620AT_TEMP=m -CONFIG_LTC2983=m -CONFIG_MAXIM_THERMOCOUPLE=m -CONFIG_HID_SENSOR_TEMP=m -CONFIG_MLX90614=m -CONFIG_MLX90632=m -CONFIG_MLX90635=m -CONFIG_TMP006=m -CONFIG_TMP007=m -CONFIG_TMP117=m -CONFIG_TSYS01=m -CONFIG_TSYS02D=m -CONFIG_MAX30208=m -CONFIG_MAX31856=m -CONFIG_MAX31865=m -CONFIG_MCP9600=m -CONFIG_NTB=m -CONFIG_NTB_MSI=y -CONFIG_NTB_AMD=m -CONFIG_NTB_IDT=m -CONFIG_NTB_INTEL=m -CONFIG_NTB_EPF=m -CONFIG_NTB_SWITCHTEC=m -CONFIG_NTB_PINGPONG=m -CONFIG_NTB_TOOL=m -CONFIG_NTB_PERF=m -CONFIG_NTB_MSI_TEST=m -CONFIG_NTB_TRANSPORT=m -CONFIG_PWM=y -CONFIG_PWM_CLK=m -CONFIG_PWM_CRC=y -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_DWC=m -CONFIG_PWM_GPIO=m -CONFIG_PWM_IQS620A=m -CONFIG_PWM_LP3943=m -CONFIG_PWM_LPSS_PCI=m -CONFIG_PWM_LPSS_PLATFORM=m -CONFIG_PWM_PCA9685=m -CONFIG_PWM_TWL=m -CONFIG_PWM_TWL_LED=m -CONFIG_IPACK_BUS=m -CONFIG_BOARD_TPCI200=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SMPRO=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SPD5118=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_STTS751=m +# CONFIG_SENSORS_SURFACE_FAN is not set +CONFIG_SENSORS_SURFACE_TEMP=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_TPS23861=m +CONFIG_SENSORS_TPS25990=m +CONFIG_SENSORS_TPS25990_REGULATOR=y +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_TSL2563=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VIA_CPUTEMP=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_WM831X=m +CONFIG_SENSORS_WM8350=m +CONFIG_SENSORS_XDP710=m +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_XGENE=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_CS=m +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=m +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_LPSS=m +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_MEN_MCB=m +CONFIG_SERIAL_8250_MID=m +CONFIG_SERIAL_8250_NI=m +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PCI1XXXX=m +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_ALTERA_JTAGUART=m +CONFIG_SERIAL_ALTERA_UART=m +CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 +CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_FSL_LINFLEXUART=m +CONFIG_SERIAL_FSL_LPUART=m CONFIG_SERIAL_IPOCTAL=m -CONFIG_RESET_SIMPLE=y -CONFIG_RESET_TI_SYSCON=m -CONFIG_RESET_TI_TPS380X=m -CONFIG_USB_LGM_PHY=m -CONFIG_PHY_CAN_TRANSCEIVER=m -CONFIG_BCM_KONA_USB2_PHY=m -CONFIG_PHY_PXA_28NM_HSIC=m -CONFIG_PHY_PXA_28NM_USB2=m -CONFIG_PHY_CPCAP_USB=m -CONFIG_PHY_QCOM_USB_HS=m -CONFIG_PHY_QCOM_USB_HSIC=m -CONFIG_PHY_SAMSUNG_USB2=m -CONFIG_PHY_TUSB1210=m -CONFIG_PHY_INTEL_LGM_EMMC=m -CONFIG_INTEL_RAPL=m -CONFIG_INTEL_RAPL_TPMI=m -CONFIG_MCB=m -CONFIG_MCB_PCI=m -CONFIG_MCB_LPC=m -CONFIG_DWC_PCIE_PMU=m -CONFIG_CXL_PMU=m -CONFIG_USB4=m -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_BINDERFS=y -CONFIG_BLK_DEV_PMEM=m -CONFIG_DEV_DAX=m -CONFIG_NVMEM_RAVE_SP_EEPROM=m -CONFIG_NVMEM_RMEM=m -CONFIG_NVMEM_SPMI_SDAM=m -CONFIG_STM=m -CONFIG_STM_PROTO_BASIC=m -CONFIG_STM_PROTO_SYS_T=m -CONFIG_STM_DUMMY=m -CONFIG_STM_SOURCE_CONSOLE=m -CONFIG_STM_SOURCE_HEARTBEAT=m -CONFIG_STM_SOURCE_FTRACE=m -CONFIG_INTEL_TH=m -CONFIG_INTEL_TH_PCI=m -CONFIG_INTEL_TH_ACPI=m -CONFIG_INTEL_TH_GTH=m -CONFIG_INTEL_TH_STH=m -CONFIG_INTEL_TH_MSU=m -CONFIG_INTEL_TH_PTI=m -CONFIG_FPGA=m -CONFIG_ALTERA_PR_IP_CORE=m -CONFIG_FPGA_MGR_ALTERA_PS_SPI=m -CONFIG_FPGA_MGR_ALTERA_CVP=m -CONFIG_FPGA_MGR_XILINX_SELECTMAP=m -CONFIG_FPGA_MGR_XILINX_SPI=m -CONFIG_FPGA_MGR_MACHXO2_SPI=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_XILINX_PR_DECOUPLER=m -CONFIG_FPGA_DFL=m -CONFIG_FPGA_DFL_FME=m -CONFIG_FPGA_DFL_FME_MGR=m -CONFIG_FPGA_DFL_FME_BRIDGE=m -CONFIG_FPGA_DFL_FME_REGION=m -CONFIG_FPGA_DFL_AFU=m -CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m -CONFIG_FPGA_DFL_PCI=m -CONFIG_FPGA_M10_BMC_SEC_UPDATE=m -CONFIG_FPGA_MGR_MICROCHIP_SPI=m -CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m -CONFIG_TEE=m -CONFIG_MUX_ADG792A=m -CONFIG_MUX_ADGS1408=m -CONFIG_MUX_GPIO=m +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_LANTIQ=m +CONFIG_SERIAL_MAX3100=m +CONFIG_SERIAL_MAX310X=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MEN_Z135=m +CONFIG_SERIAL_MULTI_INSTANTIATE=m +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=m +CONFIG_SERIAL_SC16IS7XX_SPI=m +CONFIG_SERIAL_SCCNXP=y +CONFIG_SERIAL_SCCNXP_CONSOLE=y +# CONFIG_SERIAL_SPRD is not set +CONFIG_SERIAL_UARTLITE=m +CONFIG_SERIAL_UARTLITE_NR_UARTS=1 +CONFIG_SERIO=y +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_ARC_PS2=m +CONFIG_SERIO_CT82C710=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_SERIO_I8042=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_PS2MULT=m +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=m +CONFIG_SFC=m +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_MTD=y +CONFIG_SFC_SIENA=m +CONFIG_SFC_SIENA_MCDI_LOGGING=y +CONFIG_SFC_SIENA_MCDI_MON=y +CONFIG_SFC_SIENA_MTD=y +CONFIG_SFC_SIENA_SRIOV=y +CONFIG_SFC_SRIOV=y +CONFIG_SFP=m +CONFIG_SF_PDMA=m +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SGI_PARTITION=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SI1133=m +CONFIG_SI1145=m +CONFIG_SI7005=m +CONFIG_SI7020=m +CONFIG_SI7210=m +CONFIG_SIEMENS_SIMATIC_IPC=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT_APOLLOLAKE=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT_ELKHARTLAKE=m +CONFIG_SIEMENS_SIMATIC_IPC_BATT_F7188X=m +CONFIG_SIEMENS_SIMATIC_IPC_WDT=m +CONFIG_SIGNALFD=y +CONFIG_SIGNATURE=y +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set +CONFIG_SILICOM_PLATFORM=m +# CONFIG_SIOX is not set +CONFIG_SIS190=m +CONFIG_SIS900=m +CONFIG_SKB_EXTENSIONS=y +CONFIG_SKFP=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_OBJ_EXT=y +CONFIG_SLHC=y +CONFIG_SLICOSS=m # CONFIG_SLIMBUS is not set -CONFIG_COUNTER=m -CONFIG_INTEL_QEP=m -CONFIG_INTERRUPT_CNT=m -CONFIG_MOST=m -CONFIG_MOST_USB_HDM=m -CONFIG_MOST_CDEV=m -CONFIG_MOST_SND=m -CONFIG_HTE=y -CONFIG_VALIDATE_FS_PARSER=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -CONFIG_JFS_STATISTICS=y -CONFIG_XFS_FS=y -CONFIG_XFS_SUPPORT_V4=y -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -# CONFIG_XFS_ONLINE_SCRUB is not set -CONFIG_GFS2_FS=m -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_OCFS2_FS=m -CONFIG_BTRFS_FS=y -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=m -CONFIG_F2FS_FS=m -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_FS_COMPRESSION=y -# CONFIG_F2FS_IOSTAT is not set -CONFIG_F2FS_UNFAIR_RWSEM=y -CONFIG_ZONEFS_FS=m -CONFIG_FS_DAX=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_VERITY=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m -CONFIG_AUTOFS_FS=m -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_VIRTIO_FS=m -CONFIG_OVERLAY_FS=m -# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set -CONFIG_NETFS_DEBUG=y -CONFIG_FSCACHE_STATS=y -CONFIG_CACHEFILES=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=y -CONFIG_EXFAT_FS=m -CONFIG_NTFS3_LZX_XPRESS=y -CONFIG_NTFS_FS=m -CONFIG_PROC_KCORE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HUGETLBFS=y -CONFIG_EFIVAR_FS=y -CONFIG_ORANGEFS_FS=m -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=m -CONFIG_UBIFS_ATIME_SUPPORT=y -CONFIG_UBIFS_FS_AUTHENTICATION=y -CONFIG_CRAMFS=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_SLIP_SMART=y +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_SMBFS=m +# CONFIG_SMB_SERVER is not set +CONFIG_SMI240=m +CONFIG_SMP=y +CONFIG_SMPRO_ERRMON=m +CONFIG_SMPRO_MISC=m +CONFIG_SMSC37B787_WDT=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +CONFIG_SMSC_SCH311X_WDT=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_SMS_SIANO_DEBUGFS=y +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +CONFIG_SMS_USB_DRV=m +CONFIG_SM_FTL=m +CONFIG_SND=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_AD1889=m +CONFIG_SND_ALI5451=m +CONFIG_SND_ALOOP=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +CONFIG_SND_AMD_ACP_CONFIG=m +CONFIG_SND_AMD_ASOC_ACP63=m +CONFIG_SND_AMD_ASOC_ACP70=m +CONFIG_SND_AMD_ASOC_REMBRANDT=m +CONFIG_SND_AMD_ASOC_RENOIR=m +CONFIG_SND_AMD_SOUNDWIRE_ACPI=m +CONFIG_SND_ASIHPI=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_AZT3328=m +CONFIG_SND_BCD2000=m +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_BEBOB=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_COMPRESS_ACCEL=y +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_CTL_INPUT_VALIDATION=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_DARLA24=m +# CONFIG_SND_DEBUG is not set +CONFIG_SND_DESIGNWARE_I2S=m +# CONFIG_SND_DESIGNWARE_PCM is not set +CONFIG_SND_DICE=m +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DMA_SGBUF=y +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_ECHO3G=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_EMU10K1_SEQ=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FIREFACE=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_GINA20=m +CONFIG_SND_GINA24=m +CONFIG_SND_HDA=m +CONFIG_SND_HDA_ACPI=m +CONFIG_SND_HDA_CIRRUS_SCODEC=m +CONFIG_SND_HDA_CODEC_ALC260=m +CONFIG_SND_HDA_CODEC_ALC262=m +CONFIG_SND_HDA_CODEC_ALC268=m +CONFIG_SND_HDA_CODEC_ALC269=m +CONFIG_SND_HDA_CODEC_ALC662=m +CONFIG_SND_HDA_CODEC_ALC680=m +CONFIG_SND_HDA_CODEC_ALC861=m +CONFIG_SND_HDA_CODEC_ALC861VD=m +CONFIG_SND_HDA_CODEC_ALC880=m +CONFIG_SND_HDA_CODEC_ALC882=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CM9825=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CS420X=m +CONFIG_SND_HDA_CODEC_CS421X=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_HDMI_ATI=m +CONFIG_SND_HDA_CODEC_HDMI_GENERIC=m +CONFIG_SND_HDA_CODEC_HDMI_INTEL=m +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m +CONFIG_SND_HDA_CODEC_HDMI_SIMPLE=m +CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_REALTEK_LIB=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_CORE=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_I915=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +CONFIG_SND_HDA_PREALLOC_SIZE=0 +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_SCODEC_COMPONENT=m +CONFIG_SND_HDA_SCODEC_CS35L41=m +CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m +CONFIG_SND_HDA_SCODEC_CS35L56=m +CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m +CONFIG_SND_HDA_SCODEC_TAS2781=m +CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m +CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_HWDEP=m +CONFIG_SND_I2S_HI6210_I2S=m +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_INTEL_BYT_PREFER_SOF=y +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_KORG1212=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_MIA=m +CONFIG_SND_MIXART=m +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_MONA=m +CONFIG_SND_MPU401=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_NM256=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_OXFW=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_PCI=y +CONFIG_SND_PCM=m +CONFIG_SND_PCMCIA=y +# CONFIG_SND_PCMTEST is not set +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCSP is not set +CONFIG_SND_PCXHR=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_PROC_FS=y +CONFIG_SND_RAWMIDI=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_SB_COMMON=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQUENCER_OSS is not set +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_UMP=y +CONFIG_SND_SEQ_UMP_CLIENT=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ACPI=m +CONFIG_SND_SOC_ACPI_AMD_MATCH=m +CONFIG_SND_SOC_ACPI_INTEL_MATCH=m +CONFIG_SND_SOC_ACPI_INTEL_SDCA_QUIRKS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1373=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4619=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_ACP3x=m +CONFIG_SND_SOC_AMD_ACP5x=m +CONFIG_SND_SOC_AMD_ACP63_TOPLEVEL=m +CONFIG_SND_SOC_AMD_ACP6x=m +CONFIG_SND_SOC_AMD_ACPI_MACH=m +CONFIG_SND_SOC_AMD_ACP_COMMON=m +CONFIG_SND_SOC_AMD_ACP_I2S=m +CONFIG_SND_SOC_AMD_ACP_LEGACY_COMMON=m +CONFIG_SND_SOC_AMD_ACP_PCI=m +CONFIG_SND_SOC_AMD_ACP_PCM=m +CONFIG_SND_SOC_AMD_ACP_PDM=m +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_SOC_AMD_LEGACY_MACH=m +CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH=m +CONFIG_SND_SOC_AMD_MACH_COMMON=m +CONFIG_SND_SOC_AMD_PS=m +CONFIG_SND_SOC_AMD_PS_MACH=m +CONFIG_SND_SOC_AMD_RENOIR=m +CONFIG_SND_SOC_AMD_RENOIR_MACH=m +CONFIG_SND_SOC_AMD_RPL_ACP6x=m +CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m +CONFIG_SND_SOC_AMD_SDW_MACH_COMMON=m +CONFIG_SND_SOC_AMD_SOF_MACH=m +CONFIG_SND_SOC_AMD_SOF_SDW_MACH=m +CONFIG_SND_SOC_AMD_SOUNDWIRE=m +CONFIG_SND_SOC_AMD_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m +CONFIG_SND_SOC_AMD_VANGOGH_MACH=m +CONFIG_SND_SOC_AMD_YC_MACH=m +CONFIG_SND_SOC_ARIZONA=m +CONFIG_SND_SOC_AUDIO_IIO_AUX=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_AW87390=m +CONFIG_SND_SOC_AW88081=m +CONFIG_SND_SOC_AW88166=m +CONFIG_SND_SOC_AW88261=m +CONFIG_SND_SOC_AW88395=m +CONFIG_SND_SOC_AW88395_LIB=m +CONFIG_SND_SOC_AW88399=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CHV3_CODEC=m +CONFIG_SND_SOC_CHV3_I2S=m +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_CROS_EC_CODEC=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L41_LIB=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L56=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SDW=m +CONFIG_SND_SOC_CS35L56_SHARED=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_CORE=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L43=m +CONFIG_SND_SOC_CS42L43_SDW=m +CONFIG_SND_SOC_CS42L51=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS42L84=m +CONFIG_SND_SOC_CS42XX8=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS48L32=m +CONFIG_SND_SOC_CS530X=m +CONFIG_SND_SOC_CS530X_I2C=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CS_AMP_LIB=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DA7219=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8311=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8323=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_ES8375=m +CONFIG_SND_SOC_ES8389=m +CONFIG_SND_SOC_ES83XX_DSM_COMMON=m +# CONFIG_SND_SOC_FS210X is not set +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_UTILS=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_I2C_AND_SPI=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_IDT821034=m +CONFIG_SND_SOC_IMX_AUDMUX=m +CONFIG_SND_SOC_INTEL_AVS=m +# CONFIG_SND_SOC_INTEL_AVS_CARDNAME_OBSOLETE is not set +CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m +CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m +CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336=m +CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m +CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=m +CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m +CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A=m +CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663=m +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m +CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m +CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m +CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m +CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m +CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m +CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m +CONFIG_SND_SOC_INTEL_CATPT=m +CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m +CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m +CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m +CONFIG_SND_SOC_INTEL_HASWELL_MACH=m +CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m +CONFIG_SND_SOC_INTEL_MACH=y +CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m +CONFIG_SND_SOC_INTEL_SOF_BOARD_HELPERS=m +CONFIG_SND_SOC_INTEL_SOF_CIRRUS_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m +CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m +CONFIG_SND_SOC_INTEL_SOF_DA7219_MACH=m +CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m +CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m +CONFIG_SND_SOC_INTEL_SOF_NUVOTON_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m +CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=m +CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m +CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m +CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m +CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=m +CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y +CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98090=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98388=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX9860=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6357=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_MTK_BTCVSD=m +CONFIG_SND_SOC_NAU8315=m +# CONFIG_SND_SOC_NAU8325 is not set +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_NAU8825=m +CONFIG_SND_SOC_NTP8835=m +CONFIG_SND_SOC_NTP8918=m +CONFIG_SND_SOC_NTPFW=m +CONFIG_SND_SOC_PCM1681=m +# CONFIG_SND_SOC_PCM1754 is not set +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +CONFIG_SND_SOC_PCM3168A=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_PCM3168A_SPI=m +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_PCM6240=m +CONFIG_SND_SOC_PEB2466=m +# CONFIG_SND_SOC_PM4125_SDW is not set +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RL6347A=m +CONFIG_SND_SOC_RT1011=m +CONFIG_SND_SOC_RT1015=m +CONFIG_SND_SOC_RT1015P=m +CONFIG_SND_SOC_RT1017_SDCA_SDW=m +CONFIG_SND_SOC_RT1019=m +CONFIG_SND_SOC_RT1308=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m +CONFIG_SND_SOC_RT274=m +CONFIG_SND_SOC_RT286=m +CONFIG_SND_SOC_RT298=m +CONFIG_SND_SOC_RT5514=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5651=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5660=m +CONFIG_SND_SOC_RT5663=m +CONFIG_SND_SOC_RT5670=m +CONFIG_SND_SOC_RT5677=m +CONFIG_SND_SOC_RT5677_SPI=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682S=m +CONFIG_SND_SOC_RT5682_I2C=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +CONFIG_SND_SOC_RT712_SDCA_SDW=m +CONFIG_SND_SOC_RT715=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT721_SDCA_SDW=m +CONFIG_SND_SOC_RT722_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_RT9123=m +CONFIG_SND_SOC_RT9123P=m +CONFIG_SND_SOC_RTQ9124=m +CONFIG_SND_SOC_RTQ9128=m +CONFIG_SND_SOC_RT_SDW_COMMON=m +CONFIG_SND_SOC_SDCA=m +CONFIG_SND_SOC_SDCA_HID=y +CONFIG_SND_SOC_SDCA_IRQ=y +CONFIG_SND_SOC_SDCA_OPTIONAL=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SDW_UTILS=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SI476X=m +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SMA1303=m +CONFIG_SND_SOC_SMA1307=m +CONFIG_SND_SOC_SOF=m +CONFIG_SND_SOC_SOF_ACPI=m +CONFIG_SND_SOC_SOF_ACPI_DEV=m +CONFIG_SND_SOC_SOF_ACP_PROBES=m +CONFIG_SND_SOC_SOF_ALDERLAKE=m +CONFIG_SND_SOC_SOF_AMD_ACP63=m +CONFIG_SND_SOC_SOF_AMD_ACP70=m +CONFIG_SND_SOC_SOF_AMD_COMMON=m +CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m +CONFIG_SND_SOC_SOF_AMD_RENOIR=m +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE=m +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m +CONFIG_SND_SOC_SOF_AMD_VANGOGH=m +CONFIG_SND_SOC_SOF_APOLLOLAKE=m +CONFIG_SND_SOC_SOF_BAYTRAIL=m +CONFIG_SND_SOC_SOF_BROADWELL=m +CONFIG_SND_SOC_SOF_CANNONLAKE=m +CONFIG_SND_SOC_SOF_CLIENT=m +CONFIG_SND_SOC_SOF_COFFEELAKE=m +CONFIG_SND_SOC_SOF_COMETLAKE=m +CONFIG_SND_SOC_SOF_DEBUG_PROBES=m +# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set +CONFIG_SND_SOC_SOF_ELKHARTLAKE=m +CONFIG_SND_SOC_SOF_GEMINILAKE=m +CONFIG_SND_SOC_SOF_HDA=m +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y +CONFIG_SND_SOC_SOF_HDA_COMMON=m +CONFIG_SND_SOC_SOF_HDA_GENERIC=m +CONFIG_SND_SOC_SOF_HDA_LINK=y +CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_HDA_MLINK=m +CONFIG_SND_SOC_SOF_HDA_PROBES=m +CONFIG_SND_SOC_SOF_ICELAKE=m +CONFIG_SND_SOC_SOF_INTEL_APL=m +CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m +CONFIG_SND_SOC_SOF_INTEL_CNL=m +CONFIG_SND_SOC_SOF_INTEL_COMMON=m +CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m +CONFIG_SND_SOC_SOF_INTEL_ICL=m +CONFIG_SND_SOC_SOF_INTEL_LNL=m +CONFIG_SND_SOC_SOF_INTEL_MTL=m +CONFIG_SND_SOC_SOF_INTEL_PTL=m +CONFIG_SND_SOC_SOF_INTEL_SKL=m +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m +CONFIG_SND_SOC_SOF_INTEL_TGL=m +CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IPC3=y +CONFIG_SND_SOC_SOF_IPC4=y +CONFIG_SND_SOC_SOF_JASPERLAKE=m +CONFIG_SND_SOC_SOF_KABYLAKE=m +CONFIG_SND_SOC_SOF_LUNARLAKE=m +CONFIG_SND_SOC_SOF_MERRIFIELD=m +CONFIG_SND_SOC_SOF_METEORLAKE=m +CONFIG_SND_SOC_SOF_PANTHERLAKE=m +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_PCI_DEV=m +CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y +CONFIG_SND_SOC_SOF_SKYLAKE=m +CONFIG_SND_SOC_SOF_TIGERLAKE=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_XTENSA=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS2781_COMLIB=m +CONFIG_SND_SOC_TAS2781_COMLIB_I2C=m +CONFIG_SND_SOC_TAS2781_FMWLIB=m +CONFIG_SND_SOC_TAS2781_I2C=m +# CONFIG_SND_SOC_TAS2783_SDW is not set +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TLV320AIC23=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TOPOLOGY=y +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_UDA1342=m +CONFIG_SND_SOC_USB=m +CONFIG_SND_SOC_WCD937X=m +CONFIG_SND_SOC_WCD937X_SDW=m +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +# CONFIG_SND_SOC_WCD939X_SDW is not set +CONFIG_SND_SOC_WCD_CLASSH=m +CONFIG_SND_SOC_WCD_COMMON=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WM5102=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8961=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WM8998=m +CONFIG_SND_SOC_WM_ADSP=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_WSA884X=m +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +CONFIG_SND_SOC_XILINX_I2S=m +# CONFIG_SND_SOC_XILINX_SPDIF is not set +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOF_SOF_HDA_SDW_BPT=m +CONFIG_SND_SONICVIBES=m +CONFIG_SND_SPI=y +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_SYNTH_EMUX=m +CONFIG_SND_TIMER=m +CONFIG_SND_TRIDENT=m +CONFIG_SND_UMP=m +CONFIG_SND_UMP_LEGACY_RAWMIDI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_USB_AUDIO_QMI=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_US122L=m +# CONFIG_SND_USB_US144MKII is not set +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_UTIMER=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_VIRTIO=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VMASTER=y +CONFIG_SND_VX222=m +CONFIG_SND_VXPOCKET=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_X86=y +CONFIG_SND_XEN_FRONTEND=m +CONFIG_SND_YMFPCI=m +CONFIG_SNET_VDPA=m +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOC_TI=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONYPI_COMPAT=y +CONFIG_SONY_FF=y +CONFIG_SONY_LAPTOP=m +CONFIG_SOUND=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_AMD=m +CONFIG_SOUNDWIRE_CADENCE=m +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m +CONFIG_SOUNDWIRE_INTEL=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SP5100_TCO=m +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP_PREINIT=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPEAKUP=m +# CONFIG_SPEAKUP_SYNTH_ACNTSA is not set +# CONFIG_SPEAKUP_SYNTH_APOLLO is not set +# CONFIG_SPEAKUP_SYNTH_AUDPTR is not set +# CONFIG_SPEAKUP_SYNTH_BNS is not set +# CONFIG_SPEAKUP_SYNTH_DECEXT is not set +# CONFIG_SPEAKUP_SYNTH_DECTLK is not set +# CONFIG_SPEAKUP_SYNTH_DUMMY is not set +# CONFIG_SPEAKUP_SYNTH_LTLK is not set +CONFIG_SPEAKUP_SYNTH_SOFT=m +# CONFIG_SPEAKUP_SYNTH_SPKOUT is not set +# CONFIG_SPEAKUP_SYNTH_TXPRT is not set +CONFIG_SPI=y +CONFIG_SPI_ALTERA=m +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +CONFIG_SPI_AMD=m +CONFIG_SPI_AX88796C=m +CONFIG_SPI_AX88796C_COMPRESSION=y +CONFIG_SPI_AXI_SPI_ENGINE=m +CONFIG_SPI_BITBANG=m +CONFIG_SPI_BUTTERFLY=m +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CH341=m +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DLN2=m +# CONFIG_SPI_DW_DMA is not set +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_GPIO=m +# CONFIG_SPI_INTEL_PCI is not set +# CONFIG_SPI_INTEL_PLATFORM is not set +CONFIG_SPI_KSPI2=m +CONFIG_SPI_LANTIQ_SSC=m +CONFIG_SPI_LJCA=m +CONFIG_SPI_LM70_LLP=m +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_MUX=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_OFFLOAD=y +CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m +CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m +CONFIG_SPI_PCI1XXXX=m +CONFIG_SPI_PXA2XX=m +CONFIG_SPI_PXA2XX_PCI=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SIFIVE=m +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_TLE62X0=m +# CONFIG_SPI_VIRTIO is not set +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SPMI=m +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_FILE_DIRECT=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE is not set CONFIG_SQUASHFS_COMP_CACHE_FULL=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XATTR=y CONFIG_SQUASHFS_XZ=y -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_QNX6FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_PSTORE_RAM=m -CONFIG_UFS_FS=m -CONFIG_EROFS_FS=m -# CONFIG_EROFS_FS_ZIP is not set -CONFIG_VBOXSF_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V2=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=m -CONFIG_NFS_SWAP=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_NFS_V4_1_MIGRATION=y -CONFIG_NFS_FSCACHE=y -# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set -# CONFIG_NFS_V4_2_READ_PLUS is not set -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_V4_SECURITY_LABEL=y -# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set -CONFIG_NFS_LOCALIO=y -CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y -CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_ZSTD is not set +CONFIG_SRAM=y +CONFIG_SRF04=m +CONFIG_SRF08=m +CONFIG_SSB=m +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SPROM=y +CONFIG_SSFDC=m +CONFIG_SSIF_IPMI_BMC=m +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +CONFIG_STACKTRACE_BUILD_ID=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_STACK_TRACER=y +CONFIG_STACK_VALIDATION=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_STANDALONE is not set +# CONFIG_STATIC_CALL_SELFTEST is not set +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +CONFIG_STEAM_FF=y +CONFIG_STK3310=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +CONFIG_STM=m +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_PCI is not set +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STM_DUMMY=m +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +CONFIG_STM_SOURCE_CONSOLE=m +CONFIG_STM_SOURCE_FTRACE=m +CONFIG_STM_SOURCE_HEARTBEAT=m +CONFIG_STP=m +CONFIG_STREAM_PARSER=y +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +# CONFIG_STRICT_SIGALTSTACK_SIZE is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_SUNDANCE is not set +CONFIG_SUNGEM=m +CONFIG_SUNGEM_PHY=m +CONFIG_SUNRPC=m +CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_SUNRPC_DEBUG=y -CONFIG_CEPH_FS=m -CONFIG_CEPH_FSCACHE=y -CONFIG_CEPH_FS_POSIX_ACL=y -CONFIG_CEPH_FS_SECURITY_LABEL=y -CONFIG_CIFS=m -# CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_CIFS_SWN_UPCALL=y -CONFIG_CIFS_FSCACHE=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_AFS_FSCACHE=y -CONFIG_9P_FS=m -CONFIG_9P_FSCACHE=y -CONFIG_9P_FS_POSIX_ACL=y -CONFIG_9P_FS_SECURITY=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_DLM=m -CONFIG_KEYS_REQUEST_CACHE=y -CONFIG_PERSISTENT_KEYRINGS=y +# CONFIG_SUNRPC_DEBUG_TRACE is not set +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_SWAP=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_SUN_PARTITION=y +CONFIG_SURFACE3_WMI=m +CONFIG_SURFACE_3_POWER_OPREGION=m +CONFIG_SURFACE_ACPI_NOTIFY=m +CONFIG_SURFACE_AGGREGATOR=m +CONFIG_SURFACE_AGGREGATOR_BUS=y +# CONFIG_SURFACE_AGGREGATOR_CDEV is not set +# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set +CONFIG_SURFACE_AGGREGATOR_HUB=m +CONFIG_SURFACE_AGGREGATOR_REGISTRY=m +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m +CONFIG_SURFACE_DTX=m +CONFIG_SURFACE_GPE=m +CONFIG_SURFACE_HID=m +CONFIG_SURFACE_HID_CORE=m +CONFIG_SURFACE_HOTPLUG=m +CONFIG_SURFACE_KBD=m +CONFIG_SURFACE_PLATFORMS=y +CONFIG_SURFACE_PLATFORM_PROFILE=m +CONFIG_SURFACE_PRO3_BUTTON=m +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SVC_I3C_MASTER=m +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SWIOTLB_XEN=y +CONFIG_SWPHY=y +# CONFIG_SW_SYNC is not set +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SXGBE_ETH=m +CONFIG_SX_COMMON=m +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYN_COOKIES=y +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_SYSFS=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSTEM76_ACPI=m +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +CONFIG_SYSV68_PARTITION=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYS_HYPERVISOR=y +CONFIG_T5403=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TAHVO_USB=m +CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y +CONFIG_TAP=m +CONFIG_TARGET_CORE=m +CONFIG_TASKSTATS=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +CONFIG_TCG_INFINEON=m +CONFIG_TCG_NSC=m +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_ATMEL=m +# CONFIG_TCG_TIS_I2C_CR50 is not set +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI=m +# CONFIG_TCG_TIS_SPI_CR50 is not set +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TPM2_HMAC=y +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_XEN=m +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_TCM_USER2=m +CONFIG_TCP_AO=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +CONFIG_TCP_SIGPOOL=y +CONFIG_TCS3414=m +CONFIG_TCS3472=m +CONFIG_TDX_GUEST_DRIVER=m +CONFIG_TEE=m +CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m +CONFIG_TELCLOCK=m +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_BPF=m +# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set +# CONFIG_TEST_DHRY is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +CONFIG_TEST_FIRMWARE=m +# CONFIG_TEST_FPU is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_IDA=m +# CONFIG_TEST_KALLSYMS is not set +# CONFIG_TEST_KEXEC_HANDOVER is not set +# CONFIG_TEST_KMOD is not set +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_LKM=m +# CONFIG_TEST_LOCKUP is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_MULDIV64 is not set +CONFIG_TEST_OBJAGG=m +CONFIG_TEST_OBJPOOL=m +CONFIG_TEST_PARMAN=m +CONFIG_TEST_POWER=m +# CONFIG_TEST_REF_TRACKER is not set +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_STATIC_KEYS=m +# CONFIG_TEST_SYSCTL is not set +CONFIG_TEST_UDELAY=m +CONFIG_TEST_UUID=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_XARRAY=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_TEXTSEARCH_KMP=m +CONFIG_THERMAL=y +# CONFIG_THERMAL_CORE_TESTING is not set +CONFIG_THERMAL_DEBUGFS=y +# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_NETLINK=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THINKPAD_ACPI=m +CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y +# CONFIG_THINKPAD_ACPI_DEBUG is not set +CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y +CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y +# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set +CONFIG_THINKPAD_ACPI_VIDEO=y +CONFIG_THINKPAD_LMI=m +CONFIG_THP_SWAP=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TICK_ONESHOT=y +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIMERFD=y +# CONFIG_TIMERLAT_TRACER is not set +CONFIG_TIME_NS=y +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_SHARP_MEMORY=m +CONFIG_TIPC=m +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TI_ADC081C=m +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC108S102=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC128S052=m +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS1100=m +CONFIG_TI_ADS1119=m +CONFIG_TI_ADS124S08=m +# CONFIG_TI_ADS1298 is not set +CONFIG_TI_ADS131E08=m +CONFIG_TI_ADS7138=m +CONFIG_TI_ADS7924=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +CONFIG_TI_ADS8688=m +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +CONFIG_TI_FPC202=m +CONFIG_TI_LMP92064=m +CONFIG_TI_TLC4541=m +# CONFIG_TI_TMAG5273 is not set +CONFIG_TI_TSC2046=m +CONFIG_TLAN=m +CONFIG_TLS=m +# CONFIG_TLS_DEVICE is not set +# CONFIG_TLS_TOE is not set +CONFIG_TMP006=m +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TMPFS=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_XATTR=y +CONFIG_TOOLS_SUPPORT_RELR=y +CONFIG_TOPSTAR_LAPTOP=m +CONFIG_TORTURE_TEST=m +CONFIG_TOSHIBA_BT_RFKILL=m +CONFIG_TOSHIBA_HAPS=m +CONFIG_TOSHIBA_WMI=m +CONFIG_TOUCHSCREEN_88PM860X=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP5=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP_SPI=m +CONFIG_TOUCHSCREEN_DA9034=m +CONFIG_TOUCHSCREEN_DA9052=m +# CONFIG_TOUCHSCREEN_DMI is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +# CONFIG_TOUCHSCREEN_HIMAX_HX852X is not set +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +# CONFIG_TOUCHSCREEN_HYNITRON_CST816X is not set +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_IMAGIS=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_IQS7211=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MC13783=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +CONFIG_TOUCHSCREEN_PCAP=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_SUR40=m +CONFIG_TOUCHSCREEN_SURFACE3_SPI=m +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM831X=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TPL0102=m +CONFIG_TPS6105X=m +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +CONFIG_TPS6594_ESM=y +CONFIG_TPS6594_PFSM=y +CONFIG_TPS68470_PMIC_OPREGION=y +CONFIG_TQMX86_WDT=m +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y +CONFIG_TRACEPOINTS=y +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_GPU_MEM is not set +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_TRUSTED_KEYS=y -CONFIG_KEY_DH_OPERATIONS=y -CONFIG_KEY_NOTIFICATIONS=y -CONFIG_SECURITY_DMESG_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK_XFRM=y -CONFIG_INTEL_TXT=y -CONFIG_LSM_MMAP_MIN_ADDR=0 -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_SELINUX_DEBUG=y -CONFIG_SECURITY_SMACK=y -CONFIG_SECURITY_SMACK_NETFILTER=y -CONFIG_SECURITY_TOMOYO=y -CONFIG_SECURITY_APPARMOR=y -CONFIG_SECURITY_YAMA=y -CONFIG_SECURITY_LANDLOCK=y -CONFIG_INTEGRITY_SIGNATURE=y -CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y -CONFIG_IMA=y -CONFIG_IMA_KEXEC=y -CONFIG_IMA_APPRAISE=y -CONFIG_IMA_DISABLE_HTABLE=y -CONFIG_EVM=y -CONFIG_EVM_EXTRA_SMACK_XATTRS=y -CONFIG_DEFAULT_SECURITY_APPARMOR=y -CONFIG_LSM="yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo" -CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y -CONFIG_ZERO_CALL_USED_REGS=y -CONFIG_FORTIFY_SOURCE=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_CRYPTO_USER=m -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_PCRYPT=m -CONFIG_CRYPTO_ECDSA=m -CONFIG_CRYPTO_ECRDSA=m -CONFIG_CRYPTO_AES_TI=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SM4_GENERIC=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_ADIANTUM=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_HCTR2=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SM3_GENERIC=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_CRC32=m -CONFIG_CRYPTO_842=m -CONFIG_CRYPTO_LZ4=m -CONFIG_CRYPTO_LZ4HC=m -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y -CONFIG_CRYPTO_USER_API_HASH=m -CONFIG_CRYPTO_USER_API_SKCIPHER=m -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_USER_API_AEAD=m -CONFIG_CRYPTO_AES_NI_INTEL=m -CONFIG_CRYPTO_BLOWFISH_X86_64=m -CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m -CONFIG_CRYPTO_CAST5_AVX_X86_64=m -CONFIG_CRYPTO_CAST6_AVX_X86_64=m -CONFIG_CRYPTO_DES3_EDE_X86_64=m -CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m -CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m -CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m -CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m -CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64=m -CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m -CONFIG_CRYPTO_NHPOLY1305_SSE2=m -CONFIG_CRYPTO_NHPOLY1305_AVX2=m -CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m -CONFIG_CRYPTO_SM3_AVX_X86_64=m -CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m -CONFIG_CRYPTO_DEV_PADLOCK=y -CONFIG_CRYPTO_DEV_PADLOCK_AES=m -CONFIG_CRYPTO_DEV_PADLOCK_SHA=m -CONFIG_CRYPTO_DEV_ATMEL_ECC=m -CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m -CONFIG_CRYPTO_DEV_CCP=y -CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m -CONFIG_CRYPTO_DEV_QAT_DH895xCC=m -CONFIG_CRYPTO_DEV_QAT_C3XXX=m -CONFIG_CRYPTO_DEV_QAT_C62X=m -CONFIG_CRYPTO_DEV_QAT_4XXX=m -CONFIG_CRYPTO_DEV_QAT_420XX=m -CONFIG_CRYPTO_DEV_QAT_6XXX=m -CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m -CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m -CONFIG_CRYPTO_DEV_QAT_C62XVF=m -CONFIG_CRYPTO_DEV_IAA_CRYPTO=m -CONFIG_CRYPTO_DEV_CHELSIO=m -CONFIG_CRYPTO_DEV_VIRTIO=m -CONFIG_CRYPTO_DEV_SAFEXCEL=m -CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m -CONFIG_PKCS8_PRIVATE_KEY_PARSER=m -CONFIG_PRIME_NUMBERS=m -CONFIG_XZ_DEC_MICROLZMA=y -CONFIG_XZ_DEC_TEST=m -CONFIG_DMA_CMA=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_6x10=y -CONFIG_FONT_TER16x32=y -CONFIG_FONT_6x8=y -CONFIG_PRINTK_TIME=y -CONFIG_STACKTRACE_BUILD_ID=y -CONFIG_BOOT_PRINTK_DELAY=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_DEBUG_INFO_BTF=y -CONFIG_FRAME_WARN=1024 -CONFIG_STACK_VALIDATION=y -CONFIG_KGDB=y -CONFIG_KGDB_LOW_LEVEL_TRAP=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_KEYBOARD=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m -CONFIG_MEM_ALLOC_PROFILING=y -CONFIG_MEM_ALLOC_PROFILING_DEBUG=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=0 -CONFIG_HARDLOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK_BLOCKER is not set -CONFIG_SCHEDSTATS=y -CONFIG_LOCK_TORTURE_TEST=m +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_TSL2583=m +CONFIG_TSL2591=m +CONFIG_TSL2772=m +CONFIG_TSL4531=m +CONFIG_TSM_GUEST=y +CONFIG_TSM_MEASUREMENTS=y +CONFIG_TSM_REPORTS=m +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_TTPCI_EEPROM=m +CONFIG_TTY=y +CONFIG_TTY_PRINTK=y +CONFIG_TTY_PRINTK_LEVEL=6 +CONFIG_TULIP=m +# CONFIG_TULIP_MMIO is not set +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_NAPI is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_TUXEDO_NB04_WMI_AB=m +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_MADC=m +CONFIG_TWL4030_WATCHDOG=m +CONFIG_TWL6030_GPADC=m +CONFIG_TWL6040_CORE=y +CONFIG_TXGBE=m +CONFIG_TXGBEVF=m +CONFIG_TYPEC=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_MT6360=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_INTEL_PMC=m +# CONFIG_TYPEC_MUX_IT5205 is not set +CONFIG_TYPEC_MUX_NB7VPQ904M=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_MUX_PS883X=m +CONFIG_TYPEC_MUX_PTN36502=m +CONFIG_TYPEC_MUX_TUSB1046=m +CONFIG_TYPEC_MUX_WCD939X_USBSS=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_TBT_ALTMODE=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_UCSI=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPHOON=m +CONFIG_UACCE=m +CONFIG_UBIFS_ATIME_SUPPORT=y +CONFIG_UBIFS_FS=m +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_SECURITY=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y +# CONFIG_UBSAN is not set +# CONFIG_UCLAMP_TASK is not set +CONFIG_UCS2_STRING=y +CONFIG_UCSI_ACPI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_UDF_FS=m +# CONFIG_UDMABUF is not set +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UFS_DEBUG is not set +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +CONFIG_UHID=m +CONFIG_UID16=y +CONFIG_UIO=m +CONFIG_UIO_AEC=m +CONFIG_UIO_CIF=m +CONFIG_UIO_DFL=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_MF624=m +CONFIG_UIO_NETX=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_SERCOS3=m +CONFIG_ULI526X=m +CONFIG_ULTRIX_PARTITION=y +CONFIG_UNACCEPTED_MEMORY=y +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNION_FIND=y +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX_DIAG=m +CONFIG_UNWINDER_FRAME_POINTER=y +# CONFIG_UNWINDER_ORC is not set +CONFIG_UNWIND_USER=y +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y +CONFIG_US5182D=m +CONFIG_USB=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +CONFIG_USB4_NET=m +CONFIG_USBIP_CORE=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_VUDC=m +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AMD5536UDC=m +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_ATM=m +CONFIG_USB_AUDIO=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_BDC_UDC=m +CONFIG_USB_BELKIN=y +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_CATC=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_CDNS2_UDC=m +CONFIG_USB_CDNS3=m +# CONFIG_USB_CDNS3_GADGET is not set +# CONFIG_USB_CDNS3_HOST is not set +CONFIG_USB_CDNS3_PCI_WRAP=m +CONFIG_USB_CDNSP_GADGET=y +CONFIG_USB_CDNSP_HOST=y +CONFIG_USB_CDNSP_PCI=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_CHIPIDEA=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_NPCM=m +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_COMMON=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_MIDI2=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +# CONFIG_USB_CONFIGFS_F_TCM is not set +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_CXACRU=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DSBR=m +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_DEBUG is not set +CONFIG_USB_DWC2_HOST=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_HAPS=m +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3_PCI=m +CONFIG_USB_DWC3_ULPI=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_EG20T=m +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC=m +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_F_ACM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_MIDI2=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_TCM=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_GADGET=m +CONFIG_USB_GADGETFS=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GL860=m +CONFIG_USB_GOKU=m +CONFIG_USB_GPIO_VBUS=m +CONFIG_USB_GR_UDC=m +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_HID=m +# CONFIG_USB_G_MULTI is not set +CONFIG_USB_G_NCM=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_HACKRF=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=m +CONFIG_USB_HIDDEV=y +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_HSO=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_IPHETH=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_ISP1301=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_DUAL_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +CONFIG_USB_ISP1760_HCD=y +# CONFIG_USB_ISP1760_HOST_ROLE is not set +CONFIG_USB_ISP1761_UDC=y +CONFIG_USB_KAWETH=m +CONFIG_USB_KBD=m +CONFIG_USB_KC2190=y +CONFIG_USB_KEENE=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LGM_PHY=m +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_LINK_LAYER_TEST=m +CONFIG_USB_LJCA=m +CONFIG_USB_M5602=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_MA901=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_MAX3420_UDC=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_MON=m +CONFIG_USB_MOUSE=m +CONFIG_USB_MR800=m +CONFIG_USB_MSI2500=m +CONFIG_USB_MUSB_DUAL_ROLE=y +# CONFIG_USB_MUSB_GADGET is not set +CONFIG_USB_MUSB_HDRC=m +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_NET2280=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_PCI=y +CONFIG_USB_PCI_AMD=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_PHY=y +CONFIG_USB_PRINTER=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_PXA27X=m +CONFIG_USB_R8A66597=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_RAINSHADOW_CEC=m +CONFIG_USB_RAREMONO=m +CONFIG_USB_RAW_GADGET=m +CONFIG_USB_ROLES_INTEL_XHCI=m +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_USB_S2255=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_SI470X=m +CONFIG_USB_SI4713=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SL811_CS=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STV06XX=m +CONFIG_USB_SUPPORT=y +CONFIG_USB_TEST=m +CONFIG_USB_TMC=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_UAS=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +# CONFIG_USB_USBIO is not set +CONFIG_USB_USBNET=m +CONFIG_USB_USS720=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +CONFIG_USB_XEN_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XHCI_SIDEBAND=y +CONFIG_USB_XUSBATM=m +CONFIG_USB_YUREX=m +CONFIG_USB_ZERO=m +CONFIG_USERFAULTFD=y +CONFIG_USERIO=m +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USER_NS=y +CONFIG_USER_RETURN_NOTIFIER=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_USE_X86_SEG_SUPPORT=y +CONFIG_UTS_NS=y +CONFIG_UVC_COMMON=m +# CONFIG_U_SERIAL_CONSOLE is not set +CONFIG_V4L2_ASYNC=m +CONFIG_V4L2_CCI=m +CONFIG_V4L2_CCI_I2C=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_MEM2MEM_DEV=m +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_VBOXGUEST=m +CONFIG_VBOXSF_FS=m +CONFIG_VCAP=y +CONFIG_VCNL3020=m +CONFIG_VCNL4000=m +CONFIG_VCNL4035=m +CONFIG_VDPA=m +# CONFIG_VDPA_SIM is not set +CONFIG_VDPA_USER=m +CONFIG_VDSO_GETRANDOM=y +CONFIG_VEML3235=m +CONFIG_VEML6030=m +CONFIG_VEML6040=m +# CONFIG_VEML6046X00 is not set +CONFIG_VEML6070=m +CONFIG_VEML6075=m +CONFIG_VETH=m +CONFIG_VF610_ADC=m +CONFIG_VF610_DAC=m +CONFIG_VFAT_FS=y +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +CONFIG_VFIO_GROUP=y +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO_MDEV=m +CONFIG_VFIO_NOIOMMU=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_IGD=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI_VGA=y +CONFIG_VFIO_VIRQFD=y +CONFIG_VGASTATE=m +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VGA_CONSOLE=y +CONFIG_VGA_SWITCHEROO=y +CONFIG_VHOST=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_RING=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST_VDPA=m +CONFIG_VHOST_VSOCK=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_VIA_WDT=m +CONFIG_VIDEO=y +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_ADV7511=m +CONFIG_VIDEO_ADV7511_CEC=y +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_ALVIUM_CSI2=m +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT848=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m +CONFIG_VIDEO_CAFE_CCIC=m +CONFIG_VIDEO_CAMERA_LENS=y +CONFIG_VIDEO_CAMERA_SENSOR=y +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_COBALT=m +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_CX23885=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9719=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_FB_IVTV=m +# CONFIG_VIDEO_FB_IVTV_FORCE_PAT is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC0310 is not set +CONFIG_VIDEO_GC05A2=m +CONFIG_VIDEO_GC08A3=m +CONFIG_VIDEO_GC2145=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GS1662=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_INTEL_IPU6=m +CONFIG_VIDEO_INTEL_IPU7=m +CONFIG_VIDEO_IPU3_CIO2=m +CONFIG_VIDEO_IPU3_IMGU=m +CONFIG_VIDEO_IR_I2C=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_VIDEO_LT6911UXE=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MAX96717=m +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MGB4=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9M114=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_OG01A1B=m +# CONFIG_VIDEO_OG0VE1B is not set +CONFIG_VIDEO_OV01A10=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV02C10=m +CONFIG_VIDEO_OV02E10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +# CONFIG_VIDEO_OV2735 is not set +CONFIG_VIDEO_OV2740=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +# CONFIG_VIDEO_OV6211 is not set +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_OV9734=m +CONFIG_VIDEO_PVRUSB2=m +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_PVRUSB2_DVB=y +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_RP1_CFE=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_SAA6588=m +CONFIG_VIDEO_SAA6752HS=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_SAA7164=m +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TC358746=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_THP7312=m +CONFIG_VIDEO_THS7303=m +CONFIG_VIDEO_THS8200=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +CONFIG_VIDEO_TW9900=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEO_VD55G1=m +CONFIG_VIDEO_VD56G3=m +CONFIG_VIDEO_VIA_CAMERA=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIM2M=m +# CONFIG_VIDEO_VIMC is not set +# CONFIG_VIDEO_VISL is not set +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +# CONFIG_VIDEO_VIVID_OSD is not set +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_ZORAN is not set +CONFIG_VIPERBOARD_ADC=m +CONFIG_VIRTIO=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_DEBUG=y +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VIRTIO_FS=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_IOMMU=m +CONFIG_VIRTIO_MEM=m +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_ADMIN_LEGACY=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_RTC=m +CONFIG_VIRTIO_RTC_CLASS=y +CONFIG_VIRTIO_RTC_PTP=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_VFIO_PCI=m +CONFIG_VIRTIO_VFIO_PCI_ADMIN_LEGACY=y +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_VIRTUALIZATION=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRT_WIFI=m +CONFIG_VIRT_XFER_TO_GUEST_WORK=y +CONFIG_VITESSE_PHY=m +CONFIG_VL53L0X_I2C=m +CONFIG_VL6180=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_PFN=y +CONFIG_VMAP_STACK=y +CONFIG_VMCORE_INFO=y +CONFIG_VMD=m +CONFIG_VME_BUS=y +# CONFIG_VME_FAKE is not set +CONFIG_VME_TSI148=m +CONFIG_VME_USER=m +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_VMWARE_BALLOON=m +CONFIG_VMWARE_PVSCSI=m +CONFIG_VMWARE_VMCI=m +CONFIG_VMWARE_VMCI_VSOCKETS=m +CONFIG_VMXNET3=m +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VORTEX=m +CONFIG_VP_VDPA=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKMON=m +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VXFS_FS=m +CONFIG_VXLAN=m +CONFIG_VZ89X=m +CONFIG_W1=m +CONFIG_W1_CON=y +CONFIG_W1_MASTER_AMD_AXI=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_SGI=m +# CONFIG_W1_MASTER_UART is not set +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +# CONFIG_W1_SLAVE_DS2433_CRC is not set +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W83627HF_WDT=m +CONFIG_W83877F_WDT=m +CONFIG_W83977F_WDT=m +CONFIG_WAFER_WDT=m +CONFIG_WAN=y +CONFIG_WANT_COMPAT_NETLINK_MESSAGES=y +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_WANXL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCH_QUEUE=y +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WDAT_WDT=m +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +CONFIG_WFX=m +CONFIG_WIL6210=m +CONFIG_WIL6210_DEBUGFS=y +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +CONFIG_WILC1000=m +# CONFIG_WILC1000_HW_OOB_INTR is not set +CONFIG_WILC1000_SDIO=m +CONFIG_WILC1000_SPI=m +CONFIG_WILCO_EC=m +# CONFIG_WILCO_EC_DEBUGFS is not set +CONFIG_WILCO_EC_EVENTS=m +CONFIG_WILCO_EC_TELEMETRY=m +CONFIG_WINBOND_840=m +CONFIG_WINMATE_FM07_KEYS=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_HOTKEY=m +CONFIG_WIZNET_BUS_ANY=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_W5100=m +# CONFIG_WIZNET_W5100_SPI is not set +CONFIG_WIZNET_W5300=m +CONFIG_WL1251=m +CONFIG_WL1251_SDIO=m +CONFIG_WL1251_SPI=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_PURELIFI=y +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLCORE=m +CONFIG_WLCORE_SDIO=m +CONFIG_WM831X_BACKUP=m +CONFIG_WM831X_POWER=m +CONFIG_WM831X_WATCHDOG=m +CONFIG_WM8350_POWER=m +CONFIG_WM8350_WATCHDOG=m +CONFIG_WMI_BMOF=m +CONFIG_WPCM450_SOC=m +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_WQ_WATCHDOG is not set +CONFIG_WWAN=y +# CONFIG_WWAN_DEBUGFS is not set +# CONFIG_WWAN_HWSIM is not set CONFIG_WW_MUTEX_SELFTEST=m -CONFIG_RCU_CPU_STALL_TIMEOUT=60 -# CONFIG_RCU_TRACE is not set -CONFIG_FPROBE=y -CONFIG_FUNCTION_PROFILER=y -CONFIG_STACK_TRACER=y -CONFIG_SCHED_TRACER=y -CONFIG_MMIOTRACE=y -CONFIG_FTRACE_SYSCALLS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_SYNTH_EVENTS=y -CONFIG_IO_STRICT_DEVMEM=y +CONFIG_X25=m +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_X86=y +CONFIG_X86_16BIT=y +CONFIG_X86_64=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_X86_ACPI_CPUFREQ=y +CONFIG_X86_ACPI_CPUFREQ_CPB=y +CONFIG_X86_AMD_FREQ_SENSITIVITY=m +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_X86_AMD_PSTATE=y +CONFIG_X86_AMD_PSTATE_DEFAULT_MODE=3 +# CONFIG_X86_AMD_PSTATE_UT is not set +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y +CONFIG_X86_BUS_LOCK_DETECT=y +CONFIG_X86_CET=y +CONFIG_X86_CHECK_BIOS_CORRUPTION=y +CONFIG_X86_CMOV=y +# CONFIG_X86_CPA_STATISTICS is not set +CONFIG_X86_CPUID=m +# CONFIG_X86_CPU_RESCTRL is not set +CONFIG_X86_CX8=y +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_X86_DEBUG_FPU=y +# CONFIG_X86_DECODER_SELFTEST is not set +CONFIG_X86_DIRECT_GBPAGES=y +CONFIG_X86_DISABLED_FEATURE_CENTAUR_MCR=y +CONFIG_X86_DISABLED_FEATURE_CYRIX_ARR=y +CONFIG_X86_DISABLED_FEATURE_K6_MTRR=y +CONFIG_X86_DISABLED_FEATURE_LAM=y +CONFIG_X86_DISABLED_FEATURE_USER_SHSTK=y +CONFIG_X86_DISABLED_FEATURE_VME=y +CONFIG_X86_ESPFIX64=y +CONFIG_X86_EXTENDED_PLATFORM=y +CONFIG_X86_FRED=y +# CONFIG_X86_GOLDFISH is not set +CONFIG_X86_HAVE_PAE=y +CONFIG_X86_HV_CALLBACK_VECTOR=y +CONFIG_X86_INTEL_LPSS=y +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +# CONFIG_X86_INTEL_MID is not set +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_IOPL_IOPERM=y +CONFIG_X86_IO_APIC=y +CONFIG_X86_KERNEL_IBT=y +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_AMD=y +# CONFIG_X86_MCE_INJECT is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_THRESHOLD=y +CONFIG_X86_MEM_ENCRYPT=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_MPPARSE=y +CONFIG_X86_MSR=m +# CONFIG_X86_NATIVE_CPU is not set +CONFIG_X86_NEED_RELOCS=y +CONFIG_X86_NUMACHIP=y +CONFIG_X86_P4_CLOCKMOD=m +CONFIG_X86_PAT=y +CONFIG_X86_PCC_CPUFREQ=y +CONFIG_X86_PKG_TEMP_THERMAL=m +CONFIG_X86_PLATFORM_DEVICES=y +CONFIG_X86_PLATFORM_DRIVERS_DELL=y +CONFIG_X86_PLATFORM_DRIVERS_HP=y +CONFIG_X86_PMEM_LEGACY=y +CONFIG_X86_PMEM_LEGACY_DEVICE=y +CONFIG_X86_PM_TIMER=y +# CONFIG_X86_POSTED_MSI is not set +CONFIG_X86_POWERNOW_K8=y +CONFIG_X86_REQUIRED_FEATURE_ALWAYS=y +CONFIG_X86_REQUIRED_FEATURE_CMOV=y +CONFIG_X86_REQUIRED_FEATURE_CPUID=y +CONFIG_X86_REQUIRED_FEATURE_CX8=y +CONFIG_X86_REQUIRED_FEATURE_FPU=y +CONFIG_X86_REQUIRED_FEATURE_FXSR=y +CONFIG_X86_REQUIRED_FEATURE_LM=y +CONFIG_X86_REQUIRED_FEATURE_MSR=y +CONFIG_X86_REQUIRED_FEATURE_NOPL=y +CONFIG_X86_REQUIRED_FEATURE_PAE=y +CONFIG_X86_REQUIRED_FEATURE_XMM=y +CONFIG_X86_REQUIRED_FEATURE_XMM2=y +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_SGX=y +CONFIG_X86_SGX_KVM=y +CONFIG_X86_SPEEDSTEP_CENTRINO=y +CONFIG_X86_SPEEDSTEP_LIB=m +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_X86_THERMAL_VECTOR=y +CONFIG_X86_TSC=y +CONFIG_X86_UMIP=y +# CONFIG_X86_USER_SHADOW_STACK is not set +# CONFIG_X86_UV is not set # CONFIG_X86_VERBOSE_BOOTUP is not set -CONFIG_EARLY_PRINTK_DBGP=y -CONFIG_IO_DELAY_0XED=y -CONFIG_PUNIT_ATOM_DEBUG=m -CONFIG_UNWINDER_FRAME_POINTER=y -CONFIG_NOTIFIER_ERROR_INJECTION=m -CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m -CONFIG_FUNCTION_ERROR_INJECTION=y -CONFIG_INTERVAL_TREE_TEST=m -CONFIG_PERCPU_TEST=m -CONFIG_ASYNC_RAID6_TEST=m -CONFIG_TEST_HEXDUMP=m -CONFIG_TEST_KSTRTOX=m -CONFIG_TEST_BITMAP=m -CONFIG_TEST_UUID=m -CONFIG_TEST_XARRAY=m -CONFIG_TEST_RHASHTABLE=m -CONFIG_TEST_IDA=m -CONFIG_TEST_PARMAN=m -CONFIG_TEST_LKM=m -CONFIG_TEST_BITOPS=m -CONFIG_TEST_VMALLOC=m -CONFIG_TEST_BPF=m -CONFIG_FIND_BIT_BENCHMARK=m -CONFIG_TEST_FIRMWARE=m -CONFIG_TEST_UDELAY=m -CONFIG_TEST_STATIC_KEYS=m -CONFIG_TEST_OBJAGG=m -CONFIG_TEST_OBJPOOL=m -CONFIG_MEMTEST=y +CONFIG_X86_VMX_FEATURE_NAMES=y +# CONFIG_X86_VSMP is not set +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_X2APIC=y +CONFIG_X86_X32_ABI=y +CONFIG_X9250=m +CONFIG_XARRAY_MULTI=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XEN=y +CONFIG_XENFS=m +CONFIG_XEN_512GB=y +CONFIG_XEN_ACPI=y +CONFIG_XEN_ACPI_PROCESSOR=y +CONFIG_XEN_AUTO_XLATE=y +CONFIG_XEN_BACKEND=y +CONFIG_XEN_BALLOON=y +CONFIG_XEN_BALLOON_MEMORY_HOTPLUG=y +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_XEN_BLKDEV_FRONTEND=y +CONFIG_XEN_COMPAT_XENFS=y +# CONFIG_XEN_DEBUG_FS is not set +CONFIG_XEN_DEV_EVTCHN=m +CONFIG_XEN_DOM0=y +CONFIG_XEN_EFI=y +CONFIG_XEN_FBDEV_FRONTEND=m +CONFIG_XEN_FRONT_PGDIR_SHBUF=m +CONFIG_XEN_GNTDEV=m +CONFIG_XEN_GRANT_DEV_ALLOC=m +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_XEN_GRANT_DMA_OPS=y +CONFIG_XEN_HAVE_PVMMU=y +CONFIG_XEN_HAVE_VPMU=y +CONFIG_XEN_MCE_LOG=y +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT=512 +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_XEN_NETDEV_FRONTEND=y +CONFIG_XEN_PCIDEV_BACKEND=m +CONFIG_XEN_PCIDEV_FRONTEND=m +CONFIG_XEN_PCI_STUB=y +CONFIG_XEN_PRIVCMD=m +CONFIG_XEN_PRIVCMD_EVENTFD=y +CONFIG_XEN_PV=y +# CONFIG_XEN_PVCALLS_BACKEND is not set +CONFIG_XEN_PVCALLS_FRONTEND=m +CONFIG_XEN_PVH=y +CONFIG_XEN_PVHVM=y +CONFIG_XEN_PVHVM_GUEST=y +CONFIG_XEN_PVHVM_SMP=y +CONFIG_XEN_PV_DOM0=y +CONFIG_XEN_PV_MSR_SAFE=y +CONFIG_XEN_PV_SMP=y +CONFIG_XEN_SCRUB_PAGES_DEFAULT=y +CONFIG_XEN_SCSI_BACKEND=m +CONFIG_XEN_SCSI_FRONTEND=m +CONFIG_XEN_SYMS=y +CONFIG_XEN_SYS_HYPERVISOR=y +CONFIG_XEN_UNPOPULATED_ALLOC=y +CONFIG_XEN_VIRTIO=y +# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set +CONFIG_XEN_WDT=m +CONFIG_XEN_XENBUS_FRONTEND=y +CONFIG_XFRM=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_IPCOMP=m +# CONFIG_XFRM_IPTFS is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_USER=m +CONFIG_XFRM_USER_COMPAT=m +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_ONLINE_SCRUB is not set +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +# CONFIG_XFS_SUPPORT_ASCII_CI is not set +CONFIG_XFS_SUPPORT_V4=y +# CONFIG_XFS_WARN is not set +CONFIG_XIAOMI_WMI=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_DMA=m +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_XILINX_SDFEC=m +CONFIG_XILINX_VCU=m +CONFIG_XILINX_WATCHDOG=m +CONFIG_XILINX_XADC=m +CONFIG_XILINX_XDMA=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +CONFIG_XOR_BLOCKS=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARM64=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_RISCV=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_TEST=m +CONFIG_XZ_DEC_X86=y +CONFIG_YAM=m +CONFIG_YAMAHA_YAS530=m +CONFIG_YELLOWFIN=m +CONFIG_YENTA=m +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_YOGABOOK=m +CONFIG_YT2_1380=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_ZEROPLUS_FF=y +CONFIG_ZERO_CALL_USED_REGS=y +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_ZISOFS=y +CONFIG_ZL3073X=m +CONFIG_ZL3073X_I2C=m +CONFIG_ZL3073X_SPI=m +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONEFS_FS=m +CONFIG_ZONE_DEVICE=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ZOPT2201=m +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +CONFIG_ZRAM=m +CONFIG_ZRAM_BACKEND_842=y +CONFIG_ZRAM_BACKEND_DEFLATE=y +CONFIG_ZRAM_BACKEND_LZ4=y +CONFIG_ZRAM_BACKEND_LZ4HC=y +CONFIG_ZRAM_BACKEND_LZO=y +CONFIG_ZRAM_BACKEND_ZSTD=y +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_DEF_COMP_842 is not set +# CONFIG_ZRAM_DEF_COMP_DEFLATE is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC=y +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set diff --git a/SPECS/linux-lts/linux-lts.spec b/SPECS/linux-lts/linux-lts.spec index 6b4d19c424..ccaad86697 100644 --- a/SPECS/linux-lts/linux-lts.spec +++ b/SPECS/linux-lts/linux-lts.spec @@ -25,16 +25,24 @@ %global kver %{version}-%{release} %global kernel_make_flags LD=ld.bfd KBUILD_BUILD_VERSION=%{release} +%if "%{?openruyi_riscv_arch}" == "-march=rva20u64" + %global arch_suffix -rva20 +%else + %global arch_suffix %{nil} +%endif + Name: linux-lts -Version: 6.18.34 +Version: 6.18.38 Release: %autorelease Summary: The Linux lts Kernel License: GPL-2.0-only URL: https://www.kernel.org/ -#!RemoteAsset: sha256:640c4732fb42842166db97e032c1fe7e5ff72c85a8982c75b40f74be3555d760 +#!RemoteAsset: sha256:ac26e508abd56e9f8b89872b6e10c49fc823bcc70d8068a5d8504c1a7c4ff045 Source0: https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-%{version}.tar.xz -Source1: config.%{_arch} -Source2: series +Source1: series +Source2: config.x86_64 +Source3: config.riscv64 +Source4: config.riscv64-rva20 BuildRequires: gcc BuildRequires: bison @@ -82,7 +90,7 @@ Requires(post): kernel-install Requires(postun): kernel-install %patchlist -%include %{SOURCE2} +%include %{SOURCE1} %description This is a meta-package that installs the core kernel image and modules. @@ -125,7 +133,7 @@ for booting. %prep %autosetup -p1 -n linux-%{version} -cp %{SOURCE1} .config +cp -v %{_sourcedir}/config.%{_arch}%{arch_suffix} .config echo "-%{release}" > localversion %conf diff --git a/SPECS/linux-lts/series b/SPECS/linux-lts/series index aa3b3648e0..0bd7c7dfe4 100644 --- a/SPECS/linux-lts/series +++ b/SPECS/linux-lts/series @@ -289,184 +289,279 @@ 0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch 0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch 0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch -0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch -0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch -0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch -0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch -0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch -0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch -0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch -0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch -0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch -0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch -0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch -0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch -0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch -0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch -0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch -0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch -0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch 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