10:0.2.0 test confused

[BruceHz]

our sample fail with tnvme 10:0.2.0 , trace describe as below：

1. host mask msix and send several cmds
2. cmds handled with out msix and host did not update cq head
3. host update cq head and unmask msix ， then msix been sent
   4. host mask msix， update cq head and unmask again
   5. since msix-pending bit has cleared，our sample has no msix sent
   6. test fail

I guess if send msix in #5, the test will be pass. I did not find the proof in PCIe&NVMe spec.
And could please show me the proof？ thank you very much。