diff --git a/.agents/benchmark-record.md b/.agents/benchmark-record.md
index ae772e7b7..17047de06 100644
--- a/.agents/benchmark-record.md
+++ b/.agents/benchmark-record.md
@@ -9719,7 +9719,7 @@ M=$HOME/.cache/huggingface/hub/models--deepseek-ai--DeepSeek-V2-Lite/snapshots/6
 | fp8 cuBLASLt plan cache (`KERNEL-GEMM-FP8`) | **DONE / MEASURED NEUTRAL - bit-exact mirror, OPT-IN (`VT_FP8_PLAN_CACHE=1`), premise disproven** | The fp8 dense GEMM (`cuda_matmul.cu`) rebuilt the cuBLASLt descriptor + 3 TN layouts + heuristic every call; vLLM reuses an in-graph plan. Added a per-device `{desc,layouts,algo}` cache keyed on the full shape/config (`fp8_plan_cache.h`); BIT-EXACT (algo process-deterministic per shape - byte-exact cached==fresh `test_ops_fp8_cutlass` + CPU key/flag 4/4; 27B 235/235 + 35B 315/315 both flags). **Same-binary 35B A/B (one flock) is wall-clock NEUTRAL**: prefill TTFT in1024/c8 async-on ON 1491.5/OFF 1496.8, async-off ~1496.7/~1503.2; decode TPOT c1 15.16/15.14, c4 21.79/21.83. **nsys (async-off eager prefill): the pre-fp8-GEMM GPU gap is UNCHANGED - median 210 µs (off) vs 204 µs (on)** ⇒ the grounded "~0.8 ms removable gap" premise is NOT reproduced; the heuristic host cost is negligible/hidden (prefill GPU-bound; decode graph-captured so the heuristic runs at capture, not per replay-step). Kept opt-in for eager/non-graph regimes; default NOT flipped (faster unmet). Evidence `dgx:/tmp/fp8pc-*` + `~/work/prefill-attr-35b` | None - the vLLM-mirror lands opt-in; no default-flip and no speed credit |
 | Serving transport (TCP_NODELAY) | **DONE / MEASURED NEUTRAL on the gate workload** | Mirror landed (`SERVE-HTTP-TRANSPORT`): `set_tcp_nodelay(true)` matches vLLM's uvicorn/asyncio default; behavioral accepted-socket test RED **0** → GREEN **1**, 22/22 cases. The non-binding one-lock localhost A/B (`~/work/vllm.cpp-tcpnodelay-sizing/ff915e8…`, 4a450f9 Nagle-ON vs ff915e8 Nagle-OFF, c1/c2 ×2 reps, identical pinned-client workload; raw-set SHA `f5b52900…2128`) is **neutral within noise** on every ITL/TPOT/throughput metric (c1 mean ITL ~102.7 both arms; c2 ~108-109; first cold-start leg excluded). Mechanism: ~100 ms per-token write cadence vs µs loopback ACKs means Nagle never coalesces - the rescan's rank-1 gain hypothesis is REFUTED for the loopback gate; the mirror stays for real-network parity | None for the gate - the c2/c8 full-step attribution is complete (transport ruled out; c2 gap is GPU-busy kernel glue) |
 | Block-table host-cluster cleanup ([rescan](specs/rescan-lost-lanes-2026-07-16.md) §1,§5,§6) | **CPU-SIDE, BIT-IDENTICAL; `benchmark_binding=false`, no speed credit** - the payoff is measured by the dispatched correct-state c2/c8 full-step probe and the next authorized exact grid, not by these mirrors. **(c) LANDED** - `block_table.compute_slot_mapping` drops the dead tail-pad (`~2×(max_num_batched_tokens−total)` int64 writes/step; the decode graph re-pads via `BuildPaddedDecode`, the only other consumer slices `[0,total)`); test_block_table 11/11, test_prepare_inputs 6/6. **(d) LANDED** - the decode-graph capture-size set is DERIVED from `max_num_seqs` (`include/vllm/model_executor/models/decode_graph_sizes.h`, `DecodeGraphSizes`/`PadToCaptureSize`; mirrors vLLM `_set_cudagraph_sizes` reduced to the full-decode-cudagraph regime): `max_num_seqs=32` → `{1,2,4,8,16,24,32}` (adds the missing 24 bucket, drops the never-reachable 64; batches 17-24 stop over-padding to 32, +1 captured graph). CUDA-only; padding rows inert → token-exact. RED→GREEN `test_decode_graph_sizes` 5 cases/478 asserts (RED = 24 bucket absent under the old fixed set). **(e) LANDED** - `InputBatch::make_sampling_metadata` caches + rebuilds only on batch change (add/remove/condense/swap set a dirty flag), mirroring vLLM `refresh_metadata` (gpu_input_batch.py:812-830); deviation: the penalty-active path rebuilds every step (our port copies output_token_ids where vLLM holds a live ref), so the greedy/no-penalties gate gets the full win bit-identically. `scheduler.cpp:371,377` `std::move`s the `num_scheduled_tokens` map + `finished_req_ids` set (container plumbing, zero policy change; move-then-clear keeps observable behavior identical). RED→GREEN `test_input_batch` (+2 cases; RED = stale cache after a 2nd add returns size 1 != 2); `test_scheduler` 31/31, `test_runner` 228/228, `test_sampling_metadata` 6/6 unchanged. Items (a)-runner + (b) (GDN col-0) are in `runner.cpp` (async/GDN-claim owned) - reported, not touched. Landed `8a717b2`/`81afc36`/`0c4b41c` (merged `e027ad5`); clean full `-Werror` rebuild 0 warnings, CPU battery + tools 164/164 green. **DGX token-exactness gate PASSED** on the `e027ad5` build (GB10, one `flock /tmp/gpu` series, root `dgx:~/work/vllm.cpp-blocktable-gate`): 27B default **235/235**, 27B `VT_GDN_PACKED_DECODE=0` rollback **235/235**, 35B **315/315**, all exit 0 | **CLOSED - claim released.** No A/B by design (`benchmark_binding=false`, no speed credit); payoff measured by the c2/c8 attribution probe + the next authorized exact grid |
-| Host-weight ownership | **Established 27B binding memory axes remain PASS at `246a23c`. Local plain-BF16 4B remains `GATING`.** Current direct ON/OFF/stable-vLLM peak PSS is **2.406/8.592/7.662 GiB**, stable PSS **0.759/8.589/4.029 GiB**, and peak VRAM **12850.7/12843.3/12942.7 MiB**. Direct ON=OFF output IDs match 128/128 in every pair; direct loading cuts peak/stable PSS **72.0%/91.2%** and stays within the +8 MiB ON-vs-OFF VRAM gate. | H32 AOT, plain-BF16 graph and ratio-4 FA2 are complete. Current total throughput is **5769.99/5660.70/5849.80 tok/s** for ON/OFF/vLLM, so ON is **0.9864x** vLLM; TPOT/ITL **43.72 vs 38.55 ms** keeps speed open. Implement a compaction-safe device-resident sampled-token map for discrete CUDA, remove the immediate main-stream wait, then rerun the exact series. [Binding evidence](../docs/bench-evidence/qwen35-4b-main-repair-20260725.md). |
+| Host-weight ownership | **Established 27B binding memory axes remain PASS at `246a23c`. Local plain-BF16 4B remains `GATING`.** Current direct ON/OFF/stable-vLLM peak PSS is **2.406/8.592/7.662 GiB**, stable PSS **0.759/8.589/4.029 GiB**, and peak VRAM **12850.7/12843.3/12942.7 MiB**. Direct ON=OFF output IDs match 128/128 in every pair; direct loading cuts peak/stable PSS **72.0%/91.2%** and stays within the +8 MiB ON-vs-OFF VRAM gate. | H32 AOT, plain-BF16 graph and ratio-4 FA2 are complete. As of 2026-07-25 total throughput was **5769.99/5660.70/5849.80 tok/s** for ON/OFF/vLLM, so ON was **0.9864x** vLLM; TPOT/ITL **43.72 vs 38.55 ms**. **SUPERSEDED 2026-08-12 ([#527](https://github.com/mudler/vllm.cpp/issues/527)):** the "implement a compaction-safe device-resident sampled-token map for discrete CUDA, remove the immediate main-stream wait, then rerun the exact series" next-action is DONE and its premise REFUTED — the map landed `deed7c2a1` (2026-07-27) and is DEFAULT ON since `1718bf155` (2026-08-05), and `deed7c2a1` records that the 497-`cudaStreamSynchronize` attribution motivating the wait removal is wrong for this workload (`vllm-bench` drives the synchronous `LLMEngine::step()`, so `sample_tokens_async` never runs). The series was rerun through 2026-08-09: throughput **6831.71 vs 6643.40 tok/s (1.0283x PASS)**; TPOT/ITL **1.0165x** and peak VRAM **+118.7 MiB** remain the open axes. Next action is same-tool interval profiling to split the residual TTFT into intake vs prefill. [2026-07-25 binding evidence](../docs/bench-evidence/qwen35-4b-main-repair-20260725.md); [current sm_120 baseline](../docs/bench-evidence/qwen35-4b-sm120-main-20260807.md). |
 | Qwen3.6-35B-A3B performance | **BLOCKED / NOT RUN (grid crash FIXED)** | Correctness passes; no current v0.25.0 performance denominator exists. The 35B online-serving **c2+ crash that blocked the grid is root-caused + FIXED** (2026-07-18, `CLAIM-35B-GRAPH-SCRATCH-1`, [spec](specs/decode-graph-scratch-uaf-2026-07-18.md)): at concurrency > 1 the engine died with `cudaEventSynchronize: an illegal memory access`. cuda-gdb pinned the faulting kernel to `marlin_moe_wna16::Marlin<…><<<(144,1,1),(128,1,1)>>>` - its fp32-reduce scratch `c_tmp` (`EnsureCtmp`, `cuda_moe_marlin.cu`) is a grow-on-free per-stream buffer whose pointer is baked into the captured pure-decode CUDA graph; a bigger later prefill/decode `cudaFreeAsync`s it → the next graph replay reads freed memory (single-stream c1 never grows it → never crashed). Differential isolation: needs graphs ON + concurrency > 1 + long context; async/WMMA ruled OUT (async-off + wmma-off still 5/5 crash; graphs-off CLEAN); memcheck masks it. Fix = retire-on-grow (`RetireGraphScratch`, `src/vt/cuda/graph_safe_scratch.h`) across the four decode-graph-reached scratch allocators. Sweep c1-c16 pre-fix 5/5 crash → post-fix 0; 315/315 token-exact preserved. `benchmark_binding=false` (correctness fix, no speed credit) | Run the v0.25.0 performance grid (now unblocked) after 27B reaches 124/124 |
 | 35B FA2-prefill + fused-preamble lever | **LANDED / default-ON (2026-07-18, `CLAIM-35B-FA2-FLIP-1`); `benchmark_binding=false` (offline op A/B, no grid speed credit - the 35B grid re-measures in-situ)** ([spec](specs/qwen36-35b-fa2-prefill-oracle-2026-07-18.md)) | `FuseAttnPreambleOn` flipped default-ON all arches ⇒ the 35B ratio-8 full-attn layers take the exact `flash_fwd_splitkv` kernel (kernel-side `fa2_prefill` admits any GQA ratio at head_dim 256, `cuda_paged_attn.cu:2494`). FULL current-main default-set gate (async + GDN cubin + all fast kernels + flip): **35B `test_qwen36_paged_engine` 315/315 + 27B `test_qwen27_paged_engine` 235/235** (`dgx:/tmp/fa2gates_u.log`); **memcheck 35B prefill 0 errors** (`dgx:/tmp/fa2_memcheck2.log`); `test_ops_attn_preamble` 14/14. Realistic input-1024 TTFT A/B (same binary, FA2 default vs `VT_FA2_PREFILL=0`, conc8/num-prompts32, 3 interleaved on/off pairs + dropped warmup, `dgx:/tmp/fa2_ttft2.log`): **FA2-on Mean TTFT 824.7 ms vs off 874.4 ms = −5.7%** (median 638.6 vs 676.9 = −5.7%; prefill token-throughput 5170.5 vs 4902.5 tok/s = +5.5%; per-arm spread <7 ms, so the ~50 ms gap is well-separated). Below the ~7-9% offline-kernel target because the 1.86× attention-kernel win dilutes across the whole prefill (GEMM/MoE/GDN dominate); no decode/TPOT regression (prefill-only lever, both arms 315/315 token-exact). The "round normed q/k→bf16 before RoPE" tighten (`fused_qk_norm_rope.py:67`) was op-level bit-identical (fused-bf16 == unfused-bf16, q/k 0-mismatch) but flipped the 27B tok6 whitespace near-tie away from the pip-vLLM oracle (233/235) in COMBINATION (RMSNorm-saga) ⇒ NOT shipped; preamble ships UNTIGHTENED, both arches token-exact. CPU gate: clean `-Werror` rebuild 0 errors/0 warnings, full DGX ctest **156/157** (both engine gates green; the sole failure `test_capi` is a KNOWN pre-existing nondeterministic dgx-box detokenizer UTF-8 flake - 3 runs of the same binary give 3 different results - not a regression, unrelated to the attention path), tools unittest 164/164, checkers green | The 35B v0.25.0 perf grid (orchestrator-owned) re-measures the in-situ prefill/TTFT gain from this lever |
 | 35B FA2-decode lever (split-KV, ratio-8) | **LANDED / default-ON (2026-07-19, `CLAIM-35B-FA2-DECODE-1`); `benchmark_binding=false` (focused same-binary in-situ A/B - the 35B grid re-measures)** ([spec §35B ratio-8 extension](specs/fa2-gqa-split-kv-decode.md)) | Extended the ratio-6-only FA2 split-KV DECODE to the 35B ratio-8 (Hq/Hkv=16/2) hd-256 full-attn layers (new env `VT_FA2_DECODE_35B`, default ON). The old ratio-8 decode ran `PagedAttentionDecodeGqaKernel` at **grid=(num_reqs,num_kv_heads) = 2 blocks** at single-request decode (near-zero GB10 occupancy); the vendored `flash_fwd_splitkv` main+combine splits the KV dimension so the grid fills the machine. nsys `--cuda-graph-trace=node` (`test_qwen36_paged_engine`): clean 1:1 decode-kernel swap - OFF `PagedAttentionDecodeGqaKernel<...(int)8...>` ×300 (grid (1,2,1)=2 / (8,2,1)=16, no combine) → ON `flash_fwd_splitkv_kernel` ×300 + `flash_fwd_splitkv_combine_kernel` ×300 (split axis GridZ up to 16), old kernel absent. FULL current-main default-set token gate: 35B `test_qwen36_paged_engine` **315/315** + 27B `test_qwen27_paged_engine` **235/235**; operator `test_ops_paged_attn` **21 cases / 454,358 assertions** (adds ratio-8 parity ladder B∈{1,2,4,8,16} + ratio-4/window/toggle fallback); memcheck 35B decode **0 illegal-access errors** (315/315; `--leak-check full` leaks are engine exit-time model residency). IN-SITU A/B (35B NVFP4, input-1024/output-128, greedy, same binary `VT_FA2_DECODE_35B=1` vs `=0`, one flock, 4 interleaved ON/OFF pairs, first dropped, pooled pairs 2-4): **c1 Mean TPOT 14.96 vs 16.72 ms = −10.5%** (total tput 540.1 vs 489.3 = +10.4%); **c8 Mean TPOT 33.02 vs 34.12 ms = −3.2%** (tput 1835.1 vs 1785.7 = +2.8%); Mean TTFT neutral (c1 ~233, c8 ~826 ms both arms - decode-only lever). Per-arm spread <0.15 ms TPOT, well-separated. Token-exact + faster ⇒ default-ON. Evidence `dgx:~/work/vllm.cpp-35b-fa2-decode/{gpu_series,gates_engine,gates_default,memcheck35,nsys_ON,nsys_OFF}.log`. CPU gate: clean `-Werror` CUDA build 0/0, tools 164/164, checkers green; full DGX ctest `-j8` **157/160** - 3 non-numerics misses: `test_async_llm` (parallel-port flake, passes 1/1 isolated), `test_capi` (documented nondeterministic dgx detokenizer UTF-8 flake, fails even isolated, unrelated to attention), `test_qwen36_gguf_engine` (MEMORY-capacity artifact: loads TWO full 35B GGUF models sequentially; with FA2 decode ON the first runs 16/16 correct through the FA2 decode path then the second model load OOMs; `VT_FA2_DECODE_35B=0` rerun passes 2 cases / 28/28, so the added decode scratch tips an already-marginal ~119 GiB unified-memory box - NOT a correctness regression; the production safetensors NVFP4 35B is 315/315 ON - flagged for a decode-scratch-pool follow-up) | The 35B v0.25.0 perf grid (orchestrator-owned) re-measures the in-situ c1-c4 decode-TPOT gain; this directly targets the 35B c1 decode 0.810× low-batch residual |
diff --git a/.agents/coordination.md b/.agents/coordination.md
index 3dc1288fa..ddf74ca78 100644
--- a/.agents/coordination.md
+++ b/.agents/coordination.md
@@ -2213,6 +2213,18 @@ list of what the project supports.
   request-compaction-safe device token map, not retune FA2 blindly or delete
   the synchronization without preserving row identity.
   Evidence: [2026-07-25 4B repair](../docs/bench-evidence/qwen35-4b-main-repair-20260725.md).
+  **That next-owner directive is SUPERSEDED, 2026-08-12
+  ([#527](https://github.com/mudler/vllm.cpp/issues/527)) — the checkpoint text
+  above is left as written, but do not act on it.** The
+  request-compaction-safe device token map landed two days later in `deed7c2a1`
+  (2026-07-27, runner-owned device buffers + `LaunchApplyLastSampledOps` replaying
+  condense's row edits on-device) and is DEFAULT ON since `1718bf155`
+  (2026-08-05); the wait it was meant to repair does not exist on the benchmarked
+  path, because `vllm-bench` drives the synchronous `LLMEngine::step()` and never
+  enters `sample_tokens_async` — `deed7c2a1` records that refutation of the
+  497-`cudaStreamSynchronize` attribution itself. The exact series was rerun
+  through 2026-08-09 (**1.0283x PASS** on throughput). The row's live plan is
+  [the sm_120 Pareto campaign](specs/sm120-qwen35-pareto-2026-08-09.md).
 
 **DFlash D14 note (2026-07-27, `CLAIM-DFLASH-D14`, GPU-GATED on dgx, SPEED GATE MET → `SPEC-DFLASH` DONE, NOT pushed — FULL SHA reported to caller).** Closes `SPEC-DFLASH` (engine-matrix row `SPEC-DFLASH` + kernel-matrix `KERNEL-ATTN-DFLASH-PAGED-BLOCK` + model-matrix `MODEL-SPEC-qwen3-dflash-dflash-qwen3-for-causal-lm`) → `DONE`. Base `origin/main` `4657f6f3`, isolated worktree `/home/mudler/_git/wt-dflash-d14` (branch `dflash-d14`); dgx reused tree `~/work/dflash-d12/tree/build-cuda`, one `flock $HOME/gpu.lock`. An nsys of the graphed spec-on step attributed the D13 ~2% residual to the from-scratch draft-attention kernel; ported it to a WARP-scoped online-softmax variant (`DFlashPagedBlockAttentionWarpKernel`, 3.1× faster) → our-ON graphed 29.32 ≥ vLLM-ON graphed 29.240 (non-overlapping 3-rep bands, 1.003×). Correctness UNCHANGED (27/27 graph==eager, acceptance 19/39/29/25, 1629 accepted identical warp-vs-block, CUDA==CPU 795648/795648 + sanitizer 0); inertness SACRED 235/235 + MTP 9/9. **Owned files ONLY:** `src/vt/cuda/cuda_ops.cu` (additive: `DFlashPagedBlockAttentionWarpKernel` + `UseDflashAttnBlockKernel` + a launcher branch; the D12 block kernel retained under `VT_DFLASH_ATTN_BLOCK=1`) + the record surfaces (spec §0 D14 RESULT, engine-matrix, kernel-matrix, model-matrix + checklist rollup, roadmap, ledger, state, this note, README, `docs/BENCHMARKS.md`). **EXPLICIT NON-COLLISION:** does NOT touch the causal `kAttention`/`kPagedAttention`, any non-DFlash op, the runner, or the models — the warp kernel is reached ONLY via `DFlashPagedBlockAttention` (DFlash draft path). Roadmap's FINAL open speed item; SPEC-DFLASH is now correctness-complete AND at/above vLLM throughput.
 
diff --git a/.agents/roadmap_v1.md b/.agents/roadmap_v1.md
index 63ee573b7..2a4bf2f1b 100644
--- a/.agents/roadmap_v1.md
+++ b/.agents/roadmap_v1.md
@@ -40,6 +40,7 @@ issue is not yet placed. Keyed record: update in place, never append.
 |---:|---|---|---|
 | [#168](https://github.com/mudler/vllm.cpp/issues/168) | `BACKEND-CUDA-SM110` | Jetson AGX Thor (sm_110): 32B NVFP4, Tekken tokenizer blocker | feature |
 | [#433](https://github.com/mudler/vllm.cpp/issues/433) | `BACKEND-GATE-CPU-LLAMACPP` | No x86_64 arm: the closed CPU floor is Arm/i8mm-only and every lever that closed it is Arm-specific | perf |
+| [#529](https://github.com/mudler/vllm.cpp/issues/529) | `BACKEND-GATE-CPU-LLAMACPP` | `test_cpu_x86_llamacpp_floor` fails on a BUSY host, so preflight can fail itself: the contended-leg test asserts exit 2 but the unpinned real-loadavg quiet window exits 4 first | bug |
 | [#199](https://github.com/mudler/vllm.cpp/issues/199) | `BACKEND-METAL-MLX` | macOS MLX build fails on `-Werror` in MLX headers | bug |
 | [#41](https://github.com/mudler/vllm.cpp/issues/41) | `BACKEND-ROCM` | ROCm (AMD GPU) backend | feature |
 | [#132](https://github.com/mudler/vllm.cpp/issues/132) | `BACKEND-ROCM` | ROCm `-O0` RmsNorm CLR HostcallListener teardown deadlock | bug |
@@ -118,6 +119,7 @@ issue is not yet placed. Keyed record: update in place, never append.
 | [#314](https://github.com/mudler/vllm.cpp/issues/314) | `ROAD-V1-C1` | `FUSION-DENSE-MIGRATE` glue half: `glm4`/`phi3` still hand-call add+RMSNorm instead of `vt::FusedChain` (split out of #299, which closed the merged-GEMM half only) | bug |
 | [#337](https://github.com/mudler/vllm.cpp/issues/337) | `ROAD-V1-C1` | `FUSION-DENSE-MIGRATE`: the five dgx SACRED paged-engine gates are OWED after the merged-GEMM fold (`test_{commandr,glm4,minicpm,minicpm3,phi3}_paged_engine` SKIP on a CPU box) | bug |
 | [#338](https://github.com/mudler/vllm.cpp/issues/338) | `ROAD-V1-C1` | MiniCPM/MiniCPM3 hard-code SiLU: upstream `MiniCPMMLP` (`minicpm.py:219-226`) selects `FatreluAndMul` on `hidden_act == "fatrelu"` and raises otherwise; our `parse_config` never reads `hidden_act` | bug |
+| [#527](https://github.com/mudler/vllm.cpp/issues/527) | `ROAD-V1-C2-LOCAL-BF16` | Punch-list item 14 directs work that landed 2026-07-27 (`deed7c2a1`, default-ON `1718bf155`), on a 497-`cudaStreamSynchronize` premise the same commit refuted | bug |
 | [#241](https://github.com/mudler/vllm.cpp/issues/241) | `ROAD-V1-H3` | MiniMax-H3: support the PRUNED (AdaLN timestep-curve) checkpoint variants | feature |
 | [#471](https://github.com/mudler/vllm.cpp/issues/471) | `GATE-PIN-UNPINNED-SNAPSHOTS` | Checkpoint gates resolve their snapshot UNPINNED: 56 of 61 take whatever `directory_iterator` yields, including the three DFlash gates on a repo caching two materially different revisions (spec `specs/gate-pin-unpinned-snapshots.md`) | bug |
 | [#472](https://github.com/mudler/vllm.cpp/issues/472) | `GATE-PIN-UNPINNED-SNAPSHOTS` | 80 of 92 committed goldens record no checkpoint revision, so their gates cannot be pinned from evidence (`q3mxfp4`, DFlash, every `*_greedy` corpus) | bug |
diff --git a/.agents/specs/roadmap-v1-completion.md b/.agents/specs/roadmap-v1-completion.md
index c8184459f..69a16f83a 100644
--- a/.agents/specs/roadmap-v1-completion.md
+++ b/.agents/specs/roadmap-v1-completion.md
@@ -36,7 +36,7 @@ carry more than one class list the dominant one first.
 | `ROAD-V1-MM` multimodal | **RI** (+EXT sub) | **Image + video STRICT token-exact 32/32** on Qwen3.6-27B and Qwen3-VL-4B; **audio e2e** on Voxtral-Mini-3B (near-tie-robust; decoder 48/48). Correctness is the user's #1 priority and it LANDED. SPEED progress: tower lever #1 CLOSED (2114→148 ms, faster than vLLM eager encode); decode lever #2 CLOSED 2026-07-27 (on-GPU greedy argmax + no embed round-trip; bit-exact; 27B decode NEUTRAL at parity, audio ~0.4% win — multimodal-speed.md §8); lever #3 FIRST BRICK 2026-07-27 (the 27B image+video decode now routes through the production `Qwen3_5DenseDecodeGraph` captured decode = GRAPH-CAPTURABLE, token-exact 32/32 held, NEUTRAL at the 27B bandwidth floor — multimodal-speed.md §9); lever #3 **W1 LANDED 2026-07-27** (new `VoxtralDecodeGraph` graph-captures the Voxtral audio decode; bit-exact 14/14 held; A/B steady TPOT graphed 60.94 vs eager 61.71 ms/tok, non-overlapping — a small real win that NARROWS the audio gap 1.52×→1.49× but does NOT close it — multimodal-speed.md §10); decode-kernel efficiency ATTRIBUTED + VALIDATED ceiling 2026-07-27 (`CLAIM-MM-SPEED-DECODE-KERN`, multimodal-speed.md §11) — the whole ~20 ms/tok audio residual is the naive scalar `PagedAttentionKernel` decode attention (723 µs × 30 = 21.7 ms/step); the 1:1 vLLM lever (FA2 `flash_attn_varlen` decode) is already in-binary, gated off only because the driver's single KV block (444) isn't ÷16; `block_size÷16` → TPOT 59.4→38.2 ms/tok (−21.2, ~36%) = 0.94× vLLM 40.8 ms (BEATS parity), FA2 sequence teacher-force-VALID (0 divergences, gap 0.0), but it flips the committed near-tie golden → blocked byte-exact; RECORDS-ONLY, 14/14 held, win one `block_size÷16` + golden regen away. **ADOPTED 2026-07-27 (USER-APPROVED, `CLAIM-MM-SPEED-DECODE-KERN-ADOPT`, multimodal-speed.md §12): FA2 decode SHIPS as the Voxtral default — audio DECODE BEATS vLLM (0.97×), the LAST mm decode-speed gap CLOSED.** One-line `block_size÷16` (nsys: `flash_fwd_splitkv` 1410 @ 18.5 µs, zero `PagedAttentionKernel`); `test_voxtral_e2e` → ratified near-tie DISTRIBUTIONAL gate (binding = teacher-force PASS, kernel-independent; strict prefix exact to first bf16 tie, FA2 pos 18; determinism anchor to the FA2 seq); `voxtral_neartie.json` regenerated (md5 `937b9ad3…`), STRICT greedy golden UNCHANGED; gate PASS 16/16; teacher-force vLLM 0.25.0 = 0 divergent, gap 0.0, PASS; capture-safe (graph 46 replays + compute-sanitizer 0 errors + 3-run byte-identical) ⇒ DEFAULT graph path; A/B scalar 60.50 → FA2 **39.50 ms/tok** (−21.0, ~35%, NON-OVERLAPPING) = 0.97× vLLM 40.8. Audio DECODE now correctness+speed DONE; umbrella MM row stays PARTIAL (audio TTFT/encoder + c2+ batched serving). **ENCODER TTFT MEASURED + warp-attention brick 2026-07-27 (`CLAIM-MM-SPEED-AUDIO-ENC`, multimodal-speed.md §13):** routed the Whisper encoder self-attention (hd-64, non-causal) from the naive O(t²) `kAttention` to the warp-scoped `vt::AttentionDenseFast` (§7 tower fix; text byte-identical) — encoder forward **8870→1890 ms (4.7×, NON-OVERLAPPING)**, `test_voxtral_e2e` **16/16** with ZERO token flips, goldens md5 unchanged; **NOT at parity** (~1.89 s vs vLLM 43 ms, ~44× — the warp kernel is STILL 31.8 ms/layer, O(t²) memory-bound), closing needs a flash-TILED non-causal hd-64 attention (LARGE) + resident one-time encoder weights (MEDIUM, byte-exact). | Every-axis **SPEED** gate on all mm rows — none is DONE (`MODEL-MM-*` all PARTIAL/ACTIVE, speed-pending). Dominant residual = **lever #3: batched/graphed mm serving (c2+)**; the audio decode-KERNEL residual is now FULLY ATTRIBUTED (the scalar `PagedAttentionKernel`) and the fix is a VALIDATED bf16-near-tie ceiling (FA2 decode beats vLLM but changes the golden's near-tie branch — §11). **W1 REFINED the audio attribution:** graphing the Voxtral decode removed the per-step launch overhead but it was only ~1.25% of TPOT, so the ~20 ms/tok gap vs vLLM's 40.8 ms is per-step COMPUTE (the scalar decode-attention kernel), NOT launch overhead as §9.5 hypothesized. The audio decode win is now ADOPTED (FA2 SHIPS, §12 — audio decode BEATS vLLM 0.97×). Remaining lever-#3 W-plan (multimodal-speed.md §9.5/§13): audio TTFT NOW MEASURED our-side (32-layer Whisper encoder forward 1890 ms after the §13 warp-attention brick, still ~44× vs vLLM 43 ms — a flash-TILED non-causal hd-64 encoder attention + resident one-time encoder weights close it); W2 batched multi-seq (c2+); W3 `image_url`/`audio_url` serving ingestion. Gemma-4 mm/audio = EXT (below). Qwen3.6-35B mm needs a vision-inclusive checkpoint download + M2/M3 tower attach. |
 | `ROAD-V1-C1` extensibility | **DONE** (cornerstone) | Drop-in kernel ABI W0, Platform seam, model self-registration, and the **portable op-fusion framework ORDER-1 milestone** (W0–W4 merged+gated, `KERNEL-FUSION-FRAMEWORK`); consistency-audit CI check landed. `BACKEND-ABI-VT`/`BACKEND-CUDA-ARCH-ADDITIVITY` seams gated on sm_121a. | Row stays SPIKE-open only for **non-blocking** tail: Tier-1 fusion perf interpreter (composite-only → single-launch), `FUSION-DENSE-MIGRATE` (route 5 drift models — CLOSED 2026-08-10, [#299](https://github.com/mudler/vllm.cpp/issues/299)), a real Metal/Vulkan catalog realization (M4-reachable / HW-blocked), and migrating a production kernel family onto the common adapter. Correctness cornerstone is closed. |
 | `ROAD-V1-C2` model families | **RI** (+HW/EXT sub) | First additive model (Qwen3 dense) + a broad **text sweep correctness-complete + SACRED-gated**: Qwen3/Qwen3Moe/Coder, Llama/Yi/InternLM3, Mistral, GLM-4-9B/GLM-4.7-Flash, Gemma-1/2/3, OPT, DeepSeek-V2-Lite (MLA), OLMo-2, Phi-3/4, Phi-1/2, Granite-3, StableLM, InternLM2, MiniCPM, MiniCPM3 (MLA). 20 ACTIVE model rows. | **SPEED close** on every one (all 20 are "correctness-complete, speed pending"). MoE/SSM breadth (Qwen3-Next, Falcon, Falcon-H1, GraniteMoe*, Cohere2Moe, PhiMoE, Mamba/Jamba/Zamba2/NemotronH) = RI (INVENTORIED/SPIKE). Frontier: Kimi-Linear-48B fits (RI, +KDA kernel); DeepSeek-V3/GLM-5/MiniMax-M2/M3/Kimi-K2 = HW (>119 GiB); Command-R = EXT (HF token). |
-| `ROAD-V1-C2-LOCAL-BF16` | **RI** (S) | Local Qwen3.5-4B plain-BF16 diagnostic rebased onto current additive seams; CPU/CUDA + direct ON/OFF token-equivalence green; H32 AOT / plain-BF16 graphs / ratio-4 FA2 landed + trace-proven. | Port device-resident sampled-token mapping to discrete CUDA (remove the measured main-stream wait) and rerun the exact 4B series. Small. |
+| `ROAD-V1-C2-LOCAL-BF16` | **RI** (S) | Local Qwen3.5-4B plain-BF16 diagnostic rebased onto current additive seams; CPU/CUDA + direct ON/OFF token-equivalence green; H32 AOT / plain-BF16 graphs / ratio-4 FA2 landed + trace-proven. **Device-resident sampled tokens are DONE for discrete CUDA and DEFAULT ON** (`deed7c2a1` 2026-07-27 port, `1718bf155` 2026-08-05 flip), and the exact 4B series has been rerun six times through 2026-08-09 — throughput now **6831.71 vs 6643.40 tok/s (1.0283x PASS)**. | Same-tool `nsys --cuda-graph-trace=node` interval profiling on both engines to split the residual TTFT into intake vs prefill, then close the largest attributable interval without surrendering the throughput lead; TPOT/ITL **1.0165x** and peak VRAM **+118.7 MiB** stay open. Small. (The prior "port the sampled-token map / remove the measured main-stream wait" plan is SUPERSEDED and its 497-sync attribution REFUTED — §3 item 14, [#527](https://github.com/mudler/vllm.cpp/issues/527).) |
 | `ROAD-V1-C3` spec-decode | **DONE** (core) | **MTP k=1 DONE + gated on BOTH gate models** (`SPEC-MTP`, c1 token-exact + above vLLM, c2–c8 on-par-or-above); **DFlash DONE + speed gate MET** (`SPEC-DFLASH` D14, our-ON ≥ vLLM-ON). | Named tail only: DSpark (`SPEC-DSPARK`) + heterogeneous-vocabulary TLI (`SPEC-TLI`) unspiked — overlaps `ROAD-V1-D3`. Core spec-decode is gate-closed. |
 | `ROAD-V1-C4` quantization | **RI** | **3 schemes DONE**: NVFP4-MO-W4A16, NVFP4-CT-W4A4, FP8-MO-STATIC (all R/M/C/E/P). **GGUF CPU vs llama.cpp is CLOSED** (2026-07-22, aarch64 binding host): decode **at parity** (1.03× behind, inside llama.cpp's ±1.8% run spread — the elementwise f16/bf16 GEMM lever `KERNEL-GEMM-CPU-ELEM` E1-E4 `18094ee2` took it 3.38×→1.03×), prefill **1.18× ahead** (q8_0 repack-at-load G7), RSS **1.01×**, byte-identical greedy tokens. | NVFP4-CT-W4A16 perf gate. FP8-generic dispatch (static/dyn × tensor/channel/token/block). Breadth: AWQ/GPTQ/Marlin-wiring, i-quants, MXFP4/MX, bitsandbytes, KV-quant — all INVENTORIED. (GGUF-vs-llama.cpp speed is no longer an open C4 blocker.) |
 | `ROAD-V1-C5` sliding/YaRN | **RI** | Joint spike accepted; all W1–W8 leaves implemented and CPU/oracle/sanitizer green. **CUDA GPU CLOSURE 2026-07-27 (`CLAIM-ROADMAP-C5`, dgx GB10 sm_121a, clean build of `489f7771`, oracle vLLM 0.26.0.dev0):** shared scaled-RoPE + local-mask CUDA path compiles `-Werror`-clean + RUNS on GB10; feature-positive correctness gates PASS — SWA Gemma-2/Gemma-3 48/48, LongRoPE Phi-4-mini 16/16 (RED-first), llama3 Llama-3.2-1B 16/16, dynamic-NTK InternLM2 16/16; both RoPE 0.26-oracle recaptures BIT-IDENTICAL to goldens. `ATTN-SLIDING-WINDOW`/`ATTN-ROPE-{LLAMA3,LONGROPE,DYNAMIC-NTK}`/`ATTN-YARN` → `ACTIVE`; `ATTN-CHUNKED-LOCAL` + `KV-*-SPEC` honest. | **Honest residual (vehicle-blocked, not skipped):** YaRN model e2e (no cached Nomic/gpt-oss consumer) + chunked-local model e2e (no Llama4 row) REACHABLE-BLOCKED; long-context positive-mask (prompt > W) SWA e2e + KV-memory G8; every-axis **SPEED** tail (all leaves correctness-complete, speed-pending). |
@@ -203,7 +203,40 @@ gate → size (S/M/L) → vehicle model. `[H]` = user-directed headline.
     lever is CIQ `G5` (x86 AVX2/AVX-512 quant tier + an AVX-512 consumer for the
     `G7` repack), and a per-pool RSS attribution for the 6.33 MB.
     **The Metal/MLX half is untouched: it needs an Apple M4.**
-14. **`ROAD-V1-C2-LOCAL-BF16` device-resident sampled-token rerun** (small). **Size S.**
+14. **`ROAD-V1-C2-LOCAL-BF16` local 4B Pareto close** (small). **Size S.**
+    **The item's original W-plan — "port device-resident sampled-token mapping to
+    discrete CUDA (remove the measured main-stream wait) and rerun the exact 4B
+    series" — is SUPERSEDED, 2026-08-12
+    ([#527](https://github.com/mudler/vllm.cpp/issues/527)).** It was authored from
+    the 2026-07-25 `CLAIM-LOCAL-BF16-H32-AOT` checkpoint and never reconciled.
+    All three clauses are stale, and re-deriving that costs a fresh implementer a
+    session. (a) The **port landed `deed7c2a1` (2026-07-27)** — runner-owned device
+    `last_sampled`/`prefill_len`/`query_start_loc`/`seq_lens`/`input_ids` plus
+    `LaunchApplyLastSampledOps`, which replays our condense's structural row edits
+    on-device in stream order: exactly the asked-for compaction-safe device token
+    map. (b) It is **DEFAULT ON since `1718bf155` (2026-08-05)**, not opt-in:
+    `async_device_mirror()` (`src/vllm/v1/worker/gpu/runner.cpp:2430-2455`) engages
+    on any real CUDA GPU and names discrete first — *"the mirror is REQUIRED,
+    because the host fallback would main-stream Synchronize to read the sampled
+    ids"* — with `VT_ASYNC_DEVICE_MIRROR=0` the rollback. The `Synchronize` this
+    item asks to remove survives only on the non-CUDA host branch
+    (`runner.cpp:2687-2695`), where it is correct and required. (c) The **motivating
+    measurement is REFUTED by that same commit**: `vllm-bench` drives the synchronous
+    `LLMEngine::step()` loop, so `sample_tokens_async` never runs on the benchmarked
+    path and the 2026-07-25 attribution of 497 `cudaStreamSynchronize` (20.975 s,
+    42.20 ms/call) to it is wrong for this workload. (d) The 4B series has been
+    **rerun six times since** (`docs/bench-evidence/qwen35-4b-*` 0727/0728/0729/0803/
+    0805/0807); roadmap row 2a already carries the corrected three-repetition
+    cross-engine throughput **6831.71 vs 6643.40 tok/s (1.0283x PASS)** against the
+    0.9864x the stale cell quoted. The successor lever was also tried and
+    **rejected**: geometric argmax scratch migrated the wait and cost +1% TPOT
+    ([spec](sm120-qwen35-argmax-scratch-growth-2026-08-09.md)).
+    **Real remaining work** (roadmap row 2a + [campaign spec](sm120-qwen35-pareto-2026-08-09.md)
+    steps 3-5, neither of which mentions sampled tokens): same-tool `nsys
+    --cuda-graph-trace=node` interval profiling on both engines to split the residual
+    TTFT into intake vs prefill, then the largest attributable interval; TPOT/ITL
+    (1.0165x) and peak VRAM (+118.7 MiB) stay open; preserve the throughput stack.
+    Row stays `GATING`; no 4B-to-gate-model extrapolation.
 15. **`ROAD-V1-C1` fusion perf interpreter** (cornerstone done; perf tail,
     ≤3.5%/step ceiling). **Size M.** `FUSION-DENSE-MIGRATE` is CLOSED (2026-08-10,
     [#299](https://github.com/mudler/vllm.cpp/issues/299), spec
diff --git a/.agents/specs/sm120-qwen35-pareto-2026-08-09.md b/.agents/specs/sm120-qwen35-pareto-2026-08-09.md
index 2b9954d5e..509875a17 100644
--- a/.agents/specs/sm120-qwen35-pareto-2026-08-09.md
+++ b/.agents/specs/sm120-qwen35-pareto-2026-08-09.md
@@ -292,3 +292,48 @@ A local win stays explicit opt-in until it reproduces, passes fresh mutation
 review, and meets all local axes. No local 4B result grants a shared default or
 27B/35B release claim; those remain pending their named hardware gate. Never
 declare an unresolved gap a ceiling: record the next same-tool discriminator.
+
+## Record reconciliation (2026-08-12, [#527](https://github.com/mudler/vllm.cpp/issues/527))
+
+This campaign is the row's live plan, and it deliberately says nothing about
+sampled tokens. Three older records still directed the next owner of
+`ROAD-V1-C2-LOCAL-BF16` at a pre-campaign W-plan — "port device-resident
+sampled-token mapping to discrete CUDA (remove the measured main-stream wait)
+and rerun the exact 4B series" — carried forward unreconciled from the
+2026-07-25 `CLAIM-LOCAL-BF16-H32-AOT` checkpoint. They are now marked
+SUPERSEDED in place: `roadmap-v1-completion.md` §2 RI table and §3 punch-list
+item 14, `benchmark-record.md`'s `Host-weight ownership` key, and
+`coordination.md`'s 2026-07-25 bullet.
+
+The reconciliation is a records-only change; no `src/`, `include/` or `tests/`
+file moved and the row stays `GATING`. What git shows:
+
+- The compaction-safe device token map **landed `deed7c2a1` (2026-07-27)** —
+  runner-owned device `last_sampled` / `prefill_len` / `query_start_loc` /
+  `seq_lens` / `input_ids`, plus `LaunchApplyLastSampledOps` to replay our
+  condense's structural row edits on-device in stream order (upstream never
+  condenses; `states.py:132` frees slot indices into a pool).
+- It is **DEFAULT ON since `1718bf155` (2026-08-05)**, not opt-in.
+  `async_device_mirror()` (`src/vllm/v1/worker/gpu/runner.cpp:2430-2455`)
+  engages on any real CUDA GPU and names discrete first, because there the
+  host fallback would main-stream `Synchronize`. `VT_ASYNC_DEVICE_MIRROR=0`
+  is the rollback. The surviving `Synchronize` is the non-CUDA host branch
+  (`runner.cpp:2687-2695`), where it is correct and required.
+- The **motivating measurement is refuted by `deed7c2a1` itself**: `vllm-bench`
+  drives the synchronous `LLMEngine::step()` loop, which calls `sample_tokens()`,
+  so `sample_tokens_async` never runs on the benchmarked path and the 2026-07-25
+  attribution of 497 `cudaStreamSynchronize` (20.975 s, 42.20 ms/call) to it is
+  wrong for this workload. Those syncs remain **unattributed**, and re-attributing
+  them is step 3 of the Ordered campaign, not a separate lever.
+- The exact 4B series has been **rerun six times since** — `qwen35-4b-*`
+  `20260727`, `20260728`, `20260729`, `20260803`, `20260805`, `20260807` in
+  `docs/bench-evidence/` — and the throughput axis moved from **0.9864x** to
+  **1.0283x PASS** (6831.71 vs 6643.40 tok/s, three repetitions).
+- The successor lever on the same wait was tried and **rejected**: geometric
+  argmax scratch migrated the wait rather than removing it and cost +1% TPOT
+  ([spec](sm120-qwen35-argmax-scratch-growth-2026-08-09.md)).
+
+Open axes are unchanged by this reconciliation: TPOT/ITL **1.0165x** and peak
+VRAM **+118.7 MiB**. The next same-tool discriminator is Ordered-campaign
+step 3 — `nsys --cuda-graph-trace=node` on both engines over the identical
+workload, splitting the residual TTFT into intake versus prefill.
diff --git a/docs/BENCHMARKS.md b/docs/BENCHMARKS.md
index 4081d3638..85ef276b8 100644
--- a/docs/BENCHMARKS.md
+++ b/docs/BENCHMARKS.md
@@ -42,7 +42,7 @@ The binding comparison. vLLM runs its **production graphed config**, never
 | Qwen3.6-27B | NVFP4 (`nvidia` @`0893e160`, ModelOpt `modelopt_mixed`) | 0.25.0 | 0/6 | **BEHIND, uniformly 0.94x** on decode, flat c1-c32 (6-point, `gate_pass:false`); greedy continuation IDENTICAL to vLLM. Different model from the `unsloth` row (NVFP4 MLP + FP8 W8A8 tower) |
 | Qwen3.6-35B-A3B | NVFP4 `modelopt_mixed` | 0.25.0 | 2/18 | 3-rep grid 2026-08-05 @`1ea26427`: 0.93-1.03x (c4 wins), c16 0.93x. Both c16 levers A/B'd NEG: drain event -1.9%, mirror 0.999x. ★ probe found a prod async batch-1 greedy DEGENERATION bug the mirror fixes |
 | DeepSeek-V2-Lite | bf16 MLA | 0.25.0 | 4/25 | Attributed miss, row stays `ACTIVE` |
-| Qwen3.5-4B | bf16 direct-load | 0.26.0.dev0 | **1.0283x tput, `PENDING`** | OPEN: TTFT/TPOT/E2E 1.085/1.017/1.029x, VRAM +118.7 MiB ([data](bench-evidence/qwen35-4b-sm120-main-20260807.md)) |
+| Qwen3.5-4B | bf16 direct-load | 0.26.0.dev0 | **1.0283x tput, `PENDING`** | OPEN: TTFT/TPOT/E2E 1.085/1.017/1.029x, VRAM +118.7 MiB ([data](bench-evidence/qwen35-4b-sm120-main-20260807.md)). Next: both-engine TTFT intake/prefill split ([#527](https://github.com/mudler/vllm.cpp/issues/527)) |
 
 ### GDN prefill kernels by GPU
 
diff --git a/docs/STATUS.md b/docs/STATUS.md
index 96d4829ac..66431b993 100644
--- a/docs/STATUS.md
+++ b/docs/STATUS.md
@@ -91,7 +91,7 @@ token-for-token correctness against the pinned oracle.
 | Qwen3.6-27B (NVFP4) text generation | Correctness-complete; speed is CHECKPOINT-dependent | Token-exact GB10 on both. `unsloth` @`890bdef7` beats vLLM every c (1.007-1.045x), 115/124; `nvidia` @`0893e160` **flat 0.937-0.956 c1-c32** (#349; 0.838 void) |
 | Qwen3.6-35B-A3B (NVFP4, GDN MoE) | Correctness-complete; **canonical 0.918-0.972x c1-c32** @`348c265d` (first c16/c32) | Token-exact SYNC+ASYNC; `VT_ASYNC_DEVICE_MIRROR` ON fixes async batch-1 token-0 degeneration |
 | Qwen3 / Qwen2 dense (BF16) | Correctness-complete, speed-pending. Async-serving P0 FIXED (#323: the decode graph replayed stale HOST ids, now declines while the mirror is live; async 7/7 incl. Llama/Mistral/InternLM2) | Near-tie-robust token-exact vs vLLM (Qwen3-0.6B, Qwen3-4B); c1 effective parity, c8 decode residual. **Async device-mirror (`ROW-SERVE-ASYNC-DENSE-MIRROR`, `f9c969ae`): the #31 fix ported to the classic dense family, dgx-VERIFIED.** The shared dense `EmbedInto` (qwen3.cpp) raced the async combine's device input-ids write against a stale host upload → token-0 degeneration on the depth-2 AsyncLLM serving path (quant-independent). `EmbedInto` now consumes the device override published by `ForwardQwen3ForCausalLM`'s `DeviceTokenIdsScope` (27B-dense template); gate `test_qwen3_dense_async_serving` RED on `VT_ASYNC_DEVICE_MIRROR=0`, GREEN default, byte-identical mirror-off. dgx GB10: async gate RED→GREEN 0.6B+4B, SACRED 0.6B+4B 184/184 unchanged (byte-neutral sync path), memcheck 0 errors; Yi30/Qwen3-8B-MXFP4 default-config e2e coherent + 3/4 token-exact (p2 = oracle-ratified near-tie, gap 0.0000), closing the QUANT-CT-MXFP4 async-default residual. RESIDUAL: sibling InternLM2/Mistral/Llama scope one-liner; W4 bench RAN; FA2 GQA-swap default-ON, c2-c8 <1.0x. `FLASH-PTXAS` #82: codegen at PARITY (no ptxas lever); gap=engine context. **D1 (2026-07-31, `CLAIM-D1-BF16-MERGED-QKV`): the bf16 merged-QKV path (`Qwen3QkvMergeEnabled`/`VT_QWEN3_QKV_MERGE`) is now default-ON** — one `vt::MatmulBT` over the merged `[qdim+2kdim,H]` owner + a contiguous `vt::QkvSplit` (OLMo-2 exemplar), replacing three per-shard GEMMs. Bit-exact GEMM math (A/B unit `test_ops_qkv_merge` byte-identical, RED-first); the wider-N cuBLASLt K-reduction flips the 0.6B genuine bf16 near-tie so the SACRED 0.6B golden was regenerated (all tokens within the near-tie band, max 0.125 nats), while Qwen3-4B is byte-neutral (0 diffs, stays STRICT). Re-gated 0.6B 16/16 + 4B 16/16; consistency/launch-count fold (measured NEUTRAL on 4B decode), no new throughput owed |
-| Qwen3.5-4B BF16 direct-load on discrete CUDA | Correct; throughput/host PSS ahead, acceptance `PENDING`; latency/VRAM open | Atomic pretoken exact. Ratios: tput 1.0283x; TTFT/TPOT/E2E 1.0853/1.0165/1.0288x slower; VRAM +118.7 MiB. GDN local stack retained ([data](bench-evidence/qwen35-4b-sm120-main-20260807.md)) |
+| Qwen3.5-4B BF16 direct-load on discrete CUDA | Correct; throughput/host PSS ahead, acceptance `PENDING`; latency/VRAM open; sampled-token lever CLOSED, next is the TTFT intake/prefill split ([#527](https://github.com/mudler/vllm.cpp/issues/527)) | Atomic pretoken exact. Ratios: tput 1.0283x; TTFT/TPOT/E2E 1.0853/1.0165/1.0288x slower; VRAM +118.7 MiB. GDN local stack retained ([data](bench-evidence/qwen35-4b-sm120-main-20260807.md)) |
 | Qwen3-Coder-30B-A3B MoE (BF16) | Correctness-complete, speed-pending | Near-tie-robust token-exact 6/6; 11 of 16 binding grid cells at or above vLLM. **D1 (2026-07-31): inherits the default-ON bf16 merged-QKV via the shared dense `AttnBlock` — byte-neutral (0 token diffs, golden UNCHANGED); re-gated 6/6** |
 | Llama-3.x dense (BF16) | Correctness-complete, speed-pending | Near-tie-robust token-exact 16/16 (Llama-3.2-1B); llama3 RoPE scaling |
 | Mistral dense (BF16) | Correctness-complete, speed-pending | Paged-engine token-exact 16/16 (Mistral-7B-v0.3) |