Hello , there are some problems after using your source code and documentation.
1.The register address in the code is inconsistent with the register address assignment in the document.
The register data_event_enable address in the document needs to be modified to 0x40
The status bits of Data_event_status register are defined differently in the documentation and in the source code.
2、It is recommended to modify the default value of blocksize in the control register to 511, I used the FPGA to control the controller by default, resulting in an error in the CRC in the data0 feedback value after the block data is sent, and there is no CRC error after changing it to 511.
Hello , there are some problems after using your source code and documentation.
1.The register address in the code is inconsistent with the register address assignment in the document.
The register data_event_enable address in the document needs to be modified to 0x40
The status bits of Data_event_status register are defined differently in the documentation and in the source code.
2、It is recommended to modify the default value of blocksize in the control register to 511, I used the FPGA to control the controller by default, resulting in an error in the CRC in the data0 feedback value after the block data is sent, and there is no CRC error after changing it to 511.