i found when i add the generated clock constrain in the xilinx XDC file:
create_generated_clock -name sd_clk_ -source [get_pins {pcie3_ultrascale_0_support_i/pcie3_ultrascale_0_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O}] -divide_by 1 [get_pins {pcie_app_uscale_i/PIO_i/pio_ep/ep_mem/sdc_controller_u/clock_divider0/SD_CLK_O_reg/Q}]
ths sd card operation will timeout:
and then a invert the clock out (in "sd_controller.v"),it will fixed:
//assign sd_clk_o_pad = sd_clk_o ;
//will@20220916
assign sd_clk_o_pad = ~sd_clk_o ;
i think it is risk?
i found when i add the generated clock constrain in the xilinx XDC file:
ths sd card operation will timeout:
and then a invert the clock out (in "sd_controller.v"),it will fixed:
i think it is risk?