Emap - Arrival Time Assertion Triggered

[cowardsa]

Thanks for the great tool suite - really helpful in my research - hit this bug and wondered if anyone was still working on this.

Bug

mockturtle/include/mockturtle/algorithms/emap.hpp

Lines 1833 to 1836 in 420f027

	if ( node_data.map_refs[0] )
	assert( node_data.arrival[0] < node_data.required[0] + epsilon );
	if ( node_data.map_refs[1] )
	assert( node_data.arrival[1] < node_data.required[1] + epsilon );

emap assert failed at node 1232 phase 1: arrival=293.97 required=257.73

Assertion triggered when trying to perform technology mapping using the multioutput library provided in the experiments/cell_library -reproduction details below. Have hit this bug for lots of different designs, so not an isolated issue - but unable to reproduce it when looking at smaller designs i.e. 2-4 bit inputs.

Reproduction

Synthesized the following design:

module FmaSgn #(
    BW = 16
)
(
    input logic   signed [BW-1:0] a,
    input logic   signed [BW-1:0] b,
    input logic   signed [BW-1:0] c,
    output logic  signed [2*BW-1:0] res
);

assign res = a*b + c;   

endmodule

Using yosys command:
yosys -f verilog -p "read_verilog -sv <filename>; synth; aigmap; write_aiger <aig_file>"

Then fed to emap with multioutput library (ASAP7nm with 2 multi-output cells) and asserted.

[aletempiac]

Hi Samuel,

Sorry for the late reply. I can look into this. Could you share the parameter configuration of the tech_library and emap.

There is a known issue when the following happens: a gate is mapped to a full adder in the critical path, but then the carry out of the full adder is not connected in the mapping solution. Then, emap tries to switch the full adder for a single-output gate, but this might increase the delay and violating the required time, for instance, if a XOR3 cell is not available in the library.

Let me know if this is the case with the current library. I added an option to go around this problem. Try setting option of tech_library: load_multioutput_gates_single = true.
Else, you can add a placeholder XOR3 that can be then switched with another implementation "such as 2 XOR2 gates" later on.

Thanks,
Alessandro