Implementation of Cache

[egrath]

Hi, would it be possible to implement the cache controller of the Mega STe? There's a free implementation of a generic instruction-/data cache available, written in Verilog and based on Patterson-Henessy's description in "Computer Organization and Design". From my research, this is the same approach used in the generic cache controller ICs used for the various 68000 speeders that were available for the ST (like the ST Hyper Cache).

Currently there are around 380 Kbit of BRAM unused from which approximately 130 KBit could be used for the cache. I'm not sure if the implementation would fit in the remaining LEs. Maybe this could be implemented as a conditional module (e.g. have the cache module instead of the TG68K core to fit)

cache_controller_tb.v.txt
cache_controller.v.txt

(Original code from: https://electrobinary.blogspot.com/2021/05/cache-controller-design-verilog-code.html)

[egrath]

If this is at some point considered for implementation, it probably would be even better to "just" use the cache module from Minimig-AGA which also already includes the ability to do bus snooping if a DMA transfer occurs:

https://github.com/minimig-dev/MinimigAGA-MiST-TC64/blob/master/rtl/sdram/cpu_cache_new.v

[gyurco]

I'm not really planning to work on it (but maybe one day...), however I think the double bus speed used in place of the cache more or less makes it redundant.