From 4f8c5a432a632b8e9d0453e94a3b87c8ebf5a586 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 12 Nov 2024 14:09:29 +0100 Subject: [PATCH 01/85] modules/zstd/BUILD: increase pipeline_stages for DecoderMux proc Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 3ac0a4c322..0a973f2eac 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -504,7 +504,7 @@ xls_dslx_verilog( codegen_args = { "module_name": "DecoderMux", "delay_model": "asap7", - "pipeline_stages": "2", + "pipeline_stages": "3", "reset": "rst", "use_system_verilog": "false", }, @@ -518,7 +518,7 @@ xls_benchmark_ir( name = "dec_mux_opt_ir_benchmark", src = ":dec_mux_verilog.opt.ir", benchmark_ir_args = { - "pipeline_stages": "2", + "pipeline_stages": "10", "delay_model": "asap7", }, tags = ["manual"], From 4ca0a3fb51090c23757ca2cf938045aeb93febbf Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Oct 2024 15:59:05 +0200 Subject: [PATCH 02/85] modules/zstd: Remove MagicNumberDecoder Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 18 -------- xls/modules/zstd/magic.x | 89 ---------------------------------------- 2 files changed, 107 deletions(-) delete mode 100644 xls/modules/zstd/magic.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 0a973f2eac..6d85509278 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -128,23 +128,6 @@ place_and_route( target_die_utilization_percentage = "10", ) -xls_dslx_library( - name = "magic_dslx", - srcs = [ - "magic.x", - ], - deps = [ - ":buffer_dslx", - ], -) - -xls_dslx_test( - name = "magic_dslx_test", - dslx_test_args = {"compare": "jit"}, - library = ":magic_dslx", - tags = ["manual"], -) - cc_library( name = "data_generator", srcs = ["data_generator.cc"], @@ -947,7 +930,6 @@ xls_dslx_library( ":common_dslx", ":frame_header_dslx", ":frame_header_test_dslx", - ":magic_dslx", ":ram_printer_dslx", ":repacketizer_dslx", ":sequence_executor_dslx", diff --git a/xls/modules/zstd/magic.x b/xls/modules/zstd/magic.x deleted file mode 100644 index 196f2f528f..0000000000 --- a/xls/modules/zstd/magic.x +++ /dev/null @@ -1,89 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// This file contains utilities related to ZSTD magic number parsing -// More information about the ZSTD Magic Number can be found in: -// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1 - -import std; -import xls.modules.zstd.buffer as buff; - -type Buffer = buff::Buffer; -type BufferStatus = buff::BufferStatus; - -// Magic number value, as in: -// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1 -const MAGIC_NUMBER = u32:0xFD2FB528; - -// Status values reported by the magic number parsing function -pub enum MagicStatus: u2 { - OK = 0, - CORRUPTED = 1, - NO_ENOUGH_DATA = 2, -} - -// structure for returning results of magic number parsing -pub struct MagicResult { - buffer: Buffer, - status: MagicStatus, -} - -// Parses a Buffer and checks if it contains the magic number. -// The buffer is assumed to contain a valid beginning of the ZSTD file. -// The function returns MagicResult structure with the buffer after parsing -// the magic number and the status of the operation. On failure, the returned -// buffer is the same as the input buffer. -pub fn parse_magic_number(buffer: Buffer) -> MagicResult { - let (result, data) = buff::buffer_fixed_pop_checked(buffer); - - match result.status { - BufferStatus::OK => { - if data == MAGIC_NUMBER { - trace_fmt!("parse_magic_number: Magic number found!"); - MagicResult {status: MagicStatus::OK, buffer: result.buffer} - } else { - trace_fmt!("parse_magic_number: Magic number not found!"); - MagicResult {status: MagicStatus::CORRUPTED, buffer: buffer} - } - }, - _ => { - trace_fmt!("parse_frame_header: Not enough data to parse magic number!"); - MagicResult {status: MagicStatus::NO_ENOUGH_DATA, buffer: buffer} - } - } -} - -#[test] -fn test_parse_magic_number() { - let buffer = Buffer { content: MAGIC_NUMBER, length: u32:32}; - let result = parse_magic_number(buffer); - assert_eq(result, MagicResult { - status: MagicStatus::OK, - buffer: Buffer {content: u32:0, length: u32:0}, - }); - - let buffer = Buffer { content: u32:0x12345678, length: u32:32}; - let result = parse_magic_number(buffer); - assert_eq(result, MagicResult { - status: MagicStatus::CORRUPTED, - buffer: buffer - }); - - let buffer = Buffer { content: u32:0x1234, length: u32:16}; - let result = parse_magic_number(buffer); - assert_eq(result, MagicResult { - status: MagicStatus::NO_ENOUGH_DATA, - buffer: buffer, - }); -} From 7f003153ccfecccd9963666f092e1de06eb6c61b Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Oct 2024 16:07:13 +0200 Subject: [PATCH 03/85] modules/zstd: Remove BlockDecoder proc Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 90 ------------------- xls/modules/zstd/block_dec.x | 170 ----------------------------------- 2 files changed, 260 deletions(-) delete mode 100644 xls/modules/zstd/block_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 6d85509278..af281da3db 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -622,95 +622,6 @@ place_and_route( target_die_utilization_percentage = "5", ) -xls_dslx_library( - name = "block_dec_dslx", - srcs = [ - "block_dec.x", - ], - deps = [ - ":common_dslx", - ":dec_demux_dslx", - ":dec_mux_dslx", - ":raw_block_dec_dslx", - ":rle_block_dec_dslx", - ], -) - -xls_dslx_test( - name = "block_dec_dslx_test", - dslx_test_args = {"compare": "jit"}, - library = ":block_dec_dslx", - tags = ["manual"], -) - -xls_dslx_verilog( - name = "block_dec_verilog", - codegen_args = { - "module_name": "BlockDecoder", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "use_system_verilog": "false", - "fifo_module": "", - "materialize_internal_fifos": "true", - }, - dslx_top = "BlockDecoder", - library = ":block_dec_dslx", - opt_ir_args = { - "top": "__xls_modules_zstd_dec_mux__BlockDecoder__DecoderMux_0_next", - }, - tags = ["manual"], - verilog_file = "block_dec.v", -) - -xls_benchmark_ir( - name = "block_dec_opt_ir_benchmark", - src = ":block_dec_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - "fifo_module": "", - "materialize_internal_fifos": "true", - }, - tags = ["manual"], -) - -verilog_library( - name = "block_dec_verilog_lib", - srcs = [ - ":block_dec.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "block_dec_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "BlockDecoder", - deps = [ - ":block_dec_verilog_lib", - ], -) - -benchmark_synth( - name = "block_dec_benchmark_synth", - synth_target = ":block_dec_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "block_dec_place_and_route", - clock_period = "750", - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":block_dec_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "10", -) - xls_dslx_library( name = "ram_printer_dslx", srcs = ["ram_printer.x"], @@ -924,7 +835,6 @@ xls_dslx_library( "zstd_dec.x", ], deps = [ - ":block_dec_dslx", ":block_header_dslx", ":buffer_dslx", ":common_dslx", diff --git a/xls/modules/zstd/block_dec.x b/xls/modules/zstd/block_dec.x deleted file mode 100644 index f068a8e8b6..0000000000 --- a/xls/modules/zstd/block_dec.x +++ /dev/null @@ -1,170 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -import xls.modules.zstd.common; -import xls.modules.zstd.dec_demux as demux; -import xls.modules.zstd.raw_block_dec as raw; -import xls.modules.zstd.rle_block_dec as rle; -import xls.modules.zstd.dec_mux as mux; - -type BlockDataPacket = common::BlockDataPacket; -type BlockData = common::BlockData; -type BlockPacketLength = common::BlockPacketLength; -type ExtendedBlockDataPacket = common::ExtendedBlockDataPacket; -type CopyOrMatchContent = common::CopyOrMatchContent; -type CopyOrMatchLength = common::CopyOrMatchLength; -type SequenceExecutorPacket = common::SequenceExecutorPacket; -type SequenceExecutorMessageType = common::SequenceExecutorMessageType; - -// Proc responsible for connecting internal procs used in Block data decoding. -// It handles incoming block data packets by redirecting those to demuxer which passes those to -// block decoder procs specific for given block type. Results are then gathered by mux which -// transfers decoded data further. The connections are visualised on the following diagram: -// -// Block Decoder -// ┌───────────────────────────────────────┐ -// │ Raw Block Decoder │ -// │ ┌───────────────────┐ │ -// │ ┌─► ├┐ │ -// │ Demux │ └───────────────────┘│ Mux │ -// │┌─────┐│ Rle Block Decoder │ ┌─────┐│ -// ││ ├┘ ┌───────────────────┐└─► ││ -// ──┼► ├──► ├──► ├┼─► -// ││ ├┐ └───────────────────┘┌─► ││ -// │└─────┘│ Cmp Block Decoder │ └─────┘│ -// │ │ ┌───────────────────┐│ │ -// │ └─► ├┘ │ -// │ └───────────────────┘ │ -// └───────────────────────────────────────┘ - -pub proc BlockDecoder { - input_r: chan in; - output_s: chan out; - - config (input_r: chan in, output_s: chan out) { - let (demux_raw_s, demux_raw_r) = chan("demux_raw"); - let (demux_rle_s, demux_rle_r) = chan("demux_rle"); - let (demux_cmp_s, demux_cmp_r) = chan("demux_cmp"); - let (mux_raw_s, mux_raw_r) = chan("mux_raw"); - let (mux_rle_s, mux_rle_r) = chan("mux_rle"); - let (mux_cmp_s, mux_cmp_r) = chan("mux_cmp"); - - spawn demux::DecoderDemux(input_r, demux_raw_s, demux_rle_s, demux_cmp_s); - spawn raw::RawBlockDecoder(demux_raw_r, mux_raw_s); - spawn rle::RleBlockDecoder(demux_rle_r, mux_rle_s); - // TODO(antmicro): 2023-11-28 change to compressed block decoder proc - spawn raw::RawBlockDecoder(demux_cmp_r, mux_cmp_s); - spawn mux::DecoderMux(mux_raw_r, mux_rle_r, mux_cmp_r, output_s); - - (input_r, output_s) - } - - init { } - - next(state: ()) { } -} - -#[test_proc] -proc BlockDecoderTest { - terminator: chan out; - input_s: chan out; - output_r: chan in; - - init {} - - config (terminator: chan out) { - let (input_s, input_r) = chan("input"); - let (output_s, output_r) = chan("output"); - - spawn BlockDecoder(input_r, output_s); - - (terminator, input_s, output_r) - } - - next(state: ()) { - let tok = join(); - let EncodedDataBlocksPackets: BlockDataPacket[13] = [ - // RAW Block 1 byte - BlockDataPacket { id: u32:0, last: true, last_block: false, data: BlockData:0xDE000008, length: BlockPacketLength:32 }, - // RAW Block 2 bytes - BlockDataPacket { id: u32:1, last: true, last_block: false, data: BlockData:0xDEAD000010, length: BlockPacketLength:40 }, - // RAW Block 4 bytes - BlockDataPacket { id: u32:2, last: true, last_block: false, data: BlockData:0xDEADBEEF000020, length: BlockPacketLength:56 }, - // RAW Block 5 bytes (block header takes one full packet) - BlockDataPacket { id: u32:3, last: true, last_block: false, data: BlockData:0xDEADBEEFEF000028, length: BlockPacketLength:64 }, - // RAW Block 24 bytes (multi-packet block header with unaligned data in the last packet) - BlockDataPacket { id: u32:4, last: false, last_block: false, data: BlockData:0x12345678900000C0, length: BlockPacketLength:64 }, - BlockDataPacket { id: u32:4, last: false, last_block: false, data: BlockData:0x1234567890ABCDEF, length: BlockPacketLength:64 }, - BlockDataPacket { id: u32:4, last: false, last_block: false, data: BlockData:0xFEDCBA0987654321, length: BlockPacketLength:64 }, - BlockDataPacket { id: u32:4, last: true, last_block: false, data: BlockData:0xF0F0F0, length: BlockPacketLength:24 }, - - // RLE Block 1 byte - BlockDataPacket { id: u32:5, last: true, last_block: false, data: BlockData:0x6700000a, length: BlockPacketLength:32 }, - // RLE Block 2 bytes - BlockDataPacket { id: u32:6, last: true, last_block: false, data: BlockData:0x45000012, length: BlockPacketLength:32 }, - // RLE Block 4 bytes - BlockDataPacket { id: u32:7, last: true, last_block: false, data: BlockData:0x23000022, length: BlockPacketLength:32 }, - // RLE Block 8 bytes (block takes one full packet) - BlockDataPacket { id: u32:8, last: true, last_block: false, data: BlockData:0x10000042, length: BlockPacketLength:32 }, - // RLE Block 26 bytes (multi-packet block header with unaligned data in the last packet) - BlockDataPacket { id: u32:9, last: true, last_block: true, data: BlockData:0xDE0000d2, length: BlockPacketLength:32 }, - ]; - - let tok = for ((counter, block_packet), tok): ((u32, BlockDataPacket), token) in enumerate(EncodedDataBlocksPackets) { - let tok = send(tok, input_s, block_packet); - trace_fmt!("Sent #{} encoded block packet, {:#x}", counter + u32:1, block_packet); - (tok) - }(tok); - - let DecodedDataBlocksPackets: SequenceExecutorPacket[16] = [ - // RAW Block 1 byte - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDE, length: CopyOrMatchLength:8 }, - // RAW Block 2 bytes - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEAD, length: CopyOrMatchLength:16 }, - // RAW Block 4 bytes - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEADBEEF, length: CopyOrMatchLength:32 }, - // RAW Block 5 bytes (block header takes one full packet) - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEADBEEFEF, length: CopyOrMatchLength:40 }, - // RAW Block 24 bytes (multi-packet block header with unaligned data in the last packet) - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x1234567890, length: CopyOrMatchLength:40 }, - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x1234567890ABCDEF, length: CopyOrMatchLength:64 }, - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xFEDCBA0987654321, length: CopyOrMatchLength:64 }, - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xF0F0F0, length: CopyOrMatchLength:24 }, - - // RLE Block 1 byte - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x67, length: CopyOrMatchLength:8 }, - // RLE Block 2 bytes - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x4545, length: CopyOrMatchLength:16 }, - // RLE Block 4 bytes - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x23232323, length: CopyOrMatchLength:32 }, - // RLE Block 8 bytes (block takes one full packet) - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x1010101010101010, length: CopyOrMatchLength:64 }, - // RLE Block 26 bytes (multi-packet block header with unaligned data in the last packet) - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEDEDEDEDEDEDEDE, length: CopyOrMatchLength:64 }, - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEDEDEDEDEDEDEDE, length: CopyOrMatchLength:64 }, - SequenceExecutorPacket { last: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEDEDEDEDEDEDEDE, length: CopyOrMatchLength:64 }, - SequenceExecutorPacket { last: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDEDE, length: CopyOrMatchLength:16 }, - ]; - - let tok = for ((counter, expected_block_packet), tok): ((u32, SequenceExecutorPacket), token) in enumerate(DecodedDataBlocksPackets) { - let (tok, decoded_block_packet) = recv(tok, output_r); - trace_fmt!("Received #{} decoded block packet, data: 0x{:x}", counter + u32:1, decoded_block_packet); - trace_fmt!("Expected #{} decoded block packet, data: 0x{:x}", counter + u32:1, expected_block_packet); - assert_eq(decoded_block_packet, expected_block_packet); - (tok) - }(tok); - - send(tok, terminator, true); - } -} From 1a2863de786d07e7c1db6ac36c7a71a317d86398 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Oct 2024 16:09:42 +0200 Subject: [PATCH 04/85] modules/zstd: Remove DecDemux proc Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 79 ------------------------------------------ 1 file changed, 79 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index af281da3db..520e664be3 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -543,85 +543,6 @@ place_and_route( target_die_utilization_percentage = "10", ) -xls_dslx_library( - name = "dec_demux_dslx", - srcs = [ - "dec_demux.x", - ], - deps = [ - ":block_header_dslx", - ":common_dslx", - ], -) - -xls_dslx_test( - name = "dec_demux_dslx_test", - dslx_test_args = {"compare": "jit"}, - library = ":dec_demux_dslx", - tags = ["manual"], -) - -xls_dslx_verilog( - name = "dec_demux_verilog", - codegen_args = { - "module_name": "DecoderDemux", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "use_system_verilog": "false", - }, - dslx_top = "DecoderDemux", - library = ":dec_demux_dslx", - tags = ["manual"], - verilog_file = "dec_demux.v", -) - -xls_benchmark_ir( - name = "dec_demux_opt_ir_benchmark", - src = ":dec_demux_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, - tags = ["manual"], -) - -verilog_library( - name = "dec_demux_verilog_lib", - srcs = [ - ":dec_demux.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "dec_demux_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "DecoderDemux", - deps = [ - ":dec_demux_verilog_lib", - ], -) - -benchmark_synth( - name = "dec_demux_benchmark_synth", - synth_target = ":dec_demux_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "dec_demux_place_and_route", - clock_period = "750", - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":dec_demux_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "5", -) - xls_dslx_library( name = "ram_printer_dslx", srcs = ["ram_printer.x"], From bf6183d81219c6dd44858765179ad48589924e1b Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Thu, 3 Oct 2024 14:16:47 +0200 Subject: [PATCH 05/85] modules/zstd/block_header: Specify new type for the block size Signed-off-by: Maciej Torhan --- xls/modules/zstd/block_header.x | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/xls/modules/zstd/block_header.x b/xls/modules/zstd/block_header.x index 455b3295e1..a0b52491b8 100644 --- a/xls/modules/zstd/block_header.x +++ b/xls/modules/zstd/block_header.x @@ -23,6 +23,7 @@ import xls.modules.zstd.common as common; type Buffer = buff::Buffer; type BufferStatus = buff::BufferStatus; type BlockType = common::BlockType; +type BlockSize = common::BlockSize; // Status values reported by the block header parsing function pub enum BlockHeaderStatus: u2 { @@ -35,7 +36,7 @@ pub enum BlockHeaderStatus: u2 { pub struct BlockHeader { last: bool, btype: BlockType, - size: u21, + size: BlockSize, } // Structure for returning results of block header parsing @@ -86,7 +87,7 @@ fn test_parse_block_header() { let result = parse_block_header(buffer); assert_eq(result, BlockHeaderResult { status: BlockHeaderStatus::OK, - header: BlockHeader { last: u1:1, btype: BlockType::RAW, size: u21:0x1000 }, + header: BlockHeader { last: u1:1, btype: BlockType::RAW, size: BlockSize:0x1000 }, buffer: Buffer { content: u32:0, length: u32:0 } }); @@ -94,7 +95,7 @@ fn test_parse_block_header() { let result = parse_block_header(buffer); assert_eq(result, BlockHeaderResult { status: BlockHeaderStatus::OK, - header: BlockHeader { last: u1:0, btype: BlockType::RLE, size: u21:0x1234 }, + header: BlockHeader { last: u1:0, btype: BlockType::RLE, size: BlockSize:0x1234 }, buffer: Buffer { content: u32:0, length: u32:0 } }); From 9618166075421e9d7e4c39b7bd5eb3d7c7f7a0df Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Oct 2024 16:04:11 +0200 Subject: [PATCH 06/85] modules/zstd: Cleanup BlockHeader Remove references to buffer structs as those are not used anywhere Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 35 ++++++++++---------- xls/modules/zstd/block_header.x | 58 --------------------------------- 2 files changed, 17 insertions(+), 76 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 520e664be3..ab3befa0a2 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -280,6 +280,23 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "block_header_dslx", + srcs = [ + "block_header.x", + ], + deps = [ + ":common_dslx", + ], +) + +xls_dslx_test( + name = "block_header_dslx_test", + dslx_test_args = {"compare": "jit"}, + library = ":block_header_dslx", + tags = ["manual"], +) + xls_dslx_library( name = "raw_block_dec_dslx", srcs = [ @@ -447,24 +464,6 @@ place_and_route( target_die_utilization_percentage = "10", ) -xls_dslx_library( - name = "block_header_dslx", - srcs = [ - "block_header.x", - ], - deps = [ - ":buffer_dslx", - ":common_dslx", - ], -) - -xls_dslx_test( - name = "block_header_dslx_test", - dslx_test_args = {"compare": "jit"}, - library = ":block_header_dslx", - tags = ["manual"], -) - xls_dslx_library( name = "dec_mux_dslx", srcs = [ diff --git a/xls/modules/zstd/block_header.x b/xls/modules/zstd/block_header.x index a0b52491b8..9e8679a72d 100644 --- a/xls/modules/zstd/block_header.x +++ b/xls/modules/zstd/block_header.x @@ -17,11 +17,8 @@ // https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.2 import std; -import xls.modules.zstd.buffer as buff; import xls.modules.zstd.common as common; -type Buffer = buff::Buffer; -type BufferStatus = buff::BufferStatus; type BlockType = common::BlockType; type BlockSize = common::BlockSize; @@ -39,13 +36,6 @@ pub struct BlockHeader { size: BlockSize, } -// Structure for returning results of block header parsing -pub struct BlockHeaderResult { - buffer: Buffer, - status: BlockHeaderStatus, - header: BlockHeader, -} - // Auxiliary constant that can be used to initialize Proc's state // with empty FrameHeader, because `zero!` cannot be used in that context pub const ZERO_BLOCK_HEADER = zero!(); @@ -59,51 +49,3 @@ pub fn extract_block_header(data:u24) -> BlockHeader { last: data[0:1], } } - -// Parses a Buffer and extracts information from a Block_Header. Returns BufferResult -// with outcome of operations on buffer and information extracted from the Block_Header. -pub fn parse_block_header(buffer: Buffer) -> BlockHeaderResult { - let (result, data) = buff::buffer_fixed_pop_checked(buffer); - - match result.status { - BufferStatus::OK => { - let block_header = extract_block_header(data); - if (block_header.btype != BlockType::RESERVED) { - BlockHeaderResult {status: BlockHeaderStatus::OK, header: block_header, buffer: result.buffer} - } else { - BlockHeaderResult {status: BlockHeaderStatus::CORRUPTED, header: zero!(), buffer: buffer} - } - }, - _ => { - trace_fmt!("parse_block_header: Not enough data to parse block header! {}", buffer.length); - BlockHeaderResult {status: BlockHeaderStatus::NO_ENOUGH_DATA, header: zero!(), buffer: buffer} - } - } -} - -#[test] -fn test_parse_block_header() { - let buffer = Buffer { content: u32:0x8001 , length: u32:24}; - let result = parse_block_header(buffer); - assert_eq(result, BlockHeaderResult { - status: BlockHeaderStatus::OK, - header: BlockHeader { last: u1:1, btype: BlockType::RAW, size: BlockSize:0x1000 }, - buffer: Buffer { content: u32:0, length: u32:0 } - }); - - let buffer = Buffer { content: u32:0x91A2, length: u32:24}; - let result = parse_block_header(buffer); - assert_eq(result, BlockHeaderResult { - status: BlockHeaderStatus::OK, - header: BlockHeader { last: u1:0, btype: BlockType::RLE, size: BlockSize:0x1234 }, - buffer: Buffer { content: u32:0, length: u32:0 } - }); - - let buffer = Buffer { content: u32:0x001, length: u32:16}; - let result = parse_block_header(buffer); - assert_eq(result, BlockHeaderResult { - status: BlockHeaderStatus::NO_ENOUGH_DATA, - header: zero!(), - buffer: Buffer { content: u32:0x001, length: u32:16 } - }); -} From 49162f24c635bea21eee19755d37329455fd2d2a Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Wed, 9 Oct 2024 11:05:59 +0200 Subject: [PATCH 07/85] modules/zstd/BUILD: Introduce common codegen args Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 144 +++++++++++++++++++++-------------------- 1 file changed, 74 insertions(+), 70 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index ab3befa0a2..28fb70013c 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -33,6 +33,19 @@ package( licenses = ["notice"], ) +CLOCK_PERIOD_PS = "750" +# Clock periods for modules that exceed the 750ps critical path in IR benchmark + +common_codegen_args = { + "delay_model": "asap7", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + "clock_period_ps": CLOCK_PERIOD_PS, + "clock_margin_percent": "20", + "multi_proc": "true", +} + xls_dslx_library( name = "buffer_dslx", srcs = [ @@ -64,20 +77,17 @@ xls_dslx_test( tags = ["manual"], ) +window_buffer_codegen_args = common_codegen_args | { + "module_name": "WindowBuffer64", + "clock_period_ps": "0", + "pipeline_stages": "1", +} + xls_dslx_verilog( name = "window_buffer_verilog", - codegen_args = { - "module_name": "WindowBuffer64", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "use_system_verilog": "false", - }, + codegen_args = window_buffer_codegen_args, dslx_top = "WindowBuffer64", library = ":window_buffer_dslx", - opt_ir_args = { - "top": "__window_buffer__WindowBuffer64__WindowBuffer_0__64_32_48_next", - }, tags = ["manual"], verilog_file = "window_buffer.v", ) @@ -85,9 +95,9 @@ xls_dslx_verilog( xls_benchmark_ir( name = "window_buffer_opt_ir_benchmark", src = ":window_buffer_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", + benchmark_ir_args = window_buffer_codegen_args | { + "pipeline_stages": "10", + "top": "__window_buffer__WindowBuffer64__WindowBuffer_0__64_32_48_next", }, tags = ["manual"], ) @@ -118,7 +128,7 @@ benchmark_synth( place_and_route( name = "window_buffer_place_and_route", - clock_period = "750", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", @@ -481,15 +491,15 @@ xls_dslx_test( tags = ["manual"], ) +dec_mux_codegen_args = common_codegen_args | { + "module_name": "DecoderMux", + "clock_period_ps": "0", + "pipeline_stages": "3", +} + xls_dslx_verilog( name = "dec_mux_verilog", - codegen_args = { - "module_name": "DecoderMux", - "delay_model": "asap7", - "pipeline_stages": "3", - "reset": "rst", - "use_system_verilog": "false", - }, + codegen_args = dec_mux_codegen_args, dslx_top = "DecoderMux", library = ":dec_mux_dslx", tags = ["manual"], @@ -499,9 +509,8 @@ xls_dslx_verilog( xls_benchmark_ir( name = "dec_mux_opt_ir_benchmark", src = ":dec_mux_verilog.opt.ir", - benchmark_ir_args = { + benchmark_ir_args = dec_mux_codegen_args | { "pipeline_stages": "10", - "delay_model": "asap7", }, tags = ["manual"], ) @@ -532,7 +541,7 @@ benchmark_synth( place_and_route( name = "dec_mux_place_and_route", - clock_period = "750", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", @@ -578,36 +587,35 @@ xls_dslx_test( tags = ["manual"], ) +sequence_executor_codegen_args = common_codegen_args | { + "module_name": "sequence_executor", + "clock_period_ps": "0", + "generator": "pipeline", + "delay_model": "asap7", + "ram_configurations": ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram{}".format(num), + rd_req = "sequence_executor__rd_req_m{}_s".format(num), + rd_resp = "sequence_executor__rd_resp_m{}_r".format(num), + wr_req = "sequence_executor__wr_req_m{}_s".format(num), + wr_resp = "sequence_executor__wr_resp_m{}_r".format(num), + ) + for num in range(7) + ]), + "pipeline_stages": "6", + "reset": "rst", + "reset_data_path": "true", + "reset_active_low": "false", + "reset_asynchronous": "true", + "flop_inputs": "false", + "flop_single_value_channels": "false", + "flop_outputs": "false", +} + xls_dslx_verilog( name = "sequence_executor_verilog", - codegen_args = { - "module_name": "sequence_executor", - "generator": "pipeline", - "delay_model": "asap7", - "ram_configurations": ",".join([ - "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, - ram_name = "ram{}".format(num), - rd_req = "sequence_executor__rd_req_m{}_s".format(num), - rd_resp = "sequence_executor__rd_resp_m{}_r".format(num), - wr_req = "sequence_executor__wr_req_m{}_s".format(num), - wr_resp = "sequence_executor__wr_resp_m{}_r".format(num), - ) - for num in range(7) - ]), - "pipeline_stages": "8", - "reset": "rst", - "reset_data_path": "true", - "reset_active_low": "false", - "reset_asynchronous": "true", - "flop_inputs": "false", - "flop_single_value_channels": "false", - "flop_outputs": "false", - "worst_case_throughput": "1", - "use_system_verilog": "false", - "fifo_module": "", - "materialize_internal_fifos": "true", - }, + codegen_args = sequence_executor_codegen_args, dslx_top = "SequenceExecutorZstd", library = ":sequence_executor_dslx", opt_ir_args = { @@ -618,13 +626,10 @@ xls_dslx_verilog( ) xls_benchmark_ir( - name = "sequence_executor_ir_benchmark", + name = "sequence_executor_opt_ir_benchmark", src = ":sequence_executor_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "8", - "delay_model": "asap7", - "fifo_module": "", - "materialize_internal_fifos": "true", + benchmark_ir_args = sequence_executor_codegen_args | { + "pipeline_stages": "10", }, tags = ["manual"], ) @@ -661,7 +666,7 @@ benchmark_synth( place_and_route( name = "sequence_executor_place_and_route", - clock_period = "750", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.4", placement_density = "0.30", @@ -688,15 +693,15 @@ xls_dslx_test( tags = ["manual"], ) +repacketizer_codegen_args = common_codegen_args | { + "module_name": "Repacketizer", + "clock_period_ps": "0", + "pipeline_stages": "2", +} + xls_dslx_verilog( name = "repacketizer_verilog", - codegen_args = { - "module_name": "Repacketizer", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "use_system_verilog": "false", - }, + codegen_args = repacketizer_codegen_args, dslx_top = "Repacketizer", library = ":repacketizer_dslx", tags = ["manual"], @@ -706,9 +711,8 @@ xls_dslx_verilog( xls_benchmark_ir( name = "repacketizer_opt_ir_benchmark", src = ":repacketizer_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", + benchmark_ir_args = repacketizer_codegen_args | { + "pipeline_stages": "10", }, tags = ["manual"], ) @@ -739,7 +743,7 @@ benchmark_synth( place_and_route( name = "repacketizer_place_and_route", - clock_period = "750", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", From 5b883286d46da177a9442a66c20e5a93ced2d8ab Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Oct 2024 17:41:55 +0200 Subject: [PATCH 08/85] modules/zstd: Add AxiCsrAccessor Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 77 ++++++ xls/modules/zstd/axi_csr_accessor.x | 384 ++++++++++++++++++++++++++++ 2 files changed, 461 insertions(+) create mode 100644 xls/modules/zstd/axi_csr_accessor.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 28fb70013c..f769fb4078 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -898,3 +898,80 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "axi_csr_accessor_dslx", + srcs = [ + "axi_csr_accessor.x", + ], + deps = [ + ":csr_config_dslx", + "//xls/modules/zstd/memory:axi_dslx", + ], +) + +xls_dslx_test( + name = "axi_csr_accessor_dslx_test", + library = ":axi_csr_accessor_dslx", + tags = ["manual"], +) + +axi_csr_accessor_codegen_args = common_codegen_args | { + "module_name": "AxiCsrAccessor", + "pipeline_stages": "1", +} + +xls_dslx_verilog( + name = "axi_csr_accessor_verilog", + codegen_args = axi_csr_accessor_codegen_args, + dslx_top = "AxiCsrAccessorInst", + library = ":axi_csr_accessor_dslx", + tags = ["manual"], + verilog_file = "axi_csr_accessor.v", +) + +xls_benchmark_ir( + name = "axi_csr_accessor_opt_ir_benchmark", + src = ":axi_csr_accessor_verilog.opt.ir", + benchmark_ir_args = axi_csr_accessor_codegen_args | { + "pipeline_stages": "10", + "top": "__axi_csr_accessor__AxiCsrAccessorInst__AxiCsrAccessor_0__16_32_4_4_2_4_16_next", + }, + tags = ["manual"], +) + +verilog_library( + name = "axi_csr_accessor_verilog_lib", + srcs = [ + ":axi_csr_accessor.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "axi_csr_accessor_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "AxiCsrAccessor", + deps = [ + ":axi_csr_accessor_verilog_lib", + ], +) + +benchmark_synth( + name = "axi_csr_accessor_benchmark_synth", + synth_target = ":axi_csr_accessor_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "axi_csr_accessor_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":axi_csr_accessor_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) diff --git a/xls/modules/zstd/axi_csr_accessor.x b/xls/modules/zstd/axi_csr_accessor.x new file mode 100644 index 0000000000..01cef68cd9 --- /dev/null +++ b/xls/modules/zstd/axi_csr_accessor.x @@ -0,0 +1,384 @@ +// Copyright 2023-2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains implementation of a proc that handles CSRs. It provides +// an AXI interface for reading and writing the values as well as separate +// request/response channels. Apart from that it has an output channel which +// notifies aboud changes made to CSRs. + +import std; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.csr_config; + + +struct AxiCsrAccessorState { + w_id: uN[ID_W], + w_addr: uN[ADDR_W], + r_id: uN[ID_W], + r_addr: uN[ADDR_W], +} + +pub proc AxiCsrAccessor< + ID_W: u32, ADDR_W: u32, DATA_W: u32, REGS_N: u32, + DATA_W_DIV8: u32 = { DATA_W / u32:8 }, + LOG2_REGS_N: u32 = { std::clog2(REGS_N) }, + LOG2_DATA_W_DIV8: u32 = { std::clog2(DATA_W / u32:8) }, +> { + type AxiAw = axi::AxiAw; + type AxiW = axi::AxiW; + type AxiB = axi::AxiB; + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; + + type RdReq = csr_config::CsrRdReq; + type RdResp = csr_config::CsrRdResp; + type WrReq = csr_config::CsrWrReq; + type WrResp = csr_config::CsrWrResp; + + type State = AxiCsrAccessorState; + type Data = uN[DATA_W]; + type RegN = uN[LOG2_REGS_N]; + + axi_aw_r: chan in; + axi_w_r: chan in; + axi_b_s: chan out; + axi_ar_r: chan in; + axi_r_s: chan out; + + csr_rd_req_s: chan out; + csr_rd_resp_r: chan in; + csr_wr_req_s: chan out; + csr_wr_resp_r: chan in; + + config ( + axi_aw_r: chan in, + axi_w_r: chan in, + axi_b_s: chan out, + axi_ar_r: chan in, + axi_r_s: chan out, + + csr_rd_req_s: chan out, + csr_rd_resp_r: chan in, + csr_wr_req_s: chan out, + csr_wr_resp_r: chan in, + ) { + ( + axi_aw_r, axi_w_r, axi_b_s, + axi_ar_r, axi_r_s, + csr_rd_req_s, csr_rd_resp_r, + csr_wr_req_s, csr_wr_resp_r, + ) + } + + init { + zero!() + } + + next (state: State) { + let tok_0 = join(); + // write to CSR via AXI + let (tok_1_1, axi_aw, axi_aw_valid) = recv_non_blocking(tok_0, axi_aw_r, AxiAw {id: state.w_id, addr: state.w_addr, ..zero!()}); + + // validate axi aw + assert!(!(axi_aw_valid && axi_aw.addr as u32 >= REGS_N), "invalid_aw_addr"); + assert!(!(axi_aw_valid && axi_aw.len != u8:0), "invalid_aw_len"); + + let (tok_1_2, axi_w, axi_w_valid) = recv_non_blocking(tok_1_1, axi_w_r, zero!()); + + // Send WriteRequest to CSRs + let data_w = if axi_w_valid { + let (w_data, _, _) = for (i, (w_data, strb, mask)): (u32, (uN[DATA_W], uN[DATA_W_DIV8], uN[DATA_W])) in range(u32:0, DATA_W_DIV8) { + let w_data = if axi_w.strb as u1 { + w_data | (axi_w.data & mask) + } else { + w_data + }; + ( + w_data, + strb >> u32:1, + mask << u32:8, + ) + }((uN[DATA_W]:0, axi_w.strb, uN[DATA_W]:0xFF)); + w_data + } else { + uN[DATA_W]:0 + }; + + let wr_req = WrReq { + csr: (axi_aw.addr >> LOG2_DATA_W_DIV8) as uN[LOG2_REGS_N], + value: data_w + }; + + let tok_1_3 = send_if(tok_1_2, csr_wr_req_s, axi_w_valid, wr_req); + + let (tok_2_1, csr_wr_resp, csr_wr_resp_valid) = recv_non_blocking(tok_0, csr_wr_resp_r, zero!()); + let axi_write_resp = AxiB { + resp: axi::AxiWriteResp::OKAY, + id: axi_aw.id, + }; + let tok_2_2 = send_if(tok_2_1, axi_b_s, csr_wr_resp_valid, axi_write_resp); + + + // Send ReadRequest to CSRs + let (tok_3_1, axi_ar, axi_ar_valid) = recv_non_blocking(tok_0, axi_ar_r, AxiAr {id: state.r_id, addr: state.r_addr, ..zero!()}); + // validate ar bundle + assert!(!(axi_ar_valid && axi_ar.addr as u32 >= REGS_N), "invalid_ar_addr"); + assert!(!(axi_ar_valid && axi_ar.len != u8:0), "invalid_ar_len"); + let rd_req = RdReq { + csr: (axi_ar.addr >> LOG2_DATA_W_DIV8) as uN[LOG2_REGS_N], + }; + let tok_3_2 = send_if(tok_3_1, csr_rd_req_s, axi_ar_valid, rd_req); + + let (tok_4_1, csr_rd_resp, csr_rd_resp_valid) = recv_non_blocking(tok_0, csr_rd_resp_r, zero!()); + + let axi_read_resp = AxiR { + id: axi_ar.id, + data: csr_rd_resp.value, + resp: axi::AxiReadResp::OKAY, + last: true, + }; + let tok_4_2 = send_if(tok_4_1, axi_r_s, csr_rd_resp_valid, axi_read_resp); + + State { + w_id: axi_aw.id, + w_addr: axi_aw.addr, + r_id: axi_ar.id, + r_addr: axi_ar.addr, + } + } +} + +const INST_ID_W = u32:4; +const INST_DATA_W = u32:32; +const INST_ADDR_W = u32:16; +const INST_REGS_N = u32:16; +const INST_DATA_W_DIV8 = INST_DATA_W / u32:8; +const INST_LOG2_REGS_N = std::clog2(INST_REGS_N); + +proc AxiCsrAccessorInst { + type InstAxiAw = axi::AxiAw; + type InstAxiW = axi::AxiW; + type InstAxiB = axi::AxiB; + type InstAxiAr = axi::AxiAr; + type InstAxiR = axi::AxiR; + + type InstCsrRdReq = csr_config::CsrRdReq; + type InstCsrRdResp = csr_config::CsrRdResp; + type InstCsrWrReq = csr_config::CsrWrReq; + type InstCsrWrResp = csr_config::CsrWrResp; + type InstCsrChange = csr_config::CsrChange; + + config( + axi_aw_r: chan in, + axi_w_r: chan in, + axi_b_s: chan out, + axi_ar_r: chan in, + axi_r_s: chan out, + + + csr_rd_req_s: chan out, + csr_rd_resp_r: chan in, + csr_wr_req_s: chan out, + csr_wr_resp_r: chan in, + ) { + spawn AxiCsrAccessor ( + axi_aw_r, axi_w_r, axi_b_s, + axi_ar_r, axi_r_s, + csr_rd_req_s, csr_rd_resp_r, + csr_wr_req_s, csr_wr_resp_r, + ); + } + + init { } + + next (state: ()) { } +} + +const TEST_ID_W = u32:4; +const TEST_DATA_W = u32:32; +const TEST_ADDR_W = u32:16; +const TEST_REGS_N = u32:16; +const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; +const TEST_LOG2_REGS_N = std::clog2(TEST_REGS_N); +const TEST_LOG2_DATA_W_DIV8 = std::clog2(TEST_DATA_W_DIV8); + +type TestCsr = uN[TEST_LOG2_REGS_N]; +type TestValue = uN[TEST_DATA_W]; + +struct TestData { + csr: uN[TEST_LOG2_REGS_N], + value: uN[TEST_DATA_W], +} + +const TEST_DATA = TestData[20]:[ + TestData{ csr: TestCsr:0, value: TestValue:0xca32_9f4a }, + TestData{ csr: TestCsr:1, value: TestValue:0x0fb3_fa42 }, + TestData{ csr: TestCsr:2, value: TestValue:0xe7ee_da41 }, + TestData{ csr: TestCsr:3, value: TestValue:0xef51_f98c }, + TestData{ csr: TestCsr:0, value: TestValue:0x97a3_a2d2 }, + TestData{ csr: TestCsr:0, value: TestValue:0xea06_e94b }, + TestData{ csr: TestCsr:1, value: TestValue:0x5fac_17ce }, + TestData{ csr: TestCsr:3, value: TestValue:0xf9d8_9938 }, + TestData{ csr: TestCsr:2, value: TestValue:0xc262_2d2e }, + TestData{ csr: TestCsr:2, value: TestValue:0xb4dd_424e }, + TestData{ csr: TestCsr:1, value: TestValue:0x01f9_b9e4 }, + TestData{ csr: TestCsr:1, value: TestValue:0x3020_6eec }, + TestData{ csr: TestCsr:3, value: TestValue:0x3124_87b5 }, + TestData{ csr: TestCsr:0, value: TestValue:0x0a49_f5e3 }, + TestData{ csr: TestCsr:2, value: TestValue:0xde3b_5d0f }, + TestData{ csr: TestCsr:3, value: TestValue:0x5948_c1b3 }, + TestData{ csr: TestCsr:0, value: TestValue:0xa26d_851f }, + TestData{ csr: TestCsr:3, value: TestValue:0x3fa9_59c0 }, + TestData{ csr: TestCsr:1, value: TestValue:0x4efd_dd09 }, + TestData{ csr: TestCsr:1, value: TestValue:0x6d75_058a }, +]; + +#[test_proc] +proc AxiCsrAccessorTest { + type TestAxiAw = axi::AxiAw; + type TestAxiW = axi::AxiW; + type TestAxiB = axi::AxiB; + type TestAxiAr = axi::AxiAr; + type TestAxiR = axi::AxiR; + + + type TestCsrRdReq = csr_config::CsrRdReq; + type TestCsrRdResp = csr_config::CsrRdResp; + type TestCsrWrReq = csr_config::CsrWrReq; + type TestCsrWrResp = csr_config::CsrWrResp; + type TestCsrChange = csr_config::CsrChange; + + terminator: chan out; + + axi_aw_s: chan out; + axi_w_s: chan out; + axi_b_r: chan in; + axi_ar_s: chan out; + axi_r_r: chan in; + + csr_rd_req_r: chan in; + csr_rd_resp_s: chan out; + csr_wr_req_r: chan in; + csr_wr_resp_s: chan out; + + config (terminator: chan out) { + let (axi_aw_s, axi_aw_r) = chan("axi_aw"); + let (axi_w_s, axi_w_r) = chan("axi_w"); + let (axi_b_s, axi_b_r) = chan("axi_b"); + let (axi_ar_s, axi_ar_r) = chan("axi_ar"); + let (axi_r_s, axi_r_r) = chan("axi_r"); + + let (csr_rd_req_s, csr_rd_req_r) = chan("csr_rd_req"); + let (csr_rd_resp_s, csr_rd_resp_r) = chan("csr_rd_resp"); + + let (csr_wr_req_s, csr_wr_req_r) = chan("csr_wr_req"); + let (csr_wr_resp_s, csr_wr_resp_r) = chan("csr_wr_resp"); + + spawn AxiCsrAccessor ( + axi_aw_r, axi_w_r, axi_b_s, + axi_ar_r, axi_r_s, + csr_rd_req_s, csr_rd_resp_r, + csr_wr_req_s, csr_wr_resp_r, + ); + + ( + terminator, + axi_aw_s, axi_w_s, axi_b_r, + axi_ar_s, axi_r_r, + csr_rd_req_r, csr_rd_resp_s, + csr_wr_req_r, csr_wr_resp_s, + ) + } + + init { } + + next (state: ()) { + // test writing via AXI + let tok = for ((i, test_data), tok): ((u32, TestData), token) in enumerate(TEST_DATA) { + // write CSR via AXI + let axi_aw = TestAxiAw { + id: i as uN[TEST_ID_W], + addr: (test_data.csr << TEST_LOG2_DATA_W_DIV8) as uN[TEST_ADDR_W], + size: axi::AxiAxSize::MAX_4B_TRANSFER, + len: u8:0, + burst: axi::AxiAxBurst::FIXED, + }; + let tok = send(tok, axi_aw_s, axi_aw); + trace_fmt!("Sent #{} AXI AW: {:#x}", i + u32:1, axi_aw); + + let axi_w = TestAxiW { + data: test_data.value, + strb: !uN[TEST_DATA_W_DIV8]:0, + last: true, + }; + let tok = send(tok, axi_w_s, axi_w); + trace_fmt!("Sent #{} AXI W: {:#x}", i + u32:1, axi_w); + + let expected_wr_req = TestCsrWrReq { + csr: test_data.csr, + value: test_data.value + }; + let (tok, wr_req) = recv(tok, csr_wr_req_r); + trace_fmt!("Received #{} CSR WriteRequest: {:#x}", i + u32:1, wr_req); + assert_eq(expected_wr_req, wr_req); + + let tok = send(tok, csr_wr_resp_s, TestCsrWrResp{}); + trace_fmt!("Sent #{} CsrWrResp", i + u32:1); + let (tok, axi_b) = recv(tok, axi_b_r); + trace_fmt!("Received #{} AXI B: {:#x}", i + u32:1, axi_b); + let expected_axi_resp = TestAxiB{ + resp: axi::AxiWriteResp::OKAY, + id: i as uN[TEST_ID_W], + }; + assert_eq(expected_axi_resp, axi_b); + + // read CSRs via AXI + let axi_ar = TestAxiAr { + id: i as uN[TEST_ID_W], + addr: (test_data.csr << TEST_LOG2_DATA_W_DIV8) as uN[TEST_ADDR_W], + len: u8:0, + ..zero!() + }; + let tok = send(tok, axi_ar_s, axi_ar); + trace_fmt!("Sent #{} AXI AR: {:#x}", i + u32:1, axi_ar); + + let expected_rd_req = TestCsrRdReq { + csr: test_data.csr, + }; + let (tok, rd_req) = recv(tok, csr_rd_req_r); + trace_fmt!("Received #{} CSR ReadRequest: {:#x}", i + u32:1, rd_req); + assert_eq(expected_rd_req, rd_req); + let rd_resp = TestCsrRdResp { + csr: test_data.csr, + value: test_data.value + }; + let tok = send(tok, csr_rd_resp_s, rd_resp); + trace_fmt!("Sent #{} CsrRdResp: {:#x}", i + u32:1, rd_resp); + + let (tok, axi_r) = recv(tok, axi_r_r); + trace_fmt!("Received #{} AXI R: {:#x}", i + u32:1, axi_r); + let expected_axi_rd_resp = TestAxiR{ + id: i as uN[TEST_ID_W], + data: test_data.value, + resp: axi::AxiReadResp::OKAY, + last: true, + }; + assert_eq(expected_axi_rd_resp, axi_r); + + tok + }(join()); + + send(tok, terminator, true); + } +} From 579bfe48cd3520514d065f41b9a86dbb3fe95784 Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Tue, 8 Oct 2024 17:49:59 +0200 Subject: [PATCH 09/85] modules/zstd: Add CsrConfig Co-authored-by: Pawel Czarnecki Co-authored-by: Robert Winkler Signed-off-by: Maciej Torhan Signed-off-by: Pawel Czarnecki Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 76 +++++++ xls/modules/zstd/csr_config.x | 397 ++++++++++++++++++++++++++++++++++ 2 files changed, 473 insertions(+) create mode 100644 xls/modules/zstd/csr_config.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index f769fb4078..b717e7be96 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -975,3 +975,79 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "csr_config_dslx", + srcs = [ + "csr_config.x", + ], + deps = [ + "//xls/modules/zstd/memory:axi_dslx", + ], +) + +xls_dslx_test( + name = "csr_config_dslx_test", + library = ":csr_config_dslx", + tags = ["manual"], +) + +csr_config_codegen_args = common_codegen_args | { + "module_name": "CsrConfig", + "pipeline_stages": "3", +} + +xls_dslx_verilog( + name = "csr_config_verilog", + codegen_args = csr_config_codegen_args, + dslx_top = "CsrConfigInst", + library = ":csr_config_dslx", + tags = ["manual"], + verilog_file = "csr_config.v", +) + +xls_benchmark_ir( + name = "csr_config_opt_ir_benchmark", + src = ":csr_config_verilog.opt.ir", + benchmark_ir_args = csr_config_codegen_args | { + "pipeline_stages": "10", + "top": "__csr_config__CsrConfigInst__CsrConfig_0__2_32_4_32_2_4_next", + }, + tags = ["manual"], +) + +verilog_library( + name = "csr_config_verilog_lib", + srcs = [ + ":csr_config.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "csr_config_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "CsrConfig", + deps = [ + ":csr_config_verilog_lib", + ], +) + +benchmark_synth( + name = "csr_config_benchmark_synth", + synth_target = ":csr_config_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "csr_config_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":csr_config_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) diff --git a/xls/modules/zstd/csr_config.x b/xls/modules/zstd/csr_config.x new file mode 100644 index 0000000000..a792757cfa --- /dev/null +++ b/xls/modules/zstd/csr_config.x @@ -0,0 +1,397 @@ +// Copyright 2023-2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains implementation of a proc that handles CSRs. It provides +// an AXI interface for reading and writing the values as well as separate +// request/response channels. Apart from that it has an output channel which +// notifies aboud changes made to CSRs. + +import std; +import xls.modules.zstd.memory.axi; + +pub struct CsrRdReq { + csr: uN[LOG2_REGS_N], +} + +pub struct CsrRdResp { + csr: uN[LOG2_REGS_N], + value: uN[DATA_W], +} + +pub struct CsrWrReq { + csr: uN[LOG2_REGS_N], + value: uN[DATA_W], +} + +pub struct CsrWrResp { } + +pub struct CsrChange { + csr: uN[LOG2_REGS_N], +} + +struct CsrConfigState { + register_file: uN[DATA_W][REGS_N], +} + +pub proc CsrConfig< + ID_W: u32, ADDR_W: u32, DATA_W: u32, REGS_N: u32, + //REGS_INIT: u64[64] = {u64[64]:[u64:0, ...]}, + DATA_W_DIV8: u32 = { DATA_W / u32:8 }, + LOG2_REGS_N: u32 = { std::clog2(REGS_N) }, +> { + + type RdReq = CsrRdReq; + type RdResp = CsrRdResp; + type WrReq = CsrWrReq; + type WrResp = CsrWrResp; + type Change = CsrChange; + + type State = CsrConfigState; + type Data = uN[DATA_W]; + type RegN = uN[LOG2_REGS_N]; + + ext_csr_rd_req_r: chan in; + ext_csr_rd_resp_s: chan out; + ext_csr_wr_req_r: chan in; + ext_csr_wr_resp_s: chan out; + + csr_rd_req_r: chan in; + csr_rd_resp_s: chan out; + csr_wr_req_r: chan in; + csr_wr_resp_s: chan out; + + csr_change_s: chan out; + + config ( + ext_csr_rd_req_r: chan in, + ext_csr_rd_resp_s: chan out, + ext_csr_wr_req_r: chan in, + ext_csr_wr_resp_s: chan out, + + csr_rd_req_r: chan in, + csr_rd_resp_s: chan out, + csr_wr_req_r: chan in, + csr_wr_resp_s: chan out, + csr_change_s: chan out, + ) { + ( + ext_csr_rd_req_r, ext_csr_rd_resp_s, + ext_csr_wr_req_r, ext_csr_wr_resp_s, + csr_rd_req_r, csr_rd_resp_s, + csr_wr_req_r, csr_wr_resp_s, + csr_change_s, + ) + } + + init { + zero!() + } + + next (state: State) { + let register_file = state.register_file; + + let tok_0 = join(); + + // write to CSR + let (tok_1_1_1, ext_csr_wr_req, ext_csr_wr_req_valid) = recv_non_blocking(tok_0, ext_csr_wr_req_r, zero!()); + let (tok_1_1_2, csr_wr_req, csr_wr_req_valid) = recv_non_blocking(tok_0, csr_wr_req_r, zero!()); + + // Mux the Write Requests from External and Internal sources + // Write requests from external source take precedence before internal writes + let wr_req = if (ext_csr_wr_req_valid) { + ext_csr_wr_req + } else if {csr_wr_req_valid} { + csr_wr_req + } else { + zero!() + }; + + let wr_req_valid = ext_csr_wr_req_valid | csr_wr_req_valid; + + let register_file = if wr_req_valid { + update(register_file, wr_req.csr as u32, wr_req.value) + } else { + register_file + }; + + // Send Write Response + let tok_1_1 = join(tok_1_1_1, tok_1_1_2); + let tok_1_2_1 = send_if(tok_1_1, ext_csr_wr_resp_s, ext_csr_wr_req_valid, WrResp {}); + let tok_1_2_2 = send_if(tok_1_1, csr_wr_resp_s, csr_wr_req_valid, WrResp {}); + + // Send change notification + let tok_1_2 = join(tok_1_2_1, tok_1_2_2); + let tok_1_3 = send_if(tok_1_2, csr_change_s, wr_req_valid, Change { csr: wr_req.csr }); + + + // Read from CSRs + let (tok_2_1, ext_csr_rd_req, ext_csr_req_valid) = recv_non_blocking(tok_0, ext_csr_rd_req_r, zero!()); + + send_if(tok_2_1, ext_csr_rd_resp_s, ext_csr_req_valid, RdResp { + csr: ext_csr_rd_req.csr, + value: register_file[ext_csr_rd_req.csr as u32], + }); + + let (tok_3_1, csr_rd_req, csr_req_valid) = recv_non_blocking(tok_0, csr_rd_req_r, zero!()); + send_if(tok_3_1, csr_rd_resp_s, csr_req_valid, RdResp { + csr: csr_rd_req.csr, + value: register_file[csr_rd_req.csr as u32], + }); + + State { + register_file: register_file, + } + } +} + +const INST_ID_W = u32:32; +const INST_DATA_W = u32:32; +const INST_ADDR_W = u32:2; +const INST_REGS_N = u32:4; +const INST_DATA_W_DIV8 = INST_DATA_W / u32:8; +const INST_LOG2_REGS_N = std::clog2(INST_REGS_N); + +proc CsrConfigInst { + type InstCsrRdReq = CsrRdReq; + type InstCsrRdResp = CsrRdResp; + type InstCsrWrReq = CsrWrReq; + type InstCsrWrResp = CsrWrResp; + type InstCsrChange = CsrChange; + + config( + ext_csr_rd_req_r: chan in, + ext_csr_rd_resp_s: chan out, + ext_csr_wr_req_r: chan in, + ext_csr_wr_resp_s: chan out, + + csr_rd_req_r: chan in, + csr_rd_resp_s: chan out, + csr_wr_req_r: chan in, + csr_wr_resp_s: chan out, + csr_change_s: chan out, + ) { + spawn CsrConfig ( + ext_csr_rd_req_r, ext_csr_rd_resp_s, + ext_csr_wr_req_r, ext_csr_wr_resp_s, + csr_rd_req_r, csr_rd_resp_s, + csr_wr_req_r, csr_wr_resp_s, + csr_change_s, + ); + } + + init { } + + next (state: ()) { } +} + +const TEST_ID_W = u32:32; +const TEST_DATA_W = u32:32; +const TEST_ADDR_W = u32:2; +const TEST_REGS_N = u32:4; +const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; +const TEST_LOG2_REGS_N = std::clog2(TEST_REGS_N); + +type TestCsr = uN[TEST_LOG2_REGS_N]; +type TestValue = uN[TEST_DATA_W]; + +struct TestData { + csr: uN[TEST_LOG2_REGS_N], + value: uN[TEST_DATA_W], +} + +const TEST_DATA = TestData[20]:[ + TestData{ csr: TestCsr:0, value: TestValue:0xca32_9f4a }, + TestData{ csr: TestCsr:1, value: TestValue:0x0fb3_fa42 }, + TestData{ csr: TestCsr:2, value: TestValue:0xe7ee_da41 }, + TestData{ csr: TestCsr:3, value: TestValue:0xef51_f98c }, + TestData{ csr: TestCsr:0, value: TestValue:0x97a3_a2d2 }, + TestData{ csr: TestCsr:0, value: TestValue:0xea06_e94b }, + TestData{ csr: TestCsr:1, value: TestValue:0x5fac_17ce }, + TestData{ csr: TestCsr:3, value: TestValue:0xf9d8_9938 }, + TestData{ csr: TestCsr:2, value: TestValue:0xc262_2d2e }, + TestData{ csr: TestCsr:2, value: TestValue:0xb4dd_424e }, + TestData{ csr: TestCsr:1, value: TestValue:0x01f9_b9e4 }, + TestData{ csr: TestCsr:1, value: TestValue:0x3020_6eec }, + TestData{ csr: TestCsr:3, value: TestValue:0x3124_87b5 }, + TestData{ csr: TestCsr:0, value: TestValue:0x0a49_f5e3 }, + TestData{ csr: TestCsr:2, value: TestValue:0xde3b_5d0f }, + TestData{ csr: TestCsr:3, value: TestValue:0x5948_c1b3 }, + TestData{ csr: TestCsr:0, value: TestValue:0xa26d_851f }, + TestData{ csr: TestCsr:3, value: TestValue:0x3fa9_59c0 }, + TestData{ csr: TestCsr:1, value: TestValue:0x4efd_dd09 }, + TestData{ csr: TestCsr:1, value: TestValue:0x6d75_058a }, +]; + +#[test_proc] +proc CsrConfig_test { + type TestCsrRdReq = CsrRdReq; + type TestCsrRdResp = CsrRdResp; + type TestCsrWrReq = CsrWrReq; + type TestCsrWrResp = CsrWrResp; + type TestCsrChange = CsrChange; + + terminator: chan out; + + ext_csr_rd_req_s: chan out; + ext_csr_rd_resp_r: chan in; + ext_csr_wr_req_s: chan out; + ext_csr_wr_resp_r: chan in; + + csr_rd_req_s: chan out; + csr_rd_resp_r: chan in; + csr_wr_req_s: chan out; + csr_wr_resp_r: chan in; + + csr_change_r: chan in; + + config (terminator: chan out) { + let (ext_csr_rd_req_s, ext_csr_rd_req_r) = chan("ext_csr_rd_req"); + let (ext_csr_rd_resp_s, ext_csr_rd_resp_r) = chan("ext_csr_rd_resp"); + + let (ext_csr_wr_req_s, ext_csr_wr_req_r) = chan("ext_csr_wr_req"); + let (ext_csr_wr_resp_s, ext_csr_wr_resp_r) = chan("ext_csr_wr_resp"); + + let (csr_rd_req_s, csr_rd_req_r) = chan("csr_rd_req"); + let (csr_rd_resp_s, csr_rd_resp_r) = chan("csr_rd_resp"); + + let (csr_wr_req_s, csr_wr_req_r) = chan("csr_wr_req"); + let (csr_wr_resp_s, csr_wr_resp_r) = chan("csr_wr_resp"); + + let (csr_change_s, csr_change_r) = chan("csr_change"); + + spawn CsrConfig ( + ext_csr_rd_req_r, ext_csr_rd_resp_s, + ext_csr_wr_req_r, ext_csr_wr_resp_s, + csr_rd_req_r, csr_rd_resp_s, + csr_wr_req_r, csr_wr_resp_s, + csr_change_s, + ); + + ( + terminator, + ext_csr_rd_req_s, ext_csr_rd_resp_r, + ext_csr_wr_req_s, ext_csr_wr_resp_r, + csr_rd_req_s, csr_rd_resp_r, + csr_wr_req_s, csr_wr_resp_r, + csr_change_r, + ) + } + + init { } + + next (state: ()) { + let expected_values = zero!(); + + // Test Writes through external interface + let (tok, expected_values) = for ((i, test_data), (tok, expected_values)): ((u32, TestData), (token, uN[TEST_DATA_W][TEST_REGS_N])) in enumerate(TEST_DATA) { + // write CSR via external interface + let wr_req = TestCsrWrReq { + csr: test_data.csr, + value: test_data.value, + }; + let tok = send(tok, ext_csr_wr_req_s, wr_req); + trace_fmt!("Sent #{} WrReq through external interface: {:#x}", i + u32:1, wr_req); + + let (tok, wr_resp) = recv(tok, ext_csr_wr_resp_r); + trace_fmt!("Received #{} WrResp through external interface: {:#x}", i + u32:1, wr_resp); + + // read CSR change + let (tok, csr_change) = recv(tok, csr_change_r); + trace_fmt!("Received #{} CSR change {:#x}", i + u32:1, csr_change); + + assert_eq(test_data.csr, csr_change.csr); + + // update expected values + let expected_values = update(expected_values, test_data.csr as u32, test_data.value); + + let tok = for (test_csr, tok): (u32, token) in u32:0..u32:4 { + let rd_req = TestCsrRdReq { + csr: test_csr as TestCsr, + }; + let expected_rd_resp = TestCsrRdResp{ + csr: test_csr as TestCsr, + value: expected_values[test_csr as u32] + }; + + // Read CSR via external interface + let tok = send(tok, ext_csr_rd_req_s, rd_req); + trace_fmt!("Sent #{} RdReq through external interface: {:#x}", i + u32:1, rd_req); + let (tok, rd_resp) = recv(tok, ext_csr_rd_resp_r); + trace_fmt!("Received #{} RdResp through external interface: {:#x}", i + u32:1, rd_resp); + assert_eq(expected_rd_resp, rd_resp); + + // Read CSR via internal interface + let tok = send(tok, csr_rd_req_s, rd_req); + trace_fmt!("Sent #{} RdReq through internal interface: {:#x}", i + u32:1, rd_req); + let (tok, csr_rd_resp) = recv(tok, csr_rd_resp_r); + trace_fmt!("Received #{} RdResp through internal interface: {:#x}", i + u32:1, csr_rd_resp); + assert_eq(expected_rd_resp, csr_rd_resp); + tok + }(tok); + + (tok, expected_values) + }((join(), expected_values)); + + // Test writes via internal interface + let (tok, _) = for ((i, test_data), (tok, expected_values)): ((u32, TestData), (token, uN[TEST_DATA_W][TEST_REGS_N])) in enumerate(TEST_DATA) { + // write CSR via request channel + let csr_wr_req = TestCsrWrReq { + csr: test_data.csr, + value: test_data.value, + }; + let tok = send(tok, csr_wr_req_s, csr_wr_req); + trace_fmt!("Sent #{} WrReq through internal interface: {:#x}", i + u32:1, csr_wr_req); + + let (tok, csr_wr_resp) = recv(tok, csr_wr_resp_r); + trace_fmt!("Received #{} WrResp through internal interface {:#x}", i + u32:1, csr_wr_resp); + + // read CSR change + let (tok, csr_change) = recv(tok, csr_change_r); + trace_fmt!("Received #{} CSR change {:#x}", i + u32:1, csr_change); + assert_eq(test_data.csr, csr_change.csr); + + // update expected values + let expected_values = update(expected_values, test_data.csr as u32, test_data.value); + + let tok = for (test_csr, tok): (u32, token) in u32:0..u32:4 { + let rd_req = TestCsrRdReq { + csr: test_csr as TestCsr, + }; + let expected_rd_resp = TestCsrRdResp{ + csr: test_csr as TestCsr, + value: expected_values[test_csr as u32] + }; + + // Read CSR via external interface + let tok = send(tok, ext_csr_rd_req_s, rd_req); + trace_fmt!("Sent #{} RdReq through external interface: {:#x}", i + u32:1, rd_req); + let (tok, rd_resp) = recv(tok, ext_csr_rd_resp_r); + trace_fmt!("Received #{} RdResp through external interface: {:#x}", i + u32:1, rd_resp); + assert_eq(expected_rd_resp, rd_resp); + + // Read CSR via internal interface + let tok = send(tok, csr_rd_req_s, rd_req); + trace_fmt!("Sent #{} RdReq through internal interface: {:#x}", i + u32:1, rd_req); + let (tok, csr_rd_resp) = recv(tok, csr_rd_resp_r); + trace_fmt!("Received #{} RdResp through internal interface: {:#x}", i + u32:1, csr_rd_resp); + assert_eq(expected_rd_resp, csr_rd_resp); + tok + }(tok); + + (tok, expected_values) + }((join(), expected_values)); + + send(tok, terminator, true); + } +} From d6e1b356e224aebf43669f3fc60cd584e6f81335 Mon Sep 17 00:00:00 2001 From: Krzysztof Oblonczek Date: Tue, 8 Oct 2024 18:02:20 +0200 Subject: [PATCH 10/85] modules/zstd: Add FrameHeaderDecoder Signed-off-by: Krzysztof Oblonczek --- xls/modules/zstd/BUILD | 112 ++--- xls/modules/zstd/frame_header_dec.x | 670 ++++++++++++++++++++++++++ xls/modules/zstd/frame_header_test.cc | 407 ---------------- xls/modules/zstd/frame_header_test.x | 30 -- 4 files changed, 703 insertions(+), 516 deletions(-) create mode 100644 xls/modules/zstd/frame_header_dec.x delete mode 100644 xls/modules/zstd/frame_header_test.cc delete mode 100644 xls/modules/zstd/frame_header_test.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index b717e7be96..b6ba693a28 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -158,16 +158,6 @@ cc_library( ], ) -xls_dslx_library( - name = "frame_header_dslx", - srcs = [ - "frame_header.x", - ], - deps = [ - ":buffer_dslx", - ], -) - xls_dslx_library( name = "common_dslx", srcs = [ @@ -176,116 +166,80 @@ xls_dslx_library( deps = [], ) -xls_dslx_test( - name = "frame_header_dslx_test", - dslx_test_args = {"compare": "jit"}, - library = ":frame_header_dslx", - tags = ["manual"], -) - xls_dslx_library( - name = "frame_header_test_dslx", + name = "frame_header_dec_dslx", srcs = [ - "frame_header_test.x", + "frame_header_dec.x", ], deps = [ - ":buffer_dslx", - ":frame_header_dslx", + "//xls/modules/zstd/memory:axi_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) -cc_test( - name = "frame_header_cc_test", - srcs = [ - "frame_header_test.cc", - ], - data = [ - ":frame_header_test_dslx", - ], - shard_count = 50, - deps = [ - ":data_generator", - "//xls/common:xls_gunit_main", - "//xls/common/file:filesystem", - "//xls/common/file:get_runfile_path", - "//xls/common/fuzzing:fuzztest", - "//xls/common/status:matchers", - "//xls/common/status:ret_check", - "//xls/dslx:create_import_data", - "//xls/dslx:import_data", - "//xls/dslx:parse_and_typecheck", - "//xls/dslx/ir_convert:convert_options", - "//xls/dslx/ir_convert:ir_converter", - "//xls/dslx/type_system:parametric_env", - "//xls/ir:bits", - "//xls/ir:value", - "//xls/simulation:sim_test_base", - "@com_google_absl//absl/container:flat_hash_map", - "@com_google_absl//absl/status:statusor", - "@com_google_absl//absl/types:span", - "@googletest//:gtest", - "@zstd", - ], +xls_dslx_test( + name = "frame_header_dec_dslx_test", + library = ":frame_header_dec_dslx", + tags = ["manual"], ) +frame_header_dec_codegen_args = common_codegen_args | { + "module_name": "FrameHeaderDecoder", + "clock_period_ps": "0", + "pipeline_stages": "6", +} + xls_dslx_verilog( - name = "frame_header_verilog", - codegen_args = { - "module_name": "FrameHeaderDecoder", - "delay_model": "asap7", - "pipeline_stages": "9", - "reset": "rst", - "reset_data_path": "false", - "use_system_verilog": "false", - }, - dslx_top = "parse_frame_header_128", - library = ":frame_header_test_dslx", + name = "frame_header_dec_verilog", + codegen_args = frame_header_dec_codegen_args, + dslx_top = "FrameHeaderDecoderInst", + library = ":frame_header_dec_dslx", tags = ["manual"], - verilog_file = "frame_header.v", + verilog_file = "frame_header_dec.v", ) xls_benchmark_ir( - name = "frame_header_opt_ir_benchmark", - src = ":frame_header_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "9", - "delay_model": "asap7", + name = "frame_header_dec_opt_ir_benchmark", + src = ":frame_header_dec_verilog.opt.ir", + benchmark_ir_args = frame_header_dec_codegen_args | { + "top": "__frame_header_dec__FrameHeaderDecoderInst__FrameHeaderDecoder_0__16_32_30_5_next", + "pipeline_stages": "10", }, tags = ["manual"], ) verilog_library( - name = "frame_header_verilog_lib", + name = "frame_header_dec_verilog_lib", srcs = [ - ":frame_header.v", + ":frame_header_dec.v", ], tags = ["manual"], ) synthesize_rtl( - name = "frame_header_synth_asap7", + name = "frame_header_dec_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", tags = ["manual"], top_module = "FrameHeaderDecoder", deps = [ - ":frame_header_verilog_lib", + ":frame_header_dec_verilog_lib", ], ) benchmark_synth( - name = "frame_header_benchmark_synth", - synth_target = ":frame_header_synth_asap7", + name = "frame_header_dec_benchmark_synth", + synth_target = ":frame_header_dec_synth_asap7", tags = ["manual"], ) place_and_route( - name = "frame_header_place_and_route", - clock_period = "750", + name = "frame_header_dec_place_and_route", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", stop_after_step = "global_routing", - synthesized_rtl = ":frame_header_synth_asap7", + synthesized_rtl = ":frame_header_dec_synth_asap7", tags = ["manual"], target_die_utilization_percentage = "10", ) diff --git a/xls/modules/zstd/frame_header_dec.x b/xls/modules/zstd/frame_header_dec.x new file mode 100644 index 0000000000..8647435996 --- /dev/null +++ b/xls/modules/zstd/frame_header_dec.x @@ -0,0 +1,670 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains utilities related to ZSTD Frame Header parsing. +// More information about the ZSTD Frame Header can be found in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.1 + +import std; +import xls.modules.zstd.memory.mem_reader; + +pub type WindowSize = u64; +pub type FrameContentSize = u64; +pub type DictionaryId = u32; + +// Structure for data obtained from decoding the Frame_Header_Descriptor +pub struct FrameHeader { + window_size: WindowSize, + frame_content_size: FrameContentSize, + dictionary_id: DictionaryId, + content_checksum_flag: u1, +} + +// Status values reported by the frame header parsing function +pub enum FrameHeaderDecoderStatus: u2 { + OKAY = 0, + CORRUPTED = 1, + UNSUPPORTED_WINDOW_SIZE = 2, +} + +pub struct FrameHeaderDecoderReq { + addr: uN[ADDR_W], +} + +pub struct FrameHeaderDecoderResp { + status: FrameHeaderDecoderStatus, + header: FrameHeader, + length: u5, +} + +// Maximal mantissa value for calculating maximal accepted window_size +// as per https://datatracker.ietf.org/doc/html/rfc8878#name-window-descriptor +const MAX_MANTISSA = WindowSize:0b111; + +// Structure for holding ZSTD Frame_Header_Descriptor data, as in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.1.1 +pub struct FrameHeaderDescriptor { + frame_content_size_flag: u2, + single_segment_flag: u1, + unused: u1, + reserved: u1, + content_checksum_flag: u1, + dictionary_id_flag: u2, +} + +// Auxiliary constant that can be used to initialize Proc's state +// with empty FrameHeader, because `zero!` cannot be used in that context +pub const ZERO_FRAME_HEADER = zero!(); +pub const FRAME_CONTENT_SIZE_NOT_PROVIDED_VALUE = FrameContentSize::MAX; + +// Extracts Frame_Header_Descriptor fields from 8-bit chunk of data +// that is assumed to be a valid Frame_Header_Descriptor +fn extract_frame_header_descriptor(data:u8) -> FrameHeaderDescriptor { + FrameHeaderDescriptor { + frame_content_size_flag: data[6:8], + single_segment_flag: data[5:6], + unused: data[4:5], + reserved: data[3:4], + content_checksum_flag: data[2:3], + dictionary_id_flag: data[0:2], + } +} + +#[test] +fn test_extract_frame_header_descriptor() { + assert_eq( + extract_frame_header_descriptor(u8:0xA4), + FrameHeaderDescriptor { + frame_content_size_flag: u2:0x2, + single_segment_flag: u1:0x1, + unused: u1:0x0, + reserved: u1:0x0, + content_checksum_flag: u1:0x1, + dictionary_id_flag: u2:0x0 + } + ); + + assert_eq( + extract_frame_header_descriptor(u8:0x0), + FrameHeaderDescriptor { + frame_content_size_flag: u2:0x0, + single_segment_flag: u1:0x0, + unused: u1:0x0, + reserved: u1:0x0, + content_checksum_flag: u1:0x0, + dictionary_id_flag: u2:0x0 + } + ); +} + +// Returns a boolean showing if the Window_Descriptor section exists +// for the frame with the given FrameHeaderDescriptor +fn window_descriptor_exists(desc: FrameHeaderDescriptor) -> bool { + desc.single_segment_flag == u1:0 +} + +#[test] +fn test_window_descriptor_exists() { + let zero_desc = zero!(); + + let desc_with_ss = FrameHeaderDescriptor {single_segment_flag: u1:1, ..zero_desc}; + assert_eq(window_descriptor_exists(desc_with_ss), false); + + let desc_without_ss = FrameHeaderDescriptor {single_segment_flag: u1:0, ..zero_desc}; + assert_eq(window_descriptor_exists(desc_without_ss), true); +} + +// Extracts window size from 8-bit chunk of data +// that is assumed to be a valid Window_Descriptor +fn extract_window_size_from_window_descriptor(data: u8) -> u64 { + let exponent = data[3:8]; + let mantissa = data[0:3]; + + let window_base = (u42:1 << (u6:10 + exponent as u6)); + let window_base_add = (window_base >> u2:3) as u42; + // optimization: perform multiplication by a 3-bit value with adds and shifts + // because XLS only allows multiplying operands of the same width + let window_add = match mantissa { + u3:0 => u42:0, + u3:1 => window_base_add, // u39 + u3:2 => window_base_add + window_base_add, // u39 + u39 = u40 + u3:3 => (window_base_add << u1:1) + window_base_add, // u40 + u39 = u41 + u3:4 => (window_base_add << u1:1) + (window_base_add << u1:1), // u40 + u40 = u41 + u3:5 => (window_base_add << u2:2) + window_base_add, // u41 + u39 = u42 + u3:6 => (window_base_add << u2:2) + (window_base_add << u2:1), // u41 + u40 = u42 + u3:7 => (window_base_add << u2:3) - window_base_add, // u42 - u39 = u42 + _ => fail!("extract_window_size_from_window_descriptor_unreachable", u42:0), + }; + + window_base as u64 + window_add as u64 +} + +#[test] +fn test_extract_window_size_from_window_descriptor() { + assert_eq(extract_window_size_from_window_descriptor(u8:0x0), u64:0x400); + assert_eq(extract_window_size_from_window_descriptor(u8:0x9), u64:0x900); + assert_eq(extract_window_size_from_window_descriptor(u8:0xFF), u64:0x3c000000000); +} + +// Returns boolean showing if the Frame_Content_Size section exists for +// the frame with the given FrameHeaderDescriptor. +fn frame_content_size_exists(desc: FrameHeaderDescriptor) -> bool { + desc.single_segment_flag != u1:0 || desc.frame_content_size_flag != u2:0 +} + +#[test] +fn test_frame_content_size_exists() { + let zero_desc = zero!(); + + let desc = FrameHeaderDescriptor {single_segment_flag: u1:0, frame_content_size_flag: u2:0, ..zero_desc}; + assert_eq(frame_content_size_exists(desc), false); + + let desc = FrameHeaderDescriptor {single_segment_flag: u1:0, frame_content_size_flag: u2:2, ..zero_desc}; + assert_eq(frame_content_size_exists(desc), true); + + let desc = FrameHeaderDescriptor {single_segment_flag: u1:1, frame_content_size_flag: u2:0, ..zero_desc}; + assert_eq(frame_content_size_exists(desc), true); + + let desc = FrameHeaderDescriptor {single_segment_flag: u1:1, frame_content_size_flag: u2:3, ..zero_desc}; + assert_eq(frame_content_size_exists(desc), true); +} + + +// Calculate maximal accepted window_size for given WINDOW_LOG_MAX and return whether given +// window_size should be accepted or discarded. +// Based on window_size calculation from: RFC 8878 +// https://datatracker.ietf.org/doc/html/rfc8878#name-window-descriptor +fn window_size_valid(window_size: WindowSize) -> bool { + let max_window_size = (WindowSize:1 << WINDOW_LOG_MAX) + (((WindowSize:1 << WINDOW_LOG_MAX) >> WindowSize:3) * MAX_MANTISSA); + + window_size <= max_window_size +} + + +pub fn parse_frame_header(header_raw: uN[112]) -> (FrameHeader, u4, u1) { + let fhd_raw = header_raw[0:8]; + let fhd = extract_frame_header_descriptor(fhd_raw); + // RFC8878 Section 3.1.1.1.1.4 + // "This [reserved] bit is reserved for some future feature. Its value + // must be zero. A decoder compliant with this specification version must + // ensure it is not set." + let header_ok = !fhd.reserved; + + let window_descriptor_start = u32:1; + // RFC8878 Section 3.1.1.1.2 + // "When Single_Segment_Flag is set, Window_Descriptor is not present." + let window_descriptor_len = match fhd.single_segment_flag { + u1:0 => u1:1, + u1:1 => u1:0, + _ => fail!("window_descriptor_len_unreachable", u1:0), + }; + let window_descriptor_raw = header_raw[u32:8*window_descriptor_start+:u8]; + let window_size = extract_window_size_from_window_descriptor(window_descriptor_raw); + + let dictionary_id_start = window_descriptor_start + window_descriptor_len as u32; + let dictionary_id_len = match fhd.dictionary_id_flag { + u2:0 => u32:0, + u2:1 => u32:1, + u2:2 => u32:2, + u2:3 => u32:4, + _ => fail!("dictionary_id_len_unreachable", u32:0), + }; + let dictionary_id_raw = header_raw[u32:8*dictionary_id_start+:u32]; + let dictionary_id = dictionary_id_raw & match fhd.dictionary_id_flag { + u2:0 => u32:0x0000_0000, + u2:1 => u32:0x0000_00ff, + u2:2 => u32:0x0000_ffff, + u2:3 => u32:0xffff_ffff, + _ => fail!("dictionary_id_unreachable", u32:0), + }; + + let frame_content_size_start = dictionary_id_start + dictionary_id_len; + // RFC8878 Section 3.1.1.1.1.1 + // "When Frame_Content_Size_Flag is 0, FCS_Field_Size depends on + // Single_Segment_Flag: If Single_Segment_Flag is set, FCS_Field_Siz + // is 1. Otherwise, FCS_Field_Size is 0;" + let frame_content_size_len = match (fhd.frame_content_size_flag, fhd.single_segment_flag) { + (u2:0, u1:0) => u32:0, + (u2:0, u1:1) => u32:1, + (u2:1, _) => u32:2, + (u2:2, _) => u32:4, + (u2:3, _) => u32:8, + _ => fail!("frame_content_size_len_unreachable", u32:0), + }; + + let frame_content_size_raw = header_raw[u32:8*frame_content_size_start+:u64]; + let frame_content_size_masked = frame_content_size_raw & match frame_content_size_len { + u32:0 => u64:0x0000_0000_0000_0000, + u32:1 => u64:0x0000_0000_0000_00ff, + u32:2 => u64:0x0000_0000_0000_ffff, + u32:4 => u64:0x0000_0000_ffff_ffff, + u32:8 => u64:0xffff_ffff_ffff_ffff, + _ => fail!("frame_content_size_masked_unreachable", u64:0), + }; + + // RFC8878 Section 3.1.1.1.4 + // "When FCS_Field_Size is 2, the offset of 256 is added." + let frame_content_size = frame_content_size_masked + match frame_content_size_len { + u32:2 => u64:256, + _ => u64:0, + }; + + // RFC8878 Section 3.1.1.1.2 + // "When Single_Segment_Flag is set, Window_Descriptor is not present. + // In this case, Window_Size is Frame_Content_Size [...]" + let window_size = if (window_descriptor_exists(fhd)) { + window_size + } else if (frame_content_size_exists(fhd)) { + frame_content_size + } else { + WindowSize:0 + }; + + let total_header_len = (frame_content_size_start + frame_content_size_len) as u4; + + (FrameHeader { + window_size: window_size, + frame_content_size: if frame_content_size_len != u32:0 { frame_content_size } else { FrameContentSize:0 }, + dictionary_id: if dictionary_id_len != u32:0 { dictionary_id } else { DictionaryId:0 }, + content_checksum_flag: fhd.content_checksum_flag, + }, total_header_len, header_ok) +} + + +#[test] +fn test_parse_frame_header() { + // normal case + let test_vec = uN[112]:0x1234567890ABCDEF_CAFE_09_C2; + let (frame_header_result, len, ok) = parse_frame_header(test_vec); + assert_eq(frame_header_result, FrameHeader { + window_size: u64:0x900, + frame_content_size: u64:0x1234567890ABCDEF, + dictionary_id: u32:0xCAFE, + content_checksum_flag: u1:0, + }); + assert_eq(len, u4:12); + assert_eq(ok, u1:1); + + // SingleSegmentFlag is set + let test_vec = uN[112]:0xaa20; + let (frame_header_result, len, ok) = parse_frame_header(test_vec); + assert_eq(frame_header_result, FrameHeader { + window_size: u64:0xaa, + frame_content_size: u64:0xaa, + dictionary_id: u32:0x0, + content_checksum_flag: u1:0, + }); + assert_eq(len, u4:2); + assert_eq(ok, u1:1); + + // SingleSegmentFlag is set and FrameContentSize is bigger than accepted window_size + let test_vec = uN[112]:0x1234567890ABCDEF_CAFE_E2; + let (frame_header_result, len, ok) = parse_frame_header(test_vec); + assert_eq(frame_header_result, FrameHeader { + window_size: u64:0x1234567890ABCDEF, + frame_content_size: u64:0x1234567890ABCDEF, + dictionary_id: u32:0xCAFE, + content_checksum_flag: u1:0, + }); + assert_eq(len, u4:11); + assert_eq(ok, u1:1); + + // Frame header descriptor is corrupted (we don't check frame header and length) + let test_vec = uN[112]:0x1234567890ABCDEF_1234_09_CA; + let (_, _, ok) = parse_frame_header(test_vec); + assert_eq(ok, u1:0); + + // Large window size + let test_vec = uN[112]:0xd310; + let (frame_header_result, len, ok) = parse_frame_header(test_vec); + assert_eq(frame_header_result, FrameHeader { + window_size: u64:0x1600000000, + ..zero!() + }); + assert_eq(len, u4:2); + assert_eq(ok, u1:1); + + // Large window size + let test_vec = uN[112]:0xf45b5b5b0db1; + let (frame_header_result, len, ok) = parse_frame_header(test_vec); + assert_eq(frame_header_result, FrameHeader { + window_size: u64:0xf45b5b5b, + frame_content_size: u64:0xf45b5b5b, + dictionary_id: u32:0xD, + content_checksum_flag: u1:0, + }); + assert_eq(len, u4:6); + assert_eq(ok, u1:1); + + // Large window size + let test_vec = uN[112]:0xc0659db6813a16b33f3da53a79e4; + let (frame_header_result, len, ok) = parse_frame_header(test_vec); + assert_eq(frame_header_result, FrameHeader { + window_size: u64:0x3a16b33f3da53a79, + frame_content_size: u64:0x3a16b33f3da53a79, + dictionary_id: u32:0, + content_checksum_flag: u1:1, + }); + assert_eq(len, u4:9); + assert_eq(ok, u1:1); +} + + +enum FrameHeaderDecoderFsm: u1 { + RECV = 0, + RESP = 1 +} + +// Magic number value, as in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1 +const MAGIC_NUMBER = u32:0xFD2FB528; +const MAGIC_NUMBER_LEN = u32:4; + +const MAX_HEADER_LEN = u32:14; +const MAX_MAGIC_PLUS_HEADER_LEN = MAGIC_NUMBER_LEN + MAX_HEADER_LEN; + +struct FrameHeaderDecoderState { + fsm: FrameHeaderDecoderFsm, + xfers: u32, + raw_header: uN[XFER_SIZE][XFER_COUNT], +} + +pub proc FrameHeaderDecoder< + WINDOW_LOG_MAX: u32, + DATA_W: u32, + ADDR_W: u32, + XFERS_FOR_HEADER: u32 = {((MAX_MAGIC_PLUS_HEADER_LEN * u32:8) / DATA_W) + u32:1}, +> { + type State = FrameHeaderDecoderState; + type Fsm = FrameHeaderDecoderFsm; + type Req = FrameHeaderDecoderReq; + type Resp = FrameHeaderDecoderResp; + type ReaderReq = mem_reader::MemReaderReq; + type ReaderResp = mem_reader::MemReaderResp; + + reader_req_s: chan out; + reader_resp_r: chan in; + + decode_req_r: chan in; + decode_resp_s: chan out; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + decode_req_r: chan in, + decode_resp_s: chan out + ) { + (reader_req_s, reader_resp_r, decode_req_r, decode_resp_s) + } + + init { zero!() } + + next(state: State) { + type ReaderReq = mem_reader::MemReaderReq; + type State = FrameHeaderDecoderState; + + let tok0 = join(); + let (tok_req, req, do_req) = recv_non_blocking(tok0, decode_req_r, zero!()); + send_if(tok_req, reader_req_s, do_req, ReaderReq { addr: req.addr, length: MAX_MAGIC_PLUS_HEADER_LEN as uN[ADDR_W] }); + + let do_recv = (state.fsm == Fsm::RECV); + let (tok, resp, recvd) = recv_if_non_blocking(tok0, reader_resp_r, do_recv, zero!()); + + let do_resp = (state.fsm == Fsm::RESP); + let raw_header_bits = state.raw_header as uN[DATA_W * XFERS_FOR_HEADER]; + let raw_magic_number = raw_header_bits[:s32:8 * MAGIC_NUMBER_LEN as s32]; + let raw_header = raw_header_bits[s32:8 * MAGIC_NUMBER_LEN as s32 : s32:8 * MAX_MAGIC_PLUS_HEADER_LEN as s32]; + let magic_number_ok = raw_magic_number == MAGIC_NUMBER; + let (decoded_header, header_len, header_ok) = parse_frame_header(raw_header); + + let status = if (!header_ok || !magic_number_ok) { + FrameHeaderDecoderStatus::CORRUPTED + } else if (!window_size_valid(decoded_header.window_size)) { + FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE + } else { + FrameHeaderDecoderStatus::OKAY + }; + + let header_result = FrameHeaderDecoderResp { + status: status, + header: decoded_header, + length: header_len as u5 + MAGIC_NUMBER_LEN as u5, + }; + + send_if(tok0, decode_resp_s, do_resp, header_result); + + let next_state = match (state.fsm) { + Fsm::RECV => { + if (recvd) { + // raw_header is updated from the highest to lowest index because + // highest index in an array contains least significant bytes when + // casting to a bit vector + let update_idx = XFERS_FOR_HEADER - state.xfers - u32:1; + let next_raw_header = update(state.raw_header, update_idx, resp.data); + if (resp.last) { + State { raw_header: next_raw_header, fsm: Fsm::RESP, ..state } + } else { + State { raw_header: next_raw_header, xfers: state.xfers + u32:1, ..state } + } + } else { + state + } + }, + Fsm::RESP => { + State { fsm: Fsm::RECV, xfers: u32:0, ..state } + }, + _ => fail!("FrameHeaderDecoder_fsm_unreachable", zero!()) + }; + + next_state + } +} + +// The largest allowed WindowLog for DSLX tests +pub const TEST_WINDOW_LOG_MAX = u32:22; +pub const TEST_DATA_W = u32:32; +pub const TEST_ADDR_W = u32:16; +pub const TEST_XFERS_FOR_HEADER = ((MAX_MAGIC_PLUS_HEADER_LEN * u32:8) / TEST_DATA_W) + u32:1; + +#[test_proc] +proc FrameHeaderDecoderTest { + type Req = FrameHeaderDecoderReq; + type Resp = FrameHeaderDecoderResp; + type ReaderReq = mem_reader::MemReaderReq; + type ReaderResp = mem_reader::MemReaderResp; + + terminator: chan out; + + reader_req_r: chan in; + reader_resp_s: chan out; + + decode_req_s: chan out; + decode_resp_r: chan in; + + config(terminator: chan out) { + let (reader_req_s, reader_req_r) = chan("reader_req"); + let (reader_resp_s, reader_resp_r) = chan("reader_resp"); + let (decode_req_s, decode_req_r) = chan("decode_req"); + let (decode_resp_s, decode_resp_r) = chan("decode_resp"); + spawn FrameHeaderDecoder( + reader_req_s, + reader_resp_r, + decode_req_r, + decode_resp_s + ); + (terminator, reader_req_r, reader_resp_s, decode_req_s, decode_resp_r) + } + + init {} + + next(state: ()) { + let tok = join(); + let tests: (u32[TEST_XFERS_FOR_HEADER], FrameHeaderDecoderResp)[7] = [ + ( + // normal case + [u32:0xFD2FB528, u32:0xCAFE_09_C2, u32:0x90ABCDEF, u32:0x12345678, u32:0x0], + FrameHeaderDecoderResp { + header: FrameHeader { + window_size: u64:0x900, + frame_content_size: u64:0x1234567890ABCDEF, + dictionary_id: u32:0xCAFE, + content_checksum_flag: u1:0, + }, + status: FrameHeaderDecoderStatus::OKAY, + length: u5:16 + }, + ), ( + // SingleSegmentFlag is set + [u32:0xFD2FB528, u32:0xAA20, u32:0x0, u32:0x0, u32:0x0], + FrameHeaderDecoderResp { + header: FrameHeader { + window_size: u64:0xaa, + frame_content_size: u64:0xaa, + dictionary_id: u32:0x0, + content_checksum_flag: u1:0, + }, + status: FrameHeaderDecoderStatus::OKAY, + length: u5:6 + }, + ), ( + // SingleSegmentFlag is set and FrameContentSize is bigger than accepted window_size + [u32:0xFD2FB528, u32:0xEF_CAFE_E2, u32:0x7890ABCD, u32:0x123456, u32:0x0], + FrameHeaderDecoderResp { + header: FrameHeader { + window_size: u64:0x1234567890ABCDEF, + frame_content_size: u64:0x1234567890ABCDEF, + dictionary_id: u32:0xCAFE, + content_checksum_flag: u1:0, + }, + status: FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE, + length: u5:15 + }, + ), ( + // Frame header descriptor is corrupted (we don't check 'header' and 'length' fields) + [u32:0xFD2FB528, u32:0x1234_09_CA, u32:0x90ABCDEF, u32:0x12345678, u32:0x0], + FrameHeaderDecoderResp { + header: zero!(), + status: FrameHeaderDecoderStatus::CORRUPTED, + length: u5:0 + }, + ), ( + // Window size required by frame is too big for given decoder configuration + [u32:0xFD2FB528, u32:0xD310, u32:0x0, u32:0x0, u32:0x0], + FrameHeaderDecoderResp { + header: FrameHeader { + window_size: u64:0x1600000000, + ..zero!() + }, + status: FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE, + length: u5:6 + }, + ), ( + // Window size required by frame is too big for given decoder configuration + [u32:0xFD2FB528, u32:0x5B5B0DB1, u32:0xF45B, u32:0x0, u32:0x0], + FrameHeaderDecoderResp { + header: FrameHeader { + window_size: u64:0xf45b5b5b, + frame_content_size: u64:0xf45b5b5b, + dictionary_id: u32:0xD, + content_checksum_flag: u1:0, + }, + status: FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE, + length: u5:10 + }, + ), ( + // Window size required by frame is too big for given decoder configuration + [u32:0xFD2FB528, u32:0xA53A79E4, u32:0x16B33F3D, u32:0x9DB6813A, u32:0xC065], + FrameHeaderDecoderResp { + header: FrameHeader { + window_size: u64:0x3a16b33f3da53a79, + frame_content_size: u64:0x3a16b33f3da53a79, + dictionary_id: u32:0, + content_checksum_flag: u1:1, + }, + status: FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE, + length: u5:13 + } + ) + ]; + + const ADDR = u16:0x1234; + let tok = for ((_, (test_vec, expected)), tok): ((u32, (u32[TEST_XFERS_FOR_HEADER], FrameHeaderDecoderResp)), token) in enumerate(tests) { + let tok = send(tok, decode_req_s, FrameHeaderDecoderReq { addr: ADDR }); + let (tok, recv_data) = recv(tok, reader_req_r); + + assert_eq(recv_data, ReaderReq { addr: ADDR, length: MAX_MAGIC_PLUS_HEADER_LEN as u16 }); + + let tok = for ((j, word), tok): ((u32, u32), token) in enumerate(test_vec) { + let last = j + u32:1 == array_size(test_vec); + send(tok, reader_resp_s, ReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: word, + length: if !last { (TEST_DATA_W / u32:8) as u16 } else { (MAX_MAGIC_PLUS_HEADER_LEN % TEST_XFERS_FOR_HEADER) as u16 }, + last: last, + }) + }(tok); + + let (tok, recv_data) = recv(tok, decode_resp_r); + if (recv_data.status == FrameHeaderDecoderStatus::OKAY || recv_data.status == FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE) { + assert_eq(recv_data, expected); + } else { + // if the header is corrupted we don't offer any guarantees + // about its contents so we just check that the status matches + assert_eq(recv_data.status, expected.status); + }; + + tok + }(tok); + + send(tok, terminator, true); + } +} + + +// Largest allowed WindowLog accepted by libzstd decompression function +// https://github.com/facebook/zstd/blob/v1.4.7/lib/decompress/zstd_decompress.c#L296 +// Use only in C++ tests when comparing DSLX ZSTD Decoder with libzstd +pub const TEST_WINDOW_LOG_MAX_LIBZSTD = u32:30; + +proc FrameHeaderDecoderInst { + type Req = FrameHeaderDecoderReq; + type Resp = FrameHeaderDecoderResp; + type ReaderReq = mem_reader::MemReaderReq; + type ReaderResp = mem_reader::MemReaderResp; + + reader_req_s: chan out; + reader_resp_r: chan in; + + decode_req_r: chan in; + decode_resp_s: chan out; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + decode_req_r: chan in, + decode_resp_s: chan out, + ) { + spawn FrameHeaderDecoder( + reader_req_s, + reader_resp_r, + decode_req_r, + decode_resp_s + ); + (reader_req_s, reader_resp_r, decode_req_r, decode_resp_s) + } + + init {} + + next(state: ()) {} +} diff --git a/xls/modules/zstd/frame_header_test.cc b/xls/modules/zstd/frame_header_test.cc deleted file mode 100644 index 55530c80f5..0000000000 --- a/xls/modules/zstd/frame_header_test.cc +++ /dev/null @@ -1,407 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this kFile except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include - -// NOLINTBEGIN(build/include_order) - Silence include order warnings. -#include "xls/simulation/sim_test_base.h" -#define ZSTD_STATIC_LINKING_ONLY 1 - -#include -#include -#include -#include -#include // NOLINT -#include -#include -#include -// NOLINTEND(build/include_order) - Silence include order warnings. - -#include "gtest/gtest.h" -#include "xls/common/fuzzing/fuzztest.h" -#include "absl/container/flat_hash_map.h" -#include "absl/status/statusor.h" -#include "absl/types/span.h" -#include "xls/common/file/filesystem.h" -#include "xls/common/file/get_runfile_path.h" -#include "xls/common/status/matchers.h" -#include "xls/common/status/ret_check.h" -#include "xls/dslx/create_import_data.h" -#include "xls/dslx/import_data.h" -#include "xls/dslx/ir_convert/convert_options.h" -#include "xls/dslx/ir_convert/ir_converter.h" -#include "xls/dslx/parse_and_typecheck.h" -#include "xls/dslx/type_system/parametric_env.h" -#include "xls/ir/bits.h" -#include "xls/ir/value.h" -#include "xls/modules/zstd/data_generator.h" -#include "external/zstd/lib/zstd.h" -#include "external/zstd/lib/zstd_errors.h" - -namespace xls { -namespace { - -// Must be in sync with FrameHeaderStatus from -// xls/modules/zstd/frame_header.x -enum FrameHeaderStatus : uint8_t { - OK, - CORRUPTED, - NO_ENOUGH_DATA, - UNSUPPORTED_WINDOW_SIZE -}; - -class ZstdFrameHeader { - public: - absl::Span buffer() const { - return absl::MakeConstSpan(buffer_); - } - - ZSTD_frameHeader header() const { return header_; } - - size_t result() const { return result_; } - - ZstdFrameHeader(absl::Span buffer, ZSTD_frameHeader h, - size_t r) - : header_(h), result_(r) { - std::vector v(buffer.begin(), buffer.end()); - buffer_ = v; - } - // Parse a frame header from an arbitrary buffer with the ZSTD library. - static absl::StatusOr Parse( - absl::Span buffer) { - XLS_RET_CHECK(!buffer.empty()); - XLS_RET_CHECK(buffer.data() != nullptr); - ZSTD_frameHeader zstd_fh; - size_t result = ZSTD_getFrameHeader_advanced( - &zstd_fh, buffer.data(), buffer.size(), ZSTD_f_zstd1_magicless); - return ZstdFrameHeader(buffer, zstd_fh, result); - } - - private: - std::vector buffer_; - ZSTD_frameHeader header_; - size_t result_; -}; - -class FrameHeaderTest : public xls::SimTestBase { - public: - // Prepare simulation environment - void SetUp() override { - XLS_ASSERT_OK_AND_ASSIGN(std::filesystem::path path, - xls::GetXlsRunfilePath(this->kFile)); - XLS_ASSERT_OK_AND_ASSIGN(std::string module_text, - xls::GetFileContents(path)); - - auto import_data = xls::dslx::CreateImportDataForTest(); - XLS_ASSERT_OK_AND_ASSIGN( - xls::dslx::TypecheckedModule checked_module, - xls::dslx::ParseAndTypecheck(module_text, this->kFileName, - this->kModuleName, &import_data)); - - auto options = xls::dslx::ConvertOptions{}; - /* FIXME: The following code should work with a parametrized version of - * the `parse_frame_header` function. However, it seems that - * the symbolic_bindings are not correctly propagated inside - * ConvertOneFunction. To leverage the problem, a simple specialization - * of the function is used (`parse_frame_header_128`). - * Once the problem is solved, we can restore the code below. - */ - // auto symbolic_bindings = xls::dslx::ParametricEnv( - // absl::flat_hash_map{ - // {"CAPACITY", xls::dslx::InterpValue::MakeUBits(/*bit_count=*/32, - // /*value=*/32)}}); - dslx::ParametricEnv* symbolic_bindings = nullptr; - XLS_ASSERT_OK_AND_ASSIGN( - this->converted, xls::dslx::ConvertOneFunction( - checked_module.module, kFunctionName, &import_data, - symbolic_bindings, options)); - } - - // Prepare inputs for DSLX simulation based on the given zstd header, - // form the expected output from the simulation, - // run the simulation of frame header parser and compare the results against - // expected values. - void RunAndExpectFrameHeader(const ZstdFrameHeader& zstd_frame_header) { - // Extend buffer contents to 128 bits if necessary. - const absl::Span buffer = zstd_frame_header.buffer(); - std::vector buffer_extended(kDslxBufferSizeBytes, 0); - absl::Span input_buffer; - if (buffer.size() < kDslxBufferSizeBytes) { - std::copy(buffer.begin(), buffer.end(), buffer_extended.begin()); - input_buffer = absl::MakeSpan(buffer_extended); - } else { - input_buffer = buffer; - } - - // Decide on the expected status - ZSTD_frameHeader zstd_fh = zstd_frame_header.header(); - size_t result = zstd_frame_header.result(); - FrameHeaderStatus expected_status = FrameHeaderStatus::OK; - if (result != 0) { - if (ZSTD_isError(result)) { - switch (ZSTD_getErrorCode(result)) { - case ZSTD_error_frameParameter_windowTooLarge: - expected_status = FrameHeaderStatus::UNSUPPORTED_WINDOW_SIZE; - break; - case ZSTD_error_frameParameter_unsupported: - // Occurs when reserved_bit == 1, should result in CORRUPTED state - default: - // Provided data is corrupted. Unable to correctly parse ZSTD frame. - expected_status = FrameHeaderStatus::CORRUPTED; - break; - } - } else { - // Provided data is to small to correctly parse ZSTD frame, should - // have `result` bytes, got `buffer.size()` bytes. - expected_status = FrameHeaderStatus::NO_ENOUGH_DATA; - } - // Make sure that the FCS does not exceed max window buffer size - // Frame Header decoding failed - Special case - difference between the - // reference library and the decoder - } else if (!window_size_valid(zstd_fh.windowSize)) { - expected_status = FrameHeaderStatus::UNSUPPORTED_WINDOW_SIZE; - } - - auto input = CreateDslxSimulationInput(buffer.size(), input_buffer); - absl::flat_hash_map hashed_input = {{"buffer", input}}; - - auto expected_frame_header_result = CreateExpectedFrameHeaderResult( - &zstd_fh, input, buffer, expected_status); - - RunAndExpectEq(hashed_input, expected_frame_header_result, this->converted, - true, true); - } - - const std::string_view kFile = "xls/modules/zstd/frame_header_test.x"; - const std::string_view kModuleName = "frame_header_test"; - const std::string_view kFileName = "frame_header_test.x"; - const std::string_view kFunctionName = "parse_frame_header_128"; - std::string converted; - - private: - static const size_t kDslxBufferSize = 128; - static const size_t kDslxBufferSizeBytes = - (kDslxBufferSize + CHAR_BIT - 1) / CHAR_BIT; - - // Largest allowed WindowLog accepted by libzstd decompression function - // https://github.com/facebook/zstd/blob/v1.5.6/lib/decompress/zstd_decompress.c#L515 - // Use only in C++ tests when comparing DSLX ZSTD Decoder with libzstd - // Must be in sync with kTestWindowLogMaxLibZstd in frame_header_test.x - const uint64_t kTestWindowLogMaxLibZstd = 30; - - // Maximal mantissa value for calculating maximal accepted window_size - // as per https://datatracker.ietf.org/doc/html/rfc8878#name-window-descriptor - const uint64_t kMaxMantissa = 0b111; - - // Calculate maximal accepted window_size for given WINDOW_LOG_MAX and return - // whether given window_size should be accepted or discarded. Based on - // window_size calculation from: RFC 8878 - // https://datatracker.ietf.org/doc/html/rfc8878#name-window-descriptor - bool window_size_valid(uint64_t window_size) { - auto max_window_size = - (1 << kTestWindowLogMaxLibZstd) + - (((1 << kTestWindowLogMaxLibZstd) >> 3) * kMaxMantissa); - - return window_size <= max_window_size; - } - - // Form DSLX Value representing ZSTD Frame header based on data parsed with - // ZSTD library. Represents DSLX struct `FrameHeader`. - Value CreateExpectedFrameHeader(ZSTD_frameHeader* fh, - FrameHeaderStatus expected_status) { - if (expected_status == FrameHeaderStatus::CORRUPTED || - expected_status == FrameHeaderStatus::UNSUPPORTED_WINDOW_SIZE) { - return Value::Tuple({ - /*window_size=*/Value(UBits(0, 64)), - /*frame_content_size=*/Value(UBits(0, 64)), - /*dictionary_id=*/Value(UBits(0, 32)), - /*content_checksum_flag=*/Value(UBits(0, 1)), - }); - } - return Value::Tuple({ - /*window_size=*/Value(UBits(fh->windowSize, 64)), - /*frame_content_size=*/Value(UBits(fh->frameContentSize, 64)), - /*dictionary_id=*/Value(UBits(fh->dictID, 32)), - /*content_checksum_flag=*/Value(UBits(fh->checksumFlag, 1)), - }); - } - - // Create DSLX Value representing Buffer contents after parsing frame header - // in simulation. Represents DSLX struct `Buffer`. - Value CreateExpectedBuffer(Value dslx_simulation_input, - absl::Span input_buffer, - size_t consumed_bytes_count, - FrameHeaderStatus expected_status) { - // Return original buffer contents - if (expected_status == FrameHeaderStatus::NO_ENOUGH_DATA) { - return dslx_simulation_input; - } - // Critical failure - return empty buffer - if (expected_status == FrameHeaderStatus::CORRUPTED || - expected_status == FrameHeaderStatus::UNSUPPORTED_WINDOW_SIZE) { - return Value::Tuple({/*contents:*/ Value(UBits(0, kDslxBufferSize)), - /*length:*/ Value(UBits(0, 32))}); - } - - // Frame Header parsing succeeded. Expect output buffer contents with - // removed first `consumed_bytes_count` bytes and extended to - // kDslxBufferSize if necessary - size_t bytes_to_extend = - kDslxBufferSizeBytes - (input_buffer.size() - consumed_bytes_count); - std::vector output_buffer(input_buffer.begin() + consumed_bytes_count, - input_buffer.end()); - for (int i = 0; i < bytes_to_extend; i++) { - output_buffer.push_back(0); - } - - auto expected_buffer_contents = - Value(Bits::FromBytes(output_buffer, kDslxBufferSize)); - size_t output_buffer_size_bits = - (input_buffer.size() - consumed_bytes_count) * CHAR_BIT; - size_t expected_buffer_size = output_buffer_size_bits > kDslxBufferSize - ? kDslxBufferSize - : output_buffer_size_bits; - - return Value::Tuple({/*contents:*/ expected_buffer_contents, - /*length:*/ Value(UBits(expected_buffer_size, 32))}); - } - - // Prepare DSLX Value representing Full Result of frame header parsing - // simulation. It consists of expected status, parsing result and buffer - // contents after parsing. Represents DSLX struct `FrameHeaderResult`. - Value CreateExpectedFrameHeaderResult(ZSTD_frameHeader* fh, - Value dslx_simulation_input, - absl::Span input_buffer, - FrameHeaderStatus expected_status) { - auto expected_buffer = - CreateExpectedBuffer(std::move(dslx_simulation_input), input_buffer, - fh->headerSize, expected_status); - auto expected_frame_header = CreateExpectedFrameHeader(fh, expected_status); - return Value::Tuple({/*status:*/ Value(UBits(expected_status, 2)), - /*header:*/ expected_frame_header, - /*buffer:*/ expected_buffer}); - } - - // Return DSLX Value used as input argument for running frame header parsing - // simulation. Represents DSLX struct `Buffer`. - Value CreateDslxSimulationInput(size_t buffer_size, - absl::Span input_buffer) { - size_t size = buffer_size; - - // ignore buffer contents that won't fit into specialized buffer - if (buffer_size > kDslxBufferSizeBytes) { - size = kDslxBufferSizeBytes; - } - - return Value::Tuple( - {/*contents:*/ Value(Bits::FromBytes(input_buffer, kDslxBufferSize)), - /*length:*/ Value(UBits(size * CHAR_BIT, 32))}); - } -}; - -/* TESTS */ - -TEST_F(FrameHeaderTest, Success) { - XLS_ASSERT_OK_AND_ASSIGN( - auto header, - ZstdFrameHeader::Parse({0xC2, 0x09, 0xFE, 0xCA, 0xEF, 0xCD, 0xAB, 0x90, - 0x78, 0x56, 0x34, 0x12})); - this->RunAndExpectFrameHeader(header); -} - -TEST_F(FrameHeaderTest, FailCorruptedReservedBit) { - XLS_ASSERT_OK_AND_ASSIGN( - auto header, ZstdFrameHeader::Parse({0xEA, 0xFE, 0xCA, 0xEF, 0xCD, 0xAB, - 0x90, 0x78, 0x56, 0x34, 0x12})); - this->RunAndExpectFrameHeader(header); -} - -TEST_F(FrameHeaderTest, FailUnsupportedWindowSizeTooBig) { - XLS_ASSERT_OK_AND_ASSIGN(auto header, ZstdFrameHeader::Parse({0x10, 0xD3})); - this->RunAndExpectFrameHeader(header); -} - -TEST_F(FrameHeaderTest, FailNoEnoughData) { - XLS_ASSERT_OK_AND_ASSIGN(auto header, ZstdFrameHeader::Parse({0xD3, 0xED})); - this->RunAndExpectFrameHeader(header); -} - -// NO_ENOUGH_DATA has priority over CORRUPTED from reserved bit -TEST_F(FrameHeaderTest, FailNoEnoughDataReservedBit) { - XLS_ASSERT_OK_AND_ASSIGN(auto header, ZstdFrameHeader::Parse({0xED, 0xD3})); - this->RunAndExpectFrameHeader(header); -} - -TEST_F(FrameHeaderTest, FailUnsupportedFrameContentSizeThroughSingleSegment) { - XLS_ASSERT_OK_AND_ASSIGN( - auto header, ZstdFrameHeader::Parse({0261, 015, 91, 91, 91, 0364})); - this->RunAndExpectFrameHeader(header); -} - -TEST_F(FrameHeaderTest, - FailUnsupportedVeryLargeFrameContentSizeThroughSingleSegment) { - XLS_ASSERT_OK_AND_ASSIGN( - auto header, - ZstdFrameHeader::Parse({0344, 'y', ':', 0245, '=', '?', 0263, 0026, ':', - 0201, 0266, 0235, 'e', 0300})); - this->RunAndExpectFrameHeader(header); -} - -TEST_F(FrameHeaderTest, FailUnsupportedWindowSize) { - XLS_ASSERT_OK_AND_ASSIGN( - auto header, - ZstdFrameHeader::Parse({'S', 0301, 'i', 0320, 0, 0256, 'd', 'D', 0226, - 'F', 'Z', 'Z', 0332, 0370, 'A'})); - this->RunAndExpectFrameHeader(header); -} - -class FrameHeaderSeededTest : public FrameHeaderTest, - public ::testing::WithParamInterface { - public: - static const uint32_t random_headers_count = 50; -}; - -// Test `random_headers_count` instances of randomly generated valid -// frame headers, generated with `decodecorpus` tool. -TEST_P(FrameHeaderSeededTest, ParseMultipleFrameHeaders) { - auto seed = GetParam(); - XLS_ASSERT_OK_AND_ASSIGN(auto buffer, zstd::GenerateFrameHeader(seed, false)); - XLS_ASSERT_OK_AND_ASSIGN(auto frame_header, ZstdFrameHeader::Parse(buffer)); - this->RunAndExpectFrameHeader(frame_header); -} - -INSTANTIATE_TEST_SUITE_P( - FrameHeaderSeededTest, FrameHeaderSeededTest, - ::testing::Range(0, FrameHeaderSeededTest::random_headers_count)); - -class FrameHeaderFuzzTest - : public fuzztest::PerFuzzTestFixtureAdapter { - public: - void ParseMultipleRandomFrameHeaders(const std::vector& buffer) { - auto frame_header = ZstdFrameHeader::Parse(buffer); - XLS_ASSERT_OK(frame_header); - this->RunAndExpectFrameHeader(frame_header.value()); - } -}; - -// Perform UNDETERMINISTIC FuzzTests with input vectors of variable length and -// contents. Frame Headers generated by FuzzTests can be invalid. -// This test checks if negative cases are handled correctly. -FUZZ_TEST_F(FrameHeaderFuzzTest, ParseMultipleRandomFrameHeaders) - .WithDomains(fuzztest::Arbitrary>() - .WithMinSize(1) - .WithMaxSize(16)); - -} // namespace -} // namespace xls diff --git a/xls/modules/zstd/frame_header_test.x b/xls/modules/zstd/frame_header_test.x deleted file mode 100644 index 9216dfab8d..0000000000 --- a/xls/modules/zstd/frame_header_test.x +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -import std; -import xls.modules.zstd.buffer as buff; -import xls.modules.zstd.frame_header as frame_header; - -type Buffer = buff::Buffer; -type FrameHeaderResult = frame_header::FrameHeaderResult; -type WindowSize = frame_header::WindowSize; - -// Largest allowed WindowLog accepted by libzstd decompression function -// https://github.com/facebook/zstd/blob/v1.4.7/lib/decompress/zstd_decompress.c#L296 -// Use only in C++ tests when comparing DSLX ZSTD Decoder with libzstd -pub const TEST_WINDOW_LOG_MAX_LIBZSTD = WindowSize:30; - -pub fn parse_frame_header_128(buffer: Buffer<128>) -> FrameHeaderResult<128> { - frame_header::parse_frame_header(buffer) -} From e3477dee1ee8e9264348d67686caaae7cef1b7ef Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Tue, 8 Oct 2024 18:04:07 +0200 Subject: [PATCH 11/85] modules/zstd: Add BlockHeaderDecoder Signed-off-by: Maciej Torhan --- xls/modules/zstd/BUILD | 78 ++++++++ xls/modules/zstd/block_header_dec.x | 293 ++++++++++++++++++++++++++++ 2 files changed, 371 insertions(+) create mode 100644 xls/modules/zstd/block_header_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index b6ba693a28..ede9709eb9 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -261,6 +261,84 @@ xls_dslx_test( tags = ["manual"], ) +xls_dslx_library( + name = "block_header_dec_dslx", + srcs = [ + "block_header_dec.x", + ], + deps = [ + ":block_header_dslx", + ":common_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + ], +) + +xls_dslx_test( + name = "block_header_dec_dslx_test", + library = ":block_header_dec_dslx", + tags = ["manual"], +) + +block_header_dec_codegen_args = common_codegen_args | { + "module_name": "BlockHeaderDec", + "pipeline_stages": "1", +} + +xls_dslx_verilog( + name = "block_header_dec_verilog", + codegen_args = block_header_dec_codegen_args, + dslx_top = "BlockHeaderDecoderInst", + library = ":block_header_dec_dslx", + tags = ["manual"], + verilog_file = "block_header_dec.v", +) + +xls_benchmark_ir( + name = "block_header_dec_opt_ir_benchmark", + src = ":block_header_dec_verilog.opt.ir", + benchmark_ir_args = block_header_dec_codegen_args | { + "pipeline_stages": "10", + "top": "__block_header_dec__BlockHeaderDecoderInst__BlockHeaderDecoder_0__16_64_next", + }, + tags = ["manual"], +) + +verilog_library( + name = "block_header_dec_verilog_lib", + srcs = [ + ":block_header_dec.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "block_header_dec_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "BlockHeaderDec", + deps = [ + ":block_header_dec_verilog_lib", + ], +) + +benchmark_synth( + name = "block_header_dec_benchmark_synth", + synth_target = ":block_header_dec_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "block_header_dec_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":block_header_dec_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + xls_dslx_library( name = "raw_block_dec_dslx", srcs = [ diff --git a/xls/modules/zstd/block_header_dec.x b/xls/modules/zstd/block_header_dec.x new file mode 100644 index 0000000000..45c69e921c --- /dev/null +++ b/xls/modules/zstd/block_header_dec.x @@ -0,0 +1,293 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import xls.modules.zstd.block_header as block_header; +import xls.modules.zstd.common as common; +import xls.modules.zstd.memory.mem_reader as mem_reader; + +type BlockSize = common::BlockSize; +type BlockType = common::BlockType; +type BlockHeader = block_header::BlockHeader; + +pub struct BlockHeaderDecoderReq { + addr: uN[ADDR_W], +} + +pub enum BlockHeaderDecoderStatus: u2 { + OKAY = 0, + CORRUPTED = 1, + MEMORY_ACCESS_ERROR = 2, +} + +pub struct BlockHeaderDecoderResp { + status: BlockHeaderDecoderStatus, + header: BlockHeader, + rle_symbol: u8, +} + +pub proc BlockHeaderDecoder { + type Req = BlockHeaderDecoderReq; + type Resp = BlockHeaderDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + type Status = BlockHeaderDecoderStatus; + type Length = uN[ADDR_W]; + type Addr = uN[ADDR_W]; + + req_r: chan in; + resp_s: chan out; + mem_req_s: chan out; + mem_resp_r: chan in; + + config ( + req_r: chan in, + resp_s: chan out, + mem_req_s: chan out, + mem_resp_r: chan in, + ) { + (req_r, resp_s, mem_req_s, mem_resp_r) + } + + init { } + + next (state: ()) { + let tok0 = join(); + + // receive request + let (tok1_0, req, req_valid) = recv_non_blocking(tok0, req_r, zero!()); + + // send memory read request + let mem_req = MemReaderReq {addr: req.addr, length: Length:4 }; + let tok2_0 = send_if(tok1_0, mem_req_s, req_valid, mem_req); + + // receive memory read response + let (tok1_1, mem_resp, mem_resp_valid) = recv_non_blocking(tok0, mem_resp_r, zero!()); + + let header = block_header::extract_block_header(mem_resp.data as u24); + let rle_symbol = mem_resp.data[u32:24 +: u8]; + let status = match ( mem_resp.status == MemReaderStatus::OKAY, header.btype != BlockType::RESERVED) { + (true, true) => Status::OKAY, + (true, false) => Status::CORRUPTED, + ( _, _) => Status::MEMORY_ACCESS_ERROR, + }; + + let resp = Resp { status, header, rle_symbol }; + let tok2_1 = send_if(tok1_1, resp_s, mem_resp_valid, resp); + } +} + +const INST_DATA_W = u32:64; +const INST_ADDR_W = u32:16; + +proc BlockHeaderDecoderInst { + type Req = BlockHeaderDecoderReq; + type Resp = BlockHeaderDecoderResp; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + config ( + req_r: chan in, + resp_s: chan out, + mem_req_s: chan out, + mem_resp_r: chan in, + ) { + spawn BlockHeaderDecoder( req_r, resp_s, mem_req_s, mem_resp_r); + } + + init { } + next (state: ()) { } +} + +const TEST_DATA_W = u32:32; +const TEST_ADDR_W = u32:32; + +fn header_to_raw(header: BlockHeader, rle_symbol: u8) -> u32 { + rle_symbol ++ header.size ++ (header.btype as u2) ++ header.last +} + + +#[test_proc] +proc BlockHeaderDecoderTest { + type Req = BlockHeaderDecoderReq; + type Resp = BlockHeaderDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + type Data = uN[TEST_DATA_W]; + type Addr = uN[TEST_ADDR_W]; + type Length = uN[TEST_ADDR_W]; + + terminator: chan out; + + req_s: chan out; + resp_r: chan in; + + mem_req_r: chan in; + mem_resp_s: chan out; + + config (terminator: chan out) { + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + let (mem_req_s, mem_req_r) = chan("mem_req"); + let (mem_resp_s, mem_resp_r) = chan("mem_resp"); + + spawn BlockHeaderDecoder ( + req_r, resp_s, mem_req_s, mem_resp_r + ); + + (terminator, req_s, resp_r, mem_req_r, mem_resp_s) + } + + init { } + + next (state: ()) { + const LENGTH = Length:4; + + let tok = join(); + + // Test Raw + let addr = Addr:0x1234; + let header = BlockHeader { size: BlockSize:0x100, btype: BlockType::RAW, last: true}; + let rle_symbol = u8:0; + + let req = Req { addr }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr, length: LENGTH }); + + let mem_resp = MemReaderResp { + status: MemReaderStatus::OKAY, + data: checked_cast(header_to_raw(header, rle_symbol)), + length: LENGTH, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: BlockHeaderDecoderStatus::OKAY, + header: header, + rle_symbol: rle_symbol + }); + + // Test RLE + let addr = Addr:0x2000; + let header = BlockHeader { size: BlockSize:0x40, btype: BlockType::RLE, last: false}; + let rle_symbol = u8:123; + + let req = Req { addr }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr, length: LENGTH }); + + let mem_resp = MemReaderResp { + status: MemReaderStatus::OKAY, + data: checked_cast(header_to_raw(header, rle_symbol)), + length: LENGTH, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: BlockHeaderDecoderStatus::OKAY, + header: header, + rle_symbol: rle_symbol + }); + + // Test COMPRESSED + let addr = Addr:0x2000; + let header = BlockHeader { size: BlockSize:0x40, btype: BlockType::COMPRESSED, last: true}; + let rle_symbol = u8:0; + + let req = Req { addr }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr, length: LENGTH }); + + let mem_resp = MemReaderResp { + status: MemReaderStatus::OKAY, + data: checked_cast(header_to_raw(header, rle_symbol)), + length: LENGTH, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: BlockHeaderDecoderStatus::OKAY, + header: header, + rle_symbol: rle_symbol + }); + + // Test RESERVED + let addr = Addr:0x2000; + let header = BlockHeader { size: BlockSize:0x40, btype: BlockType::RESERVED, last: true}; + let rle_symbol = u8:0; + + let req = Req { addr }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr, length: LENGTH }); + + let mem_resp = MemReaderResp { + status: MemReaderStatus::OKAY, + data: checked_cast(header_to_raw(header, rle_symbol)), + length: LENGTH, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: BlockHeaderDecoderStatus::CORRUPTED, + header: header, + rle_symbol: rle_symbol + }); + + // Test memory error + let addr = Addr:0x2000; + let header = BlockHeader { size: BlockSize:0x40, btype: BlockType::RESERVED, last: true}; + let rle_symbol = u8:0; + + let req = Req { addr }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr, length: LENGTH }); + + let mem_resp = MemReaderResp { + status: MemReaderStatus::ERROR, + data: checked_cast(header_to_raw(header, rle_symbol)), + length: LENGTH, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: BlockHeaderDecoderStatus::MEMORY_ACCESS_ERROR, + header: header, + rle_symbol: rle_symbol + }); + + send(tok, terminator, true); + } +} From 59f7d9d4e501428848825d9c36e56baec13c765a Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Tue, 8 Oct 2024 18:06:13 +0200 Subject: [PATCH 12/85] modules/zstd: Add RawBlockDecoder Co-authored-by: Pawel Czarnecki Signed-off-by: Maciej Torhan Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 25 ++- xls/modules/zstd/raw_block_dec.x | 312 +++++++++++++++++++++++++------ 2 files changed, 267 insertions(+), 70 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index ede9709eb9..79021e59b1 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -345,8 +345,8 @@ xls_dslx_library( "raw_block_dec.x", ], deps = [ - ":buffer_dslx", ":common_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -357,16 +357,15 @@ xls_dslx_test( tags = ["manual"], ) +raw_block_dec_codegen_args = common_codegen_args | { + "module_name": "RawBlockDecoder", + "pipeline_stages": "1", +} + xls_dslx_verilog( name = "raw_block_dec_verilog", - codegen_args = { - "module_name": "RawBlockDecoder", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "use_system_verilog": "false", - }, - dslx_top = "RawBlockDecoder", + codegen_args = raw_block_dec_codegen_args, + dslx_top = "RawBlockDecoderInst", library = ":raw_block_dec_dslx", tags = ["manual"], verilog_file = "raw_block_dec.v", @@ -375,9 +374,9 @@ xls_dslx_verilog( xls_benchmark_ir( name = "raw_block_dec_opt_ir_benchmark", src = ":raw_block_dec_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", + benchmark_ir_args = raw_block_dec_codegen_args | { + "pipeline_stages": "10", + "top": "__raw_block_dec__RawBlockDecoderInst__RawBlockDecoder_0__32_32_next", }, tags = ["manual"], ) @@ -408,7 +407,7 @@ benchmark_synth( place_and_route( name = "raw_block_dec_place_and_route", - clock_period = "750", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", diff --git a/xls/modules/zstd/raw_block_dec.x b/xls/modules/zstd/raw_block_dec.x index a3656011b0..669b66d5b1 100644 --- a/xls/modules/zstd/raw_block_dec.x +++ b/xls/modules/zstd/raw_block_dec.x @@ -17,6 +17,7 @@ // https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.2.2 import xls.modules.zstd.common as common; +import xls.modules.zstd.memory.mem_reader as mem_reader; type BlockDataPacket = common::BlockDataPacket; type BlockPacketLength = common::BlockPacketLength; @@ -26,92 +27,289 @@ type CopyOrMatchContent = common::CopyOrMatchContent; type CopyOrMatchLength = common::CopyOrMatchLength; type SequenceExecutorMessageType = common::SequenceExecutorMessageType; -struct RawBlockDecoderState { - prev_id: u32, // ID of the previous block - prev_last: bool, // if the previous packet was the last one that makes up the whole block - prev_valid: bool, // if prev_id and prev_last contain valid data +pub struct RawBlockDecoderReq { + id: u32, + addr: uN[ADDR_W], + length: uN[ADDR_W], + last_block: bool, } -const ZERO_RAW_BLOCK_DECODER_STATE = zero!(); +pub enum RawBlockDecoderStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +pub struct RawBlockDecoderResp { + status: RawBlockDecoderStatus, +} + +struct RawBlockDecoderState { + id: u32, // ID of the block + last_block: bool, // if the block is the last one +} // RawBlockDecoder is responsible for decoding Raw Blocks, // it should be a part of the ZSTD Decoder pipeline. -pub proc RawBlockDecoder { - input_r: chan in; - output_s: chan out; +pub proc RawBlockDecoder { + type Req = RawBlockDecoderReq; + type Resp = RawBlockDecoderResp; + type Output = ExtendedBlockDataPacket; + type Status = RawBlockDecoderStatus; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + type State = RawBlockDecoderState; - init { (ZERO_RAW_BLOCK_DECODER_STATE) } + // decoder input + req_r: chan in; + resp_s: chan out; + + // decoder output + output_s: chan out; + + // memory interface + mem_req_s: chan out; + mem_resp_r: chan in; + + init { zero!() } config( - input_r: chan in, - output_s: chan out - ) {(input_r, output_s)} + req_r: chan in, + resp_s: chan out, + output_s: chan out, - next(state: RawBlockDecoderState) { - let tok = join(); - let (tok, data) = recv(tok, input_r); - if state.prev_valid && (data.id != state.prev_id) && (state.prev_last == false) { - trace_fmt!("ID changed but previous packet have no last!"); - fail!("no_last", ()); - } else {}; - - let output_data = ExtendedBlockDataPacket { - // Decoded RAW block is always a literal + mem_req_s: chan out, + mem_resp_r: chan in, + ) { + ( + req_r, resp_s, output_s, + mem_req_s, mem_resp_r, + ) + } + + next(state: State) { + let tok0 = join(); + + // receive request + let (tok1_0, req, req_valid) = recv_non_blocking(tok0, req_r, zero!>()); + + // update ID and last in state + let state = if req_valid { + State { id: req.id, last_block: req.last_block} + } else { state }; + + // send memory read request + let req = MemReaderReq { addr: req.addr, length: req.length }; + let tok2_0 = send_if(tok1_0, mem_req_s, req_valid, req); + + // receive memory read response + let (tok1_1, mem_resp, mem_resp_valid) = recv_non_blocking(tok0, mem_resp_r, zero!()); + let mem_resp_error = (mem_resp.status != MemReaderStatus::OKAY); + + // prepare output data, decoded RAW block is always a literal + let output_data = Output { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { - last: data.last, - last_block: data.last_block, - id: data.id, - data: data.data as BlockData, - length: data.length as BlockPacketLength, + last: mem_resp.last, + last_block: state.last_block, + id: state.id, + data: checked_cast(mem_resp.data), + length: checked_cast(mem_resp.length ++ u3:0), }, }; - let tok = send(tok, output_s, output_data); + // send output data + let mem_resp_correct = mem_resp_valid && !mem_resp_error; + let tok2_1 = send_if(tok1_1, output_s, mem_resp_correct, output_data); + + // send response after block end + let resp = if mem_resp_correct { + Resp { status: Status::OKAY } + } else { + Resp { status: Status::ERROR } + }; + + let do_send_resp = mem_resp_valid && mem_resp.last; + let tok2_2 = send_if(tok1_1, resp_s, do_send_resp, resp); - RawBlockDecoderState { - prev_valid: true, - prev_id: output_data.packet.id, - prev_last: output_data.packet.last - } + state } } +const INST_DATA_W = u32:32; +const INST_ADDR_W = u32:32; + +pub proc RawBlockDecoderInst { + type Req = RawBlockDecoderReq; + type Resp = RawBlockDecoderResp; + type Output = ExtendedBlockDataPacket; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + config ( + req_r: chan in, + resp_s: chan out, + output_s: chan out, + mem_req_s: chan out, + mem_resp_r: chan in, + ) { + spawn RawBlockDecoder( + req_r, resp_s, output_s, mem_req_s, mem_resp_r + ); + } + + init { } + + next (state: ()) { } +} + +const TEST_DATA_W = u32:64; +const TEST_ADDR_W = u32:32; + #[test_proc] proc RawBlockDecoderTest { + type Req = RawBlockDecoderReq; + type Resp = RawBlockDecoderResp; + type Output = ExtendedBlockDataPacket; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type Data = uN[TEST_DATA_W]; + type Addr = uN[TEST_ADDR_W]; + type Length = uN[TEST_ADDR_W]; + terminator: chan out; - dec_input_s: chan out; - dec_output_r: chan in; + + req_s: chan out; + resp_r: chan in; + output_r: chan in; + + mem_req_r: chan in; + mem_resp_s: chan out; config(terminator: chan out) { - let (dec_input_s, dec_input_r) = chan("dec_input"); - let (dec_output_s, dec_output_r) = chan("dec_output"); - spawn RawBlockDecoder(dec_input_r, dec_output_s); - (terminator, dec_input_s, dec_output_r) + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (output_s, output_r) = chan("output"); + + let (mem_req_s, mem_req_r) = chan("mem_req"); + let (mem_resp_s, mem_resp_r) = chan("mem_resp"); + + spawn RawBlockDecoder( + req_r, resp_s, output_s, mem_req_s, mem_resp_r + ); + + (terminator, req_s, resp_r, output_r, mem_req_r, mem_resp_s) } init { } next(state: ()) { + let tok = join(); - let data_to_send: BlockDataPacket[5] = [ - BlockDataPacket { id: u32:1, last: u1:false, last_block: u1:false, data: BlockData:1, length: BlockPacketLength:32 }, - BlockDataPacket { id: u32:1, last: u1:false, last_block: u1:false, data: BlockData:2, length: BlockPacketLength:32 }, - BlockDataPacket { id: u32:1, last: u1:true, last_block: u1:false, data: BlockData:3, length: BlockPacketLength:32 }, - BlockDataPacket { id: u32:2, last: u1:false, last_block: u1:false, data: BlockData:4, length: BlockPacketLength:32 }, - BlockDataPacket { id: u32:2, last: u1:true, last_block: u1:true, data: BlockData:5, length: BlockPacketLength:32 }, - ]; - - let tok = for ((_, data), tok): ((u32, BlockDataPacket), token) in enumerate(data_to_send) { - let tok = send(tok, dec_input_s, data); - let (tok, received_data) = recv(tok, dec_output_r); - let expected_data = ExtendedBlockDataPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - packet: data, - }; - assert_eq(expected_data, received_data); - (tok) - }(tok); + + // Test 0 + let req = Req { id: u32:0, last_block: false, addr: Addr:0, length: Length:8 }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr: Addr:0, length: Length:8 }); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0x1122_3344, + length: Length:8, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: true, + last_block: false, + id: u32:0, + data: Data:0x1122_3344, + length: Length:64, + }, + }); + + // Test 1 + let req = Req { id: u32:1, last_block: true, addr: Addr:0x1001, length: Length:15 }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr: Addr:0x1001, length: Length:15 }); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0x1122_3344_5566_7788, + length: Length:8, + last: false + }; + let tok = send(tok, mem_resp_s, mem_resp); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0xAA_BBCC_DDEE_FF99, + length: Length:7, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: false, + last_block: true, + id: u32:1, + data: Data:0x1122_3344_5566_7788, + length: Length:64, + }, + }); + + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: true, + last_block: true, + id: u32:1, + data: Data:0xAA_BBCC_DDEE_FF99, + length: Length:56, + }, + }); + + // Test 2 + let req = Req {id: u32:2, last_block: false, addr: Addr:0x2000, length: Length:0 }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr: Addr:0x2000, length: Length:0 }); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0x0, + length: Length:0, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: true, + last_block: false, + id: u32:2, + data: Data:0x0, + length: Length:0, + }, + }); send(tok, terminator, true); } From 978a8e0d3830be4326ffc9626415ee7149cc6996 Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Tue, 8 Oct 2024 17:59:46 +0200 Subject: [PATCH 13/85] modules/zstd: Add RleBlockDecoder Co-authored-by: Pawel Czarnecki Co-authored-by: Robert Winkler Signed-off-by: Maciej Torhan Signed-off-by: Pawel Czarnecki Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 33 +- xls/modules/zstd/rle_block_dec.x | 844 +++++++------------------------ 2 files changed, 190 insertions(+), 687 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 79021e59b1..255418a161 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -423,10 +423,7 @@ xls_dslx_library( "rle_block_dec.x", ], deps = [ - ":buffer_dslx", ":common_dslx", - "//xls/modules/rle:rle_common_dslx", - "//xls/modules/rle:rle_dec_dslx", ], ) @@ -437,22 +434,16 @@ xls_dslx_test( tags = ["manual"], ) +rle_block_dec_codegen_args = common_codegen_args | { + "module_name": "RleBlockDecoder", + "pipeline_stages": "1", +} + xls_dslx_verilog( name = "rle_block_dec_verilog", - codegen_args = { - "module_name": "RleBlockDecoder", - "delay_model": "asap7", - "pipeline_stages": "3", - "reset": "rst", - "use_system_verilog": "false", - "fifo_module": "", - "materialize_internal_fifos": "true", - }, - dslx_top = "RleBlockDecoder", + codegen_args = rle_block_dec_codegen_args, + dslx_top = "RleBlockDecoderInst", library = ":rle_block_dec_dslx", - opt_ir_args = { - "top": "__rle_block_dec__RleBlockDecoder__BatchPacker_0_next", - }, tags = ["manual"], verilog_file = "rle_block_dec.v", ) @@ -460,11 +451,9 @@ xls_dslx_verilog( xls_benchmark_ir( name = "rle_block_dec_opt_ir_benchmark", src = ":rle_block_dec_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "3", - "delay_model": "asap7", - "fifo_module": "", - "materialize_internal_fifos": "true", + benchmark_ir_args = rle_block_dec_codegen_args | { + "pipeline_stages": "10", + "top": "__rle_block_dec__RleBlockDecoderInst__RleBlockDecoder_0__64_next", }, tags = ["manual"], ) @@ -495,7 +484,7 @@ benchmark_synth( place_and_route( name = "rle_block_dec_place_and_route", - clock_period = "750", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", diff --git a/xls/modules/zstd/rle_block_dec.x b/xls/modules/zstd/rle_block_dec.x index 232d9a6381..c5529c978b 100644 --- a/xls/modules/zstd/rle_block_dec.x +++ b/xls/modules/zstd/rle_block_dec.x @@ -12,44 +12,10 @@ // See the License for the specific language governing permissions and // limitations under the License. -// This file contains the implementation of RleBlockDecoder responsible for decoding -// ZSTD RLE Blocks. More Information about Rle Block's format can be found in: -// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.2.2 -// -// The implementation consist of 3 procs: -// * RleDataPacker -// * RunLengthDecoder -// * BatchPacker -// Connections between those is represented on the diagram below: -// -// RleBlockDecoder -// ┌─────────────────────────────────────────────────────────────┐ -// │ RleDataPacker RunLengthDecoder BatchPacker │ -// │ ┌───────────────┐ ┌──────────────────┐ ┌─────────────┐ │ -// ───┼─►│ ├──►│ ├──►│ ├─┼──► -// │ └───────┬───────┘ └──────────────────┘ └─────────────┘ │ -// │ │ ▲ │ -// │ │ SynchronizationData │ │ -// │ └─────────────────────────────────────────┘ │ -// └─────────────────────────────────────────────────────────────┘ -// -// RleDataPacker is responsible for receiving the incoming packets of block data, converting -// those to format accepted by RunLengthDecoder and passing the data to the actual decoder block. -// It also extracts from the input packets the synchronization data like block_id and last_block -// and then passes those to BatchPacker proc. -// RunLengthDecoder decodes RLE blocks and outputs one symbol for each transaction on output -// channel. -// BatchPacker then gathers those symbols into packets, appends synchronization data received from -// RleDataPacker and passes such packets to the output of the RleBlockDecoder. +import std; import xls.modules.zstd.common; -import xls.modules.rle.rle_dec; -import xls.modules.rle.rle_common; -const SYMBOL_WIDTH = common::SYMBOL_WIDTH; -const BLOCK_SIZE_WIDTH = common::BLOCK_SIZE_WIDTH; -const DATA_WIDTH = common::DATA_WIDTH; -const BATCH_SIZE = DATA_WIDTH / SYMBOL_WIDTH; type BlockDataPacket = common::BlockDataPacket; type BlockPacketLength = common::BlockPacketLength; @@ -61,696 +27,244 @@ type CopyOrMatchContent = common::CopyOrMatchContent; type CopyOrMatchLength = common::CopyOrMatchLength; type SequenceExecutorMessageType = common::SequenceExecutorMessageType; -type RleInput = rle_common::CompressedData; -type RleOutput = rle_common::PlainData; -type Symbol = bits[SYMBOL_WIDTH]; -type SymbolCount = BlockSize; -struct BlockSyncData { - last_block: bool, - count: SymbolCount, - id: u32 +pub enum RleBlockDecoderStatus: u1 { + OKAY = 0, } -proc RleDataPacker { - block_data_r: chan in; - rle_data_s: chan out; - sync_s: chan out; - - config( - block_data_r: chan in, - rle_data_s: chan out, - sync_s: chan out - ) { - (block_data_r, rle_data_s, sync_s) - } - - init { } - - next(state: ()) { - let tok = join(); - let (tok, input) = recv(tok, block_data_r); - let rle_dec_data = RleInput { - symbol: input.data as Symbol, count: input.length as SymbolCount, last: true - }; - // send RLE packet for decoding unless it has symbol count == 0 - let send_always = rle_dec_data.count != SymbolCount:0; - let data_tok = send_if(tok, rle_data_s, send_always, rle_dec_data); - let sync_data = BlockSyncData { last_block: input.last_block, count: rle_dec_data.count, id: input.id }; - // send last block packet even if it has symbol count == 0 - let sync_tok = send(data_tok, sync_s, sync_data); - } +pub struct RleBlockDecoderReq { + id: u32, + symbol: u8, + length: BlockSize, + last_block: bool, } -type RleTestVector = (Symbol, SymbolCount); - -#[test_proc] -proc RleDataPacker_test { - terminator: chan out; - in_s: chan out; - out_r: chan in; - sync_r: chan in; - - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); - let (sync_s, sync_r) = chan("sync"); - - spawn RleDataPacker(in_r, out_s, sync_s); - - (terminator, in_s, out_r, sync_r) - } - - init { } - - next(state: ()) { - let tok = join(); - let EncodedRleBlocks: RleTestVector[6] = [ - (Symbol:0x1, SymbolCount:0x1), - (Symbol:0x2, SymbolCount:0x2), - (Symbol:0x3, SymbolCount:0x4), - (Symbol:0x4, SymbolCount:0x8), - (Symbol:0x5, SymbolCount:0x10), - (Symbol:0x6, SymbolCount:0x1F), - ]; - let tok = for ((counter, block), tok): ((u32, RleTestVector), token) in enumerate(EncodedRleBlocks) { - let last_block = (counter == (array_size(EncodedRleBlocks) - u32:1)); - let data_in = BlockDataPacket { - last: true, - last_block, - id: counter, - data: block.0 as BlockData, - length: block.1 as BlockPacketLength - }; - let tok = send(tok, in_s, data_in); - trace_fmt!("Sent #{} raw encoded block, {:#x}", counter + u32:1, data_in); - - let data_out = RleInput { - last: true, symbol: block.0 as Symbol, count: block.1 as BlockSize - }; - let (tok, dec_output) = recv(tok, out_r); - trace_fmt!("Received #{} packed rle encoded block, {:#x}", counter + u32:1, dec_output); - assert_eq(dec_output, data_out); - - let sync_out = BlockSyncData { - id: counter, - count: block.1, - last_block: counter == (array_size(EncodedRleBlocks) - u32:1), - }; - let (tok, sync_output) = recv(tok, sync_r); - trace_fmt!("Received #{} synchronization data, {:#x}", counter + u32:1, sync_output); - assert_eq(sync_output, sync_out); - (tok) - }(tok); - send(tok, terminator, true); - } +pub struct RleBlockDecoderResp { + status: RleBlockDecoderStatus } -#[test_proc] -proc RleDataPacker_empty_blocks_test { - terminator: chan out; - in_s: chan out; - out_r: chan in; - sync_r: chan in; - - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); - let (sync_s, sync_r) = chan("sync"); - - spawn RleDataPacker(in_r, out_s, sync_s); - - (terminator, in_s, out_r, sync_r) - } - - init { } - - next(state: ()) { - let tok = join(); - let EncodedRleBlocks: RleTestVector[8] = [ - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0x1, SymbolCount:0x1), - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0x3, SymbolCount:0x4), - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0x5, SymbolCount:0x10), - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0xFF, SymbolCount:0x0), - ]; - let tok = for ((counter, block), tok): ((u32, RleTestVector), token) in enumerate(EncodedRleBlocks) { - let last_block = (counter == (array_size(EncodedRleBlocks) - u32:1)); - let data_in = BlockDataPacket { - last: true, - last_block, - id: counter, - data: block.0 as BlockData, - length: block.1 as BlockPacketLength - }; - let tok = send(tok, in_s, data_in); - trace_fmt!("Sent #{} raw encoded block, {:#x}", counter + u32:1, data_in); - (tok) - }(tok); - - let RleInputs: RleInput[3] = [ - RleInput {last: true, symbol: Symbol:0x1, count: BlockSize:0x1}, - RleInput {last: true, symbol: Symbol:0x3, count: BlockSize:0x4}, - RleInput {last: true, symbol: Symbol:0x5, count: BlockSize:0x10}, - ]; - let tok = for ((counter, rle_in), tok): ((u32, RleInput), token) in enumerate(RleInputs) { - let (tok, dec_output) = recv(tok, out_r); - trace_fmt!("Received #{} packed rle encoded block, {:#x}", counter + u32:1, dec_output); - assert_eq(dec_output, rle_in); - (tok) - }(tok); - - let BlockSyncDataInputs: BlockSyncData[8] = [ - BlockSyncData { id: 0, count: BlockSize:0x0, last_block: false }, - BlockSyncData { id: 1, count: BlockSize:0x1, last_block: false }, - BlockSyncData { id: 2, count: BlockSize:0x0, last_block: false }, - BlockSyncData { id: 3, count: BlockSize:0x4, last_block: false }, - BlockSyncData { id: 4, count: BlockSize:0x0, last_block: false }, - BlockSyncData { id: 5, count: BlockSize:0x10, last_block: false }, - BlockSyncData { id: 6, count: BlockSize:0x0, last_block: false }, - BlockSyncData { id: 7, count: BlockSize:0x0, last_block: true }, - ]; - let tok = for ((counter, sync_data), tok): ((u32, BlockSyncData), token) in enumerate(BlockSyncDataInputs) { - let (tok, sync_output) = recv(tok, sync_r); - trace_fmt!("Received #{} synchronization data, {:#x}", counter + u32:1, sync_output); - assert_eq(sync_output, sync_data); - (tok) - }(tok); - send(tok, terminator, true); - } +struct RleBlockDecoderState { + req: RleBlockDecoderReq, + req_valid: bool, } -struct BatchPackerState { - batch: BlockData, - symbols_in_batch: BlockPacketLength, - symbols_in_block: BlockPacketLength, - prev_last: bool, - prev_sync: BlockSyncData, -} +pub proc RleBlockDecoder { + type Req = RleBlockDecoderReq; + type Resp = RleBlockDecoderResp; + type Output = ExtendedBlockDataPacket; -const ZERO_BATCH_STATE = zero!(); -const ZERO_BLOCK_SYNC_DATA = zero!(); -const ZERO_RLE_OUTPUT = zero!(); -const EMPTY_RLE_OUTPUT = RleOutput {last: true, ..ZERO_RLE_OUTPUT}; + type State = RleBlockDecoderState; -proc BatchPacker { - rle_data_r: chan in; - sync_r: chan in; - block_data_s: chan out; + req_r: chan in; + resp_s: chan out; + output_s: chan out; - config( - rle_data_r: chan in, - sync_r: chan in, - block_data_s: chan out - ) { - (rle_data_r, sync_r, block_data_s) - } + config( req_r: chan in, + resp_s: chan out, + output_s: chan out, + ) { (req_r, resp_s, output_s) } - // Init the state to signal new batch to process - init { (BatchPackerState { prev_last: true, ..ZERO_BATCH_STATE }) } + init { zero!() } - next(state: BatchPackerState) { - let tok = join(); - trace_fmt!("start state: {:#x}", state); - let prev_expected_symbols_in_block = state.prev_sync.count as BlockPacketLength; - let symbols_in_batch = state.symbols_in_batch; - let symbols_in_block = state.symbols_in_block; - let block_in_progress = (symbols_in_block != prev_expected_symbols_in_block); - trace_fmt!("block_in_progress: {:#x}", block_in_progress); - - // Finished receiving RLE data of the previous block - // Proceed with receiving sync data for the next block - let start_new_block = !block_in_progress; - let (tok, sync_data) = recv_if(tok, sync_r, start_new_block, state.prev_sync); - if (start_new_block) { - trace_fmt!("received sync_data: {:#x}", sync_data); - } else { - trace_fmt!("got sync_data from the state: {:#x}", sync_data); - }; + next(state: State) { + const MAX_OUTPUT_SYMBOLS = (DATA_W / u32:8); + const MAX_LEN = MAX_OUTPUT_SYMBOLS as uN[common::BLOCK_SIZE_WIDTH]; - let expected_symbols_in_block = if (start_new_block) { sync_data.count as BlockPacketLength } else { prev_expected_symbols_in_block }; - trace_fmt!("expected_symbols_in_block: {:#x}", expected_symbols_in_block); + let tok0 = join(); - let batch = state.batch; - let empty_block = (expected_symbols_in_block == BlockPacketLength:0); - trace_fmt!("batch: {:#x}", batch); - trace_fmt!("empty_block: {:#x}", empty_block); + let (tok1, req) = recv_if(tok0, req_r, !state.req_valid, state.req); - let do_recv_rle = !empty_block && block_in_progress; - let default_rle_output = if (empty_block) { EMPTY_RLE_OUTPUT } else { ZERO_RLE_OUTPUT }; - let (tok, decoded_data) = recv_if(tok, rle_data_r, do_recv_rle, default_rle_output); - if (do_recv_rle) { - trace_fmt!("received rle_data: {:#x}", decoded_data); - } else { - trace_fmt!("got empty rle_data: {:#x}", decoded_data); - }; + let last = req.length <= MAX_LEN; + let length = if last { req.length } else { MAX_LEN }; + let data = unroll_for! (i, data): (u32, uN[DATA_W]) in range(u32:0, MAX_OUTPUT_SYMBOLS) { + bit_slice_update(data, i * u32:8, req.symbol) + }(uN[DATA_W]:0); - let (batch, symbols_in_batch, symbols_in_block) = if (do_recv_rle) { - // TODO: Improve performance: remove variable shift - let shift = symbols_in_batch << u32:3; // multiply by 8 bits - let updated_batch = batch | ((decoded_data.symbol as BlockData) << shift); - let updated_symbols_in_batch = symbols_in_batch + BlockPacketLength:1; - let updated_symbols_in_block = symbols_in_block + BlockPacketLength:1; - (updated_batch, updated_symbols_in_batch, updated_symbols_in_block) - } else { - (batch, symbols_in_batch, symbols_in_block) - }; - trace_fmt!("updated batch: {:#x}", batch); - trace_fmt!("updated symbols_in_batch: {:#x}", symbols_in_batch); - trace_fmt!("updated symbols_in_block: {:#x}", symbols_in_block); - - let block_in_progress = (symbols_in_block != expected_symbols_in_block); - trace_fmt!("updated block_in_progress: {:#x}", block_in_progress); - - // Last should not occur when batch is still being processed - assert!(!(!block_in_progress ^ decoded_data.last), "corrupted_decoding_flow"); - - let batch_full = symbols_in_batch >= BATCH_SIZE; - trace_fmt!("batch_full: {:#x}", batch_full); - // Send decoded RLE packet when - // - batch size reached the maximal size - // - RLE block decoding is finished - // - Decoded RLE block is empty and is the last block in ZSTD frame - let last = decoded_data.last || (sync_data.last_block && empty_block); - let do_send_batch = (batch_full || last); - trace_fmt!("do_send_batch: {:#x}", do_send_batch); - - let decoded_batch_data = ExtendedBlockDataPacket { - // Decoded RLE block is always a literal + let output = Output { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { - last: last, - last_block: sync_data.last_block, - id: sync_data.id, - data: batch as BlockData, - // length in bits - length: (symbols_in_batch << 3) as BlockPacketLength, + last, + last_block: req.last_block, + id: req.id, + data: checked_cast(data), + length: checked_cast(length << 3), } }; - let data_tok = - send_if(tok, block_data_s, do_send_batch, decoded_batch_data); - if (do_send_batch) { - trace_fmt!("sent decoded_batch_data: {:#x}", decoded_batch_data); - } else { - trace_fmt!("decoded_batch_data: {:#x}", decoded_batch_data); - }; - - let (new_batch, new_symbols_in_batch) = if (do_send_batch) { - (BlockData:0, BlockPacketLength:0) - } else { - (batch, symbols_in_batch) - }; + send_if(tok1, resp_s, last, zero!()); + send(tok1, output_s, output); - let (new_sync_data, new_symbols_in_block) = if (decoded_data.last || (sync_data.last_block && empty_block)) { - (ZERO_BLOCK_SYNC_DATA, BlockPacketLength:0) + if last { + zero!() } else { - (sync_data, symbols_in_block) - }; - - let new_state = BatchPackerState { - batch: new_batch, - symbols_in_batch: new_symbols_in_batch, - symbols_in_block: new_symbols_in_block, - prev_last: decoded_data.last, - prev_sync: new_sync_data - }; - - trace_fmt!("new_state: {:#x}", new_state); - - new_state + let length = req.length - MAX_LEN; + State { + req: Req { length, ..req }, + req_valid: true, + } + } } } -type BatchTestVector = (Symbol, bool); - -#[test_proc] -proc BatchPacker_test { - terminator: chan out; - in_s: chan out; - sync_s: chan out; - out_r: chan in; - - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (sync_s, sync_r) = chan("sync"); - let (out_s, out_r) = chan("out"); - spawn BatchPacker(in_r, sync_r, out_s); - - (terminator, in_s, sync_s, out_r) - } +const TEST_DATA_W = u32:64; - init { } +#[test_proc] +proc RleBlockDecoderTest { + type Req = RleBlockDecoderReq; + type Resp = RleBlockDecoderResp; + type Output = ExtendedBlockDataPacket; - next(state: ()) { - let tok = join(); - let SyncData: BlockSyncData[6] = [ - BlockSyncData { last_block: false, count: SymbolCount:1, id: u32:0 }, - BlockSyncData { last_block: false, count: SymbolCount:2, id: u32:1 }, - BlockSyncData { last_block: false, count: SymbolCount:4, id: u32:2 }, - BlockSyncData { last_block: false, count: SymbolCount:8, id: u32:3 }, - BlockSyncData { last_block: false, count: SymbolCount:16, id: u32:4 }, - BlockSyncData { last_block: true, count: SymbolCount:31, id: u32:5 }, - ]; - let tok = for ((counter, sync_data), tok): ((u32, BlockSyncData), token) in enumerate(SyncData) { - let tok = send(tok, sync_s, sync_data); - trace_fmt!("Sent #{} synchronization data, {:#x}", counter + u32:1, sync_data); - (tok) - }(tok); - - let DecodedRleBlocks: BatchTestVector[62] = [ - // 1st block - (Symbol:0x01, bool:true), - // 2nd block - (Symbol:0x02, bool:false), (Symbol:0x02, bool:true), - // 3rd block - (Symbol:0x03, bool:false), (Symbol:0x03, bool:false), (Symbol:0x03, bool:false), - (Symbol:0x03, bool:true), - // 4th block - (Symbol:0x04, bool:false), (Symbol:0x04, bool:false), (Symbol:0x04, bool:false), - (Symbol:0x04, bool:false), (Symbol:0x04, bool:false), (Symbol:0x04, bool:false), - (Symbol:0x04, bool:false), (Symbol:0x04, bool:true), - // 5th block - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:true), - // 6th block - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), (Symbol:0x06, bool:false), - (Symbol:0x06, bool:true), - ]; - let tok = for ((counter, test_data), tok): ((u32, BatchTestVector), token) in enumerate(DecodedRleBlocks) { - let symbol = test_data.0 as Symbol; - let last = test_data.1; - let data_in = RleOutput { symbol, last }; - let tok = send(tok, in_s, data_in); - trace_fmt!("Sent #{} decoded rle symbol, {:#x}", counter + u32:1, data_in); - (tok) - }(tok); - - let BatchedDecodedRleSymbols: ExtendedBlockDataPacket[10] = [ - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:0, data: BlockData:0x01, length: BlockPacketLength:8}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:1, data: BlockData:0x0202, length: BlockPacketLength:16}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:2, data: BlockData:0x03030303, length: BlockPacketLength:32}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:3, data: BlockData:0x0404040404040404, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:false, last_block: bool:false, id: u32:4, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:4, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:false, last_block: bool:true, id: u32:5, data: BlockData:0x0606060606060606, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:false, last_block: bool:true, id: u32:5, data: BlockData:0x0606060606060606, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:false, last_block: bool:true, id: u32:5, data: BlockData:0x0606060606060606, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:true, id: u32:5, data: BlockData:0x06060606060606, length: BlockPacketLength:56}}, - ]; - - let tok = for ((counter, expected), tok): ((u32, ExtendedBlockDataPacket), token) in enumerate(BatchedDecodedRleSymbols) { - let (tok, dec_output) = recv(tok, out_r); - trace_fmt!("Received #{} batched decoded rle symbols, {:#x}", counter + u32:1, dec_output); - assert_eq(dec_output, expected); - (tok) - }(tok); - send(tok, terminator, true); - } -} + type Data = uN[TEST_DATA_W]; + type Length = uN[common::BLOCK_SIZE_WIDTH]; -#[test_proc] -proc BatchPacker_empty_blocks_test { terminator: chan out; - in_s: chan out; - sync_s: chan out; - out_r: chan in; - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (sync_s, sync_r) = chan("sync"); - let (out_s, out_r) = chan("out"); + req_s: chan out; + resp_r: chan in; + output_r: chan in; + + config (terminator: chan out) { + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (output_s, output_r) = chan("output"); - spawn BatchPacker(in_r, sync_r, out_s); + spawn RleBlockDecoder( + req_r, resp_s, output_s + ); - (terminator, in_s, sync_s, out_r) + (terminator, req_s, resp_r, output_r) } - init { } + init { } - next(state: ()) { + next (state: ()) { let tok = join(); - let SyncData: BlockSyncData[8] = [ - BlockSyncData { last_block: false, count: SymbolCount:0, id: u32:0 }, - BlockSyncData { last_block: false, count: SymbolCount:1, id: u32:1 }, - BlockSyncData { last_block: false, count: SymbolCount:0, id: u32:2 }, - BlockSyncData { last_block: false, count: SymbolCount:4, id: u32:3 }, - BlockSyncData { last_block: false, count: SymbolCount:0, id: u32:4 }, - BlockSyncData { last_block: false, count: SymbolCount:16, id: u32:5 }, - BlockSyncData { last_block: false, count: SymbolCount:0, id: u32:6 }, - BlockSyncData { last_block: true, count: SymbolCount:0, id: u32:7 }, - ]; - let tok = for ((counter, sync_data), tok): ((u32, BlockSyncData), token) in enumerate(SyncData) { - let tok = send(tok, sync_s, sync_data); - trace_fmt!("Sent #{} synchronization data, {:#x}", counter + u32:1, sync_data); - (tok) - }(tok); - - let DecodedRleBlocks: BatchTestVector[21] = [ - // 0 block - // EMPTY - // 1st block - (Symbol:0x01, bool:true), - // 2nd block - // EMPTY - // 3rd block - (Symbol:0x03, bool:false), (Symbol:0x03, bool:false), (Symbol:0x03, bool:false), - (Symbol:0x03, bool:true), - // 4th block - // EMPTY - // 5th block - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), (Symbol:0x05, bool:false), - (Symbol:0x05, bool:true), - // 6th block - // EMPTY - // 7th block - // EMPTY - ]; - let tok = for ((counter, test_data), tok): ((u32, BatchTestVector), token) in enumerate(DecodedRleBlocks) { - let symbol = test_data.0 as Symbol; - let last = test_data.1; - let data_in = RleOutput { symbol, last }; - let tok = send(tok, in_s, data_in); - trace_fmt!("Sent #{} decoded rle symbol, {:#x}", counter + u32:1, data_in); - (tok) - }(tok); - - let BatchedDecodedRleSymbols: ExtendedBlockDataPacket[9] = [ - // 0 block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:0, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 1st block - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:1, data: BlockData:0x01, length: BlockPacketLength:8}}, - // 2nd block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:2, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 3rd block - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:3, data: BlockData:0x03030303, length: BlockPacketLength:32}}, - // 4th block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:4, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 5th block - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:false, last_block: bool:false, id: u32:5, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:5, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - // 6th block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:6, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 7th block - // EMPTY with LAST_BLOCK - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:true, id: u32:7, data: BlockData:0x0, length: BlockPacketLength:0}}, - ]; - - let tok = for ((counter, expected), tok): ((u32, ExtendedBlockDataPacket), token) in enumerate(BatchedDecodedRleSymbols) { - let (tok, dec_output) = recv(tok, out_r); - trace_fmt!("Received #{} batched decoded rle symbols, {:#x}", counter + u32:1, dec_output); - assert_eq(dec_output, expected); - (tok) - }(tok); - send(tok, terminator, true); - } -} -pub proc RleBlockDecoder { - input_r: chan in; - output_s: chan out; + let tok = send(tok, req_s, Req { id: u32:5, symbol: u8:0xAB, length: Length:0x28, last_block: true }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { status: RleBlockDecoderStatus::OKAY }); - config(input_r: chan in, output_s: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); - let (sync_s, sync_r) = chan("sync"); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: false, + last_block: true, + id: u32:5, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:64 + } + }); - spawn RleDataPacker(input_r, in_s, sync_s); - spawn rle_dec::RunLengthDecoder( - in_r, out_s); - spawn BatchPacker(out_r, sync_r, output_s); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: false, + last_block: true, + id: u32:5, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:64 + } + }); - (input_r, output_s) - } - init { } + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: false, + last_block: true, + id: u32:5, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:64 + } + }); - next(state: ()) { } -} -#[test_proc] -proc RleBlockDecoder_test { - terminator: chan out; - in_s: chan out; - out_r: chan in; + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: false, + last_block: true, + id: u32:5, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:64 + } + }); - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); - spawn RleBlockDecoder(in_r, out_s); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: true, + last_block: true, + id: u32:5, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:64 + } + }); - (terminator, in_s, out_r) - } + let tok = send(tok, req_s, Req { id: u32:1, symbol: u8:0xAB, length: Length:0, last_block: true }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { status: RleBlockDecoderStatus::OKAY }); - init { } + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: true, + last_block: true, + id: u32:1, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:0 + } + }); + + let tok = send(tok, req_s, Req { id: u32:10, symbol: u8:0xAB, length: Length:0, last_block: false }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { status: RleBlockDecoderStatus::OKAY }); + + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: true, + last_block: false, + id: u32:10, + data: BlockData:0xABAB_ABAB_ABAB_ABAB, + length: BlockPacketLength:0 + } + }); - next(state: ()) { - let tok = join(); - let EncodedRleBlocks: RleTestVector[6] = [ - (Symbol:0x1, SymbolCount:0x1), - (Symbol:0x2, SymbolCount:0x2), - (Symbol:0x3, SymbolCount:0x4), - (Symbol:0x4, SymbolCount:0x8), - (Symbol:0x5, SymbolCount:0x10), - (Symbol:0x6, SymbolCount:0x1F), - ]; - let tok = for ((counter, block), tok): ((u32, RleTestVector), token) in enumerate(EncodedRleBlocks) { - let last_block = (counter == (array_size(EncodedRleBlocks) - u32:1)); - let data_in = BlockDataPacket { - last: true, // RLE block fits into single packet, each will be last for given block - last_block, - id: counter, - data: block.0 as BlockData, - length: block.1 as BlockPacketLength - }; - let tok = send(tok, in_s, data_in); - trace_fmt!("Sent #{} raw encoded block, {:#x}", counter + u32:1, data_in); - (tok) - }(tok); - - let BatchedDecodedRleSymbols: ExtendedBlockDataPacket[10] = [ - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:true, last_block: bool:false, id: u32:0, data: BlockData:0x01, length: BlockPacketLength:8}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:true, last_block: bool:false, id: u32:1, data: BlockData:0x0202, length: BlockPacketLength:16}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:true, last_block: bool:false, id: u32:2, data: BlockData:0x03030303, length: BlockPacketLength:32}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:true, last_block: bool:false, id: u32:3, data: BlockData:0x0404040404040404, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:false, last_block: bool:false, id: u32:4, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:true, last_block: bool:false, id: u32:4, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:false, last_block: bool:true, id: u32:5, data: BlockData:0x0606060606060606, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:false, last_block: bool:true, id: u32:5, data: BlockData:0x0606060606060606, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:false, last_block: bool:true, id: u32:5, data: BlockData:0x0606060606060606, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { last: bool:true, last_block: bool:true, id: u32:5, data: BlockData:0x06060606060606, length: BlockPacketLength:56}}, - ]; - - let tok = for ((counter, expected), tok): ((u32, ExtendedBlockDataPacket), token) in enumerate(BatchedDecodedRleSymbols) { - let (tok, dec_output) = recv(tok, out_r); - trace_fmt!("Received #{} batched decoded rle symbols, {:#x}", counter + u32:1, dec_output); - assert_eq(dec_output, expected); - (tok) - }(tok); send(tok, terminator, true); } } -#[test_proc] -proc RleBlockDecoder_empty_blocks_test { - terminator: chan out; - in_s: chan out; - out_r: chan in; - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); +const INST_DATA_W = u32:64; - spawn RleBlockDecoder(in_r, out_s); +proc RleBlockDecoderInst { + type Req = RleBlockDecoderReq; + type Resp = RleBlockDecoderResp; + type Output = ExtendedBlockDataPacket; - (terminator, in_s, out_r) + type Data = uN[INST_DATA_W]; + type Length = uN[common::BLOCK_SIZE_WIDTH]; + + config( + req_r: chan in, + resp_s: chan out, + output_s: chan out, + ) { + spawn RleBlockDecoder(req_r, resp_s, output_s); } - init { } - next(state: ()) { - let tok = join(); - let EncodedRleBlocks: RleTestVector[8] = [ - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0x1, SymbolCount:0x1), - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0x3, SymbolCount:0x4), - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0x5, SymbolCount:0x10), - (Symbol:0xFF, SymbolCount:0x0), - (Symbol:0xFF, SymbolCount:0x0), - ]; - let tok = for ((counter, block), tok): ((u32, RleTestVector), token) in enumerate(EncodedRleBlocks) { - let last_block = (counter == (array_size(EncodedRleBlocks) - u32:1)); - let data_in = BlockDataPacket { - last: true, // RLE block fits into single packet, each will be last for given block - last_block, - id: counter, - data: block.0 as BlockData, - length: block.1 as BlockPacketLength - }; - let tok = send(tok, in_s, data_in); - trace_fmt!("Sent #{} raw encoded block, {:#x}", counter + u32:1, data_in); - (tok) - }(tok); - - let BatchedDecodedRleSymbols: ExtendedBlockDataPacket[9] = [ - // 0 block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:0, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 1st block - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:1, data: BlockData:0x01, length: BlockPacketLength:8}}, - // 2nd block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:2, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 3rd block - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:3, data: BlockData:0x03030303, length: BlockPacketLength:32}}, - // 4th block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:4, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 5th block - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:false, last_block: bool:false, id: u32:5, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:5, data: BlockData:0x0505050505050505, length: BlockPacketLength:64}}, - // 6th block - // EMPTY - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:false, id: u32:6, data: BlockData:0x0, length: BlockPacketLength:0}}, - // 7th block - // EMPTY with LAST_BLOCK - ExtendedBlockDataPacket {msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket {last: bool:true, last_block: bool:true, id: u32:7, data: BlockData:0x0, length: BlockPacketLength:0}}, - ]; - - let tok = for ((counter, expected), tok): ((u32, ExtendedBlockDataPacket), token) in enumerate(BatchedDecodedRleSymbols) { - let (tok, dec_output) = recv(tok, out_r); - trace_fmt!("Received #{} batched decoded rle symbols, {:#x}", counter + u32:1, dec_output); - assert_eq(dec_output, expected); - (tok) - }(tok); - send(tok, terminator, true); - } + init { } + + next (state: ()) {} } From 315d7e84ccd353284c9c62de8612393798f2efdd Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 8 Oct 2024 17:53:10 +0200 Subject: [PATCH 14/85] modules/zstd: Add ZstdDecoder Co-authored-by: Pawel Czarnecki Signed-off-by: Robert Winkler Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 312 ++---- xls/modules/zstd/zstd_dec.x | 1737 ++++++++++++++++++++++------- xls/modules/zstd/zstd_dec_test.cc | 297 ----- 3 files changed, 1406 insertions(+), 940 deletions(-) delete mode 100644 xls/modules/zstd/zstd_dec_test.cc diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 255418a161..c086942d22 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -21,7 +21,6 @@ load( "//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_ir", "xls_benchmark_verilog", - "xls_dslx_ir", "xls_dslx_library", "xls_dslx_test", "xls_dslx_verilog", @@ -696,229 +695,6 @@ place_and_route( target_die_utilization_percentage = "10", ) -xls_dslx_library( - name = "repacketizer_dslx", - srcs = [ - "repacketizer.x", - ], - deps = [ - ":common_dslx", - ], -) - -xls_dslx_test( - name = "repacketizer_dslx_test", - dslx_test_args = {"compare": "jit"}, - library = ":repacketizer_dslx", - tags = ["manual"], -) - -repacketizer_codegen_args = common_codegen_args | { - "module_name": "Repacketizer", - "clock_period_ps": "0", - "pipeline_stages": "2", -} - -xls_dslx_verilog( - name = "repacketizer_verilog", - codegen_args = repacketizer_codegen_args, - dslx_top = "Repacketizer", - library = ":repacketizer_dslx", - tags = ["manual"], - verilog_file = "repacketizer.v", -) - -xls_benchmark_ir( - name = "repacketizer_opt_ir_benchmark", - src = ":repacketizer_verilog.opt.ir", - benchmark_ir_args = repacketizer_codegen_args | { - "pipeline_stages": "10", - }, - tags = ["manual"], -) - -verilog_library( - name = "repacketizer_verilog_lib", - srcs = [ - ":repacketizer.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "repacketizer_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "Repacketizer", - deps = [ - ":repacketizer_verilog_lib", - ], -) - -benchmark_synth( - name = "repacketizer_benchmark_synth", - synth_target = ":repacketizer_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "repacketizer_place_and_route", - clock_period = CLOCK_PERIOD_PS, - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":repacketizer_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "10", -) - -xls_dslx_library( - name = "zstd_dec_dslx", - srcs = [ - "zstd_dec.x", - ], - deps = [ - ":block_header_dslx", - ":buffer_dslx", - ":common_dslx", - ":frame_header_dslx", - ":frame_header_test_dslx", - ":ram_printer_dslx", - ":repacketizer_dslx", - ":sequence_executor_dslx", - "//xls/examples:ram_dslx", - ], -) - -xls_dslx_verilog( - name = "zstd_dec_verilog", - codegen_args = { - "module_name": "ZstdDecoder", - "generator": "pipeline", - "delay_model": "asap7", - "ram_configurations": ",".join([ - "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, - ram_name = "ram{}".format(num), - rd_req = "zstd_dec__ram_rd_req_{}_s".format(num), - rd_resp = "zstd_dec__ram_rd_resp_{}_r".format(num), - wr_req = "zstd_dec__ram_wr_req_{}_s".format(num), - wr_resp = "zstd_dec__ram_wr_resp_{}_r".format(num), - ) - for num in range(7) - ]), - "pipeline_stages": "10", - "reset": "rst", - "reset_data_path": "true", - "reset_active_low": "false", - "reset_asynchronous": "true", - "flop_inputs": "false", - "flop_single_value_channels": "false", - "flop_outputs": "false", - "worst_case_throughput": "1", - "use_system_verilog": "false", - "fifo_module": "", - "materialize_internal_fifos": "true", - }, - dslx_top = "ZstdDecoder", - library = ":zstd_dec_dslx", - tags = ["manual"], - verilog_file = "zstd_dec.v", -) - -xls_dslx_ir( - name = "zstd_dec_test_ir", - dslx_top = "ZstdDecoderTest", - ir_file = "zstd_dec_test.ir", - library = ":zstd_dec_dslx", - tags = ["manual"], -) - -cc_test( - name = "zstd_dec_cc_test", - size = "large", - srcs = [ - "zstd_dec_test.cc", - ], - data = [ - ":zstd_dec_test.ir", - ], - shard_count = 50, - deps = [ - ":data_generator", - "//xls/common:xls_gunit_main", - "//xls/common/file:filesystem", - "//xls/common/file:get_runfile_path", - "//xls/common/status:matchers", - "//xls/common/status:ret_check", - "//xls/interpreter:channel_queue", - "//xls/interpreter:serial_proc_runtime", - "//xls/ir", - "//xls/ir:bits", - "//xls/ir:channel", - "//xls/ir:events", - "//xls/ir:ir_parser", - "//xls/ir:value", - "//xls/jit:jit_proc_runtime", - "@com_google_absl//absl/container:flat_hash_map", - "@com_google_absl//absl/log", - "@com_google_absl//absl/status:statusor", - "@com_google_absl//absl/types:span", - "@googletest//:gtest", - "@zstd", - ], -) - -xls_benchmark_ir( - name = "zstd_dec_opt_ir_benchmark", - src = ":zstd_dec_verilog.opt.ir", - benchmark_ir_args = { - #TODO: rewrite ram in opt_ir step to perform valid IR benchmark - "pipeline_stages": "1", - "delay_model": "asap7", - "fifo_module": "", - "materialize_internal_fifos": "true", - }, - tags = ["manual"], -) - -verilog_library( - name = "zstd_dec_verilog_lib", - srcs = [ - ":zstd_dec.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "zstd_dec_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "ZstdDecoder", - deps = [ - ":zstd_dec_verilog_lib", - ], -) - -benchmark_synth( - name = "zstd_dec_benchmark_synth", - synth_target = ":zstd_dec_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "zstd_dec_place_and_route", - clock_period = "750", - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":zstd_dec_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "10", -) - xls_dslx_library( name = "axi_csr_accessor_dslx", srcs = [ @@ -1071,3 +847,91 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "zstd_dec_dslx", + srcs = [ + "zstd_dec.x", + ], + deps = [ + ":axi_csr_accessor_dslx", + ":block_header_dec_dslx", + ":block_header_dslx", + ":common_dslx", + ":csr_config_dslx", + ":dec_mux_dslx", + ":frame_header_dec_dslx", + ":raw_block_dec_dslx", + ":repacketizer_dslx", + ":rle_block_dec_dslx", + ":sequence_executor_dslx", + "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + ], +) + +xls_dslx_test( + name = "zstd_dec_dslx_test", + library = ":zstd_dec_dslx", + tags = ["manual"], +) + +zstd_dec_internal_codegen_args = common_codegen_args | { + "module_name": "ZstdDecoderInternal", + "pipeline_stages": "2", +} + +xls_dslx_verilog( + name = "zstd_dec_internal_verilog", + codegen_args = zstd_dec_internal_codegen_args, + dslx_top = "ZstdDecoderInternalInst", + library = ":zstd_dec_dslx", + tags = ["manual"], + verilog_file = "zstd_dec_internal.v", +) + +xls_benchmark_ir( + name = "zstd_dec_internal_opt_ir_benchmark", + src = ":zstd_dec_internal_verilog.opt.ir", + benchmark_ir_args = { + "top": "__zstd_dec__ZstdDecoderInternalInst__ZstdDecoderInternal_0__16_64_8_4_16_next", + "pipeline_stages": "10", + }, + tags = ["manual"], +) + +verilog_library( + name = "zstd_dec_internal_verilog_lib", + srcs = [ + ":zstd_dec_internal.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "zstd_dec_internal_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "ZstdDecoderInternal", + deps = [ + ":zstd_dec_internal_verilog_lib", + ], +) + +benchmark_synth( + name = "zstd_dec_internal_benchmark_synth", + synth_target = ":zstd_dec_internal_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "zstd_dec_internal_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.35", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":zstd_dec_internal_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index d3dea6ae59..6e28bd8167 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -17,479 +17,1378 @@ // https://datatracker.ietf.org/doc/html/rfc8878 import std; +import xls.examples.ram; +import xls.modules.zstd.axi_csr_accessor; +import xls.modules.zstd.common; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.csr_config; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.frame_header_dec; import xls.modules.zstd.block_header; -import xls.modules.zstd.block_dec; +import xls.modules.zstd.block_header_dec; +import xls.modules.zstd.raw_block_dec; +import xls.modules.zstd.rle_block_dec; +import xls.modules.zstd.dec_mux; import xls.modules.zstd.sequence_executor; -import xls.modules.zstd.buffer as buff; -import xls.modules.zstd.common; -import xls.modules.zstd.frame_header; -import xls.modules.zstd.frame_header_test; -import xls.modules.zstd.magic; import xls.modules.zstd.repacketizer; -import xls.examples.ram; -type Buffer = buff::Buffer; -type BlockDataPacket = common::BlockDataPacket; -type BlockData = common::BlockData; type BlockSize = common::BlockSize; -type SequenceExecutorPacket = common::SequenceExecutorPacket; -type ZstdDecodedPacket = common::ZstdDecodedPacket; - -// TODO: all of this porboably should be in common.x -const TEST_WINDOW_LOG_MAX_LIBZSTD = frame_header_test::TEST_WINDOW_LOG_MAX_LIBZSTD; - -const ZSTD_RAM_ADDR_WIDTH = sequence_executor::ZSTD_RAM_ADDR_WIDTH; -const RAM_DATA_WIDTH = sequence_executor::RAM_DATA_WIDTH; -const RAM_NUM_PARTITIONS = sequence_executor::RAM_NUM_PARTITIONS; -const ZSTD_HISTORY_BUFFER_SIZE_KB = sequence_executor::ZSTD_HISTORY_BUFFER_SIZE_KB; - -const BUFFER_WIDTH = common::BUFFER_WIDTH; -const DATA_WIDTH = common::DATA_WIDTH; -const ZERO_FRAME_HEADER = frame_header::ZERO_FRAME_HEADER; -const ZERO_BLOCK_HEADER = block_header::ZERO_BLOCK_HEADER; - -enum ZstdDecoderStatus : u8 { - DECODE_MAGIC_NUMBER = 0, - DECODE_FRAME_HEADER = 1, - DECODE_BLOCK_HEADER = 2, - FEED_BLOCK_DECODER = 3, - DECODE_CHECKSUM = 4, - ERROR = 255, +type BlockType = common::BlockType; +type BlockHeader = block_header::BlockHeader; + +enum ZstdDecoderInternalFsm: u4 { + IDLE = 0, + READ_CONFIG = 1, + DECODE_FRAME_HEADER = 2, + DECODE_BLOCK_HEADER = 3, + DECODE_RAW_BLOCK = 4, + DECODE_RLE_BLOCK = 5, + DECODE_COMPRESSED_BLOCK = 6, + DECODE_CHECKSUM = 7, + FINISH = 8, + ERROR = 13, + INVALID = 15, } -struct ZstdDecoderState { - status: ZstdDecoderStatus, - buffer: Buffer, - frame_header: frame_header::FrameHeader, - block_size_bytes: BlockSize, - last: bool, - bytes_sent: BlockSize, +enum ZstdDecoderStatus: u3 { + OKAY = 0, + FINISHED = 1, + FRAME_HEADER_CORRUPTED = 2, + FRAME_HEADER_UNSUPPORTED_WINDOW_SIZE = 3, + BLOCK_HEADER_CORRUPTED = 4, } -const ZERO_DECODER_STATE = zero!(); - -fn decode_magic_number(state: ZstdDecoderState) -> (bool, BlockDataPacket, ZstdDecoderState) { - trace_fmt!("zstd_dec: decode_magic_number: DECODING NEW FRAME"); - trace_fmt!("zstd_dec: decode_magic_number: state: {:#x}", state); - trace_fmt!("zstd_dec: decode_magic_number: Decoding magic number"); - let magic_result = magic::parse_magic_number(state.buffer); - trace_fmt!("zstd_dec: decode_magic_number: magic_result: {:#x}", magic_result); - let new_state = match magic_result.status { - magic::MagicStatus::OK => ZstdDecoderState { - status: ZstdDecoderStatus::DECODE_FRAME_HEADER, - buffer: magic_result.buffer, - ..state - }, - magic::MagicStatus::CORRUPTED => ZstdDecoderState { - status: ZstdDecoderStatus::ERROR, - ..ZERO_DECODER_STATE - }, - magic::MagicStatus::NO_ENOUGH_DATA => state, - }; - trace_fmt!("zstd_dec: decode_magic_number: new_state: {:#x}", new_state); - - (false, zero!(), new_state) +enum Csr: u3 { + STATUS = 0, // Keeps the code describing the current state of the ZSTD Decoder + START = 1, // Writing 1 when decoder is in IDLE state starts the decoding process + RESET = 2, // Writing 1 will reset the decoder to the IDLE state + INPUT_BUFFER = 3, // Keeps the base address for the input buffer that is used for storing the frame to decode + OUTPUT_BUFFER = 4, // Keeps the base address for the output buffer, ZSTD Decoder will write the decoded frame into memory starting from this address. + WHO_AM_I = 5, // Contains the identification number of the ZSTD Decoder } -fn decode_frame_header(state: ZstdDecoderState) -> (bool, BlockDataPacket, ZstdDecoderState) { - trace_fmt!("zstd_dec: decode_frame_header: DECODING FRAME HEADER"); - trace_fmt!("zstd_dec: decode_frame_header: state: {:#x}", state); - let frame_header_result = frame_header::parse_frame_header(state.buffer); - trace_fmt!("zstd_dec: decode_frame_header: frame_header_result: {:#x}", frame_header_result); - let new_state = match frame_header_result.status { - frame_header::FrameHeaderStatus::OK => ZstdDecoderState { - status: ZstdDecoderStatus::DECODE_BLOCK_HEADER, - buffer: frame_header_result.buffer, - frame_header: frame_header_result.header, - ..state - }, - frame_header::FrameHeaderStatus::CORRUPTED => ZstdDecoderState { - status: ZstdDecoderStatus::ERROR, - ..ZERO_DECODER_STATE - }, - frame_header::FrameHeaderStatus::NO_ENOUGH_DATA => state, - frame_header::FrameHeaderStatus::UNSUPPORTED_WINDOW_SIZE => ZstdDecoderState { - status: ZstdDecoderStatus::ERROR, - ..ZERO_DECODER_STATE - }, - }; - trace_fmt!("zstd_dec: decode_frame_header: new_state: {:#x}", new_state); - - (false, zero!(), new_state) +fn csr(c: Csr) -> uN[LOG2_REGS_N] { + c as uN[LOG2_REGS_N] } -fn decode_block_header(state: ZstdDecoderState) -> (bool, BlockDataPacket, ZstdDecoderState) { - trace_fmt!("zstd_dec: decode_block_header: DECODING BLOCK HEADER"); - trace_fmt!("zstd_dec: decode_block_header: state: {:#x}", state); - let block_header_result = block_header::parse_block_header(state.buffer); - trace_fmt!("zstd_dec: decode_block_header: block_header_result: {:#x}", block_header_result); - let new_state = match block_header_result.status { - block_header::BlockHeaderStatus::OK => { - trace_fmt!("zstd_dec: BlockHeader: {:#x}", block_header_result.header); - match block_header_result.header.btype { - common::BlockType::RAW => ZstdDecoderState { - status: ZstdDecoderStatus::FEED_BLOCK_DECODER, - buffer: state.buffer, - block_size_bytes: block_header_result.header.size as BlockSize + BlockSize:3, - last: block_header_result.header.last, - bytes_sent: BlockSize:0, - ..state - }, - common::BlockType::RLE => ZstdDecoderState { - status: ZstdDecoderStatus::FEED_BLOCK_DECODER, - buffer: state.buffer, - block_size_bytes: BlockSize:4, - last: block_header_result.header.last, - bytes_sent: BlockSize:0, - ..state - }, - common::BlockType::COMPRESSED => ZstdDecoderState { - status: ZstdDecoderStatus::FEED_BLOCK_DECODER, - buffer: state.buffer, - block_size_bytes: block_header_result.header.size as BlockSize + BlockSize:3, - last: block_header_result.header.last, - bytes_sent: BlockSize:0, - ..state - }, - _ => { - fail!("impossible_case", state) - } - } - }, - block_header::BlockHeaderStatus::CORRUPTED => ZstdDecoderState { - status: ZstdDecoderStatus::ERROR, - ..ZERO_DECODER_STATE - }, - block_header::BlockHeaderStatus::NO_ENOUGH_DATA => state, - }; - trace_fmt!("zstd_dec: decode_block_header: new_state: {:#x}", new_state); - - (false, zero!(), new_state) +struct ZstdDecoderInternalState { + fsm: ZstdDecoderInternalFsm, + + // Reading CSRs + conf_cnt: uN[LOG2_REGS_N], + conf_send: bool, + input_buffer: uN[AXI_ADDR_W], + input_buffer_valid: bool, + output_buffer: uN[AXI_ADDR_W], + output_buffer_valid: bool, + + // Writing to CSRs + csr_wr_req: csr_config::CsrWrReq, + csr_wr_req_valid: bool, + + // BH address + bh_addr: uN[AXI_ADDR_W], + + // Block + block_addr: uN[AXI_ADDR_W], + block_length: uN[AXI_ADDR_W], + block_last: bool, + block_id: u32, + block_rle_symbol: u8, + + // Req + req_sent: bool, } -fn feed_block_decoder(state: ZstdDecoderState) -> (bool, BlockDataPacket, ZstdDecoderState) { - trace_fmt!("zstd_dec: feed_block_decoder: FEEDING BLOCK DECODER"); - trace_fmt!("zstd_dec: feed_block_decoder: state: {:#x}", state); - let remaining_bytes_to_send = state.block_size_bytes - state.bytes_sent; - trace_fmt!("zstd_dec: feed_block_decoder: remaining_bytes_to_send: {}", remaining_bytes_to_send); - let buffer_length_bytes = state.buffer.length >> 3; - trace_fmt!("zstd_dec: feed_block_decoder: buffer_length_bytes: {}", buffer_length_bytes); - let data_width_bytes = (DATA_WIDTH >> 3) as BlockSize; - trace_fmt!("zstd_dec: feed_block_decoder: data_width_bytes: {}", data_width_bytes); - let remaining_bytes_to_send_now = std::min(remaining_bytes_to_send, data_width_bytes); - trace_fmt!("zstd_dec: feed_block_decoder: remaining_bytes_to_send_now: {}", remaining_bytes_to_send_now); - if (buffer_length_bytes >= remaining_bytes_to_send_now as u32) { - let remaining_bits_to_send_now = (remaining_bytes_to_send_now as u32) << 3; - trace_fmt!("zstd_dec: feed_block_decoder: remaining_bits_to_send_now: {}", remaining_bits_to_send_now); - let last_packet = (remaining_bytes_to_send == remaining_bytes_to_send_now); - trace_fmt!("zstd_dec: feed_block_decoder: last_packet: {}", last_packet); - let (buffer_result, data_to_send) = buff::buffer_pop_checked(state.buffer, remaining_bits_to_send_now); - match buffer_result.status { - buff::BufferStatus::OK => { - let decoder_channel_data = BlockDataPacket { - last: last_packet, - last_block: state.last, - id: u32:0, - data: data_to_send[0: DATA_WIDTH as s32], - length: remaining_bits_to_send_now, +proc ZstdDecoderInternal< + AXI_DATA_W: u32, AXI_ADDR_W: u32, REGS_N: u32, + LOG2_REGS_N:u32 = {std::clog2(REGS_N)}, + HB_RAM_N:u32 = {u32:8}, +> { + + type State = ZstdDecoderInternalState; + type Fsm = ZstdDecoderInternalFsm; + type Reg = uN[LOG2_REGS_N]; + type Data = uN[AXI_DATA_W]; + type Addr = uN[AXI_ADDR_W]; + + type CsrRdReq = csr_config::CsrRdReq; + type CsrRdResp = csr_config::CsrRdResp; + type CsrWrReq = csr_config::CsrWrReq; + type CsrWrResp = csr_config::CsrWrResp; + type CsrChange = csr_config::CsrChange; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type FrameHeaderDecoderStatus = frame_header_dec::FrameHeaderDecoderStatus; + type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; + type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; + + type BlockHeaderDecoderStatus = block_header_dec::BlockHeaderDecoderStatus; + type BlockHeaderDecoderReq = block_header_dec::BlockHeaderDecoderReq; + type BlockHeaderDecoderResp = block_header_dec::BlockHeaderDecoderResp; + + type RawBlockDecoderStatus = raw_block_dec::RawBlockDecoderStatus; + type RawBlockDecoderReq = raw_block_dec::RawBlockDecoderReq; + type RawBlockDecoderResp = raw_block_dec::RawBlockDecoderResp; + + type RleBlockDecoderStatus = rle_block_dec::RleBlockDecoderStatus; + type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; + type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + + // CsrConfig + csr_rd_req_s: chan out; + csr_rd_resp_r: chan in; + csr_wr_req_s: chan out; + csr_wr_resp_r: chan in; + csr_change_r: chan in; + + // MemReader + FameHeaderDecoder + fh_req_s: chan out; + fh_resp_r: chan in; + + // MemReader + BlockHeaderDecoder + bh_req_s: chan out; + bh_resp_r: chan in; + + // MemReader + RawBlockDecoder + raw_req_s: chan out; + raw_resp_r: chan in; + + // MemReader + RleBlockDecoder + rle_req_s: chan out; + rle_resp_r: chan in; + + notify_s: chan<()> out; + + init { + zero!() + } + + config( + csr_rd_req_s: chan out, + csr_rd_resp_r: chan in, + csr_wr_req_s: chan out, + csr_wr_resp_r: chan in, + csr_change_r: chan in, + + // MemReader + FameHeaderDecoder + fh_req_s: chan out, + fh_resp_r: chan in, + + // MemReader + BlockHeaderDecoder + bh_req_s: chan out, + bh_resp_r: chan in, + + // MemReader + RawBlockDecoder + raw_req_s: chan out, + raw_resp_r: chan in, + + // MemReader + RleBlockDecoder + rle_req_s: chan out, + rle_resp_r: chan in, + + notify_s: chan<()> out, + ) { + ( + csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, + fh_req_s, fh_resp_r, + bh_req_s, bh_resp_r, + raw_req_s, raw_resp_r, + rle_req_s, rle_resp_r, + notify_s, + ) + } + + next (state: State) { + let tok0 = join(); + + const CSR_REQS = CsrRdReq[2]:[ + CsrRdReq {csr: csr(Csr::INPUT_BUFFER)}, + CsrRdReq {csr: csr(Csr::OUTPUT_BUFFER)} + ]; + + const CSR_REQS_MAX = checked_cast(array_size(CSR_REQS) - u32:1); + + let (tok1_0, csr_change, csr_change_valid) = recv_non_blocking(tok0, csr_change_r, zero!()); + let is_start = (csr_change_valid && (csr_change.csr == csr(Csr::START))); + + let do_send_csr_req = (state.fsm == Fsm::READ_CONFIG) && (!state.conf_send); + let csr_req = CSR_REQS[state.conf_cnt]; + let tok1_1 = send_if(tok0, csr_rd_req_s, do_send_csr_req, csr_req); + if do_send_csr_req { + trace_fmt!("[READ_CONFIG] Sending read request {:#x}", csr_req); + } else {}; + + let do_recv_csr_resp = (state.fsm == Fsm::READ_CONFIG); + let (tok1_2, csr_data, csr_data_valid) = recv_if_non_blocking(tok0, csr_rd_resp_r, do_recv_csr_resp, zero!()); + if csr_data_valid { + trace_fmt!("[READ_CONFIG] Received CSR data: {:#x}", csr_data); + } else {}; + + let do_send_fh_req = (state.fsm == Fsm::DECODE_FRAME_HEADER) && !state.req_sent; + let fh_req = FrameHeaderDecoderReq { addr: state.input_buffer }; + let tok1_3 = send_if(tok0, fh_req_s, do_send_fh_req, fh_req); + if do_send_fh_req { + trace_fmt!("[DECODE_FRAME_HEADER] Sending FH request {:#x}", fh_req); + } else {}; + + let do_recv_fh_resp = (state.fsm == Fsm::DECODE_FRAME_HEADER); + let (tok1_4, fh_resp, fh_resp_valid) = recv_if_non_blocking(tok0, fh_resp_r, do_recv_fh_resp, zero!()); + if fh_resp_valid { + trace_fmt!("[DECODE_FRAME_HEADER]: Received FH {:#x}", fh_resp); + } else {}; + + let do_send_notify = (state.fsm == Fsm::ERROR || state.fsm == Fsm::FINISH); + let tok = send_if(tok0, notify_s, do_send_notify, ()); + if do_send_notify { + trace_fmt!("[[NOTIFY]]"); + } else {}; + + let tok1_5 = send_if(tok0, csr_wr_req_s, state.csr_wr_req_valid, state.csr_wr_req); + let (tok, _, _) = recv_non_blocking(tok0, csr_wr_resp_r, zero!()); + if state.csr_wr_req_valid { + trace_fmt!("[[CSR_WR_REQ]] Request: {:#x}", state.csr_wr_req); + } else {}; + + let do_send_bh_req = (state.fsm == Fsm::DECODE_BLOCK_HEADER) && !state.req_sent; + let bh_req = BlockHeaderDecoderReq { addr: state.bh_addr }; + let tok1_6 = send_if(tok0, bh_req_s, do_send_bh_req, bh_req); + if do_send_bh_req { + trace_fmt!("[DECODE_BLOCK_HEADER]: Sending BH request: {:#x}", bh_req); + } else {}; + + let do_recv_bh_resp = (state.fsm == Fsm::DECODE_BLOCK_HEADER); + let (tok1_4, bh_resp, bh_resp_valid) = recv_if_non_blocking(tok0, bh_resp_r, do_recv_bh_resp, zero!()); + if bh_resp_valid { + trace_fmt!("[DECODE_BLOCK_HEADER]: Received BH {:#x}", bh_resp); + } else {}; + + let do_send_raw_req = (state.fsm == Fsm::DECODE_RAW_BLOCK) && !state.req_sent; + let raw_req = RawBlockDecoderReq { + id: state.block_id, + last_block: state.block_last, + addr: state.block_addr, + length: state.block_length, + }; + let tok1_6 = send_if(tok0, raw_req_s, do_send_raw_req, raw_req); + if do_send_raw_req { + trace_fmt!("[DECODE_RAW_BLOCK]: Sending RAW request: {:#x}", raw_req); + } else {}; + + let do_recv_raw_resp = (state.fsm == Fsm::DECODE_RAW_BLOCK); + let (tok1_7, raw_resp, raw_resp_valid) = recv_if_non_blocking(tok0, raw_resp_r, do_recv_raw_resp, zero!()); + if raw_resp_valid { + trace_fmt!("[DECODE_RAW_BLOCK]: Received RAW {:#x}", raw_resp); + } else {}; + + let do_send_rle_req = (state.fsm == Fsm::DECODE_RLE_BLOCK) && !state.req_sent; + let rle_req = RleBlockDecoderReq { + id: state.block_id, + symbol: state.block_rle_symbol, + length: checked_cast(state.block_length), + last_block: state.block_last, + }; + let tok1_7 = send_if(tok0, rle_req_s, do_send_rle_req, rle_req); + if do_send_rle_req { + trace_fmt!("[DECODE_RLE_BLOCK]: Sending RLE request: {:#x}", rle_req); + } else {}; + + let do_recv_rle_resp = (state.fsm == Fsm::DECODE_RLE_BLOCK); + let (tok1_8, rle_resp, rle_resp_valid) = recv_if_non_blocking(tok0, rle_resp_r, do_recv_rle_resp, zero!()); + if raw_resp_valid { + trace_fmt!("[DECODE_RLE_BLOCK]: Received RAW {:#x}", raw_resp); + } else {}; + + let new_state = match (state.fsm) { + Fsm::IDLE => { + trace_fmt!("[IDLE]"); + if is_start { + State { fsm: Fsm::READ_CONFIG, conf_cnt: CSR_REQS_MAX, ..zero!() } + } else { zero!() } + }, + + Fsm::READ_CONFIG => { + trace_fmt!("[READ_CONFIG]"); + let is_input_buffer_csr = (csr_data.csr == csr(Csr::INPUT_BUFFER)); + let input_buffer = if csr_data_valid && is_input_buffer_csr { checked_cast(csr_data.value) } else { state.input_buffer }; + let input_buffer_valid = if csr_data_valid && is_input_buffer_csr { true } else { state.input_buffer_valid }; + + let is_output_buffer_csr = (csr_data.csr == csr(Csr::OUTPUT_BUFFER)); + let output_buffer = if (csr_data_valid && is_output_buffer_csr) { checked_cast(csr_data.value) } else { state.output_buffer }; + let output_buffer_valid = if (csr_data_valid && is_output_buffer_csr) { true } else { state.output_buffer_valid }; + + let all_collected = input_buffer_valid & output_buffer_valid; + let fsm = if all_collected { Fsm::DECODE_FRAME_HEADER } else { Fsm::READ_CONFIG }; + + let conf_send = (state.conf_cnt == Reg:0); + let conf_cnt = if conf_send { Reg:0 } else {state.conf_cnt - Reg:1}; + + State { + fsm, conf_cnt, conf_send, input_buffer, input_buffer_valid, output_buffer, output_buffer_valid, + ..zero!() + } + }, + + Fsm::DECODE_FRAME_HEADER => { + trace_fmt!("[DECODE_FRAME_HEADER]"); + let error = (fh_resp.status != FrameHeaderDecoderStatus::OKAY); + + let csr_wr_req_valid = (fh_resp_valid && error); + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(fh_resp.status), + }; + + let fsm = match (fh_resp_valid, error) { + ( true, false) => Fsm::DECODE_BLOCK_HEADER, + ( true, true) => Fsm::ERROR, + ( _, _) => Fsm::DECODE_FRAME_HEADER, + }; + + let bh_addr = state.input_buffer + fh_resp.length as Addr; + let req_sent = if !fh_resp_valid && !error { true } else { false }; + State {fsm, csr_wr_req, csr_wr_req_valid, bh_addr, req_sent, ..state } + }, + + Fsm::DECODE_BLOCK_HEADER => { + trace_fmt!("[DECODE_BLOCK_HEADER]"); + let error = (bh_resp.status != BlockHeaderDecoderStatus::OKAY); + + let csr_wr_req_valid = (bh_resp_valid && error); + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(bh_resp.status), }; - let new_fsm_status = if (last_packet) { - if (state.last) { - if (state.frame_header.content_checksum_flag) { - ZstdDecoderStatus::DECODE_CHECKSUM - } else { - ZstdDecoderStatus::DECODE_MAGIC_NUMBER - } + + let fsm = match (bh_resp_valid, error, bh_resp.header.btype) { + ( true, false, BlockType::RAW ) => Fsm::DECODE_RAW_BLOCK, + ( true, false, BlockType::RLE ) => Fsm::DECODE_RLE_BLOCK, + ( true, false, BlockType::COMPRESSED) => Fsm::ERROR, + ( true, true, _) => Fsm::ERROR, + ( _, _, _) => Fsm::DECODE_BLOCK_HEADER, + }; + + let (block_addr, block_length, block_last, block_rle_symbol, bh_addr) = if bh_resp_valid { + let block_addr = state.bh_addr + Addr:3; + let block_length = checked_cast(bh_resp.header.size); + let block_rle_symbol = bh_resp.rle_symbol; + let bh_addr = if bh_resp.header.btype == BlockType::RLE { + block_addr + Addr:1 } else { - ZstdDecoderStatus::DECODE_BLOCK_HEADER - } + block_addr + block_length + }; + + trace_fmt!("bh_addr: {:#x}", bh_addr); + + (block_addr, block_length, bh_resp.header.last, block_rle_symbol, bh_addr) } else { - ZstdDecoderStatus::FEED_BLOCK_DECODER + (state.block_addr, state.block_length, state.block_last, state.block_rle_symbol, state.bh_addr) }; - trace_fmt!("zstd_dec: feed_block_decoder: packet to decode: {:#x}", decoder_channel_data); - let new_state = (true, decoder_channel_data, ZstdDecoderState { - bytes_sent: state.bytes_sent + remaining_bytes_to_send_now, - buffer: buffer_result.buffer, - status: new_fsm_status, + + let req_sent = if !bh_resp_valid && !error { true } else { false }; + State { + fsm, bh_addr, req_sent, + block_addr, block_length, block_last, block_rle_symbol, + csr_wr_req, csr_wr_req_valid, ..state - }); - trace_fmt!("zstd_dec: feed_block_decoder: new_state: {:#x}", new_state); - new_state + } }, - _ => { - fail!("should_not_happen_1", (false, zero!(), state)) - } - } - } else { - trace_fmt!("zstd_dec: feed_block_decoder: Not enough data for intermediate FEED_BLOCK_DECODER block dump"); - (false, zero!(), state) + + Fsm::DECODE_RAW_BLOCK => { + trace_fmt!("[DECODE_RAW_BLOCK]"); + + let error = (raw_resp.status != RawBlockDecoderStatus::OKAY); + + let csr_wr_req_valid = (raw_resp_valid && error); + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(raw_resp.status), + }; + + let fsm = match (raw_resp_valid, error, state.block_last) { + (true, false, false) => Fsm::DECODE_BLOCK_HEADER, + (true, false, true) => Fsm::DECODE_CHECKSUM, + (true, true, _) => Fsm::ERROR, + ( _, _, _) => Fsm::DECODE_RAW_BLOCK, + }; + + let req_sent = if !raw_resp_valid && !error { true } else { false }; + let block_id = if raw_resp_valid { state.block_id + u32:1} else {state.block_id }; + + let state = State {fsm, block_id, csr_wr_req, csr_wr_req_valid, req_sent, ..state}; + if fsm == Fsm::DECODE_BLOCK_HEADER { + trace_fmt!("Going to decode block header: {:#x}", state); + } else {}; + + state + }, + + Fsm::DECODE_RLE_BLOCK => { + trace_fmt!("[DECODE_RLE_BLOCK]"); + let error = (rle_resp.status != RleBlockDecoderStatus::OKAY); + + let csr_wr_req_valid = (rle_resp_valid && error); + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(rle_resp.status), + }; + + let fsm = match (rle_resp_valid, error, state.block_last) { + (true, false, false) => Fsm::DECODE_BLOCK_HEADER, + (true, false, true) => Fsm::DECODE_CHECKSUM, + (true, true, _) => Fsm::ERROR, + ( _, _, _) => Fsm::DECODE_RLE_BLOCK, + }; + + let req_sent = if !rle_resp_valid && !error { true } else { false }; + let block_id = if rle_resp_valid { state.block_id + u32:1} else {state.block_id }; + + let state = State {fsm, block_id, csr_wr_req, csr_wr_req_valid, req_sent, ..state}; + if fsm == Fsm::DECODE_BLOCK_HEADER { + trace_fmt!("Going to decode block header: {:#x}", state); + } else {}; + + state + }, + + Fsm::DECODE_CHECKSUM => { + trace_fmt!("[DECODE_CHECKSUM]"); + State {fsm: Fsm::FINISH, ..zero!() } + + }, + + Fsm::ERROR => { + trace_fmt!("[ERROR]"); + State { fsm: Fsm::IDLE, ..zero!() } + }, + + Fsm::FINISH => { + trace_fmt!("[FINISH]"); + let csr_wr_req_valid = true; + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(fh_resp.status), + }; + + State { fsm: Fsm::IDLE, csr_wr_req, csr_wr_req_valid, ..zero!() } + }, + + _ => zero!(), + }; + + new_state } } -fn decode_checksum(state: ZstdDecoderState) -> (bool, BlockDataPacket, ZstdDecoderState) { - trace_fmt!("zstd_dec: decode_checksum: DECODE CHECKSUM"); - trace_fmt!("zstd_dec: decode_checksum: state: {:#x}", state); - // Pop fixed checksum size of 4 bytes - let (buffer_result, _) = buff::buffer_pop_checked(state.buffer, u32:32); +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_ID_W = u32:8; +const TEST_AXI_DEST_W = u32:8; +const TEST_REGS_N = u32:5; +const TEST_WINDOW_LOG_MAX = u32:30; + +const TEST_HB_ADDR_W = sequence_executor::ZSTD_RAM_ADDR_WIDTH; +const TEST_HB_DATA_W = sequence_executor::RAM_DATA_WIDTH; +const TEST_HB_NUM_PARTITIONS = sequence_executor::RAM_NUM_PARTITIONS; +const TEST_HB_SIZE_KB = sequence_executor::ZSTD_HISTORY_BUFFER_SIZE_KB; + +const TEST_LOG2_REGS_N = std::clog2(TEST_REGS_N); +const TEST_AXI_DATA_W_DIV8 = TEST_AXI_DATA_W / u32:8; +const TEST_HB_RAM_N = u32:8; + +const TEST_HB_SIZE = sequence_executor::ram_size(TEST_HB_SIZE_KB); +const TEST_HB_RAM_WORD_PARTITION_SIZE = sequence_executor::RAM_WORD_PARTITION_SIZE; +const TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = sequence_executor::TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR; +const TEST_HB_RAM_INITIALIZED = sequence_executor::TEST_RAM_INITIALIZED; +const TEST_HB_RAM_ASSERT_VALID_READ:bool = {false}; + + +#[test_proc] +proc ZstdDecoderInternalTest { + + type BlockType = common::BlockType; + type BlockSize = common::BlockSize; + type BlockHeader = block_header::BlockHeader; + type BlockHeaderDecoderStatus = block_header_dec::BlockHeaderDecoderStatus; + + type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; + type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; + type FrameHeaderDecoderStatus = frame_header_dec::FrameHeaderDecoderStatus; + type FrameContentSize = frame_header_dec::FrameContentSize; + type FrameHeader = frame_header_dec::FrameHeader; + type WindowSize = frame_header_dec::WindowSize; + type DictionaryId = frame_header_dec::DictionaryId; + + type CsrRdReq = csr_config::CsrRdReq; + type CsrRdResp = csr_config::CsrRdResp; + type CsrWrReq = csr_config::CsrWrReq; + type CsrWrResp = csr_config::CsrWrResp; + type CsrChange = csr_config::CsrChange; + + type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; + type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; + + type BlockHeaderDecoderReq = block_header_dec::BlockHeaderDecoderReq; + type BlockHeaderDecoderResp = block_header_dec::BlockHeaderDecoderResp; + + type RawBlockDecoderReq = raw_block_dec::RawBlockDecoderReq; + type RawBlockDecoderResp = raw_block_dec::RawBlockDecoderResp; + type RawBlockDecoderStatus = raw_block_dec::RawBlockDecoderStatus; + + type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; + type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + type RleBlockDecoderStatus = rle_block_dec::RleBlockDecoderStatus; + + terminator: chan out; + + csr_rd_req_r: chan in; + csr_rd_resp_s: chan out; + csr_wr_req_r: chan in; + csr_wr_resp_s: chan out; + csr_change_s: chan out; + + fh_req_r: chan in; + fh_resp_s: chan out; + + bh_req_r: chan in; + bh_resp_s: chan out; + + raw_req_r: chan in; + raw_resp_s: chan out; + + rle_req_r: chan in; + rle_resp_s: chan out; + + notify_r: chan<()> in; + + init {} + + config(terminator: chan out) { + let (csr_rd_req_s, csr_rd_req_r) = chan("csr_rd_req"); + let (csr_rd_resp_s, csr_rd_resp_r) = chan("csr_rd_resp"); + let (csr_wr_req_s, csr_wr_req_r) = chan("csr_wr_req"); + let (csr_wr_resp_s, csr_wr_resp_r) = chan("csr_wr_resp"); + let (csr_change_s, csr_change_r) = chan("csr_change"); + + let (fh_req_s, fh_req_r) = chan("fh_req"); + let (fh_resp_s, fh_resp_r) = chan("fh_resp"); + + let (bh_req_s, bh_req_r) = chan("bh_req"); + let (bh_resp_s, bh_resp_r) = chan("bh_resp"); + + let (raw_req_s, raw_req_r) = chan("raw_req"); + let (raw_resp_s, raw_resp_r) = chan("raw_resp"); + + let (rle_req_s, rle_req_r) = chan("rle_req"); + let (rle_resp_s, rle_resp_r) = chan("rle_resp"); + + let (notify_s, notify_r) = chan<()>("notify"); + + spawn ZstdDecoderInternal( + csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, + fh_req_s, fh_resp_r, + bh_req_s, bh_resp_r, + raw_req_s, raw_resp_r, + rle_req_s, rle_resp_r, + notify_s, + ); + + ( + terminator, + csr_rd_req_r, csr_rd_resp_s, csr_wr_req_r, csr_wr_resp_s, csr_change_s, + fh_req_r, fh_resp_s, + bh_req_r, bh_resp_s, + raw_req_r, raw_resp_s, + rle_req_r, rle_resp_s, + notify_r, + ) + } + + next (state: ()) { + type Addr = uN[TEST_AXI_ADDR_W]; + type Length = uN[TEST_AXI_ADDR_W]; + + let tok = join(); + + // Error in frame header + + let tok = send(tok, csr_change_s, CsrChange { csr: csr(Csr::START)}); + let (tok, csr_data) = recv(tok, csr_rd_req_r); + assert_eq(csr_data, CsrRdReq {csr: csr(Csr::OUTPUT_BUFFER)}); + let (tok, csr_data) = recv(tok, csr_rd_req_r); + assert_eq(csr_data, CsrRdReq {csr: csr(Csr::INPUT_BUFFER)}); - let new_state = ZstdDecoderState { - status: ZstdDecoderStatus::DECODE_MAGIC_NUMBER, - buffer: buffer_result.buffer, - ..state - }; - trace_fmt!("zstd_dec: decode_checksum: new_state: {:#x}", new_state); + send(tok, csr_rd_resp_s, CsrRdResp { + csr: csr(Csr::INPUT_BUFFER), + value: uN[TEST_AXI_DATA_W]:0x1000 + }); + send(tok, csr_rd_resp_s, CsrRdResp { + csr: csr(Csr::OUTPUT_BUFFER), + value: uN[TEST_AXI_DATA_W]:0x2000 + }); + let (tok, fh_req) = recv(tok, fh_req_r); + assert_eq(fh_req, FrameHeaderDecoderReq { addr: Addr:0x1000 }); - (false, zero!(), new_state) + let tok = send(tok, fh_resp_s, FrameHeaderDecoderResp { + status: FrameHeaderDecoderStatus::CORRUPTED, + header: FrameHeader { + window_size: WindowSize:100, + frame_content_size: FrameContentSize:200, + dictionary_id: DictionaryId:123, + content_checksum_flag: u1:1, + }, + length: u5:3, + }); + + + let (tok, ()) = recv(tok, notify_r); + + // Correct case + let tok = send(tok, csr_change_s, CsrChange { csr: csr(Csr::START)}); + let (tok, csr_data) = recv(tok, csr_rd_req_r); + assert_eq(csr_data, CsrRdReq {csr: csr(Csr::OUTPUT_BUFFER)}); + let (tok, csr_data) = recv(tok, csr_rd_req_r); + assert_eq(csr_data, CsrRdReq {csr: csr(Csr::INPUT_BUFFER)}); + + send(tok, csr_rd_resp_s, CsrRdResp { + csr: csr(Csr::INPUT_BUFFER), + value: uN[TEST_AXI_DATA_W]:0x1000 + }); + send(tok, csr_rd_resp_s, CsrRdResp { + csr: csr(Csr::OUTPUT_BUFFER), + value: uN[TEST_AXI_DATA_W]:0x2000 + }); + let (tok, fh_req) = recv(tok, fh_req_r); + assert_eq(fh_req, FrameHeaderDecoderReq { addr: Addr:0x1000 }); + + let tok = send(tok, fh_resp_s, FrameHeaderDecoderResp { + status: FrameHeaderDecoderStatus::OKAY, + header: FrameHeader { + window_size: WindowSize:100, + frame_content_size: FrameContentSize:200, + dictionary_id: DictionaryId:123, + content_checksum_flag: u1:1, + }, + length: u5:3, + }); + + let (tok, bh_req) = recv(tok, bh_req_r); + assert_eq(bh_req, BlockHeaderDecoderReq { + addr: Addr:0x1003, + }); + + let tok = send(tok, bh_resp_s, BlockHeaderDecoderResp { + status: BlockHeaderDecoderStatus::OKAY, + header: BlockHeader { + last: false, + btype: BlockType::RAW, + size: BlockSize:0x1000, + }, + rle_symbol: u8:0, + }); + + let (tok, raw_req) = recv(tok, raw_req_r); + assert_eq(raw_req, RawBlockDecoderReq { + last_block: false, + id: u32:0, + addr: Addr:0x1006, + length: Length:0x1000 + }); + + let tok = send(tok, raw_resp_s, RawBlockDecoderResp { + status: RawBlockDecoderStatus::OKAY, + }); + + let (tok, bh_req) = recv(tok, bh_req_r); + assert_eq(bh_req, BlockHeaderDecoderReq { + addr: Addr:0x2006 + }); + let tok = send(tok, bh_resp_s, BlockHeaderDecoderResp { + status: BlockHeaderDecoderStatus::OKAY, + header: BlockHeader { + last: false, + btype: BlockType::RLE, + size: BlockSize:0x1000, + }, + rle_symbol: u8:123, + }); + + let (tok, rle_req) = recv(tok, rle_req_r); + assert_eq(rle_req, RleBlockDecoderReq { + id: u32:1, + symbol: u8:123, + last_block: false, + length: checked_cast(Length:0x1000), + }); + let tok = send(tok, rle_resp_s, RleBlockDecoderResp { + status: RleBlockDecoderStatus::OKAY, + }); + + let (tok, bh_req) = recv(tok, bh_req_r); + assert_eq(bh_req, BlockHeaderDecoderReq { + addr: Addr:0x200A, + }); + + let tok = send(tok, bh_resp_s, BlockHeaderDecoderResp { + status: BlockHeaderDecoderStatus::OKAY, + header: BlockHeader { + last: true, + btype: BlockType::RAW, + size: BlockSize:0x1000, + }, + rle_symbol: u8:0, + }); + + let (tok, raw_req) = recv(tok, raw_req_r); + assert_eq(raw_req, RawBlockDecoderReq { + last_block: true, + id: u32:2, + addr: Addr:0x200D, + length: Length:0x1000 + }); + + let tok = send(tok, raw_resp_s, RawBlockDecoderResp { + status: RawBlockDecoderStatus::OKAY, + }); + + let (tok, ()) = recv(tok, notify_r); + + send(tok, terminator, true); + } } -pub proc ZstdDecoder { - input_r: chan in; - block_dec_in_s: chan out; - output_s: chan out; - looped_channel_r: chan in; - looped_channel_s: chan out; - ram_rd_req_0_s: chan> out; - ram_rd_req_1_s: chan> out; - ram_rd_req_2_s: chan> out; - ram_rd_req_3_s: chan> out; - ram_rd_req_4_s: chan> out; - ram_rd_req_5_s: chan> out; - ram_rd_req_6_s: chan> out; - ram_rd_req_7_s: chan> out; - ram_rd_resp_0_r: chan> in; - ram_rd_resp_1_r: chan> in; - ram_rd_resp_2_r: chan> in; - ram_rd_resp_3_r: chan> in; - ram_rd_resp_4_r: chan> in; - ram_rd_resp_5_r: chan> in; - ram_rd_resp_6_r: chan> in; - ram_rd_resp_7_r: chan> in; - ram_wr_req_0_s: chan> out; - ram_wr_req_1_s: chan> out; - ram_wr_req_2_s: chan> out; - ram_wr_req_3_s: chan> out; - ram_wr_req_4_s: chan> out; - ram_wr_req_5_s: chan> out; - ram_wr_req_6_s: chan> out; - ram_wr_req_7_s: chan> out; - ram_wr_resp_0_r: chan in; - ram_wr_resp_1_r: chan in; - ram_wr_resp_2_r: chan in; - ram_wr_resp_3_r: chan in; - ram_wr_resp_4_r: chan in; - ram_wr_resp_5_r: chan in; - ram_wr_resp_6_r: chan in; - ram_wr_resp_7_r: chan in; - - init {(ZERO_DECODER_STATE)} - - config ( - input_r: chan in, + +proc ZstdDecoder< + // AXI parameters + AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + // decoder parameters + REGS_N: u32, WINDOW_LOG_MAX: u32, + HB_ADDR_W: u32, HB_DATA_W: u32, HB_NUM_PARTITIONS: u32, HB_SIZE_KB: u32, + // calculated parameters + AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, + LOG2_REGS_N: u32 = {std::clog2(REGS_N)}, + HB_RAM_N: u32 = {u32:8}, +> { + type CsrAxiAr = axi::AxiAr; + type CsrAxiR = axi::AxiR; + type CsrAxiAw = axi::AxiAw; + type CsrAxiW = axi::AxiW; + type CsrAxiB = axi::AxiB; + + type CsrRdReq = csr_config::CsrRdReq; + type CsrRdResp = csr_config::CsrRdResp; + type CsrWrReq = csr_config::CsrWrReq; + type CsrWrResp = csr_config::CsrWrResp; + type CsrChange = csr_config::CsrChange; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; + type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; + + type BlockHeaderDecoderReq = block_header_dec::BlockHeaderDecoderReq; + type BlockHeaderDecoderResp = block_header_dec::BlockHeaderDecoderResp; + + type RawBlockDecoderReq = raw_block_dec::RawBlockDecoderReq; + type RawBlockDecoderResp = raw_block_dec::RawBlockDecoderResp; + type ExtendedBlockDataPacket = common::ExtendedBlockDataPacket; + + type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; + type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + + type SequenceExecutorPacket = common::SequenceExecutorPacket; + type ZstdDecodedPacket = common::ZstdDecodedPacket; + + type RamRdReq = ram::ReadReq; + type RamRdResp = ram::ReadResp; + type RamWrReq = ram::WriteReq; + type RamWrResp = ram::WriteResp; + + // Complex Block Decoder + cmp_output_s: chan out; + + init {} + + config( + // AXI Ctrl (subordinate) + csr_axi_aw_r: chan in, + csr_axi_w_r: chan in, + csr_axi_b_s: chan out, + csr_axi_ar_r: chan in, + csr_axi_r_s: chan out, + + // AXI Frame Header Decoder (manager) + fh_axi_ar_s: chan out, + fh_axi_r_r: chan in, + + //// AXI Block Header Decoder (manager) + bh_axi_ar_s: chan out, + bh_axi_r_r: chan in, + + //// AXI RAW Block Decoder (manager) + raw_axi_ar_s: chan out, + raw_axi_r_r: chan in, + + // History Buffer + ram_rd_req_0_s: chan out, + ram_rd_req_1_s: chan out, + ram_rd_req_2_s: chan out, + ram_rd_req_3_s: chan out, + ram_rd_req_4_s: chan out, + ram_rd_req_5_s: chan out, + ram_rd_req_6_s: chan out, + ram_rd_req_7_s: chan out, + ram_rd_resp_0_r: chan in, + ram_rd_resp_1_r: chan in, + ram_rd_resp_2_r: chan in, + ram_rd_resp_3_r: chan in, + ram_rd_resp_4_r: chan in, + ram_rd_resp_5_r: chan in, + ram_rd_resp_6_r: chan in, + ram_rd_resp_7_r: chan in, + ram_wr_req_0_s: chan out, + ram_wr_req_1_s: chan out, + ram_wr_req_2_s: chan out, + ram_wr_req_3_s: chan out, + ram_wr_req_4_s: chan out, + ram_wr_req_5_s: chan out, + ram_wr_req_6_s: chan out, + ram_wr_req_7_s: chan out, + ram_wr_resp_0_r: chan in, + ram_wr_resp_1_r: chan in, + ram_wr_resp_2_r: chan in, + ram_wr_resp_3_r: chan in, + ram_wr_resp_4_r: chan in, + ram_wr_resp_5_r: chan in, + ram_wr_resp_6_r: chan in, + ram_wr_resp_7_r: chan in, + + // Decoder output output_s: chan out, - looped_channel_r: chan in, - looped_channel_s: chan out, - ram_rd_req_0_s: chan> out, - ram_rd_req_1_s: chan> out, - ram_rd_req_2_s: chan> out, - ram_rd_req_3_s: chan> out, - ram_rd_req_4_s: chan> out, - ram_rd_req_5_s: chan> out, - ram_rd_req_6_s: chan> out, - ram_rd_req_7_s: chan> out, - ram_rd_resp_0_r: chan> in, - ram_rd_resp_1_r: chan> in, - ram_rd_resp_2_r: chan> in, - ram_rd_resp_3_r: chan> in, - ram_rd_resp_4_r: chan> in, - ram_rd_resp_5_r: chan> in, - ram_rd_resp_6_r: chan> in, - ram_rd_resp_7_r: chan> in, - ram_wr_req_0_s: chan> out, - ram_wr_req_1_s: chan> out, - ram_wr_req_2_s: chan> out, - ram_wr_req_3_s: chan> out, - ram_wr_req_4_s: chan> out, - ram_wr_req_5_s: chan> out, - ram_wr_req_6_s: chan> out, - ram_wr_req_7_s: chan> out, - ram_wr_resp_0_r: chan in, - ram_wr_resp_1_r: chan in, - ram_wr_resp_2_r: chan in, - ram_wr_resp_3_r: chan in, - ram_wr_resp_4_r: chan in, - ram_wr_resp_5_r: chan in, - ram_wr_resp_6_r: chan in, - ram_wr_resp_7_r: chan in, + notify_s: chan<()> out, ) { - let (block_dec_in_s, block_dec_in_r) = chan("block_dec_in"); - let (seq_exec_in_s, seq_exec_in_r) = chan("seq_exec_in"); - let (repacketizer_in_s, repacketizer_in_r) = chan("repacketizer_in"); + const CHANNEL_DEPTH = u32:1; + + // CSRs + + let (ext_csr_rd_req_s, ext_csr_rd_req_r) = chan("csr_rd_req"); + let (ext_csr_rd_resp_s, ext_csr_rd_resp_r) = chan("csr_rd_resp"); + let (ext_csr_wr_req_s, ext_csr_wr_req_r) = chan("csr_wr_req"); + let (ext_csr_wr_resp_s, ext_csr_wr_resp_r) = chan("csr_wr_resp"); + + let (csr_rd_req_s, csr_rd_req_r) = chan("csr_rd_req"); + let (csr_rd_resp_s, csr_rd_resp_r) = chan("csr_rd_resp"); + let (csr_wr_req_s, csr_wr_req_r) = chan("csr_wr_req"); + let (csr_wr_resp_s, csr_wr_resp_r) = chan("csr_wr_resp"); + + let (csr_change_s, csr_change_r) = chan("csr_change"); + + spawn axi_csr_accessor::AxiCsrAccessor( + csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, // csr write from AXI + csr_axi_ar_r, csr_axi_r_s, // csr read from AXI + ext_csr_rd_req_s, ext_csr_rd_resp_r, // csr read to CsrConfig + ext_csr_wr_req_s, ext_csr_wr_resp_r, // csr write to CsrConfig + ); + + spawn csr_config::CsrConfig( + ext_csr_rd_req_r, ext_csr_rd_resp_s, // csr read from AxiCsrAccessor + ext_csr_wr_req_r, ext_csr_wr_resp_s, // csr write from AxiCsrAccessor + csr_rd_req_r, csr_rd_resp_s, // csr read from design + csr_wr_req_r, csr_wr_resp_s, // csr write from design + csr_change_s, // notification about csr change + ); + + // Frame Header + + let (fh_mem_rd_req_s, fh_mem_rd_req_r) = chan("fh_mem_rd_req"); + let (fh_mem_rd_resp_s, fh_mem_rd_resp_r) = chan("fh_mem_rd_resp"); + + spawn mem_reader::MemReader( + fh_mem_rd_req_r, fh_mem_rd_resp_s, + fh_axi_ar_s, fh_axi_r_r, + ); + + let (fh_req_s, fh_req_r) = chan("fh_req"); + let (fh_resp_s, fh_resp_r) = chan("fh_resp"); + + spawn frame_header_dec::FrameHeaderDecoder( + fh_mem_rd_req_s, fh_mem_rd_resp_r, + fh_req_r, fh_resp_s, + ); + + // Block Header + + let (bh_mem_rd_req_s, bh_mem_rd_req_r) = chan("bh_mem_rd_req"); + let (bh_mem_rd_resp_s, bh_mem_rd_resp_r) = chan("bh_mem_rd_resp"); + + spawn mem_reader::MemReader( + bh_mem_rd_req_r, bh_mem_rd_resp_s, + bh_axi_ar_s, bh_axi_r_r, + ); + + let (bh_req_s, bh_req_r) = chan("bh_req"); + let (bh_resp_s, bh_resp_r) = chan("bh_resp"); + + spawn block_header_dec::BlockHeaderDecoder( + bh_req_r, bh_resp_s, + bh_mem_rd_req_s, bh_mem_rd_resp_r, + ); + + // Raw Block Decoder + + let (raw_mem_rd_req_s, raw_mem_rd_req_r) = chan("raw_mem_rd_req"); + let (raw_mem_rd_resp_s, raw_mem_rd_resp_r) = chan("raw_mem_rd_resp"); + + spawn mem_reader::MemReader( + raw_mem_rd_req_r, raw_mem_rd_resp_s, + raw_axi_ar_s, raw_axi_r_r, + ); + + let (raw_req_s, raw_req_r) = chan("raw_req"); + let (raw_resp_s, raw_resp_r) = chan("raw_resp"); + let (raw_output_s, raw_output_r) = chan("raw_output"); + + spawn raw_block_dec::RawBlockDecoder( + raw_req_r, raw_resp_s, raw_output_s, + raw_mem_rd_req_s, raw_mem_rd_resp_r, + ); + + // RLE Block Decoder + + let (rle_req_s, rle_req_r) = chan("rle_req"); + let (rle_resp_s, rle_resp_r) = chan("rle_resp"); + let (rle_output_s, rle_output_r) = chan("rle_output"); + + spawn rle_block_dec::RleBlockDecoder( + rle_req_r, rle_resp_s, rle_output_s + ); + + // Collecting Packets + + let (cmp_output_s, cmp_output_r) = chan("cmp_output"); + let (seq_exec_input_s, seq_exec_input_r) = chan("demux_output"); + + spawn dec_mux::DecoderMux( + raw_output_r, rle_output_r, cmp_output_r, + seq_exec_input_s, + ); - spawn block_dec::BlockDecoder(block_dec_in_r, seq_exec_in_s); + // Sequence Execution - spawn sequence_executor::SequenceExecutor( - seq_exec_in_r, repacketizer_in_s, - looped_channel_r, looped_channel_s, - ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, - ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, + let (seq_exec_looped_s, seq_exec_looped_r) = chan("seq_exec_looped"); + let (seq_exec_output_s, seq_exec_output_r) = chan("seq_exec_output"); + + spawn sequence_executor::SequenceExecutor( + seq_exec_input_r, seq_exec_output_s, + seq_exec_looped_r, seq_exec_looped_s, + ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, + ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, ram_rd_resp_0_r, ram_rd_resp_1_r, ram_rd_resp_2_r, ram_rd_resp_3_r, ram_rd_resp_4_r, ram_rd_resp_5_r, ram_rd_resp_6_r, ram_rd_resp_7_r, - ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, - ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, + ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, + ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, - ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, + ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r ); - spawn repacketizer::Repacketizer(repacketizer_in_r, output_s); - - (input_r, block_dec_in_s, output_s, looped_channel_r, looped_channel_s, - ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, - ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, - ram_rd_resp_0_r, ram_rd_resp_1_r, ram_rd_resp_2_r, ram_rd_resp_3_r, - ram_rd_resp_4_r, ram_rd_resp_5_r, ram_rd_resp_6_r, ram_rd_resp_7_r, - ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, - ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, - ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, - ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r) + // Repacketizer + + spawn repacketizer::Repacketizer(seq_exec_output_r, output_s); + + // Zstd Decoder Control + + spawn ZstdDecoderInternal ( + csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, + fh_req_s, fh_resp_r, + bh_req_s, bh_resp_r, + raw_req_s, raw_resp_r, + rle_req_s, rle_resp_r, + notify_s, + ); + + (cmp_output_s,) } - next (state: ZstdDecoderState) { - let tok = join(); - trace_fmt!("zstd_dec: next(): state: {:#x}", state); - let can_fit = buff::buffer_can_fit(state.buffer, BlockData:0); - trace_fmt!("zstd_dec: next(): can_fit: {}", can_fit); - let (tok, data, recv_valid) = recv_if_non_blocking(tok, input_r, can_fit, BlockData:0); - let state = if (can_fit && recv_valid) { - let buffer = buff::buffer_append(state.buffer, data); - trace_fmt!("zstd_dec: next(): received more data: {:#x}", data); - ZstdDecoderState {buffer, ..state} - } else { - state - }; - trace_fmt!("zstd_dec: next(): state after receive: {:#x}", state); - - let (do_send, data_to_send, state) = match state.status { - ZstdDecoderStatus::DECODE_MAGIC_NUMBER => - decode_magic_number(state), - ZstdDecoderStatus::DECODE_FRAME_HEADER => - decode_frame_header(state), - ZstdDecoderStatus::DECODE_BLOCK_HEADER => - decode_block_header(state), - ZstdDecoderStatus::FEED_BLOCK_DECODER => - feed_block_decoder(state), - ZstdDecoderStatus::DECODE_CHECKSUM => - decode_checksum(state), - _ => (false, zero!(), state) - }; + next (state: ()) { + send_if(join(), cmp_output_s, false, zero!()); + } +} - trace_fmt!("zstd_dec: next(): do_send: {:#x}, data_to_send: {:#x}, state: {:#x}", do_send, data_to_send, state); - let tok = send_if(tok, block_dec_in_s, do_send, data_to_send); +//#[test_proc] +//proc ZstdDecoderTest { +// type CsrAxiAr = axi::AxiAr; +// type CsrAxiR = axi::AxiR; +// type CsrAxiAw = axi::AxiAw; +// type CsrAxiW = axi::AxiW; +// type CsrAxiB = axi::AxiB; +// +// type CsrRdReq = csr_config::CsrRdReq; +// type CsrRdResp = csr_config::CsrRdResp; +// type CsrWrReq = csr_config::CsrWrReq; +// type CsrWrResp = csr_config::CsrWrResp; +// type CsrChange = csr_config::CsrChange; +// +// type MemAxiAr = axi::AxiAr; +// type MemAxiR = axi::AxiR; +// type MemAxiAw = axi::AxiAw; +// type MemAxiW = axi::AxiW; +// type MemAxiB = axi::AxiB; +// +// type RamRdReq = ram::ReadReq; +// type RamRdResp = ram::ReadResp; +// type RamWrReq = ram::WriteReq; +// type RamWrResp = ram::WriteResp; +// +// type ZstdDecodedPacket = common::ZstdDecodedPacket; +// terminator: chan out; +// +// init {} +// +// config(terminator: chan out) { +// +// let (csr_axi_aw_s, csr_axi_aw_r) = chan("csr_axi_aw"); +// let (csr_axi_w_s, csr_axi_w_r) = chan("csr_axi_w"); +// let (csr_axi_b_s, csr_axi_b_r) = chan("csr_axi_b"); +// let (csr_axi_ar_s, csr_axi_ar_r) = chan("csr_axi_ar"); +// let (csr_axi_r_s, csr_axi_r_r) = chan("csr_axi_r"); +// +// let (fh_axi_ar_s, fh_axi_ar_r) = chan("fh_axi_ar_s"); +// let (fh_axi_r_s, fh_axi_r_r) = chan("fh_axi_r_r"); +// +// let (bh_axi_ar_s, bh_axi_ar_r) = chan("bh_axi_ar"); +// let (bh_axi_r_s, bh_axi_r_r) = chan("bh_axi_r"); +// +// let (raw_axi_ar_s, raw_axi_ar_r) = chan("raw_axi_ar"); +// let (raw_axi_r_s, raw_axi_r_r) = chan("raw_axi_r"); +// +// let (rle_axi_ar_s, rle_axi_ar_r) = chan("rle_axi_ar"); +// let (rle_axi_r_s, rle_axi_r_r) = chan("rle_axi_r"); +// +// let (ram_rd_req_0_s, ram_rd_req_0_r) = chan("ram_rd_req_0"); +// let (ram_rd_req_1_s, ram_rd_req_1_r) = chan("ram_rd_req_1"); +// let (ram_rd_req_2_s, ram_rd_req_2_r) = chan("ram_rd_req_2"); +// let (ram_rd_req_3_s, ram_rd_req_3_r) = chan("ram_rd_req_3"); +// let (ram_rd_req_4_s, ram_rd_req_4_r) = chan("ram_rd_req_4"); +// let (ram_rd_req_5_s, ram_rd_req_5_r) = chan("ram_rd_req_5"); +// let (ram_rd_req_6_s, ram_rd_req_6_r) = chan("ram_rd_req_6"); +// let (ram_rd_req_7_s, ram_rd_req_7_r) = chan("ram_rd_req_7"); +// +// let (ram_rd_resp_0_s, ram_rd_resp_0_r) = chan("ram_rd_resp_0"); +// let (ram_rd_resp_1_s, ram_rd_resp_1_r) = chan("ram_rd_resp_1"); +// let (ram_rd_resp_2_s, ram_rd_resp_2_r) = chan("ram_rd_resp_2"); +// let (ram_rd_resp_3_s, ram_rd_resp_3_r) = chan("ram_rd_resp_3"); +// let (ram_rd_resp_4_s, ram_rd_resp_4_r) = chan("ram_rd_resp_4"); +// let (ram_rd_resp_5_s, ram_rd_resp_5_r) = chan("ram_rd_resp_5"); +// let (ram_rd_resp_6_s, ram_rd_resp_6_r) = chan("ram_rd_resp_6"); +// let (ram_rd_resp_7_s, ram_rd_resp_7_r) = chan("ram_rd_resp_7"); +// +// let (ram_wr_req_0_s, ram_wr_req_0_r) = chan("ram_wr_req_0"); +// let (ram_wr_req_1_s, ram_wr_req_1_r) = chan("ram_wr_req_1"); +// let (ram_wr_req_2_s, ram_wr_req_2_r) = chan("ram_wr_req_2"); +// let (ram_wr_req_3_s, ram_wr_req_3_r) = chan("ram_wr_req_3"); +// let (ram_wr_req_4_s, ram_wr_req_4_r) = chan("ram_wr_req_4"); +// let (ram_wr_req_5_s, ram_wr_req_5_r) = chan("ram_wr_req_5"); +// let (ram_wr_req_6_s, ram_wr_req_6_r) = chan("ram_wr_req_6"); +// let (ram_wr_req_7_s, ram_wr_req_7_r) = chan("ram_wr_req_7"); +// +// let (ram_wr_resp_0_s, ram_wr_resp_0_r) = chan("ram_wr_resp_0"); +// let (ram_wr_resp_1_s, ram_wr_resp_1_r) = chan("ram_wr_resp_1"); +// let (ram_wr_resp_2_s, ram_wr_resp_2_r) = chan("ram_wr_resp_2"); +// let (ram_wr_resp_3_s, ram_wr_resp_3_r) = chan("ram_wr_resp_3"); +// let (ram_wr_resp_4_s, ram_wr_resp_4_r) = chan("ram_wr_resp_4"); +// let (ram_wr_resp_5_s, ram_wr_resp_5_r) = chan("ram_wr_resp_5"); +// let (ram_wr_resp_6_s, ram_wr_resp_6_r) = chan("ram_wr_resp_6"); +// let (ram_wr_resp_7_s, ram_wr_resp_7_r) = chan("ram_wr_resp_7"); +// +// let (output_s, output_r) = chan("output"); +// let (notify_s, notify_r) = chan<()>("notify"); +// +// spawn ZstdDecoder< +// TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, +// TEST_REGS_N, TEST_WINDOW_LOG_MAX, +// TEST_HB_ADDR_W, TEST_HB_DATA_W, TEST_HB_NUM_PARTITIONS, TEST_HB_SIZE_KB, +// >( +// csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, +// fh_axi_ar_s, fh_axi_r_r, +// bh_axi_ar_s, bh_axi_r_r, +// raw_axi_ar_s, raw_axi_r_r, +// rle_axi_ar_s, rle_axi_r_r, +// ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, +// ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, +// ram_rd_resp_0_r, ram_rd_resp_1_r, ram_rd_resp_2_r, ram_rd_resp_3_r, +// ram_rd_resp_4_r, ram_rd_resp_5_r, ram_rd_resp_6_r, ram_rd_resp_7_r, +// ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, +// ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, +// ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, +// ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, +// output_s, notify_s, +// ); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_HB_RAM_ASSERT_VALID_READ +// > (ram_rd_req_0_r, ram_rd_resp_0_s, ram_wr_req_0_r, ram_wr_resp_0_s); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_HB_RAM_ASSERT_VALID_READ +// > (ram_rd_req_1_r, ram_rd_resp_1_s, ram_wr_req_1_r, ram_wr_resp_1_s); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_RAM_ASSERT_VALID_READ +// > (ram_rd_req_2_r, ram_rd_resp_2_s, ram_wr_req_2_r, ram_wr_resp_2_s); +// +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_RAM_ASSERT_VALID_READ +// > (ram_rd_req_3_r, ram_rd_resp_3_s, ram_wr_req_3_r, ram_wr_resp_3_s); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_RAM_ASSERT_VALID_READ +// > (ram_rd_req_4_r, ram_rd_resp_4_s, ram_wr_req_4_r, ram_wr_resp_4_s); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_RAM_ASSERT_VALID_READ +// > (ram_rd_req_5_r, ram_rd_resp_5_s, ram_wr_req_5_r, ram_wr_resp_5_s); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_RAM_ASSERT_VALID_READ +// > (ram_rd_req_6_r, ram_rd_resp_6_s, ram_wr_req_6_r, ram_wr_resp_6_s); +// +// spawn ram::RamModel< +// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, +// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, +// TEST_RAM_ASSERT_VALID_READ +// > (ram_rd_req_7_r, ram_rd_resp_7_s, ram_wr_req_7_r, ram_wr_resp_7_s); +// +// ( +// terminator, +// csr_axi_aw_s, csr_axi_w_s, csr_axi_b_r, csr_axi_ar_s, csr_axi_s_r, +// fh_axi_ar_r, fh_axi_s_s, +// bh_axi_ar_r, bh_axi_s_s, +// raw_axi_ar_r, raw_axi_s_s, +// rle_axi_ar_r, rle_axi_s_s, +// ram_sd_seq_0_r, ram_sd_seq_1_r, ram_sd_seq_2_r, ram_sd_seq_3_r, +// ram_sd_seq_4_r, ram_sd_seq_5_r, ram_sd_seq_6_r, ram_sd_seq_7_r, +// ram_sd_sesp_0_s, ram_sd_sesp_1_s, ram_sd_sesp_2_s, ram_sd_sesp_3_s, +// ram_sd_sesp_4_s, ram_sd_sesp_5_s, ram_sd_sesp_6_s, ram_sd_sesp_7_s, +// ram_wr_seq_0_r, ram_wr_seq_1_r, ram_wr_seq_2_r, ram_wr_seq_3_r, +// ram_wr_seq_4_r, ram_wr_seq_5_r, ram_wr_seq_6_r, ram_wr_seq_7_r, +// ram_wr_sesp_0_s, ram_wr_sesp_1_s, ram_wr_sesp_2_s, ram_wr_sesp_3_s, +// ram_wr_sesp_4_s, ram_wr_sesp_5_s, ram_wr_sesp_6_s, ram_wr_sesp_7_s, +// output_r, notify_r, +// ) +// } +// +// next (state: ()) { +// +// trace_fmt!("Test start"); +// +// send(join(), terminator, true); +// } +//} + + +const INST_AXI_DATA_W = u32:64; +const INST_AXI_ADDR_W = u32:16; +const INST_AXI_ID_W = u32:4; +const INST_AXI_DEST_W = u32:4; +const INST_REGS_N = u32:16; +const INST_WINDOW_LOG_MAX = u32:30; +const INST_HB_ADDR_W = sequence_executor::ZSTD_RAM_ADDR_WIDTH; +const INST_HB_DATA_W = sequence_executor::RAM_DATA_WIDTH; +const INST_HB_NUM_PARTITIONS = sequence_executor::RAM_NUM_PARTITIONS; +const INST_HB_SIZE_KB = sequence_executor::ZSTD_HISTORY_BUFFER_SIZE_KB; + +const INST_LOG2_REGS_N = std::clog2(INST_REGS_N); +const INST_AXI_DATA_W_DIV8 = INST_AXI_DATA_W / u32:8; +const INST_HB_RAM_N = u32:8; + +proc ZstdDecoderInternalInst { + type State = ZstdDecoderInternalState; + type Fsm = ZstdDecoderInternalFsm; + + type CsrRdReq = csr_config::CsrRdReq; + type CsrRdResp = csr_config::CsrRdResp; + type CsrWrReq = csr_config::CsrWrReq; + type CsrWrResp = csr_config::CsrWrResp; + type CsrChange = csr_config::CsrChange; + + type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; + type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; + + type BlockHeaderDecoderReq = block_header_dec::BlockHeaderDecoderReq; + type BlockHeaderDecoderResp = block_header_dec::BlockHeaderDecoderResp; + + type RawBlockDecoderReq = raw_block_dec::RawBlockDecoderReq; + type RawBlockDecoderResp = raw_block_dec::RawBlockDecoderResp; + + type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; + type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + + init { } + + config( + csr_rd_req_s: chan out, + csr_rd_resp_r: chan in, + csr_wr_req_s: chan out, + csr_wr_resp_r: chan in, + csr_change_r: chan in, + + // MemReader + FameHeaderDecoder + fh_req_s: chan out, + fh_resp_r: chan in, + + // MemReader + BlockHeaderDecoder + bh_req_s: chan out, + bh_resp_r: chan in, + + // MemReader + RawBlockDecoder + raw_req_s: chan out, + raw_resp_r: chan in, + + // MemReader + RleBlockDecoder + rle_req_s: chan out, + rle_resp_r: chan in, + + // IRQ + notify_s: chan<()> out, + ) { + spawn ZstdDecoderInternal< + INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_REGS_N, + > ( + csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, + fh_req_s, fh_resp_r, + bh_req_s, bh_resp_r, + raw_req_s, raw_resp_r, + rle_req_s, rle_resp_r, + notify_s, + ); - state } + + next(state: ()) {} } -const TEST_RAM_SIZE = sequence_executor::ram_size(ZSTD_HISTORY_BUFFER_SIZE_KB); -const RAM_WORD_PARTITION_SIZE = sequence_executor::RAM_WORD_PARTITION_SIZE; -const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = sequence_executor::TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR; -const TEST_RAM_INITIALIZED = sequence_executor::TEST_RAM_INITIALIZED; -const TEST_RAM_ASSERT_VALID_READ:bool = {false}; +proc ZstdDecoderInst { + type CsrAxiAr = axi::AxiAr; + type CsrAxiR = axi::AxiR; + type CsrAxiAw = axi::AxiAw; + type CsrAxiW = axi::AxiW; + type CsrAxiB = axi::AxiB; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type RamRdReq = ram::ReadReq; + type RamRdResp = ram::ReadResp; + type RamWrReq = ram::WriteReq; + type RamWrResp = ram::WriteResp; + + type ZstdDecodedPacket = common::ZstdDecodedPacket; + + init { } -pub proc ZstdDecoderTest { - input_r: chan in; - output_s: chan out; + config( + // AXI Ctrl (subordinate) + csr_axi_aw_r: chan in, + csr_axi_w_r: chan in, + csr_axi_b_s: chan out, + csr_axi_ar_r: chan in, + csr_axi_r_s: chan out, - init {()} + // AXI Frame Header Decoder (manager) + fh_axi_ar_s: chan out, + fh_axi_r_r: chan in, - config ( - input_r: chan in, + // AXI Block Header Decoder (manager) + bh_axi_ar_s: chan out, + bh_axi_r_r: chan in, + + // AXI RAW Block Decoder (manager) + raw_axi_ar_s: chan out, + raw_axi_r_r: chan in, + + // History Buffer + ram_rd_req_0_s: chan out, + ram_rd_req_1_s: chan out, + ram_rd_req_2_s: chan out, + ram_rd_req_3_s: chan out, + ram_rd_req_4_s: chan out, + ram_rd_req_5_s: chan out, + ram_rd_req_6_s: chan out, + ram_rd_req_7_s: chan out, + ram_rd_resp_0_r: chan in, + ram_rd_resp_1_r: chan in, + ram_rd_resp_2_r: chan in, + ram_rd_resp_3_r: chan in, + ram_rd_resp_4_r: chan in, + ram_rd_resp_5_r: chan in, + ram_rd_resp_6_r: chan in, + ram_rd_resp_7_r: chan in, + ram_wr_req_0_s: chan out, + ram_wr_req_1_s: chan out, + ram_wr_req_2_s: chan out, + ram_wr_req_3_s: chan out, + ram_wr_req_4_s: chan out, + ram_wr_req_5_s: chan out, + ram_wr_req_6_s: chan out, + ram_wr_req_7_s: chan out, + ram_wr_resp_0_r: chan in, + ram_wr_resp_1_r: chan in, + ram_wr_resp_2_r: chan in, + ram_wr_resp_3_r: chan in, + ram_wr_resp_4_r: chan in, + ram_wr_resp_5_r: chan in, + ram_wr_resp_6_r: chan in, + ram_wr_resp_7_r: chan in, + + // Decoder output output_s: chan out, + notify_s: chan<()> out, ) { - let (looped_channel_s, looped_channel_r) = chan("looped_channel"); - - let (ram_rd_req_0_s, ram_rd_req_0_r) = chan, u32:1>("ram_rd_req_0"); - let (ram_rd_req_1_s, ram_rd_req_1_r) = chan, u32:1>("ram_rd_req_1"); - let (ram_rd_req_2_s, ram_rd_req_2_r) = chan, u32:1>("ram_rd_req_2"); - let (ram_rd_req_3_s, ram_rd_req_3_r) = chan, u32:1>("ram_rd_req_3"); - let (ram_rd_req_4_s, ram_rd_req_4_r) = chan, u32:1>("ram_rd_req_4"); - let (ram_rd_req_5_s, ram_rd_req_5_r) = chan, u32:1>("ram_rd_req_5"); - let (ram_rd_req_6_s, ram_rd_req_6_r) = chan, u32:1>("ram_rd_req_6"); - let (ram_rd_req_7_s, ram_rd_req_7_r) = chan, u32:1>("ram_rd_req_7"); - - let (ram_rd_resp_0_s, ram_rd_resp_0_r) = chan, u32:1>("ram_rd_resp_0"); - let (ram_rd_resp_1_s, ram_rd_resp_1_r) = chan, u32:1>("ram_rd_resp_1"); - let (ram_rd_resp_2_s, ram_rd_resp_2_r) = chan, u32:1>("ram_rd_resp_2"); - let (ram_rd_resp_3_s, ram_rd_resp_3_r) = chan, u32:1>("ram_rd_resp_3"); - let (ram_rd_resp_4_s, ram_rd_resp_4_r) = chan, u32:1>("ram_rd_resp_4"); - let (ram_rd_resp_5_s, ram_rd_resp_5_r) = chan, u32:1>("ram_rd_resp_5"); - let (ram_rd_resp_6_s, ram_rd_resp_6_r) = chan, u32:1>("ram_rd_resp_6"); - let (ram_rd_resp_7_s, ram_rd_resp_7_r) = chan, u32:1>("ram_rd_resp_7"); - - let (ram_wr_req_0_s, ram_wr_req_0_r) = chan, u32:1>("ram_wr_req_0"); - let (ram_wr_req_1_s, ram_wr_req_1_r) = chan, u32:1>("ram_wr_req_1"); - let (ram_wr_req_2_s, ram_wr_req_2_r) = chan, u32:1>("ram_wr_req_2"); - let (ram_wr_req_3_s, ram_wr_req_3_r) = chan, u32:1>("ram_wr_req_3"); - let (ram_wr_req_4_s, ram_wr_req_4_r) = chan, u32:1>("ram_wr_req_4"); - let (ram_wr_req_5_s, ram_wr_req_5_r) = chan, u32:1>("ram_wr_req_5"); - let (ram_wr_req_6_s, ram_wr_req_6_r) = chan, u32:1>("ram_wr_req_6"); - let (ram_wr_req_7_s, ram_wr_req_7_r) = chan, u32:1>("ram_wr_req_7"); - - let (ram_wr_resp_0_s, ram_wr_resp_0_r) = chan("ram_wr_resp_0"); - let (ram_wr_resp_1_s, ram_wr_resp_1_r) = chan("ram_wr_resp_1"); - let (ram_wr_resp_2_s, ram_wr_resp_2_r) = chan("ram_wr_resp_2"); - let (ram_wr_resp_3_s, ram_wr_resp_3_r) = chan("ram_wr_resp_3"); - let (ram_wr_resp_4_s, ram_wr_resp_4_r) = chan("ram_wr_resp_4"); - let (ram_wr_resp_5_s, ram_wr_resp_5_r) = chan("ram_wr_resp_5"); - let (ram_wr_resp_6_s, ram_wr_resp_6_r) = chan("ram_wr_resp_6"); - let (ram_wr_resp_7_s, ram_wr_resp_7_r) = chan("ram_wr_resp_7"); - - spawn ZstdDecoder( - input_r, output_s, - looped_channel_r, looped_channel_s, - ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, - ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, + spawn ZstdDecoder< + INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, + INST_REGS_N, INST_WINDOW_LOG_MAX, + INST_HB_ADDR_W, INST_HB_DATA_W, INST_HB_NUM_PARTITIONS, INST_HB_SIZE_KB, + >( + csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, + fh_axi_ar_s, fh_axi_r_r, + bh_axi_ar_s, bh_axi_r_r, + raw_axi_ar_s, raw_axi_r_r, + ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, + ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, ram_rd_resp_0_r, ram_rd_resp_1_r, ram_rd_resp_2_r, ram_rd_resp_3_r, ram_rd_resp_4_r, ram_rd_resp_5_r, ram_rd_resp_6_r, ram_rd_resp_7_r, - ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, - ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, + ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, + ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, + output_s, notify_s, ); - - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_0_r, ram_rd_resp_0_s, ram_wr_req_0_r, ram_wr_resp_0_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_1_r, ram_rd_resp_1_s, ram_wr_req_1_r, ram_wr_resp_1_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_2_r, ram_rd_resp_2_s, ram_wr_req_2_r, ram_wr_resp_2_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_3_r, ram_rd_resp_3_s, ram_wr_req_3_r, ram_wr_resp_3_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_4_r, ram_rd_resp_4_s, ram_wr_req_4_r, ram_wr_resp_4_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_5_r, ram_rd_resp_5_s, ram_wr_req_5_r, ram_wr_resp_5_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_6_r, ram_rd_resp_6_s, ram_wr_req_6_r, ram_wr_resp_6_s); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, TEST_RAM_ASSERT_VALID_READ> - (ram_rd_req_7_r, ram_rd_resp_7_s, ram_wr_req_7_r, ram_wr_resp_7_s); - - (input_r, output_s) } next (state: ()) {} diff --git a/xls/modules/zstd/zstd_dec_test.cc b/xls/modules/zstd/zstd_dec_test.cc deleted file mode 100644 index 0a6679a11d..0000000000 --- a/xls/modules/zstd/zstd_dec_test.cc +++ /dev/null @@ -1,297 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -#include -#include -#include -#include -#include -#include -#include // NOLINT -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gtest/gtest.h" -#include "absl/container/flat_hash_map.h" -#include "absl/log/log.h" -#include "absl/status/statusor.h" -#include "absl/types/span.h" -#include "xls/common/file/filesystem.h" -#include "xls/common/file/get_runfile_path.h" -#include "xls/common/status/matchers.h" -#include "xls/common/status/ret_check.h" -#include "xls/interpreter/channel_queue.h" -#include "xls/interpreter/serial_proc_runtime.h" -#include "xls/ir/bits.h" -#include "xls/ir/channel.h" -#include "xls/ir/events.h" -#include "xls/ir/ir_parser.h" -#include "xls/ir/package.h" -#include "xls/ir/proc.h" -#include "xls/ir/value.h" -#include "xls/jit/jit_proc_runtime.h" -#include "xls/modules/zstd/data_generator.h" -#include "external/zstd/lib/zstd.h" - -namespace xls { -namespace { - -class ZstdDecodedPacket { - public: - static absl::StatusOr MakeZstdDecodedPacket( - const Value& packet) { - // Expect tuple - XLS_RET_CHECK(packet.IsTuple()); - // Expect exactly 3 fields - XLS_RET_CHECK(packet.size() == 3); - for (int i = 0; i < 3; i++) { - // Expect fields to be Bits - XLS_RET_CHECK(packet.element(i).IsBits()); - // All fields must fit in 64 bits - XLS_RET_CHECK(packet.element(i).bits().FitsInUint64()); - } - - std::vector data = packet.element(0).bits().ToBytes(); - absl::StatusOr len = packet.element(1).bits().ToUint64(); - XLS_RET_CHECK(len.ok()); - uint64_t length = *len; - bool last = packet.element(2).bits().IsOne(); - - return ZstdDecodedPacket(data, length, last); - } - - std::vector& GetData() { return data; } - - uint64_t GetLength() { return length; } - - bool IsLast() { return last; } - - std::string ToString() const { - std::stringstream s; - for (int j = 0; j < sizeof(uint64_t) && j < data.size(); j++) { - s << "0x" << std::setw(2) << std::setfill('0') << std::right << std::hex - << static_cast(data[j]) << std::dec << ", "; - } - return s.str(); - } - - private: - ZstdDecodedPacket(std::vector data, uint64_t length, bool last) - : data(std::move(data)), length(length), last(last) {} - - std::vector data; - uint64_t length; - bool last; -}; - -class ZstdDecoderTest : public ::testing::Test { - public: - void SetUp() override { - XLS_ASSERT_OK_AND_ASSIGN(std::filesystem::path ir_path, - xls::GetXlsRunfilePath(this->kIrFile)); - XLS_ASSERT_OK_AND_ASSIGN(std::string ir_text, - xls::GetFileContents(ir_path)); - XLS_ASSERT_OK_AND_ASSIGN(this->package, xls::Parser::ParsePackage(ir_text)); - XLS_ASSERT_OK_AND_ASSIGN(this->interpreter, - CreateJitSerialProcRuntime(this->package.get())); - - auto& queue_manager = this->interpreter->queue_manager(); - XLS_ASSERT_OK_AND_ASSIGN( - this->recv_queue, queue_manager.GetQueueByName(this->kRecvChannelName)); - XLS_ASSERT_OK_AND_ASSIGN( - this->send_queue, queue_manager.GetQueueByName(this->kSendChannelName)); - } - - void PrintTraceMessages(const std::string& pname) { - XLS_ASSERT_OK_AND_ASSIGN(Proc * proc, this->package->GetProc(pname)); - const InterpreterEvents& events = - this->interpreter->GetInterpreterEvents(proc); - - if (!events.trace_msgs.empty()) { - for (const auto& tm : events.trace_msgs) { - LOG(INFO) << "[TRACE] " << tm.message << "\n"; - } - } - } - - const std::string_view kProcName = "__zstd_dec__ZstdDecoderTest_0_next"; - const std::string_view kRecvChannelName = "zstd_dec__output_s"; - const std::string_view kSendChannelName = "zstd_dec__input_r"; - - const std::string_view kIrFile = "xls/modules/zstd/zstd_dec_test.ir"; - - std::unique_ptr package; - std::unique_ptr interpreter; - ChannelQueue *recv_queue, *send_queue; - - void PrintVector(absl::Span vec) { - for (int i = 0; i < vec.size(); i += 8) { - LOG(INFO) << "0x" << std::hex << std::setw(3) << std::left << i - << std::dec << ": "; - for (int j = 0; j < sizeof(uint64_t) && (i + j) < vec.size(); j++) { - LOG(INFO) << std::setfill('0') << std::setw(2) << std::hex - << static_cast(vec[i + j]) << std::dec << " "; - } - LOG(INFO) << "\n"; - } - } - - void DecompressWithLibZSTD(std::vector encoded_frame, - std::vector& decoded_frame) { - size_t buff_out_size = ZSTD_DStreamOutSize(); - uint8_t* const buff_out = new uint8_t[buff_out_size]; - - ZSTD_DCtx* const dctx = ZSTD_createDCtx(); - EXPECT_FALSE(dctx == nullptr); - - void* const frame = static_cast(encoded_frame.data()); - size_t const frame_size = encoded_frame.size(); - // Put the whole frame in the buffer - ZSTD_inBuffer input_buffer = {frame, frame_size, 0}; - - while (input_buffer.pos < input_buffer.size) { - ZSTD_outBuffer output_buffer = {buff_out, buff_out_size, 0}; - size_t decomp_result = - ZSTD_decompressStream(dctx, &output_buffer, &input_buffer); - bool decomp_success = ZSTD_isError(decomp_result) != 0u; - EXPECT_FALSE(decomp_success); - - // Append output buffer contents to output vector - decoded_frame.insert( - decoded_frame.end(), static_cast(output_buffer.dst), - (static_cast(output_buffer.dst) + output_buffer.pos)); - - EXPECT_TRUE(decomp_result == 0 && output_buffer.pos < output_buffer.size); - } - - ZSTD_freeDCtx(dctx); - delete[] buff_out; - } - - void ParseAndCompareWithZstd(std::vector frame) { - std::vector lib_decomp; - DecompressWithLibZSTD(frame, lib_decomp); - size_t lib_decomp_size = lib_decomp.size(); - std::cerr << "lib_decomp_size: " << lib_decomp_size << "\n"; - - std::vector sim_decomp; - size_t sim_decomp_size_words = - (lib_decomp_size + sizeof(uint64_t) - 1) / sizeof(uint64_t); - size_t sim_decomp_size_bytes = - (lib_decomp_size + sizeof(uint64_t) - 1) * sizeof(uint64_t); - sim_decomp.reserve(sim_decomp_size_bytes); - - // Send compressed frame to decoder simulation - for (int i = 0; i < frame.size(); i += 8) { - // Pad packet w/ zeros to match the frame size expected by the design. - std::array packet_data = {}; - auto frame_packet_begin = frame.begin() + i; - auto frame_packet_end = frame_packet_begin + 8 < frame.end() - ? frame_packet_begin + 8 - : frame.end(); - std::copy(frame_packet_begin, frame_packet_end, packet_data.begin()); - auto span = absl::MakeSpan(packet_data.data(), 8); - auto value = Value(Bits::FromBytes(span, 64)); - XLS_EXPECT_OK(this->send_queue->Write(value)); - XLS_EXPECT_OK(this->interpreter->Tick()); - } - PrintTraceMessages("__zstd_dec__ZstdDecoderTest_0_next"); - - // Tick decoder simulation until we get expected amount of output data - // batches on output channel queue - std::optional ticks_timeout = std::nullopt; - absl::flat_hash_map output_counts = { - {this->recv_queue->channel(), sim_decomp_size_words}}; - XLS_EXPECT_OK( - this->interpreter->TickUntilOutput(output_counts, ticks_timeout)); - - // Read decompressed data from output channel queue - for (int i = 0; i < sim_decomp_size_words; i++) { - auto read_value = this->recv_queue->Read(); - EXPECT_EQ(read_value.has_value(), true); - auto packet = - ZstdDecodedPacket::MakeZstdDecodedPacket(read_value.value()); - XLS_EXPECT_OK(packet); - auto word_vec = packet->GetData(); - auto valid_length = packet->GetLength() / CHAR_BIT; - std::copy(begin(word_vec), begin(word_vec) + valid_length, - back_inserter(sim_decomp)); - } - - EXPECT_EQ(lib_decomp_size, sim_decomp.size()); - for (int i = 0; i < lib_decomp_size; i++) { - EXPECT_EQ(lib_decomp[i], sim_decomp[i]); - } - } -}; - -/* TESTS */ - -TEST_F(ZstdDecoderTest, ParseFrameWithRawBlocks) { - int seed = 3; // Arbitrary seed value for small ZSTD frame - auto frame = zstd::GenerateFrame(seed, zstd::BlockType::RAW); - EXPECT_TRUE(frame.ok()); - this->ParseAndCompareWithZstd(frame.value()); -} - -TEST_F(ZstdDecoderTest, ParseFrameWithRleBlocks) { - int seed = 3; // Arbitrary seed value for small ZSTD frame - auto frame = zstd::GenerateFrame(seed, zstd::BlockType::RLE); - EXPECT_TRUE(frame.ok()); - this->ParseAndCompareWithZstd(frame.value()); -} - -class ZstdDecoderSeededTest : public ZstdDecoderTest, - public ::testing::WithParamInterface { - public: - static const uint32_t seed_generator_start = 0; - static const uint32_t random_frames_count = 100; -}; - -// Test `random_frames_count` instances of randomly generated valid -// frames, generated with `decodecorpus` tool. - -TEST_P(ZstdDecoderSeededTest, ParseMultipleFramesWithRawBlocks) { - auto seed = GetParam(); - auto frame = zstd::GenerateFrame(seed, zstd::BlockType::RAW); - EXPECT_TRUE(frame.ok()); - this->ParseAndCompareWithZstd(frame.value()); -} - -TEST_P(ZstdDecoderSeededTest, ParseMultipleFramesWithRleBlocks) { - auto seed = GetParam(); - auto frame = zstd::GenerateFrame(seed, zstd::BlockType::RLE); - EXPECT_TRUE(frame.ok()); - this->ParseAndCompareWithZstd(frame.value()); -} - -INSTANTIATE_TEST_SUITE_P( - ZstdDecoderSeededTest, ZstdDecoderSeededTest, - ::testing::Range(ZstdDecoderSeededTest::seed_generator_start, - ZstdDecoderSeededTest::seed_generator_start + - ZstdDecoderSeededTest::random_frames_count)); - -} // namespace -} // namespace xls From 1915cf40a5fb8b74b2f4680523aa44bc708f73c8 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Thu, 10 Oct 2024 12:39:17 +0200 Subject: [PATCH 15/85] modules/zstd: Update documentation Internal-tag: [#67096] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/README.md | 401 ++++++++++-------- xls/modules/zstd/img/ZSTD_decoder.png | Bin 28375 -> 315264 bytes xls/modules/zstd/img/ZSTD_decoder_wrapper.png | Bin 0 -> 126231 bytes 3 files changed, 216 insertions(+), 185 deletions(-) create mode 100644 xls/modules/zstd/img/ZSTD_decoder_wrapper.png diff --git a/xls/modules/zstd/README.md b/xls/modules/zstd/README.md index 85c9919e4f..e606a02918 100644 --- a/xls/modules/zstd/README.md +++ b/xls/modules/zstd/README.md @@ -2,105 +2,196 @@ The ZSTD decoder decompresses the correctly formed ZSTD frames and blocks. It implements the [RFC 8878](https://www.rfc-editor.org/rfc/rfc8878.html) decompression algorithm. -Overview of the decoder architecture is presented on the diagram below. +An overview of the decoder architecture is presented in the diagram below. The decoder comprises: -* frame decoder, -* block dispatcher, -* 3 types of processing units: RAW, RLE, and compressed, -* command aggregator, -* history buffer, -* repacketizer. - -Incoming ZSTD frames are processed in the following order: -1. magic number is detected, -2. frame header is parsed, -3. ZSTD data blocks are being redirected to correct processing unit based on the block header, -4. processing unit results are aggregated in correct order into a stream -and routed to the history buffer, -5. data block outputs are assembled based on the history buffer contents and update history, -6. decoded data is processed by repacketizer in order to prepare the final output of the decoder, -7. (optional) calculated checksum is compared against frame checksum. +* Memory Readers +* Memory Writer[^2], +* Control and Status Registers, +* Frame Header Decoder, +* Block Header Decoder, +* 3 types of processing units: RAW-, RLE-, and Compressed Block Decoders[^1], +* Command Aggregator, +* Repacketizer. + +The Decoder interacts with the environment through a set of ports: +* Memory Interface (AXI) +* CSR Interface (AXI) +* Notify line +* Stream Output + +The software controls the core through registers accessible through the `CSR Interface`. +The CSRs are used to configure the decoder and to start the decoding process. + +ZSTD frames to decode are placed in a memory that should be connected to +decoder's `Memory Interface`. + +Once the decoding process is started, the decoder: + +1. Reads the configuration from the CSRs, +2. Decodes the Frame Header, +3. Decodes the Block Header, +4. Decodes the Block Data with the correct processing unit picked based on the Block Type from the Block Header, +4. Aggregates the processing unit results in the correct order into a stream and routes it to the history buffer, +5. Assembles the data block outputs based on the history buffer contents and updates the history, +6. Prepares the final output of the decoder, +7. (Optional) Calculates checksum and compares it against the checksum read from the frame.[^3] ![](img/ZSTD_decoder.png) +## Registers description + +The ZSTD Decoder operation is based on the values stored in a set of CSRs accessible to the user through the AXI bus. +The registers are defined below: + +| Name | Address | Description | +| ---- | ------- | ----------- | +| Status | 0x0 | Keeps the code describing the current state of the ZSTD Decoder | +| Start | 0x8 | Writing `1` when the decoder is in the `IDLE` state starts the decoding process | +| Reset | 0x10 | Writing `1` will reset the decoder to the `IDLE` state | +| Input Buffer | 0x18 | Keeps the base address for the input buffer that is used for storing the frame to decode | +| Output Buffer | 0x20 | Keeps the base address for the output buffer, ZSTD Decoder will write the decoded frame into memory starting from this address. | + +### Status codes + +The following is a list of all available status codes that can be written in the `Status` register. + +| Name | Value | Description | +| ---- | ------- | ----------- | +| IDLE | 0 | Previous decoding finished successfully. The decoder waits for the configuration and writes to the `Start` register. | +| RUNNING | 1 | Decoding process is started | +| READ_CONFIG_OK |2 | Successfully read configuration from the CSRs | +| FRAME_HEADER_OK | 3 | Successfully decoded frame header | +| FRAME_HEADER_CORRUPTED | 4 | Frame header data is not valid | +| FRAME_HEADER_UNSUPPORTED_WINDOW_SIZE | 5 | The `WindowSize` parameter read from the frame header is not supported in the decoder | +| BLOCK_HEADER_OK | 6 | Successfully read the header of the Zstd data block | +| BLOCK_HEADER_CORRUPTED | 7 | Block type is `Reserved` | +| BLOCK_HEADER_MEMORY_ACCESS_ERROR | 8 | Failure in communication with the memory | +| RAW_BLOCK_OK | 9 | Successfully decoded raw data block | +| RAW_BLOCK_ERROR | 10 | Failure in communication with the memory | +| RLE_BLOCK_OK | 11 | Successfully decoded RLE data block | + +### Reset handling + +The expected behavior of the `Reset` CSR cannot be achieved solely in the DSLX code. +As of [cb2829ab](https://github.com/google/xls/commit/cb2829ab809c58f21d957a47e400456a8c8f8db1), the XLS toolchain does not support resetting the proc network on the DSLX level. +As a workaround for this issue, the `ZstdDec` proc defines a `reset` output channel that sends a pulse when there is a write to the `Reset` CSR. +The Verilog code that integrates the decoder in a target system must connect this output back to the standard `rst` input of the decoder. +If any external reset signal exists and is intended to be used with the decoder, it should be OR-ed with the `reset` channel output before connecting to the decoder's `rst` input. +Please refer to the diagram of the Verilog wrapper in the [Testing Methodology](#testing-methodology) chapter for example reset connection. + +## Controlling the decoder from the software + +The configuration done by the software must be carried out when the decoder is in the `IDLE` state. +It is the only time when the decoder will be able to take the configuration values from the CSRs and use those in the decoding process. + +The software should first read the `Status` register to confirm that the decoder is in the `IDLE` state. +In case it is not in the `IDLE` state, it is possible to reset the decoder by writing `1` to the `Reset` register. +Please note that this will stop ongoing decoding and all progress will be lost. + +Then, the software has to reserve the memory for the input buffer and write the frame to decode there. +The address of the buffer should be written into `Input Buffer` register so that the decoder will know where to look for the frame to decode. + +The next step is to reserve the memory space for the decoded frame where the Decoder will write the decompressed data. +The address to that buffer should be written to the `Output Buffer` register. + +Finally, it is possible to start the decoding process by writing `1` to the `Start` register. +This orders the Decoder to read the configuration CSRs and start reading and decoding data stored in the input buffer. +The Decoder transitions to the `RUNNING` state and then to other states that describe the status of the last operation finished in the decoder (see #status-codes for other possible status codes) which will be visible in the `Status` register. + +When the decoding process is finished the Decoder transitions back to the `IDLE` state and signals this on the `Notify` IRQ line. +The decoded data is stored under the address configured previously in the `Output Buffer` register. + +In case an error occurs during the decoding process it is also signaled on the `Notify` IRQ line and the error code is written to the `Status` CSR. + ## ZSTD decoder architecture ### Top level Proc -This state machine is responsible for receiving encoded ZSTD frames, buffering the input and passing it to decoder's internal components based on the state of the proc. -The states defined for the processing of ZSTD frame are as follows: +This state machine is responsible for controlling the operation of the whole decoder. +It uses the configuration data from the CSRs, connects all underlying modules and sends processing requests to those based on the state of the machine. +The states defined for the processing of the ZSTD frame are as follows: ```mermaid stateDiagram - direction LR + [*] --> IDLE + + IDLE --> READ_CONFIG: Start - [*] --> DECODE_MAGIC_NUMBER + READ_CONFIG --> DECODE_FRAME_HEADER - DECODE_MAGIC_NUMBER --> DECODE_MAGIC_NUMBER: Not enough data - DECODE_MAGIC_NUMBER --> DECODE_FRAME_HEADER: Got magic number - DECODE_MAGIC_NUMBER --> ERROR: Corrupted + DECODE_FRAME_HEADER --> DECODE_BLOCK_HEADER + DECODE_FRAME_HEADER --> ERROR - DECODE_FRAME_HEADER --> DECODE_FRAME_HEADER: Not enough data - DECODE_FRAME_HEADER --> DECODE_BLOCK_HEADER: Header decoded - DECODE_FRAME_HEADER --> ERROR: Unsupported window size - DECODE_FRAME_HEADER --> ERROR: Corrupted + DECODE_BLOCK_HEADER --> DECODE_RAW_BLOCK + DECODE_BLOCK_HEADER --> DECODE_RLE_BLOCK + DECODE_BLOCK_HEADER --> DECODE_COMPRESED_BLOCK + DECODE_BLOCK_HEADER --> ERROR - DECODE_BLOCK_HEADER --> DECODE_BLOCK_HEADER: Not enough data - DECODE_BLOCK_HEADER --> FEED_BLOCK_DECODER: Feed raw data - DECODE_BLOCK_HEADER --> FEED_BLOCK_DECODER: Feed RLE data - DECODE_BLOCK_HEADER --> FEED_BLOCK_DECODER: Feed compressed data - DECODE_BLOCK_HEADER --> ERROR: Corrupted + state if_block_last <> + DECODE_RAW_BLOCK --> ERROR + DECODE_RAW_BLOCK --> if_block_last - state if_decode_checksum <> - state if_block_done <> + DECODE_RLE_BLOCK --> ERROR + DECODE_RLE_BLOCK --> if_block_last - FEED_BLOCK_DECODER --> if_decode_checksum: Is the checksum available? - if_decode_checksum --> DECODE_CHECKSUM: True - if_decode_checksum --> DECODE_MAGIC_NUMBER: False - FEED_BLOCK_DECODER --> if_block_done: Is the block decoding done? - if_block_done --> DECODE_BLOCK_HEADER: Decode next block - if_block_done --> FEED_BLOCK_DECODER: Continue feeding + DECODE_COMPRESSED_BLOCK --> ERROR + DECODE_COMPRESSED_BLOCK --> if_block_last - DECODE_CHECKSUM --> DECODE_MAGIC_NUMBER: Frame decoded + if_block_last --> DECODE_BLOCK_HEADER: Not last block in the frame + if_block_last --> DECODE_CHECKSUM: Last block in the frame - ERROR --> [*] + DECODE_CHECKSUM --> FINISH + + FINISH --> IDLE + ERROR --> IDLE ``` -After going through initial stages of decoding magic number and frame header, decoder starts the block division process. -It decodes block headers to calculate how many bytes must be sent to the block dispatcher and when the current frame's last data block is being processed. -Knowing that, it starts feeding the block decoder with data required for decoding current block. -After transmitting all data required for current block, it loops around to the block header decoding state and when next block header is not found it decodes checksum when it was requested in frame header or finishes ZSTD frame decoding and loops around to magic number decoding. - -### ZSTD frame header decoder -This part of the design starts with detecting the ZSTD magic number. -Then it parses and decodes the frame header's content and checks the header's correctness. -If the frame header has the checksum option enabled, this will enable `DECODE_CHECKSUM` stage at the end of the frame decoding where the frame's checksum will be computed and compared with the checksum embedded at the end of the frame stream. - -### Block dispatcher (demux) -At this stage, block headers are parsed and removed from the block data stream. -Based on parse values, it directs the block data stream to either RAW, RLE or compressed block sections. -For this task it uses an 8 byte native interface: a 64-bit data bus and a 64-bit length field that contains the number of correct bits on the data bus. -It also attaches a unique block ID value to each processed data block. -The IDs are sequential starting from 0 and are reset only after receiving and processing the current frame's last data block. - -### RAW -This proc passes the received data directly to its output channel. +After going through the initial stage of reading the configuration from the CSRs, the decoder sends the processing requests to the underlying parts of the decoder. +The processing requests contain the addresses in the memory where particular parts of the encoded ZSTD frames reside. +The decoder, based on responses from consecutive internal modules, calculates offsets from the base address that was written to `Input Buffer` CSR and forms the requests for the next internal modules, e.g.: for `BlockHeaderDecoder` or any of the processing units (`RawBlockDecoder`, `RleBlockDecoder`, `CompressedBlockDecoder`). + +Each of the internal modules waits for the processing request. +Once received, the module fetches the data from the memory starting from the address received in the processing request. +`MemReader` procs are used by those modules to communicate with the external memory through the AXI interface. +Internal modules decode the acquired parts of the frame and return responses with the results back to the top level proc. + +The processing units also output the decoded blocks of data through a stream-based interface to `SequenceExecutor` and further to `Repacketizer` procs. +Those procs perform the last steps of the decoding before the final output is sent out back to the memory under the address stored in the `Output Buffer` CSR or through the stream-based output channel. +Once the decoding process is completed, the decoder sends the `Notify` signal and transitions back to the `IDLE` state. + +### Internal modules + +#### FrameHeaderDecoder +This proc receives requests with the address of the beginning of the ZSTD frame. +It then reads the frame data from the memory and starts parsing the frame header. +If the magic number is not detected or the frame header is invalid, the proc will send a response with an error code. +Otherwise, it will put the frame header into internal DSLX representation, calculate the length of the header and send those as a response with `OKAY` status. + +#### BlockHeaderDecoder +ZSTD block header size is always 3 bytes. +BlockHeaderDecoder always reads 4 bytes of data. +It extracts the information on block type, size and whether the block is the last one in the ZSTD frame and puts that data in the response. +The additional byte is also placed in the response as an optimization for the RleBlockDecoder. + +#### RawBlockDecoder +This proc passes the data read from the memory directly to its output channel. It preserves the block ID and attaches a tag, stating that the data contains literals and should be placed in the history buffer unchanged, to each data output. -### RLE decoder -This proc receives a tuple (s, N), where s is an 8 bit symbol and N is an accompanying `symbol_count`. +#### RleBlockDecoder +This proc receives a tuple (s, N), where s is an 8-bit symbol and N is an accompanying `symbol_count`. +It does not have to read the 8-bit symbol from the memory because `BlockHeaderDecoder` did that before and passed the symbol in the processing request to the `RleBlockDecoder`. The proc produces `N*s` repeats of the given symbol. This step preserves the block ID and attaches the literals tag to all its outputs. -### Compressed block decoder +#### CompressedBlockDecoder[^1] This part of the design is responsible for decoding the compressed data blocks. -It ingests the bytes stream, internally translates and interprets incoming data. +It ingests the bytes stream, and internally translates and interprets incoming data. Only this part of the design creates data chunks tagged both with `literals` and/or `copy`. This step preserves the block ID. -More in depth description can be found in [Compressed block decoder architecture](#compressed-block-decoder-architecture) paragraph of this doc. +More in-depth description can be found in [Compressed block decoder architecture](#compressed-block-decoder-architecture) paragraph of this doc. -### Commands aggregator (mux) -This stage takes the output from either RAW, RLE or Command constructor and sends it to the History buffer and command execution stage. -This stage orders streams based on the ID value assigned by the block dispatcher. +#### Commands aggregator (DecMux) +This stage takes the output from either RAW, RLE or CompressedBlockDecoder and sends it to the History buffer and command execution stage. +This stage orders streams based on the ID value assigned by the top level proc. It is expected that single base decoders (RAW, RLE, compressed block decoder) will be continuously transmitting a single ID to the point of sending the `last` signal which marks the last packet of currently decoded block. That ID can change only when mux receives the `last` signal or `last` and `last_block` signals. @@ -110,7 +201,7 @@ It continues to read that stream until the `last` signal is set, then it switche The command aggregator starts by waiting for `ID = 0`, after receiving the `last` signal it expects `ID = 1` and so on. Only when both `last` and `last_block` are set the command aggregator will wait for `ID = 0`. -### History buffer and command execution +#### History buffer and command execution (SequenceExecutor) This stage receives data which is tagged either `literals` or `copy`. This stage will show the following behavior, depending on the tag: * `literals` @@ -121,13 +212,26 @@ This stage will show the following behavior, depending on the tag: * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the decoder's output, * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the history buffer as the newest. -### Compressed block decoder architecture +#### Repacketizer +This proc is used at the end of the processing flow in the ZSTD decoder. +It gathers the output of `SequenceExecutor` proc and processes it to form the final output packets of the ZSTD decoder. +Input packets coming from the `SequenceExecutor` consist of: + +* data - bit vector of constant length +* length - field describing how many bits in bit vector are valid +* last - flag which marks the last packet in currently decoded ZSTD frame. + +It is not guaranteed that all bits in data bit vectors in packets received from `SequenceExecutor` are valid as those can include padding bits that were added in previous decoding steps and now have to be removed. +Repacketizer buffers input packets, removes the padding bits and forms new packets with all bits of the bit vector valid, meaning that all bits are decoded data. +Newly formed packets are then sent out to the output of the whole ZSTD decoder. + +### Compressed block decoder architecture[^1] This part of the design is responsible for processing the compressed blocks up to the `literals`/`copy` command sequence. -This sequence is then processed by the history buffer to generate expected data output. -Overview of the architecture is provided on the diagram below. -The architecture is split into 2 paths: literals path and sequence path. +This sequence is then processed by the history buffer to generate the expected data output. +An overview of the architecture is provided in the diagram below. +The architecture is split into 2 paths: the literals path and the sequence path. Architecture is split into 3 paths: literals path, FSE encoded Huffman trees and sequence path. -Literals path uses Hufman trees to decode some types of compressed blocks: Compressed and Treeless blocks. +Literals path uses Huffman trees to decode some types of compressed blocks: Compressed and Treeless blocks. ![](img/ZSTD_compressed_block_decoder.png) @@ -144,11 +248,11 @@ When `literals length` is greater than 0, it will send a request to the literals Then based on the offset and copy length it either creates a match command using the provided offset and match lengths, or uses repeated offset and updates the repeated offset memory. Formed commands are sent to the Commands aggregator (mux). -### Literals path architecture +#### Literals path architecture ![](img/ZSTD_compressed_block_literals_decoder.png) -#### Literals decoder dispatcher +##### Literals decoder dispatcher This proc parses and consumes the literals section header. Based on the received values it passes the remaining bytes to RAW/RLE/Huffman tree/Huffman code decoders. It also controls the 4 stream operation mode [4-stream mode in RFC](https://www.rfc-editor.org/rfc/rfc8878.html#name-jump_table). @@ -156,59 +260,59 @@ It also controls the 4 stream operation mode [4-stream mode in RFC](https://www. All packets sent to the Huffman bitstream buffer will be tagged either `in_progress` or `finished`. If the compressed literals use the 4 streams encoding, the dispatcher will send the `finished` tag 4 times, each time a fully compressed stream is sent to the bitstream buffer. -#### RAW Literals +##### RAW Literals This stage simply passes the incoming bytes as literals to the literals buffer. -#### RLE Literals +##### RLE Literals This stage works similarly to the [RLE stage](#rle-decoder) for RLE data blocks. -#### Huffman bitstream buffer +##### Huffman bitstream buffer This stage takes data from the literals decoder dispatcher and stores it in the buffer memory. Once the data with the `finished` tag set is received, this stage sends a tuple containing (start, end) positions for the current bitstream to the Huffman codes decoder. This stage receives a response from the Huffman codes decoder when decoding is done and all bits got processed. Upon receiving this message, the buffer will reclaim free space. -#### Huffman codes decoder +##### Huffman codes decoder This stage receives bitstream pointers from the Huffman bitstream buffer and Huffman tree configuration from the Huffman tree builder. It accesses the bitstream buffers memory to retrieve bitstream data in reversed byte order and runs it through an array of comparators to decode Huffman code to correct literals values. -#### Literals buffer +##### Literals buffer This stage receives data either from RAW, RLE or Huffman decoder and stores it. Upon receiving the literals copy command from the Command Constructor for `N` number of bytes, it provides a reply with `N` literals. -### FSE Huffman decoder architecture +#### FSE Huffman decoder architecture ![](img/ZSTD_compressed_block_Huffman_decoder.png) -#### Huffman tree decoder dispatcher +##### Huffman tree decoder dispatcher This stage parses and consumes the Huffman tree description header. Based on the value of the Huffman descriptor header, it passes the tree description to the FSE decoder or to direct weight extraction. -#### FSE weight decoder +##### FSE weight decoder This stage performs multiple functions. 1. It decodes and builds the FSE distribution table. 2. It stores all remaining bitstream data. 3. After receiving the last byte, it translates the bitstream to Huffman weights using 2 interleaved FSE streams. -#### Direct weight decoder +##### Direct weight decoder This stage takes the incoming bytes and translates them to the stream of Huffman tree weights. The first byte of the transfer defines the number of symbols to be decoded. -#### Weight aggregator +##### Weight aggregator This stage receives tree weights either from the FSE decoder or the direct decoder and transfers them to Huffman tree builder. This stage also resolves the number of bits of the final weight and the max number of bits required in the tree representation. This stage will emit the weights and number of symbols of the same weight before the current symbol for all possible byte values. -#### Huffman tree builder +##### Huffman tree builder This stage takes `max_number_of_bits` (maximal length of Huffman code) as the first value, then the number of symbols with lower weight for each possible weight (11 bytes), followed by a tuple (number of preceding symbols with the same weight, symbol's_weight). It's expected to receive weights for all possible byte values in the correct order. Based on this information, this stage will configure the Huffman codes decoder. -### Sequence path architecture +#### Sequence path architecture ![](img/ZSTD_compressed_block_sequence_decoder.png) -#### Sequence Header parser and dispatcher +##### Sequence Header parser and dispatcher This stage parses and consumes `Sequences_Section_Header`. Based on the parsed data, it redirects FSE description to the FSE table decoder and triggers Literals FSE, Offset FSE or Match FSE decoder to reconfigure its values based on the FSE table decoder. After parsing the FSE tables, this stage buffers bitstream and starts sending bytes, starting from the last one received as per ZSTD format. @@ -216,37 +320,24 @@ Bytes are sent to all decoders at the same time. This stage monitors and triggers sequence decoding phases starting from initialization, followed by decode and state advance. FSE decoders send each other the number of bits they read. -#### Literals FSE decoder +##### Literals FSE decoder This stage reconfigures its FSE table when triggered from [sequence header parse and dispatcher](#sequence-header-parser-and-dispatcher). It initializes its state as the first FSE decoder. In the decode phase, this stage is the last one to decode extra raw bits from the bitstream, and the number of ingested bits is transmitted to all other decoders. This stage is the first stage to get a new FSE state from the bitstream, and it transmits the number of bits it used. -#### Offset FSE decoder +##### Offset FSE decoder This stage reconfigures its FSE table when triggered from [sequence header parse and dispatcher](#sequence-header-parser-and-dispatcher). It initializes its state as the second FSE decoder. In the decode phase, this stage is the first one to decode extra raw bits from bitstream, and the number of ingested bits is transmitted to all other decoders. This stage is the last decoder to update its FSE state after the decode phase, and it transmits the number of used bits to other decoders. -#### Match FSE decoder +##### Match FSE decoder This stage reconfigures its FSE table when triggered from [sequence header parse and dispatcher](#sequence-header-parser-and-dispatcher). It initializes its state as the last FSE decoder. In the decode phase, this stage is the second one to decode extra raw bits from the bitstream, and the number of ingested bits is transmitted to all other decoders. This stage is the second stage to update its state after the decode phase, and the number of used bits is sent to all other decoders. -### Repacketizer -This proc is used at the end of the processing flow in the ZSTD decoder. -It gathers the output of `SequenceExecutor` proc and processes it to form final output packets of the ZSTD decoder. -Input packets coming from the `SequenceExecutor` consist of: - -* data - bit vector of constant length -* length - field describing how many bits in bit vector are valid -* last - flag which marks the last packet in currently decoded ZSTD frame. - -It is not guaranteed that all bits in data bit vectors in packets received from `SequenceExecutor` are valid as those can include padding bits which were added in previous decoding steps and now have to be removed. -Repacketizer buffers input packets, removes the padding bits and forms new packets with all bits of the bit vector valid, meaning that all bits are decoded data. -Newly formed packets are then sent out to the output of the whole ZSTD decoder. - ## Testing methodology Testing of the `ZSTD decoder` is carried out on two levels: @@ -255,14 +346,22 @@ Testing of the `ZSTD decoder` is carried out on two levels: * Integrated decoder Each component of the decoder is tested individually in DSLX tests. -Testing on the DSLX level allows the creation of small test cases that test for both positive and negative outcomes of a given part of the design. +Testing on the DSLX level allows the creation of small test cases that test for positive outcomes of a given part of the design. When need be, those test cases can be also modified by the user to better understand how the component operates. -Tests of the integrated ZSTD decoder are written in C++. +Tests of the integrated ZSTD decoder are carried out on DSLX and Verilog levels. The objective of those is to verify the functionality of the decoder as a whole. Testing setup for the ZSTD decoder is based on comparing the simulated decoding results against the decoding of the reference library. Currently, due to the restrictions from the ZSTD frame generator, it is possible to test only the positive cases (decoding valid ZSTD frames). +ZstdDecoder's main communication interfaces are the AXI buses. +Due to the way XLS handles the codegen of DSLX channels that model the AXI channels, the particular ports of the AXI channels are not represented correctly. +This enforces the introduction of a Verilog wrapper that maps the ports generated by XLS into proper AXI ports (see AXI peripherals [README](memory/README.md) for more information). +Additionally, the wrapper is used to mux multiple AXI interfaces from `Memory Readers` into a single outside-facing AXI interface (`Memory Interface`) that can be connected to the external memory. +The mux is implemented by a third-party [AXI Interconnect](https://github.com/alexforencich/verilog-axi). + +![](img/ZSTD_decoder_wrapper.png) + ### Failure points #### User-facing decoder errors @@ -274,19 +373,8 @@ The design will fail the tests under the following conditions: * Simulation encounters `assert!()` or `fail!()` statements * The decoding result from the simulation has a different size than the results from the reference library * The decoding result from the simulation has different contents than the results from the reference library -* Caveats: - * Timeout occurred while waiting for a valid `Magic Number` to start the decoding process - * Other timeouts occurring while waiting on channel operations (To be fixed) Currently, all mentioned conditions lead to an eventual test failure. -Most of those cases are handled properly while some are yet to be reworked to finish faster or to provide more information about the error. -For example, in case of transitioning to the `ERROR` state, the test will timeout on channel operations waiting to read from the decoder output. -In case of waiting for a valid `Magic Number`, the decoder will transition to an `ERROR` state without registering the correct `Magic Number` on the input channel which will lead to a similar timeout. - -Those cases should be handled in a way that allows for early failure of the test. -It can be done through a Proc parameter enabled for tests that change the behavior of the logic, e.g. launching `assert!()` when the decoder enters the `ERROR` state. -Another idea is to use a special output channel for signaling internal states and errors to monitor the decoder for the errors encountered during decoding. -For example, in an invalid `Magic Number`, the test case should expect a certain type of error reported on this channel at the very beginning of the simulation. #### Failures in ZSTD Decoder components @@ -295,24 +383,20 @@ However, the majority of the errors require modification of the deeper parts of Because of that, it is better to rely on DSLX tests for the individual components where inputs for the test cases are smaller, easier to understand and modify when needed. The components of the ZSTD decoder can fail on `assert!()` and `fail!()` statements or propagate specific error states to the Top Level Proc and cause it to transition to the `ERROR` state. +Upon entering the `ERROR` state, the decoder will write a specific error code to the `Status` CSR and send a `Notify` signal to the output. +The interacting software can then read the code from the register and properly handle the error. + The following enumeration will describe how to trigger each possible ZSTD Decoder error. -The `ERROR` state can be encountered under the following conditions when running Top Level Proc C++ tests but also in DSLX tests for the specific components: -* Corrupted data on the `Magic Number` decoding stage +The `ERROR` state can be encountered under the following conditions when running Top Level Proc Verilog tests but also in DSLX tests for the specific components: +* Corrupted data on the frame header decoding stage * Provide data for the decoding with the first 4 bytes not being the valid `Magic Number` (0xFD2FB528) -* Corrupted data during frame header decoding * Set the `Reserved bit` in the frame header descriptor -* Unsupported Window Size during frame header decoding * Set `Window Size` in frame header to value greater than `max window size` calculated from current `WINDOW_LOG_MAX` (by default in Top Level Proc tests `Window Size` must be greater than `0x78000000` to trigger the error) * Corrupted data during Block Header decoding * Set the `Block Type` of any block in the ZSTD frame to `RESERVED` The `assert!()` or `fail!()` will occur in: -* Buffer - * Add data to the buffer with `buffer_append()` when it is already full or unable to fit the whole length of the data - * Fetch data from the buffer with `buffer_pop()` when it is empty or have not enough data -* DecoderDemux - * Receive more than one `raw` or `compressed` block in a single `BlockDataPacket` * RawBlockDecoder * Receive `BlockDataPacket` with `ID` different than the previous packet which did not have the `last` flag set * DecoderMux @@ -321,62 +405,9 @@ The `assert!()` or `fail!()` will occur in: * SequenceExecutor * Receive `SequenceExecutorPacket` with `msg_type==SEQUENCE` and `content` field with value: `0` -There are also several `impossible cases` covered by `assert!()` and `fail!()`: +There are also several `impossible cases` covered by `fail!()`. +Those are mostly enforced by the type checker for the `match` expressions to cover unreachable cases. +This is done for example in: * Frame header decoder - * `Window Descriptor` does not exist after checking that it is available in the frame header - * `Frame Content Size` does not exist after checking that it is available in the frame header - * `Dictionary ID Flag` has an illegal value - * `Frame Content Size Flag` has an illegal value -* DecoderDemux - * Data packet has a different `Block Type` than `RAW`, `RLE` or `COMPRESSED` * SequenceExecutor - * Proc transitions to `SEQUENCE_READ` state after receiving `SequenceExecutorPacket` with `msg_type` different than `SEQUENCE` or the message was invalid -* Top Level Proc - * Block header type is different than `RAW`, `RLE`, `COMPRESSED` - * There is not enough data to feed the `BlockDecoder`, even though the previous check indicated a valid amount of data in the buffer - -### Testing against [libzstd](https://github.com/facebook/zstd) - -Design is verified by comparing decoding results to the reference library `libzstd`. -ZSTD frames used for testing are generated with [decodecorpus](https://github.com/facebook/zstd/blob/dev/tests/decodecorpus.c) utility. -The generated frame is then decoded with `libzstd`. - -#### Positive test cases - -If the results of decoding with `libzstd` are valid, the test runs the same encoded frame through the simulation of DSLX design. -The output of the simulation is gathered and compared with the results of `libzstd` in terms of its size and contents. - -Encoded ZSTD frame is generated with the function `GenerateFrame(int seed, BlockType btype)` from [data_generator](https://github.com/antmicro/xls/blob/52186-zstd-top/xls/modules/zstd/data_generator.cc) library. -This function takes as arguments the seed for the generator and enum which codes the type of blocks that should be generated in a given frame. -The available block types are: - -* RAW -* RLE -* COMPRESSED -* RANDOM - -The function returns a vector of bytes representing a valid encoded ZSTD frame. -Such generated frame can be passed to `ParseAndCompareWithZstd(std::vector frame)` which is responsible for decoding the frame, running simulation and comparing the results. - -Tests are available in the `zstd_dec_test.cc` file and can be launched with the following Bazel command: - -``` -bazel test //xls/modules/zstd:zstd_dec_cc_test -``` - -#### Negative test cases - -Currently, `decodecorpus` does not support generating ZSTD frames with subtle errors that trigger failure points provided in the ZSTD Decoder. -Because of that, it is not possible to efficiently provide valuable negative tests for the integrated ZSTD Decoder. - -The alternatives for writing negative tests include: - -* Generating a well-known valid ZSTD frame from a specific generator seed and then tweaking the raw bits in this frame to trigger the error response from the decoder -* Using [FuzzTest](https://github.com/google/fuzztest) to create multiple randomized test cases for the decoder and then compare `libzstd` decoder failure with `ZSTD Decoder` failure. - -### Known Limitations - -* **[WIP]** Bugs in the current flow cause failures in some of the test cases of decoding ZSTD frame with RLE block types -* **[WIP]** Compressed block type is not supported -* Checksum is not being verified diff --git a/xls/modules/zstd/img/ZSTD_decoder.png b/xls/modules/zstd/img/ZSTD_decoder.png index f157751512745dc923beec4b242377fe3962eb89..494926d89f7108623b2a4d958d1980b9a34f75cc 100644 GIT binary patch literal 315264 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      o`n4 zH3K;(o6B25nJSU0aAG=Ft~p4(?csPJv%D*YbMrFI%YWDtdO|{Qs&_e;a4C@(-dcXf!km+0G8DpX}ai7@rdH9o^g zIWpeSmx73YSv3^yfB>7+lsQEx*kL-!E6hO&JTLuBTdxbGNz9MggF1x9W*LgVHydo2 zE7*!FRxp%5HXVbR3)FTOn$L;b+?{ZI{bo&tJ){Q@JgfL)|OD^w;2q)D-va5zM; z11`j5fAcE%q4z9=T(kn3bP-0~8W`#{rAhB#+8c5H;$_!6*YW->nM1=MLc91EtNvc> z{}siMD)%{DmW^!ch`TcFZf%W=#vloiO(sQ%mj7SWQz|MI#NYah9NhS}n(?TM zukG}AZf`GbVc<*QdV4~If8}2~0*NR>B@4QMGRF<2bj^9J63c<&B=@gVFDRoaZo-fC zAQ%!rQ^45nRXn+N;J8{qmUv!|0Vej_$N+W9s4PsG_Rj|A=OBEI z8DWs?1w{)VIoUy>km%=$ot`MQ1$hUyRo${}M~+_JeIOraIk+GEwM$4%w4KJEFEnr8 z00bO9QAKSNCYN*zX9#DVlcERne1g6?Uj6JJo#XOjS?*yP+<^9@yX5Zxko`F)S?_*dfJ3kfIRNp)Q3 zG^+pq;k$p?^|)8xH`l$1vVRt+46MP0Kl{FY_7%AM3AFMZbTk2QFmYkTG^X210-zm_ z3w5+T6$SDbi>-q%Kl6REZPr!Q_9iIp{fH6 z&M%bkqZ-&?S zU$=i1);u7Z1P{Os>*h!J+z?~z1sVrhBr3?U^1#*WF{-5fd( zfQHS02b!J&t|&Y@=Ob{Ny|QUmSa;=|irQ|0k0~*rh)hjS#hR8j9yzd$BLkSDmH`*} zqBm86HIxRZHMrx)64>@tSozPubk Date: Fri, 30 Aug 2024 13:52:13 +0200 Subject: [PATCH 16/85] modules/zstd: Add AxiRamReader implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Maciej Torhan Signed-off-by: Krzysztof Obłonczek --- xls/modules/zstd/memory/BUILD | 88 ++++ xls/modules/zstd/memory/axi.x | 17 +- xls/modules/zstd/memory/axi_ram.x | 767 ++++++++++++++++++++++++++++++ 3 files changed, 869 insertions(+), 3 deletions(-) create mode 100644 xls/modules/zstd/memory/axi_ram.x diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index 47cd431e77..c8ee0a7fc6 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -301,6 +301,94 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "axi_ram_dslx", + srcs = ["axi_ram.x"], + deps = [ + ":axi_dslx", + "//xls/examples:ram_dslx", + "//xls/modules/zstd:math_dslx", + ], +) + +xls_dslx_test( + name = "axi_ram_dslx_test", + library = ":axi_ram_dslx", +) + +xls_dslx_verilog( + name = "axi_ram_verilog", + codegen_args = { + "module_name": "AxiRam", + "delay_model": "asap7", + "ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram", + rd_req = "axi_ram__rd_req_s", + rd_resp = "axi_ram__rd_resp_r", + wr_req = "axi_ram__wr_req_s", + wr_resp = "axi_ram__wr_resp_r", + ), + "pipeline_stages": "8", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "AxiRamReaderInstWithEmptyWrites", + library = ":axi_ram_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__axi_ram__AxiRamReaderInstWithEmptyWrites__AxiRamReader_0__AxiRamReaderResponder_0__32_32_4_8_8_32768_7_32_4_100_next", + }, + tags = ["manual"], + verilog_file = "axi_ram.v", +) + +verilog_library( + name = "axi_ram_verilog_lib", + srcs = [ + ":axi_ram.v", + ], + tags = ["manual"], +) + +xls_benchmark_ir( + name = "axi_ram_opt_ir_benchmark", + src = ":axi_ram_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "4", + "delay_model": "asap7", + }, + tags = ["manual"], +) + +synthesize_rtl( + name = "axi_ram_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "AxiRam", + deps = [ + ":axi_ram_verilog_lib", + ], +) + +benchmark_synth( + name = "axi_ram_benchmark_synth", + synth_target = ":axi_ram_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "axi_ram_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":axi_ram_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + xls_dslx_library( name = "mem_reader_dslx", srcs = ["mem_reader.x"], diff --git a/xls/modules/zstd/memory/axi.x b/xls/modules/zstd/memory/axi.x index 09bfc194e2..d4b347f013 100644 --- a/xls/modules/zstd/memory/axi.x +++ b/xls/modules/zstd/memory/axi.x @@ -25,7 +25,18 @@ pub enum AxiAxSize : u3 { MAX_128B_TRANSFER = 7, } -pub enum AxiWriteResp : u3 { +pub const AXI_AXSIZE_ENCODING_TO_SIZE = u11[8]:[ + u11:8, + u11:16, + u11:32, + u11:64, + u11:128, + u11:256, + u11:512, + u11:1024, +]; + +pub enum AxiWriteResp: u3 { OKAY = 0, EXOKAY = 1, SLVERR = 2, @@ -95,12 +106,12 @@ pub struct AxiAw { pub struct AxiW { data: uN[DATA_W], strb: uN[STRB_W], - last: u1 + last: u1, } pub struct AxiB { resp: AxiWriteResp, - id: uN[ID_W] + id: uN[ID_W], } pub struct AxiAr { diff --git a/xls/modules/zstd/memory/axi_ram.x b/xls/modules/zstd/memory/axi_ram.x new file mode 100644 index 0000000000..28326a848d --- /dev/null +++ b/xls/modules/zstd/memory/axi_ram.x @@ -0,0 +1,767 @@ +// Copyright 2023-2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; + +import xls.modules.zstd.math; +import xls.modules.zstd.memory.axi; +import xls.examples.ram; + +type AxiAr = axi::AxiAr; +type AxiR = axi::AxiR; + +type AxiReadResp = axi::AxiReadResp; +type AxiAxBurst = axi::AxiAxBurst; + +const AXI_AXSIZE_ENCODING_TO_SIZE = axi::AXI_AXSIZE_ENCODING_TO_SIZE; + +enum AxiRamReaderStatus: u1 { + IDLE = 0, + READ_BURST = 1, +} + +// FIXME: add default value for RAM_DATA_W_LOG2 = {std::clog2(AXI_DATA_W + u32:1)} (https://github.com/google/xls/issues/992) +struct AxiRamReaderSync { + do_recv_ram_resp: bool, + read_data_size: uN[RAM_DATA_W_LOG2], + read_data_offset: uN[RAM_DATA_W_LOG2], + send_data: bool, + resp: AxiReadResp, + id: uN[AXI_ID_W], + last: bool, +} + +struct AxiRamReaderRequesterState { + status: AxiRamReaderStatus, + ar_bundle: AxiAr, + read_data_size: u32, + addr: uN[AXI_ADDR_W], + ram_rd_req_idx: u8, +} + +// FIXME: add default value for AXI_DATA_W_LOG2 = {std::clog2(AXI_DATA_W + u32:1)} (https://github.com/google/xls/issues/992) +struct AxiRamReaderResponderState { + data: uN[AXI_DATA_W], + data_size: uN[AXI_DATA_W_LOG2], +} + +// Translates RAM requests to AXI read requests +proc AxiRamReaderRequester< + // AXI parameters + AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_DEST_W: u32, AXI_ID_W: u32, + + // FIXME: The parameter below should be calculated correctly, + // but causes deduction errors. The issue is possibly related to: + // https://github.com/google/xls/issues/1523 + + // RAM parameters + RAM_SIZE: u32, + RAM_DATA_W: u32, // = {AXI_DATA_W}, + RAM_ADDR_W: u32, // = {AXI_ADDR_W}, + RAM_NUM_PARTITIONS: u32, // = {AXI_DATA_W / u32:8 }, + + BASE_ADDR: u32, // = {u32:0}, + AXI_DATA_W_DIV8: u32, // = { AXI_DATA_W / u32:8 } +> { + type AxiAr = axi::AxiAr; + // FIXME: Replace with params + type ReadReq = ram::ReadReq; + + type State = AxiRamReaderRequesterState; + type Status = AxiRamReaderStatus; + type Sync = AxiRamReaderSync; + + axi_ar_r: chan in; + rd_req_s: chan out; + + sync_s: chan out; + + init { zero!() } + + config( + // AXI interface + axi_ar_r: chan in, + rd_req_s: chan out, + sync_s: chan out, + ) { + (axi_ar_r, rd_req_s, sync_s) + } + + next(state: State) { + const AXI_DATA_W_LOG2 = std::flog2(AXI_DATA_W) + u32:1; + const RAM_DATA_W_LOG2 = std::flog2(RAM_DATA_W) + u32:1; + const RAM_DATA_W_DIV8 = RAM_DATA_W >> u32:3; + + // receive AXI read request + let (tok, ar_bundle, ar_bundle_valid) = recv_if_non_blocking(join(), axi_ar_r, state.status == Status::IDLE, zero!()); + + // validate bundle + let ar_bundle_ok = ar_bundle_valid && ((ar_bundle.size as u32 + u32:3) < AXI_DATA_W_LOG2); + + let tok = send_if(tok, sync_s, ar_bundle_valid && !ar_bundle_ok, Sync { + id: ar_bundle.id, + resp: AxiReadResp::SLVERR, + last: true, + send_data: true, + ..zero!() + }); + + // send RAM read reqest + let addr_valid = state.addr < ((RAM_SIZE * RAM_DATA_W_DIV8) as uN[AXI_ADDR_W]); + let addr = (state.addr / RAM_DATA_W_DIV8) as uN[RAM_ADDR_W]; + + let do_read_from_ram = ( + (state.status == Status::READ_BURST) && + addr_valid && + (state.ram_rd_req_idx <= state.ar_bundle.len) + ); + let ram_read_req = ReadReq { + addr: addr, + mask: !uN[RAM_NUM_PARTITIONS]:0, + }; + let tok = send_if(join(), rd_req_s, do_read_from_ram, ram_read_req); + if do_read_from_ram { + trace_fmt!("Sent RAM read request {:#x}", ram_read_req); + } else {}; + + // send sync + let resp = if addr_valid { + AxiReadResp::OKAY + } else { + AxiReadResp::DECERR + }; + + // calculate read size and offset + let arsize_bits = AXI_AXSIZE_ENCODING_TO_SIZE[state.ar_bundle.size as u3] as uN[AXI_DATA_W_LOG2]; + + let (read_data_size, read_data_offset) = if (arsize_bits > RAM_DATA_W as uN[AXI_DATA_W_LOG2]) { + ( + RAM_DATA_W as uN[RAM_DATA_W_LOG2], + uN[RAM_DATA_W_LOG2]:0, + ) + } else { + ( + arsize_bits, + ((state.addr % RAM_DATA_W_DIV8) << u32:3) as uN[RAM_DATA_W_LOG2], + ) + }; + + let tok = send_if(tok, sync_s, state.status == Status::READ_BURST, Sync { + do_recv_ram_resp: do_read_from_ram, + read_data_size: read_data_size, + read_data_offset: read_data_offset, + send_data: read_data_size == arsize_bits, + resp: resp, + id: state.ar_bundle.id, + last: state.ram_rd_req_idx == state.ar_bundle.len, + }); + + // update state + match state.status { + Status::IDLE => { + if ar_bundle_ok { + State { + status: AxiRamReaderStatus::READ_BURST, + ar_bundle: ar_bundle, + addr: ar_bundle.addr, + ram_rd_req_idx: u8:0, + read_data_size: u32:0, + } + } else { state } + }, + Status::READ_BURST => { + if (state.ram_rd_req_idx == state.ar_bundle.len) { + State { + status: Status::IDLE, + ..state + } + } else { + let incr = math::logshiftl(uN[AXI_ADDR_W]:1, state.ar_bundle.size as uN[AXI_ADDR_W]); + let addr = match state.ar_bundle.burst { + AxiAxBurst::FIXED => state.addr, + AxiAxBurst::INCR => state.addr + incr, + AxiAxBurst::WRAP => if ((state.addr + incr) >= (RAM_SIZE * RAM_DATA_W_DIV8)) { + uN[AXI_ADDR_W]:0 + } else { + state.addr + incr + }, + _ => fail!("invalid_burst_mode", state.addr), + }; + State { + ram_rd_req_idx: state.ram_rd_req_idx + u8:1, + addr: addr, + ..state + } + } + }, + _ => state, + } + } +} + +// Should translate RAM responses to AXI read responses +proc AxiRamReaderResponder< + // AXI parameters + AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_DEST_W: u32, AXI_ID_W: u32, + + // FIXME: The parameter below should be calculated correctly, + // but causes deduction errors. The issue is possibly related to: + // https://github.com/google/xls/issues/1523 + + // RAM parameters + RAM_SIZE: u32, + RAM_DATA_W: u32, // = {AXI_DATA_W}, + RAM_ADDR_W: u32, // = {AXI_ADDR_W}, + RAM_NUM_PARTITIONS: u32, // = {AXI_DATA_W / u32:8 }, + + BASE_ADDR: u32, // = {u32:0}, + AXI_DATA_W_DIV8: u32, // = { AXI_DATA_W / u32:8 } +> { + // FIXME: Replace with params + type AxiR = axi::AxiR; + type ReadResp = ram::ReadResp; + + // FIXME: Replace with params + type State = AxiRamReaderResponderState; + // FIXME: Replace with params + type Sync = AxiRamReaderSync; + + rd_resp_r: chan in; + axi_r_s: chan out; + + sync_r: chan in; + + init { zero!() } + + config( + rd_resp_r: chan in, + axi_r_s: chan out, + sync_r: chan in, + ) { + (rd_resp_r, axi_r_s, sync_r) + } + + next(state: State) { + let tok = join(); + + // receive sync + let (tok, sync_data) = recv(tok, sync_r); + trace_fmt!("Received sync {:#x}", sync_data); + + // receive RAM read respose + let (tok, ram_read_resp) = recv_if(tok, rd_resp_r, sync_data.do_recv_ram_resp, zero!()); + if sync_data.do_recv_ram_resp { + trace_fmt!("Received RAM response {:#x}", ram_read_resp); + } else {}; + + let mask = math::logshiftl(uN[RAM_DATA_W]:1, sync_data.read_data_size as uN[RAM_DATA_W]) - uN[RAM_DATA_W]:1; + let mask = math::logshiftl(mask, state.data_size); + + let ram_data_shifted = if (sync_data.read_data_offset > state.data_size) { + math::logshiftr(ram_read_resp.data, sync_data.read_data_offset - state.data_size) as uN[AXI_DATA_W] & mask + } else { + math::logshiftl(ram_read_resp.data, state.data_size - sync_data.read_data_offset) as uN[AXI_DATA_W] & mask + }; + + // update state + let state = State { + data: ram_data_shifted, + data_size: state.data_size + sync_data.read_data_size, + }; + + // send AXI read response + let axi_r_bundle = AxiR { + id: sync_data.id, + data: state.data, + resp: sync_data.resp, + last: sync_data.last, + }; + let tok = send_if(tok, axi_r_s, sync_data.send_data, axi_r_bundle); + + if sync_data.send_data { + zero!() + } else { + state + } + } +} + +proc AxiRamReader< + // AXI parameters + AXI_ADDR_W: u32, + AXI_DATA_W: u32, + AXI_DEST_W: u32, + AXI_ID_W: u32, + + // RAM parameters + RAM_SIZE: u32, + + // FIXME: The parameter below should be calculated correctly, + // but causes deduction errors. The issue is possibly related to: + // https://github.com/google/xls/issues/1523 + + RAM_DATA_W: u32, // = {AXI_DATA_W}, + RAM_ADDR_W: u32, // = {AXI_ADDR_W}, + RAM_NUM_PARTITIONS: u32, // = { AXI_DATA_W / u32:8 }, + + BASE_ADDR: u32, // = {u32:0}, + AXI_DATA_W_DIV8: u32, // = { AXI_DATA_W / u32:8 } +> { + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; + + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + + // FIXME: Replace with params + type Sync = AxiRamReaderSync; + + init { } + + config( + // AXI interface + axi_ar_r: chan in, + axi_r_s: chan out, + + // RAM interface + rd_req_s: chan out, + rd_resp_r: chan in, + ) { + let (sync_s, sync_r) = chan("sync"); + + spawn AxiRamReaderRequester< + AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, + RAM_SIZE, RAM_DATA_W, RAM_ADDR_W, RAM_NUM_PARTITIONS, + BASE_ADDR, AXI_DATA_W_DIV8, + >(axi_ar_r, rd_req_s, sync_s); + spawn AxiRamReaderResponder< + AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, + RAM_SIZE, RAM_DATA_W, RAM_ADDR_W, RAM_NUM_PARTITIONS, + BASE_ADDR, AXI_DATA_W_DIV8, + >(rd_resp_r, axi_r_s, sync_r); + } + + next(state: ()) { } +} + +const INST_AXI_ADDR_W = u32:32; +const INST_AXI_DATA_W = u32:32; +const INST_AXI_DEST_W = u32:8; +const INST_AXI_ID_W = u32:8; +const INST_AXI_DATA_W_DIV8 = INST_AXI_DATA_W / u32:8; + +const INST_RAM_SIZE = u32:100; +const INST_RAM_DATA_W = INST_AXI_DATA_W; +const INST_RAM_ADDR_W = std::clog2(INST_RAM_SIZE); +const INST_RAM_WORD_PARTITION_SIZE = u32:8; +const INST_RAM_NUM_PARTITIONS = INST_RAM_DATA_W / INST_RAM_WORD_PARTITION_SIZE; + +const INST_BASE_ADDR = u32:0x8000; + +proc AxiRamReaderInst< + FAKE_PARAM: u32 = {u32:0} // FIXME: remove after https://github.com/google/xls/issues/1415 is fixed +> { + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + + init { } + + config( + // AXI interface + axi_ar_r: chan in, + axi_r_s: chan out, + // RAM interface + rd_req_s: chan out, + rd_resp_r: chan in, + ) { + spawn AxiRamReader< + INST_AXI_ADDR_W, INST_AXI_DATA_W, INST_AXI_DEST_W, INST_AXI_ID_W, + INST_RAM_SIZE, INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, + INST_BASE_ADDR, INST_AXI_DATA_W_DIV8 + > (axi_ar_r, axi_r_s, rd_req_s, rd_resp_r); + } + + next(state: ()) { } +} + +// only for RAM rewrite +proc AxiRamReaderInstWithEmptyWrites { + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + wr_req_s: chan out; + wr_resp_r: chan in; + + init { } + + config( + // AXI interface + axi_ar_r: chan in, + axi_r_s: chan out, + // RAM interface + rd_req_s: chan out, + rd_resp_r: chan in, + wr_req_s: chan out, + wr_resp_r: chan in, + ) { + spawn AxiRamReader< + INST_AXI_ADDR_W, INST_AXI_DATA_W, INST_AXI_DEST_W, INST_AXI_ID_W, + INST_RAM_SIZE, INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, + INST_BASE_ADDR, INST_AXI_DATA_W_DIV8 + > (axi_ar_r, axi_r_s, rd_req_s, rd_resp_r); + + ( + wr_req_s, wr_resp_r + ) + } + + next(state: ()) { + send_if(join(), wr_req_s, false, zero!()); + recv_if(join(), wr_resp_r, false, zero!()); + } +} + +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_DATA_W = u32:32; +const TEST_AXI_DEST_W = u32:8; +const TEST_AXI_ID_W = u32:8; +const TEST_AXI_DATA_W_DIV8 = TEST_AXI_DATA_W / u32:8; + +const TEST_RAM_SIZE = u32:100; +const TEST_RAM_DATA_W = TEST_AXI_DATA_W; +const TEST_RAM_ADDR_W = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE = u32:8; +const TEST_RAM_NUM_PARTITIONS = TEST_RAM_DATA_W / TEST_RAM_WORD_PARTITION_SIZE; +const TEST_RAM_SIZE_BYTES = TEST_RAM_SIZE * (TEST_RAM_DATA_W / u32:8); + +const TEST_BASE_ADDR = u32:0x8000; + +type TestAxiAr = axi::AxiAr; +type TestAxiR = axi::AxiR; + +type TestReadReq = ram::ReadReq; +type TestReadResp = ram::ReadResp; +type TestWriteReq = ram::WriteReq; +type TestWriteResp = ram::WriteResp; + +const ZERO_AXI_AR_BUNDLE = zero!(); + +type TestAxiId = uN[TEST_AXI_ID_W]; +type TestAxiAddr = uN[TEST_AXI_ADDR_W]; +type TestAxiRegion = uN[4]; +type TestAxiLen = uN[8]; +type TestAxiSize = axi::AxiAxSize; +type TestAxiBurst = axi::AxiAxBurst; +type TestAxiCache = axi::AxiArCache; +type TestAxiProt = uN[3]; +type TestAxiQos = uN[4]; + +const TEST_RAM_DATA = u32[TEST_RAM_SIZE]:[ + u32:0xD945_50A5, u32:0xA20C_D8D3, u32:0xB0BE_D046, u32:0xF83C_6D26, u32:0xFAE4_B0C4, + u32:0x9A78_91C4, u32:0xFDA0_9B1E, u32:0x5E66_D76D, u32:0xCB7D_76CB, u32:0x4033_5F2F, + u32:0x2128_9B0B, u32:0xD263_365F, u32:0xD989_DD81, u32:0xE4CB_45C9, u32:0x0425_06B6, + u32:0x5D31_107C, u32:0x2282_7A67, u32:0xCAC7_0C94, u32:0x23A9_5FD8, u32:0x6122_BBC3, + u32:0x1F99_F3D0, u32:0xA70C_FB34, u32:0x3812_5EF2, u32:0x9157_61BC, u32:0x171A_C1B1, + + u32:0xDE6F_1B08, u32:0x420D_F1AF, u32:0xAEE9_F51B, u32:0xB31E_E3A3, u32:0x66AC_09D6, + u32:0x18E9_9703, u32:0xEE87_1E7A, u32:0xB63D_47DE, u32:0x59BF_4F52, u32:0x94D8_5636, + u32:0x2B81_34EE, u32:0x6711_9968, u32:0xFB2B_F8CB, u32:0x173F_CB1B, u32:0xFB94_3A67, + u32:0xF40B_714F, u32:0x383B_82FE, u32:0xA692_055E, u32:0x58A6_2110, u32:0x0185_B5E0, + u32:0x9DF0_9C22, u32:0x54CA_DB57, u32:0xC626_097F, u32:0xEA04_3110, u32:0xF11C_4D36, + + u32:0xB8CC_FAB0, u32:0x7801_3B20, u32:0x8189_BF9C, u32:0xE380_A505, u32:0x4672_AE34, + u32:0x1CD5_1B3A, u32:0x5F95_EE9E, u32:0xBC5C_9931, u32:0xBCE6_50D2, u32:0xC10D_0544, + u32:0x5AB4_DEA1, u32:0x5E20_3394, u32:0x7FDA_0CA1, u32:0x6FEC_112E, u32:0x107A_2F81, + u32:0x86CA_4491, u32:0xEA68_0EB7, u32:0x50F1_AA22, u32:0x3F47_F2CA, u32:0xE407_92F7, + u32:0xF35C_EEE0, u32:0x1D6B_E819, u32:0x3FA7_05FA, u32:0x08BB_A499, u32:0x7C0C_4812, + + u32:0xF5A5_3D5C, u32:0x079A_BE16, u32:0xACA1_F84B, u32:0x4D2B_9402, u32:0x45B1_28FD, + u32:0x2C7C_CBA5, u32:0x6874_FC32, u32:0x95A0_8288, u32:0xFB13_E707, u32:0x61F9_2FEF, + u32:0xF6E3_DAFC, u32:0xDBA0_0A80, u32:0xBB84_831B, u32:0xAD63_2520, u32:0xEFB3_D817, + u32:0xD190_C435, u32:0x9064_1E4F, u32:0x0839_3D28, u32:0x1C07_874C, u32:0xBBEB_D633, + u32:0xB0A9_C751, u32:0x83B9_A340, u32:0x028A_FF8A, u32:0xB4ED_EE5C, u32:0xD700_BD9C, +]; + +const TEST_AXI_AR_BUNDLES = TestAxiAr[16]:[ + AxiAr { + id: TestAxiId:0, + addr: TestAxiAddr:40, + len: TestAxiLen:8, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::FIXED, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:0, + addr: TestAxiAddr:440, + len: TestAxiLen:8, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::FIXED, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:1, + addr: TestAxiAddr:32, + len: TestAxiLen:8, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::FIXED, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:2, + addr: TestAxiAddr:16, + len: TestAxiLen:8, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:3, + addr: TestAxiAddr:92, + len: TestAxiLen:4, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:4, + addr: TestAxiAddr:0, + len: TestAxiLen:2, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:5, + addr: TestAxiAddr:52, + len: TestAxiLen:20, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:6, + addr: TestAxiAddr:96, + len: TestAxiLen:10, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:7, + addr: TestAxiAddr:128, + len: TestAxiLen:16, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::WRAP, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:8, + addr: TestAxiAddr:256, + len: TestAxiLen:2, + size: TestAxiSize::MAX_4B_TRANSFER, + burst: TestAxiBurst::WRAP, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:9, + addr: TestAxiAddr:32, + len: TestAxiLen:4, + size: TestAxiSize::MAX_2B_TRANSFER, + burst: TestAxiBurst::FIXED, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:10, + addr: TestAxiAddr:80, + len: TestAxiLen:4, + size: TestAxiSize::MAX_1B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:11, + addr: TestAxiAddr:256, + len: TestAxiLen:16, + size: TestAxiSize::MAX_2B_TRANSFER, + burst: TestAxiBurst::WRAP, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:12, + addr: TestAxiAddr:64, + len: TestAxiLen:2, + size: TestAxiSize::MAX_8B_TRANSFER, + burst: TestAxiBurst::FIXED, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:13, + addr: TestAxiAddr:192, + len: TestAxiLen:16, + size: TestAxiSize::MAX_64B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, + AxiAr { + id: TestAxiId:14, + addr: TestAxiAddr:16, + len: TestAxiLen:16, + size: TestAxiSize::MAX_128B_TRANSFER, + burst: TestAxiBurst::INCR, + ..ZERO_AXI_AR_BUNDLE + }, +]; + +#[test_proc] +proc AxiRamReaderTest { + terminator: chan out; + + axi_ar_s: chan out; + axi_r_r: chan in; + + wr_req_s: chan out; + wr_resp_r: chan in; + + init {} + + config( + terminator: chan out, + ) { + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + spawn ram::RamModel ( + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s + ); + + let (axi_ar_s, axi_ar_r) = chan("axi_ar"); + let (axi_r_s, axi_r_r) = chan("axi_r"); + + spawn AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_RAM_SIZE, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, TEST_RAM_NUM_PARTITIONS, + TEST_BASE_ADDR, TEST_AXI_DATA_W_DIV8, + >(axi_ar_r, axi_r_s, rd_req_s, rd_resp_r); + + ( + terminator, + axi_ar_s, axi_r_r, wr_req_s, wr_resp_r, + ) + } + + next(state: ()) { + type RamAddr = bits[TEST_RAM_ADDR_W]; + type RamData = bits[TEST_RAM_DATA_W]; + type RamMask = bits[TEST_RAM_NUM_PARTITIONS]; + + let tok = join(); + + // write test RAM data + let tok = for ((i, data), tok): ((u32, u32), token) in enumerate(TEST_RAM_DATA) { + let tok = send(tok, wr_req_s, TestWriteReq { + addr: i as RamAddr, + data: data, + mask: !bits[TEST_RAM_NUM_PARTITIONS]:0, + }); + let (tok, _) = recv(tok, wr_resp_r); + + tok + }(tok); + + let tok = for ((i, axi_ar_bundle), tok): ((u32, TestAxiAr), token) in enumerate(TEST_AXI_AR_BUNDLES) { + let tok = send(tok, axi_ar_s, axi_ar_bundle); + trace_fmt!("Sent bundle #{} {:#x}", i + u32:1, axi_ar_bundle); + + let size_valid = (u32:1 << (axi_ar_bundle.size as u32 + u32:3)) <= TEST_AXI_DATA_W; + + let data_len = if size_valid { + axi_ar_bundle.len as u32 + } else { + u32:0 + }; + + for (j, tok): (u32, token) in range(u32:0, TEST_RAM_SIZE) { + if (j <= data_len) { + let (tok, data) = recv(tok, axi_r_r); + trace_fmt!("Received data #{} {:#x}", j, data); + // compute address + let araddr = match axi_ar_bundle.burst { + AxiAxBurst::FIXED => { + axi_ar_bundle.addr + }, + AxiAxBurst::INCR => { + axi_ar_bundle.addr + j * (u32:1 << (axi_ar_bundle.size as u32)) + }, + AxiAxBurst::WRAP => { + (axi_ar_bundle.addr + j * (u32:1 << (axi_ar_bundle.size as u32))) % (TEST_RAM_SIZE * (TEST_RAM_DATA_W / u32:8)) + }, + }; + // create expected data using RAM data + let (expected_data, addr_valid) = for (k, (expected_data, addr_valid)): (u32, (uN[TEST_AXI_DATA_W], bool)) in range(u32:0, TEST_AXI_DATA_W / u32:8) { + if k < (u32:1 << (axi_ar_bundle.size as u32)) { + let ram_addr = (araddr + k) / (TEST_RAM_DATA_W / u32:8); + let ram_offset = ((araddr + k) % (TEST_RAM_DATA_W / u32:8)) * u32:8; + if ram_addr < TEST_RAM_SIZE { + ( + expected_data | (((TEST_RAM_DATA[ram_addr] >> ram_offset) & u32:0xFF) << (u32:8 * k)), + addr_valid, + ) + } else { + ( + uN[TEST_AXI_DATA_W]:0, + false, + ) + } + } else { + ( + expected_data, + addr_valid + ) + } + }((uN[TEST_AXI_DATA_W]:0, true)); + + let expected_rresp = if !size_valid { + AxiReadResp::SLVERR + } else if addr_valid { + AxiReadResp::OKAY + } else { + AxiReadResp::DECERR + }; + + assert_eq(expected_rresp, data.resp); + assert_eq(j == data_len, data.last); + assert_eq(axi_ar_bundle.id, data.id); + if expected_rresp == AxiReadResp::OKAY { + // valid read + assert_eq(expected_data, data.data); + } else { }; + tok + } else { tok } + }(tok) + }(tok); + + send(tok, terminator, true); + } +} + + From 34db10a243ba6e1d494ce9e3d6b1b90984e15efc Mon Sep 17 00:00:00 2001 From: Krzysztof Oblonczek Date: Mon, 12 May 2025 19:37:09 +0200 Subject: [PATCH 17/85] Adjust to changes in toolchain --- xls/modules/zstd/axi_csr_accessor.x | 13 +- xls/modules/zstd/memory/BUILD | 2 +- xls/modules/zstd/memory/axi_ram.x | 130 +++++++-------- xls/modules/zstd/sequence_executor.x | 2 +- xls/modules/zstd/zstd_dec.x | 237 +++------------------------ 5 files changed, 95 insertions(+), 289 deletions(-) diff --git a/xls/modules/zstd/axi_csr_accessor.x b/xls/modules/zstd/axi_csr_accessor.x index 01cef68cd9..860b36fe36 100644 --- a/xls/modules/zstd/axi_csr_accessor.x +++ b/xls/modules/zstd/axi_csr_accessor.x @@ -89,15 +89,16 @@ pub proc AxiCsrAccessor< let tok_0 = join(); // write to CSR via AXI let (tok_1_1, axi_aw, axi_aw_valid) = recv_non_blocking(tok_0, axi_aw_r, AxiAw {id: state.w_id, addr: state.w_addr, ..zero!()}); - // validate axi aw - assert!(!(axi_aw_valid && axi_aw.addr as u32 >= REGS_N), "invalid_aw_addr"); + assert!(!(axi_aw_valid && axi_aw.addr as u32 >= (REGS_N << LOG2_DATA_W_DIV8)), "invalid_aw_addr"); assert!(!(axi_aw_valid && axi_aw.len != u8:0), "invalid_aw_len"); let (tok_1_2, axi_w, axi_w_valid) = recv_non_blocking(tok_1_1, axi_w_r, zero!()); // Send WriteRequest to CSRs let data_w = if axi_w_valid { + trace_fmt!("[CSR ACCESSOR] received csr write at {:#x}", axi_w); + let (w_data, _, _) = for (i, (w_data, strb, mask)): (u32, (uN[DATA_W], uN[DATA_W_DIV8], uN[DATA_W])) in range(u32:0, DATA_W_DIV8) { let w_data = if axi_w.strb as u1 { w_data | (axi_w.data & mask) @@ -133,7 +134,7 @@ pub proc AxiCsrAccessor< // Send ReadRequest to CSRs let (tok_3_1, axi_ar, axi_ar_valid) = recv_non_blocking(tok_0, axi_ar_r, AxiAr {id: state.r_id, addr: state.r_addr, ..zero!()}); // validate ar bundle - assert!(!(axi_ar_valid && axi_ar.addr as u32 >= REGS_N), "invalid_ar_addr"); + assert!(!(axi_ar_valid && axi_ar.addr as u32 >= (REGS_N << LOG2_DATA_W_DIV8)), "invalid_ar_addr"); assert!(!(axi_ar_valid && axi_ar.len != u8:0), "invalid_ar_len"); let rd_req = RdReq { csr: (axi_ar.addr >> LOG2_DATA_W_DIV8) as uN[LOG2_REGS_N], @@ -208,7 +209,7 @@ proc AxiCsrAccessorInst { const TEST_ID_W = u32:4; const TEST_DATA_W = u32:32; const TEST_ADDR_W = u32:16; -const TEST_REGS_N = u32:16; +const TEST_REGS_N = u32:4; const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; const TEST_LOG2_REGS_N = std::clog2(TEST_REGS_N); const TEST_LOG2_DATA_W_DIV8 = std::clog2(TEST_DATA_W_DIV8); @@ -309,7 +310,7 @@ proc AxiCsrAccessorTest { // write CSR via AXI let axi_aw = TestAxiAw { id: i as uN[TEST_ID_W], - addr: (test_data.csr << TEST_LOG2_DATA_W_DIV8) as uN[TEST_ADDR_W], + addr: (test_data.csr as uN[TEST_ADDR_W]) << TEST_LOG2_DATA_W_DIV8, size: axi::AxiAxSize::MAX_4B_TRANSFER, len: u8:0, burst: axi::AxiAxBurst::FIXED, @@ -346,7 +347,7 @@ proc AxiCsrAccessorTest { // read CSRs via AXI let axi_ar = TestAxiAr { id: i as uN[TEST_ID_W], - addr: (test_data.csr << TEST_LOG2_DATA_W_DIV8) as uN[TEST_ADDR_W], + addr: (test_data.csr as uN[TEST_ADDR_W]) << TEST_LOG2_DATA_W_DIV8, len: u8:0, ..zero!() }; diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index c8ee0a7fc6..96e824b19c 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -337,7 +337,7 @@ xls_dslx_verilog( library = ":axi_ram_dslx", opt_ir_args = { "inline_procs": "true", - "top": "__axi_ram__AxiRamReaderInstWithEmptyWrites__AxiRamReader_0__AxiRamReaderResponder_0__32_32_4_8_8_32768_7_32_4_100_next", + "top": "__axi_ram__AxiRamReaderInstWithEmptyWrites__AxiRamReader_0__AxiRamReaderResponder_0__32_32_4_5_6_8_8_32768_7_32_5_6_4_100_next", }, tags = ["manual"], verilog_file = "axi_ram.v", diff --git a/xls/modules/zstd/memory/axi_ram.x b/xls/modules/zstd/memory/axi_ram.x index 28326a848d..9683e61fc6 100644 --- a/xls/modules/zstd/memory/axi_ram.x +++ b/xls/modules/zstd/memory/axi_ram.x @@ -31,11 +31,11 @@ enum AxiRamReaderStatus: u1 { READ_BURST = 1, } -// FIXME: add default value for RAM_DATA_W_LOG2 = {std::clog2(AXI_DATA_W + u32:1)} (https://github.com/google/xls/issues/992) -struct AxiRamReaderSync { +// FIXME: add default value for RAM_DATA_W_PLUS1_LOG2 = {std::clog2(AXI_DATA_W + u32:1)} (https://github.com/google/xls/issues/992) +struct AxiRamReaderSync { do_recv_ram_resp: bool, - read_data_size: uN[RAM_DATA_W_LOG2], - read_data_offset: uN[RAM_DATA_W_LOG2], + read_data_size: uN[RAM_DATA_W_PLUS1_LOG2], + read_data_offset: uN[RAM_DATA_W_PLUS1_LOG2], send_data: bool, resp: AxiReadResp, id: uN[AXI_ID_W], @@ -50,10 +50,10 @@ struct AxiRamReaderRequesterState { ram_rd_req_idx: u8, } -// FIXME: add default value for AXI_DATA_W_LOG2 = {std::clog2(AXI_DATA_W + u32:1)} (https://github.com/google/xls/issues/992) -struct AxiRamReaderResponderState { +// FIXME: add default value for AXI_DATA_W_PLUS1_LOG2 = {std::clog2(AXI_DATA_W + u32:1)} (https://github.com/google/xls/issues/992) +struct AxiRamReaderResponderState { data: uN[AXI_DATA_W], - data_size: uN[AXI_DATA_W_LOG2], + data_size: uN[AXI_DATA_W_PLUS1_LOG2], } // Translates RAM requests to AXI read requests @@ -61,26 +61,25 @@ proc AxiRamReaderRequester< // AXI parameters AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_DEST_W: u32, AXI_ID_W: u32, - // FIXME: The parameter below should be calculated correctly, - // but causes deduction errors. The issue is possibly related to: - // https://github.com/google/xls/issues/1523 - // RAM parameters RAM_SIZE: u32, - RAM_DATA_W: u32, // = {AXI_DATA_W}, - RAM_ADDR_W: u32, // = {AXI_ADDR_W}, - RAM_NUM_PARTITIONS: u32, // = {AXI_DATA_W / u32:8 }, - - BASE_ADDR: u32, // = {u32:0}, - AXI_DATA_W_DIV8: u32, // = { AXI_DATA_W / u32:8 } + BASE_ADDR: u32 = {u32:0}, + RAM_DATA_W: u32 = {AXI_DATA_W}, + RAM_ADDR_W: u32 = {AXI_ADDR_W}, + RAM_NUM_PARTITIONS: u32 = {AXI_DATA_W / u32:8 }, + + AXI_DATA_W_DIV8: u32 = { AXI_DATA_W / u32:8 }, + RAM_DATA_W_LOG2: u32 = { std::clog2(RAM_DATA_W) }, + AXI_DATA_W_LOG2: u32 = { std::clog2(AXI_DATA_W) }, + AXI_DATA_W_PLUS1_LOG2: u32 = { std::clog2(AXI_DATA_W + u32:1) }, + RAM_DATA_W_PLUS1_LOG2: u32 = { std::clog2(RAM_DATA_W + u32:1) }, > { type AxiAr = axi::AxiAr; - // FIXME: Replace with params - type ReadReq = ram::ReadReq; + type ReadReq = ram::ReadReq; type State = AxiRamReaderRequesterState; type Status = AxiRamReaderStatus; - type Sync = AxiRamReaderSync; + type Sync = AxiRamReaderSync; axi_ar_r: chan in; rd_req_s: chan out; @@ -99,16 +98,16 @@ proc AxiRamReaderRequester< } next(state: State) { - const AXI_DATA_W_LOG2 = std::flog2(AXI_DATA_W) + u32:1; - const RAM_DATA_W_LOG2 = std::flog2(RAM_DATA_W) + u32:1; const RAM_DATA_W_DIV8 = RAM_DATA_W >> u32:3; // receive AXI read request let (tok, ar_bundle, ar_bundle_valid) = recv_if_non_blocking(join(), axi_ar_r, state.status == Status::IDLE, zero!()); // validate bundle - let ar_bundle_ok = ar_bundle_valid && ((ar_bundle.size as u32 + u32:3) < AXI_DATA_W_LOG2); - + let ar_bundle_ok = ar_bundle_valid && ((ar_bundle.size as u32 + u32:3) <= AXI_DATA_W_LOG2); + if ar_bundle_valid { + trace_fmt!("{:#x}", ar_bundle); + } else {}; let tok = send_if(tok, sync_s, ar_bundle_valid && !ar_bundle_ok, Sync { id: ar_bundle.id, resp: AxiReadResp::SLVERR, @@ -143,17 +142,17 @@ proc AxiRamReaderRequester< }; // calculate read size and offset - let arsize_bits = AXI_AXSIZE_ENCODING_TO_SIZE[state.ar_bundle.size as u3] as uN[AXI_DATA_W_LOG2]; + let arsize_bits = AXI_AXSIZE_ENCODING_TO_SIZE[state.ar_bundle.size as u3] as uN[AXI_DATA_W_PLUS1_LOG2]; - let (read_data_size, read_data_offset) = if (arsize_bits > RAM_DATA_W as uN[AXI_DATA_W_LOG2]) { + let (read_data_size, read_data_offset) = if (arsize_bits > RAM_DATA_W as uN[AXI_DATA_W_PLUS1_LOG2]) { ( - RAM_DATA_W as uN[RAM_DATA_W_LOG2], - uN[RAM_DATA_W_LOG2]:0, + RAM_DATA_W as uN[RAM_DATA_W_PLUS1_LOG2], + uN[RAM_DATA_W_PLUS1_LOG2]:0, ) } else { ( arsize_bits, - ((state.addr % RAM_DATA_W_DIV8) << u32:3) as uN[RAM_DATA_W_LOG2], + ((state.addr % RAM_DATA_W_DIV8) << u32:3) as uN[RAM_DATA_W_PLUS1_LOG2], ) }; @@ -215,27 +214,24 @@ proc AxiRamReaderResponder< // AXI parameters AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_DEST_W: u32, AXI_ID_W: u32, - // FIXME: The parameter below should be calculated correctly, - // but causes deduction errors. The issue is possibly related to: - // https://github.com/google/xls/issues/1523 - // RAM parameters RAM_SIZE: u32, - RAM_DATA_W: u32, // = {AXI_DATA_W}, - RAM_ADDR_W: u32, // = {AXI_ADDR_W}, - RAM_NUM_PARTITIONS: u32, // = {AXI_DATA_W / u32:8 }, - - BASE_ADDR: u32, // = {u32:0}, - AXI_DATA_W_DIV8: u32, // = { AXI_DATA_W / u32:8 } + BASE_ADDR: u32 = {u32:0}, + RAM_DATA_W: u32 = {AXI_DATA_W}, + RAM_ADDR_W: u32 = {AXI_ADDR_W}, + RAM_NUM_PARTITIONS: u32 = {AXI_DATA_W / u32:8 }, + + AXI_DATA_W_DIV8: u32 = { AXI_DATA_W / u32:8 }, + AXI_DATA_W_LOG2: u32 = { std::clog2(AXI_DATA_W) }, + RAM_DATA_W_LOG2: u32 = { std::clog2(RAM_DATA_W) }, + AXI_DATA_W_PLUS1_LOG2: u32 = { std::clog2(AXI_DATA_W + u32:1) }, + RAM_DATA_W_PLUS1_LOG2: u32 = { std::clog2(RAM_DATA_W + u32:1) }, > { - // FIXME: Replace with params - type AxiR = axi::AxiR; + type AxiR = axi::AxiR; type ReadResp = ram::ReadResp; - // FIXME: Replace with params - type State = AxiRamReaderResponderState; - // FIXME: Replace with params - type Sync = AxiRamReaderSync; + type State = AxiRamReaderResponderState; + type Sync = AxiRamReaderSync; rd_resp_r: chan in; axi_r_s: chan out; @@ -297,7 +293,7 @@ proc AxiRamReaderResponder< } } -proc AxiRamReader< +pub proc AxiRamReader< // AXI parameters AXI_ADDR_W: u32, AXI_DATA_W: u32, @@ -306,17 +302,14 @@ proc AxiRamReader< // RAM parameters RAM_SIZE: u32, - - // FIXME: The parameter below should be calculated correctly, - // but causes deduction errors. The issue is possibly related to: - // https://github.com/google/xls/issues/1523 - - RAM_DATA_W: u32, // = {AXI_DATA_W}, - RAM_ADDR_W: u32, // = {AXI_ADDR_W}, - RAM_NUM_PARTITIONS: u32, // = { AXI_DATA_W / u32:8 }, - - BASE_ADDR: u32, // = {u32:0}, - AXI_DATA_W_DIV8: u32, // = { AXI_DATA_W / u32:8 } + BASE_ADDR: u32 = {u32:0}, + RAM_DATA_W: u32 = {AXI_DATA_W}, + RAM_ADDR_W: u32 = {AXI_ADDR_W}, + RAM_NUM_PARTITIONS: u32 = { AXI_DATA_W / u32:8 }, + + AXI_DATA_W_DIV8: u32 = { AXI_DATA_W / u32:8 }, + RAM_DATA_W_LOG2: u32 = { std::clog2(RAM_DATA_W) }, + RAM_DATA_W_PLUS1_LOG2: u32 = { std::clog2(RAM_DATA_W + u32:1) }, > { type AxiAr = axi::AxiAr; type AxiR = axi::AxiR; @@ -324,8 +317,7 @@ proc AxiRamReader< type ReadReq = ram::ReadReq; type ReadResp = ram::ReadResp; - // FIXME: Replace with params - type Sync = AxiRamReaderSync; + type Sync = AxiRamReaderSync; init { } @@ -342,13 +334,13 @@ proc AxiRamReader< spawn AxiRamReaderRequester< AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, - RAM_SIZE, RAM_DATA_W, RAM_ADDR_W, RAM_NUM_PARTITIONS, - BASE_ADDR, AXI_DATA_W_DIV8, + RAM_SIZE, BASE_ADDR, RAM_DATA_W, RAM_ADDR_W, RAM_NUM_PARTITIONS, + AXI_DATA_W_DIV8, >(axi_ar_r, rd_req_s, sync_s); spawn AxiRamReaderResponder< AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, - RAM_SIZE, RAM_DATA_W, RAM_ADDR_W, RAM_NUM_PARTITIONS, - BASE_ADDR, AXI_DATA_W_DIV8, + RAM_SIZE, BASE_ADDR, RAM_DATA_W, RAM_ADDR_W, RAM_NUM_PARTITIONS, + AXI_DATA_W_DIV8, >(rd_resp_r, axi_r_s, sync_r); } @@ -389,8 +381,8 @@ proc AxiRamReaderInst< ) { spawn AxiRamReader< INST_AXI_ADDR_W, INST_AXI_DATA_W, INST_AXI_DEST_W, INST_AXI_ID_W, - INST_RAM_SIZE, INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, - INST_BASE_ADDR, INST_AXI_DATA_W_DIV8 + INST_RAM_SIZE, INST_BASE_ADDR, INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, + INST_AXI_DATA_W_DIV8 > (axi_ar_r, axi_r_s, rd_req_s, rd_resp_r); } @@ -423,8 +415,8 @@ proc AxiRamReaderInstWithEmptyWrites { ) { spawn AxiRamReader< INST_AXI_ADDR_W, INST_AXI_DATA_W, INST_AXI_DEST_W, INST_AXI_ID_W, - INST_RAM_SIZE, INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, - INST_BASE_ADDR, INST_AXI_DATA_W_DIV8 + INST_RAM_SIZE, INST_BASE_ADDR, INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, + INST_AXI_DATA_W_DIV8 > (axi_ar_r, axi_r_s, rd_req_s, rd_resp_r); ( @@ -659,8 +651,8 @@ proc AxiRamReaderTest { spawn AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, - TEST_RAM_SIZE, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, TEST_RAM_NUM_PARTITIONS, - TEST_BASE_ADDR, TEST_AXI_DATA_W_DIV8, + TEST_RAM_SIZE, TEST_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, TEST_RAM_NUM_PARTITIONS, + TEST_AXI_DATA_W_DIV8, >(axi_ar_r, axi_r_s, rd_req_s, rd_resp_r); ( diff --git a/xls/modules/zstd/sequence_executor.x b/xls/modules/zstd/sequence_executor.x index 78251408c5..1e01f9b03c 100644 --- a/xls/modules/zstd/sequence_executor.x +++ b/xls/modules/zstd/sequence_executor.x @@ -1140,7 +1140,7 @@ pub proc SequenceExecutor in; notify_s: chan<()> out; + reset_s: chan<()> out; init { zero!() @@ -190,6 +191,7 @@ proc ZstdDecoderInternal< rle_resp_r: chan in, notify_s: chan<()> out, + reset_s: chan<()> out, ) { ( csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, @@ -197,7 +199,7 @@ proc ZstdDecoderInternal< bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, - notify_s, + notify_s, reset_s, ) } @@ -214,6 +216,16 @@ proc ZstdDecoderInternal< let (tok1_0, csr_change, csr_change_valid) = recv_non_blocking(tok0, csr_change_r, zero!()); let is_start = (csr_change_valid && (csr_change.csr == csr(Csr::START))); + let is_reset = (csr_change_valid && (csr_change.csr == csr(Csr::RESET))); + let tok = send_if(tok0, reset_s, is_reset, ()); + if is_reset { + trace_fmt!("[[RESET]]"); + } else {}; + + if csr_change_valid { + trace_fmt!("[CSR CHANGE] {:#x}", csr_change); + } else {}; + let do_send_csr_req = (state.fsm == Fsm::READ_CONFIG) && (!state.conf_send); let csr_req = CSR_REQS[state.conf_cnt]; let tok1_1 = send_if(tok0, csr_rd_req_s, do_send_csr_req, csr_req); @@ -484,26 +496,8 @@ proc ZstdDecoderInternal< const TEST_AXI_DATA_W = u32:64; const TEST_AXI_ADDR_W = u32:32; -const TEST_AXI_ID_W = u32:8; -const TEST_AXI_DEST_W = u32:8; const TEST_REGS_N = u32:5; -const TEST_WINDOW_LOG_MAX = u32:30; - -const TEST_HB_ADDR_W = sequence_executor::ZSTD_RAM_ADDR_WIDTH; -const TEST_HB_DATA_W = sequence_executor::RAM_DATA_WIDTH; -const TEST_HB_NUM_PARTITIONS = sequence_executor::RAM_NUM_PARTITIONS; -const TEST_HB_SIZE_KB = sequence_executor::ZSTD_HISTORY_BUFFER_SIZE_KB; - const TEST_LOG2_REGS_N = std::clog2(TEST_REGS_N); -const TEST_AXI_DATA_W_DIV8 = TEST_AXI_DATA_W / u32:8; -const TEST_HB_RAM_N = u32:8; - -const TEST_HB_SIZE = sequence_executor::ram_size(TEST_HB_SIZE_KB); -const TEST_HB_RAM_WORD_PARTITION_SIZE = sequence_executor::RAM_WORD_PARTITION_SIZE; -const TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = sequence_executor::TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR; -const TEST_HB_RAM_INITIALIZED = sequence_executor::TEST_RAM_INITIALIZED; -const TEST_HB_RAM_ASSERT_VALID_READ:bool = {false}; - #[test_proc] proc ZstdDecoderInternalTest { @@ -562,6 +556,7 @@ proc ZstdDecoderInternalTest { rle_resp_s: chan out; notify_r: chan<()> in; + reset_r: chan<()> in; init {} @@ -585,6 +580,7 @@ proc ZstdDecoderInternalTest { let (rle_resp_s, rle_resp_r) = chan("rle_resp"); let (notify_s, notify_r) = chan<()>("notify"); + let (reset_s, reset_r) = chan<()>("reset"); spawn ZstdDecoderInternal( csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, @@ -592,7 +588,7 @@ proc ZstdDecoderInternalTest { bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, - notify_s, + notify_s, reset_s, ); ( @@ -602,7 +598,7 @@ proc ZstdDecoderInternalTest { bh_req_r, bh_resp_s, raw_req_r, raw_resp_s, rle_req_r, rle_resp_s, - notify_r, + notify_r, reset_r, ) } @@ -760,7 +756,7 @@ proc ZstdDecoderInternalTest { } -proc ZstdDecoder< +pub proc ZstdDecoder< // AXI parameters AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, // decoder parameters @@ -875,6 +871,7 @@ proc ZstdDecoder< // Decoder output output_s: chan out, notify_s: chan<()> out, + reset_s: chan<()> out, ) { const CHANNEL_DEPTH = u32:1; @@ -1012,7 +1009,7 @@ proc ZstdDecoder< bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, - notify_s, + notify_s, reset_s, ); (cmp_output_s,) @@ -1023,192 +1020,6 @@ proc ZstdDecoder< } } -//#[test_proc] -//proc ZstdDecoderTest { -// type CsrAxiAr = axi::AxiAr; -// type CsrAxiR = axi::AxiR; -// type CsrAxiAw = axi::AxiAw; -// type CsrAxiW = axi::AxiW; -// type CsrAxiB = axi::AxiB; -// -// type CsrRdReq = csr_config::CsrRdReq; -// type CsrRdResp = csr_config::CsrRdResp; -// type CsrWrReq = csr_config::CsrWrReq; -// type CsrWrResp = csr_config::CsrWrResp; -// type CsrChange = csr_config::CsrChange; -// -// type MemAxiAr = axi::AxiAr; -// type MemAxiR = axi::AxiR; -// type MemAxiAw = axi::AxiAw; -// type MemAxiW = axi::AxiW; -// type MemAxiB = axi::AxiB; -// -// type RamRdReq = ram::ReadReq; -// type RamRdResp = ram::ReadResp; -// type RamWrReq = ram::WriteReq; -// type RamWrResp = ram::WriteResp; -// -// type ZstdDecodedPacket = common::ZstdDecodedPacket; -// terminator: chan out; -// -// init {} -// -// config(terminator: chan out) { -// -// let (csr_axi_aw_s, csr_axi_aw_r) = chan("csr_axi_aw"); -// let (csr_axi_w_s, csr_axi_w_r) = chan("csr_axi_w"); -// let (csr_axi_b_s, csr_axi_b_r) = chan("csr_axi_b"); -// let (csr_axi_ar_s, csr_axi_ar_r) = chan("csr_axi_ar"); -// let (csr_axi_r_s, csr_axi_r_r) = chan("csr_axi_r"); -// -// let (fh_axi_ar_s, fh_axi_ar_r) = chan("fh_axi_ar_s"); -// let (fh_axi_r_s, fh_axi_r_r) = chan("fh_axi_r_r"); -// -// let (bh_axi_ar_s, bh_axi_ar_r) = chan("bh_axi_ar"); -// let (bh_axi_r_s, bh_axi_r_r) = chan("bh_axi_r"); -// -// let (raw_axi_ar_s, raw_axi_ar_r) = chan("raw_axi_ar"); -// let (raw_axi_r_s, raw_axi_r_r) = chan("raw_axi_r"); -// -// let (rle_axi_ar_s, rle_axi_ar_r) = chan("rle_axi_ar"); -// let (rle_axi_r_s, rle_axi_r_r) = chan("rle_axi_r"); -// -// let (ram_rd_req_0_s, ram_rd_req_0_r) = chan("ram_rd_req_0"); -// let (ram_rd_req_1_s, ram_rd_req_1_r) = chan("ram_rd_req_1"); -// let (ram_rd_req_2_s, ram_rd_req_2_r) = chan("ram_rd_req_2"); -// let (ram_rd_req_3_s, ram_rd_req_3_r) = chan("ram_rd_req_3"); -// let (ram_rd_req_4_s, ram_rd_req_4_r) = chan("ram_rd_req_4"); -// let (ram_rd_req_5_s, ram_rd_req_5_r) = chan("ram_rd_req_5"); -// let (ram_rd_req_6_s, ram_rd_req_6_r) = chan("ram_rd_req_6"); -// let (ram_rd_req_7_s, ram_rd_req_7_r) = chan("ram_rd_req_7"); -// -// let (ram_rd_resp_0_s, ram_rd_resp_0_r) = chan("ram_rd_resp_0"); -// let (ram_rd_resp_1_s, ram_rd_resp_1_r) = chan("ram_rd_resp_1"); -// let (ram_rd_resp_2_s, ram_rd_resp_2_r) = chan("ram_rd_resp_2"); -// let (ram_rd_resp_3_s, ram_rd_resp_3_r) = chan("ram_rd_resp_3"); -// let (ram_rd_resp_4_s, ram_rd_resp_4_r) = chan("ram_rd_resp_4"); -// let (ram_rd_resp_5_s, ram_rd_resp_5_r) = chan("ram_rd_resp_5"); -// let (ram_rd_resp_6_s, ram_rd_resp_6_r) = chan("ram_rd_resp_6"); -// let (ram_rd_resp_7_s, ram_rd_resp_7_r) = chan("ram_rd_resp_7"); -// -// let (ram_wr_req_0_s, ram_wr_req_0_r) = chan("ram_wr_req_0"); -// let (ram_wr_req_1_s, ram_wr_req_1_r) = chan("ram_wr_req_1"); -// let (ram_wr_req_2_s, ram_wr_req_2_r) = chan("ram_wr_req_2"); -// let (ram_wr_req_3_s, ram_wr_req_3_r) = chan("ram_wr_req_3"); -// let (ram_wr_req_4_s, ram_wr_req_4_r) = chan("ram_wr_req_4"); -// let (ram_wr_req_5_s, ram_wr_req_5_r) = chan("ram_wr_req_5"); -// let (ram_wr_req_6_s, ram_wr_req_6_r) = chan("ram_wr_req_6"); -// let (ram_wr_req_7_s, ram_wr_req_7_r) = chan("ram_wr_req_7"); -// -// let (ram_wr_resp_0_s, ram_wr_resp_0_r) = chan("ram_wr_resp_0"); -// let (ram_wr_resp_1_s, ram_wr_resp_1_r) = chan("ram_wr_resp_1"); -// let (ram_wr_resp_2_s, ram_wr_resp_2_r) = chan("ram_wr_resp_2"); -// let (ram_wr_resp_3_s, ram_wr_resp_3_r) = chan("ram_wr_resp_3"); -// let (ram_wr_resp_4_s, ram_wr_resp_4_r) = chan("ram_wr_resp_4"); -// let (ram_wr_resp_5_s, ram_wr_resp_5_r) = chan("ram_wr_resp_5"); -// let (ram_wr_resp_6_s, ram_wr_resp_6_r) = chan("ram_wr_resp_6"); -// let (ram_wr_resp_7_s, ram_wr_resp_7_r) = chan("ram_wr_resp_7"); -// -// let (output_s, output_r) = chan("output"); -// let (notify_s, notify_r) = chan<()>("notify"); -// -// spawn ZstdDecoder< -// TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, -// TEST_REGS_N, TEST_WINDOW_LOG_MAX, -// TEST_HB_ADDR_W, TEST_HB_DATA_W, TEST_HB_NUM_PARTITIONS, TEST_HB_SIZE_KB, -// >( -// csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, -// fh_axi_ar_s, fh_axi_r_r, -// bh_axi_ar_s, bh_axi_r_r, -// raw_axi_ar_s, raw_axi_r_r, -// rle_axi_ar_s, rle_axi_r_r, -// ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, -// ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, -// ram_rd_resp_0_r, ram_rd_resp_1_r, ram_rd_resp_2_r, ram_rd_resp_3_r, -// ram_rd_resp_4_r, ram_rd_resp_5_r, ram_rd_resp_6_r, ram_rd_resp_7_r, -// ram_wr_req_0_s, ram_wr_req_1_s, ram_wr_req_2_s, ram_wr_req_3_s, -// ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, -// ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, -// ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, -// output_s, notify_s, -// ); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_HB_RAM_ASSERT_VALID_READ -// > (ram_rd_req_0_r, ram_rd_resp_0_s, ram_wr_req_0_r, ram_wr_resp_0_s); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_HB_RAM_ASSERT_VALID_READ -// > (ram_rd_req_1_r, ram_rd_resp_1_s, ram_wr_req_1_r, ram_wr_resp_1_s); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_RAM_ASSERT_VALID_READ -// > (ram_rd_req_2_r, ram_rd_resp_2_s, ram_wr_req_2_r, ram_wr_resp_2_s); -// -// spawn ram::RamModel< -// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_RAM_ASSERT_VALID_READ -// > (ram_rd_req_3_r, ram_rd_resp_3_s, ram_wr_req_3_r, ram_wr_resp_3_s); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_RAM_ASSERT_VALID_READ -// > (ram_rd_req_4_r, ram_rd_resp_4_s, ram_wr_req_4_r, ram_wr_resp_4_s); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_RAM_ASSERT_VALID_READ -// > (ram_rd_req_5_r, ram_rd_resp_5_s, ram_wr_req_5_r, ram_wr_resp_5_s); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_RAM_ASSERT_VALID_READ -// > (ram_rd_req_6_r, ram_rd_resp_6_s, ram_wr_req_6_r, ram_wr_resp_6_s); -// -// spawn ram::RamModel< -// TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, -// TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, -// TEST_RAM_ASSERT_VALID_READ -// > (ram_rd_req_7_r, ram_rd_resp_7_s, ram_wr_req_7_r, ram_wr_resp_7_s); -// -// ( -// terminator, -// csr_axi_aw_s, csr_axi_w_s, csr_axi_b_r, csr_axi_ar_s, csr_axi_s_r, -// fh_axi_ar_r, fh_axi_s_s, -// bh_axi_ar_r, bh_axi_s_s, -// raw_axi_ar_r, raw_axi_s_s, -// rle_axi_ar_r, rle_axi_s_s, -// ram_sd_seq_0_r, ram_sd_seq_1_r, ram_sd_seq_2_r, ram_sd_seq_3_r, -// ram_sd_seq_4_r, ram_sd_seq_5_r, ram_sd_seq_6_r, ram_sd_seq_7_r, -// ram_sd_sesp_0_s, ram_sd_sesp_1_s, ram_sd_sesp_2_s, ram_sd_sesp_3_s, -// ram_sd_sesp_4_s, ram_sd_sesp_5_s, ram_sd_sesp_6_s, ram_sd_sesp_7_s, -// ram_wr_seq_0_r, ram_wr_seq_1_r, ram_wr_seq_2_r, ram_wr_seq_3_r, -// ram_wr_seq_4_r, ram_wr_seq_5_r, ram_wr_seq_6_r, ram_wr_seq_7_r, -// ram_wr_sesp_0_s, ram_wr_sesp_1_s, ram_wr_sesp_2_s, ram_wr_sesp_3_s, -// ram_wr_sesp_4_s, ram_wr_sesp_5_s, ram_wr_sesp_6_s, ram_wr_sesp_7_s, -// output_r, notify_r, -// ) -// } -// -// next (state: ()) { -// -// trace_fmt!("Test start"); -// -// send(join(), terminator, true); -// } -//} - - const INST_AXI_DATA_W = u32:64; const INST_AXI_ADDR_W = u32:16; const INST_AXI_ID_W = u32:4; @@ -1273,6 +1084,7 @@ proc ZstdDecoderInternalInst { // IRQ notify_s: chan<()> out, + reset_s: chan<()> out, ) { spawn ZstdDecoderInternal< INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_REGS_N, @@ -1282,7 +1094,7 @@ proc ZstdDecoderInternalInst { bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, - notify_s, + notify_s, reset_s, ); } @@ -1369,6 +1181,7 @@ proc ZstdDecoderInst { // Decoder output output_s: chan out, notify_s: chan<()> out, + reset_s: chan<()> out, ) { spawn ZstdDecoder< INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, @@ -1387,7 +1200,7 @@ proc ZstdDecoderInst { ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, - output_s, notify_s, + output_s, notify_s, reset_s, ); } From 009e26518c979a899cfbb160e4914c2b289d084a Mon Sep 17 00:00:00 2001 From: Krzysztof Oblonczek Date: Tue, 13 May 2025 14:33:14 +0200 Subject: [PATCH 18/85] modules/zstd/zstd_dec: Add DSLX tests for ZstdDecoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Krzysztof Obłonczek --- xls/modules/zstd/BUILD | 53 +++-- xls/modules/zstd/math.x | 88 ++++++++ xls/modules/zstd/zstd_dec_test.x | 367 +++++++++++++++++++++++++++++++ 3 files changed, 492 insertions(+), 16 deletions(-) create mode 100644 xls/modules/zstd/math.x create mode 100644 xls/modules/zstd/zstd_dec_test.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index c086942d22..70bda5af9b 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -45,6 +45,19 @@ common_codegen_args = { "multi_proc": "true", } +xls_dslx_library( + name = "math_dslx", + srcs = [ + "math.x", + ], +) + +xls_dslx_test( + name = "math_dslx_test", + library = ":math_dslx", + tags = ["manual"], +) + xls_dslx_library( name = "buffer_dslx", srcs = [ @@ -848,32 +861,40 @@ place_and_route( target_die_utilization_percentage = "10", ) +zstd_dec_deps = [ + ":axi_csr_accessor_dslx", + ":block_header_dec_dslx", + ":block_header_dslx", + ":common_dslx", + ":csr_config_dslx", + ":dec_mux_dslx", + ":frame_header_dec_dslx", + ":raw_block_dec_dslx", + ":repacketizer_dslx", + ":rle_block_dec_dslx", + ":sequence_executor_dslx", + "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", +] + xls_dslx_library( name = "zstd_dec_dslx", srcs = [ "zstd_dec.x", ], - deps = [ - ":axi_csr_accessor_dslx", - ":block_header_dec_dslx", - ":block_header_dslx", - ":common_dslx", - ":csr_config_dslx", - ":dec_mux_dslx", - ":frame_header_dec_dslx", - ":raw_block_dec_dslx", - ":repacketizer_dslx", - ":rle_block_dec_dslx", - ":sequence_executor_dslx", - "//xls/examples:ram_dslx", - "//xls/modules/zstd/memory:mem_reader_dslx", - ], + deps = zstd_dec_deps, ) xls_dslx_test( name = "zstd_dec_dslx_test", - library = ":zstd_dec_dslx", + srcs = [ + "zstd_dec.x", + "zstd_dec_test.x", + "zstd_frame_testcases.x", + ], tags = ["manual"], + deps = zstd_dec_deps, ) zstd_dec_internal_codegen_args = common_codegen_args | { diff --git a/xls/modules/zstd/math.x b/xls/modules/zstd/math.x new file mode 100644 index 0000000000..1b9a8dd1db --- /dev/null +++ b/xls/modules/zstd/math.x @@ -0,0 +1,88 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; + +fn fast_if(cond: bool, arg1: uN[N], arg2: uN[N]) -> uN[N] { + let mask = if cond { !bits[N]:0 } else { bits[N]:0 }; + (arg1 & mask) | (arg2 & !mask) +} + +#[test] +fn fast_if_test() { + assert_eq(if true { u32:1 } else { u32:5 }, fast_if(true, u32:1, u32:5)); + assert_eq(if false { u32:1 } else { u32:5 }, fast_if(false, u32:1, u32:5)); +} + +// Log-depth shift bits left +pub fn logshiftl(n: bits[N], r: bits[R]) -> bits[N] { + for (i, y) in u32:0..R { + fast_if(r[i+:u1], { y << (bits[R]:1 << i) }, { y }) + }(n as bits[N]) +} + +#[test] +fn logshiftl_test() { + // Test varying base + assert_eq(logshiftl(bits[64]:0, bits[6]:3), bits[64]:0 << u32:3); + assert_eq(logshiftl(bits[64]:1, bits[6]:3), bits[64]:1 << u32:3); + assert_eq(logshiftl(bits[64]:2, bits[6]:3), bits[64]:2 << u32:3); + assert_eq(logshiftl(bits[64]:3, bits[6]:3), bits[64]:3 << u32:3); + assert_eq(logshiftl(bits[64]:4, bits[6]:3), bits[64]:4 << u32:3); + + // Test varying exponent + assert_eq(logshiftl(bits[64]:50, bits[6]:0), bits[64]:50 << u32:0); + assert_eq(logshiftl(bits[64]:50, bits[6]:1), bits[64]:50 << u32:1); + assert_eq(logshiftl(bits[64]:50, bits[6]:2), bits[64]:50 << u32:2); + assert_eq(logshiftl(bits[64]:50, bits[6]:3), bits[64]:50 << u32:3); + assert_eq(logshiftl(bits[64]:50, bits[6]:4), bits[64]:50 << u32:4); + + // Test overflow + let max = std::unsigned_max_value(); + assert_eq(logshiftl(max, u4:4), max << u4:4); + assert_eq(logshiftl(max, u4:5), max << u4:5); + assert_eq(logshiftl(max, u4:15), max << u4:15); + assert_eq(logshiftl(bits[24]:0xc0ffee, u8:12), bits[24]:0xfee000); +} + +// Log-depth shift bits right +pub fn logshiftr(n: bits[N], r: bits[R]) -> bits[N] { + for (i, y) in u32:0..R { + fast_if(r[i+:u1], { y >> (bits[R]:1 << i) }, { y }) + }(n as bits[N]) +} + +#[test] +fn logshiftr_test() { + // Test varying base + assert_eq(logshiftr(bits[64]:0x0fac4e782, bits[6]:3), bits[64]:0x0fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x1fac4e782, bits[6]:3), bits[64]:0x1fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x2fac4e782, bits[6]:3), bits[64]:0x2fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x3fac4e782, bits[6]:3), bits[64]:0x3fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x4fac4e782, bits[6]:3), bits[64]:0x4fac4e782 >> u32:3); + + // Test varying exponent + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:0), bits[64]:0x50fac4e782 >> u32:0); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:1), bits[64]:0x50fac4e782 >> u32:1); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:2), bits[64]:0x50fac4e782 >> u32:2); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:3), bits[64]:0x50fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:4), bits[64]:0x50fac4e782 >> u32:4); + + // Test overflow + let max = std::unsigned_max_value(); + assert_eq(logshiftr(max, u4:4), max >> u4:4); + assert_eq(logshiftr(max, u4:5), max >> u4:5); + assert_eq(logshiftr(max, u4:15), max >> u4:15); + assert_eq(logshiftr(bits[24]:0xc0ffee, u8:12), bits[24]:0x000c0f); +} diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x new file mode 100644 index 0000000000..a166e1743d --- /dev/null +++ b/xls/modules/zstd/zstd_dec_test.x @@ -0,0 +1,367 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.csr_config; +import xls.modules.zstd.sequence_executor; +import xls.modules.zstd.zstd_frame_testcases; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.zstd_dec; + +const TEST_WINDOW_LOG_MAX = u32:30; + +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_ID_W = u32:8; +const TEST_AXI_DEST_W = u32:8; +const TEST_AXI_DATA_W_DIV8 = TEST_AXI_DATA_W / u32:8; + +const TEST_REGS_N = u32:5; +const TEST_LOG2_REGS_N = std::clog2(TEST_REGS_N); + +const TEST_HB_RAM_N = u32:8; +const TEST_HB_ADDR_W = sequence_executor::ZSTD_RAM_ADDR_WIDTH; +const TEST_HB_DATA_W = sequence_executor::RAM_DATA_WIDTH; +const TEST_HB_NUM_PARTITIONS = sequence_executor::RAM_NUM_PARTITIONS; +const TEST_HB_SIZE_KB = sequence_executor::ZSTD_HISTORY_BUFFER_SIZE_KB; +const TEST_HB_RAM_SIZE = sequence_executor::ZSTD_RAM_SIZE; +const TEST_HB_RAM_WORD_PARTITION_SIZE = sequence_executor::RAM_WORD_PARTITION_SIZE; +const TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = sequence_executor::TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR; +const TEST_HB_RAM_INITIALIZED = sequence_executor::TEST_RAM_INITIALIZED; +const TEST_HB_RAM_ASSERT_VALID_READ:bool = false; + +const TEST_RAM_DATA_W:u32 = TEST_AXI_DATA_W; +const TEST_RAM_SIZE:u32 = u32:16384; +const TEST_RAM_ADDR_W:u32 = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE:u32 = u32:8; +const TEST_RAM_NUM_PARTITIONS:u32 = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_W); +const TEST_RAM_BASE_ADDR:u32 = u32:0; +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_INITIALIZED = true; + +fn csr_addr(c: zstd_dec::Csr) -> uN[TEST_AXI_ADDR_W] { + (c as uN[TEST_AXI_ADDR_W]) << 3 +} + +#[test_proc] +proc ZstdDecoderTest { + type CsrAxiAr = axi::AxiAr; + type CsrAxiR = axi::AxiR; + type CsrAxiAw = axi::AxiAw; + type CsrAxiW = axi::AxiW; + type CsrAxiB = axi::AxiB; + + type CsrRdReq = csr_config::CsrRdReq; + type CsrRdResp = csr_config::CsrRdResp; + type CsrWrReq = csr_config::CsrWrReq; + type CsrWrResp = csr_config::CsrWrResp; + type CsrChange = csr_config::CsrChange; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type RamRdReqHB = ram::ReadReq; + type RamRdRespHB = ram::ReadResp; + type RamWrReqHB = ram::WriteReq; + type RamWrRespHB = ram::WriteResp; + + type RamRdReq = ram::ReadReq; + type RamRdResp = ram::ReadResp; + type RamWrReq = ram::WriteReq; + type RamWrResp = ram::WriteResp; + + type ZstdDecodedPacket = common::ZstdDecodedPacket; + terminator: chan out; + csr_axi_aw_s: chan out; + csr_axi_w_s: chan out; + csr_axi_b_r: chan in; + csr_axi_ar_s: chan out; + csr_axi_r_r: chan in; + fh_axi_ar_r: chan in; + fh_axi_r_s: chan out; + bh_axi_ar_r: chan in; + bh_axi_r_s: chan out; + raw_axi_ar_r: chan in; + raw_axi_r_s: chan out; + + ram_rd_req_r: chan[8] in; + ram_rd_resp_s: chan[8] out; + ram_wr_req_r: chan[8] in; + ram_wr_resp_s: chan[8] out; + + ram_wr_req_fh_s: chan out; + ram_wr_req_bh_s: chan out; + ram_wr_req_raw_s: chan out; + raw_wr_resp_fh_r: chan in; + raw_wr_resp_bh_r: chan in; + raw_wr_resp_raw_r: chan in; + + output_r: chan in; + notify_r: chan<()> in; + reset_r: chan<()> in; + + init {} + + config(terminator: chan out) { + + let (csr_axi_aw_s, csr_axi_aw_r) = chan("csr_axi_aw"); + let (csr_axi_w_s, csr_axi_w_r) = chan("csr_axi_w"); + let (csr_axi_b_s, csr_axi_b_r) = chan("csr_axi_b"); + let (csr_axi_ar_s, csr_axi_ar_r) = chan("csr_axi_ar"); + let (csr_axi_r_s, csr_axi_r_r) = chan("csr_axi_r"); + + let (fh_axi_ar_s, fh_axi_ar_r) = chan("fh_axi_ar"); + let (fh_axi_r_s, fh_axi_r_r) = chan("fh_axi_r"); + + let (bh_axi_ar_s, bh_axi_ar_r) = chan("bh_axi_ar"); + let (bh_axi_r_s, bh_axi_r_r) = chan("bh_axi_r"); + + let (raw_axi_ar_s, raw_axi_ar_r) = chan("raw_axi_ar"); + let (raw_axi_r_s, raw_axi_r_r) = chan("raw_axi_r"); + + let (ram_rd_req_s, ram_rd_req_r) = chan[8]("ram_rd_req"); + let (ram_rd_resp_s, ram_rd_resp_r) = chan[8]("ram_rd_resp"); + let (ram_wr_req_s, ram_wr_req_r) = chan[8]("ram_wr_req"); + let (ram_wr_resp_s, ram_wr_resp_r) = chan[8]("ram_wr_resp"); + + let (ram_rd_req_fh_s, ram_rd_req_fh_r) = chan("ram_rd_req_fh"); + let (ram_rd_req_bh_s, ram_rd_req_bh_r) = chan("ram_rd_req_bh"); + let (ram_rd_req_raw_s, ram_rd_req_raw_r) = chan("ram_rd_req_raw"); + let (ram_rd_resp_fh_s, ram_rd_resp_fh_r) = chan("ram_rd_resp_fh"); + let (ram_rd_resp_bh_s, ram_rd_resp_bh_r) = chan("ram_rd_resp_bh"); + let (ram_rd_resp_raw_s, ram_rd_resp_raw_r) = chan("ram_rd_resp_raw"); + + let (ram_wr_req_fh_s, ram_wr_req_fh_r) = chan("ram_wr_req_fh"); + let (ram_wr_req_bh_s, ram_wr_req_bh_r) = chan("ram_wr_req_bh"); + let (ram_wr_req_raw_s, ram_wr_req_raw_r) = chan("ram_wr_req_raw"); + let (ram_wr_resp_fh_s, ram_wr_resp_fh_r) = chan("ram_wr_resp_fh"); + let (ram_wr_resp_bh_s, ram_wr_resp_bh_r) = chan("ram_wr_resp_bh"); + let (ram_wr_resp_raw_s, ram_wr_resp_raw_r) = chan("ram_wr_resp_raw"); + + let (output_s, output_r) = chan("output"); + let (notify_s, notify_r) = chan<()>("notify"); + let (reset_s, reset_r) = chan<()>("reset"); + + spawn zstd_dec::ZstdDecoder< + TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, + TEST_REGS_N, TEST_WINDOW_LOG_MAX, + TEST_HB_ADDR_W, TEST_HB_DATA_W, TEST_HB_NUM_PARTITIONS, TEST_HB_SIZE_KB, + >( + csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, + fh_axi_ar_s, fh_axi_r_r, + bh_axi_ar_s, bh_axi_r_r, + raw_axi_ar_s, raw_axi_r_r, + ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], + ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], + ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], + ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], + ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], + ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], + ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], + ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7], + output_s, notify_s, reset_s, + ); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); + + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + > (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); + + spawn ram::RamModel< + TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + > (ram_rd_req_fh_r, ram_rd_resp_fh_s, ram_wr_req_fh_r, ram_wr_resp_fh_s); + + spawn ram::RamModel< + TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + > (ram_rd_req_bh_r, ram_rd_resp_bh_s, ram_wr_req_bh_r, ram_wr_resp_bh_s); + + spawn ram::RamModel< + TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + > (ram_rd_req_raw_r, ram_rd_resp_raw_s, ram_wr_req_raw_r, ram_wr_resp_raw_s); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, + >(fh_axi_ar_r, fh_axi_r_s, ram_rd_req_fh_s, ram_rd_resp_fh_r); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, + >(bh_axi_ar_r, bh_axi_r_s, ram_rd_req_bh_s, ram_rd_resp_bh_r); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, + >(raw_axi_ar_r, raw_axi_r_s, ram_rd_req_raw_s, ram_rd_resp_raw_r); + + ( + terminator, + csr_axi_aw_s, csr_axi_w_s, csr_axi_b_r, csr_axi_ar_s, csr_axi_r_r, + fh_axi_ar_r, fh_axi_r_s, + bh_axi_ar_r, bh_axi_r_s, + raw_axi_ar_r, raw_axi_r_s, + ram_rd_req_r, ram_rd_resp_s, ram_wr_req_r, ram_wr_resp_s, + ram_wr_req_fh_s, ram_wr_req_bh_s, ram_wr_req_raw_s, + ram_wr_resp_fh_r, ram_wr_resp_bh_r, ram_wr_resp_raw_r, + output_r, notify_r, reset_r, + ) + } + + next (state: ()) { + trace_fmt!("Test start"); + let frames_count = array_size(zstd_frame_testcases::FRAMES); + + let tok = join(); + let tok = unroll_for! (test_i, tok): (u32, token) in range(u32:0, frames_count) { + trace_fmt!("Loading testcase {:x}", test_i); + let frame = zstd_frame_testcases::FRAMES[test_i]; + let tok = for (i, tok): (u32, token) in range(u32:0, frame.array_length) { + let req = RamWrReq { + addr: i as uN[TEST_RAM_ADDR_W], + data: frame.data[i] as uN[TEST_RAM_DATA_W], + mask: uN[TEST_RAM_NUM_PARTITIONS]:0xFF + }; + let tok = send(tok, ram_wr_req_fh_s, req); + let tok = send(tok, ram_wr_req_bh_s, req); + let tok = send(tok, ram_wr_req_raw_s, req); + tok + }(tok); + + trace_fmt!("Running decoder on testcase {:x}", test_i); + let addr_req = axi::AxiAw { + id: uN[TEST_AXI_ID_W]:0, + addr: uN[TEST_AXI_ADDR_W]:0, + size: axi::AxiAxSize::MAX_4B_TRANSFER, + len: u8:0, + burst: axi::AxiAxBurst::FIXED, + }; + let data_req = axi::AxiW { + data: uN[TEST_AXI_DATA_W]:0, + strb: uN[TEST_AXI_DATA_W_DIV8]:0xFF, + last: u1:1, + }; + + // reset the decoder + trace_fmt!("Sending reset"); + let tok = send(tok, csr_axi_aw_s, axi::AxiAw { + addr: csr_addr(zstd_dec::Csr::RESET), + ..addr_req + }); + let tok = send(tok, csr_axi_w_s, axi::AxiW { + data: uN[TEST_AXI_DATA_W]:0x1, + ..data_req + }); + trace_fmt!("Sent reset"); + let (tok, _) = recv(tok, csr_axi_b_r); + // Wait for reset notification before issuing further CSR writes + let (tok, _) = recv(tok, reset_r); + // configure input buffer address + let tok = send(tok, csr_axi_aw_s, axi::AxiAw { + addr: csr_addr(zstd_dec::Csr::INPUT_BUFFER), + ..addr_req + }); + let tok = send(tok, csr_axi_w_s, axi::AxiW { + data: uN[TEST_AXI_DATA_W]:0x0, + ..data_req + }); + let (tok, _) = recv(tok, csr_axi_b_r); + // configure output buffer address + let tok = send(tok, csr_axi_aw_s, axi::AxiAw { + addr: csr_addr(zstd_dec::Csr::OUTPUT_BUFFER), + ..addr_req + }); + let tok = send(tok, csr_axi_w_s, axi::AxiW { + data: uN[TEST_AXI_DATA_W]:0x1000, + ..data_req + }); + let (tok, _) = recv(tok, csr_axi_b_r); + // start decoder + let tok = send(tok, csr_axi_aw_s, axi::AxiAw { + addr: csr_addr(zstd_dec::Csr::START), + ..addr_req + }); + let tok = send(tok, csr_axi_w_s, axi::AxiW { + data: uN[TEST_AXI_DATA_W]:0x1, + ..data_req + }); + let (tok, _) = recv(tok, csr_axi_b_r); + + let decomp_frame = zstd_frame_testcases::DECOMPRESSED_FRAMES[test_i]; + let tok = for (decomp_i, tok): (u32, token) in range(u32:0, decomp_frame.array_length) { + let (tok, decomp_packet) = recv(tok, output_r); + assert_eq(decomp_packet.data, decomp_frame.data[decomp_i]); + assert_eq(decomp_packet.last, decomp_i == (decomp_frame.length - u32:1) / u32:8); + tok + }(tok); + + let (tok, ()) = recv(tok, notify_r); + trace_fmt!("Finished decoding testcase {:x} correctly", test_i); + tok + }(tok); + send(tok, terminator, true); + } +} + From a979e29ba0b792ac38261efd5c32ff4143286f13 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 22 Oct 2024 15:38:22 +0200 Subject: [PATCH 19/85] modules/zstd/zstd_dec: handle contents of the Status CSR Internal-tag: [#66955] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/zstd_dec.x | 85 +++++++++++++++++++++++++++++-------- 1 file changed, 68 insertions(+), 17 deletions(-) diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index be58763dd3..528d16d599 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -50,12 +50,19 @@ enum ZstdDecoderInternalFsm: u4 { INVALID = 15, } -enum ZstdDecoderStatus: u3 { - OKAY = 0, - FINISHED = 1, - FRAME_HEADER_CORRUPTED = 2, - FRAME_HEADER_UNSUPPORTED_WINDOW_SIZE = 3, - BLOCK_HEADER_CORRUPTED = 4, +enum ZstdDecoderStatus: u5 { + IDLE = 0, + RUNNING = 1, + READ_CONFIG_OK = 2, + FRAME_HEADER_OK = 3, + FRAME_HEADER_CORRUPTED = 4, + FRAME_HEADER_UNSUPPORTED_WINDOW_SIZE = 5, + BLOCK_HEADER_OK = 6, + BLOCK_HEADER_CORRUPTED = 7, + BLOCK_HEADER_MEMORY_ACCESS_ERROR = 8, + RAW_BLOCK_OK = 9, + RAW_BLOCK_ERROR = 10, + RLE_BLOCK_OK = 11, } pub enum Csr: u3 { @@ -317,7 +324,15 @@ proc ZstdDecoderInternal< Fsm::IDLE => { trace_fmt!("[IDLE]"); if is_start { - State { fsm: Fsm::READ_CONFIG, conf_cnt: CSR_REQS_MAX, ..zero!() } + let status = ZstdDecoderStatus::RUNNING; + + let csr_wr_req_valid = true; + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(status), + }; + + State { fsm: Fsm::READ_CONFIG, csr_wr_req, csr_wr_req_valid, conf_cnt: CSR_REQS_MAX, ..zero!() } } else { zero!() } }, @@ -337,8 +352,19 @@ proc ZstdDecoderInternal< let conf_send = (state.conf_cnt == Reg:0); let conf_cnt = if conf_send { Reg:0 } else {state.conf_cnt - Reg:1}; + let status = match(all_collected) { + true => ZstdDecoderStatus::READ_CONFIG_OK, + _ => ZstdDecoderStatus::RUNNING, + }; + + let csr_wr_req_valid = all_collected; + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: checked_cast(status), + }; + State { - fsm, conf_cnt, conf_send, input_buffer, input_buffer_valid, output_buffer, output_buffer_valid, + fsm, csr_wr_req, csr_wr_req_valid, conf_cnt, conf_send, input_buffer, input_buffer_valid, output_buffer, output_buffer_valid, ..zero!() } }, @@ -347,10 +373,17 @@ proc ZstdDecoderInternal< trace_fmt!("[DECODE_FRAME_HEADER]"); let error = (fh_resp.status != FrameHeaderDecoderStatus::OKAY); - let csr_wr_req_valid = (fh_resp_valid && error); + let status = match(fh_resp_valid, fh_resp.status) { + (true, FrameHeaderDecoderStatus::OKAY) => ZstdDecoderStatus::FRAME_HEADER_OK, + (true, FrameHeaderDecoderStatus::CORRUPTED) => ZstdDecoderStatus::FRAME_HEADER_CORRUPTED, + (true, FrameHeaderDecoderStatus::UNSUPPORTED_WINDOW_SIZE) => ZstdDecoderStatus::FRAME_HEADER_UNSUPPORTED_WINDOW_SIZE, + (_, _) => ZstdDecoderStatus::RUNNING, + }; + + let csr_wr_req_valid = (fh_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(fh_resp.status), + value: checked_cast(status), }; let fsm = match (fh_resp_valid, error) { @@ -368,10 +401,17 @@ proc ZstdDecoderInternal< trace_fmt!("[DECODE_BLOCK_HEADER]"); let error = (bh_resp.status != BlockHeaderDecoderStatus::OKAY); - let csr_wr_req_valid = (bh_resp_valid && error); + let status = match(bh_resp_valid, bh_resp.status) { + (true, BlockHeaderDecoderStatus::OKAY) => ZstdDecoderStatus::BLOCK_HEADER_OK, + (true, BlockHeaderDecoderStatus::CORRUPTED) => ZstdDecoderStatus::BLOCK_HEADER_CORRUPTED, + (true, BlockHeaderDecoderStatus::MEMORY_ACCESS_ERROR) => ZstdDecoderStatus::BLOCK_HEADER_MEMORY_ACCESS_ERROR, + (_, _) => ZstdDecoderStatus::RUNNING, + }; + + let csr_wr_req_valid = (bh_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(bh_resp.status), + value: checked_cast(status), }; let fsm = match (bh_resp_valid, error, bh_resp.header.btype) { @@ -413,10 +453,16 @@ proc ZstdDecoderInternal< let error = (raw_resp.status != RawBlockDecoderStatus::OKAY); - let csr_wr_req_valid = (raw_resp_valid && error); + let status = match(raw_resp_valid, raw_resp.status) { + (true, RawBlockDecoderStatus::OKAY) => ZstdDecoderStatus::RAW_BLOCK_OK, + (true, RawBlockDecoderStatus::ERROR) => ZstdDecoderStatus::RAW_BLOCK_ERROR, + (_, _) => ZstdDecoderStatus::RUNNING, + }; + + let csr_wr_req_valid = (raw_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(raw_resp.status), + value: checked_cast(status), }; let fsm = match (raw_resp_valid, error, state.block_last) { @@ -441,10 +487,15 @@ proc ZstdDecoderInternal< trace_fmt!("[DECODE_RLE_BLOCK]"); let error = (rle_resp.status != RleBlockDecoderStatus::OKAY); - let csr_wr_req_valid = (rle_resp_valid && error); + let status = match(rle_resp_valid, rle_resp.status) { + (true, RleBlockDecoderStatus::OKAY) => ZstdDecoderStatus::RLE_BLOCK_OK, + (_, _) => ZstdDecoderStatus::RUNNING, + }; + + let csr_wr_req_valid = (rle_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(rle_resp.status), + value: checked_cast(status), }; let fsm = match (rle_resp_valid, error, state.block_last) { @@ -481,7 +532,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = true; let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(fh_resp.status), + value: checked_cast(ZstdDecoderStatus::IDLE), }; State { fsm: Fsm::IDLE, csr_wr_req, csr_wr_req_valid, ..zero!() } From 7560da5a8ffe49b03c3281ca28d3b207994bee02 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 18 Nov 2024 14:04:39 +0100 Subject: [PATCH 20/85] modules/zstd/data_generator: fix formatting Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/data_generator.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/xls/modules/zstd/data_generator.cc b/xls/modules/zstd/data_generator.cc index 81ffe95ed9..98b1eb4dba 100644 --- a/xls/modules/zstd/data_generator.cc +++ b/xls/modules/zstd/data_generator.cc @@ -60,9 +60,8 @@ static absl::StatusOr CallDecodecorpus( absl::Span args, const std::optional& cwd = std::nullopt, std::optional timeout = std::nullopt) { - XLS_ASSIGN_OR_RETURN( - std::filesystem::path path, - xls::GetXlsRunfilePath("external/zstd/decodecorpus")); + XLS_ASSIGN_OR_RETURN(std::filesystem::path path, + xls::GetXlsRunfilePath("external/zstd/decodecorpus")); std::vector cmd = {path}; cmd.insert(cmd.end(), args.begin(), args.end()); From 09ea65b98658fe82f21d070db4c8058c1e8b5341 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 29 Oct 2024 16:47:45 +0100 Subject: [PATCH 21/85] modules/zstd/memory:axi_stream_remove_empty: Fix byte ordering * Fix byte ordering when receiving a series of non-empty packets * Adjust MemReader DSLX tests Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- .../zstd/memory/axi_stream_remove_empty.x | 64 ++++++++++++++++++- xls/modules/zstd/memory/mem_reader.x | 9 ++- 2 files changed, 68 insertions(+), 5 deletions(-) diff --git a/xls/modules/zstd/memory/axi_stream_remove_empty.x b/xls/modules/zstd/memory/axi_stream_remove_empty.x index a1b48f37a7..1c295159ba 100644 --- a/xls/modules/zstd/memory/axi_stream_remove_empty.x +++ b/xls/modules/zstd/memory/axi_stream_remove_empty.x @@ -130,7 +130,6 @@ pub proc AxiStreamRemoveEmpty< let exact_transfer = (empty_input_bytes == state.len); let combined_state_data = state.data | data << state.len; - let combined_input_data = data | state.data << len; let overflow_len = get_overflow_len(state.len, len); let sum_len = state.len + len; @@ -172,7 +171,7 @@ pub proc AxiStreamRemoveEmpty< // store ( State { - data: combined_input_data, + data: combined_state_data, len: sum_len, ..state }, @@ -405,6 +404,67 @@ proc AxiStreamRemoveEmptyTest { dest: Dest:0, }); + // Test 6: Some bits set, last set in the last transfer. + + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x0000_00B9, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x0000_007F, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x0000_0069, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x00DF_5EF7, + str: Str:0b0111, + keep: Keep:0b0111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x0000_C735, + str: Str:0b0011, + keep: Keep:0b0011, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xF769_7FB9, + str: Str:0xF, + keep: Keep:0xF, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xC735_DF5E, + str: Str:0xF, + keep: Keep:0xF, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); send(tok, terminator, true); } } diff --git a/xls/modules/zstd/memory/mem_reader.x b/xls/modules/zstd/memory/mem_reader.x index c0d6c5709d..f96257663c 100644 --- a/xls/modules/zstd/memory/mem_reader.x +++ b/xls/modules/zstd/memory/mem_reader.x @@ -579,7 +579,8 @@ proc MemReaderTest { let tok = send(tok, axi_r_s, AxiR { id: AxiId:0x0, - data: AxiData:0x1122_3344_5566_7788_9900_AABB_CCDD_EEFF, + data: AxiData:0x1122_3344_5566_7788_9900_AABB_CCDD_EE55, + // Addresses: ^ 0xFFF ^ 0xFF0 resp: AxiResp::OKAY, last: AxiLast:true }); @@ -599,7 +600,8 @@ proc MemReaderTest { let tok = send(tok, axi_r_s, AxiR { id: AxiId:0x0, - data: AxiData:0x1122_3344_5566_7788_9900_AABB_CCDD_EEFF, + data: AxiData:0x5522_3344_5566_7788_9900_AABB_CCDD_EEFF, + // Addresses: ^ 0x100F ^ 0x1000 resp: AxiResp::OKAY, last: AxiLast:true }); @@ -607,7 +609,8 @@ proc MemReaderTest { let (tok, resp) = recv(tok, resp_r); assert_eq(resp, Resp { status: Status::OKAY, - data: Data:0x11FF, + data: Data:0xFF11, + // 0x1000 ^ ^ 0x0FFF length: Length:2, last: true }); From ed2120036799b7fefc971f501ddf5d0878229103 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 4 Nov 2024 16:22:34 +0100 Subject: [PATCH 22/85] modules/zstd/memory/axi_stream_remove_empty: Extract remove_empty_bytes function into a separate proc * Extract the operation of removing not-strobed bytes from input frames to a separate proc * Extract control logic to AxiStreamRemoveEmptyInternal proc * Optimize strobe calculation Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/BUILD | 139 ++++- .../zstd/memory/axi_stream_remove_empty.x | 555 ++++++++++++++++-- 2 files changed, 629 insertions(+), 65 deletions(-) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index 96e824b19c..2368579c26 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -58,8 +58,6 @@ CLOCK_PERIOD_PS = "750" # Clock periods for modules that exceed the 750ps critical path in IR benchmark AXI_READER_CLOCK_PERIOD_PS = "1800" -AXI_STREAM_REMOVE_EMPTY_CLOCK_PERIOD_PS = "1300" - MEM_READER_CLOCK_PERIOD_PS = "2600" common_codegen_args = { @@ -166,9 +164,68 @@ xls_dslx_test( tags = ["manual"], ) +axi_stream_remove_empty_internal_codegen_args = common_codegen_args | { + "module_name": "axi_stream_remove_empty_internal", + "pipeline_stages": "1", +} + +xls_dslx_verilog( + name = "axi_stream_remove_empty_internal_verilog", + codegen_args = axi_stream_remove_empty_internal_codegen_args, + dslx_top = "AxiStreamRemoveEmptyInternalInst", + library = ":axi_stream_remove_empty_dslx", + tags = ["manual"], + verilog_file = "axi_stream_remove_empty_internal.v", +) + +xls_benchmark_ir( + name = "axi_stream_remove_empty_internal_opt_ir_benchmark", + src = ":axi_stream_remove_empty_internal_verilog.opt.ir", + benchmark_ir_args = axi_stream_remove_empty_internal_codegen_args | { + "pipeline_stages": "10", + "top": "__axi_stream_remove_empty__AxiStreamRemoveEmptyInternalInst__AxiStreamRemoveEmptyInternal_0__32_4_6_32_32_next", + }, + tags = ["manual"], +) + +verilog_library( + name = "axi_stream_remove_empty_internal_verilog_lib", + srcs = [ + ":axi_stream_remove_empty_internal.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "axi_stream_remove_empty_internal_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "axi_stream_remove_empty_internal", + deps = [ + ":axi_stream_remove_empty_internal_verilog_lib", + ], +) + +benchmark_synth( + name = "axi_stream_remove_empty_internal_benchmark_synth", + synth_target = ":axi_stream_remove_empty_internal_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "axi_stream_remove_empty_internal_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":axi_stream_remove_empty_internal_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + axi_stream_remove_empty_codegen_args = common_codegen_args | { "module_name": "axi_stream_remove_empty", - "clock_period_ps": AXI_STREAM_REMOVE_EMPTY_CLOCK_PERIOD_PS, "pipeline_stages": "2", } @@ -181,16 +238,6 @@ xls_dslx_verilog( verilog_file = "axi_stream_remove_empty.v", ) -xls_benchmark_ir( - name = "axi_stream_remove_empty_opt_ir_benchmark", - src = ":axi_stream_remove_empty_verilog.opt.ir", - benchmark_ir_args = axi_stream_remove_empty_codegen_args | { - "pipeline_stages": "10", - "top": "__axi_stream_remove_empty__AxiStreamRemoveEmptyInst__AxiStreamRemoveEmpty_0__32_4_6_32_32_next", - }, - tags = ["manual"], -) - verilog_library( name = "axi_stream_remove_empty_verilog_lib", srcs = [ @@ -227,6 +274,66 @@ place_and_route( target_die_utilization_percentage = "10", ) +remove_empty_bytes_codegen_args = common_codegen_args | { + "module_name": "remove_empty_bytes", + "pipeline_stages": "2", +} + +xls_dslx_verilog( + name = "remove_empty_bytes_verilog", + codegen_args = remove_empty_bytes_codegen_args, + dslx_top = "RemoveEmptyBytesInst", + library = ":axi_stream_remove_empty_dslx", + tags = ["manual"], + verilog_file = "remove_empty_bytes.v", +) + +xls_benchmark_ir( + name = "remove_empty_bytes_opt_ir_benchmark", + src = ":remove_empty_bytes_verilog.opt.ir", + benchmark_ir_args = remove_empty_bytes_codegen_args | { + "top": "__axi_stream_remove_empty__RemoveEmptyBytesInst__RemoveEmptyBytes_0__32_4_6_32_9_32_next", + "pipeline_stages": "10", + }, + tags = ["manual"], +) + +verilog_library( + name = "remove_empty_bytes_verilog_lib", + srcs = [ + ":remove_empty_bytes.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "remove_empty_bytes_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "remove_empty_bytes", + deps = [ + ":remove_empty_bytes_verilog_lib", + ], +) + +benchmark_synth( + name = "remove_empty_bytes_benchmark_synth", + synth_target = ":remove_empty_bytes_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "remove_empty_bytes_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":remove_empty_bytes_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + xls_dslx_library( name = "axi_stream_downscaler_dslx", srcs = ["axi_stream_downscaler.x"], @@ -468,13 +575,12 @@ place_and_route( ) mem_reader_codegen_args = common_codegen_args | { + "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, "module_name": "mem_reader", "pipeline_stages": "4", "streaming_channel_data_suffix": "_data", "flop_inputs_kind": "skid", "flop_outputs_kind": "skid", - "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, - "fifo_module": "", "materialize_internal_fifos": "true", } @@ -524,13 +630,12 @@ place_and_route( ) mem_reader_adv_codegen_args = common_codegen_args | { + "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, "module_name": "mem_reader_adv", "pipeline_stages": "4", "streaming_channel_data_suffix": "_data", "flop_inputs_kind": "skid", "flop_outputs_kind": "skid", - "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, - "fifo_module": "", "materialize_internal_fifos": "true", } diff --git a/xls/modules/zstd/memory/axi_stream_remove_empty.x b/xls/modules/zstd/memory/axi_stream_remove_empty.x index 1c295159ba..40c8aa9208 100644 --- a/xls/modules/zstd/memory/axi_stream_remove_empty.x +++ b/xls/modules/zstd/memory/axi_stream_remove_empty.x @@ -29,34 +29,185 @@ struct AxiStreamRemoveEmptyState< dest: uN[DEST_W], } +pub struct ContinuousStream< + DATA_W: u32, + DEST_W: u32, + ID_W: u32, + DATA_W_LOG2: u32 = {std::clog2(DATA_W + u32:1)}, +> { + data: uN[DATA_W], + len: uN[DATA_W_LOG2], + id: uN[ID_W], + dest: uN[DEST_W], + last: u1 +} + +const INST_DATA_W = u32:32; +const INST_DATA_W_DIV8 = INST_DATA_W / u32:8; +const INST_DATA_W_LOG2 = std::clog2(INST_DATA_W + u32:1); +const INST_DEST_W = u32:32; +const INST_ID_W = u32:32; +const TEST_DATA_W = u32:32; +const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; +const TEST_DATA_W_LOG2 = std::clog2(TEST_DATA_W + u32:1); +const TEST_DEST_W = u32:32; +const TEST_ID_W = u32:32; // Returns a tuple containing data and length, afer removing non-data // bytes from the in_data varaiable, using information from keep and str fields -fn remove_empty_bytes ( - in_data: uN[DATA_W], keep: uN[DATA_W_DIV8], str: uN[DATA_W_DIV8] -) -> (uN[DATA_W], uN[DATA_W_LOG2]) { - - const EXT_OFFSET_W = DATA_W_LOG2 + u32:3; - +pub proc RemoveEmptyBytes< + DATA_W: u32, DEST_W: u32, ID_W: u32, + DATA_W_DIV8: u32 = {DATA_W / u32:8}, + DATA_W_LOG2: u32 = {std::clog2(DATA_W + u32:1)}, + EXT_OFFSET_W: u32 = {(std::clog2(DATA_W + u32:1)) + u32:3}, +> { type Data = uN[DATA_W]; type Str = uN[DATA_W_DIV8]; - type Keep = uN[DATA_W_DIV8]; type Offset = uN[DATA_W_LOG2]; type OffsetExt = uN[EXT_OFFSET_W]; type Length = uN[DATA_W_LOG2]; - let (data, len, _) = for (i, (data, len, offset)): (u32, (Data, Length, Offset)) in u32:0..DATA_W_DIV8 { - if str[i +: u1] & keep[i +: u1] { - ( - data | (in_data & (Data:0xFF << (u32:8 * i))) >> (OffsetExt:8 * offset as OffsetExt), - len + Length:8, - offset, - ) - } else { - (data, len, offset + Offset:1) - } - }((Data:0, Length:0, Offset:0)); - (data, len) + type AxiStream = axi_st::AxiStream; + type StrobedStream = ContinuousStream; + + stream_r: chan in; + continuous_stream_s: chan out; + + config ( + stream_r: chan in, + continuous_stream_s: chan out, + ) { + (stream_r, continuous_stream_s) + } + + init { () } + + next (state: ()) { + let (tok, frame) = recv(join(), stream_r); + let (in_data, str) = (frame.data, frame.str); + + let (data, len, _) = unroll_for! (i, (data, len, offset)): (u32, (Data, Length, Offset)) in range(u32:0, DATA_W_DIV8) { + if str[i +: u1] { + ( + data | (in_data & (Data:0xFF << (u32:8 * i))) >> (OffsetExt:8 * offset as OffsetExt), + len + Length:8, + offset, + ) + } else { + (data, len, offset + Offset:1) + } + }((Data:0, Length:0, Offset:0)); + + let continuous_stream = StrobedStream { + data: data, + len: len, + id: frame.id, + dest: frame.dest, + last: frame.last, + }; + send(tok, continuous_stream_s, continuous_stream); + } +} + +pub proc RemoveEmptyBytesInst { + type AxiStream = axi_st::AxiStream; + type StrobedStream = ContinuousStream; + + config ( + stream_r: chan in, + continuous_stream_s: chan out, + ) { + spawn RemoveEmptyBytes( + stream_r, continuous_stream_s + ); + } + + init { () } + + next (state: ()) {} +} + +#[test_proc] +proc RemoveEmptyBytesTest { + type TestAxiStream = axi_st::AxiStream; + type TestStrobedStream = ContinuousStream; + terminator: chan out; + stream_s: chan out; + continuous_stream_r: chan in; + + config ( + terminator: chan out, + ) { + let (stream_s, stream_r) = chan("frame_data"); + let (continuous_stream_s, continuous_stream_r) = chan("bare_data"); + + spawn RemoveEmptyBytes( + stream_r, continuous_stream_s + ); + + (terminator, stream_s, continuous_stream_r) + } + + init { } + + next (state: ()) { + type Data = uN[TEST_DATA_W]; + type Str = uN[TEST_DATA_W_DIV8]; + type Id = uN[TEST_ID_W]; + type Dest = uN[TEST_DEST_W]; + type Length = uN[TEST_DATA_W_LOG2]; + + let tok = join(); + + let data = Data:0xDEADBEEF; + let input_data: TestAxiStream[16] = [ + TestAxiStream{data: data, str: Str:0b0000, keep: Str:0b0000, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0001, keep: Str:0b0001, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0010, keep: Str:0b0010, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0011, keep: Str:0b0011, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0100, keep: Str:0b0100, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0101, keep: Str:0b0101, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0110, keep: Str:0b0110, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b0111, keep: Str:0b0111, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1000, keep: Str:0b1000, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1001, keep: Str:0b1001, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1010, keep: Str:0b1010, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1011, keep: Str:0b1011, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1100, keep: Str:0b1100, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1101, keep: Str:0b1101, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1110, keep: Str:0b1110, id: Id:0, dest: Dest:0, last: false}, + TestAxiStream{data: data, str: Str:0b1111, keep: Str:0b1111, id: Id:0, dest: Dest:0, last: true} + ]; + let expected_output: TestStrobedStream[16] = [ + TestStrobedStream{data: Data:0x00, len: Length:0, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xEF, len: Length:8, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xBE, len: Length:8, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xBEEF, len: Length:16, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xAD, len: Length:8, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xADEF, len: Length:16, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xADBE, len: Length:16, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xADBEEF, len: Length:24, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDE, len: Length:8, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEEF, len: Length:16, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEBE, len: Length:16, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEBEEF, len: Length:24, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEAD, len: Length:16, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEADEF, len: Length:24, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEADBE, len: Length:24, id: Id:0, dest: Dest:0, last: false}, + TestStrobedStream{data: Data:0xDEADBEEF, len: Length:32, id: Id:0, dest: Dest:0, last: true} + ]; + + let tok = for (i, tok): (u32, token) in range(u32:0, u32:16) { + let tok = send(tok, stream_s, input_data[i]); + trace_fmt!("TestRemoveEmptyBytes: Sent #{} strobed packet: {:#x}", i + u32:1, input_data[i]); + let (tok, continuous_stream) = recv(tok, continuous_stream_r); + trace_fmt!("TestRemoveEmptyBytes: Received #{} continuous packet: {:#x}", i + u32:1, continuous_stream); + assert_eq(continuous_stream, expected_output[i]); + (tok) + } (tok); + + send(tok, terminator, true); + } } // Returns the number of bytes that should be soted in the state in case we @@ -71,22 +222,23 @@ fn get_overflow_len(len1: uN[LENGTH_W], len2: uN[LEN // Return the new mask for keep and str fields, calculated using new data length fn get_mask(len: uN[DATA_W_LOG2]) -> uN[DATA_W_DIV8] { - const MAX_LEN = DATA_W as uN[DATA_W_LOG2]; - const MASK = !uN[DATA_W_DIV8]:0; + let len_bytes = std::div_pow2(len, uN[DATA_W_LOG2]:8); + let mask = (uN[DATA_W_DIV8]:1 << len_bytes as uN[DATA_W_DIV8]) - uN[DATA_W_DIV8]:1; - let shift = std::div_pow2((MAX_LEN - len), uN[DATA_W_LOG2]:8); - MASK >> shift + mask } // A proc that removes empty bytes from the Axi Stream and provides aligned data // to other procs, allowing for a simpler implementation of the receiving side // of the design. -pub proc AxiStreamRemoveEmpty< +pub proc AxiStreamRemoveEmptyInternal< DATA_W: u32, DEST_W: u32, ID_W: u32, DATA_W_DIV8: u32 = {DATA_W / u32:8}, DATA_W_LOG2: u32 = {std::clog2(DATA_W + u32:1)}, > { type AxiStream = axi_st::AxiStream; + type StrobedStream = ContinuousStream; + type State = AxiStreamRemoveEmptyState; type Offset = uN[DATA_W_LOG2]; @@ -95,11 +247,11 @@ pub proc AxiStreamRemoveEmpty< type Str = uN[DATA_W_DIV8]; type Data = uN[DATA_W]; - stream_in_r: chan in; + stream_in_r: chan in; stream_out_s: chan out; config ( - stream_in_r: chan in, + stream_in_r: chan in, stream_out_s: chan out, ) { (stream_in_r, stream_out_s) @@ -112,17 +264,13 @@ pub proc AxiStreamRemoveEmpty< const MAX_MASK = !uN[DATA_W_DIV8]:0; let do_recv = !state.last; - let (tok, stream_in) = recv_if(join(), stream_in_r, !state.last, zero!()); - let (id, dest) = if !state.last { - (stream_in.id, stream_in.dest) + let (tok, stream_in) = recv_if(join(), stream_in_r, do_recv, zero!()); + let (id, dest, data, len) = if do_recv { + (stream_in.id, stream_in.dest, stream_in.data, stream_in.len) } else { - (state.id, state.dest) + (state.id, state.dest, Data:0, Length:0) }; - let (data, len) = remove_empty_bytes( - stream_in.data, stream_in.keep, stream_in.str - ); - let empty_input_bytes = MAX_LEN - len; let empty_state_bytes = MAX_LEN - state.len; @@ -131,12 +279,11 @@ pub proc AxiStreamRemoveEmpty< let combined_state_data = state.data | data << state.len; - let overflow_len = get_overflow_len(state.len, len); let sum_len = state.len + len; - let sum_mask = get_mask(sum_len); let (next_state, do_send, data) = if !state.last & exceeds_transfer { // flush and store + let overflow_len = get_overflow_len(state.len, len); ( State { data: data >> empty_state_bytes, @@ -156,6 +303,7 @@ pub proc AxiStreamRemoveEmpty< ) } else if state.last | stream_in.last | exact_transfer { // flush only + let sum_mask = get_mask(sum_len); ( zero!(), true, @@ -185,15 +333,55 @@ pub proc AxiStreamRemoveEmpty< } } +type InstAxiStream = axi_st::AxiStream; +type InstStrobedStream = ContinuousStream; -const INST_DATA_W = u32:32; -const INST_DEST_W = u32:32; -const INST_ID_W = u32:32; +proc AxiStreamRemoveEmptyInternalInst { + config ( + stream_in_r: chan in, + stream_out_s: chan out, + ) { + spawn AxiStreamRemoveEmptyInternal ( + stream_in_r, + stream_out_s + ); + } -const INST_DATA_W_DIV8 = INST_DATA_W / u32:8; -const INST_DATA_W_LOG2 = std::clog2(INST_DATA_W + u32:1); + init { } -type InstAxiStream = axi_st::AxiStream; + next (state:()) { } +} + +pub proc AxiStreamRemoveEmpty< + DATA_W: u32, DEST_W: u32, ID_W: u32, + DATA_W_DIV8: u32 = {DATA_W / u32:8}, + DATA_W_LOG2: u32 = {std::clog2(DATA_W + u32:1)}, +> { + type AxiStream = axi_st::AxiStream; + type StrobedStream = ContinuousStream; + + config ( + stream_in_r: chan in, + stream_out_s: chan out, + ) { + let (continuous_stream_s, continuous_stream_r) = chan("continuous_stream"); + + spawn RemoveEmptyBytes( + stream_in_r, + continuous_stream_s + ); + spawn AxiStreamRemoveEmptyInternal ( + continuous_stream_r, + stream_out_s + ); + + () + } + + init { () } + + next (state: ()) {} +} proc AxiStreamRemoveEmptyInst { config ( @@ -211,12 +399,6 @@ proc AxiStreamRemoveEmptyInst { next (state:()) { } } - -const TEST_DATA_W = u32:32; -const TEST_DEST_W = u32:32; -const TEST_ID_W = u32:32; -const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; - type TestAxiStream = axi_st::AxiStream; #[test_proc] @@ -465,6 +647,283 @@ proc AxiStreamRemoveEmptyTest { id: Id:0, dest: Dest:0, }); + + // Test 7: Some bits set, last set in the last transfer. + + + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xf7697fb9, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xc735df5e, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x70d3da1f, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x0000001d, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x01eaf614, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x00001734, + str: Str:0b0011, + keep: Keep:0b0011, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xe935b870, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x00f149f5, + str: Str:0b0111, + keep: Keep:0b0111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xf073eed1, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xce97b5bd, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x950cddd9, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x08f0ebd4, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xABEB9592, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0xB16E2D5C, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x157CF9C6, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let tok = send(tok, stream_in_s, TestAxiStream { + data: Data:0x00000019, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xf7697fb9, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xc735df5e, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x70d3da1f, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x0000001d, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x01eaf614, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x00001734, + str: Str:0b0011, + keep: Keep:0b0011, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xe935b870, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x00f149f5, + str: Str:0b0111, + keep: Keep:0b0111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xf073eed1, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xce97b5bd, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x950cddd9, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x08f0ebd4, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xABEB9592, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0xB16E2D5C, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x157CF9C6, + str: Str:0b1111, + keep: Keep:0b1111, + last: u1:0, + id: Id:0, + dest: Dest:0, + }); + let (tok, stream_out) = recv(tok, stream_out_r); + assert_eq(stream_out, TestAxiStream { + data: Data:0x00000019, + str: Str:0b0001, + keep: Keep:0b0001, + last: u1:1, + id: Id:0, + dest: Dest:0, + }); + send(tok, terminator, true); } } From c5ec87b5847183dadf710b2c8a9e58226d0f7c8d Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Wed, 13 Nov 2024 14:14:00 +0100 Subject: [PATCH 23/85] modules/zstd/memory/axi_writer: Assign parameterized max lane value Fix paramaterization of the proc Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/axi_writer.x | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xls/modules/zstd/memory/axi_writer.x b/xls/modules/zstd/memory/axi_writer.x index 58ed5dfbf3..1a5e7c5eef 100644 --- a/xls/modules/zstd/memory/axi_writer.x +++ b/xls/modules/zstd/memory/axi_writer.x @@ -124,6 +124,7 @@ pub proc AxiWriter< next(state: State) { const BYTES_IN_TRANSFER = DATA_W_DIV8 as Addr; const MAX_AXI_BURST_BYTES = Addr:256 * BYTES_IN_TRANSFER; + const MAX_LANE = std::unsigned_max_value(); let tok_0 = join(); @@ -273,7 +274,7 @@ pub proc AxiWriter< Fsm::AXI_WRITE_W => { let last = state.burst_counter == state.burst_end; let low_lane = state.req_low_lane; - let high_lane = if (last) { state.req_high_lane } else {Lane:3}; + let high_lane = if (last) { state.req_high_lane } else {MAX_LANE}; let mask = common::lane_mask(low_lane, high_lane); AxiW { From 70384f360daa810ae17e5e19dfafc088f55775a7 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 12 May 2025 19:53:06 +0200 Subject: [PATCH 24/85] modules/zstd/memory/mem_writer: Add support for not-full input data packets Add AxiStreamRemoveEmpty proc to the processing pipeline. It removes non-strobed bytes from the input AXI Stream frames and forms full frames (ensures that only the last input data packet won't be full). Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/BUILD | 5 +- xls/modules/zstd/memory/mem_writer.x | 86 +++++++++++++++++++++++++++- 2 files changed, 85 insertions(+), 6 deletions(-) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index 2368579c26..f80c064ead 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -847,6 +847,7 @@ xls_dslx_library( ":axi_dslx", ":axi_st_dslx", ":axi_stream_add_empty_dslx", + ":axi_stream_remove_empty_dslx", ":axi_writer_dslx", ":common_dslx", ], @@ -859,13 +860,11 @@ xls_dslx_test( mem_writer_codegen_args = common_codegen_args | { "module_name": "mem_writer", - "pipeline_stages": "2", + "pipeline_stages": "3", "streaming_channel_data_suffix": "_data", "multi_proc": "true", "flop_inputs_kind": "skid", "flop_outputs_kind": "skid", - "worst_case_throughput": "1", - "fifo_module": "", "materialize_internal_fifos": "true", } diff --git a/xls/modules/zstd/memory/mem_writer.x b/xls/modules/zstd/memory/mem_writer.x index 277c9910ef..8e53155b05 100644 --- a/xls/modules/zstd/memory/mem_writer.x +++ b/xls/modules/zstd/memory/mem_writer.x @@ -35,6 +35,7 @@ import xls.modules.zstd.memory.axi; import xls.modules.zstd.memory.axi_st; import xls.modules.zstd.memory.common; import xls.modules.zstd.memory.axi_writer; +import xls.modules.zstd.memory.axi_stream_remove_empty; import xls.modules.zstd.memory.axi_stream_add_empty; pub struct MemWriterReq { @@ -108,11 +109,15 @@ proc MemWriter< let (axi_writer_req_s, axi_writer_req_r) = chan("axi_writer_req"); let (padding_req_s, padding_req_r) = chan("padding_req"); let (axi_st_raw_s, axi_st_raw_r) = chan("axi_st_raw"); + let (axi_st_clean_s, axi_st_clean_r) = chan("axi_st_clean"); let (axi_st_padded_s, axi_st_padded_r) = chan("axi_st_padded"); + spawn axi_stream_remove_empty::AxiStreamRemoveEmpty< + DATA_W, DEST_W, ID_W + >(axi_st_raw_r, axi_st_clean_s); spawn axi_stream_add_empty::AxiStreamAddEmpty< DATA_W, DEST_W, ID_W, ADDR_W - >(padding_req_r, axi_st_raw_r, axi_st_padded_s); + >(padding_req_r, axi_st_clean_r, axi_st_padded_s); spawn axi_writer::AxiWriter< ADDR_W, DATA_W, DEST_W, ID_W >(axi_writer_req_r, resp_s, axi_aw_s, axi_w_s, axi_b_r, axi_st_padded_r); @@ -147,7 +152,7 @@ proc MemWriter< } }, Fsm::SEND_DATA => { - let next_req_len = state.req_len - sLength:4; + let next_req_len = state.req_len - data_in.length as sLength; State { fsm: if (next_req_len <= sLength:0) {Fsm::RECV_REQ} else {Fsm::SEND_DATA}, req_len: next_req_len, @@ -162,7 +167,7 @@ proc MemWriter< let raw_axi_st_frame = match(state.fsm) { Fsm::SEND_DATA => { - let next_req_len = state.req_len - sLength:4; + let next_req_len = next_state.req_len; let str_keep = ((Length:1 << data_in.length) - Length:1) as Strobe; AxiStream { data: data_in.data, @@ -631,6 +636,81 @@ proc MemWriterTest { let (tok, resp) = recv(tok, resp_r); assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + // Unligned 3 transfers + let tok = send(tok, req_in_s, TestReq { + addr: TestAddr:0x1f3, + length: TestLength:15 + }); + let tok = send(tok, data_in_s, TestData { + data: TestDataBits:0x11223344, + length: TestLength:4, + last: false, + }); + let tok = send(tok, data_in_s, TestData { + data: TestDataBits:0x00005566, + length: TestLength:2, + last: false, + }); + let tok = send(tok, data_in_s, TestData { + data: TestDataBits:0x778899aa, + length: TestLength:4, + last: false, + }); + let tok = send(tok, data_in_s, TestData { + data: TestDataBits:0x00bbccdd, + length: TestLength:3, + last: false, + }); + let tok = send(tok, data_in_s, TestData { + data: TestDataBits:0x0000eeff, + length: TestLength:2, + last: true, + }); + let (tok, aw) = recv(tok, axi_aw_r); + assert_eq(aw, TestAxiAW { + id: TestId:12, + addr: TestAddr:0x1f0, + size: TestAxiAxSize::MAX_4B_TRANSFER, + len: u8:4, + burst: TestAxiAxBurst::INCR, + }); + let (tok, w) = recv(tok, axi_w_r); + assert_eq(w, TestAxiW { + data: TestDataBits:0x44000000, + strb: TestStrobe:0x8, + last: false, + }); + let (tok, w) = recv(tok, axi_w_r); + assert_eq(w, TestAxiW { + data: TestDataBits:0x66112233, + strb: TestStrobe:0xF, + last: false, + }); + let (tok, w) = recv(tok, axi_w_r); + assert_eq(w, TestAxiW { + data: TestDataBits:0x8899aa55, + strb: TestStrobe:0xf, + last: false, + }); + let (tok, w) = recv(tok, axi_w_r); + assert_eq(w, TestAxiW { + data: TestDataBits:0xbbccdd77, + strb: TestStrobe:0xf, + last: false, + }); + let (tok, w) = recv(tok, axi_w_r); + assert_eq(w, TestAxiW { + data: TestDataBits:0x0000eeff, + strb: TestStrobe:0x3, + last: true, + }); + let tok = send(tok, axi_b_s, TestAxiB { + resp: TestAxiWriteResp::OKAY, + id: TestId:12, + }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + send(tok, terminator, true); } } From 4e7350a997f28951b8fedc0748e506d8b5266f4c Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 12 May 2025 20:42:00 +0200 Subject: [PATCH 25/85] modules/zstd/memory/mem_writer: Add MemWriterInternal proc * Extract control logic to MemWriterInternal proc * Create alias for the MemWriter response type Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/BUILD | 63 ++++++++++- xls/modules/zstd/memory/mem_writer.x | 153 +++++++++++++++++++-------- 2 files changed, 168 insertions(+), 48 deletions(-) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index f80c064ead..39a111dfe5 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -858,11 +858,70 @@ xls_dslx_test( library = ":mem_writer_dslx", ) +mem_writer_internal_codegen_args = common_codegen_args | { + "module_name": "mem_writer_internal", + "pipeline_stages": "2", +} + +xls_dslx_verilog( + name = "mem_writer_internal_verilog", + codegen_args = mem_writer_internal_codegen_args, + dslx_top = "MemWriterInternalInst", + library = ":mem_writer_dslx", + tags = ["manual"], + verilog_file = "mem_writer_internal.v", +) + +xls_benchmark_ir( + name = "mem_writer_internal_opt_ir_benchmark", + src = ":mem_writer_internal_verilog.opt.ir", + benchmark_ir_args = common_codegen_args | { + "pipeline_stages": "10", + "top": "__mem_writer__MemWriterInternalInst__MemWriterInternal_0__16_32_4_4_4_2_next", + }, + tags = ["manual"], +) + +verilog_library( + name = "mem_writer_internal_verilog_lib", + srcs = [ + ":mem_writer_internal.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "mem_writer_internal_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "mem_writer_internal", + deps = [ + ":mem_writer_internal_verilog_lib", + ], +) + +benchmark_synth( + name = "mem_writer_internal_benchmark_synth", + synth_target = ":mem_writer_internal_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "mem_writer_internal_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":mem_writer_internal_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + mem_writer_codegen_args = common_codegen_args | { "module_name": "mem_writer", - "pipeline_stages": "3", + "pipeline_stages": "10", "streaming_channel_data_suffix": "_data", - "multi_proc": "true", "flop_inputs_kind": "skid", "flop_outputs_kind": "skid", "materialize_internal_fifos": "true", diff --git a/xls/modules/zstd/memory/mem_writer.x b/xls/modules/zstd/memory/mem_writer.x index 8e53155b05..f49d147785 100644 --- a/xls/modules/zstd/memory/mem_writer.x +++ b/xls/modules/zstd/memory/mem_writer.x @@ -43,6 +43,9 @@ pub struct MemWriterReq { length: uN[ADDR_W], } +pub type MemWriterResp = axi_writer::AxiWriterResp; +pub type MemWriterRespStatus = axi_writer::AxiWriterRespStatus; + pub struct MemWriterDataPacket { data: uN[DATA_W], length: uN[ADDR_W], // Expressed in bytes @@ -68,20 +71,15 @@ struct MemWriterState< axi_writer_req: axi_writer::AxiWriterRequest, } -proc MemWriter< +proc MemWriterInternal< ADDR_W: u32, DATA_W: u32, DEST_W: u32, ID_W: u32, WRITER_ID: u32, - DATA_W_DIV8: u32 = {DATA_W / u32:8}, - DATA_W_LOG2: u32 = {std::clog2(DATA_W / u32:8)} + DATA_W_DIV8: u32 = {DATA_W / u32:8} > { type Req = MemWriterReq; type Data = MemWriterDataPacket; type AxiWriterReq = axi_writer::AxiWriterRequest; - type AxiWriterResp = axi_writer::AxiWriterResp; type PaddingReq = axi_writer::AxiWriterRequest; type AxiStream = axi_st::AxiStream; - type AxiAW = axi::AxiAw; - type AxiW = axi::AxiW; - type AxiB = axi::AxiB; type State = MemWriterState; type Fsm = MemWriterFsm; @@ -96,33 +94,16 @@ proc MemWriter< axi_writer_req_s: chan out; padding_req_s: chan out; axi_st_raw_s: chan out; - resp_s: chan out; config( req_in_r: chan in, data_in_r: chan in, - axi_aw_s: chan out, - axi_w_s: chan out, - axi_b_r: chan in, - resp_s: chan out, + axi_writer_req_s: chan out, + padding_req_s: chan out, + axi_st_raw_s: chan out, ) { - let (axi_writer_req_s, axi_writer_req_r) = chan("axi_writer_req"); - let (padding_req_s, padding_req_r) = chan("padding_req"); - let (axi_st_raw_s, axi_st_raw_r) = chan("axi_st_raw"); - let (axi_st_clean_s, axi_st_clean_r) = chan("axi_st_clean"); - let (axi_st_padded_s, axi_st_padded_r) = chan("axi_st_padded"); - - spawn axi_stream_remove_empty::AxiStreamRemoveEmpty< - DATA_W, DEST_W, ID_W - >(axi_st_raw_r, axi_st_clean_s); - spawn axi_stream_add_empty::AxiStreamAddEmpty< - DATA_W, DEST_W, ID_W, ADDR_W - >(padding_req_r, axi_st_clean_r, axi_st_padded_s); - spawn axi_writer::AxiWriter< - ADDR_W, DATA_W, DEST_W, ID_W - >(axi_writer_req_r, resp_s, axi_aw_s, axi_w_s, axi_b_r, axi_st_padded_r); - (req_in_r, data_in_r, axi_writer_req_s, padding_req_s, axi_st_raw_s, resp_s) + (req_in_r, data_in_r, axi_writer_req_s, padding_req_s, axi_st_raw_s) } init { zero!() } @@ -194,9 +175,90 @@ const INST_DATA_W = u32:32; const INST_DATA_W_DIV8 = INST_DATA_W / u32:8; const INST_DEST_W = INST_DATA_W / u32:8; const INST_ID_W = INST_DATA_W / u32:8; -const INST_DATA_W_LOG2 = u32:6; const INST_WRITER_ID = u32:2; +proc MemWriterInternalInst { + type Req = MemWriterReq; + type Data = MemWriterDataPacket; + type AxiWriterReq = axi_writer::AxiWriterRequest; + type PaddingReq = axi_writer::AxiWriterRequest; + type AxiStream = axi_st::AxiStream; + + config( + req_in_r: chan in, + data_in_r: chan in, + axi_writer_req_s: chan out, + padding_req_s: chan out, + axi_st_raw_s: chan out, + ) { + + spawn MemWriterInternal< + INST_ADDR_W, INST_DATA_W, INST_DEST_W, INST_ID_W, INST_WRITER_ID + >(req_in_r, data_in_r, axi_writer_req_s, padding_req_s, axi_st_raw_s); + () + } + + init {} + + next(state: ()) {} +} + +pub proc MemWriter< + ADDR_W: u32, DATA_W: u32, DEST_W: u32, ID_W: u32, WRITER_ID: u32, + DATA_W_DIV8: u32 = {DATA_W / u32:8} +> { + type Req = MemWriterReq; + type Data = MemWriterDataPacket; + type AxiWriterReq = axi_writer::AxiWriterRequest; + type PaddingReq = axi_writer::AxiWriterRequest; + type AxiStream = axi_st::AxiStream; + type AxiAW = axi::AxiAw; + type AxiW = axi::AxiW; + type AxiB = axi::AxiB; + type State = MemWriterState; + type Fsm = MemWriterFsm; + + type Length = uN[ADDR_W]; + type sLength = sN[ADDR_W]; + type Strobe = uN[DATA_W_DIV8]; + type Id = uN[ID_W]; + type Dest = uN[DEST_W]; + + config( + req_in_r: chan in, + data_in_r: chan in, + axi_aw_s: chan out, + axi_w_s: chan out, + axi_b_r: chan in, + resp_s: chan out, + ) { + let (axi_writer_req_s, axi_writer_req_r) = chan("axi_writer_req"); + let (padding_req_s, padding_req_r) = chan("padding_req"); + let (axi_st_raw_s, axi_st_raw_r) = chan("axi_st_raw"); + let (axi_st_clean_s, axi_st_clean_r) = chan("axi_st_clean"); + let (axi_st_padded_s, axi_st_padded_r) = chan("axi_st_padded"); + + spawn MemWriterInternal< + ADDR_W, DATA_W, DEST_W, ID_W, WRITER_ID + >(req_in_r, data_in_r, axi_writer_req_s, padding_req_s, axi_st_raw_s); + spawn axi_stream_remove_empty::AxiStreamRemoveEmpty< + DATA_W, DEST_W, ID_W + >(axi_st_raw_r, axi_st_clean_s); + spawn axi_stream_add_empty::AxiStreamAddEmpty< + DATA_W, DEST_W, ID_W, ADDR_W + >(padding_req_r, axi_st_clean_r, axi_st_padded_s); + spawn axi_writer::AxiWriter< + ADDR_W, DATA_W, DEST_W, ID_W + >(axi_writer_req_r, resp_s, axi_aw_s, axi_w_s, axi_b_r, axi_st_padded_r); + + () + } + + init {} + + next(state: ()) {} +} + proc MemWriterInst { type InstReq = MemWriterReq; type InstData = MemWriterDataPacket; @@ -204,7 +266,7 @@ proc MemWriterInst { type InstAxiAW = axi::AxiAw; type InstAxiW = axi::AxiW; type InstAxiB = axi::AxiB; - type InstAxiWriterResp = axi_writer::AxiWriterResp; + type InstMemWriterResp = MemWriterResp; config( req_in_r: chan in, @@ -212,7 +274,7 @@ proc MemWriterInst { axi_aw_s: chan out, axi_w_s: chan out, axi_b_r: chan in, - resp_s: chan out + resp_s: chan out ) { spawn MemWriter< INST_ADDR_W, INST_DATA_W, INST_DEST_W, INST_ID_W, INST_WRITER_ID @@ -230,13 +292,12 @@ const TEST_DATA_W = u32:32; const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; const TEST_DEST_W = TEST_DATA_W / u32:8; const TEST_ID_W = TEST_DATA_W / u32:8; -const TEST_DATA_W_LOG2 = u32:6; const TEST_WRITER_ID = u32:2; type TestReq = MemWriterReq; type TestData = MemWriterDataPacket; -type TestAxiWriterResp = axi_writer::AxiWriterResp; -type TestAxiWriterRespStatus = axi_writer::AxiWriterRespStatus; +type TestMemWriterResp = MemWriterResp; +type TestMemWriterRespStatus = MemWriterRespStatus; type TestAxiStream = axi_st::AxiStream; type TestAxiAW = axi::AxiAw; type TestAxiW = axi::AxiW; @@ -260,7 +321,7 @@ proc MemWriterTest { axi_aw_r: chan in; axi_w_r: chan in; axi_b_s: chan out; - resp_r: chan in; + resp_r: chan in; config( terminator: chan out, @@ -270,7 +331,7 @@ proc MemWriterTest { let (axi_aw_s, axi_aw_r) = chan("axi_aw"); let (axi_w_s, axi_w_r) = chan("axi_w"); let (axi_b_s, axi_b_r) = chan("axi_b"); - let (resp_s, resp_r) = chan("resp"); + let (resp_s, resp_r) = chan("resp"); spawn MemWriter< TEST_ADDR_W, TEST_DATA_W, TEST_DEST_W, TEST_ID_W, TEST_WRITER_ID >(req_in_r, data_in_r, axi_aw_s, axi_w_s, axi_b_r, resp_s); @@ -311,7 +372,7 @@ proc MemWriterTest { id: TestId:1, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unaligned single transfer let tok = send(tok, req_in_s, TestReq { @@ -342,7 +403,7 @@ proc MemWriterTest { id: TestId:2, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unaligned single transfer let tok = send(tok, req_in_s, TestReq { @@ -373,7 +434,7 @@ proc MemWriterTest { id: TestId:3, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unaligned single transfer let tok = send(tok, req_in_s, TestReq { @@ -404,7 +465,7 @@ proc MemWriterTest { id: TestId:4, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unaligned single transfer let tok = send(tok, req_in_s, TestReq { @@ -435,7 +496,7 @@ proc MemWriterTest { id: TestId:5, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unaligned 2 transfers let tok = send(tok, req_in_s, TestReq { @@ -472,7 +533,7 @@ proc MemWriterTest { id: TestId:6, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unligned 3 transfers let tok = send(tok, req_in_s, TestReq { @@ -520,7 +581,7 @@ proc MemWriterTest { id: TestId:7, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Crossing AXI 4kB boundary, aligned 2 burst transfers let tok = send(tok, req_in_s, TestReq { @@ -574,7 +635,7 @@ proc MemWriterTest { id: TestId:9, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Crossing AXI 4kB boundary, unaligned 2 burst transfers let tok = send(tok, req_in_s, TestReq { @@ -634,7 +695,7 @@ proc MemWriterTest { id: TestId:11, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); // Unligned 3 transfers let tok = send(tok, req_in_s, TestReq { @@ -709,7 +770,7 @@ proc MemWriterTest { id: TestId:12, }); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, TestAxiWriterResp{status: TestAxiWriterRespStatus::OKAY}); + assert_eq(resp, TestMemWriterResp{status: TestMemWriterRespStatus::OKAY}); send(tok, terminator, true); } From 7bc669bd8fc671388f7d702a2d1564662a2a54ae Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 13 May 2025 14:44:07 +0200 Subject: [PATCH 26/85] modules/zstd/zstd_dec: Write decoded data to the memory SequenceExecutor: * Add output channel in the format compliant with MemWriter input data channel type ZstdDecoder: * Add MemWriter proc: * Write request formed based on the address of the OutputBuffer CSR and FrameContentSize field from the Frame Header * Data to write is sent out to the proc by the SequenceExecutor * Transition to the FINISH state (and triggers notify channel) only after receiving the response from the MemWriter * DSLX tests: * Receive decoded data sent out on the AXI interface by the MemWriter proc * Mock the output memory buffer as a DSLX array Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 5 +- xls/modules/zstd/sequence_executor.x | 75 ++++++++++++++-- xls/modules/zstd/zstd_dec.x | 89 +++++++++++++++++- xls/modules/zstd/zstd_dec_test.x | 129 +++++++++++++++++++++------ 4 files changed, 260 insertions(+), 38 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 70bda5af9b..77c0270bd9 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -607,6 +607,7 @@ xls_dslx_library( ":common_dslx", ":ram_printer_dslx", "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:mem_writer_dslx", ], ) @@ -651,7 +652,8 @@ xls_dslx_verilog( dslx_top = "SequenceExecutorZstd", library = ":sequence_executor_dslx", opt_ir_args = { - "top": "__sequence_executor__SequenceExecutorZstd__SequenceExecutor_0__64_0_0_0_13_8192_65536_next", + "inline_procs": "true", + "top": "__sequence_executor__SequenceExecutorZstd__SequenceExecutor_0__16_64_64_0_0_0_13_8192_65536_next", }, tags = ["manual"], verilog_file = "sequence_executor.v", @@ -875,6 +877,7 @@ zstd_dec_deps = [ ":sequence_executor_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", + "//xls/modules/zstd/memory:mem_writer_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", ] diff --git a/xls/modules/zstd/sequence_executor.x b/xls/modules/zstd/sequence_executor.x index 1e01f9b03c..d87bfc1bd6 100644 --- a/xls/modules/zstd/sequence_executor.x +++ b/xls/modules/zstd/sequence_executor.x @@ -14,6 +14,7 @@ import std; import xls.modules.zstd.common as common; +import xls.modules.zstd.memory.mem_writer as mem_writer; import xls.modules.zstd.ram_printer as ram_printer; import xls.examples.ram; @@ -53,6 +54,8 @@ fn ram_addr_width(hb_size_kb: u32) -> u32 { std::clog2(ram_size(hb_size_kb)) } // RAM related constants common for tests const TEST_HISTORY_BUFFER_SIZE_KB = u32:1; +const TEST_DATA_W = u32:64; +const TEST_ADDR_W = u32:16; const TEST_RAM_SIZE = ram_size(TEST_HISTORY_BUFFER_SIZE_KB); const TEST_RAM_ADDR_WIDTH = ram_addr_width(TEST_HISTORY_BUFFER_SIZE_KB); pub const TEST_RAM_INITIALIZED = true; @@ -114,6 +117,36 @@ fn test_decode_literal_packet() { }) } +fn convert_output_packet(packet: ZstdDecodedPacket) -> mem_writer::MemWriterDataPacket { + type MemWriterDataPacket = mem_writer::MemWriterDataPacket; + MemWriterDataPacket { + data: packet.data as uN[DATA_W], + length: std::div_pow2(packet.length, u32:8) as uN[ADDR_W], + last: packet.last + } +} + +#[test] +fn test_convert_output_packet() { + const DATA_W = u32:64; + const ADDR_W = u32:16; + + type MemWriterDataPacket = mem_writer::MemWriterDataPacket; + + let packet = ZstdDecodedPacket { + data: CopyOrMatchContent:0xAA00BB11CC22DD33, + length: BlockPacketLength:64, + last: false + }; + let expected = MemWriterDataPacket { + data: uN[DATA_W]:0xAA00BB11CC22DD33, + length: uN[ADDR_W]:8, + last: false + }; + + assert_eq(convert_output_packet(packet), expected) +} + fn round_up_to_pow2(x: uN[N]) -> uN[N] { let base = x[Y_CLOG2 as s32:]; let reminder = x[0:Y_CLOG2 as s32] != bits[Y_CLOG2]:0; @@ -808,14 +841,18 @@ fn handle_reapeated_offset_for_sequences } pub proc SequenceExecutor { + type MemWriterDataPacket = mem_writer::MemWriterDataPacket; + input_r: chan in; output_s: chan out; + output_mem_wr_data_in_s: chan out; ram_comp_input_s: chan> out; ram_comp_output_r: chan> in; ram_resp_input_s: chan out; @@ -840,6 +877,7 @@ pub proc SequenceExecutor in, output_s: chan out, + output_mem_wr_data_in_s: chan out, ram_resp_output_r: chan in, ram_resp_output_s: chan out, rd_req_m0_s: chan> out, @@ -890,7 +928,7 @@ pub proc SequenceExecutor(output_data); + let tok2_10_1 = send_if(tok1, output_mem_wr_data_in_s, do_write_output, output_mem_wr_data_in); // Ask for response let tok2_11 = send_if(tok1, rd_req_m0_s, (read_reqs[0]).mask != RAM_REQ_MASK_NONE, read_reqs[0]); @@ -1142,14 +1182,18 @@ pub proc SequenceExecutor; init { } config( input_r: chan in, output_s: chan out, + output_mem_wr_data_in_s: chan out, looped_channel_r: chan in, looped_channel_s: chan out, rd_req_m0_s: chan> out, @@ -1185,8 +1229,9 @@ pub proc SequenceExecutorZstd { wr_resp_m6_r: chan in, wr_resp_m7_r: chan in ) { - spawn SequenceExecutor ( - input_r, output_s, + spawn SequenceExecutor ( + input_r, output_s, output_mem_wr_data_in_s, looped_channel_r, looped_channel_s, rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, @@ -1298,10 +1343,12 @@ const LITERAL_TEST_MEMORY_CONTENT:(TestRamAddr, RamData)[3][RAM_NUM] = [ #[test_proc] proc SequenceExecutorLiteralsTest { + type MemWriterDataPacket = mem_writer::MemWriterDataPacket; terminator: chan out; input_s: chan> out; output_r: chan in; + output_mem_wr_data_in_r: chan in; print_start_s: chan<()> out; print_finish_r: chan<()> in; @@ -1314,6 +1361,7 @@ proc SequenceExecutorLiteralsTest { config(terminator: chan out) { let (input_s, input_r) = chan>("input"); let (output_s, output_r) = chan("output"); + let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); let (looped_channel_s, looped_channel_r) = chan("looped_channels"); @@ -1328,11 +1376,12 @@ proc SequenceExecutorLiteralsTest { let INIT_HB_PTR_ADDR = u32:127; spawn SequenceExecutor< TEST_HISTORY_BUFFER_SIZE_KB, + TEST_DATA_W, TEST_ADDR_W, TEST_RAM_SIZE, TEST_RAM_ADDR_WIDTH, INIT_HB_PTR_ADDR, > ( - input_r, output_s, + input_r, output_s, output_mem_wr_data_in_s, looped_channel_r, looped_channel_s, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], @@ -1384,7 +1433,7 @@ proc SequenceExecutorLiteralsTest { ( terminator, - input_s, output_r, + input_s, output_r, output_mem_wr_data_in_r, print_start_s, print_finish_r, ram_rd_req_s, ram_rd_resp_r, ram_wr_req_s, ram_wr_resp_r @@ -1404,6 +1453,9 @@ proc SequenceExecutorLiteralsTest { let (tok, recv_data) = recv(tok, output_r); let expected = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); assert_eq(expected, recv_data); + let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); + let expected_mem_writer_data = convert_output_packet(expected); + assert_eq(expected_mem_writer_data, recv_mem_writer_data); } else {} }(()); @@ -1554,10 +1606,12 @@ const SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS:ZstdDecodedPacket[11] = [ #[test_proc] proc SequenceExecutorSequenceTest { + type MemWriterDataPacket = mem_writer::MemWriterDataPacket; terminator: chan out; input_s: chan out; output_r: chan in; + output_mem_wr_data_in_r: chan in; print_start_s: chan<()> out; print_finish_r: chan<()> in; @@ -1570,6 +1624,7 @@ proc SequenceExecutorSequenceTest { config(terminator: chan out) { let (input_s, input_r) = chan("input"); let (output_s, output_r) = chan("output"); + let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); let (looped_channel_s, looped_channel_r) = chan("looped_channel"); @@ -1584,11 +1639,12 @@ proc SequenceExecutorSequenceTest { let INIT_HB_PTR_ADDR = u32:127; spawn SequenceExecutor< TEST_HISTORY_BUFFER_SIZE_KB, + TEST_DATA_W, TEST_ADDR_W, TEST_RAM_SIZE, TEST_RAM_ADDR_WIDTH, INIT_HB_PTR_ADDR, > ( - input_r, output_s, + input_r, output_s, output_mem_wr_data_in_s, looped_channel_r, looped_channel_s, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], @@ -1640,7 +1696,7 @@ proc SequenceExecutorSequenceTest { ( terminator, - input_s, output_r, + input_s, output_r, output_mem_wr_data_in_r, print_start_s, print_finish_r, ram_rd_req_s, ram_rd_resp_r, ram_wr_req_s, ram_wr_resp_r ) @@ -1659,6 +1715,9 @@ proc SequenceExecutorSequenceTest { let (tok, recv_data) = recv(tok, output_r); let expected = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); assert_eq(expected, recv_data); + let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); + let expected_mem_writer_data = convert_output_packet(expected); + assert_eq(expected_mem_writer_data, recv_mem_writer_data); } else {} }(()); diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index 528d16d599..7fc5fb260e 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -23,6 +23,7 @@ import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; import xls.modules.zstd.csr_config; import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.memory.mem_writer; import xls.modules.zstd.frame_header_dec; import xls.modules.zstd.block_header; import xls.modules.zstd.block_header_dec; @@ -45,7 +46,8 @@ enum ZstdDecoderInternalFsm: u4 { DECODE_RLE_BLOCK = 5, DECODE_COMPRESSED_BLOCK = 6, DECODE_CHECKSUM = 7, - FINISH = 8, + WRITE_OUTPUT = 8, + FINISH = 9, ERROR = 13, INVALID = 15, } @@ -128,6 +130,9 @@ proc ZstdDecoderInternal< type MemReaderReq = mem_reader::MemReaderReq; type MemReaderResp = mem_reader::MemReaderResp; + type MemWriterReq = mem_writer::MemWriterReq; + type MemWriterResp = mem_writer::MemWriterResp; + type FrameHeaderDecoderStatus = frame_header_dec::FrameHeaderDecoderStatus; type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; @@ -167,6 +172,10 @@ proc ZstdDecoderInternal< rle_req_s: chan out; rle_resp_r: chan in; + // Output MemWriter + output_mem_wr_req_s: chan out; + output_mem_wr_resp_r: chan in; + notify_s: chan<()> out; reset_s: chan<()> out; @@ -197,6 +206,10 @@ proc ZstdDecoderInternal< rle_req_s: chan out, rle_resp_r: chan in, + // Output MemWriter + output_mem_wr_req_s: chan out, + output_mem_wr_resp_r: chan in, + notify_s: chan<()> out, reset_s: chan<()> out, ) { @@ -206,6 +219,7 @@ proc ZstdDecoderInternal< bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ) } @@ -259,6 +273,15 @@ proc ZstdDecoderInternal< trace_fmt!("[DECODE_FRAME_HEADER]: Received FH {:#x}", fh_resp); } else {}; + let output_mem_wr_req = MemWriterReq {addr: state.output_buffer, length: fh_resp.header.frame_content_size as uN[AXI_ADDR_W]}; + let tok = send_if(tok0, output_mem_wr_req_s, fh_resp_valid, output_mem_wr_req); + + let do_recv_output_mem_wr_resp = (state.fsm == Fsm::WRITE_OUTPUT); + let (tok_x, output_write_resp, output_write_done) = recv_if_non_blocking(tok0, output_mem_wr_resp_r, do_recv_output_mem_wr_resp, zero!()); + if output_write_done { + trace_fmt!("[WRITE_OUTPUT]: Received response {:#x}", output_write_resp); + } else {}; + let do_send_notify = (state.fsm == Fsm::ERROR || state.fsm == Fsm::FINISH); let tok = send_if(tok0, notify_s, do_send_notify, ()); if do_send_notify { @@ -518,10 +541,22 @@ proc ZstdDecoderInternal< Fsm::DECODE_CHECKSUM => { trace_fmt!("[DECODE_CHECKSUM]"); - State {fsm: Fsm::FINISH, ..zero!() } + State {fsm: Fsm::WRITE_OUTPUT, ..zero!() } }, + Fsm::WRITE_OUTPUT => { + trace_fmt!("[WRITE_OUTPUT]"); + let error = (output_write_resp.status != mem_writer::MemWriterRespStatus::OKAY); + let fsm = match (output_write_done, error) { + (true, false) => Fsm::FINISH, + (true, true) => Fsm::ERROR, + ( _, _) => Fsm::WRITE_OUTPUT, + }; + + State {fsm: fsm, ..zero!() } + }, + Fsm::ERROR => { trace_fmt!("[ERROR]"); State { fsm: Fsm::IDLE, ..zero!() } @@ -586,6 +621,9 @@ proc ZstdDecoderInternalTest { type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; type RleBlockDecoderStatus = rle_block_dec::RleBlockDecoderStatus; + type MemWriterReq = mem_writer::MemWriterReq; + type MemWriterResp = mem_writer::MemWriterResp; + terminator: chan out; csr_rd_req_r: chan in; @@ -606,6 +644,9 @@ proc ZstdDecoderInternalTest { rle_req_r: chan in; rle_resp_s: chan out; + output_mem_wr_req_r: chan in; + output_mem_wr_resp_s: chan out; + notify_r: chan<()> in; reset_r: chan<()> in; @@ -630,6 +671,9 @@ proc ZstdDecoderInternalTest { let (rle_req_s, rle_req_r) = chan("rle_req"); let (rle_resp_s, rle_resp_r) = chan("rle_resp"); + let (output_mem_wr_req_s, output_mem_wr_req_r) = chan("output_mem_wr_req"); + let (output_mem_wr_resp_s, output_mem_wr_resp_r) = chan("output_mem_wr_resp"); + let (notify_s, notify_r) = chan<()>("notify"); let (reset_s, reset_r) = chan<()>("reset"); @@ -639,6 +683,7 @@ proc ZstdDecoderInternalTest { bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ); @@ -649,6 +694,7 @@ proc ZstdDecoderInternalTest { bh_req_r, bh_resp_s, raw_req_r, raw_resp_s, rle_req_r, rle_resp_s, + output_mem_wr_req_r, output_mem_wr_resp_s, notify_r, reset_r, ) } @@ -802,6 +848,9 @@ proc ZstdDecoderInternalTest { let (tok, ()) = recv(tok, notify_r); + let (tok, _) = recv(tok, output_mem_wr_req_r); + let tok = send(tok, output_mem_wr_resp_s, MemWriterResp {status: mem_writer::MemWriterRespStatus::OKAY}); + send(tok, terminator, true); } } @@ -817,6 +866,7 @@ pub proc ZstdDecoder< AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, LOG2_REGS_N: u32 = {std::clog2(REGS_N)}, HB_RAM_N: u32 = {u32:8}, + MEM_WRITER_ID: u32 = {u32:0}, > { type CsrAxiAr = axi::AxiAr; type CsrAxiR = axi::AxiR; @@ -838,6 +888,9 @@ pub proc ZstdDecoder< type MemReaderReq = mem_reader::MemReaderReq; type MemReaderResp = mem_reader::MemReaderResp; + type MemWriterReq = mem_writer::MemWriterReq; + type MemWriterResp = mem_writer::MemWriterResp; + type MemWriterDataPacket = mem_writer::MemWriterDataPacket; type FrameHeaderDecoderReq = frame_header_dec::FrameHeaderDecoderReq; type FrameHeaderDecoderResp = frame_header_dec::FrameHeaderDecoderResp; @@ -885,6 +938,11 @@ pub proc ZstdDecoder< raw_axi_ar_s: chan out, raw_axi_r_r: chan in, + //// AXI Output Writer (manager) + output_axi_aw_s: chan out, + output_axi_w_s: chan out, + output_axi_b_r: chan in, + // History Buffer ram_rd_req_0_s: chan out, ram_rd_req_1_s: chan out, @@ -1031,12 +1089,13 @@ pub proc ZstdDecoder< ); // Sequence Execution - let (seq_exec_looped_s, seq_exec_looped_r) = chan("seq_exec_looped"); let (seq_exec_output_s, seq_exec_output_r) = chan("seq_exec_output"); + let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); - spawn sequence_executor::SequenceExecutor( + spawn sequence_executor::SequenceExecutor( seq_exec_input_r, seq_exec_output_s, + output_mem_wr_data_in_s, seq_exec_looped_r, seq_exec_looped_s, ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, @@ -1053,6 +1112,13 @@ pub proc ZstdDecoder< spawn repacketizer::Repacketizer(seq_exec_output_r, output_s); // Zstd Decoder Control + let (output_mem_wr_req_s, output_mem_wr_req_r) = chan("output_mem_wr_req"); + let (output_mem_wr_resp_s, output_mem_wr_resp_r) = chan("output_mem_wr_resp"); + + spawn mem_writer::MemWriter( + output_mem_wr_req_r, output_mem_wr_data_in_r, + output_axi_aw_s, output_axi_w_s, output_axi_b_r, output_mem_wr_resp_s + ); spawn ZstdDecoderInternal ( csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, @@ -1060,6 +1126,7 @@ pub proc ZstdDecoder< bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ); @@ -1108,6 +1175,9 @@ proc ZstdDecoderInternalInst { type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + type MemWriterReq = mem_writer::MemWriterReq; + type MemWriterResp = mem_writer::MemWriterResp; + init { } config( @@ -1133,6 +1203,10 @@ proc ZstdDecoderInternalInst { rle_req_s: chan out, rle_resp_r: chan in, + // Output MemWriter + output_mem_wr_req_s: chan out, + output_mem_wr_resp_r: chan in, + // IRQ notify_s: chan<()> out, reset_s: chan<()> out, @@ -1145,6 +1219,7 @@ proc ZstdDecoderInternalInst { bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ); @@ -1195,6 +1270,11 @@ proc ZstdDecoderInst { raw_axi_ar_s: chan out, raw_axi_r_r: chan in, + //// AXI Output Writer (manager) + output_axi_aw_s: chan out, + output_axi_w_s: chan out, + output_axi_b_r: chan in, + // History Buffer ram_rd_req_0_s: chan out, ram_rd_req_1_s: chan out, @@ -1243,6 +1323,7 @@ proc ZstdDecoderInst { fh_axi_ar_s, fh_axi_r_r, bh_axi_ar_s, bh_axi_r_r, raw_axi_ar_s, raw_axi_r_r, + output_axi_aw_s, output_axi_w_s, output_axi_b_r, ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, ram_rd_resp_0_r, ram_rd_resp_1_r, ram_rd_resp_2_r, ram_rd_resp_3_r, diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index a166e1743d..a57f7e499e 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -53,6 +53,8 @@ const TEST_RAM_BASE_ADDR:u32 = u32:0; const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; const TEST_RAM_INITIALIZED = true; +const TEST_MOCK_OUTPUT_RAM_SIZE:u32 = TEST_RAM_SIZE / TEST_AXI_DATA_W_DIV8; + fn csr_addr(c: zstd_dec::Csr) -> uN[TEST_AXI_ADDR_W] { (c as uN[TEST_AXI_ADDR_W]) << 3 } @@ -64,19 +66,19 @@ proc ZstdDecoderTest { type CsrAxiAw = axi::AxiAw; type CsrAxiW = axi::AxiW; type CsrAxiB = axi::AxiB; - + type CsrRdReq = csr_config::CsrRdReq; type CsrRdResp = csr_config::CsrRdResp; type CsrWrReq = csr_config::CsrWrReq; type CsrWrResp = csr_config::CsrWrResp; type CsrChange = csr_config::CsrChange; - + type MemAxiAr = axi::AxiAr; type MemAxiR = axi::AxiR; type MemAxiAw = axi::AxiAw; type MemAxiW = axi::AxiW; type MemAxiB = axi::AxiB; - + type RamRdReqHB = ram::ReadReq; type RamRdRespHB = ram::ReadResp; type RamWrReqHB = ram::WriteReq; @@ -86,7 +88,7 @@ proc ZstdDecoderTest { type RamRdResp = ram::ReadResp; type RamWrReq = ram::WriteReq; type RamWrResp = ram::WriteResp; - + type ZstdDecodedPacket = common::ZstdDecodedPacket; terminator: chan out; csr_axi_aw_s: chan out; @@ -100,6 +102,9 @@ proc ZstdDecoderTest { bh_axi_r_s: chan out; raw_axi_ar_r: chan in; raw_axi_r_s: chan out; + output_axi_aw_r: chan in; + output_axi_w_r: chan in; + output_axi_b_s: chan out; ram_rd_req_r: chan[8] in; ram_rd_resp_s: chan[8] out; @@ -116,31 +121,35 @@ proc ZstdDecoderTest { output_r: chan in; notify_r: chan<()> in; reset_r: chan<()> in; - + init {} - + config(terminator: chan out) { - + let (csr_axi_aw_s, csr_axi_aw_r) = chan("csr_axi_aw"); let (csr_axi_w_s, csr_axi_w_r) = chan("csr_axi_w"); let (csr_axi_b_s, csr_axi_b_r) = chan("csr_axi_b"); let (csr_axi_ar_s, csr_axi_ar_r) = chan("csr_axi_ar"); let (csr_axi_r_s, csr_axi_r_r) = chan("csr_axi_r"); - + let (fh_axi_ar_s, fh_axi_ar_r) = chan("fh_axi_ar"); let (fh_axi_r_s, fh_axi_r_r) = chan("fh_axi_r"); - + let (bh_axi_ar_s, bh_axi_ar_r) = chan("bh_axi_ar"); let (bh_axi_r_s, bh_axi_r_r) = chan("bh_axi_r"); - + let (raw_axi_ar_s, raw_axi_ar_r) = chan("raw_axi_ar"); let (raw_axi_r_s, raw_axi_r_r) = chan("raw_axi_r"); + let (output_axi_aw_s, output_axi_aw_r) = chan("output_axi_aw"); + let (output_axi_w_s, output_axi_w_r) = chan("output_axi_w"); + let (output_axi_b_s, output_axi_b_r) = chan("output_axi_b"); + let (ram_rd_req_s, ram_rd_req_r) = chan[8]("ram_rd_req"); let (ram_rd_resp_s, ram_rd_resp_r) = chan[8]("ram_rd_resp"); let (ram_wr_req_s, ram_wr_req_r) = chan[8]("ram_wr_req"); let (ram_wr_resp_s, ram_wr_resp_r) = chan[8]("ram_wr_resp"); - + let (ram_rd_req_fh_s, ram_rd_req_fh_r) = chan("ram_rd_req_fh"); let (ram_rd_req_bh_s, ram_rd_req_bh_r) = chan("ram_rd_req_bh"); let (ram_rd_req_raw_s, ram_rd_req_raw_r) = chan("ram_rd_req_raw"); @@ -158,7 +167,7 @@ proc ZstdDecoderTest { let (output_s, output_r) = chan("output"); let (notify_s, notify_r) = chan<()>("notify"); let (reset_s, reset_r) = chan<()>("reset"); - + spawn zstd_dec::ZstdDecoder< TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, TEST_REGS_N, TEST_WINDOW_LOG_MAX, @@ -168,6 +177,7 @@ proc ZstdDecoderTest { fh_axi_ar_s, fh_axi_r_r, bh_axi_ar_s, bh_axi_r_r, raw_axi_ar_s, raw_axi_r_r, + output_axi_aw_s, output_axi_w_s, output_axi_b_r, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], @@ -178,49 +188,49 @@ proc ZstdDecoderTest { ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7], output_s, notify_s, reset_s, ); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, TEST_HB_RAM_ASSERT_VALID_READ > (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); - + spawn ram::RamModel< TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, @@ -231,7 +241,7 @@ proc ZstdDecoderTest { TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, > (ram_rd_req_fh_r, ram_rd_resp_fh_s, ram_wr_req_fh_r, ram_wr_resp_fh_s); - + spawn ram::RamModel< TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, @@ -263,20 +273,21 @@ proc ZstdDecoderTest { fh_axi_ar_r, fh_axi_r_s, bh_axi_ar_r, bh_axi_r_s, raw_axi_ar_r, raw_axi_r_s, + output_axi_aw_r, output_axi_w_r, output_axi_b_s, ram_rd_req_r, ram_rd_resp_s, ram_wr_req_r, ram_wr_resp_s, ram_wr_req_fh_s, ram_wr_req_bh_s, ram_wr_req_raw_s, ram_wr_resp_fh_r, ram_wr_resp_bh_r, ram_wr_resp_raw_r, output_r, notify_r, reset_r, ) } - + next (state: ()) { trace_fmt!("Test start"); let frames_count = array_size(zstd_frame_testcases::FRAMES); let tok = join(); let tok = unroll_for! (test_i, tok): (u32, token) in range(u32:0, frames_count) { - trace_fmt!("Loading testcase {:x}", test_i); + trace_fmt!("Loading testcase {:x}", test_i + u32:1); let frame = zstd_frame_testcases::FRAMES[test_i]; let tok = for (i, tok): (u32, token) in range(u32:0, frame.array_length) { let req = RamWrReq { @@ -290,7 +301,7 @@ proc ZstdDecoderTest { tok }(tok); - trace_fmt!("Running decoder on testcase {:x}", test_i); + trace_fmt!("Running decoder on testcase {:x}", test_i + u32:1); let addr_req = axi::AxiAw { id: uN[TEST_AXI_ID_W]:0, addr: uN[TEST_AXI_ADDR_W]:0, @@ -357,10 +368,78 @@ proc ZstdDecoderTest { tok }(tok); + // Test ZstdDecoder memory output interface + // Mock the output memory buffer as a DSLX array + // It is required to handle AXI write transactions and to write the incoming data to + // the DSXL array. + // The number of AXI transactions is not known beforehand because it depends on the + // length of the decoded data and the address of the output buffer. The same goes + // with the lengths of the particular AXI burst transactions (the number of transfers). + // Because of that we cannot write for loops to handle AXI transactions dynamically. + // As a workaround, the loops are constrained with upper bounds for AXI transactions + // required for writing maximal supported payload and maximal possible burst transfer + // size. + + // It is possible to decode payloads up to 16kB + // The smallest possible AXI transaction will transfer 1 byte of data + let MAX_AXI_TRANSACTIONS = u32:16384; + // The maximal number if beats in AXI burst transaction + let MAX_AXI_TRANSFERS = u32:256; + // Actual size of decompressed payload for current test + let DECOMPRESSED_BYTES = zstd_frame_testcases::DECOMPRESSED_FRAMES[test_i].length; + trace_fmt!("ZstdDecTest: Start receiving output"); + let (tok, final_output_memory, final_output_memory_id, final_transfered_bytes) = + for (axi_transaction, (tok, output_memory, output_memory_id, transfered_bytes)): + (u32, (token, uN[TEST_AXI_DATA_W][TEST_MOCK_OUTPUT_RAM_SIZE], u32, u32)) + in range(u32:0, MAX_AXI_TRANSACTIONS) { + if (transfered_bytes < DECOMPRESSED_BYTES) { + trace_fmt!("ZstdDecTest: Handle AXI Write transaction #{}", axi_transaction); + let (tok, axi_aw) = recv(tok, output_axi_aw_r); + trace_fmt!("ZstdDecTest: Received AXI AW: {:#x}", axi_aw); + let (tok, internal_output_memory, internal_output_memory_id, internal_transfered_bytes) = + for (axi_transfer, (tok, out_mem, out_mem_id, transf_bytes)): + (u32, (token, uN[TEST_AXI_DATA_W][TEST_MOCK_OUTPUT_RAM_SIZE], u32, u32)) + in range(u32:0, MAX_AXI_TRANSFERS) { + if (axi_transfer as u8 <= axi_aw.len) { + // Receive AXI burst beat transfers + let (tok, axi_w) = recv(tok, output_axi_w_r); + trace_fmt!("ZstdDecTest: Received AXI W #{}: {:#x}", axi_transfer, axi_w); + let strobe_cnt = std::popcount(axi_w.strb) as u32; + // Assume continuous strobe, e.g.: 0b1111; 0b0111; 0b0011; 0b0001; 0b0000 + let strobe_mask = (uN[TEST_AXI_DATA_W]:1 << (strobe_cnt * u32:8) as uN[TEST_AXI_DATA_W]) - uN[TEST_AXI_DATA_W]:1; + let strobed_data = axi_w.data & strobe_mask; + trace_fmt!("ZstdDecTest: write out_mem[{}] = {:#x}", out_mem_id, strobed_data); + let mem = update(out_mem, out_mem_id, (out_mem[out_mem_id] & !strobe_mask) | strobed_data); + let id = out_mem_id + u32:1; + let bytes_written = transf_bytes + strobe_cnt; + trace_fmt!("ZstdDecTest: bytes written: {}", bytes_written); + (tok, mem, id, bytes_written) + } else { + (tok, out_mem, out_mem_id, transf_bytes) + } + // Pass outer loop accumulator as initial accumulator for inner loop + }((tok, output_memory, output_memory_id, transfered_bytes)); + let axi_b = axi::AxiB{resp: axi::AxiWriteResp::OKAY, id: axi_aw.id}; + let tok = send(tok, output_axi_b_s, axi_b); + trace_fmt!("ZstdDecTest: Sent AXI B #{}: {:#x}", axi_transaction, axi_b); + (tok, internal_output_memory, internal_output_memory_id, internal_transfered_bytes) + } else { + (tok, output_memory, output_memory_id, transfered_bytes) + } + }((tok, uN[TEST_AXI_DATA_W][TEST_MOCK_OUTPUT_RAM_SIZE]:[uN[TEST_AXI_DATA_W]:0, ...], u32:0, u32:0)); + trace_fmt!("ZstdDecTest: Finished receiving output"); + + assert_eq(final_transfered_bytes, DECOMPRESSED_BYTES); + assert_eq(final_output_memory_id, decomp_frame.array_length); + for (memory_id, _): (u32, ()) in range(u32:0, decomp_frame.array_length) { + assert_eq(final_output_memory[memory_id], decomp_frame.data[memory_id]); + }(()); + let (tok, ()) = recv(tok, notify_r); - trace_fmt!("Finished decoding testcase {:x} correctly", test_i); + trace_fmt!("Finished decoding testcase {:x} correctly", test_i + u32:1); tok }(tok); + send(tok, terminator, true); } } From 63372d4cc0c8e732afe6739c49a07b115bffb656 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 12 May 2025 19:57:48 +0200 Subject: [PATCH 27/85] modules/zstd/zstd_dec: Remove stream-based output interface * Remove Repacketizer proc * Remove stream-based output channels from * SequenceExecutor * ZstdDecoder Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 1 - xls/modules/zstd/repacketizer.x | 215 --------------------------- xls/modules/zstd/sequence_executor.x | 124 +++++++-------- xls/modules/zstd/zstd_dec.x | 25 ++-- xls/modules/zstd/zstd_dec_test.x | 13 +- 5 files changed, 67 insertions(+), 311 deletions(-) delete mode 100644 xls/modules/zstd/repacketizer.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 77c0270bd9..355afd913d 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -872,7 +872,6 @@ zstd_dec_deps = [ ":dec_mux_dslx", ":frame_header_dec_dslx", ":raw_block_dec_dslx", - ":repacketizer_dslx", ":rle_block_dec_dslx", ":sequence_executor_dslx", "//xls/examples:ram_dslx", diff --git a/xls/modules/zstd/repacketizer.x b/xls/modules/zstd/repacketizer.x deleted file mode 100644 index f2abd638d1..0000000000 --- a/xls/modules/zstd/repacketizer.x +++ /dev/null @@ -1,215 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Repacketizer -// -// Remove invalid bytes from input packets, -// form new packets with all bits valid if possible. - -import std; -import xls.modules.zstd.common as common; - -type ZstdDecodedPacket = common::ZstdDecodedPacket; -type BlockData = common::BlockData; -type BlockPacketLength = common::BlockPacketLength; - -const DATA_WIDTH = common::DATA_WIDTH; - -struct RepacketizerState { - repacked_data: BlockData, - valid_length: BlockPacketLength, - to_fill: BlockPacketLength, - send_last_leftover: bool -} - -const ZERO_ZSTD_DECODED_PACKET = zero!(); -const ZERO_REPACKETIZER_STATE = zero!(); -const INIT_REPACKETIZER_STATE = RepacketizerState {to_fill: DATA_WIDTH, ..ZERO_REPACKETIZER_STATE}; - -pub proc Repacketizer { - input_r: chan in; - output_s: chan out; - - init {(INIT_REPACKETIZER_STATE)} - - config ( - input_r: chan in, - output_s: chan out, - ) { - (input_r, output_s) - } - - next (state: RepacketizerState) { - let tok = join(); - // Don't receive if we process leftovers - let (tok, decoded_packet) = recv_if(tok, input_r, !state.send_last_leftover, ZERO_ZSTD_DECODED_PACKET); - - // Will be able to send repacketized packet in current next() evaluation - let send_now = state.to_fill <= decoded_packet.length || decoded_packet.last || state.send_last_leftover; - // Received last packet in frame which won't fit into currently processed repacketized packet. - // Set flag indicating that Repacketizer will send another packet to finish the frame in - // next evaluation. - let next_send_last_leftover = decoded_packet.last && state.to_fill < decoded_packet.length; - - let combined_length = state.valid_length + decoded_packet.length; - let leftover_length = (combined_length - DATA_WIDTH) as s32; - let next_valid_length = if leftover_length >= s32:0 {leftover_length as BlockPacketLength} else {combined_length}; - let next_to_fill = DATA_WIDTH - next_valid_length; - - let current_valid_length = if leftover_length >= s32:0 {DATA_WIDTH} else {combined_length}; - let bits_to_take_length = if leftover_length >= s32:0 {state.to_fill} else {decoded_packet.length}; - - // Append lest signifiant bits of received packet to most significant positions of repacked data buffer - let masked_data = ((BlockData:1 << bits_to_take_length) - BlockData:1) & decoded_packet.data; - let repacked_data = state.repacked_data | (masked_data << state.valid_length); - - // Prepare buffer state for the next evaluation - take leftover most significant bits of - // received packet - let leftover_mask = (BlockData:1 << (decoded_packet.length - bits_to_take_length)) - BlockData:1; - let leftover_masked_data = (decoded_packet.data >> bits_to_take_length) & leftover_mask; - let next_repacked_data = if (send_now) {leftover_masked_data} else {repacked_data}; - - let packet_to_send = ZstdDecodedPacket { - data: repacked_data, - length: current_valid_length, - last: state.send_last_leftover || (decoded_packet.last && !next_send_last_leftover), - }; - let tok = send_if(tok, output_s, send_now, packet_to_send); - - let next_state = if (state.send_last_leftover || (decoded_packet.last && !next_send_last_leftover)) { - INIT_REPACKETIZER_STATE - } else { - RepacketizerState { - repacked_data: next_repacked_data, - valid_length: next_valid_length, - to_fill: next_to_fill, - send_last_leftover: next_send_last_leftover, - } - }; - - trace_fmt!("Repacketizer: state: {:#x}", state); - if (!state.send_last_leftover) { - trace_fmt!("Repacketizer: Received packet: {:#x}", decoded_packet); - } else {}; - trace_fmt!("Repacketizer: send_now: {}", send_now); - trace_fmt!("Repacketizer: next_send_last_leftover: {}", next_send_last_leftover); - trace_fmt!("Repacketizer: combined_length: {}", combined_length); - trace_fmt!("Repacketizer: leftover_length: {}", leftover_length); - trace_fmt!("Repacketizer: next_valid_length: {}", next_valid_length); - trace_fmt!("Repacketizer: next_to_fill: {}", next_to_fill); - trace_fmt!("Repacketizer: current_valid_length: {}", current_valid_length); - trace_fmt!("Repacketizer: bits_to_take_length: {}", bits_to_take_length); - trace_fmt!("Repacketizer: masked_data: {:#x}", masked_data); - trace_fmt!("Repacketizer: repacked_data: {:#x}", repacked_data); - trace_fmt!("Repacketizer: leftover_mask: {:#x}", leftover_mask); - trace_fmt!("Repacketizer: leftover_masked_data: {:#x}", leftover_masked_data); - trace_fmt!("Repacketizer: next_repacked_data: {:#x}", next_repacked_data); - if (send_now) { - trace_fmt!("Repacketizer: Sent repacketized packet: {:#x}", packet_to_send); - } else {}; - trace_fmt!("Repacketizer: next_state: {:#x}", next_state); - - next_state - } -} - -#[test_proc] -proc RepacketizerTest { - terminator: chan out; - input_s: chan out; - output_r: chan in; - - init {} - - config (terminator: chan out) { - let (input_s, input_r) = chan("input"); - let (output_s, output_r) = chan("output"); - - spawn Repacketizer(input_r, output_s); - (terminator, input_s, output_r) - } - - next(state: ()) { - let tok = join(); - let DecodedInputs: ZstdDecodedPacket[24] = [ - // Full packet - no need for removing alignment zeros - ZstdDecodedPacket {data: BlockData:0xDEADBEEF12345678, length: BlockPacketLength:64, last:false}, - // Data in 4 packets - should be batched together into one full output packet - ZstdDecodedPacket {data: BlockData:0x78, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x56, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x1234, length: BlockPacketLength:16, last:false}, - ZstdDecodedPacket {data: BlockData:0xDEADBEEF, length: BlockPacketLength:32, last:false}, - // Small last packet - should be send out separatelly - ZstdDecodedPacket {data: BlockData:0x9A, length: BlockPacketLength:8, last:true}, - // One not-full packet and consecutive last packet packet in frame which completes previous packet and - // starts new one which should be marked as last - ZstdDecodedPacket {data: BlockData:0xADBEEF12345678, length: BlockPacketLength:56, last:false}, - ZstdDecodedPacket {data: BlockData:0x9ADE, length: BlockPacketLength:16, last:true}, - // 8 1-byte packets forming single output packet - ZstdDecodedPacket {data: BlockData:0xEF, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0xCD, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0xAB, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x89, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x67, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x45, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x23, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x01, length: BlockPacketLength:8, last:false}, - // 7 1-byte packets and 1 8-byte packet forming 1 full and 1 7-byte output packet - // marked as last - ZstdDecodedPacket {data: BlockData:0xEF, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0xCD, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0xAB, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x89, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x67, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x45, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0x23, length: BlockPacketLength:8, last:false}, - ZstdDecodedPacket {data: BlockData:0xFEDCBA9876543201, length: BlockPacketLength:64, last:true}, - ]; - - let DecodedOutputs: ZstdDecodedPacket[8] = [ - // Full packet - no need for removing alignment zeros - ZstdDecodedPacket {data: BlockData:0xDEADBEEF12345678, length: BlockPacketLength:64, last:false}, - // Data in 4 packets - should be batched together into one full output packet - ZstdDecodedPacket {data: BlockData:0xDEADBEEF12345678, length: BlockPacketLength:64, last:false}, - // Small last packet - should be send out separatelly - ZstdDecodedPacket {data: BlockData:0x9A, length: BlockPacketLength:8, last:true}, - // One not-full packet and consecutive last packet packet in frame which completes previous packet and - // starts new one which should be marked as last - ZstdDecodedPacket {data: BlockData:0xDEADBEEF12345678, length: BlockPacketLength:64, last:false}, - ZstdDecodedPacket {data: BlockData:0x9A, length: BlockPacketLength:8, last:true}, - // 8 1-byte packets forming single output packet - ZstdDecodedPacket {data: BlockData:0x0123456789ABCDEF, length: BlockPacketLength:64, last:false}, - // 7 1-byte packets and 1 8-byte packet forming 1 full and 1 7-byte output packet - // marked as last - ZstdDecodedPacket {data: BlockData:0x0123456789ABCDEF, length: BlockPacketLength:64, last:false}, - ZstdDecodedPacket {data: BlockData:0xFEDCBA98765432, length: BlockPacketLength:56, last:true}, - ]; - - let tok = for ((counter, decoded_input), tok): ((u32, ZstdDecodedPacket), token) in enumerate(DecodedInputs) { - let tok = send(tok, input_s, decoded_input); - trace_fmt!("Sent #{} decoded zero-filled packet, {:#x}", counter + u32:1, decoded_input); - (tok) - } (tok); - - let tok = for ((counter, expected_output), tok): ((u32, ZstdDecodedPacket), token) in enumerate(DecodedOutputs) { - let (tok, decoded_output) = recv(tok, output_r); - trace_fmt!("Received #{} decoded non-zero-filled packet, {:#x}", counter + u32:1, decoded_output); - trace_fmt!("Expected #{} decoded non-zero-filled packet, {:#x}", counter + u32:1, expected_output); - assert_eq(decoded_output, expected_output); - (tok) - } (tok); - - send(tok, terminator, true); - } -} diff --git a/xls/modules/zstd/sequence_executor.x b/xls/modules/zstd/sequence_executor.x index d87bfc1bd6..b46180a307 100644 --- a/xls/modules/zstd/sequence_executor.x +++ b/xls/modules/zstd/sequence_executor.x @@ -851,7 +851,6 @@ pub proc SequenceExecutor; input_r: chan in; - output_s: chan out; output_mem_wr_data_in_s: chan out; ram_comp_input_s: chan> out; ram_comp_output_r: chan> in; @@ -876,7 +875,6 @@ pub proc SequenceExecutor in, - output_s: chan out, output_mem_wr_data_in_s: chan out, ram_resp_output_r: chan in, ram_resp_output_s: chan out, @@ -928,7 +926,7 @@ pub proc SequenceExecutor(output_data); + let output_mem_wr_data_in = convert_output_packet(decode_literal_packet(packet)); + if do_write_output { trace_fmt!("Sending output MemWriter data: {:#x}", output_mem_wr_data_in); } else { }; let tok2_10_1 = send_if(tok1, output_mem_wr_data_in_s, do_write_output, output_mem_wr_data_in); // Ask for response @@ -1192,7 +1188,6 @@ pub proc SequenceExecutorZstd { config( input_r: chan in, - output_s: chan out, output_mem_wr_data_in_s: chan out, looped_channel_r: chan in, looped_channel_s: chan out, @@ -1231,7 +1226,7 @@ pub proc SequenceExecutorZstd { ) { spawn SequenceExecutor ( - input_r, output_s, output_mem_wr_data_in_s, + input_r, output_mem_wr_data_in_s, looped_channel_r, looped_channel_s, rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, @@ -1347,7 +1342,6 @@ proc SequenceExecutorLiteralsTest { terminator: chan out; input_s: chan> out; - output_r: chan in; output_mem_wr_data_in_r: chan in; print_start_s: chan<()> out; @@ -1360,7 +1354,6 @@ proc SequenceExecutorLiteralsTest { config(terminator: chan out) { let (input_s, input_r) = chan>("input"); - let (output_s, output_r) = chan("output"); let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); let (looped_channel_s, looped_channel_r) = chan("looped_channels"); @@ -1381,7 +1374,7 @@ proc SequenceExecutorLiteralsTest { TEST_RAM_ADDR_WIDTH, INIT_HB_PTR_ADDR, > ( - input_r, output_s, output_mem_wr_data_in_s, + input_r, output_mem_wr_data_in_s, looped_channel_r, looped_channel_s, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], @@ -1433,7 +1426,7 @@ proc SequenceExecutorLiteralsTest { ( terminator, - input_s, output_r, output_mem_wr_data_in_r, + input_s, output_mem_wr_data_in_r, print_start_s, print_finish_r, ram_rd_req_s, ram_rd_resp_r, ram_wr_req_s, ram_wr_resp_r @@ -1450,11 +1443,9 @@ proc SequenceExecutorLiteralsTest { if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || LITERAL_TEST_INPUT_DATA[i].last) { - let (tok, recv_data) = recv(tok, output_r); let expected = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); - assert_eq(expected, recv_data); - let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); let expected_mem_writer_data = convert_output_packet(expected); + let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(expected_mem_writer_data, recv_mem_writer_data); } else {} }(()); @@ -1546,60 +1537,61 @@ const SEQUENCE_TEST_INPUT_SEQUENCES = SequenceExecutorPacket[11]: [ }, ]; -const SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS:ZstdDecodedPacket[11] = [ - ZstdDecodedPacket { - data: BlockData:0x8C_7E_B8_B9_7C_A3_9D_AF, - length: BlockPacketLength:64, +type TestMemWriterDataPacket = mem_writer::MemWriterDataPacket; +const SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS:TestMemWriterDataPacket[11] = [ + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x8C_7E_B8_B9_7C_A3_9D_AF, + length: uN[TEST_ADDR_W]:8, last: false }, - ZstdDecodedPacket { - data: BlockData:0x7D, - length: BlockPacketLength:8, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x7D, + length: uN[TEST_ADDR_W]:1, last: false }, - ZstdDecodedPacket { - data: BlockData:0xB8, - length: BlockPacketLength:8, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0xB8, + length: uN[TEST_ADDR_W]:1, last: false }, - ZstdDecodedPacket { - data: BlockData:0xB8, - length: BlockPacketLength:8, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0xB8, + length: uN[TEST_ADDR_W]:1, last: false }, - ZstdDecodedPacket { - data: BlockData:0xB8_B9_7C_A3_9D, - length: BlockPacketLength:40, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0xB8_B9_7C_A3_9D, + length: uN[TEST_ADDR_W]:5, last: false }, - ZstdDecodedPacket { - data: BlockData:0xB9_7C_A3, - length: BlockPacketLength:24, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0xB9_7C_A3, + length: uN[TEST_ADDR_W]:3, last: false }, - ZstdDecodedPacket { - data: BlockData:0xB8, - length: BlockPacketLength:8, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0xB8, + length: uN[TEST_ADDR_W]:1, last: false }, - ZstdDecodedPacket { - data: BlockData:0x7C, - length: BlockPacketLength:8, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x7C, + length: uN[TEST_ADDR_W]:1, last: false }, - ZstdDecodedPacket { - data: BlockData:0xB9_7C_A3_B8_B9_7C_A3_9D, - length: BlockPacketLength:64, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0xB9_7C_A3_B8_B9_7C_A3_9D, + length: uN[TEST_ADDR_W]:8, last: false }, - ZstdDecodedPacket { - data: BlockData:0x7C_B8, - length: BlockPacketLength:16, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x7C_B8, + length: uN[TEST_ADDR_W]:2, last: true }, - ZstdDecodedPacket { - data: BlockData:0x9D, - length: BlockPacketLength:8, + TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x9D, + length: uN[TEST_ADDR_W]:1, last: false } ]; @@ -1610,7 +1602,6 @@ proc SequenceExecutorSequenceTest { terminator: chan out; input_s: chan out; - output_r: chan in; output_mem_wr_data_in_r: chan in; print_start_s: chan<()> out; @@ -1623,7 +1614,6 @@ proc SequenceExecutorSequenceTest { config(terminator: chan out) { let (input_s, input_r) = chan("input"); - let (output_s, output_r) = chan("output"); let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); let (looped_channel_s, looped_channel_r) = chan("looped_channel"); @@ -1644,7 +1634,7 @@ proc SequenceExecutorSequenceTest { TEST_RAM_ADDR_WIDTH, INIT_HB_PTR_ADDR, > ( - input_r, output_s, output_mem_wr_data_in_s, + input_r, output_mem_wr_data_in_s, looped_channel_r, looped_channel_s, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], @@ -1696,7 +1686,7 @@ proc SequenceExecutorSequenceTest { ( terminator, - input_s, output_r, output_mem_wr_data_in_r, + input_s, output_mem_wr_data_in_r, print_start_s, print_finish_r, ram_rd_req_s, ram_rd_resp_r, ram_wr_req_s, ram_wr_resp_r ) @@ -1712,11 +1702,9 @@ proc SequenceExecutorSequenceTest { if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || LITERAL_TEST_INPUT_DATA[i].last) { - let (tok, recv_data) = recv(tok, output_r); let expected = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); - assert_eq(expected, recv_data); - let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); let expected_mem_writer_data = convert_output_packet(expected); + let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(expected_mem_writer_data, recv_mem_writer_data); } else {} }(()); @@ -1726,45 +1714,45 @@ proc SequenceExecutorSequenceTest { let (tok, _) = recv(tok, print_finish_r); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[0]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[0], recv_data); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[1], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[1]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[2], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[2]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[3], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[3]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[4], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[4]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[5], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[5]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[6], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[6]); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[7]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[7], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[8]); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[9]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[8], recv_data); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[9], recv_data); let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[10]); - let (tok, recv_data) = recv(tok, output_r); + let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[10], recv_data); // Print RAM content diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index 7fc5fb260e..a5f5460905 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -31,7 +31,6 @@ import xls.modules.zstd.raw_block_dec; import xls.modules.zstd.rle_block_dec; import xls.modules.zstd.dec_mux; import xls.modules.zstd.sequence_executor; -import xls.modules.zstd.repacketizer; type BlockSize = common::BlockSize; type BlockType = common::BlockType; @@ -846,11 +845,15 @@ proc ZstdDecoderInternalTest { status: RawBlockDecoderStatus::OKAY, }); - let (tok, ()) = recv(tok, notify_r); - - let (tok, _) = recv(tok, output_mem_wr_req_r); + let (tok, mem_wr_req) = recv(tok, output_mem_wr_req_r); + assert_eq(mem_wr_req, MemWriterReq { + addr: uN[TEST_AXI_ADDR_W]:0x2000, + length: uN[TEST_AXI_ADDR_W]:200 + }); let tok = send(tok, output_mem_wr_resp_s, MemWriterResp {status: mem_writer::MemWriterRespStatus::OKAY}); + let (tok, ()) = recv(tok, notify_r); + send(tok, terminator, true); } } @@ -977,8 +980,6 @@ pub proc ZstdDecoder< ram_wr_resp_6_r: chan in, ram_wr_resp_7_r: chan in, - // Decoder output - output_s: chan out, notify_s: chan<()> out, reset_s: chan<()> out, ) { @@ -1090,12 +1091,10 @@ pub proc ZstdDecoder< // Sequence Execution let (seq_exec_looped_s, seq_exec_looped_r) = chan("seq_exec_looped"); - let (seq_exec_output_s, seq_exec_output_r) = chan("seq_exec_output"); let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); spawn sequence_executor::SequenceExecutor( - seq_exec_input_r, seq_exec_output_s, - output_mem_wr_data_in_s, + seq_exec_input_r, output_mem_wr_data_in_s, seq_exec_looped_r, seq_exec_looped_s, ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, @@ -1107,10 +1106,6 @@ pub proc ZstdDecoder< ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r ); - // Repacketizer - - spawn repacketizer::Repacketizer(seq_exec_output_r, output_s); - // Zstd Decoder Control let (output_mem_wr_req_s, output_mem_wr_req_r) = chan("output_mem_wr_req"); let (output_mem_wr_resp_s, output_mem_wr_resp_r) = chan("output_mem_wr_resp"); @@ -1309,8 +1304,6 @@ proc ZstdDecoderInst { ram_wr_resp_6_r: chan in, ram_wr_resp_7_r: chan in, - // Decoder output - output_s: chan out, notify_s: chan<()> out, reset_s: chan<()> out, ) { @@ -1332,7 +1325,7 @@ proc ZstdDecoderInst { ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, - output_s, notify_s, reset_s, + notify_s, reset_s, ); } diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index a57f7e499e..bd90210ef1 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -118,7 +118,6 @@ proc ZstdDecoderTest { raw_wr_resp_bh_r: chan in; raw_wr_resp_raw_r: chan in; - output_r: chan in; notify_r: chan<()> in; reset_r: chan<()> in; @@ -164,7 +163,6 @@ proc ZstdDecoderTest { let (ram_wr_resp_bh_s, ram_wr_resp_bh_r) = chan("ram_wr_resp_bh"); let (ram_wr_resp_raw_s, ram_wr_resp_raw_r) = chan("ram_wr_resp_raw"); - let (output_s, output_r) = chan("output"); let (notify_s, notify_r) = chan<()>("notify"); let (reset_s, reset_r) = chan<()>("reset"); @@ -186,7 +184,7 @@ proc ZstdDecoderTest { ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7], - output_s, notify_s, reset_s, + notify_s, reset_s, ); spawn ram::RamModel< @@ -277,7 +275,7 @@ proc ZstdDecoderTest { ram_rd_req_r, ram_rd_resp_s, ram_wr_req_r, ram_wr_resp_s, ram_wr_req_fh_s, ram_wr_req_bh_s, ram_wr_req_raw_s, ram_wr_resp_fh_r, ram_wr_resp_bh_r, ram_wr_resp_raw_r, - output_r, notify_r, reset_r, + notify_r, reset_r, ) } @@ -361,13 +359,6 @@ proc ZstdDecoderTest { let (tok, _) = recv(tok, csr_axi_b_r); let decomp_frame = zstd_frame_testcases::DECOMPRESSED_FRAMES[test_i]; - let tok = for (decomp_i, tok): (u32, token) in range(u32:0, decomp_frame.array_length) { - let (tok, decomp_packet) = recv(tok, output_r); - assert_eq(decomp_packet.data, decomp_frame.data[decomp_i]); - assert_eq(decomp_packet.last, decomp_i == (decomp_frame.length - u32:1) / u32:8); - tok - }(tok); - // Test ZstdDecoder memory output interface // Mock the output memory buffer as a DSLX array // It is required to handle AXI write transactions and to write the incoming data to From d9bb1015381c3da979c22c344803227579b9fc17 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 19 Nov 2024 12:31:15 +0100 Subject: [PATCH 28/85] modules/zstd/README: Update output interface description Internal-tag: [#67272] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/README.md | 43 ++++++++---------- xls/modules/zstd/img/ZSTD_decoder.png | Bin 315264 -> 312837 bytes xls/modules/zstd/img/ZSTD_decoder_wrapper.png | Bin 126231 -> 123219 bytes 3 files changed, 19 insertions(+), 24 deletions(-) diff --git a/xls/modules/zstd/README.md b/xls/modules/zstd/README.md index e606a02918..0842d65c49 100644 --- a/xls/modules/zstd/README.md +++ b/xls/modules/zstd/README.md @@ -5,19 +5,17 @@ It implements the [RFC 8878](https://www.rfc-editor.org/rfc/rfc8878.html) decomp An overview of the decoder architecture is presented in the diagram below. The decoder comprises: * Memory Readers -* Memory Writer[^2], +* Memory Writer, * Control and Status Registers, * Frame Header Decoder, * Block Header Decoder, * 3 types of processing units: RAW-, RLE-, and Compressed Block Decoders[^1], * Command Aggregator, -* Repacketizer. The Decoder interacts with the environment through a set of ports: * Memory Interface (AXI) * CSR Interface (AXI) * Notify line -* Stream Output The software controls the core through registers accessible through the `CSR Interface`. The CSRs are used to configure the decoder and to start the decoding process. @@ -33,8 +31,8 @@ Once the decoding process is started, the decoder: 4. Decodes the Block Data with the correct processing unit picked based on the Block Type from the Block Header, 4. Aggregates the processing unit results in the correct order into a stream and routes it to the history buffer, 5. Assembles the data block outputs based on the history buffer contents and updates the history, -6. Prepares the final output of the decoder, -7. (Optional) Calculates checksum and compares it against the checksum read from the frame.[^3] +6. Prepares the final output of the decoder and writes it to the memory, +7. (Optional) Calculates checksum and compares it against the checksum read from the frame.[^2] ![](img/ZSTD_decoder.png) @@ -115,31 +113,41 @@ stateDiagram [*] --> IDLE IDLE --> READ_CONFIG: Start + IDLE --> mem_write_done READ_CONFIG --> DECODE_FRAME_HEADER + READ_CONFIG --> mem_write_done DECODE_FRAME_HEADER --> DECODE_BLOCK_HEADER DECODE_FRAME_HEADER --> ERROR + DECODE_FRAME_HEADER --> mem_write_done DECODE_BLOCK_HEADER --> DECODE_RAW_BLOCK DECODE_BLOCK_HEADER --> DECODE_RLE_BLOCK DECODE_BLOCK_HEADER --> DECODE_COMPRESED_BLOCK DECODE_BLOCK_HEADER --> ERROR + DECODE_BLOCK_HEADER --> mem_write_done state if_block_last <> DECODE_RAW_BLOCK --> ERROR DECODE_RAW_BLOCK --> if_block_last + DECODE_RAW_BLOCK --> mem_write_done DECODE_RLE_BLOCK --> ERROR DECODE_RLE_BLOCK --> if_block_last + DECODE_RLE_BLOCK --> mem_write_done DECODE_COMPRESSED_BLOCK --> ERROR DECODE_COMPRESSED_BLOCK --> if_block_last + DECODE_COMPRESSED_BLOCK --> mem_write_done if_block_last --> DECODE_BLOCK_HEADER: Not last block in the frame if_block_last --> DECODE_CHECKSUM: Last block in the frame - DECODE_CHECKSUM --> FINISH + DECODE_CHECKSUM --> mem_write_done + + state mem_write_done <> + mem_write_done --> FINISH: Frame written to the memory FINISH --> IDLE ERROR --> IDLE @@ -154,9 +162,9 @@ Once received, the module fetches the data from the memory starting from the add `MemReader` procs are used by those modules to communicate with the external memory through the AXI interface. Internal modules decode the acquired parts of the frame and return responses with the results back to the top level proc. -The processing units also output the decoded blocks of data through a stream-based interface to `SequenceExecutor` and further to `Repacketizer` procs. -Those procs perform the last steps of the decoding before the final output is sent out back to the memory under the address stored in the `Output Buffer` CSR or through the stream-based output channel. -Once the decoding process is completed, the decoder sends the `Notify` signal and transitions back to the `IDLE` state. +The processing units also output the decoded blocks of data through a stream-based interface to the `SequenceExecutor` proc. +This proc performs the last step of the decoding before the final output is sent out back to the memory under the address stored in the `Output Buffer` CSR by the `MemWriter` proc. +Once the decoding process is completed and the decoded frame is written back to the memory, the decoder sends the `Notify` signal and transitions back to the `IDLE` state. ### Internal modules @@ -212,19 +220,6 @@ This stage will show the following behavior, depending on the tag: * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the decoder's output, * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the history buffer as the newest. -#### Repacketizer -This proc is used at the end of the processing flow in the ZSTD decoder. -It gathers the output of `SequenceExecutor` proc and processes it to form the final output packets of the ZSTD decoder. -Input packets coming from the `SequenceExecutor` consist of: - -* data - bit vector of constant length -* length - field describing how many bits in bit vector are valid -* last - flag which marks the last packet in currently decoded ZSTD frame. - -It is not guaranteed that all bits in data bit vectors in packets received from `SequenceExecutor` are valid as those can include padding bits that were added in previous decoding steps and now have to be removed. -Repacketizer buffers input packets, removes the padding bits and forms new packets with all bits of the bit vector valid, meaning that all bits are decoded data. -Newly formed packets are then sent out to the output of the whole ZSTD decoder. - ### Compressed block decoder architecture[^1] This part of the design is responsible for processing the compressed blocks up to the `literals`/`copy` command sequence. This sequence is then processed by the history buffer to generate the expected data output. @@ -357,8 +352,8 @@ Currently, due to the restrictions from the ZSTD frame generator, it is possible ZstdDecoder's main communication interfaces are the AXI buses. Due to the way XLS handles the codegen of DSLX channels that model the AXI channels, the particular ports of the AXI channels are not represented correctly. This enforces the introduction of a Verilog wrapper that maps the ports generated by XLS into proper AXI ports (see AXI peripherals [README](memory/README.md) for more information). -Additionally, the wrapper is used to mux multiple AXI interfaces from `Memory Readers` into a single outside-facing AXI interface (`Memory Interface`) that can be connected to the external memory. -The mux is implemented by a third-party [AXI Interconnect](https://github.com/alexforencich/verilog-axi). +Additionally, the wrapper is used to mux multiple AXI interfaces from `Memory Readers` and `Memory Writer` into a single outside-facing AXI interface (`Memory Interface`) that can be connected to the external memory. +The mux is implemented by a third-party [AXI Crossbar](https://github.com/alexforencich/verilog-axi). ![](img/ZSTD_decoder_wrapper.png) diff --git a/xls/modules/zstd/img/ZSTD_decoder.png b/xls/modules/zstd/img/ZSTD_decoder.png index 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From e72ee793f31356d2f72e661123bfb9b5a5fea4f7 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 31 Dec 2024 17:24:34 +0100 Subject: [PATCH 29/85] modules/zstd/memory/axi_stream_remove_empty: add fifo module definition for verilog library Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/BUILD | 1 + 1 file changed, 1 insertion(+) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index 39a111dfe5..e9ab9c0119 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -242,6 +242,7 @@ verilog_library( name = "axi_stream_remove_empty_verilog_lib", srcs = [ ":axi_stream_remove_empty.v", + "//xls/modules/zstd:xls_fifo_wrapper.v", ], tags = ["manual"], ) From f8a83dab36cc8c8cd6885b2d145be30a85942b43 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 13 Jan 2025 13:39:49 +0100 Subject: [PATCH 30/85] modules/zstd/zstd_dec: use regular cast instead of checked_cast on status enums Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/zstd_dec.x | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index a5f5460905..7bbd356cf4 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -351,7 +351,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = true; let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(status), + value: status as Data, }; State { fsm: Fsm::READ_CONFIG, csr_wr_req, csr_wr_req_valid, conf_cnt: CSR_REQS_MAX, ..zero!() } @@ -382,7 +382,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = all_collected; let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(status), + value: status as Data, }; State { @@ -405,7 +405,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = (fh_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(status), + value: status as Data, }; let fsm = match (fh_resp_valid, error) { @@ -433,7 +433,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = (bh_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(status), + value: status as Data, }; let fsm = match (bh_resp_valid, error, bh_resp.header.btype) { @@ -484,7 +484,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = (raw_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(status), + value: status as Data, }; let fsm = match (raw_resp_valid, error, state.block_last) { @@ -517,7 +517,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = (rle_resp_valid); let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(status), + value: status as Data, }; let fsm = match (rle_resp_valid, error, state.block_last) { @@ -566,7 +566,7 @@ proc ZstdDecoderInternal< let csr_wr_req_valid = true; let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), - value: checked_cast(ZstdDecoderStatus::IDLE), + value: ZstdDecoderStatus::IDLE as Data, }; State { fsm: Fsm::IDLE, csr_wr_req, csr_wr_req_valid, ..zero!() } From c2471c099b6340c4ed3132e9b1a0232b8ba642b3 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Thu, 28 Nov 2024 11:51:03 +0100 Subject: [PATCH 31/85] modules/zstd: express data length in bytes Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/dec_mux.x | 144 +++++++++++++++---------------- xls/modules/zstd/raw_block_dec.x | 8 +- xls/modules/zstd/rle_block_dec.x | 12 +-- 3 files changed, 82 insertions(+), 82 deletions(-) diff --git a/xls/modules/zstd/dec_mux.x b/xls/modules/zstd/dec_mux.x index 429a908c44..ef24e9b542 100644 --- a/xls/modules/zstd/dec_mux.x +++ b/xls/modules/zstd/dec_mux.x @@ -234,19 +234,19 @@ proc DecoderMuxTest { next(state: ()) { let tok = join(); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:32 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:32 }}); - let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: true, data: BlockData:0x00000000, length: BlockPacketLength:32 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:32 }}); - - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:32 }); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:4 }}); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:4 }}); + let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: true, data: BlockData:0x00000000, length: BlockPacketLength:4 }}); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:4 }}); + + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:4 }); send(tok, terminator, true); } @@ -274,16 +274,16 @@ proc DecoderMuxEmptyRawBlocksTest { next(state: ()) { let tok = join(); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:4 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:4 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:4, last: bool: true, last_block: bool: true, data: BlockData:0x0, length: BlockPacketLength:0 }}); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); send(tok, terminator, true); @@ -312,16 +312,16 @@ proc DecoderMuxEmptyRleBlocksTest { next(state: ()) { let tok = join(); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:4 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:4 }}); let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:4, last: bool: true, last_block: bool: true, data: BlockData:0x0, length: BlockPacketLength:0 }}); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); send(tok, terminator, true); @@ -350,21 +350,21 @@ proc DecoderMuxEmptyBlockBetweenRegularBlocksOnTheSameInputChannelTest { next(state: ()) { let tok = join(); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:4 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: true, data: BlockData:0x00000000, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: true, data: BlockData:0x00000000, length: BlockPacketLength:4 }}); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:4 }); send(tok, terminator, true); } @@ -392,21 +392,21 @@ proc DecoderMuxEmptyBlockBetweenRegularBlocksOnDifferentInputChannelsTest { next(state: ()) { let tok = join(); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:4 }}); let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:32 }}); - let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: true, data: BlockData:0x00000000, length: BlockPacketLength:32 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:32 }}); - - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:32 }); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:4 }}); + let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: true, data: BlockData:0x00000000, length: BlockPacketLength:4 }}); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:4 }}); + + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:4 }); send(tok, terminator, true); } @@ -435,22 +435,22 @@ proc DecoderMuxMultipleFramesTest { next(state: ()) { let tok = join(); // Frame #1 - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:32 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:32 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:32 }}); - let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0xCCCCCCCC, length: BlockPacketLength:32 }}); - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0xDDDDDDDD, length: BlockPacketLength:32 }}); - let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:4, last: bool: true, last_block: bool: false, data: BlockData:0xEEEEEEEE, length: BlockPacketLength:32 }}); - let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:5, last: bool: true, last_block: bool: true, data: BlockData:0xFFFFFFFF, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x11111111, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: false, last_block: bool: false, data: BlockData:0x22222222, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x33333333, length: BlockPacketLength:4 }}); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: false, last_block: bool: false, data: BlockData:0xAAAAAAAA, length: BlockPacketLength:4 }}); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0xBBBBBBBB, length: BlockPacketLength:4 }}); + let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0xCCCCCCCC, length: BlockPacketLength:4 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0xDDDDDDDD, length: BlockPacketLength:4 }}); + let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:4, last: bool: true, last_block: bool: false, data: BlockData:0xEEEEEEEE, length: BlockPacketLength:4 }}); + let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:5, last: bool: true, last_block: bool: true, data: BlockData:0xFFFFFFFF, length: BlockPacketLength:4 }}); // Frame #2 - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x44444444, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x44444444, length: BlockPacketLength:4 }}); let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); let tok = send(tok, cmp_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); let tok = send(tok, rle_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: true, data: BlockData:0x0, length: BlockPacketLength:0 }}); // Frame #3 - let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x55555555, length: BlockPacketLength:32 }}); + let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:0, last: bool: true, last_block: bool: false, data: BlockData:0x55555555, length: BlockPacketLength:4 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:1, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:2, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:3, last: bool: true, last_block: bool: false, data: BlockData:0x0, length: BlockPacketLength:0 }}); @@ -462,22 +462,22 @@ proc DecoderMuxMultipleFramesTest { let tok = send(tok, raw_s, ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { id: u32:9, last: bool: true, last_block: bool: true, data: BlockData:0x0, length: BlockPacketLength:0 }}); // Frame #1 - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xCCCCCCCC, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDDDDDDDD, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xEEEEEEEE, length: CopyOrMatchLength:32 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xFFFFFFFF, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xCCCCCCCC, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xDDDDDDDD, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xEEEEEEEE, length: CopyOrMatchLength:4 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xFFFFFFFF, length: CopyOrMatchLength:4 }); // Frame #2 - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x44444444, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x44444444, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); // Frame #3 - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x55555555, length: CopyOrMatchLength:32 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x55555555, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); diff --git a/xls/modules/zstd/raw_block_dec.x b/xls/modules/zstd/raw_block_dec.x index 669b66d5b1..3617a41783 100644 --- a/xls/modules/zstd/raw_block_dec.x +++ b/xls/modules/zstd/raw_block_dec.x @@ -116,7 +116,7 @@ pub proc RawBlockDecoder { last_block: state.last_block, id: state.id, data: checked_cast(mem_resp.data), - length: checked_cast(mem_resp.length ++ u3:0), + length: checked_cast(mem_resp.length), }, }; @@ -234,7 +234,7 @@ proc RawBlockDecoderTest { last_block: false, id: u32:0, data: Data:0x1122_3344, - length: Length:64, + length: Length:8, }, }); @@ -269,7 +269,7 @@ proc RawBlockDecoderTest { last_block: true, id: u32:1, data: Data:0x1122_3344_5566_7788, - length: Length:64, + length: Length:8, }, }); @@ -281,7 +281,7 @@ proc RawBlockDecoderTest { last_block: true, id: u32:1, data: Data:0xAA_BBCC_DDEE_FF99, - length: Length:56, + length: Length:7, }, }); diff --git a/xls/modules/zstd/rle_block_dec.x b/xls/modules/zstd/rle_block_dec.x index c5529c978b..4982023fdc 100644 --- a/xls/modules/zstd/rle_block_dec.x +++ b/xls/modules/zstd/rle_block_dec.x @@ -87,7 +87,7 @@ pub proc RleBlockDecoder { last_block: req.last_block, id: req.id, data: checked_cast(data), - length: checked_cast(length << 3), + length: checked_cast(length), } }; @@ -153,7 +153,7 @@ proc RleBlockDecoderTest { last_block: true, id: u32:5, data: BlockData:0xABAB_ABAB_ABAB_ABAB, - length: BlockPacketLength:64 + length: BlockPacketLength:8 } }); @@ -165,7 +165,7 @@ proc RleBlockDecoderTest { last_block: true, id: u32:5, data: BlockData:0xABAB_ABAB_ABAB_ABAB, - length: BlockPacketLength:64 + length: BlockPacketLength:8 } }); @@ -178,7 +178,7 @@ proc RleBlockDecoderTest { last_block: true, id: u32:5, data: BlockData:0xABAB_ABAB_ABAB_ABAB, - length: BlockPacketLength:64 + length: BlockPacketLength:8 } }); @@ -191,7 +191,7 @@ proc RleBlockDecoderTest { last_block: true, id: u32:5, data: BlockData:0xABAB_ABAB_ABAB_ABAB, - length: BlockPacketLength:64 + length: BlockPacketLength:8 } }); @@ -204,7 +204,7 @@ proc RleBlockDecoderTest { last_block: true, id: u32:5, data: BlockData:0xABAB_ABAB_ABAB_ABAB, - length: BlockPacketLength:64 + length: BlockPacketLength:8 } }); From d98bfd844c41017ee1c5b88c0ef135310e101cfd Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 16 May 2024 09:27:40 +0200 Subject: [PATCH 32/85] modules/zstd: Add buffer implementing desired API Add a buffering proc that implements the desired API of the final buffering mechanism. A more efficient implementation will be provided later. Internal-tag: [#55149] Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 72 ++++++++++ xls/modules/zstd/buffer.x | 21 +++ xls/modules/zstd/shift_buffer.x | 246 ++++++++++++++++++++++++++++++++ 3 files changed, 339 insertions(+) create mode 100644 xls/modules/zstd/shift_buffer.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 355afd913d..976a8107c3 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -863,6 +863,78 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "shift_buffer_dslx", + srcs = ["shift_buffer.x"], + deps = [ + ":buffer_dslx", + ], +) + +xls_dslx_test( + name = "shift_buffer_dslx_test", + library = ":shift_buffer_dslx", +) + +xls_dslx_verilog( + name = "shift_buffer_verilog", + codegen_args = { + "module_name": "ShiftBuffer", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferInst", + library = ":shift_buffer_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__shift_buffer__ShiftBufferInst__ShiftBuffer_0__128_64_7_next", + }, + verilog_file = "shift_buffer.v", +) + +xls_benchmark_ir( + name = "shift_buffer_opt_ir_benchmark", + src = ":shift_buffer_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "shift_buffer_verilog_lib", + srcs = [ + ":shift_buffer.v", + ], +) + +synthesize_rtl( + name = "shift_buffer_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBuffer", + deps = [ + ":shift_buffer_verilog_lib", + ], +) + +benchmark_synth( + name = "shift_buffer_benchmark_synth", + synth_target = ":shift_buffer_synth_asap7", +) + +place_and_route( + name = "shift_buffer_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_synth_asap7", + target_die_utilization_percentage = "10", +) + zstd_dec_deps = [ ":axi_csr_accessor_dslx", ":block_header_dec_dslx", diff --git a/xls/modules/zstd/buffer.x b/xls/modules/zstd/buffer.x index d4f9acfa20..218f6f2c8d 100644 --- a/xls/modules/zstd/buffer.x +++ b/xls/modules/zstd/buffer.x @@ -119,6 +119,27 @@ fn test_buffer_append() { assert_eq(buffer, Buffer { content: u32:0xDEADBEEF, length: u32:32 }); } +pub fn buffer_append_with_length (buffer: Buffer, data: bits[CAPACITY], length: u32) -> Buffer { + if buffer.length + length > CAPACITY { + fail!("not_enough_space", buffer) + } else { + let mask = (bits[CAPACITY]:1 << length) - bits[CAPACITY]:1; + Buffer { + content: ((data & mask) << buffer.length) | buffer.content, + length: length + buffer.length + } + } +} + +#[test] +fn test_buffer_append_with_length() { + let buffer = Buffer { content: u32:0, length: u32:0 }; + let buffer = buffer_append_with_length(buffer, u32:0xBEEF, u32:8); + assert_eq(buffer, Buffer { content: u32:0xEF, length: u32:8 }); + let buffer = buffer_append_with_length(buffer, u32:0xDEAD, u32:8); + assert_eq(buffer, Buffer { content: u32:0xADEF, length: u32:16 }); +} + // Returns a new buffer with the `data` appended to the original `buffer` if // the buffer has enough space. Otherwise, it returns an unmodified buffer // along with an error. The results are stored in the BufferResult structure. diff --git a/xls/modules/zstd/shift_buffer.x b/xls/modules/zstd/shift_buffer.x new file mode 100644 index 0000000000..fd520774cb --- /dev/null +++ b/xls/modules/zstd/shift_buffer.x @@ -0,0 +1,246 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of a buffering proc responsible for +// reading the data stream and dividing it into the smallest packets of the +// requested size. + +import std; +import xls.modules.zstd.buffer; + +fn buffer_width(data_width: u32) -> u32 { data_width * u32:2 } + +pub struct ShiftBufferInput { + data: uN[DATA_W], + length: uN[LENGTH_W], + last: bool, +} + +pub struct ShiftBufferOutput { + data: uN[DATA_W], + length: uN[LENGTH_W], + last: bool, +} + +pub struct ShiftBufferCtrl { + length: uN[LENGTH_W], +} + +enum ShiftBufferStatus : u1 { + REFILL = 0, + FLUSH = 1, +} + +struct ShiftBufferState { + status: ShiftBufferStatus, + buff: buffer::Buffer, + ctrl: ShiftBufferCtrl, + ctrl_valid: bool, + last: bool, +} + +pub fn mask_data (data: bits[DATA_W], length: bits[LENGTH_W]) -> bits[DATA_W] { + type Data = bits[DATA_W]; + type Length = bits[LENGTH_W]; + + let mask = if length != Length:0 { (Data:1 << length) - Data:1 } else { Data:0 }; + data & mask +} + +pub proc ShiftBuffer< + DATA_W: u32, LENGTH_W: u32, + BUFFER_W: u32 = {buffer_width(DATA_W)} +> { + type Data = uN[DATA_W]; + type Length = uN[LENGTH_W]; + type BufferData = uN[BUFFER_W]; + type Input = ShiftBufferInput; + type Ctrl = ShiftBufferCtrl; + type Output = ShiftBufferOutput; + type State = ShiftBufferState; + type Status = ShiftBufferStatus; + + in_data_r: chan in; + in_ctrl_r: chan in; + out_data_s: chan out; + + config( + in_data_r: chan in, + in_ctrl_r: chan in, + out_data_s: chan out, + ) { (in_data_r, in_ctrl_r, out_data_s) } + + init { zero!() } + + next(state: State) { + + let tok0 = join(); + + // Receive control + let (tok1_0, ctrl, ctrl_valid) = + recv_if_non_blocking(tok0, in_ctrl_r, !state.ctrl_valid, state.ctrl); + + // Receive data + let can_fit = buffer::buffer_can_fit(state.buff, Data:0); + let do_recv_data = can_fit && state.status == Status::REFILL; + let (tok1_1, recv_data, recv_data_valid) = + recv_if_non_blocking(tok0, in_data_r, do_recv_data, zero!()); + + let tok1 = join(tok1_0, tok1_1); + + // Handle the request + // Uses buffer from the previous next evaluation (from state) to prevent + // creating long combinatorial logic that would allow receiving and + // sending back the data in the same cycle. + + let has_valid_request = ctrl_valid || state.ctrl_valid; + let has_enough_data = buffer::buffer_has_at_least(state.buff, ctrl.length as u32); + + let (data, do_send, new_buff, new_ctrl, new_ctrl_valid) = if has_valid_request && has_enough_data { + let (buff, data) = buffer::buffer_pop(state.buff, ctrl.length as u32); + let last = buff.length == u32:0 && state.last; + let output = Output { data: data as Data, length: ctrl.length, last }; + let do_send = ctrl.length != Length:0; + (output, do_send, buff, zero!(), false) + } else { + (zero!(), false, state.buff, ctrl, has_valid_request) + }; + + let tok2_0 = send_if(tok1, out_data_s, do_send, data); + + // Handle input data + let (new_buff, new_last) = if can_fit && recv_data_valid { + ( + buffer::buffer_append_with_length( + new_buff, recv_data.data as BufferData, recv_data.length as u32), + recv_data.last, + ) + } else { + (new_buff, state.last) + }; + + // Handle state change + let new_status = if state.status == Status::REFILL && recv_data_valid && recv_data.last { + Status::FLUSH + } else if state.status == Status::FLUSH && state.buff.length == ctrl.length as u32 { + Status::REFILL + } else { + state.status + }; + + State { + status: new_status, + buff: new_buff, + ctrl: new_ctrl, + ctrl_valid: new_ctrl_valid, + last: new_last + } + } +} + +const INST_DATA_W = u32:64; +const INST_LENGTH_W = std::clog2(INST_DATA_W) + u32:1; + +proc ShiftBufferInst { + type Input = ShiftBufferInput; + type Ctrl = ShiftBufferCtrl; + type Output = ShiftBufferOutput; + + config( + data_r: chan in, + ctrl_r: chan in, + out_s: chan out + ) { + spawn ShiftBuffer(data_r, ctrl_r, out_s); + } + + init { } + + next(state: ()) { } +} + +const TEST_DATA_W = u32:64; +const TEST_LENGTH_W = std::clog2(TEST_DATA_W) + u32:1; + +#[test_proc] +proc ShiftBufferTest { + type Input = ShiftBufferInput; + type Ctrl = ShiftBufferCtrl; + type Output = ShiftBufferOutput; + type Data = uN[TEST_DATA_W]; + type Length = uN[TEST_LENGTH_W]; + + terminator: chan out; + data_s: chan out; + ctrl_s: chan out; + out_r: chan in; + + config(terminator: chan out) { + let (data_s, data_r) = chan("in_data"); + let (ctrl_s, ctrl_r) = chan("in_ctrl"); + let (out_s, out_r) = chan("out_data"); + + spawn ShiftBuffer(data_r, ctrl_r, out_s); + (terminator, data_s, ctrl_s, out_r) + } + + init { } + + next(state: ()) { + + let tok = join(); + let tok = send(tok, data_s, Input { data: Data:0xDD_44, length: Length:16, last: false }); + let tok = send(tok, data_s, Input { data: Data:0xAA_11_BB_22_CC_33, length: Length:48, last: false }); + let tok = send(tok, data_s, Input { data: Data:0xEE_55_FF_66_00_77_11_88, length: Length:64, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:8 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x44, length: Length:8, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:4 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0xD, length: Length:4, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x18_8A_A1_1B_B2_2C_C3_3D, length: Length:64, last: false }); + + let tok = send(tok, data_s, Input { data: Data:0x44_BB_55_CC, length: Length:32, last: false }); + let tok = send(tok, data_s, Input { data: Data:0x22_99_33_AA, length: Length:32, last: true }); + let tok = send(tok, data_s, Input { data: Data:0x66_DD_77_EE_88_FF_99_00, length: Length:64, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:4 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x1, length: Length:4, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x55_CC_EE_55_FF_66_00_77, length: Length:64, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:16 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x44_BB, length: Length:16, last: false }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:32 }); + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x22_99_33_AA, length: Length:32, last: true }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); + + let (tok, output) = recv(tok, out_r); + assert_eq(output, Output { data: Data:0x66_DD_77_EE_88_FF_99_00, length: Length:64, last: false }); + + send(tok, terminator, true); + } +} From e0e461abc89b74d76bfdeaffe228f1d499c71dfc Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 16 May 2024 09:28:46 +0200 Subject: [PATCH 33/85] modules/zstd: Add FSE procs Internal-tag: [#57353] Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 99 ++++ xls/modules/zstd/common.x | 89 +++- xls/modules/zstd/fse_proba_freq_dec.x | 737 ++++++++++++++++++++++++++ 3 files changed, 919 insertions(+), 6 deletions(-) create mode 100644 xls/modules/zstd/fse_proba_freq_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 976a8107c3..2144b2e0e5 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -935,6 +935,105 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "fse_proba_freq_dec_dslx", + srcs = ["fse_proba_freq_dec.x"], + deps = [ + ":common_dslx", + ":ram_wr_handler_dslx", + ":shift_buffer_dslx", + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "fse_proba_freq_dec_dslx_test", + library = ":fse_proba_freq_dec_dslx", +) + +xls_dslx_verilog( + name = "fse_proba_freq_dec_verilog", + codegen_args = { + "module_name": "FseProbaFreqDec", + "generator": "pipeline", + "delay_model": "asap7", + # FIXME: update ram rewrite + #"ram_configurations": "ram:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + # latency = 5, + # rd_req = "fse_proba_freq_dec__rd_req_s", + # rd_resp = "fse_proba_freq_dec__rd_resp_r", + # wr_req = "fse_proba_freq_dec__wr_req_s", + # wr_resp = "fse_proba_freq_dec__wr_resp_r", + #), + "pipeline_stages": "6", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "FseProbaFreqDecoderInst", + library = ":fse_proba_freq_dec_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__fse_proba_freq_dec__FseProbaFreqDecoderInst__FseProbaFreqDecoder_0__64_7_8_10_1_next", + }, + verilog_file = "fse_proba_freq_dec.v", +) + +xls_benchmark_ir( + name = "fse_proba_freq_dec_opt_ir_benchmark", + src = ":fse_proba_freq_dec_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "delay_model": "asap7", + "inline_procs": "true", + "reset": "rst", + # FIXME: update ram rewrite + #"ram_configurations": "ram:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + # latency = 5, + # rd_req = "fse_proba_freq_dec__rd_req_s", + # rd_resp = "fse_proba_freq_dec__rd_resp_r", + # wr_req = "fse_proba_freq_dec__wr_req_s", + # wr_resp = "fse_proba_freq_dec__wr_resp_r", + #), + }, +) + +xls_benchmark_verilog( + name = "fse_proba_freq_dec_verilog_benchmark", + verilog_target = "fse_proba_freq_dec_verilog", +) + +verilog_library( + name = "fse_proba_freq_dec_lib", + srcs = [ + ":fse_proba_freq_dec.v", + ], +) + +synthesize_rtl( + name = "fse_proba_freq_dec_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "FseProbaFreqDec", + deps = [ + ":fse_proba_freq_dec_lib", + ], +) + +benchmark_synth( + name = "fse_proba_freq_dec_benchmark_synth", + synth_target = ":fse_proba_freq_dec_asap7", +) + +place_and_route( + name = "fse_proba_freq_dec_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "detailed_routing", + synthesized_rtl = ":fse_proba_freq_dec_asap7", + target_die_utilization_percentage = "10", +) + zstd_dec_deps = [ ":axi_csr_accessor_dslx", ":block_header_dec_dslx", diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 8c6b1f1c5d..98c58c60e1 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -12,6 +12,8 @@ // See the License for the specific language governing permissions and // limitations under the License. +import std; + pub const DATA_WIDTH = u32:64; pub const MAX_ID = u32::MAX; pub const SYMBOL_WIDTH = u32:8; @@ -20,8 +22,10 @@ pub const OFFSET_WIDTH = u32:22; pub const HISTORY_BUFFER_SIZE_KB = u32:64; pub const BUFFER_WIDTH = u32:128; +pub const BLOCK_PACKET_WIDTH = u32:32; + pub type BlockData = bits[DATA_WIDTH]; -pub type BlockPacketLength = u32; +pub type BlockPacketLength = bits[BLOCK_PACKET_WIDTH]; pub type BlockSize = bits[BLOCK_SIZE_WIDTH]; pub type CopyOrMatchContent = BlockData; pub type CopyOrMatchLength = u64; @@ -43,8 +47,8 @@ pub struct BlockDataPacket { } pub enum SequenceExecutorMessageType : u1 { - LITERAL = 0, - SEQUENCE = 1, + LITERAL = 0, + SEQUENCE = 1, } pub struct ExtendedBlockDataPacket { @@ -54,9 +58,9 @@ pub struct ExtendedBlockDataPacket { pub struct SequenceExecutorPacket { msg_type: SequenceExecutorMessageType, - length: CopyOrMatchLength, // Literal length or match length - content: CopyOrMatchContent, // Literal data or match offset - last: bool, // Last packet in frame + length: CopyOrMatchLength, // Literal length or match length + content: CopyOrMatchContent, // Literal data or match offset + last: bool, // Last packet in frame } // Defines output format of the ZSTD Decoder @@ -65,3 +69,76 @@ pub struct ZstdDecodedPacket { length: BlockPacketLength, // valid bits in data last: bool, // Last decoded packet in frame } + +pub enum CompressionMode : u2 { + PREDEFINED = 0, + RLE = 1, + COMPRESSED = 2, + REPEAT = 3, +} + +pub struct SequenceConf { + sequence_count: u17, + literals_mode: CompressionMode, + offset_mode: CompressionMode, + match_mode: CompressionMode, +} + +pub struct SequencePathCtrl { + literals_count: u20, + last_block: bool, + id: u32, + sequence_conf: SequenceConf, +} + +pub struct SequenceData { bytes: bits[64], length: u32, last: bool } + +// FSE + +pub const FSE_MAX_ACCURACY_LOG = u32:9; +pub const FSE_MAX_SYMBOLS = u32:256; + +pub const FSE_ACCURACY_LOG_WIDTH = std::clog2(FSE_MAX_ACCURACY_LOG + u32:1); +pub const FSE_SYMBOL_COUNT_WIDTH = std::clog2(FSE_MAX_SYMBOLS + u32:1); +pub const FSE_REMAINING_PROBA_WIDTH = std::clog2((u32:1 << FSE_MAX_ACCURACY_LOG) + u32:1); + +pub type FseRemainingProba = uN[FSE_REMAINING_PROBA_WIDTH]; +pub type FseAccuracyLog = uN[FSE_ACCURACY_LOG_WIDTH]; +pub type FseSymbolCount = uN[FSE_SYMBOL_COUNT_WIDTH]; + +// defined in https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.2.2.1 +pub const FSE_LITERAL_LENGTH_DEFAULT_DIST = s16[36]:[ + s16:4, s16:3, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, + s16:1, s16:1, s16:1, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:3, + s16:2, s16:1, s16:1, s16:1, s16:1, s16:1, s16:-1, s16:-1, s16:-1, s16:-1, +]; + +// defined in https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.2.2.2 +pub const FSE_OFFSET_DEFAULT_DIST = s16[29]:[ + s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:2, s16:2, s16:2, s16:1, s16:1, s16:1, s16:1, + s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:-1, s16:-1, + s16:-1, s16:-1, s16:-1, +]; + +// defined in https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.2.2.3 +pub const FSE_MATCH_LENGTH_DEFAULT_DIST = s16[53]:[ + s16:1, s16:4, s16:3, s16:2, s16:2, s16:2, s16:2, s16:2, s16:2, s16:1, s16:1, s16:1, s16:1, + s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, + s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, + s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:1, s16:-1, s16:-1, s16:-1, s16:-1, s16:-1, s16:-1, + s16:-1, +]; + +pub enum FSETableInitMode : u1 { + DEFAULT = 0, + EXTERNAL = 1, +} + +pub enum FSETableType : u2 { + LITERAL = 0, + OFFSET = 1, + MATCH = 2, +} + +pub struct FseRemainder { value: u1, valid: bool } +pub struct FseProbaFreqDecoderCtrl { remainder: FseRemainder, finished: bool } diff --git a/xls/modules/zstd/fse_proba_freq_dec.x b/xls/modules/zstd/fse_proba_freq_dec.x new file mode 100644 index 0000000000..19150851c5 --- /dev/null +++ b/xls/modules/zstd/fse_proba_freq_dec.x @@ -0,0 +1,737 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains a proc responsible for decoding probability frequencies +// to probability distribution, as described in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-4.1.1 + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.shift_buffer; +import xls.modules.zstd.ram_wr_handler as ram_wr; + +pub const FSE_MAX_SYMBOLS = u32:256; +pub const FSE_MAX_ACCURACY_LOG = u32:9; + +pub const FSE_ACCURACY_LOG_WIDTH = std::clog2(FSE_MAX_ACCURACY_LOG + u32:1); +pub const FSE_SYMBOL_COUNT_WIDTH = std::clog2(FSE_MAX_SYMBOLS + u32:1); +pub const FSE_REMAINING_PROBA_WIDTH = std::clog2((u32:1 << FSE_MAX_ACCURACY_LOG) + u32:1); + +pub type FseRemainingProba = uN[FSE_REMAINING_PROBA_WIDTH]; +pub type FseAccuracyLog = uN[FSE_ACCURACY_LOG_WIDTH]; +pub type FseSymbolCount = uN[FSE_SYMBOL_COUNT_WIDTH]; + +type AccuracyLog = common::FseAccuracyLog; +type RemainingProba = common::FseRemainingProba; +type SymbolCount = common::FseSymbolCount; +type SequenceData = common::SequenceData; + +const SYMBOL_COUNT_WIDTH = common::FSE_SYMBOL_COUNT_WIDTH; +const ACCURACY_LOG_WIDTH = common::FSE_ACCURACY_LOG_WIDTH; + +pub struct Remainder { value: u1, valid: bool } + +enum FseProbaFreqDecoderStatus: u1 { + OK = 0, + ERROR = 1, +} + +pub struct FseProbaFreqDecoderReq {} +pub struct FseProbaFreqDecoderResp { status: FseProbaFreqDecoderStatus } + +enum Fsm : u4 { + IDLE = 0, + SEND_ACCURACY_LOG_REQ = 1, + RECV_ACCURACY_LOG = 2, + SEND_SYMBOL_REQ = 3, + RECV_SYMBOL = 4, + RECV_ZERO_PROBA = 5, + WRITE_ZERO_PROBA = 6, + WAIT_FOR_COMPLETION = 7, + INVALID = 8, +} + +struct State { + fsm: Fsm, + // accuracy log used in the FSE decoding table + accuracy_log: AccuracyLog, + // remaining bit that can be a leftover from parsing small probability frequencies + remainder: Remainder, + // indicates if one more packet with zero probabilities is expected + next_recv_zero: bool, + // information about remaining probability points + remaining_proba: RemainingProba, + // number of received probability symbols + symbol_count: SymbolCount, + // number of probability symbols written to RAM + written_symbol_count: SymbolCount, + // number of processed zero probability symbols + zero_proba_count: SymbolCount, +} + +// Adapter for input data, converting the data to a shift buffer input type +pub proc FseInputBuffer { + type BufferInput = shift_buffer::ShiftBufferInput; + type BufferCtrl = shift_buffer::ShiftBufferCtrl; + type BufferOutput = shift_buffer::ShiftBufferOutput; + type Data = common::BlockData; + type Length = bits[LENGTH_WIDTH]; + + in_data_r: chan in; + buff_data_s: chan out; + + config( + data_r: chan in, + ctrl_r: chan in, + out_s: chan out, + ) { + let (buff_data_s, buff_data_r) = chan("buff_in_data"); + + spawn shift_buffer::ShiftBuffer( + buff_data_r, ctrl_r, out_s); + + (data_r, buff_data_s) + } + + init { } + + next (state: ()) { + let tok0 = join(); + let (tok1, recv_data, recv_valid) = recv_non_blocking(tok0, in_data_r, zero!()); + + let shift_buffer_data = BufferInput { + data: recv_data.bytes as Data, + length: recv_data.length as Length, + last: recv_data.last + }; + + send_if(tok1, buff_data_s, recv_valid, shift_buffer_data); + } +} + +// calculates bit_with of the next probability frequency based on the remaining probability points +fn get_bit_width(remaining_proba: RemainingProba) -> u16 { + let highest_set_bit = std::flog2(remaining_proba as u32 + u32:1); + highest_set_bit as u16 + u16:1 +} + +// calculates mask for small probability frequency values +fn get_lower_mask(bit_width: u16) -> u16 { + (u16:1 << (bit_width - u16:1)) - u16:1 +} + +// calculates threshold for a duplicated "upper" range of small probability frequencies +fn get_threshold(bit_width: u16, remaining_proba: u16) -> u16 { + (u16:1 << bit_width) - u16:1 - (remaining_proba + u16:1) +} + +// get the adjusted stream value for calculating probability points +fn get_adjusted_value(data: u16, remainder: Remainder) -> u16 { + if remainder.valid { (data << u16:1) | (remainder.value as u16) } else { data } +} + +// proc for filling probability frequencies table +pub proc FseProbaFreqDecoder< + RAM_DATA_WIDTH: u32, + RAM_SIZE: u32, + RAM_WORD_PARTITION_SIZE: u32, + RAM_ADDR_WIDTH: u32 = {std::clog2(RAM_SIZE)}, + RAM_NUM_PARTITIONS: u32 = {ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH)}, + DATA_WIDTH: u32 = {common::DATA_WIDTH}, + LENGTH_WIDTH: u32 = {common::BLOCK_PACKET_WIDTH} +> { + type Length = bits[LENGTH_WIDTH]; + type BufferCtrl = shift_buffer::ShiftBufferCtrl; + type BufferOutput = shift_buffer::ShiftBufferOutput; + type RamWriteReq = ram::WriteReq; + type RamWriteResp = ram::WriteResp; + type RamReadReq = ram::ReadReq; + type RamReadResp = ram::ReadResp; + type RamAddr = bits[RAM_ADDR_WIDTH]; + type RamData = bits[RAM_DATA_WIDTH]; + + type Req = FseProbaFreqDecoderReq; + type Resp = FseProbaFreqDecoderResp; + type Status = FseProbaFreqDecoderStatus; + + req_r: chan in; + resp_s: chan out; + + buff_in_ctrl_s: chan out; + buff_out_data_r: chan in; + resp_in_s: chan out; + resp_out_r: chan in; + + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + + config( + // control + req_r: chan in, + resp_s: chan out, + + // incomming data + buff_in_ctrl_s: chan out, + buff_out_data_r: chan in, + + // created lookup + rd_req_s: chan out, + rd_resp_r: chan in, + wr_req_s: chan out, + wr_resp_r: chan in + ) { + let (resp_in_s, resp_in_r) = chan("resp_in"); + let (resp_out_s, resp_out_r) = chan("resp_out"); + + spawn ram_wr::RamWrRespHandler( + resp_in_r, resp_out_s, wr_resp_r + ); + + ( + req_r, resp_s, + buff_in_ctrl_s, buff_out_data_r, + resp_in_s, resp_out_r, + rd_req_s, rd_resp_r, wr_req_s, + ) + } + + init { zero!() } + + next(state: State) { + let tok0 = join(); + + type BufferCtrl = shift_buffer::ShiftBufferCtrl; + type BufferOutput = shift_buffer::ShiftBufferOutput; + + type RamWriteReq = ram::WriteReq; + type RamWriteResp = ram::WriteResp; + type RamReadReq = ram::ReadReq; + type RamReadResp = ram::ReadResp; + + let do_recv_req = (state.fsm == Fsm::IDLE); + + let (tok1_0, _) = recv_if(tok0, req_r, do_recv_req, zero!()); + + let do_buff_data_recv = match (state.fsm) { + Fsm::RECV_ACCURACY_LOG => true, + Fsm::RECV_SYMBOL => true, + Fsm::RECV_ZERO_PROBA => true, + _ => false, + }; + let (tok1_1, out_data) = recv_if(tok0, buff_out_data_r, do_buff_data_recv, zero!()); + + let (tok1_2, written_symbol_count, written_symb_count_valid) = + recv_non_blocking(tok0, resp_out_r, state.written_symbol_count); + + let tok1 = join(tok1_1, tok1_2); + + let (buffer_ctrl_option, ram_option, resp_option, new_state) = match state.fsm { + Fsm::IDLE => { + ( + (false, zero!()), + (false, zero!()), + (false, zero!()), + State { fsm: Fsm::SEND_ACCURACY_LOG_REQ, ..state }, + ) + }, + Fsm::SEND_ACCURACY_LOG_REQ => { + ( + (true, BufferCtrl { length: ACCURACY_LOG_WIDTH as Length }), + (false, zero!()), + (false, zero!()), + State { fsm: Fsm::RECV_ACCURACY_LOG, written_symbol_count, ..state }, + ) + }, + Fsm::RECV_ACCURACY_LOG => { + let accuracy_log = AccuracyLog:5 + out_data.data as AccuracyLog; + let remaining_proba = RemainingProba:1 << accuracy_log; + + ( + (false, zero!()), + (false, zero!()), + (false, zero!()), + State { + fsm: Fsm::SEND_SYMBOL_REQ, + accuracy_log, + remaining_proba, + written_symbol_count, + ..state + }, + ) + }, + Fsm::SEND_SYMBOL_REQ => { + let bit_width = get_bit_width(state.remaining_proba); + ( + (true, BufferCtrl { length: bit_width as Length }), + (false, zero!()), + (false, zero!()), + State { fsm: Fsm::RECV_SYMBOL, written_symbol_count, ..state }, + ) + }, + Fsm::RECV_SYMBOL => { + let bit_width = get_bit_width(state.remaining_proba); + let lower_mask = get_lower_mask(bit_width); + let threshold = get_threshold(bit_width, state.remaining_proba as u16); + + let mask = (u16:1 << out_data.length) - u16:1; + let data = out_data.data as u16; + assert!(data & mask == data, "data should not contain additional bits"); + + let value = get_adjusted_value(data, state.remainder); + let (remainder, value) = if (value & lower_mask) < threshold { + (Remainder { value: value[bit_width - u16:1+:u1], valid: true }, value & lower_mask) + } else if value > lower_mask { + (zero!(), value - threshold) + } else { + (zero!(), value) + }; + + let proba = value as s16 - s16:1; + let proba_points = if proba < s16:0 { RemainingProba:1 } else { proba as RemainingProba }; + assert!(proba_points <= state.remaining_proba, "corrupted_data"); + + let remaining_proba = state.remaining_proba - proba_points; + let symbol_count = state.symbol_count + SymbolCount:1; + let remainder_count = if remainder.valid { u16:1 } else { u16:0 }; + + // received all the symbols + if remaining_proba == RemainingProba:0 { + ( + (false, zero!()), + (true, RamWriteReq { + addr: state.symbol_count as RamAddr, + data: proba as RamData, + mask: std::unsigned_max_value() + }), + (false, zero!()), + State { + fsm: Fsm::WAIT_FOR_COMPLETION, + written_symbol_count, + symbol_count, + remaining_proba, + remainder, + ..state + }, + ) + // there are remaining symbols, and next symbol is normal + } else if remaining_proba > RemainingProba:0 && proba != s16:0 { + let next_bit_width = get_bit_width(remaining_proba) - remainder_count; + ( + (true, BufferCtrl { length: next_bit_width as Length }), + (true, RamWriteReq { + addr: state.symbol_count as RamAddr, + data: proba as RamData, + mask: std::unsigned_max_value() + }), + (false, zero!()), + State { + fsm: Fsm::RECV_SYMBOL, + written_symbol_count, + symbol_count, + remaining_proba, + remainder, + ..state + }, + ) + // there are remaining symbols, and next data is info about zero probability + } else if remaining_proba > RemainingProba:0 && proba == s16:0 { + let next_bit_width = u16:2 - remainder_count; + ( + (true, BufferCtrl { length: next_bit_width as Length }), + (true, RamWriteReq { + addr: state.symbol_count as RamAddr, + data: proba as RamData, + mask: std::unsigned_max_value() + }), + (false, zero!()), + State { + fsm: Fsm::RECV_ZERO_PROBA, + written_symbol_count, + symbol_count, + remaining_proba, + remainder, + ..state + } + ) + } else { + fail!( + "unhandled_case", + ( + (false, zero!()), + (false, zero!()), + (false, zero!()), + State { fsm: Fsm::INVALID, ..zero!() }, + )) + } + }, + Fsm::RECV_ZERO_PROBA => { + let zero_proba_count = out_data.data as SymbolCount; + let zero_proba_length = out_data.length as SymbolCount; + let zero_proba_count = get_adjusted_value(zero_proba_count as u16, state.remainder) as SymbolCount; + + // all zero probabilitis received + if zero_proba_count == SymbolCount:0 { + let new_fsm = if state.remaining_proba > RemainingProba:0 { + Fsm::SEND_SYMBOL_REQ + } else if state.remaining_proba == RemainingProba:0 { + Fsm::WAIT_FOR_COMPLETION + } else { + Fsm::INVALID + }; + + ( + (true, zero!()), + (false, zero!()), + (false, zero!()), + State { + fsm: new_fsm, + remainder: zero!(), + written_symbol_count, + ..state + }, + ) + // some zero probabilities left + } else { + let next_recv_zero = zero_proba_count == SymbolCount:3; + ( + (false, zero!()), + (false, zero!()), + (false, zero!()), + State { + fsm: Fsm::WRITE_ZERO_PROBA, + remainder: zero!(), + written_symbol_count, + zero_proba_count, + next_recv_zero, + ..state + }, + ) + } + }, + Fsm::WRITE_ZERO_PROBA => { + let zero_proba_count = state.zero_proba_count - SymbolCount:1; + let symbol_count = state.symbol_count + SymbolCount:1; + + let write_req = RamWriteReq { + addr: state.symbol_count as RamAddr, + data: RamData:0, + mask: std::unsigned_max_value() + }; + + if zero_proba_count == SymbolCount:0 && state.next_recv_zero == true { + ( + (true, BufferCtrl { length: Length:2 }), + (true, write_req), + (false, zero!()), + State { + fsm: Fsm::RECV_ZERO_PROBA, + next_recv_zero: false, + written_symbol_count, + zero_proba_count, + symbol_count, + ..state + }, + ) + } else if zero_proba_count == SymbolCount:0 && state.next_recv_zero == false { + ( + (false, zero!()), + (true, write_req), + (false, zero!()), + State { + fsm: Fsm::SEND_SYMBOL_REQ, + next_recv_zero: false, + zero_proba_count: SymbolCount:0, + written_symbol_count, + symbol_count, + ..state + }, + ) + } else { + ( + (false, zero!()), + (true, write_req), + (false, zero!()), + State { + fsm: Fsm::WRITE_ZERO_PROBA, + zero_proba_count, + symbol_count, + written_symbol_count, + ..state + }, + ) + } + }, + Fsm::WAIT_FOR_COMPLETION => { + if written_symbol_count == state.symbol_count { + ( + (false, zero!()), + (false, zero!()), + (true, Resp { status: Status::OK }), + zero!(), + ) + } else { + ( + (false, zero!()), + (false, zero!()), + (false, zero!()), + state, + ) + } + }, + _ => { + trace_fmt!("Invalid state"); + fail!( + "not_handled", + ( + (false, zero!()), + (false, zero!()), + (false, zero!()), + state, + )) + }, + }; + + let (do_send_ctrl, ctrl_data) = buffer_ctrl_option; + let tok2_0 = send_if(tok1, buff_in_ctrl_s, do_send_ctrl, ctrl_data); + + let (do_send_ram, ram_data) = ram_option; + let tok2_1 = send_if(tok1, wr_req_s, do_send_ram, ram_data); + let tok2_2 = send_if(tok1, resp_in_s, do_send_ram, state.symbol_count == SymbolCount:0); + + let (do_send_finish, finish_data) = resp_option; + let tok2_3 = send_if(tok1, resp_s, do_send_finish, finish_data); + + // unused channels + send_if(tok0, rd_req_s, false, zero!()); + recv_if(tok0, rd_resp_r, false, zero!()); + + new_state + } +} + +const INST_RAM_SIZE = common::FSE_MAX_SYMBOLS; +const INST_RAM_ADDR_WIDTH = std::clog2(INST_RAM_SIZE); +const INST_RAM_DATA_WIDTH = get_bit_width(RemainingProba:1 << common::FSE_MAX_ACCURACY_LOG) as u32; +const INST_RAM_WORD_PARTITION_SIZE = INST_RAM_DATA_WIDTH; +const INST_RAM_NUM_PARTITIONS = ram::num_partitions(INST_RAM_WORD_PARTITION_SIZE, INST_RAM_DATA_WIDTH); +const INST_DATA_WIDTH = common::DATA_WIDTH; +const INST_LENGTH_WIDTH = common::BLOCK_PACKET_WIDTH; + +proc FseProbaFreqDecoderInst { + rd_req_s: chan> out; + rd_resp_r: chan> in; + + config( + req_r: chan in, + resp_s: chan out, + buff_in_ctrl_s: chan> out, + buff_out_data_r: chan> in, + rd_req_s: chan> out, + rd_resp_r: chan> in, + wr_req_s: chan> out, + wr_resp_r: chan in) { + + spawn FseProbaFreqDecoder( + req_r, resp_s, + buff_in_ctrl_s, buff_out_data_r, + rd_req_s, rd_resp_r, wr_req_s, wr_resp_r + ); + + (rd_req_s, rd_resp_r) + } + + init { } + next(state: ()) { } +} + +const TEST_RAM_DATA_WIDTH = u32:16; +const TEST_RAM_SIZE = u32:100; +const TEST_RAM_ADDR_WIDTH = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE = TEST_RAM_DATA_WIDTH; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_WIDTH); +const TEST_DATA_WIDTH = common::DATA_WIDTH; +const TEST_LENGTH_WIDTH = common::BLOCK_PACKET_WIDTH; + +#[test_proc] +proc FseProbaFreqDecoderTest { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + type BufferCtrl = shift_buffer::ShiftBufferCtrl; + type BufferOutput = shift_buffer::ShiftBufferOutput; + type RamAddr = bits[TEST_RAM_ADDR_WIDTH]; + type RamData = uN[TEST_RAM_DATA_WIDTH]; + type RamDataSigned = sN[TEST_RAM_DATA_WIDTH]; + type Req = FseProbaFreqDecoderReq; + type Resp = FseProbaFreqDecoderResp; + + terminator: chan out; + seq_data_s: chan out; + req_s: chan out; + resp_r: chan in; + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + wr_resp_r: chan in; + + config(terminator: chan out) { + // RAM channels + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + // FseProbaFreqDecoder channels + let (seq_data_s, seq_data_r) = chan("seq_data"); + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + let (buff_in_ctrl_s, buff_in_ctrl_r) = chan("buff_in_ctrl"); + let (buff_out_data_s, buff_out_data_r) = chan("buff_out_data"); + + spawn FseInputBuffer( + seq_data_r, buff_in_ctrl_r, buff_out_data_s); + + spawn FseProbaFreqDecoder( + req_r, resp_s, + buff_in_ctrl_s, buff_out_data_r, + rd_req_s, rd_resp_r, wr_req_s, wr_resp_r); + + spawn ram::RamModel( + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s); + + (terminator, seq_data_s, req_s, resp_r, rd_req_s, rd_resp_r, wr_req_s, wr_resp_r) + } + + init { } + + next(state: ()) { + let tok = join(); + + // * accuracy_log = 8 + // * probability frequencies: + // | value | probability | bits (real) | symbol number | + // | ----- | ----------- | ---------- | ------------- | + // | 97 | 96 | 8(9) | 0 | + // | 117 | 116 | 8 | 1 | + // | 55 | 36 | 6 | 2 | + // | 1 | 0 | 4(3) | 3 | + // | 2* | 0 0 0 | (2) | 4 5 6 | + // | 1* | 0 | (2) | 7 | + // | 3 | 2 | 4(3) | 8 | + // | 1 | 0 | 3 | 9 | + // | 0 | -1 | 3 | 10 | + // | 6 | 5 | 3 | 11 | + + const EXPECTED_RAM_CONTENTS = RamData[12]:[ + RamData:96, + RamData:116, + RamData:36, + RamData:0, + RamData:0, RamData:0, RamData:0, + RamData:0, + RamData:2, + RamData:0, + RamDataSigned:-1 as RamData, + RamData:5 + ]; + + let tok = send(tok, seq_data_s, common::SequenceData { + bytes: u64:0b111_000_00_001_011_01_11_001_110111_01110101_01100001_0011, + length: u32:47, + last: false + }); + let tok = send(tok, req_s, zero!()); + let (tok, _) = recv(tok, resp_r); + + for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { + let tok = send(tok, rd_req_s, ReadReq { + addr: i as RamAddr, + mask: std::unsigned_max_value(), + }); + + let (tok, recv_data) = recv(tok, rd_resp_r); + assert_eq(recv_data.data, exp_val); + tok + }((tok)); + + // * accuracy_log = 9 + // * probability frequencies: + // | value | probability | bits (real) | symbol number | + // | ----- | ----------- | ---------- | ------------- | + // | 1022 | 511 | 10 | 0 | + // | 0 | -1 | 2(1) | 1 | + + const EXPECTED_RAM_CONTENTS = RamData[2]:[ + RamData:511, + RamDataSigned:-1 as RamData, + ]; + + let tok = send(tok, seq_data_s, common::SequenceData { + bytes: u64:0b00_1111111110_0100, + length: u32:16, + last: false + }); + let tok = send(tok, req_s, zero!()); + let (tok, _) = recv(tok, resp_r); + + for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { + let tok = send(tok, rd_req_s, ReadReq { + addr: i as RamAddr, + mask: std::unsigned_max_value(), + }); + + let (tok, recv_data) = recv(tok, rd_resp_r); + assert_eq(recv_data.data, exp_val); + tok + }((tok)); + + // * accuracy_log = 9 + // * probability frequencies: + // | value | probability | bits (real) | symbol number | + // | ----- | ----------- | ---------- | ------------- | + // | 1022 | 511 | 10 | 0 | + // | 2 | -1 | 2(1) | 1 | + + const EXPECTED_RAM_CONTENTS = RamData[2]:[ + RamData:511, + RamDataSigned:-1 as RamData, + ]; + + let tok = send(tok, seq_data_s, common::SequenceData { + bytes: u64:0b10_1111111110_0100, + length: u32:16, + last: false + }); + let tok = send(tok, req_s, zero!()); + let (tok, _) = recv(tok, resp_r); + + for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { + let tok = send(tok, rd_req_s, ReadReq { + addr: i as RamAddr, + mask: std::unsigned_max_value(), + }); + + let (tok, recv_data) = recv(tok, rd_resp_r); + assert_eq(recv_data.data, exp_val); + tok + }((tok)); + + let tok = send(tok, terminator, true); + } +} From 3a4c765cf94914bb9239c1e1be027aae5e50c703 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 16 May 2024 09:30:04 +0200 Subject: [PATCH 34/85] modules/zstd: Add a proc handling RAM write completion Internal-tag: [#57353] Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 71 ++++++++++++++ xls/modules/zstd/ram_wr_handler.x | 152 ++++++++++++++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 xls/modules/zstd/ram_wr_handler.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 2144b2e0e5..c46ee0376e 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -935,6 +935,77 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "ram_wr_handler_dslx", + srcs = ["ram_wr_handler.x"], + deps = [ + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "ram_wr_handler_dslx_test", + library = ":ram_wr_handler_dslx", +) + +xls_dslx_verilog( + name = "ram_rw_handler_verilog", + codegen_args = { + "module_name": "RamWrRespHandler", + "delay_model": "asap7", + "pipeline_stages": "1", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "RamWrRespHandlerInst", + library = ":ram_wr_handler_dslx", + opt_ir_args = { + "top": "__ram_wr_handler__RamWrRespHandlerInst__RamWrRespHandler_0__32_next", + }, + verilog_file = "ram_rw_handler.v", +) + +xls_benchmark_ir( + name = "ram_rw_handler_opt_ir_benchmark", + src = ":ram_rw_handler_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "ram_rw_handler_verilog_lib", + srcs = [ + ":ram_rw_handler.v", + ], +) + +synthesize_rtl( + name = "ram_rw_handler_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "RamWrRespHandler", + deps = [ + ":ram_rw_handler_verilog_lib", + ], +) + +benchmark_synth( + name = "ram_rw_handler_benchmark_synth", + synth_target = ":ram_rw_handler_synth_asap7", +) + +place_and_route( + name = "ram_rw_handler_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":ram_rw_handler_synth_asap7", + target_die_utilization_percentage = "10", +) + xls_dslx_library( name = "fse_proba_freq_dec_dslx", srcs = ["fse_proba_freq_dec.x"], diff --git a/xls/modules/zstd/ram_wr_handler.x b/xls/modules/zstd/ram_wr_handler.x new file mode 100644 index 0000000000..a59fd0b256 --- /dev/null +++ b/xls/modules/zstd/ram_wr_handler.x @@ -0,0 +1,152 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of a proc responsible for receiving +// RAM completions and counting their number. The proc might be used to simplify +// the implementation of other procedures. + +import std; +import xls.examples.ram; + +proc RamWrRespHandler { + type Reset = bool; + type WriteCnt = bits[CNT_WIDTH]; + type WriteResp = ram::WriteResp; + + input_r: chan in; + output_s: chan out; + wr_resp_r: chan in; + + config( + input_r: chan in, + output_s: chan out, + wr_resp_r: chan in + ) { + (input_r, output_s, wr_resp_r) + } + + init { WriteCnt:0 } + + next(wr_cnt: WriteCnt) { + let tok0 = join(); + + let (tok1, reset) = recv(tok0, input_r); + recv(tok1, wr_resp_r); + + let wr_cnt = if reset { WriteCnt:1 } else { wr_cnt }; + send(tok1, output_s, wr_cnt); + + wr_cnt + WriteCnt:1 + } +} + +const INST_CNT_WIDTH = u32:32; +proc RamWrRespHandlerInst { + type Reset = bool; + type WriteCnt = bits[INST_CNT_WIDTH]; + type WriteResp = ram::WriteResp; + + config( + input_r: chan in, + output_s: chan out, + wr_resp_r: chan in + ) { + spawn RamWrRespHandler(input_r, output_s, wr_resp_r); + } + + init { } + next(state: ()) { } +} + +const TEST_CNT_WIDTH = u32:32; +const TEST_RAM_DATA_WIDTH = u32:8; +const TEST_RAM_SIZE = u32:256; +const TEST_RAM_ADDR_WIDTH = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE = TEST_RAM_DATA_WIDTH; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_WIDTH); + +const TEST_SYMBOLS_TO_SEND = u32:12; + +struct RamWrRespHandlerTestState { rd_cnt: u32, wr_cnt: u32 } + +#[test_proc] +proc RamWrRespHandlerTest { + type RamReadReq = ram::ReadReq; + type RamReadResp = ram::ReadResp; + type RamWriteReq = ram::WriteReq; + type RamWriteResp = ram::WriteResp; + type RamAddr = bits[TEST_RAM_ADDR_WIDTH]; + type RamData = bits[TEST_RAM_DATA_WIDTH]; + type State = RamWrRespHandlerTestState; + type CntWidth = bits[TEST_CNT_WIDTH]; + + terminator: chan out; + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + wr_resp_r: chan in; + resp_in_s: chan out; + resp_out_r: chan in; + + config(terminator: chan out) { + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + let (resp_in_s, resp_in_r) = chan("resp_in"); + let (resp_out_s, resp_out_r) = chan("resp_out"); + + spawn RamWrRespHandler(resp_in_r, resp_out_s, wr_resp_r); + + spawn ram::RamModel( + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s); + + (terminator, rd_req_s, rd_resp_r, wr_req_s, wr_resp_r, resp_in_s, resp_out_r) + } + + init { + type State = RamWrRespHandlerTestState; + zero!() + } + + next(state: State) { + let tok0 = join(); + + let start = (state.rd_cnt == u32:0); + const MASK = std::unsigned_max_value(); + + let (tok1, wr_cnt, _) = recv_non_blocking(tok0, resp_out_r, state.wr_cnt); + + let do_send_ram = state.rd_cnt < TEST_SYMBOLS_TO_SEND; + let wr_req = RamWriteReq { + addr: state.rd_cnt as RamAddr, + data: state.rd_cnt as RamData, + mask: MASK + }; + + let tok2_0 = send_if(tok1, wr_req_s, do_send_ram, wr_req); + let tok2_1 = send_if(tok1, resp_in_s, do_send_ram, start); + + let do_terminate = (state.wr_cnt == (TEST_SYMBOLS_TO_SEND - u32:1)); + let tok2_2 = send_if(tok1, terminator, do_terminate, true); + + if do_terminate { + zero!() + } else { + let rd_cnt = state.rd_cnt + u32:1; + State { rd_cnt, wr_cnt } + } + } +} From ab87033902cd10fe55c52941f24165e49332a36b Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 31 Oct 2024 23:03:31 +0100 Subject: [PATCH 35/85] modules/zstd: Add Sequence and Literals Section Header decoders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Krzysztof Obłonczek Signed-off-by: Robert Winkler Signed-off-by: Krzysztof Obłonczek --- xls/modules/zstd/BUILD | 86 ++++ xls/modules/zstd/comp_block_dec.x | 244 +++++++++++ xls/modules/zstd/literals_block_header_dec.x | 436 +++++++++++++++++++ xls/modules/zstd/ram_wr_handler.x | 2 +- xls/modules/zstd/sequence_conf_dec.x | 342 +++++++++++++++ 5 files changed, 1109 insertions(+), 1 deletion(-) create mode 100644 xls/modules/zstd/comp_block_dec.x create mode 100644 xls/modules/zstd/literals_block_header_dec.x create mode 100644 xls/modules/zstd/sequence_conf_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index c46ee0376e..9860a0791f 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1105,6 +1105,92 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "literals_block_header_dec_dslx", + srcs = ["literals_block_header_dec.x"], + deps = [ + "//xls/modules/zstd/memory:mem_reader_dslx", + ], +) + +xls_dslx_test( + name = "literals_block_header_dec_dslx_test", + dslx_test_args = {"compare": "jit"}, + library = ":literals_block_header_dec_dslx", +) + + +xls_dslx_verilog( + name = "literals_block_header_dec_verilog", + codegen_args = window_buffer_codegen_args, + dslx_top = "LiteralsHeaderDecoderInst", + library = ":literals_block_header_dec_dslx", + tags = ["manual"], + verilog_file = "literals_block_header_dec.v", +) + +xls_benchmark_ir( + name = "literals_block_header_dec_opt_ir_benchmark", + src = ":literals_block_header_dec_verilog.opt.ir", + benchmark_ir_args = { + "top": "__literals_block_header_dec__LiteralsHeaderDecoderInst__LiteralsHeaderDecoder_0__16_64_next", + "pipeline_stages": "10", + }, + tags = ["manual"], +) + + +xls_dslx_library( + name = "sequence_conf_dec_dslx", + srcs = ["sequence_conf_dec.x"], + deps = [ + "//xls/modules/zstd/memory:mem_reader_dslx", + ":common_dslx", + ], +) + +xls_dslx_test( + name = "sequence_conf_dec_dslx_test", + dslx_test_args = {"compare": "jit"}, + library = ":sequence_conf_dec_dslx", +) + +xls_dslx_verilog( + name = "sequence_conf_dec_verilog", + codegen_args = window_buffer_codegen_args, + dslx_top = "SequenceConfDecoderInst", + library = ":sequence_conf_dec_dslx", + tags = ["manual"], + verilog_file = "sequence_conf_dec.v", +) + +xls_benchmark_ir( + name = "sequence_conf_dec_opt_ir_benchmark", + src = ":sequence_conf_dec_verilog.opt.ir", + benchmark_ir_args = { + "top": "__sequence_conf_dec__SequenceConfDecoderInst__SequenceConfDecoder_0__16_64_next", + "pipeline_stages": "10", + }, + tags = ["manual"], +) + +#xls_dslx_library( +# name = "comp_block_dec_dslx", +# srcs = ["comp_block_dec.x"], +# deps = [ +# "//xls/examples:ram_dslx", +# "//xls/modules/zstd/memory:mem_reader_dslx", +# "//xls/modules/zstd/memory:axi_ram_dslx", +# ":fse_proba_freq_dec_dslx", +# ":literals_block_header_dec_dslx", +# ], +#) +# +#xls_dslx_test( +# name = "comp_block_dec_dslx_test", +# library = ":comp_block_dec_dslx", +#) + zstd_dec_deps = [ ":axi_csr_accessor_dslx", ":block_header_dec_dslx", diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x new file mode 100644 index 0000000000..877998336d --- /dev/null +++ b/xls/modules/zstd/comp_block_dec.x @@ -0,0 +1,244 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; +import xls.examples.ram; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.fse_proba_freq_dec; +import xls.modules.zstd.comp_block_header_dec; + + +struct CompressBlockDecoderReq { } +struct CompressBlockDecoderResp { } + +struct CompressBlockDecoderControlState { } + +proc CompressBlockDecoderControl { + type Req = CompressBlockDecoderReq; + type Resp = CompressBlockDecoderResp; + type State = CompressBlockDecoderControlState; + + type HeaderDecoderReq = comp_block_header_dec::CompressBlockHeaderDecoderReq; + type HeaderDecoderResp = comp_block_header_dec::CompressBlockHeaderDecoderResp; + + req_r: chan in; + resp_s: chan out; + cmph_req_s: chan out; + cmph_resp_r: chan in; + + init { zero!() } + + config( + req_r: chan in, + resp_s: chan out, + cmph_req_s: chan out, + cmph_resp_r: chan in, + ) { + (req_r, resp_s, cmph_req_s, cmph_resp_r) + } + + next (state: State) { + let tok = join(); + + send_if(tok, resp_s, false, zero!()); + send_if(tok, cmph_req_s, false, zero!()); + + recv_if(tok, req_r, false, zero!()); + recv_if(tok, cmph_resp_r, false, zero!()); + + state + } +} + +proc CompressBlockDecoder< + // AXI parameters + AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + + // FSE proba + FSE_PROBA_DIST_W: u32 = {u32:16}, + FSE_PROBA_MAX_DISTS: u32 = {u32:256}, + + // constants + FSE_DEF_PROBA_DIST_RAM_DATA_W: u32 = {FSE_PROBA_DIST_W}, + FSE_DEF_PROBA_DIST_RAM_SIZE: u32 = {FSE_PROBA_MAX_DISTS}, + FSE_DEF_PROBA_DIST_ADDR_W: u32 = {std::clog2(FSE_DEF_PROBA_DIST_RAM_SIZE)}, + FSE_DEF_PROBA_DIST_RAM_WORD_PARTITION_SIZE: u32 = { FSE_DEF_PROBA_DIST_RAM_DATA_W }, + FSE_DEF_PROBA_DIST_RAM_NUM_PARTITIONS: u32 = { ram::num_partitions(FSE_DEF_PROBA_DIST_RAM_WORD_PARTITION_SIZE, FSE_DEF_PROBA_DIST_RAM_DATA_W) }, + AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, +> { + type Req = CompressBlockDecoderReq; + type Resp = CompressBlockDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type HeaderDecoderReq = comp_block_header_dec::CompressBlockHeaderDecoderReq; + type HeaderDecoderResp = comp_block_header_dec::CompressBlockHeaderDecoderResp; + + //type ShiftBufferInput = shift_buffer::ShiftBufferInput; + //type ShiftBufferCtrl = shift_buffer::ShiftBufferCtrl; + //type ShiftBufferOutput = shift_buffer::ShiftBufferOutput; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + init {} + next(state: ()) {} + + config( + req_r: chan in, + resp_s: chan out, + + // AXI Compressed Block Header Decoder (manager) + cmph_axi_ar_s: chan out, + cmph_axi_r_r: chan in, + + // AXI Fse Probability Frequence Decoder (manager) + //pfd_axi_ar_s: chan out, + //pfd_axi_r_r: chan in, + + ) { + + const CHANNEL_DEPTH = u32:1; + + // Compress Block Header Memory Reader + + let (cmph_mem_rd_req_s, cmph_mem_rd_req_r) = chan("cmph_mem_rd_req"); + let (cmph_mem_rd_resp_s, cmph_mem_rd_resp_r) = chan("cmph_mem_rd_resp"); + + spawn mem_reader::MemReader( + cmph_mem_rd_req_r, cmph_mem_rd_resp_s, + cmph_axi_ar_s, cmph_axi_r_r, + ); + + let (cmph_req_s, cmph_req_r) = chan("cmph_dec_req"); + let (cmph_resp_s, cmph_resp_r) = chan("cmph_dec_resp"); + + spawn comp_block_header_dec::CompressBlockHeaderDecoder( + cmph_mem_rd_req_s, cmph_mem_rd_resp_r, + cmph_req_r, cmph_resp_s + ); + + // FseProbaFreqDecoder channels + // + // This part of the decoder is used to prepare FSE lookups if they + // are provided in the encoded ZSTD bitstream (FSE_Compressed_Mode). + // This part of the design sould take the input from the input buffer + // located on the system bus, and decode the probability frequencies + // into probability distribution. The outpud data should be stored in + // a local RAM. One chalange related to this part of the code is how + // to us a single instance of the proc to prepare three different FSE tables + // (for Offsets, Matches, and Literals Lenghts). + + // spawn mem_reader::MemReader< + // AXI_DATA_W, AXI_ADDR_W, AXI_DEST_W, AXI_ID_W, CHANNEL_DEPTH + // >( + // pfd_mem_rd_req_r, pfd_mem_rd_resp_s, + // pfd_axi_ar_s, pfd_axi_r_r, + // ); + // + // spawn shift_buffer::ShiftBuffer< + // SHIFT_BUFFER_DATA_W, SHIFT_BUFFER_LENGTH_W + // >(buff_data_r, ctrl_r, out_s); + // + // + // spawn FseProbaFreqDecoder< + // FSE_DEF_PROBA_DIST_RAM_DATA_W, + // FSE_DEF_PROBA_DIST_RAM_SIZE, + // FSE_DEF_PROBA_DIST_RAM_WORD_PARTITION_SIZE + // >( + // req_r, resp_s, + // buff_in_ctrl_s, buff_out_data_r, + // rd_req_s, rd_resp_r, wr_req_s, wr_resp_r + // ); + // + // let (dpd_rd_req_r, dpd_rd_req_s) = chan("rd_req"); + // let (dpd_rd_req_r, dpd_rd_req_s) = chan("rd_resp"); + // let (dpd_wr_req_r, dpd_wr_req_s) = chan("wr_req"); + // let (dpd_wr_resp_r, dpd_wr_resp_s) = chan("wr_resp"); + // + // spawn ram::RamModel< + // FSE_PROBA_DATA_W, + // FSE_PROBA_RAM_SIZE, + // FSE_PROBA_RAM_WORD_PARTITION_SIZE + // >( + // rd_req_r, rd_resp_s, wr_req_r, wr_resp_s + // ); + + //spawn CompressBlockDecoderControl< + //>( + // req_r, resp_s + // cmph_req_s, cmph_resp_r, + //); + + //spawn fse_proba_freq_dec::FseProbaFreqDecoder(); + () + } +} + +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_ID_W = u32:4; +const TEST_AXI_DEST_W = u32:4; + +#[test_proc] +proc CompressBlockDecoderTest { + type Req = CompressBlockDecoderReq; + type Resp = CompressBlockDecoderResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + + terminator: chan out; + req_s: chan out; + resp_r: chan in; + cmph_axi_ar_r: chan in; + cmph_axi_r_s: chan out; + + init {} + config(terminator: chan out) { + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + let (cmph_axi_ar_s, cmph_axi_ar_r) = chan("cmph_axi_ar"); + let (cmph_axi_r_s, cmph_axi_r_r) = chan("cmph_axi_r"); + + spawn CompressBlockDecoder< + TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W + >( + req_r, resp_s, + cmph_axi_ar_s, cmph_axi_r_r); + + ( + terminator, + req_s, resp_r, + cmph_axi_ar_r, cmph_axi_r_s + ) + } + + next(state: ()) { + let tok = join(); + send(tok, terminator, true); + } +} + diff --git a/xls/modules/zstd/literals_block_header_dec.x b/xls/modules/zstd/literals_block_header_dec.x new file mode 100644 index 0000000000..86e6597c01 --- /dev/null +++ b/xls/modules/zstd/literals_block_header_dec.x @@ -0,0 +1,436 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import xls.modules.zstd.memory.mem_reader; + +pub enum LiteralsHeaderSize : u3 { + SINGLE_BYTE = 0, + TWO_BYTES = 1, + THREE_BYTES = 2, + COMP_THREE_BYTES = 4, + COMP_FOUR_BYTES = 5, + COMP_FIVE_BYTES = 6, +} + +pub enum LiteralsBlockType: u3 { + RAW = 0, + RLE = 1, + COMP = 2, + COMP_4 = 3, + TREELESS = 4, + TREELESS_4 = 5, +} + + +pub fn parse_literals_header_first_byte(first_byte :u8) -> (LiteralsBlockType, LiteralsHeaderSize) { + match (first_byte[:2], first_byte[2:4]) { + (u2:0, u2:1) => (LiteralsBlockType::RAW, LiteralsHeaderSize::TWO_BYTES), + (u2:0, u2:3) => (LiteralsBlockType::RAW, LiteralsHeaderSize::THREE_BYTES), + (u2:0, _) => (LiteralsBlockType::RAW, LiteralsHeaderSize::SINGLE_BYTE), + (u2:1, u2:1) => (LiteralsBlockType::RLE, LiteralsHeaderSize::TWO_BYTES), + (u2:1, u2:3) => (LiteralsBlockType::RLE, LiteralsHeaderSize::THREE_BYTES), + (u2:1, _) => (LiteralsBlockType::RLE, LiteralsHeaderSize::SINGLE_BYTE), + (u2:2, u2:0) => (LiteralsBlockType::COMP, LiteralsHeaderSize::COMP_THREE_BYTES), + (u2:2, u2:1) => (LiteralsBlockType::COMP_4, LiteralsHeaderSize::COMP_THREE_BYTES), + (u2:2, u2:2) => (LiteralsBlockType::COMP_4, LiteralsHeaderSize::COMP_FOUR_BYTES), + (u2:2, u2:3) => (LiteralsBlockType::COMP_4, LiteralsHeaderSize::COMP_FIVE_BYTES), + (u2:3, u2:0) => (LiteralsBlockType::TREELESS, LiteralsHeaderSize::COMP_THREE_BYTES), + (u2:3, u2:1) => (LiteralsBlockType::TREELESS_4, LiteralsHeaderSize::COMP_THREE_BYTES), + (u2:3, u2:2) => (LiteralsBlockType::TREELESS_4, LiteralsHeaderSize::COMP_FOUR_BYTES), + (u2:3, u2:3) => (LiteralsBlockType::TREELESS_4, LiteralsHeaderSize::COMP_FIVE_BYTES), + _ => (LiteralsBlockType::TREELESS, LiteralsHeaderSize::COMP_THREE_BYTES), + // fail!() doesn't work with quicktest, JIT failes to translate such function + //_ => fail!("Should_never_be_called", (LiteralsBlockType::RAW, LiteralsHeaderSize::SINGLE_BYTE)) + } +} + +#[quickcheck] +fn test_parse_literals_header_first_byte(x: u8) -> bool { + let (literal, length) = parse_literals_header_first_byte(x); + ((literal == LiteralsBlockType::RAW || literal == LiteralsBlockType::RLE) && + (length == LiteralsHeaderSize::SINGLE_BYTE || length == LiteralsHeaderSize::TWO_BYTES || + length == LiteralsHeaderSize::THREE_BYTES)) || + ((literal == LiteralsBlockType::COMP || literal == LiteralsBlockType::TREELESS) && + (length == LiteralsHeaderSize::COMP_THREE_BYTES)) || + ((literal == LiteralsBlockType::COMP_4 || literal == LiteralsBlockType::TREELESS_4) && + (length == LiteralsHeaderSize::COMP_THREE_BYTES || length == LiteralsHeaderSize::COMP_FOUR_BYTES || + length == LiteralsHeaderSize::COMP_FIVE_BYTES) + ) +} + +pub struct LiteralsHeader { + literal_type: LiteralsBlockType, + regenerated_size: u20, + compressed_size: u20, +} + +pub fn parse_literals_header(header_raw: u40) -> (LiteralsHeader, u3) { + let (literal_type, header_size) = parse_literals_header_first_byte(header_raw[0:8]); + let (regenerated_size, compressed_size, header_length) = match (header_size) { + LiteralsHeaderSize::SINGLE_BYTE => (header_raw[3:8] as u20, header_raw[3:8] as u20, u3:1), + LiteralsHeaderSize::TWO_BYTES => (header_raw[4:16] as u20, header_raw[4:16] as u20, u3:2), + LiteralsHeaderSize::THREE_BYTES => (header_raw[4:24] as u20, header_raw[4:24] as u20, u3:3), + LiteralsHeaderSize::COMP_THREE_BYTES => (header_raw[4:14] as u20, header_raw[14:24] as u20, u3:3), + LiteralsHeaderSize::COMP_FOUR_BYTES => (header_raw[4:18] as u20, header_raw[18:32] as u20, u3:4), + LiteralsHeaderSize::COMP_FIVE_BYTES => (header_raw[4:22] as u20, header_raw[22:40] as u20, u3:5), + // fail!() doesn't work with quicktest, JIT failes to translate such function + //_ => fail!("Unrecognized_header_sizeC" ,CompressedBlockSize { + _ => (u20:0, u20:0, u3:0), + }; + (LiteralsHeader { + literal_type: literal_type, + regenerated_size: regenerated_size, + compressed_size: match (literal_type) { + LiteralsBlockType::RLE => u20:1, + _ => compressed_size, + } + }, header_length) +} + +#[quickcheck] +fn test_parse_literals_header(x: u40) -> bool { + let (header, header_length_bytes) = parse_literals_header(x); + let (_, header_size) = parse_literals_header_first_byte(x[0:8]); + + let length_bytes_equivalence = match (header_size) { + LiteralsHeaderSize::SINGLE_BYTE => header_length_bytes == u3:1, + LiteralsHeaderSize::TWO_BYTES => header_length_bytes == u3:2, + LiteralsHeaderSize::THREE_BYTES | LiteralsHeaderSize::COMP_THREE_BYTES => header_length_bytes == u3:3, + LiteralsHeaderSize::COMP_FOUR_BYTES => header_length_bytes == u3:4, + LiteralsHeaderSize::COMP_FIVE_BYTES => header_length_bytes == u3:5, + _ => false + }; + let raw_length_equivalence = if (header.literal_type == LiteralsBlockType::RAW) { + header.regenerated_size == header.compressed_size + } else { true }; + let regen_comp_size_equivalence = if (header.literal_type == LiteralsBlockType::RAW || header.literal_type == LiteralsBlockType::RLE) { + raw_length_equivalence && match(header_size) { + LiteralsHeaderSize::SINGLE_BYTE => header.regenerated_size == x[3:8] as u20, + LiteralsHeaderSize::TWO_BYTES => header.regenerated_size == x[4:16] as u20, + LiteralsHeaderSize::THREE_BYTES => header.regenerated_size == x[4:24], + _ => false + } + } else { + match(header_size) { + LiteralsHeaderSize::COMP_THREE_BYTES => { + header.regenerated_size == x[4:14] as u20 && + header.compressed_size == x[14:24] as u20 + }, + LiteralsHeaderSize::COMP_FOUR_BYTES => { + header.regenerated_size == x[4:18] as u20 && + header.compressed_size == x[18:32] as u20 + }, + LiteralsHeaderSize::COMP_FIVE_BYTES => { + header.regenerated_size == x[4:22] as u20 && + header.compressed_size == x[22:40] as u20 + }, + _ => false + } + }; + length_bytes_equivalence && raw_length_equivalence && regen_comp_size_equivalence +} + +pub enum LiteralsHeaderDecoderStatus : u1 { + OKAY = 0, + ERROR = 1, +} + +pub struct LiteralsHeaderDecoderReq { + addr: uN[ADDR_W], +} + +pub struct LiteralsHeaderDecoderResp { + header: LiteralsHeader, + length: u3, + status: LiteralsHeaderDecoderStatus, +} + +pub proc LiteralsHeaderDecoder { + + type Req = LiteralsHeaderDecoderReq; + type Resp = LiteralsHeaderDecoderResp; + type Status = LiteralsHeaderDecoderStatus; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; + + req_r: chan in; + resp_s: chan out; + + init {} + + config( + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, + + req_r: chan in, + resp_s: chan out, + ) { + (mem_rd_req_s, mem_rd_resp_r, req_r, resp_s) + } + + next(state: ()) { + let tok = join(); + + let (tok, decode_request) = recv(tok, req_r); + send(tok, mem_rd_req_s, MemReaderReq { + addr: decode_request.addr, + // max number of bytes that the header can have, see RFC8878 Section 3.1.1.3.1.1. + length: uN[AXI_ADDR_W]:5, + }); + // TODO: handle multiple receives on mem_rd_resp_r when AXI_DATA_W < 40 + const_assert!(AXI_DATA_W >= u32:64); + let (tok, raw) = recv(tok, mem_rd_resp_r); + let (header, length) = parse_literals_header(raw.data[:40]); + send(tok, resp_s, Resp { + header: header, + length: length, + status: match (raw.status) { + MemReaderStatus::OKAY => Status::OKAY, + MemReaderStatus::ERROR => Status::ERROR, + _ => fail!("literals_header_decoder_status_unreachable", Status::OKAY), + } + }); + } +} + +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_ADDR_W = u32:32; + +#[test_proc] +proc LiteralsHeaderDecoderTest { + type Req = LiteralsHeaderDecoderReq; + type Resp = LiteralsHeaderDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + terminator: chan out; + + mem_rd_req_r: chan in; + mem_rd_resp_s: chan out; + req_s: chan out; + resp_r: chan in; + + init {} + + config(terminator: chan out) { + + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + spawn LiteralsHeaderDecoder ( + mem_rd_req_s, mem_rd_resp_r, req_r, resp_s + ); + + ( + terminator, + mem_rd_req_r, mem_rd_resp_s, + req_s, resp_r + ) + } + + next(state: ()) { + let tok = join(); + + // test data format: raw header, expected size in bytes, expected parsed header + let tests: (u40, u3, LiteralsHeader)[16] = [ + // 2 bits block type == RAW, 1 bit size_format == 0, 5 bits regenerated_size + (u40:0b10100_0_00, u3:1, LiteralsHeader { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0b10100, + compressed_size: u20:0b10100, + }), + // 2 bits block type == RAW, 2 bit size_format == 1, 12 bits regenerated_size + (u40:0b101010101010_01_00, u3:2, LiteralsHeader { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0b101010101010, + compressed_size: u20:0b101010101010, + }), + // 2 bits block type == RAW, 1 bit size_format == 2, 5 bits regenerated_size + (u40:0b10101_0_00, u3:1, LiteralsHeader { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0b10101, + compressed_size: u20:0b10101, + }), + // 2 bits block type == RAW, 2 bit size_format == 3, 20 bits regenerated_size + (u40:0b10101010101010101010_11_00, u3:3, LiteralsHeader { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0b10101010101010101010, + compressed_size: u20:0b10101010101010101010, + }), + + // 2 bits block type == RLE, 1 bit size_format == 0, 5 bits regenerated_size + (u40:0b10100_0_01, u3:1, LiteralsHeader { + literal_type: LiteralsBlockType::RLE, + regenerated_size: u20:0b10100, + compressed_size: u20:1, + }), + // 2 bits block type == RLE, 2 bits size_format == 1, 12 bits regenerated_size + (u40:0b101010101010_01_01, u3:2, LiteralsHeader { + literal_type: LiteralsBlockType::RLE, + regenerated_size: u20:0b101010101010, + compressed_size: u20:1, + }), + // 2 bits block type == RLE, 1 bit size_format == 2, 5 bits regenerated_size + (u40:0b10101_0_01, u3:1, LiteralsHeader { + literal_type: LiteralsBlockType::RLE, + regenerated_size: u20:0b10101, + compressed_size: u20:1, + }), + // 2 bits block type == RLE, 2 bits size_format == 3, 20 bits regenerated_size + (u40:0b10101010101010101010_11_01, u3:3, LiteralsHeader { + literal_type: LiteralsBlockType::RLE, + regenerated_size: u20:0b10101010101010101010, + compressed_size: u20:1, + }), + + // 2 bits block type == COMPRESSED, 2 bits size_format == 0, 10 bits regenerated_size and compressed_size + (u40:0b1010101010_0101010101_00_10, u3:3, LiteralsHeader { + literal_type: LiteralsBlockType::COMP, + regenerated_size: u20:0b0101010101, + compressed_size: u20:0b1010101010, + }), + // 2 bits block type == COMPRESSED, 2 bits size_format == 1, 10 bits regenerated_size and compressed_size + (u40:0b1010101010_0101010101_01_10, u3:3, LiteralsHeader { + literal_type: LiteralsBlockType::COMP_4, + regenerated_size: u20:0b0101010101, + compressed_size: u20:0b1010101010, + }), + // 2 bits block type == COMPRESSED, 2 bits size_format == 2, 14 bits regenerated_size and compressed_size + (u40:0b10101010101010_01010101010101_10_10, u3:4, LiteralsHeader { + literal_type: LiteralsBlockType::COMP_4, + regenerated_size: u20:0b01010101010101, + compressed_size: u20:0b10101010101010, + }), + // 2 bits block type == COMPRESSED, 2 bits size_format == 3, 18 bits regenerated_size and compressed_size + (u40:0b101010101010101010_010101010101010101_11_10, u3:5, LiteralsHeader { + literal_type: LiteralsBlockType::COMP_4, + regenerated_size: u20:0b010101010101010101, + compressed_size: u20:0b101010101010101010, + }), + + // 2 bits block type == TREELESS, 2 bits size_format == 0, 10 bits regenerated_size and compressed_size + (u40:0b1010101010_0101010101_00_11, u3:3, LiteralsHeader { + literal_type: LiteralsBlockType::TREELESS, + regenerated_size: u20:0b0101010101, + compressed_size: u20:0b1010101010, + }), + // 2 bits block type == TREELESS, 2 bits size_format == 1, 10 bits regenerated_size and compressed_size + (u40:0b1010101010_0101010101_01_11, u3:3, LiteralsHeader { + literal_type: LiteralsBlockType::TREELESS_4, + regenerated_size: u20:0b0101010101, + compressed_size: u20:0b1010101010, + }), + // 2 bits block type == TREELESS, 2 bits size_format == 2, 14 bits regenerated_size and compressed_size + (u40:0b10101010101010_01010101010101_10_11, u3:4, LiteralsHeader { + literal_type: LiteralsBlockType::TREELESS_4, + regenerated_size: u20:0b01010101010101, + compressed_size: u20:0b10101010101010, + }), + // 2 bits block type == TREELESS, 2 bits size_format == 3, 18 bits regenerated_size and compressed_size + (u40:0b101010101010101010_010101010101010101_11_11, u3:5, LiteralsHeader { + literal_type: LiteralsBlockType::TREELESS_4, + regenerated_size: u20:0b010101010101010101, + compressed_size: u20:0b101010101010101010, + }), + ]; + const ADDR = uN[TEST_AXI_ADDR_W]:0xDEAD; + + // positive cases + let tok = for ((_, (test_vec, expected_length, expected_header)), tok): ((u32, (u40, u3, LiteralsHeader)), token) in enumerate(tests) { + send(tok, req_s, Req { + addr: ADDR, + }); + let (tok, req) = recv(tok, mem_rd_req_r); + assert_eq(req, MemReaderReq { + addr: ADDR, + length: uN[TEST_AXI_ADDR_W]:5 + }); + let tok = send(tok, mem_rd_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: test_vec as uN[TEST_AXI_DATA_W], + length: uN[TEST_AXI_ADDR_W]:5, + last: true, + }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, LiteralsHeaderDecoderResp { + header: expected_header, + status: LiteralsHeaderDecoderStatus::OKAY, + length: expected_length, + }); + tok + }(tok); + + // negative case: AXI Error + send(tok, req_s, Req { + addr: ADDR, + }); + let (tok, req) = recv(tok, mem_rd_req_r); + assert_eq(req, MemReaderReq { + addr: ADDR, + length: uN[TEST_AXI_ADDR_W]:5 + }); + let tok = send(tok, mem_rd_resp_s, MemReaderResp { + status: MemReaderStatus::ERROR, + data: uN[TEST_AXI_DATA_W]:0, + length: uN[TEST_AXI_ADDR_W]:0, + last: true, + }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp.status, LiteralsHeaderDecoderStatus::ERROR); + + send(join(), terminator, true); + } +} + +proc LiteralsHeaderDecoderInst { + type Req = LiteralsHeaderDecoderReq; + type Resp = LiteralsHeaderDecoderResp; + type ReaderReq = mem_reader::MemReaderReq; + type ReaderResp = mem_reader::MemReaderResp; + + reader_req_s: chan out; + reader_resp_r: chan in; + + decode_req_r: chan in; + decode_resp_s: chan out; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + decode_req_r: chan in, + decode_resp_s: chan out, + ) { + spawn LiteralsHeaderDecoder( + reader_req_s, + reader_resp_r, + decode_req_r, + decode_resp_s + ); + (reader_req_s, reader_resp_r, decode_req_r, decode_resp_s) + } + + init {} + + next(state: ()) {} +} diff --git a/xls/modules/zstd/ram_wr_handler.x b/xls/modules/zstd/ram_wr_handler.x index a59fd0b256..c7891e270e 100644 --- a/xls/modules/zstd/ram_wr_handler.x +++ b/xls/modules/zstd/ram_wr_handler.x @@ -19,7 +19,7 @@ import std; import xls.examples.ram; -proc RamWrRespHandler { +pub proc RamWrRespHandler { type Reset = bool; type WriteCnt = bits[CNT_WIDTH]; type WriteResp = ram::WriteResp; diff --git a/xls/modules/zstd/sequence_conf_dec.x b/xls/modules/zstd/sequence_conf_dec.x new file mode 100644 index 0000000000..166df10d8c --- /dev/null +++ b/xls/modules/zstd/sequence_conf_dec.x @@ -0,0 +1,342 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.common; + +type CompressionMode = common::CompressionMode; +type SequenceConf = common::SequenceConf; + +enum SequenceHeaderSize : u2 { + TWO_BYTES = 0, + THREE_BYTES = 1, + FOUR_BYTES = 2, +} + +fn parse_sequence_first_byte(byte :u8) -> SequenceHeaderSize { + if byte == u8:0 { + SequenceHeaderSize::TWO_BYTES + } else if byte == u8:255 { + SequenceHeaderSize::FOUR_BYTES + } else if byte[7:] == u1:1 { + SequenceHeaderSize::THREE_BYTES + } else { + SequenceHeaderSize::TWO_BYTES + } +} + +fn extract_seq_mode(byte: u8) -> (CompressionMode, CompressionMode, CompressionMode) { + (byte[2:4] as CompressionMode, + byte[4:6] as CompressionMode, + byte[6:] as CompressionMode) +} + +pub fn parse_sequence_conf(header: u32) -> (SequenceConf, u3) { + let header_size = parse_sequence_first_byte(header[:8]); + let sum1 = (header[0:7] ++ header[8:16]) as u17; + let sum2 = sum1 + (header[16:24] ++ u8:0) as u17 ; + match(header_size) { + SequenceHeaderSize::TWO_BYTES => { + let (match_mode, offset_mode, literals_mode) = extract_seq_mode(header[8:16]); + (SequenceConf{ + sequence_count: header[:8] as u17, + match_mode: match_mode, + offset_mode: offset_mode, + literals_mode: literals_mode, + }, u3:2) + }, + SequenceHeaderSize::THREE_BYTES => { + let (match_mode, offset_mode, literals_mode) = extract_seq_mode(header[16:24]); + (SequenceConf{ + sequence_count: sum1, + match_mode: match_mode, + offset_mode: offset_mode, + literals_mode: literals_mode, + }, u3:3) + }, + SequenceHeaderSize::FOUR_BYTES => { + let (match_mode, offset_mode, literals_mode) = extract_seq_mode(header[24:32]); + (SequenceConf{ + sequence_count: sum2, + match_mode: match_mode, + offset_mode: offset_mode, + literals_mode: literals_mode, + }, u3:4) + }, + _ => (zero!(), u3:0) + // fail!() doesn't work with quicktest, JIT failes to translate such function + // _ => fail!("Incorrect_header_size", zero!()) + } +} + +#[quickcheck(test_count=50000)] +fn test_parse_sequence_conf(x: u32) -> bool { + // let length = parse_sequence_first_byte(x[0:8]); + let (seq_conf, length) = parse_sequence_conf(x); + let byte0 = x[0:8]; + let byte1 = x[8:16]; + let byte2 = x[16:24]; + + if x[0:8] < u8:128 { + length == u3:2 && seq_conf.sequence_count == byte0 as u17 + } else if x[0:8] < u8:255 { + length == u3:3 && seq_conf.sequence_count == (((byte0 - u8:128) as u17) << u8:8) as u17 + byte1 as u17 + } else { + length == u3:4 && seq_conf.sequence_count == u17:0x7f00 + byte1 as u17 + ((byte2 as u17) << u8:8) as u17 + } +} + + +pub enum SequenceConfDecoderStatus : u1 { + OKAY = 0, + ERROR = 1, +} + +pub struct SequenceConfDecoderReq { + addr: uN[ADDR_W], +} + +pub struct SequenceConfDecoderResp { + header: SequenceConf, + length: u3, + status: SequenceConfDecoderStatus, +} + +pub proc SequenceConfDecoder { + + type Req = SequenceConfDecoderReq; + type Resp = SequenceConfDecoderResp; + type Status = SequenceConfDecoderStatus; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; + + req_r: chan in; + resp_s: chan out; + + init {} + + config( + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, + + req_r: chan in, + resp_s: chan out, + ) { + (mem_rd_req_s, mem_rd_resp_r, req_r, resp_s) + } + + next(state: ()) { + let tok = join(); + + let (tok, decode_request) = recv(tok, req_r); + send(tok, mem_rd_req_s, MemReaderReq { + addr: decode_request.addr, + // max number of bytes that the header can have, see RFC8878 Section 3.1.1.3.2.1. + length: uN[AXI_ADDR_W]:4, + }); + // TODO: handle multiple receives on mem_rd_resp_r when AXI_DATA_W < 32 + const_assert!(AXI_DATA_W >= u32:32); + let (tok, raw) = recv(tok, mem_rd_resp_r); + let (header, length) = parse_sequence_conf(raw.data[:32]); + send(tok, resp_s, Resp { + header: header, + length: length, + status: match (raw.status) { + MemReaderStatus::OKAY => Status::OKAY, + MemReaderStatus::ERROR => Status::ERROR, + _ => fail!("literals_header_decoder_status_unreachable", Status::OKAY), + } + }); + } +} + +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_ADDR_W = u32:32; + +#[test_proc] +proc SequenceConfDecoderTest { + type Req = SequenceConfDecoderReq; + type Resp = SequenceConfDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + terminator: chan out; + + mem_rd_req_r: chan in; + mem_rd_resp_s: chan out; + req_s: chan out; + resp_r: chan in; + + init {} + + config(terminator: chan out) { + + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + spawn SequenceConfDecoder ( + mem_rd_req_s, mem_rd_resp_r, req_r, resp_s + ); + + ( + terminator, + mem_rd_req_r, mem_rd_resp_s, + req_s, resp_r + ) + } + + next(state: ()) { + let tok = join(); + + // test data format: raw header, expected size in bytes, expected parsed header + let tests: (u32, u3, SequenceConf)[8] = [ + (u32:0x00_00, u3:2, SequenceConf { + sequence_count: u17:0, + literals_mode: CompressionMode::PREDEFINED, + offset_mode: CompressionMode::PREDEFINED, + match_mode: CompressionMode::PREDEFINED, + }), + (u32:0x6C_00, u3:2, SequenceConf { + sequence_count: u17:0, + literals_mode: CompressionMode::RLE, + offset_mode: CompressionMode::COMPRESSED, + match_mode: CompressionMode::REPEAT, + }), + (u32:0xE4_01, u3:2, SequenceConf { + sequence_count: u17:0x01, + literals_mode: CompressionMode::REPEAT, + offset_mode: CompressionMode::COMPRESSED, + match_mode: CompressionMode::RLE, + }), + (u32:0xAC_7F, u3:2, SequenceConf { + sequence_count: u17:0x7F, + literals_mode: CompressionMode::COMPRESSED, + offset_mode: CompressionMode::COMPRESSED, + match_mode: CompressionMode::REPEAT, + }), + (u32:0x84_0080, u3:3, SequenceConf { + sequence_count: u17:0, + literals_mode: CompressionMode::COMPRESSED, + offset_mode: CompressionMode::PREDEFINED, + match_mode: CompressionMode::RLE, + }), + (u32:0x18_FFFE, u3:3, SequenceConf { + sequence_count: u17:0x7EFF, + literals_mode: CompressionMode::PREDEFINED, + offset_mode: CompressionMode::RLE, + match_mode: CompressionMode::COMPRESSED, + }), + (u32:0x70_0000FF, u3:4, SequenceConf { + sequence_count: u17:0x7F00, + literals_mode: CompressionMode::RLE, + offset_mode: CompressionMode::REPEAT, + match_mode: CompressionMode::PREDEFINED, + }), + (u32:0x68_FFFFFF, u3:4, SequenceConf { + sequence_count: u17:0x17EFF, + literals_mode: CompressionMode::RLE, + offset_mode: CompressionMode::COMPRESSED, + match_mode: CompressionMode::COMPRESSED, + }), + ]; + const ADDR = uN[TEST_AXI_ADDR_W]:0xDEAD; + + // positive cases + let tok = for ((_, (test_vec, expected_length, expected_header)), tok): ((u32, (u32, u3, SequenceConf)), token) in enumerate(tests) { + send(tok, req_s, Req { + addr: ADDR, + }); + let (tok, req) = recv(tok, mem_rd_req_r); + assert_eq(req, MemReaderReq { + addr: ADDR, + length: uN[TEST_AXI_ADDR_W]:4 + }); + let tok = send(tok, mem_rd_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: test_vec as uN[TEST_AXI_DATA_W], + length: uN[TEST_AXI_ADDR_W]:4, + last: true, + }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, SequenceConfDecoderResp { + header: expected_header, + status: SequenceConfDecoderStatus::OKAY, + length: expected_length, + }); + tok + }(tok); + + // negative case: AXI Error + send(tok, req_s, Req { + addr: ADDR, + }); + let (tok, req) = recv(tok, mem_rd_req_r); + assert_eq(req, MemReaderReq { + addr: ADDR, + length: uN[TEST_AXI_ADDR_W]:4 + }); + let tok = send(tok, mem_rd_resp_s, MemReaderResp { + status: MemReaderStatus::ERROR, + data: uN[TEST_AXI_DATA_W]:0, + length: uN[TEST_AXI_ADDR_W]:0, + last: true, + }); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp.status, SequenceConfDecoderStatus::ERROR); + + send(join(), terminator, true); + } +} + +proc SequenceConfDecoderInst { + type Req = SequenceConfDecoderReq; + type Resp = SequenceConfDecoderResp; + type ReaderReq = mem_reader::MemReaderReq; + type ReaderResp = mem_reader::MemReaderResp; + + reader_req_s: chan out; + reader_resp_r: chan in; + + decode_req_r: chan in; + decode_resp_s: chan out; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + decode_req_r: chan in, + decode_resp_s: chan out, + ) { + spawn SequenceConfDecoder( + reader_req_s, + reader_resp_r, + decode_req_r, + decode_resp_s + ); + (reader_req_s, reader_resp_r, decode_req_r, decode_resp_s) + } + + init {} + + next(state: ()) {} +} From 95eec628397479ede58c91f515cf6e878132be1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Tue, 16 Apr 2024 18:58:28 +0200 Subject: [PATCH 36/85] modules: Add ShiftBuffer and RefillingShiftBuffer implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Robert Winkler Co-authored-by: Pawel Czarnecki Signed-off-by: Robert Winkler Signed-off-by: Pawel Czarnecki Signed-off-by: Krzysztof Obłonczek --- xls/modules/shift_buffer/BUILD | 285 ++++++ xls/modules/shift_buffer/fixme.x | 52 ++ xls/modules/shift_buffer/math.x | 97 ++ xls/modules/shift_buffer/shift_buffer.x | 641 +++++++++++++ xls/modules/shift_buffer/shift_buffer_inst.x | 71 ++ xls/modules/zstd/BUILD | 167 ++-- xls/modules/zstd/refilling_shift_buffer.x | 889 +++++++++++++++++++ xls/modules/zstd/shift_buffer.x | 246 ----- 8 files changed, 2117 insertions(+), 331 deletions(-) create mode 100644 xls/modules/shift_buffer/BUILD create mode 100644 xls/modules/shift_buffer/fixme.x create mode 100644 xls/modules/shift_buffer/math.x create mode 100644 xls/modules/shift_buffer/shift_buffer.x create mode 100644 xls/modules/shift_buffer/shift_buffer_inst.x create mode 100644 xls/modules/zstd/refilling_shift_buffer.x delete mode 100644 xls/modules/zstd/shift_buffer.x diff --git a/xls/modules/shift_buffer/BUILD b/xls/modules/shift_buffer/BUILD new file mode 100644 index 0000000000..201bbf6fcc --- /dev/null +++ b/xls/modules/shift_buffer/BUILD @@ -0,0 +1,285 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# This is a pipeline-aware data buffer. The implementation aligns incoming data +# before it enters the buffer and mutates its state. + +load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route") +load("@rules_hdl//synthesis:build_defs.bzl", "benchmark_synth", "synthesize_rtl") +load("@rules_hdl//verilog:providers.bzl", "verilog_library") +load( + "//xls/build_rules:xls_build_defs.bzl", + "xls_benchmark_ir", + "xls_benchmark_verilog", + "xls_dslx_ir", + "xls_dslx_library", + "xls_dslx_opt_ir", + "xls_dslx_test", + "xls_dslx_verilog", + "xls_ir_opt_ir", + "xls_ir_verilog", +) + +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//xls:xls_users"], + licenses = ["notice"], +) + +xls_dslx_library( + name = "fixme_dslx", + srcs = ["fixme.x"], +) + +xls_dslx_test( + name = "fixme_dslx_test", + library = ":fixme_dslx", +) + +xls_dslx_library( + name = "math_dslx", + srcs = ["math.x"], + deps = [":fixme_dslx"] +) + +xls_dslx_test( + name = "math_dslx_test", + library = ":math_dslx", +) + +## ShiftBuffer + +xls_dslx_library( + name = "shift_buffer_dslx", + srcs = ["shift_buffer.x"], + deps = [ + ":math_dslx", + ":fixme_dslx", + ], +) + +xls_dslx_test( + name = "shift_buffer_dslx_test", + library = ":shift_buffer_dslx", +) + +xls_dslx_library( + name = "shift_buffer_inst_dslx", + srcs = ["shift_buffer_inst.x"], + deps = [ + ":shift_buffer_dslx", + ], +) + +# ShiftBufferAligner + +xls_dslx_verilog( + name = "shift_buffer_aligner_verilog", + codegen_args = { + "module_name": "ShiftBufferAligner", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferAlignerInst", + library = ":shift_buffer_inst_dslx", + opt_ir_args = { + "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferAlignerInst__ShiftBufferAligner_0__64_128_7_next", + }, + verilog_file = "shift_buffer_aligner.v", +) + +xls_benchmark_ir( + name = "shift_buffer_aligner_opt_ir_benchmark", + src = ":shift_buffer_aligner_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "shift_buffer_aligner_verilog_lib", + srcs = [ + ":shift_buffer_aligner.v", + ], +) + +synthesize_rtl( + name = "shift_buffer_aligner_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBufferAligner", + deps = [ + ":shift_buffer_aligner_verilog_lib", + ], +) + +benchmark_synth( + name = "shift_buffer_aligner_benchmark_synth", + synth_target = ":shift_buffer_aligner_synth_asap7", +) + +place_and_route( + name = "shift_buffer_aligner_place_and_route", + clock_period = "650", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_aligner_synth_asap7", + target_die_utilization_percentage = "5", +) + +xls_benchmark_verilog( + name = "shift_buffer_aligner_verilog_benchmark", + verilog_target = "shift_buffer_aligner_verilog", +) + +## ShiftBufferStorage + +xls_dslx_verilog( + name = "shift_buffer_storage_verilog", + codegen_args = { + "module_name": "ShiftBufferStorage", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferStorageInst", + library = ":shift_buffer_inst_dslx", + opt_ir_args = { + "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferStorageInst__ShiftBufferStorage_0__64_7_next", + }, + verilog_file = "shift_buffer_storage.v", +) + +xls_benchmark_ir( + name = "shift_buffer_storage_opt_ir_benchmark", + src = ":shift_buffer_storage_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "shift_buffer_storage_verilog_lib", + srcs = [ + ":shift_buffer_storage.v", + ], +) + +synthesize_rtl( + name = "shift_buffer_storage_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBufferStorage", + deps = [ + ":shift_buffer_storage_verilog_lib", + ], +) + +benchmark_synth( + name = "shift_buffer_storage_benchmark_synth", + synth_target = ":shift_buffer_storage_synth_asap7", +) + +place_and_route( + name = "shift_buffer_storage_place_and_route", + clock_period = "650", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_storage_synth_asap7", + target_die_utilization_percentage = "5", +) + +xls_benchmark_verilog( + name = "shift_buffer_storage_verilog_benchmark", + verilog_target = "shift_buffer_storage_verilog", +) + +## ShiftBuffer + +xls_dslx_verilog( + name = "shift_buffer_verilog", + codegen_args = { + "module_name": "ShiftBuffer", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferInst", + library = ":shift_buffer_inst_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferInst__ShiftBuffer_0__ShiftBufferStorage_0__64_7_next", + }, + verilog_file = "shift_buffer.v", +) + +xls_benchmark_ir( + name = "shift_buffer_opt_ir_benchmark", + src = ":shift_buffer_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "shift_buffer_verilog_lib", + srcs = [ + ":shift_buffer.v", + ], +) + +synthesize_rtl( + name = "shift_buffer_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBuffer", + deps = [ + ":shift_buffer_verilog_lib", + ], +) + +benchmark_synth( + name = "shift_buffer_benchmark_synth", + synth_target = ":shift_buffer_synth_asap7", +) + +place_and_route( + name = "shift_buffer_place_and_route", + clock_period = "650", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_synth_asap7", + target_die_utilization_percentage = "5", +) + +xls_benchmark_verilog( + name = "shift_buffer_verilog_benchmark", + verilog_target = "shift_buffer_verilog", +) diff --git a/xls/modules/shift_buffer/fixme.x b/xls/modules/shift_buffer/fixme.x new file mode 100644 index 0000000000..9fa79247c1 --- /dev/null +++ b/xls/modules/shift_buffer/fixme.x @@ -0,0 +1,52 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +pub fn fast_if(cond: bool, arg1: uN[N], arg2: uN[N]) -> uN[N] { + let mask = if cond { !bits[N]:0 } else { bits[N]:0 }; + (arg1 & mask) | (arg2 & !mask) +} + +pub fn fast_if_tuple_2 + (cond: bool, arg1: (uN[N], uN[M]), arg2: (uN[N], uN[M])) -> (uN[N], uN[M]) { + (fast_if(cond, arg1.0, arg2.0), fast_if(cond, arg1.1, arg2.1)) +} + +pub fn fast_if_tuple_3 + (cond: bool, arg1: (uN[N], uN[M], uN[O]), arg2: (uN[N], uN[M], uN[O])) + -> (uN[N], uN[M], uN[O]) { + (fast_if(cond, arg1.0, arg2.0), fast_if(cond, arg1.1, arg2.1), fast_if(cond, arg1.2, arg2.2)) +} + +#[test] +fn fast_if_test() { + assert_eq(if true { u32:1 } else { u32:5 }, fast_if(true, u32:1, u32:5)); + assert_eq(if false { u32:1 } else { u32:5 }, fast_if(false, u32:1, u32:5)); + + assert_eq( + if true { + trace_fmt!("if: true"); + u16:74 + } else { + trace_fmt!("if: false"); + u16:32 + }, + fast_if(true, { + trace_fmt!("fast_if: true"); + u16:74 + }, { + trace_fmt!("fast_if: false"); + u16:32 + }) + ); +} diff --git a/xls/modules/shift_buffer/math.x b/xls/modules/shift_buffer/math.x new file mode 100644 index 0000000000..057a843556 --- /dev/null +++ b/xls/modules/shift_buffer/math.x @@ -0,0 +1,97 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; +import xls.modules.shift_buffer.fixme; + +// Log-depth shift bits left +pub fn logshiftl(n: bits[N], r: bits[R]) -> bits[N] { + for (i, y) in u32:0..R { + fixme::fast_if(r[i+:u1], { y << (bits[R]:1 << i) }, { y }) + }(n as bits[N]) +} + +#[test] +fn logshiftl_test() { + // Test varying base + assert_eq(logshiftl(bits[64]:0, bits[6]:3), bits[64]:0 << u32:3); + assert_eq(logshiftl(bits[64]:1, bits[6]:3), bits[64]:1 << u32:3); + assert_eq(logshiftl(bits[64]:2, bits[6]:3), bits[64]:2 << u32:3); + assert_eq(logshiftl(bits[64]:3, bits[6]:3), bits[64]:3 << u32:3); + assert_eq(logshiftl(bits[64]:4, bits[6]:3), bits[64]:4 << u32:3); + + // Test varying exponent + assert_eq(logshiftl(bits[64]:50, bits[6]:0), bits[64]:50 << u32:0); + assert_eq(logshiftl(bits[64]:50, bits[6]:1), bits[64]:50 << u32:1); + assert_eq(logshiftl(bits[64]:50, bits[6]:2), bits[64]:50 << u32:2); + assert_eq(logshiftl(bits[64]:50, bits[6]:3), bits[64]:50 << u32:3); + assert_eq(logshiftl(bits[64]:50, bits[6]:4), bits[64]:50 << u32:4); + + // Test overflow + let max = std::unsigned_max_value(); + assert_eq(logshiftl(max, u4:4), max << u4:4); + assert_eq(logshiftl(max, u4:5), max << u4:5); + assert_eq(logshiftl(max, u4:15), max << u4:15); + assert_eq(logshiftl(bits[24]:0xc0ffee, u8:12), bits[24]:0xfee000); +} + + +// Log-depth shift bits right +pub fn logshiftr(n: bits[N], r: bits[R]) -> bits[N] { + for (i, y) in u32:0..R { + fixme::fast_if(r[i+:u1], { y >> (bits[R]:1 << i) }, { y }) + }(n as bits[N]) +} + +#[test] +fn logshiftr_test() { + // Test varying base + assert_eq(logshiftr(bits[64]:0x0fac4e782, bits[6]:3), bits[64]:0x0fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x1fac4e782, bits[6]:3), bits[64]:0x1fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x2fac4e782, bits[6]:3), bits[64]:0x2fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x3fac4e782, bits[6]:3), bits[64]:0x3fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x4fac4e782, bits[6]:3), bits[64]:0x4fac4e782 >> u32:3); + + // Test varying exponent + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:0), bits[64]:0x50fac4e782 >> u32:0); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:1), bits[64]:0x50fac4e782 >> u32:1); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:2), bits[64]:0x50fac4e782 >> u32:2); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:3), bits[64]:0x50fac4e782 >> u32:3); + assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:4), bits[64]:0x50fac4e782 >> u32:4); + + // Test overflow + let max = std::unsigned_max_value(); + assert_eq(logshiftr(max, u4:4), max >> u4:4); + assert_eq(logshiftr(max, u4:5), max >> u4:5); + assert_eq(logshiftr(max, u4:15), max >> u4:15); + assert_eq(logshiftr(bits[24]:0xc0ffee, u8:12), bits[24]:0x000c0f); +} + +// Return given value with m first bits masked +pub fn mask(n: bits[N], m: bits[M]) -> bits[N] { + n & (std::mask_bits() >> (N as bits[M] - m)) +} + +#[test] +fn mask_test() { + assert_eq(mask(u8:0b11111111, u4:0), u8:0b00000000); + assert_eq(mask(u8:0b11111111, u4:1), u8:0b00000001); + assert_eq(mask(u8:0b11111111, u4:2), u8:0b00000011); + assert_eq(mask(u8:0b11111111, u4:4), u8:0b00001111); + assert_eq(mask(u8:0b11111111, u4:8), u8:0b11111111); + assert_eq(mask(u8:0b11111111, u4:9), u8:0b00000000); // FIXME: sketchy result, I would expect + // 0b11111111 +} + + diff --git a/xls/modules/shift_buffer/shift_buffer.x b/xls/modules/shift_buffer/shift_buffer.x new file mode 100644 index 0000000000..add66ffe3e --- /dev/null +++ b/xls/modules/shift_buffer/shift_buffer.x @@ -0,0 +1,641 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; +import xls.modules.shift_buffer.fixme; +import xls.modules.shift_buffer.math; + +pub enum ShiftBufferStatus : u1 { + OK = 0, + ERROR = 1, +} + +pub fn length_width(data_width: u32) -> u32 { + std::clog2(data_width + u32:1) +} + +// Common definition for buffer input and output payload +pub struct ShiftBufferPacket { + data: uN[DATA_WIDTH], + length: uN[LENGTH_WIDTH], +} + +// Output structure - packet with embedded status of the buffer operation +pub type ShiftBufferOutput = ShiftBufferPacket; + +// Buffer pop command +pub struct ShiftBufferCtrl { + length: uN[LENGTH_WIDTH] +} + +struct ShiftBufferAlignerState { + ptr: uN[LENGTH_WIDTH] +} + +pub proc ShiftBufferAligner< + DATA_WIDTH: u32, + LENGTH_WIDTH: u32 = {length_width(DATA_WIDTH)}, + DATA_WIDTH_X2: u32 = {DATA_WIDTH * u32:2}, +> { + type Length = uN[LENGTH_WIDTH]; + type Data = uN[DATA_WIDTH]; + type DataX2 = uN[DATA_WIDTH_X2]; + + type State = ShiftBufferAlignerState; + type Input = ShiftBufferPacket; + type Inter = ShiftBufferPacket; + + input_r: chan in; + inter_s: chan out; + + config( + input_r: chan in, + inter_s: chan out, + ) { + (input_r, inter_s) + } + + init {zero!()} + + next(state: State) { + // FIXME: Remove when https://github.com/google/xls/issues/1368 is resolved + type Inter = ShiftBufferPacket; + + let tok = join(); + + let (tok0, data) = recv(tok, input_r); + let tok0 = send(tok0, inter_s, Inter { + length: data.length, + data: math::logshiftl(data.data as DataX2, state.ptr), + }); + + State {ptr: (state.ptr + data.length) % (DATA_WIDTH as Length) } + } +} + +const ALIGNER_TEST_DATA_WIDTH = u32:64; +const ALIGNER_TEST_LENGTH_WIDTH = length_width(ALIGNER_TEST_DATA_WIDTH); +const ALIGNER_TEST_DATA_WIDTH_X2 = ALIGNER_TEST_DATA_WIDTH * u32:2; + +#[test_proc] +proc ShiftBufferAlignerTest { + terminator: chan out; + type Input = ShiftBufferPacket; + type Inter = ShiftBufferPacket; + + type Data = uN[ALIGNER_TEST_DATA_WIDTH]; + type Length = uN[ALIGNER_TEST_LENGTH_WIDTH]; + type DataX2 = uN[ALIGNER_TEST_DATA_WIDTH_X2]; + + input_s: chan out; + inter_r: chan in; + + config(terminator: chan out) { + let (input_s, input_r) = chan("input"); + let (inter_s, inter_r) = chan("inter"); + + spawn ShiftBufferAligner(input_r, inter_s); + + (terminator, input_s, inter_r) + } + + init { } + + next(state: ()) { + let tok = send(join(), input_s, Input { data: Data:0xAABB_CCDD, length: Length:32}); + let tok = send(tok, input_s, Input { data: Data:0x1122, length: Length:16}); + let tok = send(tok, input_s, Input { data: Data:0x33, length: Length:8}); + let tok = send(tok, input_s, Input { data: Data:0x44, length: Length:8}); + let tok = send(tok, input_s, Input { data: Data:0xFFFF, length: Length:4}); + let tok = send(tok, input_s, Input { data: Data:0x0, length: Length:0}); + let tok = send(tok, input_s, Input { data: Data:0x0, length: Length:4}); + let tok = send(tok, input_s, Input { data: Data:0x1, length: Length:1}); + let tok = send(tok, input_s, Input { data: Data:0xF, length: Length:3}); + let tok = send(tok, input_s, Input { data: Data:0xF, length: Length:4}); + + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2: 0xAABB_CCDD, length: Length: 32}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2: 0x1122_0000_0000, length: Length: 16}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2: 0x33_0000_0000_0000, length: Length: 8}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2: 0x4400_0000_0000_0000, length: Length: 8}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2:0xFFFF, length: Length:4}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2:0x0, length: Length:0}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2:0x00, length: Length:4}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2:0x100, length: Length:1}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2:0x1E00, length: Length:3}); + let (tok, data) = recv(tok, inter_r); + assert_eq(data, Inter { data: DataX2:0xF000, length: Length:4}); + + send(tok, terminator, true); + } +} + +struct ShiftBufferStorageState { + buffer: bits[BUFFER_WIDTH], // The storage element. + buffer_cnt: bits[LENGTH_WIDTH + u32:2], // Number of valid bits in the buffer. + read_ptr: bits[LENGTH_WIDTH + u32:2], // First occupied bit in the buffer when buffer_cnt > 0. + write_ptr: bits[LENGTH_WIDTH + u32:2], // First free bit in the buffer. + cmd: ShiftBufferCtrl, // Received command of ShiftBufferCtrl type. + cmd_valid: bool, // Field cmd is valid. +} + +pub proc ShiftBufferStorage { + type Buffer = bits[DATA_WIDTH * u32:3]; + type BufferLength = bits[LENGTH_WIDTH + u32:2]; // TODO: where does this "+ u32:2" come from? shouldn't it be number_of_bits_required_to_represent(DATA_WIDTH * u32:3)? + type Data = bits[DATA_WIDTH]; + type DataLength = bits[LENGTH_WIDTH]; + type State = ShiftBufferStorageState; + type Ctrl = ShiftBufferCtrl; + type Inter = ShiftBufferPacket; + type Output = ShiftBufferOutput; + ctrl: chan> in; + inter: chan> in; + output: chan> out; + + config( + ctrl: chan> in, + inter: chan> in, + output: chan> out, + ) { + (ctrl, inter, output) + } + + init { + type State = ShiftBufferStorageState<{DATA_WIDTH * u32:3}, LENGTH_WIDTH>; + zero!() + } + + next(state: State<{DATA_WIDTH * u32:3}, LENGTH_WIDTH>) { + type State = ShiftBufferStorageState<{DATA_WIDTH * u32:3}, LENGTH_WIDTH>; + type Ctrl = ShiftBufferCtrl; + type Inter = ShiftBufferPacket<{DATA_WIDTH * u32:2}, LENGTH_WIDTH>; + type Output = ShiftBufferOutput; + type OutputPayload = ShiftBufferPacket; + type OutputStatus = ShiftBufferStatus; + type DataLength = bits[LENGTH_WIDTH]; + // trace_fmt!("state: {:#x}", state); + + const MAX_BUFFER_CNT = (DATA_WIDTH * u32:3) as BufferLength; + + let shift_buffer_right = state.read_ptr >= (DATA_WIDTH as BufferLength); + // trace_fmt!("shift_buffer_right: {:#x}", shift_buffer_right); + let shift_data_left = + state.write_ptr >= (DATA_WIDTH as BufferLength) && !shift_buffer_right; + // trace_fmt!("shift_data_left: {:#x}", shift_data_left); + let recv_new_input = state.write_ptr < (DATA_WIDTH * u32:2) as BufferLength; + // trace_fmt!("recv_new_input: {:#x}", recv_new_input); + let has_enough_data = (state.cmd.length as BufferLength <= state.buffer_cnt); + let send_response = state.cmd_valid && has_enough_data; + // trace_fmt!("send_response: {:#x}", send_response); + let recv_new_cmd = !state.cmd_valid || send_response; + // trace_fmt!("recv_new_cmd: {:#x}", recv_new_cmd); + + let tok = join(); + + // Shift buffer if required + let (new_buffer, new_read_ptr, new_write_ptr) = if shift_buffer_right { + (state.buffer >> DATA_WIDTH, + state.read_ptr - DATA_WIDTH as BufferLength, + state.write_ptr - DATA_WIDTH as BufferLength) + } else { + (state.buffer, + state.read_ptr, + state.write_ptr) + }; + + // if (shift_buffer_right) { + // trace_fmt!("Shifted data"); + // trace_fmt!("new_buffer: {:#x}", new_buffer); + // trace_fmt!("new_read_ptr: {}", new_read_ptr); + // trace_fmt!("new_write_ptr: {}", new_write_ptr); + // } else { () }; + + // Handle incoming writes + let (tok_input, wdata, wdata_valid) = recv_if_non_blocking(tok, inter, recv_new_input, zero!()); + + let (new_buffer, new_write_ptr) = if wdata_valid { + // Shift data if required + let new_data = if shift_data_left { + wdata.data as Buffer << DATA_WIDTH + } else { + wdata.data as Buffer + }; + let new_buffer = new_buffer | new_data; + let new_write_ptr = new_write_ptr + wdata.length as BufferLength; + + (new_buffer, new_write_ptr) + } else { + (new_buffer, new_write_ptr) + }; + + // if (wdata_valid) { + // trace_fmt!("Received aligned data {:#x}", wdata); + // trace_fmt!("new_buffer: {:#x}", new_buffer); + // trace_fmt!("new_write_ptr: {}", new_write_ptr); + // } else { () }; + + // Handle incoming reads + let (tok_ctrl, new_cmd, new_cmd_valid) = + recv_if_non_blocking(tok, ctrl, recv_new_cmd, state.cmd); + + // if (new_cmd_valid) { + // trace_fmt!("Received new cmd: {}", new_cmd); + // } else {()}; + let new_cmd_valid = if recv_new_cmd { new_cmd_valid } else { state.cmd_valid }; + // Handle current read + + let (rdata, new_read_ptr) = if send_response { + let new_read_ptr = new_read_ptr + state.cmd.length as BufferLength; + let rdata = Output { + length: state.cmd.length, + data: math::mask(math::logshiftr(state.buffer, state.read_ptr) as Data, state.cmd.length), + }; + + // trace_fmt!("rdata: {:#x}", rdata); + // trace_fmt!("new_read_ptr: {}", new_read_ptr); + + (rdata, new_read_ptr) + } else { + (zero!(), new_read_ptr) + }; + + let tok = join(tok_input, tok_ctrl); + send_if(tok, output, send_response, rdata); + // if (send_response) { + // trace_fmt!("Sent out rdata: {:#x}", rdata); + // } else {()}; + + let new_buffer_cnt = new_write_ptr - new_read_ptr; + + let new_state = State { + buffer: new_buffer, + buffer_cnt: new_buffer_cnt, + read_ptr: new_read_ptr, + write_ptr: new_write_ptr, + cmd: new_cmd, + cmd_valid: new_cmd_valid, + }; + + new_state + } +} + +const STORAGE_TEST_DATA_WIDTH = u32:64; +const STORAGE_TEST_LENGTH_WIDTH = length_width(STORAGE_TEST_DATA_WIDTH); +const STORAGE_TEST_DATA_WIDTH_X2 = STORAGE_TEST_DATA_WIDTH * u32:2; + +#[test_proc] +proc ShiftBufferStorageTest { + terminator: chan out; + type Ctrl = ShiftBufferCtrl; + type Inter = ShiftBufferPacket; + type Output = ShiftBufferOutput; + type OutputPayload = ShiftBufferPacket; + type OutputStatus = ShiftBufferStatus; + + type Length = uN[STORAGE_TEST_LENGTH_WIDTH]; + type Data = uN[STORAGE_TEST_DATA_WIDTH]; + type DataX2 = uN[STORAGE_TEST_DATA_WIDTH_X2]; + + ctrl_s: chan out; + inter_s: chan out; + output_r: chan in; + + config(terminator: chan out) { + let (ctrl_s, ctrl_r) = chan("ctrl"); + let (inter_s, inter_r) = chan("inter"); + let (output_s, output_r) = chan("output"); + + spawn ShiftBufferStorage(ctrl_r, inter_r, output_s); + + (terminator, ctrl_s, inter_s, output_r) + } + + init { } + + next(state: ()) { + // Single input, single output packet 32bit buffering + let tok = send(join(), inter_s, Inter { data: DataX2: 0xAABB_CCDD, length: Length: 32}); + + // Multiple input packets, single output 32bit buffering + let tok = send(tok, inter_s, Inter { data: DataX2: 0x3344_0000_0000, length: Length: 16}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0x22_0000_0000_0000, length: Length: 8}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0x1100_0000_0000_0000, length: Length: 8}); + + // Small consecutive single input, single output 8bit buffering + let tok = send(tok, inter_s, Inter { data: DataX2: 0x55, length: Length: 8}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0x6600, length: Length: 8}); + + // Multiple input packets, single output 64bit buffering + let tok = send(tok, inter_s, Inter { data: DataX2: 0xDDEE_0000, length: Length: 16}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0xBBCC_0000_0000, length: Length: 16}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0x99AA_0000_0000_0000, length: Length: 16}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0x7788, length: Length: 16}); + + // Single input packet, single output 64bit buffering + let tok = send(tok, inter_s, Inter { data: DataX2: 0x1122_3344_5566_7788_0000, length: Length: 64}); + + // Single 64bit input packet, multiple output packets of different sizes + let tok = send(tok, inter_s, Inter { data: DataX2: 0xEEFF_0011_CCDD_BBAA_0000, length: Length: 64}); + + // Account for leftover 0xEEFF from the previous packet + let tok = send(tok, inter_s, Inter { data: DataX2: 0x1122_0000, length: Length: 16}); + // Should operate on flushed buffer + let tok = send(tok, inter_s, Inter { data: DataX2: 0x3344_0000_0000, length: Length: 16}); + + // Input packets additionally span across 2 shift buffer aligner shift domains + let tok = send(tok, inter_s, Inter { data: DataX2: 0x7788_0000_0000_0000, length: Length: 16}); + let tok = send(tok, inter_s, Inter { data: DataX2: 0x5566, length: Length: 16}); + + // Single input, single output packet 32bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0xAABB_CCDD, length: Length: 32}); + + // Multiple input packets, single output 32bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x1122_3344, length: Length: 32}); + + // Small consecutive single input, single output 8bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x55, length: Length: 8}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x66, length: Length: 8}); + + // Multiple input packets, single output 64bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:64}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x7788_99AA_BBCC_DDEE, length: Length: 64}); + + // Single input packet, single output 64bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:64}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x1122_3344_5566_7788, length: Length: 64}); + + // Single 64bit input packet, multiple output packets of different sizes + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0xAA, length: Length: 8}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0xBB, length: Length: 8}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:16}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0xCCDD, length: Length: 16}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0xEEFF_0011, length: Length: 32}); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:16}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x1122, length: Length: 16}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:16}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x3344, length: Length: 16}); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0x5566_7788, length: Length: 32}); + + // Test attempting to read more data than available in the buffer + // This should wait indefinitely, we test this by checking that we can't + // receive data over the next consecutive 100 iterations + let tok = send(tok, ctrl_s, Ctrl { length: Length:64}); + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, data_valid) = recv_non_blocking(tok, output_r, zero!()); + assert_eq(data_valid, false); + tok + }(tok); + + // Refill the buffer with more data - not enough to reply to the earlier request for 64b + let tok = send(tok, inter_s, Inter { data: DataX2: 0xDEAD_BEEF_0000, length: Length: 32}); + // Check that we can't receive still + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, data_valid) = recv_non_blocking(tok, output_r, zero!()); + assert_eq(data_valid, false); + tok + }(tok); + + // Refill buffer with enough data + let tok = send(tok, inter_s, Inter { data: DataX2: 0xF00B_A4BA_0000_0000_0000, length: Length: 32}); + // Now we should be able to receive a response for 64b request + let (tok, data) = recv(tok, output_r); + assert_eq(data, Output { data: Data: 0xF00BA4BA_DEADBEEF, length: Length: 64}); + + send(tok, terminator, true); + } +} + +pub proc ShiftBuffer { + type Input = ShiftBufferPacket; + type Ctrl = ShiftBufferCtrl; + type Inter = ShiftBufferPacket; + type Output = ShiftBufferOutput; + + config(ctrl: chan> in, input: chan> in, + output: chan> out) { + let (inter_out, inter_in) = + chan, u32:1>("inter"); + spawn ShiftBufferAligner(input, inter_out); + spawn ShiftBufferStorage(ctrl, inter_in, output); + } + + init { } + + next(state: ()) { } +} + +const TEST_DATA_WIDTH = u32:64; +const TEST_LENGTH_WIDTH = std::clog2(TEST_DATA_WIDTH) + u32:1; // TODO: other places in the code use length_width(TEST_DATA_WIDTH) which is clog2(TEST_DATA_WIDTH + 1) instead, why clog2(TEST_DATA_WIDTH) + 1 here? + +#[test_proc] +proc ShiftBufferTest { + type Input = ShiftBufferPacket; + type Ctrl = ShiftBufferCtrl; + type Output = ShiftBufferOutput; + + terminator: chan out; + input_s: chan> out; + ctrl_s: chan> out; + data_r: chan> in; + + config(terminator: chan out) { + let (input_s, input_r) = chan, u32:1>("input"); + let (ctrl_s, ctrl_r) = chan, u32:1>("ctrl"); + let (data_s, data_r) = chan, u32:1>("data"); + + spawn ShiftBuffer(ctrl_r, input_r, data_s); + + (terminator, input_s, ctrl_s, data_r) + } + + init { } + + next(state: ()) { + type Data = bits[TEST_DATA_WIDTH]; + type Length = bits[TEST_LENGTH_WIDTH]; + type Input = ShiftBufferPacket; + type Output = ShiftBufferOutput; + type OutputPayload = ShiftBufferPacket; + type OutputStatus = ShiftBufferStatus; + type Ctrl = ShiftBufferCtrl; + + let tok = send(join(), input_s, Input { data: Data:0xDD_44, length: Length:16 }); + let tok = send(tok, input_s, Input { data: Data:0xAA_11_BB_22_CC_33, length: Length:48 }); + let tok = send(tok, input_s, Input { data: Data:0xEE_55_FF_66_00_77_11_88, length: Length:64 }); + + // Single input, single output packet 32bit buffering + let tok = send(join(), input_s, Input { data: Data: 0xAABB_CCDD, length: Length: 32}); + + // Multiple input packets, single output 32bit buffering + let tok = send(tok, input_s, Input { data: Data: 0x3344, length: Length: 16}); + let tok = send(tok, input_s, Input { data: Data: 0x22, length: Length: 8}); + let tok = send(tok, input_s, Input { data: Data: 0x11, length: Length: 8}); + + // Small consecutive single input, single output 8bit buffering + let tok = send(tok, input_s, Input { data: Data: 0x55, length: Length: 8}); + let tok = send(tok, input_s, Input { data: Data: 0x66, length: Length: 8}); + + // Multiple input packets, single output 64bit buffering + let tok = send(tok, input_s, Input { data: Data: 0xDDEE, length: Length: 16}); + let tok = send(tok, input_s, Input { data: Data: 0xBBCC, length: Length: 16}); + let tok = send(tok, input_s, Input { data: Data: 0x99AA, length: Length: 16}); + let tok = send(tok, input_s, Input { data: Data: 0x7788, length: Length: 16}); + + // Single input packet, single output 64bit buffering + let tok = send(tok, input_s, Input { data: Data: 0x1122_3344_5566_7788, length: Length: 64}); + + // Single 64bit input packet, multiple output packets of different sizes + let tok = send(tok, input_s, Input { data: Data: 0xEEFF_0011_CCDD_BBAA, length: Length: 64}); + + // Account for leftover 0xEEFF from the previous packet + let tok = send(tok, input_s, Input { data: Data: 0x1122, length: Length: 16}); + // Should operate on flushed buffer + let tok = send(tok, input_s, Input { data: Data: 0x3344, length: Length: 16}); + + // Input packets additionally span across 2 shift buffer aligner shift domains + let tok = send(tok, input_s, Input { data: Data: 0x7788, length: Length: 16}); + let tok = send(tok, input_s, Input { data: Data: 0x5566, length: Length: 16}); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:8 }); + let (tok, output) = recv(tok, data_r); + assert_eq(output, Output { data: Data:0x44, length: Length:8 }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:4 }); + let (tok, output) = recv(tok, data_r); + assert_eq(output, Output { data: Data:0xD, length: Length:4 }); + let tok = send(tok, ctrl_s, Ctrl { length: Length:4 }); + let (tok, output) = recv(tok, data_r); + assert_eq(output, Output { data: Data:0xD, length: Length:4 }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:48 }); + let (tok, output) = recv(tok, data_r); + assert_eq(output, Output { data: Data:0xAA_11_BB_22_CC_33, length: Length:48 }); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); + let (tok, output) = recv(tok, data_r); + assert_eq(output, Output { data: Data:0xEE_55_FF_66_00_77_11_88, length: Length:64 }); + + // Single input, single output packet 32bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0xAABB_CCDD, length: Length: 32}); + + // Multiple input packets, single output 32bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x1122_3344, length: Length: 32}); + + // Small consecutive single input, single output 8bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x55, length: Length: 8}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x66, length: Length: 8}); + + // Multiple input packets, single output 64bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:64}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x7788_99AA_BBCC_DDEE, length: Length: 64}); + + // Single input packet, single output 64bit buffering + let tok = send(tok, ctrl_s, Ctrl { length: Length:64}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x1122_3344_5566_7788, length: Length: 64}); + + // Single 64bit input packet, multiple output packets of different sizes + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0xAA, length: Length: 8}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:8}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0xBB, length: Length: 8}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:16}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0xCCDD, length: Length: 16}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0xEEFF_0011, length: Length: 32}); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:16}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x1122, length: Length: 16}); + let tok = send(tok, ctrl_s, Ctrl { length: Length:16}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x3344, length: Length: 16}); + + let tok = send(tok, ctrl_s, Ctrl { length: Length:32}); + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0x5566_7788, length: Length: 32}); + + // Test attempting to read more data than available in the buffer + // This should wait indefinitely, we test this by checking that we can't + // receive data over the next consecutive 100 iterations + let tok = send(tok, ctrl_s, Ctrl { length: Length:64}); + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, data_valid) = recv_non_blocking(tok, data_r, zero!()); + assert_eq(data_valid, false); + tok + }(tok); + + // Refill the buffer with more data - not enough to reply to the earlier request for 64b + let tok = send(tok, input_s, Input { data: Data: 0xDEAD_BEEF, length: Length: 32}); + // Check that we can't receive still + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, data_valid) = recv_non_blocking(tok, data_r, zero!()); + assert_eq(data_valid, false); + tok + }(tok); + + // Refill buffer with enough data + let tok = send(tok, input_s, Input { data: Data: 0xF00B_A4BA, length: Length: 32}); + // Now we should be able to receive a response for 64b request + let (tok, data) = recv(tok, data_r); + assert_eq(data, Output { data: Data: 0xF00BA4BA_DEADBEEF, length: Length: 64}); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/shift_buffer/shift_buffer_inst.x b/xls/modules/shift_buffer/shift_buffer_inst.x new file mode 100644 index 0000000000..44c2df8be9 --- /dev/null +++ b/xls/modules/shift_buffer/shift_buffer_inst.x @@ -0,0 +1,71 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; +import xls.modules.shift_buffer.shift_buffer; + +const TEST_DATA_WIDTH = u32:64; +const TEST_DATA_WIDTH_X2 = u32:128; +const TEST_LENGTH_WIDTH = std::clog2(TEST_DATA_WIDTH) + u32:1; + +proc ShiftBufferInst { + type Input = shift_buffer::ShiftBufferPacket; + type Ctrl = shift_buffer::ShiftBufferCtrl; + type Output = shift_buffer::ShiftBufferOutput; + input_r: chan> in; + ctrl_r: chan> in; + output_s: chan> out; + + config(input_r: chan> in, + ctrl_r: chan> in, + output_s: chan> out) { + + spawn shift_buffer::ShiftBuffer(ctrl_r, input_r, output_s); + + (input_r, ctrl_r, output_s) + } + + init { } + + next(state: ()) {} +} + +proc ShiftBufferAlignerInst { + type Input = shift_buffer::ShiftBufferPacket; + type Inter = shift_buffer::ShiftBufferPacket; + + config(input: chan in, inter: chan out) { + spawn shift_buffer::ShiftBufferAligner(input, inter); + } + + init { } + + next(state: ()) { } +} + +proc ShiftBufferStorageInst { + type Ctrl = shift_buffer::ShiftBufferCtrl; + type Inter = shift_buffer::ShiftBufferPacket; + type Output = shift_buffer::ShiftBufferOutput; + + config(ctrl: chan in, inter: chan in, output: chan out) { + spawn shift_buffer::ShiftBufferStorage(ctrl, inter, output); + } + + init { } + + next(state: ()) { } +} + + diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 9860a0791f..32e9e05ebf 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -45,19 +45,6 @@ common_codegen_args = { "multi_proc": "true", } -xls_dslx_library( - name = "math_dslx", - srcs = [ - "math.x", - ], -) - -xls_dslx_test( - name = "math_dslx_test", - library = ":math_dslx", - tags = ["manual"], -) - xls_dslx_library( name = "buffer_dslx", srcs = [ @@ -93,6 +80,7 @@ window_buffer_codegen_args = common_codegen_args | { "module_name": "WindowBuffer64", "clock_period_ps": "0", "pipeline_stages": "1", + "worst_case_throughput": "2", } xls_dslx_verilog( @@ -863,78 +851,6 @@ place_and_route( target_die_utilization_percentage = "10", ) -xls_dslx_library( - name = "shift_buffer_dslx", - srcs = ["shift_buffer.x"], - deps = [ - ":buffer_dslx", - ], -) - -xls_dslx_test( - name = "shift_buffer_dslx_test", - library = ":shift_buffer_dslx", -) - -xls_dslx_verilog( - name = "shift_buffer_verilog", - codegen_args = { - "module_name": "ShiftBuffer", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "use_system_verilog": "false", - }, - dslx_top = "ShiftBufferInst", - library = ":shift_buffer_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__shift_buffer__ShiftBufferInst__ShiftBuffer_0__128_64_7_next", - }, - verilog_file = "shift_buffer.v", -) - -xls_benchmark_ir( - name = "shift_buffer_opt_ir_benchmark", - src = ":shift_buffer_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, -) - -verilog_library( - name = "shift_buffer_verilog_lib", - srcs = [ - ":shift_buffer.v", - ], -) - -synthesize_rtl( - name = "shift_buffer_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - top_module = "ShiftBuffer", - deps = [ - ":shift_buffer_verilog_lib", - ], -) - -benchmark_synth( - name = "shift_buffer_benchmark_synth", - synth_target = ":shift_buffer_synth_asap7", -) - -place_and_route( - name = "shift_buffer_place_and_route", - clock_period = CLOCK_PERIOD_PS, - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":shift_buffer_synth_asap7", - target_die_utilization_percentage = "10", -) - xls_dslx_library( name = "ram_wr_handler_dslx", srcs = ["ram_wr_handler.x"], @@ -1191,6 +1107,87 @@ xls_benchmark_ir( # library = ":comp_block_dec_dslx", #) +xls_dslx_library( + name = "refilling_shift_buffer_dslx", + srcs = ["refilling_shift_buffer.x"], + deps = [ + "//xls/modules/shift_buffer:shift_buffer_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + ], +) + +xls_dslx_test( + name = "refilling_shift_buffer_dslx_test", + dslx_test_args = {"compare": "jit"}, + library = ":refilling_shift_buffer_dslx", +) + +xls_dslx_verilog( + name = "refilling_shift_buffer_internal_verilog", + codegen_args = common_codegen_args | { + "module_name": "RefillingShiftBufferInternalInst" + }, + dslx_top = "RefillingShiftBufferInternalInst", + library = ":refilling_shift_buffer_dslx", + tags = ["manual"], + verilog_file = "refilling_shift_buffer_internal.v", +) + +xls_benchmark_ir( + name = "refilling_shift_buffer_internal_opt_ir_benchmark", + src = ":refilling_shift_buffer_internal_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "inline_procs": "false", + }, + tags = ["manual"], +) + +verilog_library( + name = "refilling_shift_buffer_internal_verilog_lib", + srcs = [ + ":refilling_shift_buffer_internal.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "refilling_shift_buffer_internal_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "RefillingShiftBufferInternalInst", + deps = [ + ":refilling_shift_buffer_internal_verilog_lib", + ], +) + +benchmark_synth( + name = "refilling_shift_buffer_internal_benchmark_synth", + synth_target = ":refilling_shift_buffer_internal_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "refilling_shift_buffer_internal_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.4", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":refilling_shift_buffer_internal_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + +#xls_dslx_verilog( +# name = "refilling_shift_buffer_verilog", +# codegen_args = common_codegen_args, +# dslx_top = "RefillingShiftBufferInst", +# library = ":refilling_shift_buffer_dslx", +# tags = ["manual"], +# verilog_file = "refilling_shift_buffer.v", +#) + zstd_dec_deps = [ ":axi_csr_accessor_dslx", ":block_header_dec_dslx", diff --git a/xls/modules/zstd/refilling_shift_buffer.x b/xls/modules/zstd/refilling_shift_buffer.x new file mode 100644 index 0000000000..3be573f8ef --- /dev/null +++ b/xls/modules/zstd/refilling_shift_buffer.x @@ -0,0 +1,889 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains proc responsible for automatically refilling ShiftBuffer +// with data from memory from some starting address, consecutive data from +// increasing addresses + + +import std; +import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.memory.mem_reader; + + +pub type RefillingShiftBufferInput = shift_buffer::ShiftBufferPacket; +pub type RefillingShiftBufferCtrl = shift_buffer::ShiftBufferCtrl; + +pub struct RefillStart { + start_addr: uN[ADDR_W] +} + +pub struct RefillingShiftBufferOutput { + data: uN[DATA_WIDTH], + length: uN[LENGTH_WIDTH], + error: bool, +} + +enum RefillerFsm: u2 { + IDLE = 0, + REFILLING = 1, + FLUSHING = 2, +} + +struct RefillerState { + curr_addr: uN[ADDR_W], // next memory address to request data from + fsm: RefillerFsm, // FSM state + future_buf_occupancy: uN[BUFFER_W_CLOG2], // amount of bits that are currently in the ShiftBuffer + + // amount of bits that will enter ShiftBuffer once all + // pending memory requests are served + axi_error: bool, // whether or not at least one memory read resulted in AXI error - + // - this bit is sticky and can be cleared only by flushing + bits_to_axi_error: uN[BUFFER_W_CLOG2], // amount of bits that we need to consume from the + // ShiftBuffer to trigger an AXI error + bits_to_flush: uN[BUFFER_W_CLOG2], // amount of bits left to flush during flushing state +} + +pub fn length_width(data_width: u32) -> u32 { + shift_buffer::length_width(data_width) +} + +// works only on values with bit length divisible by 8 +fn reverse_byte_order(data: uN[N_BITS]) -> uN[N_BITS] { + const_assert!(std::ceil_div(N_BITS, u32:8) == N_BITS / u32:8); + unroll_for! (i, acc): (u32, uN[N_BITS]) in range(u32:0, N_BYTES) { + let offset = i * u32:8; + let offset_rev = (N_BYTES - i - u32:1) * u32:8; + acc | (rev(data[offset +: u8]) as uN[N_BITS] << offset_rev) + }(uN[N_BITS]:0) +} + +#[test] +fn test_reverse_byte_order() { + assert_eq(reverse_byte_order(u64:0b00000001_00100011_01000101_01100111_10001001_10101011_11001101_11101111), u64:0b11110111_10110011_11010101_10010001_11100110_10100010_11000100_10000000); + assert_eq(reverse_byte_order(u32:0b10001001_10101011_11001101_11101111), u32:0b11110111_10110011_11010101_10010001); + assert_eq(reverse_byte_order(u16:0b11001101_11101111), u16:0b11110111_10110011); +} + +proc RefillingShiftBufferInternal< + DATA_W: u32, ADDR_W: u32, BACKWARDS: bool = {false}, INSTANCE: u32 = {u32:0}, + LENGTH_W: u32 = {length_width(DATA_W)}, + DATA_W_DIV8: u32 = {DATA_W / u32:8}, + BUFFER_W: u32 = {DATA_W * u32:2}, // TODO: fix implementation detail of ShiftBuffer leaking here + BUFFER_W_CLOG2: u32 = {std::clog2(BUFFER_W) + u32:1}, +>{ + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + type StartReq = RefillStart; + type RSBInput = RefillingShiftBufferInput; + type RSBOutput = RefillingShiftBufferOutput; + type RSBCtrl = RefillingShiftBufferCtrl; + type SBOutput = shift_buffer::ShiftBufferOutput; + type State = RefillerState; + type Fsm = RefillerFsm; + type BufferSize = uN[BUFFER_W_CLOG2]; + + reader_req_s: chan out; + reader_resp_r: chan in; + start_req_r: chan in; + stop_flush_req_r: chan<()> in; + buffer_data_in_s: chan out; + buffer_data_out_s: chan out; + buffer_ctrl_r: chan in; + snoop_data_out_r: chan in; + snoop_ctrl_s: chan out; + flushing_done_s: chan<()> out; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + start_req_r: chan in, + stop_flush_req_r: chan<()> in, + buffer_ctrl_r: chan in, + buffer_data_out_s: chan out, + snoop_ctrl_s: chan out, + buffer_data_in_s: chan out, + snoop_data_out_r: chan in, + flushing_done_s: chan<()> out, + ) { + (reader_req_s, reader_resp_r, start_req_r, stop_flush_req_r, + buffer_data_in_s, buffer_data_out_s, buffer_ctrl_r, snoop_data_out_r, + snoop_ctrl_s, flushing_done_s) + } + + init { + zero!() + } + + next(state: State) { + let tok = join(); + + // trace_fmt!("Current refiller state: {:#x}", state); + + // receive start and stop&flush requests + let (_, start_req, start_valid) = recv_if_non_blocking(tok, start_req_r, state.fsm == Fsm::IDLE, zero!()); + let (_, (), stop_flush_valid) = recv_if_non_blocking(tok, stop_flush_req_r, state.fsm == Fsm::REFILLING, ()); + + // flush logic + let flushing_end = state.future_buf_occupancy == BufferSize:0; + let flushing = state.fsm == Fsm::FLUSHING; + // flush at most DATA_W bits in a given next() evaluation + let flush_amount_bits = std::min(DATA_W as BufferSize, state.bits_to_flush); + // send "flushing done" notification once we complete it + send_if(tok, flushing_done_s, flushing && flushing_end, ()); + // if (flushing && flushing_end) { + // trace_fmt!("Sent done on the flushing done channel"); + // } else {}; + + // snooping logic for the ShiftBuffer control channel + // recv and immediately send out control packets heading for ShiftBuffer, + // unless we're flushing, if so we block receiving any new control packets + let (_, snoop_ctrl, snoop_ctrl_valid) = recv_if_non_blocking(tok, buffer_ctrl_r, !flushing, zero!()); + // If we're flushing send our packets for taking out data from the shiftbuffer + // (that data will then be discarded) + let ctrl_packet = if (flushing) { + RSBCtrl {length: flush_amount_bits as uN[LENGTH_W]} + } else if (snoop_ctrl_valid) { + snoop_ctrl + } else { + zero!() + }; + let do_send_ctrl = (flushing && flush_amount_bits > BufferSize:0) || snoop_ctrl_valid; + send_if(tok, snoop_ctrl_s, do_send_ctrl, ctrl_packet); + // if do_send_ctrl { + // trace_fmt!("Sent snooped/injected control packet: {:#x}", ctrl_packet); + // } else {}; + + // snoop data output packet (for keeping track how many bits in ShiftBuffer are occupied) + let (_, snoop_data, snoop_data_valid) = recv_non_blocking(tok, snoop_data_out_r, zero!()); + + // refilling logic + const REFILL_SIZE = DATA_W_DIV8 as uN[ADDR_W]; + // we eagerly request data based on the *future* capacity of the buffer, + // this might stall us (and in turn MemReader and potentially the whole bus) + // on send to buffer_data_in_s if the proc sending control requests isn't + // receiving the data on the output channel fast enough, but this is true + // of any proc that uses MemReader and we don't consider this an issue + let buf_will_have_enough_space = state.future_buf_occupancy <= DATA_W as BufferSize; // TODO: fix implementation detail of ShiftBuffer leaking here + let do_refill_cycle = state.fsm == Fsm::REFILLING && buf_will_have_enough_space; + // send request to memory for more data under the assumption + // that there's enough space in the ShiftBuffer to fit it + let mem_req = MemReaderReq { + addr: state.curr_addr, + length: REFILL_SIZE, + }; + send_if(tok, reader_req_s, do_refill_cycle, mem_req); + // if (do_refill_cycle) { + // trace_fmt!("[{:#x}] Sent request for data to memory: {:#x}", INSTANCE, mem_req); + // } else {}; + // receive data from memory + let (_, reader_resp, reader_resp_valid) = recv_non_blocking(tok, reader_resp_r, zero!()); + // if reader_resp_valid { + // trace_fmt!("[{:#x}] Received data from memory: {:#x}", INSTANCE, reader_resp); + // } else {}; + // always send some data regardless of the reader_resp.status to allow for all requests + // to complete (possibly with invalid data) since the response channel queue must be empty for + // flushing to work correctly + let do_buffer_refill = reader_resp_valid; + let reader_resp_len_bits = DATA_W as uN[LENGTH_W]; + let data_packet = RSBInput { + data: if BACKWARDS { reverse_byte_order(reader_resp.data) } else { reader_resp.data }, + length: reader_resp_len_bits, + }; + // this send might stall only if proc that receives responses isn't reading from the + // ShiftBuffer fast enough, apart from that since part of the condition `do_buffer_refill` + // is `buf_will_have_enough_space` it should not block + send_if(tok, buffer_data_in_s, do_buffer_refill, data_packet); + // if (do_buffer_refill) { + // trace_fmt!("Sent data to the ShiftBuffer: {:#x}", data_packet); + // } else {}; + + // length of additional data that will be inserted into the ShiftBuffer *in the future* + // once all pending memory requests are served + let future_input_bits = if (do_refill_cycle) { + DATA_W as BufferSize + } else { + BufferSize:0 + }; + // actual amount of bits inserted into the ShiftBuffer in this next() evaluation + let input_bits = if (do_buffer_refill) { + DATA_W as BufferSize + } else { + BufferSize:0 + }; + // length of data that was snooped on the ShiftBuffer output + // note: default value of snoop_ctrl.length from its recv_if_non_blocking is 0 + let output_bits = snoop_data.length as BufferSize; + // calculate the difference in the amount of bits inserted/taken out + // this will never underflow as it's always true that output_bits <= state.future_buf_occupancy + // (because output_bits is based on the number of outgoing bits from the buffer which cannot be + // larger than its current occupancy) + let next_future_buf_occupancy = state.future_buf_occupancy + future_input_bits - output_bits; + + // keep track of the amount of remaining bits to flush + let next_bits_to_flush = if (flushing) { + state.bits_to_flush - flush_amount_bits + } else { + next_future_buf_occupancy + }; + + // error handling + // we've encountered an error, either previously or in this next() evaluation + let axi_error = state.axi_error || (reader_resp_valid && reader_resp.status == MemReaderStatus::ERROR); + let next_bits_to_axi_error = if (axi_error) { + if (state.bits_to_axi_error < snoop_data.length as BufferSize) { + // prevent underflow + BufferSize:0 + } else { + // keep track of amount of bits to reach offending data (from ERROR memory response) + state.bits_to_axi_error - (snoop_data.length as BufferSize) + } + } else if (flushing_end) { + // reset the counter after a flush since its state will be invalid after that + BufferSize:0 + } else { + // keep track of current amount of bits in the buffer + state.bits_to_axi_error + input_bits - output_bits + }; + // check if we will consume at least one bit from the data that returned AXI error + let reads_error_bits = snoop_data_valid && state.bits_to_axi_error < snoop_data.length as BufferSize; + + // data snoop forwarding logic + // forward data heading for the ShiftBuffer output, attaching an error bit + // if we've encountered an AXI error, unless we're flushing - in that case discard snoop_data + let forward_snooped_data = snoop_data_valid && !flushing; + send_if(tok, buffer_data_out_s, forward_snooped_data, RSBOutput { + data: if BACKWARDS { + rev(snoop_data.data) >> (u32:64 - snoop_data.length as u32) + } else { + snoop_data.data + }, + length: snoop_data.length, + error: axi_error && reads_error_bits, + }); + // if forward_snooped_data { + // trace_fmt!("[{:#x}] Forwarded snooped data output packet: {:#x}", INSTANCE, snoop_data); + // } else {}; + + // FSM + let next_state = match (state.fsm) { + Fsm::IDLE => { + if (start_valid) { + State { + fsm: Fsm::REFILLING, + curr_addr: if BACKWARDS { + start_req.start_addr - DATA_W_DIV8 as uN[ADDR_W] + } else { + start_req.start_addr + }, + ..state + } + } else { + state + } + }, + Fsm::REFILLING => { + // stop and AXI error might happen on the same cycle, + // in that case stop&flush takes precedence over error + if (stop_flush_valid) { + State { + fsm: Fsm::FLUSHING, + ..state + } + } else if (do_refill_cycle) { + State { + curr_addr: if BACKWARDS { + state.curr_addr - REFILL_SIZE + } else { + state.curr_addr + REFILL_SIZE + }, + ..state + } + } else { + state + } + }, + Fsm::FLUSHING => { + if (flushing_end) { + State { + fsm: Fsm::IDLE, + ..state + } + } else { + state + } + }, + _ => fail!("refilling_shift_buffer_fsm_unreachable", zero!()) + }; + + let next_axi_error = axi_error && next_state.fsm == Fsm::REFILLING; + + // combine next FSM state with buffer occupancy data + let next_state = State { + future_buf_occupancy: next_future_buf_occupancy, + bits_to_axi_error: next_bits_to_axi_error, + bits_to_flush: next_bits_to_flush, + axi_error: next_axi_error, + ..next_state + }; + + // check some invariants + // asserts are equivalent to implications in a preceding comment + // state.fsm == Fsm::IDLE -> next_future_buf_occupancy == 0 + assert!(!(state.fsm == Fsm::IDLE) || state.future_buf_occupancy == BufferSize:0, "future_buf_occupancy was not 0 in IDLE state"); + // state.fsm == Fsm::IDLE -> state.bits_to_axi_error == BufferSize:0 + assert!(!(state.fsm == Fsm::IDLE) || state.bits_to_axi_error == BufferSize:0, "bits_to_axi_error was not 0 in IDLE state"); + // state.fsm == Fsm::IDLE -> state.bits_to_flush == BufferSize:0 + assert!(!(state.fsm == Fsm::IDLE) || state.bits_to_flush == BufferSize:0, "bits_to_flush was not 0 in IDLE state"); + + // state.fsm == Fsm::REFILLING -> state.future_buf_occupancy >= state.bits_to_axi_error + assert!(!(state.fsm == Fsm::REFILLING) || state.future_buf_occupancy >= state.bits_to_axi_error, "future_buf_occupancy >= bits_to_axi_error in REFILLING state"); + // state.fsm == Fsm::REFILLING -> state.future_buf_occupancy >= state.bits_to_flush + assert!(!(state.fsm == Fsm::REFILLING) || state.future_buf_occupancy >= state.bits_to_flush, "future_buf_occupancy >= bits_to_flush in REFILLING state"); + // state.fsm == Fsm::REFILLING -> state.bits_to_flush >= state.bits_to_axi_error + assert!(!(state.fsm == Fsm::REFILLING) || state.bits_to_flush >= state.bits_to_axi_error, "bits_to_flush >= bits_to_axi_error in REFILLING state"); + + // state.fsm != Fsm::REFILLING -> state.axi_error == false + assert!(!(state.fsm != Fsm::REFILLING) || state.axi_error == false, "axi_error was true in a state other than REFILLING"); + // axi_error -> state.bits_to_axi_error >= next_bits_to_axi_error + assert!(!axi_error || state.bits_to_axi_error >= next_bits_to_axi_error, "state.bits_to_axi_error increased during axi_error"); + // flushing -> state.bits_to_flush >= next_bits_to_flush + assert!(!flushing || state.bits_to_flush >= next_bits_to_flush, "state.bits_to_flush increased during flushing"); + + next_state + } +} + +// Main proc for RefillingShiftBuffer +// +// Typical usage pattern is as follows: +// 1. Send start request with starting address where the refilling is supposed +// to start from on start_req channel +// 2. Send requests for up to DATA_W bits on buffer_ctrl channel +// 3. Receive responses on buffer_data_out channel +// 4. Once you're done, send a request on stop_flush_req channel +// and wait for confirmation on flushing_done channel +// +// In case of an AXI error on the bus an error bit is set in response +// on buffer_data_out channel. You may still send requests on buffer_ctrl +// and receive responses on buffer_data_out but the data is not guaranteed +// to be correct and said error bit will always be set from that point +// onwards until you trigger a flush +// +// To send a request on stop_flush_req channel, you must first receive all +// responses from the buffer_data_out channel that you sent requests for on +// buffer_ctrl channel + +pub proc RefillingShiftBuffer< + DATA_W: u32, + ADDR_W: u32, + BACKWARDS: bool = {false}, + INSTANCE: u32 = {u32:0}, + LENGTH_W: u32 = {length_width(DATA_W)}, +> { + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type StartReq = RefillStart; + type RSBInput = RefillingShiftBufferInput; + type RSBOutput = RefillingShiftBufferOutput; + type RSBCtrl = RefillingShiftBufferCtrl; + type SBOutput = shift_buffer::ShiftBufferOutput; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + start_req_r: chan in, + stop_flush_req_r: chan<()> in, + buffer_ctrl_r: chan in, + buffer_data_out_s: chan out, + flushing_done_s: chan<()> out, + ) { + const CHANNEL_DEPTH = u32:1; + + let (buffer_data_in_s, buffer_data_in_r) = chan("buffer_data_in"); + let (snoop_data_out_s, snoop_data_out_r) = chan("snoop_data_out_s"); + let (snoop_ctrl_s, snoop_ctrl_r) = chan("snoop_ctrl"); + + spawn shift_buffer::ShiftBuffer( + snoop_ctrl_r, buffer_data_in_r, snoop_data_out_s + ); + spawn RefillingShiftBufferInternal( + reader_req_s, + reader_resp_r, + start_req_r, + stop_flush_req_r, + buffer_ctrl_r, + buffer_data_out_s, + snoop_ctrl_s, + buffer_data_in_s, + snoop_data_out_r, + flushing_done_s, + ); + } + + init {} + + next(_: ()) {} +} + + +const TEST_DATA_W = u32:64; +const TEST_ADDR_W = u32:32; +const TEST_LENGTH_W = length_width(TEST_DATA_W); +const TEST_DATA_W_DIV8 = TEST_DATA_W / u32:8; +const TEST_BUFFER_W = TEST_DATA_W * u32:2; // TODO: fix implementation detail of ShiftBuffer leaking here +const TEST_BUFFER_W_CLOG2 = std::clog2(TEST_BUFFER_W); + +proc RefillingShiftBufferTest { + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + type StartReq = RefillStart; + type RSBInput = RefillingShiftBufferInput; + type RSBOutput = RefillingShiftBufferOutput; + type RSBCtrl = RefillingShiftBufferCtrl; + type State = RefillerState; + + terminator: chan out; + reader_req_r: chan in; + reader_resp_s: chan out; + start_req_s: chan out; + stop_flush_req_s: chan<()> out; + buffer_ctrl_s: chan out; + buffer_data_out_r: chan in; + flushing_done_r: chan<()> in; + + config(terminator: chan out) { + let (reader_req_s, reader_req_r) = chan("reader_req"); + let (reader_resp_s, reader_resp_r) = chan("reader_resp"); + let (start_req_s, start_req_r) = chan("start_req"); + let (stop_flush_req_s, stop_flush_req_r) = chan<()>("stop_flush_req"); + let (buffer_ctrl_s, buffer_ctrl_r) = chan("buffer_ctrl"); + let (buffer_data_out_s, buffer_data_out_r) = chan("buffer_data_out"); + let (flushing_done_s, flushing_done_r) = chan<()>("flushing_done"); + + spawn RefillingShiftBuffer( + reader_req_s, reader_resp_r, start_req_r, stop_flush_req_r, + buffer_ctrl_r, buffer_data_out_s, flushing_done_s, + ); + + ( + terminator, reader_req_r, reader_resp_s, start_req_s, + stop_flush_req_s, buffer_ctrl_s, buffer_data_out_r, + flushing_done_r, + ) + } + + init { } + + next(state: ()) { + type Addr = uN[TEST_ADDR_W]; + type Data = uN[TEST_DATA_W]; + type Length = uN[TEST_LENGTH_W]; + + let tok = join(); + + const REFILL_SIZE = TEST_DATA_W_DIV8 as Addr; + let tok = send(tok, start_req_s, StartReq { start_addr: Addr:0xDEAD_0008 }); + + // proc should ask for data 2 times (2/3 of the size of the internal ShiftBuffer) + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr: 0xDEAD_0000 } else { Addr:0xDEAD_0008 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0x01234567_89ABCDEF, + length: REFILL_SIZE, + last: true, + }); + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr: 0xDEAC_FFF8 } else { Addr:0xDEAD_0010 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0xFEDCBA98_76543210, + length: REFILL_SIZE, + last: true, + }); + + // read single byte + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:8 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0x01 } else { Data:0xEF }, + length: Length:8, + error: false, + }); + + // proc shouldn't be asking for any more data at this point + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, data_valid) = recv_non_blocking(tok, reader_req_r, zero!()); + assert_eq(data_valid, false); + tok + }(tok); + + // read enough data from the buffer to trigger a refill + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:56 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0x23456789ABCDEF } else { Data:0x01234567_89ABCD }, + length: Length:56, + error: false, + }); + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr: 0xDEAC_FFF0 } else { Addr:0xDEAD_0018 } , + length: REFILL_SIZE, + }); + // don't respond to the request yet + + // we have 64 bits in the buffer at this point - almost empty it manually + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:60 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0x0FEDCBA9_87654321 } else { Data:0xEDCBA98_76543210 }, + length: Length:60, + error: false, + }); + + // ask for more data from the buffer (but not enough data is available) + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:12 + }); + // make sure that reading from output is stuck + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, data_valid) = recv_non_blocking(tok, buffer_data_out_r, zero!()); + assert_eq(data_valid, false); + tok + }(tok); + + // serve earlier memory request + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0x02481357_8ACE9BD0, + length: REFILL_SIZE, + last: true, + }); + // should be able to receive from the buffer now + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0x02 } else { Data:0xD0F }, + length: Length:12, + error: false, + }); + + // buffer now contains 56 bits - proc should have sent 1 more + // memory requests by this point - serve it + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr:0xDEAC_FFE8 } else { Addr:0xDEAD_0020 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0x86868686_42424242, + length: REFILL_SIZE, + last: true, + }); + + // make sure proc is not requesting more data that we can insert into the buffer + let tok = for (_, tok): (u32, token) in u32:1..u32:100 { + let (tok, _, req_valid) = recv_non_blocking(tok, reader_req_r, zero!()); + assert_eq(req_valid, false); + tok + }(tok); + + // try flushing + let tok = send(tok, stop_flush_req_s, ()); + let (tok, ()) = recv(tok, flushing_done_r); + + // start from a new address and refill buffer with more data + let tok = send(tok, start_req_s, StartReq { start_addr: u32: 0x1000_11F0 }); + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr: 0x1000_11E8 } else { Addr: 0x1000_11F0 } , + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0xFEFDFCFB_FAF9F8F7, + length: REFILL_SIZE, + last: true, + }); + + // try reading data from the buffer after the flush + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:4 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data: 0xF } else { Data:0x7 }, + length: Length:4, + error: false, + }); + + // refill with even more data + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr: 0x1000_11E0 } else { Addr:0x1000_11F8 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0xABBA_BAAB_AABB_BBAA, + length: REFILL_SIZE, + last: true, + }); + + // test receiving more than DATA_W bits + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:64 + }); + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:60 + }); + + // receive all of the new data and verify that no old data + // remained in the buffer + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0xEFDFCFBFAF9F8F7A } else { Data:0xAFEFDFCF_BFAF9F8F }, + length: Length:64, + error: false, + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0xBBABAABAABBBBAA } else { Data:0xABBA_BAAB_AABB_BBA }, + length: Length:60, + error: false, + }); + + // proc should've requested more data by now + // respond with AXI error from MemReader + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr:0x1000_11D8 } else { Addr:0x1000_1200 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::ERROR, + data: Data:0x0, + length: Addr:0x0, + last: true, + }); + + // try reading from the buffer that's tainted by + // AXI error - should induce a packet on the error channel + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:1 + }); + + // to comply with the usage protocol of refiller we need to recv response + let (tok, resp) = recv(tok, buffer_data_out_r); + // don't assume anything about the response except that the lenght must be 1 and error true + assert_eq(resp.length, Length:1); + assert_eq(resp.error, true); + + // send some more data, can be OK status this time + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr:0x1000_11D0 } else { Addr:0x1000_1208 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0xDEADBEEF_FEEBDAED, + length: Addr:0x40, + last: true, + }); + + // check that we get another error after trying to read from the buffer once more + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:64 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + // again don't assume anything about the response other data length and error + assert_eq(resp.length, Length:64); + assert_eq(resp.error, true); + + // to comply with the usage protocol of refiller we must flush it after + // receiving the error to permit further operation in non-error state + let tok = send(tok, stop_flush_req_s, ()); + + // test that flushing works even if response from memory arrives after + // flushing is requested + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr:0x1000_11C8 } else { Addr:0x1000_1210 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0xFFFF_EEEE_DDDD_CCCC, + length: Addr:0x40, + last: true, + }); + + let (tok, ()) = recv(tok, flushing_done_r); + + // test that we can restart refilling after flushing from an error state + let tok = send(tok, start_req_s, StartReq { + start_addr: Addr:0xABCD_0000 + }); + + // respond to memory request + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr:0xABCC_FFF8 } else { Addr:0xABCD_0000 }, + length: REFILL_SIZE, + }); + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::OKAY, + data: Data:0x0123_4567_89AB_CDEF, + length: Addr:0x40, + last: true, + }); + + // ask for some data + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:8 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: if BACKWARDS { Data:0x01 } else { Data:0xEF }, + length: Length:8, + error: false, + }); + + // respond to second memory request + let (tok, req) = recv(tok, reader_req_r); + assert_eq(req, MemReaderReq { + addr: if BACKWARDS { Addr: 0xABCC_FFF0 } else { Addr:0xABCD_0008 }, + length: REFILL_SIZE, + }); + // taint this response + let tok = send(tok, reader_resp_s, MemReaderResp { + status: MemReaderStatus::ERROR, + data: Data:0x8888_7777_6666_5555, + length: Addr:0x40, + last: true, + }); + + // ask for data that won't trigger an error + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length:48 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp, RSBOutput { + data: Data:0x23456789ABCD, + length: Length:48, + error: false, + }); + + // now ask for data that *will* trigger an error + // we have 72 bits in the buffer, 8 untainted and 64 tainted + let tok = send(tok, buffer_ctrl_s, RSBCtrl { + length: Length: 9 + }); + let (tok, resp) = recv(tok, buffer_data_out_r); + assert_eq(resp.length, Length:9); + assert_eq(resp.error, true); + + send(tok, terminator, true); + } +} + +#[test_proc] +proc RefillingShiftBufferTestForward { + terminator_r: chan in; + terminator: chan out; + + config(terminator: chan out) { + // we need to instantiate an intermediate channel since terminator channel + // cannot be passed directly to the proc + let (terminator_s, terminator_r) = chan("terminator"); + spawn RefillingShiftBufferTest(terminator_s); + (terminator_r, terminator) + } + init {} + next(_: ()) { + let tok = join(); + let (tok, value) = recv(tok, terminator_r); + send(tok, terminator, value); + } +} + +#[test_proc] +proc RefillingShiftBufferTestBackward { + terminator_r: chan in; + terminator: chan out; + + config(terminator: chan out) { + let (terminator_s, terminator_r) = chan("terminator"); + spawn RefillingShiftBufferTest(terminator_s); + (terminator_r, terminator) + } + init {} + next(_: ()) { + let tok = join(); + let (tok, value) = recv(tok, terminator_r); + send(tok, terminator, value); + } +} + +proc RefillingShiftBufferInternalInst { + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + type StartReq = RefillStart; + type RSBInput = RefillingShiftBufferInput; + type RSBOutput = RefillingShiftBufferOutput; + type RSBCtrl = RefillingShiftBufferCtrl; + type SBOutput = shift_buffer::ShiftBufferOutput; + type State = RefillerState; + + config( + reader_req_s: chan out, + reader_resp_r: chan in, + start_req_r: chan in, + stop_flush_req_r: chan<()> in, + buffer_ctrl_r: chan in, + buffer_data_out_s: chan out, + snoop_ctrl_s: chan out, + buffer_data_in_s: chan out, + snoop_data_out_r: chan in, + flushing_done_s: chan<()> out, + ) { + // instantiate with BACKWARDS = true to test worst-case results + spawn RefillingShiftBufferInternal( + reader_req_s, reader_resp_r, start_req_r, stop_flush_req_r, + buffer_ctrl_r, buffer_data_out_s, snoop_ctrl_s, + buffer_data_in_s, snoop_data_out_r, flushing_done_s, + ); + } + + init { } + + next(state: ()) { } +} diff --git a/xls/modules/zstd/shift_buffer.x b/xls/modules/zstd/shift_buffer.x deleted file mode 100644 index fd520774cb..0000000000 --- a/xls/modules/zstd/shift_buffer.x +++ /dev/null @@ -1,246 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// This file contains the implementation of a buffering proc responsible for -// reading the data stream and dividing it into the smallest packets of the -// requested size. - -import std; -import xls.modules.zstd.buffer; - -fn buffer_width(data_width: u32) -> u32 { data_width * u32:2 } - -pub struct ShiftBufferInput { - data: uN[DATA_W], - length: uN[LENGTH_W], - last: bool, -} - -pub struct ShiftBufferOutput { - data: uN[DATA_W], - length: uN[LENGTH_W], - last: bool, -} - -pub struct ShiftBufferCtrl { - length: uN[LENGTH_W], -} - -enum ShiftBufferStatus : u1 { - REFILL = 0, - FLUSH = 1, -} - -struct ShiftBufferState { - status: ShiftBufferStatus, - buff: buffer::Buffer, - ctrl: ShiftBufferCtrl, - ctrl_valid: bool, - last: bool, -} - -pub fn mask_data (data: bits[DATA_W], length: bits[LENGTH_W]) -> bits[DATA_W] { - type Data = bits[DATA_W]; - type Length = bits[LENGTH_W]; - - let mask = if length != Length:0 { (Data:1 << length) - Data:1 } else { Data:0 }; - data & mask -} - -pub proc ShiftBuffer< - DATA_W: u32, LENGTH_W: u32, - BUFFER_W: u32 = {buffer_width(DATA_W)} -> { - type Data = uN[DATA_W]; - type Length = uN[LENGTH_W]; - type BufferData = uN[BUFFER_W]; - type Input = ShiftBufferInput; - type Ctrl = ShiftBufferCtrl; - type Output = ShiftBufferOutput; - type State = ShiftBufferState; - type Status = ShiftBufferStatus; - - in_data_r: chan in; - in_ctrl_r: chan in; - out_data_s: chan out; - - config( - in_data_r: chan in, - in_ctrl_r: chan in, - out_data_s: chan out, - ) { (in_data_r, in_ctrl_r, out_data_s) } - - init { zero!() } - - next(state: State) { - - let tok0 = join(); - - // Receive control - let (tok1_0, ctrl, ctrl_valid) = - recv_if_non_blocking(tok0, in_ctrl_r, !state.ctrl_valid, state.ctrl); - - // Receive data - let can_fit = buffer::buffer_can_fit(state.buff, Data:0); - let do_recv_data = can_fit && state.status == Status::REFILL; - let (tok1_1, recv_data, recv_data_valid) = - recv_if_non_blocking(tok0, in_data_r, do_recv_data, zero!()); - - let tok1 = join(tok1_0, tok1_1); - - // Handle the request - // Uses buffer from the previous next evaluation (from state) to prevent - // creating long combinatorial logic that would allow receiving and - // sending back the data in the same cycle. - - let has_valid_request = ctrl_valid || state.ctrl_valid; - let has_enough_data = buffer::buffer_has_at_least(state.buff, ctrl.length as u32); - - let (data, do_send, new_buff, new_ctrl, new_ctrl_valid) = if has_valid_request && has_enough_data { - let (buff, data) = buffer::buffer_pop(state.buff, ctrl.length as u32); - let last = buff.length == u32:0 && state.last; - let output = Output { data: data as Data, length: ctrl.length, last }; - let do_send = ctrl.length != Length:0; - (output, do_send, buff, zero!(), false) - } else { - (zero!(), false, state.buff, ctrl, has_valid_request) - }; - - let tok2_0 = send_if(tok1, out_data_s, do_send, data); - - // Handle input data - let (new_buff, new_last) = if can_fit && recv_data_valid { - ( - buffer::buffer_append_with_length( - new_buff, recv_data.data as BufferData, recv_data.length as u32), - recv_data.last, - ) - } else { - (new_buff, state.last) - }; - - // Handle state change - let new_status = if state.status == Status::REFILL && recv_data_valid && recv_data.last { - Status::FLUSH - } else if state.status == Status::FLUSH && state.buff.length == ctrl.length as u32 { - Status::REFILL - } else { - state.status - }; - - State { - status: new_status, - buff: new_buff, - ctrl: new_ctrl, - ctrl_valid: new_ctrl_valid, - last: new_last - } - } -} - -const INST_DATA_W = u32:64; -const INST_LENGTH_W = std::clog2(INST_DATA_W) + u32:1; - -proc ShiftBufferInst { - type Input = ShiftBufferInput; - type Ctrl = ShiftBufferCtrl; - type Output = ShiftBufferOutput; - - config( - data_r: chan in, - ctrl_r: chan in, - out_s: chan out - ) { - spawn ShiftBuffer(data_r, ctrl_r, out_s); - } - - init { } - - next(state: ()) { } -} - -const TEST_DATA_W = u32:64; -const TEST_LENGTH_W = std::clog2(TEST_DATA_W) + u32:1; - -#[test_proc] -proc ShiftBufferTest { - type Input = ShiftBufferInput; - type Ctrl = ShiftBufferCtrl; - type Output = ShiftBufferOutput; - type Data = uN[TEST_DATA_W]; - type Length = uN[TEST_LENGTH_W]; - - terminator: chan out; - data_s: chan out; - ctrl_s: chan out; - out_r: chan in; - - config(terminator: chan out) { - let (data_s, data_r) = chan("in_data"); - let (ctrl_s, ctrl_r) = chan("in_ctrl"); - let (out_s, out_r) = chan("out_data"); - - spawn ShiftBuffer(data_r, ctrl_r, out_s); - (terminator, data_s, ctrl_s, out_r) - } - - init { } - - next(state: ()) { - - let tok = join(); - let tok = send(tok, data_s, Input { data: Data:0xDD_44, length: Length:16, last: false }); - let tok = send(tok, data_s, Input { data: Data:0xAA_11_BB_22_CC_33, length: Length:48, last: false }); - let tok = send(tok, data_s, Input { data: Data:0xEE_55_FF_66_00_77_11_88, length: Length:64, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:8 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x44, length: Length:8, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:4 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0xD, length: Length:4, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x18_8A_A1_1B_B2_2C_C3_3D, length: Length:64, last: false }); - - let tok = send(tok, data_s, Input { data: Data:0x44_BB_55_CC, length: Length:32, last: false }); - let tok = send(tok, data_s, Input { data: Data:0x22_99_33_AA, length: Length:32, last: true }); - let tok = send(tok, data_s, Input { data: Data:0x66_DD_77_EE_88_FF_99_00, length: Length:64, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:4 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x1, length: Length:4, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x55_CC_EE_55_FF_66_00_77, length: Length:64, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:16 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x44_BB, length: Length:16, last: false }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:32 }); - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x22_99_33_AA, length: Length:32, last: true }); - - let tok = send(tok, ctrl_s, Ctrl { length: Length:64 }); - - let (tok, output) = recv(tok, out_r); - assert_eq(output, Output { data: Data:0x66_DD_77_EE_88_FF_99_00, length: Length:64, last: false }); - - send(tok, terminator, true); - } -} From f63f0b29d021032b8315fdf2504d179e2ae6158c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Wed, 13 Nov 2024 22:32:07 +0100 Subject: [PATCH 37/85] modules/zstd: Add FSE tables and lookup decoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Internal-tag: [#68052] Signed-off-by: Krzysztof Obłonczek --- xls/modules/zstd/BUILD | 280 +++++- xls/modules/zstd/common.x | 102 +- xls/modules/zstd/fse_dec.x | 1320 +++++++++++++++++++++++++ xls/modules/zstd/fse_lookup_dec.x | 1049 ++++++++++++++++++++ xls/modules/zstd/fse_proba_freq_dec.x | 212 ++-- xls/modules/zstd/fse_table_creator.x | 652 ++++++++++++ xls/modules/zstd/fse_table_iterator.x | 124 +++ 7 files changed, 3669 insertions(+), 70 deletions(-) create mode 100644 xls/modules/zstd/fse_dec.x create mode 100644 xls/modules/zstd/fse_lookup_dec.x create mode 100644 xls/modules/zstd/fse_table_creator.x create mode 100644 xls/modules/zstd/fse_table_iterator.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 32e9e05ebf..3360a55e03 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -45,6 +45,19 @@ common_codegen_args = { "multi_proc": "true", } +xls_dslx_library( + name = "math_dslx", + srcs = [ + "math.x", + ], +) + +xls_dslx_test( + name = "math_dslx_test", + library = ":math_dslx", + tags = ["manual"], +) + xls_dslx_library( name = "buffer_dslx", srcs = [ @@ -163,7 +176,10 @@ xls_dslx_library( srcs = [ "common.x", ], - deps = [], + deps = [ + "//xls/modules/shift_buffer:shift_buffer_dslx", + "//xls/examples:ram_dslx", + ], ) xls_dslx_library( @@ -928,7 +944,8 @@ xls_dslx_library( deps = [ ":common_dslx", ":ram_wr_handler_dslx", - ":shift_buffer_dslx", + ":refilling_shift_buffer_dslx", + "//xls/modules/shift_buffer:shift_buffer_dslx", "//xls/examples:ram_dslx", ], ) @@ -1283,3 +1300,262 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "fse_lookup_dec_dslx", + srcs = [ + "fse_lookup_dec.x", + ], + deps = [ + "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:axi_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd:common_dslx", + "//xls/modules/zstd:fse_table_creator_dslx", + "//xls/modules/zstd:refilling_shift_buffer_dslx", + "//xls/modules/zstd:fse_proba_freq_dec_dslx", + "//xls/modules/shift_buffer:shift_buffer_dslx", + ] +) + +xls_dslx_test( + name = "fse_lookup_dec_dslx_test", + library = ":fse_lookup_dec_dslx", +) + +xls_dslx_library( + name = "fse_table_iterator_dslx", + srcs = ["fse_table_iterator.x"], + deps = [ + ":common_dslx", + ], +) + +xls_dslx_test( + name = "fse_table_iterator_dslx_test", + library = ":fse_table_iterator_dslx", +) + +xls_dslx_verilog( + name = "fse_table_iterator_verilog", + codegen_args = { + "module_name": "FseTableIterator", + "delay_model": "asap7", + "pipeline_stages": "1", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "FseTableIterator", + library = ":fse_table_iterator_dslx", + verilog_file = "fse_table_iterator.v", +) + +xls_benchmark_ir( + name = "fse_table_iterator_opt_ir_benchmark", + src = ":fse_table_iterator_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "fse_table_iterator_verilog_lib", + srcs = [ + ":fse_table_iterator.v", + ], +) + +synthesize_rtl( + name = "fse_table_iterator_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "FseTableIterator", + deps = [ + ":fse_table_iterator_verilog_lib", + ], +) + +benchmark_synth( + name = "fse_table_iterator_benchmark_synth", + synth_target = ":fse_table_iterator_synth_asap7", +) + +place_and_route( + name = "fse_table_iterator_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":fse_table_iterator_synth_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "fse_table_creator_dslx", + srcs = ["fse_table_creator.x"], + deps = [ + ":common_dslx", + ":fse_table_iterator_dslx", + ":ram_wr_handler_dslx", + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "fse_table_creator_dslx_test", + library = ":fse_table_creator_dslx", +) + +xls_dslx_verilog( + name = "fse_table_creator_verilog", + codegen_args = { + "module_name": "FseTableCreator", + "delay_model": "asap7", + "pipeline_stages": "4", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "FseTableCreatorInst", + library = ":fse_table_creator_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__fse_table_creator__FseTableCreatorInst__FseTableCreator_0__8_16_1_8_32_4_8_16_1_next", + }, + verilog_file = "fse_table_creator.v", + tags = ["manual"], +) + +xls_benchmark_ir( + name = "fse_table_creator_opt_ir_benchmark", + src = ":fse_table_creator_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "delay_model": "asap7", + }, +) + +xls_benchmark_verilog( + name = "fse_table_creator_verilog_benchmark", + verilog_target = "fse_table_creator_verilog", +) + +verilog_library( + name = "fse_table_creator_lib", + srcs = [ + ":fse_table_creator.v", + ], +) + +synthesize_rtl( + name = "fse_table_creator_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "FseTableCreator", + deps = [ + ":fse_table_creator_lib", + ], +) + +benchmark_synth( + name = "fse_table_creator_benchmark_synth", + synth_target = ":fse_table_creator_asap7", +) + +place_and_route( + name = "fse_table_creator_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":fse_table_creator_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "fse_dec_dslx", + srcs = [ + "fse_dec.x", + ], + deps = [ + "//xls/examples:ram_dslx", + ":common_dslx", + ":math_dslx", + ":fse_table_creator_dslx", + "//xls/modules/zstd:refilling_shift_buffer_dslx", + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "fse_dec_dslx_test", + library = ":fse_dec_dslx", + tags = ["manual"], +) + +xls_dslx_verilog( + name = "fse_dec_verilog", + codegen_args = { + "module_name": "FseDecoder", + "delay_model": "asap7", + "pipeline_stages": "8", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "FseDecoderInst", + opt_ir_args = { + "top": "__fse_dec__FseDecoderInst__FseDecoder_0__64_8_32_4_64_7_next" + }, + library = ":fse_dec_dslx", + tags = ["manual"], + verilog_file = "fse_dec.v", +) + +xls_benchmark_ir( + name = "fse_dec_opt_ir_benchmark", + src = ":fse_dec_verilog.opt.ir", + benchmark_ir_args = { + "delay_model": "asap7", + "pipeline_stages": "3", + "inline_procs": "false" + }, + tags = ["manual"], +) + +verilog_library( + name = "fse_dec_verilog_lib", + srcs = [ + ":fse_dec.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "fse_dec_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "FseDecoder", + deps = [ + ":fse_dec_verilog_lib", + ], +) + +benchmark_synth( + name = "fse_dec_benchmark_synth", + synth_target = ":fse_dec_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "fse_dec_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + die_height_microns = 100, + die_width_microns = 100, + stop_after_step = "global_routing", + synthesized_rtl = ":fse_dec_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 98c58c60e1..13773aad47 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -13,6 +13,8 @@ // limitations under the License. import std; +import xls.examples.ram; +import xls.modules.shift_buffer.shift_buffer; pub const DATA_WIDTH = u32:64; pub const MAX_ID = u32::MAX; @@ -21,6 +23,7 @@ pub const BLOCK_SIZE_WIDTH = u32:21; pub const OFFSET_WIDTH = u32:22; pub const HISTORY_BUFFER_SIZE_KB = u32:64; pub const BUFFER_WIDTH = u32:128; +pub const MAX_BLOCK_SIZE_KB = u32:64; pub const BLOCK_PACKET_WIDTH = u32:32; @@ -58,9 +61,19 @@ pub struct ExtendedBlockDataPacket { pub struct SequenceExecutorPacket { msg_type: SequenceExecutorMessageType, - length: CopyOrMatchLength, // Literal length or match length - content: CopyOrMatchContent, // Literal data or match offset - last: bool, // Last packet in frame + length: CopyOrMatchLength, // Literal length or match length + content: CopyOrMatchContent, // Literal data or match offset + last: bool, // Last packet in frame +} + +pub struct BlockSyncData { + id: u32, + last_block: bool, +} + +pub struct CommandConstructorData { + sync: BlockSyncData, + data: SequenceExecutorPacket, } // Defines output format of the ZSTD Decoder @@ -101,10 +114,17 @@ pub const FSE_MAX_SYMBOLS = u32:256; pub const FSE_ACCURACY_LOG_WIDTH = std::clog2(FSE_MAX_ACCURACY_LOG + u32:1); pub const FSE_SYMBOL_COUNT_WIDTH = std::clog2(FSE_MAX_SYMBOLS + u32:1); pub const FSE_REMAINING_PROBA_WIDTH = std::clog2((u32:1 << FSE_MAX_ACCURACY_LOG) + u32:1); +pub const FSE_TABLE_INDEX_WIDTH = std::clog2(u32:1 << FSE_MAX_ACCURACY_LOG); + +pub const FSE_PROB_DIST_WIDTH = u32:16; +pub const FSE_MAX_PROB_DIST = u32:256; +pub const FSE_SYMBOL_WIDTH = u32:16; pub type FseRemainingProba = uN[FSE_REMAINING_PROBA_WIDTH]; pub type FseAccuracyLog = uN[FSE_ACCURACY_LOG_WIDTH]; pub type FseSymbolCount = uN[FSE_SYMBOL_COUNT_WIDTH]; +pub type FseTableIndex = uN[FSE_TABLE_INDEX_WIDTH]; + // defined in https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.2.2.1 pub const FSE_LITERAL_LENGTH_DEFAULT_DIST = s16[36]:[ @@ -140,5 +160,81 @@ pub enum FSETableType : u2 { MATCH = 2, } +pub struct FseTableRecord { + symbol: u8, + num_of_bits: u8, + base: u16 +} + pub struct FseRemainder { value: u1, valid: bool } pub struct FseProbaFreqDecoderCtrl { remainder: FseRemainder, finished: bool } + +pub struct FseTableCreatorCtrl { + accuracy_log: FseAccuracyLog, + negative_proba_count: FseSymbolCount +} + +pub fn highest_set_bit(num: uN[N]) -> u16 { std::flog2(num) } + +// SequenceDecoder + +pub const SEQDEC_DPD_RAM_DATA_WIDTH = FSE_PROB_DIST_WIDTH; +pub const SEQDEC_DPD_RAM_SIZE = FSE_MAX_PROB_DIST; +pub const SEQDEC_DPD_RAM_WORD_PARTITION_SIZE = SEQDEC_DPD_RAM_DATA_WIDTH; +pub const SEQDEC_DPD_RAM_ADDR_WIDTH = std::clog2(SEQDEC_DPD_RAM_SIZE); +pub const SEQDEC_DPD_RAM_NUM_PARTITIONS = ram::num_partitions(SEQDEC_DPD_RAM_WORD_PARTITION_SIZE, SEQDEC_DPD_RAM_DATA_WIDTH); + +pub const SEQDEC_TMP_RAM_DATA_WIDTH = FSE_PROB_DIST_WIDTH; +pub const SEQDEC_TMP_RAM_SIZE = FSE_MAX_PROB_DIST; +pub const SEQDEC_TMP_RAM_WORD_PARTITION_SIZE = SEQDEC_TMP_RAM_DATA_WIDTH; +pub const SEQDEC_TMP_RAM_ADDR_WIDTH = std::clog2(SEQDEC_TMP_RAM_SIZE); +pub const SEQDEC_TMP_RAM_NUM_PARTITIONS = ram::num_partitions(SEQDEC_TMP_RAM_WORD_PARTITION_SIZE, SEQDEC_TMP_RAM_DATA_WIDTH); + +pub const SEQDEC_FSE_RAM_DATA_WIDTH = u32:32; +pub const SEQDEC_FSE_RAM_SIZE = FSE_MAX_SYMBOLS; +pub const SEQDEC_FSE_RAM_WORD_PARTITION_SIZE = SEQDEC_FSE_RAM_DATA_WIDTH / u32:3; +pub const SEQDEC_FSE_RAM_ADDR_WIDTH: u32 = std::clog2(SEQDEC_FSE_RAM_SIZE); +pub const SEQDEC_FSE_RAM_NUM_PARTITIONS: u32 = ram::num_partitions(SEQDEC_FSE_RAM_WORD_PARTITION_SIZE, SEQDEC_FSE_RAM_DATA_WIDTH); + +pub const SEQDEC_BLOCK_RAM_DATA_WIDTH = DATA_WIDTH; +pub const SEQDEC_BLOCK_RAM_SIZE = (MAX_BLOCK_SIZE_KB * u32:1024 * u32:8) / SEQDEC_BLOCK_RAM_DATA_WIDTH; +pub const SEQDEC_BLOCK_RAM_WORD_PARTITION_SIZE = SEQDEC_BLOCK_RAM_DATA_WIDTH; +pub const SEQDEC_BLOCK_RAM_ADDR_WIDTH = std::clog2(SEQDEC_BLOCK_RAM_SIZE); +pub const SEQDEC_BLOCK_RAM_NUM_PARTITIONS: u32 = ram::num_partitions(SEQDEC_BLOCK_RAM_WORD_PARTITION_SIZE, SEQDEC_BLOCK_RAM_DATA_WIDTH); + +pub const SEQDEC_SHIFT_BUFFER_DATA_WIDTH = DATA_WIDTH; +pub const SEQDEC_SHIFT_BUFFER_LENGTH_WIDTH = std::clog2(SEQDEC_SHIFT_BUFFER_DATA_WIDTH + u32:1); + +pub type SeqDecDpdRamReadReq = ram::ReadReq; +pub type SeqDecDpdRamReadResp = ram::ReadResp; +pub type SeqDecDpdRamWriteReq = ram::WriteReq; +pub type SeqDecDpdRamWriteResp = ram::WriteResp; +pub type SeqDecDpdRamAddr = bits[SEQDEC_DPD_RAM_ADDR_WIDTH]; +pub type SeqDecDpdRamData = bits[SEQDEC_DPD_RAM_DATA_WIDTH]; + +pub type SeqDecTmpRamReadReq = ram::ReadReq; +pub type SeqDecTmpRamReadResp = ram::ReadResp; +pub type SeqDecTmpRamWriteReq = ram::WriteReq; +pub type SeqDecTmpRamWriteResp = ram::WriteResp; +pub type SeqDecTmpRamAddr = bits[SEQDEC_TMP_RAM_ADDR_WIDTH]; +pub type SeqDecTmpRamData = bits[SEQDEC_TMP_RAM_DATA_WIDTH]; + +pub type SeqDecFseRamReadReq = ram::ReadReq; +pub type SeqDecFseRamReadResp = ram::ReadResp; +pub type SeqDecFseRamWriteReq = ram::WriteReq; +pub type SeqDecFseRamWriteResp = ram::WriteResp; +pub type SeqDecFseRamAddr = bits[SEQDEC_FSE_RAM_ADDR_WIDTH]; +pub type SeqDecFseRamData = bits[SEQDEC_FSE_RAM_DATA_WIDTH]; + +pub type SeqDecBlockRamReadReq = ram::ReadReq; +pub type SeqDecBlockRamReadResp = ram::ReadResp; +pub type SeqDecBlockRamWriteReq = ram::WriteReq; +pub type SeqDecBlockRamWriteResp = ram::WriteResp; +pub type SeqDecBlockRamAddr = bits[SEQDEC_BLOCK_RAM_ADDR_WIDTH]; +pub type SeqDecBlockRamData = bits[SEQDEC_BLOCK_RAM_DATA_WIDTH]; + +pub type SeqDecShiftBufferCtrl = shift_buffer::ShiftBufferCtrl; +pub type SeqDecShiftBufferInput = shift_buffer::ShiftBufferPacket; +pub type SeqDecShiftBufferOutput = shift_buffer::ShiftBufferOutput; +pub type SeqDecShiftBufferPacket = shift_buffer::ShiftBufferPacket; +pub type SeqDecShiftBufferStatus = shift_buffer::ShiftBufferStatus; diff --git a/xls/modules/zstd/fse_dec.x b/xls/modules/zstd/fse_dec.x new file mode 100644 index 0000000000..01a1416862 --- /dev/null +++ b/xls/modules/zstd/fse_dec.x @@ -0,0 +1,1320 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.math; +import xls.modules.zstd.refilling_shift_buffer; +import xls.modules.zstd.fse_table_creator; + +type FseTableRecord = common::FseTableRecord; + +// +// type Base = u16; +// type Symbol = u16; +// type NumOfBits = u16; +// +// struct FseTableRecord { +// symbol: Symbol, +// num_of_bits: NumOfBits, +// base: Base +// } +// +// pub fn bits_to_fse_record(bit: u48) -> FseTableRecord { +// FseTableRecord { +// symbol: bit[0:16], +// num_of_bits: bit[16:32], +// base: bit[32:48] +// } +// } +// +// fn fse_record_to_bits(record: FseTableRecord) -> u48 { +// record.base ++ record.num_of_bits ++ record.symbol +// } + + + +type BlockSyncData = common::BlockSyncData; +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; +type SequenceExecutorPacket = common::SequenceExecutorPacket; +type CommandConstructorData = common::CommandConstructorData; + +type CopyOrMatchLength = common::CopyOrMatchLength; +type CopyOrMatchContent = common::CopyOrMatchContent; + +type RefillingSBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; +type RefillingSBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + +pub enum FseDecoderStatus: u1 { + OK = 0, + ERROR = 1, +} + +pub struct FseDecoderCtrl { + sync: BlockSyncData, + sequences_count: u24, + literals_count: u20, + of_acc_log: u7, + ll_acc_log: u7, + ml_acc_log: u7, +} + +pub struct FseDecoderFinish { + status: FseDecoderStatus +} + +// 3.1.1.3.2.1.1. Sequence Codes for Lengths and Offsets +const SEQ_MAX_CODES_LL = u8:35; +const SEQ_MAX_CODES_ML = u8:51; + +const SEQ_LITERAL_LENGTH_BASELINES = u32[36]:[ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 18, 20, 22, 24, 28, 32, 40, + 48, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 +]; +const SEQ_LITERAL_LENGTH_EXTRA_BITS = u8[36]:[ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 2, 2, 3, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +]; + +const SEQ_MATCH_LENGTH_BASELINES = u32[53]:[ + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32, 33, 34, 35, 37, 39, 41, 43, 47, 51, 59, 67, 83, + 99, 131, 259, 515, 1027, 2051, 4099, 8195, 16387, 32771, 65539 +]; +const SEQ_MATCH_LENGTH_EXTRA_BITS = u8[53]:[ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + 2, 2, 3, 3, 4, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 +]; + +enum SEQ_PART : u2 { + LiteralLength = 0, + Offset = 1, + MatchLength = 2, +} + +enum FseDecoderFSM : u5 { + RECV_CTRL = 0, + PADDING = 1, + INIT_OF_STATE = 2, + INIT_ML_STATE = 3, + INIT_LL_STATE = 4, + SEND_RAM_RD_REQ = 5, + RECV_RAM_RD_RESP = 6, + READ_OF_BITS = 7, + READ_ML_BITS = 8, + READ_LL_BITS = 9, + UPDATE_OF_STATE = 10, + UPDATE_ML_STATE = 11, + UPDATE_LL_STATE = 12, + SEND_COMMAND_LITERAL = 13, + SEND_COMMAND_SEQUENCE = 14, + SEND_LEFTOVER_LITERALS_REQ = 15, + SEND_FINISH = 16, +} + +struct FseDecoderState { + fsm: FseDecoderFSM, + ctrl: FseDecoderCtrl, + sequences_count: u24, + literals_count: u20, + of: u64, + ll: u64, + ml: u64, + of_fse_table_record: FseTableRecord, + ll_fse_table_record: FseTableRecord, + ml_fse_table_record: FseTableRecord, + of_fse_table_record_valid: bool, + ll_fse_table_record_valid: bool, + ml_fse_table_record_valid: bool, + of_state: u16, + ll_state: u16, + ml_state: u16, + read_bits: u16, + read_bits_length: u7, + read_bits_needed: u7, + sent_buf_ctrl: bool, + shift_buffer_error: bool, + padding: u4, +} + +pub proc FseDecoder< + RAM_DATA_W: u32, RAM_ADDR_W: u32, RAM_NUM_PARTITIONS:u32, + AXI_DATA_W: u32, + REFILLING_SB_DATA_W: u32 = {AXI_DATA_W}, + REFILLING_SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(REFILLING_SB_DATA_W)}, +> { + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + + type RefillingSBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type RefillingSBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + + // control + ctrl_r: chan in; + finish_s: chan out; + + // shift buffer + rsb_ctrl_s: chan out; + rsb_data_r: chan in; + + // output command + command_s: chan out; + + // RAMs + ll_fse_rd_req_s: chan out; + ll_fse_rd_resp_r: chan in; + + ml_fse_rd_req_s: chan out; + ml_fse_rd_resp_r: chan in; + + of_fse_rd_req_s: chan out; + of_fse_rd_resp_r: chan in; + + config ( + ctrl_r: chan in, + finish_s: chan out, + rsb_ctrl_s: chan out, + rsb_data_r: chan in, + command_s: chan out, + ll_fse_rd_req_s: chan out, + ll_fse_rd_resp_r: chan in, + ml_fse_rd_req_s: chan out, + ml_fse_rd_resp_r: chan in, + of_fse_rd_req_s: chan out, + of_fse_rd_resp_r: chan in, + ) { + ( + ctrl_r, finish_s, + rsb_ctrl_s, rsb_data_r, + command_s, + ll_fse_rd_req_s, ll_fse_rd_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, + ) + } + + init { zero!() } + + next (state: FseDecoderState) { + type RamAddr = uN[RAM_ADDR_W]; + const RAM_MASK_ALL = std::unsigned_max_value(); + + let tok0 = join(); + + // receive ctrl + let (_, ctrl, ctrl_valid) = recv_if_non_blocking(tok0, ctrl_r, state.fsm == FseDecoderFSM::RECV_CTRL, zero!()); + if ctrl_valid { + trace_fmt!("ctrl: {:#x}", ctrl); + } else {}; + let state = if ctrl_valid { + FseDecoderState { + ctrl: ctrl, + sequences_count: ctrl.sequences_count, + ..state + } + } else { state }; + + // receive ram read response + let (_, ll_rd_resp, ll_rd_resp_valid) = recv_if_non_blocking(tok0, ll_fse_rd_resp_r, state.fsm == FseDecoderFSM::RECV_RAM_RD_RESP, zero!()); + let (_, ml_rd_resp, ml_rd_resp_valid) = recv_if_non_blocking(tok0, ml_fse_rd_resp_r, state.fsm == FseDecoderFSM::RECV_RAM_RD_RESP, zero!()); + let (_, of_rd_resp, of_rd_resp_valid) = recv_if_non_blocking(tok0, of_fse_rd_resp_r, state.fsm == FseDecoderFSM::RECV_RAM_RD_RESP, zero!()); + + let ll_fse_table_record = fse_table_creator::bits_to_fse_record(ll_rd_resp.data); + let ml_fse_table_record = fse_table_creator::bits_to_fse_record(ml_rd_resp.data); + let of_fse_table_record = fse_table_creator::bits_to_fse_record(of_rd_resp.data); + + // if ll_rd_resp_valid { + // trace_fmt!("ll_fse_table_record: {:#x}", ll_fse_table_record); + // } else {}; + // if ml_rd_resp_valid { + // trace_fmt!("ml_fse_table_record: {:#x}", ml_fse_table_record); + // } else {}; + // if of_rd_resp_valid { + // trace_fmt!("of_fse_table_record: {:#x}", of_fse_table_record); + // } else {}; + // validate LL and ML symbols + assert!(!(ll_rd_resp_valid && ll_fse_table_record.symbol > SEQ_MAX_CODES_LL), "invalid_literal_length_symbol"); + assert!(!(ml_rd_resp_valid && ml_fse_table_record.symbol > SEQ_MAX_CODES_ML), "invalid_match_length_symbol"); + + // request records + let do_send_ram_rd_req = state.fsm == FseDecoderFSM::SEND_RAM_RD_REQ; + + let ll_req = FseRamRdReq { addr: state.ll_state as RamAddr, mask: RAM_MASK_ALL}; + let ml_req = FseRamRdReq { addr: state.ml_state as RamAddr, mask: RAM_MASK_ALL}; + let of_req = FseRamRdReq { addr: state.of_state as RamAddr, mask: RAM_MASK_ALL}; + + send_if(tok0, ll_fse_rd_req_s, do_send_ram_rd_req, ll_req); + send_if(tok0, ml_fse_rd_req_s, do_send_ram_rd_req, ml_req); + send_if(tok0, of_fse_rd_req_s, do_send_ram_rd_req, of_req); + + if do_send_ram_rd_req { + trace_fmt!("ll_req: {:#x}", ll_req); + trace_fmt!("ml_req: {:#x}", ml_req); + trace_fmt!("of_req: {:#x}", of_req); + } else {}; + + // read bits + let do_read_bits = ( + state.fsm == FseDecoderFSM::PADDING || + state.fsm == FseDecoderFSM::INIT_OF_STATE || + state.fsm == FseDecoderFSM::INIT_ML_STATE || + state.fsm == FseDecoderFSM::INIT_LL_STATE || + state.fsm == FseDecoderFSM::READ_OF_BITS || + state.fsm == FseDecoderFSM::READ_ML_BITS || + state.fsm == FseDecoderFSM::READ_LL_BITS || + state.fsm == FseDecoderFSM::UPDATE_OF_STATE || + state.fsm == FseDecoderFSM::UPDATE_ML_STATE || + state.fsm == FseDecoderFSM::UPDATE_LL_STATE + ); + let do_send_buf_ctrl = do_read_bits && !state.sent_buf_ctrl; + + let buf_ctrl_length = if ((state.read_bits_needed - state.read_bits_length) > REFILLING_SB_DATA_W as u7) { + REFILLING_SB_DATA_W as u7 + } else { + state.read_bits_needed - state.read_bits_length + }; + + if do_send_buf_ctrl { + trace_fmt!("Asking for {:#x} data", buf_ctrl_length); + } else {}; + + send_if(tok0, rsb_ctrl_s, do_send_buf_ctrl, RefillingSBCtrl { + length: buf_ctrl_length, + }); + + let state = if do_send_buf_ctrl { + FseDecoderState { sent_buf_ctrl: do_send_buf_ctrl, ..state } + } else { state }; + + let recv_sb_output = (do_read_bits && state.sent_buf_ctrl); + let (_, buf_data, buf_data_valid) = recv_if_non_blocking(tok0, rsb_data_r, recv_sb_output, zero!()); + if buf_data_valid { + trace_fmt!("[FseDecoder] Received data {:#x} in state {}", buf_data, state.fsm); + } else { }; + + let state = if do_read_bits & buf_data_valid { + FseDecoderState { + sent_buf_ctrl: false, + read_bits: math::logshiftl(buf_data.data as u16, state.read_bits_length) | state.read_bits, + read_bits_length: state.read_bits_length + buf_data.length, + shift_buffer_error: state.shift_buffer_error | buf_data.error, + ..state + } + } else { state }; + + // send command + let literals_count = state.literals_count + state.ll as u20; + let command_data = if state.fsm == FseDecoderFSM::SEND_COMMAND_LITERAL { + trace_fmt!("(ll: {:#x}, ml: {:#x}, of: {:#x}", state.ll, state.ml, state.of); + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: state.ll, + content: CopyOrMatchContent:0, + last: false, + } + } else if state.fsm == FseDecoderFSM::SEND_COMMAND_SEQUENCE { + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: state.ml, + content: state.of, + last: (state.sequences_count == u24:1) && (state.literals_count == state.ctrl.literals_count), + } + } else { + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: (state.ctrl.literals_count - state.literals_count) as CopyOrMatchLength, + content: CopyOrMatchContent:0, + last: true, + } + }; + let do_send_command = ( + (command_data.length != CopyOrMatchLength:0) && + ( + state.fsm == FseDecoderFSM::SEND_COMMAND_LITERAL || + state.fsm == FseDecoderFSM::SEND_COMMAND_SEQUENCE || + state.fsm == FseDecoderFSM::SEND_LEFTOVER_LITERALS_REQ + ) + ); + let command = CommandConstructorData { + sync: state.ctrl.sync, + data: command_data, + }; + + if do_send_command { + trace_fmt!("[FseDecoder] Sending command: {:#x}", command); + } else {}; + send_if(tok0, command_s, do_send_command, command); + + // send finish + send_if(tok0, finish_s, state.fsm == FseDecoderFSM::SEND_FINISH, FseDecoderFinish { + status: if state.shift_buffer_error { FseDecoderStatus::ERROR } else { FseDecoderStatus::OK } + }); + + // update state + match (state.fsm) { + FseDecoderFSM::RECV_CTRL => { + if (ctrl_valid) { + trace_fmt!("[FseDecoder]: Moving to PADDING"); + if ctrl.sequences_count == u24:0 { + FseDecoderState { + fsm: FseDecoderFSM::SEND_LEFTOVER_LITERALS_REQ, + ctrl: ctrl, + ..state + } + } else { + FseDecoderState { + fsm: FseDecoderFSM::PADDING, + ctrl: ctrl, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: u7:1, + ..state + } + } + } else { state } + }, + FseDecoderFSM::PADDING => { + if (state.read_bits_needed == state.read_bits_length && !state.sent_buf_ctrl) { + trace_fmt!("[FseDecoder]: Moving to INIT_LL_STATE"); + + let padding = state.padding + u4:1; + assert!(padding <= u4:8, "invalid_padding"); + + let padding_available = (state.read_bits as u1 == u1:0); + if padding_available { + FseDecoderState { + fsm: FseDecoderFSM::PADDING, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: u7:1, + padding, ..state + } + } else { + trace_fmt!("padding is: {:#x}", padding); + FseDecoderState { + fsm: FseDecoderFSM::INIT_LL_STATE, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.ctrl.ll_acc_log, + ..state + } + } + } else { state } + }, + + FseDecoderFSM::INIT_LL_STATE => { + if (state.read_bits_needed == state.read_bits_length && !state.sent_buf_ctrl) { + trace_fmt!("[FseDecoder]: Moving to INIT_OF_STATE"); + FseDecoderState { + fsm: FseDecoderFSM::INIT_OF_STATE, + ll_state: state.read_bits, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.ctrl.of_acc_log, + ..state + } + } else { state } + }, + FseDecoderFSM::INIT_OF_STATE => { + if (state.read_bits_needed == state.read_bits_length && !state.sent_buf_ctrl) { + trace_fmt!("[FseDecoder]: Moving to INIT_ML_STATE"); + FseDecoderState { + fsm: FseDecoderFSM::INIT_ML_STATE, + of_state: state.read_bits, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.ctrl.ml_acc_log, + ..state + } + } else { state } + }, + FseDecoderFSM::INIT_ML_STATE => { + if (state.read_bits_needed == state.read_bits_length && !state.sent_buf_ctrl) { + trace_fmt!("[FseDecoder]: Moving to RAM_RD_REQ"); + FseDecoderState { + fsm: FseDecoderFSM::SEND_RAM_RD_REQ, + ml_state: state.read_bits, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: u7:0, + ..state + } + } else { state } + }, + FseDecoderFSM::SEND_RAM_RD_REQ => { + // trace_fmt!("State LL: {} ML: {} OF: {}", state.ll_state, state.ml_state, state.of_state); + trace_fmt!("State LL: {:#x} ML: {:#x} OF: {:#x}", state.ll_state, state.ml_state, state.of_state); + FseDecoderState { + fsm: FseDecoderFSM::RECV_RAM_RD_RESP, + ll_fse_table_record_valid: false, + ml_fse_table_record_valid: false, + of_fse_table_record_valid: false, + ..state + } + }, + FseDecoderFSM::RECV_RAM_RD_RESP => { + trace_fmt!("RECV_RAM_RD_RESP"); + // save fse records in state + let state = if ll_rd_resp_valid { + FseDecoderState { ll_fse_table_record: ll_fse_table_record, ll_fse_table_record_valid: true, ..state } + } else { state }; + let state = if ml_rd_resp_valid { + FseDecoderState { ml_fse_table_record: ml_fse_table_record, ml_fse_table_record_valid: true, ..state } + } else { state }; + let state = if of_rd_resp_valid { + FseDecoderState { of_fse_table_record: of_fse_table_record, of_fse_table_record_valid: true, ..state } + } else { state }; + + if (state.ll_fse_table_record_valid && + state.ml_fse_table_record_valid && + state.of_fse_table_record_valid + ) { + trace_fmt!("all states received: {:#x}", state); + FseDecoderState { + fsm: FseDecoderFSM::READ_OF_BITS, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.of_fse_table_record.symbol as u7, + ..state + } + } else { state } + }, + FseDecoderFSM::READ_OF_BITS => { + if ((state.read_bits_needed == state.read_bits_length) && !state.sent_buf_ctrl) { + trace_fmt!("of_code: {:#x}", state.of_fse_table_record.symbol); + FseDecoderState { + fsm: FseDecoderFSM::READ_ML_BITS, + of: (math::logshiftl(u32:1, state.of_fse_table_record.symbol) + state.read_bits as u32) as u64, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: SEQ_MATCH_LENGTH_EXTRA_BITS[state.ml_fse_table_record.symbol] as u7, + ..state + } + } else { state } + }, + FseDecoderFSM::READ_ML_BITS => { + if ((state.read_bits_needed == state.read_bits_length) && !state.sent_buf_ctrl) { + FseDecoderState { + fsm: FseDecoderFSM::READ_LL_BITS, + ml: (SEQ_MATCH_LENGTH_BASELINES[state.ml_fse_table_record.symbol] + state.read_bits as u32) as u64, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: SEQ_LITERAL_LENGTH_EXTRA_BITS[state.ll_fse_table_record.symbol] as u7, + ..state + } + } else { state } + + }, + FseDecoderFSM::READ_LL_BITS => { + if ((state.read_bits_needed == state.read_bits_length) && !state.sent_buf_ctrl) { + if state.sequences_count == u24:1 { + // skip state update for last sequence + FseDecoderState { + fsm: FseDecoderFSM::SEND_COMMAND_LITERAL, + of_state: state.of_fse_table_record.base + state.read_bits, + ll: (SEQ_LITERAL_LENGTH_BASELINES[state.ll_fse_table_record.symbol] + state.read_bits as u32) as u64, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: u7:0, + ..state + } + } else { + FseDecoderState { + fsm: FseDecoderFSM::UPDATE_LL_STATE, + ll: (SEQ_LITERAL_LENGTH_BASELINES[state.ll_fse_table_record.symbol] + state.read_bits as u32) as u64, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.ll_fse_table_record.num_of_bits as u7, + ..state + } + } + } else { state } + }, + FseDecoderFSM::UPDATE_LL_STATE => { + trace_fmt!("Values LL: {:#x} ML: {:#x} OF: {:#x}", state.ll, state.ml, state.of); + if ((state.read_bits_needed == state.read_bits_length) && !state.sent_buf_ctrl) { + FseDecoderState { + fsm: FseDecoderFSM::UPDATE_ML_STATE, + ll_state: state.ll_fse_table_record.base + state.read_bits, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.ml_fse_table_record.num_of_bits as u7, + ..state + } + } else { state } + }, + FseDecoderFSM::UPDATE_ML_STATE => { + if ((state.read_bits_needed == state.read_bits_length) && !state.sent_buf_ctrl) { + FseDecoderState { + fsm: FseDecoderFSM::UPDATE_OF_STATE, + ml_state: state.ml_fse_table_record.base + state.read_bits, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: state.of_fse_table_record.num_of_bits as u7, + ..state + } + } else { state } + }, + FseDecoderFSM::UPDATE_OF_STATE => { + if ((state.read_bits_needed == state.read_bits_length) && !state.sent_buf_ctrl) { + FseDecoderState { + fsm: FseDecoderFSM::SEND_COMMAND_LITERAL, + of_state: state.of_fse_table_record.base + state.read_bits, + read_bits: u16:0, + read_bits_length: u7:0, + read_bits_needed: u7:0, + ..state + } + } else { state } + }, + FseDecoderFSM::SEND_COMMAND_LITERAL => { + trace_fmt!("LITERALS_COUNT: {:#x}/{:#x}", literals_count, state.ctrl.literals_count); + FseDecoderState { + fsm: FseDecoderFSM::SEND_COMMAND_SEQUENCE, + literals_count, ..state + } + }, + FseDecoderFSM::SEND_COMMAND_SEQUENCE => { + if (state.sequences_count == u24:1) { + if state.literals_count < state.ctrl.literals_count { + trace_fmt!("Going to LEFTOVER"); + FseDecoderState { + fsm: FseDecoderFSM::SEND_LEFTOVER_LITERALS_REQ, + sequences_count: u24:0, + ..state + } + } else if state.literals_count == state.ctrl.literals_count { + trace_fmt!("Going to FINISH"); + FseDecoderState { + fsm: FseDecoderFSM::SEND_FINISH, + sequences_count: u24:0, + ..state + } + } else { + fail!("too_many_literals", zero!()) + } + } else { + FseDecoderState { + fsm: FseDecoderFSM::SEND_RAM_RD_REQ, + sequences_count: state.sequences_count - u24:1, + ..state + } + } + }, + FseDecoderFSM::SEND_LEFTOVER_LITERALS_REQ => { + FseDecoderState { + fsm:FseDecoderFSM::SEND_FINISH, + ..zero!() + } + }, + + FseDecoderFSM::SEND_FINISH => { + FseDecoderState { + fsm:FseDecoderFSM::RECV_CTRL, + ..zero!() + } + }, + _ => { + fail!("impossible_case", state) + }, + } + } +} + +const INST_RAM_SIZE = common::FSE_MAX_SYMBOLS; +const INST_RAM_ADDR_W = std::clog2(INST_RAM_SIZE); +const INST_RAM_DATA_W = u32:32; +const INST_RAM_WORD_PARTITION_SIZE = INST_RAM_DATA_W / u32:3; +const INST_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_RAM_WORD_PARTITION_SIZE, INST_RAM_DATA_W); +const INST_AXI_DATA_W = u32:64; +const INST_REFILLING_SB_DATA_W = INST_AXI_DATA_W; +const INST_REFILLING_SB_LENGTH_W = refilling_shift_buffer::length_width(INST_REFILLING_SB_DATA_W); + +pub proc FseDecoderInst { + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + + type RefillingSBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type RefillingSBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + + config ( + ctrl_r: chan in, + finish_s: chan out, + rsb_ctrl_s: chan out, + rsb_data_r: chan in, + command_s: chan out, + ll_fse_rd_req_s: chan out, + ll_fse_rd_resp_r: chan in, + ml_fse_rd_req_s: chan out, + ml_fse_rd_resp_r: chan in, + of_fse_rd_req_s: chan out, + of_fse_rd_resp_r: chan in, + ) { + spawn FseDecoder< + INST_RAM_DATA_W, INST_RAM_ADDR_W, INST_RAM_NUM_PARTITIONS, + INST_AXI_DATA_W, + >( + ctrl_r, finish_s, + rsb_ctrl_s, rsb_data_r, + command_s, + ll_fse_rd_req_s, ll_fse_rd_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, + ); + } + + init { () } + + next (state: ()) {} +} + +// test data was generated using decodecorpus and educational_decoder from zstd repository +// block #0 seed: 58602 +// block #1 seed: 48401 + +const TEST_OF_TABLE = u32[256][2]:[[ + u32:0x00_03_0008, u32:0x02_02_0004, u32:0x03_02_0014, u32:0x03_02_0018, u32:0x04_03_0008, u32:0x00_03_0010, u32:0x02_02_0008, u32:0x03_02_001c, + u32:0x03_01_0000, u32:0x04_03_0010, u32:0x02_02_000c, u32:0x02_02_0010, u32:0x03_01_0002, u32:0x04_03_0018, u32:0x00_03_0018, u32:0x02_02_0014, + u32:0x03_01_0004, u32:0x03_01_0006, u32:0x04_02_0000, u32:0x02_02_0018, u32:0x02_02_001c, u32:0x03_01_0008, u32:0x03_01_000a, u32:0x00_02_0000, + u32:0x02_01_0000, u32:0x03_01_000c, u32:0x03_01_000e, u32:0x04_02_0004, u32:0x00_02_0004, u32:0x02_01_0002, u32:0x03_01_0010, u32:0x03_01_0012, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0031, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_0100, u32:0x00_00_0101, u32:0x00_00_0003, u32:0x00_00_0101, u32:0x00_00_0301, u32:0x00_00_0101, u32:0x00_00_0301, u32:0x00_00_0100, + u32:0x03_08_0101, u32:0x02_00_0103, u32:0x02_04_0101, u32:0x02_00_0001, u32:0x03_14_0101, u32:0x03_00_0301, u32:0x02_18_0100, u32:0x02_00_0101, + u32:0x01_08_0000, u32:0x03_00_0000, u32:0x02_10_0000, u32:0x02_00_0000, u32:0x01_08_0031, u32:0x03_00_0000, u32:0x03_1c_0000, u32:0x02_00_0000, + u32:0x01_00_0103, u32:0x01_00_0101, u32:0x02_10_0303, u32:0x02_00_0101, u32:0x02_0c_0301, u32:0x01_00_0101, u32:0x01_10_0301, u32:0x02_00_0103, + u32:0x01_02_0000, u32:0x01_00_0002, u32:0x01_18_0000, u32:0x02_00_0200, u32:0x02_18_0000, u32:0x01_00_0200, u32:0x01_14_0002, u32:0x01_00_0000, + u32:0x00_04_0000, u32:0x00_00_0000, u32:0x00_06_0000, u32:0x00_00_0000, u32:0x00_00_0051, u32:0x00_00_0000, u32:0x00_18_0000, u32:0x00_00_0000, + u32:0x51_1c_0008, u32:0x00_00_000c, u32:0x00_08_000e, u32:0x00_00_0010, u32:0x00_0a_0008, u32:0x00_00_0010, u32:0x00_00_0012, u32:0x00_00_0014, + u32:0x08_00_0016, u32:0x00_00_0010, u32:0x04_0c_0018, u32:0x00_00_001a, u32:0x14_0e_001c, u32:0x00_00_0018, u32:0x18_04_0018, u32:0x00_00_001e, + u32:0x08_04_0000, u32:0x00_00_0001, u32:0x10_02_0000, u32:0x00_00_0002, u32:0x08_10_0003, u32:0x00_00_0004, u32:0x1c_12_0005, u32:0x00_00_0000, + u32:0x00_00_0006, u32:0x00_00_0007, u32:0x10_00_0008, u32:0x00_00_0004, u32:0x0c_00_0004, u32:0x00_00_0009, u32:0x10_00_000a, u32:0x00_00_000b, + u32:0x02_31_0000, u32:0x00_00_0000, u32:0x18_00_0000, u32:0x00_00_0000, u32:0x18_00_0411, u32:0x00_00_0000, u32:0x14_00_0000, u32:0x00_00_0000, + u32:0x04_00_3230, u32:0x00_01_3020, u32:0x06_01_2030, u32:0x00_01_3233, u32:0x00_03_3033, u32:0x00_00_2020, u32:0x18_01_3030, u32:0x00_01_3020, + u32:0x1c_01_2031, u32:0x00_03_3033, u32:0x08_01_3333, u32:0x00_01_2020, u32:0x0a_01_3830, u32:0x00_03_3020, u32:0x00_00_2031, u32:0x00_01_3333, + u32:0x00_01_3333, u32:0x00_01_2020, u32:0x0c_03_3030, u32:0x00_01_3020, u32:0x0e_01_2031, u32:0x00_01_3033, u32:0x04_01_3032, u32:0x00_00_2020, + u32:0x04_01_6530, u32:0x00_01_3020, u32:0x02_01_2031, u32:0x00_03_3032, u32:0x10_00_3133, u32:0x00_01_2020, u32:0x12_01_3030, u32:0x00_01_3020, + u32:0x00_00_2031, u32:0x00_00_3032, u32:0x00_00_3032, u32:0x00_00_2020, u32:0x00_00_3231, u32:0x00_00_3020, u32:0x00_00_2031, u32:0x00_00_3032, + u32:0x31_31_3133, u32:0x00_00_2020, u32:0x00_00_3030, u32:0x00_00_3020, u32:0x00_00_2030, u32:0x00_00_3033, u32:0x00_00_3233, u32:0x00_00_2020, + u32:0x00_03_000a, u32:0x01_01_0000, u32:0x01_01_0000, u32:0x01_01_0000, u32:0x03_03_0000, u32:0x00_03_0000, u32:0x01_01_0000, u32:0x01_01_0000, + u32:0x01_01_0000, u32:0x03_03_0000, u32:0x01_01_0000, u32:0x01_01_0000, u32:0x01_01_0000, u32:0x03_03_0000, u32:0x00_03_0000, u32:0x01_01_0000, + u32:0x01_00_0000, u32:0x01_00_0000, u32:0x03_02_0000, u32:0x01_00_0000, u32:0x01_00_0000, u32:0x01_00_0000, u32:0x01_00_0000, u32:0x00_02_0000, + u32:0x01_00_0000, u32:0x01_00_0000, u32:0x01_00_0000, u32:0x03_02_0000, u32:0x00_02_0000, u32:0x01_00_0000, u32:0x01_00_0000, u32:0x01_00_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x03_08_0000, u32:0x01_00_0000, u32:0x01_0c_0000, u32:0x01_00_0000, u32:0x03_0e_0000, u32:0x03_00_0000, u32:0x01_10_0000, u32:0x01_00_0000, + u32:0x01_08_0000, u32:0x03_00_0000, u32:0x01_10_0000, u32:0x01_00_0000, u32:0x01_12_0000, u32:0x03_00_0000, u32:0x03_14_0000, u32:0x01_00_0000, + u32:0x00_16_0000, u32:0x00_00_0000, u32:0x02_10_0000, u32:0x00_00_0000, u32:0x00_18_0000, u32:0x00_00_0000, u32:0x00_1a_0000, u32:0x02_00_0000, + u32:0x00_1c_0000, u32:0x00_00_0000, u32:0x00_18_0000, u32:0x02_00_0000, u32:0x02_18_0000, u32:0x00_00_0000, u32:0x00_1e_0000, u32:0x00_00_0000, +],[ + u32:0x00_05_0000, u32:0x06_04_0000, u32:0x09_05_0000, u32:0x0f_05_0000, u32:0x15_05_0000, u32:0x03_05_0000, u32:0x07_04_0000, u32:0x0c_05_0000, + u32:0x12_05_0000, u32:0x17_05_0000, u32:0x05_05_0000, u32:0x08_04_0000, u32:0x0e_05_0000, u32:0x14_05_0000, u32:0x02_05_0000, u32:0x07_04_0010, + u32:0x0b_05_0000, u32:0x11_05_0000, u32:0x16_05_0000, u32:0x04_05_0000, u32:0x08_04_0010, u32:0x0d_05_0000, u32:0x13_05_0000, u32:0x01_05_0000, + u32:0x06_04_0010, u32:0x0a_05_0000, u32:0x10_05_0000, u32:0x1c_05_0000, u32:0x1b_05_0000, u32:0x1a_05_0000, u32:0x19_05_0000, u32:0x18_05_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0051, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_0100, u32:0x00_00_0302, u32:0x00_00_0605, u32:0x00_00_0a08, u32:0x00_00_100d, u32:0x00_00_1613, u32:0x00_00_1c19, u32:0x00_00_211f, + u32:0x05_00_2523, u32:0x04_00_2927, u32:0x05_00_2d2b, u32:0x05_00_0201, u32:0x05_00_0403, u32:0x05_00_0706, u32:0x04_00_0c09, u32:0x05_00_120f, + u32:0x05_00_1815, u32:0x05_00_1e1b, u32:0x05_00_2220, u32:0x04_00_2624, u32:0x05_00_2a28, u32:0x05_00_012c, u32:0x05_00_0201, u32:0x04_00_0504, + u32:0x05_00_0807, u32:0x05_00_0e0b, u32:0x05_00_1411, u32:0x05_00_1a17, u32:0x04_00_341d, u32:0x05_00_3233, u32:0x05_00_3031, u32:0x05_00_2e2f, + u32:0x04_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0051, u32:0x05_00_0000, u32:0x05_10_0000, u32:0x05_00_0000, + u32:0x00_00_0406, u32:0x00_00_0505, u32:0x00_00_0505, u32:0x00_00_0605, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, + u32:0x51_10_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0404, u32:0x00_00_0505, u32:0x00_00_0505, u32:0x00_00_0606, u32:0x00_00_0606, + u32:0x00_10_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0406, u32:0x00_00_0404, u32:0x00_00_0505, + u32:0x00_00_0505, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0091, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_51_0000, u32:0x00_00_0000, u32:0x00_00_0020, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x10_00_0000, u32:0x00_00_0000, + u32:0x00_00_0000, u32:0x00_01_0000, u32:0x00_02_0000, u32:0x00_03_0000, u32:0x00_05_0000, u32:0x00_06_0000, u32:0x00_08_0000, u32:0x00_0a_0000, + u32:0x10_0d_0000, u32:0x00_10_0000, u32:0x00_13_0000, u32:0x00_16_0000, u32:0x00_19_0000, u32:0x00_1c_0000, u32:0x00_1f_0010, u32:0x00_21_0000, + u32:0x10_23_0020, u32:0x00_25_0000, u32:0x00_27_0020, u32:0x00_29_0000, u32:0x00_2b_0000, u32:0x00_2d_0000, u32:0x00_01_0000, u32:0x00_02_0000, + u32:0x00_03_0000, u32:0x00_04_0000, u32:0x00_06_0000, u32:0x00_07_0000, u32:0x00_09_0000, u32:0x00_0c_0000, u32:0x00_0f_0000, u32:0x00_12_0000, + u32:0x00_15_0000, u32:0x00_18_0000, u32:0x00_1b_0000, u32:0x00_1e_0020, u32:0x00_20_0030, u32:0x00_22_0010, u32:0x00_24_0020, u32:0x00_26_0020, + u32:0x51_28_0020, u32:0x00_2a_0020, u32:0x00_2c_0000, u32:0x00_01_0000, u32:0x00_01_0000, u32:0x00_02_0000, u32:0x00_04_0000, u32:0x00_05_0000, + u32:0x00_07_0000, u32:0x01_08_0000, u32:0x02_0b_0000, u32:0x03_0e_0000, u32:0x05_11_0000, u32:0x06_14_0000, u32:0x08_17_0000, u32:0x0a_1a_0000, + u32:0x0d_1d_0000, u32:0x10_34_0000, u32:0x13_33_0000, u32:0x16_32_0000, u32:0x19_31_0411, u32:0x1c_30_0000, u32:0x1f_2f_0000, u32:0x21_2e_0000, + u32:0x23_00_6430, u32:0x25_00_3020, u32:0x27_00_2030, u32:0x29_00_3436, u32:0x2b_00_3033, u32:0x2d_00_2020, u32:0x01_00_3532, u32:0x02_00_3020, + u32:0x03_51_2030, u32:0x04_00_3033, u32:0x06_00_3333, u32:0x07_00_2020, u32:0x09_00_3630, u32:0x0c_00_3020, u32:0x0f_00_2030, u32:0x12_00_3333, + u32:0x15_06_3333, u32:0x18_04_2020, u32:0x1b_05_3730, u32:0x1e_05_3020, u32:0x20_05_2035, u32:0x22_05_3033, u32:0x24_05_3032, u32:0x26_06_2020, + u32:0x28_06_3032, u32:0x2a_06_3020, u32:0x2c_06_2035, u32:0x01_06_3032, u32:0x01_06_3533, u32:0x02_06_2020, u32:0x04_06_3230, u32:0x05_06_3020, + u32:0x07_06_2036, u32:0x08_06_3032, u32:0x0b_06_3032, u32:0x0e_06_2020, u32:0x11_06_3430, u32:0x14_06_3020, u32:0x17_04_2036, u32:0x1a_04_3032, + u32:0x1d_05_3633, u32:0x34_05_2020, u32:0x33_05_6131, u32:0x32_05_3020, u32:0x31_06_2034, u32:0x30_06_3033, u32:0x2f_06_3233, u32:0x2e_06_2020, + u32:0x00_06_000a, u32:0x00_06_0000, u32:0x00_06_0000, u32:0x00_06_0000, u32:0x00_06_0000, u32:0x00_06_0000, u32:0x00_06_0000, u32:0x00_06_0000, + u32:0x51_06_0000, u32:0x00_06_0000, u32:0x00_06_0000, u32:0x00_04_0000, u32:0x00_04_0000, u32:0x00_04_0000, u32:0x00_05_0000, u32:0x00_05_0000, +]]; + +const TEST_ML_TABLE = u32[256][2]:[[ + u32:0x00_03_0008, u32:0x01_01_000c, u32:0x01_01_000e, u32:0x01_01_0010, u32:0x03_03_0008, u32:0x00_03_0010, u32:0x01_01_0012, u32:0x01_01_0014, + u32:0x01_01_0016, u32:0x03_03_0010, u32:0x01_01_0018, u32:0x01_01_001a, u32:0x01_01_001c, u32:0x03_03_0018, u32:0x00_03_0018, u32:0x01_01_001e, + u32:0x01_00_0000, u32:0x01_00_0001, u32:0x03_02_0000, u32:0x01_00_0002, u32:0x01_00_0003, u32:0x01_00_0004, u32:0x01_00_0005, u32:0x00_02_0000, + u32:0x01_00_0006, u32:0x01_00_0007, u32:0x01_00_0008, u32:0x03_02_0004, u32:0x00_02_0004, u32:0x01_00_0009, u32:0x01_00_000a, u32:0x01_00_000b, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0411, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_3030, u32:0x00_00_3520, u32:0x00_00_2031, u32:0x00_00_3033, u32:0x00_00_3033, u32:0x00_00_2020, u32:0x00_00_3030, u32:0x00_00_3020, + u32:0x03_08_2030, u32:0x01_00_3533, u32:0x01_0c_3333, u32:0x01_00_2020, u32:0x03_0e_3130, u32:0x03_00_3020, u32:0x01_10_2063, u32:0x01_00_3333, + u32:0x01_08_3333, u32:0x03_00_2020, u32:0x01_10_3130, u32:0x01_00_3020, u32:0x01_12_2030, u32:0x03_00_3033, u32:0x03_14_3032, u32:0x01_00_2020, + u32:0x00_16_3130, u32:0x00_00_3120, u32:0x02_10_2032, u32:0x00_00_3032, u32:0x00_18_3033, u32:0x00_00_2020, u32:0x00_1a_3030, u32:0x02_00_3020, + u32:0x00_1c_2030, u32:0x00_00_3032, u32:0x00_18_3032, u32:0x02_00_2020, u32:0x02_18_3030, u32:0x00_00_3120, u32:0x00_1e_2061, u32:0x00_00_3032, + u32:0x00_00_3136, u32:0x00_00_2020, u32:0x00_01_3030, u32:0x00_00_3020, u32:0x00_00_2030, u32:0x00_00_3033, u32:0x00_02_3233, u32:0x00_00_2020, + u32:0x51_03_000a, u32:0x00_00_0000, u32:0x00_04_0000, u32:0x00_00_0000, u32:0x00_05_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x08_06_0000, u32:0x00_00_0000, u32:0x0c_07_0000, u32:0x00_00_0000, u32:0x0e_08_0000, u32:0x00_00_0000, u32:0x10_04_0000, u32:0x00_00_0000, + u32:0x08_04_0000, u32:0x00_00_0000, u32:0x10_09_0000, u32:0x00_00_0000, u32:0x12_0a_0000, u32:0x00_00_0000, u32:0x14_0b_0000, u32:0x00_00_0000, + u32:0x16_00_0000, u32:0x00_00_0000, u32:0x10_00_0000, u32:0x00_00_0000, u32:0x18_00_0000, u32:0x00_00_0000, u32:0x1a_00_0000, u32:0x00_00_0000, + u32:0x1c_11_0000, u32:0x00_04_0000, u32:0x18_00_0000, u32:0x00_00_0000, u32:0x18_00_0000, u32:0x00_00_0000, u32:0x1e_00_0000, u32:0x00_00_0000, + u32:0x00_31_0000, u32:0x00_30_0000, u32:0x01_20_0000, u32:0x00_33_0000, u32:0x00_31_0000, u32:0x00_20_0000, u32:0x02_30_0000, u32:0x00_30_0000, + u32:0x03_30_0000, u32:0x00_30_0000, u32:0x04_20_0000, u32:0x00_20_0000, u32:0x05_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_33_0000, + u32:0x06_30_0000, u32:0x00_20_0000, u32:0x07_30_0000, u32:0x00_30_0000, u32:0x08_30_0000, u32:0x00_30_0000, u32:0x04_20_0000, u32:0x00_20_0000, + u32:0x04_30_0000, u32:0x00_37_0000, u32:0x09_20_0000, u32:0x00_32_0000, u32:0x0a_30_0000, u32:0x00_20_0000, u32:0x0b_30_0000, u32:0x00_30_0000, + u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_20_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_32_0000, + u32:0x11_30_0000, u32:0x04_20_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_20_0000, + u32:0x31_30_0000, u32:0x31_30_0000, u32:0x20_20_0000, u32:0x33_33_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x30_30_0000, u32:0x30_30_0000, + u32:0x30_30_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x20_20_0000, u32:0x33_32_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x33_33_0000, + u32:0x30_30_0000, u32:0x20_20_0000, u32:0x30_30_0000, u32:0x30_30_0000, u32:0x30_30_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x20_20_0000, + u32:0x33_32_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x32_32_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x30_30_0000, u32:0x30_30_0000, + u32:0x30_30_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x20_20_0000, u32:0x32_33_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x32_33_0000, + u32:0x30_33_0000, u32:0x20_20_0000, u32:0x30_30_0000, u32:0x30_30_0000, u32:0x30_30_0000, u32:0x30_30_0000, u32:0x20_20_0000, u32:0x20_20_0000, + u32:0x33_0a_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x33_00_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x30_00_0000, u32:0x30_00_0000, + u32:0x30_00_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x20_00_0000, u32:0x32_00_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x30_00_0000, + u32:0x30_00_0000, u32:0x20_00_0000, u32:0x30_00_0000, u32:0x30_00_0000, u32:0x30_00_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x20_00_0000, + u32:0x32_00_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x30_00_0000, u32:0x30_00_0000, u32:0x20_00_0000, u32:0x30_00_0000, u32:0x30_00_0000, +],[ + u32:0x00_06_0000, u32:0x01_04_0000, u32:0x02_05_0020, u32:0x03_05_0000, u32:0x05_05_0000, u32:0x06_05_0000, u32:0x08_05_0000, u32:0x0a_06_0000, + u32:0x0d_06_0000, u32:0x10_06_0000, u32:0x13_06_0000, u32:0x16_06_0000, u32:0x19_06_0000, u32:0x1c_06_0000, u32:0x1f_06_0000, u32:0x21_06_0000, + u32:0x23_06_0000, u32:0x25_06_0000, u32:0x27_06_0000, u32:0x29_06_0000, u32:0x2b_06_0000, u32:0x2d_06_0000, u32:0x01_04_0010, u32:0x02_04_0000, + u32:0x03_05_0020, u32:0x04_05_0000, u32:0x06_05_0020, u32:0x07_05_0000, u32:0x09_06_0000, u32:0x0c_06_0000, u32:0x0f_06_0000, u32:0x12_06_0000, + u32:0x15_06_0000, u32:0x18_06_0000, u32:0x1b_06_0000, u32:0x1e_06_0000, u32:0x20_06_0000, u32:0x22_06_0000, u32:0x24_06_0000, u32:0x26_06_0000, + u32:0x28_06_0000, u32:0x2a_06_0000, u32:0x2c_06_0000, u32:0x01_04_0020, u32:0x01_04_0030, u32:0x02_04_0010, u32:0x04_05_0020, u32:0x05_05_0020, + u32:0x07_05_0020, u32:0x08_05_0020, u32:0x0b_06_0000, u32:0x0e_06_0000, u32:0x11_06_0000, u32:0x14_06_0000, u32:0x17_06_0000, u32:0x1a_06_0000, + u32:0x1d_06_0000, u32:0x34_06_0000, u32:0x33_06_0000, u32:0x32_06_0000, u32:0x31_06_0000, u32:0x30_06_0000, u32:0x2f_06_0000, u32:0x2e_06_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0411, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x51_91_3030, u32:0x00_00_3920, u32:0x00_00_2031, u32:0x00_00_3033, u32:0x00_00_3033, u32:0x00_00_2020, u32:0x00_00_3030, u32:0x00_00_3020, + u32:0x06_00_2030, u32:0x04_00_3933, u32:0x05_00_3333, u32:0x05_00_2020, u32:0x05_20_3530, u32:0x05_00_3020, u32:0x05_00_2030, u32:0x06_00_3333, + u32:0x06_00_3333, u32:0x06_00_2020, u32:0x06_00_3530, u32:0x06_00_3020, u32:0x06_00_2030, u32:0x06_00_3033, u32:0x06_00_3032, u32:0x06_00_2020, + u32:0x06_00_3630, u32:0x06_00_3020, u32:0x06_00_2030, u32:0x06_00_3032, u32:0x06_00_3033, u32:0x06_00_2020, u32:0x04_00_3630, u32:0x04_00_3020, + u32:0x05_00_2030, u32:0x05_00_3032, u32:0x05_00_3032, u32:0x05_00_2020, u32:0x06_00_3430, u32:0x06_00_3020, u32:0x06_00_2030, u32:0x06_00_3032, + u32:0x06_00_3033, u32:0x06_00_2020, u32:0x06_00_3630, u32:0x06_00_3020, u32:0x06_00_2030, u32:0x06_00_3033, u32:0x06_00_3233, u32:0x06_00_2020, + u32:0x06_00_000a, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x04_00_0000, u32:0x04_10_0000, u32:0x04_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, + u32:0x05_20_0000, u32:0x05_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_20_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, + u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, u32:0x06_00_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x91_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x20_00_0000, u32:0x00_00_0000, u32:0x00_20_0000, u32:0x00_00_0000, + u32:0x00_30_0000, u32:0x00_00_0000, u32:0x00_10_0000, u32:0x00_00_0000, u32:0x00_20_0000, u32:0x00_00_0000, u32:0x00_20_0000, u32:0x00_00_0000, + u32:0x00_20_0000, u32:0x00_00_0000, u32:0x00_20_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x10_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x20_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x20_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_11_0000, u32:0x00_04_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_33_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_30_0000, u32:0x00_30_0000, + u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_20_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_33_0000, + u32:0x00_30_0000, u32:0x00_20_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x00_30_0000, u32:0x20_20_0000, u32:0x00_20_0000, + u32:0x30_30_0000, u32:0x00_30_0000, u32:0x10_20_0000, u32:0x00_32_0000, u32:0x20_30_0000, u32:0x00_20_0000, u32:0x20_30_0000, u32:0x00_30_0000, +]]; + +const TEST_LL_TABLE = u32[256][2]:[[ + u32:0x00_01_000e, u32:0x00_01_0010, u32:0x00_01_0012, u32:0x00_01_0014, u32:0x01_02_0004, u32:0x00_01_0016, u32:0x00_01_0018, u32:0x00_01_001a, + u32:0x01_02_0008, u32:0x01_02_000c, u32:0x00_01_001c, u32:0x00_01_001e, u32:0x00_00_0000, u32:0x01_02_0010, u32:0x00_00_0001, u32:0x00_00_0002, + u32:0x00_00_0003, u32:0x01_02_0014, u32:0x01_02_0018, u32:0x00_00_0004, u32:0x00_00_0005, u32:0x00_00_0006, u32:0x01_02_001c, u32:0x00_00_0007, + u32:0x00_00_0008, u32:0x00_00_0009, u32:0x00_00_000a, u32:0x01_01_0000, u32:0x00_00_000b, u32:0x00_00_000c, u32:0x00_00_000d, u32:0x01_01_0002, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0031, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_0200, u32:0x00_00_0303, u32:0x00_00_0004, u32:0x00_00_0302, u32:0x00_00_0403, u32:0x00_00_0202, u32:0x00_00_0403, u32:0x00_00_0200, + u32:0x01_0e_0303, u32:0x01_00_0204, u32:0x01_10_0302, u32:0x01_00_0003, u32:0x02_12_0302, u32:0x01_00_0403, u32:0x01_14_0200, u32:0x01_00_0303, + u32:0x02_04_0000, u32:0x02_00_0000, u32:0x01_16_0000, u32:0x01_00_0000, u32:0x00_18_0031, u32:0x02_00_0000, u32:0x00_1a_0000, u32:0x00_00_0000, + u32:0x00_08_0203, u32:0x02_00_0202, u32:0x02_0c_0303, u32:0x00_00_0202, u32:0x00_1c_0301, u32:0x00_00_0202, u32:0x02_1e_0301, u32:0x00_00_0203, + u32:0x00_00_0101, u32:0x00_00_0202, u32:0x00_10_0102, u32:0x01_00_0201, u32:0x00_01_0101, u32:0x00_00_0201, u32:0x00_02_0102, u32:0x01_00_0101, + u32:0x00_03_0000, u32:0x00_00_0000, u32:0x00_14_0000, u32:0x00_00_0000, u32:0x00_18_0051, u32:0x00_00_0000, u32:0x00_04_0000, u32:0x00_00_0000, + u32:0x51_05_0008, u32:0x00_00_0004, u32:0x00_06_0014, u32:0x00_00_0018, u32:0x00_1c_0008, u32:0x00_00_0010, u32:0x00_07_0008, u32:0x00_00_001c, + u32:0x0e_08_0000, u32:0x00_00_0010, u32:0x10_09_000c, u32:0x00_00_0010, u32:0x12_0a_0002, u32:0x00_00_0018, u32:0x14_00_0018, u32:0x00_00_0014, + u32:0x04_0b_0004, u32:0x00_00_0006, u32:0x16_0c_0000, u32:0x00_00_0018, u32:0x18_0d_001c, u32:0x00_00_0008, u32:0x1a_02_000a, u32:0x00_00_0000, + u32:0x08_00_0000, u32:0x00_00_000c, u32:0x0c_00_000e, u32:0x00_00_0004, u32:0x1c_00_0004, u32:0x00_00_0002, u32:0x1e_00_0010, u32:0x00_00_0012, + u32:0x00_31_0000, u32:0x00_00_0000, u32:0x10_00_0000, u32:0x00_00_0000, u32:0x01_00_0031, u32:0x00_00_0000, u32:0x02_00_0000, u32:0x00_00_0000, + u32:0x03_00_0100, u32:0x00_02_0101, u32:0x14_03_0003, u32:0x00_03_0101, u32:0x18_04_0301, u32:0x00_00_0101, u32:0x04_02_0301, u32:0x00_03_0100, + u32:0x05_03_0101, u32:0x00_04_0103, u32:0x06_02_0101, u32:0x00_02_0001, u32:0x1c_03_0101, u32:0x00_04_0301, u32:0x07_00_0100, u32:0x00_02_0101, + u32:0x08_03_0000, u32:0x00_03_0000, u32:0x09_04_0000, u32:0x00_02_0000, u32:0x0a_02_0031, u32:0x00_03_0000, u32:0x00_03_0000, u32:0x00_00_0000, + u32:0x0b_02_0103, u32:0x00_03_0101, u32:0x0c_03_0303, u32:0x00_04_0101, u32:0x0d_00_0301, u32:0x00_02_0101, u32:0x02_03_0301, u32:0x00_03_0103, + u32:0x00_00_0000, u32:0x00_00_0002, u32:0x00_00_0000, u32:0x00_00_0200, u32:0x00_00_0000, u32:0x00_00_0200, u32:0x00_00_0002, u32:0x00_00_0000, + u32:0x31_31_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0051, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x00_03_0008, u32:0x02_02_000c, u32:0x03_02_000e, u32:0x03_02_0010, u32:0x04_03_0008, u32:0x00_03_0010, u32:0x02_02_0012, u32:0x03_02_0014, + u32:0x03_01_0016, u32:0x04_03_0010, u32:0x02_02_0018, u32:0x02_02_001a, u32:0x03_01_001c, u32:0x04_03_0018, u32:0x00_03_0018, u32:0x02_02_001e, + u32:0x03_01_0000, u32:0x03_01_0001, u32:0x04_02_0000, u32:0x02_02_0002, u32:0x02_02_0003, u32:0x03_01_0004, u32:0x03_01_0005, u32:0x00_02_0000, + u32:0x02_01_0006, u32:0x03_01_0007, u32:0x03_01_0008, u32:0x04_02_0004, u32:0x00_02_0004, u32:0x02_01_0009, u32:0x03_01_000a, u32:0x03_01_000b, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0411, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_3030, u32:0x00_00_3520, u32:0x00_00_2031, u32:0x00_00_3033, u32:0x00_00_3033, u32:0x00_00_2020, u32:0x00_00_3030, u32:0x00_00_3020, + u32:0x03_08_2030, u32:0x02_00_3533, u32:0x02_04_3333, u32:0x02_00_2020, u32:0x03_14_3230, u32:0x03_00_3020, u32:0x02_18_2034, u32:0x02_00_3333, + u32:0x01_08_3333, u32:0x03_00_2020, u32:0x02_10_3230, u32:0x02_00_3020, u32:0x01_08_2030, u32:0x03_00_3033, u32:0x03_1c_3032, u32:0x02_00_2020, + u32:0x01_00_3130, u32:0x01_00_3020, u32:0x02_10_2038, u32:0x02_00_3032, u32:0x02_0c_3033, u32:0x01_00_2020, u32:0x01_10_3130, u32:0x02_00_3020, + u32:0x01_02_2030, u32:0x01_00_3032, u32:0x01_18_3032, u32:0x02_00_2020, u32:0x02_18_3130, u32:0x01_00_3120, u32:0x01_14_2030, u32:0x01_00_3032, +],[ + u32:0x00_02_0010, u32:0x00_02_0014, u32:0x01_03_0008, u32:0x03_03_0008, u32:0x0d_03_0008, u32:0x00_02_0018, u32:0x00_02_001c, u32:0x03_03_0010, + u32:0x05_03_0008, u32:0x0d_03_0010, u32:0x00_01_0000, u32:0x01_03_0010, u32:0x03_03_0018, u32:0x0d_03_0018, u32:0x00_01_0002, u32:0x00_01_0004, + u32:0x01_03_0018, u32:0x05_03_0010, u32:0x0d_02_0000, u32:0x00_01_0006, u32:0x01_02_0000, u32:0x03_02_0000, u32:0x05_03_0018, u32:0x00_01_0008, + u32:0x00_01_000a, u32:0x01_02_0004, u32:0x05_02_0000, u32:0x0d_02_0004, u32:0x00_01_000c, u32:0x00_01_000e, u32:0x03_02_0004, u32:0x05_02_0004, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0031, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_0600, u32:0x00_00_0f09, u32:0x00_00_0315, u32:0x00_00_0c07, u32:0x00_00_1712, u32:0x00_00_0805, u32:0x00_00_140e, u32:0x00_00_0702, + u32:0x02_10_110b, u32:0x02_00_0416, u32:0x03_14_0d08, u32:0x03_00_0113, u32:0x03_08_0a06, u32:0x02_00_1c10, u32:0x02_08_1a1b, u32:0x03_00_1819, + u32:0x03_08_0000, u32:0x03_00_0000, u32:0x01_18_0000, u32:0x03_00_0000, u32:0x03_1c_0031, u32:0x03_00_0000, u32:0x01_10_0000, u32:0x01_00_0000, + u32:0x03_08_0405, u32:0x03_00_0505, u32:0x02_10_0505, u32:0x01_00_0504, u32:0x02_00_0505, u32:0x02_00_0405, u32:0x03_10_0505, u32:0x01_00_0405, + u32:0x01_18_0505, u32:0x02_00_0505, u32:0x02_18_0504, u32:0x02_00_0505, u32:0x01_02_0504, u32:0x01_00_0505, u32:0x02_04_0505, u32:0x02_00_0505, + u32:0x00_18_0000, u32:0x00_00_0000, u32:0x00_10_0000, u32:0x00_00_0000, u32:0x00_00_0051, u32:0x00_00_0000, u32:0x00_06_0000, u32:0x00_00_0000, + u32:0x51_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_18_0000, u32:0x00_00_0000, u32:0x00_08_0000, u32:0x00_00_0000, + u32:0x10_0a_0000, u32:0x00_00_0000, u32:0x14_04_0000, u32:0x00_00_0000, u32:0x08_00_0000, u32:0x00_00_0000, u32:0x08_04_0000, u32:0x00_00_0010, + u32:0x08_0c_0000, u32:0x00_00_0000, u32:0x18_0e_0000, u32:0x00_00_0000, u32:0x1c_04_0010, u32:0x00_00_0000, u32:0x10_04_0000, u32:0x00_00_0000, + u32:0x08_00_0010, u32:0x00_00_0000, u32:0x10_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x10_00_0000, u32:0x00_00_0000, + u32:0x18_31_0000, u32:0x00_00_0000, u32:0x18_00_0000, u32:0x00_00_0000, u32:0x02_00_0051, u32:0x00_00_0000, u32:0x04_00_0000, u32:0x00_00_0000, + u32:0x18_00_0100, u32:0x00_06_0302, u32:0x10_09_0605, u32:0x00_0f_0a08, u32:0x00_15_100d, u32:0x00_03_1613, u32:0x06_07_1c19, u32:0x00_0c_211f, + u32:0x00_12_2523, u32:0x00_17_2927, u32:0x00_05_2d2b, u32:0x00_08_0201, u32:0x18_0e_0403, u32:0x00_14_0706, u32:0x08_02_0c09, u32:0x00_07_120f, + u32:0x0a_0b_1815, u32:0x00_11_1e1b, u32:0x04_16_2220, u32:0x00_04_2624, u32:0x00_08_2a28, u32:0x00_0d_012c, u32:0x04_13_0201, u32:0x00_01_0504, + u32:0x0c_06_0807, u32:0x00_0a_0e0b, u32:0x0e_10_1411, u32:0x00_1c_1a17, u32:0x04_1b_341d, u32:0x00_1a_3233, u32:0x04_19_3031, u32:0x00_18_2e2f, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0051, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_31_0406, u32:0x00_00_0505, u32:0x00_00_0505, u32:0x00_00_0605, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, u32:0x00_00_0606, + u32:0x00_05_0606, u32:0x06_04_0606, u32:0x09_05_0606, u32:0x0f_05_0404, u32:0x15_05_0505, u32:0x03_05_0505, u32:0x07_04_0606, u32:0x0c_05_0606, + u32:0x12_05_0606, u32:0x17_05_0606, u32:0x05_05_0606, u32:0x08_04_0606, u32:0x0e_05_0606, u32:0x14_05_0406, u32:0x02_05_0404, u32:0x07_04_0505, + u32:0x0b_05_0505, u32:0x11_05_0606, u32:0x16_05_0606, u32:0x04_05_0606, u32:0x08_04_0606, u32:0x0d_05_0606, u32:0x13_05_0606, u32:0x01_05_0606, + u32:0x06_04_0000, u32:0x0a_05_0000, u32:0x10_05_0000, u32:0x1c_05_0000, u32:0x1b_05_0091, u32:0x1a_05_0000, u32:0x19_05_0000, u32:0x18_05_0000, + u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0020, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x31_51_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, u32:0x00_00_0000, + u32:0x05_00_0000, u32:0x04_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x04_00_0010, u32:0x05_00_0000, + u32:0x05_00_0020, u32:0x05_00_0000, u32:0x05_00_0020, u32:0x04_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x04_00_0000, + u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x04_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, + u32:0x04_00_0000, u32:0x05_00_0000, u32:0x05_00_0000, u32:0x05_00_0020, u32:0x05_00_0030, u32:0x05_00_0010, u32:0x05_10_0020, u32:0x05_00_0020, +]]; + +const TEST_SYNC = BlockSyncData[2]:[ + BlockSyncData {id: u32:1234, last_block: false}, + BlockSyncData {id: u32:1235, last_block: true}, +]; + +const TEST_CTRL = FseDecoderCtrl[2]:[ + FseDecoderCtrl { + sync: TEST_SYNC[0], + sequences_count: u24:8, + literals_count: u20:0, + of_acc_log: u7:5, + ll_acc_log: u7:5, + ml_acc_log: u7:5, + }, + FseDecoderCtrl { + sync: TEST_SYNC[1], + sequences_count: u24:7, + literals_count: u20:0, + of_acc_log: u7:5, + ll_acc_log: u7:5, + ml_acc_log: u7:6, + }, +]; + + +const TEST_AXI_DATA_W = u32:64; +const TEST_REFILLING_SB_DATA_W = TEST_AXI_DATA_W; +const TEST_REFILLING_SB_LENGTH_W = refilling_shift_buffer::length_width(TEST_REFILLING_SB_DATA_W); +const TEST_RAM_DATA_W = u32:32; +const TEST_RAM_SIZE = common::FSE_MAX_SYMBOLS; +const TEST_RAM_ADDR_W = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE = TEST_RAM_DATA_W / u32:3; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_W); + +type TestRefillingSBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + +const TEST_DATA_0 = TestRefillingSBOutput[48]:[ + // init states + TestRefillingSBOutput { error: false, data: u64:0b11111, length: u7:5}, + TestRefillingSBOutput { error: false, data: u64:0b101, length: u7:5}, + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:5}, + // symbols (seq #0) + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b100, length: u7:3}, + // symbols (seq #1) + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b110, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:2}, + // symbols (seq #2) + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + // symbols (seq #3) + TestRefillingSBOutput { error: false, data: u64:0b11, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + // symbols (seq #4) + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b1, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:3}, + // symbols (seq #5) + TestRefillingSBOutput { error: false, data: u64:0b101, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b1, length: u7:1}, + // symbols (seq #6) + TestRefillingSBOutput { error: false, data: u64:0b11, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:2}, + // symbols (seq #7) + TestRefillingSBOutput { error: false, data: u64:0b1000, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // no state update for last sequence +]; + +const TEST_DATA_1 = TestRefillingSBOutput[42]:[ + // init states + TestRefillingSBOutput { error: false, data: u64:0b10000, length: u7:5}, + TestRefillingSBOutput { error: false, data: u64:0b1110, length: u7:5}, + TestRefillingSBOutput { error: false, data: u64:0b11001, length: u7:6}, + // symbols (seq #0) + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b110, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:5}, + TestRefillingSBOutput { error: false, data: u64:0b1110, length: u7:5}, + // symbols (seq #1) + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b1, length: u7:6}, + TestRefillingSBOutput { error: false, data: u64:0b101, length: u7:5}, + // symbols (seq #2) + TestRefillingSBOutput { error: false, data: u64:0b110, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b11, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b1, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b10011, length: u7:5}, + // symbols (seq #3) + TestRefillingSBOutput { error: false, data: u64:0b11, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:2}, + TestRefillingSBOutput { error: false, data: u64:0b1, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:5}, + // symbols (seq #4) + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:3}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b1010, length: u7:5}, + // symbols (seq #5) + TestRefillingSBOutput { error: false, data: u64:0b1110, length: u7:5}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // state update + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:1}, + TestRefillingSBOutput { error: false, data: u64:0b11, length: u7:6}, + TestRefillingSBOutput { error: false, data: u64:0b10011, length: u7:5}, + // symbols (seq #6) + TestRefillingSBOutput { error: false, data: u64:0b10, length: u7:4}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + TestRefillingSBOutput { error: false, data: u64:0b0, length: u7:0}, + // no state update for last sequence +]; +// FIXME: test error propagation with TestRefillingSBOutput { error: true, ...} + + +fn test_command(block_idx: u32, msg_type: SequenceExecutorMessageType, length: CopyOrMatchLength, content: CopyOrMatchContent, last: bool) -> CommandConstructorData { + CommandConstructorData { + sync: TEST_SYNC[block_idx], + data: SequenceExecutorPacket { + msg_type: msg_type, + length: length, + content: content, + last: last, + }, + } +} + +const TEST_EXPECTED_COMMANDS_0 = CommandConstructorData[16]:[ + // block #0 + // seq #0 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:1, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:1, false), + // seq #1 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:3, CopyOrMatchContent:6, false), + // seq #2 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:1, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:8, false), + // seq #3 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:11, false), + // seq #4 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:16, false), + // seq #5 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:13, false), + // seq #6 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:6, CopyOrMatchContent:7, false), + // seq #7 + test_command(u32:0, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:0, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:3, CopyOrMatchContent:24, true), +]; + +const TEST_EXPECTED_COMMANDS_1 = CommandConstructorData[14]:[ + // block #1 + // seq #0 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:1, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:7, CopyOrMatchContent:4, false), + // seq #1 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:3, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:3, CopyOrMatchContent:6, false), + // seq #2 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:14, false), + // seq #3 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:5, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:19, false), + // seq #4 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:13, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:4, CopyOrMatchContent:1, false), + // seq #5 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:3, CopyOrMatchContent:46, false), + // seq #6 + test_command(u32:1, SequenceExecutorMessageType::LITERAL, CopyOrMatchLength:0, CopyOrMatchContent:0, false), + test_command(u32:1, SequenceExecutorMessageType::SEQUENCE, CopyOrMatchLength:6, CopyOrMatchContent:18, true), +]; + +//#[test_proc] +//proc FseDecoderTest { +// type FseRamRdReq = ram::ReadReq; +// type FseRamRdResp = ram::ReadResp; +// +// type FseRamWrReq = ram::WriteReq; +// type FseRamWrResp = ram::WriteResp; +// +// type RefillingSBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; +// type RefillingSBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; +// +// terminator: chan out; +// +// ctrl_s: chan out; +// finish_r: chan in; +// +// rsb_ctrl_r: chan in; +// rsb_data_s: chan out; +// +// command_r: chan in; +// +// ll_fse_wr_req_s: chan out; +// ll_fse_wr_resp_r: chan in; +// +// ml_fse_wr_req_s: chan out; +// ml_fse_wr_resp_r: chan in; +// +// of_fse_wr_req_s: chan out; +// of_fse_wr_resp_r: chan in; +// +// config (terminator: chan out) { +// let (ctrl_s, ctrl_r) = chan("ctrl"); +// let (finish_s, finish_r) = chan("finish"); +// +// let (rsb_ctrl_s, rsb_ctrl_r) = chan("rsb_ctrl"); +// let (rsb_data_s, rsb_data_r) = chan("rsb_out_data"); +// +// let (command_s, command_r) = chan("command"); +// +// // RAM with FSE lookup for Literal Lengths +// let (ll_fse_rd_req_s, ll_fse_rd_req_r) = chan("ll_fse_rd_req"); +// let (ll_fse_rd_resp_s, ll_fse_rd_resp_r) = chan("ll_fse_rd_resp"); +// let (ll_fse_wr_req_s, ll_fse_wr_req_r) = chan("ll_fse_wr_req"); +// let (ll_fse_wr_resp_s, ll_fse_wr_resp_r) = chan("ll_fse_wr_resp"); +// +// spawn ram::RamModel< +// TEST_RAM_DATA_W, +// TEST_RAM_SIZE, +// TEST_RAM_WORD_PARTITION_SIZE, +// >(ll_fse_rd_req_r, ll_fse_rd_resp_s, ll_fse_wr_req_r, ll_fse_wr_resp_s); +// +// // RAM with FSE lookup for Match Lengths +// let (ml_fse_rd_req_s, ml_fse_rd_req_r) = chan("ml_fse_rd_req"); +// let (ml_fse_rd_resp_s, ml_fse_rd_resp_r) = chan("ml_fse_rd_resp"); +// let (ml_fse_wr_req_s, ml_fse_wr_req_r) = chan("ml_fse_wr_req"); +// let (ml_fse_wr_resp_s, ml_fse_wr_resp_r) = chan("ml_fse_wr_resp"); +// +// spawn ram::RamModel< +// TEST_RAM_DATA_W, +// TEST_RAM_SIZE, +// TEST_RAM_WORD_PARTITION_SIZE, +// >(ml_fse_rd_req_r, ml_fse_rd_resp_s, ml_fse_wr_req_r, ml_fse_wr_resp_s); +// +// // RAM with FSE lookup for Offsets +// let (of_fse_rd_req_s, of_fse_rd_req_r) = chan("of_fse_rd_req"); +// let (of_fse_rd_resp_s, of_fse_rd_resp_r) = chan("of_fse_rd_resp"); +// let (of_fse_wr_req_s, of_fse_wr_req_r) = chan("of_fse_wr_req"); +// let (of_fse_wr_resp_s, of_fse_wr_resp_r) = chan("of_fse_wr_resp"); +// +// spawn ram::RamModel< +// TEST_RAM_DATA_W, +// TEST_RAM_SIZE, +// TEST_RAM_WORD_PARTITION_SIZE, +// >(of_fse_rd_req_r, of_fse_rd_resp_s, of_fse_wr_req_r, of_fse_wr_resp_s); +// +// spawn FseDecoder< +// TEST_RAM_DATA_W, TEST_RAM_ADDR_W, TEST_RAM_NUM_PARTITIONS, +// TEST_AXI_DATA_W, +// >( +// ctrl_r, finish_s, +// rsb_ctrl_s, rsb_data_r, +// command_s, +// ll_fse_rd_req_s, ll_fse_rd_resp_r, +// ml_fse_rd_req_s, ml_fse_rd_resp_r, +// of_fse_rd_req_s, of_fse_rd_resp_r, +// ); +// +// ( +// terminator, +// ctrl_s, finish_r, +// rsb_ctrl_r, rsb_data_s, +// command_r, +// ll_fse_wr_req_s, ll_fse_wr_resp_r, +// ml_fse_wr_req_s, ml_fse_wr_resp_r, +// of_fse_wr_req_s, of_fse_wr_resp_r, +// ) +// } +// +// init { u32:0 } +// +// next (state: u32) { +// let tok = join(); +// +// // write OF table +// let tok = for ((i, of_record), tok): ((u32, u32), token) in enumerate(TEST_OF_TABLE[state]) { +// let tok = send(tok, of_fse_wr_req_s, FseRamWrReq { +// addr: i as u8, +// data: of_record, +// mask: u4:0xf, +// }); +// let (tok, _) = recv(tok, of_fse_wr_resp_r); +// tok +// }(tok); +// +// // write ML table +// let tok = for ((i, ml_record), tok): ((u32, u32), token) in enumerate(TEST_ML_TABLE[state]) { +// let tok = send(tok, ml_fse_wr_req_s, FseRamWrReq { +// addr: i as u8, +// data: ml_record, +// mask: u4:0xf, +// }); +// let (tok, _) = recv(tok, ml_fse_wr_resp_r); +// tok +// }(tok); +// +// // write LL table +// let tok = for ((i, ll_record), tok): ((u32, u32), token) in enumerate(TEST_LL_TABLE[state]) { +// let tok = send(tok, ll_fse_wr_req_s, FseRamWrReq { +// addr: i as u8, +// data: ll_record, +// mask: u4:0xf, +// }); +// let (tok, _) = recv(tok, ll_fse_wr_resp_r); +// tok +// }(tok); +// +// // send ctrl +// let tok = send(tok, ctrl_s, TEST_CTRL[state]); +// trace_fmt!("Sent ctrl {:#x}", TEST_CTRL[state]); +// +// match state { +// u32:0 => { +// // block #0 +// // send data +// let tok = for ((i, data), tok): ((u32, RefillingSBOutput), token) in enumerate(TEST_DATA_0) { +// let (tok, buf_ctrl) = recv(tok, rsb_ctrl_r); +// trace_fmt!("Received #{} buf ctrl {:#x}", i + u32:1, buf_ctrl); +// assert_eq(RefillingSBCtrl {length: data.length}, buf_ctrl); +// let tok = send(tok, rsb_data_s, data); +// trace_fmt!("Sent #{} buf data {:#x}", i + u32:1, data); +// tok +// }(tok); +// +// // recv commands +// let tok = for ((i, expected_cmd), tok): ((u32, CommandConstructorData), token) in enumerate(TEST_EXPECTED_COMMANDS_0) { +// let (tok, cmd) = recv(tok, command_r); +// trace_fmt!("Received #{} cmd {:#x}", i + u32:1, cmd); +// assert_eq(expected_cmd, cmd); +// tok +// }(tok); +// +// // recv finish +// let (tok, _) = recv(tok, finish_r); +// }, +// u32:1 => { +// // block #1 +// // send data +// let tok = for ((i, data), tok): ((u32, RefillingSBOutput), token) in enumerate(TEST_DATA_1) { +// let (tok, buf_ctrl) = recv(tok, rsb_ctrl_r); +// trace_fmt!("Received #{} buf ctrl {:#x}", i + u32:1, buf_ctrl); +// assert_eq(RefillingSBCtrl {length: data.length}, buf_ctrl); +// let tok = send(tok, rsb_data_s, data); +// trace_fmt!("Sent #{} buf data {:#x}", i + u32:1, data); +// tok +// }(tok); +// +// // recv commands +// let tok = for ((i, expected_cmd), tok): ((u32, CommandConstructorData), token) in enumerate(TEST_EXPECTED_COMMANDS_1) { +// let (tok, cmd) = recv(tok, command_r); +// trace_fmt!("Received #{} cmd {:#x}", i + u32:1, cmd); +// assert_eq(expected_cmd, cmd); +// tok +// }(tok); +// +// // recv finish +// let (tok, _) = recv(tok, finish_r); +// +// send(tok, terminator, true); +// }, +// }; +// +// state + u32:1 +// } +//} diff --git a/xls/modules/zstd/fse_lookup_dec.x b/xls/modules/zstd/fse_lookup_dec.x new file mode 100644 index 0000000000..5c2fa5ec80 --- /dev/null +++ b/xls/modules/zstd/fse_lookup_dec.x @@ -0,0 +1,1049 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.fse_table_creator; +import xls.modules.zstd.refilling_shift_buffer; +import xls.modules.zstd.fse_proba_freq_dec; +import xls.modules.shift_buffer.shift_buffer; + +type AccuracyLog = common::FseAccuracyLog; + +pub enum FseLookupDecoderStatus: u1 { + OK = 0, + ERROR = 1, +} + +pub struct FseLookupDecoderReq { + addr: uN[AXI_ADDR_W] +} + +pub struct FseLookupDecoderResp { + status: FseLookupDecoderStatus, + accuracy_log: common::FseAccuracyLog +} + +pub proc FseLookupDecoder< + AXI_DATA_W: u32, AXI_ADDR_W: u32, + DPD_RAM_DATA_W: u32, DPD_RAM_ADDR_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_DATA_W: u32, TMP_RAM_ADDR_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + FSE_RAM_DATA_W: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, +> { + type Req = FseLookupDecoderReq; + type Resp = FseLookupDecoderResp; + type Status = FseLookupDecoderStatus; + + type FseTableStart = fse_table_creator::FseStartMsg; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type RefillerStartReq = refilling_shift_buffer::RefillStart; + type RefillerError = refilling_shift_buffer::RefillError; + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type FsePFDecReq = fse_proba_freq_dec::FseProbaFreqDecoderReq; + type FsePFDecResp = fse_proba_freq_dec::FseProbaFreqDecoderResp; + type FsePFDecStatus = fse_proba_freq_dec::FseProbaFreqDecoderStatus; + + req_r: chan in; + resp_s: chan out; + + start_req_s: chan out; + stop_flush_req_s: chan<()> out; + flushing_done_r: chan<()> in; + + fse_pf_dec_req_s: chan out; + fse_pf_dec_resp_r: chan in; + fse_table_start_s: chan out; + fse_table_finish_r: chan<()> in; + + init {} + + config( + req_r: chan in, + resp_s: chan out, + + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, + + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + fse_rd_req_s: chan out, + fse_rd_resp_r: chan in, + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, + ) { + const CHANNEL_DEPTH = u32:1; + + let (fse_table_start_s, fse_table_start_r) = chan("fse_table_start"); + let (fse_table_finish_s, fse_table_finish_r) = chan<(), CHANNEL_DEPTH>("fse_table_finish"); + + spawn fse_table_creator::FseTableCreator< + DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, + TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, + >( + fse_table_start_r, fse_table_finish_s, + dpd_rd_req_s, dpd_rd_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + ); + + let (start_req_s, start_req_r) = chan("start_req"); + let (stop_flush_req_s, stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("stop_flush_req"); + let (buffer_ctrl_s, buffer_ctrl_r) = chan("buffer_ctrl"); + let (buffer_data_out_s, buffer_data_out_r) = chan("buffer_data_out"); + let (flushing_done_s, flushing_done_r) = chan<(), CHANNEL_DEPTH>("flushing_done"); + + spawn refilling_shift_buffer::RefillingShiftBuffer( + mem_rd_req_s, + mem_rd_resp_r, + start_req_r, + stop_flush_req_r, + buffer_ctrl_r, + buffer_data_out_s, + flushing_done_s, + ); + + let (fse_pf_dec_req_s, fse_pf_dec_req_r) = chan("fse_pf_dec_req"); + let (fse_pf_dec_resp_s, fse_pf_dec_resp_r) = chan("fse_pf_dec_resp"); + + spawn fse_proba_freq_dec::FseProbaFreqDecoder< + DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + >( + fse_pf_dec_req_r, fse_pf_dec_resp_s, + buffer_ctrl_s, buffer_data_out_r, + dpd_wr_req_s, dpd_wr_resp_r, + ); + + ( + req_r, resp_s, + start_req_s, + stop_flush_req_s, + flushing_done_r, + fse_pf_dec_req_s, fse_pf_dec_resp_r, + fse_table_start_s, fse_table_finish_r, + ) + } + + next(state: ()) { + let tok = join(); + let (tok, start_req) = recv(tok, req_r); + + // start refilling shift buffer + let tok_dec_pf1 = send(tok, start_req_s, RefillerStartReq { + start_addr: start_req.addr + }); + // start FSE probability frequency decoder + let tok_dec_pf2 = send(tok, fse_pf_dec_req_s, FsePFDecReq {}); + + // wait for completion from FSE probability frequency decoder + let tok = join(tok_dec_pf1, tok_dec_pf2); + let (tok_dec_resp, pf_dec_res) = recv(tok, fse_pf_dec_resp_r); + + // flush refilling shift buffer (regardless of any errors) + let tok_flush = send(tok_dec_resp, stop_flush_req_s, ()); + recv(tok_flush, flushing_done_r); + + let pf_dec_ok = pf_dec_res.status == FsePFDecStatus::OK; + // run FSE Table creation conditional or previous processing succeeding + let tok = send_if(tok_dec_resp, fse_table_start_s, pf_dec_ok, FseTableStart { + num_symbs: pf_dec_res.symbol_count, + accuracy_log: pf_dec_res.accuracy_log, + }); + // wait for completion from FSE table creator + let (tok, ()) = recv_if(tok, fse_table_finish_r, pf_dec_ok, ()); + + let resp = if pf_dec_ok { + Resp { status: Status::OK, accuracy_log: pf_dec_res.accuracy_log } + } else { + Resp { status: Status::ERROR, ..zero!() } + }; + send(tok, resp_s, resp); + } +} + + +const TEST_AXI_DATA_WIDTH = u32:64; +const TEST_AXI_ADDR_WIDTH = u32:32; +const TEST_AXI_ID_WIDTH = u32:8; +const TEST_AXI_DEST_WIDTH = u32:8; + +const TEST_CASE_RAM_DATA_WIDTH = u32:64; +const TEST_CASE_RAM_SIZE = u32:256; +const TEST_CASE_RAM_ADDR_WIDTH = std::clog2(TEST_CASE_RAM_SIZE); +const TEST_CASE_RAM_WORD_PARTITION_SIZE = TEST_CASE_RAM_DATA_WIDTH; +const TEST_CASE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_CASE_RAM_DATA_WIDTH); +const TEST_CASE_RAM_BASE_ADDR = u32:0; + +const TEST_DPD_RAM_DATA_WIDTH = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_WIDTH = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_WIDTH; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_WIDTH); + +const TEST_FSE_RAM_DATA_WIDTH = u32:32; +const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_ADDR_WIDTH = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH / u32:3; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_WIDTH); + +const TEST_TMP_RAM_DATA_WIDTH = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_WIDTH = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_WIDTH; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_WIDTH); + +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_INITIALIZED = true; + +type FseTableRecord = common::FseTableRecord; + +const FSE_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], FseLookupDecoderResp)[10] = [ + ( + u64[64]:[u64:0x72AAAAABBB1D25C0, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x1861862062081932, u64:0xC18628A106184184, u64:0x850720FACC49238, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x40 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + ), + ( + u64[64]:[u64:0x60C3082082085072, u64:0x1C06F8077D850F20, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x58 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + ), + ( + u64[64]:[u64:0x41081C158003A5D0, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x17 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x1101141108088A1, u64:0xA210842108421011, u64:0xAC90E792007A5B4, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x8 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:6 } + ), + ( + u64[64]:[u64:0x4AF830AC90E7920, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xa }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xe }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0xa }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0xF47FFEBBFF1D25C0, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0xA84DF134544CA40, u64:0xEEC609988403B0C, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x8 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x38100EEC60998840, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0xc }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x6B1CA24D0CE43810, u64:0x6651065104A4DFFD, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x24, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x24, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x8 }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), +]; + +#[test_proc] +proc FseLookupDecoderTest { + type Req = FseLookupDecoderReq; + type Resp = FseLookupDecoderResp; + type Status = FseLookupDecoderStatus; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type TestcaseRamRdReq = ram::ReadReq; + type TestcaseRamRdResp = ram::ReadResp; + type TestcaseRamWrReq = ram::WriteReq; + type TestcaseRamWrResp = ram::WriteResp; + + type AxiR = axi::AxiR; + type AxiAr = axi::AxiAr; + + terminator: chan out; + req_s: chan out; + resp_r: chan in; + fse_rd_req_s: chan out; + fse_rd_resp_r: chan in; + fse_wr_req_s: chan out; + fse_wr_resp_r: chan in; + testcase_wr_req_s: chan out; + testcase_wr_resp_r: chan in; + + config(terminator: chan out) { + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + + let (testcase_rd_req_s, testcase_rd_req_r) = chan("testcase_rd_req"); + let (testcase_rd_resp_s, testcase_rd_resp_r) = chan("testcase_rd_resp"); + let (testcase_wr_req_s, testcase_wr_req_r) = chan("testcase_wr_req"); + let (testcase_wr_resp_s, testcase_wr_resp_r) = chan("testcase_wr_resp"); + + spawn FseLookupDecoder< + TEST_AXI_DATA_WIDTH, TEST_AXI_ADDR_WIDTH, + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, + >( + req_r, + resp_s, + mem_rd_req_s, + mem_rd_resp_r, + dpd_rd_req_s, + dpd_rd_resp_r, + dpd_wr_req_s, + dpd_wr_resp_r, + tmp_rd_req_s, + tmp_rd_resp_r, + tmp_wr_req_s, + tmp_wr_resp_r, + fse_rd_req_s, + fse_rd_resp_r, + fse_wr_req_s, + fse_wr_resp_r, + ); + + spawn ram::RamModel< + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_SIZE, TEST_DPD_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_SIZE, TEST_FSE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(fse_rd_req_r, fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s); + + spawn ram::RamModel< + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + + spawn ram::RamModel< + TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(testcase_rd_req_r, testcase_rd_resp_s, testcase_wr_req_r, testcase_wr_resp_s); + + let (testcase_axi_r_s, testcase_axi_r_r) = chan("testcase_axi_r"); + let (testcase_axi_ar_s, testcase_axi_ar_r) = chan("testcase_axi_ar"); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_WIDTH, TEST_AXI_DATA_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH, + TEST_CASE_RAM_SIZE, TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_WIDTH, + TEST_CASE_RAM_ADDR_WIDTH, TEST_CASE_RAM_NUM_PARTITIONS, + >(testcase_axi_ar_r, testcase_axi_r_s, testcase_rd_req_s, testcase_rd_resp_r); + + spawn mem_reader::MemReader< + TEST_AXI_DATA_WIDTH, TEST_AXI_ADDR_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH + >(mem_rd_req_r, mem_rd_resp_s, testcase_axi_ar_s, testcase_axi_r_r); + + ( + terminator, req_s, resp_r, fse_rd_req_s, fse_rd_resp_r, + fse_wr_req_s, fse_wr_resp_r, testcase_wr_req_s, testcase_wr_resp_r, + ) + } + + init {} + + next(_: ()) { + let tok = join(); + // This has to be outside of unroll_for!, otherwise typechecker reports type mismatch on identical types + let req_start = Req { addr: uN[TEST_AXI_ADDR_WIDTH]:0x0 }; + + let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(FSE_LOOKUP_DECODER_TESTCASES)) { + let (input, output, resp_ok) = FSE_LOOKUP_DECODER_TESTCASES[test_i]; + + trace_fmt!("Loading testcase {:x}", test_i); + let tok = for ((i, input_data), tok): ((u32, u64), token) in enumerate(input) { + let req = TestcaseRamWrReq { + addr: i as uN[TEST_CASE_RAM_ADDR_WIDTH], + data: input_data as uN[TEST_CASE_RAM_DATA_WIDTH], + mask: uN[TEST_CASE_RAM_NUM_PARTITIONS]:0x1 + }; + let tok = send(tok, testcase_wr_req_s, req); + let (tok, _) = recv(tok, testcase_wr_resp_r); + tok + }(tok); + + trace_fmt!("Running FSE lookup decoder on testcase {:x}", test_i); + let tok = send(tok, req_s, req_start); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, resp_ok); + + let tok = for ((i, output_data), tok): ((u32, FseTableRecord), token) in enumerate(output) { + let req = FseRamRdReq { + addr: i as uN[TEST_FSE_RAM_ADDR_WIDTH], + mask: uN[TEST_FSE_RAM_NUM_PARTITIONS]:0x7, + }; + let tok = send(tok, fse_rd_req_s, req); + let (tok, resp) = recv(tok, fse_rd_resp_r); + assert_eq(fse_table_creator::bits_to_fse_record(resp.data), output_data); + + // erase output for next test to start with clean memory + let clear_req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_WIDTH], + mask: uN[TEST_FSE_RAM_NUM_PARTITIONS]:0x7, + data: uN[TEST_FSE_RAM_DATA_WIDTH]:0x0, + }; + let tok = send(tok, fse_wr_req_s, clear_req); + let (tok, _) = recv(tok, fse_wr_resp_r); + tok + }(tok); + tok + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/fse_proba_freq_dec.x b/xls/modules/zstd/fse_proba_freq_dec.x index 19150851c5..5daf857aef 100644 --- a/xls/modules/zstd/fse_proba_freq_dec.x +++ b/xls/modules/zstd/fse_proba_freq_dec.x @@ -19,7 +19,8 @@ import std; import xls.examples.ram; import xls.modules.zstd.common; -import xls.modules.zstd.shift_buffer; +import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.ram_wr_handler as ram_wr; pub const FSE_MAX_SYMBOLS = u32:256; @@ -43,13 +44,17 @@ const ACCURACY_LOG_WIDTH = common::FSE_ACCURACY_LOG_WIDTH; pub struct Remainder { value: u1, valid: bool } -enum FseProbaFreqDecoderStatus: u1 { +pub enum FseProbaFreqDecoderStatus: u1 { OK = 0, ERROR = 1, } pub struct FseProbaFreqDecoderReq {} -pub struct FseProbaFreqDecoderResp { status: FseProbaFreqDecoderStatus } +pub struct FseProbaFreqDecoderResp { + status: FseProbaFreqDecoderStatus, + accuracy_log: AccuracyLog, + symbol_count: SymbolCount, +} enum Fsm : u4 { IDLE = 0, @@ -60,7 +65,8 @@ enum Fsm : u4 { RECV_ZERO_PROBA = 5, WRITE_ZERO_PROBA = 6, WAIT_FOR_COMPLETION = 7, - INVALID = 8, + CONSUME_PADDING = 8, + INVALID = 9, } struct State { @@ -79,45 +85,62 @@ struct State { written_symbol_count: SymbolCount, // number of processed zero probability symbols zero_proba_count: SymbolCount, + // indicates error condition: either passed on from ShiftBuffer or due to + // using up more probability points than were available + data_invalid: bool, + // number of bits read from RefillingShiftBuffer modulo 8 + read_bits_mod8: u3 } // Adapter for input data, converting the data to a shift buffer input type pub proc FseInputBuffer { - type BufferInput = shift_buffer::ShiftBufferInput; + type BufferInput = shift_buffer::ShiftBufferPacket; type BufferCtrl = shift_buffer::ShiftBufferCtrl; type BufferOutput = shift_buffer::ShiftBufferOutput; + type RefillingBufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type Data = common::BlockData; type Length = bits[LENGTH_WIDTH]; in_data_r: chan in; buff_data_s: chan out; + out_s: chan out; + buff_data_out_r: chan in; config( data_r: chan in, ctrl_r: chan in, - out_s: chan out, + out_s: chan out, ) { - let (buff_data_s, buff_data_r) = chan("buff_in_data"); + const CHANNEL_DEPTH = u32:1; + + let (buff_data_s, buff_data_r) = chan("buff_in_data"); + let (buff_data_out_s, buff_data_out_r) = chan("buff_out_data"); spawn shift_buffer::ShiftBuffer( - buff_data_r, ctrl_r, out_s); + ctrl_r, buff_data_r, buff_data_out_s); - (data_r, buff_data_s) + (data_r, buff_data_s, out_s, buff_data_out_r) } init { } - next (state: ()) { + next(state: ()) { let tok0 = join(); - let (tok1, recv_data, recv_valid) = recv_non_blocking(tok0, in_data_r, zero!()); + let (tok1, recv_data, recv_valid) = recv_non_blocking(tok0, in_data_r, zero!()); let shift_buffer_data = BufferInput { data: recv_data.bytes as Data, length: recv_data.length as Length, - last: recv_data.last }; - send_if(tok1, buff_data_s, recv_valid, shift_buffer_data); + + let (tok2, recv_data_out, recv_data_out_valid) = recv_non_blocking(tok0, buff_data_out_r, zero!()); + let shift_buffer_data_out = RefillingBufferOutput { + data: recv_data_out.data, + length: recv_data_out.length, + error: false, + }; + send_if(tok2, out_s, recv_data_out_valid, shift_buffer_data_out); } } @@ -145,16 +168,14 @@ fn get_adjusted_value(data: u16, remainder: Remainder) -> u16 { // proc for filling probability frequencies table pub proc FseProbaFreqDecoder< RAM_DATA_WIDTH: u32, - RAM_SIZE: u32, - RAM_WORD_PARTITION_SIZE: u32, - RAM_ADDR_WIDTH: u32 = {std::clog2(RAM_SIZE)}, - RAM_NUM_PARTITIONS: u32 = {ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH)}, + RAM_ADDR_WIDTH: u32, + RAM_NUM_PARTITIONS: u32, DATA_WIDTH: u32 = {common::DATA_WIDTH}, - LENGTH_WIDTH: u32 = {common::BLOCK_PACKET_WIDTH} + LENGTH_WIDTH: u32 = {refilling_shift_buffer::length_width(DATA_WIDTH)}, > { type Length = bits[LENGTH_WIDTH]; - type BufferCtrl = shift_buffer::ShiftBufferCtrl; - type BufferOutput = shift_buffer::ShiftBufferOutput; + type BufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type BufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type RamWriteReq = ram::WriteReq; type RamWriteResp = ram::WriteResp; type RamReadReq = ram::ReadReq; @@ -174,8 +195,6 @@ pub proc FseProbaFreqDecoder< resp_in_s: chan out; resp_out_r: chan in; - rd_req_s: chan out; - rd_resp_r: chan in; wr_req_s: chan out; config( @@ -188,13 +207,13 @@ pub proc FseProbaFreqDecoder< buff_out_data_r: chan in, // created lookup - rd_req_s: chan out, - rd_resp_r: chan in, wr_req_s: chan out, wr_resp_r: chan in ) { - let (resp_in_s, resp_in_r) = chan("resp_in"); - let (resp_out_s, resp_out_r) = chan("resp_out"); + const CHANNEL_DEPTH = u32:1; + + let (resp_in_s, resp_in_r) = chan("resp_in"); + let (resp_out_s, resp_out_r) = chan("resp_out"); spawn ram_wr::RamWrRespHandler( resp_in_r, resp_out_s, wr_resp_r @@ -204,7 +223,7 @@ pub proc FseProbaFreqDecoder< req_r, resp_s, buff_in_ctrl_s, buff_out_data_r, resp_in_s, resp_out_r, - rd_req_s, rd_resp_r, wr_req_s, + wr_req_s, ) } @@ -213,8 +232,8 @@ pub proc FseProbaFreqDecoder< next(state: State) { let tok0 = join(); - type BufferCtrl = shift_buffer::ShiftBufferCtrl; - type BufferOutput = shift_buffer::ShiftBufferOutput; + type BufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type BufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type RamWriteReq = ram::WriteReq; type RamWriteResp = ram::WriteResp; @@ -223,15 +242,19 @@ pub proc FseProbaFreqDecoder< let do_recv_req = (state.fsm == Fsm::IDLE); + let tok0 = join(); let (tok1_0, _) = recv_if(tok0, req_r, do_recv_req, zero!()); let do_buff_data_recv = match (state.fsm) { Fsm::RECV_ACCURACY_LOG => true, Fsm::RECV_SYMBOL => true, Fsm::RECV_ZERO_PROBA => true, + Fsm::CONSUME_PADDING => state.read_bits_mod8 != u3:0, _ => false, }; let (tok1_1, out_data) = recv_if(tok0, buff_out_data_r, do_buff_data_recv, zero!()); + let data_invalid = state.data_invalid || out_data.error; + let read_bits_mod8 = state.read_bits_mod8 + out_data.length as u3; let (tok1_2, written_symbol_count, written_symb_count_valid) = recv_non_blocking(tok0, resp_out_r, state.written_symbol_count); @@ -268,6 +291,8 @@ pub proc FseProbaFreqDecoder< accuracy_log, remaining_proba, written_symbol_count, + data_invalid, + read_bits_mod8, ..state }, ) @@ -301,14 +326,16 @@ pub proc FseProbaFreqDecoder< let proba = value as s16 - s16:1; let proba_points = if proba < s16:0 { RemainingProba:1 } else { proba as RemainingProba }; - assert!(proba_points <= state.remaining_proba, "corrupted_data"); let remaining_proba = state.remaining_proba - proba_points; + let remaining_proba_invalid = proba_points > state.remaining_proba; let symbol_count = state.symbol_count + SymbolCount:1; let remainder_count = if remainder.valid { u16:1 } else { u16:0 }; - // received all the symbols - if remaining_proba == RemainingProba:0 { + let data_invalid = data_invalid || remaining_proba_invalid; + // received all the symbols or the data is invalid either due to corrupted data + // or error propagated from ShiftBuffer + if remaining_proba == RemainingProba:0 || data_invalid { ( (false, zero!()), (true, RamWriteReq { @@ -323,6 +350,8 @@ pub proc FseProbaFreqDecoder< symbol_count, remaining_proba, remainder, + data_invalid, + read_bits_mod8, ..state }, ) @@ -343,6 +372,7 @@ pub proc FseProbaFreqDecoder< symbol_count, remaining_proba, remainder, + read_bits_mod8, ..state }, ) @@ -363,6 +393,7 @@ pub proc FseProbaFreqDecoder< symbol_count, remaining_proba, remainder, + read_bits_mod8, ..state } ) @@ -393,13 +424,15 @@ pub proc FseProbaFreqDecoder< }; ( - (true, zero!()), + (false, zero!()), (false, zero!()), (false, zero!()), State { fsm: new_fsm, remainder: zero!(), written_symbol_count, + data_invalid, + read_bits_mod8, ..state }, ) @@ -416,6 +449,8 @@ pub proc FseProbaFreqDecoder< written_symbol_count, zero_proba_count, next_recv_zero, + data_invalid, + read_bits_mod8, ..state }, ) @@ -477,10 +512,17 @@ pub proc FseProbaFreqDecoder< Fsm::WAIT_FOR_COMPLETION => { if written_symbol_count == state.symbol_count { ( - (false, zero!()), + if state.read_bits_mod8 != u3:0 { + (true, BufferCtrl { length: Length:8 - state.read_bits_mod8 as Length }) + } else { + (false, zero!()) + }, (false, zero!()), - (true, Resp { status: Status::OK }), - zero!(), + (false, zero!()), + State { + fsm: Fsm::CONSUME_PADDING, + ..state + } ) } else { ( @@ -491,6 +533,20 @@ pub proc FseProbaFreqDecoder< ) } }, + Fsm::CONSUME_PADDING => { + ( + (false, zero!()), + (false, zero!()), + // sending this response is conditioned on receiving response from + // RefillingShiftBuffer if there was padding to be consumed + (true, Resp { + status: if state.data_invalid { Status::ERROR } else { Status::OK }, + accuracy_log: state.accuracy_log, + symbol_count: state.symbol_count, + }), + zero!() + ) + }, _ => { trace_fmt!("Invalid state"); fail!( @@ -514,10 +570,6 @@ pub proc FseProbaFreqDecoder< let (do_send_finish, finish_data) = resp_option; let tok2_3 = send_if(tok1, resp_s, do_send_finish, finish_data); - // unused channels - send_if(tok0, rd_req_s, false, zero!()); - recv_if(tok0, rd_resp_r, false, zero!()); - new_state } } @@ -528,29 +580,22 @@ const INST_RAM_DATA_WIDTH = get_bit_width(RemainingProba:1 << common::FSE_MAX_AC const INST_RAM_WORD_PARTITION_SIZE = INST_RAM_DATA_WIDTH; const INST_RAM_NUM_PARTITIONS = ram::num_partitions(INST_RAM_WORD_PARTITION_SIZE, INST_RAM_DATA_WIDTH); const INST_DATA_WIDTH = common::DATA_WIDTH; -const INST_LENGTH_WIDTH = common::BLOCK_PACKET_WIDTH; +const INST_LENGTH_WIDTH = refilling_shift_buffer::length_width(INST_DATA_WIDTH); proc FseProbaFreqDecoderInst { - rd_req_s: chan> out; - rd_resp_r: chan> in; - config( req_r: chan in, resp_s: chan out, - buff_in_ctrl_s: chan> out, - buff_out_data_r: chan> in, - rd_req_s: chan> out, - rd_resp_r: chan> in, + buff_in_ctrl_s: chan> out, + buff_out_data_r: chan> in, wr_req_s: chan> out, wr_resp_r: chan in) { - spawn FseProbaFreqDecoder( + spawn FseProbaFreqDecoder( req_r, resp_s, buff_in_ctrl_s, buff_out_data_r, - rd_req_s, rd_resp_r, wr_req_s, wr_resp_r + wr_req_s, wr_resp_r ); - - (rd_req_s, rd_resp_r) } init { } @@ -563,7 +608,7 @@ const TEST_RAM_ADDR_WIDTH = std::clog2(TEST_RAM_SIZE); const TEST_RAM_WORD_PARTITION_SIZE = TEST_RAM_DATA_WIDTH; const TEST_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_WIDTH); const TEST_DATA_WIDTH = common::DATA_WIDTH; -const TEST_LENGTH_WIDTH = common::BLOCK_PACKET_WIDTH; +const TEST_LENGTH_WIDTH = refilling_shift_buffer::length_width(TEST_DATA_WIDTH); #[test_proc] proc FseProbaFreqDecoderTest { @@ -571,8 +616,8 @@ proc FseProbaFreqDecoderTest { type ReadResp = ram::ReadResp; type WriteReq = ram::WriteReq; type WriteResp = ram::WriteResp; - type BufferCtrl = shift_buffer::ShiftBufferCtrl; - type BufferOutput = shift_buffer::ShiftBufferOutput; + type BufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type BufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type RamAddr = bits[TEST_RAM_ADDR_WIDTH]; type RamData = uN[TEST_RAM_DATA_WIDTH]; type RamDataSigned = sN[TEST_RAM_DATA_WIDTH]; @@ -587,6 +632,8 @@ proc FseProbaFreqDecoderTest { rd_resp_r: chan in; wr_req_s: chan out; wr_resp_r: chan in; + buff_in_ctrl_s: chan out; + buff_out_data_r: chan in; config(terminator: chan out) { // RAM channels @@ -607,22 +654,20 @@ proc FseProbaFreqDecoderTest { spawn FseInputBuffer( seq_data_r, buff_in_ctrl_r, buff_out_data_s); - spawn FseProbaFreqDecoder( + spawn FseProbaFreqDecoder( req_r, resp_s, buff_in_ctrl_s, buff_out_data_r, - rd_req_s, rd_resp_r, wr_req_s, wr_resp_r); + wr_req_s, wr_resp_r); spawn ram::RamModel( rd_req_r, rd_resp_s, wr_req_r, wr_resp_s); - (terminator, seq_data_s, req_s, resp_r, rd_req_s, rd_resp_r, wr_req_s, wr_resp_r) + (terminator, seq_data_s, req_s, resp_r, rd_req_s, rd_resp_r, wr_req_s, wr_resp_r, buff_in_ctrl_s, buff_out_data_r) } init { } next(state: ()) { - let tok = join(); - // * accuracy_log = 8 // * probability frequencies: // | value | probability | bits (real) | symbol number | @@ -651,13 +696,37 @@ proc FseProbaFreqDecoderTest { RamData:5 ]; + let tok = join(); + let tok = send(tok, seq_data_s, common::SequenceData { - bytes: u64:0b111_000_00_001_011_01_11_001_110111_01110101_01100001_0011, - length: u32:47, + // 1 bit of padding for 8-bit alignment + bytes: u64:0b0111_000_00_001_011_01_11_001_110111_01110101_01100001_0011, + length: u32:48, last: false }); let tok = send(tok, req_s, zero!()); - let (tok, _) = recv(tok, resp_r); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: FseProbaFreqDecoderStatus::OK, + accuracy_log: AccuracyLog:8, + symbol_count: SymbolCount:12, + }); + + // check that the proc consumed the padding by sending request + // and checking over 100 cycles that it won't be served + let tok = send(tok, buff_in_ctrl_s, BufferCtrl { length: u7:0x1 }); + let tok = for (_, tok): (u32, token) in range(u32:0, u32:100) { + let (tok, _, valid) = recv_non_blocking(tok, buff_out_data_r, zero!()); + assert_eq(valid, false); + tok + }(tok); + // add input data to permit processing the request + let tok = send(tok, seq_data_s, common::SequenceData { + bytes: u64:1, + length: u32:1, + last: false, + }); + let (tok, _) = recv(tok, buff_out_data_r); for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { let tok = send(tok, rd_req_s, ReadReq { @@ -688,7 +757,12 @@ proc FseProbaFreqDecoderTest { last: false }); let tok = send(tok, req_s, zero!()); - let (tok, _) = recv(tok, resp_r); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: FseProbaFreqDecoderStatus::OK, + accuracy_log: AccuracyLog:9, + symbol_count: SymbolCount:2, + }); for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { let tok = send(tok, rd_req_s, ReadReq { @@ -719,7 +793,12 @@ proc FseProbaFreqDecoderTest { last: false }); let tok = send(tok, req_s, zero!()); - let (tok, _) = recv(tok, resp_r); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: FseProbaFreqDecoderStatus::OK, + accuracy_log: AccuracyLog:9, + symbol_count: SymbolCount:2, + }); for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { let tok = send(tok, rd_req_s, ReadReq { @@ -732,6 +811,9 @@ proc FseProbaFreqDecoderTest { tok }((tok)); + // FIXME: test error path: error propagated from ShiftBuffer and assigning more + // probability points than available + let tok = send(tok, terminator, true); } } diff --git a/xls/modules/zstd/fse_table_creator.x b/xls/modules/zstd/fse_table_creator.x new file mode 100644 index 0000000000..3eca396d90 --- /dev/null +++ b/xls/modules/zstd/fse_table_creator.x @@ -0,0 +1,652 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// FseTableCreator generates a decoding table from a probability distribution. +// The algorithm for creating the decoding lookup is described in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-4.1.1. + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.ram_wr_handler as ram_wr; +import xls.modules.zstd.fse_table_iterator as fse_table_iterator; + +type SymbolCount = common::FseSymbolCount; +type AccuracyLog = common::FseAccuracyLog; + +enum Status : u4 { + RECEIVE_START = 0, + TEST_NEGATIVE_PROB = 1, + HANDLE_NEGATIVE_PROB = 2, + TEST_POSITIVE_PROB = 3, + HANDLE_POSITIVE_PROB = 4, + HANDLE_POSITIVE_PROB_WRITE_STATE_DESC = 5, + INNER_FOR_GET_POS = 6, + INNER_FOR_WRITE_SYM = 7, + LAST_FOR = 8, + GET_STATE_DESC = 9, + SET_STATE_DESC = 10, + SEND_FINISH = 11, + START_ITERATING_POS = 12, +} + +struct FseTableCreatorState { + status: Status, + req: bool, + idx: u8, + // TODO: num_symbs is u8, possibly other fields as well + num_symbs: u8, + curr_symbol: u8, + state_desc_for_symbol: u16, + accuracy_log: u16, + high_threshold: u16, + inner_for_idx: u16, + inner_for_range: u16, + dpd_data: u16, + pos: u16, +} + +type FseTableRecord = common::FseTableRecord; + +pub struct FseStartMsg { num_symbs: SymbolCount, accuracy_log: AccuracyLog } + +pub fn fse_record_to_bits(record: FseTableRecord) -> u32 { + record.base ++ record.num_of_bits ++ record.symbol +} + +#[test] +fn test_fse_record_to_bits() { + let bit = fse_record_to_bits( + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x05, base: u16:0x0020 } + ); + assert_eq(bit, u32:0x0020_05_17); +} + +pub fn bits_to_fse_record(bit: u32) -> FseTableRecord { + FseTableRecord { + symbol: bit[0:8], + num_of_bits: bit[8:16], + base: bit[16:32] + } +} + +#[test] +fn test_bits_to_fse_record() { + let record = bits_to_fse_record(u32:0x0020_05_17); + assert_eq(record, FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x05, base: u16:0x0020 }); +} + +pub proc FseTableCreator< + // Default Probability Distribution RAM parameters + DPD_RAM_DATA_WIDTH: u32, DPD_RAM_ADDR_WIDTH: u32, DPD_RAM_NUM_PARTITIONS: u32, + // FSE lookup table parameters + FSE_RAM_DATA_WIDTH: u32, FSE_RAM_ADDR_WIDTH: u32, FSE_RAM_NUM_PARTITIONS: u32, + // Temp RAM parameters + TMP_RAM_DATA_WIDTH: u32, TMP_RAM_ADDR_WIDTH: u32, TMP_RAM_NUM_PARTITIONS: u32, +> { + type State = FseTableCreatorState; + + type DpdRamReadReq = ram::ReadReq; + type DpdRamReadResp = ram::ReadResp; + + type FseRamWriteReq = ram::WriteReq; + type FseRamWriteResp = ram::WriteResp; + type FseRamReadReq = ram::ReadReq; + type FseRamReadResp = ram::ReadResp; + + type TmpRamWriteReq = ram::WriteReq; + type TmpRamWriteResp = ram::WriteResp; + type TmpRamReadReq = ram::ReadReq; + type TmpRamReadResp = ram::ReadResp; + + type IterCtrl = common::FseTableCreatorCtrl; + type IterIndex = common::FseTableIndex; + + dpd_rd_req_s: chan out; + dpd_rd_resp_r: chan in; + + // a request to start creating the FSE decoding table + fse_table_start_r: chan in; + // a response with information that the table has been saved to RAM + fse_table_finish_s: chan<()> out; + + fse_rd_req_s: chan out; + fse_rd_resp_r: chan in; + fse_wr_req_s: chan out; + fse_wr_resp_r: chan in; + + tmp_rd_req_s: chan out; + tmp_rd_resp_r: chan in; + tmp_wr_req_s: chan out; + tmp_wr_resp_r: chan in; + + it_ctrl_s: chan out; + it_index_r: chan in; + + config( + fse_table_start_r: chan in, + fse_table_finish_s: chan<()> out, + + // RAM with default probability distribution + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + + // Ram with FSE decoding table + fse_rd_req_s: chan out, + fse_rd_resp_r: chan in, + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in + ) { + let (it_ctrl_s, it_ctrl_r) = chan("it_ctrl"); + let (it_index_s, it_index_r) = chan("it_index"); + spawn fse_table_iterator::FseTableIterator(it_ctrl_r, it_index_s); + + ( + dpd_rd_req_s, dpd_rd_resp_r, + fse_table_start_r, fse_table_finish_s, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + it_ctrl_s, it_index_r + ) + } + + init { zero!() } + + next(state: State) { + const DPD_RAM_REQ_MASK_ALL = std::unsigned_max_value(); + const FSE_RAM_REQ_MASK_ALL = std::unsigned_max_value(); + const FSE_RAM_REQ_MASK_SYMBOL = uN[FSE_RAM_NUM_PARTITIONS]:1; + const TMP_RAM_REQ_MASK_ALL = std::unsigned_max_value(); + + // Type definitions repeated because of https://github.com/google/xls/issues/1368 + type DpdRamReadReq = ram::ReadReq; + type FseRamWriteReq = ram::WriteReq; + type FseRamWriteResp = ram::WriteResp; + type FseRamReadReq = ram::ReadReq; + type TmpRamWriteReq = ram::WriteReq; + type TestRamWriteResp = ram::WriteResp; + type TmpRamReadReq = ram::ReadReq; + + let tok0 = join(); + + let receive_start = (state.status == Status::RECEIVE_START); + let (tok1, fse_start_msg) = recv_if(tok0, fse_table_start_r, receive_start, zero!()); + + let get_dpd_data = state.status == Status::TEST_NEGATIVE_PROB || + state.status == Status::TEST_POSITIVE_PROB || + state.status == Status::HANDLE_POSITIVE_PROB; + + let send_dpd_req = get_dpd_data && state.req; + let tok_dpd_req = send_if(tok0, dpd_rd_req_s, send_dpd_req, + DpdRamReadReq { + addr: checked_cast(state.idx), + mask: DPD_RAM_REQ_MASK_ALL + }); + let get_dpd_resp = get_dpd_data && !state.req; + let (tok_dpd_resp, dpd_resp) = recv_if(tok0, dpd_rd_resp_r, get_dpd_resp, zero!()); + + let handle_negative_prob_req = state.status == Status::HANDLE_NEGATIVE_PROB; + let decreased_high_threshold = state.high_threshold - u16:1; + let index_as_symbol_record = FseTableRecord { + symbol: state.idx, + num_of_bits: u8:0, + base: u16:0 + }; + let fse_record_as_bits = fse_record_to_bits(index_as_symbol_record); + let fse_wr_req = if handle_negative_prob_req { + FseRamWriteReq { + addr: checked_cast(decreased_high_threshold), + data: checked_cast(fse_record_as_bits), + mask: FSE_RAM_REQ_MASK_SYMBOL + } + } else { + zero!() + }; + let tok3 = send_if(tok0, fse_wr_req_s, handle_negative_prob_req, fse_wr_req); + let handle_negative_prob_resp = (state.status == Status::HANDLE_NEGATIVE_PROB); + let (tok3, _) = recv_if(tok3, fse_wr_resp_r, handle_negative_prob_resp, FseRamWriteResp {}); + + let tok5 = send_if(tok0, tmp_wr_req_s, handle_negative_prob_req, + TmpRamWriteReq { + addr: checked_cast(state.idx), + data: checked_cast(u16:1), + mask: TMP_RAM_REQ_MASK_ALL + }); + let (tok5, _) = recv_if(tok5, tmp_wr_resp_r, handle_negative_prob_resp, TestRamWriteResp {}); + + let handle_positive_prob_write_state_desc = (state.status == Status::HANDLE_POSITIVE_PROB_WRITE_STATE_DESC); + let tok6 = send_if(tok0, tmp_wr_req_s, handle_positive_prob_write_state_desc, + TmpRamWriteReq { + addr: checked_cast(state.idx), + data: checked_cast(state.dpd_data), + mask: TMP_RAM_REQ_MASK_ALL + } + ); + let (tok6, _) = recv_if(tok6, tmp_wr_resp_r, handle_positive_prob_write_state_desc, TmpRamWriteResp {}); + + let inner_for_start_counting = state.status == Status::START_ITERATING_POS; + let negative_proba_count = (u16:1 << state.accuracy_log) - state.high_threshold; + let tok7 = send_if( tok0, it_ctrl_s, inner_for_start_counting, + IterCtrl { + accuracy_log: checked_cast(state.accuracy_log), + negative_proba_count: checked_cast(negative_proba_count), + } + ); + let inner_for_get_pos = (state.status == Status::INNER_FOR_GET_POS); + let (_, pos) = recv_if(tok0, it_index_r, inner_for_get_pos, zero!()); + + let inner_for_write_sym = state.status == Status::INNER_FOR_WRITE_SYM; + let tok4 = send_if( tok0, fse_wr_req_s, inner_for_write_sym, + FseRamWriteReq { + addr: checked_cast(state.pos), + data: checked_cast(fse_record_as_bits), + mask: FSE_RAM_REQ_MASK_SYMBOL + } + ); + + let (tok4, _) = recv_if(tok4, fse_wr_resp_r, inner_for_write_sym, FseRamWriteResp {}); + + let last_for = state.status == Status::LAST_FOR; + let tok8 = send_if(tok0, fse_rd_req_s, last_for, + FseRamReadReq { + addr: checked_cast(state.idx), + mask: FSE_RAM_REQ_MASK_SYMBOL + } + ); + let (tok8, fse_resp) = recv_if(tok8, fse_rd_resp_r, last_for, zero!()); + let fse_record = bits_to_fse_record(fse_resp.data); + + let get_state_desc = state.status == Status::GET_STATE_DESC; + let symbol = state.curr_symbol; + let tok8 = send_if(tok8, tmp_rd_req_s, get_state_desc, + TmpRamReadReq { + addr: checked_cast(symbol), + mask: TMP_RAM_REQ_MASK_ALL + } + ); + let (tok8, tmp_resp) = recv_if(tok8, tmp_rd_resp_r, get_state_desc, zero!()); + + let set_state_desc = state.status == Status::SET_STATE_DESC; + let tok9 = send_if(tok8, tmp_wr_req_s, set_state_desc, + TmpRamWriteReq { + addr: checked_cast(symbol), + data: checked_cast(state.state_desc_for_symbol + u16:1), + mask: TMP_RAM_REQ_MASK_ALL + } + ); + let (tok9, _) = recv_if(tok9, tmp_wr_resp_r, set_state_desc, TmpRamWriteResp {}); + + let num_bits = state.accuracy_log - common::highest_set_bit(state.state_desc_for_symbol); + let size = u16:1 << state.accuracy_log; + let new_state_base = (state.state_desc_for_symbol << num_bits) - size; + + let complete_record = FseTableRecord { + symbol: symbol, + num_of_bits: checked_cast(num_bits), + base: new_state_base + }; + let complete_record_as_bits = fse_record_to_bits(complete_record); + let tok10 = send_if(tok8, fse_wr_req_s, set_state_desc, + FseRamWriteReq { + addr: checked_cast(state.idx), + data: checked_cast(complete_record_as_bits), + mask: FSE_RAM_REQ_MASK_ALL + } + ); + let (tok10, _) = recv_if(tok10, fse_wr_resp_r, set_state_desc, FseRamWriteResp {}); + + let send_finish = state.status == Status::SEND_FINISH; + let tok11 = send_if(tok0, fse_table_finish_s, send_finish, ()); + + trace_fmt!("fse lookup state: {:#x}", state); + + if state.req && ( + state.status == Status::TEST_NEGATIVE_PROB || + state.status == Status::TEST_POSITIVE_PROB || + state.status == Status::HANDLE_POSITIVE_PROB) { + State { req: false, ..state } + } else { + match (state.status) { + Status::RECEIVE_START => { + State { + status: Status::TEST_NEGATIVE_PROB, + req: true, + num_symbs: checked_cast(fse_start_msg.num_symbs), + accuracy_log: checked_cast(fse_start_msg.accuracy_log), + high_threshold: u16:1 << fse_start_msg.accuracy_log, + ..state + } + }, + Status::TEST_NEGATIVE_PROB => { + if dpd_resp.data == s16:-1 as u16 { + State { status: Status::HANDLE_NEGATIVE_PROB, ..state } + } else { + let next_idx = state.idx + u8:1; + if next_idx < state.num_symbs { + State { status: Status::TEST_NEGATIVE_PROB, req: true, idx: next_idx, ..state } + } else { + State { status: Status::START_ITERATING_POS, req: true, idx: u8:0, ..state } + } + } + }, + Status::HANDLE_NEGATIVE_PROB => { + // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2143-L2146 + let next_idx = state.idx + u8:1; + if next_idx < state.num_symbs { + State { status: Status::TEST_NEGATIVE_PROB, req: true, idx: next_idx, high_threshold: decreased_high_threshold, ..state } + } else { + State { status: Status::START_ITERATING_POS, req: true, idx: u8:0, high_threshold: decreased_high_threshold, ..state } + } + }, + Status::START_ITERATING_POS => { + State { status: Status::TEST_POSITIVE_PROB, ..state } + }, + Status::TEST_POSITIVE_PROB => { + if dpd_resp.data as s16 > s16:0 { + State { status: Status::HANDLE_POSITIVE_PROB, req: true, ..state } + } else { + let next_idx = state.idx + u8:1; + if next_idx < state.num_symbs { + State { status: Status::TEST_POSITIVE_PROB, req: true, idx: next_idx, ..state } + } else { + State { status: Status::LAST_FOR, idx: u8:0, ..state } + } + } + }, + Status::HANDLE_POSITIVE_PROB => { + // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2161 + State { status: Status::HANDLE_POSITIVE_PROB_WRITE_STATE_DESC, dpd_data: dpd_resp.data, ..state } + }, + Status::HANDLE_POSITIVE_PROB_WRITE_STATE_DESC => { + State { status: Status::INNER_FOR_GET_POS, inner_for_idx: u16:0, inner_for_range: checked_cast(state.dpd_data), ..state } + }, + Status::INNER_FOR_GET_POS => { + // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2165 + State { status: Status::INNER_FOR_WRITE_SYM, pos: checked_cast(pos), ..state } + }, + Status::INNER_FOR_WRITE_SYM => { + let next_idx = state.inner_for_idx + u16:1; + if next_idx < state.inner_for_range { + State { status: Status::INNER_FOR_GET_POS, inner_for_idx: next_idx, ..state } + } else { + assert!(pos == IterIndex:0, "corruption_detected_while_decompressing"); + let next_idx = state.idx + u8:1; + if next_idx < state.num_symbs { + State { status: Status::TEST_POSITIVE_PROB, req: true, idx: next_idx, ..state } + } else { + State { status: Status::LAST_FOR, idx: u8:0, ..state } + } + } + }, + Status::LAST_FOR => { + // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2183 + State { status: Status::GET_STATE_DESC, curr_symbol: fse_record.symbol, ..state } + }, + Status::GET_STATE_DESC => { + // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2184 + State { status: Status::SET_STATE_DESC, state_desc_for_symbol: tmp_resp.data, ..state } + }, + Status::SET_STATE_DESC => { + let next_idx = state.idx + u8:1; + if next_idx as u16 < size { + State { status: Status::LAST_FOR, idx: next_idx, ..state } + } else { + State { status: Status::SEND_FINISH, ..state } + } + }, + Status::SEND_FINISH => { State { status: Status::RECEIVE_START, ..zero!() } }, + _ => fail!("impossible_case", zero!()), + } + } + } +} + +const TEST_DPD_RAM_DATA_WIDTH = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_WIDTH = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_WIDTH; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_WIDTH); + +const TEST_FSE_RAM_DATA_WIDTH = u32:32; +const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_ADDR_WIDTH = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH / u32:3; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_WIDTH); + +const TEST_TMP_RAM_DATA_WIDTH = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_WIDTH = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_WIDTH; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_WIDTH); + +proc FseTableCreatorInst { + type DpdRamReadReq = ram::ReadReq; + type DpdRamReadResp = ram::ReadResp; + + type FseRamReadReq = ram::ReadReq; + type FseRamReadResp = ram::ReadResp; + type FseRamWriteReq = ram::WriteReq; + type FseRamWriteResp = ram::WriteResp; + + type TmpRamWriteReq = ram::WriteReq; + type TmpRamWriteResp = ram::WriteResp; + type TmpRamReadReq = ram::ReadReq; + type TmpRamReadResp = ram::ReadResp; + + config( + fse_table_start_r: chan in, + fse_table_finish_s: chan<()> out, + + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + + fse_rd_req_s: chan out, + fse_rd_resp_r: chan in, + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in + ) { + spawn FseTableCreator< + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + >( + fse_table_start_r, fse_table_finish_s, + dpd_rd_req_s, dpd_rd_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r + ); + } + + init { } + + next(state: ()) { } +} + +const TEST_OFFSET_CODE_TABLE = FseTableRecord[32]:[ + FseTableRecord { symbol: u8:0, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:6, num_of_bits: u8:4, base: u16:0 }, + FseTableRecord { symbol: u8:9, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:15, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:21, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:3, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:7, num_of_bits: u8:4, base: u16:0 }, + FseTableRecord { symbol: u8:12, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:18, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:23, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:5, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:8, num_of_bits: u8:4, base: u16:0 }, + FseTableRecord { symbol: u8:14, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:20, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:2, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:7, num_of_bits: u8:4, base: u16:16 }, + FseTableRecord { symbol: u8:11, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:17, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:22, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:4, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:8, num_of_bits: u8:4, base: u16:16 }, + FseTableRecord { symbol: u8:13, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:19, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:1, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:6, num_of_bits: u8:4, base: u16:16 }, + FseTableRecord { symbol: u8:10, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:16, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:28, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:27, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:26, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:25, num_of_bits: u8:5, base: u16:0 }, + FseTableRecord { symbol: u8:24, num_of_bits: u8:5, base: u16:0 }, +]; + +#[test_proc] +proc FseTableCreatorTest { + type DpdRamReadReq = ram::ReadReq; + type DpdRamReadResp = ram::ReadResp; + type DpdRamWriteReq = ram::WriteReq; + type DpdRamWriteResp = ram::WriteResp; + + type FseRamReadReq = ram::ReadReq; + type FseRamReadResp = ram::ReadResp; + type FseRamWriteReq = ram::WriteReq; + type FseRamWriteResp = ram::WriteResp; + + type TmpRamReadReq = ram::ReadReq; + type TmpRamReadResp = ram::ReadResp; + type TmpRamWriteReq = ram::WriteReq; + type TmpRamWriteResp = ram::WriteResp; + + terminator: chan out; + fse_table_start_s: chan out; + fse_table_finish_r: chan<()> in; + + dpd_wr_req_s: chan out; + dpd_wr_resp_r: chan in; + + fse_rd_req_s: chan out; + fse_rd_resp_r: chan in; + + config(terminator: chan out) { + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + + spawn ram::RamModel< + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_SIZE, TEST_DPD_RAM_WORD_PARTITION_SIZE>( + dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s); + + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_SIZE, TEST_FSE_RAM_WORD_PARTITION_SIZE>( + fse_rd_req_r, fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s); + + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + + spawn ram::RamModel< + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE>( + tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + + let (fse_table_start_s, fse_table_start_r) = chan("fse_table_start"); + let (fse_table_finish_s, fse_table_finish_r) = chan<()>("fse_table_finish"); + + spawn FseTableCreator< + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + >( + fse_table_start_r, fse_table_finish_s, + dpd_rd_req_s, dpd_rd_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r + ); + + ( + terminator, + fse_table_start_s, fse_table_finish_r, + dpd_wr_req_s, dpd_wr_resp_r, + fse_rd_req_s, fse_rd_resp_r, + ) + } + + init { } + + next(state: ()) { + const DPD_RAM_REQ_MASK_ALL = std::unsigned_max_value(); + const FSE_RAM_REQ_MASK_ALL = std::unsigned_max_value(); + + let tok = join(); + + let dist_arr_length = array_size(common::FSE_OFFSET_DEFAULT_DIST); + let accuracy_log = AccuracyLog:5; + // 1. Fill the DPD Ram with default probability distribution + let tok = for (idx, tok): (u32, token) in range(u32:0, dist_arr_length) { + let tok = send( + tok, dpd_wr_req_s, + DpdRamWriteReq { + addr: checked_cast(idx), + data: checked_cast( + std::to_unsigned(common::FSE_OFFSET_DEFAULT_DIST[idx]) + ), + mask: DPD_RAM_REQ_MASK_ALL + }); + let (tok, _) = recv(tok, dpd_wr_resp_r); + (tok) + }(tok); + // 2. send start request over the fse_table_start_s channel + let tok = send(tok, fse_table_start_s, FseStartMsg { + num_symbs: checked_cast(dist_arr_length), + accuracy_log + }); + // 3. wait for finish response on fse_table_finish_r channel + let (tok, _) = recv(tok, fse_table_finish_r); + // 4. Read FSE Ram and verify values + // (https://datatracker.ietf.org/doc/html/rfc8878#section-appendix.a) + let code_length = u16:1 << accuracy_log; + let tok = for (idx, tok): (u16, token) in range(u16:0, code_length) { + let tok = send(tok, fse_rd_req_s, + FseRamReadReq { + addr: checked_cast(idx), + mask: FSE_RAM_REQ_MASK_ALL + } + ); + let (tok, resp) = recv(tok, fse_rd_resp_r); + let fse_record = bits_to_fse_record(resp.data); + assert_eq(fse_record.symbol, TEST_OFFSET_CODE_TABLE[idx].symbol); + assert_eq(fse_record.num_of_bits, TEST_OFFSET_CODE_TABLE[idx].num_of_bits); + assert_eq(fse_record.base, TEST_OFFSET_CODE_TABLE[idx].base); + (tok) + }(tok); + + let tok = send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/fse_table_iterator.x b/xls/modules/zstd/fse_table_iterator.x new file mode 100644 index 0000000000..f652d793ef --- /dev/null +++ b/xls/modules/zstd/fse_table_iterator.x @@ -0,0 +1,124 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This proc provides the order in which the FSE decoding table should be +// filled with symbols. The algorithm is described in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-4.1.1 + +import std; +import xls.modules.zstd.common; + +type Reset = bool; +type Index = common::FseTableIndex; +type Ctrl = common::FseTableCreatorCtrl; + +type AccuracyLog = common::FseAccuracyLog; +type SymbolCount = common::FseSymbolCount; + +enum Status : u1 { + CONFIGURE = 0, + SEND = 1, +} + +struct State { status: Status, ctrl: Ctrl, cnt: u16, pos: u16 } + +pub proc FseTableIterator { + ctrl_r: chan in; + idx_s: chan out; + + config( + ctrl_r: chan in, + idx_s: chan out + ) { (ctrl_r, idx_s) } + + init { zero!() } + + next(state: State) { + const ZERO_STATE = zero!(); + const ZERO_IDX_OPTION = (false, u16:0); + + let tok0 = join(); + + let do_recv_ctrl = state.status == Status::CONFIGURE; + let (tok1, ctrl) = recv_if(tok0, ctrl_r, do_recv_ctrl, zero!()); + + let ((do_send_idx, idx), new_state) = match (state.status) { + Status::CONFIGURE => { + ((true, u16:0), State { ctrl, status: Status::SEND, ..ZERO_STATE }) + }, + Status::SEND => { + let size = u16:1 << state.ctrl.accuracy_log; + let high_threshold = size - state.ctrl.negative_proba_count as u16; + let step = (size >> 1) + (size >> 3) + u16:3; + let mask = size - u16:1; + + let pos = (state.pos + step) & mask; + + let valid = pos < high_threshold; + let next_cnt = state.cnt + u16:1; + let last = (valid && (next_cnt == high_threshold - u16:1)); + + if last { + ((true, pos), ZERO_STATE) + } else if valid { + ((true, pos), State { cnt: next_cnt, pos, ..state }) + } else { + (ZERO_IDX_OPTION, State { cnt: state.cnt, pos, ..state }) + } + }, + _ => fail!("incorrect_state", (ZERO_IDX_OPTION, ZERO_STATE)), + }; + + let tok2 = send_if(tok1, idx_s, do_send_idx, checked_cast(idx)); + if do_send_idx { trace_fmt!("[IO]: Send index: {}", idx); } else { }; + + new_state + } +} + +const TEST_EXPECTRED_IDX = Index[27]:[ + Index:0, Index:23, Index:14, Index:5, Index:19, Index:10, Index:1, Index:24, Index:15, Index:6, + Index:20, Index:11, Index:2, Index:25, Index:16, Index:7, Index:21, Index:12, Index:3, Index:26, + Index:17, Index:8, Index:22, Index:13, Index:4, Index:18, Index:9, +]; + +#[test_proc] +proc FseTableIteratorTest { + terminator: chan out; + ctrl_s: chan out; + idx_r: chan in; + + config(terminator: chan out) { + let (ctrl_s, ctrl_r) = chan("ctrl"); + let (idx_s, idx_r) = chan("idx"); + + spawn FseTableIterator(ctrl_r, idx_s); + (terminator, ctrl_s, idx_r) + } + + init { } + + next(state: ()) { + let tok = join(); + let tok = send( + tok, ctrl_s, Ctrl { accuracy_log: AccuracyLog:5, negative_proba_count: SymbolCount:5 }); + let tok = for (exp_idx, tok): (Index, token) in TEST_EXPECTRED_IDX { + let (tok, idx) = recv(tok, idx_r); + assert_eq(idx, exp_idx); + (tok) + }(tok); + + send(tok, terminator, true); + } +} From b6b971b9558f38a8158f927ad886e6e2c7a8a313 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Wed, 24 Apr 2024 09:55:46 +0200 Subject: [PATCH 38/85] modules/zstd: Add CommandConstructor proc Internal-tag: [#58422] Signed-off-by: Ryszard Rozak --- xls/modules/zstd/BUILD | 75 ++++++ xls/modules/zstd/command_constructor.x | 339 +++++++++++++++++++++++++ 2 files changed, 414 insertions(+) create mode 100644 xls/modules/zstd/command_constructor.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 3360a55e03..55ae6ffdf7 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1472,6 +1472,80 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "command_constructor_dslx", + srcs = ["command_constructor.x"], + deps = [ + ":common_dslx", + ], +) + +xls_dslx_test( + name = "command_constructor_dslx_test", + dslx_test_args = {"compare": "none"}, + library = ":command_constructor_dslx", +) + +xls_dslx_verilog( + name = "command_constructor_verilog", + codegen_args = { + "module_name": "CommandConstructor", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "CommandConstructor", + library = ":command_constructor_dslx", + verilog_file = "command_constructor.v", +) + +xls_benchmark_ir( + name = "command_constructor_opt_ir_benchmark", + src = ":command_constructor_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "8", + "delay_model": "asap7", + }, +) + +xls_benchmark_verilog( + name = "command_constructor_verilog_benchmark", + verilog_target = "command_constructor_verilog", +) + +verilog_library( + name = "command_constructor_lib", + srcs = [ + ":command_constructor.v", + ], +) + +synthesize_rtl( + name = "command_constructor_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "CommandConstructor", + deps = [ + ":command_constructor_lib", + ], +) + +benchmark_synth( + name = "command_constructor_benchmark_synth", + synth_target = ":command_constructor_asap7", +) + +place_and_route( + name = "command_constructor_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.3", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":command_constructor_asap7", + target_die_utilization_percentage = "10", +) + xls_dslx_library( name = "fse_dec_dslx", srcs = [ @@ -1559,3 +1633,4 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + diff --git a/xls/modules/zstd/command_constructor.x b/xls/modules/zstd/command_constructor.x new file mode 100644 index 0000000000..9fd3f9eb9d --- /dev/null +++ b/xls/modules/zstd/command_constructor.x @@ -0,0 +1,339 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains implementation of CommandConstructor, which adjusts +// the data obtained from the SequenceDecoder for the SequenceExecutor block. +// It can receive two types of values: sequences that are copied directly +// to the output, and length-only literals packets, which before sending +// them to the output, should be redirected to the LiteralsBuffer to be filled +// with actual data. + +import std; +import xls.modules.zstd.common; + +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; +type CopyOrMatchContent = common::CopyOrMatchContent; +type CopyOrMatchLength = common::CopyOrMatchLength; + +type SequenceExecutorPacket = common::SequenceExecutorPacket; +type LiteralsBufferCtrl = common::LiteralsBufferCtrl; +type CommandConstructorData = common::CommandConstructorData; +type ExtendedBlockDataPacket = common::ExtendedBlockDataPacket; +type BlockSyncData = common::BlockSyncData; +type BlockDataPacket = common::BlockDataPacket; + +enum Status : u1 { + RECV_COMMAND = 0, + RECV_LITERALS = 1, +} + +struct State { + status: Status, + received_literals: CopyOrMatchLength, + literals_to_receive: CopyOrMatchLength, + sync: BlockSyncData, +} + +pub proc CommandConstructor { + sequence_decoder_r: chan in; + command_aggregator_s: chan out; + literals_buffer_resp_r: chan in; + literals_buffer_req_s: chan out; + + config(sequence_decoder_r: chan in, + command_aggregator_s: chan out, + literals_buffer_resp_r: chan in, + literals_buffer_req_s: chan out) { + (sequence_decoder_r, command_aggregator_s, literals_buffer_resp_r, literals_buffer_req_s) + } + + init { zero!() } + + next(state: State) { + let tok0 = join(); + + let recv_command = state.status == Status::RECV_COMMAND; + let (tok1_0, command) = + recv_if(tok0, sequence_decoder_r, recv_command, zero!()); + + let recv_literals = state.status == Status::RECV_LITERALS; + let (tok1_1, literals) = + recv_if(tok0, literals_buffer_resp_r, recv_literals, zero!()); + + let tok1 = join(tok1_0, tok1_1); + + let (new_state, do_send_command, do_send_literals_req) = match (state.status) { + Status::RECV_COMMAND => { + if command.data.msg_type == SequenceExecutorMessageType::LITERAL { + ( + State { + status: Status::RECV_LITERALS, + received_literals: CopyOrMatchLength:0, + literals_to_receive: command.data.length, + sync: command.sync, + }, false, true, + ) + } else { + (zero!(), true, false) + } + }, + Status::RECV_LITERALS => { + let received_literals = state.received_literals + literals.length; + if received_literals < state.literals_to_receive { + (State { received_literals, ..state }, true, false) + } else { + assert!( + received_literals >= state.literals_to_receive, + "Too many literals received"); + (zero!(), true, false) + } + }, + _ => fail!("impossible_case", (zero!(), false, false)), + }; + + let req = LiteralsBufferCtrl { length: command.data.length as u32, last: command.data.last}; // FIXME: remove cast after unifying types of 'length' fields + send_if(tok1, literals_buffer_req_s, do_send_literals_req, req); + + let resp = match(state.status) { + // sent only if the original message was of type SEQUENCE + Status::RECV_COMMAND => ExtendedBlockDataPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { + last: command.data.last, + last_block: command.sync.last_block, + id: command.sync.id, + data: command.data.content, + length: command.data.length as u32, // FIXME: remove cast after unifying types of 'length' fields + } + }, + Status::RECV_LITERALS => ExtendedBlockDataPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { + last: literals.last, + last_block: state.sync.last_block, + id: state.sync.id, + data: literals.content, + length: literals.length as u32, // FIXME: remove cast after unifying types of 'length' fields + } + }, + _ => fail!("resp_match_unreachable", zero!()) + }; + send_if(tok1, command_aggregator_s, do_send_command, resp); + + new_state + } +} + +// Tests + +enum FakeLiteralsBufferStatus : u1 { + RECV = 0, + SEND = 1, +} + +struct FakeLiteralsBufferState { + status: FakeLiteralsBufferStatus, + literals_left_to_send: CopyOrMatchLength, +} + +pub fn get_dummy_content(length: CopyOrMatchLength) -> CopyOrMatchContent { + let value = std::unsigned_max_value() >> (CopyOrMatchLength:64 - length); + value as CopyOrMatchContent +} + +proc FakeLiteralsBuffer { + literals_buffer_resp_s: chan out; + literals_buffer_req_r: chan in; + + config(literals_buffer_resp_s: chan out, + literals_buffer_req_r: chan in) { + (literals_buffer_resp_s, literals_buffer_req_r) + } + + init { zero!() } + + next(state: FakeLiteralsBufferState) { + let tok = join(); + let do_recv_req = state.status == FakeLiteralsBufferStatus::RECV; + let (tok, resp) = + recv_if(tok, literals_buffer_req_r, do_recv_req, zero!()); + + let (new_state, do_send, resp) = match (state.status) { + FakeLiteralsBufferStatus::RECV => { + ( + FakeLiteralsBufferState { + status: FakeLiteralsBufferStatus::SEND, + literals_left_to_send: resp.length as u64 // FIXME: remove cast after unifying types of 'length' fields + }, false, zero!(), + ) + }, + FakeLiteralsBufferStatus::SEND => { + let length = std::umin(state.literals_left_to_send, CopyOrMatchLength:64); + let next_left_to_send = state.literals_left_to_send - length; + let last = next_left_to_send == CopyOrMatchLength:0; + let resp = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + content: get_dummy_content(length), + length, + last + }; + + if last { + ( + FakeLiteralsBufferState { + status: FakeLiteralsBufferStatus::RECV, + literals_left_to_send: CopyOrMatchLength:0 + }, true, resp, + ) + } else { + ( + FakeLiteralsBufferState { + status: FakeLiteralsBufferStatus::SEND, + literals_left_to_send: next_left_to_send + }, true, resp, + ) + } + }, + _ => { + fail!( + "impossible_case", + (zero!(), false, zero!())) + }, + }; + + send_if(tok, literals_buffer_resp_s, do_send, resp); + new_state + } +} + +fn cmd_constr_to_ext_block(data: CommandConstructorData) -> ExtendedBlockDataPacket { + ExtendedBlockDataPacket { + msg_type: data.data.msg_type, + packet: BlockDataPacket { + last: data.data.last, + last_block: data.sync.last_block, + id: data.sync.id, + data: data.data.content, + length: data.data.length as u32, + } + } +} + +#[test_proc] +proc CommandConstructorTest { + terminator: chan out; + sequence_decoder_s: chan out; + command_aggregator_r: chan in; + + config(terminator: chan out) { + let (sequence_decoder_s, sequence_decoder_r) = chan("sequence_decoder"); + let (command_aggregator_s, command_aggregator_r) = chan("command_aggregator"); + + let (literals_buffer_resp_s, literals_buffer_resp_r) = chan("literals_buffer_resp"); + let (literals_buffer_req_s, literals_buffer_req_r) = chan("literals_buffer_req"); + + spawn CommandConstructor( + sequence_decoder_r, command_aggregator_s, literals_buffer_resp_r, literals_buffer_req_s); + + spawn FakeLiteralsBuffer(literals_buffer_resp_s, literals_buffer_req_r); + + (terminator, sequence_decoder_s, command_aggregator_r) + } + + init { } + + next(state: ()) { + const EMPTY_PACKET = zero!(); + + let tok = join(); + + let sequence_packet1 = CommandConstructorData { + data: SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + content: CopyOrMatchContent:11, + length: CopyOrMatchLength:4, + last: true, + }, + sync: BlockSyncData { + id: u32:1234, + last_block: false, + }, + }; + let tok = send(tok, sequence_decoder_s, sequence_packet1); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(cmd_constr_to_ext_block(sequence_packet1), resp); + + let literals_packet1 = CommandConstructorData { + data: SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:4, + ..EMPTY_PACKET + }, + sync: BlockSyncData { + id: u32:1234, + last_block: false, + }, + }; + let tok = send(tok, sequence_decoder_s, literals_packet1); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(get_dummy_content(CopyOrMatchLength:4), resp.packet.data); + + let literals_packet2 = CommandConstructorData { + data: SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:65, + ..EMPTY_PACKET + }, + sync: BlockSyncData { + id: u32:1234, + last_block: false, + }, + }; + let tok = send(tok, sequence_decoder_s, literals_packet2); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(get_dummy_content(CopyOrMatchLength:64), resp.packet.data); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(get_dummy_content(CopyOrMatchLength:1), resp.packet.data); + + let literals_packet3 = CommandConstructorData { + data: SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:64, + ..EMPTY_PACKET + }, + sync: BlockSyncData { + id: u32:1234, + last_block: false, + }, + }; + let tok = send(tok, sequence_decoder_s, literals_packet3); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(get_dummy_content(CopyOrMatchLength:64), resp.packet.data); + + let literals_packet4 = CommandConstructorData { + data: SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:128, + ..EMPTY_PACKET + }, + sync: BlockSyncData { + id: u32:1234, + last_block: false, + }, + }; + let tok = send(tok, sequence_decoder_s, literals_packet4); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(get_dummy_content(CopyOrMatchLength:64), resp.packet.data); + let (tok, resp) = recv(tok, command_aggregator_r); + assert_eq(get_dummy_content(CopyOrMatchLength:64), resp.packet.data); + + let tok = send(tok, terminator, true); + } +} From 824c2cee591ce9d44c8175dca5c6193afc98844f Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 25 Apr 2024 12:48:06 +0200 Subject: [PATCH 39/85] modules/zstd: Add Ram demux Internal-tag: [#58557] Co-authored-by: Ryszard Rozak Co-authored-by: Maciej Torhan Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 159 +++++++ xls/modules/zstd/ram_demux.x | 782 +++++++++++++++++++++++++++++++++++ 2 files changed, 941 insertions(+) create mode 100644 xls/modules/zstd/ram_demux.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 55ae6ffdf7..6769a643be 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1546,6 +1546,165 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "ram_demux_dslx", + srcs = ["ram_demux.x"], + deps = [ + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "ram_demux_dslx_test", + dslx_test_args = {"compare": "none"}, + library = ":ram_demux_dslx", +) + +xls_dslx_verilog( + name = "ram_demux_verilog", + codegen_args = { + "module_name": "RamDemux", + "generator": "pipeline", + "delay_model": "asap7", + "ram_configurations": ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram{}".format(num), + rd_req = "ram_demux__rd_req{}_s".format(num), + rd_resp = "ram_demux__rd_resp{}_r".format(num), + wr_req = "ram_demux__wr_req{}_s".format(num), + wr_resp = "ram_demux__wr_resp{}_r".format(num), + ) + for num in range(2) + ]), + "pipeline_stages": "6", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "RamDemuxInst", + library = ":ram_demux_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_8_5_next", + }, + verilog_file = "ram_demux.v", +) + +xls_benchmark_ir( + name = "ram_demux_opt_ir_benchmark", + src = "ram_demux_verilog.opt.ir", + benchmark_ir_args = { + "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_8_5_next", + }, + codegen_args = { + "pipeline_stages": "10", + }, +) + +verilog_library( + name = "ram_demux_verilog_lib", + srcs = [ + ":ram_demux.v", + ], +) + +synthesize_rtl( + name = "ram_demux_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "RamDemux", + deps = [ + ":ram_demux_verilog_lib", + ], +) + +benchmark_synth( + name = "ram_demux_benchmark_synth", + synth_target = ":ram_demux_synth_asap7", +) + +place_and_route( + name = "ram_demux_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":ram_demux_synth_asap7", + target_die_utilization_percentage = "5", +) + +xls_dslx_verilog( + name = "ram_demux_naive_verilog", + codegen_args = { + "module_name": "RamDemuxNaive", + "generator": "pipeline", + "delay_model": "asap7", + "ram_configurations": ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram{}".format(num), + rd_req = "ram_demux__rd_req{}_s".format(num), + rd_resp = "ram_demux__rd_resp{}_r".format(num), + wr_req = "ram_demux__wr_req{}_s".format(num), + wr_resp = "ram_demux__wr_resp{}_r".format(num), + ) + for num in range(2) + ]), + "pipeline_stages": "6", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "RamDemuxNaiveInst", + library = ":ram_demux_dslx", + opt_ir_args = { + "top": "__ram_demux__RamDemuxNaiveInst__RamDemuxNaive_0__5_8_0_8_next", + }, + verilog_file = "ram_demux_naive.v", +) + +xls_benchmark_ir( + name = "ram_demux_naive_opt_ir_benchmark", + src = "ram_demux_naive_verilog.opt.ir", + benchmark_ir_args = { + "top": "__ram_demux__RamDemuxNaiveInst__RamDemuxNaive_0__5_8_0_8_next", + }, + codegen_args = { + "pipeline_stages": "10", + }, +) + +verilog_library( + name = "ram_demux_naive_verilog_lib", + srcs = [ + ":ram_demux_naive.v", + ], +) + +synthesize_rtl( + name = "ram_demux_naive_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "RamDemuxNaive", + deps = [ + ":ram_demux_naive_verilog_lib", + ], +) + +benchmark_synth( + name = "ram_demux_naive_benchmark_synth", + synth_target = ":ram_demux_naive_synth_asap7", +) + +place_and_route( + name = "ram_demux_naive_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":ram_demux_naive_synth_asap7", + target_die_utilization_percentage = "5", +) + xls_dslx_library( name = "fse_dec_dslx", srcs = [ diff --git a/xls/modules/zstd/ram_demux.x b/xls/modules/zstd/ram_demux.x new file mode 100644 index 0000000000..2b188de92b --- /dev/null +++ b/xls/modules/zstd/ram_demux.x @@ -0,0 +1,782 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains a RamDemux implementation that can be used to connect +// a single proc with two RAM instances, by using a single RAM interface and +// switching between the RAMs, when requested. The switching occurs only after +// each request has received the corresponding response. +// Additionally, a "naive" implementation is provided that does not ensure +// any synchronization when switching RAMs. + +import std; +import xls.examples.ram; + +// First bit of queue is not used to simplify the implementation. +// Queue end is encoded using one-hot and if it is equal to 1, +// then the queue is empty. Queue length should be greater or equal +// to RAM latency, otherways the demux might not work properly. +struct RamDemuxState { + sel: u1, + sel_q_rd: uN[QUEUE_LEN + u32:1], + sel_q_wr: uN[QUEUE_LEN + u32:1], + sel_q_rd_end: uN[QUEUE_LEN + u32:1], + sel_q_wr_end: uN[QUEUE_LEN + u32:1], +} + +pub proc RamDemux< + ADDR_WIDTH: u32, + DATA_WIDTH: u32, + NUM_PARTITIONS: u32, + INIT_SEL: u1 = {u1:0}, + QUEUE_LEN: u32 = {u32:5} +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + type Queue = uN[QUEUE_LEN + u32:1]; + + sel_req_r: chan in; + sel_resp_s: chan<()> out; + + rd_req_r: chan in; + rd_resp_s: chan out; + wr_req_r: chan in; + wr_resp_s: chan out; + + rd_req0_s: chan out; + rd_resp0_r: chan in; + wr_req0_s: chan out; + wr_resp0_r: chan in; + + rd_req1_s: chan out; + rd_resp1_r: chan in; + wr_req1_s: chan out; + wr_resp1_r: chan in; + + config( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + rd_req_r: chan in, + rd_resp_s: chan out, + wr_req_r: chan in, + wr_resp_s: chan out, + + rd_req0_s: chan out, + rd_resp0_r: chan in, + wr_req0_s: chan out, + wr_resp0_r: chan in, + + rd_req1_s: chan out, + rd_resp1_r: chan in, + wr_req1_s: chan out, + wr_resp1_r: chan in + ) { + ( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + ) + } + + init { + RamDemuxState { + sel: INIT_SEL, + sel_q_rd: Queue:0, + sel_q_wr: Queue:0, + sel_q_rd_end: Queue:1, + sel_q_wr_end: Queue:1 + } + } + + next(state: RamDemuxState) { + let sel = state.sel; + let sel_q_rd = state.sel_q_rd; + let sel_q_wr = state.sel_q_wr; + let sel_q_rd_end = state.sel_q_rd_end; + let sel_q_wr_end = state.sel_q_wr_end; + + let tok = join(); + + // receive requests from input channel + // conditional reading is not required here ase the queue would + // never be full (assuming its length is greater or equal to RAM + // latency), as there would be at maxiumum one new request added + // to queue per cycle and the response for the first one should + // be received after number of cycles equal to RAM latency (which + // is less or equal to queue length) + let (tok1_0, rd_req, rd_req_valid) = recv_non_blocking(tok, rd_req_r, zero!()); + let (sel_q_rd_end, sel_q_rd) = if rd_req_valid { + (sel_q_rd_end << u32:1, (sel_q_rd << u32:1) | ((sel as Queue) << u32:1)) + } else { + (sel_q_rd_end, sel_q_rd) + }; + + let (tok1_1, wr_req, wr_req_valid) = recv_non_blocking(tok, wr_req_r, zero!()); + let (sel_q_wr_end, sel_q_wr) = if wr_req_valid { + (sel_q_wr_end << u32:1, (sel_q_wr << u32:1) | ((sel as Queue) << u32:1)) + } else { + (sel_q_wr_end, sel_q_wr) + }; + + // send requests to output channel 0 + let rd_req0_cond = ((sel_q_rd >> u32:1) as u1 == u1:0 && rd_req_valid); + let tok1_2 = send_if(tok, rd_req0_s, rd_req0_cond, rd_req); + + let wr_req0_cond = ((sel_q_wr >> u32:1) as u1 == u1:0 && wr_req_valid); + let tok1_3 = send_if(tok, wr_req0_s, wr_req0_cond, wr_req); + + // send requests to output channel 1 + let rd_req1_cond = ((sel_q_rd >> u32:1) as u1 == u1:1 && rd_req_valid); + let tok1_4 = send_if(tok, rd_req1_s, rd_req1_cond, rd_req); + + let wr_req1_cond = ((sel_q_wr >> u32:1) as u1 == u1:1 && wr_req_valid); + let tok1_5 = send_if(tok, wr_req1_s, wr_req1_cond, wr_req); + + // join tokens + let tok1 = join(tok1_0, tok1_1, tok1_2, tok1_3, tok1_4, tok1_5); + + // check which channel should be used for read/write + let rd_resp_ch = if (sel_q_rd & sel_q_rd_end) == Queue:0 { u1:0 } else { u1:1 }; + let wr_resp_ch = if (sel_q_wr & sel_q_wr_end) == Queue:0 { u1:0 } else { u1:1 }; + + // receive responses from output channel 0 + let (tok2_0, rd_resp0, rd_resp0_valid) = + recv_if_non_blocking(tok1, rd_resp0_r, rd_resp_ch == u1:0, zero!()); + let (tok2_1, wr_resp0, wr_resp0_valid) = + recv_if_non_blocking(tok1, wr_resp0_r, wr_resp_ch == u1:0, zero!()); + + // receive responses from output channel 1 + let (tok2_2, rd_resp1, rd_resp1_valid) = + recv_if_non_blocking(tok1, rd_resp1_r, rd_resp_ch == u1:1, zero!()); + let (tok2_3, wr_resp1, wr_resp1_valid) = + recv_if_non_blocking(tok1, wr_resp1_r, wr_resp_ch == u1:1, zero!()); + + // prepare read output values + let (rd_resp, rd_resp_valid) = if rd_resp_ch == u1:0 { + (rd_resp0, rd_resp0_valid) + } else { + (rd_resp1, rd_resp1_valid) + }; + + // prepare write output values + let (wr_resp, wr_resp_valid) = if wr_resp_ch == u1:0 { + (wr_resp0, wr_resp0_valid) + } else { + (wr_resp1, wr_resp1_valid) + }; + + // send responses to input channel + let tok2_4 = send_if(tok1, rd_resp_s, rd_resp_valid, rd_resp); + let sel_q_rd_end = if rd_resp_valid { sel_q_rd_end >> u32:1 } else { sel_q_rd_end }; + + let tok2_5 = send_if(tok1, wr_resp_s, wr_resp_valid, wr_resp); + let sel_q_wr_end = if wr_resp_valid { sel_q_wr_end >> u32:1 } else { sel_q_wr_end }; + + // handle select + let (tok1_6, sel, sel_valid) = recv_non_blocking(tok, sel_req_r, sel); + + let tok1_7 = send_if(tok1_6, sel_resp_s, sel_valid, ()); + + RamDemuxState { sel, sel_q_rd, sel_q_wr, sel_q_rd_end, sel_q_wr_end } + } +} + +const TEST_RAM_SIZE = u32:32; +const TEST_RAM_DATA_WIDTH = u32:8; +const TEST_RAM_ADDR_WIDTH = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE = u32:1; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_WIDTH); +const TEST_DEMUX_INIT_SEL = u1:0; +const TEST_DEMUX_QUEUE_LEN = u32:5; + +type TestWriteReq = ram::WriteReq; +type TestReadResp = ram::ReadResp; +type TestReadReq = ram::ReadReq; +type TestWriteResp = ram::WriteResp; +type TestDemuxAddr = uN[TEST_RAM_ADDR_WIDTH]; +type TestDemuxData = uN[TEST_RAM_DATA_WIDTH]; + +fn TestDemuxWriteWordReq(addr: TestDemuxAddr, data: TestDemuxData) -> TestWriteReq { + ram::WriteWordReq(addr, data) +} + +fn TestDemuxReadWordReq(addr: TestDemuxAddr) -> TestReadReq { + ram::ReadWordReq(addr) +} + +#[test_proc] +proc RamDemuxTest { + terminator: chan out; + + sel_req_s: chan out; + sel_resp_r: chan<()> in; + + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + wr_resp_r: chan in; + + rd_req0_s: chan out; + rd_resp0_r: chan in; + wr_req0_s: chan out; + wr_resp0_r: chan in; + + rd_req1_s: chan out; + rd_resp1_r: chan in; + wr_req1_s: chan out; + wr_resp1_r: chan in; + + config(terminator: chan out) { + let (sel_req_s, sel_req_r) = chan("sel_req"); + let (sel_resp_s, sel_resp_r) = chan<()>("sel_resp"); + + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + let (rd_req0_s, rd_req0_r) = chan("rd_req0"); + let (rd_resp0_s, rd_resp0_r) = chan("rd_resp0"); + let (wr_req0_s, wr_req0_r) = chan("wr_req0"); + let (wr_resp0_s, wr_resp0_r) = chan("wr_resp0"); + + let (rd_req1_s, rd_req1_r) = chan("rd_req1"); + let (rd_resp1_s, rd_resp1_r) = chan("rd_resp1"); + let (wr_req1_s, wr_req1_r) = chan("wr_req1"); + let (wr_resp1_s, wr_resp1_r) = chan("wr_resp1"); + + spawn RamDemux< + TEST_RAM_ADDR_WIDTH, TEST_RAM_DATA_WIDTH, TEST_RAM_NUM_PARTITIONS, + TEST_DEMUX_INIT_SEL, TEST_DEMUX_QUEUE_LEN + >( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r + ); + + spawn ram::RamModel( + rd_req0_r, rd_resp0_s, wr_req0_r, wr_resp0_s); + + spawn ram::RamModel( + rd_req1_r, rd_resp1_s, wr_req1_r, wr_resp1_s); + ( + terminator, sel_req_s, sel_resp_r, + rd_req_s, rd_resp_r, wr_req_s, wr_resp_r, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + ) + } + + init { } + + next(state: ()) { + let tok = join(); + // test case 0: write data with demux to ram0 and read directly + let addr = TestDemuxAddr:0; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x12); + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // write via demux + let tok = send(tok, wr_req_s, req); + let (tok, _) = recv(tok, wr_resp_r); + // read directly from ram0 + let tok = send(tok, rd_req0_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp0_r); + assert_eq(resp.data, req.data); + + // test case 1: write data with demux to ram1 and read directly + let addr = TestDemuxAddr:1; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x34); + // set sel to 1 + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // write via demux + let tok = send(tok, wr_req_s, req); + let (tok, _) = recv(tok, wr_resp_r); + // read directly from ram1 + let tok = send(tok, rd_req1_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp1_r); + assert_eq(resp.data, req.data); + + // test case 2: write data directly to ram0 and read with demux + let addr = TestDemuxAddr:0; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x56); + // write directly to ram0 + let tok = send(tok, wr_req0_s, req); + let (tok, _) = recv(tok, wr_resp0_r); + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // read via demux + let tok = send(tok, rd_req_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp_r); + assert_eq(resp.data, req.data); + + // test case 3: write data directly to ram1 and read with demux + let addr = TestDemuxAddr:0; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x78); + // write directly to ram1 + let tok = send(tok, wr_req1_s, req); + let (tok, _) = recv(tok, wr_resp1_r); + // set sel to 1 + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // read via demux + let tok = send(tok, rd_req_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp_r); + assert_eq(resp.data, req.data); + + // test case 4: try to switch sel during write + let addr = TestDemuxAddr:1; + // request + let req0 = TestDemuxWriteWordReq(addr, TestDemuxData:0xAB); + let req1 = TestDemuxWriteWordReq(addr, TestDemuxData:0xCD); + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // start write via demux + let tok = send(tok, wr_req_s, req0); + // set sel to 1 during read + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // finish write via demux + let (tok, _) = recv(tok, wr_resp_r); + // perform second write + let tok = send(tok, wr_req_s, req1); + let (tok, _) = recv(tok, wr_resp_r); + // read directly from ram0 and assert data from req0 was written + let tok = send(tok, rd_req0_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp0_r); + assert_eq(resp.data, req0.data); + // read directly from ram1 and assert data from req1 was written + let tok = send(tok, rd_req1_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp1_r); + assert_eq(resp.data, req1.data); + + // test case 5: try to switch sel during read + let addr = TestDemuxAddr:1; + // request + let req0 = TestDemuxWriteWordReq(addr, TestDemuxData:0xAB); + // write directly to ram0 + let tok = send(tok, wr_req0_s, req0); + let (tok, _) = recv(tok, wr_resp0_r); + let req1 = TestDemuxWriteWordReq(addr, TestDemuxData:0xCD); + // write directly to ram1 + let tok = send(tok, wr_req1_s, req1); + let (tok, _) = recv(tok, wr_resp1_r); + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // start read via demux + let tok = send(tok, rd_req_s, TestDemuxReadWordReq(addr)); + // set sel to 1 during read + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // finish read via demux + let (tok, resp0) = recv(tok, rd_resp_r); + // perform second read + let tok = send(tok, rd_req_s, TestDemuxReadWordReq(addr)); + let (tok, resp1) = recv(tok, rd_resp_r); + // assert that first read returned data from ram0 + assert_eq(resp0.data, req0.data); + // assert that second read returned data from ram1 + assert_eq(resp1.data, req1.data); + + // test case 6: sending more write requests than queue can hold + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // send 8 write requests + let tok = for (i, tok): (u32, token) in range(u32:0, TEST_DEMUX_QUEUE_LEN + u32:3) { + let req = TestDemuxWriteWordReq(i as TestDemuxAddr, i as TestDemuxData); + let tok = send(tok, wr_req_s, req); + let (tok, _) = recv(tok, wr_resp_r); + tok + }(tok); + // read values directly from ram + let tok = for (i, tok): (u32, token) in range(u32:0, TEST_DEMUX_QUEUE_LEN + u32:3) { + let req0 = TestDemuxReadWordReq(i as TestDemuxAddr); + let tok = send(tok, rd_req0_s, req0); + let (tok, resp0) = recv(tok, rd_resp0_r); + assert_eq(resp0.data, i as TestDemuxData); + tok + }(tok); + + // test case 7: sending more read requests than queue can hold + // set sel to 1 + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // write values directly to ram + let tok = for (i, tok): (u32, token) in range(u32:0, TEST_DEMUX_QUEUE_LEN + u32:3) { + let req1 = TestDemuxWriteWordReq(i as TestDemuxAddr, i as TestDemuxData); + let tok = send(tok, wr_req1_s, req1); + let (tok, _) = recv(tok, wr_resp1_r); + tok + }(tok); + // send 8 write requests + let tok = for (i, tok): (u32, token) in range(u32:0, TEST_DEMUX_QUEUE_LEN + u32:3) { + let req = TestDemuxReadWordReq(i as TestDemuxAddr); + let tok = send(tok, rd_req_s, req); + let (tok, resp) = recv(tok, rd_resp_r); + assert_eq(resp.data, i as TestDemuxData); + tok + }(tok); + + let tok = send(tok, terminator, true); + } +} + +const RAM_SIZE = u32:32; +const RAM_DATA_WIDTH = u32:8; +const RAM_ADDR_WIDTH = std::clog2(RAM_SIZE); +const RAM_WORD_PARTITION_SIZE = u32:1; +const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH); + +// Sample for codegen +pub proc RamDemuxInst { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + config( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + + rd_req_r: chan in, + rd_resp_s: chan out, + wr_req_r: chan in, + wr_resp_s: chan out, + + rd_req0_s: chan out, + rd_resp0_r: chan in, + wr_req0_s: chan out, + wr_resp0_r: chan in, + + rd_req1_s: chan out, + rd_resp1_r: chan in, + wr_req1_s: chan out, + wr_resp1_r: chan in + ) { + spawn RamDemux( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r + ); + } + + init { } + + next(state: ()) { } +} + +struct RamDemuxNaiveState { sel: u1 } + +// This implementation does not support sel switching during read/write operation +proc RamDemuxNaive< + ADDR_WIDTH: u32, + DATA_WIDTH: u32, + NUM_PARTITIONS: u32, + INIT_SEL: u1 = {u1:0} +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + sel_req_r: chan in; + sel_resp_s: chan<()> out; + + rd_req_r: chan in; + rd_resp_s: chan out; + wr_req_r: chan in; + wr_resp_s: chan out; + + rd_req0_s: chan out; + rd_resp0_r: chan in; + wr_req0_s: chan out; + wr_resp0_r: chan in; + + rd_req1_s: chan out; + rd_resp1_r: chan in; + wr_req1_s: chan out; + wr_resp1_r: chan in; + + config( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + rd_req_r: chan in, + rd_resp_s: chan out, + wr_req_r: chan in, + wr_resp_s: chan out, + + rd_req0_s: chan out, + rd_resp0_r: chan in, + wr_req0_s: chan out, + wr_resp0_r: chan in, + + rd_req1_s: chan out, + rd_resp1_r: chan in, + wr_req1_s: chan out, + wr_resp1_r: chan in + ) { + ( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + ) + } + + init { RamDemuxNaiveState { sel: INIT_SEL } } + + next(state: RamDemuxNaiveState) { + let tok = join(); + + let sel = state.sel; + + // receive requests from input channel + let (tok1_0, rd_req, rd_req_valid) = recv_non_blocking(tok, rd_req_r, zero!()); + let (tok1_1, wr_req, wr_req_valid) = recv_non_blocking(tok, wr_req_r, zero!()); + + // send requests to output channel 0 + let rd_req0_cond = (sel == u1:0 && rd_req_valid); + let tok1_2 = send_if(tok, rd_req0_s, rd_req0_cond, rd_req); + + let wr_req0_cond = (sel == u1:0 && wr_req_valid); + let tok1_3 = send_if(tok, wr_req0_s, wr_req0_cond, wr_req); + + // send requests to output channel 1 + let rd_req1_cond = (sel == u1:1 && rd_req_valid); + let tok1_4 = send_if(tok, rd_req1_s, rd_req1_cond, rd_req); + + let wr_req1_cond = (sel == u1:1 && wr_req_valid); + let tok1_5 = send_if(tok, wr_req1_s, wr_req1_cond, wr_req); + + // join tokens + let tok1 = join(tok1_0, tok1_1, tok1_2, tok1_3, tok1_4, tok1_5); + + // receive responses from output channel 0 + let (tok2_0, rd_resp0, rd_resp0_valid) = + recv_if_non_blocking(tok1, rd_resp0_r, sel == u1:0, zero!()); + let (tok2_1, wr_resp0, wr_resp0_valid) = + recv_if_non_blocking(tok1, wr_resp0_r, sel == u1:0, zero!()); + + // receive responses from output channel 1 + let (tok2_2, rd_resp1, rd_resp1_valid) = + recv_if_non_blocking(tok1, rd_resp1_r, sel == u1:1, zero!()); + let (tok2_3, wr_resp1, wr_resp1_valid) = + recv_if_non_blocking(tok1, wr_resp1_r, sel == u1:1, zero!()); + + // prepare output values + let (rd_resp, rd_resp_valid, wr_resp, wr_resp_valid) = if sel == u1:0 { + (rd_resp0, rd_resp0_valid, wr_resp0, wr_resp0_valid) + } else { + (rd_resp1, rd_resp1_valid, wr_resp1, wr_resp1_valid) + }; + + // send responses to input channel + let tok2_4 = send_if(tok1, rd_resp_s, rd_resp_valid, rd_resp); + let tok2_5 = send_if(tok1, wr_resp_s, wr_resp_valid, wr_resp); + + // handle select + let (tok1_6, sel, sel_valid) = recv_non_blocking(tok, sel_req_r, sel); + + let tok1_7 = send_if(tok1_6, sel_resp_s, sel_valid, ()); + + RamDemuxNaiveState { sel } + } +} + +#[test_proc] +proc RamDemuxNaiveTest { + terminator: chan out; + + sel_req_s: chan out; + sel_resp_r: chan<()> in; + + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + wr_resp_r: chan in; + + rd_req0_s: chan out; + rd_resp0_r: chan in; + wr_req0_s: chan out; + wr_resp0_r: chan in; + + rd_req1_s: chan out; + rd_resp1_r: chan in; + wr_req1_s: chan out; + wr_resp1_r: chan in; + + config(terminator: chan out) { + let (sel_req_s, sel_req_r) = chan("sel_req"); + let (sel_resp_s, sel_resp_r) = chan<()>("sel_resp"); + + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + let (rd_req0_s, rd_req0_r) = chan("rd_req0"); + let (rd_resp0_s, rd_resp0_r) = chan("rd_resp0"); + let (wr_req0_s, wr_req0_r) = chan("wr_req0"); + let (wr_resp0_s, wr_resp0_r) = chan("wr_resp0"); + + let (rd_req1_s, rd_req1_r) = chan("wr_req1"); + let (rd_resp1_s, rd_resp1_r) = chan("wr_resp1"); + let (wr_req1_s, wr_req1_r) = chan("wr_req1"); + let (wr_resp1_s, wr_resp1_r) = chan("wr_resp1"); + + spawn RamDemuxNaive( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r + ); + + spawn ram::RamModel( + rd_req0_r, rd_resp0_s, wr_req0_r, wr_resp0_s); + + spawn ram::RamModel( + rd_req1_r, rd_resp1_s, wr_req1_r, wr_resp1_s); + ( + terminator, sel_req_s, sel_resp_r, + rd_req_s, rd_resp_r, wr_req_s, wr_resp_r, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + ) + } + + init { } + + next(state: ()) { + let tok = join(); + // test case 0: write data with demux to ram0 and read directly + let addr = TestDemuxAddr:0; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x12); + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // write via demux + let tok = send(tok, wr_req_s, req); + let (tok, _) = recv(tok, wr_resp_r); + // read directly from ram0 + let tok = send(tok, rd_req0_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp0_r); + assert_eq(resp.data, req.data); + + // test case 1: write data with demux to ram1 and read directly + let addr = TestDemuxAddr:1; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x34); + // set sel to 1 + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // write via demux + let tok = send(tok, wr_req_s, req); + let (tok, _) = recv(tok, wr_resp_r); + // read directly from ram1 + let tok = send(tok, rd_req1_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp1_r); + assert_eq(resp.data, req.data); + + // test case 2: write data directly to ram0 and read with demux + let addr = TestDemuxAddr:0; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x56); + // write directly to ram0 + let tok = send(tok, wr_req0_s, req); + let (tok, _) = recv(tok, wr_resp0_r); + // set sel to 0 + let tok = send(tok, sel_req_s, u1:0); + let (tok, _) = recv(tok, sel_resp_r); + // read via demux + let tok = send(tok, rd_req_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp_r); + assert_eq(resp.data, req.data); + + // test case 3: write data directly to ram1 and read with demux + let addr = TestDemuxAddr:0; + // request + let req = TestDemuxWriteWordReq(addr, TestDemuxData:0x78); + // write directly to ram1 + let tok = send(tok, wr_req1_s, req); + let (tok, _) = recv(tok, wr_resp1_r); + // set sel to 1 + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + // read via demux + let tok = send(tok, rd_req_s, TestDemuxReadWordReq(addr)); + let (tok, resp) = recv(tok, rd_resp_r); + assert_eq(resp.data, req.data); + + // test cases 4 and 5 from RamDemuxTest are not relevant here as this naive + // implementation does not support sel switching during read/write operations + + let tok = send(tok, terminator, true); + } +} + +// Sample for codegen +pub proc RamDemuxNaiveInst { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + config( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + + rd_req_r: chan in, + rd_resp_s: chan out, + wr_req_r: chan in, + wr_resp_s: chan out, + + rd_req0_s: chan out, + rd_resp0_r: chan in, + wr_req0_s: chan out, + wr_resp0_r: chan in, + + rd_req1_s: chan out, + rd_resp1_r: chan in, + wr_req1_s: chan out, + wr_resp1_r: chan in + ) { + spawn RamDemuxNaive( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r + ); + } + + init { } + + next(state: ()) { } +} From e551ac5fcc74b41ecc5000d33882cf30d0cbf478 Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Fri, 10 May 2024 15:21:33 +0200 Subject: [PATCH 40/85] modules/zstd: Add literals decoding Co-authored-by: Pawel Czarnecki Co-authored-by: Ryszard Rozak Signed-off-by: Maciej Torhan Signed-off-by: Pawel Czarnecki Signed-off-by: Ryszard Rozak --- xls/modules/zstd/BUILD | 445 ++++++++- xls/modules/zstd/common.x | 71 +- xls/modules/zstd/dec_mux.x | 2 +- xls/modules/zstd/literals_buffer.x | 1185 ++++++++++++++++++++++++ xls/modules/zstd/literals_decoder.x | 709 ++++++++++++++ xls/modules/zstd/literals_dispatcher.x | 243 +++++ xls/modules/zstd/parallel_rams.x | 720 ++++++++++++++ xls/modules/zstd/raw_literals_dec.x | 81 ++ xls/modules/zstd/rle_literals_dec.x | 409 ++++++++ xls/modules/zstd/sequence_executor.x | 856 ++--------------- xls/modules/zstd/zstd_dec.x | 2 +- 11 files changed, 3957 insertions(+), 766 deletions(-) create mode 100644 xls/modules/zstd/literals_buffer.x create mode 100644 xls/modules/zstd/literals_decoder.x create mode 100644 xls/modules/zstd/literals_dispatcher.x create mode 100644 xls/modules/zstd/parallel_rams.x create mode 100644 xls/modules/zstd/raw_literals_dec.x create mode 100644 xls/modules/zstd/rle_literals_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 6769a643be..9fe726bbe2 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -602,6 +602,20 @@ xls_dslx_test( tags = ["manual"], ) +xls_dslx_library( + name = "parallel_rams_dslx", + srcs = ["parallel_rams.x"], + deps = [ + ":common_dslx", + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "parallel_rams_dslx_test", + library = ":parallel_rams_dslx", +) + xls_dslx_library( name = "sequence_executor_dslx", srcs = [ @@ -610,6 +624,7 @@ xls_dslx_library( deps = [ ":common_dslx", ":ram_printer_dslx", + ":parallel_rams_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:mem_writer_dslx", ], @@ -707,6 +722,8 @@ place_and_route( clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.4", + die_height_microns = 120, + die_width_microns = 120, placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":sequence_executor_asap7", @@ -1711,7 +1728,6 @@ xls_dslx_library( "fse_dec.x", ], deps = [ - "//xls/examples:ram_dslx", ":common_dslx", ":math_dslx", ":fse_table_creator_dslx", @@ -1783,13 +1799,436 @@ place_and_route( name = "fse_dec_place_and_route", clock_period = "750", core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", die_height_microns = 100, die_width_microns = 100, + min_pin_distance = "0.5", + placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":fse_dec_synth_asap7", tags = ["manual"], target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "literals_dispatcher_dslx", + srcs = [ + "literals_dispatcher.x", + ], + deps = [ + ":common_dslx", + ], +) + +xls_dslx_test( + name = "literals_dispatcher_dslx_test", + library = ":literals_dispatcher_dslx", +) + +xls_dslx_verilog( + name = "literals_dispatcher_verilog", + codegen_args = { + "module_name": "LiteralsDispatcher", + "delay_model": "asap7", + "pipeline_stages": "1", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "LiteralsDispatcher", + library = ":literals_dispatcher_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__literals_dispatcher__LiteralsDispatcher_0_next", + }, + verilog_file = "literals_dispatcher.v", +) + +xls_benchmark_ir( + name = "literals_dispatcher_opt_ir_benchmark", + src = ":literals_dispatcher_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "1", + "delay_model": "asap7", + }, +) + +xls_benchmark_verilog( + name = "literals_dispatcher_verilog_benchmark", + verilog_target = "literals_dispatcher_verilog", +) + +verilog_library( + name = "literals_dispatcher_verilog_lib", + srcs = [ + ":literals_dispatcher.v", + ], +) + +synthesize_rtl( + name = "literals_dispatcher_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "LiteralsDispatcher", + deps = [ + ":literals_dispatcher_verilog_lib", + ], +) + +benchmark_synth( + name = "literals_dispatcher_benchmark_synth", + synth_target = ":literals_dispatcher_synth_asap7", +) + +place_and_route( + name = "literals_dispatcher_place_and_route", + clock_period = "750", + core_padding_microns = 2, + die_height_microns = 64, + die_width_microns = 64, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":literals_dispatcher_synth_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "rle_literals_dec_dslx", + srcs = [ + "rle_literals_dec.x", + ], + deps = [ + ":common_dslx", + "//xls/modules/rle:rle_common_dslx", + "//xls/modules/rle:rle_dec_dslx", + ], +) + +xls_dslx_test( + name = "rle_literals_dec_dslx_test", + library = ":rle_literals_dec_dslx", +) + +xls_dslx_verilog( + name = "rle_literals_dec_verilog", + codegen_args = { + "module_name": "rle_literals_dec", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "RleLiteralsDecoder", + library = ":rle_literals_dec_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__rle_literals_dec__RleLiteralsDecoder__BatchPacker_0_next", + }, + verilog_file = "rle_literals_dec.v", +) + +xls_benchmark_ir( + name = "rle_literals_dec_opt_ir_benchmark", + src = ":rle_literals_dec_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, +) + +verilog_library( + name = "rle_literals_dec_verilog_lib", + srcs = [ + ":rle_literals_dec.v", + ], +) + +synthesize_rtl( + name = "rle_literals_dec_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "rle_literals_dec", + deps = [ + ":rle_literals_dec_verilog_lib", + ], +) + +benchmark_synth( + name = "rle_literals_dec_benchmark_synth", + synth_target = ":rle_literals_dec_synth_asap7", +) + +place_and_route( + name = "rle_literals_dec_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":rle_literals_dec_synth_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "raw_literals_dec_dslx", + srcs = ["raw_literals_dec.x"], + deps = [ + ":common_dslx", + ], +) + +xls_dslx_test( + name = "raw_literals_dec_dslx_test", + library = ":raw_literals_dec_dslx", +) + +xls_dslx_verilog( + name = "raw_literals_dec_verilog", + codegen_args = { + "module_name": "RawLiteralsDecoder", + "delay_model": "asap7", + "pipeline_stages": "1", + "reset": "rst", + "use_system_verilog": "false", + }, + dslx_top = "RawLiteralsDecoder", + library = ":raw_literals_dec_dslx", + verilog_file = "raw_literals_dec.v", +) + +xls_benchmark_ir( + name = "raw_literals_dec_opt_ir_benchmark", + src = ":raw_literals_dec_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "delay_model": "asap7", + }, +) + +xls_benchmark_verilog( + name = "raw_literals_dec_verilog_benchmark", + verilog_target = "raw_literals_dec_verilog", +) + +verilog_library( + name = "raw_literals_dec_lib", + srcs = [ + ":raw_literals_dec.v", + ], +) + +synthesize_rtl( + name = "raw_literals_dec_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "RawLiteralsDecoder", + deps = [ + ":raw_literals_dec_lib", + ], +) + +benchmark_synth( + name = "raw_literals_dec_benchmark_synth", + synth_target = ":raw_literals_dec_asap7", +) + +place_and_route( + name = "raw_literals_dec_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.09", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":raw_literals_dec_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "literals_buffer_dslx", + srcs = [ + "literals_buffer.x", + ], + deps = [ + ":common_dslx", + ":ram_printer_dslx", + ":parallel_rams_dslx", + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "literals_buffer_dslx_test", + library = ":literals_buffer_dslx", +) + +xls_dslx_verilog( + name = "literals_buffer_verilog", + codegen_args = { + "module_name": "LiteralsBuffer", + "delay_model": "asap7", + "ram_configurations": ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram{}".format(num), + rd_req = "literals_buffer__rd_req_m{}_s".format(num), + rd_resp = "literals_buffer__rd_resp_m{}_r".format(num), + wr_req = "literals_buffer__wr_req_m{}_s".format(num), + wr_resp = "literals_buffer__wr_resp_m{}_r".format(num), + ) + for num in range(7) + ]), + "pipeline_stages": "6", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "LiteralsBufferInst", + library = ":literals_buffer_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__literals_buffer__LiteralsBufferInst__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next" + }, + verilog_file = "literals_buffer.v", +) + +xls_benchmark_ir( + name = "literals_buffer_opt_ir_benchmark", + src = ":literals_buffer_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "6", + "delay_model": "asap7", + }, +) + +xls_benchmark_verilog( + name = "literals_buffer_verilog_benchmark", + verilog_target = "literals_buffer_verilog", +) + +verilog_library( + name = "literals_buffer_verilog_lib", + srcs = [ + ":literals_buffer.v", + ], +) + +synthesize_rtl( + name = "literals_buffer_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "LiteralsBuffer", + deps = [ + ":literals_buffer_verilog_lib", + ], +) + +benchmark_synth( + name = "literals_buffer_benchmark_synth", + synth_target = ":literals_buffer_synth_asap7", +) + +place_and_route( + name = "literals_buffer_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":literals_buffer_synth_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "literals_decoder_dslx", + srcs = [ + "literals_decoder.x", + ], + deps = [ + "//xls/examples:ram_dslx", + ":common_dslx", + ":literals_buffer_dslx", + ":literals_dispatcher_dslx", + ":parallel_rams_dslx", + ":ram_printer_dslx", + ":raw_literals_dec_dslx", + ":rle_literals_dec_dslx", + ], +) + +xls_dslx_test( + name = "literals_decoder_dslx_test", + library = ":literals_decoder_dslx", +) + +xls_dslx_verilog( + name = "literals_decoder_verilog", + codegen_args = { + "module_name": "LiteralsDecoder", + "delay_model": "asap7", + "ram_configurations": ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram{}".format(num), + rd_req = "literals_decoder__rd_req_m{}_s".format(num), + rd_resp = "literals_decoder__rd_resp_m{}_r".format(num), + wr_req = "literals_decoder__wr_req_m{}_s".format(num), + wr_resp = "literals_decoder__wr_resp_m{}_r".format(num), + ) + for num in range(7) + ]), + "pipeline_stages": "8", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "LiteralsDecoderInst", + library = ":literals_decoder_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__xls_modules_zstd_literals_buffer__LiteralsDecoderInst__LiteralsDecoder_0__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next", + }, + verilog_file = "literals_decoder.v", +) + +xls_benchmark_ir( + name = "literals_decoder_opt_ir_benchmark", + src = ":literals_decoder_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "10", + "delay_model": "asap7", + }, +) + +xls_benchmark_verilog( + name = "literals_decoder_verilog_benchmark", + verilog_target = "literals_decoder_verilog", +) + +verilog_library( + name = "literals_decoder_verilog_lib", + srcs = [ + ":literals_decoder.v", + ], +) + +synthesize_rtl( + name = "literals_decoder_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "LiteralsDecoder", + deps = [ + ":literals_decoder_verilog_lib", + ], +) + +benchmark_synth( + name = "literals_decoder_benchmark_synth", + synth_target = ":literals_decoder_synth_asap7", +) + +place_and_route( + name = "literals_decoder_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":literals_decoder_synth_asap7", + target_die_utilization_percentage = "10", +) diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 13773aad47..68ff6bf81a 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -26,6 +26,7 @@ pub const BUFFER_WIDTH = u32:128; pub const MAX_BLOCK_SIZE_KB = u32:64; pub const BLOCK_PACKET_WIDTH = u32:32; +pub const SYMBOLS_IN_PACKET = DATA_WIDTH/SYMBOL_WIDTH; pub type BlockData = bits[DATA_WIDTH]; pub type BlockPacketLength = bits[BLOCK_PACKET_WIDTH]; @@ -59,10 +60,10 @@ pub struct ExtendedBlockDataPacket { packet: BlockDataPacket, } -pub struct SequenceExecutorPacket { +pub struct SequenceExecutorPacket { msg_type: SequenceExecutorMessageType, length: CopyOrMatchLength, // Literal length or match length - content: CopyOrMatchContent, // Literal data or match offset + content: uN[DATA_W * u32:8], // Literal data or match offset last: bool, // Last packet in frame } @@ -73,7 +74,7 @@ pub struct BlockSyncData { pub struct CommandConstructorData { sync: BlockSyncData, - data: SequenceExecutorPacket, + data: SequenceExecutorPacket, } // Defines output format of the ZSTD Decoder @@ -238,3 +239,67 @@ pub type SeqDecShiftBufferInput = shift_buffer::ShiftBufferPacket; pub type SeqDecShiftBufferPacket = shift_buffer::ShiftBufferPacket; pub type SeqDecShiftBufferStatus = shift_buffer::ShiftBufferStatus; + +// Literals decoding + +pub const RLE_LITERALS_DATA_WIDTH = u32:8; +pub const RLE_LITERALS_REPEAT_WIDTH = u32:20; +pub const LITERALS_DATA_WIDTH = u32:64; +pub const LITERALS_LENGTH_WIDTH = std::clog2( + std::ceil_div(LITERALS_DATA_WIDTH, RLE_LITERALS_DATA_WIDTH) + u32:1 +); + +pub type RleLitData = uN[RLE_LITERALS_DATA_WIDTH]; +pub type RleLitRepeat = uN[RLE_LITERALS_REPEAT_WIDTH]; +pub type LitData = uN[LITERALS_DATA_WIDTH]; +pub type LitLength = uN[LITERALS_LENGTH_WIDTH]; +pub type LitID = u32; + +pub type DecompressedSize = u20; + +pub enum LiteralType: u3 { + RAW = 0, + RLE = 1, + COMP = 2, + COMP_4 = 3, + TREELESS = 4, + TREELESS_4 = 5, +} + +pub struct Streams { + count: bits[2], + stream_lengths: bits[20][4], +} + +pub struct LiteralsPathCtrl { + data_conf: Streams, + decompressed_size: DecompressedSize, + literals_type: LiteralType, +} + +pub struct RleLiteralsData { + data: RleLitData, + repeat: RleLitRepeat, + last: bool, + id: LitID, +} + +pub struct LiteralsData { + data: LitData, + length: LitLength, + last: bool, +} + +pub struct LiteralsDataWithSync { + data: LitData, + length: LitLength, + last: bool, + id: LitID, + literals_last: bool, +} + +pub struct LiteralsBufferCtrl { + length: u32, + last: bool, +} + diff --git a/xls/modules/zstd/dec_mux.x b/xls/modules/zstd/dec_mux.x index ef24e9b542..6f0d1d7f8b 100644 --- a/xls/modules/zstd/dec_mux.x +++ b/xls/modules/zstd/dec_mux.x @@ -26,7 +26,7 @@ type BlockPacketLength = common::BlockPacketLength; type CopyOrMatchContent = common::CopyOrMatchContent; type CopyOrMatchLength = common::CopyOrMatchLength; type SequenceExecutorMessageType = common::SequenceExecutorMessageType; -type SequenceExecutorPacket = common::SequenceExecutorPacket; +type SequenceExecutorPacket = common::SequenceExecutorPacket; const MAX_ID = common::DATA_WIDTH; const DATA_WIDTH = common::DATA_WIDTH; diff --git a/xls/modules/zstd/literals_buffer.x b/xls/modules/zstd/literals_buffer.x new file mode 100644 index 0000000000..1ad9ff4407 --- /dev/null +++ b/xls/modules/zstd/literals_buffer.x @@ -0,0 +1,1185 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of LiteralsBuffer responsible for +// storing data received either from RAW, RLE or Huffman literals decoder and +// sending it to CommandConstructor. + +import std; + +import xls.examples.ram; +import xls.modules.zstd.common as common; +import xls.modules.zstd.parallel_rams as parallel_rams; +import xls.modules.zstd.ram_printer as ram_printer; + +type CopyOrMatchContent = common::CopyOrMatchContent; +type CopyOrMatchLength = common::CopyOrMatchLength; +type LitData = common::LitData; +type LitID = common::LitID; +type LitLength = common::LitLength; +type LiteralsBufferCtrl = common::LiteralsBufferCtrl; +type LiteralsData = common::LiteralsData; +type LiteralsDataWithSync = common::LiteralsDataWithSync; +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; +type SequenceExecutorPacket = common::SequenceExecutorPacket; + +type HistoryBufferPtr = parallel_rams::HistoryBufferPtr; +type RamNumber = parallel_rams::RamNumber; +type RamReadStart = parallel_rams::RamReadStart; +type RamRdRespHandlerData = parallel_rams::RamRdRespHandlerData; +type RamWrRespHandlerData = parallel_rams::RamWrRespHandlerData; +type RamWrRespHandlerResp = parallel_rams::RamWrRespHandlerResp; + +// Constants calculated from RAM parameters +pub const RAM_NUM = parallel_rams::RAM_NUM; +const RAM_NUM_WIDTH = parallel_rams::RAM_NUM_WIDTH; +pub const RAM_DATA_WIDTH = common::SYMBOL_WIDTH + u32:1; // the +1 is used to store "last" flag +pub const RAM_WORD_PARTITION_SIZE = RAM_DATA_WIDTH; +pub const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH); + +// Literals data with last flag +type LiteralsWithLast = uN[RAM_DATA_WIDTH * RAM_NUM]; + +// RAM related constants common for tests +const TEST_HISTORY_BUFFER_SIZE_KB = u32:1; +const TEST_RAM_SIZE = parallel_rams::ram_size(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_RAM_ADDR_WIDTH = parallel_rams::ram_addr_width(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_INIT_HB_PTR_ADDR = u32:127; +const TEST_RAM_INITIALIZED = true; +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; + +type TestRamAddr = bits[TEST_RAM_ADDR_WIDTH]; +type TestWriteReq = ram::WriteReq; +type TestWriteResp = ram::WriteResp; +type TestReadReq = ram::ReadReq; +type TestReadResp = ram::ReadResp; + +struct LiteralsBufferMuxState { + // Literals sync handling + ctrl_last: bool, + literals_id: LitID, + // Received literals + raw_literals_valid: bool, + raw_literals_data: LiteralsDataWithSync, + rle_literals_valid: bool, + rle_literals_data: LiteralsDataWithSync, + huff_literals_valid: bool, + huff_literals_data: LiteralsDataWithSync, +} + +struct LiteralsBufferWriterState { + // History Buffer handling + hyp_ptr: HistoryBufferPtr, + hb_len: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], + literals_in_ram: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], +} + +struct LiteralsBufferReaderState { + // History Buffer handling + hyp_ptr: HistoryBufferPtr, + hb_len: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], + literals_in_ram: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], + ctrl_last: bool, + left_to_read: u32, +} + +struct LiteralsBufferWriterToReaderSync { + literals_written: LitLength, +} + +struct LiteralsBufferReaderToWriterSync { + literals_read: LitLength, +} + +// PacketDecoder is responsible for receiving read bytes from RAMs response +// handler, removing the "last" flag from each literal and adding this flag +// to the packet. It also validates the data. +proc PacketDecoder { + literals_in_r: chan> in; + literals_out_s: chan> out; + buffer_sync_s: chan out; + + config( + literals_in_r: chan> in, + literals_out_s: chan> out, + buffer_sync_s: chan out, + ) { + (literals_in_r, literals_out_s, buffer_sync_s) + } + + init { } + + next (state: ()) { + let tok = join(); + let (tok, literals) = recv(tok, literals_in_r); + + // Strip flag last from literals + let literals_data = for (i, data): (u32, CopyOrMatchContent) in range(u32:0, RAM_NUM) { + bit_slice_update( + data, + common::SYMBOL_WIDTH * i, + (literals.content >> (RAM_DATA_WIDTH * i)) as uN[common::SYMBOL_WIDTH] + ) + }(CopyOrMatchContent:0); + + // Extract last and validate packet. The resulting last is set if and + // only if any of the literas has it set. Also if any literal has set + // this flag, then the flag in following literal must also be set. In + // other case, the assertion is triggered. + let (last, _, packet_valid, _) = for (i, (last, prev_literal_last, packet_valid, prev_calc)): (u32, (bool, bool, bool, bool)) in range(u32:0, RAM_NUM) { + let literal_last = (literals.content >> (RAM_DATA_WIDTH * (i + u32:1) - u32:1)) as u1; + let calc = if (i == literals.length as uN[32]) { + false + } else { + prev_calc + }; + if (calc) { + ( + last | literal_last, + literal_last, + packet_valid & (!prev_literal_last | literal_last), + calc + ) + } else { + ( + last, + literal_last, + packet_valid, + calc + ) + } + }((false, false, true, true)); + + assert!(packet_valid && (literals.last == last), "Invalid packet"); + + // Send literals data + let tok = send(tok, literals_out_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: literals.length, + content: literals_data, + last: last + }); + + // Send sync data to buffer writer + let tok = send(tok, buffer_sync_s, LiteralsBufferReaderToWriterSync { + literals_read: literals.length as LitLength, + }); + } +} + +fn literals_content(literal: u8, last: u1, pos: u3) -> LiteralsWithLast { + ( + literal as LiteralsWithLast | + ((last as LiteralsWithLast) << common::SYMBOL_WIDTH)) << (RAM_DATA_WIDTH * (pos as u32) + ) +} + + +const TEST_LITERALS_IN: SequenceExecutorPacket[4] = [ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: literals_content(u8:0xAB, u1:0, u3:0), + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:2, + content: ( + literals_content(u8:0x12, u1:0, u3:1) | + literals_content(u8:0x34, u1:0, u3:0) + ), + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: ( + literals_content(u8:0xFE, u1:0, u3:7) | + literals_content(u8:0xDC, u1:0, u3:6) | + literals_content(u8:0xBA, u1:0, u3:5) | + literals_content(u8:0x98, u1:0, u3:4) | + literals_content(u8:0x76, u1:0, u3:3) | + literals_content(u8:0x54, u1:0, u3:2) | + literals_content(u8:0x32, u1:0, u3:1) | + literals_content(u8:0x10, u1:0, u3:0) + ), + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: ( + literals_content(u8:0xAA, u1:1, u3:3) | + literals_content(u8:0xBB, u1:1, u3:2) | + literals_content(u8:0xCC, u1:0, u3:1) | + literals_content(u8:0xDD, u1:0, u3:0) + ), + last: true, + }, +]; + +const TEST_LITERALS_OUT: SequenceExecutorPacket[4] = [ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0xAB, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:2, + content: CopyOrMatchContent:0x1234, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xFEDC_BA98_7654_3210, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0xAABB_CCDD, + last: true, + }, +]; + +#[test_proc] +proc PacketDecoder_test { + terminator: chan out; + + literals_in_s: chan> out; + literals_out_r: chan> in; + buffer_sync_r: chan in; + + config(terminator: chan out) { + let (literals_in_s, literals_in_r) = chan>("literals_in"); + let (literals_out_s, literals_out_r) = chan>("literals_out"); + let (buffer_sync_s, buffer_sync_r) = chan("buffer_sync"); + + spawn PacketDecoder(literals_in_r, literals_out_s, buffer_sync_s); + + (terminator, literals_in_s, literals_out_r, buffer_sync_r) + } + + init { } + + next (state: ()) { + let tok = join(); + let tok = for (i, tok): (u32, token) in range(u32:0, array_size(TEST_LITERALS_IN)) { + let tok = send(tok, literals_in_s, TEST_LITERALS_IN[i]); + trace_fmt!("Sent #{} literals {:#x}", i, TEST_LITERALS_IN[i]); + tok + }(tok); + + let tok = for (i, tok): (u32, token) in range(u32:0, array_size(TEST_LITERALS_OUT)) { + let (tok, literals) = recv(tok, literals_out_r); + trace_fmt!("Received #{} literals {:#x}", i, literals); + assert_eq(TEST_LITERALS_OUT[i], literals); + tok + }(tok); + + send(tok, terminator, true); + } +} + +// Proc responsible for receiving literals from RAW, RLE and Huffman decoders +// and sending them to the writer in correct order. +proc LiteralsBufferMux { + raw_literals_r: chan in; + rle_literals_r: chan in; + huff_literals_r: chan in; + + out_literals_s: chan out; + + config( + raw_literals_r: chan in, + rle_literals_r: chan in, + huff_literals_r: chan in, + out_literals_s: chan out, + ) { + ( + raw_literals_r, rle_literals_r, huff_literals_r, + out_literals_s + ) + } + + init { zero!() } + + next (state: LiteralsBufferMuxState) { + let tok0 = join(); + // Receive literals + + let (tok1_0, raw_literals, raw_literals_valid) = recv_if_non_blocking( + tok0, raw_literals_r, !state.raw_literals_valid, state.raw_literals_data + ); + let (tok1_1, rle_literals, rle_literals_valid) = recv_if_non_blocking( + tok0, rle_literals_r, !state.rle_literals_valid, state.rle_literals_data + ); + let (tok1_2, huff_literals, huff_literals_valid) = recv_if_non_blocking( + tok0, huff_literals_r, !state.huff_literals_valid, state.huff_literals_data + ); + let state = LiteralsBufferMuxState { + raw_literals_valid: state.raw_literals_valid || raw_literals_valid, + raw_literals_data: raw_literals, + rle_literals_valid: state.rle_literals_valid || rle_literals_valid, + rle_literals_data: rle_literals, + huff_literals_valid: state.huff_literals_valid || huff_literals_valid, + huff_literals_data: huff_literals, + ..state + }; + + let tok1 = join(tok1_0, tok1_1, tok1_2); + + // Select proper literals + let sel_raw_literals = state.raw_literals_valid && state.raw_literals_data.id == state.literals_id; + let sel_rle_literals = state.rle_literals_valid && state.rle_literals_data.id == state.literals_id; + let sel_huff_literals = state.huff_literals_valid && state.huff_literals_data.id == state.literals_id; + + let literals_data = zero!(); + let literals_valid = sel_raw_literals || sel_rle_literals || sel_huff_literals; + + let (literals_data, state) = if (sel_raw_literals) { + ( + state.raw_literals_data, + LiteralsBufferMuxState { raw_literals_valid: false, ..state } + ) + } else if (sel_rle_literals) { + ( + state.rle_literals_data, + LiteralsBufferMuxState { rle_literals_valid: false, ..state } + ) + } else if (sel_huff_literals) { + ( + state.huff_literals_data, + LiteralsBufferMuxState { huff_literals_valid: false, ..state } + ) + } else { + ( + literals_data, + state + ) + }; + + send_if(tok1, out_literals_s, literals_valid, LiteralsData { + data: literals_data.data, + length: literals_data.length, + last: literals_data.last, + }); + + if (literals_data.literals_last) { + LiteralsBufferMuxState { literals_id: state.literals_id + LitID:1, ..state } + } else { + state + } + } +} + +// Proc responsible for writing received literals to RAMs +proc LiteralsBufferWriter< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, + RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + INIT_HB_PTR_ADDR: u32 = {u32:0}, + INIT_HB_PTR_RAM: u32 = {u32:0}, + INIT_HB_LENGTH: u32 = {u32:0}, + RAM_SIZE_TOTAL: u32 = {RAM_SIZE * RAM_NUM} +> { + type HistoryBufferLength = uN[RAM_ADDR_WIDTH + std::clog2(RAM_NUM)]; + type RamAddr = bits[RAM_ADDR_WIDTH]; + type State = LiteralsBufferWriterState; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + literals_r: chan in; + + ram_comp_input_s: chan> out; + ram_comp_output_r: chan> in; + + buffer_sync_r: chan in; + buffer_sync_s: chan out; + + wr_req_m0_s: chan out; + wr_req_m1_s: chan out; + wr_req_m2_s: chan out; + wr_req_m3_s: chan out; + wr_req_m4_s: chan out; + wr_req_m5_s: chan out; + wr_req_m6_s: chan out; + wr_req_m7_s: chan out; + + config ( + literals_r: chan in, + buffer_sync_r: chan in, + buffer_sync_s: chan out, + wr_req_m0_s: chan out, + wr_req_m1_s: chan out, + wr_req_m2_s: chan out, + wr_req_m3_s: chan out, + wr_req_m4_s: chan out, + wr_req_m5_s: chan out, + wr_req_m6_s: chan out, + wr_req_m7_s: chan out, + wr_resp_m0_r: chan in, + wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, + wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, + wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, + wr_resp_m7_r: chan in + ) { + let (ram_comp_input_s, ram_comp_input_r) = chan, u32:1>("ram_comp_input"); + let (ram_comp_output_s, ram_comp_output_r) = chan, u32:1>("ram_comp_output"); + + spawn parallel_rams::RamWrRespHandler( + ram_comp_input_r, ram_comp_output_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, + wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + ); + + ( + literals_r, + ram_comp_input_s, ram_comp_output_r, + buffer_sync_r, buffer_sync_s, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, + wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + ) + } + + init { + type State = LiteralsBufferWriterState; + let INIT_HB_PTR = HistoryBufferPtr { + number: INIT_HB_PTR_RAM as RamNumber, addr: INIT_HB_PTR_ADDR as RamAddr + }; + + State { + hyp_ptr: INIT_HB_PTR, + hb_len: INIT_HB_LENGTH as uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], + ..zero!() + } + } + next (state: State) { + let tok0 = join(); + // TODO: Remove this workaround when fixed: https://github.com/google/xls/issues/1368 + type State = LiteralsBufferWriterState; + type WriteReq = ram::WriteReq; + + const ZERO_WRITE_REQS = WriteReq[RAM_NUM]:[zero!(), ...]; + const RAM_REQ_MASK_NONE = bits[RAM_NUM_PARTITIONS]:0; + + + // read from sync + let (_, sync_data, sync_data_valid) = recv_non_blocking(tok0, buffer_sync_r, zero!()); + + if (sync_data_valid) { + trace_fmt!("Received buffer reader-to-writer sync data {:#x}", sync_data); + } else {}; + + // read literals + let do_recv_literals = state.hb_len as u32 < HISTORY_BUFFER_SIZE_KB << u32:10; + + let (tok1, literals_data, literals_data_valid) = recv_if_non_blocking(tok0, literals_r, do_recv_literals, zero!()); + + // write literals to RAM + let packet_data = for (i, data): (u32, LiteralsWithLast) in range(u32:0, RAM_NUM) { + let literal = (((literals_data.data >> (common::SYMBOL_WIDTH * i)) as uN[common::SYMBOL_WIDTH]) as LiteralsWithLast) | + ((literals_data.last as LiteralsWithLast) << common::SYMBOL_WIDTH); + data | (literal << (RAM_DATA_WIDTH * i)) + }(LiteralsWithLast:0); + + let packet = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: literals_data.length as CopyOrMatchLength, + content: packet_data, + last: literals_data.last, + }; + let (write_reqs, new_hyp_ptr) = parallel_rams::literal_packet_to_write_reqs< + HISTORY_BUFFER_SIZE_KB, RAM_ADDR_WIDTH, RAM_DATA_WIDTH + >( + state.hyp_ptr, packet + ); + let hb_add = packet.length as HistoryBufferLength; + let new_hb_len = std::mod_pow2(state.hb_len + hb_add, RAM_SIZE_TOTAL as HistoryBufferLength); + + let write_reqs = if (literals_data_valid) { + write_reqs + } else { + ZERO_WRITE_REQS + }; + + // send write requests to RAMs + let tok2_0 = send_if(tok1, wr_req_m0_s, write_reqs[0].mask != RAM_REQ_MASK_NONE, write_reqs[0]); + let tok2_1 = send_if(tok1, wr_req_m1_s, write_reqs[1].mask != RAM_REQ_MASK_NONE, write_reqs[1]); + let tok2_2 = send_if(tok1, wr_req_m2_s, write_reqs[2].mask != RAM_REQ_MASK_NONE, write_reqs[2]); + let tok2_3 = send_if(tok1, wr_req_m3_s, write_reqs[3].mask != RAM_REQ_MASK_NONE, write_reqs[3]); + let tok2_4 = send_if(tok1, wr_req_m4_s, write_reqs[4].mask != RAM_REQ_MASK_NONE, write_reqs[4]); + let tok2_5 = send_if(tok1, wr_req_m5_s, write_reqs[5].mask != RAM_REQ_MASK_NONE, write_reqs[5]); + let tok2_6 = send_if(tok1, wr_req_m6_s, write_reqs[6].mask != RAM_REQ_MASK_NONE, write_reqs[6]); + let tok2_7 = send_if(tok1, wr_req_m7_s, write_reqs[7].mask != RAM_REQ_MASK_NONE, write_reqs[7]); + + let tok2 = join(tok2_0, tok2_1, tok2_2, tok2_3, tok2_4, tok2_5, tok2_6, tok2_7); + + // write completion + let (do_write, wr_resp_handler_data) = parallel_rams::create_ram_wr_data(write_reqs, state.hyp_ptr); + if do_write {trace_fmt!("Sending request to RamWrRespHandler: {:#x}", wr_resp_handler_data);} else { }; + + let tok3_0 = send_if(tok2, ram_comp_input_s, do_write, wr_resp_handler_data); + + let (tok3_1, comp_data, comp_data_valid) = recv_non_blocking(tok2, ram_comp_output_r, zero!()); + + // update state + let state = if (literals_data_valid) { + State { + hyp_ptr: new_hyp_ptr, + hb_len: new_hb_len, + ..state + } + } else { + state + }; + + let state = if (comp_data_valid) { + trace_fmt!("COMP {:#x}", comp_data); + State { + literals_in_ram: state.literals_in_ram + comp_data.length as uN[RAM_ADDR_WIDTH + std::clog2(RAM_NUM)], + ..state + } + } else { + state + }; + + let state = if (sync_data_valid) { + State { + literals_in_ram: state.literals_in_ram - sync_data.literals_read as HistoryBufferLength, + hb_len: state.hb_len - sync_data.literals_read as HistoryBufferLength, + ..state + } + } else { + state + }; + + // send sync + let tok3 = join(tok3_0, tok3_1); + + let sync_data = LiteralsBufferWriterToReaderSync { + literals_written: comp_data.length, + }; + let tok4 = send_if(tok3, buffer_sync_s, comp_data_valid, sync_data); + + if (comp_data_valid) { + trace_fmt!("Sent buffer writer-to-reader sync data {:#x}", sync_data); + } else {}; + + state + } +} + +// Proc responsible for reading requestes literals from RAMs +proc LiteralsBufferReader< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, + RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + INIT_HB_PTR_ADDR: u32 = {u32:0}, + INIT_HB_PTR_RAM: u32 = {u32:0}, + INIT_HB_LENGTH: u32 = {u32:0}, + RAM_SIZE_TOTAL: u32 = {RAM_SIZE * RAM_NUM} +> { + type HistoryBufferLength = uN[RAM_ADDR_WIDTH + std::clog2(RAM_NUM)]; + type RamAddr = bits[RAM_ADDR_WIDTH]; + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type State = LiteralsBufferReaderState; + + literals_buf_ctrl_r: chan in; + literals_s: chan> out; + + ram_resp_input_s: chan out; + + buffer_sync_r: chan in; + + rd_req_m0_s: chan out; + rd_req_m1_s: chan out; + rd_req_m2_s: chan out; + rd_req_m3_s: chan out; + rd_req_m4_s: chan out; + rd_req_m5_s: chan out; + rd_req_m6_s: chan out; + rd_req_m7_s: chan out; + + config ( + literals_buf_ctrl_r: chan in, + literals_s: chan> out, + buffer_sync_r: chan in, + buffer_sync_s: chan out, + rd_req_m0_s: chan out, + rd_req_m1_s: chan out, + rd_req_m2_s: chan out, + rd_req_m3_s: chan out, + rd_req_m4_s: chan out, + rd_req_m5_s: chan out, + rd_req_m6_s: chan out, + rd_req_m7_s: chan out, + rd_resp_m0_r: chan in, + rd_resp_m1_r: chan in, + rd_resp_m2_r: chan in, + rd_resp_m3_r: chan in, + rd_resp_m4_r: chan in, + rd_resp_m5_r: chan in, + rd_resp_m6_r: chan in, + rd_resp_m7_r: chan in, + ) { + let (ram_resp_input_s, ram_resp_input_r) = chan("ram_resp_input"); + let (literals_enc_s, literals_enc_r) = chan, u32:1>("literals_enc"); + + spawn parallel_rams::RamRdRespHandler( + ram_resp_input_r, literals_enc_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, + rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + ); + + spawn PacketDecoder( + literals_enc_r, literals_s, buffer_sync_s + ); + + ( + literals_buf_ctrl_r, + literals_s, + ram_resp_input_s, + buffer_sync_r, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, + rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + ) + } + + init { + type State = LiteralsBufferReaderState; + let INIT_HB_PTR = HistoryBufferPtr { + number: INIT_HB_PTR_RAM as RamNumber, addr: INIT_HB_PTR_ADDR as RamAddr + }; + + State { + hyp_ptr: INIT_HB_PTR, + hb_len: INIT_HB_LENGTH as uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], + ..zero!() + } + } + + next (state: State) { + let tok0 = join(); + // TODO: Remove this workaround when fixed: https://github.com/google/xls/issues/1368 + type ReadReq = ram::ReadReq; + type State = LiteralsBufferReaderState; + + const ZERO_READ_REQS = ReadReq[RAM_NUM]:[zero!(), ...]; + const RAM_REQ_MASK_NONE = bits[RAM_NUM_PARTITIONS]:0; + + // read from ctrl + let (tok1, literals_buf_ctrl, literals_buf_ctrl_valid) = recv_if_non_blocking( + tok0, literals_buf_ctrl_r, state.left_to_read == u32:0, zero!() + ); + let (left_to_read, ctrl_last) = if (literals_buf_ctrl_valid) { + ( + literals_buf_ctrl.length, + literals_buf_ctrl.last + ) + } else { + ( + state.left_to_read, + state.ctrl_last + ) + }; + + // read literals from RAM + // limit read to 8 literals + let literals_to_read = if (left_to_read > (RAM_NUM as u32)) { + RAM_NUM as u32 + } else { + left_to_read + }; + // if there is not enough literals in RAMs, don't read and wait for more literals + let literals_to_read = if (literals_to_read > state.literals_in_ram as u32) { + u32:0 + } else { + literals_to_read + }; + + let packet = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: literals_to_read as CopyOrMatchLength, + content: state.hb_len as LiteralsWithLast, + last: ctrl_last, + }; + + let (read_reqs, read_start, read_len, packet, _) = parallel_rams::sequence_packet_to_read_reqs< + HISTORY_BUFFER_SIZE_KB, RAM_ADDR_WIDTH, RAM_DATA_WIDTH + >( + state.hyp_ptr, packet, state.hb_len + ); + + let (read_reqs, read_start, state) = if (literals_to_read > u32:0) { + ( + read_reqs, + read_start, + State { + hb_len: state.hb_len - literals_to_read as HistoryBufferLength, + literals_in_ram: state.literals_in_ram - literals_to_read as uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH], + left_to_read: left_to_read - literals_to_read, + ctrl_last: ctrl_last, + ..state + }, + ) + } else { + ( + ZERO_READ_REQS, + RamReadStart:0, + State { + left_to_read: left_to_read, + ctrl_last: ctrl_last, + ..state + } + ) + }; + + // read requests + let tok2_0 = send_if(tok1, rd_req_m0_s, read_reqs[0].mask != RAM_REQ_MASK_NONE, read_reqs[0]); + let tok2_1 = send_if(tok1, rd_req_m1_s, read_reqs[1].mask != RAM_REQ_MASK_NONE, read_reqs[1]); + let tok2_2 = send_if(tok1, rd_req_m2_s, read_reqs[2].mask != RAM_REQ_MASK_NONE, read_reqs[2]); + let tok2_3 = send_if(tok1, rd_req_m3_s, read_reqs[3].mask != RAM_REQ_MASK_NONE, read_reqs[3]); + let tok2_4 = send_if(tok1, rd_req_m4_s, read_reqs[4].mask != RAM_REQ_MASK_NONE, read_reqs[4]); + let tok2_5 = send_if(tok1, rd_req_m5_s, read_reqs[5].mask != RAM_REQ_MASK_NONE, read_reqs[5]); + let tok2_6 = send_if(tok1, rd_req_m6_s, read_reqs[6].mask != RAM_REQ_MASK_NONE, read_reqs[6]); + let tok2_7 = send_if(tok1, rd_req_m7_s, read_reqs[7].mask != RAM_REQ_MASK_NONE, read_reqs[7]); + + let tok2 = join(tok2_0, tok2_1, tok2_2, tok2_3, tok2_4, tok2_5, tok2_6, tok2_7); + let last_access = if (state.left_to_read > u32:0) { + false + } else { + state.ctrl_last + }; + + let (do_read, rd_resp_handler_data) = + parallel_rams::create_ram_rd_data( + read_reqs, read_start, read_len, last_access, !last_access + ); + if do_read { + trace_fmt!("Sending request to RamRdRespHandler: {:#x}", rd_resp_handler_data); + } else { }; + let tok3 = send_if(tok2, ram_resp_input_s, do_read, rd_resp_handler_data); + + // read from sync + let (_, sync_data, sync_data_valid) = recv_non_blocking(tok0, buffer_sync_r, zero!()); + + if (sync_data_valid) { + trace_fmt!("Received buffer writer-to-reader sync data {:#x}", sync_data); + } else {}; + + let state = if (sync_data_valid) { + State { + hyp_ptr: parallel_rams::hb_ptr_from_offset_forw( + state.hyp_ptr, sync_data.literals_written as parallel_rams::Offset + ), + hb_len: state.hb_len + sync_data.literals_written as HistoryBufferLength, + literals_in_ram: state.literals_in_ram + sync_data.literals_written as uN[RAM_ADDR_WIDTH + std::clog2(RAM_NUM)], + ..state + } + } else { + state + }; + + state + } +} + +pub proc LiteralsBuffer< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, + RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + INIT_HB_PTR_ADDR: u32 = {u32:0}, + INIT_HB_PTR_RAM: u32 = {u32:0}, + INIT_HB_LENGTH: u32 = {u32:0}, + RAM_SIZE_TOTAL: u32 = {RAM_SIZE * RAM_NUM} +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + init { } + + config ( + raw_literals_r: chan in, + rle_literals_r: chan in, + huff_literals_r: chan in, + literals_buf_ctrl_r: chan in, + literals_s: chan> out, + rd_req_m0_s: chan out, + rd_req_m1_s: chan out, + rd_req_m2_s: chan out, + rd_req_m3_s: chan out, + rd_req_m4_s: chan out, + rd_req_m5_s: chan out, + rd_req_m6_s: chan out, + rd_req_m7_s: chan out, + rd_resp_m0_r: chan in, + rd_resp_m1_r: chan in, + rd_resp_m2_r: chan in, + rd_resp_m3_r: chan in, + rd_resp_m4_r: chan in, + rd_resp_m5_r: chan in, + rd_resp_m6_r: chan in, + rd_resp_m7_r: chan in, + wr_req_m0_s: chan out, + wr_req_m1_s: chan out, + wr_req_m2_s: chan out, + wr_req_m3_s: chan out, + wr_req_m4_s: chan out, + wr_req_m5_s: chan out, + wr_req_m6_s: chan out, + wr_req_m7_s: chan out, + wr_resp_m0_r: chan in, + wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, + wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, + wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, + wr_resp_m7_r: chan in + ) { + type SyncWriterToReader = LiteralsBufferWriterToReaderSync; + type SyncReaderToWriter = LiteralsBufferReaderToWriterSync; + + let (buffer_sync_writer_to_reader_s, buffer_sync_writer_to_reader_r) = chan("buffer_sync_writer_to_reader"); + let (buffer_sync_reader_to_writer_s, buffer_sync_reader_to_writer_r) = chan("buffer_sync_reader_to_writer"); + let (sync_literals_s, sync_literals_r) = chan("sync_literals"); + + spawn LiteralsBufferMux ( + raw_literals_r, rle_literals_r, huff_literals_r, + sync_literals_s + ); + + spawn LiteralsBufferWriter< + HISTORY_BUFFER_SIZE_KB, RAM_SIZE, RAM_ADDR_WIDTH, INIT_HB_PTR_ADDR, INIT_HB_PTR_RAM, INIT_HB_LENGTH, RAM_SIZE_TOTAL + > ( + sync_literals_r, + buffer_sync_reader_to_writer_r, buffer_sync_writer_to_reader_s, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, + wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, + wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + ); + + spawn LiteralsBufferReader< + HISTORY_BUFFER_SIZE_KB, RAM_SIZE, RAM_ADDR_WIDTH, INIT_HB_PTR_ADDR, INIT_HB_PTR_RAM, INIT_HB_LENGTH, RAM_SIZE_TOTAL + > ( + literals_buf_ctrl_r, literals_s, + buffer_sync_writer_to_reader_r, buffer_sync_reader_to_writer_s, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, + rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, + rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + ); + } + + next (state: ()) { } +} + +const INST_HISTORY_BUFFER_SIZE_KB = u32:64; +const INST_RAM_ADDR_WIDTH = parallel_rams::ram_addr_width(INST_HISTORY_BUFFER_SIZE_KB); +const INST_RAM_NUM_PARTITIONS = RAM_NUM_PARTITIONS; +const INST_RAM_DATA_WIDTH = RAM_DATA_WIDTH; +const INST_SYMBOL_WIDTH = common::SYMBOL_WIDTH; + +pub proc LiteralsBufferInst { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + init { } + + config ( + raw_literals_r: chan in, + rle_literals_r: chan in, + huff_literals_r: chan in, + literals_buf_ctrl_r: chan in, + literals_s: chan> out, + rd_req_m0_s: chan out, + rd_req_m1_s: chan out, + rd_req_m2_s: chan out, + rd_req_m3_s: chan out, + rd_req_m4_s: chan out, + rd_req_m5_s: chan out, + rd_req_m6_s: chan out, + rd_req_m7_s: chan out, + rd_resp_m0_r: chan in, + rd_resp_m1_r: chan in, + rd_resp_m2_r: chan in, + rd_resp_m3_r: chan in, + rd_resp_m4_r: chan in, + rd_resp_m5_r: chan in, + rd_resp_m6_r: chan in, + rd_resp_m7_r: chan in, + wr_req_m0_s: chan out, + wr_req_m1_s: chan out, + wr_req_m2_s: chan out, + wr_req_m3_s: chan out, + wr_req_m4_s: chan out, + wr_req_m5_s: chan out, + wr_req_m6_s: chan out, + wr_req_m7_s: chan out, + wr_resp_m0_r: chan in, + wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, + wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, + wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, + wr_resp_m7_r: chan in + ) { + spawn LiteralsBuffer ( + raw_literals_r, rle_literals_r, huff_literals_r, + literals_buf_ctrl_r, literals_s, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, + rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, + rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, + wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, + wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + ); + } + + next (state: ()) { } +} + +enum LiteralsChannel: u2 { + RAW = 0, + RLE = 1, + HUFF = 2, +} + +const TEST_LITERALS_DATA: (LiteralsChannel, LiteralsDataWithSync)[9] = [ + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x12_3456_789A, length: LitLength:5, last: false, id: LitID:0, literals_last: true}), + (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xBBBB_BBBB, length: LitLength:4, last: false, id: LitID:1, literals_last: true}), + (LiteralsChannel::HUFF, LiteralsDataWithSync {data: LitData:0x64, length: LitLength:1, last: false, id: LitID:2, literals_last: true}), + (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xABCD_DCBA_1234_4321, length: LitLength:8, last: false, id: LitID:3, literals_last: true}), + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x21_4365, length: LitLength:3, last: false, id: LitID:4, literals_last: true}), + (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xAA_BBBB_CCCC_DDDD, length: LitLength:7, last: false, id: LitID:5, literals_last: true}), + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0xDCBA_ABCD_1234_4321, length: LitLength:8, last: false, id: LitID:6, literals_last: false}), + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x78, length: LitLength:1, last: false, id: LitID:6, literals_last: true}), + (LiteralsChannel::HUFF, LiteralsDataWithSync {data: LitData:0x26, length: LitLength:1, last: true, id: LitID:7, literals_last: true}), +]; + +const TEST_BUFFER_CTRL: LiteralsBufferCtrl[6] = [ + LiteralsBufferCtrl {length: u32:2, last: false}, + LiteralsBufferCtrl {length: u32:1, last: false}, + LiteralsBufferCtrl {length: u32:13, last: false}, + LiteralsBufferCtrl {length: u32:8, last: false}, + LiteralsBufferCtrl {length: u32:4, last: false}, + LiteralsBufferCtrl {length: u32:10, last: true}, +]; + +const TEST_EXPECTED_PACKETS: SequenceExecutorPacket[8] = [ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:2, + content: CopyOrMatchContent:0x789A, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0x56, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x2164_BBBB_BBBB_1234, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:5, + content: CopyOrMatchContent:0xDC_BA12_3443, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xCCDD_DD21_4365_ABCD, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0xAABB_BBCC, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xDCBA_ABCD_1234_4321, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:2, + content: CopyOrMatchContent:0x2678, + last: true + }, +]; + +#[test_proc] +proc LiteralsBuffer_test { + terminator: chan out; + + raw_literals_s: chan out; + rle_literals_s: chan out; + huff_literals_s: chan out; + + literals_buf_ctrl_s: chan out; + literals_r: chan> in; + + print_start_s: chan<()> out; + print_finish_r: chan<()> in; + + ram_rd_req_s: chan[RAM_NUM] out; + ram_rd_resp_r: chan[RAM_NUM] in; + ram_wr_req_s: chan[RAM_NUM] out; + ram_wr_resp_r: chan[RAM_NUM] in; + + config(terminator: chan out) { + let (raw_literals_s, raw_literals_r) = chan("raw_literals"); + let (rle_literals_s, rle_literals_r) = chan("rle_literals"); + let (huff_literals_s, huff_literals_r) = chan("huff_literals"); + + let (literals_buf_ctrl_s, literals_buf_ctrl_r) = chan("literals_buf_ctrl"); + let (literals_s, literals_r) = chan>("literals"); + + let (print_start_s, print_start_r) = chan<()>("print_start"); + let (print_finish_s, print_finish_r) = chan<()>("print_finish"); + + let (ram_rd_req_s, ram_rd_req_r) = chan[RAM_NUM]("ram_rd_req"); + let (ram_rd_resp_s, ram_rd_resp_r) = chan[RAM_NUM]("ram_rd_resp"); + let (ram_wr_req_s, ram_wr_req_r) = chan[RAM_NUM]("ram_wr_req"); + let (ram_wr_resp_s, ram_wr_resp_r) = chan[RAM_NUM]("ram_wr_resp"); + + spawn LiteralsBuffer< + TEST_HISTORY_BUFFER_SIZE_KB, + TEST_RAM_SIZE, + TEST_RAM_ADDR_WIDTH, + TEST_INIT_HB_PTR_ADDR + > ( + raw_literals_r, rle_literals_r, huff_literals_r, + literals_buf_ctrl_r, literals_s, + ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], + ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], + ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], + ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], + ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], + ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], + ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], + ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7] + ); + spawn ram_printer::RamPrinter< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_NUM_PARTITIONS, + TEST_RAM_ADDR_WIDTH, RAM_NUM> + (print_start_r, print_finish_s, ram_rd_req_s, ram_rd_resp_r); + + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); + spawn ram::RamModel< + RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); + + ( + terminator, + raw_literals_s, rle_literals_s, huff_literals_s, + literals_buf_ctrl_s, literals_r, + print_start_s, print_finish_r, + ram_rd_req_s, ram_rd_resp_r, + ram_wr_req_s, ram_wr_resp_r, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + // send literals + let tok = for ((i, test_literals_data), tok): ((u32, (LiteralsChannel, LiteralsDataWithSync)), token) in enumerate(TEST_LITERALS_DATA) { + let literals_channel_s = match test_literals_data.0 { + LiteralsChannel::RAW => raw_literals_s, + LiteralsChannel::RLE => rle_literals_s, + LiteralsChannel::HUFF => huff_literals_s, + }; + let tok = send(tok, literals_channel_s, test_literals_data.1); + trace_fmt!("Sent #{} literals {:#x} to channel {}", i + u32:1, test_literals_data.1, test_literals_data.0); + tok + }(tok); + + // send ctrl + let tok = for ((i, test_buf_ctrl), tok): ((u32, LiteralsBufferCtrl), token) in enumerate(TEST_BUFFER_CTRL) { + let tok = send(tok, literals_buf_ctrl_s, test_buf_ctrl); + trace_fmt!("Send #{} ctrl {:#x}", i + u32:1, test_buf_ctrl); + tok + }(tok); + + // receive and check packets + let tok = for ((i, test_exp_literals), tok): ((u32, SequenceExecutorPacket), token) in enumerate(TEST_EXPECTED_PACKETS) { + let (tok, literals) = recv(tok, literals_r); + trace_fmt!("Received #{} literals packet {:#x}", i + u32:1, literals); + assert_eq(test_exp_literals, literals); + tok + }(tok); + + // print RAM content + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/literals_decoder.x b/xls/modules/zstd/literals_decoder.x new file mode 100644 index 0000000000..24c0a05d2e --- /dev/null +++ b/xls/modules/zstd/literals_decoder.x @@ -0,0 +1,709 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of LiteralsDecoder. + +import std; + +import xls.examples.ram; +import xls.modules.zstd.common as common; +import xls.modules.zstd.literals_buffer as literals_buffer; +import xls.modules.zstd.literals_dispatcher as literals_dispatcher; +import xls.modules.zstd.parallel_rams as parallel_rams; +import xls.modules.zstd.ram_printer as ram_printer; +import xls.modules.zstd.raw_literals_dec as raw_literals_dec; +import xls.modules.zstd.rle_literals_dec as rle_literals_dec; + +type CopyOrMatchContent = common::CopyOrMatchContent; +type CopyOrMatchLength = common::CopyOrMatchLength; +type LitData = common::LitData; +type LitLength = common::LitLength; +type LiteralType = common::LiteralType; +type LiteralsBufferCtrl = common::LiteralsBufferCtrl; +type LiteralsData = common::LiteralsData; +type LiteralsDataWithSync = common::LiteralsDataWithSync; +type LiteralsPathCtrl = common::LiteralsPathCtrl; +type RleLiteralsData = common::RleLiteralsData; +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; +type SequenceExecutorPacket = common::SequenceExecutorPacket; +type Streams = common::Streams; + +proc LiteralsDecoder< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, + RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + literals_ctrl_r: chan in; + literals_data_r: chan in; + literals_buf_ctrl_r: chan in; + literals_s: chan out; + + config ( + literals_ctrl_r: chan in, + literals_data_r: chan in, + literals_buf_ctrl_r: chan in, + literals_s: chan out, + rd_req_m0_s: chan out, + rd_req_m1_s: chan out, + rd_req_m2_s: chan out, + rd_req_m3_s: chan out, + rd_req_m4_s: chan out, + rd_req_m5_s: chan out, + rd_req_m6_s: chan out, + rd_req_m7_s: chan out, + rd_resp_m0_r: chan in, + rd_resp_m1_r: chan in, + rd_resp_m2_r: chan in, + rd_resp_m3_r: chan in, + rd_resp_m4_r: chan in, + rd_resp_m5_r: chan in, + rd_resp_m6_r: chan in, + rd_resp_m7_r: chan in, + wr_req_m0_s: chan out, + wr_req_m1_s: chan out, + wr_req_m2_s: chan out, + wr_req_m3_s: chan out, + wr_req_m4_s: chan out, + wr_req_m5_s: chan out, + wr_req_m6_s: chan out, + wr_req_m7_s: chan out, + wr_resp_m0_r: chan in, + wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, + wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, + wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, + wr_resp_m7_r: chan in + ) { + let (raw_literals_s, raw_literals_r) = chan("raw_literals"); + let (rle_literals_s, rle_literals_r) = chan("rle_literals"); + let (huff_literals_s, huff_literals_r) = chan("huff_literals"); + + let (decoded_raw_literals_s, decoded_raw_literals_r) = chan("decoded_raw_literals"); + let (decoded_rle_literals_s, decoded_rle_literals_r) = chan("decoded_rle_literals"); + + spawn literals_dispatcher::LiteralsDispatcher( + literals_ctrl_r, literals_data_r, + raw_literals_s, rle_literals_s, huff_literals_s, + ); + + spawn raw_literals_dec::RawLiteralsDecoder(raw_literals_r, decoded_raw_literals_s); + + spawn rle_literals_dec::RleLiteralsDecoder(rle_literals_r, decoded_rle_literals_s); + + spawn literals_buffer::LiteralsBuffer ( + decoded_raw_literals_r, decoded_rle_literals_r, huff_literals_r, + literals_buf_ctrl_r, literals_s, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, + rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, + rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, + wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, + wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + ); + + ( + literals_ctrl_r, literals_data_r, + literals_buf_ctrl_r, literals_s, + ) + } + + init { } + + next (state: ()) { } +} + +const ZSTD_HISTORY_BUFFER_SIZE_KB: u32 = u32:64; +const ZSTD_RAM_ADDR_WIDTH: u32 = parallel_rams::ram_addr_width(ZSTD_HISTORY_BUFFER_SIZE_KB); + +proc LiteralsDecoderInst { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + config ( + literals_ctrl_r: chan in, + literals_data_r: chan in, + literals_buf_ctrl_r: chan in, + literals_s: chan out, + rd_req_m0_s: chan out, + rd_req_m1_s: chan out, + rd_req_m2_s: chan out, + rd_req_m3_s: chan out, + rd_req_m4_s: chan out, + rd_req_m5_s: chan out, + rd_req_m6_s: chan out, + rd_req_m7_s: chan out, + rd_resp_m0_r: chan in, + rd_resp_m1_r: chan in, + rd_resp_m2_r: chan in, + rd_resp_m3_r: chan in, + rd_resp_m4_r: chan in, + rd_resp_m5_r: chan in, + rd_resp_m6_r: chan in, + rd_resp_m7_r: chan in, + wr_req_m0_s: chan out, + wr_req_m1_s: chan out, + wr_req_m2_s: chan out, + wr_req_m3_s: chan out, + wr_req_m4_s: chan out, + wr_req_m5_s: chan out, + wr_req_m6_s: chan out, + wr_req_m7_s: chan out, + wr_resp_m0_r: chan in, + wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, + wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, + wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, + wr_resp_m7_r: chan in + ) { + spawn LiteralsDecoder ( + literals_ctrl_r, literals_data_r, + literals_buf_ctrl_r, literals_s, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, + rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, + rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, + wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, + wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + ); + } + + init {} + + next (state: ()) {} +} + +// RAM related constants common for tests +const TEST_HISTORY_BUFFER_SIZE_KB = u32:1; +const TEST_RAM_SIZE = parallel_rams::ram_size(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_RAM_ADDR_WIDTH = parallel_rams::ram_addr_width(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_RAM_INITIALIZED = true; +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; + +type TestRamAddr = bits[TEST_RAM_ADDR_WIDTH]; +type TestWriteReq = ram::WriteReq; +type TestWriteResp = ram::WriteResp; +type TestReadReq = ram::ReadReq; +type TestReadResp = ram::ReadResp; + +const TEST_CTRL: LiteralsPathCtrl[7] = [ + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:8, literals_type: LiteralType::RAW}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:4, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:2, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:15, literals_type: LiteralType::RAW}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:12, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:0, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:31, literals_type: LiteralType::RAW}, +]; + +const TEST_DATA: LiteralsData[11] = [ + // 0. RAW + LiteralsData {data: LitData:0x1657_3465_A6DB_5DB0, length: LitLength:8, last: false}, + // 1. RLE + LiteralsData {data: LitData:0x23, length: LitLength:1, last: false}, + // 2. RLE + LiteralsData {data: LitData:0x35, length: LitLength:1, last: false}, + // 3. RAW + LiteralsData {data: LitData:0x4CFB_41C6_7B60_5370, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0x009B_0F9C_E1BA_A96D, length: LitLength:7, last: true}, + // 4. RLE + LiteralsData {data: LitData:0x5A, length: LitLength:1, last: false}, + // 5. RLE + LiteralsData {data: LitData:0xFF, length: LitLength:1, last: false}, + // 6. RAW + LiteralsData {data: LitData:0x6094_3E96_1834_C247, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0xBC02_D0E8_D728_9ABE, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0xF864_C38B_E1FA_8D12, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0x0019_63F1_CE21_C294, length: LitLength:7, last: true}, +]; + +const TEST_BUF_CTRL: LiteralsBufferCtrl[5] = [ + LiteralsBufferCtrl {length: u32:11, last: false}, + LiteralsBufferCtrl {length: u32:2, last: false}, + LiteralsBufferCtrl {length: u32:16, last: true}, + LiteralsBufferCtrl {length: u32:11, last: false}, + LiteralsBufferCtrl {length: u32:32, last: true}, +]; + +const TEST_EXPECTED_LITERALS: SequenceExecutorPacket[11] = [ + // ctrl 0 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x1657_3465_A6DB_5DB0, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:3, + content: CopyOrMatchContent:0x23_2323, + last: false + }, + // ctrl 1 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:2, + content: CopyOrMatchContent:0x35_23, + last: false + }, + // ctrl 2 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xFB41_C67B_6053_7035, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x9B0F_9CE1_BAA9_6D4C, + last: true + }, + // ctrl 3 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x5A5A_5A5A_5A5A_5A5A, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:3, + content: CopyOrMatchContent:0x5A_5A5A, + last: false + }, + // ctrl 4 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x943E_9618_34C2_475A, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x02D0_E8D7_289A_BE60, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x64C3_8BE1_FA8D_12BC, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x1963_F1CE_21C2_94F8, + last: true + }, +]; + +#[test_proc] +proc LiteralsDecoder_test { + terminator: chan out; + + literals_ctrl_s: chan out; + literals_data_s: chan out; + literals_buf_ctrl_s: chan out; + literals_r: chan in; + + print_start_s: chan<()> out; + print_finish_r: chan<()> in; + + config (terminator: chan out) { + let (literals_ctrl_s, literals_ctrl_r) = chan("literals_ctrl"); + let (literals_data_s, literals_data_r) = chan("literals_data"); + let (literals_buf_ctrl_s, literals_buf_ctrl_r) = chan("literals_buf_ctrl"); + let (literals_s, literals_r) = chan("literals"); + + let (print_start_s, print_start_r) = chan<()>("print_start"); + let (print_finish_s, print_finish_r) = chan<()>("print_finish"); + + let (ram_rd_req_s, ram_rd_req_r) = chan[literals_buffer::RAM_NUM]("ram_rd_req"); + let (ram_rd_resp_s, ram_rd_resp_r) = chan[literals_buffer::RAM_NUM]("ram_rd_resp"); + let (ram_wr_req_s, ram_wr_req_r) = chan[literals_buffer::RAM_NUM]("ram_wr_req"); + let (ram_wr_resp_s, ram_wr_resp_r) = chan[literals_buffer::RAM_NUM]("ram_wr_resp"); + + spawn LiteralsDecoder( + literals_ctrl_r, literals_data_r, + literals_buf_ctrl_r, literals_s, + ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], + ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], + ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], + ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], + ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], + ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], + ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], + ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7] + ); + + spawn ram_printer::RamPrinter< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_NUM_PARTITIONS, + TEST_RAM_ADDR_WIDTH, literals_buffer::RAM_NUM> + (print_start_r, print_finish_s, ram_rd_req_s, ram_rd_resp_r); + + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); + spawn ram::RamModel< + literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> + (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); + + ( + terminator, + literals_ctrl_s, literals_data_s, + literals_buf_ctrl_s, literals_r, + print_start_s, print_finish_r, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + // send literals + let tok = for ((i, test_data), tok): ((u32, LiteralsData), token) in enumerate(TEST_DATA) { + let tok = send(tok, literals_data_s, test_data); + trace_fmt!("Sent #{} literals data, {:#x}", i + u32:1, test_data); + tok + }(tok); + + // send ctrl + let tok = for ((i, test_ctrl), tok): ((u32, LiteralsPathCtrl), token) in enumerate(TEST_CTRL) { + let tok = send(tok, literals_ctrl_s, test_ctrl); + trace_fmt!("Sent #{} literals ctrl, {:#x}", i + u32:1, test_ctrl); + tok + }(tok); + + // send buffer ctrl + let tok = for ((i, test_buf_ctrl), tok): ((u32, LiteralsBufferCtrl), token) in enumerate(TEST_BUF_CTRL) { + let tok = send(tok, literals_buf_ctrl_s, test_buf_ctrl); + trace_fmt!("Sent #{} ctrl {:#x}", i + u32:1, test_buf_ctrl); + tok + }(tok); + + // receive and check packets + let tok = for ((i, test_exp_literals), tok): ((u32, SequenceExecutorPacket), token) in enumerate(TEST_EXPECTED_LITERALS) { + let (tok, literals) = recv(tok, literals_r); + trace_fmt!("Received #{} literals packet {:#x}", i + u32:1, literals); + assert_eq(test_exp_literals, literals); + tok + }(tok); + + // print RAM content + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + send(tok, terminator, true); + } +} + +// TODO: Uncomment this test when fixed: https://github.com/google/xls/issues/1502 +// type RamData = uN[literals_buffer::RAM_DATA_WIDTH]; + +// // Expected RAM content after each ctrl +// const TEST_EXPECTED_RAM_CONTENT = RamData[literals_buffer::RAM_NUM][10][7]:[ +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData:0x023, RamData:0x023, RamData:0x023, RamData:0x023], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData: 0x0, RamData: 0x0, RamData:0x035, RamData:0x035, RamData:0x023, RamData:0x023, RamData:0x023, RamData:0x023], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData:0x053, RamData:0x070, RamData:0x035, RamData:0x035, RamData:0x023, RamData:0x023, RamData:0x023, RamData:0x023], +// [RamData:0x1a9, RamData:0x16d, RamData:0x04c, RamData:0x0fb, RamData:0x041, RamData:0x0c6, RamData:0x07b, RamData:0x060], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData:0x19b, RamData:0x10f, RamData:0x19c, RamData:0x1e1, RamData:0x1ba], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData:0x053, RamData:0x070, RamData:0x035, RamData:0x035, RamData:0x023, RamData:0x023, RamData:0x023, RamData:0x023], +// [RamData:0x1a9, RamData:0x16d, RamData:0x04c, RamData:0x0fb, RamData:0x041, RamData:0x0c6, RamData:0x07b, RamData:0x060], +// [RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x19b, RamData:0x10f, RamData:0x19c, RamData:0x1e1, RamData:0x1ba], +// [RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData:0x05a], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData:0x053, RamData:0x070, RamData:0x035, RamData:0x035, RamData:0x023, RamData:0x023, RamData:0x023, RamData:0x023], +// [RamData:0x1a9, RamData:0x16d, RamData:0x04c, RamData:0x0fb, RamData:0x041, RamData:0x0c6, RamData:0x07b, RamData:0x060], +// [RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x19b, RamData:0x10f, RamData:0x19c, RamData:0x1e1, RamData:0x1ba], +// [RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData:0x05a], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// [ +// [RamData:0x016, RamData:0x057, RamData:0x034, RamData:0x065, RamData:0x0a6, RamData:0x0db, RamData:0x05d, RamData:0x0b0], +// [RamData:0x053, RamData:0x070, RamData:0x035, RamData:0x035, RamData:0x023, RamData:0x023, RamData:0x023, RamData:0x023], +// [RamData:0x1a9, RamData:0x16d, RamData:0x04c, RamData:0x0fb, RamData:0x041, RamData:0x0c6, RamData:0x07b, RamData:0x060], +// [RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x19b, RamData:0x10f, RamData:0x19c, RamData:0x1e1, RamData:0x1ba], +// [RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a, RamData:0x05a], +// [RamData:0x094, RamData:0x03e, RamData:0x096, RamData:0x018, RamData:0x034, RamData:0x0c2, RamData:0x047, RamData:0x05a], +// [RamData:0x002, RamData:0x0d0, RamData:0x0e8, RamData:0x0d7, RamData:0x028, RamData:0x09a, RamData:0x0be, RamData:0x060], +// [RamData:0x064, RamData:0x0c3, RamData:0x08b, RamData:0x0e1, RamData:0x0fa, RamData:0x08d, RamData:0x012, RamData:0x0bc], +// [RamData:0x119, RamData:0x163, RamData:0x1f1, RamData:0x1ce, RamData:0x121, RamData:0x1c2, RamData:0x194, RamData:0x0f8], +// [RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0, RamData: 0x0], +// ], +// ]; + +// const CYCLES_PER_RAM_READ = u32:16; + +// #[test_proc] +// proc LiteralsDecoderRamContent_test { +// terminator: chan out; + +// literals_ctrl_s: chan out; +// literals_data_s: chan out; +// literals_buf_ctrl_s: chan out; +// literals_r: chan in; + +// ram_rd_req_m0_s: chan out; +// ram_rd_req_m1_s: chan out; +// ram_rd_req_m2_s: chan out; +// ram_rd_req_m3_s: chan out; +// ram_rd_req_m4_s: chan out; +// ram_rd_req_m5_s: chan out; +// ram_rd_req_m6_s: chan out; +// ram_rd_req_m7_s: chan out; + +// ram_rd_resp_m0_r: chan in; +// ram_rd_resp_m1_r: chan in; +// ram_rd_resp_m2_r: chan in; +// ram_rd_resp_m3_r: chan in; +// ram_rd_resp_m4_r: chan in; +// ram_rd_resp_m5_r: chan in; +// ram_rd_resp_m6_r: chan in; +// ram_rd_resp_m7_r: chan in; + +// config (terminator: chan out) { +// let (literals_ctrl_s, literals_ctrl_r) = chan("literals_ctrl"); +// let (literals_data_s, literals_data_r) = chan("literals_data"); +// let (literals_buf_ctrl_s, literals_buf_ctrl_r) = chan("literals_buf_ctrl"); +// let (literals_s, literals_r) = chan("literals"); + +// let (ram_rd_req_s, ram_rd_req_r) = chan[literals_buffer::RAM_NUM]("ram_rd_req"); +// let (ram_rd_resp_s, ram_rd_resp_r) = chan[literals_buffer::RAM_NUM]("ram_rd_resp"); +// let (ram_wr_req_s, ram_wr_req_r) = chan[literals_buffer::RAM_NUM]("ram_wr_req"); +// let (ram_wr_resp_s, ram_wr_resp_r) = chan[literals_buffer::RAM_NUM]("ram_wr_resp"); + +// spawn LiteralsDecoder( +// literals_ctrl_r, literals_data_r, +// literals_buf_ctrl_r, literals_s, +// ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], +// ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], +// ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], +// ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], +// ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], +// ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], +// ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], +// ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7] +// ); + +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); +// spawn ram::RamModel< +// literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); + +// ( +// terminator, +// literals_ctrl_s, literals_data_s, +// literals_buf_ctrl_s, literals_r, +// ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], +// ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], +// ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], +// ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], +// ) +// } + +// init { u32:0 } + +// next (state: u32) { +// // send literals +// let ok = if (state == u32:0) { +// for ((i, test_data), tok): ((u32, LiteralsData), token) in enumerate(TEST_DATA) { +// let tok = send(tok, literals_data_s, test_data); +// trace_fmt!("Sent #{} literals data, {:#x}", i + u32:1, test_data); +// tok +// }(tok) +// } else { tok }; + +// // send ctrl and read RAM content +// let tok = for ((i, test_ctrl), tok): ((u32, LiteralsPathCtrl), token) in enumerate(TEST_CTRL) { +// if (state == i * CYCLES_PER_RAM_READ) { +// let tok = send(tok, literals_ctrl_s, test_ctrl); +// trace_fmt!("Sent #{} literals ctrl, {:#x}", i + u32:1, test_ctrl); +// tok +// } else if (state == (i + u32:1) * CYCLES_PER_RAM_READ - u32:1) { +// for (addr, tok): (u32, token) in range(u32:0, u32:10) { +// let read_req = TestReadReq { +// addr: addr as uN[TEST_RAM_ADDR_WIDTH], +// mask: u1:1 +// }; + +// let tok = send(tok, ram_rd_req_m0_s, read_req); +// let tok = send(tok, ram_rd_req_m1_s, read_req); +// let tok = send(tok, ram_rd_req_m2_s, read_req); +// let tok = send(tok, ram_rd_req_m3_s, read_req); +// let tok = send(tok, ram_rd_req_m4_s, read_req); +// let tok = send(tok, ram_rd_req_m5_s, read_req); +// let tok = send(tok, ram_rd_req_m6_s, read_req); +// let tok = send(tok, ram_rd_req_m7_s, read_req); + +// let (tok, ram_rd_resp_m0) = recv(tok, ram_rd_resp_m0_r); +// let (tok, ram_rd_resp_m1) = recv(tok, ram_rd_resp_m1_r); +// let (tok, ram_rd_resp_m2) = recv(tok, ram_rd_resp_m2_r); +// let (tok, ram_rd_resp_m3) = recv(tok, ram_rd_resp_m3_r); +// let (tok, ram_rd_resp_m4) = recv(tok, ram_rd_resp_m4_r); +// let (tok, ram_rd_resp_m5) = recv(tok, ram_rd_resp_m5_r); +// let (tok, ram_rd_resp_m6) = recv(tok, ram_rd_resp_m6_r); +// let (tok, ram_rd_resp_m7) = recv(tok, ram_rd_resp_m7_r); +// trace_fmt!( +// "Received RAM read responses: [{:#x}, {:#x}, {:#x}, {:#x}, {:#x}, {:#x}, {:#x}, {:#x}]", +// ram_rd_resp_m7.data, ram_rd_resp_m6.data, ram_rd_resp_m5.data, ram_rd_resp_m4.data, +// ram_rd_resp_m3.data, ram_rd_resp_m2.data, ram_rd_resp_m1.data, ram_rd_resp_m0.data, +// ); + +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][7], ram_rd_resp_m0.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][6], ram_rd_resp_m1.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][5], ram_rd_resp_m2.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][4], ram_rd_resp_m3.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][3], ram_rd_resp_m4.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][2], ram_rd_resp_m5.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][1], ram_rd_resp_m6.data); +// assert_eq(TEST_EXPECTED_RAM_CONTENT[i][addr][0], ram_rd_resp_m7.data); + +// tok +// }(tok) +// } else { +// tok +// } +// }(tok); + +// send_if(tok, terminator, state == array_size(TEST_CTRL) * CYCLES_PER_RAM_READ, true); + +// state + u32:1 +// } +// } diff --git a/xls/modules/zstd/literals_dispatcher.x b/xls/modules/zstd/literals_dispatcher.x new file mode 100644 index 0000000000..39fe949321 --- /dev/null +++ b/xls/modules/zstd/literals_dispatcher.x @@ -0,0 +1,243 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of LiteralsDispatcher responsible for +// dispatching ZSTD Literals. More information about Literals' format can be found in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.1 + +import xls.modules.zstd.common; + +type LiteralsPathCtrl = common::LiteralsPathCtrl; +type LiteralsData = common::LiteralsData; +type LiteralsDataWithSync = common::LiteralsDataWithSync; +type RleLiteralsData = common::RleLiteralsData; +type LiteralType = common::LiteralType; +type Streams = common::Streams; +type DecompressedSize = common::DecompressedSize; + +type RleLitData = common::RleLitData; +type RleLitRepeat = common::RleLitRepeat; +type LitData = common::LitData; +type LitLength = common::LitLength; +type LitID = common::LitID; + +struct LiteralsDispatcherState { + // literals type received from ctrl channel + literals_type: LiteralType, + // number of literals to be read. The initial value is received + // from ctrl channel and decreased after each read from literals channel + left_to_read: DecompressedSize, + literals_id: LitID, +} + +pub proc LiteralsDispatcher { + literals_ctrl_r: chan in; + literals_data_r: chan in; + raw_literals_s: chan out; + rle_literals_s: chan out; + huff_literals_s: chan out; + + config ( + literals_ctrl_r: chan in, + literals_data_r: chan in, + raw_literals_s: chan out, + rle_literals_s: chan out, + huff_literals_s: chan out, + ) { + ( + literals_ctrl_r, + literals_data_r, + raw_literals_s, + rle_literals_s, + huff_literals_s, + ) + } + + init { zero!() } + + next(state: LiteralsDispatcherState ) { + + let tok = join(); + let do_recv_ctrl = (state.left_to_read == DecompressedSize:0); + let (tok, literals_path_ctrl) = recv_if(tok, literals_ctrl_r, do_recv_ctrl, zero!()); + + let (literals_type, left_to_read) = if do_recv_ctrl { + (literals_path_ctrl.literals_type, literals_path_ctrl.decompressed_size) + } else { + (state.literals_type, state.left_to_read) + }; + + // RLE literals consist of single byte + let (tok, literals_data) = recv(tok, literals_data_r); + + let is_empty = left_to_read == DecompressedSize:0 && !literals_data.last; + + let left_to_read = if (literals_type == LiteralType::RLE) { + DecompressedSize:0 + } else { + left_to_read - (literals_data.length as DecompressedSize) + }; + + let literals_data = LiteralsDataWithSync { + data: literals_data.data, + length: literals_data.length, + last: literals_data.last, + id: state.literals_id, + literals_last: true + }; + + let tok = send_if(tok, raw_literals_s, LiteralType::RAW == literals_type, literals_data); + + let rle_literals_data = RleLiteralsData { + data: (literals_data.data as u8), + repeat: literals_path_ctrl.decompressed_size, + id: if (is_empty) { LitID:0 } else { literals_data.id }, + last: literals_data.last, + }; + let tok = send_if(tok, rle_literals_s, LiteralType::RLE == literals_type, rle_literals_data); + + let do_send_huff = ( + LiteralType::COMP == literals_type || LiteralType::COMP_4 == literals_type || + LiteralType::TREELESS == literals_type || LiteralType::TREELESS_4 == literals_type + ); + assert!(!do_send_huff, "Huffmann coding not implemented yet"); + let tok = send_if(tok, huff_literals_s, false, zero!()); + + // empty RLE literals with last not set will not be sent by RLE decoder to buffer + let literals_id = if (is_empty && state.literals_type == LiteralType::RLE) { + state.literals_id + } else { + state.literals_id + LitID:1 + }; + LiteralsDispatcherState { + literals_type: literals_type, + left_to_read: left_to_read, + literals_id: literals_id, + } + } +} + +#[test_proc] +proc LiteralsDispatcher_test { + terminator: chan out; + literals_ctrl_s: chan out; + literals_data_s: chan out; + raw_literals_r: chan in; + rle_literals_r: chan in; + huff_literals_r: chan in; + + config(terminator: chan out) { + let (literals_ctrl_s, literals_ctrl_r) = chan("literals_ctrl"); + let (literals_data_s, literals_data_r) = chan("literals_data"); + let (raw_literals_s, raw_literals_r) = chan("raw_literals"); + let (rle_literals_s, rle_literals_r) = chan("rle_literals"); + let (huff_literals_s, huff_literals_r) = chan("huff_literals"); + + spawn LiteralsDispatcher( + literals_ctrl_r, + literals_data_r, + raw_literals_s, + rle_literals_s, + huff_literals_s, + ); + + ( + terminator, + literals_ctrl_s, + literals_data_s, + raw_literals_r, + rle_literals_r, + huff_literals_r, + ) + } + + init { } + + next(state: ()) { + let tok = join(); + let test_ctrl: LiteralsPathCtrl[6] = [ + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:8, literals_type: LiteralType::RAW}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:4, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:13, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:15, literals_type: LiteralType::RAW}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:123, literals_type: LiteralType::RLE}, + LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:31, literals_type: LiteralType::RAW}, + ]; + let test_data: LiteralsData[10] = [ + // 0. RAW + LiteralsData {data: LitData:0x1657_3465_A6DB_5DB0, length: LitLength:8, last: false}, + // 1. RLE + LiteralsData {data: LitData:0x23, length: LitLength:1, last: false}, + // 2. RLE + LiteralsData {data: LitData:0x35, length: LitLength:1, last: true}, + // 3. RAW + LiteralsData {data: LitData:0x4CFB_41C6_7B60_5370, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0x009B_0F9C_E1BA_A96D, length: LitLength:7, last: false}, + // 4. RLE + LiteralsData {data: LitData:0x5A, length: LitLength:1, last: false}, + // 5. RAW + LiteralsData {data: LitData:0x6094_3E96_1834_C247, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0xBC02_D0E8_D728_9ABE, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0xF864_C38B_E1FA_8D12, length: LitLength:8, last: false}, + LiteralsData {data: LitData:0xFC19_63F1_CE21_C294, length: LitLength:7, last: true}, + ]; + let expected_raw: LiteralsDataWithSync[7] = [ + // 0. + LiteralsDataWithSync {data: LitData:0x1657_3465_A6DB_5DB0, length: LitLength:8, id: LitID:0, last: false, literals_last: true}, + // 3. + LiteralsDataWithSync {data: LitData:0x4CFB_41C6_7B60_5370, length: LitLength:8, id: LitID:3, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x009B_0F9C_E1BA_A96D, length: LitLength:7, id: LitID:4, last: false, literals_last: true}, + // 5. + LiteralsDataWithSync {data: LitData:0x6094_3E96_1834_C247, length: LitLength:8, id: LitID:6, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0xBC02_D0E8_D728_9ABE, length: LitLength:8, id: LitID:7, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0xF864_C38B_E1FA_8D12, length: LitLength:8, id: LitID:8, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0xFC19_63F1_CE21_C294, length: LitLength:7, id: LitID:9, last: true, literals_last: true}, + ]; + let expected_rle: RleLiteralsData[3] = [ + // 1. + RleLiteralsData {data: RleLitData:0x23, repeat: RleLitRepeat:4, id: LitID:1, last: false}, + // 2. + RleLiteralsData {data: RleLitData:0x35, repeat: RleLitRepeat:13, id: LitID:2, last: true}, + // 4. + RleLiteralsData {data: RleLitData:0x5A, repeat: RleLitRepeat:123, id: LitID:5, last: false}, + ]; + let tok = for ((counter, test_ctrl), tok): ((u32, LiteralsPathCtrl), token) in enumerate(test_ctrl) { + let tok = send(tok, literals_ctrl_s, test_ctrl); + trace_fmt!("Send #{} literals ctrl, {:#x}", counter + u32:1, test_ctrl); + (tok) + }(tok); + + let tok = for ((counter, test_data), tok): ((u32, LiteralsData), token) in enumerate(test_data) { + let tok = send(tok, literals_data_s, test_data); + trace_fmt!("Send #{} literals data, {:#x}", counter + u32:1, test_data); + (tok) + }(tok); + + let tok_1 = for ((counter, expected_raw), tok_1): ((u32, LiteralsDataWithSync), token) in enumerate(expected_raw) { + let (tok_1, raw) = recv(tok_1, raw_literals_r); + trace_fmt!("Recv #{} raw literals, {:#x}", counter + u32:1, raw); + assert_eq(expected_raw, raw); + (tok_1) + }(tok); + + let tok_2 = for ((counter, expected_rle), tok_2): ((u32, RleLiteralsData), token) in enumerate(expected_rle) { + let (tok_2, rle) = recv(tok_2, rle_literals_r); + trace_fmt!("Recv #{} rle literals, {:#x}", counter + u32:1, rle); + assert_eq(expected_rle, rle); + (tok_2) + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/parallel_rams.x b/xls/modules/zstd/parallel_rams.x new file mode 100644 index 0000000000..24f9718326 --- /dev/null +++ b/xls/modules/zstd/parallel_rams.x @@ -0,0 +1,720 @@ +// Copyright 2023 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// this file contains implementation of parallel RAMs handling + +import std; +import xls.modules.zstd.common as common; +import xls.examples.ram; + +type BlockData = common::BlockData; +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; +type SequenceExecutorPacket = common::SequenceExecutorPacket; +type CopyOrMatchContent = common::CopyOrMatchContent; +type CopyOrMatchLength = common::CopyOrMatchLength; +type ZstdDecodedPacket = common::ZstdDecodedPacket; +type BlockPacketLength = common::BlockPacketLength; +pub type Offset = common::Offset; + +// Configurable RAM parameters, RAM_NUM has to be a power of 2 +pub const RAM_NUM = u32:8; + +// Constants calculated from RAM parameters +pub const RAM_NUM_WIDTH = std::clog2(RAM_NUM); + +pub type RamNumber = bits[RAM_NUM_WIDTH]; +pub type RamReadStart = bits[RAM_NUM_WIDTH]; +pub type RamReadLen = bits[std::clog2(RAM_NUM + u32:1)]; + +pub fn ram_size(hb_size_kb: u32) -> u32 { + (hb_size_kb * u32:1024 * u32:8) / RAM_DATA_WIDTH / RAM_NUM +} + +pub fn ram_addr_width(hb_size_kb: u32) -> u32 { + std::clog2(ram_size(hb_size_kb)) +} + +// RAM related constants common for tests +const TEST_HISTORY_BUFFER_SIZE_KB = u32:1; +const TEST_RAM_SIZE = ram_size(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_RAM_ADDR_WIDTH = ram_addr_width(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_RAM_DATA_WIDTH = common::SYMBOL_WIDTH; +const TEST_RAM_WORD_PARTITION_SIZE = TEST_RAM_DATA_WIDTH; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_WIDTH); +const TEST_RAM_INITIALIZED = true; +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_REQ_MASK_ALL = std::unsigned_max_value(); +const TEST_RAM_REQ_MASK_NONE = bits[TEST_RAM_NUM_PARTITIONS]:0; + +type TestRamAddr = bits[TEST_RAM_ADDR_WIDTH]; +type TestWriteReq = ram::WriteReq; +type TestWriteResp = ram::WriteResp; +type TestReadReq = ram::ReadReq; +type TestReadResp = ram::ReadResp; + +pub struct HistoryBufferPtr { number: RamNumber, addr: bits[RAM_ADDR_WIDTH] } + +pub fn hb_ptr_from_offset_back< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_SIZE: u32 = {ram_size(HISTORY_BUFFER_SIZE_KB)}, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)} +>( + ptr: HistoryBufferPtr, offset: Offset) -> HistoryBufferPtr { + + const_assert!(common::OFFSET_WIDTH < u32:32); + type RamAddr = bits[RAM_ADDR_WIDTH]; + + let buff_change = offset as RamNumber; + let max_row_span = (offset >> RAM_NUM_WIDTH) as RamAddr; + let addr_change = if ptr.number >= buff_change { + (max_row_span) + } else { + (max_row_span + RamAddr:1) + }; + let number = ptr.number - buff_change; + let addr = ptr.addr - addr_change; + HistoryBufferPtr { number, addr } +} + +#[test] +fn test_hb_ptr_from_offset_back() { + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:0), + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:1), + HistoryBufferPtr { number: RamNumber:3, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:2), + HistoryBufferPtr { number: RamNumber:2, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:3), + HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:4), + HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:5), + HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:1 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:6), + HistoryBufferPtr { number: RamNumber:6, addr: TestRamAddr:1 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:7), + HistoryBufferPtr { number: RamNumber:5, addr: TestRamAddr:1 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:8), + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:1 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:15), + HistoryBufferPtr { number: RamNumber:5, addr: TestRamAddr:0 }); + assert_eq( + hb_ptr_from_offset_back( + HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0 }, Offset:1), + HistoryBufferPtr { number: RamNumber:7, addr: (TEST_RAM_SIZE - u32:1) as TestRamAddr }); +} + +pub fn hb_ptr_from_offset_forw< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_SIZE: u32 = {ram_size(HISTORY_BUFFER_SIZE_KB)}, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)} +>(ptr: HistoryBufferPtr, offset: Offset) -> HistoryBufferPtr { + + type RamAddr = bits[RAM_ADDR_WIDTH]; + const MAX_ADDR = (RAM_SIZE - u32:1) as RamAddr; + + let buff_change = std::mod_pow2(offset as u32, RAM_NUM) as RamNumber; + let rounded_offset = std::round_up_to_nearest_pow2_unsigned(offset as u32 + u32:1, RAM_NUM as u32); + let max_row_span = std::div_pow2(rounded_offset, RAM_NUM) as RamAddr; + let (number, addr_change) = if ptr.number as u32 + buff_change as u32 < RAM_NUM { + (ptr.number + buff_change, max_row_span - RamAddr:1) + } else { + ((buff_change as u32 - (RAM_NUM - ptr.number as u32)) as RamNumber, max_row_span) + }; + + let addr = if ptr.addr + addr_change <= MAX_ADDR { + ptr.addr + addr_change + } else { + (addr_change - (MAX_ADDR - ptr.addr)) + }; + + HistoryBufferPtr { number, addr } +} + +#[test] +fn test_hb_ptr_from_offset_forw() { + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:0), + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:1), + HistoryBufferPtr { number: RamNumber:5, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:2), + HistoryBufferPtr { number: RamNumber:6, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:3), + HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:2 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:4), + HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:3 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:5), + HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:3 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:6), + HistoryBufferPtr { number: RamNumber:2, addr: TestRamAddr:3 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:7), + HistoryBufferPtr { number: RamNumber:3, addr: TestRamAddr:3 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:8), + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:3 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:15), + HistoryBufferPtr { number: RamNumber:3, addr: TestRamAddr:4 }); + assert_eq( + hb_ptr_from_offset_forw( + HistoryBufferPtr { number: RamNumber:7, addr: (TEST_RAM_SIZE - u32:1) as TestRamAddr }, + Offset:1), HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0 }); +} + +fn literal_packet_to_single_write_req< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + RAM_DATA_WIDTH: u32 = {common::SYMBOL_WIDTH}, + RAM_WORD_PARTITION_SIZE: u32 = {RAM_DATA_WIDTH}, + RAM_NUM_PARTITIONS: u32 = {ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH)} +>(ptr: HistoryBufferPtr, literal: SequenceExecutorPacket, number: RamNumber) + -> ram::WriteReq { + type RamData = uN[RAM_DATA_WIDTH]; + type WriteReq = ram::WriteReq; + + let offset = std::mod_pow2(RAM_NUM - ptr.number as u32 + number as u32, RAM_NUM) as Offset; + let we = literal.length >= offset as CopyOrMatchLength + CopyOrMatchLength:1; + let hb = hb_ptr_from_offset_forw(ptr, offset); + + if (we) { + WriteReq { + data: literal.content[offset as u32 * RAM_DATA_WIDTH+:RamData] as RamData, + addr: hb.addr, + mask: std::unsigned_max_value() + } + } else { + zero!() + } +} + +#[test] +fn test_literal_packet_to_single_write_req() { + // BEFORE: AFTER: + // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 + // 1 | | | | | | | | | 1 | | | | | | | | | + // 2 | o| | | | | | | | 2 |11| | | | | | | | + // 3 | | | | | | | | | 3 | | o|77|66|55|44|33|22| + // 4 | | | | | | | | | 4 | | | | | | | | | + type RamData = uN[TEST_RAM_DATA_WIDTH]; + + let ptr = HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:2 }; + let literals = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:7, + content: CopyOrMatchContent:0x77_6655_4433_2211, + last: false + }; + assert_eq( + literal_packet_to_single_write_req(ptr, literals, RamNumber:0), + TestWriteReq { data: RamData:0x22, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }); + assert_eq( + literal_packet_to_single_write_req(ptr, literals, RamNumber:3), + TestWriteReq { data: RamData:0x55, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }); + assert_eq( + literal_packet_to_single_write_req(ptr, literals, RamNumber:6), + zero!()); +} + +pub fn literal_packet_to_write_reqs< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + RAM_DATA_WIDTH: u32 = {common::SYMBOL_WIDTH}, + RAM_WORD_PARTITION_SIZE: u32 = {RAM_DATA_WIDTH}, + RAM_NUM_PARTITIONS: u32 = {ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH)} +>( + ptr: HistoryBufferPtr, literal: SequenceExecutorPacket +) -> (ram::WriteReq[RAM_NUM], HistoryBufferPtr) { + type WriteReq = ram::WriteReq; + let result = WriteReq[RAM_NUM]:[ + literal_packet_to_single_write_req(ptr, literal, RamNumber:0), + literal_packet_to_single_write_req(ptr, literal, RamNumber:1), + literal_packet_to_single_write_req(ptr, literal, RamNumber:2), + literal_packet_to_single_write_req(ptr, literal, RamNumber:3), + literal_packet_to_single_write_req(ptr, literal, RamNumber:4), + literal_packet_to_single_write_req(ptr, literal, RamNumber:5), + literal_packet_to_single_write_req(ptr, literal, RamNumber:6), + literal_packet_to_single_write_req(ptr, literal, RamNumber:7), + ]; + + let ptr_offset = literal.length; + (result, hb_ptr_from_offset_forw(ptr, ptr_offset as Offset)) +} + +#[test] +fn test_literal_packet_to_write_reqs() { + // BEFORE: AFTER: + // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 + // 1 | | | | | | | | | 1 | | | | | | | | | + // 2 | o| | | | | | | | 2 |11| | | | | | | | + // 3 | | | | | | | | | 3 | | | | | | | | o| + // 4 | | | | | | | | | 4 | | | | | | | | | + type RamData = uN[TEST_RAM_DATA_WIDTH]; + + let ptr = HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:0x2 }; + let literals = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + content: CopyOrMatchContent:0x11, + length: CopyOrMatchLength:1, + last: false + }; + assert_eq( + literal_packet_to_write_reqs(ptr, literals), + ( + TestWriteReq[RAM_NUM]:[ + zero!(), zero!(), zero!(), + zero!(), zero!(), zero!(), + zero!(), + TestWriteReq { data: RamData:0x11, addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }, + ], HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0x3 }, + )); + + // BEFORE: AFTER: + // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 + // 1 | | | | | | | | | 1 | | | | | | | | | + // 2 | o| | | | | | | | 2 |11| | | | | | | | + // 3 | | | | | | | | | 3 | o|88|77|66|55|44|33|22| + // 4 | | | | | | | | | 4 | | | | | | | | | + + let ptr = HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:2 }; + let literals = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + content: CopyOrMatchContent:0x8877_6655_4433_2211, + length: CopyOrMatchLength:8, + last: false + }; + assert_eq( + literal_packet_to_write_reqs(ptr, literals), + ( + TestWriteReq[RAM_NUM]:[ + TestWriteReq { data: RamData:0x22, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x33, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x44, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x55, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x66, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x77, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x88, addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestWriteReq { data: RamData:0x11, addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }, + ], HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:3 }, + )); +} + +fn max_hb_ptr_for_sequence_packet< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + RAM_DATA_WIDTH: u32 = {common::SYMBOL_WIDTH}, +> ( + ptr: HistoryBufferPtr, seq: SequenceExecutorPacket +) -> HistoryBufferPtr { + hb_ptr_from_offset_back(ptr, seq.content as Offset) +} + +fn sequence_packet_to_single_read_req< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + RAM_DATA_WIDTH: u32 = {common::SYMBOL_WIDTH}, + RAM_WORD_PARTITION_SIZE: u32 = {RAM_DATA_WIDTH}, + RAM_NUM_PARTITIONS: u32 = {ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH)} +> ( + ptr: HistoryBufferPtr, max_ptr: HistoryBufferPtr, + seq: SequenceExecutorPacket, number: RamNumber +) -> ram::ReadReq { + const RAM_REQ_MASK_ALL = bits[RAM_NUM_PARTITIONS]:1; + type ReadReq = ram::ReadReq; + + let offset_change = if max_ptr.number > number { + RAM_NUM as RamNumber - max_ptr.number + number + } else { + number - max_ptr.number + }; + let offset = (seq.content as Offset - offset_change as Offset) as Offset; + let re = (offset_change as CopyOrMatchLength) < seq.length; + let hb = hb_ptr_from_offset_back(ptr, offset); + + if (re) { + ReadReq { addr: hb.addr, mask: RAM_REQ_MASK_ALL } + } else { + zero!() + } +} + +#[test] +fn test_sequence_packet_to_single_read_req() { + // BEFORE: AFTER: + // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 + // 1 | x| x| | | | | | | 1 | | | | | | | | | + // 2 | | | | | | | x| x| 2 | | | | | | | | | + // 3 | | | | | | | o| | 3 | | | o| y| y| y| y| | + // 4 | | | | | | | | | 4 | | | | | | | | | + + let ptr = HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:0x3 }; + let sequence = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + content: CopyOrMatchContent:11, + length: CopyOrMatchLength:4, + last: false + }; + let max_ptr = max_hb_ptr_for_sequence_packet< + TEST_HISTORY_BUFFER_SIZE_KB, TEST_RAM_ADDR_WIDTH, TEST_RAM_DATA_WIDTH + >(ptr, sequence); + + assert_eq( + sequence_packet_to_single_read_req( + ptr, max_ptr, sequence, RamNumber:0), + TestReadReq { addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }); + + assert_eq( + sequence_packet_to_single_read_req( + ptr, max_ptr, sequence, RamNumber:1), + TestReadReq { addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }); + + assert_eq( + sequence_packet_to_single_read_req( + ptr, max_ptr, sequence, RamNumber:2), zero!()); + + assert_eq( + sequence_packet_to_single_read_req( + ptr, max_ptr, sequence, RamNumber:7), + TestReadReq { addr: TestRamAddr:0x1, mask: TEST_RAM_REQ_MASK_ALL }); + + assert_eq( + sequence_packet_to_single_read_req( + ptr, max_ptr, sequence, RamNumber:6), + TestReadReq { addr: TestRamAddr:0x1, mask: TEST_RAM_REQ_MASK_ALL }); +} + +pub fn sequence_packet_to_read_reqs< + HISTORY_BUFFER_SIZE_KB: u32, + RAM_ADDR_WIDTH: u32 = {ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + RAM_DATA_WIDTH: u32 = {common::SYMBOL_WIDTH}, + RAM_WORD_PARTITION_SIZE: u32 = {RAM_DATA_WIDTH}, + RAM_NUM_PARTITIONS: u32 = {ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH)} +> ( + ptr: HistoryBufferPtr, seq: SequenceExecutorPacket, hb_len: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH] +) -> (ram::ReadReq[RAM_NUM], RamReadStart, RamReadLen, SequenceExecutorPacket, bool) { + type ReadReq = ram::ReadReq; + type Packet = SequenceExecutorPacket; + + let max_len = std::umin(seq.length as u32, std::umin(RAM_NUM, hb_len as u32)); + + let (curr_seq, next_seq, next_seq_valid) = if seq.length > max_len as CopyOrMatchLength { + ( + Packet { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: max_len as CopyOrMatchLength, + content: seq.content, + last: false, + }, + Packet { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: seq.length - (max_len as CopyOrMatchLength), + content: seq.content + (max_len as uN[RAM_DATA_WIDTH * u32:8]), + last: seq.last + }, + true, + ) + } else { + (seq, zero!(), false) + }; + + let max_ptr = max_hb_ptr_for_sequence_packet(ptr, curr_seq); + let req0 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:0); + let req1 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:1); + let req2 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:2); + let req3 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:3); + let req4 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:4); + let req5 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:5); + let req6 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:6); + let req7 = sequence_packet_to_single_read_req(ptr, max_ptr, curr_seq, RamNumber:7); + + let reqs = ReadReq[RAM_NUM]:[req0, req1, req2, req3, req4, req5, req6, req7]; + + (reqs, max_ptr.number, max_len as RamReadLen, next_seq, next_seq_valid) +} + +#[test] +fn test_sequence_packet_to_read_reqs() { + // BEFORE: AFTER: + // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 + // 1 | x| x| | | | | | | 1 | | | | | | | | | + // 2 | | | | | | | x| x| 2 | | | | | | | | | + // 3 | | | | | | | o| | 3 | | | | | | | o| | + // 4 | | | | | | | | | 4 | | | | | | | | | + type Packet = SequenceExecutorPacket; + type HistoryBufferLength = uN[TEST_RAM_ADDR_WIDTH + RAM_NUM_WIDTH]; + + let ptr = HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:0x3 }; + let sequence = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + content: CopyOrMatchContent:11, + length: CopyOrMatchLength:4, + last: false + }; + let result = sequence_packet_to_read_reqs( + ptr, sequence, HistoryBufferLength:20); + let expected = ( + TestReadReq[RAM_NUM]:[ + TestReadReq { addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }, zero!(), + zero!(), zero!(), zero!(), + TestReadReq { addr: TestRamAddr:0x1, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x1, mask: TEST_RAM_REQ_MASK_ALL }, + ], + RamReadStart:6, + RamReadLen:4, + zero!(), false, + ); + assert_eq(result, expected); + + // BEFORE: AFTER: + // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 + // 1 | | | | | | | | | 1 | | | | | | | | | + // 2 | x| x| | | | | | | 2 | | | | | | | | | + // 3 | | | x| x| x| x| x| x| 3 | | x| | | | | | | + // 4 | | | | | | | | o| 4 | | | | | | | | o| + + let ptr = HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0x4 }; + let sequence = Packet { + msg_type: SequenceExecutorMessageType::SEQUENCE, + content: CopyOrMatchContent:10, + length: CopyOrMatchLength:9, + last: false + }; + let result = sequence_packet_to_read_reqs( + ptr, sequence, HistoryBufferLength:20); + let expected = ( + TestReadReq[RAM_NUM]:[ + TestReadReq { addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x3, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }, + TestReadReq { addr: TestRamAddr:0x2, mask: TEST_RAM_REQ_MASK_ALL }, + ], + RamReadStart:6, + RamReadLen:8, + Packet { + msg_type: SequenceExecutorMessageType::SEQUENCE, + content: CopyOrMatchContent:18, + length: CopyOrMatchLength:1, + last: false + }, true, + ); + assert_eq(result, expected); +} + +pub struct RamWrRespHandlerData { + resp: bool[RAM_NUM], + ptr: HistoryBufferPtr, +} + +pub struct RamWrRespHandlerResp { + length: uN[std::clog2(RAM_NUM + u32:1)], + ptr: HistoryBufferPtr, +} + +pub fn create_ram_wr_data + (reqs: ram::WriteReq[RAM_NUM], ptr: HistoryBufferPtr) -> (bool, RamWrRespHandlerData) { + const RAM_REQ_MASK_NONE = bits[RAM_NUM_PARTITIONS]:0; + + let (do_write, resp) = for (i, (do_write, resp)): (u32, (bool, bool[RAM_NUM])) in range(u32:0, RAM_NUM) { + ( + do_write || reqs[i].mask, + update(resp, i, reqs[i].mask != RAM_REQ_MASK_NONE) + ) + }((false, zero!())); + + (do_write, RamWrRespHandlerData { resp, ptr }) +} + +pub proc RamWrRespHandler { + input_r: chan in; + output_s: chan out; + wr_resp_m0_r: chan in; + wr_resp_m1_r: chan in; + wr_resp_m2_r: chan in; + wr_resp_m3_r: chan in; + wr_resp_m4_r: chan in; + wr_resp_m5_r: chan in; + wr_resp_m6_r: chan in; + wr_resp_m7_r: chan in; + + config(input_r: chan> in, + output_s: chan> out, + wr_resp_m0_r: chan in, wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, wr_resp_m7_r: chan in) { + ( + input_r, output_s, wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, + wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + ) + } + + init { } + + next(state: ()) { + let tok0 = join(); + let (tok1, input) = recv(tok0, input_r); + + let (tok2_0, _) = recv_if(tok1, wr_resp_m0_r, input.resp[0], zero!()); + let (tok2_1, _) = recv_if(tok1, wr_resp_m1_r, input.resp[1], zero!()); + let (tok2_2, _) = recv_if(tok1, wr_resp_m2_r, input.resp[2], zero!()); + let (tok2_3, _) = recv_if(tok1, wr_resp_m3_r, input.resp[3], zero!()); + let (tok2_4, _) = recv_if(tok1, wr_resp_m4_r, input.resp[4], zero!()); + let (tok2_5, _) = recv_if(tok1, wr_resp_m5_r, input.resp[5], zero!()); + let (tok2_6, _) = recv_if(tok1, wr_resp_m6_r, input.resp[6], zero!()); + let (tok2_7, _) = recv_if(tok1, wr_resp_m7_r, input.resp[7], zero!()); + let tok2 = join(tok2_0, tok2_1, tok2_2, tok2_3, tok2_4, tok2_5, tok2_6, tok2_7); + + let tok3 = send(tok2, output_s, RamWrRespHandlerResp { + length: std::popcount(std::convert_to_bits_msb0(input.resp)) as uN[std::clog2(RAM_NUM + u32:1)], + ptr: input.ptr + }); + } +} + +pub struct RamRdRespHandlerData { + resp: bool[RAM_NUM], + read_start: RamReadStart, + read_len: RamReadLen, + last: bool +} + +pub fn create_ram_rd_data + (reqs: ram::ReadReq[RAM_NUM], read_start: RamReadStart, read_len: RamReadLen, last: bool, next_packet_valid: bool) -> (bool, RamRdRespHandlerData) { + const RAM_REQ_MASK_NONE = bits[RAM_NUM_PARTITIONS]:0; + + let (do_read, resp) = for (i, (do_read, resp)): (u32, (bool, bool[RAM_NUM])) in range(u32:0, RAM_NUM) { + ( + do_read || reqs[i].mask, + update(resp, i, reqs[i].mask != RAM_REQ_MASK_NONE) + ) + }((false, zero!())); + + let last = (!next_packet_valid) && last; + (do_read, RamRdRespHandlerData { resp, read_start, read_len, last }) +} + +pub proc RamRdRespHandler { + input_r: chan in; + output_s: chan> out; + rd_resp_m0_r: chan> in; + rd_resp_m1_r: chan> in; + rd_resp_m2_r: chan> in; + rd_resp_m3_r: chan> in; + rd_resp_m4_r: chan> in; + rd_resp_m5_r: chan> in; + rd_resp_m6_r: chan> in; + rd_resp_m7_r: chan> in; + + config(input_r: chan in, output_s: chan> out, + rd_resp_m0_r: chan> in, + rd_resp_m1_r: chan> in, + rd_resp_m2_r: chan> in, + rd_resp_m3_r: chan> in, + rd_resp_m4_r: chan> in, + rd_resp_m5_r: chan> in, + rd_resp_m6_r: chan> in, + rd_resp_m7_r: chan> in) { + ( + input_r, output_s, rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, rd_resp_m4_r, + rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + ) + } + + init { } + + next(state: ()) { + let tok0 = join(); + type ReadResp = ram::ReadResp; + type Content = uN[RAM_DATA_WIDTH * u32:8]; + + let (tok1, input) = recv(tok0, input_r); + + let (tok2_0, resp_0) = recv_if(tok1, rd_resp_m0_r, input.resp[0], zero!()); + let (tok2_1, resp_1) = recv_if(tok1, rd_resp_m1_r, input.resp[1], zero!()); + let (tok2_2, resp_2) = recv_if(tok1, rd_resp_m2_r, input.resp[2], zero!()); + let (tok2_3, resp_3) = recv_if(tok1, rd_resp_m3_r, input.resp[3], zero!()); + let (tok2_4, resp_4) = recv_if(tok1, rd_resp_m4_r, input.resp[4], zero!()); + let (tok2_5, resp_5) = recv_if(tok1, rd_resp_m5_r, input.resp[5], zero!()); + let (tok2_6, resp_6) = recv_if(tok1, rd_resp_m6_r, input.resp[6], zero!()); + let (tok2_7, resp_7) = recv_if(tok1, rd_resp_m7_r, input.resp[7], zero!()); + let tok2 = join(tok2_0, tok2_1, tok2_2, tok2_3, tok2_4, tok2_5, tok2_6, tok2_7); + + let resp_data = [ + resp_0.data, resp_1.data, resp_2.data, resp_3.data, + resp_4.data, resp_5.data, resp_6.data, resp_7.data + ]; + + let content = ( + resp_data[input.read_start + u3:7] ++ + resp_data[input.read_start + u3:6] ++ + resp_data[input.read_start + u3:5] ++ + resp_data[input.read_start + u3:4] ++ + resp_data[input.read_start + u3:3] ++ + resp_data[input.read_start + u3:2] ++ + resp_data[input.read_start + u3:1] ++ + resp_data[input.read_start + u3:0] + ); + + let output_data = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: input.read_len as CopyOrMatchLength, + content: content as Content, + last: input.last, + }; + + let tok3 = send(tok2, output_s, output_data); + } +} diff --git a/xls/modules/zstd/raw_literals_dec.x b/xls/modules/zstd/raw_literals_dec.x new file mode 100644 index 0000000000..1dbb971785 --- /dev/null +++ b/xls/modules/zstd/raw_literals_dec.x @@ -0,0 +1,81 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// The proc should just pass incoming data as literals to LiteralsBuffer. +// Packets of 0 length are not passed further and a warning is log instead. + +import xls.modules.zstd.common; + +type LiteralsDataWithSync = common::LiteralsDataWithSync; +type LitData = common::LitData; +type LitLength = common::LitLength; + +pub proc RawLiteralsDecoder { + dispatcher_r: chan in; + buffer_s: chan out; + + config(dispatcher_r: chan in, buffer_s: chan out) { + (dispatcher_r, buffer_s) + } + + init { } + + next(state: ()) { + let tok = join(); + let (tok, resp) = recv(tok, dispatcher_r); + let do_send = if resp.length == LitLength:0 { + trace_fmt!("[WARNING] Packet of 0 length received by RawLiteralsDecoder"); + false + } else { + true + }; + let tok = send_if(tok, buffer_s, do_send, resp); + } +} + +#[test_proc] +proc RawLiteralsDecoderTest { + terminator: chan out; + dispatcher_s: chan out; + buffer_r: chan in; + + config(terminator: chan out) { + let (dispatcher_s, dispatcher_r) = chan("dispatcher"); + let (buffer_s, buffer_r) = chan("buffer"); + + spawn RawLiteralsDecoder(dispatcher_r, buffer_s); + + (terminator, dispatcher_s, buffer_r) + } + + init { } + + next(state: ()) { + let tok = join(); + let data = LiteralsDataWithSync { data: LitData:0x11_22_33_44_55_66, length: LitLength:6, id: u32:0, last: true, literals_last: true }; + let tok = send(tok, dispatcher_s, data); + let (tok, resp) = recv(tok, buffer_r); + assert_eq(resp, data); + + let empty_data = LiteralsDataWithSync { data: LitData:0, length: LitLength:0, id: u32:0, last: true, literals_last: true }; + let tok = send(tok, dispatcher_s, empty_data); + + // Resend the first packet to verify that the empty packet is dropped correctly. + let tok = send(tok, dispatcher_s, data); + let (tok, resp) = recv(tok, buffer_r); + assert_eq(resp, data); + + let tok = send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/rle_literals_dec.x b/xls/modules/zstd/rle_literals_dec.x new file mode 100644 index 0000000000..dda39f8208 --- /dev/null +++ b/xls/modules/zstd/rle_literals_dec.x @@ -0,0 +1,409 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of RleLiteralsDecoder responsible for decoding +// ZSTD RLE Literals. More information about Rle Literals's format can be found in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.1 + +import std; + +import xls.modules.zstd.common; +import xls.modules.rle.rle_dec; +import xls.modules.rle.rle_common; + +const RLE_LITERALS_DATA_WIDTH = common::RLE_LITERALS_DATA_WIDTH; +const RLE_LITERALS_REPEAT_WIDTH = common::RLE_LITERALS_REPEAT_WIDTH; +const LITERALS_DATA_WIDTH = common::LITERALS_DATA_WIDTH; +const LITERALS_LENGTH_WIDTH = common::LITERALS_LENGTH_WIDTH; + +type RleInput = rle_common::CompressedData; +type RleOutput = rle_common::PlainData; +type RleLiteralsData = common::RleLiteralsData; +type LiteralsDataWithSync = common::LiteralsDataWithSync; + +type RleLitData = common::RleLitData; +type RleLitRepeat = common::RleLitRepeat; +type LitData = common::LitData; +type LitID = common::LitID; +type LitLength = common::LitLength; + +struct LiteralsSyncData { + count: RleLitRepeat, + id: LitID, + last: bool, +} + +proc RleDataPacker { + literals_data_r: chan in; + rle_data_s: chan out; + sync_s: chan out; + + config( + literals_data_r: chan in, + rle_data_s: chan out, + sync_s: chan out, + ) { + (literals_data_r, rle_data_s, sync_s) + } + + init { } + + next(state: ()) { + let tok = join(); + let (tok, input) = recv(tok, literals_data_r); + let not_zero_repeat = (input.repeat != RleLitRepeat:0); + let rle_dec_data = RleInput { symbol: input.data, count: input.repeat, last: true }; + let data_tok = send_if(tok, rle_data_s, not_zero_repeat, rle_dec_data); + let sync_data = LiteralsSyncData { count: input.repeat, id: input.id, last: input.last }; + let sync_tok = send_if(data_tok, sync_s, not_zero_repeat || input.last, sync_data); + } +} + +#[test_proc] +proc RleDataPacker_test { + terminator: chan out; + in_s: chan out; + out_r: chan in; + sync_r: chan in; + + config(terminator: chan out) { + let (in_s, in_r) = chan("in"); + let (out_s, out_r) = chan("out"); + let (sync_s, sync_r) = chan("sync"); + + spawn RleDataPacker(in_r, out_s, sync_s); + + (terminator, in_s, out_r, sync_r) + } + + init { } + + next(state: ()) { + let tok = join(); + let test_data: RleLiteralsData[5] = [ + RleLiteralsData {data: RleLitData:0xAB, repeat: RleLitRepeat:11, id: LitID:0, last: bool:0}, + RleLiteralsData {data: RleLitData:0xCD, repeat: RleLitRepeat:3, id: LitID:1, last: bool:0}, + RleLiteralsData {data: RleLitData:0x12, repeat: RleLitRepeat:16, id: LitID:2, last: bool:0}, + RleLiteralsData {data: RleLitData:0x34, repeat: RleLitRepeat:20, id: LitID:3, last: bool:0}, + RleLiteralsData {data: RleLitData:0x56, repeat: RleLitRepeat:2, id: LitID:4, last: bool:1}, + ]; + + let tok = for ((counter, test_data), tok): ((u32, RleLiteralsData), token) in enumerate(test_data) { + let expected_data_out = RleInput { + symbol: test_data.data, + count: test_data.repeat, + last: true, + }; + + let expected_sync_out = LiteralsSyncData { + count: test_data.repeat, + id: test_data.id, + last: test_data.last, + }; + + let tok = send(tok, in_s, test_data); + trace_fmt!("Send #{} rle literals data, {:#x}", counter + u32:1, test_data); + + let (tok, data_out) = recv(tok, out_r); + trace_fmt!("Received #{} rle input data, {:#x}", counter + u32:1, data_out); + assert_eq(data_out, expected_data_out); + + let (tok, sync_out) = recv(tok, sync_r); + trace_fmt!("Received #{} sync data, {:#x}", counter + u32:1, sync_out); + assert_eq(sync_out, expected_sync_out); + + (tok) + }(tok); + + send(tok, terminator, true); + } +} + +struct BatchPackerState { + batch: LitData, + data_in_batch: LitLength, + count_left: RleLitRepeat, + sync_id: LitID, + sync_last: bool, +} + +// auxiliary variable used to replace multiplication with shifts +const_assert!(std::is_pow2(RLE_LITERALS_DATA_WIDTH)); +const RLE_LITERALS_DATA_WIDTH_SHIFT = std::clog2(RLE_LITERALS_DATA_WIDTH); + +proc BatchPacker { + rle_data_r: chan in; + sync_r: chan in; + literals_data_s: chan out; + + config( + rle_data_r: chan in, + sync_r: chan in, + literals_data_s: chan out, + ) { + (rle_data_r, sync_r, literals_data_s) + } + + init { zero!() } + + next(state: BatchPackerState) { + let tok = join(); + let no_count_left = (state.count_left == RleLitRepeat:0); + let (tok, sync_data) = recv_if(tok, sync_r, no_count_left, zero!()); + let (count_left, sync_id, sync_last) = if (no_count_left) { + (sync_data.count, sync_data.id, sync_data.last) + } else { + (state.count_left, state.sync_id, state.sync_last) + }; + + let (literals_data, do_send_batch, state) = if (count_left != RleLitRepeat:0) { + let (tok, decoded_data) = recv(tok, rle_data_r); + + let data_in_batch = state.data_in_batch; + // shift batch and append new symbol + let shift = (data_in_batch as u32) << RLE_LITERALS_DATA_WIDTH_SHIFT; + + let batch = state.batch | ((decoded_data.symbol as LitData) << shift); + let data_in_batch = data_in_batch + LitLength:1; + // send batch if it is the last batch or it is full + let do_send_batch = ( + decoded_data.last + | (((data_in_batch as u32 + u32:1) << RLE_LITERALS_DATA_WIDTH_SHIFT) > LITERALS_DATA_WIDTH) + ); + let literals_data = LiteralsDataWithSync { + data: batch, + length: data_in_batch, + last: sync_last && decoded_data.last, + id: sync_id, + literals_last: decoded_data.last, + }; + + let state = if do_send_batch { + BatchPackerState { + count_left: count_left - RleLitRepeat:1, + sync_id: sync_id, + sync_last: sync_last, + ..zero!() + } + } else { + BatchPackerState { + batch: batch, + data_in_batch: data_in_batch, + count_left: count_left - RleLitRepeat:1, + sync_id: sync_id, + sync_last: sync_last, + } + }; + + (literals_data, do_send_batch, state) + } else if (sync_data.last) { + // handle empty literal with last set + ( + LiteralsDataWithSync {id: sync_id, last: true, literals_last: true, ..zero!()}, + true, + BatchPackerState { + count_left: count_left, + sync_id: sync_id, + sync_last: sync_last, + ..state + }, + ) + } else { + // handle empty literal with last not set + ( + zero!(), + false, + BatchPackerState { + count_left: count_left, + sync_id: sync_id, + sync_last: sync_last, + ..state + }, + ) + }; + + let data_tok = send_if(tok, literals_data_s, do_send_batch, literals_data); + + state + } +} + +#[test_proc] +proc BatchPacker_test { + terminator: chan out; + in_s: chan out; + sync_s: chan out; + out_r: chan in; + + config(terminator: chan out) { + let (in_s, in_r) = chan("in"); + let (sync_s, sync_r) = chan("sync"); + let (out_s, out_r) = chan("out"); + + spawn BatchPacker(in_r, sync_r, out_s); + + (terminator, in_s, sync_s, out_r) + } + + init { } + + next(state: ()) { + let tok = join(); + let test_sync_data: LiteralsSyncData[4] = [ + LiteralsSyncData {count: RleLitRepeat:1, id: LitID:0, last: false}, + LiteralsSyncData {count: RleLitRepeat:8, id: LitID:1, last: false}, + LiteralsSyncData {count: RleLitRepeat:10, id: LitID:2, last: false}, + LiteralsSyncData {count: RleLitRepeat:13, id: LitID:3, last: true}, + ]; + let test_rle_data: RleOutput[32] = [ + // 1st literal + RleOutput {symbol: RleLitData:0x11, last: true}, + // 2nd literal + RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: false}, + RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: false}, + RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: false}, + RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: true}, + // 3rd literal + RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, + RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, + RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, + RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, + RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: true}, + // 4th literal + RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, + RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, + RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, + RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, + RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, + RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, + RleOutput {symbol: RleLitData:0x44, last: true}, + ]; + let test_out_data: LiteralsDataWithSync[6] = [ + LiteralsDataWithSync {data: LitData:0x0000_0000_0000_0011, length: LitLength:1, id: LitID:0, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x2222_2222_2222_2222, length: LitLength:8, id: LitID:1, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, id: LitID:2, last: false, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x0000_0000_0000_3333, length: LitLength:2, id: LitID:2, last: false, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x4444_4444_4444_4444, length: LitLength:8, id: LitID:3, last: false, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x0000_0044_4444_4444, length: LitLength:5, id: LitID:3, last: true, literals_last: true}, + ]; + + let tok = for ((counter, sync_data), tok): ((u32, LiteralsSyncData), token) in enumerate(test_sync_data) { + let tok = send(tok, sync_s, sync_data); + trace_fmt!("Sent #{} synchronization data, {:#x}", counter + u32:1, sync_data); + (tok) + }(tok); + + let tok = for ((counter, rle_data), tok): ((u32, RleOutput), token) in enumerate(test_rle_data) { + let tok = send(tok, in_s, rle_data); + trace_fmt!("Sent #{} rle data, {:#x}", counter + u32:1, rle_data); + (tok) + }(tok); + + let tok = for ((counter, expected_out_data), tok): ((u32, LiteralsDataWithSync), token) in enumerate(test_out_data) { + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received #{} batched data, {:#x}", counter + u32:1, out_data); + assert_eq(out_data, expected_out_data); + (tok) + }(tok); + + send(tok, terminator, true); + } +} + +pub proc RleLiteralsDecoder { + input_r: chan in; + output_s: chan out; + + config(input_r: chan in, output_s: chan out) { + let (in_s, in_r) = chan("in"); + let (out_s, out_r) = chan("in"); + let (sync_s, sync_r) = chan("sync"); + + spawn RleDataPacker(input_r, in_s, sync_s); + spawn rle_dec::RunLengthDecoder(in_r, out_s); + spawn BatchPacker(out_r, sync_r, output_s); + + (input_r, output_s) + } + + init { } + + next(state: ()) { } +} + +#[test_proc] +proc RleLiteralsDecoder_test { + terminator: chan out; + in_s: chan out; + out_r: chan in; + + config (terminator: chan out) { + let (in_s, in_r) = chan("in"); + let (out_s, out_r) = chan("out"); + + spawn RleLiteralsDecoder(in_r, out_s); + + (terminator, in_s, out_r) + } + + init { } + + next(state: ()) { + let tok = join(); + let test_rle_data: RleLiteralsData[7] = [ + RleLiteralsData {data: RleLitData:0x11, repeat: RleLitRepeat:11, id: LitID:0, last: false}, + RleLiteralsData {data: RleLitData:0x22, repeat: RleLitRepeat:3, id: LitID:1, last: false}, + RleLiteralsData {data: RleLitData:0x33, repeat: RleLitRepeat:16, id: LitID:2, last: false}, + RleLiteralsData {data: RleLitData:0x44, repeat: RleLitRepeat:0, id: LitID:0, last: false}, + RleLiteralsData {data: RleLitData:0x55, repeat: RleLitRepeat:2, id: LitID:3, last: false}, + RleLiteralsData {data: RleLitData:0x66, repeat: RleLitRepeat:20, id: LitID:4, last: false}, + RleLiteralsData {data: RleLitData:0x00, repeat: RleLitRepeat:0, id: LitID:5, last: true}, + ]; + + let test_out_data: LiteralsDataWithSync[10] = [ + // 1st literal + LiteralsDataWithSync {data: LitData:0x1111_1111_1111_1111, length: LitLength:8, last: false, id: LitID:0, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x0000_0000_0011_1111, length: LitLength:3, last: false, id: LitID:0, literals_last: true}, + // 2nd literal + LiteralsDataWithSync {data: LitData:0x0000_0000_0022_2222, length: LitLength:3, last: false, id: LitID:1, literals_last: true}, + // 3rd literal + LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, last: false, id: LitID:2, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, last: false, id: LitID:2, literals_last: true}, + // 4th literal (empty) + // 5th literal + LiteralsDataWithSync {data: LitData:0x0000_0000_0000_5555, length: LitLength:2, last: false, id: LitID:3, literals_last: true}, + // 6th literal + LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:8, last: false, id: LitID:4, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:8, last: false, id: LitID:4, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x0000_0000_6666_6666, length: LitLength:4, last: false, id: LitID:4, literals_last: true}, + // 7th literal + LiteralsDataWithSync {data: LitData:0x0000_0000_0000_0000, length: LitLength:0, last: true, id: LitID:5, literals_last: true}, + ]; + + let tok = for ((counter, rle_data), tok): ((u32, RleLiteralsData), token) in enumerate(test_rle_data) { + let tok = send(tok, in_s, rle_data); + trace_fmt!("Sent #{} rle data, {:#x}", counter + u32:1, rle_data); + (tok) + }(tok); + + let tok = for ((counter, expected_out_data), tok): ((u32, LiteralsDataWithSync), token) in enumerate(test_out_data) { + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received #{} batched data, {:#x}", counter + u32:1, out_data); + assert_eq(out_data, expected_out_data); + (tok) + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/sequence_executor.x b/xls/modules/zstd/sequence_executor.x index b46180a307..80a7a6e70a 100644 --- a/xls/modules/zstd/sequence_executor.x +++ b/xls/modules/zstd/sequence_executor.x @@ -15,28 +15,24 @@ import std; import xls.modules.zstd.common as common; import xls.modules.zstd.memory.mem_writer as mem_writer; +import xls.modules.zstd.parallel_rams as parallel_rams; import xls.modules.zstd.ram_printer as ram_printer; import xls.examples.ram; +// Configurable RAM parameters +pub const RAM_DATA_WIDTH = common::SYMBOL_WIDTH; +const RAM_NUM = u32:8; +const RAM_NUM_CLOG2 = std::clog2(RAM_NUM); + type BlockData = common::BlockData; type SequenceExecutorMessageType = common::SequenceExecutorMessageType; -type SequenceExecutorPacket = common::SequenceExecutorPacket; +type SequenceExecutorPacket = common::SequenceExecutorPacket; type CopyOrMatchContent = common::CopyOrMatchContent; type CopyOrMatchLength = common::CopyOrMatchLength; type ZstdDecodedPacket = common::ZstdDecodedPacket; type BlockPacketLength = common::BlockPacketLength; type Offset = common::Offset; -fn calculate_ram_addr_width(hb_size_kb: u32, ram_data_width: u32, ram_num: u32) -> u32 { - ((hb_size_kb * u32:1024 * u32:8) / ram_data_width) / ram_num -} - -// Configurable RAM parameters -pub const RAM_DATA_WIDTH = common::SYMBOL_WIDTH; -const RAM_NUM = u32:8; - -type RamData = bits[RAM_DATA_WIDTH]; - // Constants calculated from RAM parameters const RAM_NUM_WIDTH = std::clog2(RAM_NUM); pub const RAM_WORD_PARTITION_SIZE = RAM_DATA_WIDTH; @@ -45,7 +41,6 @@ pub const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_ const RAM_REQ_MASK_ALL = std::unsigned_max_value(); const RAM_REQ_MASK_NONE = bits[RAM_NUM_PARTITIONS]:0; -type RamNumber = bits[RAM_NUM_WIDTH]; type RamOrder = bits[RAM_ORDER_WIDTH]; pub fn ram_size(hb_size_kb: u32) -> u32 { (hb_size_kb * u32:1024 * u32:8) / RAM_DATA_WIDTH / RAM_NUM } @@ -67,9 +62,14 @@ type TestWriteResp = ram::WriteResp; type TestReadReq = ram::ReadReq; type TestReadResp = ram::ReadResp; -struct HistoryBufferPtr { number: RamNumber, addr: bits[RAM_ADDR_WIDTH] } - -type HistoryBufferLength = u32; +type HistoryBufferPtr = parallel_rams::HistoryBufferPtr; +type RamWrRespHandlerData = parallel_rams::RamWrRespHandlerData; +type RamWrRespHandlerResp = parallel_rams::RamWrRespHandlerResp; +type RamRdRespHandlerData = parallel_rams::RamRdRespHandlerData; +type RamData = uN[RAM_DATA_WIDTH]; +type RamNumber = parallel_rams::RamNumber; +type RamReadStart = parallel_rams::RamReadStart; +type RamReadLen = parallel_rams::RamReadLen; enum SequenceExecutorStatus : u2 { IDLE = 0, @@ -86,728 +86,69 @@ struct SequenceExecutorState { // History Buffer handling hyp_ptr: HistoryBufferPtr, real_ptr: HistoryBufferPtr, - hb_len: HistoryBufferLength, + hb_len: uN[RAM_ADDR_WIDTH + RAM_NUM_CLOG2], // Repeat Offset handling repeat_offsets: Offset[3], repeat_req: bool, seq_cnt: bool, } -fn decode_literal_packet(packet: SequenceExecutorPacket) -> ZstdDecodedPacket { - ZstdDecodedPacket { - data: packet.content, length: packet.length as BlockPacketLength, last: packet.last - } -} - -#[test] -fn test_decode_literal_packet() { - let content = CopyOrMatchContent:0xAA00BB11CC22DD33; - let length = CopyOrMatchLength:64; - let last = false; - - assert_eq( - decode_literal_packet( - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length, content, last - }), - ZstdDecodedPacket { - length: length as BlockPacketLength, - data: content, last - }) -} - -fn convert_output_packet(packet: ZstdDecodedPacket) -> mem_writer::MemWriterDataPacket { +fn decode_literal_packet(packet: SequenceExecutorPacket) -> mem_writer::MemWriterDataPacket { type MemWriterDataPacket = mem_writer::MemWriterDataPacket; MemWriterDataPacket { - data: packet.data as uN[DATA_W], - length: std::div_pow2(packet.length, u32:8) as uN[ADDR_W], + data: packet.content as uN[DATA_W], + length: packet.length as uN[ADDR_W], last: packet.last } } #[test] -fn test_convert_output_packet() { +fn test_decode_literal_packet() { const DATA_W = u32:64; const ADDR_W = u32:16; type MemWriterDataPacket = mem_writer::MemWriterDataPacket; - let packet = ZstdDecodedPacket { - data: CopyOrMatchContent:0xAA00BB11CC22DD33, - length: BlockPacketLength:64, - last: false - }; - let expected = MemWriterDataPacket { - data: uN[DATA_W]:0xAA00BB11CC22DD33, - length: uN[ADDR_W]:8, - last: false - }; - - assert_eq(convert_output_packet(packet), expected) -} - -fn round_up_to_pow2(x: uN[N]) -> uN[N] { - let base = x[Y_CLOG2 as s32:]; - let reminder = x[0:Y_CLOG2 as s32] != bits[Y_CLOG2]:0; - (base as uN[N] + reminder as uN[N]) << Y_CLOG2 -} - -#[test] -fn test_round_up_to_pow2() { - assert_eq(round_up_to_pow2(u16:0), u16:0); - assert_eq(round_up_to_pow2(u16:1), u16:8); - assert_eq(round_up_to_pow2(u16:7), u16:8); - assert_eq(round_up_to_pow2(u16:8), u16:8); - assert_eq(round_up_to_pow2(u16:9), u16:16); - assert_eq(round_up_to_pow2(u16:9), u16:16); -} - -fn hb_ptr_from_offset_back - - (ptr: HistoryBufferPtr, offset: Offset) -> HistoryBufferPtr { - - const_assert!(common::OFFSET_WIDTH < u32:32); - type RamAddr = bits[RAM_ADDR_WIDTH]; - - let buff_change = std::mod_pow2(offset as u32, RAM_NUM) as RamNumber; - let rounded_offset = round_up_to_pow2(offset as u32 + u32:1); - let max_row_span = std::div_pow2(rounded_offset, RAM_NUM) as RamAddr; - let (number, addr_change) = if ptr.number >= buff_change { - (ptr.number - buff_change, max_row_span - RamAddr:1) - } else { - ((RAM_NUM + ptr.number as u32 - buff_change as u32) as RamNumber, max_row_span) - }; - let addr = if ptr.addr > addr_change { - ptr.addr - addr_change - } else { - (RAM_SIZE + ptr.addr as u32 - addr_change as u32) as RamAddr - }; - HistoryBufferPtr { number, addr } -} - -#[test] -fn test_hb_ptr_from_offset_back() { - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:0), - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:1), - HistoryBufferPtr { number: RamNumber:3, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:2), - HistoryBufferPtr { number: RamNumber:2, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:3), - HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:4), - HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:5), - HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:1 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:6), - HistoryBufferPtr { number: RamNumber:6, addr: TestRamAddr:1 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:7), - HistoryBufferPtr { number: RamNumber:5, addr: TestRamAddr:1 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:8), - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:1 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:15), - HistoryBufferPtr { number: RamNumber:5, addr: TestRamAddr:0 }); - assert_eq( - hb_ptr_from_offset_back( - HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0 }, Offset:1), - HistoryBufferPtr { number: RamNumber:7, addr: (TEST_RAM_SIZE - u32:1) as TestRamAddr }); -} - -fn hb_ptr_from_offset_forw - - (ptr: HistoryBufferPtr, offset: Offset) -> HistoryBufferPtr { - - type RamAddr = bits[RAM_ADDR_WIDTH]; - const MAX_ADDR = (RAM_SIZE - u32:1) as RamAddr; - - let buff_change = std::mod_pow2(offset as u32, RAM_NUM) as RamNumber; - let rounded_offset = round_up_to_pow2(offset as u32 + u32:1); - let max_row_span = std::div_pow2(rounded_offset, RAM_NUM) as RamAddr; - let (number, addr_change) = if ptr.number as u32 + buff_change as u32 < RAM_NUM { - (ptr.number + buff_change, max_row_span - RamAddr:1) - } else { - ((buff_change as u32 - (RAM_NUM - ptr.number as u32)) as RamNumber, max_row_span) - }; - - let addr = if ptr.addr + addr_change <= MAX_ADDR { - ptr.addr + addr_change - } else { - (addr_change - (MAX_ADDR - ptr.addr)) - }; - - HistoryBufferPtr { number, addr } -} - -#[test] -fn test_hb_ptr_from_offset_forw() { - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:0), - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:1), - HistoryBufferPtr { number: RamNumber:5, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:2), - HistoryBufferPtr { number: RamNumber:6, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:3), - HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:2 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:4), - HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:3 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:5), - HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:3 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:6), - HistoryBufferPtr { number: RamNumber:2, addr: TestRamAddr:3 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:7), - HistoryBufferPtr { number: RamNumber:3, addr: TestRamAddr:3 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:8), - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:3 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:4, addr: TestRamAddr:2 }, Offset:15), - HistoryBufferPtr { number: RamNumber:3, addr: TestRamAddr:4 }); - assert_eq( - hb_ptr_from_offset_forw( - HistoryBufferPtr { number: RamNumber:7, addr: (TEST_RAM_SIZE - u32:1) as TestRamAddr }, - Offset:1), HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0 }); -} - -fn literal_packet_to_single_write_req - - (ptr: HistoryBufferPtr, literal: SequenceExecutorPacket, number: RamNumber) - -> ram::WriteReq { - - let offset = std::mod_pow2(RAM_NUM - ptr.number as u32 + number as u32, RAM_NUM) as Offset; - let we = literal.length >= (offset as CopyOrMatchLength + CopyOrMatchLength:1) << CopyOrMatchLength:3; - let hb = hb_ptr_from_offset_forw(ptr, offset); - - if we { - ram::WriteReq { - data: literal.content[offset as u32 << u32:3+:RamData] as RamData, - addr: hb.addr, - mask: std::unsigned_max_value() - } - } else { - ram::WriteReq { - addr: bits[RAM_ADDR_WIDTH]:0, - data: bits[RAM_DATA_WIDTH]:0, - mask: bits[RAM_NUM_PARTITIONS]:0 - } - } -} - -#[test] -fn test_literal_packet_to_single_write_req() { - // BEFORE: AFTER: - // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 - // 1 | | | | | | | | | 1 | | | | | | | | | - // 2 | o| | | | | | | | 2 |11| | | | | | | | - // 3 | | | | | | | | | 3 | | o|77|66|55|44|33|22| - // 4 | | | | | | | | | 4 | | | | | | | | | - - let ptr = HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:2 }; - let literals = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - content: CopyOrMatchContent:0x77_6655_4433_2211, - length: CopyOrMatchLength:56, - last: false - }; - assert_eq( - literal_packet_to_single_write_req(ptr, literals, RamNumber:0), - TestWriteReq { data: RamData:0x22, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }); - assert_eq( - literal_packet_to_single_write_req(ptr, literals, RamNumber:3), - TestWriteReq { data: RamData:0x55, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }); - assert_eq( - literal_packet_to_single_write_req(ptr, literals, RamNumber:6), - zero!()); -} - -fn literal_packet_to_write_reqs - - (ptr: HistoryBufferPtr, literal: SequenceExecutorPacket) - -> (ram::WriteReq[RAM_NUM], HistoryBufferPtr) { - type WriteReq = ram::WriteReq; - let result = WriteReq[RAM_NUM]:[ - literal_packet_to_single_write_req(ptr, literal, RamNumber:0), - literal_packet_to_single_write_req(ptr, literal, RamNumber:1), - literal_packet_to_single_write_req(ptr, literal, RamNumber:2), - literal_packet_to_single_write_req(ptr, literal, RamNumber:3), - literal_packet_to_single_write_req(ptr, literal, RamNumber:4), - literal_packet_to_single_write_req(ptr, literal, RamNumber:5), - literal_packet_to_single_write_req(ptr, literal, RamNumber:6), - literal_packet_to_single_write_req(ptr, literal, RamNumber:7), - ]; - - let ptr_offset = literal.length >> CopyOrMatchLength:3; - (result, hb_ptr_from_offset_forw(ptr, ptr_offset as Offset)) -} - -#[test] -fn test_literal_packet_to_write_reqs() { - // BEFORE: AFTER: - // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 - // 1 | | | | | | | | | 1 | | | | | | | | | - // 2 | o| | | | | | | | 2 |11| | | | | | | | - // 3 | | | | | | | | | 3 | | | | | | | | o| - // 4 | | | | | | | | | 4 | | | | | | | | | - - let ptr = HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:0x2 }; - let literals = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - content: CopyOrMatchContent:0x11, - length: CopyOrMatchLength:8, - last: false - }; - assert_eq( - literal_packet_to_write_reqs(ptr, literals), - ( - TestWriteReq[RAM_NUM]:[ - zero!(), zero!(), zero!(), - zero!(), zero!(), zero!(), - zero!(), - TestWriteReq { data: RamData:0x11, addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, - ], HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0x3 }, - )); - - // BEFORE: AFTER: - // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 - // 1 | | | | | | | | | 1 | | | | | | | | | - // 2 | o| | | | | | | | 2 |11| | | | | | | | - // 3 | | | | | | | | | 3 | o|88|77|66|55|44|33|22| - // 4 | | | | | | | | | 4 | | | | | | | | | - - let ptr = HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:2 }; - let literals = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - content: CopyOrMatchContent:0x8877_6655_4433_2211, - length: CopyOrMatchLength:64, - last: false - }; - assert_eq( - literal_packet_to_write_reqs(ptr, literals), - ( - TestWriteReq[RAM_NUM]:[ - TestWriteReq { data: RamData:0x22, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x33, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x44, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x55, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x66, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x77, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x88, addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestWriteReq { data: RamData:0x11, addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, - ], HistoryBufferPtr { number: RamNumber:7, addr: TestRamAddr:3 }, - )); -} - -fn max_hb_ptr_for_sequence_packet - - (ptr: HistoryBufferPtr, seq: SequenceExecutorPacket) - -> HistoryBufferPtr { - hb_ptr_from_offset_back(ptr, seq.content as Offset) -} - -fn sequence_packet_to_single_read_req - - (ptr: HistoryBufferPtr, max_ptr: HistoryBufferPtr, - seq: SequenceExecutorPacket, number: RamNumber) - -> (ram::ReadReq, RamOrder) { - type ReadReq = ram::ReadReq; - let offset_change = if max_ptr.number > number { - RAM_NUM - max_ptr.number as u32 + number as u32 - } else { - number as u32 - max_ptr.number as u32 - }; - let offset = (seq.content as u32 - offset_change) as Offset; - let re = (offset_change as CopyOrMatchLength) < seq.length; - let hb = hb_ptr_from_offset_back(ptr, offset); - - if re { - (ReadReq { addr: hb.addr, mask: RAM_REQ_MASK_ALL }, offset_change as RamOrder) - } else { - (zero!(), RamOrder:0) - } -} - -#[test] -fn test_sequence_packet_to_single_read_req() { - // BEFORE: AFTER: - // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 - // 1 | x| x| | | | | | | 1 | | | | | | | | | - // 2 | | | | | | | x| x| 2 | | | | | | | | | - // 3 | | | | | | | o| | 3 | | | o| y| y| y| y| | - // 4 | | | | | | | | | 4 | | | | | | | | | - - let ptr = HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:0x3 }; - let sequence = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - content: CopyOrMatchContent:11, - length: CopyOrMatchLength:4, - last: false - }; - let max_ptr = max_hb_ptr_for_sequence_packet(ptr, sequence); - - assert_eq( - sequence_packet_to_single_read_req( - ptr, max_ptr, sequence, RamNumber:0), - (TestReadReq { addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, RamOrder:2)); - - assert_eq( - sequence_packet_to_single_read_req( - ptr, max_ptr, sequence, RamNumber:1), - (TestReadReq { addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, RamOrder:3)); - - assert_eq( - sequence_packet_to_single_read_req( - ptr, max_ptr, sequence, RamNumber:2), (zero!(), RamOrder:0)); - - assert_eq( - sequence_packet_to_single_read_req( - ptr, max_ptr, sequence, RamNumber:7), - (TestReadReq { addr: TestRamAddr:0x1, mask: RAM_REQ_MASK_ALL }, RamOrder:1)); + let content = CopyOrMatchContent:0xAA00_BB11_CC22_DD33; + let length = CopyOrMatchLength:8; + let last = false; assert_eq( - sequence_packet_to_single_read_req( - ptr, max_ptr, sequence, RamNumber:6), - (TestReadReq { addr: TestRamAddr:0x1, mask: RAM_REQ_MASK_ALL }, RamOrder:0)); -} - -fn sequence_packet_to_read_reqs - - (ptr: HistoryBufferPtr, seq: SequenceExecutorPacket, hb_len: HistoryBufferLength) - -> (ram::ReadReq[RAM_NUM], RamOrder[RAM_NUM], SequenceExecutorPacket, bool) { - type ReadReq = ram::ReadReq; - - let max_len = std::min(seq.length as u32, std::min(RAM_NUM, hb_len)); - - let (next_seq, next_seq_valid) = if seq.length > max_len as CopyOrMatchLength { - ( + decode_literal_packet( SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: seq.length - max_len as CopyOrMatchLength, - content: seq.content, - last: seq.last - }, true, - ) - } else { - (zero!(), false) - }; - - let max_ptr = max_hb_ptr_for_sequence_packet(ptr, seq); - let (req0, order0) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:0); - let (req1, order1) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:1); - let (req2, order2) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:2); - let (req3, order3) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:3); - let (req4, order4) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:4); - let (req5, order5) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:5); - let (req6, order6) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:6); - let (req7, order7) = - sequence_packet_to_single_read_req(ptr, max_ptr, seq, RamNumber:7); - - let reqs = ReadReq[RAM_NUM]:[req0, req1, req2, req3, req4, req5, req6, req7]; - let orders = RamOrder[RAM_NUM]:[order0, order1, order2, order3, order4, order5, order6, order7]; - (reqs, orders, next_seq, next_seq_valid) -} - -#[test] -fn test_sequence_packet_to_read_reqs() { - // BEFORE: AFTER: - // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 - // 1 | x| x| | | | | | | 1 | | | | | | | | | - // 2 | | | | | | | x| x| 2 | | | | | | | | | - // 3 | | | | | | | o| | 3 | | | | | | | o| | - // 4 | | | | | | | | | 4 | | | | | | | | | - - let ptr = HistoryBufferPtr { number: RamNumber:1, addr: TestRamAddr:0x3 }; - let sequence = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - content: CopyOrMatchContent:11, - length: CopyOrMatchLength:4, - last: false - }; - let result = sequence_packet_to_read_reqs( - ptr, sequence, HistoryBufferLength:20); - let expected = ( - TestReadReq[RAM_NUM]:[ - TestReadReq { addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, zero!(), - zero!(), zero!(), zero!(), - TestReadReq { addr: TestRamAddr:0x1, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x1, mask: RAM_REQ_MASK_ALL }, - ], - RamOrder[RAM_NUM]:[ - RamOrder:2, RamOrder:3, zero!(), zero!(), zero!(), - zero!(), RamOrder:0, RamOrder:1, - ], zero!(), false, - ); - assert_eq(result, expected); - - // BEFORE: AFTER: - // 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 - // 1 | | | | | | | | | 1 | | | | | | | | | - // 2 | x| x| | | | | | | 2 | | | | | | | | | - // 3 | | | x| x| x| x| x| x| 3 | | x| | | | | | | - // 4 | | | | | | | | o| 4 | | | | | | | | o| - - let ptr = HistoryBufferPtr { number: RamNumber:0, addr: TestRamAddr:0x4 }; - let sequence = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - content: CopyOrMatchContent:10, - length: CopyOrMatchLength:9, - last: false - }; - let result = sequence_packet_to_read_reqs( - ptr, sequence, HistoryBufferLength:20); - let expected = ( - TestReadReq[RAM_NUM]:[ - TestReadReq { addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x3, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, - TestReadReq { addr: TestRamAddr:0x2, mask: RAM_REQ_MASK_ALL }, - ], - RamOrder[RAM_NUM]:[ - RamOrder:2, RamOrder:3, RamOrder:4, RamOrder:5, RamOrder:6, RamOrder:7, RamOrder:0, - RamOrder:1, - ], - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - content: CopyOrMatchContent:10, - length: CopyOrMatchLength:1, + msg_type: SequenceExecutorMessageType::LITERAL, + length, + content, + last + } + ), + MemWriterDataPacket { + data: uN[DATA_W]:0xAA00BB11CC22DD33, + length: uN[ADDR_W]:8, last: false - }, true, - ); - assert_eq(result, expected); -} - -struct RamWrRespHandlerData { - resp: bool[RAM_NUM], - ptr: HistoryBufferPtr, -} - -fn create_ram_wr_data - (reqs: ram::WriteReq[RAM_NUM], ptr: HistoryBufferPtr) -> (bool, RamWrRespHandlerData) { - let do_write = for (i, do_write): (u32, bool) in u32:0..RAM_NUM { - do_write || reqs[i].mask - }(false); - - let resp = bool[RAM_NUM]:[ - ((reqs[0]).mask != RAM_REQ_MASK_NONE), - ((reqs[1]).mask != RAM_REQ_MASK_NONE), - ((reqs[2]).mask != RAM_REQ_MASK_NONE), - ((reqs[3]).mask != RAM_REQ_MASK_NONE), - ((reqs[4]).mask != RAM_REQ_MASK_NONE), - ((reqs[5]).mask != RAM_REQ_MASK_NONE), - ((reqs[6]).mask != RAM_REQ_MASK_NONE), - ((reqs[7]).mask != RAM_REQ_MASK_NONE), - ]; - - (do_write, RamWrRespHandlerData { resp, ptr }) -} - -proc RamWrRespHandler { - input_r: chan in; - output_s: chan out; - wr_resp_m0_r: chan in; - wr_resp_m1_r: chan in; - wr_resp_m2_r: chan in; - wr_resp_m3_r: chan in; - wr_resp_m4_r: chan in; - wr_resp_m5_r: chan in; - wr_resp_m6_r: chan in; - wr_resp_m7_r: chan in; - - config(input_r: chan> in, - output_s: chan> out, - wr_resp_m0_r: chan in, wr_resp_m1_r: chan in, - wr_resp_m2_r: chan in, wr_resp_m3_r: chan in, - wr_resp_m4_r: chan in, wr_resp_m5_r: chan in, - wr_resp_m6_r: chan in, wr_resp_m7_r: chan in) { - ( - input_r, output_s, wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, - wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, - ) - } - - init { } - - next(state: ()) { - let tok0 = join(); - let (tok1, input) = recv(tok0, input_r); - - let (tok2_0, _) = recv_if(tok1, wr_resp_m0_r, input.resp[0], zero!()); - let (tok2_1, _) = recv_if(tok1, wr_resp_m1_r, input.resp[1], zero!()); - let (tok2_2, _) = recv_if(tok1, wr_resp_m2_r, input.resp[2], zero!()); - let (tok2_3, _) = recv_if(tok1, wr_resp_m3_r, input.resp[3], zero!()); - let (tok2_4, _) = recv_if(tok1, wr_resp_m4_r, input.resp[4], zero!()); - let (tok2_5, _) = recv_if(tok1, wr_resp_m5_r, input.resp[5], zero!()); - let (tok2_6, _) = recv_if(tok1, wr_resp_m6_r, input.resp[6], zero!()); - let (tok2_7, _) = recv_if(tok1, wr_resp_m7_r, input.resp[7], zero!()); - let tok2 = join(tok2_0, tok2_1, tok2_2, tok2_3, tok2_4, tok2_5, tok2_6, tok2_7); - - let tok3 = send(tok2, output_s, input.ptr); - } -} - -struct RamRdRespHandlerData { - resp: bool[RAM_NUM], - order: RamOrder[RAM_NUM], - last: bool -} - -fn create_ram_rd_data - (reqs: ram::ReadReq[RAM_NUM], order: RamOrder[RAM_NUM], last: bool, next_packet_valid: bool) -> (bool, RamRdRespHandlerData) { - let do_read = for (i, do_read): (u32, bool) in u32:0..RAM_NUM { - do_read || reqs[i].mask - }(false); - - let resp = bool[RAM_NUM]:[ - ((reqs[0]).mask != RAM_REQ_MASK_NONE), - ((reqs[1]).mask != RAM_REQ_MASK_NONE), - ((reqs[2]).mask != RAM_REQ_MASK_NONE), - ((reqs[3]).mask != RAM_REQ_MASK_NONE), - ((reqs[4]).mask != RAM_REQ_MASK_NONE), - ((reqs[5]).mask != RAM_REQ_MASK_NONE), - ((reqs[6]).mask != RAM_REQ_MASK_NONE), - ((reqs[7]).mask != RAM_REQ_MASK_NONE), - ]; - - let last = if next_packet_valid { false } else { last }; - (do_read, RamRdRespHandlerData { resp, order, last }) -} - -proc RamRdRespHandler { - input_r: chan in; - output_s: chan out; - rd_resp_m0_r: chan> in; - rd_resp_m1_r: chan> in; - rd_resp_m2_r: chan> in; - rd_resp_m3_r: chan> in; - rd_resp_m4_r: chan> in; - rd_resp_m5_r: chan> in; - rd_resp_m6_r: chan> in; - rd_resp_m7_r: chan> in; - - config(input_r: chan in, output_s: chan out, - rd_resp_m0_r: chan> in, - rd_resp_m1_r: chan> in, - rd_resp_m2_r: chan> in, - rd_resp_m3_r: chan> in, - rd_resp_m4_r: chan> in, - rd_resp_m5_r: chan> in, - rd_resp_m6_r: chan> in, - rd_resp_m7_r: chan> in) { - ( - input_r, output_s, rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, rd_resp_m4_r, - rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, - ) - } - - init { } - - next(state: ()) { - let tok0 = join(); - type ReadResp = ram::ReadResp; - - let (tok1, input) = recv(tok0, input_r); - - let (tok2_0, resp_0) = recv_if(tok1, rd_resp_m0_r, input.resp[0], zero!()); - let (tok2_1, resp_1) = recv_if(tok1, rd_resp_m1_r, input.resp[1], zero!()); - let (tok2_2, resp_2) = recv_if(tok1, rd_resp_m2_r, input.resp[2], zero!()); - let (tok2_3, resp_3) = recv_if(tok1, rd_resp_m3_r, input.resp[3], zero!()); - let (tok2_4, resp_4) = recv_if(tok1, rd_resp_m4_r, input.resp[4], zero!()); - let (tok2_5, resp_5) = recv_if(tok1, rd_resp_m5_r, input.resp[5], zero!()); - let (tok2_6, resp_6) = recv_if(tok1, rd_resp_m6_r, input.resp[6], zero!()); - let (tok2_7, resp_7) = recv_if(tok1, rd_resp_m7_r, input.resp[7], zero!()); - let tok2 = join(tok2_0, tok2_1, tok2_2, tok2_3, tok2_4, tok2_5, tok2_6, tok2_7); - - let content = (resp_0.data as CopyOrMatchContent) << (input.order[0] as CopyOrMatchContent << 3) | - (resp_1.data as CopyOrMatchContent) << (input.order[1] as CopyOrMatchContent << 3) | - (resp_2.data as CopyOrMatchContent) << (input.order[2] as CopyOrMatchContent << 3) | - (resp_3.data as CopyOrMatchContent) << (input.order[3] as CopyOrMatchContent << 3) | - (resp_4.data as CopyOrMatchContent) << (input.order[4] as CopyOrMatchContent << 3) | - (resp_5.data as CopyOrMatchContent) << (input.order[5] as CopyOrMatchContent << 3) | - (resp_6.data as CopyOrMatchContent) << (input.order[6] as CopyOrMatchContent << 3) | - (resp_7.data as CopyOrMatchContent) << (input.order[7] as CopyOrMatchContent << 3); - - let converted = std::convert_to_bits_msb0(input.resp); - let length = std::popcount(converted) << 3; - - let output_data = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: length as CopyOrMatchLength, - content: content as CopyOrMatchContent, - last: input.last, - }; - - let tok3 = send(tok2, output_s, output_data); - } + } + ) } -fn handle_reapeated_offset_for_sequences +pub fn handle_repeated_offset_for_sequences (seq: SequenceExecutorPacket, repeat_offsets: Offset[3], repeat_req: bool) -> (SequenceExecutorPacket, Offset[3]) { + type Packet = SequenceExecutorPacket; + type Content = uN[RAM_DATA_WIDTH * u32:8]; let modified_repeat_offsets = if repeat_req { Offset[3]:[repeat_offsets[1], repeat_offsets[2], repeat_offsets[0] - Offset:1] } else { repeat_offsets }; - let (seq, final_repeat_offsets) = if seq.content == CopyOrMatchContent:0 { + let (seq, final_repeat_offsets) = if seq.content == Content:0 { fail!( "match_offset_zero_not_allowed", - (zero!(), Offset[3]:[Offset:0, ...])) - } else if seq.content == CopyOrMatchContent:1 { + (zero!(), Offset[3]:[Offset:0, ...])) + } else if seq.content == Content:1 { let offset = modified_repeat_offsets[0]; ( - SequenceExecutorPacket { content: offset as CopyOrMatchContent, ..seq }, + Packet { content: offset as Content, ..seq }, Offset[3]:[ offset, repeat_offsets[1], repeat_offsets[2], ], @@ -815,7 +156,7 @@ fn handle_reapeated_offset_for_sequences } else if seq.content == CopyOrMatchContent:2 { let offset = modified_repeat_offsets[1]; ( - SequenceExecutorPacket { content: offset as CopyOrMatchContent, ..seq }, + Packet { content: offset as Content, ..seq }, Offset[3]:[ offset, repeat_offsets[0], repeat_offsets[2], ], @@ -823,7 +164,7 @@ fn handle_reapeated_offset_for_sequences } else if seq.content == CopyOrMatchContent:3 { let offset = modified_repeat_offsets[2]; ( - SequenceExecutorPacket { content: offset as CopyOrMatchContent, ..seq }, + Packet { content: offset as Content, ..seq }, Offset[3]:[ offset, repeat_offsets[0], repeat_offsets[1], ], @@ -831,7 +172,7 @@ fn handle_reapeated_offset_for_sequences } else { let offset = seq.content as Offset - Offset:3; ( - SequenceExecutorPacket { content: offset as CopyOrMatchContent, ..seq }, + Packet { content: offset as Content, ..seq }, Offset[3]:[ offset, repeat_offsets[0], repeat_offsets[1], ], @@ -842,10 +183,10 @@ fn handle_reapeated_offset_for_sequences pub proc SequenceExecutor { type MemWriterDataPacket = mem_writer::MemWriterDataPacket; @@ -853,7 +194,7 @@ pub proc SequenceExecutor in; output_mem_wr_data_in_s: chan out; ram_comp_input_s: chan> out; - ram_comp_output_r: chan> in; + ram_comp_output_r: chan> in; ram_resp_input_s: chan out; ram_resp_output_r: chan in; rd_req_m0_s: chan> out; @@ -912,15 +253,15 @@ pub proc SequenceExecutor in ) { let (ram_comp_input_s, ram_comp_input_r) = chan, u32:1>("ram_comp_input"); - let (ram_comp_output_s, ram_comp_output_r) = chan, u32:1>("ram_comp_output"); + let (ram_comp_output_s, ram_comp_output_r) = chan, u32:1>("ram_comp_output"); let (ram_resp_input_s, ram_resp_input_r) = chan("ram_resp_input"); - spawn RamWrRespHandler( + spawn parallel_rams::RamWrRespHandler( ram_comp_input_r, ram_comp_output_s, wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r); - spawn RamRdRespHandler( + spawn parallel_rams::RamRdRespHandler( ram_resp_input_r, ram_resp_output_s, rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r); @@ -950,7 +291,7 @@ pub proc SequenceExecutor; type WriteReq = ram::WriteReq; type WriteResp = ram::WriteResp; + type HistoryBufferLength = uN[RAM_ADDR_WIDTH + RAM_NUM_CLOG2]; const ZERO_READ_REQS = ReadReq[RAM_NUM]:[zero!(), ...]; const ZERO_WRITE_REQS = WriteReq[RAM_NUM]:[zero!(), ...]; - const ZERO_ORDER = RamOrder[RAM_NUM]:[RamOrder:0, ...]; // Recieve literals and sequences from the input channel ... let do_recv_input = !state.packet_valid && state.status != Status::SEQUENCE_READ && @@ -989,13 +330,13 @@ pub proc SequenceExecutor()); - if real_ptr_valid { + let (tok1_2, wr_resp, wr_resp_valid) = + recv_non_blocking(tok0, ram_comp_output_r, zero!()); + if wr_resp_valid { trace_fmt!("SequenceExecutor:: Received completion update"); } else { }; - let real_ptr = if real_ptr_valid { real_ptr } else { state.real_ptr }; + let real_ptr = if wr_resp_valid { wr_resp.ptr } else { state.real_ptr }; let tok1 = join(tok1_0, tok1_1, tok1_2); // Since we either get data from input, from frame, or from state, @@ -1020,22 +361,23 @@ pub proc SequenceExecutor { trace_fmt!("SequenceExecutor:: Handling LITERAL packet in LITERAL_WRITE step"); let (write_reqs, new_hyp_ptr) = - literal_packet_to_write_reqs(state.hyp_ptr, packet); + parallel_rams::literal_packet_to_write_reqs(state.hyp_ptr, packet); let new_repeat_req = packet.length == CopyOrMatchLength:0; - let hb_add = (packet.length >> 3) as HistoryBufferLength; - let new_hb_len = std::mod_pow2(state.hb_len + hb_add, RAM_SIZE_TOTAL); + let hb_add = packet.length as HistoryBufferLength; + let new_hb_len = std::mod_pow2(state.hb_len + hb_add, RAM_SIZE_TOTAL as uN[RAM_ADDR_WIDTH + RAM_NUM_CLOG2]); + ( - write_reqs, ZERO_READ_REQS, ZERO_ORDER, + write_reqs, ZERO_READ_REQS, RamReadStart:0, RamReadLen:0, State { status: Status::LITERAL_WRITE, - packet: zero!(), + packet: zero!(), packet_valid: false, hyp_ptr: new_hyp_ptr, real_ptr, @@ -1050,7 +392,7 @@ pub proc SequenceExecutor { trace_fmt!("Handling SEQUENCE in SEQUENCE_READ state"); let (packet, new_repeat_offsets) = if !state.seq_cnt { - handle_reapeated_offset_for_sequences( + handle_repeated_offset_for_sequences( packet, state.repeat_offsets, state.repeat_req) } else { (packet, state.repeat_offsets) }; - let (read_reqs, order, packet, packet_valid) = sequence_packet_to_read_reqs< + let (read_reqs, read_start, read_len, packet, packet_valid) = parallel_rams::sequence_packet_to_read_reqs< HISTORY_BUFFER_SIZE_KB>( state.hyp_ptr, packet, state.hb_len); ( - ZERO_WRITE_REQS, read_reqs, order, + ZERO_WRITE_REQS, read_reqs, read_start, read_len, SequenceExecutorState { status: Status::SEQUENCE_WRITE, packet, @@ -1083,19 +425,19 @@ pub proc SequenceExecutor { - let ZERO_RETURN = (ZERO_WRITE_REQS, ZERO_READ_REQS, ZERO_ORDER, zero!()); - fail!("should_no_happen", (ZERO_RETURN)) + let ZERO_RETURN = (ZERO_WRITE_REQS, ZERO_READ_REQS, RamReadStart:0, RamReadLen:0, zero!()); + fail!("should_not_happen", (ZERO_RETURN)) }, // Handling SEQUENCE_WRITE (Status::SEQUENCE_WRITE, true, MsgType::LITERAL) => { trace_fmt!("Handling LITERAL in SEQUENCE_WRITE state: {}", status); let (write_reqs, new_hyp_ptr) = - literal_packet_to_write_reqs(state.hyp_ptr, packet); + parallel_rams::literal_packet_to_write_reqs(state.hyp_ptr, packet); let hb_add = packet.length as HistoryBufferLength; - let new_hb_len = std::mod_pow2(state.hb_len + hb_add, RAM_SIZE_TOTAL); + let new_hb_len = std::mod_pow2(state.hb_len + hb_add, RAM_SIZE_TOTAL as uN[RAM_ADDR_WIDTH + RAM_NUM_CLOG2]); ( - write_reqs, ZERO_READ_REQS, ZERO_ORDER, + write_reqs, ZERO_READ_REQS, RamReadStart:0, RamReadLen:0, SequenceExecutorState { status: zero!(), packet: state.packet, @@ -1118,7 +460,7 @@ pub proc SequenceExecutor { let status = Status::IDLE; ( - ZERO_WRITE_REQS, ZERO_READ_REQS, ZERO_ORDER, + ZERO_WRITE_REQS, ZERO_READ_REQS, RamReadStart:0, RamReadLen:0, State { status, ..NO_VALID_PACKET_STATE }, ) }, @@ -1142,14 +484,14 @@ pub proc SequenceExecutor(decode_literal_packet(packet)); + let output_mem_wr_data_in = decode_literal_packet(packet); if do_write_output { trace_fmt!("Sending output MemWriter data: {:#x}", output_mem_wr_data_in); } else { }; let tok2_10_1 = send_if(tok1, output_mem_wr_data_in_s, do_write_output, output_mem_wr_data_in); @@ -1164,8 +506,8 @@ pub proc SequenceExecutor - (read_reqs, order, packet.last, new_state.packet_valid); + parallel_rams::create_ram_rd_data + (read_reqs, read_start, read_len, packet.last, new_state.packet_valid); if do_read { trace_fmt!("Sending request to RamRdRespHandler: {:#x}", rd_resp_handler_data); } else { }; @@ -1176,8 +518,8 @@ pub proc SequenceExecutor; terminator: chan out; - input_s: chan> out; + input_s: chan out; output_mem_wr_data_in_r: chan in; print_start_s: chan<()> out; @@ -1353,7 +695,7 @@ proc SequenceExecutorLiteralsTest { ram_wr_resp_r: chan[RAM_NUM] in; config(terminator: chan out) { - let (input_s, input_r) = chan>("input"); + let (input_s, input_r) = chan("input"); let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); let (looped_channel_s, looped_channel_r) = chan("looped_channels"); @@ -1443,8 +785,7 @@ proc SequenceExecutorLiteralsTest { if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || LITERAL_TEST_INPUT_DATA[i].last) { - let expected = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); - let expected_mem_writer_data = convert_output_packet(expected); + let expected_mem_writer_data = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(expected_mem_writer_data, recv_mem_writer_data); } else {} @@ -1702,8 +1043,7 @@ proc SequenceExecutorSequenceTest { if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || LITERAL_TEST_INPUT_DATA[i].last) { - let expected = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); - let expected_mem_writer_data = convert_output_packet(expected); + let expected_mem_writer_data = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); assert_eq(expected_mem_writer_data, recv_mem_writer_data); } else {} diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index 7bbd356cf4..4657e9845a 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -908,7 +908,7 @@ pub proc ZstdDecoder< type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; - type SequenceExecutorPacket = common::SequenceExecutorPacket; + type SequenceExecutorPacket = common::SequenceExecutorPacket; type ZstdDecodedPacket = common::ZstdDecodedPacket; type RamRdReq = ram::ReadReq; From a2d63f650d7c5c0b215063a5822bb2bbd2a00d7b Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Tue, 19 Nov 2024 15:24:58 +0100 Subject: [PATCH 41/85] modules/zstd: Add Huffman literals decoder Signed-off-by: Maciej Torhan Co-authored-by: Maciej Dudek --- xls/modules/zstd/BUILD | 583 +++++++++++++++ xls/modules/zstd/fifo.v | 52 ++ xls/modules/zstd/huffman_axi_reader.x | 282 ++++++++ xls/modules/zstd/huffman_code_builder.x | 431 +++++++++++ xls/modules/zstd/huffman_common.x | 64 ++ xls/modules/zstd/huffman_ctrl.x | 284 ++++++++ xls/modules/zstd/huffman_data_preprocessor.x | 422 +++++++++++ xls/modules/zstd/huffman_decoder.x | 724 +++++++++++++++++++ xls/modules/zstd/huffman_literals_dec.x | 547 ++++++++++++++ xls/modules/zstd/huffman_prescan.x | 431 +++++++++++ 10 files changed, 3820 insertions(+) create mode 100644 xls/modules/zstd/fifo.v create mode 100644 xls/modules/zstd/huffman_axi_reader.x create mode 100644 xls/modules/zstd/huffman_code_builder.x create mode 100644 xls/modules/zstd/huffman_common.x create mode 100644 xls/modules/zstd/huffman_ctrl.x create mode 100644 xls/modules/zstd/huffman_data_preprocessor.x create mode 100644 xls/modules/zstd/huffman_decoder.x create mode 100644 xls/modules/zstd/huffman_literals_dec.x create mode 100644 xls/modules/zstd/huffman_prescan.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 9fe726bbe2..19c2595e26 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -2232,3 +2232,586 @@ place_and_route( synthesized_rtl = ":literals_decoder_synth_asap7", target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "huffman_common_dslx", + srcs = [ + "huffman_common.x", + ], + deps = [], +) + +xls_dslx_library( + name = "huffman_prescan_dslx", + srcs = [ + "huffman_prescan.x", + ], + deps = [ + "//xls/examples:ram_dslx", + "//xls/dslx/stdlib:acm_random_dslx", + ":common_dslx", + ":huffman_common_dslx", + ], +) + +xls_dslx_test( + name = "huffman_prescan_dslx_test", + library = ":huffman_prescan_dslx", +) + +prescan_codegen_args = common_codegen_args | { + "module_name": "HuffmanPrescan", + "pipeline_stages": "16", + "clock_period_ps": "750", + "worst_case_throughput": "1", + "ram_configurations": + "InternalRam:1R1W:huffman_prescan__internal_read_req_s" + + ":huffman_prescan__internal_read_rsp_r:" + + "huffman_prescan__internal_write_req_s:" + + "huffman_prescan__internal_write_rsp_r:5", + "io_constraints" : "huffman_prescan__read_req_s:send:" + + "huffman_prescan__read_rsp_r:recv:5:5", +} + +xls_dslx_verilog( + name = "huffman_prescan_verilog", + codegen_args = prescan_codegen_args, + dslx_top = "WeightPreScan", + library = ":huffman_prescan_dslx", + verilog_file = "huffman_prescan.v", +) + +xls_benchmark_ir( + name = "huffman_prescan_opt_ir_benchmark", + src = ":huffman_prescan_verilog.opt.ir", + benchmark_ir_args = prescan_codegen_args, +) + +xls_benchmark_verilog( + name = "huffman_prescan_verilog_benchmark", + verilog_target = "huffman_prescan_verilog", +) + +verilog_library( + name = "huffman_prescan_verilog_lib", + srcs = [ + ":huffman_prescan.v", + "fifo.v" + ], +) + +synthesize_rtl( + name = "huffman_prescan_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "HuffmanPrescan", + deps = [ + ":huffman_prescan_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_prescan_benchmark_synth", + synth_target = ":huffman_prescan_synth_asap7", +) + +place_and_route( + name = "huffman_prescan_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + synthesized_rtl = ":huffman_prescan_synth_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "huffman_code_builder_dslx", + srcs = [ + "huffman_code_builder.x", + ], + deps = [ + "//xls/examples:ram_dslx", + "//xls/dslx/stdlib:acm_random_dslx", + ":common_dslx", + ":huffman_common_dslx", + ], +) + +xls_dslx_test( + name = "huffman_code_builder_dslx_test", + library = ":huffman_code_builder_dslx", +) + +huffman_code_builder_codegen_args = common_codegen_args | { + "module_name": "HuffmanCodeBuilder", + "pipeline_stages": "8", + "clock_period_ps": "750", + "worst_case_throughput": "1", + "io_constraints" : "huffman_code_builder__weight_r:recv:" + + "huffman_code_builder__codes_s:send:2:2", +} + +xls_dslx_verilog( + name = "huffman_code_builder_verilog", + codegen_args = huffman_code_builder_codegen_args, + dslx_top = "WeightCodeBuilder", + library = ":huffman_code_builder_dslx", + verilog_file = "huffman_code_builder.v", +) + +xls_benchmark_ir( + name = "huffman_code_builder_opt_ir_benchmark", + src = ":huffman_code_builder_verilog.opt.ir", + benchmark_ir_args = huffman_code_builder_codegen_args, +) + +xls_benchmark_verilog( + name = "huffman_code_builder_verilog_benchmark", + verilog_target = "huffman_code_builder_verilog", +) + +verilog_library( + name = "huffman_code_builder_verilog_lib", + srcs = [ + ":huffman_code_builder.v", + "fifo.v" + ], +) + +synthesize_rtl( + name = "huffman_code_builder_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "HuffmanCodeBuilder", + deps = [ + ":huffman_code_builder_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_code_builder_benchmark_synth", + synth_target = ":huffman_code_builder_synth_asap7", +) + +place_and_route( + name = "huffman_code_builder_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + synthesized_rtl = ":huffman_code_builder_synth_asap7", + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "huffman_axi_reader_dslx", + srcs = [ + "huffman_axi_reader.x", + ], + deps = [ + "//xls/modules/zstd/memory:axi_dslx", + ], +) + +xls_dslx_test( + name = "huffman_axi_reader_dslx_test", + library = ":huffman_axi_reader_dslx", + tags = ["manual"], +) + +huffman_axi_reader_codegen_args = common_codegen_args | { + "module_name": "HuffmanAxiReader", + "pipeline_stages": "8", + "clock_period_ps": "750", + "worst_case_throughput": "2", +} + +xls_dslx_verilog( + name = "huffman_axi_reader_verilog", + codegen_args = huffman_axi_reader_codegen_args, + dslx_top = "HuffmanAxiReaderInst", + library = ":huffman_axi_reader_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__huffman_axi_reader__HuffmanAxiReaderInst__HuffmanAxiReader_0__32_32_32_next", + }, + tags = ["manual"], + verilog_file = "huffman_axi_reader.v", +) + +xls_benchmark_ir( + name = "huffman_axi_reader_opt_ir_benchmark", + src = ":huffman_axi_reader_verilog.opt.ir", + benchmark_ir_args = huffman_axi_reader_codegen_args, + tags = ["manual"], +) + +verilog_library( + name = "huffman_axi_reader_verilog_lib", + srcs = [ + ":huffman_axi_reader.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "huffman_axi_reader_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "HuffmanAxiReader", + deps = [ + ":huffman_axi_reader_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_axi_reader_benchmark_synth", + synth_target = ":huffman_axi_reader_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "huffman_axi_reader_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":huffman_axi_reader_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "huffman_data_preprocessor_dslx", + srcs = [ + "huffman_data_preprocessor.x", + ], + deps = [ + ":common_dslx", + ":huffman_axi_reader_dslx", + ":huffman_common_dslx", + ], +) + +xls_dslx_test( + name = "huffman_data_preprocessor_dslx_test", + library = ":huffman_data_preprocessor_dslx", + tags = ["manual"], +) + +huffman_data_preprocessor_codegen_args = common_codegen_args | { + "module_name": "HuffmanDataPreprocessor", + "pipeline_stages": "36", + "clock_period_ps": "810", + "clock_margin_percent": "0", + "worst_case_throughput": "1", +} + +xls_dslx_verilog( + name = "huffman_data_preprocessor_verilog", + codegen_args = huffman_data_preprocessor_codegen_args, + dslx_top = "HuffmanDataPreprocessor", + library = ":huffman_data_preprocessor_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "", + }, + tags = ["manual"], + verilog_file = "huffman_data_preprocessor.v", +) + +xls_benchmark_ir( + name = "huffman_data_preprocessor_opt_ir_benchmark", + src = ":huffman_data_preprocessor_verilog.opt.ir", + benchmark_ir_args = huffman_data_preprocessor_codegen_args, + tags = ["manual"], +) + +verilog_library( + name = "huffman_data_preprocessor_verilog_lib", + srcs = [ + ":huffman_data_preprocessor.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "huffman_data_preprocessor_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "HuffmanDataPreprocessor", + deps = [ + ":huffman_data_preprocessor_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_data_preprocessor_benchmark_synth", + synth_target = ":huffman_data_preprocessor_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "huffman_data_preprocessor_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":huffman_data_preprocessor_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "huffman_decoder_dslx", + srcs = [ + "huffman_decoder.x", + ], + deps = [ + ":common_dslx", + ":huffman_common_dslx", + ":huffman_data_preprocessor_dslx", + ], +) + +xls_dslx_test( + name = "huffman_decoder_dslx_test", + library = ":huffman_decoder_dslx", + tags = ["manual"], +) + +huffman_decoder_codegen_args = common_codegen_args | { + "module_name": "HuffmanDecoder", + "pipeline_stages": "8", + "clock_period_ps": "0", + "worst_case_throughput": "1", +} + +xls_dslx_verilog( + name = "huffman_decoder_verilog", + codegen_args = huffman_decoder_codegen_args, + dslx_top = "HuffmanDecoder", + library = ":huffman_decoder_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "", + }, + tags = ["manual"], + verilog_file = "huffman_decoder.v", +) + +xls_benchmark_ir( + name = "huffman_decoder_opt_ir_benchmark", + src = ":huffman_decoder_verilog.opt.ir", + benchmark_ir_args = huffman_decoder_codegen_args, + tags = ["manual"], +) + +verilog_library( + name = "huffman_decoder_verilog_lib", + srcs = [ + ":huffman_decoder.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "huffman_decoder_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "HuffmanDecoder", + deps = [ + ":huffman_decoder_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_decoder_benchmark_synth", + synth_target = ":huffman_decoder_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "huffman_decoder_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":huffman_decoder_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "huffman_ctrl_dslx", + srcs = [ + "huffman_ctrl.x", + ], + deps = [ + ":common_dslx", + ":huffman_axi_reader_dslx", + ":huffman_code_builder_dslx", + ":huffman_common_dslx", + ":huffman_data_preprocessor_dslx", + ":huffman_decoder_dslx", + ":huffman_prescan_dslx", + ], +) + +xls_dslx_test( + name = "huffman_ctrl_dslx_test", + library = ":huffman_ctrl_dslx", + tags = ["manual"], +) + +huffman_ctrl_codegen_args = common_codegen_args | { + "module_name": "HuffmanCtrl", + "pipeline_stages": "4", + "clock_period_ps": "750", + "worst_case_throughput": "1", +} + +xls_dslx_verilog( + name = "huffman_ctrl_verilog", + codegen_args = huffman_ctrl_codegen_args, + dslx_top = "HuffmanControlAndSequenceInst", + library = ":huffman_ctrl_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__huffman_ctrl__HuffmanControlAndSequenceInst__HuffmanControlAndSequence_0__32_next", + }, + tags = ["manual"], + verilog_file = "huffman_ctrl.v", +) + +xls_benchmark_ir( + name = "huffman_ctrl_opt_ir_benchmark", + src = ":huffman_ctrl_verilog.opt.ir", + benchmark_ir_args = huffman_ctrl_codegen_args, + tags = ["manual"], +) + +verilog_library( + name = "huffman_ctrl_verilog_lib", + srcs = [ + ":huffman_ctrl.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "huffman_ctrl_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "HuffmanCtrl", + deps = [ + ":huffman_ctrl_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_ctrl_benchmark_synth", + synth_target = ":huffman_ctrl_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "huffman_ctrl_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":huffman_ctrl_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + +xls_dslx_library( + name = "huffman_literals_dec_dslx", + srcs = [ + "huffman_literals_dec.x", + ], + deps = [ + ":common_dslx", + ":huffman_axi_reader_dslx", + ":huffman_code_builder_dslx", + ":huffman_common_dslx", + ":huffman_ctrl_dslx", + ":huffman_data_preprocessor_dslx", + ":huffman_decoder_dslx", + ":huffman_prescan_dslx", + ], +) + +xls_dslx_test( + name = "huffman_literals_dec_dslx_test", + library = ":huffman_literals_dec_dslx", + tags = ["manual"], +) + +huffman_literals_dec_codegen_args = common_codegen_args | { + "module_name": "HuffmanLiteralsDecoder", + "pipeline_stages": "64", + "clock_period_ps": "0", + "worst_case_throughput": "0", + "minimize_worst_case_throughput": "true", +} + +xls_dslx_verilog( + name = "huffman_literals_dec_verilog", + codegen_args = huffman_literals_dec_codegen_args, + dslx_top = "HuffmanLiteralsDecoderInst", + library = ":huffman_literals_dec_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__xls_modules_zstd_huffman_decoder__HuffmanLiteralsDecoderInst__HuffmanLiteralsDecoder_0__HuffmanDecoder_0_next", + }, + tags = ["manual"], + verilog_file = "huffman_literals_dec.v", +) + +xls_benchmark_ir( + name = "huffman_literals_dec_opt_ir_benchmark", + src = ":huffman_literals_dec_verilog.opt.ir", + benchmark_ir_args = huffman_literals_dec_codegen_args, + tags = ["manual"], +) + +verilog_library( + name = "huffman_literals_dec_verilog_lib", + srcs = [ + ":huffman_literals_dec.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "huffman_literals_dec_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "HuffmanLiteralsDecoder", + deps = [ + ":huffman_literals_dec_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_literals_dec_benchmark_synth", + synth_target = ":huffman_literals_dec_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "huffman_literals_dec_place_and_route", + clock_period = CLOCK_PERIOD_PS, + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":huffman_literals_dec_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) diff --git a/xls/modules/zstd/fifo.v b/xls/modules/zstd/fifo.v new file mode 100644 index 0000000000..3a1633b093 --- /dev/null +++ b/xls/modules/zstd/fifo.v @@ -0,0 +1,52 @@ +module xls_fifo_wrapper ( +clk, rst, +push_ready, push_data, push_valid, +pop_ready, pop_data, pop_valid); + parameter Width = 32, + Depth = 32, + EnableBypass = 0, + RegisterPushOutputs = 1, + RegisterPopOutputs = 1; + localparam AddrWidth = $clog2(Depth) + 1; + input wire clk; + input wire rst; + output wire push_ready; + input wire [Width-1:0] push_data; + input wire push_valid; + input wire pop_ready; + output wire [Width-1:0] pop_data; + output wire pop_valid; + + // Require depth be 1 and bypass disabled. + initial begin + if (EnableBypass || Depth != 1 || !RegisterPushOutputs || RegisterPopOutputs) begin + // FIFO configuration not supported. + // $fatal(1); + end + end + + + reg [Width-1:0] mem; + reg full; + + assign push_ready = !full; + assign pop_valid = full; + assign pop_data = mem; + + always @(posedge clk) begin + if (rst == 1'b1) begin + full <= 1'b0; + end else begin + if (push_valid && push_ready) begin + mem <= push_data; + full <= 1'b1; + end else if (pop_valid && pop_ready) begin + mem <= mem; + full <= 1'b0; + end else begin + mem <= mem; + full <= full; + end + end + end +endmodule diff --git a/xls/modules/zstd/huffman_axi_reader.x b/xls/modules/zstd/huffman_axi_reader.x new file mode 100644 index 0000000000..507008cefa --- /dev/null +++ b/xls/modules/zstd/huffman_axi_reader.x @@ -0,0 +1,282 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of Huffmann data preprocessor. + +import xls.modules.zstd.memory.axi as axi; + +pub struct HuffmanAxiReaderCtrl { + base_addr: uN[AXI_ADDR_W], + len: uN[AXI_ADDR_W], +} + +pub struct HuffmanAxiReaderData { + data: u8, + last: bool, +} + +struct HuffmanAxiReaderState { + ctrl: HuffmanAxiReaderCtrl, + bytes_requested: uN[AXI_ADDR_W], + bytes_sent: uN[AXI_ADDR_W], +} + +pub proc HuffmanAxiReader { + // FIXME: Replace hard-coded values with proc params AXI_DATA_W, AXI_ID_W + type AxiR = axi::AxiR; + // FIXME: Replace hard-coded values with proc params AXI_ADDR_W, AXI_ID_W + type AxiAr = axi::AxiAr; + + // FIXME: Replace hard-coded values with proc params AXI_ADDR_W + type Ctrl = HuffmanAxiReaderCtrl; + type Data = HuffmanAxiReaderData; + + // FIXME: Replace hard-coded values with proc params AXI_DATA_W, AXI_ADDR_W + type State = HuffmanAxiReaderState; + + ctrl_r: chan in; + axi_r_r: chan in; + axi_ar_s: chan out; + data_s: chan out; + + config ( + ctrl_r: chan in, + axi_r_r: chan in, + axi_ar_s: chan out, + data_s: chan out, + ) { + ( + ctrl_r, + axi_r_r, + axi_ar_s, + data_s, + ) + } + + init { zero!() } + + next (state: State) { + const BYTES_PER_TRANSACTION = (AXI_ADDR_W / u32:8) as u8; + + // receive and store ctrl + let (_, ctrl, ctrl_valid) = recv_if_non_blocking(join(), ctrl_r, state.ctrl.len == state.bytes_sent, zero!()); + + let state = if ctrl_valid { + trace_fmt!("Received CTRL {:#x}", ctrl); + State { + ctrl: ctrl, + ..zero!() + } + } else { state }; + + // send AXI read request + // this could be optimized to read multiple bytes per AXI transaction + let addr = state.ctrl.base_addr + state.ctrl.len - uN[AXI_ADDR_W]:1 - state.bytes_requested; + let axi_ar = AxiAr { + id: uN[AXI_ID_W]:0, + addr: addr, + ..zero!() + }; + let do_send_axi_req = (state.bytes_requested < state.ctrl.len); + send_if(join(), axi_ar_s, do_send_axi_req, axi_ar); + if (do_send_axi_req) { + trace_fmt!("Sent AXI read request {:#x}", axi_ar); + } else {}; + + let state = if do_send_axi_req { + State { + bytes_requested: state.bytes_requested + uN[AXI_ADDR_W]:1, + ..state + } + } else { + state + }; + + // receive data from AXI + let do_read_axi_resp = (state.bytes_requested > state.bytes_sent) && (state.bytes_sent < state.bytes_requested); + let (tok, axi_r, axi_r_valid) = recv_if_non_blocking(join(), axi_r_r, do_read_axi_resp, zero!()); + + // send data + let last = axi_r_valid && ((state.bytes_sent + uN[AXI_ADDR_W]:1) == state.ctrl.len); + let tok = send_if(tok, data_s, axi_r_valid, Data { + data: axi_r.data as u8, + last: last, + }); + let state = if last { + zero!() + } else if axi_r_valid { + trace_fmt!("Received AXI read response {:#x}", axi_r); + State { + bytes_sent: state.bytes_sent + uN[AXI_ADDR_W]:1, + ..state + } + } else { state }; + + state + } +} + +const INST_AXI_DATA_W = u32:32; +const INST_AXI_ADDR_W = u32:32; +const INST_AXI_ID_W = u32:32; + +proc HuffmanAxiReaderInst { + type InstHuffmanAxiReaderCtrl = HuffmanAxiReaderCtrl; + + type InstAxiAr = axi::AxiAr; + type InstAxiR = axi::AxiR; + + config ( + ctrl_r: chan in, + axi_r_r: chan in, + axi_ar_s: chan out, + data_s: chan out, + ) { + spawn HuffmanAxiReader( + ctrl_r, + axi_r_r, + axi_ar_s, + data_s, + ); + } + + init { } + + next (state: ()) { } +} + +const TEST_AXI_DATA_W = u32:32; +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_ID_W = u32:32; + +type TestHuffmanAxiReaderCtrl = HuffmanAxiReaderCtrl; + +type TestAxiAr = axi::AxiAr; +type TestAxiR = axi::AxiR; + +struct TestAxiData { + addr: uN[TEST_AXI_ADDR_W], + data: uN[TEST_AXI_DATA_W], + len: u8, + last: bool, +} + +const TEST_DATA_CTRL = TestHuffmanAxiReaderCtrl[3]:[ + TestHuffmanAxiReaderCtrl { + base_addr: uN[TEST_AXI_ADDR_W]:0, + len: uN[TEST_AXI_ADDR_W]:1, + }, + TestHuffmanAxiReaderCtrl { + base_addr: uN[TEST_AXI_ADDR_W]:128, + len: uN[TEST_AXI_ADDR_W]:4, + }, + TestHuffmanAxiReaderCtrl { + base_addr: uN[TEST_AXI_ADDR_W]:64, + len: uN[TEST_AXI_ADDR_W]:2, + }, +]; + +const TEST_DATA_AXI = TestAxiData[7]:[ + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:0, data: uN[TEST_AXI_DATA_W]:0x12, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:131, data: uN[TEST_AXI_DATA_W]:0xAA, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:130, data: uN[TEST_AXI_DATA_W]:0xBB, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:129, data: uN[TEST_AXI_DATA_W]:0xCC, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:128, data: uN[TEST_AXI_DATA_W]:0xDD, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:65, data: uN[TEST_AXI_DATA_W]:0x44, len: u8:0, last: false, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:64, data: uN[TEST_AXI_DATA_W]:0x55, len: u8:0, last: true, }, +]; + +const TEST_DATA_OUT = HuffmanAxiReaderData[7]:[ + HuffmanAxiReaderData { data: u8:0x12, last: true, }, + HuffmanAxiReaderData { data: u8:0xAA, last: false, }, + HuffmanAxiReaderData { data: u8:0xBB, last: false, }, + HuffmanAxiReaderData { data: u8:0xCC, last: false, }, + HuffmanAxiReaderData { data: u8:0xDD, last: true, }, + HuffmanAxiReaderData { data: u8:0x44, last: false, }, + HuffmanAxiReaderData { data: u8:0x55, last: true, }, +]; + +#[test_proc] +proc HuffmanAxiReader_test { + terminator: chan out; + + ctrl_s: chan out; + axi_r_s: chan out; + axi_ar_r: chan in; + data_r: chan in; + + config (terminator: chan out) { + let (ctrl_s, ctrl_r) = chan("ctrl"); + let (axi_r_s, axi_r_r) = chan("axi_r"); + let (axi_ar_s, axi_ar_r) = chan("axi_ar"); + let (data_s, data_r) = chan("data"); + + spawn HuffmanAxiReader ( + ctrl_r, + axi_r_r, + axi_ar_s, + data_s + ); + + ( + terminator, + ctrl_s, + axi_r_s, axi_ar_r, + data_r, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + + let tok = for ((i, test_ctrl), tok): ((u32, TestHuffmanAxiReaderCtrl), token) in enumerate(TEST_DATA_CTRL) { + let tok = send(tok, ctrl_s, test_ctrl); + trace_fmt!("Sent #{} ctrl {:#x}", i + u32:1, test_ctrl); + tok + }(tok); + + let tok = for ((i, test_axi), tok): ((u32, TestAxiData), token) in enumerate(TEST_DATA_AXI) { + let (tok, axi_req) = recv(tok, axi_ar_r); + trace_fmt!("Received #{} AXI request {:#x}", i + u32:1, axi_req); + + assert_eq(test_axi.addr, axi_req.addr); + assert_eq(test_axi.len, axi_req.len); + + let axi_resp = TestAxiR { + id: axi_req.id, + data: test_axi.data, + resp: axi::AxiReadResp::OKAY, + last: test_axi.last, + }; + let tok = send(tok, axi_r_s, axi_resp); + trace_fmt!("Sent #{} AXI response {:#x}", i + u32:1, axi_resp); + + tok + }(tok); + + let tok = for ((i, test_data), tok): ((u32, HuffmanAxiReaderData), token) in enumerate(TEST_DATA_OUT) { + let (tok, data) = recv(tok, data_r); + trace_fmt!("Received #{} data {:#x}", i + u32:1, data); + + assert_eq(test_data.data as u8, data.data); + assert_eq(test_data.last, data.last); + + tok + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/huffman_code_builder.x b/xls/modules/zstd/huffman_code_builder.x new file mode 100644 index 0000000000..4b554779c1 --- /dev/null +++ b/xls/modules/zstd/huffman_code_builder.x @@ -0,0 +1,431 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of Huffman tree decoder. + +import std; +import xls.dslx.stdlib.acm_random as random; + +import xls.examples.ram; +import xls.modules.zstd.common as common; +import xls.modules.zstd.huffman_common as hcommon; + +const MAX_WEIGHT = hcommon::MAX_WEIGHT; +const WEIGHT_LOG = hcommon::WEIGHT_LOG; +const MAX_SYMBOL_COUNT = hcommon::MAX_SYMBOL_COUNT; + +const PARALLEL_ACCESS_WIDTH = hcommon::PARALLEL_ACCESS_WIDTH; +const COUNTER_WIDTH = hcommon::COUNTER_WIDTH; + +const RECV_COUNT = MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH; +const RECV_COUNT_W = std::clog2(RECV_COUNT + u32:1); +const MAX_RECV = RECV_COUNT as uN[RECV_COUNT_W]; + +type WeightPreScanMetaData = hcommon::WeightPreScanMetaData; +type WeightPreScanOutput = hcommon::WeightPreScanOutput; +type CodeBuilderToPreDecoderOutput = hcommon::CodeBuilderToPreDecoderOutput; +type CodeBuilderToDecoderOutput = hcommon::CodeBuilderToDecoderOutput; + +enum WeightCodeBuilderFSM: u2 { + IDLE = u2:0, + GATHER_WEIGHTS_RUN = u2:1, + COMPUTE_MAX_LENGTH = u2:2, + GENERATE_CODES_RUN = u2:3, +} + +struct WeightCodeBuilderState { + fsm: WeightCodeBuilderFSM, + recv_counter: uN[RECV_COUNT_W], + loopback_counter: uN[RECV_COUNT_W], + sum_of_weights_powers: uN[MAX_WEIGHT + u32:2], + huffman_codes: uN[MAX_WEIGHT][MAX_WEIGHT + u32:1], + seen_weights: u1[MAX_WEIGHT + u32:1], + max_number_of_bits: uN[WEIGHT_LOG], +} + +pub proc WeightCodeBuilder +// TODO: enable parametric expresion when they start working +//proc WeightCodeBuilder< +// PARALLEL_ACCESS_WIDTH: u32 = {u32:8}, +//> { +{ + type State = WeightCodeBuilderState; + type FSM = WeightCodeBuilderFSM; + type PreScanData = WeightPreScanOutput; + type DecoderOutput = CodeBuilderToDecoderOutput; + type PreDecoderOutput = CodeBuilderToPreDecoderOutput; + + start_r: chan in; + weight_r: chan in; + codes_s: chan out; + lookahead_config_s: chan out; + + weights_pow_sum_loopback_s: chan out; + weights_pow_sum_loopback_r: chan in; + + config ( + start_r: chan in, + weight_r: chan in, + codes_s: chan out, + lookahead_config_s: chan out, + weights_pow_sum_loopback_s: chan out, + weights_pow_sum_loopback_r: chan in, + ) { + (start_r, weight_r, codes_s, lookahead_config_s, weights_pow_sum_loopback_s, weights_pow_sum_loopback_r) + } + + init {zero!()} + + next(state: State) { + let tok = join(); + + let (recv_start, recv_prescan) = match state.fsm { + FSM::IDLE => (true, false), + FSM::GATHER_WEIGHTS_RUN => (false, true), + FSM::COMPUTE_MAX_LENGTH => (false, false), + FSM::GENERATE_CODES_RUN => (false, true), + _ => { + assert!(false, "Invalid state"); + (false, false) + } + }; + let (_, start, start_valid) = recv_if_non_blocking(tok, start_r, recv_start, false); + let (_, prescan_data, prescan_data_valid) = recv_if_non_blocking(tok, weight_r, recv_prescan, zero!()); + + if start_valid { + trace_fmt!("Received start {:#x}", start); + } else {}; + + if prescan_data_valid { + trace_fmt!("Received prescan {:#x}", prescan_data); + } else {}; + + let (advance_state, send_lookahead, send_codes) = match state.fsm { + FSM::IDLE => (start && start_valid, false, false), + FSM::GATHER_WEIGHTS_RUN => (state.recv_counter == MAX_RECV, false, false), + FSM::COMPUTE_MAX_LENGTH => (state.loopback_counter == MAX_RECV, false, false), + FSM::GENERATE_CODES_RUN => { + let advance_state = state.recv_counter == (MAX_RECV * uN[RECV_COUNT_W]:2); + (advance_state, advance_state, prescan_data_valid) + }, + _ => { + assert!(false, "Invalid state"); + (false, false, false) + } + }; + + let next_fsm_state = match(state.fsm, advance_state) { + (FSM::IDLE, true) => { + trace_fmt!("IDLE -> GATHER_WEIGHTS_RUN"); + FSM::GATHER_WEIGHTS_RUN + }, + (FSM::GATHER_WEIGHTS_RUN, true) => { + trace_fmt!("GATHER_WEIGHTS_RUN -> COMPUTE_MAX_LENGTH"); + FSM::COMPUTE_MAX_LENGTH + }, + (FSM::COMPUTE_MAX_LENGTH, true) => { + trace_fmt!("COMPUTE_MAX_LENGTH -> GENERATE_CODES_RUN"); + FSM::GENERATE_CODES_RUN + }, + (FSM::GENERATE_CODES_RUN, true) => { + trace_fmt!("GENERATE_CODES_RUN -> IDLE"); + FSM::IDLE + }, + (_, false) => state.fsm, + _ => { + assert!(false, "Invalid state"); + FSM::IDLE + } + }; + + let meta_data = prescan_data.meta_data; + + // update seen weights + let seen_weights = for (i, weights) in range(u32:0, MAX_WEIGHT + u32:1) { + update(weights, i, weights[i] | meta_data.valid_weights[i]) + }(state.seen_weights); + + // compute sum of weights powers and send it to loopback + let do_send_loopback = (state.fsm == FSM::GATHER_WEIGHTS_RUN) && prescan_data_valid; + + let sum_of_weights_powers = if do_send_loopback { + for (i, acc) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + if (prescan_data.weights[i] != uN[WEIGHT_LOG]:0) { + acc + (uN[MAX_WEIGHT + u32:2]:1 << prescan_data.weights[i] as uN[MAX_WEIGHT + u32:2]) + } else { + acc + } + }(uN[MAX_WEIGHT + u32:2]:0) + } else { + uN[MAX_WEIGHT + u32:2]:0 + }; + + send_if(tok, weights_pow_sum_loopback_s, do_send_loopback, sum_of_weights_powers); + + // receive sum of weights powers from loopback + let (_, sum_of_weights_powers, sum_of_weights_powers_valid) = recv_non_blocking( + tok, weights_pow_sum_loopback_r, uN[MAX_WEIGHT + u32:2]:0 + ); + let sum_of_weights_powers = state.sum_of_weights_powers + sum_of_weights_powers; + let loopback_counter = if sum_of_weights_powers_valid { + trace_fmt!("Sum of weights powers: {}", sum_of_weights_powers); + state.loopback_counter + uN[RECV_COUNT_W]:1 + } else { + state.loopback_counter + }; + + // compute max number of bits + let max_number_of_bits = encode(sum_of_weights_powers >> u32:1) as uN[WEIGHT_LOG]; + + // intial value for huffman codes is 0 for weight 1 and 1 for the rest + // then the value is computed based on number of occurances of given weight + let huffman_codes = match(state.fsm, advance_state) { + (FSM::IDLE, _) => { + let huffman_codes = for (i, codes) in range(u32:0, MAX_WEIGHT + u32:1) { + update(codes, i, uN[MAX_WEIGHT]:1) + }(zero!()); + update(huffman_codes, u32:1, uN[MAX_WEIGHT]:0) + }, + (FSM::GENERATE_CODES_RUN, _) => { + let weights_count = meta_data.weights_count; + for(i, codes) in range(u32:0, MAX_WEIGHT + u32:1) { + update(codes, i, codes[i] + (weights_count[i] as uN[MAX_WEIGHT])) + }(state.huffman_codes) + }, + _ => state.huffman_codes, + }; + + let next_state = match(state.fsm,) { + (FSM::IDLE) => { + State { + fsm: next_fsm_state, + huffman_codes: huffman_codes, + ..zero!() + } + }, + (FSM::GATHER_WEIGHTS_RUN) => { + let recv_counter = if prescan_data_valid { + state.recv_counter + uN[RECV_COUNT_W]:1 + } else { + state.recv_counter + }; + State { + fsm: next_fsm_state, + loopback_counter: loopback_counter, + sum_of_weights_powers: sum_of_weights_powers, + recv_counter: recv_counter, + ..state + } + }, + (FSM::COMPUTE_MAX_LENGTH) => { + State { + fsm: next_fsm_state, + loopback_counter: loopback_counter, + sum_of_weights_powers: sum_of_weights_powers, + max_number_of_bits: max_number_of_bits, + ..state + } + }, + (FSM::GENERATE_CODES_RUN) => { + let recv_counter = if prescan_data_valid { + state.recv_counter + uN[RECV_COUNT_W]:1 + } else { + state.recv_counter + }; + State { + fsm: next_fsm_state, + recv_counter: recv_counter, + huffman_codes: huffman_codes, + seen_weights: seen_weights, + ..state + } + }, + _ => { + assert!(false, "Invalid state"); + zero!() + } + }; + + let lookahead_packet = PreDecoderOutput { + max_code_length: state.max_number_of_bits, + valid_weights: seen_weights, + }; + send_if(tok, lookahead_config_s, send_lookahead, lookahead_packet); + + // set symbol valid if weight is nonzero + let symbols_valid = for (i, symbol_valid) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + update(symbol_valid, i, prescan_data.weights[i] != uN[WEIGHT_LOG]:0) + }(zero!()); + + // set symbol length as max_length - weight + 1 + let codes_length = for (i, code_length) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + update(code_length, i, state.max_number_of_bits - prescan_data.weights[i] + uN[WEIGHT_LOG]:1) + }(zero!()); + + // set codes using weight, occurance number and Huffman codes per weight from previous iteration + let codes = for (i, codes) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let length = state.max_number_of_bits - prescan_data.weights[i] + uN[WEIGHT_LOG]:1; + let base_code = for(j, base_code) in range(u32:0, MAX_WEIGHT + u32:1) { + if (prescan_data.weights[i] == j as uN[WEIGHT_LOG]) { + state.huffman_codes[j] + } else { + base_code + } + }(uN[MAX_WEIGHT]:0); + let code = base_code + (meta_data.occurance_number[i] as uN[MAX_WEIGHT]); + let code = rev(code) >> (MAX_WEIGHT - length as u32); + update(codes, i, code) + }(zero!()); + + if send_codes { + trace_fmt!("{}\n{}\n{:#b}\n{:#b}", symbols_valid, codes_length, codes, state.huffman_codes); + } else {}; + + let code_packet = DecoderOutput { + symbol_valid: symbols_valid, + code_length: codes_length, + code: codes + }; + send_if(tok, codes_s, send_codes, code_packet); + + next_state + } +} + +//#[test_proc] +//proc WeightCodeBuilderSimpleTest{ +// type PrescanOut = WeightPreScanOutput; +// type DecoderOutput = CodeBuilderToDecoderOutput; +// type PreDecoderOutput = CodeBuilderToPreDecoderOutput; +// +// terminator: chan out; +//// external_ram_req: chan out; +//// external_ram_resp: chan in; +//// start_prescan: chan out; +//// prescan_response: chan in; +// init{()} +//// config (terminator: chan out) { +//// // Emulate external memory +//// let (RAMExternalWriteReq_s, RAMExternalWriteReq_r) = chan("Write_channel_req"); +//// let (RAMExternalWriteResp_s, RAMExternalWriteResp_r) = chan("Write_channel_resp"); +//// let (RAMExternalReadReq_s, RAMExternalReadReq_r) = chan("Read_channel_req"); +//// let (RAMExternalReadResp_s, RAMExternalReadResp_r) = chan("Read_channel_resp"); +//// spawn ram::RamModel( +//// RAMExternalReadReq_r, RAMExternalReadResp_s, RAMExternalWriteReq_r, RAMExternalWriteResp_s +//// ); +//// +//// // Emulate Internal prescan memory +//// let (RAMInternalWriteReq_s, RAMInternalWriteReq_r) = chan("Internal_write_channel_req"); +//// let (RAMInternalWriteResp_s, RAMInternalWriteResp_r) = chan("Internal_write_channel_resp"); +//// let (RAMInternalReadReq_s, RAMInternalReadReq_r) = chan("Internal_read_channel_req"); +//// let (RAMInternalReadResp_s, RAMInternalReadResp_r) = chan("Internal_read_channel_resp"); +//// spawn ram::RamModel<{WeightPreScanMetaDataSize()}, RAM_SIZE, {WeightPreScanMetaDataSize()}>( +//// RAMInternalReadReq_r, RAMInternalReadResp_s, RAMInternalWriteReq_r, RAMInternalWriteResp_s +//// ); +//// +//// let (PreScanStart_s, PreScanStart_r) = chan("Start_prescan"); +//// let (PreScanResponse_s, PreScanResponse_r) = chan("Start_prescan"); +//// spawn WeightPreScan( +//// PreScanStart_r, RAMExternalReadReq_s,RAMExternalReadResp_r, PreScanResponse_s, +//// RAMInternalReadReq_s, RAMInternalReadResp_r, RAMInternalWriteReq_s, RAMInternalWriteResp_r); +//// (terminator, RAMExternalWriteReq_s, RAMExternalWriteResp_r, PreScanStart_s, PreScanResponse_r) +//// } +//// next(state: ()) { +//// let tok = join(); +//// let rand_state = random::rng_new(random::rng_deterministic_seed()); +//// // Setup external memory with random values +//// for (i, rand_state) in range(u32:0, MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH) { +//// let (new_rand_state, data_to_send) = for (j, (rand_state, data_to_send)) in range(u32:0, PARALLEL_ACCESS_WIDTH) { +//// let (new_rand_state, data) = random::rng_next(rand_state); +//// let weight = (data - (data/u32:12) * u32:12) as u4; +//// let new_data_to_send = update(data_to_send as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], j, weight) as external_ram_data; +//// (new_rand_state, new_data_to_send) +//// }((rand_state, zero!())); +//// let external_w_req = WriteReq { +//// addr: i as u5, +//// data: data_to_send, +//// mask: u1:1 +//// }; +//// send(tok, external_ram_req, external_w_req); +//// recv(tok, external_ram_resp); +//// new_rand_state +//// }(rand_state); +//// send(tok, start_prescan, true); +//// // First run +//// for (_, rand_state) in range(u32:0, MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH) { +//// // Generate expected output +//// let (new_rand_state, expected_data) = for (j, (rand_state, data_to_send)) in range(u32:0, PARALLEL_ACCESS_WIDTH) { +//// let (new_rand_state, data) = random::rng_next(rand_state); +//// let weight = (data - (data/u32:12) * u32:12) as u4; +//// let new_data_to_send = update(data_to_send as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], j, weight) as external_ram_data; +//// (new_rand_state, new_data_to_send) +//// }((rand_state, zero!())); +//// let (_, prescan_resp) = recv(tok, prescan_response); +//// let expected_data = PrescanOut { +//// weights: expected_data as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], +//// meta_data: zero!() +//// }; +//// assert_eq(prescan_resp, expected_data); +//// new_rand_state +//// }(rand_state); +//// +//// // Second run +//// for (_, rand_state) in range(u32:0, MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH) { +//// // Generate expected output +//// let (new_rand_state, expected_data) = for (j, (rand_state, data_to_send)) in range(u32:0, PARALLEL_ACCESS_WIDTH) { +//// let (new_rand_state, data) = random::rng_next(rand_state); +//// let weight = (data - (data/u32:12) * u32:12) as u4; +//// let new_data_to_send = update(data_to_send as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], j, weight) as external_ram_data; +//// (new_rand_state, new_data_to_send) +//// }((rand_state, zero!())); +//// let expected_data = expected_data as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH]; +//// let valid_weights = for (i, seen_weights) in range(u32:0, PARALLEL_ACCESS_WIDTH) { +//// update(seen_weights, expected_data[i], true) +//// }(zero!()); +//// let occurance_number = for (i, occurance_number) in range(u32:0, PARALLEL_ACCESS_WIDTH) { +//// let number = for (j, number) in range(u32:0, PARALLEL_ACCESS_WIDTH){ +//// if (j < i && expected_data[j] == expected_data[i]) { +//// number + u4:1 +//// } else { +//// number +//// } +//// }(zero!()); +//// update(occurance_number, i, number) +//// }(zero!()); +//// let weights_count = for (i, weights_count) in range(u32:0, MAX_WEIGHT + u32:1) { +//// let count = for (j, count) in range(u32:0, PARALLEL_ACCESS_WIDTH) { +//// if (expected_data[j] == i as uN[COUNTER_WIDTH]) { +//// count + uN[COUNTER_WIDTH]:1 +//// } else { +//// count +//// } +//// }(zero!()); +//// update(weights_count, i, count) +//// }(zero!()); +//// let (_, prescan_resp) = recv(tok, prescan_response); +//// let expected_data = PrescanOut { +//// weights: expected_data, +//// meta_data: WeightPreScanMetaData { +//// occurance_number: occurance_number, +//// valid_weights: valid_weights, +//// weights_count: weights_count, +//// } +//// }; +//// assert_eq(prescan_resp, expected_data); +//// new_rand_state +//// }(rand_state); +//// +//// send(tok, terminator, true); +//// } +//} diff --git a/xls/modules/zstd/huffman_common.x b/xls/modules/zstd/huffman_common.x new file mode 100644 index 0000000000..7661f42315 --- /dev/null +++ b/xls/modules/zstd/huffman_common.x @@ -0,0 +1,64 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of Huffmann tree decoder. + +import std; + +pub const MAX_WEIGHT = u32:11; +pub const WEIGHT_LOG = std::clog2(MAX_WEIGHT + u32:1); +pub const MAX_SYMBOL_COUNT = u32:256; +pub const MAX_CODE_LEN = u32:12; + +pub const PARALLEL_ACCESS_WIDTH = u32:8; +pub const COUNTER_WIDTH = std::clog2(PARALLEL_ACCESS_WIDTH + u32:1); + +pub struct WeightPreScanMetaData { + occurance_number: uN[COUNTER_WIDTH][PARALLEL_ACCESS_WIDTH], + valid_weights: u1[MAX_WEIGHT + u32:1], + weights_count: uN[COUNTER_WIDTH][MAX_WEIGHT + u32:1], +} + +// TODO: Enable once parametrics work +//pub struct WeightPreScanMetaData < +// PARALLEL_ACCESS_WIDTH: u32, +// COUNTER_WIDTH: u32 = {std::clog2(PARALLEL_ACCESS_WIDTH + u32:1)} +//> { +// occurance_number: uN[COUNTER_WIDTH][PARALLEL_ACCESS_WIDTH], +// valid_weights: u1[MAX_WEIGHT + u32:1], +// weights_count: uN[COUNTER_WIDTH][MAX_WEIGHT + u32:1], +//} + +pub struct WeightPreScanOutput { + weights: uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], + meta_data: WeightPreScanMetaData, +} +// TODO: Use parametrics when they work +//pub struct WeightPreScanOutput< +// PARALLEL_ACCESS_WIDTH: u32, WEIGHT_LOG: u32 +//> { +// weights: uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], +// meta_data: WeightPreScanMetaData, +//} + +pub struct CodeBuilderToPreDecoderOutput { + max_code_length: uN[WEIGHT_LOG], + valid_weights: u1[MAX_WEIGHT + u32:1], +} + +pub struct CodeBuilderToDecoderOutput { + symbol_valid: u1[PARALLEL_ACCESS_WIDTH], + code_length: uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], + code: uN[MAX_WEIGHT][PARALLEL_ACCESS_WIDTH], +} diff --git a/xls/modules/zstd/huffman_ctrl.x b/xls/modules/zstd/huffman_ctrl.x new file mode 100644 index 0000000000..d5ac04d427 --- /dev/null +++ b/xls/modules/zstd/huffman_ctrl.x @@ -0,0 +1,284 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains Huffman decoder control and sequence proc implementation. + +import xls.modules.zstd.common as common; +import xls.modules.zstd.huffman_common as hcommon; +import xls.modules.zstd.huffman_axi_reader as axi_reader; +import xls.modules.zstd.huffman_code_builder as code_builder; +import xls.modules.zstd.huffman_data_preprocessor as data_preprocessor; +import xls.modules.zstd.huffman_decoder as decoder; +import xls.modules.zstd.huffman_prescan as prescan; + + +enum HuffmanControlAndSequenceFSM: u2 { + IDLE = 0, + DECODING = 1, +} + +pub struct HuffmanControlAndSequenceCtrl { + base_addr: uN[AXI_ADDR_W], + len: uN[AXI_ADDR_W], + new_config: bool, +} + +struct HuffmanControlAndSequenceState { + fsm: HuffmanControlAndSequenceFSM, +} + +pub proc HuffmanControlAndSequence { + type AxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; + type DataPreprocessorStart = data_preprocessor::HuffmanDataPreprocessorStart; + type DecoderStart = decoder::HuffmanDecoderStart; + + type State = HuffmanControlAndSequenceState; + type FSM = HuffmanControlAndSequenceFSM; + type Ctrl = HuffmanControlAndSequenceCtrl; + + ctrl_r: chan in; + + // prescan + prescan_start_s: chan out; + + // code builder + code_builder_start_s: chan out; + + // AXI reader + axi_reader_ctrl_s: chan out; + + // data preprocess + data_preprocess_start_s: chan out; + + // decoder + decoder_start_s: chan out; + decoder_done_r: chan<()> in; + + config ( + ctrl_r: chan in, + prescan_start_s: chan out, + code_builder_start_s: chan out, + axi_reader_ctrl_s: chan out, + data_preprocess_start_s: chan out, + decoder_start_s: chan out, + decoder_done_r: chan<()> in, + ) { + ( + ctrl_r, + prescan_start_s, + code_builder_start_s, + axi_reader_ctrl_s, + data_preprocess_start_s, + decoder_start_s, + decoder_done_r, + ) + } + + init { + zero!() + } + + next (state: State) { + // receive start + let (tok, ctrl, ctrl_valid) = recv_if_non_blocking(join(), ctrl_r, state.fsm == FSM::IDLE, zero!()); + + let state = if ctrl_valid { + State { + fsm: FSM::DECODING, + } + } else { + state + }; + + // send start to prescan and code builder + let new_config = ctrl_valid & ctrl.new_config; + + if new_config { + trace_fmt!("Sending start to prescan and code builder"); + } else {}; + send_if(tok, prescan_start_s, new_config, true); + send_if(tok, code_builder_start_s, new_config, true); + + // send address and length to AXI reader + if ctrl_valid { + trace_fmt!("Sending ctrl to AXI reader"); + } else {}; + send_if(tok, axi_reader_ctrl_s, ctrl_valid, AxiReaderCtrl { + base_addr: ctrl.base_addr, + len: ctrl.len, + }); + + // send reconfigure/keep to data preprocessor and decoder + if ctrl_valid { + trace_fmt!("Sending start to data preprocessor and decoder"); + } else {}; + send_if(tok, data_preprocess_start_s, ctrl_valid, DataPreprocessorStart { + new_config: new_config, + }); + send_if(tok, decoder_start_s, ctrl_valid, DecoderStart { + new_config: new_config, + }); + + // receive done + let (_, _, decoder_done_valid) = recv_if_non_blocking(tok, decoder_done_r, state.fsm == FSM::DECODING, ()); + if decoder_done_valid { + trace_fmt!("Received decoder done"); + } else {}; + + if decoder_done_valid { + State { + fsm: FSM::IDLE + } + } else { + state + } + } +} + + +const INST_AXI_ADDR_W = u32:32; + +proc HuffmanControlAndSequenceInst { + type AxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; + type DataPreprocessorStart = data_preprocessor::HuffmanDataPreprocessorStart; + type DecoderStart = decoder::HuffmanDecoderStart; + + config ( + ctrl_r: chan> in, + prescan_start_s: chan out, + code_builder_start_s: chan out, + axi_reader_ctrl_s: chan out, + data_preprocess_start_s: chan out, + decoder_start_s: chan out, + decoder_done_r: chan<()> in, + ) { + spawn HuffmanControlAndSequence( + ctrl_r, + prescan_start_s, + code_builder_start_s, + axi_reader_ctrl_s, + data_preprocess_start_s, + decoder_start_s, + decoder_done_r, + ); + } + + init { } + + next (state: ()) { } +} + + +const TEST_AXI_ADDR_W = u32:32; + +#[test_proc] +proc HuffmanControlAndSequence_test { + type Ctrl = HuffmanControlAndSequenceCtrl; + type AxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; + type DataPreprocessorStart = data_preprocessor::HuffmanDataPreprocessorStart; + type DecoderStart = decoder::HuffmanDecoderStart; + + terminator: chan out; + + ctrl_s: chan> out; + prescan_start_r: chan in; + code_builder_start_r: chan in; + axi_reader_ctrl_r: chan in; + data_preprocess_start_r: chan in; + decoder_start_r: chan in; + decoder_done_s: chan<()> out; + + config (terminator: chan out) { + let (ctrl_s, ctrl_r) = chan("ctrl"); + let (prescan_start_s, prescan_start_r) = chan("prescan_start"); + let (code_builder_start_s, code_builder_start_r) = chan("code_builder_start"); + let (axi_reader_ctrl_s, axi_reader_ctrl_r) = chan("axi_reader_ctrl"); + let (data_preprocess_start_s, data_preprocess_start_r) = chan("data_preprocess_start"); + let (decoder_start_s, decoder_start_r) = chan("decoder_start"); + let (decoder_done_s, decoder_done_r) = chan<()>("decoder_done"); + + spawn HuffmanControlAndSequence( + ctrl_r, + prescan_start_s, + code_builder_start_s, + axi_reader_ctrl_s, + data_preprocess_start_s, + decoder_start_s, + decoder_done_r, + ); + + ( + terminator, + ctrl_s, + prescan_start_r, + code_builder_start_r, + axi_reader_ctrl_r, + data_preprocess_start_r, + decoder_start_r, + decoder_done_s, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + + // without new config + let ctrl = Ctrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x1, + len: uN[TEST_AXI_ADDR_W]:0x2, + new_config: false, + }; + let tok = send(tok, ctrl_s, ctrl); + + let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); + assert_eq(AxiReaderCtrl {base_addr: ctrl.base_addr, len: ctrl.len}, axi_reader_ctrl); + + let (tok, data_preprocess_start) = recv(tok, data_preprocess_start_r); + assert_eq(DataPreprocessorStart {new_config: ctrl.new_config}, data_preprocess_start); + + let (tok, decoder_start) = recv(tok, decoder_start_r); + assert_eq(DecoderStart {new_config: ctrl.new_config}, decoder_start); + + let tok = send(tok, decoder_done_s, ()); + + // with new config + let ctrl = Ctrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x1, + len: uN[TEST_AXI_ADDR_W]:0x2, + new_config: true, + }; + let tok = send(tok, ctrl_s, ctrl); + + let (tok, prescan_start) = recv(tok, prescan_start_r); + assert_eq(true, prescan_start); + + let (tok, code_builder_start) = recv(tok, code_builder_start_r); + assert_eq(true, code_builder_start); + + let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); + assert_eq(AxiReaderCtrl {base_addr: ctrl.base_addr, len: ctrl.len}, axi_reader_ctrl); + + let (tok, data_preprocess_start) = recv(tok, data_preprocess_start_r); + assert_eq(DataPreprocessorStart {new_config: ctrl.new_config}, data_preprocess_start); + + let (tok, decoder_start) = recv(tok, decoder_start_r); + assert_eq(DecoderStart {new_config: ctrl.new_config}, decoder_start); + + let tok = send(tok, decoder_done_s, ()); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/huffman_data_preprocessor.x b/xls/modules/zstd/huffman_data_preprocessor.x new file mode 100644 index 0000000000..4f97cb9943 --- /dev/null +++ b/xls/modules/zstd/huffman_data_preprocessor.x @@ -0,0 +1,422 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of Huffmann data preprocessor. + +import std; + +import xls.modules.zstd.huffman_common as hcommon; +import xls.modules.zstd.huffman_axi_reader as huffman_axi_reader; + +type Config = hcommon::CodeBuilderToPreDecoderOutput; + +pub const H_DATA_W = hcommon::MAX_CODE_LEN * u32:8; +pub const H_DATA_W_LOG2 = std::clog2(H_DATA_W + u32:1); + +pub type Data = uN[H_DATA_W]; + +pub type CodeLen = uN[H_DATA_W_LOG2]; + +const MAX_PREFIX_LEN = u4:7; + +enum HuffmanDataPreprocessorFSM: u2 { + IDLE = 0, + AWAITING_CONFIG = 1, + READ_DATA = 2, + PROCESSING = 3, +} + +pub struct HuffmanDataPreprocessorStart { + new_config: bool +} + +pub struct HuffmanDataPreprocessorData { + data: Data, + data_len: CodeLen, + code_length: CodeLen[H_DATA_W], +} + +struct HuffmanDataPreprocessorState { + fsm: HuffmanDataPreprocessorFSM, + lookahead_config: Config, + data: Data, + data_len: CodeLen, +} + +pub proc HuffmanDataPreprocessor { + type State = HuffmanDataPreprocessorState; + type FSM = HuffmanDataPreprocessorFSM; + type Start = HuffmanDataPreprocessorStart; + type DataIn = huffman_axi_reader::HuffmanAxiReaderData; + type PreprocessedData = HuffmanDataPreprocessorData; + + start_r: chan in; + lookahead_config_r: chan in; + data_r: chan in; + + preprocessed_data_s: chan out; + + config ( + start_r: chan in, + lookahead_config_r: chan in, + data_r: chan in, + preprocessed_data_s: chan out, + ) { + ( + start_r, + lookahead_config_r, + data_r, + preprocessed_data_s, + ) + } + + init { zero!() } + + next (state: State) { + let tok = join(); + + // wait for start + let (tok, start, start_valid) = recv_if_non_blocking(tok, start_r, state.fsm == FSM::IDLE, zero!()); + + let state = if start_valid { + let fsm = if start.new_config { + trace_fmt!("Waiting for new config"); + FSM::AWAITING_CONFIG + } else { + FSM::READ_DATA + }; + State { + fsm: fsm, + ..state + } + } else { state }; + + // wait for config + let (tok, config, config_valid) = recv_if_non_blocking( + tok, + lookahead_config_r, + state.fsm == FSM::AWAITING_CONFIG, + zero!() + ); + + let state = if config_valid { + State { + fsm: FSM::READ_DATA, + lookahead_config: config, + ..state + } + } else { state }; + + // receive data + let do_read_data = state.fsm == FSM::READ_DATA; + let (tok, data, data_valid) = recv_if_non_blocking(tok, data_r, do_read_data, zero!()); + + // process data + let state = if data_valid { + let fsm = if data.last { + FSM::PROCESSING + } else { + state.fsm + }; + State { + fsm: fsm, + data: state.data | ((rev(data.data) as Data) << state.data_len), + data_len: state.data_len + CodeLen:8, + ..state + } + } else { state }; + + let processed_data = if state.fsm == FSM::PROCESSING { + let data_bits = state.data; + let data_bits_len = state.data_len; + + // remove prefix + let (prefix_len, _) = for (i, (prefix_len, stop)): (u32, (u4, bool)) in range(u32:0, MAX_PREFIX_LEN as u32) { + if stop || (data_bits >> i) as u1 { + ( + prefix_len, + true, + ) + } else { + ( + prefix_len + u4:1, + stop, + ) + } + }((u4:1, false)); + + trace_fmt!("Prefix len: {}", prefix_len); + + let data_bits = data_bits >> prefix_len; + let data_bits_len = data_bits_len - prefix_len as CodeLen; + + // compute Huffman code lengths + + // compute number of zeros + let (code_lengths, _) = for (i, (code_lengths, num_zeros)): (u32, (CodeLen[H_DATA_W], CodeLen)) in range(u32:0, H_DATA_W) { + // reverse order + let n = H_DATA_W - u32:1 - i; + if n < data_bits_len as u32 { + // if non zero then reset counter, otherwise increment + let num_zeros = if (data_bits >> n) as u1 { + CodeLen:0 + } else { + num_zeros + CodeLen:1 + }; + // clip code len by max code length + let code_len = if num_zeros >= state.lookahead_config.max_code_length as CodeLen { + state.lookahead_config.max_code_length as CodeLen + } else { + num_zeros + CodeLen:1 + }; + ( + update(code_lengths, n, code_len), num_zeros + ) + } else { + (code_lengths, num_zeros) + } + }((zero!(), CodeLen:0)); + + // round up number of zeros to possible length + let code_lengths = for (i, code_lengths): (u32, CodeLen[H_DATA_W]) in range(u32:0, H_DATA_W) { + if i < data_bits_len as u32 { + let length = for (weight, length): (u32, CodeLen) in range(u32:0, hcommon::MAX_WEIGHT + u32:1) { + let weight_valid = state.lookahead_config.valid_weights[weight]; + let number_of_bits = if weight > u32:0 { + state.lookahead_config.max_code_length as u32 + u32:1 - weight + } else { + u32:0 + }; + if (code_lengths[i] <= number_of_bits as CodeLen) && weight_valid { + number_of_bits as CodeLen + } else { + length + } + }(code_lengths[i]); + update(code_lengths, i, length) + } else { + code_lengths + } + }(code_lengths); + + PreprocessedData { + data: data_bits, + data_len: data_bits_len, + code_length: code_lengths, + } + + } else { zero!() }; + + let tok = send_if(tok, preprocessed_data_s, state.fsm == FSM::PROCESSING, processed_data); + + let state = if state.fsm == FSM::PROCESSING { + State { + fsm: FSM::IDLE, + lookahead_config: state.lookahead_config, + ..zero!() + } + } else { state }; + + state + } +} + +const TEST_START = HuffmanDataPreprocessorStart[2]:[ + HuffmanDataPreprocessorStart { + new_config: true, + }, + HuffmanDataPreprocessorStart { + new_config: true, + }, +]; + +const TEST_CONFIG = Config[2]:[ + Config { + max_code_length: uN[hcommon::WEIGHT_LOG]:6, + valid_weights: [false, true, false, true, true, false, true, false, false, false, false, false] + }, + Config { + max_code_length: uN[hcommon::WEIGHT_LOG]:9, + valid_weights: [false, true, false, false, true, false, false, true, false, true, false, false] + } +]; + +const TEST_DATA = huffman_axi_reader::HuffmanAxiReaderData[12]:[ + // #1 + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01010000, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01011011, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01000001, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01010011, + last: true, + }, + // #2 + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b00110100, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b11110001, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01010000, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b00101010, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b11010100, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01000010, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b01010101, + last: false, + }, + huffman_axi_reader::HuffmanAxiReaderData { + data: u8:0b10010101, + last: true, + }, +]; + +const TEST_PREPROCESSED_DATA = HuffmanDataPreprocessorData[2]:[ + HuffmanDataPreprocessorData { + data: Data:0b110_010_1_010000_010_110_1_1_010000_010, + data_len: CodeLen:30, + code_length: [ + CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, + CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + ], + }, + HuffmanDataPreprocessorData { + data: Data:0b1_010_100_110_1_010_100_100_001000_1_010_110_1_010_100000_010_101000_1_1_110_010_1, + data_len: CodeLen:61, + code_length: [ + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:1, + CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:9, CodeLen:6, CodeLen:6, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:6, + CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + ], + } +]; + +#[test_proc] +proc HuffmanDataPreprocessor_test { + type State = HuffmanDataPreprocessorState; + type Start = HuffmanDataPreprocessorStart; + type Data = huffman_axi_reader::HuffmanAxiReaderData; + type PreprocessedData = HuffmanDataPreprocessorData; + + terminator_s: chan out; + + start_s: chan out; + lookahead_config_s: chan out; + data_s: chan out; + + preprocessed_data_r: chan in; + + config (terminator_s: chan out) { + let (start_s, start_r) = chan("start"); + let (lookahead_config_s, lookahead_config_r) = chan("lookahead_config"); + let (data_s, data_r) = chan("data"); + let (preprocessed_data_s, preprocessed_data_r) = chan("preprocessed_data"); + + spawn HuffmanDataPreprocessor( + start_r, + lookahead_config_r, + data_r, + preprocessed_data_s, + ); + + ( + terminator_s, + start_s, + lookahead_config_s, + data_s, + preprocessed_data_r, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + + let (tok, _, _) = for ((i, test_start), (tok, cfg_idx, data_idx)): ((u32, Start), (token, u32, u32)) in enumerate(TEST_START) { + let tok = send(tok, start_s, test_start); + trace_fmt!("Sent #{} start {:#x}", i + u32:1, test_start); + + let (tok, cfg_idx) = if test_start.new_config { + let tok = send(tok, lookahead_config_s, TEST_CONFIG[cfg_idx]); + trace_fmt!("Sent #{} config {:#x}", cfg_idx + u32:1, TEST_CONFIG[cfg_idx]); + (tok, cfg_idx + u32:1) + } else { (tok, cfg_idx) }; + + let (tok, data_idx, _) = for (_, (tok, data_idx, do_send)) in range(u32:0, hcommon::MAX_CODE_LEN) { + if data_idx < array_size(TEST_DATA) { + let data = TEST_DATA[data_idx]; + + if do_send { + let tok = send(tok, data_s, data); + trace_fmt!("Sent #{} data {:#x}", data_idx + u32:1, data); + (tok, data_idx + u32:1, !data.last) + } else { + (tok, data_idx, false) + } + } else { (tok, data_idx, false) } + }((tok, data_idx, true)); + + let (tok, preprocessed_data) = recv(tok, preprocessed_data_r); + trace_fmt!("Received #{} preprocessed data {:#x}", i + u32:1, preprocessed_data); + assert_eq(TEST_PREPROCESSED_DATA[i], preprocessed_data); + + (tok, cfg_idx, data_idx) + }((tok, u32:0, u32:0)); + + send(tok, terminator_s, true); + } +} diff --git a/xls/modules/zstd/huffman_decoder.x b/xls/modules/zstd/huffman_decoder.x new file mode 100644 index 0000000000..e13bc484d1 --- /dev/null +++ b/xls/modules/zstd/huffman_decoder.x @@ -0,0 +1,724 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of Huffman decoder. + +import std; + +import xls.modules.zstd.common as common; +import xls.modules.zstd.huffman_common as hcommon; +import xls.modules.zstd.huffman_data_preprocessor as huffman_data_preprocessor; + +type Codes = hcommon::CodeBuilderToDecoderOutput; +type CodeLen = huffman_data_preprocessor::CodeLen; + +const SYMBOLS_N = u32:1 << common::SYMBOL_WIDTH; + +const H_DATA_W = hcommon::MAX_CODE_LEN * u32:8; +const H_DATA_W_LOG2 = std::clog2(H_DATA_W + u32:1); + +const BUFF_W = H_DATA_W * u32:2; +const BUFF_W_LOG2 = std::clog2(BUFF_W + u32:1); + +enum HuffmanDecoderFSM: u3 { + IDLE = 0, + AWAITING_CONFIG = 1, + READ_DATA = 2, + DECODE = 3, +} + +pub struct HuffmanDecoderStart { + new_config: bool, +} + +struct HuffmanDecoderState { + fsm: HuffmanDecoderFSM, + symbol_config_id: u5, + symbol_valid: bool[SYMBOLS_N], + symbol_code: uN[hcommon::MAX_WEIGHT][SYMBOLS_N], + symbol_code_len: uN[hcommon::WEIGHT_LOG][SYMBOLS_N], + data_len: uN[BUFF_W_LOG2], + data: uN[BUFF_W], + code_length: CodeLen[BUFF_W], + decoded_literals: uN[common::SYMBOL_WIDTH][u32:8], + decoded_literals_len: u4, +} + +fn extend_buff_array(buff: CodeLen[N], buff_len: u32, array: CodeLen[M]) -> CodeLen[N] { + const ELEM_SIZE = huffman_data_preprocessor::H_DATA_W_LOG2; + + let buff_flat = buff as uN[ELEM_SIZE * N]; + let array_flat = array as uN[ELEM_SIZE * M]; + let buff_flat = ( + buff_flat | + (array_flat as uN[ELEM_SIZE * N] << (ELEM_SIZE * (N - M - buff_len))) + ); + buff_flat as CodeLen[N] +} + +#[test] +fn extend_buff_array_test() { + assert_eq( + CodeLen[8]:[CodeLen:1, CodeLen:2, CodeLen:3, CodeLen:4, CodeLen:5, CodeLen:0, CodeLen:0, CodeLen:0], + extend_buff_array( + CodeLen[8]:[CodeLen:1, CodeLen:2, CodeLen:3, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0], + u32:3, + CodeLen[2]:[CodeLen:4, CodeLen:5], + ), + ); + assert_eq( + CodeLen[8]:[CodeLen:1, CodeLen:2, CodeLen:3, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0], + extend_buff_array( + zero!(), + u32:0, + CodeLen[3]:[CodeLen:1, CodeLen:2, CodeLen:3], + ), + ); +} + +fn shift_buff_array(buff: CodeLen[N], shift: u32) -> CodeLen[N] { + const ELEM_SIZE = huffman_data_preprocessor::H_DATA_W_LOG2; + + let buff_flat = buff as uN[ELEM_SIZE * N]; + let buff_flat = buff_flat << (ELEM_SIZE * shift); + buff_flat as CodeLen[N] +} + +#[test] +fn shift_buff_array_test() { + assert_eq( + CodeLen[8]:[CodeLen:4, CodeLen:5, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0], + shift_buff_array( + CodeLen[8]:[CodeLen:1, CodeLen:2, CodeLen:3, CodeLen:4, CodeLen:5, CodeLen:0, CodeLen:0, CodeLen:0], + u32:3, + ), + ); + assert_eq( + CodeLen[8]:[CodeLen:1, CodeLen:2, CodeLen:3, CodeLen:4, CodeLen:5, CodeLen:0, CodeLen:0, CodeLen:0], + shift_buff_array( + CodeLen[8]:[CodeLen:1, CodeLen:2, CodeLen:3, CodeLen:4, CodeLen:5, CodeLen:0, CodeLen:0, CodeLen:0], + u32:0, + ), + ); +} + +pub proc HuffmanDecoder { + type State = HuffmanDecoderState; + type FSM = HuffmanDecoderFSM; + type Start = HuffmanDecoderStart; + type Data = huffman_data_preprocessor::HuffmanDataPreprocessorData; + + start_r: chan in; + codes_r: chan in; + data_r: chan in; + + done_s: chan<()> out; + decoded_literals_s: chan out; + + config ( + start_r: chan in, + codes_r: chan in, + data_r: chan in, + done_s: chan<()> out, + decoded_literals_s: chan out, + ) { + ( + start_r, + codes_r, + data_r, + done_s, + decoded_literals_s, + ) + } + + init { zero!() } + + next (state: State) { + let tok = join(); + + // wait for start + let (tok, start, start_valid) = recv_if_non_blocking( + tok, start_r, state.fsm == FSM::IDLE, zero!() + ); + + let state = if start_valid { + if start.new_config { + trace_fmt!("IDLE -> AWAITING_CONFIG"); + State { + fsm: FSM::AWAITING_CONFIG, + symbol_config_id: u5:0, + ..state + } + } else { + trace_fmt!("IDLE -> READ_DATA"); + State { + fsm: FSM::READ_DATA, + ..state + } + } + } else { state }; + + // wait for config + let (tok, config, config_valid) = recv_if_non_blocking( + tok, + codes_r, + state.fsm == FSM::AWAITING_CONFIG, + zero!() + ); + + let state = if config_valid { + let (symbol_valid, symbol_code, symbol_code_len) = + for (i, (symbol_valid, symbol_code, symbol_code_len)): + ( + u32, + ( + bool[SYMBOLS_N], + uN[hcommon::MAX_WEIGHT][SYMBOLS_N], + uN[hcommon::WEIGHT_LOG][SYMBOLS_N], + ) + ) in range(u32:0, hcommon::PARALLEL_ACCESS_WIDTH) { + ( + update(symbol_valid, (state.symbol_config_id as u32 * u32:8) + i, config.symbol_valid[i]), + update(symbol_code, (state.symbol_config_id as u32 * u32:8) + i, config.code[i]), + update(symbol_code_len, (state.symbol_config_id as u32 * u32:8) + i, config.code_length[i]), + ) + }((state.symbol_valid, state.symbol_code, state.symbol_code_len)); + let fsm = if (state.symbol_config_id as u32 + u32:1) == (SYMBOLS_N / hcommon::PARALLEL_ACCESS_WIDTH) { + trace_fmt!("AWAITING_CONFIG -> READ_DATA"); + trace_fmt!("Received codes:"); + for (i, ()) in range(u32:0, SYMBOLS_N) { + if symbol_valid[i] { + trace_fmt!(" {:#b} (len {}) -> {:#x}", symbol_code[i], symbol_code_len[i], i); + } else {}; + }(()); + FSM::READ_DATA + } else { + state.fsm + }; + State { + fsm: fsm, + symbol_config_id: state.symbol_config_id + u5:1, + symbol_valid: symbol_valid, + symbol_code: symbol_code, + symbol_code_len: symbol_code_len, + ..state + } + } else { state }; + + // receive data + let (tok, data, data_valid) = recv_if_non_blocking( + tok, data_r, (state.fsm == FSM::READ_DATA) && (state.data_len as u32 < H_DATA_W), zero!() + ); + + let state = if data_valid { + trace_fmt!("READ_DATA -> DECODE"); + trace_fmt!("Received data: {:#b} (len: {})", data.data, data.data_len); + State { + fsm: FSM::DECODE, + data_len: state.data_len + data.data_len as uN[BUFF_W_LOG2], + data: state.data | (data.data as uN[BUFF_W] << state.data_len), + code_length: extend_buff_array(state.code_length, state.data_len as u32, data.code_length), + ..state + } + } else { + state + }; + + // decode data + let state = if ( + state.fsm == FSM::DECODE && + state.data_len > uN[BUFF_W_LOG2]:0 && + state.data_len >= state.code_length[0] as uN[BUFF_W_LOG2] + ) { + let data_mask = (!uN[hcommon::MAX_WEIGHT]:0) >> (hcommon::MAX_WEIGHT - state.code_length[0] as u32); + let data_masked = state.data as uN[hcommon::MAX_WEIGHT] & data_mask; + + trace_fmt!("Data to be decoded: {:#b} (len: {})", data_masked, state.code_length[0]); + + let literals = for (i, literals):(u32, uN[common::SYMBOL_WIDTH][SYMBOLS_N]) in range(u32:0, SYMBOLS_N){ + if ( + state.symbol_valid[i] && + (data_masked == state.symbol_code[i]) + ) { + update(literals, i, i as uN[common::SYMBOL_WIDTH]) + } else { + literals + } + }(zero!()); + + // assuming only one code was valid, we can compute 'or' of all array elements + let literal = for (i, literal):(u32, uN[common::SYMBOL_WIDTH]) in range(u32:0, SYMBOLS_N) { + literal | literals[i] + }(uN[common::SYMBOL_WIDTH]:0); + + // shift buffer + State { + decoded_literals: update(state.decoded_literals, state.decoded_literals_len, literal), + decoded_literals_len: state.decoded_literals_len + u4:1, + data_len: state.data_len - state.code_length[0] as uN[BUFF_W_LOG2], + data: state.data >> state.code_length[0], + code_length: shift_buff_array(state.code_length, state.code_length[0] as u32), + ..state + } + } else { + state + }; + + // send literals + let do_send_literals = ( + state.decoded_literals_len == u4:8 || + (state.decoded_literals_len > u4:0 && state.data_len == uN[BUFF_W_LOG2]:0) + ); + + let data = if do_send_literals { + for (i, data): (u32, common::LitData) in range(u32:0, u32:8) { + data | (state.decoded_literals[i] as common::LitData << (common::SYMBOL_WIDTH * i)) + }(zero!()) + } else { + zero!() + }; + + let done = state.data_len == uN[BUFF_W_LOG2]:0; + send_if(tok, decoded_literals_s, do_send_literals, common::LiteralsData{ + data: data, + length: state.decoded_literals_len as common::LitLength, + last: done, + }); + + let state = if do_send_literals { + let fsm = if state.data_len == uN[BUFF_W_LOG2]:0 { + trace_fmt!("DECODE -> IDLE"); + FSM::IDLE + } else { + FSM::DECODE + }; + State { + fsm: fsm, + decoded_literals_len: u4:0, + decoded_literals: zero!(), + ..state + } + } else { + state + }; + + send_if(tok, done_s, done, ()); + + state + } +} + +type TestCodeLen = uN[hcommon::WEIGHT_LOG]; +type TestCode = uN[hcommon::MAX_WEIGHT]; + +struct SymbolData { + symbol_valid: bool, + code_length: TestCodeLen, + code: TestCode, +} + +// helper function to improve readability of test data +fn generate_codes(data: SymbolData[8]) -> Codes { + Codes { + symbol_valid: [ + data[0].symbol_valid, data[1].symbol_valid, data[2].symbol_valid, data[3].symbol_valid, + data[4].symbol_valid, data[5].symbol_valid, data[6].symbol_valid, data[7].symbol_valid, + ], + code_length: [ + data[0].code_length, data[1].code_length, data[2].code_length, data[3].code_length, + data[4].code_length, data[5].code_length, data[6].code_length, data[7].code_length, + ], + code: [ + data[0].code, data[1].code, data[2].code, data[3].code, + data[4].code, data[5].code, data[6].code, data[7].code, + ], + } +} + +const TEST_START = HuffmanDecoderStart[3]:[ + HuffmanDecoderStart { new_config: true }, + HuffmanDecoderStart { new_config: false }, + HuffmanDecoderStart { new_config: true }, +]; + +// config #1 +// 0b1 -> 0x06 +// 0b100 -> 0x03 +// 0b010 -> 0x00 +// 0b110 -> 0x02 +// 0b1000 -> 0x1B +// 0b000000 -> 0xB6 +// 0b010000 -> 0xB5 +// 0b100000 -> 0x0D +// 0b110000 -> 0xB2 +// +// config #2 +// 0b1 -> 0x47 +// 0b001 -> 0x41 +// 0b010 -> 0xD2 +// 0b011 -> 0x8A +// 0b000001 -> 0x7A +// 0b000010 -> 0xDA +// 0b000011 -> 0x45 +// 0b000100 -> 0xD3 +// 0b000101 -> 0x89 +// 0b000110 -> 0x8D +// 0b000111 -> 0xD1 +// 0b000000001 -> 0xAC +// 0b000000010 -> 0x8F +// 0b000000011 -> 0xDB +// 0b000000100 -> 0xD4 +// 0b000000101 -> 0xFE +// 0b000000110 -> 0xDE +// 0b000000111 -> 0xD7 + +const TEST_CODES = Codes[64]:[ + // config #1 + generate_codes([ // 0x00 - 0x07 + SymbolData { symbol_valid: true, code_length: TestCodeLen:3, code: TestCode:0b010 }, + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:3, code: TestCode:0b110 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:3, code: TestCode:0b100 }, + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:1, code: TestCode:0b1 }, + zero!(), + ]), + zero!(), // 0x08 - 0x0F + zero!(), // 0x10 - 0x17 + generate_codes([ // 0x18 - 0x1F + zero!(), + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:4, code: TestCode:0b1000 }, + zero!(), + zero!(), + zero!(), + zero!(), + ]), + zero!(), // 0x20 - 0x27 + zero!(), // 0x28 - 0x2F + zero!(), // 0x30 - 0x37 + zero!(), // 0x38 - 0x3F + zero!(), // 0x40 - 0x47 + zero!(), // 0x48 - 0x4F + zero!(), // 0x50 - 0x67 + zero!(), // 0x58 - 0x5F + zero!(), // 0x60 - 0x67 + zero!(), // 0x68 - 0x6F + zero!(), // 0x70 - 0x77 + zero!(), // 0x78 - 0x7F + zero!(), // 0x80 - 0x87 + zero!(), // 0x88 - 0x8F + zero!(), // 0x90 - 0x97 + zero!(), // 0x98 - 0x9F + zero!(), // 0xA0 - 0xA7 + zero!(), // 0xA8 - 0xAF + generate_codes([ // 0xB0 - 0xB7 + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b110000 }, + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b010000 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b000000 }, + zero!(), + ]), + zero!(), // 0xB8 - 0xBF + zero!(), // 0xC0 - 0xC7 + zero!(), // 0xC8 - 0xCF + zero!(), // 0xD0 - 0xD7 + zero!(), // 0xD8 - 0xDF + zero!(), // 0xE0 - 0xE7 + zero!(), // 0xE8 - 0xEF + zero!(), // 0xF0 - 0xF7 + zero!(), // 0xF8 - 0xFF + // config #2 + zero!(), // 0x00 - 0x07 + zero!(), // 0x08 - 0x0F + zero!(), // 0x10 - 0x17 + zero!(), // 0x18 - 0x1F + zero!(), // 0x20 - 0x27 + zero!(), // 0x28 - 0x2F + zero!(), // 0x30 - 0x37 + zero!(), // 0x38 - 0x3F + generate_codes([ // 0x40 - 0x47 + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:3, code: TestCode:0b100 }, + zero!(), + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b110000 }, + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:1, code: TestCode:0b1 }, + ]), + zero!(), // 0x48 - 0x4F + zero!(), // 0x50 - 0x67 + zero!(), // 0x58 - 0x5F + zero!(), // 0x60 - 0x67 + zero!(), // 0x68 - 0x6F + zero!(), // 0x70 - 0x77 + generate_codes([ // 0x78 - 0x7F + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b100000 }, + zero!(), + zero!(), + zero!(), + zero!(), + zero!(), + ]), + zero!(), // 0x80 - 0x87 + generate_codes([ // 0x88 - 0x8F + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b101000 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:3, code: TestCode:0b110 }, + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b110000 }, + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b0100000000 }, + ]), + zero!(), // 0x90 - 0x97 + zero!(), // 0x98 - 0x9F + zero!(), // 0xA0 - 0xA7 + generate_codes([ // 0xA8 - 0xAF + zero!(), + zero!(), + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b100000000 }, + zero!(), + zero!(), + zero!(), + ]), + zero!(), // 0xB0 - 0xB7 + zero!(), // 0xB8 - 0xBF + zero!(), // 0xC0 - 0xC7 + zero!(), // 0xC8 - 0xCF + generate_codes([ // 0xD0 - 0xD7 + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b111000 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:3, code: TestCode:0b010 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b001000 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b001000000 }, + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b111000000 }, + ]), + generate_codes([ // 0xD8 - 0xDF + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:6, code: TestCode:0b010000 }, + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b110000000 }, + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b011000000 }, + zero!(), + ]), + zero!(), // 0xE0 - 0xE7 + zero!(), // 0xE8 - 0xEF + zero!(), // 0xF0 - 0xF7 + generate_codes([ // 0xF8 - 0xFF + zero!(), + zero!(), + zero!(), + zero!(), + zero!(), + zero!(), + SymbolData { symbol_valid: true, code_length: TestCodeLen:9, code: TestCode:0b101000000 }, + zero!(), + ]), +]; + +const TEST_DATA = huffman_data_preprocessor::HuffmanDataPreprocessorData[3]:[ + huffman_data_preprocessor::HuffmanDataPreprocessorData { + data: huffman_data_preprocessor::Data:0x32a0b682, + data_len: CodeLen:30, + code_length: [ + CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, + CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + ], + }, + huffman_data_preprocessor::HuffmanDataPreprocessorData { + data: huffman_data_preprocessor::Data:0x32a0b682, + data_len: CodeLen:30, + code_length: [ + CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, + CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + ], + }, + huffman_data_preprocessor::HuffmanDataPreprocessorData { + data: huffman_data_preprocessor::Data:0b1_010_100_110_1_010_100_100_001000_1_010_110_1_010_100000_010_101000_1_1_110_010_1, + data_len: CodeLen:61, + code_length: [ + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:1, + CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:9, CodeLen:6, CodeLen:6, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, + CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:6, + CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, + ], + }, +]; + +const TEST_LITERALS = common::LiteralsData[7]:[ + common::LiteralsData { + data: common::LitData:0x06B5_0002_0606_B500, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x0200, + length: common::LitLength:2, + last: true, + }, + common::LiteralsData { + data: common::LitData:0x06B5_0002_0606_B500, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x0200, + length: common::LitLength:2, + last: true, + }, + common::LiteralsData { + data: common::LitData:0x7AD2_8947_478A_D247, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x4141_D347_D28A_47D2, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x47D2_418A_47D2, + length: common::LitLength:6, + last: true, + }, +]; + +#[test_proc] +proc HuffmanDecoder_test { + type Start = HuffmanDecoderStart; + type Data = huffman_data_preprocessor::HuffmanDataPreprocessorData; + + terminator_s: chan out; + + start_s: chan out; + codes_s: chan out; + data_s: chan out; + + done_r: chan<()> in; + decoded_literals_r: chan in; + + config (terminator_s: chan out) { + let (start_s, start_r) = chan("start"); + let (codes_s, codes_r) = chan("codes"); + let (data_s, data_r) = chan("data"); + let (done_s, done_r) = chan<()>("done"); + let (decoded_literals_s, decoded_literals_r) = chan("decoded_literals"); + + spawn HuffmanDecoder( + start_r, codes_r, data_r, + done_s, decoded_literals_s, + ); + ( + terminator_s, + start_s, + codes_s, + data_s, + done_r, + decoded_literals_r, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + + let (tok, _) = for ((i, start), (tok, codes_idx)): ((u32, Start), (token, u32)) in enumerate(TEST_START) { + // send start + let tok = send(tok, start_s, start); + trace_fmt!("Sent #{} start {:#x}", i + u32:1, start); + + // send codes if required + let (tok, codes_idx) = if start.new_config { + for (_, (tok, codes_idx)): (u32, (token, u32)) in range(u32:0, SYMBOLS_N / hcommon::PARALLEL_ACCESS_WIDTH) { + let tok = send(tok, codes_s, TEST_CODES[codes_idx]); + trace_fmt!("Send #{} codes {:#x}", codes_idx + u32:1, TEST_CODES[codes_idx]); + (tok, codes_idx + u32:1) + }((tok, codes_idx)) + } else { + (tok, codes_idx) + }; + + // send data + let tok = send(tok, data_s, TEST_DATA[i]); + trace_fmt!("Sent #{} data {:#x}", i + u32:1, TEST_DATA[i]); + + (tok, codes_idx) + }((tok, u32:0)); + + let tok = for ((i, expected_literals), tok): ((u32, common::LiteralsData), token) in enumerate(TEST_LITERALS) { + // receive literals + let (tok, literals) = recv(tok, decoded_literals_r); + trace_fmt!("Received #{} literals {:#x}", i + u32:1, literals); + + assert_eq(expected_literals, literals); + + // receive done + let tok = if expected_literals.last { + let (tok, _) = recv(tok, done_r); + tok + } else { + tok + }; + + tok + }(tok); + + send(tok, terminator_s, true); + } + +} diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x new file mode 100644 index 0000000000..c93a736404 --- /dev/null +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -0,0 +1,547 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains Huffman literals decoder proc implementation. + +import xls.modules.zstd.common as common; +import xls.modules.zstd.huffman_common as hcommon; +import xls.modules.zstd.huffman_axi_reader as axi_reader; +import xls.modules.zstd.huffman_code_builder as code_builder; +import xls.modules.zstd.huffman_data_preprocessor as data_preprocessor; +import xls.modules.zstd.huffman_decoder as decoder; +import xls.modules.zstd.huffman_prescan as prescan; +import xls.modules.zstd.huffman_ctrl as ctrl; +import xls.modules.zstd.memory.axi as axi; +import xls.examples.ram; + +pub proc HuffmanLiteralsDecoder { + type AxiR = axi::AxiR; + type AxiAr = axi::AxiAr; + + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + + type HuffmanAxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; + + type PrescanInternalReadReq = ram::ReadReq; + type PrescanInternalReadResp = ram::ReadResp<{prescan::WeightPreScanMetaDataSize()}>; + type PrescanInternalWriteReq = ram::WriteReq; + type PrescanInternalWriteResp = ram::WriteResp; + + config ( + // ctrl + ctrl_r: chan in, + // output literals + decoded_literals_s: chan out, + // AXI interface + axi_ar_s: chan out, + axi_r_r: chan in, + // weight memory + ram_read_req_s: chan out, + ram_read_resp_r: chan in, + // code builder loopback + weights_pow_sum_loopback_s: chan out, + weights_pow_sum_loopback_r: chan in, + ) { + let (prescan_start_s, prescan_start_r) = chan("prescan_start"); + let (code_builder_start_s, code_builder_start_r) = chan("code_buider"); + let (axi_reader_ctrl_s, axi_reader_ctrl_r) = chan("axi_reader_ctrl"); + let (data_preprocess_start_s, data_preprocess_start_r) = chan("data_preprocess_start"); + let (decoder_start_s, decoder_start_r) = chan("decoder_start"); + let (decoder_done_s, decoder_done_r) = chan<(), u32:1>("decoder_done"); + let (prescan_response_s, prescan_response_r) = chan("prescan_response"); + let (code_builder_codes_s, code_builder_codes_r) = chan("code_builder_codes"); + let (lookahead_config_s, lookahead_config_r) = chan("lookahead_config"); + let (axi_data_s, axi_data_r) = chan("axi_data"); + let (preprocessed_data_s, preprocessed_data_r) = chan("preprocessed_data"); + + // prescan internal memory + let (prescan_internal_ram_write_req_s, prescan_internal_ram_write_req_r) = chan("prescan_internal_ram_write_req"); + let (prescan_internal_ram_write_resp_s, prescan_internal_ram_write_resp_r) = chan("prescan_internal_ram_write_resp"); + let (prescan_internal_ram_read_req_s, prescan_internal_ram_read_req_r) = chan("prescan_internal_ram_read_req"); + let (prescan_internal_ram_read_resp_s, prescan_internal_ram_read_resp_r) = chan("prescan_internal_ram_read_resp"); + + spawn ram::RamModel<{prescan::WeightPreScanMetaDataSize()}, prescan::RAM_SIZE, {prescan::WeightPreScanMetaDataSize()}>( + prescan_internal_ram_read_req_r, prescan_internal_ram_read_resp_s, + prescan_internal_ram_write_req_r, prescan_internal_ram_write_resp_s, + ); + + spawn ctrl::HuffmanControlAndSequence( + ctrl_r, + prescan_start_s, + code_builder_start_s, + axi_reader_ctrl_s, + data_preprocess_start_s, + decoder_start_s, + decoder_done_r, + ); + + spawn prescan::WeightPreScan( + prescan_start_r, + ram_read_req_s, + ram_read_resp_r, + prescan_response_s, + prescan_internal_ram_read_req_s, + prescan_internal_ram_read_resp_r, + prescan_internal_ram_write_req_s, + prescan_internal_ram_write_resp_r, + ); + + spawn code_builder::WeightCodeBuilder( + code_builder_start_r, + prescan_response_r, + code_builder_codes_s, + lookahead_config_s, + weights_pow_sum_loopback_s, + weights_pow_sum_loopback_r, + ); + + spawn axi_reader::HuffmanAxiReader( + axi_reader_ctrl_r, + axi_r_r, + axi_ar_s, + axi_data_s, + ); + + spawn data_preprocessor::HuffmanDataPreprocessor( + data_preprocess_start_r, + lookahead_config_r, + axi_data_r, + preprocessed_data_s, + ); + + spawn decoder::HuffmanDecoder( + decoder_start_r, + code_builder_codes_r, + preprocessed_data_r, + decoder_done_s, + decoded_literals_s, + ); + + () + } + + init { } + + next (state: ()) { } +} + +const INST_AXI_DATA_W = u32:32; +const INST_AXI_ADDR_W = u32:32; +const INST_AXI_ID_W = u32:32; + +const INST_RAM_ADDR_WIDTH = prescan::RAM_ADDR_WIDTH; +const INST_RAM_ACCESS_WIDTH = prescan::RAM_ACCESS_WIDTH; + +proc HuffmanLiteralsDecoderInst { + type Ctrl = ctrl::HuffmanControlAndSequenceCtrl; + type AxiR = axi::AxiR; + type AxiAr = axi::AxiAr; + + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + + config ( + ctrl_r: chan in, + decoded_literals_s: chan out, + axi_ar_s: chan out, + axi_r_r: chan in, + ram_read_req_s: chan out, + ram_read_resp_r: chan in, + weights_pow_sum_loopback_s: chan out, + weights_pow_sum_loopback_r: chan in, + ) { + spawn HuffmanLiteralsDecoder( + ctrl_r, + decoded_literals_s, + axi_ar_s, + axi_r_r, + ram_read_req_s, + ram_read_resp_r, + weights_pow_sum_loopback_s, + weights_pow_sum_loopback_r, + ); + } + + init { } + + next (state: ()) { } +} + +const TEST_AXI_DATA_W = u32:32; +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_ID_W = u32:32; + +const TEST_RAM_ADDR_WIDTH = prescan::RAM_ADDR_WIDTH; +const TEST_RAM_ACCESS_WIDTH = prescan::RAM_ACCESS_WIDTH; + +type TestCtrl = ctrl::HuffmanControlAndSequenceCtrl; +type TestAxiR = axi::AxiR; +type TestAxiAr = axi::AxiAr; + +type TestReadReq = ram::ReadReq; +type TestReadResp = ram::ReadResp; + +type TestRamEntry = uN[TEST_RAM_ACCESS_WIDTH]; + +// data for test case #0 +const TEST_CTRL_0 = TestCtrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x0, + len: uN[TEST_AXI_ADDR_W]:0x8, + new_config: true +}; + +const TEST_DATA_LEN_0 = u32:64; +const TEST_DATA_0 = ( + u8:0b1_001_010_1 ++ + u8:0b01_010_1_01 ++ + u8:0b0100_001_0 ++ + u8:0b11_010_1_00 ++ + u8:0b001_010_1_0 ++ + u8:0b01_010_000 ++ + u8:0b11_1_1_0001 ++ + u8:0b001_1_010_0 +); + +// code symbol length weight +// 0b1 0x47 1 9 +// 0b001 0x41 3 7 +// 0b010 0x8A 3 7 +// 0b011 0xD2 3 7 +// 0b000001 0x45 6 4 +// 0b000010 0x7A 6 4 +// 0b000011 0x89 6 4 +// 0b000100 0x8D 6 4 +// 0b000101 0xD1 6 4 +// 0b000110 0xD3 6 4 +// 0b000111 0xDA 6 4 +// 0b000000000 0x12 9 1 +// 0b000000001 0x8F 9 1 +// 0b000000010 0xAC 9 1 +// 0b000000011 0xD4 9 1 +// 0b000000100 0xD7 9 1 +// 0b000000101 0xDB 9 1 +// 0b000000110 0xDE 9 1 +// 0b000000111 0xFE 9 1 + +const TEST_WEIGHT_MEMORY_0 = TestRamEntry[32]:[ + // x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x0x + TestRamEntry:0x_0__0__1__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x1x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x2x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x3x + TestRamEntry:0x_0__7__0__0__0__4__0__9, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x4x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x5x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x6x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__4__0__0__0__0__0, // 0x7x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__4__7__0__0__4__0__1, // 0x8x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x9x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__1__0__0__0, // 0xAx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xBx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xCx + TestRamEntry:0x_0__4__7__4__1__0__0__1, TestRamEntry:0x_0__0__4__1__0__0__1__0, // 0xDx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xEx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__1__0, // 0xFx +]; + +const TEST_DECODED_LITERALS_0 = common::LiteralsData[3]:[ + common::LiteralsData { + data: common::LitData:0x458A_D147_47D2_8A47, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x4141_8D47_8AD2_478A, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x478A_41D2_478A, + length: common::LitLength:6, + last: true, + }, +]; + +// data for test case #1 (same config) +const TEST_CTRL_1 = TestCtrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x20, + len: uN[TEST_AXI_ADDR_W]:0x4, + new_config: false +}; + +const TEST_DATA_LEN_1 = u32:32; +const TEST_DATA_1 = ( + u8:0b0010_1_010 ++ + u8:0b000_0_000 ++ + u8:0b1_1_000000 ++ + u8:0b001_011_1_1 +); + +const TEST_DECODED_LITERALS_1 = common::LiteralsData[2]:[ + common::LiteralsData { + data: common::LitData:0x47AC_1247_4747_47D2, + length: common::LitLength:8, + last: false, + }, + common::LiteralsData { + data: common::LitData:0x8A, + length: common::LitLength:1, + last: true, + }, +]; + +// Data for test case #2 +// Source: Example from RFC 8878, 4.2.2. Huffman-Coded Streams +// https://datatracker.ietf.org/doc/html/rfc8878#huffman_coded_streams +// Weights taken from Table 25 +// Bitstream fixed to encode literal sequence "0145" +// See https://www.rfc-editor.org/errata/eid8195 + +const TEST_CTRL_2 = TestCtrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x0, + len: uN[TEST_AXI_ADDR_W]:0x2, + new_config: true +}; + +const TEST_DATA_LEN_2 = u32:16; +const TEST_DATA_2 = u64:0b00000001_00001101; + +// code symbol length weight +// N/A 0x03 0 0 +// 0b0000 0x04 4 1 +// 0b0001 0x05 4 1 +// 0b001 0x02 3 2 +// 0b01 0x01 2 3 +// 0b1 0x00 1 4 + +const TEST_WEIGHT_MEMORY_2 = TestRamEntry[32]:[ + // x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF + TestRamEntry:0x_4__3__2__0__1__1__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x0x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x1x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x2x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x3x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x4x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x5x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x6x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x7x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x8x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x9x + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xAx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xBx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xCx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xDx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xEx + TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xFx +]; + +const TEST_DECODED_LITERALS_2 = common::LiteralsData[1]:[ + common::LiteralsData { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: true, + }, +]; +#[test_proc] +proc HuffmanLiteralsDecoder_test { + terminator: chan out; + + ctrl_s: chan out; + decoded_literals_r: chan in; + axi_ar_r: chan in; + axi_r_s: chan out; + ram_read_req_r: chan in; + ram_read_resp_s: chan out; + + config (terminator: chan out) { + let (ctrl_s, ctrl_r) = chan("ctrl"); + let (decoded_literals_s, decoded_literals_r) = chan("decoded_literals"); + let (axi_ar_s, axi_ar_r) = chan("axi_ar"); + let (axi_r_s, axi_r_r) = chan("axi_r"); + let (ram_read_req_s, ram_read_req_r) = chan("ram_read_req"); + let (ram_read_resp_s, ram_read_resp_r) = chan("ram_read_resp"); + let (weights_pow_sum_loopback_s, weights_pow_sum_loopback_r) = chan("weights_pow_sum_loopback"); + + spawn HuffmanLiteralsDecoder( + ctrl_r, decoded_literals_s, + axi_ar_s, axi_r_r, + ram_read_req_s, ram_read_resp_r, + weights_pow_sum_loopback_s, weights_pow_sum_loopback_r, + ); + + ( + terminator, + ctrl_s, decoded_literals_r, + axi_ar_r, axi_r_s, + ram_read_req_r, ram_read_resp_s, + ) + } + + init { } + + next (state: ()) { + let tok = join(); + + trace_fmt!("Test Case #1"); + // send ctrl + let tok = send(tok, ctrl_s, TEST_CTRL_0); + trace_fmt!("Sent #1 ctrl {:#x}", TEST_CTRL_0); + + // receive RAM read requests and send responses + trace_fmt!("Sending weight memory content"); + let tok = for (_, tok): (u32, token) in range(u32:0, u32:2) { + for (i, tok):(u32, token) in range(u32:0, array_size(TEST_WEIGHT_MEMORY_0)) { + let (tok, ram_read_req) = recv(tok, ram_read_req_r); + trace_fmt!("Received #{} ReadReq {:#x}", i + u32:1, ram_read_req); + + let read_resp = TestReadResp { + data: TEST_WEIGHT_MEMORY_0[ram_read_req.addr] as u32, + }; + + let tok = send(tok, ram_read_resp_s, read_resp); + trace_fmt!("Sent #{} ReadResp {:#x}", i + u32:1, read_resp); + + tok + }(tok) + }(tok); + + // receive Axi requests and send responses + trace_fmt!("Sending data from AXI"); + const AXI_READS_NUM = (TEST_DATA_LEN_0 + u32:7) / u32:8; + let tok = for (i, tok):(u32, token) in range(u32:0, AXI_READS_NUM) { + let expected_axi_ar = TestAxiAr { + addr: TEST_CTRL_0.base_addr + (AXI_READS_NUM - u32:1 - i) as uN[TEST_AXI_ADDR_W], + ..zero!() + }; + let (tok, axi_ar) = recv(tok, axi_ar_r); + trace_fmt!("Received #{} AxiAr {:#x}", i + u32:1, axi_ar); + assert_eq(expected_axi_ar, axi_ar); + + let axi_r = TestAxiR { + id: axi_ar.id, + data: (TEST_DATA_0 >> (u32:8 * i)) as u32, + resp: axi::AxiReadResp::OKAY, + last: i == (AXI_READS_NUM - u32:1), + }; + + let tok = send(tok, axi_r_s, axi_r); + trace_fmt!("Sent #{} AxiR {:#x}", i + u32:1, axi_r); + + tok + }(tok); + + // receive decoded literals + let tok = for ((i, test_decoded_literals), tok):((u32, common::LiteralsData), token) in enumerate(TEST_DECODED_LITERALS_0) { + let (tok, decoded_literals) = recv(tok, decoded_literals_r); + trace_fmt!("Received #{} decoded literals {:#x}", i + u32:1, decoded_literals); + assert_eq(test_decoded_literals, decoded_literals); + tok + }(tok); + + trace_fmt!("Test Case #2"); + // send ctrl + let tok = send(tok, ctrl_s, TEST_CTRL_1); + trace_fmt!("Sent #2 ctrl {:#x}", TEST_CTRL_1); + + // receive Axi requests and send responses + trace_fmt!("Sending data from AXI"); + const AXI_READS_NUM = (TEST_DATA_LEN_1 + u32:7) / u32:8; + let tok = for (i, tok):(u32, token) in range(u32:0, AXI_READS_NUM) { + let expected_axi_ar = TestAxiAr { + addr: TEST_CTRL_1.base_addr + (AXI_READS_NUM - u32:1 - i) as uN[TEST_AXI_ADDR_W], + ..zero!() + }; + let (tok, axi_ar) = recv(tok, axi_ar_r); + trace_fmt!("Received #{} AxiAr {:#x}", i + u32:1, axi_ar); + assert_eq(expected_axi_ar, axi_ar); + + let axi_r = TestAxiR { + id: axi_ar.id, + data: (TEST_DATA_1 >> (u32:8 * i)) as u32, + resp: axi::AxiReadResp::OKAY, + last: i == (AXI_READS_NUM - u32:1), + }; + + let tok = send(tok, axi_r_s, axi_r); + trace_fmt!("Sent #{} AxiR {:#x}", i + u32:1, axi_r); + + tok + }(tok); + + // receive decoded literals + let tok = for ((i, test_decoded_literals), tok):((u32, common::LiteralsData), token) in enumerate(TEST_DECODED_LITERALS_1) { + let (tok, decoded_literals) = recv(tok, decoded_literals_r); + trace_fmt!("Received #{} decoded literals {:#x}", i + u32:1, decoded_literals); + assert_eq(test_decoded_literals, decoded_literals); + tok + }(tok); + + trace_fmt!("Test Case #3"); + // send ctrl + let tok = send(tok, ctrl_s, TEST_CTRL_2); + trace_fmt!("Sent #3 ctrl {:#x}", TEST_CTRL_2); + + // receive RAM read requests and send responses + trace_fmt!("Sending weight memory content"); + let tok = for (_, tok): (u32, token) in range(u32:0, u32:2) { + for (i, tok):(u32, token) in range(u32:0, array_size(TEST_WEIGHT_MEMORY_2)) { + let (tok, ram_read_req) = recv(tok, ram_read_req_r); + trace_fmt!("Received #{} ReadReq {:#x}", i + u32:1, ram_read_req); + + let read_resp = TestReadResp { + data: TEST_WEIGHT_MEMORY_2[ram_read_req.addr] as u32, + }; + + let tok = send(tok, ram_read_resp_s, read_resp); + trace_fmt!("Sent #{} ReadResp {:#x}", i + u32:1, read_resp); + + tok + }(tok) + }(tok); + + // receive Axi requests and send responses + trace_fmt!("Sending data from AXI"); + const AXI_READS_NUM = (TEST_DATA_LEN_2 + u32:7) / u32:8; + let tok = for (i, tok):(u32, token) in range(u32:0, AXI_READS_NUM) { + let expected_axi_ar = TestAxiAr { + addr: TEST_CTRL_2.base_addr + (AXI_READS_NUM - u32:1 - i) as uN[TEST_AXI_ADDR_W], + ..zero!() + }; + let (tok, axi_ar) = recv(tok, axi_ar_r); + trace_fmt!("Received #{} AxiAr {:#x}", i + u32:1, axi_ar); + assert_eq(expected_axi_ar, axi_ar); + + let axi_r = TestAxiR { + id: axi_ar.id, + data: (TEST_DATA_2 >> (u32:8 * i)) as u32, + resp: axi::AxiReadResp::OKAY, + last: i == (AXI_READS_NUM - u32:1), + }; + + let tok = send(tok, axi_r_s, axi_r); + trace_fmt!("Sent #{} AxiR {:#x}", i + u32:1, axi_r); + + tok + }(tok); + + // receive decoded literals + let tok = for ((i, test_decoded_literals), tok):((u32, common::LiteralsData), token) in enumerate(TEST_DECODED_LITERALS_2) { + let (tok, decoded_literals) = recv(tok, decoded_literals_r); + trace_fmt!("Received #{} decoded literals {:#x}", i + u32:1, decoded_literals); + assert_eq(test_decoded_literals, decoded_literals); + tok + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/huffman_prescan.x b/xls/modules/zstd/huffman_prescan.x new file mode 100644 index 0000000000..4cc49c9cd5 --- /dev/null +++ b/xls/modules/zstd/huffman_prescan.x @@ -0,0 +1,431 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains the implementation of Huffmann tree decoder. + +import std; +import xls.dslx.stdlib.acm_random as random; + +import xls.examples.ram; +import xls.modules.zstd.common as common; +import xls.modules.zstd.huffman_common as hcommon; + +// TODO: Enable once parametrics work +//fn WeightPreScanMetaDataSize(PARALLEL_ACCESS_WIDTH: u32) -> u32 { +// let COUNTER_WIDTH = {std::clog2(PARALLEL_ACCESS_WIDTH + u32:1)}; +// (COUNTER_WIDTH as u32) * (PARALLEL_ACCESS_WIDTH as u32) + +// (MAX_WEIGHT as u32) + u32:1 + +// (COUNTER_WIDTH as u32) * (MAX_WEIGHT as u32 + u32:1) +//} +// +//fn InternalStructToBits< +// PARALLEL_ACCESS_WIDTH: u32, +// BITS: u32 = {WeightPreScanMetaDataSize(PARALLEL_ACCESS_WIDTH)} +//> (internalStruct: WeightPreScanMetaData) -> bits[BITS] { +// internalStruct as bits[BITS] +//} +// +//fn BitsToInternalStruct< +// PARALLEL_ACCESS_WIDTH: u32, +// BITS: u32 = {WeightPreScanMetaDataSize(PARALLEL_ACCESS_WIDTH)} +//> (rawBits: bits[BITS]) -> WeightPreScanMetaData { +// rawBits as WeightPreScanMetaData +//} + +const MAX_WEIGHT = hcommon::MAX_WEIGHT; +const WEIGHT_LOG = hcommon::WEIGHT_LOG; +const MAX_SYMBOL_COUNT = hcommon::MAX_SYMBOL_COUNT; + +const PARALLEL_ACCESS_WIDTH = hcommon::PARALLEL_ACCESS_WIDTH; +const COUNTER_WIDTH = hcommon::COUNTER_WIDTH; + +type WeightPreScanMetaData = hcommon::WeightPreScanMetaData; +type WeightPreScanOutput = hcommon::WeightPreScanOutput; + +pub fn WeightPreScanMetaDataSize() -> u32 { + (COUNTER_WIDTH as u32) * (PARALLEL_ACCESS_WIDTH as u32) + + (MAX_WEIGHT as u32) + u32:1 + + (COUNTER_WIDTH as u32) * (MAX_WEIGHT as u32 + u32:1) +} + +fn InternalStructToBits< + BITS: u32 = {WeightPreScanMetaDataSize()}, + OCCURANCE_WIDTH: u32 ={COUNTER_WIDTH * PARALLEL_ACCESS_WIDTH}, +> (internalStruct: WeightPreScanMetaData) -> bits[BITS] { + (internalStruct.weights_count as bits[COUNTER_WIDTH * (MAX_WEIGHT + u32:1)] ++ + internalStruct.valid_weights as bits[MAX_WEIGHT + u32:1] ++ + internalStruct.occurance_number as bits[OCCURANCE_WIDTH]) as bits[BITS] +} + +fn BitsToInternalStruct< + BITS: u32 = {WeightPreScanMetaDataSize()}, + OCCURANCE_WIDTH: u32 ={COUNTER_WIDTH * PARALLEL_ACCESS_WIDTH}, +> (rawBits: bits[BITS]) -> WeightPreScanMetaData { + WeightPreScanMetaData { + occurance_number: rawBits[0:OCCURANCE_WIDTH as s32] as uN[COUNTER_WIDTH][PARALLEL_ACCESS_WIDTH], + valid_weights: rawBits[OCCURANCE_WIDTH as s32:(OCCURANCE_WIDTH + MAX_WEIGHT + u32:1) as s32] as u1[MAX_WEIGHT + u32:1], + weights_count: rawBits[(OCCURANCE_WIDTH + MAX_WEIGHT + u32:1) as s32:BITS as s32] as uN[COUNTER_WIDTH][MAX_WEIGHT + u32:1] + } +} + +#[quickcheck(test_count=50000)] +fn bits_to_struct_to_bits_qtest(x: bits[WeightPreScanMetaDataSize()]) -> bool { + x == InternalStructToBits(BitsToInternalStruct(x)) +} + +#[quickcheck(test_count=50000)] +fn struct_to_bots_to_struct_qtest(x: WeightPreScanMetaData) -> bool { + x == BitsToInternalStruct(InternalStructToBits(x)) +} + +pub const RAM_SIZE = MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH * u32:8 / WEIGHT_LOG; +pub const RAM_ADDR_WIDTH = {std::clog2(RAM_SIZE)}; +pub const RAM_ACCESS_WIDTH = PARALLEL_ACCESS_WIDTH * WEIGHT_LOG; +const MAX_RAM_ADDR = MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH; + +enum WeightPreScanFSM: u2 { + IDLE = u2:0, + FIRST_RUN = u2:1, + SECOND_RUN = u2:2, +} + +struct WeightPreScanState { + fsm: WeightPreScanFSM, + addr: u9, + internal_addr: u9, +} + +pub proc WeightPreScan +// TODO: enable parametric expresion when they start working +//proc WeightPreScan< +// PARALLEL_ACCESS_WIDTH: u32 = {u32:8}, +// RAM_SIZE: u32 = {MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH}, +// RAM_ADDR_WIDTH: u32 = {std::clog2(RAM_SIZE)}, +// RAM_ACCESS_WIDTH: u32 = {PARALLEL_ACCESS_WIDTH * WEIGHT_LOG}, +// MAX_RAM_ADDR: u32 = {(u32:1< { +{ + type State = WeightPreScanState; + type FSM = WeightPreScanFSM; + + type ExternalRamAddr = uN[RAM_ADDR_WIDTH]; + type ExternalRamData = uN[RAM_ACCESS_WIDTH]; + + type OutData = WeightPreScanOutput; + + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + + type InternalRamAddr = uN[RAM_ADDR_WIDTH]; + type InternalData = WeightPreScanMetaData; + type InternalRamData = bits[WeightPreScanMetaDataSize()]; + + type InternalReadReq = ram::ReadReq; + type InternalReadResp = ram::ReadResp<{WeightPreScanMetaDataSize()}>; + type InternalWriteReq = ram::WriteReq; + type InternalWriteResp = ram::WriteResp; + + start_r: chan in; + read_req_s: chan out; + read_rsp_r: chan in; + weight_s: chan out; + + internal_read_req_s: chan out; + internal_read_rsp_r: chan in; + internal_write_req_s: chan out; + internal_write_rsp_r: chan in; + + internal_memory_written_s: chan out; + internal_memory_written_r: chan in; + + config ( + start_r: chan in, + read_req_s: chan out, + read_rsp_r: chan in, + weight_s: chan out, + internal_read_req_s: chan out, + internal_read_rsp_r: chan in, + internal_write_req_s: chan out, + internal_write_rsp_r: chan in + ) { + let (internal_memory_written_s, internal_memory_written_r) = + chan("internal_loopback"); + (start_r, read_req_s, read_rsp_r, weight_s, + internal_read_req_s, internal_read_rsp_r, + internal_write_req_s, internal_write_rsp_r, + internal_memory_written_s, internal_memory_written_r) + } + + init {zero!()} + + next(state: State) { + let tok = join(); + let (recv_start, send_addr, write_internal, read_internal, addr) = match state.fsm { + FSM::IDLE => (true, false, false, false, u32:0 as ExternalRamAddr), + FSM::FIRST_RUN => (false, true, true, false, state.addr as ExternalRamAddr), + FSM::SECOND_RUN => { + let valid_data = state.addr < state.internal_addr || state.internal_addr as u32 == MAX_RAM_ADDR - u32:1; + (false, valid_data, false, valid_data, state.addr as ExternalRamAddr) + }, + _ => { + assert!(false, "Invalid state"); + (false, false, false, false, u9:0 as ExternalRamAddr) + } + }; + let (tok1, start) = recv_if(tok, start_r, recv_start, false); + + let (tok2, internal_addr, _) = recv_non_blocking(tok, internal_memory_written_r, state.internal_addr as InternalRamAddr); + let next_state = match (state.fsm, start, send_addr, state.addr as u32 == MAX_RAM_ADDR - u32:1) { + (FSM::IDLE, true, _, _) => State { + fsm: FSM::FIRST_RUN, + addr: u9:0, + internal_addr: u9:0 + }, + (FSM::FIRST_RUN, _, false, _) => State { + fsm: FSM::FIRST_RUN, + addr: state.addr, + internal_addr: internal_addr as u9 + }, + (FSM::FIRST_RUN, _, true, false) => State { + fsm: FSM::FIRST_RUN, + addr: state.addr + u9:1, + internal_addr: internal_addr as u9 + }, + (FSM::FIRST_RUN, _, true, true) => State { + fsm: FSM::SECOND_RUN, + addr: u9:0, + internal_addr: internal_addr as u9 + }, + (FSM::SECOND_RUN, _, false, _) => State { + fsm: FSM::SECOND_RUN, + addr: state.addr, + internal_addr: internal_addr as u9 + }, + (FSM::SECOND_RUN, _, true, false) => State { + fsm: FSM::SECOND_RUN, + addr: state.addr + u9:1, + internal_addr: internal_addr as u9 + }, + (FSM::SECOND_RUN, _, true, true) => State { + fsm: FSM::IDLE, + addr: u9:0, + internal_addr: internal_addr as u9 + }, + _ => { + assert!(false, "Invalid state"); + State { + fsm: FSM::IDLE, + addr: u9:0, + internal_addr: u9:0 + } + } + }; + + let external_ram_req = ReadReq { + addr: addr, + mask: u1:1, + }; + let tok3 = send_if(tok, read_req_s, send_addr, external_ram_req); + let (tok3, ram_data) = recv_if(tok3, read_rsp_r, send_addr, zero!()); + let ram_data = ram_data.data as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH]; + + let internal_ram_r_req = InternalReadReq { + addr: addr, + mask: u1:1, + }; + let tok4 = send_if(tok, internal_read_req_s, read_internal, internal_ram_r_req); + let (tok4, meta_data_flat) = recv_if(tok4, internal_read_rsp_r, read_internal, zero!()); + let meta_data = BitsToInternalStruct(meta_data_flat.data); + let tok34 = join(tok3, tok4); + + let prescan_output = OutData { + weights: ram_data, + meta_data: meta_data + }; + let tok34 = send_if(tok34, weight_s, send_addr, prescan_output); + + let occurance_matrix = for (i, occurance_matrix) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let row = for (j, row) in range(u32:0, MAX_WEIGHT + u32:1) { + if (ram_data[i] == j as uN[COUNTER_WIDTH]) { + update(row, j, row[j] + uN[COUNTER_WIDTH]:1) + } else { row } + } (occurance_matrix[i]); + update(occurance_matrix, i + u32:1, row) + }(zero!()); + + let valid_weights = for(i, valid_weights) in range(u32:0, MAX_WEIGHT + u32:1) { + if (occurance_matrix[PARALLEL_ACCESS_WIDTH][i] != uN[COUNTER_WIDTH]:0) { + update(valid_weights, i, true) + } else { valid_weights } + }(zero!()); + + let occurance_number = for (i, occurance_number) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let number = occurance_matrix[i][ram_data[i]]; + update(occurance_number, i, number) + }(zero!()); + let _meta_data = WeightPreScanMetaData { + occurance_number: occurance_number, + valid_weights: valid_weights, + weights_count: occurance_matrix[PARALLEL_ACCESS_WIDTH], + }; + + let internal_ram_w_req = InternalWriteReq { + addr: addr, + data: InternalStructToBits(_meta_data), + mask: u1:1 + }; + let tok5 = send_if(tok, internal_write_req_s, write_internal, internal_ram_w_req); + let (tok5, _) = recv_if(tok5, internal_write_rsp_r, write_internal, zero!()); + send_if(tok5, internal_memory_written_s, state.fsm == FSM::FIRST_RUN, addr as InternalRamAddr); + next_state + } +} + +#[test_proc] +proc Prescan_test{ + type external_ram_addr = uN[RAM_ADDR_WIDTH]; + type external_ram_data = uN[RAM_ACCESS_WIDTH]; + + type PrescanOut = WeightPreScanOutput; + + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp<>; + + type InternalReadReq = ram::ReadReq; + type InternalReadResp = ram::ReadResp<{WeightPreScanMetaDataSize()}>; + type InternalWriteReq = ram::WriteReq; + type InternalWriteResp = ram::WriteResp<>; + + terminator: chan out; + external_ram_req: chan out; + external_ram_resp: chan in; + start_prescan: chan out; + prescan_response: chan in; + init{()} + config (terminator: chan out) { + // Emulate external memory + let (RAMExternalWriteReq_s, RAMExternalWriteReq_r) = chan("Write_channel_req"); + let (RAMExternalWriteResp_s, RAMExternalWriteResp_r) = chan("Write_channel_resp"); + let (RAMExternalReadReq_s, RAMExternalReadReq_r) = chan("Read_channel_req"); + let (RAMExternalReadResp_s, RAMExternalReadResp_r) = chan("Read_channel_resp"); + spawn ram::RamModel( + RAMExternalReadReq_r, RAMExternalReadResp_s, RAMExternalWriteReq_r, RAMExternalWriteResp_s + ); + + // Emulate Internal prescan memory + let (RAMInternalWriteReq_s, RAMInternalWriteReq_r) = chan("Internal_write_channel_req"); + let (RAMInternalWriteResp_s, RAMInternalWriteResp_r) = chan("Internal_write_channel_resp"); + let (RAMInternalReadReq_s, RAMInternalReadReq_r) = chan("Internal_read_channel_req"); + let (RAMInternalReadResp_s, RAMInternalReadResp_r) = chan("Internal_read_channel_resp"); + spawn ram::RamModel<{WeightPreScanMetaDataSize()}, RAM_SIZE, {WeightPreScanMetaDataSize()}>( + RAMInternalReadReq_r, RAMInternalReadResp_s, RAMInternalWriteReq_r, RAMInternalWriteResp_s + ); + + let (PreScanStart_s, PreScanStart_r) = chan("Start_prescan"); + let (PreScanResponse_s, PreScanResponse_r) = chan("Start_prescan"); + spawn WeightPreScan( + PreScanStart_r, RAMExternalReadReq_s,RAMExternalReadResp_r, PreScanResponse_s, + RAMInternalReadReq_s, RAMInternalReadResp_r, RAMInternalWriteReq_s, RAMInternalWriteResp_r); + (terminator, RAMExternalWriteReq_s, RAMExternalWriteResp_r, PreScanStart_s, PreScanResponse_r) + } + next(state: ()) { + let tok = join(); + let rand_state = random::rng_new(random::rng_deterministic_seed()); + // Setup external memory with random values + for (i, rand_state) in range(u32:0, MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH) { + let (new_rand_state, data_to_send) = for (j, (rand_state, data_to_send)) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let (new_rand_state, data) = random::rng_next(rand_state); + let weight = (data - (data/u32:12) * u32:12) as u4; + let new_data_to_send = update(data_to_send as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], j, weight) as external_ram_data; + (new_rand_state, new_data_to_send) + }((rand_state, zero!())); + let external_w_req = WriteReq { + addr: i as uN[RAM_ADDR_WIDTH], + data: data_to_send, + mask: u1:1 + }; + send(tok, external_ram_req, external_w_req); + recv(tok, external_ram_resp); + new_rand_state + }(rand_state); + send(tok, start_prescan, true); + // First run + for (_, rand_state) in range(u32:0, MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH) { + // Generate expected output + let (new_rand_state, expected_data) = for (j, (rand_state, data_to_send)) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let (new_rand_state, data) = random::rng_next(rand_state); + let weight = (data - (data/u32:12) * u32:12) as u4; + let new_data_to_send = update(data_to_send as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], j, weight) as external_ram_data; + (new_rand_state, new_data_to_send) + }((rand_state, zero!())); + let (_, prescan_resp) = recv(tok, prescan_response); + let expected_data = PrescanOut { + weights: expected_data as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], + meta_data: zero!() + }; + assert_eq(prescan_resp, expected_data); + new_rand_state + }(rand_state); + + // Second run + for (_, rand_state) in range(u32:0, MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH) { + // Generate expected output + let (new_rand_state, expected_data) = for (j, (rand_state, data_to_send)) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let (new_rand_state, data) = random::rng_next(rand_state); + let weight = (data - (data/u32:12) * u32:12) as u4; + let new_data_to_send = update(data_to_send as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH], j, weight) as external_ram_data; + (new_rand_state, new_data_to_send) + }((rand_state, zero!())); + let expected_data = expected_data as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH]; + let valid_weights = for (i, seen_weights) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + update(seen_weights, expected_data[i], true) + }(zero!()); + let occurance_number = for (i, occurance_number) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + let number = for (j, number) in range(u32:0, PARALLEL_ACCESS_WIDTH){ + if (j < i && expected_data[j] == expected_data[i]) { + number + u4:1 + } else { + number + } + }(zero!()); + update(occurance_number, i, number) + }(zero!()); + let weights_count = for (i, weights_count) in range(u32:0, MAX_WEIGHT + u32:1) { + let count = for (j, count) in range(u32:0, PARALLEL_ACCESS_WIDTH) { + if (expected_data[j] == i as uN[COUNTER_WIDTH]) { + count + uN[COUNTER_WIDTH]:1 + } else { + count + } + }(zero!()); + update(weights_count, i, count) + }(zero!()); + let (_, prescan_resp) = recv(tok, prescan_response); + let expected_data = PrescanOut { + weights: expected_data, + meta_data: WeightPreScanMetaData { + occurance_number: occurance_number, + valid_weights: valid_weights, + weights_count: weights_count, + } + }; + assert_eq(prescan_resp, expected_data); + new_rand_state + }(rand_state); + + send(tok, terminator, true); + } +} From 78eee27d8159c0aa19280c780827c0f70b61ac6d Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 12 Dec 2024 17:14:20 +0100 Subject: [PATCH 42/85] modules/zstd: Add triple output RamDemux Add 3:1 demultiplexer for RamModel Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 87 +++++++++ xls/modules/zstd/ram_demux3.x | 337 ++++++++++++++++++++++++++++++++++ 2 files changed, 424 insertions(+) create mode 100644 xls/modules/zstd/ram_demux3.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 19c2595e26..67027a48ac 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1809,6 +1809,93 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "ram_demux3_dslx", + srcs = ["ram_demux3.x"], + deps = [":ram_demux_dslx"], +) + +xls_dslx_test( + name = "ram_demux3_dslx_test", + library = ":ram_demux3_dslx", +) + +xls_dslx_verilog( + name = "ram_demux3_verilog", + codegen_args = { + "module_name": "RamDemux3", + "generator": "pipeline", + "delay_model": "asap7", + "ram_configurations": ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram{}".format(num), + rd_req = "ram_demux3__rd_req{}_s".format(num), + rd_resp = "ram_demux3__rd_resp{}_r".format(num), + wr_req = "ram_demux3__wr_req{}_s".format(num), + wr_resp = "ram_demux3__wr_resp{}_r".format(num), + ) + for num in range(3) + ]), + "pipeline_stages": "6", + "reset": "rst", + "use_system_verilog": "false", + "multi_proc": "true", + }, + dslx_top = "RamDemux3Inst", + library = ":ram_demux3_dslx", + verilog_file = "ram_demux3.v", +) + +xls_benchmark_ir( + name = "ram_demux3_opt_ir_benchmark", + src = ":ram_demux3_verilog.opt.ir", + benchmark_ir_args = { + "delay_model": "asap7", + "pipeline_stages": "3", + "inline_procs": "false" + }, + tags = ["manual"], +) + +verilog_library( + name = "ram_demux3_verilog_lib", + srcs = [ + ":ram_demux3.v", + ":xls_fifo_wrapper.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "ram_demux3_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "RamDemux3", + deps = [ + ":ram_demux3_verilog_lib", + ], +) + +benchmark_synth( + name = "ram_demux3_benchmark_synth", + synth_target = ":ram_demux3_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "ram_demux3_place_and_route", + clock_period = "750", + core_padding_microns = 2, + die_height_microns = 100, + die_width_microns = 100, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":ram_demux3_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) xls_dslx_library( name = "literals_dispatcher_dslx", srcs = [ diff --git a/xls/modules/zstd/ram_demux3.x b/xls/modules/zstd/ram_demux3.x new file mode 100644 index 0000000000..1548c4aa03 --- /dev/null +++ b/xls/modules/zstd/ram_demux3.x @@ -0,0 +1,337 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains a RamDemux implementation that can be used to connect +// a single proc with two RAM instances, by using a single RAM interface and +// switching between the RAMs, when requested. The switching occurs only after +// each request has received the corresponding response. +// Additionally, a "naive" implementation is provided that does not ensure +// any synchronization when switching RAMs. + +import std; +import xls.examples.ram; +import xls.modules.zstd.ram_demux; + +pub proc RamDemux3< + ADDR_WIDTH: u32, + DATA_WIDTH: u32, + NUM_PARTITIONS: u32, + INIT_SEL: u2 = {u2:0}, + QUEUE_LEN: u32 = {u32:5}, + D1_INIT_SEL: u1 = {INIT_SEL == u2:1 || INIT_SEL == u2:2}, + D2_INIT_SEL: u1 = {INIT_SEL == u2:2 || INIT_SEL == u2:3}, +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + sel_req_r: chan in; + sel_resp_s: chan<()> out; + d1_sel_req_s: chan out; + d1_sel_resp_r: chan<()> in; + d2_sel_req_s: chan out; + d2_sel_resp_r: chan<()> in; + + config( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + + rd_req_r: chan in, + rd_resp_s: chan out, + wr_req_r: chan in, + wr_resp_s: chan out, + + rd_req0_s: chan out, + rd_resp0_r: chan in, + wr_req0_s: chan out, + wr_resp0_r: chan in, + + rd_req1_s: chan out, + rd_resp1_r: chan in, + wr_req1_s: chan out, + wr_resp1_r: chan in, + + rd_req2_s: chan out, + rd_resp2_r: chan in, + wr_req2_s: chan out, + wr_resp2_r: chan in + + ) { + const CHANNEL_DEPTH = u32:1; + + let (d1_sel_req_s, d1_sel_req_r) = chan("d1_sel_req"); + let (d1_sel_resp_s, d1_sel_resp_r) = chan<(), CHANNEL_DEPTH>("d1_sel_resp"); + + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + + spawn ram_demux::RamDemux( + d1_sel_req_r, d1_sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + ); + + let (d2_sel_req_s, d2_sel_req_r) = chan("d2_sel_req"); + let (d2_sel_resp_s, d2_sel_resp_r) = chan<(), CHANNEL_DEPTH>("d2_sel_resp"); + + spawn ram_demux::RamDemux( + d2_sel_req_r, d2_sel_resp_s, + tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + rd_req2_s, rd_resp2_r, wr_req2_s, wr_resp2_r + ); + + ( + sel_req_r, sel_resp_s, + d1_sel_req_s, d1_sel_resp_r, + d2_sel_req_s, d2_sel_resp_r, + ) + } + + init { } + + next(state: ()) { + let tok = join(); + let (tok, sel) = recv(tok, sel_req_r); + + let (sel1, sel2) = match sel { + u2:0 => (u1:0, u1:0), + u2:1 => (u1:1, u1:0), + u2:2 => (u1:1, u1:1), + _ => (u1:0, u1:1), + }; + + let tok1_0 = send(tok, d1_sel_req_s, sel1); + let (tok2_0, ()) = recv(tok1_0, d1_sel_resp_r); + + let tok1_1 = send(tok, d2_sel_req_s, sel2); + let (tok2_1, ()) = recv(tok, d2_sel_resp_r); + + let tok2 = join(tok2_0, tok2_1); + send(tok2, sel_resp_s, ()); + } +} + +const RAM_SIZE = u32:32; +const RAM_DATA_WIDTH = u32:8; +const RAM_ADDR_WIDTH = std::clog2(RAM_SIZE); +const RAM_WORD_PARTITION_SIZE = u32:1; +const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH); + +pub proc RamDemux3Inst { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + config( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + + rd_req_r: chan in, + rd_resp_s: chan out, + wr_req_r: chan in, + wr_resp_s: chan out, + + rd_req0_s: chan out, + rd_resp0_r: chan in, + wr_req0_s: chan out, + wr_resp0_r: chan in, + + rd_req1_s: chan out, + rd_resp1_r: chan in, + wr_req1_s: chan out, + wr_resp1_r: chan in, + + rd_req2_s: chan out, + rd_resp2_r: chan in, + wr_req2_s: chan out, + wr_resp2_r: chan in + + ) { + spawn RamDemux3( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + rd_req2_s, rd_resp2_r, wr_req2_s, wr_resp2_r + ); + } + + init { } + + next(state: ()) { } +} + +const TEST_RAM_SIZE = u32:32; +const TEST_RAM_DATA_WIDTH = u32:8; +const TEST_RAM_ADDR_WIDTH = std::clog2(TEST_RAM_SIZE); +const TEST_RAM_WORD_PARTITION_SIZE = u32:1; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_WIDTH); +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_INITIALIZED = true; +const TEST_DEMUX_INIT_SEL = u2:0; +const TEST_DEMUX_QUEUE_LEN = u32:5; + +#[test_proc] +proc RamDemux3Test { + + type WriteReq = ram::WriteReq; + type ReadResp = ram::ReadResp; + type ReadReq = ram::ReadReq; + type WriteResp = ram::WriteResp; + + type Addr = uN[TEST_RAM_ADDR_WIDTH]; + type Data = uN[TEST_RAM_DATA_WIDTH]; + type Mask = uN[TEST_RAM_NUM_PARTITIONS]; + + terminator: chan out; + + sel_req_s: chan out; + sel_resp_r: chan<()> in; + + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + wr_resp_r: chan in; + + rd_req0_s: chan out; + rd_resp0_r: chan in; + wr_req0_s: chan out; + wr_resp0_r: chan in; + + rd_req1_s: chan out; + rd_resp1_r: chan in; + wr_req1_s: chan out; + wr_resp1_r: chan in; + + rd_req2_s: chan out; + rd_resp2_r: chan in; + wr_req2_s: chan out; + wr_resp2_r: chan in; + + config(terminator: chan out) { + let (sel_req_s, sel_req_r) = chan("sel_req"); + let (sel_resp_s, sel_resp_r) = chan<()>("sel_resp"); + + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + let (rd_req0_s, rd_req0_r) = chan("rd_req0"); + let (rd_resp0_s, rd_resp0_r) = chan("rd_resp0"); + let (wr_req0_s, wr_req0_r) = chan("wr_req0"); + let (wr_resp0_s, wr_resp0_r) = chan("wr_resp0"); + + let (rd_req1_s, rd_req1_r) = chan("rd_req1"); + let (rd_resp1_s, rd_resp1_r) = chan("rd_resp1"); + let (wr_req1_s, wr_req1_r) = chan("wr_req1"); + let (wr_resp1_s, wr_resp1_r) = chan("wr_resp1"); + + let (rd_req2_s, rd_req2_r) = chan("rd_req2"); + let (rd_resp2_s, rd_resp2_r) = chan("rd_resp2"); + let (wr_req2_s, wr_req2_r) = chan("wr_req2"); + let (wr_resp2_s, wr_resp2_r) = chan("wr_resp2"); + + spawn RamDemux3< + TEST_RAM_ADDR_WIDTH, TEST_RAM_DATA_WIDTH, TEST_RAM_NUM_PARTITIONS, + TEST_DEMUX_INIT_SEL, TEST_DEMUX_QUEUE_LEN + >( + sel_req_r, sel_resp_s, + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + rd_req2_s, rd_resp2_r, wr_req2_s, wr_resp2_r, + ); + + spawn ram::RamModel< + TEST_RAM_DATA_WIDTH, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >(rd_req0_r, rd_resp0_s, wr_req0_r, wr_resp0_s); + + spawn ram::RamModel< + TEST_RAM_DATA_WIDTH, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >(rd_req1_r, rd_resp1_s, wr_req1_r, wr_resp1_s); + + spawn ram::RamModel< + TEST_RAM_DATA_WIDTH, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >(rd_req2_r, rd_resp2_s, wr_req2_r, wr_resp2_s); + + ( + terminator, sel_req_s, sel_resp_r, + rd_req_s, rd_resp_r, wr_req_s, wr_resp_r, + rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, + rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, + rd_req2_s, rd_resp2_r, wr_req2_s, wr_resp2_r, + ) + } + + init { } + + next(state: ()) { + let tok = join(); + + // Writes + + let tok = send(tok, sel_req_s, u2:0); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, wr_req_s, WriteReq { addr: Addr:0, data: Data:0xA, mask: !Mask:0 }); + let (tok, _) = recv(tok, wr_resp_r); + + let tok = send(tok, sel_req_s, u2:1); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, wr_req_s, WriteReq { addr: Addr:0, data: Data:0xB, mask: !Mask:0 }); + let (tok, _) = recv(tok, wr_resp_r); + + let tok = send(tok, sel_req_s, u2:2); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, wr_req_s, WriteReq { addr: Addr:0, data: Data:0xC, mask: !Mask:0 }); + let (tok, _) = recv(tok, wr_resp_r); + + // Reads + + let tok = send(tok, sel_req_s, u2:0); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, rd_req_s, ReadReq { addr: Addr:0, mask: !Mask:0 }); + let (tok, resp) = recv(tok, rd_resp_r); + trace_fmt!("Value read from the first RAM: {:#x}", resp); + + let tok = send(tok, sel_req_s, u2:1); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, rd_req_s, ReadReq { addr: Addr:0, mask: !Mask:0 }); + let (tok, resp) = recv(tok, rd_resp_r); + trace_fmt!("Value read from the second RAM: {:#x}", resp); + + let tok = send(tok, sel_req_s, u2:2); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, rd_req_s, ReadReq { addr: Addr:0, mask: !Mask:0 }); + let (tok, resp) = recv(tok, rd_resp_r); + trace_fmt!("Value read from the third RAM: {:#x}", resp); + + let tok = send(tok, terminator, true); + } +} From 9e76223b4668d71c185dcacca1463c21a0856690 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 12 Dec 2024 17:16:45 +0100 Subject: [PATCH 43/85] Add skeleton of SequenceDecoder Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 57 + xls/modules/zstd/fse_dec.x | 3 +- xls/modules/zstd/sequence_dec.x | 1945 +++++++++++++++++++++++++++++++ 3 files changed, 2004 insertions(+), 1 deletion(-) create mode 100644 xls/modules/zstd/sequence_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 67027a48ac..bf69578959 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1896,6 +1896,63 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "sequence_dec_dslx", + srcs = [ + "sequence_dec.x" + ], + deps = [ + ":sequence_conf_dec_dslx", + ":fse_lookup_dec_dslx", + ":ram_demux3_dslx", + ":common_dslx", + ":fse_dec_dslx", + ":ram_mux_dslx", + ":fse_table_creator_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd:refilling_shift_buffer_dslx", + "//xls/modules/shift_buffer:shift_buffer_dslx", + ], +) + +xls_dslx_test( + name = "sequence_dec_dslx_test", + library = ":sequence_dec_dslx", +) + +xls_dslx_verilog( + name = "fse_lookup_ctrl_verilog", + codegen_args = { + "module_name": "FseLookupCtrl", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "6", + "reset": "rst", + "use_system_verilog": "false", + "multi_proc": "true", + }, + opt_ir_args = { + "top": "__sequence_dec__FseLookupCtrlInst__FseLookupCtrl_0__32_next" + }, + dslx_top = "FseLookupCtrlInst", + library = ":sequence_dec_dslx", + verilog_file = "fse_lookup_ctrl.v", +) + +xls_benchmark_ir( + name = "fse_lookup_ctrl_opt_ir_benchmark", + src = ":fse_lookup_ctrl_verilog.opt.ir", + benchmark_ir_args = { + "delay_model": "asap7", + "pipeline_stages": "6", + "inline_procs": "false", + "multi_proc": "true", + }, + tags = ["manual"], +) + xls_dslx_library( name = "literals_dispatcher_dslx", srcs = [ diff --git a/xls/modules/zstd/fse_dec.x b/xls/modules/zstd/fse_dec.x index 01a1416862..143cd45b7f 100644 --- a/xls/modules/zstd/fse_dec.x +++ b/xls/modules/zstd/fse_dec.x @@ -606,7 +606,8 @@ pub proc FseDecoder< ..state } } else { - fail!("too_many_literals", zero!()) + trace_fmt!("Fails state: {:#x}", state); + fail!("too_many_literals", state) } } else { FseDecoderState { diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x new file mode 100644 index 0000000000..6f1823df49 --- /dev/null +++ b/xls/modules/zstd/sequence_dec.x @@ -0,0 +1,1945 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; + +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.sequence_conf_dec; +import xls.modules.zstd.fse_lookup_dec; +import xls.modules.zstd.ram_demux3; +import xls.modules.zstd.ram_demux; +import xls.modules.zstd.ram_mux; +import xls.modules.zstd.refilling_shift_buffer; +import xls.modules.zstd.fse_dec; +import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.fse_table_creator; + + +type SequenceExecutorPacket = common::SequenceExecutorPacket; +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; + +type BlockSyncData = common::BlockSyncData; +type CommandConstructorData = common::CommandConstructorData; + +enum SequenceDecoderStatus: u3 { + OK = 0, + ERROR = 1, +} + +pub struct SequenceDecoderReq { + start_addr: uN[ADDR_W], + end_addr: uN[ADDR_W], + sync: BlockSyncData, + literals_count: u20, +} + +pub struct SequenceDecoderResp { + status: SequenceDecoderStatus, +} + +enum SequenceDecoderFSM: u3 { + IDLE = 0, + DECODE_SEQUENCE_HEADER = 1, + PREPARE_LL_TABLE = 2, + PREPARE_OF_TABLE = 3, + PREPARE_ML_TABLE = 4, + + ERROR = 7, +} + +struct SequenceDecoderState { + fsm: SequenceDecoderFSM, + req: SequenceDecoderReq, + conf_resp: sequence_conf_dec::SequenceConfDecoderResp, +} + +struct FseLookupCtrlReq { + ll: bool, + ml: bool, + of: bool, + addr: uN[AXI_ADDR_W], +} + +type AccuracyLog = common::FseAccuracyLog; +struct FseLookupCtrlResp { + ll_accuracy_log: AccuracyLog, + ml_accuracy_log: AccuracyLog, + of_accuracy_log: AccuracyLog, +} + +struct FseLookupCtrlState { + decode: bool[3], + decode_valid: bool, + addr: uN[AXI_ADDR_W], + resp: FseLookupCtrlResp, + cnt: u2, +} + +pub proc FseLookupCtrl { + type Req = FseLookupCtrlReq; + type Resp = FseLookupCtrlResp; + type State = FseLookupCtrlState; + + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; + + req_r: chan in; + resp_s: chan out; + + fld_req_s: chan out; + fld_resp_r: chan in; + + fse_demux_req_s: chan out; + fse_demux_resp_r: chan<()> in; + + init { zero!() } + + config( + req_r: chan in, + resp_s: chan out, + + fld_req_s: chan out, + fld_resp_r: chan in, + + fse_demux_req_s: chan out, + fse_demux_resp_r: chan<()> in, + ) { + ( + req_r, resp_s, + fld_req_s, fld_resp_r, + fse_demux_req_s, fse_demux_resp_r, + ) + } + + next(state: State) { + let tok0 = join(); + + if !state.decode_valid { + let (tok1_0, req) = recv(tok0, req_r); + State { + decode: bool[3]:[req.ll, req.of, req.ml], + decode_valid: true, + cnt: u2:0, + addr: req.addr, + ..zero!() + } + } else { + let do_set = state.decode[state.cnt]; + match(state.cnt) { + u2:0 => trace_fmt!("Handling LL"), + u2:1 => trace_fmt!("Handling OF"), + u2:2 => trace_fmt!("Handling ML"), + _ => trace_fmt!("Impossible case"), + }; + + // trace_fmt!("Sending request to demux {:#x}", state.cnt); + let tok1 = send_if(tok0, fse_demux_req_s, do_set, state.cnt); + if do_set { + trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Sent fse_demux req {:#x}", state.cnt); + } else {}; + + let (tok2, demux_resp) = recv_if(tok1, fse_demux_resp_r, do_set, ()); + if do_set { + trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Received demux resp {:#x}", demux_resp); + } else {}; + // trace_fmt!("Received response from demux"); + + let fld_req = FseLookupDecoderReq { addr: state.addr }; + let tok3 = send_if(tok2, fld_req_s, do_set, fld_req); + if do_set { + trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Sent FseLookupDecoder req {:#x}", fld_req); + } else {}; + + // FIXME: Extract RefillingShiftBuffer from the FseLookupDecoder + // to support decoding multiple FSE Tables + let (tok4, fld_resp) = recv_if(tok3, fld_resp_r, do_set, zero!()); + if do_set { + trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Received FseLookupDecoder resp {:#x}", fld_resp); + } else {}; + + let resp = match(state.cnt) { + u2:0 => FseLookupCtrlResp { ll_accuracy_log: fld_resp.accuracy_log, ..state.resp}, + u2:1 => FseLookupCtrlResp { of_accuracy_log: fld_resp.accuracy_log, ..state.resp}, + u2:2 => FseLookupCtrlResp { ml_accuracy_log: fld_resp.accuracy_log, ..state.resp}, + _ => fail!("impossible_cnt", zero!()), + }; + + // trace_fmt!("Received response from from FseLookupDecoder {:#x}", fld_resp); + + if state.cnt >= u2:2 { + let tok5 = send(tok4, resp_s, resp); + zero!() + } else { + State { cnt: state.cnt + u2:1, resp, ..state} + } + } + } +} + +const INST_AXI_ADDR_W = u32:32; + +pub proc FseLookupCtrlInst { + type Req = FseLookupCtrlReq; + type Resp = FseLookupCtrlResp; + + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; + + init { } + + config( + req_r: chan in, + resp_s: chan out, + + fld_req_s: chan out, + fld_resp_r: chan in, + + demux_req_s: chan out, + demux_resp_r: chan<()> in, + ) { + spawn FseLookupCtrl( + req_r, resp_s, + fld_req_s, fld_resp_r, + demux_req_s, demux_resp_r, + ); + } + + next(state: ()) {} +} + +const TEST_FLC_AXI_ADDR_W = u32:32; + +//#[test_proc] +//proc FseLookupCtrlTest { +// +// type Req = FseLookupCtrlReq; +// type Resp = FseLookupCtrlResp; +// +// type Addr = uN[TEST_FLC_AXI_ADDR_W]; +// +// type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; +// type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; +// type FseLookupDecoderStatus = fse_lookup_dec::FseLookupDecoderStatus; +// +// terminator: chan out; +// +// req_s: chan out; +// resp_r: chan in; +// fld_req_r: chan in; +// fld_resp_s: chan out; +// demux_req_r: chan in; +// demux_resp_s: chan<()> out; +// +// init {} +// +// config( +// terminator: chan out, +// ) { +// let (req_s, req_r) = chan("req"); +// let (resp_s, resp_r) = chan("resp"); +// let (fld_req_s, fld_req_r) = chan("fld_req"); +// let (fld_resp_s, fld_resp_r) = chan("fld_resp"); +// let (demux_req_s, demux_req_r) = chan("demux_req"); +// let (demux_resp_s, demux_resp_r) = chan<()>("demux_resp"); +// +// spawn FseLookupCtrl( +// req_r, resp_s, +// fld_req_s, fld_resp_r, +// demux_req_s, demux_resp_r, +// ); +// +// ( +// terminator, +// req_s, resp_r, +// fld_req_r, fld_resp_s, +// demux_req_r, demux_resp_s, +// ) +// } +// +// next(state: ()) { +// +// // Decode all the tables +// // --------------------- +// +// // Start +// let tok = join(); +// let tok = send(tok, req_s, Req { ll: true, of: true, ml: true, addr: Addr:0 }); +// +// // Select LL ( u2:0 ) +// let (tok, demux_req) = recv(tok, demux_req_r); +// assert_eq(demux_req, u2:0); +// +// let tok = send(tok, demux_resp_s, ()); +// let (tok, fld_req) = recv(tok, fld_req_r); +// +// assert_eq(fld_req, zero!()); +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// // Select OF ( u2:1 ) +// let (tok, demux_req) = recv(tok, demux_req_r); +// assert_eq(demux_req, u2:1); +// +// let tok = send(tok, demux_resp_s, ()); +// let (tok, fld_req) = recv(tok, fld_req_r); +// +// assert_eq(fld_req, zero!()); +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// // Select ML ( u2:2 ) +// let (tok, demux_req) = recv(tok, demux_req_r); +// assert_eq(demux_req, u2:2); +// +// let tok = send(tok, demux_resp_s, ()); +// let (tok, _fld_req) = recv(tok, fld_req_r); +// +// assert_eq(fld_req, zero!()); +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// // Stop +// let (tok, resp) = recv(tok, resp_r); +// assert_eq(resp, FseLookupCtrlResp {}); +// +// // Decode only LL and ML +// // --------------------- +// +// // Start +// let tok = join(); +// let tok = send(tok, req_s, Req { ll: true, of: false, ml: true, addr: Addr:0 }); +// +// // Select LL ( u2:0 ) +// let (tok, demux_req) = recv(tok, demux_req_r); +// assert_eq(demux_req, u2:0); +// +// let tok = send(tok, demux_resp_s, ()); +// let (tok, fld_req) = recv(tok, fld_req_r); +// +// assert_eq(fld_req, zero!()); +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// // Select ML ( u2:2 ) +// let (tok, demux_req) = recv(tok, demux_req_r); +// assert_eq(demux_req, u2:2); +// +// let tok = send(tok, demux_resp_s, ()); +// let (tok, _fld_req) = recv(tok, fld_req_r); +// +// assert_eq(fld_req, zero!()); +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// // Stop +// let (tok, resp) = recv(tok, resp_r); +// assert_eq(resp, FseLookupCtrlResp {}); +// +// +// // Decode only OF +// // --------------------- +// +// // Start +// let tok = join(); +// let tok = send(tok, req_s, Req { ll: false, of: true, ml: false, addr: Addr:0 }); +// +// // Select OF ( u2:1 ) +// let (tok, demux_req) = recv(tok, demux_req_r); +// assert_eq(demux_req, u2:1); +// +// let tok = send(tok, demux_resp_s, ()); +// let (tok, fld_req) = recv(tok, fld_req_r); +// +// assert_eq(fld_req, zero!()); +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// // Stop +// let (tok, resp) = recv(tok, resp_r); +// assert_eq(resp, FseLookupCtrlResp {}); +// +// let tok = send(tok, terminator, true); +// } +//} + +pub proc SequenceDecoderCtrl< + AXI_ADDR_W: u32, AXI_DATA_W: u32, + REFILLING_SB_DATA_W: u32 = {AXI_DATA_W}, + REFILLING_SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, +> { + type Req = SequenceDecoderReq; + type Resp = SequenceDecoderResp; + type State = SequenceDecoderState; + type FSM = SequenceDecoderFSM; + type Status = SequenceDecoderStatus; + + type Addr = uN[AXI_ADDR_W]; + + type CompressionMode = common::CompressionMode; + type SequenceConfDecoderStatus = sequence_conf_dec::SequenceConfDecoderStatus; + + type SequenceConfDecoderReq = sequence_conf_dec::SequenceConfDecoderReq; + type SequenceConfDecoderResp = sequence_conf_dec::SequenceConfDecoderResp; + + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; + + type RefillingShiftBufferStart = refilling_shift_buffer::RefillStart; + type RefillingShiftBufferError = refilling_shift_buffer::RefillingShiftBufferInput; + type RefillingShiftBufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type RefillingShiftBufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type FseDecoderCtrl = fse_dec::FseDecoderCtrl; + type FseDecoderFinish = fse_dec::FseDecoderFinish; + + sd_req_r: chan in; + sd_resp_s: chan out; + + scd_req_s: chan out; + scd_resp_r: chan in; + + flc_req_s: chan out; + flc_resp_r: chan in; + + ll_demux_req_s: chan out; + ll_demux_resp_r: chan<()> in; + + of_demux_req_s: chan out; + of_demux_resp_r: chan<()> in; + + ml_demux_req_s: chan out; + ml_demux_resp_r: chan<()> in; + + fd_rsb_start_req_s: chan out; + fd_rsb_stop_flush_req_s: chan<()> out; + fd_rsb_flushing_done_r: chan<()> in; + + fd_ctrl_s: chan out; + fd_finish_r: chan in; + + init { } + + config( + sd_req_r: chan in, + sd_resp_s: chan out, + + scd_req_s: chan out, + scd_resp_r: chan in, + + fld_req_s: chan out, + fld_resp_r: chan in, + + fld_demux_req_s: chan out, + fld_demux_resp_r: chan<()> in, + + ll_demux_req_s: chan out, + ll_demux_resp_r: chan<()> in, + + of_demux_req_s: chan out, + of_demux_resp_r: chan<()> in, + + ml_demux_req_s: chan out, + ml_demux_resp_r: chan<()> in, + + fd_rsb_start_req_s: chan out, + fd_rsb_stop_flush_req_s: chan<()> out, + fd_rsb_flushing_done_r: chan<()> in, + + fd_ctrl_s: chan out, + fd_finish_r: chan in, + ) { + const CHANNEL_DEPTH = u32:1; + + let (flc_req_s, flc_req_r) = chan("flc_req"); + let (flc_resp_s, flc_resp_r) = chan("flc_resp"); + + spawn FseLookupCtrl( + flc_req_r, flc_resp_s, + fld_req_s, fld_resp_r, + fld_demux_req_s, fld_demux_resp_r, + ); + + ( + sd_req_r, sd_resp_s, + scd_req_s, scd_resp_r, + flc_req_s, flc_resp_r, + ll_demux_req_s, ll_demux_resp_r, + of_demux_req_s, of_demux_resp_r, + ml_demux_req_s, ml_demux_resp_r, + fd_rsb_start_req_s, fd_rsb_stop_flush_req_s, fd_rsb_flushing_done_r, + fd_ctrl_s, fd_finish_r, + ) + } + + next(state: ()) { + + // Receive Sequence Decoder request + let (tok_req_sd, req) = recv(join(), sd_req_r); + trace_fmt!("[SequenceDecoderCtrl]: Received Sequence Decoder request: {:#x}", req); + + // Request decoding Sequence Header + let scd_req = SequenceConfDecoderReq { addr: req.start_addr }; + let tok_send_scd = send(tok_req_sd, scd_req_s, scd_req); + trace_fmt!("[SequenceDecoderCtrl]: Sent Sequence Decoder request: {:#x}", scd_req); + + // Receive decoded Seqence Header + let (tok_recv_scd, conf_resp) = recv(tok_send_scd, scd_resp_r); + trace_fmt!("[SequenceDecoderCtrl]: Received decoded Sequence header: {:#x}", conf_resp); + + // Request decoding lookups + let flc_req = FseLookupCtrlReq { + addr: req.start_addr + conf_resp.length as Addr, + ll: (conf_resp.header.literals_mode == CompressionMode::COMPRESSED), + ml: (conf_resp.header.match_mode == CompressionMode::COMPRESSED), + of: (conf_resp.header.offset_mode == CompressionMode::COMPRESSED), + }; + + let zero_sequences = (conf_resp.header.sequence_count == u17:0); + let tok_send_ctrl = send_if(tok_recv_scd, flc_req_s, !zero_sequences, flc_req); + if !zero_sequences { + trace_fmt!("[SequenceDecoderCtrl]: Sent FseLookupCtrl request: {:#x}", flc_req); + } else {}; + + // Receive response about deoded lookups + let (tok_recv_ctrl, flc_resp) = recv_if(tok_send_ctrl, flc_resp_r, !zero_sequences, zero!()); + + // Set proper LL lookup through demux + let ll_demux_sel = (conf_resp.header.literals_mode != CompressionMode::PREDEFINED); + let tok_ll_demux = send_if(tok_recv_scd, ll_demux_req_s, !zero_sequences, ll_demux_sel); + // Receive response from LL lookup demux + let (tok_ll_demux, _) = recv_if(tok_ll_demux, ll_demux_resp_r, !zero_sequences, ()); + + // Set proper ML lookup through demux + let ml_demux_sel = (conf_resp.header.match_mode != CompressionMode::PREDEFINED); + let tok_ml_demux = send_if(tok_recv_scd, ml_demux_req_s, !zero_sequences, ml_demux_sel); + // Receive response from ML lookup demux + let (tok_ml_demux, _) = recv_if(tok_ml_demux, ml_demux_resp_r, !zero_sequences, ()); + + // Set proper OF lookup through demux + let of_demux_sel = (conf_resp.header.match_mode != CompressionMode::PREDEFINED); + let tok_of_demux = send_if(tok_recv_scd, of_demux_req_s, !zero_sequences, of_demux_sel); + // Receive response from OF lookup demux + let (tok_of_demux, _) = recv_if(tok_of_demux, of_demux_resp_r, !zero_sequences, ()); + + let tok_demux = join(tok_ll_demux, tok_ml_demux, tok_of_demux); + + let fd_rsb_start_req = RefillingShiftBufferStart { start_addr: req.end_addr }; + let tok_rsb_start = send_if(tok_demux, fd_rsb_start_req_s, !zero_sequences, fd_rsb_start_req); + if !zero_sequences { + trace_fmt!("[SequenceDecoderCtrl]: Sent RefillingShiftBufferStart request: {:#x}", fd_rsb_start_req); + } else {}; + + let fd_ctrl = FseDecoderCtrl { + sync: req.sync, + sequences_count: conf_resp.header.sequence_count as u24, + literals_count: req.literals_count, + ll_acc_log: if (conf_resp.header.literals_mode == CompressionMode::PREDEFINED) { u7:6 } else { flc_resp.ll_accuracy_log as u7 }, + of_acc_log: if (conf_resp.header.offset_mode == CompressionMode::PREDEFINED) { u7:5 } else { flc_resp.of_accuracy_log as u7 }, + ml_acc_log: if (conf_resp.header.match_mode == CompressionMode::PREDEFINED) { u7:6 } else { flc_resp.ml_accuracy_log as u7 }, + }; + + let tok_fse_dec = send(tok_demux, fd_ctrl_s, fd_ctrl); + let (tok_fse_dec, _) = recv(tok_fse_dec, fd_finish_r); + trace_fmt!("[SequenceDecoderCtrl]: Fse finished!"); + + let tok_rsb_flush = send_if(tok_fse_dec, fd_rsb_stop_flush_req_s, !zero_sequences, ()); + trace_fmt!("[SequenceDecoderCtrl]: Send flush request"); + let (tok_rsb_flush_done, _) = recv_if(tok_rsb_flush, fd_rsb_flushing_done_r, !zero_sequences, ()); + trace_fmt!("[SequenceDecoderCtrl]: Flush done"); + + let resp = SequenceDecoderResp { status: Status::OK }; + send(tok_rsb_flush_done, sd_resp_s, resp); + } +} + +const SDC_TEST_AXI_ADDR_W = u32:32; +const SDC_TEST_AXI_DATA_W = u32:64; +const SDC_TEST_REFILLING_SB_DATA_W = {SDC_TEST_AXI_DATA_W}; +const SDC_TEST_REFILLING_SB_LENGTH_W = refilling_shift_buffer::length_width(SDC_TEST_AXI_DATA_W); + +//#[test_proc] +//proc SequenceDecoderCtrlTest { +// +// type Req = SequenceDecoderReq; +// type Resp = SequenceDecoderResp; +// type Status = SequenceDecoderStatus; +// +// type CompressionMode = common::CompressionMode; +// type Addr = uN[SDC_TEST_AXI_ADDR_W]; +// +// type SequenceConf = common::SequenceConf; +// type SequenceConfDecoderReq = sequence_conf_dec::SequenceConfDecoderReq; +// type SequenceConfDecoderResp = sequence_conf_dec::SequenceConfDecoderResp; +// type SequenceConfDecoderStatus = sequence_conf_dec::SequenceConfDecoderStatus; +// +// type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; +// type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; +// type FseLookupDecoderStatus = fse_lookup_dec::FseLookupDecoderStatus; +// +// type RefillingShiftBufferStart = refilling_shift_buffer::RefillStart; +// type RefillingShiftBufferError = refilling_shift_buffer::RefillingShiftBufferInput; +// type RefillingShiftBufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; +// type RefillingShiftBufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; +// +// type FseDecoderCtrl = fse_dec::FseDecoderCtrl; +// type FseDecoderFinish = fse_dec::FseDecoderFinish; +// +// terminator: chan out; +// +// sd_req_s: chan out; +// sd_resp_r: chan in; +// +// scd_req_r: chan in; +// scd_resp_s: chan out; +// +// fld_req_r: chan in; +// fld_resp_s: chan out; +// +// fse_demux_req_r: chan in; +// fse_demux_resp_s: chan<()> out; +// +// ll_demux_req_r: chan in; +// ll_demux_resp_s: chan<()> out; +// +// of_demux_req_r: chan in; +// of_demux_resp_s: chan<()> out; +// +// ml_demux_req_r: chan in; +// ml_demux_resp_s: chan<()> out; +// +// fd_rsb_start_req_r: chan in; +// fd_rsb_stop_flush_req_r: chan<()> in; +// fd_rsb_flushing_done_s: chan<()> out; +// +// fd_ctrl_r: chan in; +// fd_finish_s: chan out; +// +// init { } +// +// config(terminator: chan out) { +// let (sd_req_s, sd_req_r) = chan("sd_req"); +// let (sd_resp_s, sd_resp_r) = chan("sd_resp"); +// +// let (scd_req_s, scd_req_r) = chan("scd_req"); +// let (scd_resp_s, scd_resp_r) = chan("scd_resp"); +// +// let (fld_req_s, fld_req_r) = chan("fld_req"); +// let (fld_resp_s, fld_resp_r) = chan("fld_resp"); +// +// let (fse_demux_req_s, fse_demux_req_r) = chan("fse_demux_req"); +// let (fse_demux_resp_s, fse_demux_resp_r) = chan<()>("fse_demux_resp"); +// +// let (ll_demux_req_s, ll_demux_req_r) = chan("ll_demux_req"); +// let (ll_demux_resp_s, ll_demux_resp_r) = chan<()>("ll_demux_resp"); +// +// let (of_demux_req_s, of_demux_req_r) = chan("of_demux_req"); +// let (of_demux_resp_s, of_demux_resp_r) = chan<()>("of_demux_resp"); +// +// let (ml_demux_req_s, ml_demux_req_r) = chan("ml_demux_req"); +// let (ml_demux_resp_s, ml_demux_resp_r) = chan<()>("ml_demux_resp"); +// +// let (fd_rsb_start_req_s, fd_rsb_start_req_r) = chan("fd_rsb_start_req"); +// let (fd_rsb_stop_flush_req_s, fd_rsb_stop_flush_req_r) = chan<()>("fd_rsb_stop_flush_req"); +// let (fd_rsb_flushing_done_s, fd_rsb_flushing_done_r) = chan<()>("fd_rsb_flushing_done"); +// +// let (fd_ctrl_s, fd_ctrl_r) = chan("fd_ctrl"); +// let (fd_finish_s, fd_finish_r) = chan("fd_finish"); +// +// spawn SequenceDecoderCtrl< +// SDC_TEST_AXI_ADDR_W, SDC_TEST_AXI_DATA_W +// >( +// sd_req_r, sd_resp_s, +// scd_req_s, scd_resp_r, +// fld_req_s, fld_resp_r, +// fse_demux_req_s, fse_demux_resp_r, +// ll_demux_req_s, ll_demux_resp_r, +// of_demux_req_s, of_demux_resp_r, +// ml_demux_req_s, ml_demux_resp_r, +// fd_rsb_start_req_s, fd_rsb_stop_flush_req_s, fd_rsb_flushing_done_r, +// fd_ctrl_s, fd_finish_r, +// ); +// +// ( +// terminator, +// sd_req_s, sd_resp_r, +// scd_req_r, scd_resp_s, +// fld_req_r, fld_resp_s, +// fse_demux_req_r, fse_demux_resp_s, +// ll_demux_req_r, ll_demux_resp_s, +// of_demux_req_r, of_demux_resp_s, +// ml_demux_req_r, ml_demux_resp_s, +// fd_rsb_start_req_r, fd_rsb_stop_flush_req_r, fd_rsb_flushing_done_s, +// fd_ctrl_r, fd_finish_s, +// ) +// } +// +// next(state: ()) { +// let tok = join(); +// +// let tok = send(tok, sd_req_s, Req { +// start_addr: Addr:0x1000, +// end_addr: Addr:0x1012, +// }); +// +// let (tok, scd_req) = recv(tok, scd_req_r); +// assert_eq(scd_req, SequenceConfDecoderReq { addr: Addr: 0x1000 }); +// +// let scd_resp = SequenceConfDecoderResp { +// header: SequenceConf { +// sequence_count: u17:1, +// literals_mode: CompressionMode::PREDEFINED, +// offset_mode: CompressionMode::RLE, +// match_mode: CompressionMode::COMPRESSED, +// }, +// length: u3:5, +// status: SequenceConfDecoderStatus::OKAY +// }; +// let tok = send(tok, scd_resp_s, scd_resp); +// +// let (tok, demux_req) = recv(tok, fse_demux_req_r); +// assert_eq(demux_req, u2:2); +// let tok = send(tok, fse_demux_resp_s, ()); +// +// let (tok, fld_req) = recv(tok, fld_req_r); +// assert_eq(fld_req, FseLookupDecoderReq { +// addr: Addr:0x1005, +// }); +// +// let tok = send(tok, fld_resp_s, FseLookupDecoderResp {status: FseLookupDecoderStatus::OK}); +// +// let (tok, ll_demux) = recv(tok, ll_demux_req_r); +// assert_eq(ll_demux, u1:0); +// let tok = send(tok, ll_demux_resp_s, ()); +// +// let (tok, ml_demux) = recv(tok, ml_demux_req_r); +// assert_eq(ml_demux, u1:1); +// let tok = send(tok, ml_demux_resp_s, ()); +// +// let (tok, of_demux) = recv(tok, of_demux_req_r); +// assert_eq(of_demux, u1:1); +// let tok = send(tok, of_demux_resp_s, ()); +// +// let (tok, fd_ctrl) = recv(tok, fd_ctrl_r); +// assert_eq(fd_ctrl, zero!()); +// +// send(tok, terminator, true); +// } +//} + +pub proc SequenceDecoder< + AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_DEST_W: u32, AXI_ID_W: u32, + DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + + AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, + REFILLING_SB_DATA_W: u32 = {AXI_DATA_W}, + REFILLING_SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, +> { + type Req = SequenceDecoderReq; + type Resp = SequenceDecoderResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type MemReaderStatus = mem_reader::MemReaderStatus; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type SequenceConfDecoderReq = sequence_conf_dec::SequenceConfDecoderReq; + type SequenceConfDecoderResp = sequence_conf_dec::SequenceConfDecoderResp; + + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; + + type FseDecoderCtrl = fse_dec::FseDecoderCtrl; + type FseDecoderFinish = fse_dec::FseDecoderFinish; + + type RefillingShiftBufferStart = refilling_shift_buffer::RefillStart; + type RefillingShiftBufferError = refilling_shift_buffer::RefillingShiftBufferInput; + type RefillingShiftBufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type RefillingShiftBufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + init { } + + fd_ctrl_s: chan out; + fd_finish_r: chan in; + + fd_rsb_ctrl_r: chan in; + fd_rsb_data_s: chan out; + + ll_wr_req_s: chan out; + ll_wr_resp_s: chan in; + ml_wr_req_s: chan out; + ml_wr_resp_s: chan in; + of_wr_req_s: chan out; + of_wr_resp_s: chan in; + + dummy_ll_fse_rd_req_r: chan in; + dummy_ll_fse_rd_resp_s: chan out; + dummy_ll_fse_wr_req_r: chan in; + dummy_ll_fse_wr_resp_s: chan out; + dummy_ml_fse_rd_req_r: chan in; + dummy_ml_fse_rd_resp_s: chan out; + dummy_ml_fse_wr_req_r: chan in; + dummy_ml_fse_wr_resp_s: chan out; + dummy_of_fse_rd_req_r: chan in; + dummy_of_fse_rd_resp_s: chan out; + dummy_of_fse_wr_req_r: chan in; + dummy_of_fse_wr_resp_s: chan out; + + config ( + // Sequence Conf Decoder (manager) + scd_axi_ar_s: chan out, + scd_axi_r_r: chan in, + + // Fse Lookup Decoder (manager) + fld_axi_ar_s: chan out, + fld_axi_r_r: chan in, + + // FSE decoder (manager) + fd_axi_ar_s: chan out, + fd_axi_r_r: chan in, + + req_r: chan in, + resp_s: chan out, + + // Command constructor + fd_command_s: chan out, + + // RAMs + + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + ll_def_fse_rd_req_s: chan out, + ll_def_fse_rd_resp_r: chan in, + ll_def_fse_wr_req_s: chan out, + ll_def_fse_wr_resp_r: chan in, + + ll_fse_rd_req_s: chan out, + ll_fse_rd_resp_r: chan in, + ll_fse_wr_req_s: chan out, + ll_fse_wr_resp_r: chan in, + + ml_def_fse_rd_req_s: chan out, + ml_def_fse_rd_resp_r: chan in, + ml_def_fse_wr_req_s: chan out, + ml_def_fse_wr_resp_r: chan in, + + ml_fse_rd_req_s: chan out, + ml_fse_rd_resp_r: chan in, + ml_fse_wr_req_s: chan out, + ml_fse_wr_resp_r: chan in, + + of_def_fse_rd_req_s: chan out, + of_def_fse_rd_resp_r: chan in, + of_def_fse_wr_req_s: chan out, + of_def_fse_wr_resp_r: chan in, + + of_fse_rd_req_s: chan out, + of_fse_rd_resp_r: chan in, + of_fse_wr_req_s: chan out, + of_fse_wr_resp_r: chan in, + ) { + const CHANNEL_DEPTH = u32:1; + const READ_BACKWORD = true; + + // Sequence Section Decoder + + let (scd_mem_rd_req_s, scd_mem_rd_req_r) = chan("scd_mem_rd_req"); + let (scd_mem_rd_resp_s, scd_mem_rd_resp_r) = chan("scd_mem_rd_resp"); + + spawn mem_reader::MemReader( + scd_mem_rd_req_r, scd_mem_rd_resp_s, + scd_axi_ar_s, scd_axi_r_r, + ); + + let (scd_req_s, scd_req_r) = chan("scd_req"); + let (scd_resp_s, scd_resp_r) = chan("scd_resp"); + + spawn sequence_conf_dec::SequenceConfDecoder( + scd_mem_rd_req_s, scd_mem_rd_resp_r, + scd_req_r, scd_resp_s, + ); + + // FseLookupDecoder + + let (fld_mem_rd_req_s, fld_mem_rd_req_r) = chan("fld_mem_rd_req"); + let (fld_mem_rd_resp_s, fld_mem_rd_resp_r) = chan("fld_mem_rd_resp"); + + spawn mem_reader::MemReader( + fld_mem_rd_req_r, fld_mem_rd_resp_s, + fld_axi_ar_s, fld_axi_r_r, + ); + + let (fld_req_s, fld_req_r) = chan("fse_req"); + let (fld_resp_s, fld_resp_r) = chan("fse_resp"); + + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + + spawn fse_lookup_dec::FseLookupDecoder< + AXI_DATA_W, AXI_ADDR_W, + DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, + >( + fld_req_r, fld_resp_s, + fld_mem_rd_req_s, fld_mem_rd_resp_r, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + ); + + // RamDemux3 + let (fse_demux_req_s, fse_demux_req_r) = chan("fse_demux_req"); + let (fse_demux_resp_s, fse_demux_resp_r) = chan<(), CHANNEL_DEPTH>("fse_demux_resp"); + + spawn ram_demux3::RamDemux3( + fse_demux_req_r, fse_demux_resp_s, + fse_rd_req_r, fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s, + ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, of_fse_wr_req_s, of_fse_wr_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, ml_fse_wr_req_s, ml_fse_wr_resp_r, + ); + + let (ll_demux_req_s, ll_demux_req_r) = chan("ll_demux_req"); + let (ll_demux_resp_s, ll_demux_resp_r) = chan<(), CHANNEL_DEPTH>("ll_demux_resp"); + + let (ll_rd_req_s, ll_rd_req_r) = chan("ll_rd_req"); + let (ll_rd_resp_s, ll_rd_resp_r) = chan("ll_rd_resp"); + let (ll_wr_req_s, ll_wr_req_r) = chan("ll_wr_req"); + let (ll_wr_resp_s, ll_wr_resp_r) = chan("ll_wr_resp"); + + let (dummy_ll_fse_rd_req_s, dummy_ll_fse_rd_req_r) = chan("dummy_ll_fse_rd_req"); + let (dummy_ll_fse_rd_resp_s, dummy_ll_fse_rd_resp_r) = chan("dummy_ll_fse_rd_resp"); + let (dummy_ll_fse_wr_req_s, dummy_ll_fse_wr_req_r) = chan("dummy_ll_fse_wr_req"); + let (dummy_ll_fse_wr_resp_s, dummy_ll_fse_wr_resp_r) = chan("dummy_ll_fse_wr_resp"); + + spawn ram_demux::RamDemux< + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS + > ( + ll_demux_req_r, ll_demux_resp_s, + ll_rd_req_r, ll_rd_resp_s, ll_wr_req_r, ll_wr_resp_s, + ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, + dummy_ll_fse_rd_req_s, dummy_ll_fse_rd_resp_r, dummy_ll_fse_wr_req_s, dummy_ll_fse_wr_resp_r, + ); + + let (ml_demux_req_s, ml_demux_req_r) = chan("ml_demux_req"); + let (ml_demux_resp_s, ml_demux_resp_r) = chan<(), CHANNEL_DEPTH>("ml_demux_resp"); + + let (ml_rd_req_s, ml_rd_req_r) = chan("ml_rd_req"); + let (ml_rd_resp_s, ml_rd_resp_r) = chan("ml_rd_resp"); + let (ml_wr_req_s, ml_wr_req_r) = chan("ml_wr_req"); + let (ml_wr_resp_s, ml_wr_resp_r) = chan("ml_wr_resp"); + + let (dummy_ml_fse_rd_req_s, dummy_ml_fse_rd_req_r) = chan("dummy_ml_fse_rd_req"); + let (dummy_ml_fse_rd_resp_s, dummy_ml_fse_rd_resp_r) = chan("dummy_ml_fse_rd_resp"); + let (dummy_ml_fse_wr_req_s, dummy_ml_fse_wr_req_r) = chan("dummy_ml_fse_wr_req"); + let (dummy_ml_fse_wr_resp_s, dummy_ml_fse_wr_resp_r) = chan("dummy_ml_fse_wr_resp"); + + spawn ram_demux::RamDemux< + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS + > ( + ml_demux_req_r, ml_demux_resp_s, + ml_rd_req_r, ml_rd_resp_s, ml_wr_req_r, ml_wr_resp_s, + ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, + dummy_ml_fse_rd_req_s, dummy_ml_fse_rd_resp_r, dummy_ml_fse_wr_req_s, dummy_ml_fse_wr_resp_r, + ); + + let (of_demux_req_s, of_demux_req_r) = chan("of_demux_req"); + let (of_demux_resp_s, of_demux_resp_r) = chan<(), CHANNEL_DEPTH>("of_demux_resp"); + + let (of_rd_req_s, of_rd_req_r) = chan("of_rd_req"); + let (of_rd_resp_s, of_rd_resp_r) = chan("of_rd_resp"); + let (of_wr_req_s, of_wr_req_r) = chan("of_wr_req"); + let (of_wr_resp_s, of_wr_resp_r) = chan("of_wr_resp"); + + let (dummy_of_fse_rd_req_s, dummy_of_fse_rd_req_r) = chan("dummy_of_fse_rd_req"); + let (dummy_of_fse_rd_resp_s, dummy_of_fse_rd_resp_r) = chan("dummy_of_fse_rd_resp"); + let (dummy_of_fse_wr_req_s, dummy_of_fse_wr_req_r) = chan("dummy_of_fse_wr_req"); + let (dummy_of_fse_wr_resp_s, dummy_of_fse_wr_resp_r) = chan("dummy_of_fse_wr_resp"); + + spawn ram_demux::RamDemux< + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS + > ( + of_demux_req_r, of_demux_resp_s, + of_rd_req_r, of_rd_resp_s, of_wr_req_r, of_wr_resp_s, + of_def_fse_rd_req_s, of_def_fse_rd_resp_r, of_def_fse_wr_req_s, of_def_fse_wr_resp_r, + dummy_of_fse_rd_req_s, dummy_of_fse_rd_resp_r, dummy_of_fse_wr_req_s, dummy_of_fse_wr_resp_r, + ); + + let (fd_mem_rd_req_s, fd_mem_rd_req_r) = chan("fd_mem_rd_req"); + let (fd_mem_rd_resp_s, fd_mem_rd_resp_r) = chan("fd_mem_rd_resp"); + + spawn mem_reader::MemReader( + fd_mem_rd_req_r, fd_mem_rd_resp_s, + fd_axi_ar_s, fd_axi_r_r, + ); + + let (fd_rsb_start_req_s, fd_rsb_start_req_r) = chan("fd_rsb_start_req"); + let (fd_rsb_stop_flush_req_s, fd_rsb_stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_stop_flush_req"); + let (fd_rsb_ctrl_s, fd_rsb_ctrl_r) = chan("fd_rsb_ctrl"); + let (fd_rsb_data_s, fd_rsb_data_r) = chan("fd_rsb_data"); + let (fd_rsb_flushing_done_s, fd_rsb_flushing_done_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_flushing_done"); + + spawn refilling_shift_buffer::RefillingShiftBuffer ( + fd_mem_rd_req_s, fd_mem_rd_resp_r, + fd_rsb_start_req_r, fd_rsb_stop_flush_req_r, + fd_rsb_ctrl_r, fd_rsb_data_s, + fd_rsb_flushing_done_s, + ); + + let (fd_ctrl_s, fd_ctrl_r) = chan("fd_ctrl"); + let (fd_finish_s, fd_finish_r) = chan("fd_finish"); + + spawn fse_dec::FseDecoder< + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, AXI_DATA_W, + >( + fd_ctrl_r, fd_finish_s, + fd_rsb_ctrl_s, fd_rsb_data_r, + fd_command_s, + ll_rd_req_s, ll_rd_resp_r, + ml_rd_req_s, ml_rd_resp_r, + of_rd_req_s, of_rd_resp_r, + ); + + spawn SequenceDecoderCtrl( + req_r, resp_s, + scd_req_s, scd_resp_r, + fld_req_s, fld_resp_r, + fse_demux_req_s, fse_demux_resp_r, + ll_demux_req_s, ll_demux_resp_r, + of_demux_req_s, of_demux_resp_r, + ml_demux_req_s, ml_demux_resp_r, + fd_rsb_start_req_s, fd_rsb_stop_flush_req_s, fd_rsb_flushing_done_r, + fd_ctrl_s, fd_finish_r, + ); + + ( + fd_ctrl_s, fd_finish_r, + fd_rsb_ctrl_r, fd_rsb_data_s, + ll_wr_req_s, ll_wr_resp_r, + ml_wr_req_s, ml_wr_resp_r, + of_wr_req_s, of_wr_resp_r, + dummy_ll_fse_rd_req_r, + dummy_ll_fse_rd_resp_s, + dummy_ll_fse_wr_req_r, + dummy_ll_fse_wr_resp_s, + dummy_ml_fse_rd_req_r, + dummy_ml_fse_rd_resp_s, + dummy_ml_fse_wr_req_r, + dummy_ml_fse_wr_resp_s, + dummy_of_fse_rd_req_r, + dummy_of_fse_rd_resp_s, + dummy_of_fse_wr_req_r, + dummy_of_fse_wr_resp_s, + + ) + } + + next(state: ()) { + send_if(join(), ll_wr_req_s, false, zero!()); + recv_if(join(), ll_wr_resp_s, false, zero!()); + send_if(join(), ml_wr_req_s, false, zero!()); + recv_if(join(), ml_wr_resp_s, false, zero!()); + send_if(join(), of_wr_req_s, false, zero!()); + recv_if(join(), of_wr_resp_s, false, zero!()); + + recv_if(join(), dummy_ll_fse_rd_req_r, false, zero!()); + send_if(join(), dummy_ll_fse_rd_resp_s, false, zero!()); + recv_if(join(), dummy_ll_fse_wr_req_r, false, zero!()); + send_if(join(), dummy_ll_fse_wr_resp_s, false, zero!()); + recv_if(join(), dummy_ml_fse_rd_req_r, false, zero!()); + send_if(join(), dummy_ml_fse_rd_resp_s, false, zero!()); + recv_if(join(), dummy_ml_fse_wr_req_r, false, zero!()); + send_if(join(), dummy_ml_fse_wr_resp_s, false, zero!()); + recv_if(join(), dummy_of_fse_rd_req_r, false, zero!()); + send_if(join(), dummy_of_fse_rd_resp_s, false, zero!()); + recv_if(join(), dummy_of_fse_wr_req_r, false, zero!()); + send_if(join(), dummy_of_fse_wr_resp_s, false, zero!()); + } +} + +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_DEST_W = u32:8; +const TEST_AXI_ID_W = u32:8; + +const TEST_INPUT_RAM_DATA_W = TEST_AXI_DATA_W; +const TEST_INPUT_RAM_SIZE = u32:1024; +const TEST_INPUT_RAM_ADDR_W = TEST_AXI_ADDR_W; +const TEST_INPUT_RAM_WORD_PARTITION_SIZE = TEST_INPUT_RAM_DATA_W / u32:8; +const TEST_INPUT_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_INPUT_RAM_WORD_PARTITION_SIZE, TEST_INPUT_RAM_DATA_W); +const TEST_INPUT_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_INPUT_RAM_INITIALIZED = true; +const TEST_INPUT_RAM_ASSERT_VALID_READ = true; + +const TEST_DPD_RAM_DATA_W = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_W = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_W; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); + +const TEST_FSE_RAM_DATA_W = u32:32; +const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); +const TEST_FSE_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; + +const TEST_TMP_RAM_DATA_W = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_W = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); + +const TEST_RAM_DATA = u64[40]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0x0016A400E6C3000A, // 0x100 + u64:0x225100295B0012D6, // 0x138 + u64:0x1E00123CB813DB80, // 0x140 + u64:0x1026064002C4800A, // 0x148 + u64:0x0, ... +]; + +const EXPECTED_OUTPUT = SequenceExecutorPacket[16]:[ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x001c, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x000a, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0389, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x013c, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0479, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0009, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x001d, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x024a, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x032b, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x02b5, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0002, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x03a9, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x06c3, + last: true, + }, +]; + +type Base = u16; +type Symbol = u8; +type NumOfBits = u8; + +type FseTableRecord = common::FseTableRecord; + +pub const DEFAULT_LL_TABLE = FseTableRecord[64]: [ + FseTableRecord { symbol: Symbol:0, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:0, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:3, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:4, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:6, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:7, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:9, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:10, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:12, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:14, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:16, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:18, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:19, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:21, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:22, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:24, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:25, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:26, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:27, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:29, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:31, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:0, num_of_bits: NumOfBits:4, base: Base:32 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:2, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:4, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:5, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:7, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:8, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:10, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:11, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:13, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:16, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:17, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:19, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:20, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:22, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:23, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:25, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:25, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:26, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:28, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:30, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:0, num_of_bits: NumOfBits:4, base: Base:48 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:2, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:3, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:5, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:6, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:8, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:9, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:11, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:12, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:15, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:17, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:18, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:20, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:21, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:23, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:24, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:35, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:34, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:33, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:32, num_of_bits: NumOfBits:6, base: Base:0 }, +]; + +pub const DEFAULT_ML_TABLE = FseTableRecord[64]: [ + FseTableRecord { symbol: Symbol:0, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:2, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:3, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:5, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:6, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:8, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:10, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:13, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:16, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:19, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:22, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:25, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:28, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:31, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:33, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:35, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:37, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:39, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:41, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:43, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:45, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:2, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:3, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:4, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:6, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:7, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:9, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:12, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:15, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:18, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:21, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:24, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:27, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:30, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:32, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:34, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:36, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:38, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:40, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:42, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:44, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:4, base: Base:32 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:4, base: Base:48 }, + FseTableRecord { symbol: Symbol:2, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:4, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:5, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:7, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:8, num_of_bits: NumOfBits:5, base: Base:32 }, + FseTableRecord { symbol: Symbol:11, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:14, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:17, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:20, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:23, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:26, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:29, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:52, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:51, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:50, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:49, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:48, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:47, num_of_bits: NumOfBits:6, base: Base:0 }, + FseTableRecord { symbol: Symbol:46, num_of_bits: NumOfBits:6, base: Base:0 }, +]; + +pub const DEFAULT_OF_TABLE = FseTableRecord[32]:[ + FseTableRecord { symbol: Symbol:0, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:6, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:9, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:15, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:21, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:3, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:7, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:12, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:18, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:23, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:5, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:8, num_of_bits: NumOfBits:4, base: Base:0 }, + FseTableRecord { symbol: Symbol:14, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:20, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:2, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:7, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:11, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:17, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:22, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:4, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:8, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:13, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:19, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:1, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:6, num_of_bits: NumOfBits:4, base: Base:16 }, + FseTableRecord { symbol: Symbol:10, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:16, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:28, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:27, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:26, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:25, num_of_bits: NumOfBits:5, base: Base:0 }, + FseTableRecord { symbol: Symbol:24, num_of_bits: NumOfBits:5, base: Base:0 }, +]; + +#[test_proc] +proc SequenceDecoderTest { + type Req = SequenceDecoderReq; + type Resp = SequenceDecoderResp; + + type InputAddr = uN[TEST_INPUT_RAM_ADDR_W]; + type InputData = uN[TEST_INPUT_RAM_DATA_W]; + type InputMask = uN[TEST_INPUT_RAM_NUM_PARTITIONS]; + + type InputRamRdReq = ram::ReadReq; + type InputRamRdResp = ram::ReadResp; + type InputRamWrReq = ram::WriteReq; + type InputRamWrResp = ram::WriteResp; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type FseAddr = uN[TEST_FSE_RAM_ADDR_W]; + type FseData = uN[TEST_FSE_RAM_DATA_W]; + type FseMask = uN[TEST_FSE_RAM_NUM_PARTITIONS]; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + + terminator: chan out; + + req_s: chan out; + resp_r: chan in; + + fd_command_r: chan in; + + input0_rd_req_s: chan out; + input0_rd_resp_r: chan in; + input0_wr_req_s: chan out; + input0_wr_resp_r: chan in; + + input1_rd_req_s: chan out; + input1_rd_resp_r: chan in; + input1_wr_req_s: chan out; + input1_wr_resp_r: chan in; + + input2_rd_req_s: chan out; + input2_rd_resp_r: chan in; + input2_wr_req_s: chan out; + input2_wr_resp_r: chan in; + + ll_sel_test_s: chan out; + ll_def_test_rd_req_s: chan out; + ll_def_test_rd_resp_r: chan in; + ll_def_test_wr_req_s: chan out; + ll_def_test_wr_resp_r: chan in; + + ml_sel_test_s: chan out; + ml_def_test_rd_req_s: chan out; + ml_def_test_rd_resp_r: chan in; + ml_def_test_wr_req_s: chan out; + ml_def_test_wr_resp_r: chan in; + + of_sel_test_s: chan out; + of_def_test_rd_req_s: chan out; + of_def_test_rd_resp_r: chan in; + of_def_test_wr_req_s: chan out; + of_def_test_wr_resp_r: chan in; + + init { } + + config( + terminator: chan out + ) { + // RAM for probability distribution + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + + spawn ram::RamModel< + TEST_DPD_RAM_DATA_W, + TEST_DPD_RAM_SIZE, + TEST_DPD_RAM_WORD_PARTITION_SIZE + >(dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s); + + // RAMs for temporary values when decoding probability distribution + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + + spawn ram::RamModel< + TEST_TMP_RAM_DATA_W, + TEST_TMP_RAM_SIZE, + TEST_TMP_RAM_WORD_PARTITION_SIZE + >(tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + + // RAM with default FSE lookup for Literal Lengths + + let (ll_sel_test_s, ll_sel_test_r) = chan("ll_test_sel"); + + let (ll_def_test_rd_req_s, ll_def_test_rd_req_r) = chan("ll_def_test_rd_req"); + let (ll_def_test_rd_resp_s, ll_def_test_rd_resp_r) = chan("ll_def_test_rd_resp"); + let (ll_def_test_wr_req_s, ll_def_test_wr_req_r) = chan("ll_def_test_wr_req"); + let (ll_def_test_wr_resp_s, ll_def_test_wr_resp_r) = chan("ll_def_test_wr_resp"); + + let (ll_def_fse_rd_req_s, ll_def_fse_rd_req_r) = chan("ll_def_fse_rd_req"); + let (ll_def_fse_rd_resp_s, ll_def_fse_rd_resp_r) = chan("ll_def_fse_rd_resp"); + let (ll_def_fse_wr_req_s, ll_def_fse_wr_req_r) = chan("ll_def_fse_wr_req"); + let (ll_def_fse_wr_resp_s, ll_def_fse_wr_resp_r) = chan("ll_def_fse_wr_resp"); + + let (ll_def_rd_req_s, ll_def_rd_req_r) = chan("ll_def_rd_req"); + let (ll_def_rd_resp_s, ll_def_rd_resp_r) = chan("ll_def_rd_resp"); + let (ll_def_wr_req_s, ll_def_wr_req_r) = chan("ll_def_wr_req"); + let (ll_def_wr_resp_s, ll_def_wr_resp_r) = chan("ll_def_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + ll_sel_test_r, + ll_def_test_rd_req_r, ll_def_test_rd_resp_s, ll_def_test_wr_req_r, ll_def_test_wr_resp_s, + ll_def_fse_rd_req_r, ll_def_fse_rd_resp_s, ll_def_fse_wr_req_r, ll_def_fse_wr_resp_s, + ll_def_rd_req_s, ll_def_rd_resp_r, ll_def_wr_req_s, ll_def_wr_resp_r, + ); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(ll_def_rd_req_r, ll_def_rd_resp_s, ll_def_wr_req_r, ll_def_wr_resp_s); + + // RAM for FSE lookup for Literal Lengths + let (ll_fse_rd_req_s, ll_fse_rd_req_r) = chan("ll_fse_rd_req"); + let (ll_fse_rd_resp_s, ll_fse_rd_resp_r) = chan("ll_fse_rd_resp"); + let (ll_fse_wr_req_s, ll_fse_wr_req_r) = chan("ll_fse_wr_req"); + let (ll_fse_wr_resp_s, ll_fse_wr_resp_r) = chan("ll_fse_wr_resp"); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(ll_fse_rd_req_r, ll_fse_rd_resp_s, ll_fse_wr_req_r, ll_fse_wr_resp_s); + + // RAM with default FSE lookup for Match Lengths + + let (ml_sel_test_s, ml_sel_test_r) = chan("ml_sel_test"); + + let (ml_def_test_rd_req_s, ml_def_test_rd_req_r) = chan("ml_def_test_rd_req"); + let (ml_def_test_rd_resp_s, ml_def_test_rd_resp_r) = chan("ml_def_test_rd_resp"); + let (ml_def_test_wr_req_s, ml_def_test_wr_req_r) = chan("ml_def_test_wr_req"); + let (ml_def_test_wr_resp_s, ml_def_test_wr_resp_r) = chan("ml_def_test_wr_resp"); + + let (ml_def_fse_rd_req_s, ml_def_fse_rd_req_r) = chan("ml_def_fse_rd_req"); + let (ml_def_fse_rd_resp_s, ml_def_fse_rd_resp_r) = chan("ml_def_fse_rd_resp"); + let (ml_def_fse_wr_req_s, ml_def_fse_wr_req_r) = chan("ml_def_fse_wr_req"); + let (ml_def_fse_wr_resp_s, ml_def_fse_wr_resp_r) = chan("ml_def_fse_wr_resp"); + + let (ml_def_rd_req_s, ml_def_rd_req_r) = chan("ml_def_rd_req"); + let (ml_def_rd_resp_s, ml_def_rd_resp_r) = chan("ml_def_rd_resp"); + let (ml_def_wr_req_s, ml_def_wr_req_r) = chan("ml_def_wr_req"); + let (ml_def_wr_resp_s, ml_def_wr_resp_r) = chan("ml_def_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + ml_sel_test_r, + ml_def_test_rd_req_r, ml_def_test_rd_resp_s, ml_def_test_wr_req_r, ml_def_test_wr_resp_s, + ml_def_fse_rd_req_r, ml_def_fse_rd_resp_s, ml_def_fse_wr_req_r, ml_def_fse_wr_resp_s, + ml_def_rd_req_s, ml_def_rd_resp_r, ml_def_wr_req_s, ml_def_wr_resp_r, + ); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(ml_def_rd_req_r, ml_def_rd_resp_s, ml_def_wr_req_r, ml_def_wr_resp_s); + + // RAM for FSE lookup for Match Lengths + let (ml_fse_rd_req_s, ml_fse_rd_req_r) = chan("ml_fse_rd_req"); + let (ml_fse_rd_resp_s, ml_fse_rd_resp_r) = chan("ml_fse_rd_resp"); + let (ml_fse_wr_req_s, ml_fse_wr_req_r) = chan("ml_fse_wr_req"); + let (ml_fse_wr_resp_s, ml_fse_wr_resp_r) = chan("ml_fse_wr_resp"); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(ml_fse_rd_req_r, ml_fse_rd_resp_s, ml_fse_wr_req_r, ml_fse_wr_resp_s); + + // RAM with default FSE lookup for Offsets + + let (of_sel_test_s, of_sel_test_r) = chan("of_sel_test"); + + let (of_def_test_rd_req_s, of_def_test_rd_req_r) = chan("of_def_test_rd_req"); + let (of_def_test_rd_resp_s, of_def_test_rd_resp_r) = chan("of_def_test_rd_resp"); + let (of_def_test_wr_req_s, of_def_test_wr_req_r) = chan("of_def_test_wr_req"); + let (of_def_test_wr_resp_s, of_def_test_wr_resp_r) = chan("of_def_test_wr_resp"); + + let (of_def_fse_rd_req_s, of_def_fse_rd_req_r) = chan("of_def_fse_rd_req"); + let (of_def_fse_rd_resp_s, of_def_fse_rd_resp_r) = chan("of_def_fse_rd_resp"); + let (of_def_fse_wr_req_s, of_def_fse_wr_req_r) = chan("of_def_fse_wr_req"); + let (of_def_fse_wr_resp_s, of_def_fse_wr_resp_r) = chan("of_def_fse_wr_resp"); + + let (of_def_rd_req_s, of_def_rd_req_r) = chan("of_def_rd_req"); + let (of_def_rd_resp_s, of_def_rd_resp_r) = chan("of_def_rd_resp"); + let (of_def_wr_req_s, of_def_wr_req_r) = chan("of_def_wr_req"); + let (of_def_wr_resp_s, of_def_wr_resp_r) = chan("of_def_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + of_sel_test_r, + of_def_test_rd_req_r, of_def_test_rd_resp_s, of_def_test_wr_req_r, of_def_test_wr_resp_s, + of_def_fse_rd_req_r, of_def_fse_rd_resp_s, of_def_fse_wr_req_r, of_def_fse_wr_resp_s, + of_def_rd_req_s, of_def_rd_resp_r, of_def_wr_req_s, of_def_wr_resp_r, + ); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(of_def_rd_req_r, of_def_rd_resp_s, of_def_wr_req_r, of_def_wr_resp_s); + + // RAM for FSE lookup for Offsets + let (of_fse_rd_req_s, of_fse_rd_req_r) = chan("of_fse_rd_req"); + let (of_fse_rd_resp_s, of_fse_rd_resp_r) = chan("of_fse_rd_resp"); + let (of_fse_wr_req_s, of_fse_wr_req_r) = chan("of_fse_wr_req"); + let (of_fse_wr_resp_s, of_fse_wr_resp_r) = chan("of_fse_wr_resp"); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(of_fse_rd_req_r, of_fse_rd_resp_s, of_fse_wr_req_r, of_fse_wr_resp_s); + + // Input Memory + + let (input0_rd_req_s, input0_rd_req_r) = chan("input_rd_req"); + let (input0_rd_resp_s, input0_rd_resp_r) = chan("input_rd_resp"); + let (input0_wr_req_s, input0_wr_req_r) = chan("input_wr_req"); + let (input0_wr_resp_s, input0_wr_resp_r) = chan("input_wr_resp"); + + spawn ram::RamModel< + TEST_INPUT_RAM_DATA_W, + TEST_INPUT_RAM_SIZE, + TEST_INPUT_RAM_WORD_PARTITION_SIZE, + TEST_INPUT_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_INPUT_RAM_INITIALIZED, + TEST_INPUT_RAM_ASSERT_VALID_READ, + TEST_INPUT_RAM_ADDR_W, + TEST_INPUT_RAM_NUM_PARTITIONS, + >(input0_rd_req_r, input0_rd_resp_s, input0_wr_req_r, input0_wr_resp_s); + + let (ss_axi_ar_s, ss_axi_ar_r) = chan("ss_axi_ar"); + let (ss_axi_r_s, ss_axi_r_r) = chan("ss_axi_r"); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_INPUT_RAM_SIZE + >( + ss_axi_ar_r, ss_axi_r_s, + input0_rd_req_s, input0_rd_resp_r, + ); + + let (input1_rd_req_s, input1_rd_req_r) = chan("input_rd_req"); + let (input1_rd_resp_s, input1_rd_resp_r) = chan("input_rd_resp"); + let (input1_wr_req_s, input1_wr_req_r) = chan("input_wr_req"); + let (input1_wr_resp_s, input1_wr_resp_r) = chan("input_wr_resp"); + + spawn ram::RamModel< + TEST_INPUT_RAM_DATA_W, + TEST_INPUT_RAM_SIZE, + TEST_INPUT_RAM_WORD_PARTITION_SIZE, + TEST_INPUT_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_INPUT_RAM_INITIALIZED, + TEST_INPUT_RAM_ASSERT_VALID_READ, + TEST_INPUT_RAM_ADDR_W, + TEST_INPUT_RAM_NUM_PARTITIONS, + >(input1_rd_req_r, input1_rd_resp_s, input1_wr_req_r, input1_wr_resp_s); + + let (fl_axi_ar_s, fl_axi_ar_r) = chan("fl_axi_ar"); + let (fl_axi_r_s, fl_axi_r_r) = chan("fl_axi_r"); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_INPUT_RAM_SIZE + >( + fl_axi_ar_r, fl_axi_r_s, + input1_rd_req_s, input1_rd_resp_r, + ); + + let (input2_rd_req_s, input2_rd_req_r) = chan("input_rd_req"); + let (input2_rd_resp_s, input2_rd_resp_r) = chan("input_rd_resp"); + let (input2_wr_req_s, input2_wr_req_r) = chan("input_wr_req"); + let (input2_wr_resp_s, input2_wr_resp_r) = chan("input_wr_resp"); + + spawn ram::RamModel< + TEST_INPUT_RAM_DATA_W, + TEST_INPUT_RAM_SIZE, + TEST_INPUT_RAM_WORD_PARTITION_SIZE, + TEST_INPUT_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_INPUT_RAM_INITIALIZED, + TEST_INPUT_RAM_ASSERT_VALID_READ, + TEST_INPUT_RAM_ADDR_W, + TEST_INPUT_RAM_NUM_PARTITIONS, + >(input2_rd_req_r, input2_rd_resp_s, input2_wr_req_r, input2_wr_resp_s); + + + let (fd_axi_ar_s, fd_axi_ar_r) = chan("fd_axi_ar"); + let (fd_axi_r_s, fd_axi_r_r) = chan("fd_axi_r"); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_INPUT_RAM_SIZE + >( + fd_axi_ar_r, fd_axi_r_s, + input2_rd_req_s, input2_rd_resp_r, + ); + + // Sequence Decoder + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + let (fd_command_s, fd_command_r) = chan("fd_command"); + + spawn SequenceDecoder< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, + > ( + ss_axi_ar_s, ss_axi_r_r, + fl_axi_ar_s, fl_axi_r_r, + fd_axi_ar_s, fd_axi_r_r, + + req_r, resp_s, + fd_command_s, + + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + + ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, + ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, + + ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, ml_fse_wr_req_s, ml_fse_wr_resp_r, + + of_def_fse_rd_req_s, of_def_fse_rd_resp_r, of_def_fse_wr_req_s, of_def_fse_wr_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, of_fse_wr_req_s, of_fse_wr_resp_r, + ); + + ( + terminator, + req_s, resp_r, + fd_command_r, + + input0_rd_req_s, input0_rd_resp_r, input0_wr_req_s, input0_wr_resp_r, + input1_rd_req_s, input1_rd_resp_r, input1_wr_req_s, input1_wr_resp_r, + input2_rd_req_s, input2_rd_resp_r, input2_wr_req_s, input2_wr_resp_r, + + ll_sel_test_s, + ll_def_test_rd_req_s, ll_def_test_rd_resp_r, ll_def_test_wr_req_s, ll_def_test_wr_resp_r, + + ml_sel_test_s, + ml_def_test_rd_req_s, ml_def_test_rd_resp_r, ml_def_test_wr_req_s, ml_def_test_wr_resp_r, + + of_sel_test_s, + of_def_test_rd_req_s, of_def_test_rd_resp_r, of_def_test_wr_req_s, of_def_test_wr_resp_r, + ) + } + + next(state: ()) { + let tok = join(); + + // FILL THE TEST DATA + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(TEST_RAM_DATA)) { + let req = InputRamWrReq { + addr: i as InputAddr, + data: TEST_RAM_DATA[i] as InputData, + mask: !InputMask:0, + }; + let tok = send(tok, input0_wr_req_s, req); + let (tok, _) = recv(tok, input0_wr_resp_r); + let tok = send(tok, input1_wr_req_s, req); + let (tok, _) = recv(tok, input1_wr_resp_r); + let tok = send(tok, input2_wr_req_s, req); + let (tok, _) = recv(tok, input2_wr_resp_r); + tok + }(tok); + + // FILL THE LL DEFAULT RAM + let tok = send(tok, ll_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(DEFAULT_LL_TABLE)) { + let req = FseRamWrReq { + addr: i as FseAddr, + data: fse_table_creator::fse_record_to_bits(DEFAULT_LL_TABLE[i]), + mask: !FseMask:0, + }; + let tok = send(tok, ll_def_test_wr_req_s, req); + let (tok, _) = recv(tok, ll_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, ll_sel_test_s, u1:1); + + // FILL THE OF DEFAULT RAM + let tok = send(tok, of_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(DEFAULT_OF_TABLE)) { + let req = FseRamWrReq { + addr: i as FseAddr, + data: fse_table_creator::fse_record_to_bits(DEFAULT_OF_TABLE[i]), + mask: !FseMask:0, + }; + let tok = send(tok, of_def_test_wr_req_s, req); + let (tok, _) = recv(tok, of_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, of_sel_test_s, u1:1); + + // FILL THE ML DEFAULT RAM + let tok = send(tok, ml_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(DEFAULT_ML_TABLE)) { + let req = FseRamWrReq { + addr: i as FseAddr, + data: fse_table_creator::fse_record_to_bits(DEFAULT_ML_TABLE[i]), + mask: !FseMask:0, + }; + let tok = send(tok, ml_def_test_wr_req_s, req); + let (tok, _) = recv(tok, ml_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, ml_sel_test_s, u1:1); + + // START DECODING + let tok = send(tok, req_s, Req { + sync: BlockSyncData { + id: u32:0, + last_block: false, + }, + start_addr: uN[TEST_AXI_ADDR_W]:0x100, + end_addr: uN[TEST_AXI_ADDR_W]:0x120, + literals_count: u20:24, + }); + + let tok = for ((i, output), tok): ((u32, SequenceExecutorPacket), token) in enumerate(EXPECTED_OUTPUT) { + let (tok, recv_output) = recv(tok, fd_command_r); + trace_fmt!("[{}]: Expected: {:#x}\nGot: {:#x}\n", i, output, recv_output); + assert_eq(output, recv_output.data); + tok + }(tok); + + let (tok, _) = recv(tok, resp_r); + + // START DECODING - ask for more literals - expecting additional empty output packet with + // last set + let tok = send(tok, req_s, Req { + sync: BlockSyncData { + id: u32:0, + last_block: false, + }, + start_addr: uN[TEST_AXI_ADDR_W]:0x100, + end_addr: uN[TEST_AXI_ADDR_W]:0x120, + literals_count: u20:26, + }); + + // Don't read the last output packet from the expected output array + let tok = for (i, tok): (u32, token) in u32:0..(array_size(EXPECTED_OUTPUT) - u32:1) { + let output = EXPECTED_OUTPUT[i]; + let (tok, recv_output) = recv(tok, fd_command_r); + trace_fmt!("[{}]: Expected: {:#x}\nGot: {:#x}\n", i, output, recv_output); + assert_eq(output, recv_output.data); + tok + }(tok); + + // The last packet from the expected output array is now expected to have last not set + let expected = SequenceExecutorPacket { + last: false, + ..EXPECTED_OUTPUT[array_size(EXPECTED_OUTPUT) - u32:1] + }; + let (tok, recv_output) = recv(tok, fd_command_r); + trace_fmt!("[LAST-1]: Expected: {:#x}\nGot: {:#x}\n", expected, recv_output); + assert_eq(expected, recv_output.data); + + // This is the actual last output packet + let expected = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x2, + content: u64:0x0, + last: true, + }; + let (tok, recv_output) = recv(tok, fd_command_r); + trace_fmt!("[LAST]: Expected: {:#x}\nGot: {:#x}\n", expected, recv_output); + assert_eq(expected, recv_output.data); + + let (tok, _) = recv(tok, resp_r); + + send(tok, terminator, true); + } + +} From aedd11692b265cfbd15a8f293d8e1593d7ce46fc Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 3 Dec 2024 16:12:33 +0100 Subject: [PATCH 44/85] modules/zstd: Rework literals decoding to memory-based architecture Internal-tag: [#69203] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 271 ++- xls/modules/zstd/common.x | 12 +- xls/modules/zstd/huffman_axi_reader.x | 134 +- xls/modules/zstd/huffman_code_builder.x | 8 +- xls/modules/zstd/huffman_ctrl.x | 476 ++++- xls/modules/zstd/huffman_data_preprocessor.x | 2 + xls/modules/zstd/huffman_decoder.x | 96 +- xls/modules/zstd/huffman_literals_dec.x | 1107 +++++++---- xls/modules/zstd/huffman_weights_dec.x | 1016 ++++++++++ xls/modules/zstd/literals_block_header_dec.x | 176 +- xls/modules/zstd/literals_buffer.x | 162 +- xls/modules/zstd/literals_decoder.x | 1795 +++++++++++++++--- xls/modules/zstd/literals_dispatcher.x | 243 --- xls/modules/zstd/memory/axi_ram.x | 8 +- xls/modules/zstd/raw_literals_dec.x | 279 ++- xls/modules/zstd/rle_literals_dec.x | 516 ++--- 16 files changed, 4725 insertions(+), 1576 deletions(-) create mode 100644 xls/modules/zstd/huffman_weights_dec.x delete mode 100644 xls/modules/zstd/literals_dispatcher.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index bf69578959..81826fe9a4 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1953,88 +1953,6 @@ xls_benchmark_ir( tags = ["manual"], ) -xls_dslx_library( - name = "literals_dispatcher_dslx", - srcs = [ - "literals_dispatcher.x", - ], - deps = [ - ":common_dslx", - ], -) - -xls_dslx_test( - name = "literals_dispatcher_dslx_test", - library = ":literals_dispatcher_dslx", -) - -xls_dslx_verilog( - name = "literals_dispatcher_verilog", - codegen_args = { - "module_name": "LiteralsDispatcher", - "delay_model": "asap7", - "pipeline_stages": "1", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, - dslx_top = "LiteralsDispatcher", - library = ":literals_dispatcher_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__literals_dispatcher__LiteralsDispatcher_0_next", - }, - verilog_file = "literals_dispatcher.v", -) - -xls_benchmark_ir( - name = "literals_dispatcher_opt_ir_benchmark", - src = ":literals_dispatcher_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "1", - "delay_model": "asap7", - }, -) - -xls_benchmark_verilog( - name = "literals_dispatcher_verilog_benchmark", - verilog_target = "literals_dispatcher_verilog", -) - -verilog_library( - name = "literals_dispatcher_verilog_lib", - srcs = [ - ":literals_dispatcher.v", - ], -) - -synthesize_rtl( - name = "literals_dispatcher_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - top_module = "LiteralsDispatcher", - deps = [ - ":literals_dispatcher_verilog_lib", - ], -) - -benchmark_synth( - name = "literals_dispatcher_benchmark_synth", - synth_target = ":literals_dispatcher_synth_asap7", -) - -place_and_route( - name = "literals_dispatcher_place_and_route", - clock_period = "750", - core_padding_microns = 2, - die_height_microns = 64, - die_width_microns = 64, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":literals_dispatcher_synth_asap7", - target_die_utilization_percentage = "10", -) - xls_dslx_library( name = "rle_literals_dec_dslx", srcs = [ @@ -2042,8 +1960,6 @@ xls_dslx_library( ], deps = [ ":common_dslx", - "//xls/modules/rle:rle_common_dslx", - "//xls/modules/rle:rle_dec_dslx", ], ) @@ -2062,13 +1978,14 @@ xls_dslx_verilog( "worst_case_throughput": "1", "use_system_verilog": "false", }, - dslx_top = "RleLiteralsDecoder", + dslx_top = "RleLiteralsDecoderInst", library = ":rle_literals_dec_dslx", opt_ir_args = { "inline_procs": "true", - "top": "__rle_literals_dec__RleLiteralsDecoder__BatchPacker_0_next", + "top": "__rle_literals_dec__RleLiteralsDecoderInst__RleLiteralsDecoder_0__64_next", }, verilog_file = "rle_literals_dec.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -2117,6 +2034,7 @@ xls_dslx_library( srcs = ["raw_literals_dec.x"], deps = [ ":common_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -2134,9 +2052,13 @@ xls_dslx_verilog( "reset": "rst", "use_system_verilog": "false", }, - dslx_top = "RawLiteralsDecoder", + opt_ir_args = { + "top": "__raw_literals_dec__RawLiteralsDecoderInst__RawLiteralsDecoder_0__16_64_next" + }, + dslx_top = "RawLiteralsDecoderInst", library = ":raw_literals_dec_dslx", verilog_file = "raw_literals_dec.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -2145,12 +2067,15 @@ xls_benchmark_ir( benchmark_ir_args = { "pipeline_stages": "10", "delay_model": "asap7", + "top": "__raw_literals_dec__RawLiteralsDecoderInst__RawLiteralsDecoder_0__16_64_next" }, + tags = ["manual"], ) xls_benchmark_verilog( name = "raw_literals_dec_verilog_benchmark", verilog_target = "raw_literals_dec_verilog", + tags = ["manual"], ) verilog_library( @@ -2167,22 +2092,25 @@ synthesize_rtl( deps = [ ":raw_literals_dec_lib", ], + tags = ["manual"], ) benchmark_synth( name = "raw_literals_dec_benchmark_synth", synth_target = ":raw_literals_dec_asap7", + tags = ["manual"], ) place_and_route( name = "raw_literals_dec_place_and_route", clock_period = "750", core_padding_microns = 2, - min_pin_distance = "0.09", + min_pin_distance = "0.5", placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":raw_literals_dec_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -2286,13 +2214,17 @@ xls_dslx_library( ], deps = [ "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:axi_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ":common_dslx", ":literals_buffer_dslx", - ":literals_dispatcher_dslx", + ":literals_block_header_dec_dslx", ":parallel_rams_dslx", ":ram_printer_dslx", ":raw_literals_dec_dslx", ":rle_literals_dec_dslx", + ":huffman_literals_dec_dslx", ], ) @@ -2301,6 +2233,64 @@ xls_dslx_test( library = ":literals_decoder_dslx", ) +literals_decoder_ctrl_codegen_args = common_codegen_args | { + "module_name": "LiteralsDecoderCtrl", + "pipeline_stages": "10", +} + +xls_dslx_verilog( + name = "literals_decoder_ctrl_verilog", + codegen_args = literals_decoder_ctrl_codegen_args, + opt_ir_args = { + "inline_procs": "false", + }, + dslx_top = "LiteralsDecoderCtrlInst", + library = ":literals_decoder_dslx", + verilog_file = "literals_decoder_ctrl.v", + tags = ["manual"], +) + +xls_benchmark_ir( + name = "literals_decoder_ctrl_opt_ir_benchmark", + src = ":literals_decoder_ctrl_verilog.opt.ir", + benchmark_ir_args = literals_decoder_ctrl_codegen_args | { + "multi_proc": "true", + "inline_procs": "false", + }, +) + +verilog_library( + name = "literals_decoder_ctrl_verilog_lib", + srcs = [ + ":literals_decoder_ctrl.v", + ], +) + +synthesize_rtl( + name = "literals_decoder_ctrl_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "LiteralsDecoderCtrl", + deps = [ + ":literals_decoder_ctrl_verilog_lib", + ], +) + +benchmark_synth( + name = "literals_decoder_ctrl_benchmark_synth", + synth_target = ":literals_decoder_ctrl_synth_asap7", +) + +place_and_route( + name = "literals_decoder_ctrl_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":literals_decoder_ctrl_synth_asap7", + target_die_utilization_percentage = "10", +) + xls_dslx_verilog( name = "literals_decoder_verilog", codegen_args = { @@ -2319,7 +2309,7 @@ xls_dslx_verilog( ]), "pipeline_stages": "8", "reset": "rst", - "worst_case_throughput": "1", + "worst_case_throughput": "2", "use_system_verilog": "false", }, dslx_top = "LiteralsDecoderInst", @@ -2336,13 +2326,18 @@ xls_benchmark_ir( src = ":literals_decoder_verilog.opt.ir", benchmark_ir_args = { "pipeline_stages": "10", + "worst_case_throughput": "2", "delay_model": "asap7", + "inline_procs": "true", + "top": "__xls_modules_zstd_literals_buffer__LiteralsDecoderInst__LiteralsDecoder_0__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next", }, + tags = ["manual"], ) xls_benchmark_verilog( name = "literals_decoder_verilog_benchmark", verilog_target = "literals_decoder_verilog", + tags = ["manual"], ) verilog_library( @@ -2553,6 +2548,7 @@ xls_dslx_library( ], deps = [ "//xls/modules/zstd/memory:axi_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -2566,7 +2562,7 @@ huffman_axi_reader_codegen_args = common_codegen_args | { "module_name": "HuffmanAxiReader", "pipeline_stages": "8", "clock_period_ps": "750", - "worst_case_throughput": "2", + "worst_case_throughput": "4", } xls_dslx_verilog( @@ -2576,7 +2572,7 @@ xls_dslx_verilog( library = ":huffman_axi_reader_dslx", opt_ir_args = { "inline_procs": "true", - "top": "__huffman_axi_reader__HuffmanAxiReaderInst__HuffmanAxiReader_0__32_32_32_next", + "top": "__huffman_axi_reader__HuffmanAxiReaderInst__HuffmanAxiReader_0__16_8_3_64_4_4_next", }, tags = ["manual"], verilog_file = "huffman_axi_reader.v", @@ -2801,6 +2797,7 @@ xls_dslx_library( ":huffman_data_preprocessor_dslx", ":huffman_decoder_dslx", ":huffman_prescan_dslx", + ":huffman_weights_dec_dslx", ], ) @@ -2812,9 +2809,9 @@ xls_dslx_test( huffman_ctrl_codegen_args = common_codegen_args | { "module_name": "HuffmanCtrl", - "pipeline_stages": "4", + "pipeline_stages": "8", "clock_period_ps": "750", - "worst_case_throughput": "1", + "worst_case_throughput": "2", } xls_dslx_verilog( @@ -2824,7 +2821,7 @@ xls_dslx_verilog( library = ":huffman_ctrl_dslx", opt_ir_args = { "inline_procs": "true", - "top": "__huffman_ctrl__HuffmanControlAndSequenceInst__HuffmanControlAndSequence_0__32_next", + "top": "__huffman_ctrl__HuffmanControlAndSequenceInst__HuffmanControlAndSequence_0__32_64_next", }, tags = ["manual"], verilog_file = "huffman_ctrl.v", @@ -2873,12 +2870,96 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "huffman_weights_dec_dslx", + srcs = [ + "huffman_weights_dec.x", + ], + deps = [ + "//xls/modules/zstd:huffman_prescan_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/examples:ram_dslx", + ":ram_mux_dslx", + ], +) + +xls_dslx_test( + name = "huffman_weights_dec_dslx_test", + library = ":huffman_weights_dec_dslx", + tags = ["manual"], +) + +huffman_weights_dec_codegen_args = common_codegen_args | { + "module_name": "HuffmanWeightsDecoder", + "pipeline_stages": "25", + "clock_period_ps": "750", + "worst_case_throughput": "17", +} + +xls_dslx_verilog( + name = "huffman_weights_dec_verilog", + codegen_args = huffman_weights_dec_codegen_args, + dslx_top = "HuffmanWeightsDecoderInst", + library = ":huffman_weights_dec_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__huffman_weights_dec__HuffmanWeightsDecoderInst__HuffmanWeightsDecoder_0__32_64_6_32_8_next", + }, + tags = ["manual"], + verilog_file = "huffman_weights_dec.v", +) + +xls_benchmark_ir( + name = "huffman_weights_dec_opt_ir_benchmark", + src = ":huffman_weights_dec_verilog.opt.ir", + benchmark_ir_args = huffman_weights_dec_codegen_args, + tags = ["manual"], +) + +verilog_library( + name = "huffman_weights_dec_verilog_lib", + srcs = [ + ":huffman_weights_dec.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "huffman_weights_dec_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "HuffmanWeightsDecoder", + deps = [ + ":huffman_weights_dec_verilog_lib", + ], +) + +benchmark_synth( + name = "huffman_weights_dec_benchmark_synth", + synth_target = ":huffman_weights_dec_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "huffman_weights_dec_place_and_route", + clock_period = "750", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":huffman_weights_dec_synth_asap7", + tags = ["manual"], + target_die_utilization_percentage = "10", +) + xls_dslx_library( name = "huffman_literals_dec_dslx", srcs = [ "huffman_literals_dec.x", ], deps = [ + "//xls/modules/zstd/memory:axi_ram_dslx", ":common_dslx", ":huffman_axi_reader_dslx", ":huffman_code_builder_dslx", diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 68ff6bf81a..725d74a713 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -62,6 +62,7 @@ pub struct ExtendedBlockDataPacket { pub struct SequenceExecutorPacket { msg_type: SequenceExecutorMessageType, + // TODO: this should be max(8, clog2(maximum match value)) length: CopyOrMatchLength, // Literal length or match length content: uN[DATA_W * u32:8], // Literal data or match offset last: bool, // Last packet in frame @@ -277,13 +278,6 @@ pub struct LiteralsPathCtrl { literals_type: LiteralType, } -pub struct RleLiteralsData { - data: RleLitData, - repeat: RleLitRepeat, - last: bool, - id: LitID, -} - pub struct LiteralsData { data: LitData, length: LitLength, @@ -293,9 +287,9 @@ pub struct LiteralsData { pub struct LiteralsDataWithSync { data: LitData, length: LitLength, - last: bool, + last: bool, // last packet in single literals section decoding id: LitID, - literals_last: bool, + literals_last: bool, // last literals section in ZSTD frame } pub struct LiteralsBufferCtrl { diff --git a/xls/modules/zstd/huffman_axi_reader.x b/xls/modules/zstd/huffman_axi_reader.x index 507008cefa..5166789228 100644 --- a/xls/modules/zstd/huffman_axi_reader.x +++ b/xls/modules/zstd/huffman_axi_reader.x @@ -14,7 +14,9 @@ // This file contains the implementation of Huffmann data preprocessor. +import std; import xls.modules.zstd.memory.axi as axi; +import xls.modules.zstd.memory.mem_reader as mem_reader; pub struct HuffmanAxiReaderCtrl { base_addr: uN[AXI_ADDR_W], @@ -26,28 +28,33 @@ pub struct HuffmanAxiReaderData { last: bool, } -struct HuffmanAxiReaderState { +struct HuffmanAxiReaderState { ctrl: HuffmanAxiReaderCtrl, bytes_requested: uN[AXI_ADDR_W], bytes_sent: uN[AXI_ADDR_W], } -pub proc HuffmanAxiReader { - // FIXME: Replace hard-coded values with proc params AXI_DATA_W, AXI_ID_W - type AxiR = axi::AxiR; - // FIXME: Replace hard-coded values with proc params AXI_ADDR_W, AXI_ID_W - type AxiAr = axi::AxiAr; +pub proc HuffmanAxiReader { + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; - // FIXME: Replace hard-coded values with proc params AXI_ADDR_W - type Ctrl = HuffmanAxiReaderCtrl; + type Ctrl = HuffmanAxiReaderCtrl; type Data = HuffmanAxiReaderData; - // FIXME: Replace hard-coded values with proc params AXI_DATA_W, AXI_ADDR_W - type State = HuffmanAxiReaderState; + type MemRdReq = mem_reader::MemReaderReq; + type MemRdResp = mem_reader::MemReaderResp; + + type State = HuffmanAxiReaderState; ctrl_r: chan in; - axi_r_r: chan in; - axi_ar_s: chan out; + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; data_s: chan out; config ( @@ -56,10 +63,20 @@ pub proc HuffmanAxiReader { axi_ar_s: chan out, data_s: chan out, ) { + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + + spawn mem_reader::MemReader ( + mem_rd_req_r, + mem_rd_resp_s, + axi_ar_s, + axi_r_r + ); + ( ctrl_r, - axi_r_r, - axi_ar_s, + mem_rd_req_s, + mem_rd_resp_r, data_s, ) } @@ -83,18 +100,17 @@ pub proc HuffmanAxiReader { // send AXI read request // this could be optimized to read multiple bytes per AXI transaction let addr = state.ctrl.base_addr + state.ctrl.len - uN[AXI_ADDR_W]:1 - state.bytes_requested; - let axi_ar = AxiAr { - id: uN[AXI_ID_W]:0, + let mem_rd_req = MemRdReq { addr: addr, - ..zero!() + length: uN[AXI_ADDR_W]:1 }; - let do_send_axi_req = (state.bytes_requested < state.ctrl.len); - send_if(join(), axi_ar_s, do_send_axi_req, axi_ar); - if (do_send_axi_req) { - trace_fmt!("Sent AXI read request {:#x}", axi_ar); + let do_send_mem_rd_req = (state.bytes_requested < state.ctrl.len); + send_if(join(), mem_rd_req_s, do_send_mem_rd_req, mem_rd_req); + if (do_send_mem_rd_req) { + trace_fmt!("Sent memory read request {:#x}", mem_rd_req); } else {}; - let state = if do_send_axi_req { + let state = if do_send_mem_rd_req { State { bytes_requested: state.bytes_requested + uN[AXI_ADDR_W]:1, ..state @@ -103,20 +119,27 @@ pub proc HuffmanAxiReader { state }; - // receive data from AXI - let do_read_axi_resp = (state.bytes_requested > state.bytes_sent) && (state.bytes_sent < state.bytes_requested); - let (tok, axi_r, axi_r_valid) = recv_if_non_blocking(join(), axi_r_r, do_read_axi_resp, zero!()); + // receive data + let do_read_mem_rd_resp = (state.bytes_requested > state.bytes_sent) && (state.bytes_sent < state.bytes_requested); + let (tok, mem_rd_resp, mem_rd_resp_valid) = recv_if_non_blocking(join(), mem_rd_resp_r, do_read_mem_rd_resp, zero!()); + if mem_rd_resp_valid { + trace_fmt!("Received memory read response {:#x}", mem_rd_resp); + } else {}; // send data - let last = axi_r_valid && ((state.bytes_sent + uN[AXI_ADDR_W]:1) == state.ctrl.len); - let tok = send_if(tok, data_s, axi_r_valid, Data { - data: axi_r.data as u8, + let last = mem_rd_resp_valid && ((state.bytes_sent + uN[AXI_ADDR_W]:1) == state.ctrl.len); + let data = Data { + data: mem_rd_resp.data as u8, last: last, - }); + }; + let tok = send_if(tok, data_s, mem_rd_resp_valid, data); + if mem_rd_resp_valid { + trace_fmt!("Sent output data {:#x}", data); + } else {}; + let state = if last { zero!() - } else if axi_r_valid { - trace_fmt!("Received AXI read response {:#x}", axi_r); + } else if mem_rd_resp_valid { State { bytes_sent: state.bytes_sent + uN[AXI_ADDR_W]:1, ..state @@ -127,9 +150,10 @@ pub proc HuffmanAxiReader { } } -const INST_AXI_DATA_W = u32:32; -const INST_AXI_ADDR_W = u32:32; -const INST_AXI_ID_W = u32:32; +const INST_AXI_DATA_W = u32:64; +const INST_AXI_ADDR_W = u32:16; +const INST_AXI_ID_W = u32:4; +const INST_AXI_DEST_W = u32:4; proc HuffmanAxiReaderInst { type InstHuffmanAxiReaderCtrl = HuffmanAxiReaderCtrl; @@ -143,7 +167,7 @@ proc HuffmanAxiReaderInst { axi_ar_s: chan out, data_s: chan out, ) { - spawn HuffmanAxiReader( + spawn HuffmanAxiReader( ctrl_r, axi_r_r, axi_ar_s, @@ -156,9 +180,12 @@ proc HuffmanAxiReaderInst { next (state: ()) { } } -const TEST_AXI_DATA_W = u32:32; -const TEST_AXI_ADDR_W = u32:32; -const TEST_AXI_ID_W = u32:32; +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_ADDR_W = u32:16; +const TEST_AXI_ID_W = u32:4; +const TEST_AXI_DEST_W = u32:4; +const TEST_AXI_DATA_DIV8 = TEST_AXI_DATA_W / u32:8; +const TEST_AXI_DATA_DIV8_W = std::clog2(TEST_AXI_DATA_DIV8); type TestHuffmanAxiReaderCtrl = HuffmanAxiReaderCtrl; @@ -188,23 +215,23 @@ const TEST_DATA_CTRL = TestHuffmanAxiReaderCtrl[3]:[ ]; const TEST_DATA_AXI = TestAxiData[7]:[ - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:0, data: uN[TEST_AXI_DATA_W]:0x12, len: u8:0, last: true, }, - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:131, data: uN[TEST_AXI_DATA_W]:0xAA, len: u8:0, last: true, }, - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:130, data: uN[TEST_AXI_DATA_W]:0xBB, len: u8:0, last: true, }, - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:129, data: uN[TEST_AXI_DATA_W]:0xCC, len: u8:0, last: true, }, - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:128, data: uN[TEST_AXI_DATA_W]:0xDD, len: u8:0, last: true, }, - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:65, data: uN[TEST_AXI_DATA_W]:0x44, len: u8:0, last: false, }, - TestAxiData { addr: uN[TEST_AXI_ADDR_W]:64, data: uN[TEST_AXI_DATA_W]:0x55, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:0, data: uN[TEST_AXI_DATA_W]:0x0123456789ABCDF0, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:131, data: uN[TEST_AXI_DATA_W]:0x8899AABBCCDDEEFF, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:130, data: uN[TEST_AXI_DATA_W]:0x8899AABBCCDDEEFF, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:129, data: uN[TEST_AXI_DATA_W]:0x8899AABBCCDDEEFF, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:128, data: uN[TEST_AXI_DATA_W]:0x8899AABBCCDDEEFF, len: u8:0, last: true, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:65, data: uN[TEST_AXI_DATA_W]:0xDEADBEEFFEEBDAED, len: u8:0, last: false, }, + TestAxiData { addr: uN[TEST_AXI_ADDR_W]:64, data: uN[TEST_AXI_DATA_W]:0xDEADBEEFFEEBDAED, len: u8:0, last: true, }, ]; const TEST_DATA_OUT = HuffmanAxiReaderData[7]:[ - HuffmanAxiReaderData { data: u8:0x12, last: true, }, - HuffmanAxiReaderData { data: u8:0xAA, last: false, }, - HuffmanAxiReaderData { data: u8:0xBB, last: false, }, + HuffmanAxiReaderData { data: u8:0xF0, last: true, }, HuffmanAxiReaderData { data: u8:0xCC, last: false, }, - HuffmanAxiReaderData { data: u8:0xDD, last: true, }, - HuffmanAxiReaderData { data: u8:0x44, last: false, }, - HuffmanAxiReaderData { data: u8:0x55, last: true, }, + HuffmanAxiReaderData { data: u8:0xDD, last: false, }, + HuffmanAxiReaderData { data: u8:0xEE, last: false, }, + HuffmanAxiReaderData { data: u8:0xFF, last: true, }, + HuffmanAxiReaderData { data: u8:0xDA, last: false, }, + HuffmanAxiReaderData { data: u8:0xED, last: true, }, ]; #[test_proc] @@ -222,7 +249,7 @@ proc HuffmanAxiReader_test { let (axi_ar_s, axi_ar_r) = chan("axi_ar"); let (data_s, data_r) = chan("data"); - spawn HuffmanAxiReader ( + spawn HuffmanAxiReader ( ctrl_r, axi_r_r, axi_ar_s, @@ -251,8 +278,9 @@ proc HuffmanAxiReader_test { let tok = for ((i, test_axi), tok): ((u32, TestAxiData), token) in enumerate(TEST_DATA_AXI) { let (tok, axi_req) = recv(tok, axi_ar_r); trace_fmt!("Received #{} AXI request {:#x}", i + u32:1, axi_req); + let aligned_addr = test_axi.addr & !(test_axi.addr % TEST_AXI_DATA_DIV8 as uN[TEST_AXI_ADDR_W]); - assert_eq(test_axi.addr, axi_req.addr); + assert_eq(aligned_addr, axi_req.addr); assert_eq(test_axi.len, axi_req.len); let axi_resp = TestAxiR { diff --git a/xls/modules/zstd/huffman_code_builder.x b/xls/modules/zstd/huffman_code_builder.x index 4b554779c1..226a6ad2d8 100644 --- a/xls/modules/zstd/huffman_code_builder.x +++ b/xls/modules/zstd/huffman_code_builder.x @@ -288,16 +288,16 @@ pub proc WeightCodeBuilder update(codes, i, code) }(zero!()); - if send_codes { - trace_fmt!("{}\n{}\n{:#b}\n{:#b}", symbols_valid, codes_length, codes, state.huffman_codes); - } else {}; - let code_packet = DecoderOutput { symbol_valid: symbols_valid, code_length: codes_length, code: codes }; send_if(tok, codes_s, send_codes, code_packet); + if send_codes { + trace_fmt!("Sent codes: \nsymbols_valid: {}\ncodes_length: {}\ncodes: {:#b}\nstate.huffman_codes: {:#b}", symbols_valid, codes_length, codes, state.huffman_codes); + } else {}; + next_state } diff --git a/xls/modules/zstd/huffman_ctrl.x b/xls/modules/zstd/huffman_ctrl.x index d5ac04d427..036a765525 100644 --- a/xls/modules/zstd/huffman_ctrl.x +++ b/xls/modules/zstd/huffman_ctrl.x @@ -15,12 +15,14 @@ // This file contains Huffman decoder control and sequence proc implementation. import xls.modules.zstd.common as common; +import xls.modules.zstd.memory.mem_reader as mem_reader; import xls.modules.zstd.huffman_common as hcommon; import xls.modules.zstd.huffman_axi_reader as axi_reader; import xls.modules.zstd.huffman_code_builder as code_builder; import xls.modules.zstd.huffman_data_preprocessor as data_preprocessor; import xls.modules.zstd.huffman_decoder as decoder; import xls.modules.zstd.huffman_prescan as prescan; +import xls.modules.zstd.huffman_weights_dec as weights_dec; enum HuffmanControlAndSequenceFSM: u2 { @@ -32,22 +34,57 @@ pub struct HuffmanControlAndSequenceCtrl { base_addr: uN[AXI_ADDR_W], len: uN[AXI_ADDR_W], new_config: bool, + multi_stream: bool, + id: u32, + literals_last: bool, } -struct HuffmanControlAndSequenceState { +pub enum HuffmanControlAndSequenceStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +pub struct HuffmanControlAndSequenceResp { + status: HuffmanControlAndSequenceStatus +} + +struct HuffmanControlAndSequenceState { fsm: HuffmanControlAndSequenceFSM, + weights_dec_pending: bool, + stream_dec_pending: bool, + multi_stream_dec_pending: bool, + multi_stream_decodings_finished: u3, + jump_table_dec_pending: bool, + jump_table_req_sent: bool, + tree_description_size: uN[AXI_ADDR_W], + ctrl: HuffmanControlAndSequenceCtrl, + stream_sizes: uN[AXI_ADDR_W][4], } -pub proc HuffmanControlAndSequence { +const JUMP_TABLE_SIZE = u32:6; + +pub proc HuffmanControlAndSequence { type AxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; type DataPreprocessorStart = data_preprocessor::HuffmanDataPreprocessorStart; type DecoderStart = decoder::HuffmanDecoderStart; + type WeightsDecReq = weights_dec::HuffmanWeightsDecoderReq; + type WeightsDecResp = weights_dec::HuffmanWeightsDecoderResp; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + - type State = HuffmanControlAndSequenceState; + type State = HuffmanControlAndSequenceState; type FSM = HuffmanControlAndSequenceFSM; type Ctrl = HuffmanControlAndSequenceCtrl; + type Resp = HuffmanControlAndSequenceResp; + type Status = HuffmanControlAndSequenceStatus; ctrl_r: chan in; + resp_s: chan out; + + // Huffman tree description decoder + weights_dec_req_s: chan out; + weights_dec_resp_r: chan in; // prescan prescan_start_s: chan out; @@ -65,23 +102,36 @@ pub proc HuffmanControlAndSequence { decoder_start_s: chan out; decoder_done_r: chan<()> in; + // MemReader interface for fetching the Jump Table + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; + + config ( ctrl_r: chan in, + resp_s: chan out, + weights_dec_req_s: chan out, + weights_dec_resp_r: chan in, prescan_start_s: chan out, code_builder_start_s: chan out, axi_reader_ctrl_s: chan out, data_preprocess_start_s: chan out, decoder_start_s: chan out, decoder_done_r: chan<()> in, + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, ) { ( - ctrl_r, + ctrl_r, resp_s, + weights_dec_req_s, + weights_dec_resp_r, prescan_start_s, code_builder_start_s, axi_reader_ctrl_s, data_preprocess_start_s, decoder_start_s, decoder_done_r, + mem_rd_req_s, mem_rd_resp_r, ) } @@ -92,10 +142,16 @@ pub proc HuffmanControlAndSequence { next (state: State) { // receive start let (tok, ctrl, ctrl_valid) = recv_if_non_blocking(join(), ctrl_r, state.fsm == FSM::IDLE, zero!()); + if (ctrl_valid) { trace_fmt!("Received Ctrl: {:#x}", ctrl); } else {}; let state = if ctrl_valid { State { fsm: FSM::DECODING, + ctrl: ctrl, + weights_dec_pending: ctrl.new_config, + multi_stream_dec_pending: ctrl.multi_stream, + jump_table_dec_pending: ctrl.multi_stream, + ..state } } else { state @@ -104,73 +160,204 @@ pub proc HuffmanControlAndSequence { // send start to prescan and code builder let new_config = ctrl_valid & ctrl.new_config; - if new_config { - trace_fmt!("Sending start to prescan and code builder"); + // New config means the requirement to read and decode new Huffman Tree Description + // Delegate this task to HuffmanWeightsDecoder + let weights_dec_req = WeightsDecReq { + addr: ctrl.base_addr + }; + send_if(tok, weights_dec_req_s, new_config, weights_dec_req); + if (new_config) { trace_fmt!("Sent Weights Decoding Request: {:#x}", weights_dec_req); } else {}; + + // recv response + let (tok, weights_dec_resp, weights_dec_resp_valid) = recv_if_non_blocking(tok, weights_dec_resp_r, state.weights_dec_pending, zero!()); + if (weights_dec_resp_valid) { trace_fmt!("Received Weights Decoding response: {:#x}", weights_dec_resp); } else {}; + let state = if weights_dec_resp_valid { + State { + weights_dec_pending: false, + tree_description_size: weights_dec_resp.tree_description_size, + ..state + } + } else { + state + }; + + // Fetch the Jump Table if neccessary + let jump_table_req = MemReaderReq { + addr: state.ctrl.base_addr + state.tree_description_size, + length: JUMP_TABLE_SIZE as uN[AXI_ADDR_W], + }; + let do_send_jump_table_req = !state.weights_dec_pending && state.jump_table_dec_pending && !state.jump_table_req_sent; + let tok = send_if(tok, mem_rd_req_s, do_send_jump_table_req, jump_table_req); + if do_send_jump_table_req { + trace_fmt!("Sent Jump Table read request {:#x}", jump_table_req); } else {}; - send_if(tok, prescan_start_s, new_config, true); - send_if(tok, code_builder_start_s, new_config, true); + let (tok, jump_table_raw, jump_table_valid) = recv_if_non_blocking(tok, mem_rd_resp_r, state.jump_table_dec_pending, zero!()); + let stream_sizes = jump_table_raw.data[0:48] as u16[3]; + let total_streams_size = state.ctrl.len - state.tree_description_size; + let stream_sizes = uN[AXI_ADDR_W][4]:[stream_sizes[0] as uN[AXI_ADDR_W], stream_sizes[1] as uN[AXI_ADDR_W], stream_sizes[2] as uN[AXI_ADDR_W], total_streams_size - JUMP_TABLE_SIZE as uN[AXI_ADDR_W] - (stream_sizes[0] + stream_sizes[1] + stream_sizes[2]) as uN[AXI_ADDR_W]]; + if jump_table_valid { + trace_fmt!("Received Jump Table: {:#x}", jump_table_raw); + trace_fmt!("total_streams_size: {:#x}", total_streams_size); + trace_fmt!("state.tree_description_size: {:#x}", state.tree_description_size); + trace_fmt!("stream sizes: {:#x}", stream_sizes); + } else {}; + let state = if do_send_jump_table_req { + State { + jump_table_req_sent: true, + ..state + } + } else if jump_table_valid { + State { + jump_table_dec_pending: false, + jump_table_req_sent: false, + stream_sizes: stream_sizes, + ..state + } + } else { + state + }; + + let start_decoding = ((state.fsm == FSM::DECODING) & (!state.weights_dec_pending) & (!state.stream_dec_pending) & (!state.jump_table_dec_pending) & ((!state.multi_stream_dec_pending) || (state.multi_stream_dec_pending && state.multi_stream_decodings_finished != u3:4))); + send_if(tok, prescan_start_s, start_decoding, true); + send_if(tok, code_builder_start_s, start_decoding, true); + if (start_decoding) { trace_fmt!("Sent START to prescan and code builder"); } else {}; + + let stream_sizes = state.stream_sizes; + let (huffman_stream_addr, huffman_stream_len) = match(state.ctrl.new_config, state.ctrl.multi_stream, state.multi_stream_decodings_finished) { + (false, false, _) => (state.ctrl.base_addr, state.ctrl.len), + (true, false, _) => ((state.ctrl.base_addr + state.tree_description_size), (state.ctrl.len - state.tree_description_size)), + + (false, true, u3:0) => ((state.ctrl.base_addr + JUMP_TABLE_SIZE as uN[AXI_ADDR_W]), (stream_sizes[0] as uN[AXI_ADDR_W])), + (false, true, u3:1) => ((state.ctrl.base_addr + JUMP_TABLE_SIZE as uN[AXI_ADDR_W] + stream_sizes[0]), (stream_sizes[1] as uN[AXI_ADDR_W])), + (false, true, u3:2) => ((state.ctrl.base_addr + JUMP_TABLE_SIZE as uN[AXI_ADDR_W] + stream_sizes[0] + stream_sizes[1]), (stream_sizes[2] as uN[AXI_ADDR_W])), + (false, true, u3:3) => ((state.ctrl.base_addr + JUMP_TABLE_SIZE as uN[AXI_ADDR_W] + stream_sizes[0] + stream_sizes[1] + stream_sizes[2]), (stream_sizes[3] as uN[AXI_ADDR_W])), + + (true, true, u3:0) => ((state.ctrl.base_addr + state.tree_description_size + JUMP_TABLE_SIZE as uN[AXI_ADDR_W]), (stream_sizes[0] as uN[AXI_ADDR_W])), + (true, true, u3:1) => ((state.ctrl.base_addr + state.tree_description_size + JUMP_TABLE_SIZE as uN[AXI_ADDR_W] + stream_sizes[0]), (stream_sizes[1] as uN[AXI_ADDR_W])), + (true, true, u3:2) => ((state.ctrl.base_addr + state.tree_description_size + JUMP_TABLE_SIZE as uN[AXI_ADDR_W] + stream_sizes[0] + stream_sizes[1]), (stream_sizes[2] as uN[AXI_ADDR_W])), + (true, true, u3:3) => ((state.ctrl.base_addr + state.tree_description_size + JUMP_TABLE_SIZE as uN[AXI_ADDR_W] + stream_sizes[0] + stream_sizes[1] + stream_sizes[2]), (stream_sizes[3] as uN[AXI_ADDR_W])), + + (_, _, _) => (state.ctrl.base_addr, state.ctrl.len) + }; // send address and length to AXI reader - if ctrl_valid { - trace_fmt!("Sending ctrl to AXI reader"); - } else {}; - send_if(tok, axi_reader_ctrl_s, ctrl_valid, AxiReaderCtrl { - base_addr: ctrl.base_addr, - len: ctrl.len, - }); + let axi_reader_ctrl = AxiReaderCtrl { + base_addr: huffman_stream_addr, + len: huffman_stream_len, + }; + send_if(tok, axi_reader_ctrl_s, start_decoding, axi_reader_ctrl); + if (start_decoding) { trace_fmt!("Sent request to AXI reader: {:#x}", axi_reader_ctrl); } else {}; // send reconfigure/keep to data preprocessor and decoder - if ctrl_valid { - trace_fmt!("Sending start to data preprocessor and decoder"); - } else {}; - send_if(tok, data_preprocess_start_s, ctrl_valid, DataPreprocessorStart { - new_config: new_config, - }); - send_if(tok, decoder_start_s, ctrl_valid, DecoderStart { - new_config: new_config, - }); + let config = if (state.multi_stream_decodings_finished > u3:0) { + false + } else { + state.ctrl.new_config + }; + let preprocessor_start = DataPreprocessorStart { + new_config: config, + }; + send_if(tok, data_preprocess_start_s, start_decoding, preprocessor_start); + if start_decoding { trace_fmt!("Sent preprocessor start: {:#x}", preprocessor_start); } else {}; + let decoder_start = DecoderStart { + new_config: config, + id: state.ctrl.id, // sending only if ctrl is valid + literals_last: state.ctrl.literals_last, + last_stream: !state.ctrl.multi_stream || (state.ctrl.multi_stream && state.multi_stream_decodings_finished == u3:3), + }; + send_if(tok, decoder_start_s, start_decoding, decoder_start); + if start_decoding { trace_fmt!("Sent decoder start: {:#x}", decoder_start); } else {}; + let state = if start_decoding { + State { + stream_dec_pending: true, + ..state + } + } else { + state + }; // receive done let (_, _, decoder_done_valid) = recv_if_non_blocking(tok, decoder_done_r, state.fsm == FSM::DECODING, ()); - if decoder_done_valid { - trace_fmt!("Received decoder done"); - } else {}; + if (decoder_done_valid) { trace_fmt!("Received Decoder Done"); } else {}; + let multi_stream_decodings_finished = if state.multi_stream_dec_pending { + state.multi_stream_decodings_finished + u3:1 + } else { + state.multi_stream_decodings_finished + }; + + let state = if decoder_done_valid { + State { + stream_dec_pending: false, + multi_stream_decodings_finished: multi_stream_decodings_finished, + ..state + } + } else { + state + }; - if decoder_done_valid { + let state = if (multi_stream_decodings_finished == u3:4) { + trace_fmt!("Multi-Stream decoding done"); State { - fsm: FSM::IDLE + multi_stream_dec_pending: false, + multi_stream_decodings_finished: u3:0, + ..state } } else { state + }; + + let resp = Resp { status: Status::OKAY }; + let do_send_resp = decoder_done_valid && !state.multi_stream_dec_pending && state.multi_stream_decodings_finished == u3:0; + send_if(tok, resp_s, do_send_resp, resp); + if (do_send_resp) { trace_fmt!("Sent Ctrl response: {:#x}", resp); } else {}; + + if do_send_resp { + zero!() + } else { + state } } } const INST_AXI_ADDR_W = u32:32; +const INST_AXI_DATA_W = u32:64; proc HuffmanControlAndSequenceInst { type AxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; type DataPreprocessorStart = data_preprocessor::HuffmanDataPreprocessorStart; type DecoderStart = decoder::HuffmanDecoderStart; + type WeightsDecReq = weights_dec::HuffmanWeightsDecoderReq; + type WeightsDecResp = weights_dec::HuffmanWeightsDecoderResp; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; config ( ctrl_r: chan> in, + resp_s: chan out, + weights_dec_req_s: chan out, + weights_dec_resp_r: chan in, prescan_start_s: chan out, code_builder_start_s: chan out, axi_reader_ctrl_s: chan out, data_preprocess_start_s: chan out, decoder_start_s: chan out, decoder_done_r: chan<()> in, + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, ) { - spawn HuffmanControlAndSequence( - ctrl_r, + spawn HuffmanControlAndSequence( + ctrl_r, resp_s, + weights_dec_req_s, + weights_dec_resp_r, prescan_start_s, code_builder_start_s, axi_reader_ctrl_s, data_preprocess_start_s, decoder_start_s, decoder_done_r, + mem_rd_req_s, + mem_rd_resp_r, ); } @@ -181,52 +368,78 @@ proc HuffmanControlAndSequenceInst { const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_DATA_W = u32:64; #[test_proc] proc HuffmanControlAndSequence_test { - type Ctrl = HuffmanControlAndSequenceCtrl; + type Ctrl = HuffmanControlAndSequenceCtrl; + type Resp = HuffmanControlAndSequenceResp; + type Status = HuffmanControlAndSequenceStatus; type AxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; type DataPreprocessorStart = data_preprocessor::HuffmanDataPreprocessorStart; type DecoderStart = decoder::HuffmanDecoderStart; + type WeightsDecReq = weights_dec::HuffmanWeightsDecoderReq; + type WeightsDecResp = weights_dec::HuffmanWeightsDecoderResp; + type WeightsDecStatus = weights_dec::HuffmanWeightsDecoderStatus; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; terminator: chan out; ctrl_s: chan> out; + resp_r: chan in; + weights_dec_req_r: chan in; + weights_dec_resp_s: chan out; prescan_start_r: chan in; code_builder_start_r: chan in; axi_reader_ctrl_r: chan in; data_preprocess_start_r: chan in; decoder_start_r: chan in; decoder_done_s: chan<()> out; + mem_rd_req_r: chan in; + mem_rd_resp_s: chan out; config (terminator: chan out) { let (ctrl_s, ctrl_r) = chan("ctrl"); + let (resp_s, resp_r) = chan("resp"); + let (weights_dec_req_s, weights_dec_req_r) = chan("weights_dec_req"); + let (weights_dec_resp_s, weights_dec_resp_r) = chan("weights_dec_resp"); let (prescan_start_s, prescan_start_r) = chan("prescan_start"); let (code_builder_start_s, code_builder_start_r) = chan("code_builder_start"); let (axi_reader_ctrl_s, axi_reader_ctrl_r) = chan("axi_reader_ctrl"); let (data_preprocess_start_s, data_preprocess_start_r) = chan("data_preprocess_start"); let (decoder_start_s, decoder_start_r) = chan("decoder_start"); let (decoder_done_s, decoder_done_r) = chan<()>("decoder_done"); - - spawn HuffmanControlAndSequence( - ctrl_r, + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + + spawn HuffmanControlAndSequence( + ctrl_r, resp_s, + weights_dec_req_s, + weights_dec_resp_r, prescan_start_s, code_builder_start_s, axi_reader_ctrl_s, data_preprocess_start_s, decoder_start_s, decoder_done_r, + mem_rd_req_s, + mem_rd_resp_r ); ( terminator, - ctrl_s, + ctrl_s, resp_r, + weights_dec_req_r, + weights_dec_resp_s, prescan_start_r, code_builder_start_r, axi_reader_ctrl_r, data_preprocess_start_r, decoder_start_r, decoder_done_s, + mem_rd_req_r, + mem_rd_resp_s ) } @@ -234,50 +447,227 @@ proc HuffmanControlAndSequence_test { next (state: ()) { let tok = join(); - - // without new config + // Single Stream + // Without new config + trace_fmt!("[TEST] Case #1"); let ctrl = Ctrl { base_addr: uN[TEST_AXI_ADDR_W]:0x1, len: uN[TEST_AXI_ADDR_W]:0x2, new_config: false, + multi_stream: false, + id: u32:10, + literals_last: true, }; let tok = send(tok, ctrl_s, ctrl); + let (tok, prescan_start) = recv(tok, prescan_start_r); + trace_fmt!("[TEST] Received prescan START"); + assert_eq(true, prescan_start); + + let (tok, code_builder_start) = recv(tok, code_builder_start_r); + trace_fmt!("[TEST] Received code builder START"); + assert_eq(true, code_builder_start); + let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); + trace_fmt!("[TEST] Received AXI reader CTRL"); assert_eq(AxiReaderCtrl {base_addr: ctrl.base_addr, len: ctrl.len}, axi_reader_ctrl); let (tok, data_preprocess_start) = recv(tok, data_preprocess_start_r); + trace_fmt!("[TEST] Received data preprocess START"); assert_eq(DataPreprocessorStart {new_config: ctrl.new_config}, data_preprocess_start); let (tok, decoder_start) = recv(tok, decoder_start_r); - assert_eq(DecoderStart {new_config: ctrl.new_config}, decoder_start); + trace_fmt!("[TEST] Received decoder START"); + assert_eq(DecoderStart {new_config: ctrl.new_config, id: ctrl.id, literals_last: ctrl.literals_last, last_stream: true }, decoder_start); let tok = send(tok, decoder_done_s, ()); + let (tok, resp) = recv(tok, resp_r); + trace_fmt!("[TEST] Received resp"); + assert_eq(Resp {status: Status::OKAY}, resp); - // with new config + // Single Stream + // With new config + trace_fmt!("[TEST] Case #2"); let ctrl = Ctrl { base_addr: uN[TEST_AXI_ADDR_W]:0x1, - len: uN[TEST_AXI_ADDR_W]:0x2, + len: uN[TEST_AXI_ADDR_W]:0x50, new_config: true, + multi_stream: false, + id: u32:0, + literals_last: false, }; let tok = send(tok, ctrl_s, ctrl); + let (tok, weights_dec_req) = recv(tok, weights_dec_req_r); + trace_fmt!("[TEST] Received weights decode request"); + assert_eq(WeightsDecReq {addr: uN[TEST_AXI_ADDR_W]:0x1}, weights_dec_req); + + // Signal Weight decoding done + let tree_description_size = uN[TEST_AXI_ADDR_W]:0x25; + let tok = send(tok, weights_dec_resp_s, WeightsDecResp{ + status: WeightsDecStatus::OKAY, + tree_description_size: tree_description_size + }); + let (tok, prescan_start) = recv(tok, prescan_start_r); + trace_fmt!("[TEST] Received prescan START"); assert_eq(true, prescan_start); let (tok, code_builder_start) = recv(tok, code_builder_start_r); + trace_fmt!("[TEST] Received code builder START"); assert_eq(true, code_builder_start); let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); - assert_eq(AxiReaderCtrl {base_addr: ctrl.base_addr, len: ctrl.len}, axi_reader_ctrl); + trace_fmt!("[TEST] Received AXI reader CTRL"); + assert_eq(AxiReaderCtrl {base_addr: ctrl.base_addr + tree_description_size, len: ctrl.len - tree_description_size}, axi_reader_ctrl); let (tok, data_preprocess_start) = recv(tok, data_preprocess_start_r); + trace_fmt!("[TEST] Received data preprocess START"); assert_eq(DataPreprocessorStart {new_config: ctrl.new_config}, data_preprocess_start); let (tok, decoder_start) = recv(tok, decoder_start_r); - assert_eq(DecoderStart {new_config: ctrl.new_config}, decoder_start); + trace_fmt!("[TEST] Received decoder START"); + assert_eq(DecoderStart {new_config: ctrl.new_config, id: ctrl.id, literals_last: ctrl.literals_last, last_stream: true }, decoder_start); let tok = send(tok, decoder_done_s, ()); + let (tok, resp) = recv(tok, resp_r); + trace_fmt!("[TEST] Received resp"); + assert_eq(Resp {status: Status::OKAY}, resp); + + // 4 Streams + // Without new config + trace_fmt!("[TEST] Case #3"); + let ctrl = Ctrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x1, + len: uN[TEST_AXI_ADDR_W]:0xF, + new_config: false, + multi_stream: true, + id: u32:10, + literals_last: true, + }; + let tok = send(tok, ctrl_s, ctrl); + + let (tok, mem_rd_req) = recv(tok, mem_rd_req_r); + trace_fmt!("[TEST] Received jump table read request"); + assert_eq(MemReaderReq {addr: uN[TEST_AXI_ADDR_W]:0x1, length: uN[TEST_AXI_ADDR_W]:0x6}, mem_rd_req); + + let tok = send(tok, mem_rd_resp_s, MemReaderResp {status: mem_reader::MemReaderStatus::OKAY, data: uN[TEST_AXI_DATA_W]:0x0003_0002_0001, length: uN[TEST_AXI_ADDR_W]:0x6, last:true}); + + const TEST_STREAM_ADDR = uN[TEST_AXI_ADDR_W][4]:[ + ctrl.base_addr + JUMP_TABLE_SIZE, + ctrl.base_addr + JUMP_TABLE_SIZE + uN[TEST_AXI_ADDR_W]:0x3, + ctrl.base_addr + JUMP_TABLE_SIZE + uN[TEST_AXI_ADDR_W]:0x5, + ctrl.base_addr + JUMP_TABLE_SIZE + uN[TEST_AXI_ADDR_W]:0x6, + ]; + const TEST_STREAM_LENGTH = uN[TEST_AXI_ADDR_W][4]:[ + uN[TEST_AXI_ADDR_W]:0x3, + uN[TEST_AXI_ADDR_W]:0x2, + uN[TEST_AXI_ADDR_W]:0x1, + uN[TEST_AXI_ADDR_W]:0x3, + ]; + + for (i, tok) in u32:0..u32:4 { + trace_fmt!("[TEST] Stream #{}", i); + + let (tok, prescan_start) = recv(tok, prescan_start_r); + trace_fmt!("[TEST] Received prescan START"); + assert_eq(true, prescan_start); + + let (tok, code_builder_start) = recv(tok, code_builder_start_r); + trace_fmt!("[TEST] Received code builder START"); + assert_eq(true, code_builder_start); + + let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); + trace_fmt!("[TEST] Received AXI reader CTRL"); + assert_eq(AxiReaderCtrl {base_addr: TEST_STREAM_ADDR[i], len: TEST_STREAM_LENGTH[i]}, axi_reader_ctrl); + + let (tok, data_preprocess_start) = recv(tok, data_preprocess_start_r); + trace_fmt!("[TEST] Received data preprocess START"); + assert_eq(DataPreprocessorStart {new_config: ctrl.new_config}, data_preprocess_start); + + let (tok, decoder_start) = recv(tok, decoder_start_r); + trace_fmt!("[TEST] Received decoder START"); + assert_eq(DecoderStart {new_config: ctrl.new_config, id: ctrl.id, literals_last: ctrl.literals_last, last_stream: (i == u32:3) }, decoder_start); + + let tok = send(tok, decoder_done_s, ()); + + tok + }(tok); + + let (tok, resp) = recv(tok, resp_r); + trace_fmt!("[TEST] Received resp"); + assert_eq(Resp {status: Status::OKAY}, resp); + + // 4 Streams + // With new config + trace_fmt!("[TEST] Case #4"); + let ctrl = Ctrl { + base_addr: uN[TEST_AXI_ADDR_W]:0x1, + len: uN[TEST_AXI_ADDR_W]:0x50, + new_config: true, + multi_stream: true, + id: u32:0, + literals_last: false, + }; + let tok = send(tok, ctrl_s, ctrl); + + let (tok, weights_dec_req) = recv(tok, weights_dec_req_r); + trace_fmt!("[TEST] Received weights decode request"); + assert_eq(WeightsDecReq {addr: uN[TEST_AXI_ADDR_W]:0x1}, weights_dec_req); + + // Signal Weight decoding done + let tree_description_size = uN[TEST_AXI_ADDR_W]:0x25; + let tok = send(tok, weights_dec_resp_s, WeightsDecResp{ + status: WeightsDecStatus::OKAY, + tree_description_size: tree_description_size + }); + + let (tok, mem_rd_req) = recv(tok, mem_rd_req_r); + trace_fmt!("[TEST] Received jump table read request"); + assert_eq(MemReaderReq {addr: uN[TEST_AXI_ADDR_W]:0x26, length: uN[TEST_AXI_ADDR_W]:0x6}, mem_rd_req); + + let tok = send(tok, mem_rd_resp_s, MemReaderResp {status: mem_reader::MemReaderStatus::OKAY, data: uN[TEST_AXI_DATA_W]:0x0003_0002_0001, length: uN[TEST_AXI_ADDR_W]:0x6, last:true}); + + const TEST_STREAM_ADDR = uN[TEST_AXI_ADDR_W][4]:[ + ctrl.base_addr + tree_description_size + JUMP_TABLE_SIZE, + ctrl.base_addr + tree_description_size + JUMP_TABLE_SIZE + uN[TEST_AXI_ADDR_W]:0x3, + ctrl.base_addr + tree_description_size + JUMP_TABLE_SIZE + uN[TEST_AXI_ADDR_W]:0x5, + ctrl.base_addr + tree_description_size + JUMP_TABLE_SIZE + uN[TEST_AXI_ADDR_W]:0x6, + ]; + const TEST_STREAM_LENGTH = uN[TEST_AXI_ADDR_W][4]:[ + uN[TEST_AXI_ADDR_W]:0x3, + uN[TEST_AXI_ADDR_W]:0x2, + uN[TEST_AXI_ADDR_W]:0x1, + uN[TEST_AXI_ADDR_W]:0x1F, + ]; + + for (i, tok) in u32:0..u32:4 { + trace_fmt!("[TEST] Stream #{}", i); + + let (tok, prescan_start) = recv(tok, prescan_start_r); + trace_fmt!("[TEST] Received prescan START"); + assert_eq(true, prescan_start); + + let (tok, code_builder_start) = recv(tok, code_builder_start_r); + trace_fmt!("[TEST] Received code builder START"); + assert_eq(true, code_builder_start); + + let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); + trace_fmt!("[TEST] Received AXI reader CTRL"); + assert_eq(AxiReaderCtrl {base_addr: TEST_STREAM_ADDR[i], len: TEST_STREAM_LENGTH[i]}, axi_reader_ctrl); + + let (tok, data_preprocess_start) = recv(tok, data_preprocess_start_r); + trace_fmt!("[TEST] Received data preprocess START"); + assert_eq(DataPreprocessorStart {new_config: ctrl.new_config && (i == u32:0)}, data_preprocess_start); + + let (tok, decoder_start) = recv(tok, decoder_start_r); + trace_fmt!("[TEST] Received decoder START"); + assert_eq(DecoderStart {new_config: ctrl.new_config && (i == u32:0), id: ctrl.id, literals_last: ctrl.literals_last, last_stream: (i == u32:3) }, decoder_start); + + let tok = send(tok, decoder_done_s, ()); + + tok + }(tok); send(tok, terminator, true); } diff --git a/xls/modules/zstd/huffman_data_preprocessor.x b/xls/modules/zstd/huffman_data_preprocessor.x index 4f97cb9943..445f6fed8d 100644 --- a/xls/modules/zstd/huffman_data_preprocessor.x +++ b/xls/modules/zstd/huffman_data_preprocessor.x @@ -111,6 +111,7 @@ pub proc HuffmanDataPreprocessor { ); let state = if config_valid { + trace_fmt!("Received config {:#x}", config); State { fsm: FSM::READ_DATA, lookahead_config: config, @@ -124,6 +125,7 @@ pub proc HuffmanDataPreprocessor { // process data let state = if data_valid { + trace_fmt!("Received data {:#x}", data); let fsm = if data.last { FSM::PROCESSING } else { diff --git a/xls/modules/zstd/huffman_decoder.x b/xls/modules/zstd/huffman_decoder.x index e13bc484d1..83bc91959b 100644 --- a/xls/modules/zstd/huffman_decoder.x +++ b/xls/modules/zstd/huffman_decoder.x @@ -40,6 +40,10 @@ enum HuffmanDecoderFSM: u3 { pub struct HuffmanDecoderStart { new_config: bool, + id: u32, + literals_last: bool, + last_stream: bool, // 4'th huffman coded stream decoding for multi_stream + // or single stream decoding } struct HuffmanDecoderState { @@ -53,6 +57,9 @@ struct HuffmanDecoderState { code_length: CodeLen[BUFF_W], decoded_literals: uN[common::SYMBOL_WIDTH][u32:8], decoded_literals_len: u4, + id: u32, + literals_last: bool, + last_stream: bool, } fn extend_buff_array(buff: CodeLen[N], buff_len: u32, array: CodeLen[M]) -> CodeLen[N] { @@ -124,14 +131,14 @@ pub proc HuffmanDecoder { data_r: chan in; done_s: chan<()> out; - decoded_literals_s: chan out; + decoded_literals_s: chan out; config ( start_r: chan in, codes_r: chan in, data_r: chan in, done_s: chan<()> out, - decoded_literals_s: chan out, + decoded_literals_s: chan out, ) { ( start_r, @@ -154,30 +161,38 @@ pub proc HuffmanDecoder { let state = if start_valid { if start.new_config { - trace_fmt!("IDLE -> AWAITING_CONFIG"); + trace_fmt!("{} -> AWAITING_CONFIG", state.fsm); + assert!(state.fsm == FSM::IDLE, "invalid_state_transition"); State { fsm: FSM::AWAITING_CONFIG, symbol_config_id: u5:0, + id: start.id, + literals_last: start.literals_last, + last_stream: start.last_stream, ..state } } else { - trace_fmt!("IDLE -> READ_DATA"); + trace_fmt!("{} -> READ_DATA", state.fsm); + assert!(state.fsm == FSM::IDLE, "invalid_state_transition"); State { fsm: FSM::READ_DATA, + id: start.id, + literals_last: start.literals_last, + last_stream: start.last_stream, ..state } } } else { state }; // wait for config - let (tok, config, config_valid) = recv_if_non_blocking( + let (tok, config) = recv_if( tok, codes_r, state.fsm == FSM::AWAITING_CONFIG, zero!() ); - let state = if config_valid { + let state = if state.fsm == FSM::AWAITING_CONFIG { let (symbol_valid, symbol_code, symbol_code_len) = for (i, (symbol_valid, symbol_code, symbol_code_len)): ( @@ -194,8 +209,12 @@ pub proc HuffmanDecoder { update(symbol_code_len, (state.symbol_config_id as u32 * u32:8) + i, config.code_length[i]), ) }((state.symbol_valid, state.symbol_code, state.symbol_code_len)); + trace_fmt!("state.symbol_config_id+1: {:#x}", state.symbol_config_id as u32 + u32:1); + trace_fmt!("SYMBOLS_N: {:#x}", SYMBOLS_N); + trace_fmt!("hcommon::PARALLEL_ACCESS_WIDTH: {:#x}", hcommon::PARALLEL_ACCESS_WIDTH); let fsm = if (state.symbol_config_id as u32 + u32:1) == (SYMBOLS_N / hcommon::PARALLEL_ACCESS_WIDTH) { - trace_fmt!("AWAITING_CONFIG -> READ_DATA"); + trace_fmt!("{} -> READ_DATA", state.fsm); + assert!(state.fsm == FSM::AWAITING_CONFIG, "invalid_state_transition"); trace_fmt!("Received codes:"); for (i, ()) in range(u32:0, SYMBOLS_N) { if symbol_valid[i] { @@ -222,7 +241,8 @@ pub proc HuffmanDecoder { ); let state = if data_valid { - trace_fmt!("READ_DATA -> DECODE"); + trace_fmt!("{} -> DECODE", state.fsm); + assert!(state.fsm == FSM::READ_DATA, "invalid_state_transition"); trace_fmt!("Received data: {:#b} (len: {})", data.data, data.data_len); State { fsm: FSM::DECODE, @@ -289,20 +309,28 @@ pub proc HuffmanDecoder { zero!() }; - let done = state.data_len == uN[BUFF_W_LOG2]:0; - send_if(tok, decoded_literals_s, do_send_literals, common::LiteralsData{ + let done = (state.data_len == uN[BUFF_W_LOG2]:0) && (state.fsm == FSM::DECODE); + let decoded_literals = common::LiteralsDataWithSync{ data: data, length: state.decoded_literals_len as common::LitLength, - last: done, - }); + last: done && state.last_stream, + id: state.id, + literals_last: state.literals_last, + }; + send_if(tok, decoded_literals_s, do_send_literals, decoded_literals); + if (do_send_literals) { + trace_fmt!("Sent decoded literals: {:#x}", decoded_literals); + } else {}; let state = if do_send_literals { let fsm = if state.data_len == uN[BUFF_W_LOG2]:0 { - trace_fmt!("DECODE -> IDLE"); + trace_fmt!("{} -> IDLE", state.fsm); FSM::IDLE } else { + trace_fmt!("{} -> DECODE", state.fsm); FSM::DECODE }; + assert!(state.fsm == FSM::DECODE, "invalid_state_transition"); State { fsm: fsm, decoded_literals_len: u4:0, @@ -347,9 +375,9 @@ fn generate_codes(data: SymbolData[8]) -> Codes { } const TEST_START = HuffmanDecoderStart[3]:[ - HuffmanDecoderStart { new_config: true }, - HuffmanDecoderStart { new_config: false }, - HuffmanDecoderStart { new_config: true }, + HuffmanDecoderStart { new_config: true, id: u32:0, literals_last: false, last_stream: true }, + HuffmanDecoderStart { new_config: false, id: u32:1, literals_last: true, last_stream: true }, + HuffmanDecoderStart { new_config: true, id: u32:0, literals_last: false, last_stream: true }, ]; // config #1 @@ -599,41 +627,55 @@ const TEST_DATA = huffman_data_preprocessor::HuffmanDataPreprocessorData[3]:[ }, ]; -const TEST_LITERALS = common::LiteralsData[7]:[ - common::LiteralsData { +const TEST_LITERALS = common::LiteralsDataWithSync[7]:[ + common::LiteralsDataWithSync { data: common::LitData:0x06B5_0002_0606_B500, length: common::LitLength:8, last: false, + id: u32:0, + literals_last: false, }, - common::LiteralsData { + common::LiteralsDataWithSync { data: common::LitData:0x0200, length: common::LitLength:2, last: true, + id: u32:0, + literals_last: false, }, - common::LiteralsData { + common::LiteralsDataWithSync { data: common::LitData:0x06B5_0002_0606_B500, length: common::LitLength:8, last: false, + id: u32:1, + literals_last: true, }, - common::LiteralsData { + common::LiteralsDataWithSync { data: common::LitData:0x0200, length: common::LitLength:2, last: true, + id: u32:1, + literals_last: true, }, - common::LiteralsData { + common::LiteralsDataWithSync { data: common::LitData:0x7AD2_8947_478A_D247, length: common::LitLength:8, last: false, + id: u32:0, + literals_last: false, }, - common::LiteralsData { + common::LiteralsDataWithSync { data: common::LitData:0x4141_D347_D28A_47D2, length: common::LitLength:8, last: false, + id: u32:0, + literals_last: false, }, - common::LiteralsData { + common::LiteralsDataWithSync { data: common::LitData:0x47D2_418A_47D2, length: common::LitLength:6, last: true, + id: u32:0, + literals_last: false, }, ]; @@ -649,14 +691,14 @@ proc HuffmanDecoder_test { data_s: chan out; done_r: chan<()> in; - decoded_literals_r: chan in; + decoded_literals_r: chan in; config (terminator_s: chan out) { let (start_s, start_r) = chan("start"); let (codes_s, codes_r) = chan("codes"); let (data_s, data_r) = chan("data"); let (done_s, done_r) = chan<()>("done"); - let (decoded_literals_s, decoded_literals_r) = chan("decoded_literals"); + let (decoded_literals_s, decoded_literals_r) = chan("decoded_literals"); spawn HuffmanDecoder( start_r, codes_r, data_r, @@ -700,7 +742,7 @@ proc HuffmanDecoder_test { (tok, codes_idx) }((tok, u32:0)); - let tok = for ((i, expected_literals), tok): ((u32, common::LiteralsData), token) in enumerate(TEST_LITERALS) { + let tok = for ((i, expected_literals), tok): ((u32, common::LiteralsDataWithSync), token) in enumerate(TEST_LITERALS) { // receive literals let (tok, literals) = recv(tok, decoded_literals_r); trace_fmt!("Received #{} literals {:#x}", i + u32:1, literals); diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index c93a736404..ad396a78c6 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -14,6 +14,7 @@ // This file contains Huffman literals decoder proc implementation. +import std; import xls.modules.zstd.common as common; import xls.modules.zstd.huffman_common as hcommon; import xls.modules.zstd.huffman_axi_reader as axi_reader; @@ -22,37 +23,90 @@ import xls.modules.zstd.huffman_data_preprocessor as data_preprocessor; import xls.modules.zstd.huffman_decoder as decoder; import xls.modules.zstd.huffman_prescan as prescan; import xls.modules.zstd.huffman_ctrl as ctrl; +import xls.modules.zstd.huffman_weights_dec as weights_dec; import xls.modules.zstd.memory.axi as axi; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.mem_reader as mem_reader; import xls.examples.ram; -pub proc HuffmanLiteralsDecoder { +pub fn WeightPreScanMetaDataSize() -> u32 { + prescan::WeightPreScanMetaDataSize() +} + +pub type HuffmanLiteralsDecoderReq = ctrl::HuffmanControlAndSequenceCtrl; +pub type HuffmanLiteralsDecoderResp = ctrl::HuffmanControlAndSequenceResp; +pub type HuffmanLiteralsDecoderStatus = ctrl::HuffmanControlAndSequenceStatus; + +pub const WEIGHTS_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; +pub const WEIGHTS_DATA_WIDTH: u32 = prescan::RAM_ACCESS_WIDTH; +pub const WEIGHTS_NUM_PARTITIONS: u32 = u32:1; +pub const PRESCAN_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; +pub const PRESCAN_DATA_WIDTH: u32 = prescan::WeightPreScanMetaDataSize(); +pub const PRESCAN_NUM_PARTITIONS: u32 = u32:1; + +pub proc HuffmanLiteralsDecoder< + AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + WEIGHTS_RAM_ADDR_WIDTH: u32 = {WEIGHTS_ADDR_WIDTH}, + WEIGHTS_RAM_DATA_WIDTH: u32 = {WEIGHTS_DATA_WIDTH}, + WEIGHTS_RAM_NUM_PARTITIONS: u32 = {WEIGHTS_NUM_PARTITIONS}, + PRESCAN_RAM_ADDR_WIDTH: u32 = {PRESCAN_ADDR_WIDTH}, + PRESCAN_RAM_DATA_WIDTH: u32 = {PRESCAN_DATA_WIDTH}, + PRESCAN_RAM_NUM_PARTITIONS: u32 = {PRESCAN_NUM_PARTITIONS}, + > { type AxiR = axi::AxiR; type AxiAr = axi::AxiAr; - type ReadReq = ram::ReadReq; - type ReadResp = ram::ReadResp; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type WeightsRamRdReq = ram::ReadReq; + type WeightsRamRdResp = ram::ReadResp; + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + type PrescanRamRdReq = ram::ReadReq; + type PrescanRamRdResp = ram::ReadResp; + type PrescanRamWrReq = ram::WriteReq; + type PrescanRamWrResp = ram::WriteResp; + + type WeightsDecReq = weights_dec::HuffmanWeightsDecoderReq; + type WeightsDecResp = weights_dec::HuffmanWeightsDecoderResp; type HuffmanAxiReaderCtrl = axi_reader::HuffmanAxiReaderCtrl; - type PrescanInternalReadReq = ram::ReadReq; - type PrescanInternalReadResp = ram::ReadResp<{prescan::WeightPreScanMetaDataSize()}>; - type PrescanInternalWriteReq = ram::WriteReq; - type PrescanInternalWriteResp = ram::WriteResp; + type Ctrl = HuffmanLiteralsDecoderReq; + type Resp = HuffmanLiteralsDecoderResp; config ( // ctrl - ctrl_r: chan in, + ctrl_r: chan in, + resp_s: chan out, // output literals - decoded_literals_s: chan out, - // AXI interface + decoded_literals_s: chan out, + // AXI interface - reverse reader axi_ar_s: chan out, axi_r_r: chan in, + // AXI interface - Huffman Jump Table decoder + jump_table_axi_ar_s: chan out, + jump_table_axi_r_r: chan in, + // AXI interface - Huffman tree description header decoder + weights_header_dec_axi_ar_s: chan out, + weights_header_dec_axi_r_r: chan in, + // AXI interface - RAW Huffman tree description decoder + weights_raw_dec_axi_ar_s: chan out, + weights_raw_dec_axi_r_r: chan in, + // AXI interface - FSE Huffman tree description decoder + weights_fse_dec_axi_ar_s: chan out, + weights_fse_dec_axi_r_r: chan in, // weight memory - ram_read_req_s: chan out, - ram_read_resp_r: chan in, - // code builder loopback - weights_pow_sum_loopback_s: chan out, - weights_pow_sum_loopback_r: chan in, + weights_ram_rd_req_s: chan out, + weights_ram_rd_resp_r: chan in, + weights_ram_wr_req_s: chan out, + weights_ram_wr_resp_r: chan in, + // prescan memory + prescan_ram_rd_req_s: chan out, + prescan_ram_rd_resp_r: chan in, + prescan_ram_wr_req_s: chan out, + prescan_ram_wr_resp_r: chan in, ) { let (prescan_start_s, prescan_start_r) = chan("prescan_start"); let (code_builder_start_s, code_builder_start_r) = chan("code_buider"); @@ -65,37 +119,75 @@ pub proc HuffmanLiteralsDecoder("lookahead_config"); let (axi_data_s, axi_data_r) = chan("axi_data"); let (preprocessed_data_s, preprocessed_data_r) = chan("preprocessed_data"); + let (weights_dec_req_s, weights_dec_req_r) = chan("weights_dec_req"); + let (weights_dec_resp_s, weights_dec_resp_r) = chan("weights_dec_resp"); + let (jump_table_mem_rd_req_s, jump_table_mem_rd_req_r) = chan("jump_table_req"); + let (jump_table_mem_rd_resp_s, jump_table_mem_rd_resp_r) = chan("jump_table_resp"); + let (weights_header_dec_mem_rd_req_s, weights_header_dec_mem_rd_req_r) = chan("weights_dec_mem_rd_req"); + let (weights_header_dec_mem_rd_resp_s, weights_header_dec_mem_rd_resp_r) = chan("weights_dec_mem_rd_resp"); + let (weights_raw_dec_mem_rd_req_s, weights_raw_dec_mem_rd_req_r) = chan("weights_dec_mem_rd_req"); + let (weights_raw_dec_mem_rd_resp_s, weights_raw_dec_mem_rd_resp_r) = chan("weights_dec_mem_rd_resp"); + let (weights_fse_dec_mem_rd_req_s, weights_fse_dec_mem_rd_req_r) = chan("weights_dec_mem_rd_req"); + let (weights_fse_dec_mem_rd_resp_s, weights_fse_dec_mem_rd_resp_r) = chan("weights_dec_mem_rd_resp"); - // prescan internal memory - let (prescan_internal_ram_write_req_s, prescan_internal_ram_write_req_r) = chan("prescan_internal_ram_write_req"); - let (prescan_internal_ram_write_resp_s, prescan_internal_ram_write_resp_r) = chan("prescan_internal_ram_write_resp"); - let (prescan_internal_ram_read_req_s, prescan_internal_ram_read_req_r) = chan("prescan_internal_ram_read_req"); - let (prescan_internal_ram_read_resp_s, prescan_internal_ram_read_resp_r) = chan("prescan_internal_ram_read_resp"); - - spawn ram::RamModel<{prescan::WeightPreScanMetaDataSize()}, prescan::RAM_SIZE, {prescan::WeightPreScanMetaDataSize()}>( - prescan_internal_ram_read_req_r, prescan_internal_ram_read_resp_s, - prescan_internal_ram_write_req_r, prescan_internal_ram_write_resp_s, - ); + // code builder loopback + let (weights_pow_sum_loopback_s, weights_pow_sum_loopback_r) = chan("weights_pow_sum_loopback"); - spawn ctrl::HuffmanControlAndSequence( - ctrl_r, + spawn ctrl::HuffmanControlAndSequence( + ctrl_r, resp_s, + weights_dec_req_s, weights_dec_resp_r, prescan_start_s, code_builder_start_s, axi_reader_ctrl_s, data_preprocess_start_s, decoder_start_s, decoder_done_r, + jump_table_mem_rd_req_s, + jump_table_mem_rd_resp_r, + ); + + spawn mem_reader::MemReader( + jump_table_mem_rd_req_r, jump_table_mem_rd_resp_s, + jump_table_axi_ar_s, jump_table_axi_r_r + ); + + spawn mem_reader::MemReader( + weights_header_dec_mem_rd_req_r, weights_header_dec_mem_rd_resp_s, + weights_header_dec_axi_ar_s, weights_header_dec_axi_r_r + ); + + spawn mem_reader::MemReader( + weights_raw_dec_mem_rd_req_r, weights_raw_dec_mem_rd_resp_s, + weights_raw_dec_axi_ar_s, weights_raw_dec_axi_r_r + ); + + spawn mem_reader::MemReader( + weights_fse_dec_mem_rd_req_r, weights_fse_dec_mem_rd_resp_s, + weights_fse_dec_axi_ar_s, weights_fse_dec_axi_r_r + ); + + spawn weights_dec::HuffmanWeightsDecoder< + AXI_ADDR_W, AXI_DATA_W, + WEIGHTS_RAM_ADDR_WIDTH, + WEIGHTS_RAM_DATA_WIDTH, + WEIGHTS_RAM_NUM_PARTITIONS, + >( + weights_dec_req_r, weights_dec_resp_s, + weights_header_dec_mem_rd_req_s, weights_header_dec_mem_rd_resp_r, + weights_raw_dec_mem_rd_req_s, weights_raw_dec_mem_rd_resp_r, + weights_fse_dec_mem_rd_req_s, weights_fse_dec_mem_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r, ); spawn prescan::WeightPreScan( prescan_start_r, - ram_read_req_s, - ram_read_resp_r, + weights_ram_rd_req_s, + weights_ram_rd_resp_r, prescan_response_s, - prescan_internal_ram_read_req_s, - prescan_internal_ram_read_resp_r, - prescan_internal_ram_write_req_s, - prescan_internal_ram_write_resp_r, + prescan_ram_rd_req_s, + prescan_ram_rd_resp_r, + prescan_ram_wr_req_s, + prescan_ram_wr_resp_r, ); spawn code_builder::WeightCodeBuilder( @@ -107,7 +199,7 @@ pub proc HuffmanLiteralsDecoder( + spawn axi_reader::HuffmanAxiReader( axi_reader_ctrl_r, axi_r_r, axi_ar_s, @@ -137,40 +229,72 @@ pub proc HuffmanLiteralsDecoder; + type Ctrl = HuffmanLiteralsDecoderReq; + type Resp = HuffmanLiteralsDecoderResp; type AxiR = axi::AxiR; type AxiAr = axi::AxiAr; - type ReadReq = ram::ReadReq; - type ReadResp = ram::ReadResp; + type WeightsRamRdReq = ram::ReadReq; + type WeightsRamRdResp = ram::ReadResp; + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + type PrescanRamRdReq = ram::ReadReq; + type PrescanRamRdResp = ram::ReadResp; + type PrescanRamWrReq = ram::WriteReq; + type PrescanRamWrResp = ram::WriteResp; config ( ctrl_r: chan in, - decoded_literals_s: chan out, + resp_s: chan out, + decoded_literals_s: chan out, axi_ar_s: chan out, axi_r_r: chan in, - ram_read_req_s: chan out, - ram_read_resp_r: chan in, - weights_pow_sum_loopback_s: chan out, - weights_pow_sum_loopback_r: chan in, + jump_table_axi_ar_s: chan out, + jump_table_axi_r_r: chan in, + weights_header_dec_axi_ar_s: chan out, + weights_header_dec_axi_r_r: chan in, + weights_raw_dec_axi_ar_s: chan out, + weights_raw_dec_axi_r_r: chan in, + weights_fse_dec_axi_ar_s: chan out, + weights_fse_dec_axi_r_r: chan in, + weights_ram_rd_req_s: chan out, + weights_ram_rd_resp_r: chan in, + weights_ram_wr_req_s: chan out, + weights_ram_wr_resp_r: chan in, + prescan_ram_rd_req_s: chan out, + prescan_ram_rd_resp_r: chan in, + prescan_ram_wr_req_s: chan out, + prescan_ram_wr_resp_r: chan in, ) { - spawn HuffmanLiteralsDecoder( - ctrl_r, + spawn HuffmanLiteralsDecoder< + INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, + INST_WEIGHTS_RAM_ADDR_WIDTH, INST_WEIGHTS_RAM_DATA_WIDTH, INST_WEIGHTS_RAM_NUM_PARTITIONS, + INST_PRESCAN_RAM_ADDR_WIDTH, INST_PRESCAN_RAM_DATA_WIDTH, INST_PRESCAN_RAM_NUM_PARTITIONS + >( + ctrl_r, resp_s, decoded_literals_s, - axi_ar_s, - axi_r_r, - ram_read_req_s, - ram_read_resp_r, - weights_pow_sum_loopback_s, - weights_pow_sum_loopback_r, + axi_ar_s, axi_r_r, + jump_table_axi_ar_s, jump_table_axi_r_r, + weights_header_dec_axi_ar_s, weights_header_dec_axi_r_r, + weights_raw_dec_axi_ar_s, weights_raw_dec_axi_r_r, + weights_fse_dec_axi_ar_s, weights_fse_dec_axi_r_r, + weights_ram_rd_req_s, weights_ram_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r, + prescan_ram_rd_req_s, prescan_ram_rd_resp_r, + prescan_ram_wr_req_s, prescan_ram_wr_resp_r, ); } @@ -179,369 +303,630 @@ proc HuffmanLiteralsDecoderInst { next (state: ()) { } } -const TEST_AXI_DATA_W = u32:32; -const TEST_AXI_ADDR_W = u32:32; -const TEST_AXI_ID_W = u32:32; - -const TEST_RAM_ADDR_WIDTH = prescan::RAM_ADDR_WIDTH; -const TEST_RAM_ACCESS_WIDTH = prescan::RAM_ACCESS_WIDTH; - -type TestCtrl = ctrl::HuffmanControlAndSequenceCtrl; -type TestAxiR = axi::AxiR; -type TestAxiAr = axi::AxiAr; - -type TestReadReq = ram::ReadReq; -type TestReadResp = ram::ReadResp; - -type TestRamEntry = uN[TEST_RAM_ACCESS_WIDTH]; - -// data for test case #0 -const TEST_CTRL_0 = TestCtrl { - base_addr: uN[TEST_AXI_ADDR_W]:0x0, - len: uN[TEST_AXI_ADDR_W]:0x8, - new_config: true -}; - -const TEST_DATA_LEN_0 = u32:64; -const TEST_DATA_0 = ( - u8:0b1_001_010_1 ++ - u8:0b01_010_1_01 ++ - u8:0b0100_001_0 ++ - u8:0b11_010_1_00 ++ - u8:0b001_010_1_0 ++ - u8:0b01_010_000 ++ - u8:0b11_1_1_0001 ++ - u8:0b001_1_010_0 -); - -// code symbol length weight -// 0b1 0x47 1 9 -// 0b001 0x41 3 7 -// 0b010 0x8A 3 7 -// 0b011 0xD2 3 7 -// 0b000001 0x45 6 4 -// 0b000010 0x7A 6 4 -// 0b000011 0x89 6 4 -// 0b000100 0x8D 6 4 -// 0b000101 0xD1 6 4 -// 0b000110 0xD3 6 4 -// 0b000111 0xDA 6 4 -// 0b000000000 0x12 9 1 -// 0b000000001 0x8F 9 1 -// 0b000000010 0xAC 9 1 -// 0b000000011 0xD4 9 1 -// 0b000000100 0xD7 9 1 -// 0b000000101 0xDB 9 1 -// 0b000000110 0xDE 9 1 -// 0b000000111 0xFE 9 1 - -const TEST_WEIGHT_MEMORY_0 = TestRamEntry[32]:[ - // x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x0x - TestRamEntry:0x_0__0__1__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x1x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x2x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x3x - TestRamEntry:0x_0__7__0__0__0__4__0__9, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x4x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x5x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x6x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__4__0__0__0__0__0, // 0x7x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__4__7__0__0__4__0__1, // 0x8x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x9x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__1__0__0__0, // 0xAx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xBx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xCx - TestRamEntry:0x_0__4__7__4__1__0__0__1, TestRamEntry:0x_0__0__4__1__0__0__1__0, // 0xDx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xEx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__1__0, // 0xFx +const TEST_AXI_RAM_DATA_W = u32:64; +const TEST_AXI_RAM_ADDR_W = u32:32; +const TEST_AXI_RAM_ID_W = u32:32; +const TEST_AXI_RAM_DEST_W = u32:32; +const TEST_AXI_RAM_DATA_DIV8 = TEST_AXI_RAM_DATA_W / u32:8; +const TEST_AXI_RAM_DATA_DIV8_W = std::clog2(TEST_AXI_RAM_DATA_DIV8); + +// Parameters for RamModels used for mocking the system memory for +// the LiteralsBlockHeaderDecoder, RawLiteralsDecoder and HuffmanLiteralsDecoder +const TEST_AXI_RAM_MODEL_DATA_WIDTH:u32 = TEST_AXI_RAM_DATA_W; +const TEST_AXI_RAM_MODEL_SIZE:u32 = u32:2048; +const TEST_AXI_RAM_MODEL_ADDR_WIDTH:u32 = std::clog2(TEST_AXI_RAM_MODEL_SIZE); +const TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE:u32 = u32:8; +const TEST_AXI_RAM_MODEL_NUM_PARTITIONS:u32 = ram::num_partitions(TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, TEST_AXI_RAM_MODEL_DATA_WIDTH); +const TEST_AXI_RAM_MODEL_BASE_ADDR:u32 = u32:0; +const TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_AXI_RAM_MODEL_INITIALIZED = true; +const TEST_AXI_RAM_MODEL_ASSERT_VALID_READ = true; +const TEST_AXI_RAM_MODEL_NUM = u32:1; + +pub const TEST_WEIGHTS_RAM_SIZE = prescan::RAM_SIZE; +pub const TEST_WEIGHTS_RAM_ADDR_WIDTH = WEIGHTS_ADDR_WIDTH; +pub const TEST_WEIGHTS_RAM_DATA_WIDTH = WEIGHTS_DATA_WIDTH; +pub const TEST_WEIGHTS_RAM_NUM_PARTITIONS = WEIGHTS_NUM_PARTITIONS; +pub const TEST_WEIGHTS_WORD_PARTITION_SIZE = TEST_WEIGHTS_RAM_DATA_WIDTH; +pub const TEST_PRESCAN_RAM_ADDR_WIDTH = PRESCAN_ADDR_WIDTH; +pub const TEST_PRESCAN_RAM_DATA_WIDTH = PRESCAN_DATA_WIDTH; +pub const TEST_PRESCAN_RAM_NUM_PARTITIONS = PRESCAN_NUM_PARTITIONS; +pub const TEST_PRESCAN_RAM_SIZE = prescan::RAM_SIZE; +pub const TEST_PRESCAN_WORD_PARTITION_SIZE = prescan::WeightPreScanMetaDataSize(); + +type TestCtrl = HuffmanLiteralsDecoderReq; +type TestResp = HuffmanLiteralsDecoderResp; +type TestAxiR = axi::AxiR; +type TestAxiAr = axi::AxiAr; + +// System bus external memory +type TestAxiRamRdReq = ram::ReadReq; +type TestAxiRamRdResp = ram::ReadResp; +type TestAxiRamWrReq = ram::WriteReq; +type TestAxiRamWrResp = ram::WriteResp; + +type TestWeightsRamRdReq = ram::ReadReq; +type TestWeightsRamRdResp = ram::ReadResp; +type TestWeightsRamWrReq = ram::WriteReq; +type TestWeightsRamWrResp = ram::WriteResp; +type TestPrescanRamRdReq = ram::ReadReq; +type TestPrescanRamRdResp = ram::ReadResp; +type TestPrescanRamWrReq = ram::WriteReq; +type TestPrescanRamWrResp = ram::WriteResp; + +type TestRamEntry = uN[TEST_WEIGHTS_RAM_DATA_WIDTH]; + +type TestAxiRamData = uN[TEST_AXI_RAM_MODEL_DATA_WIDTH]; +type TestAxiRamAddr = uN[TEST_AXI_RAM_MODEL_ADDR_WIDTH]; +type TestAxiRamMask = uN[TEST_AXI_RAM_MODEL_NUM_PARTITIONS]; + +// Data for test case +// Source: Example from RFC 8878, 4.2.2. Huffman-Coded Streams +// https://datatracker.ietf.org/doc/html/rfc8878#huffman_coded_streams +// Weights taken from Table 25 +// Bitstream fixed to encode literal sequence "0145" +// See https://www.rfc-editor.org/errata/eid8195 + +const TEST_MEMORY: TestAxiRamWrReq[7] = [ + // Literals #0 + // Length: 6 bytes + // New config, 1 Stream + // HTD Header: 0x85 (Direct representation, HTD length: 3 + HTD_header (1 byte)) + // Huffman Tree Description + // code symbol length weight + // N/A 0x03 0 0 + // 0b0000 0x04 4 1 + // 0b0001 0x05 4 1 // last weight implicit + // 0b001 0x02 3 2 + // 0b01 0x01 2 3 + // 0b1 0x00 1 4 + // 0b00001 padding + + TestAxiRamWrReq { addr: TestAxiRamAddr:0x0, data: (u16:0b00001_1_01_0000_0001 ++ u24:0x010234 ++ u8:0x85) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x0 ^ ^ ^ + // Huffman-coded stream HTD HTD Header + + // Literals #1 + // Length: 2 bytes + // Old config, 1 Stream + TestAxiRamWrReq { addr: TestAxiRamAddr:0x20, data: TestAxiRamData:0b00001_0001_0000_01_1, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x100 ^ + // Huffman-coded stream + + + // Literals #2 + // Length: 18 bytes + // New config, 4 Streams + // HTD Header: 0x85 (Direct representation, HTD length: 3 + HTD_header (1 byte)) + // Jump Table: 0x0002_0002_0002 (Stream1: 2 bytes; Stream2: 2 bytes; Stream3: 2 bytes) + // Huffman Tree Description + // code symbol length weight + // N/A 0x03 0 0 + // 0b0000 0x04 4 1 + // 0b0001 0x05 4 1 // last weight implicit + // 0b001 0x02 3 2 + // 0b01 0x01 2 3 + // 0b1 0x00 1 4 + // 0b00001 padding + TestAxiRamWrReq { addr: TestAxiRamAddr:0x40, data: (u32:0x0002_0002 ++ u24:0x010234 ++ u8:0x85) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x200 ^ ^ ^ + // Jump table HTD HTD Header + TestAxiRamWrReq { addr: TestAxiRamAddr:0x41, data: (u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0x0002) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x208 ^ ^ ^ ^ + // Huffman-coded stream #3 Huffman-coded stream #2 Huffman-coded stream #1 Jump table continued + TestAxiRamWrReq { addr: TestAxiRamAddr:0x42, data: TestAxiRamData:0b00001_1_01_0000_0001, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x210 ^ + // Huffman-coded stream #4 + + // Literals #3 + // Length: 14 bytes + // Old config, 4 Streams + // Jump Table: 0x0002_0002_0002 (Stream1: 2 bytes; Stream2: 2 bytes; Stream3: 2 bytes) + TestAxiRamWrReq { addr: TestAxiRamAddr:0x60, data: (u16:0b00001_1_01_0000_0001 ++ u48:0x0002_0002_0002) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x300 ^ ^ + // Huffman-coded stream #1 Jump table + TestAxiRamWrReq { addr: TestAxiRamAddr:0x61, data: (u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + // AXI addr: 0x308 ^ ^ ^ + // Huffman-coded stream #4 Huffman-coded stream #3 Huffman-coded stream #2 ]; -const TEST_DECODED_LITERALS_0 = common::LiteralsData[3]:[ - common::LiteralsData { - data: common::LitData:0x458A_D147_47D2_8A47, - length: common::LitLength:8, - last: false, +const TEST_CTRL: TestCtrl[4] = [ + // Literals #0 + TestCtrl { + base_addr: uN[TEST_AXI_RAM_ADDR_W]:0x0, + len: uN[TEST_AXI_RAM_ADDR_W]:0x6, + new_config: true, + multi_stream: false, + id: u32:0, + literals_last: false, }, - common::LiteralsData { - data: common::LitData:0x4141_8D47_8AD2_478A, - length: common::LitLength:8, - last: false, + + // Literals #1 + TestCtrl { + base_addr: uN[TEST_AXI_RAM_ADDR_W]:0x100, + len: uN[TEST_AXI_RAM_ADDR_W]:0x2, + new_config: false, + multi_stream: false, + id: u32:1, + literals_last: false, }, - common::LiteralsData { - data: common::LitData:0x478A_41D2_478A, - length: common::LitLength:6, - last: true, + + // Literals #2 + TestCtrl { + base_addr: uN[TEST_AXI_RAM_ADDR_W]:0x200, + len: uN[TEST_AXI_RAM_ADDR_W]:0x12, + new_config: true, + multi_stream: true, + id: u32:2, + literals_last: false, + }, + + // Literals #3 + TestCtrl { + base_addr: uN[TEST_AXI_RAM_ADDR_W]:0x300, + len: uN[TEST_AXI_RAM_ADDR_W]:0xE, + new_config: false, + multi_stream: true, + id: u32:3, + literals_last: true, }, ]; -// data for test case #1 (same config) -const TEST_CTRL_1 = TestCtrl { - base_addr: uN[TEST_AXI_ADDR_W]:0x20, - len: uN[TEST_AXI_ADDR_W]:0x4, - new_config: false -}; - -const TEST_DATA_LEN_1 = u32:32; -const TEST_DATA_1 = ( - u8:0b0010_1_010 ++ - u8:0b000_0_000 ++ - u8:0b1_1_000000 ++ - u8:0b001_011_1_1 -); - -const TEST_DECODED_LITERALS_1 = common::LiteralsData[2]:[ - common::LiteralsData { - data: common::LitData:0x47AC_1247_4747_47D2, - length: common::LitLength:8, +const TEST_DECODED_LITERALS = common::LiteralsDataWithSync[10]:[ + // Literals #0 + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: true, + id: u32:0, + literals_last: false, + }, + // Literals #1 + common::LiteralsDataWithSync { + data: common::LitData:0x0001_0405, + length: common::LitLength:4, + last: true, + id: u32:1, + literals_last: false, + }, + // Literals #2 + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: false, + id: u32:2, + literals_last: false, + }, + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: false, + id: u32:2, + literals_last: false, + }, + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, last: false, + id: u32:2, + literals_last: false, }, - common::LiteralsData { - data: common::LitData:0x8A, - length: common::LitLength:1, + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, last: true, + id: u32:2, + literals_last: false, }, -]; - -// Data for test case #2 -// Source: Example from RFC 8878, 4.2.2. Huffman-Coded Streams -// https://datatracker.ietf.org/doc/html/rfc8878#huffman_coded_streams -// Weights taken from Table 25 -// Bitstream fixed to encode literal sequence "0145" -// See https://www.rfc-editor.org/errata/eid8195 - -const TEST_CTRL_2 = TestCtrl { - base_addr: uN[TEST_AXI_ADDR_W]:0x0, - len: uN[TEST_AXI_ADDR_W]:0x2, - new_config: true -}; - -const TEST_DATA_LEN_2 = u32:16; -const TEST_DATA_2 = u64:0b00000001_00001101; - -// code symbol length weight -// N/A 0x03 0 0 -// 0b0000 0x04 4 1 -// 0b0001 0x05 4 1 -// 0b001 0x02 3 2 -// 0b01 0x01 2 3 -// 0b1 0x00 1 4 - -const TEST_WEIGHT_MEMORY_2 = TestRamEntry[32]:[ - // x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF - TestRamEntry:0x_4__3__2__0__1__1__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x0x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x1x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x2x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x3x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x4x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x5x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x6x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x7x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x8x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x9x - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xAx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xBx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xCx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xDx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xEx - TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xFx -]; - -const TEST_DECODED_LITERALS_2 = common::LiteralsData[1]:[ - common::LiteralsData { + // Literals #3 + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: false, + id: u32:3, + literals_last: true, + }, + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: false, + id: u32:3, + literals_last: true, + }, + common::LiteralsDataWithSync { + data: common::LitData:0x0504_0100, + length: common::LitLength:4, + last: false, + id: u32:3, + literals_last: true, + }, + common::LiteralsDataWithSync { data: common::LitData:0x0504_0100, length: common::LitLength:4, last: true, + id: u32:3, + literals_last: true, }, ]; + #[test_proc] proc HuffmanLiteralsDecoder_test { + type Status = HuffmanLiteralsDecoderStatus; + terminator: chan out; ctrl_s: chan out; - decoded_literals_r: chan in; - axi_ar_r: chan in; - axi_r_s: chan out; - ram_read_req_r: chan in; - ram_read_resp_s: chan out; + resp_r: chan in; + decoded_literals_r: chan in; + ram_wr_req_huffman_s : chan out; + ram_wr_resp_huffman_r : chan in; + ram_wr_req_jump_table_s : chan out; + ram_wr_resp_jump_table_r : chan in; + ram_wr_req_huffman_weights_header_s : chan out; + ram_wr_resp_huffman_weights_header_r : chan in; + ram_wr_req_huffman_weights_raw_s : chan out; + ram_wr_resp_huffman_weights_raw_r : chan in; + ram_wr_req_huffman_weights_fse_s : chan out; + ram_wr_resp_huffman_weights_fse_r : chan in; config (terminator: chan out) { let (ctrl_s, ctrl_r) = chan("ctrl"); - let (decoded_literals_s, decoded_literals_r) = chan("decoded_literals"); + let (resp_s, resp_r) = chan("resp"); + let (decoded_literals_s, decoded_literals_r) = chan("decoded_literals"); let (axi_ar_s, axi_ar_r) = chan("axi_ar"); let (axi_r_s, axi_r_r) = chan("axi_r"); - let (ram_read_req_s, ram_read_req_r) = chan("ram_read_req"); - let (ram_read_resp_s, ram_read_resp_r) = chan("ram_read_resp"); - let (weights_pow_sum_loopback_s, weights_pow_sum_loopback_r) = chan("weights_pow_sum_loopback"); + let (jump_table_axi_ar_s, jump_table_axi_ar_r) = chan("jump_table_axi_ar"); + let (jump_table_axi_r_s, jump_table_axi_r_r) = chan("jump_table_axi_r"); + let (weights_header_dec_axi_ar_s, weights_header_dec_axi_ar_r) = chan("weights_header_dec_axi_ar"); + let (weights_header_dec_axi_r_s, weights_header_dec_axi_r_r) = chan("weights_header_dec_axi_r"); + let (weights_raw_dec_axi_ar_s, weights_raw_dec_axi_ar_r) = chan("weights_raw_dec_axi_ar"); + let (weights_raw_dec_axi_r_s, weights_raw_dec_axi_r_r) = chan("weights_raw_dec_axi_r"); + let (weights_fse_dec_axi_ar_s, weights_fse_dec_axi_ar_r) = chan("weights_fse_dec_axi_ar"); + let (weights_fse_dec_axi_r_s, weights_fse_dec_axi_r_r) = chan("weights_fse_dec_axi_r"); + + // weights internal memory + let (weights_ram_rd_req_s, weights_ram_rd_req_r) = chan("weights_ram_rd_req"); + let (weights_ram_rd_resp_s, weights_ram_rd_resp_r) = chan("weights_ram_rd_resp"); + let (weights_ram_wr_req_s, weights_ram_wr_req_r) = chan("weights_ram_wr_req"); + let (weights_ram_wr_resp_s, weights_ram_wr_resp_r) = chan("weights_ram_wr_resp"); - spawn HuffmanLiteralsDecoder( - ctrl_r, decoded_literals_s, + // prescan internal memory + let (prescan_ram_wr_req_s, prescan_ram_wr_req_r) = chan("prescan_ram_wr_req"); + let (prescan_ram_wr_resp_s, prescan_ram_wr_resp_r) = chan("prescan_ram_wr_resp"); + let (prescan_ram_rd_req_s, prescan_ram_rd_req_r) = chan("prescan_ram_rd_req"); + let (prescan_ram_rd_resp_s, prescan_ram_rd_resp_r) = chan("prescan_ram_rd_resp"); + + spawn HuffmanLiteralsDecoder< + TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_DEST_W, + TEST_WEIGHTS_RAM_ADDR_WIDTH, TEST_WEIGHTS_RAM_DATA_WIDTH, TEST_WEIGHTS_RAM_NUM_PARTITIONS, + TEST_PRESCAN_RAM_ADDR_WIDTH, TEST_PRESCAN_RAM_DATA_WIDTH, TEST_PRESCAN_RAM_NUM_PARTITIONS + >( + ctrl_r, resp_s, decoded_literals_s, axi_ar_s, axi_r_r, - ram_read_req_s, ram_read_resp_r, - weights_pow_sum_loopback_s, weights_pow_sum_loopback_r, + jump_table_axi_ar_s, jump_table_axi_r_r, + weights_header_dec_axi_ar_s, weights_header_dec_axi_r_r, + weights_raw_dec_axi_ar_s, weights_raw_dec_axi_r_r, + weights_fse_dec_axi_ar_s, weights_fse_dec_axi_r_r, + weights_ram_rd_req_s, weights_ram_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r, + prescan_ram_rd_req_s, prescan_ram_rd_resp_r, + prescan_ram_wr_req_s, prescan_ram_wr_resp_r, ); - ( - terminator, - ctrl_s, decoded_literals_r, - axi_ar_r, axi_r_s, - ram_read_req_r, ram_read_resp_s, - ) - } - - init { } - - next (state: ()) { - let tok = join(); + // Mock RAM for HuffmanLiteralsDecoder MemReader + let (ram_rd_req_huffman_s, ram_rd_req_huffman_r) = chan("ram_rd_req_huffman"); + let (ram_rd_resp_huffman_s, ram_rd_resp_huffman_r) = chan("ram_rd_resp_huffman"); + let (ram_wr_req_huffman_s, ram_wr_req_huffman_r) = chan("ram_wr_req_huffman"); + let (ram_wr_resp_huffman_s, ram_wr_resp_huffman_r) = chan("ram_wr_resp_huffman"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_r, ram_rd_resp_huffman_s, ram_wr_req_huffman_r, ram_wr_resp_huffman_s + ); - trace_fmt!("Test Case #1"); - // send ctrl - let tok = send(tok, ctrl_s, TEST_CTRL_0); - trace_fmt!("Sent #1 ctrl {:#x}", TEST_CTRL_0); + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + axi_ar_r, axi_r_s, + ram_rd_req_huffman_s, ram_rd_resp_huffman_r + ); - // receive RAM read requests and send responses - trace_fmt!("Sending weight memory content"); - let tok = for (_, tok): (u32, token) in range(u32:0, u32:2) { - for (i, tok):(u32, token) in range(u32:0, array_size(TEST_WEIGHT_MEMORY_0)) { - let (tok, ram_read_req) = recv(tok, ram_read_req_r); - trace_fmt!("Received #{} ReadReq {:#x}", i + u32:1, ram_read_req); + // Mock RAM for Huffman Jump Table decoder MemReader + let (ram_rd_req_jump_table_s, ram_rd_req_jump_table_r) = chan("ram_rd_req_jump_table"); + let (ram_rd_resp_jump_table_s, ram_rd_resp_jump_table_r) = chan("ram_rd_resp_jump_table"); + let (ram_wr_req_jump_table_s, ram_wr_req_jump_table_r) = chan("ram_wr_req_jump_table"); + let (ram_wr_resp_jump_table_s, ram_wr_resp_jump_table_r) = chan("ram_wr_resp_jump_table"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_jump_table_r, ram_rd_resp_jump_table_s, ram_wr_req_jump_table_r, ram_wr_resp_jump_table_s + ); - let read_resp = TestReadResp { - data: TEST_WEIGHT_MEMORY_0[ram_read_req.addr] as u32, - }; + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + jump_table_axi_ar_r, jump_table_axi_r_s, + ram_rd_req_jump_table_s, ram_rd_resp_jump_table_r + ); - let tok = send(tok, ram_read_resp_s, read_resp); - trace_fmt!("Sent #{} ReadResp {:#x}", i + u32:1, read_resp); + // Mock RAM for HuffmanWeights header decoder MemReader + let (ram_rd_req_huffman_weights_header_s, ram_rd_req_huffman_weights_header_r) = chan("ram_rd_req_huffman_weights_header"); + let (ram_rd_resp_huffman_weights_header_s, ram_rd_resp_huffman_weights_header_r) = chan("ram_rd_resp_huffman_weights_header"); + let (ram_wr_req_huffman_weights_header_s, ram_wr_req_huffman_weights_header_r) = chan("ram_wr_req_huffman_weights_header"); + let (ram_wr_resp_huffman_weights_header_s, ram_wr_resp_huffman_weights_header_r) = chan("ram_wr_resp_huffman_weights_header"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_header_r, ram_rd_resp_huffman_weights_header_s, ram_wr_req_huffman_weights_header_r, ram_wr_resp_huffman_weights_header_s + ); - tok - }(tok) - }(tok); + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + weights_header_dec_axi_ar_r, weights_header_dec_axi_r_s, + ram_rd_req_huffman_weights_header_s, ram_rd_resp_huffman_weights_header_r + ); - // receive Axi requests and send responses - trace_fmt!("Sending data from AXI"); - const AXI_READS_NUM = (TEST_DATA_LEN_0 + u32:7) / u32:8; - let tok = for (i, tok):(u32, token) in range(u32:0, AXI_READS_NUM) { - let expected_axi_ar = TestAxiAr { - addr: TEST_CTRL_0.base_addr + (AXI_READS_NUM - u32:1 - i) as uN[TEST_AXI_ADDR_W], - ..zero!() - }; - let (tok, axi_ar) = recv(tok, axi_ar_r); - trace_fmt!("Received #{} AxiAr {:#x}", i + u32:1, axi_ar); - assert_eq(expected_axi_ar, axi_ar); - - let axi_r = TestAxiR { - id: axi_ar.id, - data: (TEST_DATA_0 >> (u32:8 * i)) as u32, - resp: axi::AxiReadResp::OKAY, - last: i == (AXI_READS_NUM - u32:1), - }; - - let tok = send(tok, axi_r_s, axi_r); - trace_fmt!("Sent #{} AxiR {:#x}", i + u32:1, axi_r); + // Mock RAM for HuffmanWeights raw decoder MemReader + let (ram_rd_req_huffman_weights_raw_s, ram_rd_req_huffman_weights_raw_r) = chan("ram_rd_req_huffman_weights_raw"); + let (ram_rd_resp_huffman_weights_raw_s, ram_rd_resp_huffman_weights_raw_r) = chan("ram_rd_resp_huffman_weights_raw"); + let (ram_wr_req_huffman_weights_raw_s, ram_wr_req_huffman_weights_raw_r) = chan("ram_wr_req_huffman_weights_raw"); + let (ram_wr_resp_huffman_weights_raw_s, ram_wr_resp_huffman_weights_raw_r) = chan("ram_wr_resp_huffman_weights_raw"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_raw_r, ram_rd_resp_huffman_weights_raw_s, ram_wr_req_huffman_weights_raw_r, ram_wr_resp_huffman_weights_raw_s + ); - tok - }(tok); + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + weights_raw_dec_axi_ar_r, weights_raw_dec_axi_r_s, + ram_rd_req_huffman_weights_raw_s, ram_rd_resp_huffman_weights_raw_r + ); - // receive decoded literals - let tok = for ((i, test_decoded_literals), tok):((u32, common::LiteralsData), token) in enumerate(TEST_DECODED_LITERALS_0) { - let (tok, decoded_literals) = recv(tok, decoded_literals_r); - trace_fmt!("Received #{} decoded literals {:#x}", i + u32:1, decoded_literals); - assert_eq(test_decoded_literals, decoded_literals); - tok - }(tok); + // Mock RAM for HuffmanWeights fse decoder MemReader + let (ram_rd_req_huffman_weights_fse_s, ram_rd_req_huffman_weights_fse_r) = chan("ram_rd_req_huffman_weights_fse"); + let (ram_rd_resp_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r) = chan("ram_rd_resp_huffman_weights_fse"); + let (ram_wr_req_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r) = chan("ram_wr_req_huffman_weights_fse"); + let (ram_wr_resp_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r) = chan("ram_wr_resp_huffman_weights_fse"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_fse_r, ram_rd_resp_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r, ram_wr_resp_huffman_weights_fse_s + ); - trace_fmt!("Test Case #2"); - // send ctrl - let tok = send(tok, ctrl_s, TEST_CTRL_1); - trace_fmt!("Sent #2 ctrl {:#x}", TEST_CTRL_1); - - // receive Axi requests and send responses - trace_fmt!("Sending data from AXI"); - const AXI_READS_NUM = (TEST_DATA_LEN_1 + u32:7) / u32:8; - let tok = for (i, tok):(u32, token) in range(u32:0, AXI_READS_NUM) { - let expected_axi_ar = TestAxiAr { - addr: TEST_CTRL_1.base_addr + (AXI_READS_NUM - u32:1 - i) as uN[TEST_AXI_ADDR_W], - ..zero!() - }; - let (tok, axi_ar) = recv(tok, axi_ar_r); - trace_fmt!("Received #{} AxiAr {:#x}", i + u32:1, axi_ar); - assert_eq(expected_axi_ar, axi_ar); - - let axi_r = TestAxiR { - id: axi_ar.id, - data: (TEST_DATA_1 >> (u32:8 * i)) as u32, - resp: axi::AxiReadResp::OKAY, - last: i == (AXI_READS_NUM - u32:1), - }; - - let tok = send(tok, axi_r_s, axi_r); - trace_fmt!("Sent #{} AxiR {:#x}", i + u32:1, axi_r); + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + weights_fse_dec_axi_ar_r, weights_fse_dec_axi_r_s, + ram_rd_req_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r + ); - tok - }(tok); + spawn ram::RamModel< + TEST_WEIGHTS_RAM_DATA_WIDTH, TEST_WEIGHTS_RAM_SIZE, TEST_WEIGHTS_WORD_PARTITION_SIZE + >( + weights_ram_rd_req_r, weights_ram_rd_resp_s, + weights_ram_wr_req_r, weights_ram_wr_resp_s, + ); - // receive decoded literals - let tok = for ((i, test_decoded_literals), tok):((u32, common::LiteralsData), token) in enumerate(TEST_DECODED_LITERALS_1) { - let (tok, decoded_literals) = recv(tok, decoded_literals_r); - trace_fmt!("Received #{} decoded literals {:#x}", i + u32:1, decoded_literals); - assert_eq(test_decoded_literals, decoded_literals); - tok - }(tok); + spawn ram::RamModel< + TEST_PRESCAN_RAM_DATA_WIDTH, TEST_PRESCAN_RAM_SIZE, TEST_PRESCAN_WORD_PARTITION_SIZE + >( + prescan_ram_rd_req_r, prescan_ram_rd_resp_s, + prescan_ram_wr_req_r, prescan_ram_wr_resp_s, + ); - trace_fmt!("Test Case #3"); - // send ctrl - let tok = send(tok, ctrl_s, TEST_CTRL_2); - trace_fmt!("Sent #3 ctrl {:#x}", TEST_CTRL_2); + ( + terminator, + ctrl_s, resp_r, decoded_literals_r, + ram_wr_req_huffman_s, ram_wr_resp_huffman_r, + ram_wr_req_jump_table_s, ram_wr_resp_jump_table_r, + ram_wr_req_huffman_weights_header_s, ram_wr_resp_huffman_weights_header_r, + ram_wr_req_huffman_weights_raw_s, ram_wr_resp_huffman_weights_raw_r, + ram_wr_req_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r + ) - // receive RAM read requests and send responses - trace_fmt!("Sending weight memory content"); - let tok = for (_, tok): (u32, token) in range(u32:0, u32:2) { - for (i, tok):(u32, token) in range(u32:0, array_size(TEST_WEIGHT_MEMORY_2)) { - let (tok, ram_read_req) = recv(tok, ram_read_req_r); - trace_fmt!("Received #{} ReadReq {:#x}", i + u32:1, ram_read_req); + } - let read_resp = TestReadResp { - data: TEST_WEIGHT_MEMORY_2[ram_read_req.addr] as u32, - }; + init { } - let tok = send(tok, ram_read_resp_s, read_resp); - trace_fmt!("Sent #{} ReadResp {:#x}", i + u32:1, read_resp); + next (state: ()) { + let tok = join(); - tok - }(tok) + trace_fmt!("Filling system memory mock"); + let tok = for ((i, mem_req), tok):((u32, TestAxiRamWrReq), token) in enumerate(TEST_MEMORY) { + trace_fmt!("Sent memory write request #{}: {:#x}", i + u32:1, mem_req); + let tok = send(tok, ram_wr_req_huffman_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_r); + let tok = send(tok, ram_wr_req_jump_table_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_jump_table_r); + let tok = send(tok, ram_wr_req_huffman_weights_header_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_header_r); + let tok = send(tok, ram_wr_req_huffman_weights_raw_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_raw_r); + let tok = send(tok, ram_wr_req_huffman_weights_fse_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_r); + tok }(tok); + trace_fmt!("Filling system memory mock done"); - // receive Axi requests and send responses - trace_fmt!("Sending data from AXI"); - const AXI_READS_NUM = (TEST_DATA_LEN_2 + u32:7) / u32:8; - let tok = for (i, tok):(u32, token) in range(u32:0, AXI_READS_NUM) { - let expected_axi_ar = TestAxiAr { - addr: TEST_CTRL_2.base_addr + (AXI_READS_NUM - u32:1 - i) as uN[TEST_AXI_ADDR_W], - ..zero!() - }; - let (tok, axi_ar) = recv(tok, axi_ar_r); - trace_fmt!("Received #{} AxiAr {:#x}", i + u32:1, axi_ar); - assert_eq(expected_axi_ar, axi_ar); - - let axi_r = TestAxiR { - id: axi_ar.id, - data: (TEST_DATA_2 >> (u32:8 * i)) as u32, - resp: axi::AxiReadResp::OKAY, - last: i == (AXI_READS_NUM - u32:1), - }; - - let tok = send(tok, axi_r_s, axi_r); - trace_fmt!("Sent #{} AxiR {:#x}", i + u32:1, axi_r); - + // Send Huffman Literals decoding requests + let tok = for ((i, ctrl_req), tok):((u32, TestCtrl), token) in enumerate(TEST_CTRL) { + let tok = send(tok, ctrl_s, ctrl_req); + trace_fmt!("Sent #{} ctrl {:#x}", i + u32:1, ctrl_req); tok }(tok); // receive decoded literals - let tok = for ((i, test_decoded_literals), tok):((u32, common::LiteralsData), token) in enumerate(TEST_DECODED_LITERALS_2) { + let tok = for ((i, expected_decoded_literals), tok):((u32, common::LiteralsDataWithSync), token) in enumerate(TEST_DECODED_LITERALS) { + trace_fmt!("Waiting for #{} decoded literals", i + u32:1); let (tok, decoded_literals) = recv(tok, decoded_literals_r); trace_fmt!("Received #{} decoded literals {:#x}", i + u32:1, decoded_literals); - assert_eq(test_decoded_literals, decoded_literals); + assert_eq(expected_decoded_literals, decoded_literals); + + if (decoded_literals.last) { trace_fmt!("Waiting for #{} decoding response", i + u32:1); } else {}; + let (tok, resp) = recv_if(tok, resp_r, decoded_literals.last, zero!()); + if (decoded_literals.last) { trace_fmt!("Received #{} decoding response {:#x}", i + u32:1, resp); } else {}; + assert_eq(TestResp {status: Status::OKAY}, resp); + tok }(tok); send(tok, terminator, true); } } + +// TODO: implement tests with the following Huffman Tree +//const TEST_DATA_LEN_0 = u32:64; +//const TEST_DATA_0 = ( +// u8:0b001_1_010_0 ++ // 0x34 <- last byte in the memory +// u8:0b11_1_1_0001 ++ // 0xF1 +// u8:0b01_010_000 ++ // 0x50 +// u8:0b001_010_1_0 ++ // 0x2A +// u8:0b11_010_1_00 ++ // 0xD4 +// u8:0b0100_001_0 ++ // 0x42 +// u8:0b01_010_1_01 ++ // 0x55 +// u8:0b1_001_010_1 // 0x95 <- first byte in the memory +//); +// +//// code symbol length weight +//// 0b1 0x47 1 9 +//// 0b001 0x41 3 7 +//// 0b010 0x8A 3 7 +//// 0b011 0xD2 3 7 +//// 0b000001 0x45 6 4 +//// 0b000010 0x7A 6 4 +//// 0b000011 0x89 6 4 +//// 0b000100 0x8D 6 4 +//// 0b000101 0xD1 6 4 +//// 0b000110 0xD3 6 4 +//// 0b000111 0xDA 6 4 +//// 0b000000000 0x12 9 1 +//// 0b000000001 0x8F 9 1 +//// 0b000000010 0xAC 9 1 +//// 0b000000011 0xD4 9 1 +//// 0b000000100 0xD7 9 1 +//// 0b000000101 0xDB 9 1 +//// 0b000000110 0xDE 9 1 +//// 0b000000111 0xFE 9 1 +// +//const TEST_WEIGHT_MEMORY_0 = TestRamEntry[32]:[ +// // x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x0x +// TestRamEntry:0x_0__0__1__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x1x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x2x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x3x +// TestRamEntry:0x_0__7__0__0__0__4__0__9, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x4x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x5x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x6x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__4__0__0__0__0__0, // 0x7x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__4__7__0__0__4__0__1, // 0x8x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0x9x +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__1__0__0__0, // 0xAx +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xBx +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xCx +// TestRamEntry:0x_0__4__7__4__1__0__0__1, TestRamEntry:0x_0__0__4__1__0__0__1__0, // 0xDx +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__0__0, // 0xEx +// TestRamEntry:0x_0__0__0__0__0__0__0__0, TestRamEntry:0x_0__0__0__0__0__0__1__0, // 0xFx +//]; +// +//const TEST_DECODED_LITERALS_0 = common::LiteralsDataWithSync[3]:[ +// common::LiteralsDataWithSync { +// data: common::LitData:0x458A_D147_47D2_8A47, +// length: common::LitLength:8, +// last: false, +// id: u32:0, +// literals_last: false, +// }, +// common::LiteralsDataWithSync { +// data: common::LitData:0x4141_8D47_8AD2_478A, +// length: common::LitLength:8, +// last: false, +// id: u32:0, +// literals_last: false, +// }, +// common::LiteralsDataWithSync { +// data: common::LitData:0x478A_41D2_478A, +// length: common::LitLength:6, +// last: true, +// id: u32:0, +// literals_last: false, +// }, +//]; +// +//// data for test case #1 (same config) +//const TEST_CTRL_1 = TestCtrl { +// base_addr: uN[TEST_AXI_RAM_ADDR_W]:0x20, +// len: uN[TEST_AXI_RAM_ADDR_W]:0x4, +// new_config: false, +// multi_stream: false, +// id: u32:1, +// literals_last: true, +//}; +// +//const TEST_DATA_LEN_1 = u32:32; +//const TEST_DATA_1 = ( +// u8:0b001_011_1_1 ++ // 0x2F <- last byte in the memory +// u8:0b1_1_000000 ++ // 0xC0 +// u8:0b000_0_000 ++ // 0x00 +// u8:0b0010_1_010 // 0x2A <- first byte in the memory +//); +// +//const TEST_DECODED_LITERALS_1 = common::LiteralsDataWithSync[2]:[ +// common::LiteralsDataWithSync { +// data: common::LitData:0x47AC_1247_4747_47D2, +// length: common::LitLength:8, +// last: false, +// id: u32:1, +// literals_last: true, +// }, +// common::LiteralsDataWithSync { +// data: common::LitData:0x8A, +// length: common::LitLength:1, +// last: true, +// id: u32:1, +// literals_last: true, +// }, +//]; + diff --git a/xls/modules/zstd/huffman_weights_dec.x b/xls/modules/zstd/huffman_weights_dec.x new file mode 100644 index 0000000000..4dd04173b8 --- /dev/null +++ b/xls/modules/zstd/huffman_weights_dec.x @@ -0,0 +1,1016 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import std; + +import xls.examples.ram as ram; +import xls.modules.zstd.huffman_prescan as huffman_prescan; +import xls.modules.zstd.memory.axi as axi; +import xls.modules.zstd.memory.axi_ram as axi_ram; +import xls.modules.zstd.memory.mem_reader as mem_reader; +import xls.modules.zstd.ram_mux as ram_mux; + +struct HuffmanRawWeightsDecoderReq { + addr: uN[AXI_ADDR_W], + n_symbols: u8, +} + +enum HuffmanRawWeightsDecoderStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +struct HuffmanRawWeightsDecoderResp { + status: HuffmanRawWeightsDecoderStatus, +} + +enum HuffmanRawWeightsDecoderFSM : u2 { + IDLE = 0, + DECODING = 1, + FILL_ZERO = 2, + RESP = 3, +} + +struct HuffmanRawWeightsDecoderState< + AXI_ADDR_W: u32, AXI_DATA_W: u32, + WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, + BUFF_LEN: u32 = {AXI_DATA_W + WEIGHTS_RAM_DATA_W}, + BUFF_LEN_LOG2: u32 = {std::clog2(BUFF_LEN + u32:1)}, +> { + fsm: HuffmanRawWeightsDecoderFSM, + req: HuffmanRawWeightsDecoderReq, + data_decoded: uN[AXI_ADDR_W], + ram_addr: uN[WEIGHTS_RAM_ADDR_W], + buffer: uN[BUFF_LEN], + buffer_len: uN[BUFF_LEN_LOG2], + ram_wr_resp_to_handle: u4, + sum: u32, // The sum of 2^(weight-1) from HTD +} + +proc HuffmanRawWeightsDecoder< + AXI_ADDR_W: u32, AXI_DATA_W: u32, + WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, + WEIGHTS_RAM_NUM_PARTITIONS: u32, + BUFF_LEN: u32 = {AXI_DATA_W + WEIGHTS_RAM_DATA_W}, + BUFF_LEN_LOG2: u32 = {std::clog2(BUFF_LEN + u32:1)}, +> { + type Req = HuffmanRawWeightsDecoderReq; + type Resp = HuffmanRawWeightsDecoderResp; + type Status = HuffmanRawWeightsDecoderStatus; + type FSM = HuffmanRawWeightsDecoderFSM; + type State = HuffmanRawWeightsDecoderState< + AXI_ADDR_W, AXI_DATA_W, WEIGHTS_RAM_ADDR_W, WEIGHTS_RAM_DATA_W, + BUFF_LEN, BUFF_LEN_LOG2, + >; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + + // Control + req_r: chan in; + resp_s: chan out; + + // MemReader interface for fetching Huffman Tree Description + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; + + weights_ram_wr_req_s: chan out; + weights_ram_wr_resp_r: chan in; + + init { + zero!() + } + + config( + // Control + req_r: chan in, + resp_s: chan out, + + // MemReader interface for fetching Huffman Tree Description + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, + + // RAM Write interface (goes to Huffman Weights Memory) + weights_ram_wr_req_s: chan out, + weights_ram_wr_resp_r: chan in, + ) { + + ( + req_r, resp_s, + mem_rd_req_s, mem_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r + ) + } + + next (state: State) { + let tok = join(); + + // [IDLE] + let (tok, req, req_valid) = recv_if_non_blocking(join(), req_r, state.fsm == FSM::IDLE, zero!()); + + // Fetch Data + let mem_rd_req = MemReaderReq { + addr: req.addr + uN[AXI_ADDR_W]:1, // skip header + length: ((req.n_symbols + u8:1) >> u32:1) as uN[AXI_ADDR_W], // ceil(number_of_symbols/2) + }; + let tok = send_if(tok, mem_rd_req_s, req_valid, mem_rd_req); + + // [DECODING] + let buffer = state.buffer; + let buffer_len = state.buffer_len; + + // Buffer AXI data + let do_recv_data = state.fsm == FSM::DECODING && buffer_len < (WEIGHTS_RAM_DATA_W as uN[BUFF_LEN_LOG2]); + let (tok, mem_rd_resp, mem_rd_resp_valid) = recv_if_non_blocking(tok, mem_rd_resp_r, do_recv_data, zero!()); + if do_recv_data && mem_rd_resp_valid { + trace_fmt!("[RAW] Received MemReader response {:#x}", mem_rd_resp); + } else {}; + + // FIXME: support injecting the last implicit weight for Huffman Tree Descriptions larger + // than a single bus width + // + // ^ This is partially done with saving the sum calculated below in the state. + // When the last mem_reader packet is received (received the last chunk of HTD) + // We should calculate the final sum and use it to calculate the `last_weight` of the HTD + // and put it in a correct spot in the `weights` array + + // Calculate the last weight by summing 2^(weight - 1) + // for each weight read from the HTD (excluding 0's) + // The resulting sum must be subtracted from the next power of 2 after the resulting sum. + // The result is the weight of the last literal. + const MAX_WEIGHTS_IN_PACKET = AXI_DATA_W >> u32:2; + let weights = mem_rd_resp.data as u4[MAX_WEIGHTS_IN_PACKET]; + let sum = for (i, sum): (u32, u32) in u32:0..MAX_WEIGHTS_IN_PACKET { + if (weights[i] != u4:0) { + sum + (u32:1 << (weights[i] - u4:1)) + } else { + sum + } + } (state.sum); + + let state = if (mem_rd_resp_valid) { + State { + sum: sum, + ..state + } + } else { + state + }; + + let next_power = u32:1 << std::clog2(state.sum); + let last_weight = (next_power - state.sum) as u4; + + // It is required to change the ordering of the weights. + // Huffman literals decoder expects the weight of the first symbol + // as the most significant nibble at the most significant byte + // in the first cell of the WeightsMemory. + + // Inject the last weight, take into the acount the reverse + let weights = if (state.req.n_symbols > u8:0 && (mem_rd_resp_valid && mem_rd_resp.last)) { + trace_fmt!("[RAW] The sum of weight's powers of 2's: {}", state.sum); + trace_fmt!("[RAW] The last weight: {}", last_weight); + trace_fmt!("[RAW] Injected {:#x} into weights[{}]", last_weight, MAX_WEIGHTS_IN_PACKET as u8 - state.req.n_symbols); + update(weights, (MAX_WEIGHTS_IN_PACKET as u8 - (state.req.n_symbols % MAX_WEIGHTS_IN_PACKET as u8)), last_weight) + } else { + weights + }; + + let reversed_weights = match(AXI_DATA_W) { + u32:32 => ( + weights[7] ++ weights[6] ++ weights[5] ++ weights[4] ++ + weights[3] ++ weights[2] ++ weights[1] ++ weights[0] + ) as uN[AXI_DATA_W], + u32:64 => ( + weights[15] ++ weights[14] ++ weights[13] ++ weights[12] ++ + weights[11] ++ weights[10] ++ weights[9] ++ weights[8] ++ + weights[7] ++ weights[6] ++ weights[5] ++ weights[4] ++ + weights[3] ++ weights[2] ++ weights[1] ++ weights[0] + ) as uN[AXI_DATA_W], + _ => fail!("unsupported_axi_data_width", uN[AXI_DATA_W]:0), + }; + //trace_fmt!("[RAW] Reversed weights: {:#x}", reversed_weights); + //trace_fmt!("[RAW] BUFF_LEN: {:#x}", BUFF_LEN); + //trace_fmt!("[RAW] WEIGHTS_RAM_DATA_W: {:#x}", WEIGHTS_RAM_DATA_W); + //trace_fmt!("[RAW] AXI_DATA_W: {:#x}", AXI_DATA_W); + //trace_fmt!("[RAW] buffer_len: {:#x}", buffer_len); + + if do_recv_data && mem_rd_resp_valid { + trace_fmt!("[RAW] Weights: {:#x}", weights); + } else {}; + + let (buffer, buffer_len) = if do_recv_data && mem_rd_resp_valid { + //trace_fmt!("[RAW] shift: {:#x}", BUFF_LEN - AXI_DATA_W - buffer_len as u32); + ( + buffer | ((reversed_weights as uN[BUFF_LEN] << (BUFF_LEN - AXI_DATA_W - buffer_len as u32))), + buffer_len + (AXI_DATA_W as uN[BUFF_LEN_LOG2]), + ) + } else { + ( + buffer, + buffer_len, + ) + }; + // Send to RAM + let do_send_data = state.fsm == FSM::DECODING && buffer_len >= (WEIGHTS_RAM_DATA_W as uN[BUFF_LEN_LOG2]); + let weights_ram_wr_req = WeightsRamWrReq { + addr: state.ram_addr, + data: buffer[-(WEIGHTS_RAM_DATA_W as s32):] as uN[WEIGHTS_RAM_DATA_W], + mask: !uN[WEIGHTS_RAM_NUM_PARTITIONS]:0, + }; + let tok = send_if(tok, weights_ram_wr_req_s, do_send_data, weights_ram_wr_req); + if do_send_data { + trace_fmt!("[RAW] Buffer length: {}", buffer_len); + trace_fmt!("[RAW] Sent RAM write request {:#x}", weights_ram_wr_req); + } else {}; + + let (buffer, buffer_len, data_decoded) = if do_send_data { + ( + buffer << WEIGHTS_RAM_DATA_W, + buffer_len - (WEIGHTS_RAM_DATA_W as uN[BUFF_LEN_LOG2]), + WEIGHTS_RAM_DATA_W as uN[AXI_ADDR_W], + ) + } else { + ( + buffer, + buffer_len, + uN[AXI_ADDR_W]:0, + ) + }; + + // [FILL_ZERO] + let weights_ram_wr_req = WeightsRamWrReq { + data: uN[WEIGHTS_RAM_DATA_W]:0, + addr: state.ram_addr, + mask: !uN[WEIGHTS_RAM_NUM_PARTITIONS]:0, + }; + let rok = send_if(tok, weights_ram_wr_req_s, state.fsm == FSM::FILL_ZERO, weights_ram_wr_req); + + // [RESP] + let tok = send_if(tok, resp_s, state.fsm == FSM::RESP, zero!()); + + // Update state + let ram_wr_resp_to_handle = state.ram_wr_resp_to_handle + do_send_data as u4 + (state.fsm == FSM::FILL_ZERO) as u4; + let (tok, _, weights_ram_wr_resp_valid) = recv_if_non_blocking(tok, weights_ram_wr_resp_r, ram_wr_resp_to_handle > u4:0, zero!()); + let state = if weights_ram_wr_resp_valid { + State { + ram_wr_resp_to_handle: ram_wr_resp_to_handle - u4:1, + ..state + } + } else { + State { + ram_wr_resp_to_handle: ram_wr_resp_to_handle, + ..state + } + }; + + match state.fsm { + FSM::IDLE => { + if req_valid { + trace_fmt!("[RAW] Received decoding request {:#x}", req); + trace_fmt!("[RAW] Sent MemReader request {:#x}", mem_rd_req); + State { + fsm: FSM::DECODING, + req: req, + ..zero!() + } + } else { + state + } + }, + FSM::DECODING => { + let data_to_be_decoded = uN[AXI_ADDR_W]:8 * (((state.req.n_symbols as uN[AXI_ADDR_W] + uN[AXI_ADDR_W]:1) >> u32:1)); + trace_fmt!("[RAW] Decoded {} / {}", state.data_decoded + data_decoded, data_to_be_decoded); + trace_fmt!("[RAW] Buffer {:#x}", state.buffer); + if state.data_decoded + data_decoded < data_to_be_decoded { + State { + data_decoded: state.data_decoded + data_decoded, + ram_addr: state.ram_addr + (data_decoded / WEIGHTS_RAM_DATA_W as uN[AXI_ADDR_W]) as uN[WEIGHTS_RAM_ADDR_W], + buffer: buffer, + buffer_len: buffer_len, + ..state + } + } else { + State { + fsm: FSM::FILL_ZERO, + ram_addr: state.ram_addr + (data_decoded / WEIGHTS_RAM_DATA_W as uN[AXI_ADDR_W]) as uN[WEIGHTS_RAM_ADDR_W], + ..state + } + } + }, + FSM::FILL_ZERO => { + if state.ram_addr < !uN[WEIGHTS_RAM_ADDR_W]:0 { + trace_fmt!("[RAW] Filling with zeros {} / {}", state.ram_addr + uN[WEIGHTS_RAM_ADDR_W]:1, !uN[WEIGHTS_RAM_ADDR_W]:0); + State { + ram_addr: state.ram_addr + uN[WEIGHTS_RAM_ADDR_W]:1, + ..state + } + } else { + State { + fsm: FSM::RESP, + ..state + } + } + }, + FSM::RESP => { + State { + fsm: FSM::IDLE, + ..state + } + }, + _ => fail!("impossible_state", state) + } + } +} + +struct HuffmanFseWeightsDecoderReq { + addr: uN[AXI_ADDR_W] +} + +enum HuffmanFseWeightsDecoderStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +struct HuffmanFseWeightsDecoderResp { + status: HuffmanFseWeightsDecoderStatus, +} + +struct HuffmanFseWeightsDecoderState { + placeholder: u1 +} + +proc HuffmanFseWeightsDecoder< + AXI_ADDR_W: u32, AXI_DATA_W: u32, + WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, + WEIGHTS_RAM_NUM_PARTITIONS: u32 +> { + type Req = HuffmanFseWeightsDecoderReq; + type Resp = HuffmanFseWeightsDecoderResp; + type Status = HuffmanFseWeightsDecoderStatus; + type State = HuffmanFseWeightsDecoderState; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + + // Control + req_r: chan in; + resp_s: chan out; + + // MemReader interface for fetching Huffman Tree Description + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; + + weights_ram_wr_req_s: chan out; + weights_ram_wr_resp_r: chan in; + + init { + zero!() + } + + config( + // Control + req_r: chan in, + resp_s: chan out, + + // MemReader interface for fetching Huffman Tree Description + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, + + // RAM Write interface (goes to Huffman Weights Memory) + weights_ram_wr_req_s: chan out, + weights_ram_wr_resp_r: chan in, + ) { + + ( + req_r, resp_s, + mem_rd_req_s, mem_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r + ) + } + + next (state: State) { + let tok = join(); + + let (tok, req) = recv_if(tok, req_r, false, zero!()); + + // Fetch Data + let tok = send_if(tok, mem_rd_req_s, false, zero!()); + let (tok, mem_rd_resp) = recv_if(tok, mem_rd_resp_r, false, zero!()); + + // Send to RAM + let tok = send_if(tok, weights_ram_wr_req_s, false, zero!()); + let (tok, _) = recv_if(tok, weights_ram_wr_resp_r, false, zero!()); + + let tok = send(tok, resp_s, zero!()); + + zero!() + } +} + +pub struct HuffmanWeightsDecoderReq { + addr: uN[AXI_ADDR_W], +} + +pub enum HuffmanWeightsDecoderStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +enum WeightsType: u1 { + RAW = 0, + FSE = 1, +} + +pub struct HuffmanWeightsDecoderResp { + status: HuffmanWeightsDecoderStatus, + tree_description_size: uN[AXI_ADDR_W], +} + +pub struct HuffmanWeightsDecoderState { + req: HuffmanWeightsDecoderReq, +} + +pub proc HuffmanWeightsDecoder< + AXI_ADDR_W: u32, AXI_DATA_W: u32, + WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, + WEIGHTS_RAM_NUM_PARTITIONS: u32 +> { + type Req = HuffmanWeightsDecoderReq; + type Resp = HuffmanWeightsDecoderResp; + type Status = HuffmanWeightsDecoderStatus; + type State = HuffmanWeightsDecoderState; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type WeightsRamRdReq = ram::ReadReq; + type WeightsRamRdResp = ram::ReadResp; + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + + // Types used internally + type RawWeightsReq = HuffmanRawWeightsDecoderReq; + type RawWeightsResp = HuffmanRawWeightsDecoderResp; + type FseWeightsReq = HuffmanFseWeightsDecoderReq; + type FseWeightsResp = HuffmanFseWeightsDecoderResp; + + // Control + req_r: chan in; + resp_s: chan out; + + // MemReader interface for fetching Huffman Tree Description + header_mem_rd_req_s: chan out; + header_mem_rd_resp_r: chan in; + + // Select for RamMux + decoded_weights_sel_s: chan out; + + // Raw Huffman Tree Description Decoder control + raw_weights_req_s: chan out; + raw_weights_resp_r: chan in; + + // Fse Huffman Tree Description Decoder control + fse_weights_req_s: chan out; + fse_weights_resp_r: chan in; + + // Fake ram read request channels (required by RamMux) + raw_weights_ram_rd_req_s: chan out; + raw_weights_ram_rd_resp_r: chan in; + fse_weights_ram_rd_req_s: chan out; + fse_weights_ram_rd_resp_r: chan in; + weights_ram_rd_req_r: chan in; + weights_ram_rd_resp_s: chan out; + + init { + zero!() + } + + config( + // Control + req_r: chan in, + resp_s: chan out, + + // MemReader interface for fetching Huffman Tree Description + header_mem_rd_req_s: chan out, + header_mem_rd_resp_r: chan in, + + // MemReader interface for Raw Huffman Tree Description Decoder + raw_weights_mem_rd_req_s: chan out, + raw_weights_mem_rd_resp_r: chan in, + + // MemReader interface for Fse Huffman Tree Description Decoder + fse_weights_mem_rd_req_s: chan out, + fse_weights_mem_rd_resp_r: chan in, + + // Muxed internal RAM Write interface (goes to Huffman Weights Memory) + weights_ram_wr_req_s: chan out, + weights_ram_wr_resp_r: chan in, + ) { + // Decoded Weights select for RamMux + let (decoded_weights_sel_s, decoded_weights_sel_r) = chan("decoded_weights_sel"); + + // Raw Huffman Tree Description control + let (raw_weights_req_s, raw_weights_req_r) = chan("raw_weights_req"); + let (raw_weights_resp_s, raw_weights_resp_r) = chan("raw_weights_resp"); + + // Fse Huffman Tree Description control + let (fse_weights_req_s, fse_weights_req_r) = chan("fse_weights_req"); + let (fse_weights_resp_s, fse_weights_resp_r) = chan("fse_weights_resp"); + + // Internal RAM Write interface with decoded RAW Huffman Tree Description + let (raw_weights_ram_wr_req_s, raw_weights_ram_wr_req_r) = chan("raw_weights_ram_wr_req"); + let (raw_weights_ram_wr_resp_s, raw_weights_ram_wr_resp_r) = chan("raw_weights_ram_wr_resp"); + + // Internal RAM Write interface with decoded Fse Huffman Tree Description + let (fse_weights_ram_wr_req_s, fse_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); + let (fse_weights_ram_wr_resp_s, fse_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp"); + + let (raw_weights_ram_rd_req_s, raw_weights_ram_rd_req_r) = chan("raw_weights_ram_rd_req"); + let (raw_weights_ram_rd_resp_s, raw_weights_ram_rd_resp_r) = chan("raw_weights_ram_rd_resp"); + let (fse_weights_ram_rd_req_s, fse_weights_ram_rd_req_r) = chan("fse_weights_ram_rd_req"); + let (fse_weights_ram_rd_resp_s, fse_weights_ram_rd_resp_r) = chan("fse_weights_ram_rd_resp"); + let (weights_ram_rd_req_s, weights_ram_rd_req_r) = chan("weights_ram_rd_req"); + let (weights_ram_rd_resp_s, weights_ram_rd_resp_r) = chan("weights_ram_rd_resp"); + + spawn HuffmanRawWeightsDecoder< + AXI_ADDR_W, AXI_DATA_W, + WEIGHTS_RAM_ADDR_W, WEIGHTS_RAM_DATA_W, + WEIGHTS_RAM_NUM_PARTITIONS + >( + raw_weights_req_r, raw_weights_resp_s, + raw_weights_mem_rd_req_s, raw_weights_mem_rd_resp_r, + raw_weights_ram_wr_req_s, raw_weights_ram_wr_resp_r + ); + + spawn HuffmanFseWeightsDecoder< + AXI_ADDR_W, AXI_DATA_W, + WEIGHTS_RAM_ADDR_W, WEIGHTS_RAM_DATA_W, + WEIGHTS_RAM_NUM_PARTITIONS + >( + fse_weights_req_r, fse_weights_resp_s, + fse_weights_mem_rd_req_s, fse_weights_mem_rd_resp_r, + fse_weights_ram_wr_req_s, fse_weights_ram_wr_resp_r + ); + + spawn ram_mux::RamMux( + decoded_weights_sel_r, + raw_weights_ram_rd_req_r, raw_weights_ram_rd_resp_s, // We don't care about read side + raw_weights_ram_wr_req_r, raw_weights_ram_wr_resp_s, + fse_weights_ram_rd_req_r, fse_weights_ram_rd_resp_s, // We don't care about read side + fse_weights_ram_wr_req_r, fse_weights_ram_wr_resp_s, + weights_ram_rd_req_s, weights_ram_rd_resp_r, // We don't care about read side + weights_ram_wr_req_s, weights_ram_wr_resp_r + ); + + ( + req_r, resp_s, + header_mem_rd_req_s, header_mem_rd_resp_r, + decoded_weights_sel_s, + raw_weights_req_s, raw_weights_resp_r, + fse_weights_req_s, fse_weights_resp_r, + raw_weights_ram_rd_req_s, raw_weights_ram_rd_resp_r, // We don't care about read side + fse_weights_ram_rd_req_s, fse_weights_ram_rd_resp_r, // We don't care about read side + weights_ram_rd_req_r, weights_ram_rd_resp_s, // We don't care about read side + ) + } + + next (state: State) { + let tok = join(); + + let (tok, req) = recv(tok, req_r); + trace_fmt!("Received Huffman weights decoding request {:#x}", req); + // Fetch Huffman Tree Header + let header_mem_rd_req = MemReaderReq { + addr: req.addr, + length: uN[AXI_ADDR_W]:1, + }; + let tok = send(tok, header_mem_rd_req_s, header_mem_rd_req); + let (tok, header_mem_rd_resp) = recv(tok, header_mem_rd_resp_r); + + // Decode Huffman Tree Header + // Now we know Huffman Tree Description size and the type of the description (RAW or FSE) + // Send proper select signal for the RamMux + // Send decoding request to HuffmanRawWeightsDecoder or HuffmanFseWeightsDecoder + // Receive response from HuffmanRawWeightsDecoder or HuffmanFseWeightsDecoder + + let header_byte = header_mem_rd_resp.data as u8; + trace_fmt!("Huffman weights header: {:#x}", header_byte); + + let weights_type = if header_byte < u8:128 { + WeightsType::FSE + } else { + WeightsType::RAW + }; + + let tok = send(tok, decoded_weights_sel_s, weights_type == WeightsType::FSE); + + // FSE + trace_fmt!("Decoding FSE Huffman weights"); + let fse_weights_req = zero!(); + let tok = send_if(tok, fse_weights_req_s, weights_type == WeightsType::FSE, fse_weights_req); + let (tok, fse_weights_resp) = recv_if(tok, fse_weights_resp_r, weights_type == WeightsType::FSE, zero!()); + + let fse_status = match fse_weights_resp.status { + HuffmanFseWeightsDecoderStatus::OKAY => HuffmanWeightsDecoderStatus::OKAY, + HuffmanFseWeightsDecoderStatus::ERROR => HuffmanWeightsDecoderStatus::ERROR, + _ => fail!("impossible_status_fse", HuffmanWeightsDecoderStatus::ERROR) + }; + + // RAW + trace_fmt!("Decoding RAW Huffman weights"); + let raw_weights_req = RawWeightsReq { + addr: req.addr, + n_symbols: header_byte - u8:127, + }; + let tok = send_if(tok, raw_weights_req_s, weights_type == WeightsType::RAW, raw_weights_req); + let (tok, raw_weights_resp) = recv_if(tok, raw_weights_resp_r, weights_type == WeightsType::RAW, zero!()); + + let raw_status = match raw_weights_resp.status { + HuffmanRawWeightsDecoderStatus::OKAY => HuffmanWeightsDecoderStatus::OKAY, + HuffmanRawWeightsDecoderStatus::ERROR => HuffmanWeightsDecoderStatus::ERROR, + _ => fail!("impossible_status_raw", HuffmanWeightsDecoderStatus::ERROR) + }; + + let resp = match weights_type { + WeightsType::RAW => { + Resp { + status: raw_status, + tree_description_size: (((header_byte - u8:127) >> u8:1) + u8:1) as uN[AXI_ADDR_W], + } + }, + WeightsType::FSE => { + Resp { + status: fse_status, + tree_description_size: header_byte as uN[AXI_ADDR_W], + } + }, + _ => fail!("impossible_weights_type", zero!()), + }; + + let tok = send(tok, resp_s, resp); + + // Handle fake ram read request channels + let tok = send_if(tok, raw_weights_ram_rd_req_s, false, zero!()); + let tok = send_if(tok, fse_weights_ram_rd_req_s, false, zero!()); + let (tok, _) = recv_if(tok, weights_ram_rd_req_r, false, zero!()); + let tok = send_if(tok, weights_ram_rd_resp_s, false, zero!()); + let (tok, _) = recv_if(tok, raw_weights_ram_rd_resp_r, false, zero!()); + let (tok, _) = recv_if(tok, fse_weights_ram_rd_resp_r, false, zero!()); + + zero!() + } +} + +const INST_AXI_ADDR_W = u32:32; +const INST_AXI_DATA_W = u32:64; +const INST_AXI_DEST_W = u32:8; +const INST_AXI_ID_W = u32:8; + +const INST_RAM_DATA_W = INST_AXI_DATA_W; +const INST_RAM_SIZE = u32:1024; +const INST_RAM_ADDR_W = INST_AXI_ADDR_W; +const INST_RAM_PARTITION_SIZE = INST_RAM_DATA_W / u32:8; +const INST_RAM_NUM_PARTITIONS = ram::num_partitions(INST_RAM_PARTITION_SIZE, INST_RAM_DATA_W); +const INST_RAM_SIMULTANEOUS_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const INST_RAM_INITIALIZED = true; +const INST_RAM_ASSERT_VALID_READ = true; + +const INST_WEIGHTS_RAM_ADDR_W = huffman_prescan::RAM_ADDR_WIDTH; +const INST_WEIGHTS_RAM_SIZE = huffman_prescan::RAM_SIZE; +const INST_WEIGHTS_RAM_DATA_W = huffman_prescan::RAM_ACCESS_WIDTH; +const INST_WEIGHTS_RAM_PARTITION_SIZE = INST_WEIGHTS_RAM_DATA_W / u32:8; +const INST_WEIGHTS_RAM_NUM_PARTITIONS = ram::num_partitions(INST_WEIGHTS_RAM_PARTITION_SIZE, INST_WEIGHTS_RAM_DATA_W); +const INST_WEIGHTS_RAM_SIMULTANEOUS_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const INST_WEIGHTS_RAM_INITIALIZED = true; +const INST_WEIGHTS_RAM_ASSERT_VALID_READ = true; + +proc HuffmanWeightsDecoderInst { + // Memory Reader + Input + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type InputBufferRamRdReq = ram::ReadReq; + type InputBufferRamRdResp = ram::ReadResp; + type InputBufferRamWrReq = ram::WriteReq; + type InputBufferRamWrResp = ram::WriteResp; + + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; + + // Weights RAM + + type WeightsRamRdReq = ram::ReadReq; + type WeightsRamRdResp = ram::ReadResp; + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + + // Huffman Weights Decoder + type Req = HuffmanWeightsDecoderReq; + type Resp = HuffmanWeightsDecoderResp; + type Status = HuffmanWeightsDecoderStatus; + type State = HuffmanWeightsDecoderState; + + config ( + req_r: chan in, + resp_s: chan out, + header_mem_rd_req_s: chan out, + header_mem_rd_resp_r: chan in, + raw_weights_mem_rd_req_s: chan out, + raw_weights_mem_rd_resp_r: chan in, + fse_weights_mem_rd_req_s: chan out, + fse_weights_mem_rd_resp_r: chan in, + weights_ram_wr_req_s: chan out, + weights_ram_wr_resp_r: chan in, + ) { + spawn HuffmanWeightsDecoder< + INST_AXI_ADDR_W, INST_AXI_DATA_W, + INST_WEIGHTS_RAM_ADDR_W, INST_WEIGHTS_RAM_DATA_W, + INST_WEIGHTS_RAM_NUM_PARTITIONS + > ( + req_r, resp_s, + header_mem_rd_req_s, header_mem_rd_resp_r, + raw_weights_mem_rd_req_s, raw_weights_mem_rd_resp_r, + fse_weights_mem_rd_req_s, fse_weights_mem_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r, + ); + } + + init { } + + next (state: ()) { } +} + + +const TEST_AXI_ADDR_W = u32:32; +const TEST_AXI_DATA_W = u32:64; +const TEST_AXI_DEST_W = u32:8; +const TEST_AXI_ID_W = u32:8; + +const TEST_RAM_DATA_W = TEST_AXI_DATA_W; +const TEST_RAM_SIZE = u32:1024; +const TEST_RAM_ADDR_W = TEST_AXI_ADDR_W; +const TEST_RAM_PARTITION_SIZE = TEST_RAM_DATA_W / u32:8; +const TEST_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_RAM_PARTITION_SIZE, TEST_RAM_DATA_W); +const TEST_RAM_SIMULTANEOUS_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_INITIALIZED = true; +const TEST_RAM_ASSERT_VALID_READ = true; + +const TEST_WEIGHTS_RAM_ADDR_W = huffman_prescan::RAM_ADDR_WIDTH; +const TEST_WEIGHTS_RAM_SIZE = huffman_prescan::RAM_SIZE; +const TEST_WEIGHTS_RAM_DATA_W = huffman_prescan::RAM_ACCESS_WIDTH; +const TEST_WEIGHTS_RAM_PARTITION_SIZE = TEST_WEIGHTS_RAM_DATA_W / u32:8; +const TEST_WEIGHTS_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_WEIGHTS_RAM_PARTITION_SIZE, TEST_WEIGHTS_RAM_DATA_W); +const TEST_WEIGHTS_RAM_SIMULTANEOUS_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_WEIGHTS_RAM_INITIALIZED = true; +const TEST_WEIGHTS_RAM_ASSERT_VALID_READ = true; + +const TEST_INPUT_ADDR = uN[TEST_AXI_ADDR_W]:0x40; + +// Weights sum is 1010, so the last one will be 14 +const TEST_DATA = u8[65]:[ + // len x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF + u8:248, u8:0xB__6, u8:0x8__5, u8:0x6__A, u8:0x9__C, u8:0x0__C, u8:0xA__9, u8:0x0__0, u8:0xD__0, // 0x0x + u8:0x6__E, u8:0x3__9, u8:0x8__4, u8:0x7__C, u8:0xC__2, u8:0x4__2, u8:0xB__A, u8:0x4__E, // 0x1x + u8:0xF__6, u8:0x2__7, u8:0x9__4, u8:0xD__1, u8:0xD__8, u8:0x2__B, u8:0xE__2, u8:0xD__1, // 0x2x + u8:0x8__F, u8:0x2__4, u8:0xD__3, u8:0x0__E, u8:0xF__E, u8:0x1__B, u8:0xF__9, u8:0x8__2, // 0x3x + u8:0xC__A, u8:0x6__1, u8:0x0__3, u8:0xD__C, u8:0xF__5, u8:0x1__D, u8:0x7__0, u8:0x1__6, // 0x4x + u8:0xA__A, u8:0x3__2, u8:0x8__8, u8:0x0__6, u8:0xE__7, u8:0x6__7, u8:0x8__E, u8:0x6__2, // 0x5x + u8:0x1__F, u8:0x3__E, u8:0xF__0, u8:0xC__7, u8:0x4__1, u8:0x7__E, u8:0x8__C, u8:0x8__4, // 0x6x + u8:0x3__3, u8:0xA__8, u8:0xE__E, u8:0x4__B, u8:0x0__0, u8:0x0__0, u8:0x0__0, u8:0x0__0, // 0x7x +]; + +const TEST_DATA_LAST_WEIGHT = u8:0xA; + +#[test_proc] +proc HuffmanWeightsDecoder_test { + // Memory Reader + Input + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type InputBufferRamRdReq = ram::ReadReq; + type InputBufferRamRdResp = ram::ReadResp; + type InputBufferRamWrReq = ram::WriteReq; + type InputBufferRamWrResp = ram::WriteResp; + + type AxiAr = axi::AxiAr; + type AxiR = axi::AxiR; + + // Weights RAM + + type WeightsRamRdReq = ram::ReadReq; + type WeightsRamRdResp = ram::ReadResp; + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + + // Huffman Weights Decoder + type Req = HuffmanWeightsDecoderReq; + type Resp = HuffmanWeightsDecoderResp; + type Status = HuffmanWeightsDecoderStatus; + type State = HuffmanWeightsDecoderState; + + terminator: chan out; + + req_s: chan out; + resp_r: chan in; + + input_ram_wr_req_s: chan[3] out; + input_ram_wr_resp_r: chan[3] in; + + weights_ram_rd_req_s: chan out; + weights_ram_rd_resp_r: chan in; + + config (terminator: chan out) { + + // Input Memory + + let (input_ram_rd_req_s, input_ram_rd_req_r) = chan[3]("input_ram_rd_req"); + let (input_ram_rd_resp_s, input_ram_rd_resp_r) = chan[3]("input_ram_rd_resp"); + let (input_ram_wr_req_s, input_ram_wr_req_r) = chan[3]("input_ram_wr_req"); + let (input_ram_wr_resp_s, input_ram_wr_resp_r) = chan[3]("input_ram_wr_resp"); + + unroll_for! (i, _) in range(u32:0, u32:3) { + spawn ram::RamModel< + TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_RW_BEHAVIOR, TEST_RAM_INITIALIZED, + TEST_RAM_ASSERT_VALID_READ, TEST_RAM_ADDR_W, + >( + input_ram_rd_req_r[i], input_ram_rd_resp_s[i], + input_ram_wr_req_r[i], input_ram_wr_resp_s[i], + ); + }(()); + + // Input Memory Axi Reader + + let (axi_ar_s, axi_ar_r) = chan[3]("axi_ar"); + let (axi_r_s, axi_r_r) = chan[3]("axi_r"); + + unroll_for! (i, _) in range(u32:0, u32:3) { + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, + TEST_AXI_DEST_W, TEST_AXI_ID_W, + TEST_RAM_SIZE, + >( + axi_ar_r[i], axi_r_s[i], + input_ram_rd_req_s[i], input_ram_rd_resp_r[i], + ); + }(()); + + // Input Memory Reader + + let (mem_rd_req_s, mem_rd_req_r) = chan[3]("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan[3]("mem_rd_resp"); + + unroll_for! (i, _) in range(u32:0, u32:3) { + spawn mem_reader::MemReader< + TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, + >( + mem_rd_req_r[i], mem_rd_resp_s[i], + axi_ar_s[i], axi_r_r[i], + ); + }(()); + + // Weights RAM + + let (weights_ram_rd_req_s, weights_ram_rd_req_r) = chan("weights_ram_rd_req"); + let (weights_ram_rd_resp_s, weights_ram_rd_resp_r) = chan("weights_ram_rd_resp"); + let (weights_ram_wr_req_s, weights_ram_wr_req_r) = chan("weights_ram_wr_req"); + let (weights_ram_wr_resp_s, weights_ram_wr_resp_r) = chan("weights_ram_wr_resp"); + + spawn ram::RamModel< + TEST_WEIGHTS_RAM_DATA_W, TEST_WEIGHTS_RAM_SIZE, TEST_WEIGHTS_RAM_PARTITION_SIZE, + TEST_WEIGHTS_RAM_SIMULTANEOUS_RW_BEHAVIOR, TEST_WEIGHTS_RAM_INITIALIZED, + TEST_WEIGHTS_RAM_ASSERT_VALID_READ, TEST_WEIGHTS_RAM_ADDR_W, + >( + weights_ram_rd_req_r, weights_ram_rd_resp_s, + weights_ram_wr_req_r, weights_ram_wr_resp_s, + ); + + // Huffman Weights Decoder + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + + spawn HuffmanWeightsDecoder< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, + TEST_WEIGHTS_RAM_ADDR_W, TEST_WEIGHTS_RAM_DATA_W, + TEST_WEIGHTS_RAM_NUM_PARTITIONS + > ( + req_r, resp_s, + mem_rd_req_s[0], mem_rd_resp_r[0], + mem_rd_req_s[1], mem_rd_resp_r[1], + mem_rd_req_s[2], mem_rd_resp_r[2], + weights_ram_wr_req_s, weights_ram_wr_resp_r, + ); + + ( + terminator, + req_s, resp_r, + input_ram_wr_req_s, input_ram_wr_resp_r, + weights_ram_rd_req_s, weights_ram_rd_resp_r, + ) + } + + init { } + + next (state: ()) { + const TEST_DATA_PER_RAM_WRITE = TEST_RAM_DATA_W / u32:8; + + let tok = join(); + + // Fill input RAM + for (i, tok) in range(u32:0, (array_size(TEST_DATA) + TEST_DATA_PER_RAM_WRITE - u32:1) / TEST_DATA_PER_RAM_WRITE) { + let ram_data = for (j, ram_data) in range(u32:0, TEST_DATA_PER_RAM_WRITE) { + let data_idx = i * TEST_DATA_PER_RAM_WRITE + j; + if (data_idx < array_size(TEST_DATA)) { + ram_data | ((TEST_DATA[data_idx] as uN[TEST_RAM_DATA_W]) << (u32:8 * j)) + } else { + ram_data + } + }(uN[TEST_RAM_DATA_W]:0); + + let input_ram_wr_req = InputBufferRamWrReq { + addr: (TEST_INPUT_ADDR / u32:8) + i as uN[TEST_RAM_ADDR_W], + data: ram_data, + mask: !uN[TEST_RAM_NUM_PARTITIONS]:0, + }; + + let tok = send(tok, input_ram_wr_req_s[0], input_ram_wr_req); + let (tok, _) = recv(tok, input_ram_wr_resp_r[0]); + let tok = send(tok, input_ram_wr_req_s[1], input_ram_wr_req); + let (tok, _) = recv(tok, input_ram_wr_resp_r[1]); + let tok = send(tok, input_ram_wr_req_s[2], input_ram_wr_req); + let (tok, _) = recv(tok, input_ram_wr_resp_r[2]); + + trace_fmt!("[TEST] Sent RAM write request to input RAMs {:#x}", input_ram_wr_req); + + tok + }(tok); + + // Send decoding request + let req = Req { + addr: TEST_INPUT_ADDR, + }; + let tok = send(tok, req_s, req); + trace_fmt!("[TEST] Sent request {:#x}", req); + + // Receive response + let (tok, resp) = recv(tok, resp_r); + trace_fmt!("[TEST] Received respose {:#x}", resp); + assert_eq(HuffmanWeightsDecoderStatus::OKAY, resp.status); + assert_eq(((TEST_DATA[0] - u8:127 + u8:1) >> u32:1) as uN[TEST_AXI_ADDR_W], resp.tree_description_size); + + // Insert last weight in test data + let last_weight_idx = ((TEST_DATA[0] as u32 - u32:127) / u32:2) + u32:1; + let last_weight_entry = ( + TEST_DATA[last_weight_idx] | + (TEST_DATA_LAST_WEIGHT << (u32:4 * (u32:1 - ((TEST_DATA[0] - u8:127) as u1 as u32)))) + ); + let test_data = update(TEST_DATA, last_weight_idx, last_weight_entry); + + // Check output RAM + let tok = for (i, tok) in range(u32:0, u32:32) { + let expected_value = if i < u32:16 { + ( + (test_data[4*i + u32:1] as u4) ++ ((test_data[4*i + u32:1] >> u32:4) as u4) ++ + (test_data[4*i + u32:2] as u4) ++ ((test_data[4*i + u32:2] >> u32:4) as u4) ++ + (test_data[4*i + u32:3] as u4) ++ ((test_data[4*i + u32:3] >> u32:4) as u4) ++ + (test_data[4*i + u32:4] as u4) ++ ((test_data[4*i + u32:4] >> u32:4) as u4) + ) + } else { + u32:0 + }; + + let weights_ram_rd_req = WeightsRamRdReq { + addr: i as uN[TEST_WEIGHTS_RAM_ADDR_W], + mask: !uN[TEST_WEIGHTS_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, weights_ram_rd_req_s, weights_ram_rd_req); + let (tok, weights_ram_rd_resp) = recv(tok, weights_ram_rd_resp_r); + trace_fmt!("[TEST] Weights RAM content - addr: {:#x} data: {:#x}", i, weights_ram_rd_resp.data); + + assert_eq(expected_value, weights_ram_rd_resp.data); + + tok + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/literals_block_header_dec.x b/xls/modules/zstd/literals_block_header_dec.x index 86e6597c01..950c394394 100644 --- a/xls/modules/zstd/literals_block_header_dec.x +++ b/xls/modules/zstd/literals_block_header_dec.x @@ -75,18 +75,18 @@ pub struct LiteralsHeader { compressed_size: u20, } -pub fn parse_literals_header(header_raw: u40) -> (LiteralsHeader, u3) { +pub fn parse_literals_header(header_raw: u40) -> (LiteralsHeader, u3, u8) { let (literal_type, header_size) = parse_literals_header_first_byte(header_raw[0:8]); - let (regenerated_size, compressed_size, header_length) = match (header_size) { - LiteralsHeaderSize::SINGLE_BYTE => (header_raw[3:8] as u20, header_raw[3:8] as u20, u3:1), - LiteralsHeaderSize::TWO_BYTES => (header_raw[4:16] as u20, header_raw[4:16] as u20, u3:2), - LiteralsHeaderSize::THREE_BYTES => (header_raw[4:24] as u20, header_raw[4:24] as u20, u3:3), - LiteralsHeaderSize::COMP_THREE_BYTES => (header_raw[4:14] as u20, header_raw[14:24] as u20, u3:3), - LiteralsHeaderSize::COMP_FOUR_BYTES => (header_raw[4:18] as u20, header_raw[18:32] as u20, u3:4), - LiteralsHeaderSize::COMP_FIVE_BYTES => (header_raw[4:22] as u20, header_raw[22:40] as u20, u3:5), + let (regenerated_size, compressed_size, header_length, symbol) = match (header_size) { + LiteralsHeaderSize::SINGLE_BYTE => (header_raw[3:8] as u20, header_raw[3:8] as u20, u3:1, header_raw[8:16]), + LiteralsHeaderSize::TWO_BYTES => (header_raw[4:16] as u20, header_raw[4:16] as u20, u3:2, header_raw[16:24]), + LiteralsHeaderSize::THREE_BYTES => (header_raw[4:24] as u20, header_raw[4:24] as u20, u3:3, header_raw[24:32]), + LiteralsHeaderSize::COMP_THREE_BYTES => (header_raw[4:14] as u20, header_raw[14:24] as u20, u3:3, header_raw[24:32]), + LiteralsHeaderSize::COMP_FOUR_BYTES => (header_raw[4:18] as u20, header_raw[18:32] as u20, u3:4, u8:0), + LiteralsHeaderSize::COMP_FIVE_BYTES => (header_raw[4:22] as u20, header_raw[22:40] as u20, u3:5, u8:0), // fail!() doesn't work with quicktest, JIT failes to translate such function //_ => fail!("Unrecognized_header_sizeC" ,CompressedBlockSize { - _ => (u20:0, u20:0, u3:0), + _ => (u20:0, u20:0, u3:0, u8:0), }; (LiteralsHeader { literal_type: literal_type, @@ -95,12 +95,12 @@ pub fn parse_literals_header(header_raw: u40) -> (LiteralsHeader, u3) { LiteralsBlockType::RLE => u20:1, _ => compressed_size, } - }, header_length) + }, header_length, symbol) } #[quickcheck] fn test_parse_literals_header(x: u40) -> bool { - let (header, header_length_bytes) = parse_literals_header(x); + let (header, header_length_bytes, symbol) = parse_literals_header(x); let (_, header_size) = parse_literals_header_first_byte(x[0:8]); let length_bytes_equivalence = match (header_size) { @@ -138,7 +138,17 @@ fn test_parse_literals_header(x: u40) -> bool { _ => false } }; - length_bytes_equivalence && raw_length_equivalence && regen_comp_size_equivalence + + let symbol_equivalence = match (header_size) { + LiteralsHeaderSize::SINGLE_BYTE => symbol == x[8:16], + LiteralsHeaderSize::TWO_BYTES => symbol == x[16:24], + LiteralsHeaderSize::THREE_BYTES | LiteralsHeaderSize::COMP_THREE_BYTES => symbol == x[24:32], + LiteralsHeaderSize::COMP_FOUR_BYTES => symbol == u8:0, + LiteralsHeaderSize::COMP_FIVE_BYTES => symbol == u8:0, + _ => false + }; + + length_bytes_equivalence && raw_length_equivalence && regen_comp_size_equivalence && symbol_equivalence } pub enum LiteralsHeaderDecoderStatus : u1 { @@ -152,6 +162,7 @@ pub struct LiteralsHeaderDecoderReq { pub struct LiteralsHeaderDecoderResp { header: LiteralsHeader, + symbol: u8, length: u3, status: LiteralsHeaderDecoderStatus, } @@ -166,22 +177,21 @@ pub proc LiteralsHeaderDecoder { type MemReaderResp = mem_reader::MemReaderResp; type MemReaderStatus = mem_reader::MemReaderStatus; - mem_rd_req_s: chan out; - mem_rd_resp_r: chan in; - req_r: chan in; resp_s: chan out; + mem_rd_req_s: chan out; + mem_rd_resp_r: chan in; + init {} config( - mem_rd_req_s: chan out, - mem_rd_resp_r: chan in, - req_r: chan in, resp_s: chan out, + mem_rd_req_s: chan out, + mem_rd_resp_r: chan in, ) { - (mem_rd_req_s, mem_rd_resp_r, req_r, resp_s) + (req_r, resp_s, mem_rd_req_s, mem_rd_resp_r) } next(state: ()) { @@ -196,9 +206,10 @@ pub proc LiteralsHeaderDecoder { // TODO: handle multiple receives on mem_rd_resp_r when AXI_DATA_W < 40 const_assert!(AXI_DATA_W >= u32:64); let (tok, raw) = recv(tok, mem_rd_resp_r); - let (header, length) = parse_literals_header(raw.data[:40]); + let (header, length, symbol) = parse_literals_header(raw.data[:40]); send(tok, resp_s, Resp { header: header, + symbol: symbol, length: length, status: match (raw.status) { MemReaderStatus::OKAY => Status::OKAY, @@ -223,10 +234,10 @@ proc LiteralsHeaderDecoderTest { terminator: chan out; - mem_rd_req_r: chan in; - mem_rd_resp_s: chan out; req_s: chan out; resp_r: chan in; + mem_rd_req_r: chan in; + mem_rd_resp_s: chan out; init {} @@ -239,125 +250,125 @@ proc LiteralsHeaderDecoderTest { let (resp_s, resp_r) = chan("resp"); spawn LiteralsHeaderDecoder ( - mem_rd_req_s, mem_rd_resp_r, req_r, resp_s + req_r, resp_s, mem_rd_req_s, mem_rd_resp_r ); ( terminator, + req_s, resp_r, mem_rd_req_r, mem_rd_resp_s, - req_s, resp_r ) } next(state: ()) { let tok = join(); - + // test data format: raw header, expected size in bytes, expected parsed header - let tests: (u40, u3, LiteralsHeader)[16] = [ - // 2 bits block type == RAW, 1 bit size_format == 0, 5 bits regenerated_size - (u40:0b10100_0_00, u3:1, LiteralsHeader { + let tests: (u40, u3, LiteralsHeader, u8)[16] = [ + // 2 bits block type == RAW, 1 bit size_format == 0, 5 bits regenerated_size, symbol: 0xAA + (u40:0b10101010_10100_0_00, u3:1, LiteralsHeader { literal_type: LiteralsBlockType::RAW, regenerated_size: u20:0b10100, compressed_size: u20:0b10100, - }), - // 2 bits block type == RAW, 2 bit size_format == 1, 12 bits regenerated_size - (u40:0b101010101010_01_00, u3:2, LiteralsHeader { + }, u8:0xAA), + // 2 bits block type == RAW, 2 bit size_format == 1, 12 bits regenerated_size, symbol: 0xF5 + (u40:0b11110101_101010101010_01_00, u3:2, LiteralsHeader { literal_type: LiteralsBlockType::RAW, regenerated_size: u20:0b101010101010, compressed_size: u20:0b101010101010, - }), - // 2 bits block type == RAW, 1 bit size_format == 2, 5 bits regenerated_size - (u40:0b10101_0_00, u3:1, LiteralsHeader { + }, u8:0xF5), + // 2 bits block type == RAW, 1 bit size_format == 2, 5 bits regenerated_size, symbol: 0xF0 + (u40:0b11110000_10101_0_00, u3:1, LiteralsHeader { literal_type: LiteralsBlockType::RAW, regenerated_size: u20:0b10101, compressed_size: u20:0b10101, - }), - // 2 bits block type == RAW, 2 bit size_format == 3, 20 bits regenerated_size - (u40:0b10101010101010101010_11_00, u3:3, LiteralsHeader { + }, u8:0xF0), + // 2 bits block type == RAW, 2 bit size_format == 3, 20 bits regenerated_size, symbol: 0xF0 + (u40:0b11110000_10101010101010101010_11_00, u3:3, LiteralsHeader { literal_type: LiteralsBlockType::RAW, regenerated_size: u20:0b10101010101010101010, compressed_size: u20:0b10101010101010101010, - }), + }, u8:0xF0), - // 2 bits block type == RLE, 1 bit size_format == 0, 5 bits regenerated_size - (u40:0b10100_0_01, u3:1, LiteralsHeader { + // 2 bits block type == RLE, 1 bit size_format == 0, 5 bits regenerated_size, symbol: 0xF0 + (u40:0b11110000_10100_0_01, u3:1, LiteralsHeader { literal_type: LiteralsBlockType::RLE, regenerated_size: u20:0b10100, compressed_size: u20:1, - }), - // 2 bits block type == RLE, 2 bits size_format == 1, 12 bits regenerated_size - (u40:0b101010101010_01_01, u3:2, LiteralsHeader { + }, u8:0xF0), + // 2 bits block type == RLE, 2 bits size_format == 1, 12 bits regenerated_size, symbol: 0xF0 + (u40:0b11110000_101010101010_01_01, u3:2, LiteralsHeader { literal_type: LiteralsBlockType::RLE, regenerated_size: u20:0b101010101010, compressed_size: u20:1, - }), - // 2 bits block type == RLE, 1 bit size_format == 2, 5 bits regenerated_size - (u40:0b10101_0_01, u3:1, LiteralsHeader { + }, u8:0xF0), + // 2 bits block type == RLE, 1 bit size_format == 2, 5 bits regenerated_size, symbol: 0xF0 + (u40:0b11110000_10101_0_01, u3:1, LiteralsHeader { literal_type: LiteralsBlockType::RLE, regenerated_size: u20:0b10101, compressed_size: u20:1, - }), - // 2 bits block type == RLE, 2 bits size_format == 3, 20 bits regenerated_size - (u40:0b10101010101010101010_11_01, u3:3, LiteralsHeader { + }, u8:0xF0), + // 2 bits block type == RLE, 2 bits size_format == 3, 20 bits regenerated_size, symbol: 0xF0 + (u40:0b11110000_10101010101010101010_11_01, u3:3, LiteralsHeader { literal_type: LiteralsBlockType::RLE, regenerated_size: u20:0b10101010101010101010, compressed_size: u20:1, - }), + }, u8:0xF0), - // 2 bits block type == COMPRESSED, 2 bits size_format == 0, 10 bits regenerated_size and compressed_size - (u40:0b1010101010_0101010101_00_10, u3:3, LiteralsHeader { + // 2 bits block type == COMPRESSED, 2 bits size_format == 0, 10 bits regenerated_size and compressed_size, symbol: 0xF0 + (u40:0b11110000_1010101010_0101010101_00_10, u3:3, LiteralsHeader { literal_type: LiteralsBlockType::COMP, regenerated_size: u20:0b0101010101, compressed_size: u20:0b1010101010, - }), - // 2 bits block type == COMPRESSED, 2 bits size_format == 1, 10 bits regenerated_size and compressed_size - (u40:0b1010101010_0101010101_01_10, u3:3, LiteralsHeader { + }, u8:0xF0), + // 2 bits block type == COMPRESSED, 2 bits size_format == 1, 10 bits regenerated_size and compressed_size, symbol: 0xF0 + (u40:0b11110000_1010101010_0101010101_01_10, u3:3, LiteralsHeader { literal_type: LiteralsBlockType::COMP_4, regenerated_size: u20:0b0101010101, compressed_size: u20:0b1010101010, - }), - // 2 bits block type == COMPRESSED, 2 bits size_format == 2, 14 bits regenerated_size and compressed_size + }, u8:0xF0), + // 2 bits block type == COMPRESSED, 2 bits size_format == 2, 14 bits regenerated_size and compressed_size, symbol: 0x0 (u40:0b10101010101010_01010101010101_10_10, u3:4, LiteralsHeader { literal_type: LiteralsBlockType::COMP_4, regenerated_size: u20:0b01010101010101, compressed_size: u20:0b10101010101010, - }), - // 2 bits block type == COMPRESSED, 2 bits size_format == 3, 18 bits regenerated_size and compressed_size + }, u8:0x0), + // 2 bits block type == COMPRESSED, 2 bits size_format == 3, 18 bits regenerated_size and compressed_size, symbol: 0x0 (u40:0b101010101010101010_010101010101010101_11_10, u3:5, LiteralsHeader { literal_type: LiteralsBlockType::COMP_4, regenerated_size: u20:0b010101010101010101, compressed_size: u20:0b101010101010101010, - }), + }, u8:0x0), - // 2 bits block type == TREELESS, 2 bits size_format == 0, 10 bits regenerated_size and compressed_size + // 2 bits block type == TREELESS, 2 bits size_format == 0, 10 bits regenerated_size and compressed_size, symbol: 0x0 (u40:0b1010101010_0101010101_00_11, u3:3, LiteralsHeader { literal_type: LiteralsBlockType::TREELESS, regenerated_size: u20:0b0101010101, compressed_size: u20:0b1010101010, - }), - // 2 bits block type == TREELESS, 2 bits size_format == 1, 10 bits regenerated_size and compressed_size + }, u8:0x0), + // 2 bits block type == TREELESS, 2 bits size_format == 1, 10 bits regenerated_size and compressed_size, symbol: 0x0 (u40:0b1010101010_0101010101_01_11, u3:3, LiteralsHeader { literal_type: LiteralsBlockType::TREELESS_4, regenerated_size: u20:0b0101010101, compressed_size: u20:0b1010101010, - }), - // 2 bits block type == TREELESS, 2 bits size_format == 2, 14 bits regenerated_size and compressed_size + }, u8:0x0), + // 2 bits block type == TREELESS, 2 bits size_format == 2, 14 bits regenerated_size and compressed_size, symbol: 0x0 (u40:0b10101010101010_01010101010101_10_11, u3:4, LiteralsHeader { literal_type: LiteralsBlockType::TREELESS_4, regenerated_size: u20:0b01010101010101, compressed_size: u20:0b10101010101010, - }), - // 2 bits block type == TREELESS, 2 bits size_format == 3, 18 bits regenerated_size and compressed_size + }, u8:0x0), + // 2 bits block type == TREELESS, 2 bits size_format == 3, 18 bits regenerated_size and compressed_size, symbol: 0x0 (u40:0b101010101010101010_010101010101010101_11_11, u3:5, LiteralsHeader { literal_type: LiteralsBlockType::TREELESS_4, regenerated_size: u20:0b010101010101010101, compressed_size: u20:0b101010101010101010, - }), + }, u8:0x0), ]; - const ADDR = uN[TEST_AXI_ADDR_W]:0xDEAD; - + const ADDR = uN[TEST_AXI_ADDR_W]:0xDEAD; + // positive cases - let tok = for ((_, (test_vec, expected_length, expected_header)), tok): ((u32, (u40, u3, LiteralsHeader)), token) in enumerate(tests) { + let tok = for ((_, (test_vec, expected_length, expected_header, expected_symbol)), tok): ((u32, (u40, u3, LiteralsHeader, u8)), token) in enumerate(tests) { send(tok, req_s, Req { addr: ADDR, }); @@ -367,7 +378,7 @@ proc LiteralsHeaderDecoderTest { length: uN[TEST_AXI_ADDR_W]:5 }); let tok = send(tok, mem_rd_resp_s, MemReaderResp { - status: MemReaderStatus::OKAY, + status: MemReaderStatus::OKAY, data: test_vec as uN[TEST_AXI_DATA_W], length: uN[TEST_AXI_ADDR_W]:5, last: true, @@ -375,6 +386,7 @@ proc LiteralsHeaderDecoderTest { let (tok, resp) = recv(tok, resp_r); assert_eq(resp, LiteralsHeaderDecoderResp { header: expected_header, + symbol: expected_symbol, status: LiteralsHeaderDecoderStatus::OKAY, length: expected_length, }); @@ -391,7 +403,7 @@ proc LiteralsHeaderDecoderTest { length: uN[TEST_AXI_ADDR_W]:5 }); let tok = send(tok, mem_rd_resp_s, MemReaderResp { - status: MemReaderStatus::ERROR, + status: MemReaderStatus::ERROR, data: uN[TEST_AXI_DATA_W]:0, length: uN[TEST_AXI_ADDR_W]:0, last: true, @@ -409,25 +421,25 @@ proc LiteralsHeaderDecoderInst { type ReaderReq = mem_reader::MemReaderReq; type ReaderResp = mem_reader::MemReaderResp; - reader_req_s: chan out; - reader_resp_r: chan in; - decode_req_r: chan in; decode_resp_s: chan out; + reader_req_s: chan out; + reader_resp_r: chan in; + config( - reader_req_s: chan out, - reader_resp_r: chan in, decode_req_r: chan in, decode_resp_s: chan out, + reader_req_s: chan out, + reader_resp_r: chan in, ) { spawn LiteralsHeaderDecoder( - reader_req_s, - reader_resp_r, decode_req_r, - decode_resp_s + decode_resp_s, + reader_req_s, + reader_resp_r ); - (reader_req_s, reader_resp_r, decode_req_r, decode_resp_s) + (decode_req_r, decode_resp_s, reader_req_s, reader_resp_r) } init {} diff --git a/xls/modules/zstd/literals_buffer.x b/xls/modules/zstd/literals_buffer.x index 1ad9ff4407..b1e02c21c8 100644 --- a/xls/modules/zstd/literals_buffer.x +++ b/xls/modules/zstd/literals_buffer.x @@ -103,7 +103,7 @@ struct LiteralsBufferReaderToWriterSync { } // PacketDecoder is responsible for receiving read bytes from RAMs response -// handler, removing the "last" flag from each literal and adding this flag +// handler, removing the "literals_last" flag from each literal and adding this flag // to the packet. It also validates the data. proc PacketDecoder { literals_in_r: chan> in; @@ -133,43 +133,23 @@ proc PacketDecoder { ) }(CopyOrMatchContent:0); - // Extract last and validate packet. The resulting last is set if and - // only if any of the literas has it set. Also if any literal has set - // this flag, then the flag in following literal must also be set. In - // other case, the assertion is triggered. - let (last, _, packet_valid, _) = for (i, (last, prev_literal_last, packet_valid, prev_calc)): (u32, (bool, bool, bool, bool)) in range(u32:0, RAM_NUM) { - let literal_last = (literals.content >> (RAM_DATA_WIDTH * (i + u32:1) - u32:1)) as u1; - let calc = if (i == literals.length as uN[32]) { - false - } else { - prev_calc - }; - if (calc) { - ( - last | literal_last, - literal_last, - packet_valid & (!prev_literal_last | literal_last), - calc - ) - } else { - ( - last, - literal_last, - packet_valid, - calc - ) - } - }((false, false, true, true)); + let literals_lasts = for (i, lasts): (u32, bool[RAM_NUM]) in range(u32:0, RAM_NUM) { + let last = (literals.content >> (RAM_DATA_WIDTH * (i + u32:1) - u32:1)) as u1; + update(lasts, i, last) + }(bool[RAM_NUM]:[0, ...]); + let literals_last = literals_lasts[literals.length - u64:1]; - assert!(packet_valid && (literals.last == last), "Invalid packet"); + // TODO: Restore this check after extending request to CommandConstructor + // assert!(literals.last == literals_last, "Invalid packet"); // Send literals data - let tok = send(tok, literals_out_s, SequenceExecutorPacket { + let literals_out = SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, length: literals.length, content: literals_data, - last: last - }); + last: literals_last + }; + let tok = send(tok, literals_out_s, literals_out); // Send sync data to buffer writer let tok = send(tok, buffer_sync_s, LiteralsBufferReaderToWriterSync { @@ -348,8 +328,6 @@ proc LiteralsBufferMux { let sel_raw_literals = state.raw_literals_valid && state.raw_literals_data.id == state.literals_id; let sel_rle_literals = state.rle_literals_valid && state.rle_literals_data.id == state.literals_id; let sel_huff_literals = state.huff_literals_valid && state.huff_literals_data.id == state.literals_id; - - let literals_data = zero!(); let literals_valid = sel_raw_literals || sel_rle_literals || sel_huff_literals; let (literals_data, state) = if (sel_raw_literals) { @@ -369,22 +347,29 @@ proc LiteralsBufferMux { ) } else { ( - literals_data, + zero!(), state ) }; - send_if(tok1, out_literals_s, literals_valid, LiteralsData { + let out_literals = LiteralsData { data: literals_data.data, length: literals_data.length, last: literals_data.last, - }); + }; - if (literals_data.literals_last) { - LiteralsBufferMuxState { literals_id: state.literals_id + LitID:1, ..state } - } else { - state - } + send_if(tok1, out_literals_s, literals_valid, out_literals); + if literals_valid { + trace_fmt!("[LiteralsBufferMux] literals: {:#x}", out_literals); + } else {}; + + let next_state = match (literals_data.last, literals_data.literals_last) { + (true, false) => LiteralsBufferMuxState { literals_id: state.literals_id + LitID:1, ..state }, + (true, true) => zero!(), + (_, _) => state, + }; + + next_state } } @@ -496,8 +481,8 @@ proc LiteralsBufferWriter< // write literals to RAM let packet_data = for (i, data): (u32, LiteralsWithLast) in range(u32:0, RAM_NUM) { - let literal = (((literals_data.data >> (common::SYMBOL_WIDTH * i)) as uN[common::SYMBOL_WIDTH]) as LiteralsWithLast) | - ((literals_data.last as LiteralsWithLast) << common::SYMBOL_WIDTH); + let last = if literals_data.length as u32 == i + u32:1 { (literals_data.last as LiteralsWithLast) << common::SYMBOL_WIDTH } else {LiteralsWithLast:0}; + let literal = (((literals_data.data >> (common::SYMBOL_WIDTH * i)) as uN[common::SYMBOL_WIDTH]) as LiteralsWithLast) | last; data | (literal << (RAM_DATA_WIDTH * i)) }(LiteralsWithLast:0); @@ -974,27 +959,41 @@ enum LiteralsChannel: u2 { } const TEST_LITERALS_DATA: (LiteralsChannel, LiteralsDataWithSync)[9] = [ - (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x12_3456_789A, length: LitLength:5, last: false, id: LitID:0, literals_last: true}), - (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xBBBB_BBBB, length: LitLength:4, last: false, id: LitID:1, literals_last: true}), - (LiteralsChannel::HUFF, LiteralsDataWithSync {data: LitData:0x64, length: LitLength:1, last: false, id: LitID:2, literals_last: true}), - (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xABCD_DCBA_1234_4321, length: LitLength:8, last: false, id: LitID:3, literals_last: true}), - (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x21_4365, length: LitLength:3, last: false, id: LitID:4, literals_last: true}), - (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xAA_BBBB_CCCC_DDDD, length: LitLength:7, last: false, id: LitID:5, literals_last: true}), + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x12_3456_789A, length: LitLength:5, last: true, id: LitID:0, literals_last: false}), + (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xBBBB_BBBB, length: LitLength:4, last: true, id: LitID:1, literals_last: false}), + (LiteralsChannel::HUFF, LiteralsDataWithSync {data: LitData:0x64, length: LitLength:1, last: true, id: LitID:2, literals_last: false}), + (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xABCD_DCBA_1234_4321, length: LitLength:8, last: true, id: LitID:3, literals_last: false}), + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x21_4365, length: LitLength:3, last: true, id: LitID:4, literals_last: false}), + (LiteralsChannel::RLE, LiteralsDataWithSync {data: LitData:0xAA_BBBB_CCCC_DDDD, length: LitLength:7, last: true, id: LitID:5, literals_last: false}), (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0xDCBA_ABCD_1234_4321, length: LitLength:8, last: false, id: LitID:6, literals_last: false}), - (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x78, length: LitLength:1, last: false, id: LitID:6, literals_last: true}), + (LiteralsChannel::RAW, LiteralsDataWithSync {data: LitData:0x78, length: LitLength:1, last: true, id: LitID:6, literals_last: false}), (LiteralsChannel::HUFF, LiteralsDataWithSync {data: LitData:0x26, length: LitLength:1, last: true, id: LitID:7, literals_last: true}), ]; -const TEST_BUFFER_CTRL: LiteralsBufferCtrl[6] = [ +const TEST_BUFFER_CTRL: LiteralsBufferCtrl[11] = [ + // Literal #0 LiteralsBufferCtrl {length: u32:2, last: false}, LiteralsBufferCtrl {length: u32:1, last: false}, - LiteralsBufferCtrl {length: u32:13, last: false}, + LiteralsBufferCtrl {length: u32:2, last: true}, + // Literal #1 + LiteralsBufferCtrl {length: u32:4, last: true}, + // Literal #2 + LiteralsBufferCtrl {length: u32:1, last: true}, + // Literal #3 + LiteralsBufferCtrl {length: u32:8, last: true}, + // Literal #4 + LiteralsBufferCtrl {length: u32:3, last: true}, + // Literal #5 + LiteralsBufferCtrl {length: u32:7, last: true}, + // Literal #6 LiteralsBufferCtrl {length: u32:8, last: false}, - LiteralsBufferCtrl {length: u32:4, last: false}, - LiteralsBufferCtrl {length: u32:10, last: true}, + LiteralsBufferCtrl {length: u32:1, last: true}, + // Literal #7 + LiteralsBufferCtrl {length: u32:1, last: true}, ]; -const TEST_EXPECTED_PACKETS: SequenceExecutorPacket[8] = [ +const TEST_EXPECTED_PACKETS: SequenceExecutorPacket[11] = [ + // Literal #0 SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:2, @@ -1009,28 +1008,46 @@ const TEST_EXPECTED_PACKETS: SequenceExecutorPacket[8] = [ }, SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x2164_BBBB_BBBB_1234, - last: false + length: CopyOrMatchLength:2, + content: CopyOrMatchContent:0x1234, + last: true }, + // Literal #1 SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:5, - content: CopyOrMatchContent:0xDC_BA12_3443, - last: false + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0xBBBB_BBBB, + last: true }, + // Literal #2 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0x64, + last: true + }, + // Literal #3 SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0xCCDD_DD21_4365_ABCD, - last: false + content: CopyOrMatchContent:0xABCD_DCBA_1234_4321, + last: true }, + // Literal #4 SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:4, - content: CopyOrMatchContent:0xAABB_BBCC, - last: false + length: CopyOrMatchLength:3, + content: CopyOrMatchContent:0x21_4365, + last: true }, + // Literal #5 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:7, + content: CopyOrMatchContent:0xAA_BBBB_CCCC_DDDD, + last: true + }, + // Literal #6 SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, length: CopyOrMatchLength:8, @@ -1039,10 +1056,17 @@ const TEST_EXPECTED_PACKETS: SequenceExecutorPacket[8] = [ }, SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:2, - content: CopyOrMatchContent:0x2678, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0x78, last: true }, + // Literal #7 + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0x26, + last: true + } ]; #[test_proc] diff --git a/xls/modules/zstd/literals_decoder.x b/xls/modules/zstd/literals_decoder.x index 24c0a05d2e..1cf493af93 100644 --- a/xls/modules/zstd/literals_decoder.x +++ b/xls/modules/zstd/literals_decoder.x @@ -18,47 +18,679 @@ import std; import xls.examples.ram; import xls.modules.zstd.common as common; +import xls.modules.zstd.literals_block_header_dec as literals_block_header_dec; import xls.modules.zstd.literals_buffer as literals_buffer; -import xls.modules.zstd.literals_dispatcher as literals_dispatcher; +import xls.modules.zstd.memory.axi as axi; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.mem_reader as mem_reader; import xls.modules.zstd.parallel_rams as parallel_rams; import xls.modules.zstd.ram_printer as ram_printer; import xls.modules.zstd.raw_literals_dec as raw_literals_dec; import xls.modules.zstd.rle_literals_dec as rle_literals_dec; +import xls.modules.zstd.huffman_literals_dec as huffman_literals_dec; type CopyOrMatchContent = common::CopyOrMatchContent; type CopyOrMatchLength = common::CopyOrMatchLength; type LitData = common::LitData; type LitLength = common::LitLength; -type LiteralType = common::LiteralType; +type LiteralsBlockType = literals_block_header_dec::LiteralsBlockType; type LiteralsBufferCtrl = common::LiteralsBufferCtrl; type LiteralsData = common::LiteralsData; type LiteralsDataWithSync = common::LiteralsDataWithSync; type LiteralsPathCtrl = common::LiteralsPathCtrl; -type RleLiteralsData = common::RleLiteralsData; type SequenceExecutorMessageType = common::SequenceExecutorMessageType; type SequenceExecutorPacket = common::SequenceExecutorPacket; type Streams = common::Streams; -proc LiteralsDecoder< +pub struct LiteralsDecoderCtrlReq { + addr: uN[AXI_ADDR_W], + literals_last: bool +} + +pub enum LiteralsDecoderCtrlStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +pub struct LiteralsDecoderCtrlResp { + status: LiteralsDecoderCtrlStatus +} + +struct LiteralsDecoderCtrlState { + id: u32, + req: LiteralsDecoderCtrlReq, + req_valid: bool, + decoding_raw_literals: bool, + decoding_rle_literals: bool, + decoding_huffman_literals: bool, +} + +proc LiteralsDecoderCtrl { + type CtrlReq = LiteralsDecoderCtrlReq; + type CtrlResp = LiteralsDecoderCtrlResp; + type HeaderReq = literals_block_header_dec::LiteralsHeaderDecoderReq; + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + type RawReq = raw_literals_dec::RawLiteralsDecoderReq; + type RawResp = raw_literals_dec::RawLiteralsDecoderResp; + type RawRespStatus = raw_literals_dec::RawLiteralsDecoderStatus; + type RleReq = rle_literals_dec::RleLiteralsDecoderReq; + type RleResp = rle_literals_dec::RleLiteralsDecoderResp; + type RleRespStatus = rle_literals_dec::RleLiteralsDecoderStatus; + type HuffmanReq = huffman_literals_dec::HuffmanLiteralsDecoderReq; + type HuffmanResp = huffman_literals_dec::HuffmanLiteralsDecoderResp; + type HuffmanRespStatus = huffman_literals_dec::HuffmanLiteralsDecoderStatus; + + type Status = LiteralsDecoderCtrlStatus; + type State = LiteralsDecoderCtrlState; + + // Literals Decoder control + lit_ctrl_req_r: chan in; + lit_ctrl_resp_s: chan out; + lit_ctrl_header_s: chan out; + + // Literals Header Decoder + lit_header_req_s: chan out; + lit_header_resp_r: chan in; + + // Raw Literals Decoder + raw_lit_req_s: chan out; + raw_lit_resp_r: chan in; + + // Rle Literals Decoder + rle_lit_req_s: chan out; + rle_lit_resp_r: chan in; + + // Huffman Literals Decoder + huffman_lit_req_s: chan out; + huffman_lit_resp_r: chan in; + + init { + zero!() + } + + config ( + // Literals Decoder control + lit_ctrl_req_r: chan in, + lit_ctrl_resp_s: chan out, + lit_ctrl_header_s: chan out, + + // Literals Header Decoder + lit_header_req_s: chan out, + lit_header_resp_r: chan in, + + // Raw Literals Decoder + raw_lit_req_s: chan out, + raw_lit_resp_r: chan in, + + // Rle Literals Decoder + rle_lit_req_s: chan out, + rle_lit_resp_r: chan in, + + // Huffman Literals Decoder + huffman_lit_req_s: chan out, + huffman_lit_resp_r: chan in + ) { + ( + lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + lit_header_req_s, lit_header_resp_r, + raw_lit_req_s, raw_lit_resp_r, + rle_lit_req_s, rle_lit_resp_r, + huffman_lit_req_s, huffman_lit_resp_r + ) + } + + next (state: State) { + let tok = join(); + // Try receiving response from Raw-, Rle- and HuffmanLiteralsDecoder procs to free + // resources at the very begining of next() evaluation + let do_recv_raw_resp = state.decoding_raw_literals; + let (tok, raw_resp, raw_resp_valid) = recv_if_non_blocking(tok, raw_lit_resp_r, do_recv_raw_resp, zero!()); + let decoding_raw_literals = if (raw_resp_valid) { + trace_fmt!("received RawResp: {:#x}", raw_resp); + false + } else { + state.decoding_raw_literals + }; + + let do_recv_rle_resp = state.decoding_rle_literals; + let (tok, rle_resp, rle_resp_valid) = recv_if_non_blocking(tok, rle_lit_resp_r, do_recv_rle_resp, zero!()); + let decoding_rle_literals = if (rle_resp_valid) { + trace_fmt!("received RleResp: {:#x}", rle_resp); + false + } else { + state.decoding_rle_literals + }; + + let do_recv_huffman_resp = state.decoding_huffman_literals; + let (tok, huffman_resp, huffman_resp_valid) = recv_if_non_blocking(tok, huffman_lit_resp_r, do_recv_huffman_resp, zero!()); + let decoding_huffman_literals = if (huffman_resp_valid) { + trace_fmt!("received HuffmanResp: {:#x}", huffman_resp); + false + } else { + state.decoding_huffman_literals + }; + + // Receive new literals decoding request if previous was handled + let tok = join(); + let do_recv_ctrl_req = !state.req_valid; + let (tok, ctrl_req, ctrl_req_valid) = recv_if_non_blocking(tok, lit_ctrl_req_r, do_recv_ctrl_req, zero!()); + + if (ctrl_req_valid) { + trace_fmt!("received CtrlReq: {:#x}", ctrl_req); + } else {}; + + let (new_ctrl_req, new_ctrl_req_valid) = if (ctrl_req_valid) { + (ctrl_req, true) + } else { + (state.req, state.req_valid) + }; + + // There's no harm in trying to receive header decoding response in every next() evaluation + let (tok, header_resp, header_resp_valid) = recv_non_blocking(tok, lit_header_resp_r, zero!()); + if (header_resp_valid) { + trace_fmt!("received HeaderReq: {:#x}", header_resp); + } else {}; + + send_if(tok, lit_ctrl_header_s, header_resp_valid, header_resp); + + // Send literals header decoding request right after receiving CtrlRequest + let header_req = HeaderReq { + addr: new_ctrl_req.addr + }; + let do_send_header_req = ctrl_req_valid; + let tok = send_if(tok, lit_header_req_s, do_send_header_req, header_req); + if (do_send_header_req) { + trace_fmt!("send HeaderReq: {:#x}", header_req); + } else {}; + + // Address of the beginning of the actual literals in the Literals Section + let literals_addr = state.req.addr + header_resp.length as uN[AXI_ADDR_W]; + + // Send raw literals decoding request right after receiving decoded literals header + let raw_req = RawReq { + addr: literals_addr, + length: header_resp.header.regenerated_size as uN[AXI_ADDR_W], + id: state.id, + literals_last: state.req.literals_last + }; + let do_send_raw_req = header_resp_valid && (header_resp.header.literal_type == LiteralsBlockType::RAW) && !state.decoding_raw_literals; + let tok = send_if(tok, raw_lit_req_s, do_send_raw_req, raw_req); + let decoding_raw_literals = if (do_send_raw_req) { + trace_fmt!("send RawReq: {:#x}", raw_req); + true + } else { + decoding_raw_literals + }; + + // Send rle literals decoding request right after receiving decoded literals header + let rle_req = RleReq { + symbol: header_resp.symbol, + length: header_resp.header.regenerated_size, + id: state.id, + literals_last: state.req.literals_last + }; + let do_send_rle_req = header_resp_valid && (header_resp.header.literal_type == LiteralsBlockType::RLE) && !state.decoding_rle_literals; + let tok = send_if(tok, rle_lit_req_s, do_send_rle_req, rle_req); + let decoding_rle_literals = if (do_send_rle_req) { + trace_fmt!("send RleReq: {:#x}", rle_req); + true + } else { + decoding_rle_literals + }; + + // Send huffman literals decoding request right after receiving decoded literals header + let huffman_new_config = match(header_resp.header.literal_type) { + LiteralsBlockType::COMP => true, + LiteralsBlockType::COMP_4 => true, + LiteralsBlockType::TREELESS => false, + LiteralsBlockType::TREELESS_4 => false, + _ => false, + }; + let huffman_multi_stream = match(header_resp.header.literal_type) { + LiteralsBlockType::COMP => false, + LiteralsBlockType::COMP_4 => true, + LiteralsBlockType::TREELESS => false, + LiteralsBlockType::TREELESS_4 => true, + _ => false, + }; + let huffman_req = HuffmanReq { + base_addr: literals_addr, + len: header_resp.header.compressed_size as uN[AXI_ADDR_W], + new_config: huffman_new_config, + multi_stream: huffman_multi_stream, + id: state.id, + literals_last: state.req.literals_last + }; + let huffman_literals_type = header_resp.header.literal_type == LiteralsBlockType::COMP || + header_resp.header.literal_type == LiteralsBlockType::COMP_4 || + header_resp.header.literal_type == LiteralsBlockType::TREELESS || + header_resp.header.literal_type == LiteralsBlockType::TREELESS_4; + let do_send_huffman_req = header_resp_valid && huffman_literals_type && !state.decoding_huffman_literals; + let tok = send_if(tok, huffman_lit_req_s, do_send_huffman_req, huffman_req); + let decoding_huffman_literals = if (do_send_huffman_req) { + trace_fmt!("send HuffmanReq: {:#x}", huffman_req); + true + } else { + decoding_huffman_literals + }; + + // Handle response after literals were decoded + let do_send_resp = raw_resp_valid || + rle_resp_valid || + huffman_resp_valid; + let new_ctrl_req_valid = if (do_send_resp) { + false + } else { + new_ctrl_req_valid + }; + // ERROR status is coded by non-zero integer + // RleLiteralsDecoder cannot fail + // Invalid (not received) response defaults to OKAY + let resp = if (raw_resp.status == RawRespStatus::ERROR || + huffman_resp.status == HuffmanRespStatus::ERROR) { + CtrlResp { status: Status::ERROR } + } else { + CtrlResp { status: Status::OKAY } + }; + let tok = send_if(tok, lit_ctrl_resp_s, do_send_resp, resp); + + let new_id = if (do_send_resp) { + if (state.req_valid && state.req.literals_last) { + u32:0 + } else { + state.id + u32:1 + } + } else { + state.id + }; + + if (do_send_resp) { + trace_fmt!("send CtrlResp: {:#x}", resp); + } else {}; + + let next_state = State { + id: new_id, + req: new_ctrl_req, + req_valid: new_ctrl_req_valid, + decoding_raw_literals: decoding_raw_literals, + decoding_rle_literals: decoding_rle_literals, + decoding_huffman_literals: decoding_huffman_literals, + }; + + next_state + } +} + +const INST_AXI_ADDR_W = u32:16; +proc LiteralsDecoderCtrlInst { + type CtrlReq = LiteralsDecoderCtrlReq; + type CtrlResp = LiteralsDecoderCtrlResp; + type HeaderReq = literals_block_header_dec::LiteralsHeaderDecoderReq; + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + type RawReq = raw_literals_dec::RawLiteralsDecoderReq; + type RawResp = raw_literals_dec::RawLiteralsDecoderResp; + type RleReq = rle_literals_dec::RleLiteralsDecoderReq; + type RleResp = rle_literals_dec::RleLiteralsDecoderResp; + type HuffmanReq = huffman_literals_dec::HuffmanLiteralsDecoderReq; + type HuffmanResp = huffman_literals_dec::HuffmanLiteralsDecoderResp; + + init {} + + config ( + // Literals Decoder control + lit_ctrl_req_r: chan in, + lit_ctrl_resp_s: chan out, + lit_ctrl_header_s: chan out, + + // Literals Header Decoder + lit_header_req_s: chan out, + lit_header_resp_r: chan in, + + // Raw Literals Decoder + raw_lit_req_s: chan out, + raw_lit_resp_r: chan in, + + // Rle Literals Decoder + rle_lit_req_s: chan out, + rle_lit_resp_r: chan in, + + // Huffman Literals Decoder + huffman_lit_req_s: chan out, + huffman_lit_resp_r: chan in + ) { + spawn LiteralsDecoderCtrl( + lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + lit_header_req_s, lit_header_resp_r, + raw_lit_req_s, raw_lit_resp_r, + rle_lit_req_s, rle_lit_resp_r, + huffman_lit_req_s, huffman_lit_resp_r + ); + } + + next (state: ()) {} +} + +const TEST_AXI_ADDR_W = u32:16; +const TEST_AXI_DATA_W = u32:64; + +#[test_proc] +proc LiteralsDecoderCtrl_test { + type CtrlReq = LiteralsDecoderCtrlReq; + type CtrlResp = LiteralsDecoderCtrlResp; + type CtrlStatus = LiteralsDecoderCtrlStatus; + type HeaderReq = literals_block_header_dec::LiteralsHeaderDecoderReq; + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + type HeaderStatus = literals_block_header_dec::LiteralsHeaderDecoderStatus; + type Header = literals_block_header_dec::LiteralsHeader; + type LiteralsBlockType = literals_block_header_dec::LiteralsBlockType; + type RawReq = raw_literals_dec::RawLiteralsDecoderReq; + type RawResp = raw_literals_dec::RawLiteralsDecoderResp; + type RawStatus = raw_literals_dec::RawLiteralsDecoderStatus; + type RleReq = rle_literals_dec::RleLiteralsDecoderReq; + type RleResp = rle_literals_dec::RleLiteralsDecoderResp; + type RleStatus = rle_literals_dec::RleLiteralsDecoderStatus; + type HuffmanReq = huffman_literals_dec::HuffmanLiteralsDecoderReq; + type HuffmanResp = huffman_literals_dec::HuffmanLiteralsDecoderResp; + type HuffmanStatus = huffman_literals_dec::HuffmanLiteralsDecoderStatus; + + type Addr = uN[TEST_AXI_ADDR_W]; + + terminator: chan out; + + // Literals Decoder control + lit_ctrl_req_s: chan out; + lit_ctrl_resp_r: chan in; + lit_ctrl_header_r: chan in; + + // Literals Header Decoder + lit_header_req_r: chan in; + lit_header_resp_s: chan out; + + // Raw Literals Decoder + raw_lit_req_r: chan in; + raw_lit_resp_s: chan out; + + // Rle Literals Decoder + rle_lit_req_r: chan in; + rle_lit_resp_s: chan out; + + // Huffman Literals Decoder + huffman_lit_req_r: chan in; + huffman_lit_resp_s: chan out; + + config (terminator: chan out) { + // Literals Decoder control + let (lit_ctrl_req_s, lit_ctrl_req_r) = chan("lit_ctrl_req"); + let (lit_ctrl_resp_s, lit_ctrl_resp_r) = chan("lit_ctrl_resp"); + let (lit_ctrl_header_s, lit_ctrl_header_r) = chan("lit_ctrl_resp"); + + // Literals Header Decoder + let (lit_header_req_s, lit_header_req_r) = chan("lit_header_req"); + let (lit_header_resp_s, lit_header_resp_r) = chan("lit_header_resp"); + + // Raw Literals Decoder + let (raw_lit_req_s, raw_lit_req_r) = chan("raw_lit_req"); + let (raw_lit_resp_s, raw_lit_resp_r) = chan("raw_lit_resp"); + + // Rle Literals Decoder + let (rle_lit_req_s, rle_lit_req_r) = chan("rle_lit_req"); + let (rle_lit_resp_s, rle_lit_resp_r) = chan("rle_lit_resp"); + + // Huffman Literals Decoder + let (huffman_lit_req_s, huffman_lit_req_r) = chan("huffman_lit_req"); + let (huffman_lit_resp_s, huffman_lit_resp_r) = chan("huffman_lit_resp"); + + spawn LiteralsDecoderCtrl( + lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + lit_header_req_s, lit_header_resp_r, + raw_lit_req_s, raw_lit_resp_r, + rle_lit_req_s, rle_lit_resp_r, + huffman_lit_req_s, huffman_lit_resp_r + ); + + ( + terminator, + lit_ctrl_req_s, lit_ctrl_resp_r, lit_ctrl_header_r, + lit_header_req_r, lit_header_resp_s, + raw_lit_req_r, raw_lit_resp_s, + rle_lit_req_r, rle_lit_resp_s, + huffman_lit_req_r, huffman_lit_resp_s + ) + } + + init {} + + next (state: ()) { + let tok = join(); + + let lit_ctrl_reqs: CtrlReq[6] = [ + CtrlReq { addr: Addr:0x4, literals_last: false }, + CtrlReq { addr: Addr:0x34, literals_last: false }, + CtrlReq { addr: Addr:0x234, literals_last: true }, + CtrlReq { addr: Addr:0x1234, literals_last: false }, + CtrlReq { addr: Addr:0x2345, literals_last: false }, + CtrlReq { addr: Addr:0x3456, literals_last: true }, + ]; + + let lit_header_resps: HeaderResp[6] = [ + HeaderResp { + header: Header { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0x10, + compressed_size: u20:0x20 + }, + symbol: u8:0x00, + length: u3:5, + status: HeaderStatus::OKAY + }, + HeaderResp { + header: Header { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0x20, + compressed_size: u20:0x10 + }, + symbol: u8:0x00, + length: u3:3, + status: HeaderStatus::OKAY + }, + HeaderResp { + header: Header { + literal_type: LiteralsBlockType::RLE, + regenerated_size: u20:0x15, + compressed_size: u20:0x20 + }, + symbol: u8:0x5B, + length: u3:4, + status: HeaderStatus::OKAY + }, + HeaderResp { + header: Header { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0x10, + compressed_size: u20:0x20 + }, + symbol: u8:0x00, + length: u3:5, + status: HeaderStatus::OKAY + }, + HeaderResp { + header: Header { + literal_type: LiteralsBlockType::RLE, + regenerated_size: u20:0x35, + compressed_size: u20:0x20 + }, + symbol: u8:0x6C, + length: u3:3, + status: HeaderStatus::OKAY + }, + HeaderResp { + header: Header { + literal_type: LiteralsBlockType::RAW, + regenerated_size: u20:0x10, + compressed_size: u20:0x20 + }, + symbol: u8:0x00, + length: u3:5, + status: HeaderStatus::OKAY + } + ]; + + // IDs of decoding requests + // Should be zero after each ctrl request with literals_last == true + let req_ids: u32[6] = [ + u32:0, + u32:1, + u32:2, + u32:0, + u32:1, + u32:2, + ]; + + // Test logic + let tok = for (i, tok): (u32, token) in range(u32:0, u32:6) { + let lit_ctrl_req = lit_ctrl_reqs[i]; + let expected_lit_header_req = HeaderReq { addr: lit_ctrl_req.addr }; + let lit_header_resp = lit_header_resps[i]; + + let tok = send(tok, lit_ctrl_req_s, lit_ctrl_req); + trace_fmt!("Test: Sent CtrlReq: {:#x}", lit_ctrl_req); + + let (tok, lit_header_req) = recv(tok, lit_header_req_r); + trace_fmt!("Test: Received HeaderReq: {:#x}", lit_header_req); + assert_eq(lit_header_req, expected_lit_header_req); + let tok = send(tok, lit_header_resp_s, lit_header_resp); + trace_fmt!("Test: Sent HeaderResp: {:#x}", lit_header_resp); + + if (lit_header_resp.header.literal_type == LiteralsBlockType::RAW) { + let (tok, raw_lit_req) = recv(tok, raw_lit_req_r); + trace_fmt!("Test: Received RawReq: {:#x}", raw_lit_req); + let expected_raw_lit_req = RawReq { + id: req_ids[i], + addr: lit_ctrl_reqs[i].addr + lit_header_resps[i].length as Addr, + length: lit_header_resps[i].header.regenerated_size as Addr, + literals_last: lit_ctrl_reqs[i].literals_last + }; + assert_eq(raw_lit_req, expected_raw_lit_req); + let raw_lit_resp = RawResp { status: RawStatus::OKAY }; + let tok = send(tok, raw_lit_resp_s, raw_lit_resp); + trace_fmt!("Test: Sent RawResp: {:#x}", raw_lit_resp); + } else if (lit_header_resp.header.literal_type == LiteralsBlockType::RLE) { + let (tok, rle_lit_req) = recv(tok, rle_lit_req_r); + trace_fmt!("Test: Received RleReq: {:#x}", rle_lit_req); + let expected_rle_lit_req = RleReq { + id: req_ids[i], + symbol: lit_header_resps[i].symbol, + length: lit_header_resps[i].header.regenerated_size, + literals_last: lit_ctrl_reqs[i].literals_last + }; + assert_eq(rle_lit_req, expected_rle_lit_req); + let rle_lit_resp = RleResp { status: RleStatus::OKAY }; + let tok = send(tok, rle_lit_resp_s, rle_lit_resp); + trace_fmt!("Test: Sent RleResp: {:#x}", rle_lit_resp); + } else { + //let (tok, huffman_lit_req) = recv(tok, huffman_lit_req_r); + //trace_fmt!("Test: Received HuffmanReq: {:#x}", huffman_lit_req); + //let expected_huffman_lit_req = HuffmanReq { + //}; + //assert_eq(huffman_lit_req, expected_huffman_lit_req); + //let huffman_lit_resp = HuffmanResp { status: HuffmanStatus::OKAY }; + //let tok = send(tok, huffman_lit_resp_s, huffman_lit_resp); + //trace_fmt!("Test: Sent HuffmanResp: {:#x}", huffman_lit_resp); + }; + + let (tok, lit_ctrl_resp) = recv(tok, lit_ctrl_resp_r); + trace_fmt!("Test: Received CtrlResp: {:#x}", lit_ctrl_resp); + let expected_lit_ctrl_resp = CtrlResp { status: CtrlStatus::OKAY }; + assert_eq(lit_ctrl_resp, expected_lit_ctrl_resp); + + tok + }(tok); + + send(tok, terminator, true); + } +} + +pub proc LiteralsDecoder< HISTORY_BUFFER_SIZE_KB: u32, - RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, - RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + // AXI parameters + AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + // Huffman weights memory parameters + HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_ADDR_WIDTH}, + HUFFMAN_WEIGHTS_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_DATA_WIDTH}, + HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::WEIGHTS_NUM_PARTITIONS}, + // Huffman prescan memory parameters + HUFFMAN_PRESCAN_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::PRESCAN_ADDR_WIDTH}, + HUFFMAN_PRESCAN_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::PRESCAN_DATA_WIDTH}, + HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::PRESCAN_NUM_PARTITIONS}, + // Literals buffer memory parameters + LITERALS_BUFFER_RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + LITERALS_BUFFER_RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, + LITERALS_BUFFER_RAM_DATA_WIDTH: u32 = {literals_buffer::RAM_DATA_WIDTH}, + LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = {literals_buffer::RAM_NUM_PARTITIONS}, > { - type ReadReq = ram::ReadReq; - type ReadResp = ram::ReadResp; - type WriteReq = ram::WriteReq; + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; type WriteResp = ram::WriteResp; - - literals_ctrl_r: chan in; - literals_data_r: chan in; - literals_buf_ctrl_r: chan in; - literals_s: chan out; + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + + type CtrlReq = LiteralsDecoderCtrlReq; + type CtrlResp = LiteralsDecoderCtrlResp; + type BufferCtrl = common::LiteralsBufferCtrl; + type BufferOut = common::SequenceExecutorPacket; + + // TODO: make sure those can use the same parameters + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; config ( - literals_ctrl_r: chan in, - literals_data_r: chan in, - literals_buf_ctrl_r: chan in, - literals_s: chan out, + // AXI Literals Header Decoder (manager) + lit_header_axi_ar_s: chan out, + lit_header_axi_r_r: chan in, + + // AXI Raw Literals Decoder (manager) + raw_lit_axi_ar_s: chan out, + raw_lit_axi_r_r: chan in, + + // AXI Huffman Literals Decoder (manager) + huffman_lit_axi_ar_s: chan out, + huffman_lit_axi_r_r: chan in, + + // AXI Huffman Jump Table Decoder (manager) + huffman_jump_table_axi_ar_s: chan out, + huffman_jump_table_axi_r_r: chan in, + + // AXI Huffman Weights Header Decoder (manager) + huffman_weights_header_axi_ar_s: chan out, + huffman_weights_header_axi_r_r: chan in, + + // AXI Huffman Weights RAW Decoder (manager) + huffman_weights_raw_axi_ar_s: chan out, + huffman_weights_raw_axi_r_r: chan in, + + // AXI Huffman Weights FSE Decoder (manager) + huffman_weights_fse_axi_ar_s: chan out, + huffman_weights_fse_axi_r_r: chan in, + + // Literals Decoder control + lit_ctrl_req_r: chan in, + lit_ctrl_resp_s: chan out, + lit_ctrl_header_s: chan out, + + // Literals Decoder output control + lit_buf_ctrl_r: chan in, + lit_buf_out_s: chan out, + + // Internal memory rd_req_m0_s: chan out, rd_req_m1_s: chan out, rd_req_m2_s: chan out, @@ -90,27 +722,105 @@ proc LiteralsDecoder< wr_resp_m4_r: chan in, wr_resp_m5_r: chan in, wr_resp_m6_r: chan in, - wr_resp_m7_r: chan in + wr_resp_m7_r: chan in, + + // Huffman weights memory + huffman_lit_weights_mem_rd_req_s: chan out, + huffman_lit_weights_mem_rd_resp_r: chan in, + huffman_lit_weights_mem_wr_req_s: chan out, + huffman_lit_weights_mem_wr_resp_r: chan in, + // Huffman prescan memory + huffman_lit_prescan_mem_rd_req_s: chan out, + huffman_lit_prescan_mem_rd_resp_r: chan in, + huffman_lit_prescan_mem_wr_req_s: chan out, + huffman_lit_prescan_mem_wr_resp_r: chan in, ) { - let (raw_literals_s, raw_literals_r) = chan("raw_literals"); - let (rle_literals_s, rle_literals_r) = chan("rle_literals"); - let (huff_literals_s, huff_literals_r) = chan("huff_literals"); + type HeaderReq = literals_block_header_dec::LiteralsHeaderDecoderReq; + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + type RawReq = raw_literals_dec::RawLiteralsDecoderReq; + type RawResp = raw_literals_dec::RawLiteralsDecoderResp; + type RleReq = rle_literals_dec::RleLiteralsDecoderReq; + type RleResp = rle_literals_dec::RleLiteralsDecoderResp; + type HuffmanReq = huffman_literals_dec::HuffmanLiteralsDecoderReq; + type HuffmanResp = huffman_literals_dec::HuffmanLiteralsDecoderResp; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + const CHANNEL_DEPTH = u32:1; + // Literals Header Decoder + let (lit_header_mem_rd_req_s, lit_header_mem_rd_req_r) = chan("lit_header_mem_rd_req"); + let (lit_header_mem_rd_resp_s, lit_header_mem_rd_resp_r) = chan("lit_header_mem_rd_resp"); + + spawn mem_reader::MemReader( + lit_header_mem_rd_req_r, lit_header_mem_rd_resp_s, + lit_header_axi_ar_s, lit_header_axi_r_r + ); + + let (lit_header_req_s, lit_header_req_r) = chan("lit_header_req"); + let (lit_header_resp_s, lit_header_resp_r) = chan("lit_header_resp"); + + spawn literals_block_header_dec::LiteralsHeaderDecoder( + lit_header_req_r, lit_header_resp_s, + lit_header_mem_rd_req_s, lit_header_mem_rd_resp_r + ); - let (decoded_raw_literals_s, decoded_raw_literals_r) = chan("decoded_raw_literals"); - let (decoded_rle_literals_s, decoded_rle_literals_r) = chan("decoded_rle_literals"); + // Raw Literals Decoder + let (raw_lit_mem_rd_req_s, raw_lit_mem_rd_req_r) = chan("raw_lit_mem_rd_req"); + let (raw_lit_mem_rd_resp_s, raw_lit_mem_rd_resp_r) = chan("raw_lit_mem_rd_resp"); - spawn literals_dispatcher::LiteralsDispatcher( - literals_ctrl_r, literals_data_r, - raw_literals_s, rle_literals_s, huff_literals_s, + spawn mem_reader::MemReader( + raw_lit_mem_rd_req_r, raw_lit_mem_rd_resp_s, + raw_lit_axi_ar_s, raw_lit_axi_r_r ); - spawn raw_literals_dec::RawLiteralsDecoder(raw_literals_r, decoded_raw_literals_s); + let (raw_lit_req_s, raw_lit_req_r) = chan("raw_lit_req"); + let (raw_lit_resp_s, raw_lit_resp_r) = chan("raw_lit_resp"); + let (raw_lit_output_s, raw_lit_output_r) = chan("raw_lit_output"); - spawn rle_literals_dec::RleLiteralsDecoder(rle_literals_r, decoded_rle_literals_s); + spawn raw_literals_dec::RawLiteralsDecoder( + raw_lit_req_r, raw_lit_resp_s, raw_lit_output_s, + raw_lit_mem_rd_req_s, raw_lit_mem_rd_resp_r + ); + + // Rle Literals Decoder + let (rle_lit_req_s, rle_lit_req_r) = chan("rle_lit_req"); + let (rle_lit_resp_s, rle_lit_resp_r) = chan("rle_lit_resp"); + let (rle_lit_output_s, rle_lit_output_r) = chan("rle_lit_output"); - spawn literals_buffer::LiteralsBuffer ( - decoded_raw_literals_r, decoded_rle_literals_r, huff_literals_r, - literals_buf_ctrl_r, literals_s, + spawn rle_literals_dec::RleLiteralsDecoder( + rle_lit_req_r, rle_lit_resp_s, rle_lit_output_s + ); + + // Huffman Literals Decoder + let (huffman_lit_req_s, huffman_lit_req_r) = chan("huffman_lit_req"); + let (huffman_lit_resp_s, huffman_lit_resp_r) = chan("huffman_lit_resp"); + let (huffman_lit_output_s, huffman_lit_output_r) = chan("huffman_lit_output"); + + spawn huffman_literals_dec::HuffmanLiteralsDecoder< + AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W, + HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH, HUFFMAN_WEIGHTS_RAM_DATA_WIDTH, HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS, + HUFFMAN_PRESCAN_RAM_ADDR_WIDTH, HUFFMAN_PRESCAN_RAM_DATA_WIDTH, HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS + >( + huffman_lit_req_r, huffman_lit_resp_s, huffman_lit_output_s, + huffman_lit_axi_ar_s, huffman_lit_axi_r_r, + huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, + huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, + huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, + huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + ); + + // Literals Buffer + spawn literals_buffer::LiteralsBuffer< + HISTORY_BUFFER_SIZE_KB, + LITERALS_BUFFER_RAM_SIZE, + LITERALS_BUFFER_RAM_ADDR_WIDTH + > ( + raw_lit_output_r, rle_lit_output_r, huffman_lit_output_r, + lit_buf_ctrl_r, lit_buf_out_s, rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, @@ -121,10 +831,15 @@ proc LiteralsDecoder< wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, ); - ( - literals_ctrl_r, literals_data_r, - literals_buf_ctrl_r, literals_s, - ) + spawn LiteralsDecoderCtrl ( + lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + lit_header_req_s, lit_header_resp_r, + raw_lit_req_s, raw_lit_resp_r, + rle_lit_req_s, rle_lit_resp_r, + huffman_lit_req_s, huffman_lit_resp_r, + ); + + () } init { } @@ -134,18 +849,79 @@ proc LiteralsDecoder< const ZSTD_HISTORY_BUFFER_SIZE_KB: u32 = u32:64; const ZSTD_RAM_ADDR_WIDTH: u32 = parallel_rams::ram_addr_width(ZSTD_HISTORY_BUFFER_SIZE_KB); +const INST_AXI_DATA_W:u32 = u32:64; +const INST_AXI_ID_W:u32 = u32:4; +const INST_AXI_DEST_W:u32 = u32:4; + +const INST_HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH = huffman_literals_dec::INST_WEIGHTS_RAM_ADDR_WIDTH; +const INST_HUFFMAN_WEIGHTS_RAM_DATA_WIDTH = huffman_literals_dec::INST_WEIGHTS_RAM_DATA_WIDTH; +const INST_HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS = huffman_literals_dec::INST_WEIGHTS_RAM_NUM_PARTITIONS; +const INST_HUFFMAN_PRESCAN_RAM_ADDR_WIDTH = huffman_literals_dec::INST_PRESCAN_RAM_ADDR_WIDTH; +const INST_HUFFMAN_PRESCAN_RAM_DATA_WIDTH = huffman_literals_dec::INST_PRESCAN_RAM_DATA_WIDTH; +const INST_HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS = huffman_literals_dec::INST_PRESCAN_RAM_NUM_PARTITIONS; proc LiteralsDecoderInst { type ReadReq = ram::ReadReq; type ReadResp = ram::ReadResp; type WriteReq = ram::WriteReq; type WriteResp = ram::WriteResp; + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + + type CtrlReq = LiteralsDecoderCtrlReq; + type CtrlResp = LiteralsDecoderCtrlResp; + type BufferCtrl = common::LiteralsBufferCtrl; + type BufferOut = common::SequenceExecutorPacket; + + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; config ( - literals_ctrl_r: chan in, - literals_data_r: chan in, - literals_buf_ctrl_r: chan in, - literals_s: chan out, + // AXI Literals Header Decoder (manager) + lit_header_axi_ar_s: chan out, + lit_header_axi_r_r: chan in, + + // AXI Raw Literals Decoder (manager) + raw_lit_axi_ar_s: chan out, + raw_lit_axi_r_r: chan in, + + // AXI Huffman Literals Decoder (manager) + huffman_lit_axi_ar_s: chan out, + huffman_lit_axi_r_r: chan in, + + // AXI Huffman Jump Table Decoder (manager) + huffman_jump_table_axi_ar_s: chan out, + huffman_jump_table_axi_r_r: chan in, + + // AXI Huffman Weights header Decoder (manager) + huffman_weights_header_axi_ar_s: chan out, + huffman_weights_header_axi_r_r: chan in, + + // AXI Huffman Weights RAW Decoder (manager) + huffman_weights_raw_axi_ar_s: chan out, + huffman_weights_raw_axi_r_r: chan in, + + // AXI Huffman Weights FSE Decoder (manager) + huffman_weights_fse_axi_ar_s: chan out, + huffman_weights_fse_axi_r_r: chan in, + + // Literals Decoder control + lit_ctrl_req_r: chan in, + lit_ctrl_resp_s: chan out, + lit_ctrl_header_s: chan out, + + // Literals Decoder output control + lit_buf_ctrl_r: chan in, + lit_buf_out_s: chan out, + rd_req_m0_s: chan out, rd_req_m1_s: chan out, rd_req_m2_s: chan out, @@ -177,11 +953,33 @@ proc LiteralsDecoderInst { wr_resp_m4_r: chan in, wr_resp_m5_r: chan in, wr_resp_m6_r: chan in, - wr_resp_m7_r: chan in + wr_resp_m7_r: chan in, + + // Huffman weights memory + huffman_lit_weights_mem_rd_req_s: chan out, + huffman_lit_weights_mem_rd_resp_r: chan in, + huffman_lit_weights_mem_wr_req_s: chan out, + huffman_lit_weights_mem_wr_resp_r: chan in, + // Huffman prescan memory + huffman_lit_prescan_mem_rd_req_s: chan out, + huffman_lit_prescan_mem_rd_resp_r: chan in, + huffman_lit_prescan_mem_wr_req_s: chan out, + huffman_lit_prescan_mem_wr_resp_r: chan in ) { - spawn LiteralsDecoder ( - literals_ctrl_r, literals_data_r, - literals_buf_ctrl_r, literals_s, + spawn LiteralsDecoder ( + lit_header_axi_ar_s, lit_header_axi_r_r, + raw_lit_axi_ar_s, raw_lit_axi_r_r, + huffman_lit_axi_ar_s, huffman_lit_axi_r_r, + huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, + huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, + huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, + huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + lit_buf_ctrl_r, lit_buf_out_s, rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, @@ -190,6 +988,10 @@ proc LiteralsDecoderInst { wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, ); } @@ -198,161 +1000,191 @@ proc LiteralsDecoderInst { next (state: ()) {} } -// RAM related constants common for tests -const TEST_HISTORY_BUFFER_SIZE_KB = u32:1; -const TEST_RAM_SIZE = parallel_rams::ram_size(TEST_HISTORY_BUFFER_SIZE_KB); -const TEST_RAM_ADDR_WIDTH = parallel_rams::ram_addr_width(TEST_HISTORY_BUFFER_SIZE_KB); -const TEST_RAM_INITIALIZED = true; -const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; - -type TestRamAddr = bits[TEST_RAM_ADDR_WIDTH]; -type TestWriteReq = ram::WriteReq; -type TestWriteResp = ram::WriteResp; -type TestReadReq = ram::ReadReq; -type TestReadResp = ram::ReadResp; - -const TEST_CTRL: LiteralsPathCtrl[7] = [ - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:8, literals_type: LiteralType::RAW}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:4, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:2, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:15, literals_type: LiteralType::RAW}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:12, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:0, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: u20:31, literals_type: LiteralType::RAW}, -]; - -const TEST_DATA: LiteralsData[11] = [ - // 0. RAW - LiteralsData {data: LitData:0x1657_3465_A6DB_5DB0, length: LitLength:8, last: false}, - // 1. RLE - LiteralsData {data: LitData:0x23, length: LitLength:1, last: false}, - // 2. RLE - LiteralsData {data: LitData:0x35, length: LitLength:1, last: false}, - // 3. RAW - LiteralsData {data: LitData:0x4CFB_41C6_7B60_5370, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0x009B_0F9C_E1BA_A96D, length: LitLength:7, last: true}, - // 4. RLE - LiteralsData {data: LitData:0x5A, length: LitLength:1, last: false}, - // 5. RLE - LiteralsData {data: LitData:0xFF, length: LitLength:1, last: false}, - // 6. RAW - LiteralsData {data: LitData:0x6094_3E96_1834_C247, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0xBC02_D0E8_D728_9ABE, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0xF864_C38B_E1FA_8D12, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0x0019_63F1_CE21_C294, length: LitLength:7, last: true}, -]; - -const TEST_BUF_CTRL: LiteralsBufferCtrl[5] = [ - LiteralsBufferCtrl {length: u32:11, last: false}, - LiteralsBufferCtrl {length: u32:2, last: false}, - LiteralsBufferCtrl {length: u32:16, last: true}, - LiteralsBufferCtrl {length: u32:11, last: false}, - LiteralsBufferCtrl {length: u32:32, last: true}, -]; - -const TEST_EXPECTED_LITERALS: SequenceExecutorPacket[11] = [ - // ctrl 0 - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x1657_3465_A6DB_5DB0, - last: false - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:3, - content: CopyOrMatchContent:0x23_2323, - last: false - }, - // ctrl 1 - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:2, - content: CopyOrMatchContent:0x35_23, - last: false - }, - // ctrl 2 - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0xFB41_C67B_6053_7035, - last: false - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x9B0F_9CE1_BAA9_6D4C, - last: true - }, - // ctrl 3 - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x5A5A_5A5A_5A5A_5A5A, - last: false - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:3, - content: CopyOrMatchContent:0x5A_5A5A, - last: false - }, - // ctrl 4 - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x943E_9618_34C2_475A, - last: false - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x02D0_E8D7_289A_BE60, - last: false - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x64C3_8BE1_FA8D_12BC, - last: false - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:8, - content: CopyOrMatchContent:0x1963_F1CE_21C2_94F8, - last: true - }, -]; +const TEST_HISTORY_BUFFER_SIZE_KB:u32 = u32:1; + +// Parameters for the AXI bus connecting LiteralsBlockHeaderDecoder, +// RawLiteralsDecoder and HuffmanLiteralsDecoder to the system memory +const TEST_AXI_RAM_ADDR_W:u32 = u32:32; +const TEST_AXI_RAM_DATA_W:u32 = u32:64; +const TEST_AXI_RAM_ID_W:u32 = u32:8; +const TEST_AXI_RAM_DEST_W:u32 = u32:8; + +// Parameters for RamModels used for mocking the system memory for +// the LiteralsBlockHeaderDecoder, RawLiteralsDecoder and HuffmanLiteralsDecoder +const TEST_AXI_RAM_MODEL_DATA_WIDTH:u32 = TEST_AXI_RAM_DATA_W; +const TEST_AXI_RAM_MODEL_SIZE:u32 = u32:1024; +const TEST_AXI_RAM_MODEL_ADDR_WIDTH:u32 = std::clog2(TEST_AXI_RAM_MODEL_SIZE); +const TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE:u32 = u32:8; +const TEST_AXI_RAM_MODEL_NUM_PARTITIONS:u32 = ram::num_partitions(TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, TEST_AXI_RAM_MODEL_DATA_WIDTH); +const TEST_AXI_RAM_MODEL_BASE_ADDR:u32 = u32:0; +const TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_AXI_RAM_MODEL_INITIALIZED = true; +const TEST_AXI_RAM_MODEL_ASSERT_VALID_READ = true; +const TEST_AXI_RAM_MODEL_NUM = u32:1; + +// Parameters for RamModels used for mocking the LiteralsBuffer internal memory +const TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH:u32 = literals_buffer::RAM_DATA_WIDTH; +const TEST_LITERALS_BUFFER_RAM_MODEL_SIZE:u32 = parallel_rams::ram_size(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_LITERALS_BUFFER_RAM_MODEL_ADDR_WIDTH:u32 = parallel_rams::ram_addr_width(TEST_HISTORY_BUFFER_SIZE_KB); +const TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE:u32 = literals_buffer::RAM_WORD_PARTITION_SIZE; +const TEST_LITERALS_BUFFER_RAM_MODEL_NUM_PARTITIONS:u32 = literals_buffer::RAM_NUM_PARTITIONS; +const TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED = true; +const TEST_LITERALS_BUFFER_RAM_MODEL_ASSERT_VALID_READ = true; +const TEST_LITERALS_BUFFER_RAM_MODEL_NUM = literals_buffer::RAM_NUM; + +// Parameters for RamModels used for mocking the HuffmanLiteralsDecoder prescan weights memory +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_DATA_WIDTH:u32 = huffman_literals_dec::TEST_PRESCAN_RAM_DATA_WIDTH; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_SIZE:u32 = huffman_literals_dec::TEST_PRESCAN_RAM_SIZE; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_ADDR_WIDTH:u32 = huffman_literals_dec::TEST_PRESCAN_RAM_ADDR_WIDTH; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_WORD_PARTITION_SIZE:u32 = huffman_literals_dec::TEST_PRESCAN_WORD_PARTITION_SIZE; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_NUM_PARTITIONS:u32 = huffman_literals_dec::TEST_PRESCAN_RAM_NUM_PARTITIONS; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_INITIALIZED = true; +const TEST_HUFFMAN_PRESCAN_RAM_MODEL_ASSERT_VALID_READ = true; + +// Parameters for RamModels used for mocking the HuffmanLiteralsDecoder internal weights memory +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_DATA_WIDTH:u32 = huffman_literals_dec::TEST_WEIGHTS_RAM_DATA_WIDTH; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_SIZE:u32 = huffman_literals_dec::TEST_WEIGHTS_RAM_SIZE; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ADDR_WIDTH:u32 = huffman_literals_dec::TEST_WEIGHTS_RAM_ADDR_WIDTH; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_WORD_PARTITION_SIZE:u32 = huffman_literals_dec::TEST_WEIGHTS_WORD_PARTITION_SIZE; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_NUM_PARTITIONS:u32 = huffman_literals_dec::TEST_WEIGHTS_RAM_NUM_PARTITIONS; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_INITIALIZED = true; +const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ASSERT_VALID_READ = true; #[test_proc] proc LiteralsDecoder_test { + // LiteralsBuffer internal memory + type LiteralsBufferRamRdReq = ram::ReadReq; + type LiteralsBufferRamRdResp = ram::ReadResp; + type LiteralsBufferRamWrReq = ram::WriteReq; + type LiteralsBufferRamWrResp = ram::WriteResp; + + // System bus + type MemAxiR = axi::AxiR; + type MemAxiAr = axi::AxiAr; + + // System bus external memory + type AxiRamRdReq = ram::ReadReq; + type AxiRamRdResp = ram::ReadResp; + type AxiRamWrReq = ram::WriteReq; + type AxiRamWrResp = ram::WriteResp; + + // Huffman weights internal memory + type HuffmanWeightsRamRdReq = ram::ReadReq; + type HuffmanWeightsRamRdResp = ram::ReadResp; + type HuffmanWeightsRamWrReq = ram::WriteReq; + type HuffmanWeightsRamWrResp = ram::WriteResp; + + // Huffman prescan internal memory + type HuffmanPrescanRamRdReq = ram::ReadReq; + type HuffmanPrescanRamRdResp = ram::ReadResp; + type HuffmanPrescanRamWrReq = ram::WriteReq; + type HuffmanPrescanRamWrResp = ram::WriteResp; + + // Control and output + type CtrlReq = LiteralsDecoderCtrlReq; + type CtrlResp = LiteralsDecoderCtrlResp; + type CtrlStatus = LiteralsDecoderCtrlStatus; + type BufferCtrl = common::LiteralsBufferCtrl; + type BufferOut = common::SequenceExecutorPacket; + + type AxiRamData = uN[TEST_AXI_RAM_MODEL_DATA_WIDTH]; + type AxiRamAddr = uN[TEST_AXI_RAM_MODEL_ADDR_WIDTH]; + type AxiRamMask = uN[TEST_AXI_RAM_MODEL_NUM_PARTITIONS]; + + type AxiAddr = uN[TEST_AXI_RAM_ADDR_W]; + + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + terminator: chan out; - literals_ctrl_s: chan out; - literals_data_s: chan out; - literals_buf_ctrl_s: chan out; - literals_r: chan in; + // Literals Decoder control + ctrl_req_s: chan out; + ctrl_resp_r: chan in; + ctrl_header_r: chan in; + + // Output control + buf_ctrl_s: chan out; + buf_out_r: chan in; print_start_s: chan<()> out; print_finish_r: chan<()> in; + ram_wr_req_header_s : chan out; + ram_wr_resp_header_r : chan in; + ram_wr_req_raw_s : chan out; + ram_wr_resp_raw_r : chan in; + ram_wr_req_huffman_s : chan out; + ram_wr_resp_huffman_r : chan in; + ram_wr_req_huffman_jump_table_s : chan out; + ram_wr_resp_huffman_jump_table_r : chan in; + ram_wr_req_huffman_weights_header_s : chan out; + ram_wr_resp_huffman_weights_header_r : chan in; + ram_wr_req_huffman_weights_raw_s : chan out; + ram_wr_resp_huffman_weights_raw_r : chan in; + ram_wr_req_huffman_weights_fse_s : chan out; + ram_wr_resp_huffman_weights_fse_r : chan in; + config (terminator: chan out) { - let (literals_ctrl_s, literals_ctrl_r) = chan("literals_ctrl"); - let (literals_data_s, literals_data_r) = chan("literals_data"); - let (literals_buf_ctrl_s, literals_buf_ctrl_r) = chan("literals_buf_ctrl"); - let (literals_s, literals_r) = chan("literals"); + let (lit_header_axi_ar_s, lit_header_axi_ar_r) = chan("lit_header_axi_ar"); + let (lit_header_axi_r_s, lit_header_axi_r_r) = chan("lit_header_axi_r"); + + let (raw_lit_axi_ar_s, raw_lit_axi_ar_r) = chan("raw_lit_axi_ar"); + let (raw_lit_axi_r_s, raw_lit_axi_r_r) = chan("raw_lit_axi_r"); + + let (huffman_lit_axi_ar_s, huffman_lit_axi_ar_r) = chan("huffman_lit_axi_ar"); + let (huffman_lit_axi_r_s, huffman_lit_axi_r_r) = chan("huffman_lit_axi_r"); + let (huffman_jump_table_axi_ar_s, huffman_jump_table_axi_ar_r) = chan("huffman_jump_table_axi_ar"); + let (huffman_jump_table_axi_r_s, huffman_jump_table_axi_r_r) = chan("huffman_jump_table_axi_r"); + let (huffman_weights_header_axi_ar_s, huffman_weights_header_axi_ar_r) = chan("huffman_weights_header_axi_ar"); + let (huffman_weights_header_axi_r_s, huffman_weights_header_axi_r_r) = chan("huffman_weights_header_axi_r"); + let (huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_ar_r) = chan("huffman_weights_raw_axi_ar"); + let (huffman_weights_raw_axi_r_s, huffman_weights_raw_axi_r_r) = chan("huffman_weights_raw_axi_r"); + let (huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_ar_r) = chan("huffman_weights_fse_axi_ar"); + let (huffman_weights_fse_axi_r_s, huffman_weights_fse_axi_r_r) = chan("huffman_weights_fse_axi_r"); + + let (ctrl_req_s, ctrl_req_r) = chan("ctrl_req"); + let (ctrl_resp_s, ctrl_resp_r) = chan("ctrl_resp"); + let (ctrl_header_s, ctrl_header_r) = chan("ctrl_header"); + let (buf_ctrl_s, buf_ctrl_r) = chan("buf_ctrl"); + let (buf_out_s, buf_out_r) = chan("buf_out"); let (print_start_s, print_start_r) = chan<()>("print_start"); let (print_finish_s, print_finish_r) = chan<()>("print_finish"); - let (ram_rd_req_s, ram_rd_req_r) = chan[literals_buffer::RAM_NUM]("ram_rd_req"); - let (ram_rd_resp_s, ram_rd_resp_r) = chan[literals_buffer::RAM_NUM]("ram_rd_resp"); - let (ram_wr_req_s, ram_wr_req_r) = chan[literals_buffer::RAM_NUM]("ram_wr_req"); - let (ram_wr_resp_s, ram_wr_resp_r) = chan[literals_buffer::RAM_NUM]("ram_wr_resp"); - - spawn LiteralsDecoder( - literals_ctrl_r, literals_data_r, - literals_buf_ctrl_r, literals_s, + let (ram_rd_req_s, ram_rd_req_r) = chan[literals_buffer::RAM_NUM]("ram_rd_req"); + let (ram_rd_resp_s, ram_rd_resp_r) = chan[literals_buffer::RAM_NUM]("ram_rd_resp"); + let (ram_wr_req_s, ram_wr_req_r) = chan[literals_buffer::RAM_NUM]("ram_wr_req"); + let (ram_wr_resp_s, ram_wr_resp_r) = chan[literals_buffer::RAM_NUM]("ram_wr_resp"); + + let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + + let (huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); + let (huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); + let (huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); + let (huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + + spawn LiteralsDecoder< + TEST_HISTORY_BUFFER_SIZE_KB, + TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_DEST_W, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_WEIGHTS_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_WEIGHTS_RAM_MODEL_NUM_PARTITIONS, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_PRESCAN_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_PRESCAN_RAM_MODEL_NUM_PARTITIONS, + TEST_LITERALS_BUFFER_RAM_MODEL_ADDR_WIDTH, TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, TEST_LITERALS_BUFFER_RAM_MODEL_NUM_PARTITIONS + > ( + lit_header_axi_ar_s, lit_header_axi_r_r, + raw_lit_axi_ar_s, raw_lit_axi_r_r, + huffman_lit_axi_ar_s, huffman_lit_axi_r_r, + huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, + huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, + huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, + huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + ctrl_req_r, ctrl_resp_s, ctrl_header_s, + buf_ctrl_r, buf_out_s, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], @@ -360,91 +1192,591 @@ proc LiteralsDecoder_test { ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], - ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7] + ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7], + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, ); spawn ram_printer::RamPrinter< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_NUM_PARTITIONS, - TEST_RAM_ADDR_WIDTH, literals_buffer::RAM_NUM> - (print_start_r, print_finish_s, ram_rd_req_s, ram_rd_resp_r); + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_NUM_PARTITIONS, + TEST_LITERALS_BUFFER_RAM_MODEL_ADDR_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_NUM + > ( + print_start_r, print_finish_s, ram_rd_req_s, ram_rd_resp_r + ); + + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6] + ); + spawn ram::RamModel< + TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, + TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_LITERALS_BUFFER_RAM_MODEL_INITIALIZED + > ( + ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7] + ); + + // Mock RAM for Literals Header MemReader + let (ram_rd_req_header_s, ram_rd_req_header_r) = chan("ram_rd_req_header"); + let (ram_rd_resp_header_s, ram_rd_resp_header_r) = chan("ram_rd_resp_header"); + let (ram_wr_req_header_s, ram_wr_req_header_r) = chan("ram_wr_req_header"); + let (ram_wr_resp_header_s, ram_wr_resp_header_r) = chan("ram_wr_resp_header"); spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_header_r, ram_rd_resp_header_s, ram_wr_req_header_r, ram_wr_resp_header_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + lit_header_axi_ar_r, lit_header_axi_r_s, + ram_rd_req_header_s, ram_rd_resp_header_r + ); + + // Mock RAM for RawLiterals MemReader + let (ram_rd_req_raw_s, ram_rd_req_raw_r) = chan("ram_rd_req_raw"); + let (ram_rd_resp_raw_s, ram_rd_resp_raw_r) = chan("ram_rd_resp_raw"); + let (ram_wr_req_raw_s, ram_wr_req_raw_r) = chan("ram_wr_req_raw"); + let (ram_wr_resp_raw_s, ram_wr_resp_raw_r) = chan("ram_wr_resp_raw"); + spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_raw_r, ram_rd_resp_raw_s, ram_wr_req_raw_r, ram_wr_resp_raw_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + raw_lit_axi_ar_r, raw_lit_axi_r_s, + ram_rd_req_raw_s, ram_rd_resp_raw_r + ); + + // Mock RAM for HuffmanLiteralsDecoder MemReader + let (ram_rd_req_huffman_s, ram_rd_req_huffman_r) = chan("ram_rd_req_huffman"); + let (ram_rd_resp_huffman_s, ram_rd_resp_huffman_r) = chan("ram_rd_resp_huffman"); + let (ram_wr_req_huffman_s, ram_wr_req_huffman_r) = chan("ram_wr_req_huffman"); + let (ram_wr_resp_huffman_s, ram_wr_resp_huffman_r) = chan("ram_wr_resp_huffman"); + spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_r, ram_rd_resp_huffman_s, ram_wr_req_huffman_r, ram_wr_resp_huffman_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + huffman_lit_axi_ar_r, huffman_lit_axi_r_s, + ram_rd_req_huffman_s, ram_rd_resp_huffman_r + ); + + // Mock RAM for Huffman Jump Table decoder MemReader + let (ram_rd_req_huffman_jump_table_s, ram_rd_req_huffman_jump_table_r) = chan("ram_rd_req_huffman_jump_table"); + let (ram_rd_resp_huffman_jump_table_s, ram_rd_resp_huffman_jump_table_r) = chan("ram_rd_resp_huffman_jump_table"); + let (ram_wr_req_huffman_jump_table_s, ram_wr_req_huffman_jump_table_r) = chan("ram_wr_req_huffman_jump_table"); + let (ram_wr_resp_huffman_jump_table_s, ram_wr_resp_huffman_jump_table_r) = chan("ram_wr_resp_huffman_jump_table"); + spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_jump_table_r, ram_rd_resp_huffman_jump_table_s, ram_wr_req_huffman_jump_table_r, ram_wr_resp_huffman_jump_table_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + huffman_jump_table_axi_ar_r, huffman_jump_table_axi_r_s, + ram_rd_req_huffman_jump_table_s, ram_rd_resp_huffman_jump_table_r + ); + + // Mock RAM for HuffmanWeights header decoder MemReader + let (ram_rd_req_huffman_weights_header_s, ram_rd_req_huffman_weights_header_r) = chan("ram_rd_req_huffman_weights_header"); + let (ram_rd_resp_huffman_weights_header_s, ram_rd_resp_huffman_weights_header_r) = chan("ram_rd_resp_huffman_weights_header"); + let (ram_wr_req_huffman_weights_header_s, ram_wr_req_huffman_weights_header_r) = chan("ram_wr_req_huffman_weights_header"); + let (ram_wr_resp_huffman_weights_header_s, ram_wr_resp_huffman_weights_header_r) = chan("ram_wr_resp_huffman_weights_header"); + spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_header_r, ram_rd_resp_huffman_weights_header_s, ram_wr_req_huffman_weights_header_r, ram_wr_resp_huffman_weights_header_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + huffman_weights_header_axi_ar_r, huffman_weights_header_axi_r_s, + ram_rd_req_huffman_weights_header_s, ram_rd_resp_huffman_weights_header_r + ); + + // Mock RAM for HuffmanWeights raw decoder MemReader + let (ram_rd_req_huffman_weights_raw_s, ram_rd_req_huffman_weights_raw_r) = chan("ram_rd_req_huffman_weights_raw"); + let (ram_rd_resp_huffman_weights_raw_s, ram_rd_resp_huffman_weights_raw_r) = chan("ram_rd_resp_huffman_weights_raw"); + let (ram_wr_req_huffman_weights_raw_s, ram_wr_req_huffman_weights_raw_r) = chan("ram_wr_req_huffman_weights_raw"); + let (ram_wr_resp_huffman_weights_raw_s, ram_wr_resp_huffman_weights_raw_r) = chan("ram_wr_resp_huffman_weights_raw"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_raw_r, ram_rd_resp_huffman_weights_raw_s, ram_wr_req_huffman_weights_raw_r, ram_wr_resp_huffman_weights_raw_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + huffman_weights_raw_axi_ar_r, huffman_weights_raw_axi_r_s, + ram_rd_req_huffman_weights_raw_s, ram_rd_resp_huffman_weights_raw_r + ); + + // Mock RAM for HuffmanWeights fse decoder MemReader + let (ram_rd_req_huffman_weights_fse_s, ram_rd_req_huffman_weights_fse_r) = chan("ram_rd_req_huffman_weights_fse"); + let (ram_rd_resp_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r) = chan("ram_rd_resp_huffman_weights_fse"); + let (ram_wr_req_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r) = chan("ram_wr_req_huffman_weights_fse"); + let (ram_wr_resp_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r) = chan("ram_wr_resp_huffman_weights_fse"); + spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_fse_r, ram_rd_resp_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r, ram_wr_resp_huffman_weights_fse_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + huffman_weights_fse_axi_ar_r, huffman_weights_fse_axi_r_s, + ram_rd_req_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r + ); + + // Huffman weigths memory spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_DATA_WIDTH, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_SIZE, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_INITIALIZED, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ASSERT_VALID_READ, + TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ADDR_WIDTH, + > ( + huffman_lit_weights_mem_rd_req_r, huffman_lit_weights_mem_rd_resp_s, + huffman_lit_weights_mem_wr_req_r, huffman_lit_weights_mem_wr_resp_s + ); + + // Huffman prescan memory spawn ram::RamModel< - literals_buffer::RAM_DATA_WIDTH, TEST_RAM_SIZE, literals_buffer::RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); + TEST_HUFFMAN_PRESCAN_RAM_MODEL_DATA_WIDTH, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_SIZE, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_INITIALIZED, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_ASSERT_VALID_READ, + TEST_HUFFMAN_PRESCAN_RAM_MODEL_ADDR_WIDTH + > ( + huffman_lit_prescan_mem_rd_req_r, huffman_lit_prescan_mem_rd_resp_s, + huffman_lit_prescan_mem_wr_req_r, huffman_lit_prescan_mem_wr_resp_s + ); ( terminator, - literals_ctrl_s, literals_data_s, - literals_buf_ctrl_s, literals_r, + ctrl_req_s, ctrl_resp_r, ctrl_header_r, + buf_ctrl_s, buf_out_r, print_start_s, print_finish_r, + ram_wr_req_header_s, ram_wr_resp_header_r, + ram_wr_req_raw_s, ram_wr_resp_raw_r, + ram_wr_req_huffman_s, ram_wr_resp_huffman_r, + ram_wr_req_huffman_jump_table_s, ram_wr_resp_huffman_jump_table_r, + ram_wr_req_huffman_weights_header_s, ram_wr_resp_huffman_weights_header_r, + ram_wr_req_huffman_weights_raw_s, ram_wr_resp_huffman_weights_raw_r, + ram_wr_req_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r ) } init { } next (state: ()) { + const TEST_MEMORY: AxiRamWrReq[21] = [ + // Literals #0 (RAW; 8 bytes) + // Header: 0x40 + AxiRamWrReq { addr: AxiRamAddr:0x0, data: AxiRamData:0x5734_65A6_DB5D_B040, mask: AxiRamMask:0xFF }, // AXI addr: 0x0 + AxiRamWrReq { addr: AxiRamAddr:0x1, data: AxiRamData:0x16, mask: AxiRamMask:0xFF }, // AXI addr: 0x8 + + // Literals #1 (RLE; 4 bytes) + // Header: 0x21 + AxiRamWrReq { addr: AxiRamAddr:0x2, data: AxiRamData:0x2321, mask: AxiRamMask:0xFF }, // AXI addr: 0x10 + + // Literals #2 (RLE; 2 bytes) + // Header: 0x11 + AxiRamWrReq { addr: AxiRamAddr:0x4, data: AxiRamData:0x3511, mask: AxiRamMask:0xFF }, // AXI addr: 0x20 + + // Literals #3 (RAW; 15 bytes) + // Header: 0x78 + AxiRamWrReq { addr: AxiRamAddr:0x6, data: AxiRamData:0xFB41_C67B_6053_7078, mask: AxiRamMask:0xFF }, // AXI addr: 0x30 + AxiRamWrReq { addr: AxiRamAddr:0x7, data: AxiRamData:0x9B0F_9CE1_BAA9_6D4C, mask: AxiRamMask:0xFF }, // AXI addr: 0x38 + + // Literals #4 (Huffman; 6 bytes) + // Header: 0x01_80_42 (0b0000000110_0000000100_00_10) + AxiRamWrReq { addr: AxiRamAddr:0x10, data: (u8:0b0000_0001 ++ u24:0x010234 ++ u8:0x85 ++ u24:0x01_80_42) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x80 + AxiRamWrReq { addr: AxiRamAddr:0x11, data: u8:0b00001_1_01 as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x88 + + // Literals #5 (RLE; 12 bytes) + // Header: 0x61 + AxiRamWrReq { addr: AxiRamAddr:0x20, data: AxiRamData:0x5A61, mask: AxiRamMask:0xFF }, // AXI addr: 0x100 + + // Literals #6 (Huffman; 4 bytes) + // Header: 0x00_80_43 (0b0000000010_0000000100_00_11) + AxiRamWrReq { addr: AxiRamAddr:0x30, data: (u16:0b00001_0001_0000_01_1 ++ u24:0x00_80_43) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x180 + + // Literals #7 (RLE; 0 bytes) + // Header: 0x01 + AxiRamWrReq { addr: AxiRamAddr:0x40, data: AxiRamData:0xFF01, mask: AxiRamMask:0xFF }, // AXI addr: 0x200 + + // Literals #8 (Huffman; 18 bytes) + // Header: 0x04_81_06 (0b0000010010_0000010010_01_10) + AxiRamWrReq { addr: AxiRamAddr:0x50, data: (u8:0x02 ++ u24:0x010234 ++ u8:0x85 ++ u24:0x04_81_06) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x280 + AxiRamWrReq { addr: AxiRamAddr:0x51, data: (u8:0b0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u40:0x0002_0002_00) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x288 + AxiRamWrReq { addr: AxiRamAddr:0x52, data: (u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u8:0b00001_1_01) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 290 + + // Literals #9 (RAW; 31 bytes) + // Header: 0xF8 + AxiRamWrReq { addr: AxiRamAddr:0x60, data: AxiRamData:0x943E_9618_34C2_47F8, mask: AxiRamMask:0xFF }, // AXI addr: 0x300 + AxiRamWrReq { addr: AxiRamAddr:0x61, data: AxiRamData:0x02D0_E8D7_289A_BE60, mask: AxiRamMask:0xFF }, // AXI addr: 0x308 + AxiRamWrReq { addr: AxiRamAddr:0x62, data: AxiRamData:0x64C3_8BE1_FA8D_12BC, mask: AxiRamMask:0xFF }, // AXI addr: 0x310 + AxiRamWrReq { addr: AxiRamAddr:0x63, data: AxiRamData:0x1963_F1CE_21C2_94F8, mask: AxiRamMask:0xFF }, // AXI addr: 0x318 + + // Literals #10 (Huffman; 15 bytes) + // Header: 0x03_80_E7 (0b0000001110_0000001110_01_11) + AxiRamWrReq { addr: AxiRamAddr:0x70, data: (u40:0x02_0002_0002 ++ u24:0x03_80_E7) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x350 + AxiRamWrReq { addr: AxiRamAddr:0x71, data: (u8:0b0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u8:0x00) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x358 + AxiRamWrReq { addr: AxiRamAddr:0x72, data: u8:0b00001_1_01 as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x358 + ]; + + const TEST_CTRL: CtrlReq[11] = [ + CtrlReq {addr: AxiAddr:0x0, literals_last: false}, + CtrlReq {addr: AxiAddr:0x10, literals_last: false}, + CtrlReq {addr: AxiAddr:0x20, literals_last: false}, + CtrlReq {addr: AxiAddr:0x30, literals_last: true}, + CtrlReq {addr: AxiAddr:0x80, literals_last: true}, + CtrlReq {addr: AxiAddr:0x100, literals_last: false}, + CtrlReq {addr: AxiAddr:0x180, literals_last: true}, + CtrlReq {addr: AxiAddr:0x200, literals_last: false}, + CtrlReq {addr: AxiAddr:0x280, literals_last: true}, + CtrlReq {addr: AxiAddr:0x300, literals_last: true}, + CtrlReq {addr: AxiAddr:0x380, literals_last: true}, + ]; + + const TEST_EXPECTED_RESP: CtrlResp[11] = [ + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + CtrlResp {status: CtrlStatus::OKAY}, + ]; + + const TEST_BUF_CTRL: LiteralsBufferCtrl[10] = [ + LiteralsBufferCtrl {length: u32:8, last: false}, + LiteralsBufferCtrl {length: u32:4 , last: false}, + LiteralsBufferCtrl {length: u32:1 , last: false}, + LiteralsBufferCtrl {length: u32:16, last: true}, + LiteralsBufferCtrl {length: u32:4, last: true}, + LiteralsBufferCtrl {length: u32:12, last: false}, + LiteralsBufferCtrl {length: u32:4, last: true}, + LiteralsBufferCtrl {length: u32:16, last: true}, + LiteralsBufferCtrl {length: u32:31, last: true}, + LiteralsBufferCtrl {length: u32:16, last: true}, + ]; + + const TEST_EXPECTED_LITERALS: SequenceExecutorPacket[17] = [ + // Literals #0 (RAW) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x1657_3465_A6DB_5DB0, + last: true + }, + // Literals #1 (RLE) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0x2323_2323, + last: true + }, + // Literals #2 (RLE) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0x35, + last: false + }, + // Literals #3 (RAW) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xFB41_C67B_6053_7035, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x9B0F_9CE1_BAA9_6D4C, + last: true + }, + // Literals #4 (Huffman) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0x0504_0100, + last: true + }, + // Literals #5 (RLE) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x5A5A_5A5A_5A5A_5A5A, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0x5A5A_5A5A, + last: true + }, + // Literals #6 (Huffman) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:4, + content: CopyOrMatchContent:0x0001_0405, + last: true + }, + // Literals #7 (RLE) + // EMPTY + // Literals #8 (Huffman) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x0504_0100_0504_0100, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x0504_0100_0504_0100, + last: true + }, + // Literals #9 (RAW) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x6094_3E96_1834_C247, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xBC02_D0E8_D728_9ABE, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0xF864_C38B_E1FA_8D12, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:7, + content: CopyOrMatchContent:0x19_63F1_CE21_C294, + last: true + }, + // Literals #10 (Huffman) + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x0504_0100_0504_0100, + last: false + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:8, + content: CopyOrMatchContent:0x0504_0100_0504_0100, + last: true + }, + ]; + let tok = join(); - // send literals - let tok = for ((i, test_data), tok): ((u32, LiteralsData), token) in enumerate(TEST_DATA) { - let tok = send(tok, literals_data_s, test_data); - trace_fmt!("Sent #{} literals data, {:#x}", i + u32:1, test_data); + + trace_fmt!("Filling system memory mock"); + let tok = for ((i, mem_req), tok):((u32, AxiRamWrReq), token) in enumerate(TEST_MEMORY) { + trace_fmt!("Sent memory write request #{}: {:#x}", i + u32:1, mem_req); + let tok = send(tok, ram_wr_req_header_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_header_r); + let tok = send(tok, ram_wr_req_raw_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_raw_r); + let tok = send(tok, ram_wr_req_huffman_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_r); + let tok = send(tok, ram_wr_req_huffman_jump_table_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_jump_table_r); + let tok = send(tok, ram_wr_req_huffman_weights_header_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_header_r); + let tok = send(tok, ram_wr_req_huffman_weights_raw_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_raw_r); + let tok = send(tok, ram_wr_req_huffman_weights_fse_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_r); tok }(tok); - // send ctrl - let tok = for ((i, test_ctrl), tok): ((u32, LiteralsPathCtrl), token) in enumerate(TEST_CTRL) { - let tok = send(tok, literals_ctrl_s, test_ctrl); - trace_fmt!("Sent #{} literals ctrl, {:#x}", i + u32:1, test_ctrl); + assert_eq(array_size(TEST_CTRL), array_size(TEST_EXPECTED_RESP)); + + trace_fmt!("Sending literals decoding requests"); + let tok = for ((i, test_ctrl), tok): ((u32, CtrlReq), token) in enumerate(TEST_CTRL) { + let tok = send(tok, ctrl_req_s, test_ctrl); + trace_fmt!("Sent #{} literals decoding request: {:#x}", i + u32:1, test_ctrl); + let (tok, resp) = recv(tok, ctrl_resp_r); + trace_fmt!("Received #{} literals decoding response {:#x}", i + u32:1, resp); + assert_eq(TEST_EXPECTED_RESP[i], resp); tok }(tok); - // send buffer ctrl + trace_fmt!("Sending literals buffer requests"); let tok = for ((i, test_buf_ctrl), tok): ((u32, LiteralsBufferCtrl), token) in enumerate(TEST_BUF_CTRL) { - let tok = send(tok, literals_buf_ctrl_s, test_buf_ctrl); - trace_fmt!("Sent #{} ctrl {:#x}", i + u32:1, test_buf_ctrl); + let tok = send(tok, buf_ctrl_s, test_buf_ctrl); + trace_fmt!("Sent #{} literals buffer request {:#x}", i + u32:1, test_buf_ctrl); tok }(tok); // receive and check packets let tok = for ((i, test_exp_literals), tok): ((u32, SequenceExecutorPacket), token) in enumerate(TEST_EXPECTED_LITERALS) { - let (tok, literals) = recv(tok, literals_r); + let (tok, literals) = recv(tok, buf_out_r); trace_fmt!("Received #{} literals packet {:#x}", i + u32:1, literals); + trace_fmt!("Expected {:#x}", test_exp_literals); assert_eq(test_exp_literals, literals); tok }(tok); - // print RAM content - let tok = send(tok, print_start_s, ()); - let (tok, _) = recv(tok, print_finish_r); + //// print RAM content + //let tok = send(tok, print_start_s, ()); + //let (tok, _) = recv(tok, print_finish_r); send(tok, terminator, true); } @@ -572,7 +1904,6 @@ proc LiteralsDecoder_test { // config (terminator: chan out) { // let (literals_ctrl_s, literals_ctrl_r) = chan("literals_ctrl"); -// let (literals_data_s, literals_data_r) = chan("literals_data"); // let (literals_buf_ctrl_s, literals_buf_ctrl_r) = chan("literals_buf_ctrl"); // let (literals_s, literals_r) = chan("literals"); @@ -582,7 +1913,7 @@ proc LiteralsDecoder_test { // let (ram_wr_resp_s, ram_wr_resp_r) = chan[literals_buffer::RAM_NUM]("ram_wr_resp"); // spawn LiteralsDecoder( -// literals_ctrl_r, literals_data_r, +// literals_ctrl_r, // literals_buf_ctrl_r, literals_s, // ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], // ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], diff --git a/xls/modules/zstd/literals_dispatcher.x b/xls/modules/zstd/literals_dispatcher.x deleted file mode 100644 index 39fe949321..0000000000 --- a/xls/modules/zstd/literals_dispatcher.x +++ /dev/null @@ -1,243 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// This file contains the implementation of LiteralsDispatcher responsible for -// dispatching ZSTD Literals. More information about Literals' format can be found in: -// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.1 - -import xls.modules.zstd.common; - -type LiteralsPathCtrl = common::LiteralsPathCtrl; -type LiteralsData = common::LiteralsData; -type LiteralsDataWithSync = common::LiteralsDataWithSync; -type RleLiteralsData = common::RleLiteralsData; -type LiteralType = common::LiteralType; -type Streams = common::Streams; -type DecompressedSize = common::DecompressedSize; - -type RleLitData = common::RleLitData; -type RleLitRepeat = common::RleLitRepeat; -type LitData = common::LitData; -type LitLength = common::LitLength; -type LitID = common::LitID; - -struct LiteralsDispatcherState { - // literals type received from ctrl channel - literals_type: LiteralType, - // number of literals to be read. The initial value is received - // from ctrl channel and decreased after each read from literals channel - left_to_read: DecompressedSize, - literals_id: LitID, -} - -pub proc LiteralsDispatcher { - literals_ctrl_r: chan in; - literals_data_r: chan in; - raw_literals_s: chan out; - rle_literals_s: chan out; - huff_literals_s: chan out; - - config ( - literals_ctrl_r: chan in, - literals_data_r: chan in, - raw_literals_s: chan out, - rle_literals_s: chan out, - huff_literals_s: chan out, - ) { - ( - literals_ctrl_r, - literals_data_r, - raw_literals_s, - rle_literals_s, - huff_literals_s, - ) - } - - init { zero!() } - - next(state: LiteralsDispatcherState ) { - - let tok = join(); - let do_recv_ctrl = (state.left_to_read == DecompressedSize:0); - let (tok, literals_path_ctrl) = recv_if(tok, literals_ctrl_r, do_recv_ctrl, zero!()); - - let (literals_type, left_to_read) = if do_recv_ctrl { - (literals_path_ctrl.literals_type, literals_path_ctrl.decompressed_size) - } else { - (state.literals_type, state.left_to_read) - }; - - // RLE literals consist of single byte - let (tok, literals_data) = recv(tok, literals_data_r); - - let is_empty = left_to_read == DecompressedSize:0 && !literals_data.last; - - let left_to_read = if (literals_type == LiteralType::RLE) { - DecompressedSize:0 - } else { - left_to_read - (literals_data.length as DecompressedSize) - }; - - let literals_data = LiteralsDataWithSync { - data: literals_data.data, - length: literals_data.length, - last: literals_data.last, - id: state.literals_id, - literals_last: true - }; - - let tok = send_if(tok, raw_literals_s, LiteralType::RAW == literals_type, literals_data); - - let rle_literals_data = RleLiteralsData { - data: (literals_data.data as u8), - repeat: literals_path_ctrl.decompressed_size, - id: if (is_empty) { LitID:0 } else { literals_data.id }, - last: literals_data.last, - }; - let tok = send_if(tok, rle_literals_s, LiteralType::RLE == literals_type, rle_literals_data); - - let do_send_huff = ( - LiteralType::COMP == literals_type || LiteralType::COMP_4 == literals_type || - LiteralType::TREELESS == literals_type || LiteralType::TREELESS_4 == literals_type - ); - assert!(!do_send_huff, "Huffmann coding not implemented yet"); - let tok = send_if(tok, huff_literals_s, false, zero!()); - - // empty RLE literals with last not set will not be sent by RLE decoder to buffer - let literals_id = if (is_empty && state.literals_type == LiteralType::RLE) { - state.literals_id - } else { - state.literals_id + LitID:1 - }; - LiteralsDispatcherState { - literals_type: literals_type, - left_to_read: left_to_read, - literals_id: literals_id, - } - } -} - -#[test_proc] -proc LiteralsDispatcher_test { - terminator: chan out; - literals_ctrl_s: chan out; - literals_data_s: chan out; - raw_literals_r: chan in; - rle_literals_r: chan in; - huff_literals_r: chan in; - - config(terminator: chan out) { - let (literals_ctrl_s, literals_ctrl_r) = chan("literals_ctrl"); - let (literals_data_s, literals_data_r) = chan("literals_data"); - let (raw_literals_s, raw_literals_r) = chan("raw_literals"); - let (rle_literals_s, rle_literals_r) = chan("rle_literals"); - let (huff_literals_s, huff_literals_r) = chan("huff_literals"); - - spawn LiteralsDispatcher( - literals_ctrl_r, - literals_data_r, - raw_literals_s, - rle_literals_s, - huff_literals_s, - ); - - ( - terminator, - literals_ctrl_s, - literals_data_s, - raw_literals_r, - rle_literals_r, - huff_literals_r, - ) - } - - init { } - - next(state: ()) { - let tok = join(); - let test_ctrl: LiteralsPathCtrl[6] = [ - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:8, literals_type: LiteralType::RAW}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:4, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:13, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:15, literals_type: LiteralType::RAW}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:123, literals_type: LiteralType::RLE}, - LiteralsPathCtrl {data_conf: zero!(), decompressed_size: DecompressedSize:31, literals_type: LiteralType::RAW}, - ]; - let test_data: LiteralsData[10] = [ - // 0. RAW - LiteralsData {data: LitData:0x1657_3465_A6DB_5DB0, length: LitLength:8, last: false}, - // 1. RLE - LiteralsData {data: LitData:0x23, length: LitLength:1, last: false}, - // 2. RLE - LiteralsData {data: LitData:0x35, length: LitLength:1, last: true}, - // 3. RAW - LiteralsData {data: LitData:0x4CFB_41C6_7B60_5370, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0x009B_0F9C_E1BA_A96D, length: LitLength:7, last: false}, - // 4. RLE - LiteralsData {data: LitData:0x5A, length: LitLength:1, last: false}, - // 5. RAW - LiteralsData {data: LitData:0x6094_3E96_1834_C247, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0xBC02_D0E8_D728_9ABE, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0xF864_C38B_E1FA_8D12, length: LitLength:8, last: false}, - LiteralsData {data: LitData:0xFC19_63F1_CE21_C294, length: LitLength:7, last: true}, - ]; - let expected_raw: LiteralsDataWithSync[7] = [ - // 0. - LiteralsDataWithSync {data: LitData:0x1657_3465_A6DB_5DB0, length: LitLength:8, id: LitID:0, last: false, literals_last: true}, - // 3. - LiteralsDataWithSync {data: LitData:0x4CFB_41C6_7B60_5370, length: LitLength:8, id: LitID:3, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0x009B_0F9C_E1BA_A96D, length: LitLength:7, id: LitID:4, last: false, literals_last: true}, - // 5. - LiteralsDataWithSync {data: LitData:0x6094_3E96_1834_C247, length: LitLength:8, id: LitID:6, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0xBC02_D0E8_D728_9ABE, length: LitLength:8, id: LitID:7, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0xF864_C38B_E1FA_8D12, length: LitLength:8, id: LitID:8, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0xFC19_63F1_CE21_C294, length: LitLength:7, id: LitID:9, last: true, literals_last: true}, - ]; - let expected_rle: RleLiteralsData[3] = [ - // 1. - RleLiteralsData {data: RleLitData:0x23, repeat: RleLitRepeat:4, id: LitID:1, last: false}, - // 2. - RleLiteralsData {data: RleLitData:0x35, repeat: RleLitRepeat:13, id: LitID:2, last: true}, - // 4. - RleLiteralsData {data: RleLitData:0x5A, repeat: RleLitRepeat:123, id: LitID:5, last: false}, - ]; - let tok = for ((counter, test_ctrl), tok): ((u32, LiteralsPathCtrl), token) in enumerate(test_ctrl) { - let tok = send(tok, literals_ctrl_s, test_ctrl); - trace_fmt!("Send #{} literals ctrl, {:#x}", counter + u32:1, test_ctrl); - (tok) - }(tok); - - let tok = for ((counter, test_data), tok): ((u32, LiteralsData), token) in enumerate(test_data) { - let tok = send(tok, literals_data_s, test_data); - trace_fmt!("Send #{} literals data, {:#x}", counter + u32:1, test_data); - (tok) - }(tok); - - let tok_1 = for ((counter, expected_raw), tok_1): ((u32, LiteralsDataWithSync), token) in enumerate(expected_raw) { - let (tok_1, raw) = recv(tok_1, raw_literals_r); - trace_fmt!("Recv #{} raw literals, {:#x}", counter + u32:1, raw); - assert_eq(expected_raw, raw); - (tok_1) - }(tok); - - let tok_2 = for ((counter, expected_rle), tok_2): ((u32, RleLiteralsData), token) in enumerate(expected_rle) { - let (tok_2, rle) = recv(tok_2, rle_literals_r); - trace_fmt!("Recv #{} rle literals, {:#x}", counter + u32:1, rle); - assert_eq(expected_rle, rle); - (tok_2) - }(tok); - - send(tok, terminator, true); - } -} diff --git a/xls/modules/zstd/memory/axi_ram.x b/xls/modules/zstd/memory/axi_ram.x index 9683e61fc6..688fe2c171 100644 --- a/xls/modules/zstd/memory/axi_ram.x +++ b/xls/modules/zstd/memory/axi_ram.x @@ -118,7 +118,7 @@ proc AxiRamReaderRequester< // send RAM read reqest let addr_valid = state.addr < ((RAM_SIZE * RAM_DATA_W_DIV8) as uN[AXI_ADDR_W]); - let addr = (state.addr / RAM_DATA_W_DIV8) as uN[RAM_ADDR_W]; + let addr = (state.addr / RAM_DATA_W_DIV8 as uN[AXI_ADDR_W]) as uN[RAM_ADDR_W]; let do_read_from_ram = ( (state.status == Status::READ_BURST) && @@ -152,7 +152,7 @@ proc AxiRamReaderRequester< } else { ( arsize_bits, - ((state.addr % RAM_DATA_W_DIV8) << u32:3) as uN[RAM_DATA_W_PLUS1_LOG2], + ((state.addr % RAM_DATA_W_DIV8 as uN[AXI_ADDR_W]) << u32:3) as uN[RAM_DATA_W_PLUS1_LOG2], ) }; @@ -190,7 +190,7 @@ proc AxiRamReaderRequester< let addr = match state.ar_bundle.burst { AxiAxBurst::FIXED => state.addr, AxiAxBurst::INCR => state.addr + incr, - AxiAxBurst::WRAP => if ((state.addr + incr) >= (RAM_SIZE * RAM_DATA_W_DIV8)) { + AxiAxBurst::WRAP => if ((state.addr + incr) as u32 >= (RAM_SIZE * RAM_DATA_W_DIV8)) { uN[AXI_ADDR_W]:0 } else { state.addr + incr @@ -424,7 +424,7 @@ proc AxiRamReaderInstWithEmptyWrites { ) } - next(state: ()) { + next(state: ()) { send_if(join(), wr_req_s, false, zero!()); recv_if(join(), wr_resp_r, false, zero!()); } diff --git a/xls/modules/zstd/raw_literals_dec.x b/xls/modules/zstd/raw_literals_dec.x index 1dbb971785..d53d5349f1 100644 --- a/xls/modules/zstd/raw_literals_dec.x +++ b/xls/modules/zstd/raw_literals_dec.x @@ -16,66 +16,283 @@ // Packets of 0 length are not passed further and a warning is log instead. import xls.modules.zstd.common; +import xls.modules.zstd.memory.mem_reader as mem_reader; type LiteralsDataWithSync = common::LiteralsDataWithSync; type LitData = common::LitData; type LitLength = common::LitLength; +type LitID = common::LitID; -pub proc RawLiteralsDecoder { - dispatcher_r: chan in; - buffer_s: chan out; +pub struct RawLiteralsDecoderReq { + id: u32, + addr: uN[ADDR_W], + length: uN[ADDR_W], + literals_last: bool, +} + +pub enum RawLiteralsDecoderStatus: u1 { + OKAY = 0, + ERROR = 1, +} + +pub struct RawLiteralsDecoderResp { + status: RawLiteralsDecoderStatus, +} + +struct RawLiteralsDecoderState { + id: u32, + literals_last: bool, +} - config(dispatcher_r: chan in, buffer_s: chan out) { - (dispatcher_r, buffer_s) +pub proc RawLiteralsDecoder { + type Req = RawLiteralsDecoderReq; + type Resp = RawLiteralsDecoderResp; + type Output = LiteralsDataWithSync; + type State = RawLiteralsDecoderState; + type Status = RawLiteralsDecoderStatus; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + // decoder input + req_r: chan in; + resp_s: chan out; + + // decoder output + output_s: chan out; + + // memory interface + mem_req_s: chan out; + mem_resp_r: chan in; + + init { zero!() } + + config( + req_r: chan in, + resp_s: chan out, + output_s: chan out, + + mem_req_s: chan out, + mem_resp_r: chan in, + ) { + ( + req_r, resp_s, output_s, + mem_req_s, mem_resp_r, + ) } - init { } + next(state: State) { + let tok0 = join(); - next(state: ()) { - let tok = join(); - let (tok, resp) = recv(tok, dispatcher_r); - let do_send = if resp.length == LitLength:0 { - trace_fmt!("[WARNING] Packet of 0 length received by RawLiteralsDecoder"); - false + // receive request + let (tok1_0, req, req_valid) = recv_non_blocking(tok0, req_r, zero!()); + + // update ID and last in state + let state = if req_valid { + State { id: req.id, literals_last: req.literals_last} + } else { state }; + + // send memory read request + let req = MemReaderReq { addr: req.addr, length: req.length }; + let tok2_0 = send_if(tok1_0, mem_req_s, req_valid, req); + + // receive memory read response + let (tok1_1, mem_resp, mem_resp_valid) = recv_non_blocking(tok0, mem_resp_r, zero!()); + let mem_resp_error = (mem_resp.status != MemReaderStatus::OKAY); + + // prepare output data, decoded RAW block is always a literal + let output_data = Output { + last: mem_resp.last, + literals_last: state.literals_last, + id: state.id as LitID, + data: checked_cast(mem_resp.data), + length: checked_cast(mem_resp.length), + }; + + // send output data + let mem_resp_correct = mem_resp_valid && !mem_resp_error; + let tok2_1 = send_if(tok1_1, output_s, mem_resp_correct, output_data); + + // send response after block end + let resp = if mem_resp_correct { + Resp { status: Status::OKAY } } else { - true + Resp { status: Status::ERROR } }; - let tok = send_if(tok, buffer_s, do_send, resp); + + let do_send_resp = mem_resp_valid && mem_resp.last; + let tok2_2 = send_if(tok1_1, resp_s, do_send_resp, resp); + + state + } +} + +const INST_DATA_W = u32:64; +const INST_ADDR_W = u32:16; + +pub proc RawLiteralsDecoderInst { + type Req = RawLiteralsDecoderReq; + type Resp = RawLiteralsDecoderResp; + type Output = LiteralsDataWithSync; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + init { () } + + config( + req_r: chan in, + resp_s: chan out, + output_s: chan out, + + mem_req_s: chan out, + mem_resp_r: chan in, + ) { + spawn RawLiteralsDecoder( + req_r, resp_s, output_s, mem_req_s, mem_resp_r + ); } + + next(state: ()) {} } +const TEST_DATA_W = u32:64; +const TEST_ADDR_W = u32:16; + #[test_proc] proc RawLiteralsDecoderTest { + type Req = RawLiteralsDecoderReq; + type Resp = RawLiteralsDecoderResp; + type Output = LiteralsDataWithSync; + type State = RawLiteralsDecoderState; + type Status = RawLiteralsDecoderStatus; + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemReaderStatus = mem_reader::MemReaderStatus; + + type Data = uN[TEST_DATA_W]; + type Addr = uN[TEST_ADDR_W]; + type Length = uN[TEST_ADDR_W]; + terminator: chan out; - dispatcher_s: chan out; - buffer_r: chan in; + // decoder input + req_s: chan out; + resp_r: chan in; + + // decoder output + output_r: chan in; + + // memory interface + mem_req_r: chan in; + mem_resp_s: chan out; config(terminator: chan out) { - let (dispatcher_s, dispatcher_r) = chan("dispatcher"); - let (buffer_s, buffer_r) = chan("buffer"); + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (output_s, output_r) = chan("output"); - spawn RawLiteralsDecoder(dispatcher_r, buffer_s); + let (mem_req_s, mem_req_r) = chan("mem_req"); + let (mem_resp_s, mem_resp_r) = chan("mem_resp"); - (terminator, dispatcher_s, buffer_r) + spawn RawLiteralsDecoder( + req_r, resp_s, output_s, mem_req_s, mem_resp_r + ); + + (terminator, req_s, resp_r, output_r, mem_req_r, mem_resp_s) } init { } next(state: ()) { + let tok = join(); - let data = LiteralsDataWithSync { data: LitData:0x11_22_33_44_55_66, length: LitLength:6, id: u32:0, last: true, literals_last: true }; - let tok = send(tok, dispatcher_s, data); - let (tok, resp) = recv(tok, buffer_r); - assert_eq(resp, data); - let empty_data = LiteralsDataWithSync { data: LitData:0, length: LitLength:0, id: u32:0, last: true, literals_last: true }; - let tok = send(tok, dispatcher_s, empty_data); + // Test 0 + let req = Req { id: u32:0, literals_last: false, addr: Addr:0, length: Length:8 }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr: Addr:0, length: Length:8 }); - // Resend the first packet to verify that the empty packet is dropped correctly. - let tok = send(tok, dispatcher_s, data); - let (tok, resp) = recv(tok, buffer_r); - assert_eq(resp, data); + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0x1122_3344, + length: Length:8, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + last: true, + literals_last: false, + id: u32:0, + data: Data:0x1122_3344, + length: LitLength:8, + }); + + // Test 1 + let req = Req { id: u32:1, literals_last: true, addr: Addr:0x1001, length: Length:15 }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr: Addr:0x1001, length: Length:15 }); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0x1122_3344_5566_7788, + length: Length:8, + last: false + }; + let tok = send(tok, mem_resp_s, mem_resp); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0xAA_BBCC_DDEE_FF99, + length: Length:7, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + last: false, + literals_last: true, + id: u32:1, + data: Data:0x1122_3344_5566_7788, + length: LitLength:8, + }); + + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + last: true, + literals_last: true, + id: u32:1, + data: Data:0xAA_BBCC_DDEE_FF99, + length: LitLength:7, + }); + + // Test 2 + let req = Req {id: u32:2, literals_last: false, addr: Addr:0x2000, length: Length:0 }; + let tok = send(tok, req_s, req); + + let (tok, mem_req) = recv(tok, mem_req_r); + assert_eq(mem_req, MemReaderReq { addr: Addr:0x2000, length: Length:0 }); + + let mem_resp = MemReaderResp { + status: mem_reader::MemReaderStatus::OKAY, + data: Data:0x0, + length: Length:0, + last: true, + }; + let tok = send(tok, mem_resp_s, mem_resp); + let (tok, output) = recv(tok, output_r); + assert_eq(output, Output { + last: true, + literals_last: false, + id: u32:2, + data: Data:0x0, + length: LitLength:0, + }); - let tok = send(tok, terminator, true); + send(tok, terminator, true); } } diff --git a/xls/modules/zstd/rle_literals_dec.x b/xls/modules/zstd/rle_literals_dec.x index dda39f8208..7cff335387 100644 --- a/xls/modules/zstd/rle_literals_dec.x +++ b/xls/modules/zstd/rle_literals_dec.x @@ -19,390 +19,260 @@ import std; import xls.modules.zstd.common; -import xls.modules.rle.rle_dec; -import xls.modules.rle.rle_common; -const RLE_LITERALS_DATA_WIDTH = common::RLE_LITERALS_DATA_WIDTH; -const RLE_LITERALS_REPEAT_WIDTH = common::RLE_LITERALS_REPEAT_WIDTH; -const LITERALS_DATA_WIDTH = common::LITERALS_DATA_WIDTH; -const LITERALS_LENGTH_WIDTH = common::LITERALS_LENGTH_WIDTH; - -type RleInput = rle_common::CompressedData; -type RleOutput = rle_common::PlainData; -type RleLiteralsData = common::RleLiteralsData; type LiteralsDataWithSync = common::LiteralsDataWithSync; - type RleLitData = common::RleLitData; type RleLitRepeat = common::RleLitRepeat; type LitData = common::LitData; type LitID = common::LitID; type LitLength = common::LitLength; -struct LiteralsSyncData { - count: RleLitRepeat, - id: LitID, - last: bool, +pub enum RleLiteralsDecoderStatus: u1 { + OKAY = 0, } -proc RleDataPacker { - literals_data_r: chan in; - rle_data_s: chan out; - sync_s: chan out; - - config( - literals_data_r: chan in, - rle_data_s: chan out, - sync_s: chan out, - ) { - (literals_data_r, rle_data_s, sync_s) - } - - init { } +pub struct RleLiteralsDecoderReq { + id: u32, + symbol: u8, + length: RleLitRepeat, + literals_last: bool, +} - next(state: ()) { - let tok = join(); - let (tok, input) = recv(tok, literals_data_r); - let not_zero_repeat = (input.repeat != RleLitRepeat:0); - let rle_dec_data = RleInput { symbol: input.data, count: input.repeat, last: true }; - let data_tok = send_if(tok, rle_data_s, not_zero_repeat, rle_dec_data); - let sync_data = LiteralsSyncData { count: input.repeat, id: input.id, last: input.last }; - let sync_tok = send_if(data_tok, sync_s, not_zero_repeat || input.last, sync_data); - } +pub struct RleLiteralsDecoderResp { + status: RleLiteralsDecoderStatus } -#[test_proc] -proc RleDataPacker_test { - terminator: chan out; - in_s: chan out; - out_r: chan in; - sync_r: chan in; +struct RleLiteralsDecoderState { + req: RleLiteralsDecoderReq, + req_valid: bool, +} - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); - let (sync_s, sync_r) = chan("sync"); +pub proc RleLiteralsDecoder { + type Req = RleLiteralsDecoderReq; + type Resp = RleLiteralsDecoderResp; + type Output = LiteralsDataWithSync; - spawn RleDataPacker(in_r, out_s, sync_s); + type State = RleLiteralsDecoderState; - (terminator, in_s, out_r, sync_r) - } + req_r: chan in; + resp_s: chan out; + output_s: chan out; - init { } + config( req_r: chan in, + resp_s: chan out, + output_s: chan out, + ) { (req_r, resp_s, output_s) } - next(state: ()) { - let tok = join(); - let test_data: RleLiteralsData[5] = [ - RleLiteralsData {data: RleLitData:0xAB, repeat: RleLitRepeat:11, id: LitID:0, last: bool:0}, - RleLiteralsData {data: RleLitData:0xCD, repeat: RleLitRepeat:3, id: LitID:1, last: bool:0}, - RleLiteralsData {data: RleLitData:0x12, repeat: RleLitRepeat:16, id: LitID:2, last: bool:0}, - RleLiteralsData {data: RleLitData:0x34, repeat: RleLitRepeat:20, id: LitID:3, last: bool:0}, - RleLiteralsData {data: RleLitData:0x56, repeat: RleLitRepeat:2, id: LitID:4, last: bool:1}, - ]; + init { zero!() } - let tok = for ((counter, test_data), tok): ((u32, RleLiteralsData), token) in enumerate(test_data) { - let expected_data_out = RleInput { - symbol: test_data.data, - count: test_data.repeat, - last: true, - }; + next(state: State) { + const MAX_OUTPUT_SYMBOLS = (DATA_W / u32:8); + const MAX_LEN = MAX_OUTPUT_SYMBOLS as RleLitRepeat; - let expected_sync_out = LiteralsSyncData { - count: test_data.repeat, - id: test_data.id, - last: test_data.last, - }; + let tok0 = join(); - let tok = send(tok, in_s, test_data); - trace_fmt!("Send #{} rle literals data, {:#x}", counter + u32:1, test_data); + let (tok1, req) = recv_if(tok0, req_r, !state.req_valid, state.req); - let (tok, data_out) = recv(tok, out_r); - trace_fmt!("Received #{} rle input data, {:#x}", counter + u32:1, data_out); - assert_eq(data_out, expected_data_out); + let last = req.length <= MAX_LEN; + let length = if last { req.length } else { MAX_LEN }; + let data = unroll_for! (i, data): (u32, uN[DATA_W]) in range(u32:0, MAX_OUTPUT_SYMBOLS) { + bit_slice_update(data, i * u32:8, req.symbol) + }(uN[DATA_W]:0); - let (tok, sync_out) = recv(tok, sync_r); - trace_fmt!("Received #{} sync data, {:#x}", counter + u32:1, sync_out); - assert_eq(sync_out, expected_sync_out); + let output = Output { + last: last, + literals_last: req.literals_last, + id: req.id, + data: checked_cast(data), + length: checked_cast(length), + }; - (tok) - }(tok); + send_if(tok1, resp_s, last, zero!()); + send(tok1, output_s, output); - send(tok, terminator, true); + if last { + zero!() + } else { + let length = req.length - MAX_LEN; + State { + req: Req { length, ..req }, + req_valid: true, + } + } } } -struct BatchPackerState { - batch: LitData, - data_in_batch: LitLength, - count_left: RleLitRepeat, - sync_id: LitID, - sync_last: bool, -} - -// auxiliary variable used to replace multiplication with shifts -const_assert!(std::is_pow2(RLE_LITERALS_DATA_WIDTH)); -const RLE_LITERALS_DATA_WIDTH_SHIFT = std::clog2(RLE_LITERALS_DATA_WIDTH); +const INST_DATA_W = u32:64; -proc BatchPacker { - rle_data_r: chan in; - sync_r: chan in; - literals_data_s: chan out; +pub proc RleLiteralsDecoderInst { + type Req = RleLiteralsDecoderReq; + type Resp = RleLiteralsDecoderResp; + type Output = LiteralsDataWithSync; config( - rle_data_r: chan in, - sync_r: chan in, - literals_data_s: chan out, + req_r: chan in, + resp_s: chan out, + output_s: chan out, ) { - (rle_data_r, sync_r, literals_data_s) - } - - init { zero!() } - - next(state: BatchPackerState) { - let tok = join(); - let no_count_left = (state.count_left == RleLitRepeat:0); - let (tok, sync_data) = recv_if(tok, sync_r, no_count_left, zero!()); - let (count_left, sync_id, sync_last) = if (no_count_left) { - (sync_data.count, sync_data.id, sync_data.last) - } else { - (state.count_left, state.sync_id, state.sync_last) - }; - - let (literals_data, do_send_batch, state) = if (count_left != RleLitRepeat:0) { - let (tok, decoded_data) = recv(tok, rle_data_r); - - let data_in_batch = state.data_in_batch; - // shift batch and append new symbol - let shift = (data_in_batch as u32) << RLE_LITERALS_DATA_WIDTH_SHIFT; - - let batch = state.batch | ((decoded_data.symbol as LitData) << shift); - let data_in_batch = data_in_batch + LitLength:1; - // send batch if it is the last batch or it is full - let do_send_batch = ( - decoded_data.last - | (((data_in_batch as u32 + u32:1) << RLE_LITERALS_DATA_WIDTH_SHIFT) > LITERALS_DATA_WIDTH) - ); - let literals_data = LiteralsDataWithSync { - data: batch, - length: data_in_batch, - last: sync_last && decoded_data.last, - id: sync_id, - literals_last: decoded_data.last, - }; - - let state = if do_send_batch { - BatchPackerState { - count_left: count_left - RleLitRepeat:1, - sync_id: sync_id, - sync_last: sync_last, - ..zero!() - } - } else { - BatchPackerState { - batch: batch, - data_in_batch: data_in_batch, - count_left: count_left - RleLitRepeat:1, - sync_id: sync_id, - sync_last: sync_last, - } - }; - - (literals_data, do_send_batch, state) - } else if (sync_data.last) { - // handle empty literal with last set - ( - LiteralsDataWithSync {id: sync_id, last: true, literals_last: true, ..zero!()}, - true, - BatchPackerState { - count_left: count_left, - sync_id: sync_id, - sync_last: sync_last, - ..state - }, - ) - } else { - // handle empty literal with last not set - ( - zero!(), - false, - BatchPackerState { - count_left: count_left, - sync_id: sync_id, - sync_last: sync_last, - ..state - }, - ) - }; - - let data_tok = send_if(tok, literals_data_s, do_send_batch, literals_data); - - state - } -} - -#[test_proc] -proc BatchPacker_test { - terminator: chan out; - in_s: chan out; - sync_s: chan out; - out_r: chan in; - - config(terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (sync_s, sync_r) = chan("sync"); - let (out_s, out_r) = chan("out"); - - spawn BatchPacker(in_r, sync_r, out_s); - - (terminator, in_s, sync_s, out_r) + spawn RleLiteralsDecoder( + req_r, resp_s, output_s + ); } - init { } - - next(state: ()) { - let tok = join(); - let test_sync_data: LiteralsSyncData[4] = [ - LiteralsSyncData {count: RleLitRepeat:1, id: LitID:0, last: false}, - LiteralsSyncData {count: RleLitRepeat:8, id: LitID:1, last: false}, - LiteralsSyncData {count: RleLitRepeat:10, id: LitID:2, last: false}, - LiteralsSyncData {count: RleLitRepeat:13, id: LitID:3, last: true}, - ]; - let test_rle_data: RleOutput[32] = [ - // 1st literal - RleOutput {symbol: RleLitData:0x11, last: true}, - // 2nd literal - RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: false}, - RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: false}, - RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: false}, - RleOutput {symbol: RleLitData:0x22, last: false}, RleOutput {symbol: RleLitData:0x22, last: true}, - // 3rd literal - RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, - RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, - RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, - RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: false}, - RleOutput {symbol: RleLitData:0x33, last: false}, RleOutput {symbol: RleLitData:0x33, last: true}, - // 4th literal - RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, - RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, - RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, - RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, - RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, - RleOutput {symbol: RleLitData:0x44, last: false}, RleOutput {symbol: RleLitData:0x44, last: false}, - RleOutput {symbol: RleLitData:0x44, last: true}, - ]; - let test_out_data: LiteralsDataWithSync[6] = [ - LiteralsDataWithSync {data: LitData:0x0000_0000_0000_0011, length: LitLength:1, id: LitID:0, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0x2222_2222_2222_2222, length: LitLength:8, id: LitID:1, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, id: LitID:2, last: false, literals_last: false}, - LiteralsDataWithSync {data: LitData:0x0000_0000_0000_3333, length: LitLength:2, id: LitID:2, last: false, literals_last: true}, - LiteralsDataWithSync {data: LitData:0x4444_4444_4444_4444, length: LitLength:8, id: LitID:3, last: false, literals_last: false}, - LiteralsDataWithSync {data: LitData:0x0000_0044_4444_4444, length: LitLength:5, id: LitID:3, last: true, literals_last: true}, - ]; - - let tok = for ((counter, sync_data), tok): ((u32, LiteralsSyncData), token) in enumerate(test_sync_data) { - let tok = send(tok, sync_s, sync_data); - trace_fmt!("Sent #{} synchronization data, {:#x}", counter + u32:1, sync_data); - (tok) - }(tok); - - let tok = for ((counter, rle_data), tok): ((u32, RleOutput), token) in enumerate(test_rle_data) { - let tok = send(tok, in_s, rle_data); - trace_fmt!("Sent #{} rle data, {:#x}", counter + u32:1, rle_data); - (tok) - }(tok); - - let tok = for ((counter, expected_out_data), tok): ((u32, LiteralsDataWithSync), token) in enumerate(test_out_data) { - let (tok, out_data) = recv(tok, out_r); - trace_fmt!("Received #{} batched data, {:#x}", counter + u32:1, out_data); - assert_eq(out_data, expected_out_data); - (tok) - }(tok); + init { () } - send(tok, terminator, true); - } + next(state: ()) {} } -pub proc RleLiteralsDecoder { - input_r: chan in; - output_s: chan out; - - config(input_r: chan in, output_s: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("in"); - let (sync_s, sync_r) = chan("sync"); - - spawn RleDataPacker(input_r, in_s, sync_s); - spawn rle_dec::RunLengthDecoder(in_r, out_s); - spawn BatchPacker(out_r, sync_r, output_s); - - (input_r, output_s) - } - - init { } - - next(state: ()) { } -} +const TEST_DATA_W = u32:64; #[test_proc] proc RleLiteralsDecoder_test { + type Req = RleLiteralsDecoderReq; + type Resp = RleLiteralsDecoderResp; + type Output = LiteralsDataWithSync; + type Status = RleLiteralsDecoderStatus; + terminator: chan out; - in_s: chan out; - out_r: chan in; + req_s: chan out; + resp_r: chan in; + out_r: chan in; config (terminator: chan out) { - let (in_s, in_r) = chan("in"); - let (out_s, out_r) = chan("out"); + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (out_s, out_r) = chan("output"); - spawn RleLiteralsDecoder(in_r, out_s); + spawn RleLiteralsDecoder( + req_r, resp_s, out_s + ); - (terminator, in_s, out_r) + (terminator, req_s, resp_r, out_r) } - init { } + init { } next(state: ()) { let tok = join(); - let test_rle_data: RleLiteralsData[7] = [ - RleLiteralsData {data: RleLitData:0x11, repeat: RleLitRepeat:11, id: LitID:0, last: false}, - RleLiteralsData {data: RleLitData:0x22, repeat: RleLitRepeat:3, id: LitID:1, last: false}, - RleLiteralsData {data: RleLitData:0x33, repeat: RleLitRepeat:16, id: LitID:2, last: false}, - RleLiteralsData {data: RleLitData:0x44, repeat: RleLitRepeat:0, id: LitID:0, last: false}, - RleLiteralsData {data: RleLitData:0x55, repeat: RleLitRepeat:2, id: LitID:3, last: false}, - RleLiteralsData {data: RleLitData:0x66, repeat: RleLitRepeat:20, id: LitID:4, last: false}, - RleLiteralsData {data: RleLitData:0x00, repeat: RleLitRepeat:0, id: LitID:5, last: true}, + let test_rle_req: Req[6] = [ + Req {symbol: RleLitData:0x11, length: RleLitRepeat:11, id: LitID:0, literals_last: false}, + Req {symbol: RleLitData:0x22, length: RleLitRepeat:3, id: LitID:1, literals_last: false}, + Req {symbol: RleLitData:0x33, length: RleLitRepeat:16, id: LitID:2, literals_last: false}, + Req {symbol: RleLitData:0x55, length: RleLitRepeat:2, id: LitID:3, literals_last: false}, + Req {symbol: RleLitData:0x66, length: RleLitRepeat:20, id: LitID:4, literals_last: false}, + Req {symbol: RleLitData:0x00, length: RleLitRepeat:0, id: LitID:5, literals_last: true}, + ]; + let test_rle_resp: Resp[6] = [ + Resp {status: Status::OKAY}, + Resp {status: Status::OKAY}, + Resp {status: Status::OKAY}, + Resp {status: Status::OKAY}, + Resp {status: Status::OKAY}, + Resp {status: Status::OKAY}, ]; let test_out_data: LiteralsDataWithSync[10] = [ // 1st literal - LiteralsDataWithSync {data: LitData:0x1111_1111_1111_1111, length: LitLength:8, last: false, id: LitID:0, literals_last: false}, - LiteralsDataWithSync {data: LitData:0x0000_0000_0011_1111, length: LitLength:3, last: false, id: LitID:0, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x1111_1111_1111_1111, length: LitLength:8, id: LitID:0, last: false, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x1111_1111_1111_1111, length: LitLength:3, id: LitID:0, last: true, literals_last: false}, // 2nd literal - LiteralsDataWithSync {data: LitData:0x0000_0000_0022_2222, length: LitLength:3, last: false, id: LitID:1, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x2222_2222_2222_2222, length: LitLength:3, id: LitID:1, last: true, literals_last: false}, // 3rd literal - LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, last: false, id: LitID:2, literals_last: false}, - LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, last: false, id: LitID:2, literals_last: true}, - // 4th literal (empty) + LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, id: LitID:2, last: false, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x3333_3333_3333_3333, length: LitLength:8, id: LitID:2, last: true, literals_last: false}, // 5th literal - LiteralsDataWithSync {data: LitData:0x0000_0000_0000_5555, length: LitLength:2, last: false, id: LitID:3, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x5555_5555_5555_5555, length: LitLength:2, id: LitID:3, last: true, literals_last: false}, // 6th literal - LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:8, last: false, id: LitID:4, literals_last: false}, - LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:8, last: false, id: LitID:4, literals_last: false}, - LiteralsDataWithSync {data: LitData:0x0000_0000_6666_6666, length: LitLength:4, last: false, id: LitID:4, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:8, id: LitID:4, last: false, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:8, id: LitID:4, last: false, literals_last: false}, + LiteralsDataWithSync {data: LitData:0x6666_6666_6666_6666, length: LitLength:4, id: LitID:4, last: true, literals_last: false}, // 7th literal - LiteralsDataWithSync {data: LitData:0x0000_0000_0000_0000, length: LitLength:0, last: true, id: LitID:5, literals_last: true}, + LiteralsDataWithSync {data: LitData:0x0000_0000_0000_0000, length: LitLength:0, id: LitID:5, last: true, literals_last: true}, ]; - let tok = for ((counter, rle_data), tok): ((u32, RleLiteralsData), token) in enumerate(test_rle_data) { - let tok = send(tok, in_s, rle_data); - trace_fmt!("Sent #{} rle data, {:#x}", counter + u32:1, rle_data); - (tok) - }(tok); - - let tok = for ((counter, expected_out_data), tok): ((u32, LiteralsDataWithSync), token) in enumerate(test_out_data) { - let (tok, out_data) = recv(tok, out_r); - trace_fmt!("Received #{} batched data, {:#x}", counter + u32:1, out_data); - assert_eq(out_data, expected_out_data); - (tok) - }(tok); + // Test #0 + let req = test_rle_req[0]; + let resp = test_rle_resp[0]; + let tok = send(tok, req_s, req); + trace_fmt!("Sent req: {:#x}", req); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[0]); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[1]); + let (tok, rle_resp) = recv(tok, resp_r); + trace_fmt!("Received resp: {:#x}", rle_resp); + assert_eq(rle_resp, resp); + + // Test #1 + let req = test_rle_req[1]; + let resp = test_rle_resp[1]; + let tok = send(tok, req_s, req); + trace_fmt!("Sent req: {:#x}", req); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[2]); + let (tok, rle_resp) = recv(tok, resp_r); + trace_fmt!("Received resp: {:#x}", rle_resp); + assert_eq(rle_resp, resp); + + // Test #2 + let req = test_rle_req[2]; + let resp = test_rle_resp[2]; + let tok = send(tok, req_s, req); + trace_fmt!("Sent req: {:#x}", req); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[3]); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[4]); + let (tok, rle_resp) = recv(tok, resp_r); + trace_fmt!("Received resp: {:#x}", rle_resp); + assert_eq(rle_resp, resp); + + // Test #3 + let req = test_rle_req[3]; + let resp = test_rle_resp[3]; + let tok = send(tok, req_s, req); + trace_fmt!("Sent req: {:#x}", req); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[5]); + let (tok, rle_resp) = recv(tok, resp_r); + trace_fmt!("Received resp: {:#x}", rle_resp); + assert_eq(rle_resp, resp); + + // Test #4 + let req = test_rle_req[4]; + let resp = test_rle_resp[4]; + let tok = send(tok, req_s, req); + trace_fmt!("Sent req: {:#x}", req); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[6]); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[7]); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[8]); + let (tok, rle_resp) = recv(tok, resp_r); + trace_fmt!("Received resp: {:#x}", rle_resp); + assert_eq(rle_resp, resp); + + // Test #5 + let req = test_rle_req[5]; + let resp = test_rle_resp[5]; + let tok = send(tok, req_s, req); + trace_fmt!("Sent req: {:#x}", req); + let (tok, out_data) = recv(tok, out_r); + trace_fmt!("Received batched data: {:#x}", out_data); + assert_eq(out_data, test_out_data[9]); + let (tok, rle_resp) = recv(tok, resp_r); + trace_fmt!("Received resp: {:#x}", rle_resp); + assert_eq(rle_resp, resp); send(tok, terminator, true); } From dae442573777e51970cfeeddc85bdca643ac6495 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 14 Jan 2025 15:58:37 +0100 Subject: [PATCH 45/85] modules/zstd/BUILD: tag targets as manual Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 103 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 81826fe9a4..0c60cced69 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -169,6 +169,7 @@ cc_library( "@com_google_absl//absl/time", "@com_google_absl//absl/types:span", ], + tags = ["manual"], ) xls_dslx_library( @@ -614,6 +615,7 @@ xls_dslx_library( xls_dslx_test( name = "parallel_rams_dslx_test", library = ":parallel_rams_dslx", + tags = ["manual"], ) xls_dslx_library( @@ -895,6 +897,7 @@ xls_dslx_library( xls_dslx_test( name = "ram_wr_handler_dslx_test", library = ":ram_wr_handler_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -912,6 +915,7 @@ xls_dslx_verilog( "top": "__ram_wr_handler__RamWrRespHandlerInst__RamWrRespHandler_0__32_next", }, verilog_file = "ram_rw_handler.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -921,6 +925,7 @@ xls_benchmark_ir( "pipeline_stages": "10", "delay_model": "asap7", }, + tags = ["manual"], ) verilog_library( @@ -928,6 +933,7 @@ verilog_library( srcs = [ ":ram_rw_handler.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -937,11 +943,13 @@ synthesize_rtl( deps = [ ":ram_rw_handler_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "ram_rw_handler_benchmark_synth", synth_target = ":ram_rw_handler_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -953,6 +961,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":ram_rw_handler_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -970,6 +979,7 @@ xls_dslx_library( xls_dslx_test( name = "fse_proba_freq_dec_dslx_test", library = ":fse_proba_freq_dec_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -997,6 +1007,7 @@ xls_dslx_verilog( "top": "__fse_proba_freq_dec__FseProbaFreqDecoderInst__FseProbaFreqDecoder_0__64_7_8_10_1_next", }, verilog_file = "fse_proba_freq_dec.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1016,11 +1027,13 @@ xls_benchmark_ir( # wr_resp = "fse_proba_freq_dec__wr_resp_r", #), }, + tags = ["manual"], ) xls_benchmark_verilog( name = "fse_proba_freq_dec_verilog_benchmark", verilog_target = "fse_proba_freq_dec_verilog", + tags = ["manual"], ) verilog_library( @@ -1028,6 +1041,7 @@ verilog_library( srcs = [ ":fse_proba_freq_dec.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -1037,11 +1051,13 @@ synthesize_rtl( deps = [ ":fse_proba_freq_dec_lib", ], + tags = ["manual"], ) benchmark_synth( name = "fse_proba_freq_dec_benchmark_synth", synth_target = ":fse_proba_freq_dec_asap7", + tags = ["manual"], ) place_and_route( @@ -1053,6 +1069,7 @@ place_and_route( stop_after_step = "detailed_routing", synthesized_rtl = ":fse_proba_freq_dec_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -1067,6 +1084,7 @@ xls_dslx_test( name = "literals_block_header_dec_dslx_test", dslx_test_args = {"compare": "jit"}, library = ":literals_block_header_dec_dslx", + tags = ["manual"], ) @@ -1103,6 +1121,7 @@ xls_dslx_test( name = "sequence_conf_dec_dslx_test", dslx_test_args = {"compare": "jit"}, library = ":sequence_conf_dec_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1154,6 +1173,7 @@ xls_dslx_test( name = "refilling_shift_buffer_dslx_test", dslx_test_args = {"compare": "jit"}, library = ":refilling_shift_buffer_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1338,6 +1358,7 @@ xls_dslx_library( xls_dslx_test( name = "fse_lookup_dec_dslx_test", library = ":fse_lookup_dec_dslx", + tags = ["manual"], ) xls_dslx_library( @@ -1351,6 +1372,7 @@ xls_dslx_library( xls_dslx_test( name = "fse_table_iterator_dslx_test", library = ":fse_table_iterator_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1365,6 +1387,7 @@ xls_dslx_verilog( dslx_top = "FseTableIterator", library = ":fse_table_iterator_dslx", verilog_file = "fse_table_iterator.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1374,6 +1397,7 @@ xls_benchmark_ir( "pipeline_stages": "10", "delay_model": "asap7", }, + tags = ["manual"], ) verilog_library( @@ -1381,6 +1405,7 @@ verilog_library( srcs = [ ":fse_table_iterator.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -1390,11 +1415,13 @@ synthesize_rtl( deps = [ ":fse_table_iterator_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "fse_table_iterator_benchmark_synth", synth_target = ":fse_table_iterator_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -1406,6 +1433,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":fse_table_iterator_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -1422,6 +1450,7 @@ xls_dslx_library( xls_dslx_test( name = "fse_table_creator_dslx_test", library = ":fse_table_creator_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1450,11 +1479,13 @@ xls_benchmark_ir( "pipeline_stages": "10", "delay_model": "asap7", }, + tags = ["manual"], ) xls_benchmark_verilog( name = "fse_table_creator_verilog_benchmark", verilog_target = "fse_table_creator_verilog", + tags = ["manual"], ) verilog_library( @@ -1462,6 +1493,7 @@ verilog_library( srcs = [ ":fse_table_creator.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -1471,11 +1503,13 @@ synthesize_rtl( deps = [ ":fse_table_creator_lib", ], + tags = ["manual"], ) benchmark_synth( name = "fse_table_creator_benchmark_synth", synth_target = ":fse_table_creator_asap7", + tags = ["manual"], ) place_and_route( @@ -1487,6 +1521,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":fse_table_creator_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -1501,6 +1536,7 @@ xls_dslx_test( name = "command_constructor_dslx_test", dslx_test_args = {"compare": "none"}, library = ":command_constructor_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1515,6 +1551,7 @@ xls_dslx_verilog( dslx_top = "CommandConstructor", library = ":command_constructor_dslx", verilog_file = "command_constructor.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1524,11 +1561,13 @@ xls_benchmark_ir( "pipeline_stages": "8", "delay_model": "asap7", }, + tags = ["manual"], ) xls_benchmark_verilog( name = "command_constructor_verilog_benchmark", verilog_target = "command_constructor_verilog", + tags = ["manual"], ) verilog_library( @@ -1536,6 +1575,7 @@ verilog_library( srcs = [ ":command_constructor.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -1545,11 +1585,13 @@ synthesize_rtl( deps = [ ":command_constructor_lib", ], + tags = ["manual"], ) benchmark_synth( name = "command_constructor_benchmark_synth", synth_target = ":command_constructor_asap7", + tags = ["manual"], ) place_and_route( @@ -1561,6 +1603,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":command_constructor_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -1575,6 +1618,7 @@ xls_dslx_test( name = "ram_demux_dslx_test", dslx_test_args = {"compare": "none"}, library = ":ram_demux_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1605,6 +1649,7 @@ xls_dslx_verilog( "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_8_5_next", }, verilog_file = "ram_demux.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1616,6 +1661,7 @@ xls_benchmark_ir( codegen_args = { "pipeline_stages": "10", }, + tags = ["manual"], ) verilog_library( @@ -1623,6 +1669,7 @@ verilog_library( srcs = [ ":ram_demux.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -1632,11 +1679,13 @@ synthesize_rtl( deps = [ ":ram_demux_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "ram_demux_benchmark_synth", synth_target = ":ram_demux_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -1648,6 +1697,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":ram_demux_synth_asap7", target_die_utilization_percentage = "5", + tags = ["manual"], ) xls_dslx_verilog( @@ -1677,6 +1727,7 @@ xls_dslx_verilog( "top": "__ram_demux__RamDemuxNaiveInst__RamDemuxNaive_0__5_8_0_8_next", }, verilog_file = "ram_demux_naive.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1688,6 +1739,7 @@ xls_benchmark_ir( codegen_args = { "pipeline_stages": "10", }, + tags = ["manual"], ) verilog_library( @@ -1695,6 +1747,7 @@ verilog_library( srcs = [ ":ram_demux_naive.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -1704,11 +1757,13 @@ synthesize_rtl( deps = [ ":ram_demux_naive_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "ram_demux_naive_benchmark_synth", synth_target = ":ram_demux_naive_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -1720,6 +1775,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":ram_demux_naive_synth_asap7", target_die_utilization_percentage = "5", + tags = ["manual"], ) xls_dslx_library( @@ -1818,6 +1874,7 @@ xls_dslx_library( xls_dslx_test( name = "ram_demux3_dslx_test", library = ":ram_demux3_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1845,6 +1902,7 @@ xls_dslx_verilog( dslx_top = "RamDemux3Inst", library = ":ram_demux3_dslx", verilog_file = "ram_demux3.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1920,6 +1978,7 @@ xls_dslx_library( xls_dslx_test( name = "sequence_dec_dslx_test", library = ":sequence_dec_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1939,6 +1998,7 @@ xls_dslx_verilog( dslx_top = "FseLookupCtrlInst", library = ":sequence_dec_dslx", verilog_file = "fse_lookup_ctrl.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -1966,6 +2026,7 @@ xls_dslx_library( xls_dslx_test( name = "rle_literals_dec_dslx_test", library = ":rle_literals_dec_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -1995,6 +2056,7 @@ xls_benchmark_ir( "pipeline_stages": "2", "delay_model": "asap7", }, + tags = ["manual"], ) verilog_library( @@ -2002,6 +2064,7 @@ verilog_library( srcs = [ ":rle_literals_dec.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -2011,11 +2074,13 @@ synthesize_rtl( deps = [ ":rle_literals_dec_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "rle_literals_dec_benchmark_synth", synth_target = ":rle_literals_dec_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -2027,6 +2092,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":rle_literals_dec_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -2041,6 +2107,7 @@ xls_dslx_library( xls_dslx_test( name = "raw_literals_dec_dslx_test", library = ":raw_literals_dec_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -2083,6 +2150,7 @@ verilog_library( srcs = [ ":raw_literals_dec.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -2129,6 +2197,7 @@ xls_dslx_library( xls_dslx_test( name = "literals_buffer_dslx_test", library = ":literals_buffer_dslx", + tags = ["manual"], ) xls_dslx_verilog( @@ -2159,6 +2228,7 @@ xls_dslx_verilog( "top": "__literals_buffer__LiteralsBufferInst__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next" }, verilog_file = "literals_buffer.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -2168,11 +2238,13 @@ xls_benchmark_ir( "pipeline_stages": "6", "delay_model": "asap7", }, + tags = ["manual"], ) xls_benchmark_verilog( name = "literals_buffer_verilog_benchmark", verilog_target = "literals_buffer_verilog", + tags = ["manual"], ) verilog_library( @@ -2180,6 +2252,7 @@ verilog_library( srcs = [ ":literals_buffer.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -2189,11 +2262,13 @@ synthesize_rtl( deps = [ ":literals_buffer_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "literals_buffer_benchmark_synth", synth_target = ":literals_buffer_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -2205,6 +2280,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":literals_buffer_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -2231,6 +2307,7 @@ xls_dslx_library( xls_dslx_test( name = "literals_decoder_dslx_test", library = ":literals_decoder_dslx", + tags = ["manual"], ) literals_decoder_ctrl_codegen_args = common_codegen_args | { @@ -2257,6 +2334,7 @@ xls_benchmark_ir( "multi_proc": "true", "inline_procs": "false", }, + tags = ["manual"], ) verilog_library( @@ -2264,6 +2342,7 @@ verilog_library( srcs = [ ":literals_decoder_ctrl.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -2273,11 +2352,13 @@ synthesize_rtl( deps = [ ":literals_decoder_ctrl_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "literals_decoder_ctrl_benchmark_synth", synth_target = ":literals_decoder_ctrl_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -2289,6 +2370,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":literals_decoder_ctrl_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_verilog( @@ -2319,6 +2401,7 @@ xls_dslx_verilog( "top": "__xls_modules_zstd_literals_buffer__LiteralsDecoderInst__LiteralsDecoder_0__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next", }, verilog_file = "literals_decoder.v", + tags = ["manual"], ) xls_benchmark_ir( @@ -2345,6 +2428,7 @@ verilog_library( srcs = [ ":literals_decoder.v", ], + tags = ["manual"], ) synthesize_rtl( @@ -2354,11 +2438,13 @@ synthesize_rtl( deps = [ ":literals_decoder_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "literals_decoder_benchmark_synth", synth_target = ":literals_decoder_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -2370,6 +2456,7 @@ place_and_route( stop_after_step = "global_routing", synthesized_rtl = ":literals_decoder_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -2396,6 +2483,7 @@ xls_dslx_library( xls_dslx_test( name = "huffman_prescan_dslx_test", library = ":huffman_prescan_dslx", + tags = ["manual"], ) prescan_codegen_args = common_codegen_args | { @@ -2418,17 +2506,20 @@ xls_dslx_verilog( dslx_top = "WeightPreScan", library = ":huffman_prescan_dslx", verilog_file = "huffman_prescan.v", + tags = ["manual"], ) xls_benchmark_ir( name = "huffman_prescan_opt_ir_benchmark", src = ":huffman_prescan_verilog.opt.ir", benchmark_ir_args = prescan_codegen_args, + tags = ["manual"], ) xls_benchmark_verilog( name = "huffman_prescan_verilog_benchmark", verilog_target = "huffman_prescan_verilog", + tags = ["manual"], ) verilog_library( @@ -2437,6 +2528,7 @@ verilog_library( ":huffman_prescan.v", "fifo.v" ], + tags = ["manual"], ) synthesize_rtl( @@ -2446,11 +2538,13 @@ synthesize_rtl( deps = [ ":huffman_prescan_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "huffman_prescan_benchmark_synth", synth_target = ":huffman_prescan_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -2461,6 +2555,7 @@ place_and_route( placement_density = "0.30", synthesized_rtl = ":huffman_prescan_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( @@ -2479,6 +2574,7 @@ xls_dslx_library( xls_dslx_test( name = "huffman_code_builder_dslx_test", library = ":huffman_code_builder_dslx", + tags = ["manual"], ) huffman_code_builder_codegen_args = common_codegen_args | { @@ -2496,17 +2592,20 @@ xls_dslx_verilog( dslx_top = "WeightCodeBuilder", library = ":huffman_code_builder_dslx", verilog_file = "huffman_code_builder.v", + tags = ["manual"], ) xls_benchmark_ir( name = "huffman_code_builder_opt_ir_benchmark", src = ":huffman_code_builder_verilog.opt.ir", benchmark_ir_args = huffman_code_builder_codegen_args, + tags = ["manual"], ) xls_benchmark_verilog( name = "huffman_code_builder_verilog_benchmark", verilog_target = "huffman_code_builder_verilog", + tags = ["manual"], ) verilog_library( @@ -2515,6 +2614,7 @@ verilog_library( ":huffman_code_builder.v", "fifo.v" ], + tags = ["manual"], ) synthesize_rtl( @@ -2524,11 +2624,13 @@ synthesize_rtl( deps = [ ":huffman_code_builder_verilog_lib", ], + tags = ["manual"], ) benchmark_synth( name = "huffman_code_builder_benchmark_synth", synth_target = ":huffman_code_builder_synth_asap7", + tags = ["manual"], ) place_and_route( @@ -2539,6 +2641,7 @@ place_and_route( placement_density = "0.30", synthesized_rtl = ":huffman_code_builder_synth_asap7", target_die_utilization_percentage = "10", + tags = ["manual"], ) xls_dslx_library( From 7f87db193b1dee0c07f4f06ff4a148259f6ebfc5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Tue, 14 Jan 2025 15:12:33 +0100 Subject: [PATCH 46/85] modules/zstd: Enable CompressedBlockDecoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Robert Winkler Signed-off-by: Robert Winkler Signed-off-by: Krzysztof Obłonczek --- xls/modules/zstd/BUILD | 49 +- xls/modules/zstd/comp_block_dec.x | 1386 ++++++++++++++++++++++++++--- 2 files changed, 1273 insertions(+), 162 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 0c60cced69..5e485baf41 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1143,23 +1143,6 @@ xls_benchmark_ir( tags = ["manual"], ) -#xls_dslx_library( -# name = "comp_block_dec_dslx", -# srcs = ["comp_block_dec.x"], -# deps = [ -# "//xls/examples:ram_dslx", -# "//xls/modules/zstd/memory:mem_reader_dslx", -# "//xls/modules/zstd/memory:axi_ram_dslx", -# ":fse_proba_freq_dec_dslx", -# ":literals_block_header_dec_dslx", -# ], -#) -# -#xls_dslx_test( -# name = "comp_block_dec_dslx_test", -# library = ":comp_block_dec_dslx", -#) - xls_dslx_library( name = "refilling_shift_buffer_dslx", srcs = ["refilling_shift_buffer.x"], @@ -1233,14 +1216,30 @@ place_and_route( target_die_utilization_percentage = "10", ) -#xls_dslx_verilog( -# name = "refilling_shift_buffer_verilog", -# codegen_args = common_codegen_args, -# dslx_top = "RefillingShiftBufferInst", -# library = ":refilling_shift_buffer_dslx", -# tags = ["manual"], -# verilog_file = "refilling_shift_buffer.v", -#) +xls_dslx_library( + name = "comp_block_dec_dslx", + srcs = ["comp_block_dec.x"], + deps = [ + "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + ":fse_proba_freq_dec_dslx", + ":literals_block_header_dec_dslx", + ":common_dslx", + ":huffman_literals_dec_dslx", + ":parallel_rams_dslx", + ":literals_buffer_dslx", + ":sequence_dec_dslx", + ":literals_decoder_dslx", + ":command_constructor_dslx", + ], +) + +xls_dslx_test( + name = "comp_block_dec_dslx_test", + library = ":comp_block_dec_dslx", + tags = ["manual"], +) zstd_dec_deps = [ ":axi_csr_accessor_dslx", diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index 877998336d..9a47caffd1 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -14,73 +14,81 @@ import std; import xls.examples.ram; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.common; +import xls.modules.zstd.huffman_literals_dec; +import xls.modules.zstd.parallel_rams; +import xls.modules.zstd.literals_buffer; +import xls.modules.zstd.sequence_dec; +import xls.modules.zstd.literals_block_header_dec; +import xls.modules.zstd.literals_decoder; +import xls.modules.zstd.command_constructor; import xls.modules.zstd.memory.axi; import xls.modules.zstd.memory.mem_reader; import xls.modules.zstd.fse_proba_freq_dec; -import xls.modules.zstd.comp_block_header_dec; +import xls.modules.zstd.fse_table_creator; +import xls.modules.zstd.ram_mux; +type SequenceExecutorPacket = common::SequenceExecutorPacket; +type ExtendedPacket = common::ExtendedBlockDataPacket; +type SequenceExecutorMessageType = common::SequenceExecutorMessageType; +type BlockDataPacket = common::BlockDataPacket; +type BlockSize = common::BlockSize; +type BlockSyncData = common::BlockSyncData; -struct CompressBlockDecoderReq { } -struct CompressBlockDecoderResp { } - -struct CompressBlockDecoderControlState { } - -proc CompressBlockDecoderControl { - type Req = CompressBlockDecoderReq; - type Resp = CompressBlockDecoderResp; - type State = CompressBlockDecoderControlState; - - type HeaderDecoderReq = comp_block_header_dec::CompressBlockHeaderDecoderReq; - type HeaderDecoderResp = comp_block_header_dec::CompressBlockHeaderDecoderResp; - - req_r: chan in; - resp_s: chan out; - cmph_req_s: chan out; - cmph_resp_r: chan in; - - init { zero!() } - - config( - req_r: chan in, - resp_s: chan out, - cmph_req_s: chan out, - cmph_resp_r: chan in, - ) { - (req_r, resp_s, cmph_req_s, cmph_resp_r) - } - - next (state: State) { - let tok = join(); - - send_if(tok, resp_s, false, zero!()); - send_if(tok, cmph_req_s, false, zero!()); - - recv_if(tok, req_r, false, zero!()); - recv_if(tok, cmph_resp_r, false, zero!()); +pub enum CompressBlockDecoderStatus: u1 { + OK = 0, + ERROR = 1, +} - state - } +pub struct CompressBlockDecoderReq { + addr: uN[AXI_ADDR_W], + length: BlockSize, + id: u32, + last_block: bool, +} +pub struct CompressBlockDecoderResp { + status: CompressBlockDecoderStatus } -proc CompressBlockDecoder< +pub proc CompressBlockDecoder< // AXI parameters AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + // FSE lookup table RAMs + DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + + // for literals decoder + HISTORY_BUFFER_SIZE_KB: u32 = {common::HISTORY_BUFFER_SIZE_KB}, + // FSE proba FSE_PROBA_DIST_W: u32 = {u32:16}, FSE_PROBA_MAX_DISTS: u32 = {u32:256}, // constants - FSE_DEF_PROBA_DIST_RAM_DATA_W: u32 = {FSE_PROBA_DIST_W}, - FSE_DEF_PROBA_DIST_RAM_SIZE: u32 = {FSE_PROBA_MAX_DISTS}, - FSE_DEF_PROBA_DIST_ADDR_W: u32 = {std::clog2(FSE_DEF_PROBA_DIST_RAM_SIZE)}, - FSE_DEF_PROBA_DIST_RAM_WORD_PARTITION_SIZE: u32 = { FSE_DEF_PROBA_DIST_RAM_DATA_W }, - FSE_DEF_PROBA_DIST_RAM_NUM_PARTITIONS: u32 = { ram::num_partitions(FSE_DEF_PROBA_DIST_RAM_WORD_PARTITION_SIZE, FSE_DEF_PROBA_DIST_RAM_DATA_W) }, AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, + + // Huffman weights memory parameters + HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_ADDR_WIDTH}, + HUFFMAN_WEIGHTS_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_DATA_WIDTH}, + HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::WEIGHTS_NUM_PARTITIONS}, + // Huffman prescan memory parameters + HUFFMAN_PRESCAN_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::PRESCAN_ADDR_WIDTH}, + HUFFMAN_PRESCAN_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::PRESCAN_DATA_WIDTH}, + HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::PRESCAN_NUM_PARTITIONS}, + // Literals buffer memory parameters + LITERALS_BUFFER_RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + LITERALS_BUFFER_RAM_DATA_WIDTH: u32 = {literals_buffer::RAM_DATA_WIDTH}, + LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = {literals_buffer::RAM_NUM_PARTITIONS}, > { - type Req = CompressBlockDecoderReq; + type Req = CompressBlockDecoderReq; type Resp = CompressBlockDecoderResp; + type SequenceDecReq = sequence_dec::SequenceDecoderReq; + type SequenceDecResp = sequence_dec::SequenceDecoderResp; + type MemReaderReq = mem_reader::MemReaderReq; type MemReaderResp = mem_reader::MemReaderResp; @@ -90,154 +98,1258 @@ proc CompressBlockDecoder< type MemAxiW = axi::AxiW; type MemAxiB = axi::AxiB; - type HeaderDecoderReq = comp_block_header_dec::CompressBlockHeaderDecoderReq; - type HeaderDecoderResp = comp_block_header_dec::CompressBlockHeaderDecoderResp; + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; - //type ShiftBufferInput = shift_buffer::ShiftBufferInput; - //type ShiftBufferCtrl = shift_buffer::ShiftBufferCtrl; - //type ShiftBufferOutput = shift_buffer::ShiftBufferOutput; + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; - type DpdRamRdReq = ram::ReadReq; - type DpdRamRdResp = ram::ReadResp; - type DpdRamWrReq = ram::WriteReq; - type DpdRamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type LiteralsHeaderDecoderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + type LiteralsBlockType = literals_block_header_dec::LiteralsBlockType; + type LiteralsDecReq = literals_decoder::LiteralsDecoderCtrlReq; + type LiteralsDecResp = literals_decoder::LiteralsDecoderCtrlResp; + type LiteralsBufCtrl = common::LiteralsBufferCtrl; + type CommandConstructorData = common::CommandConstructorData; + + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; + type LitBufRamWrResp = ram::WriteResp; + + type AxiAddrW = uN[AXI_ADDR_W]; + + req_r: chan in; + resp_s: chan out; + + lit_ctrl_req_s: chan out; + lit_ctrl_resp_r: chan in; + lit_ctrl_header_r: chan in; + + seq_dec_req_s: chan out; + seq_dec_resp_r: chan in; init {} - next(state: ()) {} config( req_r: chan in, resp_s: chan out, - // AXI Compressed Block Header Decoder (manager) - cmph_axi_ar_s: chan out, - cmph_axi_r_r: chan in, + // output from Command constructor to Sequence executor + cmd_constr_out_s: chan out, - // AXI Fse Probability Frequence Decoder (manager) - //pfd_axi_ar_s: chan out, - //pfd_axi_r_r: chan in, + // Sequence Decoder channels - ) { + // Sequence Conf Decoder (manager) + scd_axi_ar_s: chan out, + scd_axi_r_r: chan in, + + // Fse Lookup Decoder (manager) + fld_axi_ar_s: chan out, + fld_axi_r_r: chan in, + + // FSE decoder (manager) + fd_axi_ar_s: chan out, + fd_axi_r_r: chan in, + + // RAMs for FSE decoder + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + ll_def_fse_rd_req_s: chan out, + ll_def_fse_rd_resp_r: chan in, + ll_def_fse_wr_req_s: chan out, + ll_def_fse_wr_resp_r: chan in, + + ll_fse_rd_req_s: chan out, + ll_fse_rd_resp_r: chan in, + ll_fse_wr_req_s: chan out, + ll_fse_wr_resp_r: chan in, + + ml_def_fse_rd_req_s: chan out, + ml_def_fse_rd_resp_r: chan in, + ml_def_fse_wr_req_s: chan out, + ml_def_fse_wr_resp_r: chan in, + + ml_fse_rd_req_s: chan out, + ml_fse_rd_resp_r: chan in, + ml_fse_wr_req_s: chan out, + ml_fse_wr_resp_r: chan in, + + of_def_fse_rd_req_s: chan out, + of_def_fse_rd_resp_r: chan in, + of_def_fse_wr_req_s: chan out, + of_def_fse_wr_resp_r: chan in, + + of_fse_rd_req_s: chan out, + of_fse_rd_resp_r: chan in, + of_fse_wr_req_s: chan out, + of_fse_wr_resp_r: chan in, + + // Literals decoder channels + + // AXI Literals Header Decoder (manager) + lit_header_axi_ar_s: chan out, + lit_header_axi_r_r: chan in, + + // AXI Raw Literals Decoder (manager) + raw_lit_axi_ar_s: chan out, + raw_lit_axi_r_r: chan in, + + // AXI Huffman Literals Decoder (manager) + huffman_lit_axi_ar_s: chan out, + huffman_lit_axi_r_r: chan in, + + // AXI Huffman Jump Table Decoder (manager) + huffman_jump_table_axi_ar_s: chan out, + huffman_jump_table_axi_r_r: chan in, + + // AXI Huffman Weights Header Decoder (manager) + huffman_weights_header_axi_ar_s: chan out, + huffman_weights_header_axi_r_r: chan in, + + // AXI Huffman Weights RAW Decoder (manager) + huffman_weights_raw_axi_ar_s: chan out, + huffman_weights_raw_axi_r_r: chan in, + + // AXI Huffman Weights FSE Decoder (manager) + huffman_weights_fse_axi_ar_s: chan out, + huffman_weights_fse_axi_r_r: chan in, + + // Literals buffer internal memory + rd_req_m0_s: chan out, + rd_req_m1_s: chan out, + rd_req_m2_s: chan out, + rd_req_m3_s: chan out, + rd_req_m4_s: chan out, + rd_req_m5_s: chan out, + rd_req_m6_s: chan out, + rd_req_m7_s: chan out, + rd_resp_m0_r: chan in, + rd_resp_m1_r: chan in, + rd_resp_m2_r: chan in, + rd_resp_m3_r: chan in, + rd_resp_m4_r: chan in, + rd_resp_m5_r: chan in, + rd_resp_m6_r: chan in, + rd_resp_m7_r: chan in, + wr_req_m0_s: chan out, + wr_req_m1_s: chan out, + wr_req_m2_s: chan out, + wr_req_m3_s: chan out, + wr_req_m4_s: chan out, + wr_req_m5_s: chan out, + wr_req_m6_s: chan out, + wr_req_m7_s: chan out, + wr_resp_m0_r: chan in, + wr_resp_m1_r: chan in, + wr_resp_m2_r: chan in, + wr_resp_m3_r: chan in, + wr_resp_m4_r: chan in, + wr_resp_m5_r: chan in, + wr_resp_m6_r: chan in, + wr_resp_m7_r: chan in, + + // Huffman weights memory + huffman_lit_weights_mem_rd_req_s: chan out, + huffman_lit_weights_mem_rd_resp_r: chan in, + huffman_lit_weights_mem_wr_req_s: chan out, + huffman_lit_weights_mem_wr_resp_r: chan in, + + // Huffman prescan memory + huffman_lit_prescan_mem_rd_req_s: chan out, + huffman_lit_prescan_mem_rd_resp_r: chan in, + huffman_lit_prescan_mem_wr_req_s: chan out, + huffman_lit_prescan_mem_wr_resp_r: chan in, + + ) { + // TODO: for consistency all MemReaders should be in toplevel ZSTD decoder + // so we should move them up in the hierarchy from LiteralsDecoder + // and SequenceDecoder to the toplevel const CHANNEL_DEPTH = u32:1; - // Compress Block Header Memory Reader + let (lit_ctrl_req_s, lit_ctrl_req_r) = chan("lit_ctrl_req"); + let (lit_ctrl_resp_s, lit_ctrl_resp_r) = chan("lit_ctrl_resp"); + let (lit_ctrl_header_s, lit_ctrl_header_r) = chan("lit_header"); - let (cmph_mem_rd_req_s, cmph_mem_rd_req_r) = chan("cmph_mem_rd_req"); - let (cmph_mem_rd_resp_s, cmph_mem_rd_resp_r) = chan("cmph_mem_rd_resp"); + let (lit_buf_ctrl_s, lit_buf_ctrl_r) = chan("lit_buf_ctrl"); + let (lit_buf_out_s, lit_buf_out_r) = chan("lit_buf_out"); - spawn mem_reader::MemReader( - cmph_mem_rd_req_r, cmph_mem_rd_resp_s, - cmph_axi_ar_s, cmph_axi_r_r, + spawn literals_decoder::LiteralsDecoder< + HISTORY_BUFFER_SIZE_KB, + AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W + >( + lit_header_axi_ar_s, lit_header_axi_r_r, + raw_lit_axi_ar_s, raw_lit_axi_r_r, + huffman_lit_axi_ar_s, huffman_lit_axi_r_r, + huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, + huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, + huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, + huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + lit_buf_ctrl_r, lit_buf_out_s, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, ); - let (cmph_req_s, cmph_req_r) = chan("cmph_dec_req"); - let (cmph_resp_s, cmph_resp_r) = chan("cmph_dec_resp"); + let (seq_dec_req_s, seq_dec_req_r) = chan("seq_dec_req"); + let (seq_dec_resp_s, seq_dec_resp_r) = chan("seq_dec_resp"); + let (seq_dec_command_s, seq_dec_command_r) = chan("seq_dec_command"); - spawn comp_block_header_dec::CompressBlockHeaderDecoder( - cmph_mem_rd_req_s, cmph_mem_rd_resp_r, - cmph_req_r, cmph_resp_s + spawn sequence_dec::SequenceDecoder< + AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, + DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, + TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, + >( + scd_axi_ar_s, scd_axi_r_r, + fld_axi_ar_s, fld_axi_r_r, + fd_axi_ar_s, fd_axi_r_r, + seq_dec_req_r, seq_dec_resp_s, + seq_dec_command_s, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, + ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, + ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, ml_fse_wr_req_s, ml_fse_wr_resp_r, + of_def_fse_rd_req_s, of_def_fse_rd_resp_r, of_def_fse_wr_req_s, of_def_fse_wr_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, of_fse_wr_req_s, of_fse_wr_resp_r, ); - // FseProbaFreqDecoder channels - // - // This part of the decoder is used to prepare FSE lookups if they - // are provided in the encoded ZSTD bitstream (FSE_Compressed_Mode). - // This part of the design sould take the input from the input buffer - // located on the system bus, and decode the probability frequencies - // into probability distribution. The outpud data should be stored in - // a local RAM. One chalange related to this part of the code is how - // to us a single instance of the proc to prepare three different FSE tables - // (for Offsets, Matches, and Literals Lenghts). - - // spawn mem_reader::MemReader< - // AXI_DATA_W, AXI_ADDR_W, AXI_DEST_W, AXI_ID_W, CHANNEL_DEPTH - // >( - // pfd_mem_rd_req_r, pfd_mem_rd_resp_s, - // pfd_axi_ar_s, pfd_axi_r_r, - // ); - // - // spawn shift_buffer::ShiftBuffer< - // SHIFT_BUFFER_DATA_W, SHIFT_BUFFER_LENGTH_W - // >(buff_data_r, ctrl_r, out_s); - // - // - // spawn FseProbaFreqDecoder< - // FSE_DEF_PROBA_DIST_RAM_DATA_W, - // FSE_DEF_PROBA_DIST_RAM_SIZE, - // FSE_DEF_PROBA_DIST_RAM_WORD_PARTITION_SIZE - // >( - // req_r, resp_s, - // buff_in_ctrl_s, buff_out_data_r, - // rd_req_s, rd_resp_r, wr_req_s, wr_resp_r - // ); - // - // let (dpd_rd_req_r, dpd_rd_req_s) = chan("rd_req"); - // let (dpd_rd_req_r, dpd_rd_req_s) = chan("rd_resp"); - // let (dpd_wr_req_r, dpd_wr_req_s) = chan("wr_req"); - // let (dpd_wr_resp_r, dpd_wr_resp_s) = chan("wr_resp"); - // - // spawn ram::RamModel< - // FSE_PROBA_DATA_W, - // FSE_PROBA_RAM_SIZE, - // FSE_PROBA_RAM_WORD_PARTITION_SIZE - // >( - // rd_req_r, rd_resp_s, wr_req_r, wr_resp_s - // ); - - //spawn CompressBlockDecoderControl< - //>( - // req_r, resp_s - // cmph_req_s, cmph_resp_r, - //); - - //spawn fse_proba_freq_dec::FseProbaFreqDecoder(); - () + spawn command_constructor::CommandConstructor( + seq_dec_command_r, + cmd_constr_out_s, + lit_buf_out_r, + lit_buf_ctrl_s, + ); + + ( + req_r, resp_s, + lit_ctrl_req_s, lit_ctrl_resp_r, lit_ctrl_header_r, + seq_dec_req_s, seq_dec_resp_r, + ) + } + + next(_: ()) { + let tok = join(); + + let (tok_req, req) = recv(tok, req_r); + trace_fmt!("[CompressBlockDecoder] Received request: {:#x}", req); + + let lit_ctrl_req = LiteralsDecReq { + addr: req.addr, + literals_last: req.last_block, + }; + let tok_lit1 = send(tok_req, lit_ctrl_req_s, lit_ctrl_req); + trace_fmt!("[CompressBlockDecoder] Sent lit_ctrl_req: {:#x}", lit_ctrl_req); + + let (tok_lit2, lit_header) = recv(tok_lit1, lit_ctrl_header_r); + trace_fmt!("[CompressBlockDecoder] Received lit_header: {:#x}", lit_header); + + let seq_section_offset = lit_header.length as AxiAddrW + match (lit_header.header.literal_type) { + LiteralsBlockType::RAW => lit_header.header.regenerated_size, + LiteralsBlockType::RLE => u20:1, + LiteralsBlockType::COMP | LiteralsBlockType::COMP_4 => lit_header.header.compressed_size, + LiteralsBlockType::TREELESS | LiteralsBlockType::TREELESS_4 => lit_header.header.compressed_size, + _ => fail!("comp_block_dec_unreachable", u20:0), + } as AxiAddrW; + + let seq_section_start = req.addr + seq_section_offset; + let seq_section_end = req.addr + req.length as AxiAddrW; + + let (tok_fin_lit, lit_resp) = recv(tok_lit1, lit_ctrl_resp_r); + trace_fmt!("[CompressBlockDecoder] Received lit_ctrl_resp: {:#x}", lit_resp); + + let seq_req = SequenceDecReq { + start_addr: seq_section_start, + end_addr: seq_section_end, + sync: BlockSyncData { + id: req.id, + last_block: req.last_block, + }, + literals_count: lit_header.header.regenerated_size, + }; + + trace_fmt!("[CompressBlockDecoder] Sending sequence req: {:#x}", seq_req); + let tok_seq = send(tok_fin_lit, seq_dec_req_s, seq_req); + + let (tok_fin_seq, seq_resp) = recv(tok_seq, seq_dec_resp_r); + trace_fmt!("[CompressBlockDecoder] Received sequence resp: {:#x}", seq_resp); + + let tok_finish = join(tok_fin_lit, tok_fin_seq); + send(tok_finish, resp_s, Resp { + status: CompressBlockDecoderStatus::OK + }); } } +const TEST_CASE_RAM_DATA_WIDTH = u32:64; +const TEST_CASE_RAM_SIZE = u32:256; +const TEST_CASE_RAM_ADDR_WIDTH = std::clog2(TEST_CASE_RAM_SIZE); +const TEST_CASE_RAM_WORD_PARTITION_SIZE = TEST_CASE_RAM_DATA_WIDTH / u32:8; +const TEST_CASE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_CASE_RAM_DATA_WIDTH); +const TEST_CASE_RAM_BASE_ADDR = u32:0; + const TEST_AXI_DATA_W = u32:64; const TEST_AXI_ADDR_W = u32:32; const TEST_AXI_ID_W = u32:4; const TEST_AXI_DEST_W = u32:4; +const TEST_AXI_DATA_W_DIV8 = TEST_AXI_DATA_W / u32:8; + +const TEST_DPD_RAM_DATA_W = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_W = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_W; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); + +const TEST_FSE_RAM_DATA_W = u32:32; +const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); + +const TEST_TMP_RAM_DATA_W = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_W = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); + +const TEST_RAM_SIM_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_INITIALIZED = true; + +const HISTORY_BUFFER_SIZE_KB = common::HISTORY_BUFFER_SIZE_KB; + +const HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; +const HUFFMAN_WEIGHTS_RAM_DATA_WIDTH: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; +const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; +// Huffman prescan memory parameters +const HUFFMAN_PRESCAN_RAM_ADDR_WIDTH: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; +const HUFFMAN_PRESCAN_RAM_DATA_WIDTH: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; +const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; +// Literals buffer memory parameters +const LITERALS_BUFFER_RAM_ADDR_WIDTH: u32 = parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB); +const LITERALS_BUFFER_RAM_SIZE: u32 = parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB); +const LITERALS_BUFFER_RAM_DATA_WIDTH: u32 = literals_buffer::RAM_DATA_WIDTH; +const LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; +const LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = LITERALS_BUFFER_RAM_DATA_WIDTH; + +const AXI_CHAN_N = u32:10; + + +// testcase format: +// - block length (without block header, essentially length of sequences + literals sections), +// - literals and sequences sections as they appear in memory +// - expected output size +// - expected output +const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ + // RAW + ( + // Test case 0 + // raw literals (18) + sequences with 3 predefined tables (2) + // + // last block generated with: + // ./decodecorpus -pdata2.out -odata2.in -s7110 --block-type=2 --content-size iliteral-type=0 --max-block-size-log=5 + u32:0x1C, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0x1fba7f9f15523990, + u64:0x43e75b86b1dfe343, + u64:0xc0423000200d6c6, + u64:0x252c492, + u64:0, ... + ], + u32:6, + ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x431fba7f9f155239, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xe75b86b1dfe3, length: u32:6 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x192, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xd6c643, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x223, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x00, length: u32:1 } + }, + zero!(), ... + ] + ), + ( + // Test case 1 + // raw literals (64) + sequences with 3 predefined tables (1) + // + // last block generated with: + // ./decodecorpus -pdata2.out -odata2.in -s35304 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 + u32:0x48, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0xc792801500520404, + u64:0x9be2210a8b13a2bb, + u64:0x291994532c422e15, + u64:0x1c37a8940c112bcd, + u64:0xc95f959fa34764de, + u64:0x57c1079b679780bb, + u64:0x7a819dd90c2f2b97, + u64:0x5a829f58ba369e42, + u64:0x13d608b30001d27d, + u64:0, ... + ], + u32:10, + ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xa2bbc79280150052, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2e159be2210a8b13, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2bcd291994532c42, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x64de1c37a8940c11, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x9fa347, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x116, length: u32:4 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x9b679780bbc95f95, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xd90c2f2b9757c107, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x58ba369e427a819d, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0xd27d5a829f, length: u32:5 } + }, + zero!(), ... + ] + ), + // RLE + ( + // Test case 2 + // RLE literals (13) + sequences with 3 predefined tables (15) + // + // last block generated with: + // ./decodecorpus -pdata2.out -odata2.in -s52123 --block-type=2 --content-size --literal-type=1 --max-block-size-log=7 + u32:0x35, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0xf006ace2000f7669, + u64:0xdd540313be00074e, + u64:0xb005607a005e2056, + u64:0xa8e58056222e0c33, + u64:0x5404c001f64c80a, + u64:0x834002e100f7dce, + u64:0x40381ea080, + u64:0, ... + ], + u32:21, + ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x1f50, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76767676, length: u32:4 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x21a, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x1bee, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2026, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x1d93, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2a39, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x3111, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xe76, length: u32:4 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x303d, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x3, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x36ea, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x7676767676, length: u32:5 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x53be, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x14ef, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x2ce2, length: u32:4 } + }, + zero!(), ... + ], + ), + ( + // Test case 3 + // RLE literals (102) + sequences with 3 predefined tables (2) + // + // last block generated with: + // ./decodecorpus -pdata2.out -odata2.in -s52352 --block-type=2 --content-size --literal-type=1 --max-block-size-log=7 + u32:0xa, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0x42184c0002f50665, + u64:0x9570, + u64:0, ... + ], + u32:16, + ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5, length: u32:6 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2, length: u32:4 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5, length: u32:4 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x4c, length: u32:6 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5, length: u32:4 } + }, + zero!(), ... + ] + ), + // Corner cases + ( + // Test case 4 + // RLE literals (0) + sequences with 3 predefined tables (0) + // + // last block generated with: + // ./decodecorpus -pdata2.out -odata2.in -s10761 --block-type=2 --content-size --literal-type=1 --max-block-size-log=7 + u32:0x3, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0x1501, + u64:0, ... + ], + u32:0, + ExtendedPacket[128]:[ + zero!(), ... + ] + ), + ( + // Test case 5 + // RLE literals (0) + sequences with 3 predefined tables (2) + // last block generated with: + //./decodecorpus -pdata2.out -odata2.in -s7294 --block-type=2 --content-size --literal-type=1 --max-block-size-log=7 + u32:0xc, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0x6006ab770002fa01, + u64:0x1020070, + u64:0, ... + ], + u32:2, + ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf06, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x2b77, length: u32:4 } + }, + zero!(), ... + ], + ), + ( + // Test case 6 + // RAW literals (2) + sequences with 3 predefined tables (0) + // last block generated with: + //./decodecorpus -pdata2.out -odata2.in -s38193 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 + u32:0x4, + u64[64]:[ + u64:0x0, u64:0x0, // 0x000 + u64:0x0, u64:0x0, // 0x010 + u64:0x0, u64:0x0, // 0x020 + u64:0x0, u64:0x0, // 0x030 + u64:0x0, u64:0x0, // 0x040 + u64:0x0, u64:0x0, // 0x050 + u64:0x0, u64:0x0, // 0x060 + u64:0x0, u64:0x0, // 0x070 + u64:0x0, u64:0x0, // 0x080 + u64:0x0, u64:0x0, // 0x090 + u64:0x0, u64:0x0, // 0x0A0 + u64:0x0, u64:0x0, // 0x0B0 + u64:0x0, u64:0x0, // 0x0C0 + u64:0x0, u64:0x0, // 0x0D0 + u64:0x0, u64:0x0, // 0x0E0 + u64:0x0, u64:0x0, // 0x0F0 + u64:0x215a10, + u64:0, ... + ], + u32:1, + ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x215a, length: u32:2 } + }, + zero!(), ... + ], + ) +]; #[test_proc] proc CompressBlockDecoderTest { - type Req = CompressBlockDecoderReq; + type Req = CompressBlockDecoderReq; type Resp = CompressBlockDecoderResp; + type SequenceDecReq = sequence_dec::SequenceDecoderReq; + type SequenceDecResp = sequence_dec::SequenceDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + type MemAxiAr = axi::AxiAr; type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type LiteralsHeaderDecoderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; + type LiteralsBlockType = literals_block_header_dec::LiteralsBlockType; + type LiteralsDecReq = literals_decoder::LiteralsDecoderCtrlReq; + type LiteralsDecResp = literals_decoder::LiteralsDecoderCtrlResp; + type LiteralsBufCtrl = common::LiteralsBufferCtrl; + type SequenceExecutorPacket = common::SequenceExecutorPacket; + type CommandConstructorData = common::CommandConstructorData; + + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; + type LitBufRamWrResp = ram::WriteResp; + + type TestcaseRamRdReq = ram::ReadReq; + type TestcaseRamRdResp = ram::ReadResp; + type TestcaseRamWrReq = ram::WriteReq; + type TestcaseRamWrResp = ram::WriteResp; terminator: chan out; req_s: chan out; resp_r: chan in; - cmph_axi_ar_r: chan in; - cmph_axi_r_s: chan out; + cmd_constr_out_r: chan in; + axi_ram_wr_req_s: chan[AXI_CHAN_N] out; + axi_ram_wr_resp_r: chan[AXI_CHAN_N] in; + + ll_sel_test_s: chan out; + ll_def_test_rd_req_s: chan out; + ll_def_test_rd_resp_r: chan in; + ll_def_test_wr_req_s: chan out; + ll_def_test_wr_resp_r: chan in; + + ml_sel_test_s: chan out; + ml_def_test_rd_req_s: chan out; + ml_def_test_rd_resp_r: chan in; + ml_def_test_wr_req_s: chan out; + ml_def_test_wr_resp_r: chan in; + + of_sel_test_s: chan out; + of_def_test_rd_req_s: chan out; + of_def_test_rd_resp_r: chan in; + of_def_test_wr_req_s: chan out; + of_def_test_wr_resp_r: chan in; init {} config(terminator: chan out) { let (req_s, req_r) = chan("req"); let (resp_s, resp_r) = chan("resp"); - let (cmph_axi_ar_s, cmph_axi_ar_r) = chan("cmph_axi_ar"); - let (cmph_axi_r_s, cmph_axi_r_r) = chan("cmph_axi_r"); + // output from Command constructor to Sequence executor + let (cmd_constr_out_s, cmd_constr_out_r) = chan("cmd_constr_out"); + + // Huffman weights memory + let (huffman_lit_weights_mem_rd_req_s, _huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (_huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, _huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (_huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + + // Huffman prescan memory + let (huffman_lit_prescan_mem_rd_req_s, _huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); + let (_huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); + let (huffman_lit_prescan_mem_wr_req_s, _huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); + let (_huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + + // AXI channels for various blocks + let (axi_ram_rd_req_s, axi_ram_rd_req_r) = chan[AXI_CHAN_N]("axi_ram_rd_req"); + let (axi_ram_rd_resp_s, axi_ram_rd_resp_r) = chan[AXI_CHAN_N]("axi_ram_rd_resp"); + let (axi_ram_wr_req_s, axi_ram_wr_req_r) = chan[AXI_CHAN_N]("axi_ram_wr_req"); + let (axi_ram_wr_resp_s, axi_ram_wr_resp_r) = chan[AXI_CHAN_N]("axi_ram_wr_resp"); + let (axi_ram_ar_s, axi_ram_ar_r) = chan[AXI_CHAN_N]("axi_ram_ar"); + let (axi_ram_r_s, axi_ram_r_r) = chan[AXI_CHAN_N]("axi_ram_r"); + unroll_for! (i, ()): (u32, ()) in range(u32:0, AXI_CHAN_N) { + spawn ram::RamModel< + TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED + >( + axi_ram_rd_req_r[i], axi_ram_rd_resp_s[i], axi_ram_wr_req_r[i], axi_ram_wr_resp_s[i] + ); + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_CASE_RAM_SIZE, + TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_ADDR_WIDTH + >( + axi_ram_ar_r[i], axi_ram_r_s[i], axi_ram_rd_req_s[i], axi_ram_rd_resp_r[i] + ); + }(()); + + // Literals buffer RAMs + let (litbuf_rd_req_s, litbuf_rd_req_r) = chan[u32:8]("litbuf_rd_req"); + let (litbuf_rd_resp_s, litbuf_rd_resp_r) = chan[u32:8]("litbuf_rd_resp"); + let (litbuf_wr_req_s, litbuf_wr_req_r) = chan[u32:8]("litbuf_wr_req"); + let (litbuf_wr_resp_s, litbuf_wr_resp_r) = chan[u32:8]("litbuf_wr_resp"); + unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:8) { + spawn ram::RamModel< + LITERALS_BUFFER_RAM_DATA_WIDTH, LITERALS_BUFFER_RAM_SIZE, LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED + >( + litbuf_rd_req_r[i], litbuf_rd_resp_s[i], litbuf_wr_req_r[i], litbuf_wr_resp_s[i] + ); + }(()); + + // RAMs for FSE decoder + // DPD RAM + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + spawn ram::RamModel( + dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s, + ); + + // TMP RAM + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + spawn ram::RamModel< + TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED + >( + tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, + ); + + // FSE RAMs + let (fse_rd_req_s, fse_rd_req_r) = chan[u32:6]("tmp_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan[u32:6]("tmp_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan[u32:6]("tmp_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan[u32:6]("tmp_wr_resp"); + unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:6) { + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_SIZE, TEST_FSE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED + >( + fse_rd_req_r[i], fse_rd_resp_s[i], fse_wr_req_r[i], fse_wr_resp_s[i] + ); + }(()); + + // Default LL + + let (ll_sel_test_s, ll_sel_test_r) = chan("ll_sel_test"); + + let (ll_def_test_rd_req_s, ll_def_test_rd_req_r) = chan("ll_def_test_rd_req"); + let (ll_def_test_rd_resp_s, ll_def_test_rd_resp_r) = chan("ll_def_test_rd_resp"); + let (ll_def_test_wr_req_s, ll_def_test_wr_req_r) = chan("ll_def_test_wr_req"); + let (ll_def_test_wr_resp_s, ll_def_test_wr_resp_r) = chan("ll_def_test_wr_resp"); + + let (ll_def_fse_rd_req_s, ll_def_fse_rd_req_r) = chan("ll_def_fse_rd_req"); + let (ll_def_fse_rd_resp_s, ll_def_fse_rd_resp_r) = chan("ll_def_fse_rd_resp"); + let (ll_def_fse_wr_req_s, ll_def_fse_wr_req_r) = chan("ll_def_fse_wr_req"); + let (ll_def_fse_wr_resp_s, ll_def_fse_wr_resp_r) = chan("ll_def_fse_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + ll_sel_test_r, + ll_def_test_rd_req_r, ll_def_test_rd_resp_s, ll_def_test_wr_req_r, ll_def_test_wr_resp_s, + ll_def_fse_rd_req_r, ll_def_fse_rd_resp_s, ll_def_fse_wr_req_r, ll_def_fse_wr_resp_s, + fse_rd_req_s[0], fse_rd_resp_r[0], fse_wr_req_s[0], fse_wr_resp_r[0], + ); + + // Default ML + + let (ml_sel_test_s, ml_sel_test_r) = chan("ml_sel_test"); + + let (ml_def_test_rd_req_s, ml_def_test_rd_req_r) = chan("ml_def_test_rd_req"); + let (ml_def_test_rd_resp_s, ml_def_test_rd_resp_r) = chan("ml_def_test_rd_resp"); + let (ml_def_test_wr_req_s, ml_def_test_wr_req_r) = chan("ml_def_test_wr_req"); + let (ml_def_test_wr_resp_s, ml_def_test_wr_resp_r) = chan("ml_def_test_wr_resp"); + + let (ml_def_fse_rd_req_s, ml_def_fse_rd_req_r) = chan("ml_def_fse_rd_req"); + let (ml_def_fse_rd_resp_s, ml_def_fse_rd_resp_r) = chan("ml_def_fse_rd_resp"); + let (ml_def_fse_wr_req_s, ml_def_fse_wr_req_r) = chan("ml_def_fse_wr_req"); + let (ml_def_fse_wr_resp_s, ml_def_fse_wr_resp_r) = chan("ml_def_fse_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + ml_sel_test_r, + ml_def_test_rd_req_r, ml_def_test_rd_resp_s, ml_def_test_wr_req_r, ml_def_test_wr_resp_s, + ml_def_fse_rd_req_r, ml_def_fse_rd_resp_s, ml_def_fse_wr_req_r, ml_def_fse_wr_resp_s, + fse_rd_req_s[2], fse_rd_resp_r[2], fse_wr_req_s[2], fse_wr_resp_r[2], + ); + + // Default OF + + let (of_sel_test_s, of_sel_test_r) = chan("of_sel_test"); + + let (of_def_test_rd_req_s, of_def_test_rd_req_r) = chan("of_def_test_rd_req"); + let (of_def_test_rd_resp_s, of_def_test_rd_resp_r) = chan("of_def_test_rd_resp"); + let (of_def_test_wr_req_s, of_def_test_wr_req_r) = chan("of_def_test_wr_req"); + let (of_def_test_wr_resp_s, of_def_test_wr_resp_r) = chan("of_def_test_wr_resp"); + + let (of_def_fse_rd_req_s, of_def_fse_rd_req_r) = chan("of_def_fse_rd_req"); + let (of_def_fse_rd_resp_s, of_def_fse_rd_resp_r) = chan("of_def_fse_rd_resp"); + let (of_def_fse_wr_req_s, of_def_fse_wr_req_r) = chan("of_def_fse_wr_req"); + let (of_def_fse_wr_resp_s, of_def_fse_wr_resp_r) = chan("of_def_fse_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + of_sel_test_r, + of_def_test_rd_req_r, of_def_test_rd_resp_s, of_def_test_wr_req_r, of_def_test_wr_resp_s, + of_def_fse_rd_req_r, of_def_fse_rd_resp_s, of_def_fse_wr_req_r, of_def_fse_wr_resp_s, + fse_rd_req_s[4], fse_rd_resp_r[4], fse_wr_req_s[4], fse_wr_resp_r[4], + ); spawn CompressBlockDecoder< - TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W + TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, + // FSE lookup table RAMs + TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, >( req_r, resp_s, - cmph_axi_ar_s, cmph_axi_r_r); + cmd_constr_out_s, + axi_ram_ar_s[0], axi_ram_r_r[0], + axi_ram_ar_s[1], axi_ram_r_r[1], + axi_ram_ar_s[2], axi_ram_r_r[2], + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, + fse_rd_req_s[1], fse_rd_resp_r[1], fse_wr_req_s[1], fse_wr_resp_r[1], + ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, + fse_rd_req_s[3], fse_rd_resp_r[3], fse_wr_req_s[3], fse_wr_resp_r[3], + of_def_fse_rd_req_s, of_def_fse_rd_resp_r, of_def_fse_wr_req_s, of_def_fse_wr_resp_r, + fse_rd_req_s[5], fse_rd_resp_r[5], fse_wr_req_s[5], fse_wr_resp_r[5], + axi_ram_ar_s[3], axi_ram_r_r[3], + axi_ram_ar_s[4], axi_ram_r_r[4], + axi_ram_ar_s[5], axi_ram_r_r[5], + axi_ram_ar_s[6], axi_ram_r_r[6], + axi_ram_ar_s[7], axi_ram_r_r[7], + axi_ram_ar_s[8], axi_ram_r_r[8], + axi_ram_ar_s[9], axi_ram_r_r[9], + litbuf_rd_req_s[0], litbuf_rd_req_s[1], litbuf_rd_req_s[2], litbuf_rd_req_s[3], + litbuf_rd_req_s[4], litbuf_rd_req_s[5], litbuf_rd_req_s[6], litbuf_rd_req_s[7], + litbuf_rd_resp_r[0], litbuf_rd_resp_r[1], litbuf_rd_resp_r[2], litbuf_rd_resp_r[3], + litbuf_rd_resp_r[4], litbuf_rd_resp_r[5], litbuf_rd_resp_r[6], litbuf_rd_resp_r[7], + litbuf_wr_req_s[0], litbuf_wr_req_s[1], litbuf_wr_req_s[2], litbuf_wr_req_s[3], + litbuf_wr_req_s[4], litbuf_wr_req_s[5], litbuf_wr_req_s[6], litbuf_wr_req_s[7], + litbuf_wr_resp_r[0], litbuf_wr_resp_r[1], litbuf_wr_resp_r[2], litbuf_wr_resp_r[3], + litbuf_wr_resp_r[4], litbuf_wr_resp_r[5], litbuf_wr_resp_r[6], litbuf_wr_resp_r[7], + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + ); ( terminator, req_s, resp_r, - cmph_axi_ar_r, cmph_axi_r_s + cmd_constr_out_r, + axi_ram_wr_req_s, axi_ram_wr_resp_r, + + ll_sel_test_s, + ll_def_test_rd_req_s, ll_def_test_rd_resp_r, ll_def_test_wr_req_s, ll_def_test_wr_resp_r, + + ml_sel_test_s, + ml_def_test_rd_req_s, ml_def_test_rd_resp_r, ml_def_test_wr_req_s, ml_def_test_wr_resp_r, + + of_sel_test_s, + of_def_test_rd_req_s, of_def_test_rd_resp_r, of_def_test_wr_req_s, of_def_test_wr_resp_r, ) } next(state: ()) { let tok = join(); + + // FILL THE LL DEFAULT RAM + trace_fmt!("Filling LL default FSE table"); + let tok = send(tok, ll_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_LL_TABLE)) { + let req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_W], + data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_LL_TABLE[i]), + mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, ll_def_test_wr_req_s, req); + let (tok, _) = recv(tok, ll_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, ll_sel_test_s, u1:1); + + // FILL THE OF DEFAULT RAM + trace_fmt!("Filling OF default FSE table"); + let tok = send(tok, of_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_OF_TABLE)) { + let req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_W], + data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_OF_TABLE[i]), + mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, of_def_test_wr_req_s, req); + let (tok, _) = recv(tok, of_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, of_sel_test_s, u1:1); + + // FILL THE ML DEFAULT RAM + trace_fmt!("Filling ML default FSE table"); + let tok = send(tok, ml_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_ML_TABLE)) { + let req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_W], + data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_ML_TABLE[i]), + mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, ml_def_test_wr_req_s, req); + let (tok, _) = recv(tok, ml_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, ml_sel_test_s, u1:1); + + let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:6, array_size(COMP_BLOCK_DEC_TESTCASES)) { + let (input_length, input, output_length, output) = COMP_BLOCK_DEC_TESTCASES[test_i]; + + trace_fmt!("Loading testcase {}", test_i); + let tok = for ((i, input_data), tok): ((u32, u64), token) in enumerate(input) { + let req = TestcaseRamWrReq { + addr: i as uN[TEST_CASE_RAM_ADDR_WIDTH], + data: input_data as uN[TEST_CASE_RAM_DATA_WIDTH], + mask: !uN[TEST_CASE_RAM_NUM_PARTITIONS]:0 + }; + // Write to all RAMs + let tok = unroll_for! (j, tok): (u32, token) in range(u32:0, AXI_CHAN_N) { + let tok = send(tok, axi_ram_wr_req_s[j], req); + let (tok, _) = recv(tok, axi_ram_wr_resp_r[j]); + tok + }(tok); + tok + }(tok); + + trace_fmt!("Starting processing testcase {}", test_i); + + let req = Req { + addr: uN[TEST_AXI_ADDR_W]:0x100, + length: input_length as BlockSize, + id: u32:1234, + last_block: false, + }; + + trace_fmt!("Sending request to compressed block decoder: {}", req); + let tok = send(tok, req_s, req); + + let tok = for (i, tok): (u32, token) in range(u32:0, output_length) { + let expected_packet = output[i]; + let (tok, recvd_packet) = recv(tok, cmd_constr_out_r); + trace_fmt!("Received {} command constructor packet: {:#x}", i, recvd_packet); + assert_eq(expected_packet, recvd_packet); + tok + }(tok); + + let (tok, _) = recv(tok, resp_r); + trace_fmt!("Finished processing testcase {}", test_i); + tok + }(tok); + send(tok, terminator, true); } } From 81fa10d56342f02b433dd4cc15df77bfe8d3fe54 Mon Sep 17 00:00:00 2001 From: Krzysztof Oblonczek Date: Mon, 12 May 2025 20:02:31 +0200 Subject: [PATCH 47/85] modules/zstd: Enable CompressedBlockDecoder in ZstdDecoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Robert Winkler Signed-off-by: Robert Winkler Signed-off-by: Krzysztof Obłonczek --- xls/modules/zstd/BUILD | 7 +- xls/modules/zstd/zstd_dec.x | 424 +++++++++++++++++++++++-- xls/modules/zstd/zstd_dec_test.x | 529 ++++++++++++++++++++++++------- 3 files changed, 835 insertions(+), 125 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 5e485baf41..3cc6c22d56 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1251,7 +1251,11 @@ zstd_dec_deps = [ ":frame_header_dec_dslx", ":raw_block_dec_dslx", ":rle_block_dec_dslx", + ":comp_block_dec_dslx", ":sequence_executor_dslx", + ":huffman_literals_dec_dslx", + ":literals_buffer_dslx", + ":parallel_rams_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:mem_writer_dslx", @@ -1271,7 +1275,8 @@ xls_dslx_test( srcs = [ "zstd_dec.x", "zstd_dec_test.x", - "zstd_frame_testcases.x", + # "zstd_frame_testcases.x", + "comp_frame.x", ], tags = ["manual"], deps = zstd_dec_deps, diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index 4657e9845a..f88227e88e 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -29,8 +29,12 @@ import xls.modules.zstd.block_header; import xls.modules.zstd.block_header_dec; import xls.modules.zstd.raw_block_dec; import xls.modules.zstd.rle_block_dec; +import xls.modules.zstd.comp_block_dec; import xls.modules.zstd.dec_mux; import xls.modules.zstd.sequence_executor; +import xls.modules.zstd.huffman_literals_dec; +import xls.modules.zstd.literals_buffer; +import xls.modules.zstd.parallel_rams; type BlockSize = common::BlockSize; type BlockType = common::BlockType; @@ -64,6 +68,7 @@ enum ZstdDecoderStatus: u5 { RAW_BLOCK_OK = 9, RAW_BLOCK_ERROR = 10, RLE_BLOCK_OK = 11, + CMP_BLOCK_OK = 12, } pub enum Csr: u3 { @@ -148,6 +153,10 @@ proc ZstdDecoderInternal< type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + type CompressBlockDecoderStatus = comp_block_dec::CompressBlockDecoderStatus; + type CompressBlockDecoderReq = comp_block_dec::CompressBlockDecoderReq; + type CompressBlockDecoderResp = comp_block_dec::CompressBlockDecoderResp; + // CsrConfig csr_rd_req_s: chan out; csr_rd_resp_r: chan in; @@ -171,6 +180,9 @@ proc ZstdDecoderInternal< rle_req_s: chan out; rle_resp_r: chan in; + comp_block_req_s: chan out; + comp_block_resp_r: chan in; + // Output MemWriter output_mem_wr_req_s: chan out; output_mem_wr_resp_r: chan in; @@ -205,6 +217,10 @@ proc ZstdDecoderInternal< rle_req_s: chan out, rle_resp_r: chan in, + // MemReader + CompressedBlockDecoder + comp_block_req_s: chan out, + comp_block_resp_r: chan in, + // Output MemWriter output_mem_wr_req_s: chan out, output_mem_wr_resp_r: chan in, @@ -218,6 +234,7 @@ proc ZstdDecoderInternal< bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + comp_block_req_s, comp_block_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ) @@ -342,9 +359,27 @@ proc ZstdDecoderInternal< trace_fmt!("[DECODE_RLE_BLOCK]: Received RAW {:#x}", raw_resp); } else {}; + let do_send_cmp_req = (state.fsm == Fsm::DECODE_COMPRESSED_BLOCK) && !state.req_sent; + let cmp_req = CompressBlockDecoderReq { + addr: state.block_addr, + length: checked_cast(state.block_length), + id: state.block_id, + last_block: state.block_last, + }; + let tok1_8 = send_if(tok0, comp_block_req_s, do_send_cmp_req, cmp_req); + if do_send_cmp_req { + trace_fmt!("[DECODE_COMPRESSED_BLOCK]: Sending COMPRESSED request: {:#x}", cmp_req); + } else {}; + + let do_recv_cmp_resp = (state.fsm == Fsm::DECODE_COMPRESSED_BLOCK); + let (tok1_9, cmp_resp, cmp_resp_valid) = recv_if_non_blocking(tok0, comp_block_resp_r, do_recv_cmp_resp, zero!()); + if cmp_resp_valid { + trace_fmt!("[DECODE_COMPRESSED_BLOCK]: Received COMPRESSED {:#x}", cmp_resp); + } else {}; + let new_state = match (state.fsm) { Fsm::IDLE => { - trace_fmt!("[IDLE]"); + // trace_fmt!("[IDLE]"); if is_start { let status = ZstdDecoderStatus::RUNNING; @@ -359,7 +394,7 @@ proc ZstdDecoderInternal< }, Fsm::READ_CONFIG => { - trace_fmt!("[READ_CONFIG]"); + // trace_fmt!("[READ_CONFIG]"); let is_input_buffer_csr = (csr_data.csr == csr(Csr::INPUT_BUFFER)); let input_buffer = if csr_data_valid && is_input_buffer_csr { checked_cast(csr_data.value) } else { state.input_buffer }; let input_buffer_valid = if csr_data_valid && is_input_buffer_csr { true } else { state.input_buffer_valid }; @@ -392,7 +427,7 @@ proc ZstdDecoderInternal< }, Fsm::DECODE_FRAME_HEADER => { - trace_fmt!("[DECODE_FRAME_HEADER]"); + // trace_fmt!("[DECODE_FRAME_HEADER]"); let error = (fh_resp.status != FrameHeaderDecoderStatus::OKAY); let status = match(fh_resp_valid, fh_resp.status) { @@ -420,7 +455,7 @@ proc ZstdDecoderInternal< }, Fsm::DECODE_BLOCK_HEADER => { - trace_fmt!("[DECODE_BLOCK_HEADER]"); + // trace_fmt!("[DECODE_BLOCK_HEADER]"); let error = (bh_resp.status != BlockHeaderDecoderStatus::OKAY); let status = match(bh_resp_valid, bh_resp.status) { @@ -439,7 +474,7 @@ proc ZstdDecoderInternal< let fsm = match (bh_resp_valid, error, bh_resp.header.btype) { ( true, false, BlockType::RAW ) => Fsm::DECODE_RAW_BLOCK, ( true, false, BlockType::RLE ) => Fsm::DECODE_RLE_BLOCK, - ( true, false, BlockType::COMPRESSED) => Fsm::ERROR, + ( true, false, BlockType::COMPRESSED) => Fsm::DECODE_COMPRESSED_BLOCK, ( true, true, _) => Fsm::ERROR, ( _, _, _) => Fsm::DECODE_BLOCK_HEADER, }; @@ -471,7 +506,7 @@ proc ZstdDecoderInternal< }, Fsm::DECODE_RAW_BLOCK => { - trace_fmt!("[DECODE_RAW_BLOCK]"); + // trace_fmt!("[DECODE_RAW_BLOCK]"); let error = (raw_resp.status != RawBlockDecoderStatus::OKAY); @@ -506,7 +541,7 @@ proc ZstdDecoderInternal< }, Fsm::DECODE_RLE_BLOCK => { - trace_fmt!("[DECODE_RLE_BLOCK]"); + // trace_fmt!("[DECODE_RLE_BLOCK]"); let error = (rle_resp.status != RleBlockDecoderStatus::OKAY); let status = match(rle_resp_valid, rle_resp.status) { @@ -538,14 +573,47 @@ proc ZstdDecoderInternal< state }, + Fsm::DECODE_COMPRESSED_BLOCK => { + // trace_fmt!("[DECODE_COMPRESSED_BLOCK]"); + let error = (cmp_resp.status != CompressBlockDecoderStatus::OK); + + let status = match(cmp_resp_valid, cmp_resp.status) { + (true, CompressBlockDecoderStatus::OK) => ZstdDecoderStatus::CMP_BLOCK_OK, + (_, _) => ZstdDecoderStatus::RUNNING, + }; + + let csr_wr_req_valid = (cmp_resp_valid); + let csr_wr_req = CsrWrReq { + csr: csr(Csr::STATUS), + value: status as Data, + }; + + let fsm = match (cmp_resp_valid, error, state.block_last) { + (true, false, false) => Fsm::DECODE_BLOCK_HEADER, + (true, false, true) => Fsm::DECODE_CHECKSUM, + (true, true, _) => Fsm::ERROR, + ( _, _, _) => Fsm::DECODE_COMPRESSED_BLOCK, + }; + + let req_sent = if !raw_resp_valid && !error { true } else { false }; + let block_id = if raw_resp_valid { state.block_id + u32:1} else {state.block_id }; + + let state = State {fsm, block_id, csr_wr_req, csr_wr_req_valid, req_sent, ..state}; + if fsm == Fsm::DECODE_BLOCK_HEADER { + trace_fmt!("Going to decode block header: {:#x}", state); + } else {}; + + state + }, + Fsm::DECODE_CHECKSUM => { - trace_fmt!("[DECODE_CHECKSUM]"); + // trace_fmt!("[DECODE_CHECKSUM]"); State {fsm: Fsm::WRITE_OUTPUT, ..zero!() } }, Fsm::WRITE_OUTPUT => { - trace_fmt!("[WRITE_OUTPUT]"); + // trace_fmt!("[WRITE_OUTPUT]"); let error = (output_write_resp.status != mem_writer::MemWriterRespStatus::OKAY); let fsm = match (output_write_done, error) { (true, false) => Fsm::FINISH, @@ -557,12 +625,12 @@ proc ZstdDecoderInternal< }, Fsm::ERROR => { - trace_fmt!("[ERROR]"); + // trace_fmt!("[ERROR]"); State { fsm: Fsm::IDLE, ..zero!() } }, Fsm::FINISH => { - trace_fmt!("[FINISH]"); + // trace_fmt!("[FINISH]"); let csr_wr_req_valid = true; let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), @@ -620,6 +688,10 @@ proc ZstdDecoderInternalTest { type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; type RleBlockDecoderStatus = rle_block_dec::RleBlockDecoderStatus; + type CompressBlockDecoderReq = comp_block_dec::CompressBlockDecoderReq; + type CompressBlockDecoderResp = comp_block_dec::CompressBlockDecoderResp; + type CompressBlockDecoderStatus = comp_block_dec::CompressBlockDecoderStatus; + type MemWriterReq = mem_writer::MemWriterReq; type MemWriterResp = mem_writer::MemWriterResp; @@ -643,6 +715,9 @@ proc ZstdDecoderInternalTest { rle_req_r: chan in; rle_resp_s: chan out; + comp_block_req_r: chan in; + comp_block_resp_s: chan out; + output_mem_wr_req_r: chan in; output_mem_wr_resp_s: chan out; @@ -670,6 +745,9 @@ proc ZstdDecoderInternalTest { let (rle_req_s, rle_req_r) = chan("rle_req"); let (rle_resp_s, rle_resp_r) = chan("rle_resp"); + let (comp_block_req_s, comp_block_req_r) = chan("comp_block_req"); + let (comp_block_resp_s, comp_block_resp_r) = chan("comp_block_resp"); + let (output_mem_wr_req_s, output_mem_wr_req_r) = chan("output_mem_wr_req"); let (output_mem_wr_resp_s, output_mem_wr_resp_r) = chan("output_mem_wr_resp"); @@ -682,6 +760,7 @@ proc ZstdDecoderInternalTest { bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + comp_block_req_s, comp_block_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ); @@ -693,6 +772,7 @@ proc ZstdDecoderInternalTest { bh_req_r, bh_resp_s, raw_req_r, raw_resp_s, rle_req_r, rle_resp_s, + comp_block_req_r, comp_block_resp_s, output_mem_wr_req_r, output_mem_wr_resp_s, notify_r, reset_r, ) @@ -865,11 +945,32 @@ pub proc ZstdDecoder< // decoder parameters REGS_N: u32, WINDOW_LOG_MAX: u32, HB_ADDR_W: u32, HB_DATA_W: u32, HB_NUM_PARTITIONS: u32, HB_SIZE_KB: u32, + + DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + + HISTORY_BUFFER_SIZE_KB: u32, + AXI_CHAN_N: u32, + // calculated parameters AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, LOG2_REGS_N: u32 = {std::clog2(REGS_N)}, HB_RAM_N: u32 = {u32:8}, MEM_WRITER_ID: u32 = {u32:0}, + HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = {huffman_literals_dec::WEIGHTS_ADDR_WIDTH}, + HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = {huffman_literals_dec::WEIGHTS_DATA_WIDTH}, + HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::WEIGHTS_NUM_PARTITIONS}, + // Huffman prescan memory parameters + HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = {huffman_literals_dec::PRESCAN_ADDR_WIDTH}, + HUFFMAN_PRESCAN_RAM_DATA_W: u32 = {huffman_literals_dec::PRESCAN_DATA_WIDTH}, + HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::PRESCAN_NUM_PARTITIONS}, + // Literals buffer memory parameters + LITERALS_BUFFER_RAM_ADDR_W: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + LITERALS_BUFFER_RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, + LITERALS_BUFFER_RAM_DATA_W: u32 = {literals_buffer::RAM_DATA_WIDTH}, + LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = {literals_buffer::RAM_NUM_PARTITIONS}, + LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = {LITERALS_BUFFER_RAM_DATA_W}, > { type CsrAxiAr = axi::AxiAr; type CsrAxiR = axi::AxiR; @@ -916,8 +1017,44 @@ pub proc ZstdDecoder< type RamWrReq = ram::WriteReq; type RamWrResp = ram::WriteResp; + type CompressBlockDecoderReq = comp_block_dec::CompressBlockDecoderReq; + type CompressBlockDecoderResp = comp_block_dec::CompressBlockDecoderResp; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type CommandConstructorData = common::CommandConstructorData; + + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; + type LitBufRamWrResp = ram::WriteResp; + // Complex Block Decoder cmp_output_s: chan out; + comp_block_req_s: chan out; + comp_block_resp_r: chan in; init {} @@ -933,14 +1070,50 @@ pub proc ZstdDecoder< fh_axi_ar_s: chan out, fh_axi_r_r: chan in, - //// AXI Block Header Decoder (manager) + // AXI Block Header Decoder (manager) bh_axi_ar_s: chan out, bh_axi_r_r: chan in, - //// AXI RAW Block Decoder (manager) + // AXI RAW Block Decoder (manager) raw_axi_ar_s: chan out, raw_axi_r_r: chan in, + // AXI Compressed Block Decoder + comp_axi_ram_ar_s: chan[AXI_CHAN_N] out, + comp_axi_ram_r_r: chan[AXI_CHAN_N] in, + + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + fse_rd_req_s: chan[u32:6] out, + fse_rd_resp_r: chan[u32:6] in, + fse_wr_req_s: chan[u32:6] out, + fse_wr_resp_r: chan[u32:6] in, + + litbuf_rd_req_s: chan[u32:8] out, + litbuf_rd_resp_r: chan[u32:8] in, + litbuf_wr_req_s: chan[u32:8] out, + litbuf_wr_resp_r: chan[u32:8] in, + + // Huffman weights memory + huffman_lit_weights_mem_rd_req_s: chan out, + huffman_lit_weights_mem_rd_resp_r: chan in, + huffman_lit_weights_mem_wr_req_s: chan out, + huffman_lit_weights_mem_wr_resp_r: chan in, + + // Huffman prescan memory + huffman_lit_prescan_mem_rd_req_s: chan out, + huffman_lit_prescan_mem_rd_resp_r: chan in, + huffman_lit_prescan_mem_wr_req_s: chan out, + huffman_lit_prescan_mem_wr_resp_r: chan in, + //// AXI Output Writer (manager) output_axi_aw_s: chan out, output_axi_w_s: chan out, @@ -1079,13 +1252,70 @@ pub proc ZstdDecoder< rle_req_r, rle_resp_s, rle_output_s ); + // Compressed block decoder + + let (comp_block_req_s, comp_block_req_r) = chan("comp_block_req"); + let (comp_block_resp_s, comp_block_resp_r) = chan("comp_block_resp"); + + let (cmd_output_s, cmd_output_r) = chan("cmd_output"); + + spawn comp_block_dec::CompressBlockDecoder< + AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W, + // FSE lookup table RAMs + DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, + TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, + >( + // MAIN IOs + + comp_block_req_r, comp_block_resp_s, + cmd_output_s, + + // SEQUENCE DECODING + + // axi channels for sequence decoding + comp_axi_ram_ar_s[0], comp_axi_ram_r_r[0], + comp_axi_ram_ar_s[1], comp_axi_ram_r_r[1], + comp_axi_ram_ar_s[2], comp_axi_ram_r_r[2], + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + fse_rd_req_s[0], fse_rd_resp_r[0], fse_wr_req_s[0], fse_wr_resp_r[0], + fse_rd_req_s[1], fse_rd_resp_r[1], fse_wr_req_s[1], fse_wr_resp_r[1], + fse_rd_req_s[2], fse_rd_resp_r[2], fse_wr_req_s[2], fse_wr_resp_r[2], + fse_rd_req_s[3], fse_rd_resp_r[3], fse_wr_req_s[3], fse_wr_resp_r[3], + fse_rd_req_s[4], fse_rd_resp_r[4], fse_wr_req_s[4], fse_wr_resp_r[4], + fse_rd_req_s[5], fse_rd_resp_r[5], fse_wr_req_s[5], fse_wr_resp_r[5], + + // LITERALS DECODING + + // axi channels for literals decoding + comp_axi_ram_ar_s[3], comp_axi_ram_r_r[3], + comp_axi_ram_ar_s[4], comp_axi_ram_r_r[4], + comp_axi_ram_ar_s[5], comp_axi_ram_r_r[5], + comp_axi_ram_ar_s[6], comp_axi_ram_r_r[6], + comp_axi_ram_ar_s[7], comp_axi_ram_r_r[7], + comp_axi_ram_ar_s[8], comp_axi_ram_r_r[8], + comp_axi_ram_ar_s[9], comp_axi_ram_r_r[9], + litbuf_rd_req_s[0], litbuf_rd_req_s[1], litbuf_rd_req_s[2], litbuf_rd_req_s[3], + litbuf_rd_req_s[4], litbuf_rd_req_s[5], litbuf_rd_req_s[6], litbuf_rd_req_s[7], + litbuf_rd_resp_r[0], litbuf_rd_resp_r[1], litbuf_rd_resp_r[2], litbuf_rd_resp_r[3], + litbuf_rd_resp_r[4], litbuf_rd_resp_r[5], litbuf_rd_resp_r[6], litbuf_rd_resp_r[7], + litbuf_wr_req_s[0], litbuf_wr_req_s[1], litbuf_wr_req_s[2], litbuf_wr_req_s[3], + litbuf_wr_req_s[4], litbuf_wr_req_s[5], litbuf_wr_req_s[6], litbuf_wr_req_s[7], + litbuf_wr_resp_r[0], litbuf_wr_resp_r[1], litbuf_wr_resp_r[2], litbuf_wr_resp_r[3], + litbuf_wr_resp_r[4], litbuf_wr_resp_r[5], litbuf_wr_resp_r[6], litbuf_wr_resp_r[7], + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + ); + // Collecting Packets - let (cmp_output_s, cmp_output_r) = chan("cmp_output"); let (seq_exec_input_s, seq_exec_input_r) = chan("demux_output"); spawn dec_mux::DecoderMux( - raw_output_r, rle_output_r, cmp_output_r, + raw_output_r, rle_output_r, cmd_output_r, seq_exec_input_s, ); @@ -1121,11 +1351,40 @@ pub proc ZstdDecoder< bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + comp_block_req_s, comp_block_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ); - (cmp_output_s,) + + // // Sequence config (section header) decoder's memory reader + // let (scd_mem_rd_req_s, scd_mem_rd_req_r) = chan("scd_mem_rd_req"); + // let (scd_mem_rd_resp_s, scd_mem_rd_resp_r) = chan("scd_mem_rd_resp"); + + // spawn mem_reader::MemReader( + // scd_mem_rd_req_r, scd_mem_rd_resp_s, + // scd_axi_ar_s, scd_axi_r_r, + // ); + + // // FSE lookup decoder's memory reader for RefillingShiftBuffer + // let (fse_lookup_mem_rd_req_s, fse_lookup_mem_rd_req_r) = chan("fse_lookup_mem_rd_req"); + // let (fse_lookup_mem_rd_resp_s, fse_lookup_mem_rd_resp_r) = chan("fse_lookup_mem_rd_resp"); + + // spawn mem_reader::MemReader( + // fse_lookup_mem_rd_req_r, fse_lookup_mem_rd_resp_s, + // fse_lookup_axi_ar_s, fse_lookup_axi_r_r, + // ); + + // // FSE decoder's memory reader for RefillingShiftBuffer + // let (fse_dec_mem_rd_req_s, fse_dec_mem_rd_req_r) = chan("scd_mem_rd_req"); + // let (fse_dec_mem_rd_resp_s, fse_dec_mem_rd_resp_r) = chan("scd_mem_rd_resp"); + + // spawn mem_reader::MemReader( + // fse_dec_mem_rd_req_r, fse_dec_mem_rd_resp_s, + // fse_dec_axi_ar_s, fse_dec_axi_r_r, + // ); + + (cmd_output_s, comp_block_req_s, comp_block_resp_r) } next (state: ()) { @@ -1148,6 +1407,46 @@ const INST_LOG2_REGS_N = std::clog2(INST_REGS_N); const INST_AXI_DATA_W_DIV8 = INST_AXI_DATA_W / u32:8; const INST_HB_RAM_N = u32:8; +const INST_DPD_RAM_DATA_W = u32:16; +const INST_DPD_RAM_SIZE = u32:256; +const INST_DPD_RAM_ADDR_W = std::clog2(INST_DPD_RAM_SIZE); +const INST_DPD_RAM_WORD_PARTITION_SIZE = INST_DPD_RAM_DATA_W; +const INST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_DPD_RAM_WORD_PARTITION_SIZE, INST_DPD_RAM_DATA_W); + +const INST_FSE_RAM_DATA_W = u32:32; +const INST_FSE_RAM_SIZE = u32:256; +const INST_FSE_RAM_ADDR_W = std::clog2(INST_FSE_RAM_SIZE); +const INST_FSE_RAM_WORD_PARTITION_SIZE = INST_FSE_RAM_DATA_W / u32:3; +const INST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_FSE_RAM_WORD_PARTITION_SIZE, INST_FSE_RAM_DATA_W); + +const INST_TMP_RAM_DATA_W = u32:16; +const INST_TMP_RAM_SIZE = u32:256; +const INST_TMP_RAM_ADDR_W = std::clog2(INST_TMP_RAM_SIZE); +const INST_TMP_RAM_WORD_PARTITION_SIZE = INST_TMP_RAM_DATA_W; +const INST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_TMP_RAM_WORD_PARTITION_SIZE, INST_TMP_RAM_DATA_W); + +const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; +const HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; +const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; +// Huffman prescan memory parameters +const HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; +const HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; +const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; + +const INST_HISTORY_BUFFER_SIZE_KB = u32:64; +const INST_AXI_CHAN_N = u32:10; + +// Literals buffer memory parameters +const LITERALS_BUFFER_RAM_ADDR_W: u32 = parallel_rams::ram_addr_width(INST_HISTORY_BUFFER_SIZE_KB); +const LITERALS_BUFFER_RAM_SIZE: u32 = parallel_rams::ram_size(INST_HISTORY_BUFFER_SIZE_KB); +const LITERALS_BUFFER_RAM_DATA_W: u32 = literals_buffer::RAM_DATA_WIDTH; +const LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; +const LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = LITERALS_BUFFER_RAM_DATA_W; + + proc ZstdDecoderInternalInst { type State = ZstdDecoderInternalState; type Fsm = ZstdDecoderInternalFsm; @@ -1170,6 +1469,9 @@ proc ZstdDecoderInternalInst { type RleBlockDecoderReq = rle_block_dec::RleBlockDecoderReq; type RleBlockDecoderResp = rle_block_dec::RleBlockDecoderResp; + type CompressBlockDecoderReq = comp_block_dec::CompressBlockDecoderReq; + type CompressBlockDecoderResp = comp_block_dec::CompressBlockDecoderResp; + type MemWriterReq = mem_writer::MemWriterReq; type MemWriterResp = mem_writer::MemWriterResp; @@ -1198,6 +1500,9 @@ proc ZstdDecoderInternalInst { rle_req_s: chan out, rle_resp_r: chan in, + comp_req_s: chan out, + comp_resp_r: chan in, + // Output MemWriter output_mem_wr_req_s: chan out, output_mem_wr_resp_r: chan in, @@ -1214,6 +1519,7 @@ proc ZstdDecoderInternalInst { bh_req_s, bh_resp_r, raw_req_s, raw_resp_r, rle_req_s, rle_resp_r, + comp_req_s, comp_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, notify_s, reset_s, ); @@ -1243,6 +1549,35 @@ proc ZstdDecoderInst { type ZstdDecodedPacket = common::ZstdDecodedPacket; + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; + type LitBufRamWrResp = ram::WriteResp; + + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + init { } config( @@ -1257,14 +1592,49 @@ proc ZstdDecoderInst { fh_axi_ar_s: chan out, fh_axi_r_r: chan in, - // AXI Block Header Decoder (manager) + //// AXI Block Header Decoder (manager) bh_axi_ar_s: chan out, bh_axi_r_r: chan in, - // AXI RAW Block Decoder (manager) + //// AXI RAW Block Decoder (manager) raw_axi_ar_s: chan out, raw_axi_r_r: chan in, + axi_ram_ar_s: chan[INST_AXI_CHAN_N] out, + axi_ram_r_r: chan[INST_AXI_CHAN_N] in, + + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + fse_rd_req_s: chan[u32:6] out, + fse_rd_resp_r: chan[u32:6] in, + fse_wr_req_s: chan[u32:6] out, + fse_wr_resp_r: chan[u32:6] in, + + litbuf_rd_req_s: chan[u32:8] out, + litbuf_rd_resp_r: chan[u32:8] in, + litbuf_wr_req_s: chan[u32:8] out, + litbuf_wr_resp_r: chan[u32:8] in, + + // Huffman weights memory + huffman_lit_weights_mem_rd_req_s: chan out, + huffman_lit_weights_mem_rd_resp_r: chan in, + huffman_lit_weights_mem_wr_req_s: chan out, + huffman_lit_weights_mem_wr_resp_r: chan in, + + // Huffman prescan memory + huffman_lit_prescan_mem_rd_req_s: chan out, + huffman_lit_prescan_mem_rd_resp_r: chan in, + huffman_lit_prescan_mem_wr_req_s: chan out, + huffman_lit_prescan_mem_wr_resp_r: chan in, + //// AXI Output Writer (manager) output_axi_aw_s: chan out, output_axi_w_s: chan out, @@ -1311,11 +1681,29 @@ proc ZstdDecoderInst { INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, INST_REGS_N, INST_WINDOW_LOG_MAX, INST_HB_ADDR_W, INST_HB_DATA_W, INST_HB_NUM_PARTITIONS, INST_HB_SIZE_KB, + INST_DPD_RAM_ADDR_W, INST_DPD_RAM_DATA_W, INST_DPD_RAM_NUM_PARTITIONS, + INST_TMP_RAM_ADDR_W, INST_TMP_RAM_DATA_W, INST_TMP_RAM_NUM_PARTITIONS, + INST_FSE_RAM_ADDR_W, INST_FSE_RAM_DATA_W, INST_FSE_RAM_NUM_PARTITIONS, + INST_HISTORY_BUFFER_SIZE_KB, + INST_AXI_CHAN_N, >( csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, fh_axi_ar_s, fh_axi_r_r, bh_axi_ar_s, bh_axi_r_r, raw_axi_ar_s, raw_axi_r_r, + axi_ram_ar_s, axi_ram_r_r, + dpd_rd_req_s, dpd_rd_resp_r, + dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, + tmp_wr_req_s, tmp_wr_resp_r, + fse_rd_req_s, fse_rd_resp_r, + fse_wr_req_s, fse_wr_resp_r, + litbuf_rd_req_s, litbuf_rd_resp_r, + litbuf_wr_req_s, litbuf_wr_resp_r, + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, output_axi_aw_s, output_axi_w_s, output_axi_b_r, ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index bd90210ef1..a115e1f83c 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -18,9 +18,18 @@ import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; import xls.modules.zstd.csr_config; import xls.modules.zstd.sequence_executor; -import xls.modules.zstd.zstd_frame_testcases; +// import xls.modules.zstd.zstd_frame_testcases; import xls.modules.zstd.memory.axi_ram; import xls.modules.zstd.zstd_dec; +import xls.modules.zstd.comp_block_dec; +import xls.modules.zstd.sequence_dec; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.huffman_literals_dec; +import xls.modules.zstd.parallel_rams; +import xls.modules.zstd.literals_buffer; +import xls.modules.zstd.fse_table_creator; +import xls.modules.zstd.ram_mux; +import xls.modules.zstd.comp_frame; const TEST_WINDOW_LOG_MAX = u32:30; @@ -45,7 +54,7 @@ const TEST_HB_RAM_INITIALIZED = sequence_executor::TEST_RAM_INITIALIZED; const TEST_HB_RAM_ASSERT_VALID_READ:bool = false; const TEST_RAM_DATA_W:u32 = TEST_AXI_DATA_W; -const TEST_RAM_SIZE:u32 = u32:16384; +const TEST_RAM_SIZE:u32 = u32:512; const TEST_RAM_ADDR_W:u32 = std::clog2(TEST_RAM_SIZE); const TEST_RAM_WORD_PARTITION_SIZE:u32 = u32:8; const TEST_RAM_NUM_PARTITIONS:u32 = ram::num_partitions(TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_DATA_W); @@ -53,7 +62,47 @@ const TEST_RAM_BASE_ADDR:u32 = u32:0; const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; const TEST_RAM_INITIALIZED = true; -const TEST_MOCK_OUTPUT_RAM_SIZE:u32 = TEST_RAM_SIZE / TEST_AXI_DATA_W_DIV8; +const TEST_DPD_RAM_DATA_W = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_W = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_W; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); + +const TEST_FSE_RAM_DATA_W = u32:32; +const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); + +const TEST_TMP_RAM_DATA_W = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_W = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); + +const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; +const HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; +const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; +// Huffman prescan memory parameters +const HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; +const HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; +const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; + +const HISTORY_BUFFER_SIZE_KB = common::HISTORY_BUFFER_SIZE_KB; + +// Literals buffer memory parameters +const LITERALS_BUFFER_RAM_ADDR_W: u32 = parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB); +const LITERALS_BUFFER_RAM_SIZE: u32 = parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB); +const LITERALS_BUFFER_RAM_DATA_W: u32 = literals_buffer::RAM_DATA_WIDTH; +const LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; +const LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = LITERALS_BUFFER_RAM_DATA_W; + +const AXI_CHAN_N = u32:10; + +const TEST_MOCK_OUTPUT_RAM_SIZE:u32 = TEST_RAM_SIZE; fn csr_addr(c: zstd_dec::Csr) -> uN[TEST_AXI_ADDR_W] { (c as uN[TEST_AXI_ADDR_W]) << 3 @@ -90,33 +139,106 @@ proc ZstdDecoderTest { type RamWrResp = ram::WriteResp; type ZstdDecodedPacket = common::ZstdDecodedPacket; + + type Req = comp_block_dec::CompressBlockDecoderReq; + type Resp = comp_block_dec::CompressBlockDecoderResp; + + type SequenceDecReq = sequence_dec::SequenceDecoderReq; + type SequenceDecResp = sequence_dec::SequenceDecoderResp; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + type MemAxiAw = axi::AxiAw; + type MemAxiW = axi::AxiW; + type MemAxiB = axi::AxiB; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type SequenceExecutorPacket = common::SequenceExecutorPacket; + type CommandConstructorData = common::CommandConstructorData; + + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; + type HuffmanPrescanWriteResp = ram::WriteResp; + + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; + type LitBufRamWrResp = ram::WriteResp; + terminator: chan out; + csr_axi_aw_s: chan out; csr_axi_w_s: chan out; csr_axi_b_r: chan in; csr_axi_ar_s: chan out; csr_axi_r_r: chan in; + fh_axi_ar_r: chan in; fh_axi_r_s: chan out; + fh_ram_wr_req_s: chan out; + fh_raw_wr_resp_r: chan in; + bh_axi_ar_r: chan in; bh_axi_r_s: chan out; + bh_ram_wr_req_s: chan out; + bh_raw_wr_resp_r: chan in; + raw_axi_ar_r: chan in; raw_axi_r_s: chan out; + raw_ram_wr_req_s: chan out; + raw_raw_wr_resp_r: chan in; + + comp_ram_wr_req_s: chan[AXI_CHAN_N] out; + comp_ram_wr_resp_r: chan[AXI_CHAN_N] in; + output_axi_aw_r: chan in; output_axi_w_r: chan in; output_axi_b_s: chan out; - ram_rd_req_r: chan[8] in; - ram_rd_resp_s: chan[8] out; - ram_wr_req_r: chan[8] in; - ram_wr_resp_s: chan[8] out; - - ram_wr_req_fh_s: chan out; - ram_wr_req_bh_s: chan out; - ram_wr_req_raw_s: chan out; - raw_wr_resp_fh_r: chan in; - raw_wr_resp_bh_r: chan in; - raw_wr_resp_raw_r: chan in; + hb_ram_rd_req_r: chan[8] in; + hb_ram_rd_resp_s: chan[8] out; + hb_ram_wr_req_r: chan[8] in; + hb_ram_wr_resp_s: chan[8] out; + + ll_sel_test_s: chan out; + ll_def_test_rd_req_s: chan out; + ll_def_test_rd_resp_r: chan in; + ll_def_test_wr_req_s: chan out; + ll_def_test_wr_resp_r: chan in; + + ml_sel_test_s: chan out; + ml_def_test_rd_req_s: chan out; + ml_def_test_rd_resp_r: chan in; + ml_def_test_wr_req_s: chan out; + ml_def_test_wr_resp_r: chan in; + + of_sel_test_s: chan out; + of_def_test_rd_req_s: chan out; + of_def_test_rd_resp_r: chan in; + of_def_test_wr_req_s: chan out; + of_def_test_wr_resp_r: chan in; notify_r: chan<()> in; reset_r: chan<()> in; @@ -133,170 +255,365 @@ proc ZstdDecoderTest { let (fh_axi_ar_s, fh_axi_ar_r) = chan("fh_axi_ar"); let (fh_axi_r_s, fh_axi_r_r) = chan("fh_axi_r"); + let (fh_ram_wr_req_s, fh_ram_wr_req_r) = chan("fh_ram_wr_req"); + let (fh_ram_wr_resp_s, fh_ram_wr_resp_r) = chan("fh_ram_wr_resp"); + let (fh_ram_rd_req_s, fh_ram_rd_req_r) = chan("fh_ram_rd_req"); + let (fh_ram_rd_resp_s, fh_ram_rd_resp_r) = chan("fh_ram_rd_resp"); let (bh_axi_ar_s, bh_axi_ar_r) = chan("bh_axi_ar"); let (bh_axi_r_s, bh_axi_r_r) = chan("bh_axi_r"); + let (bh_ram_rd_req_s, bh_ram_rd_req_r) = chan("bh_ram_rd_req"); + let (bh_ram_rd_resp_s, bh_ram_rd_resp_r) = chan("bh_ram_rd_resp"); + let (bh_ram_wr_req_s, bh_ram_wr_req_r) = chan("bh_ram_wr_req"); + let (bh_ram_wr_resp_s, bh_ram_wr_resp_r) = chan("bh_ram_wr_resp"); let (raw_axi_ar_s, raw_axi_ar_r) = chan("raw_axi_ar"); let (raw_axi_r_s, raw_axi_r_r) = chan("raw_axi_r"); + let (raw_ram_rd_req_s, raw_ram_rd_req_r) = chan("raw_ram_rd_req"); + let (raw_ram_rd_resp_s, raw_ram_rd_resp_r) = chan("raw_ram_rd_resp"); + let (raw_ram_wr_req_s, raw_ram_wr_req_r) = chan("raw_ram_wr_req"); + let (raw_ram_wr_resp_s, raw_ram_wr_resp_r) = chan("raw_ram_wr_resp"); let (output_axi_aw_s, output_axi_aw_r) = chan("output_axi_aw"); let (output_axi_w_s, output_axi_w_r) = chan("output_axi_w"); let (output_axi_b_s, output_axi_b_r) = chan("output_axi_b"); - let (ram_rd_req_s, ram_rd_req_r) = chan[8]("ram_rd_req"); - let (ram_rd_resp_s, ram_rd_resp_r) = chan[8]("ram_rd_resp"); - let (ram_wr_req_s, ram_wr_req_r) = chan[8]("ram_wr_req"); - let (ram_wr_resp_s, ram_wr_resp_r) = chan[8]("ram_wr_resp"); - - let (ram_rd_req_fh_s, ram_rd_req_fh_r) = chan("ram_rd_req_fh"); - let (ram_rd_req_bh_s, ram_rd_req_bh_r) = chan("ram_rd_req_bh"); - let (ram_rd_req_raw_s, ram_rd_req_raw_r) = chan("ram_rd_req_raw"); - let (ram_rd_resp_fh_s, ram_rd_resp_fh_r) = chan("ram_rd_resp_fh"); - let (ram_rd_resp_bh_s, ram_rd_resp_bh_r) = chan("ram_rd_resp_bh"); - let (ram_rd_resp_raw_s, ram_rd_resp_raw_r) = chan("ram_rd_resp_raw"); - - let (ram_wr_req_fh_s, ram_wr_req_fh_r) = chan("ram_wr_req_fh"); - let (ram_wr_req_bh_s, ram_wr_req_bh_r) = chan("ram_wr_req_bh"); - let (ram_wr_req_raw_s, ram_wr_req_raw_r) = chan("ram_wr_req_raw"); - let (ram_wr_resp_fh_s, ram_wr_resp_fh_r) = chan("ram_wr_resp_fh"); - let (ram_wr_resp_bh_s, ram_wr_resp_bh_r) = chan("ram_wr_resp_bh"); - let (ram_wr_resp_raw_s, ram_wr_resp_raw_r) = chan("ram_wr_resp_raw"); + let (hb_ram_rd_req_s, hb_ram_rd_req_r) = chan[8]("hb_ram_rd_req"); + let (hb_ram_rd_resp_s, hb_ram_rd_resp_r) = chan[8]("hb_ram_rd_resp"); + let (hb_ram_wr_req_s, hb_ram_wr_req_r) = chan[8]("hb_ram_wr_req"); + let (hb_ram_wr_resp_s, hb_ram_wr_resp_r) = chan[8]("hb_ram_wr_resp"); let (notify_s, notify_r) = chan<()>("notify"); let (reset_s, reset_r) = chan<()>("reset"); + // Huffman weights memory + let (huffman_lit_weights_mem_rd_req_s, _huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (_huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, _huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (_huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + + // Huffman prescan memory + let (huffman_lit_prescan_mem_rd_req_s, _huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); + let (_huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); + let (huffman_lit_prescan_mem_wr_req_s, _huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); + let (_huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + + // AXI channels for various blocks + let (comp_axi_ar_s, comp_axi_ar_r) = chan[AXI_CHAN_N]("comp_axi_ar"); + let (comp_axi_r_s, comp_axi_r_r) = chan[AXI_CHAN_N]("comp_axi_r"); + + let (comp_ram_rd_req_s, comp_ram_rd_req_r) = chan[AXI_CHAN_N]("comp_ram_rd_req"); + let (comp_ram_rd_resp_s, comp_ram_rd_resp_r) = chan[AXI_CHAN_N]("comp_ram_rd_resp"); + let (comp_ram_wr_req_s, comp_ram_wr_req_r) = chan[AXI_CHAN_N]("comp_ram_wr_req"); + let (comp_ram_wr_resp_s, comp_ram_wr_resp_r) = chan[AXI_CHAN_N]("comp_ram_wr_resp"); + + unroll_for! (i, ()): (u32, ()) in range(u32:0, AXI_CHAN_N) { + spawn ram::RamModel< + TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >(comp_ram_rd_req_r[i], comp_ram_rd_resp_s[i], comp_ram_wr_req_r[i], comp_ram_wr_resp_s[i]); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, + TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W + >(comp_axi_ar_r[i], comp_axi_r_s[i], comp_ram_rd_req_s[i], comp_ram_rd_resp_r[i]); + }(()); + + // Literals buffer RAMs + let (litbuf_rd_req_s, litbuf_rd_req_r) = chan[u32:8]("litbuf_rd_req"); + let (litbuf_rd_resp_s, litbuf_rd_resp_r) = chan[u32:8]("litbuf_rd_resp"); + let (litbuf_wr_req_s, litbuf_wr_req_r) = chan[u32:8]("litbuf_wr_req"); + let (litbuf_wr_resp_s, litbuf_wr_resp_r) = chan[u32:8]("litbuf_wr_resp"); + unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:8) { + spawn ram::RamModel< + LITERALS_BUFFER_RAM_DATA_W, LITERALS_BUFFER_RAM_SIZE, LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + litbuf_rd_req_r[i], litbuf_rd_resp_s[i], litbuf_wr_req_r[i], litbuf_wr_resp_s[i] + ); + }(()); + + // RAMs for FSE decoder + // DPD RAM + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + spawn ram::RamModel< + TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_SIZE, TEST_DPD_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s, + ); + + // TMP RAM + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + spawn ram::RamModel< + TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, + ); + + // FSE RAMs + let (fse_rd_req_s, fse_rd_req_r) = chan[u32:6]("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan[u32:6]("fse_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan[u32:6]("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan[u32:6]("fse_wr_resp"); + unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:6) { + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_SIZE, TEST_FSE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + fse_rd_req_r[i], fse_rd_resp_s[i], fse_wr_req_r[i], fse_wr_resp_s[i] + ); + }(()); + + // Default LL + + let (ll_sel_test_s, ll_sel_test_r) = chan("ll_sel_test"); + + let (ll_def_test_rd_req_s, ll_def_test_rd_req_r) = chan("ll_def_test_rd_req"); + let (ll_def_test_rd_resp_s, ll_def_test_rd_resp_r) = chan("ll_def_test_rd_resp"); + let (ll_def_test_wr_req_s, ll_def_test_wr_req_r) = chan("ll_def_test_wr_req"); + let (ll_def_test_wr_resp_s, ll_def_test_wr_resp_r) = chan("ll_def_test_wr_resp"); + + let (ll_def_fse_rd_req_s, ll_def_fse_rd_req_r) = chan("ll_def_fse_rd_req"); + let (ll_def_fse_rd_resp_s, ll_def_fse_rd_resp_r) = chan("ll_def_fse_rd_resp"); + let (ll_def_fse_wr_req_s, ll_def_fse_wr_req_r) = chan("ll_def_fse_wr_req"); + let (ll_def_fse_wr_resp_s, ll_def_fse_wr_resp_r) = chan("ll_def_fse_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + ll_sel_test_r, + ll_def_test_rd_req_r, ll_def_test_rd_resp_s, ll_def_test_wr_req_r, ll_def_test_wr_resp_s, + ll_def_fse_rd_req_r, ll_def_fse_rd_resp_s, ll_def_fse_wr_req_r, ll_def_fse_wr_resp_s, + fse_rd_req_s[0], fse_rd_resp_r[0], fse_wr_req_s[0], fse_wr_resp_r[0], + ); + + // Default ML + + let (ml_sel_test_s, ml_sel_test_r) = chan("ml_sel_test"); + + let (ml_def_test_rd_req_s, ml_def_test_rd_req_r) = chan("ml_def_test_rd_req"); + let (ml_def_test_rd_resp_s, ml_def_test_rd_resp_r) = chan("ml_def_test_rd_resp"); + let (ml_def_test_wr_req_s, ml_def_test_wr_req_r) = chan("ml_def_test_wr_req"); + let (ml_def_test_wr_resp_s, ml_def_test_wr_resp_r) = chan("ml_def_test_wr_resp"); + + let (ml_def_fse_rd_req_s, ml_def_fse_rd_req_r) = chan("ml_def_fse_rd_req"); + let (ml_def_fse_rd_resp_s, ml_def_fse_rd_resp_r) = chan("ml_def_fse_rd_resp"); + let (ml_def_fse_wr_req_s, ml_def_fse_wr_req_r) = chan("ml_def_fse_wr_req"); + let (ml_def_fse_wr_resp_s, ml_def_fse_wr_resp_r) = chan("ml_def_fse_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + ml_sel_test_r, + ml_def_test_rd_req_r, ml_def_test_rd_resp_s, ml_def_test_wr_req_r, ml_def_test_wr_resp_s, + ml_def_fse_rd_req_r, ml_def_fse_rd_resp_s, ml_def_fse_wr_req_r, ml_def_fse_wr_resp_s, + fse_rd_req_s[2], fse_rd_resp_r[2], fse_wr_req_s[2], fse_wr_resp_r[2], + ); + + // Default OF + + let (of_sel_test_s, of_sel_test_r) = chan("of_sel_test"); + + let (of_def_test_rd_req_s, of_def_test_rd_req_r) = chan("of_def_test_rd_req"); + let (of_def_test_rd_resp_s, of_def_test_rd_resp_r) = chan("of_def_test_rd_resp"); + let (of_def_test_wr_req_s, of_def_test_wr_req_r) = chan("of_def_test_wr_req"); + let (of_def_test_wr_resp_s, of_def_test_wr_resp_r) = chan("of_def_test_wr_resp"); + + let (of_def_fse_rd_req_s, of_def_fse_rd_req_r) = chan("of_def_fse_rd_req"); + let (of_def_fse_rd_resp_s, of_def_fse_rd_resp_r) = chan("of_def_fse_rd_resp"); + let (of_def_fse_wr_req_s, of_def_fse_wr_req_r) = chan("of_def_fse_wr_req"); + let (of_def_fse_wr_resp_s, of_def_fse_wr_resp_r) = chan("of_def_fse_wr_resp"); + + spawn ram_mux::RamMux< + TEST_FSE_RAM_ADDR_W, + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_NUM_PARTITIONS, + >( + of_sel_test_r, + of_def_test_rd_req_r, of_def_test_rd_resp_s, of_def_test_wr_req_r, of_def_test_wr_resp_s, + of_def_fse_rd_req_r, of_def_fse_rd_resp_s, of_def_fse_wr_req_r, of_def_fse_wr_resp_s, + fse_rd_req_s[4], fse_rd_resp_r[4], fse_wr_req_s[4], fse_wr_resp_r[4], + ); + spawn zstd_dec::ZstdDecoder< TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, TEST_REGS_N, TEST_WINDOW_LOG_MAX, TEST_HB_ADDR_W, TEST_HB_DATA_W, TEST_HB_NUM_PARTITIONS, TEST_HB_SIZE_KB, + TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, + HISTORY_BUFFER_SIZE_KB, AXI_CHAN_N, >( csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, fh_axi_ar_s, fh_axi_r_r, bh_axi_ar_s, bh_axi_r_r, raw_axi_ar_s, raw_axi_r_r, + comp_axi_ar_s, comp_axi_r_r, + dpd_rd_req_s, dpd_rd_resp_r, + dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, + tmp_wr_req_s, tmp_wr_resp_r, + + // Channels for accessing FSE tables with muxed default FSE tables + [ll_def_fse_rd_req_s, fse_rd_req_s[1], ml_def_fse_rd_req_s, fse_rd_req_s[3], of_def_fse_rd_req_s, fse_rd_req_s[5]], + [ll_def_fse_rd_resp_r, fse_rd_resp_r[1], ml_def_fse_rd_resp_r, fse_rd_resp_r[3], of_def_fse_rd_resp_r, fse_rd_resp_r[5]], + [ll_def_fse_wr_req_s, fse_wr_req_s[1], ml_def_fse_wr_req_s, fse_wr_req_s[3], of_def_fse_wr_req_s, fse_wr_req_s[5]], + [ll_def_fse_wr_resp_r, fse_wr_resp_r[1], ml_def_fse_wr_resp_r, fse_wr_resp_r[3], of_def_fse_wr_resp_r, fse_wr_resp_r[5]], + + litbuf_rd_req_s, litbuf_rd_resp_r, + litbuf_wr_req_s, litbuf_wr_resp_r, + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, + huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, output_axi_aw_s, output_axi_w_s, output_axi_b_r, - ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], - ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], - ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], - ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], - ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], - ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], - ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], - ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7], - notify_s, reset_s, - ); - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); + // RAMs for SequenceExecutor + hb_ram_rd_req_s[0], hb_ram_rd_req_s[1], hb_ram_rd_req_s[2], hb_ram_rd_req_s[3], + hb_ram_rd_req_s[4], hb_ram_rd_req_s[5], hb_ram_rd_req_s[6], hb_ram_rd_req_s[7], + hb_ram_rd_resp_r[0], hb_ram_rd_resp_r[1], hb_ram_rd_resp_r[2], hb_ram_rd_resp_r[3], + hb_ram_rd_resp_r[4], hb_ram_rd_resp_r[5], hb_ram_rd_resp_r[6], hb_ram_rd_resp_r[7], + hb_ram_wr_req_s[0], hb_ram_wr_req_s[1], hb_ram_wr_req_s[2], hb_ram_wr_req_s[3], + hb_ram_wr_req_s[4], hb_ram_wr_req_s[5], hb_ram_wr_req_s[6], hb_ram_wr_req_s[7], + hb_ram_wr_resp_r[0], hb_ram_wr_resp_r[1], hb_ram_wr_resp_r[2], hb_ram_wr_resp_r[3], + hb_ram_wr_resp_r[4], hb_ram_wr_resp_r[5], hb_ram_wr_resp_r[6], hb_ram_wr_resp_r[7], - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); - - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); - - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); - - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); + notify_s, reset_s, + ); - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); + unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:8) { + spawn ram::RamModel< + TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, + TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, + TEST_HB_RAM_ASSERT_VALID_READ + >(hb_ram_rd_req_r[i], hb_ram_rd_resp_s[i], hb_ram_wr_req_r[i], hb_ram_wr_resp_s[i]); + }(()); - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); - - spawn ram::RamModel< - TEST_HB_DATA_W, TEST_HB_RAM_SIZE, TEST_HB_RAM_WORD_PARTITION_SIZE, - TEST_HB_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_HB_RAM_INITIALIZED, - TEST_HB_RAM_ASSERT_VALID_READ - > (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); spawn ram::RamModel< TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, - > (ram_rd_req_fh_r, ram_rd_resp_fh_s, ram_wr_req_fh_r, ram_wr_resp_fh_s); + > (fh_ram_rd_req_r, fh_ram_rd_resp_s, fh_ram_wr_req_r, fh_ram_wr_resp_s); spawn ram::RamModel< TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, - > (ram_rd_req_bh_r, ram_rd_resp_bh_s, ram_wr_req_bh_r, ram_wr_resp_bh_s); + > (bh_ram_rd_req_r, bh_ram_rd_resp_s, bh_ram_wr_req_r, bh_ram_wr_resp_s); spawn ram::RamModel< TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, - > (ram_rd_req_raw_r, ram_rd_resp_raw_s, ram_wr_req_raw_r, ram_wr_resp_raw_s); + > (raw_ram_rd_req_r, raw_ram_rd_resp_s, raw_ram_wr_req_r, raw_ram_wr_resp_s); spawn axi_ram::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, - >(fh_axi_ar_r, fh_axi_r_s, ram_rd_req_fh_s, ram_rd_resp_fh_r); + >(fh_axi_ar_r, fh_axi_r_s, fh_ram_rd_req_s, fh_ram_rd_resp_r); spawn axi_ram::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, - >(bh_axi_ar_r, bh_axi_r_s, ram_rd_req_bh_s, ram_rd_resp_bh_r); + >(bh_axi_ar_r, bh_axi_r_s, bh_ram_rd_req_s, bh_ram_rd_resp_r); spawn axi_ram::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, - >(raw_axi_ar_r, raw_axi_r_s, ram_rd_req_raw_s, ram_rd_resp_raw_r); + >(raw_axi_ar_r, raw_axi_r_s, raw_ram_rd_req_s, raw_ram_rd_resp_r); ( terminator, csr_axi_aw_s, csr_axi_w_s, csr_axi_b_r, csr_axi_ar_s, csr_axi_r_r, - fh_axi_ar_r, fh_axi_r_s, - bh_axi_ar_r, bh_axi_r_s, - raw_axi_ar_r, raw_axi_r_s, + fh_axi_ar_r, fh_axi_r_s, fh_ram_wr_req_s, fh_ram_wr_resp_r, + bh_axi_ar_r, bh_axi_r_s, bh_ram_wr_req_s, bh_ram_wr_resp_r, + raw_axi_ar_r, raw_axi_r_s, raw_ram_wr_req_s, raw_ram_wr_resp_r, + comp_ram_wr_req_s, comp_ram_wr_resp_r, output_axi_aw_r, output_axi_w_r, output_axi_b_s, - ram_rd_req_r, ram_rd_resp_s, ram_wr_req_r, ram_wr_resp_s, - ram_wr_req_fh_s, ram_wr_req_bh_s, ram_wr_req_raw_s, - ram_wr_resp_fh_r, ram_wr_resp_bh_r, ram_wr_resp_raw_r, + hb_ram_rd_req_r, hb_ram_rd_resp_s, hb_ram_wr_req_r, hb_ram_wr_resp_s, + ll_sel_test_s, ll_def_test_rd_req_s, ll_def_test_rd_resp_r, ll_def_test_wr_req_s, ll_def_test_wr_resp_r, + ml_sel_test_s, ml_def_test_rd_req_s, ml_def_test_rd_resp_r, ml_def_test_wr_req_s, ml_def_test_wr_resp_r, + of_sel_test_s, of_def_test_rd_req_s, of_def_test_rd_resp_r, of_def_test_wr_req_s, of_def_test_wr_resp_r, notify_r, reset_r, ) } next (state: ()) { trace_fmt!("Test start"); - let frames_count = array_size(zstd_frame_testcases::FRAMES); + let frames_count = array_size(comp_frame::FRAMES); let tok = join(); + + // FILL THE LL DEFAULT RAM + trace_fmt!("Filling LL default FSE table"); + let tok = send(tok, ll_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_LL_TABLE)) { + let req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_W], + data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_LL_TABLE[i]), + mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, ll_def_test_wr_req_s, req); + let (tok, _) = recv(tok, ll_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, ll_sel_test_s, u1:1); + + // FILL THE OF DEFAULT RAM + trace_fmt!("Filling OF default FSE table"); + let tok = send(tok, of_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_OF_TABLE)) { + let req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_W], + data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_OF_TABLE[i]), + mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, of_def_test_wr_req_s, req); + let (tok, _) = recv(tok, of_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, of_sel_test_s, u1:1); + + // FILL THE ML DEFAULT RAM + trace_fmt!("Filling ML default FSE table"); + let tok = send(tok, ml_sel_test_s, u1:0); + let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_ML_TABLE)) { + let req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_W], + data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_ML_TABLE[i]), + mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, ml_def_test_wr_req_s, req); + let (tok, _) = recv(tok, ml_def_test_wr_resp_r); + tok + }(tok); + let tok = send(tok, ml_sel_test_s, u1:1); + let tok = unroll_for! (test_i, tok): (u32, token) in range(u32:0, frames_count) { trace_fmt!("Loading testcase {:x}", test_i + u32:1); - let frame = zstd_frame_testcases::FRAMES[test_i]; + let frame = comp_frame::FRAMES[test_i]; let tok = for (i, tok): (u32, token) in range(u32:0, frame.array_length) { let req = RamWrReq { addr: i as uN[TEST_RAM_ADDR_W], data: frame.data[i] as uN[TEST_RAM_DATA_W], mask: uN[TEST_RAM_NUM_PARTITIONS]:0xFF }; - let tok = send(tok, ram_wr_req_fh_s, req); - let tok = send(tok, ram_wr_req_bh_s, req); - let tok = send(tok, ram_wr_req_raw_s, req); - tok + let tok = send(tok, fh_ram_wr_req_s, req); + let tok = send(tok, bh_ram_wr_req_s, req); + let tok = send(tok, raw_ram_wr_req_s, req); + for (i, tok): (u32, token) in range(u32:0, AXI_CHAN_N) { + send(tok, comp_ram_wr_req_s[i], req) + }(tok) }(tok); trace_fmt!("Running decoder on testcase {:x}", test_i + u32:1); @@ -358,7 +675,7 @@ proc ZstdDecoderTest { }); let (tok, _) = recv(tok, csr_axi_b_r); - let decomp_frame = zstd_frame_testcases::DECOMPRESSED_FRAMES[test_i]; + let decomp_frame = comp_frame::DECOMPRESSED_FRAMES[test_i]; // Test ZstdDecoder memory output interface // Mock the output memory buffer as a DSLX array // It is required to handle AXI write transactions and to write the incoming data to @@ -377,7 +694,7 @@ proc ZstdDecoderTest { // The maximal number if beats in AXI burst transaction let MAX_AXI_TRANSFERS = u32:256; // Actual size of decompressed payload for current test - let DECOMPRESSED_BYTES = zstd_frame_testcases::DECOMPRESSED_FRAMES[test_i].length; + let DECOMPRESSED_BYTES = comp_frame::DECOMPRESSED_FRAMES[test_i].length; trace_fmt!("ZstdDecTest: Start receiving output"); let (tok, final_output_memory, final_output_memory_id, final_transfered_bytes) = for (axi_transaction, (tok, output_memory, output_memory_id, transfered_bytes)): From a75f9e6c11d95b63cb0ec0917fc030222d6bae64 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 14 Jan 2025 15:33:07 +0100 Subject: [PATCH 48/85] modules/zstd: Add example frame for DSLX tests Signed-off-by: Robert Winkler --- xls/modules/zstd/comp_frame.x | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 xls/modules/zstd/comp_frame.x diff --git a/xls/modules/zstd/comp_frame.x b/xls/modules/zstd/comp_frame.x new file mode 100644 index 0000000000..5e1a97dbd4 --- /dev/null +++ b/xls/modules/zstd/comp_frame.x @@ -0,0 +1,21 @@ +pub struct DataArray{ + data: uN[BITS_PER_WORD][LENGTH], + length: u32, + array_length: u32 +} +pub const FRAMES:DataArray< + u32:64, + u32:5 +>[1] = [DataArray<64, 5>{ + length: u32:33, + array_length: u32:5, + data: uN[64][5]:[uN[64]:0x001a3384fd2fb528, uN[64]:0xc1d3500000850000, uN[64]:0xdcf0529b98db8a06, uN[64]:0x308fa3120a430001, uN[64]:0x50] +}]; +pub const DECOMPRESSED_FRAMES:DataArray< + u32:64, + u32:4 +>[1] = [DataArray<64, 4>{ + length: u32:26, + array_length: u32:4, + data: uN[64][4]:[uN[64]:0x529b98db8a06c1d3, uN[64]:0x529b98db8a06dcf0, uN[64]:0x529b98db8a06dcf0, uN[64]:0xdcf0] +}]; From 362a00e590a8dbc655753992ff98a0b1e75ded7c Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 14 Jan 2025 15:34:16 +0100 Subject: [PATCH 49/85] modules/zstd: Adjust SequenceExecutor Signed-off-by: Robert Winkler --- xls/modules/zstd/sequence_executor.x | 371 ++++++++++++++------------- 1 file changed, 188 insertions(+), 183 deletions(-) diff --git a/xls/modules/zstd/sequence_executor.x b/xls/modules/zstd/sequence_executor.x index 80a7a6e70a..cab106b244 100644 --- a/xls/modules/zstd/sequence_executor.x +++ b/xls/modules/zstd/sequence_executor.x @@ -196,7 +196,7 @@ pub proc SequenceExecutor> out; ram_comp_output_r: chan> in; ram_resp_input_s: chan out; - ram_resp_output_r: chan in; + looped_channel_r: chan in; rd_req_m0_s: chan> out; rd_req_m1_s: chan> out; rd_req_m2_s: chan> out; @@ -217,8 +217,8 @@ pub proc SequenceExecutor in, output_mem_wr_data_in_s: chan out, - ram_resp_output_r: chan in, - ram_resp_output_s: chan out, + looped_channel_r: chan in, + looped_channel_s: chan out, rd_req_m0_s: chan> out, rd_req_m1_s: chan> out, rd_req_m2_s: chan> out, @@ -262,14 +262,14 @@ pub proc SequenceExecutor()); // ... or our own sequences from the looped channel - let do_recv_ram = - (state.status == Status::SEQUENCE_READ || state.status == Status::SEQUENCE_WRITE); - let (tok1_1, ram_packet, ram_packet_valid) = - recv_if_non_blocking(tok0, ram_resp_output_r, do_recv_ram, zero!()); + let do_recv_ram = ( + state.status == Status::SEQUENCE_READ || + state.status == Status::SEQUENCE_WRITE + ); + + let (tok1_1, ram_packet, ram_packet_valid) = recv_if_non_blocking(tok0, looped_channel_r, do_recv_ram, zero!()); // Read RAM write completion, used for monitoring the real state // of the RAM and eventually changing the state to IDLE. @@ -678,136 +680,136 @@ const LITERAL_TEST_MEMORY_CONTENT:(TestRamAddr, RamData)[3][RAM_NUM] = [ ], ]; -#[test_proc] -proc SequenceExecutorLiteralsTest { - type MemWriterDataPacket = mem_writer::MemWriterDataPacket; - terminator: chan out; - - input_s: chan out; - output_mem_wr_data_in_r: chan in; - - print_start_s: chan<()> out; - print_finish_r: chan<()> in; - - ram_rd_req_s: chan[RAM_NUM] out; - ram_rd_resp_r: chan[RAM_NUM] in; - ram_wr_req_s: chan[RAM_NUM] out; - ram_wr_resp_r: chan[RAM_NUM] in; - - config(terminator: chan out) { - let (input_s, input_r) = chan("input"); - let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); - - let (looped_channel_s, looped_channel_r) = chan("looped_channels"); - - let (print_start_s, print_start_r) = chan<()>("print_start"); - let (print_finish_s, print_finish_r) = chan<()>("print_finish"); - - let (ram_rd_req_s, ram_rd_req_r) = chan[RAM_NUM]("ram_rd_req"); - let (ram_rd_resp_s, ram_rd_resp_r) = chan[RAM_NUM]("ram_rd_resp"); - let (ram_wr_req_s, ram_wr_req_r) = chan[RAM_NUM]("ram_wr_req"); - let (ram_wr_resp_s, ram_wr_resp_r) = chan[RAM_NUM]("ram_wr_resp"); - - let INIT_HB_PTR_ADDR = u32:127; - spawn SequenceExecutor< - TEST_HISTORY_BUFFER_SIZE_KB, - TEST_DATA_W, TEST_ADDR_W, - TEST_RAM_SIZE, - TEST_RAM_ADDR_WIDTH, - INIT_HB_PTR_ADDR, - > ( - input_r, output_mem_wr_data_in_s, - looped_channel_r, looped_channel_s, - ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], - ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], - ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], - ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], - ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], - ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], - ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], - ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7] - ); - - spawn ram_printer::RamPrinter< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_NUM_PARTITIONS, - TEST_RAM_ADDR_WIDTH, RAM_NUM> - (print_start_r, print_finish_s, ram_rd_req_s, ram_rd_resp_r); - - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); - spawn ram::RamModel< - RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, - TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> - (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); - - ( - terminator, - input_s, output_mem_wr_data_in_r, - print_start_s, print_finish_r, - ram_rd_req_s, ram_rd_resp_r, - ram_wr_req_s, ram_wr_resp_r - ) - } - - init { } - - next(state: ()) { - let tok = join(); - for (i, ()): (u32, ()) in u32:0..array_size(LITERAL_TEST_INPUT_DATA) { - let tok = send(tok, input_s, LITERAL_TEST_INPUT_DATA[i]); - // Don't receive when there's an empty literals packet which is not last - if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || - LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || - LITERAL_TEST_INPUT_DATA[i].last) { - let expected_mem_writer_data = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); - let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(expected_mem_writer_data, recv_mem_writer_data); - } else {} - }(()); - - for (i, ()): (u32, ()) in u32:0..RAM_NUM { - for (j, ()): (u32, ()) in u32:0..array_size(LITERAL_TEST_MEMORY_CONTENT[0]) { - let addr = LITERAL_TEST_MEMORY_CONTENT[i][j].0; - let tok = send(tok, ram_rd_req_s[i], TestReadReq { addr, mask: RAM_REQ_MASK_ALL }); - let (tok, resp) = recv(tok, ram_rd_resp_r[i]); - let expected = LITERAL_TEST_MEMORY_CONTENT[i][j].1; - assert_eq(expected, resp.data); - }(()); - }(()); - - // Print RAM content - let tok = send(tok, print_start_s, ()); - let (tok, _) = recv(tok, print_finish_r); - - send(tok, terminator, true); - } -} +// #[test_proc] +// proc SequenceExecutorLiteralsTest { +// type MemWriterDataPacket = mem_writer::MemWriterDataPacket; +// terminator: chan out; + +// input_s: chan out; +// output_mem_wr_data_in_r: chan in; + +// print_start_s: chan<()> out; +// print_finish_r: chan<()> in; + +// ram_rd_req_s: chan[RAM_NUM] out; +// ram_rd_resp_r: chan[RAM_NUM] in; +// ram_wr_req_s: chan[RAM_NUM] out; +// ram_wr_resp_r: chan[RAM_NUM] in; + +// config(terminator: chan out) { +// let (input_s, input_r) = chan("input"); +// let (output_mem_wr_data_in_s, output_mem_wr_data_in_r) = chan("output_mem_wr_data_in"); + +// let (looped_channel_s, looped_channel_r) = chan("looped_channels"); + +// let (print_start_s, print_start_r) = chan<()>("print_start"); +// let (print_finish_s, print_finish_r) = chan<()>("print_finish"); + +// let (ram_rd_req_s, ram_rd_req_r) = chan[RAM_NUM]("ram_rd_req"); +// let (ram_rd_resp_s, ram_rd_resp_r) = chan[RAM_NUM]("ram_rd_resp"); +// let (ram_wr_req_s, ram_wr_req_r) = chan[RAM_NUM]("ram_wr_req"); +// let (ram_wr_resp_s, ram_wr_resp_r) = chan[RAM_NUM]("ram_wr_resp"); + +// let INIT_HB_PTR_ADDR = u32:127; +// spawn SequenceExecutor< +// TEST_HISTORY_BUFFER_SIZE_KB, +// TEST_DATA_W, TEST_ADDR_W, +// TEST_RAM_SIZE, +// TEST_RAM_ADDR_WIDTH, +// INIT_HB_PTR_ADDR, +// > ( +// input_r, output_mem_wr_data_in_s, +// looped_channel_r, looped_channel_s, +// ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], +// ram_rd_req_s[4], ram_rd_req_s[5], ram_rd_req_s[6], ram_rd_req_s[7], +// ram_rd_resp_r[0], ram_rd_resp_r[1], ram_rd_resp_r[2], ram_rd_resp_r[3], +// ram_rd_resp_r[4], ram_rd_resp_r[5], ram_rd_resp_r[6], ram_rd_resp_r[7], +// ram_wr_req_s[0], ram_wr_req_s[1], ram_wr_req_s[2], ram_wr_req_s[3], +// ram_wr_req_s[4], ram_wr_req_s[5], ram_wr_req_s[6], ram_wr_req_s[7], +// ram_wr_resp_r[0], ram_wr_resp_r[1], ram_wr_resp_r[2], ram_wr_resp_r[3], +// ram_wr_resp_r[4], ram_wr_resp_r[5], ram_wr_resp_r[6], ram_wr_resp_r[7] +// ); + +// spawn ram_printer::RamPrinter< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_NUM_PARTITIONS, +// TEST_RAM_ADDR_WIDTH, RAM_NUM> +// (print_start_r, print_finish_s, ram_rd_req_s, ram_rd_resp_r); + +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[0], ram_rd_resp_s[0], ram_wr_req_r[0], ram_wr_resp_s[0]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[1], ram_rd_resp_s[1], ram_wr_req_r[1], ram_wr_resp_s[1]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[2], ram_rd_resp_s[2], ram_wr_req_r[2], ram_wr_resp_s[2]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[3], ram_rd_resp_s[3], ram_wr_req_r[3], ram_wr_resp_s[3]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[4], ram_rd_resp_s[4], ram_wr_req_r[4], ram_wr_resp_s[4]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[5], ram_rd_resp_s[5], ram_wr_req_r[5], ram_wr_resp_s[5]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[6], ram_rd_resp_s[6], ram_wr_req_r[6], ram_wr_resp_s[6]); +// spawn ram::RamModel< +// RAM_DATA_WIDTH, TEST_RAM_SIZE, RAM_WORD_PARTITION_SIZE, +// TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED> +// (ram_rd_req_r[7], ram_rd_resp_s[7], ram_wr_req_r[7], ram_wr_resp_s[7]); + +// ( +// terminator, +// input_s, output_mem_wr_data_in_r, +// print_start_s, print_finish_r, +// ram_rd_req_s, ram_rd_resp_r, +// ram_wr_req_s, ram_wr_resp_r +// ) +// } + +// init { } + +// next(state: ()) { +// let tok = join(); +// for (i, ()): (u32, ()) in range(u32:0, array_size(LITERAL_TEST_INPUT_DATA)) { +// let tok = send(tok, input_s, LITERAL_TEST_INPUT_DATA[i]); +// // Don't receive when there's an empty literals packet which is not last +// if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || +// LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || +// LITERAL_TEST_INPUT_DATA[i].last) { +// let expected_mem_writer_data = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); +// let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); +// assert_eq(expected_mem_writer_data, recv_mem_writer_data); +// } else {} +// }(()); + +// for (i, ()): (u32, ()) in range(u32:0, RAM_NUM) { +// for (j, ()): (u32, ()) in range(u32:0, array_size(LITERAL_TEST_MEMORY_CONTENT[0])) { +// let addr = LITERAL_TEST_MEMORY_CONTENT[i][j].0; +// let tok = send(tok, ram_rd_req_s[i], TestReadReq { addr, mask: RAM_REQ_MASK_ALL }); +// let (tok, resp) = recv(tok, ram_rd_resp_r[i]); +// let expected = LITERAL_TEST_MEMORY_CONTENT[i][j].1; +// assert_eq(expected, resp.data); +// }(()); +// }(()); + +// // Print RAM content +// let tok = send(tok, print_start_s, ()); +// let (tok, _) = recv(tok, print_finish_r); + +// send(tok, terminator, true); +// } +// } const SEQUENCE_TEST_INPUT_SEQUENCES = SequenceExecutorPacket[11]: [ SequenceExecutorPacket { @@ -1037,67 +1039,70 @@ proc SequenceExecutorSequenceTest { next(state: ()) { let tok = join(); - for (i, ()): (u32, ()) in u32:0..array_size(LITERAL_TEST_INPUT_DATA) { - let tok = send(tok, input_s, LITERAL_TEST_INPUT_DATA[i]); - // Don't receive when there's an empty literal packet which is not last - if (LITERAL_TEST_INPUT_DATA[i].msg_type != SequenceExecutorMessageType::LITERAL || - LITERAL_TEST_INPUT_DATA[i].length != CopyOrMatchLength:0 || - LITERAL_TEST_INPUT_DATA[i].last) { - let expected_mem_writer_data = decode_literal_packet(LITERAL_TEST_INPUT_DATA[i]); - let (tok, recv_mem_writer_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(expected_mem_writer_data, recv_mem_writer_data); - } else {} - }(()); // Print RAM content - let tok = send(tok, print_start_s, ()); - let (tok, _) = recv(tok, print_finish_r); - - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[0]); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[0], recv_data); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[1], recv_data); + // let tok = send(tok, print_start_s, ()); + // let (tok, _) = recv(tok, print_finish_r); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[1]); + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: CopyOrMatchLength:1, + content: CopyOrMatchContent:0x31, + last: false + }); let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[2], recv_data); + assert_eq(recv_data, TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x31, + length: uN[TEST_ADDR_W]:1, + last: false + }); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[2]); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[3], recv_data); + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[3]); + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: CopyOrMatchLength:3, + content: CopyOrMatchContent:4, + last: false + }); let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[4], recv_data); + assert_eq(recv_data, TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x31, + length: uN[TEST_ADDR_W]:1, + last: false + }); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[4]); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[5], recv_data); + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[5]); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[6], recv_data); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[6]); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[7]); let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[7], recv_data); + assert_eq(recv_data, TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x3131, + length: uN[TEST_ADDR_W]:2, + last: false + }); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[8]); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[9]); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[8], recv_data); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[9], recv_data); + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); - let tok = send(tok, input_s, SEQUENCE_TEST_INPUT_SEQUENCES[10]); + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: CopyOrMatchLength:3, + content: CopyOrMatchContent:7, + last: false + }); let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(SEQUENCE_TEST_EXPECTED_SEQUENCE_RESULTS[10], recv_data); + assert_eq(recv_data, TestMemWriterDataPacket { + data: uN[TEST_DATA_W]:0x313131, + length: uN[TEST_ADDR_W]:3, + last: false + }); - // Print RAM content let tok = send(tok, print_start_s, ()); let (tok, _) = recv(tok, print_finish_r); + send(tok, terminator, true); } } From 90f40de164db47e2733d4660341f7d1125eae1d2 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 14 Jan 2025 15:35:27 +0100 Subject: [PATCH 50/85] modules/zstd: Adjust AxiRam Signed-off-by: Robert Winkler --- xls/modules/zstd/memory/axi_ram.x | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/xls/modules/zstd/memory/axi_ram.x b/xls/modules/zstd/memory/axi_ram.x index 688fe2c171..4886028a9c 100644 --- a/xls/modules/zstd/memory/axi_ram.x +++ b/xls/modules/zstd/memory/axi_ram.x @@ -105,9 +105,9 @@ proc AxiRamReaderRequester< // validate bundle let ar_bundle_ok = ar_bundle_valid && ((ar_bundle.size as u32 + u32:3) <= AXI_DATA_W_LOG2); - if ar_bundle_valid { - trace_fmt!("{:#x}", ar_bundle); - } else {}; + //if ar_bundle_valid { + // trace_fmt!("{:#x}", ar_bundle); + //} else {}; let tok = send_if(tok, sync_s, ar_bundle_valid && !ar_bundle_ok, Sync { id: ar_bundle.id, resp: AxiReadResp::SLVERR, @@ -680,9 +680,9 @@ proc AxiRamReaderTest { tok }(tok); - let tok = for ((i, axi_ar_bundle), tok): ((u32, TestAxiAr), token) in enumerate(TEST_AXI_AR_BUNDLES) { + let tok = for ((_i, axi_ar_bundle), tok): ((u32, TestAxiAr), token) in enumerate(TEST_AXI_AR_BUNDLES) { let tok = send(tok, axi_ar_s, axi_ar_bundle); - trace_fmt!("Sent bundle #{} {:#x}", i + u32:1, axi_ar_bundle); + // trace_fmt!("Sent bundle #{} {:#x}", i + u32:1, axi_ar_bundle); let size_valid = (u32:1 << (axi_ar_bundle.size as u32 + u32:3)) <= TEST_AXI_DATA_W; From a9916cee9f05c99a2ebf570eaa8329d2273acd0e Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 14 Jan 2025 15:16:31 +0100 Subject: [PATCH 51/85] modules/zstd: Add RamMux Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 16 +++ xls/modules/zstd/ram_mux.x | 238 +++++++++++++++++++++++++++++++++++++ 2 files changed, 254 insertions(+) create mode 100644 xls/modules/zstd/ram_mux.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 3cc6c22d56..9ee783025c 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1959,6 +1959,22 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "ram_mux_dslx", + srcs = [ + "ram_mux.x" + ], + deps = [ + "//xls/examples:ram_dslx", + ], +) + +xls_dslx_test( + name = "ram_mux_dslx_test", + library = ":ram_mux_dslx", + tags = ["manual"], +) + xls_dslx_library( name = "sequence_dec_dslx", srcs = [ diff --git a/xls/modules/zstd/ram_mux.x b/xls/modules/zstd/ram_mux.x new file mode 100644 index 0000000000..25d785a69f --- /dev/null +++ b/xls/modules/zstd/ram_mux.x @@ -0,0 +1,238 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains utilities related to ZSTD Block Header parsing. +// More information about the ZSTD Block Header can be found in: +// https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.2 + + +import std; +import xls.examples.ram; + +struct RamMuxState { sel: u1, cnt0: u32, cnt1: u32 } + +pub proc RamMux< + ADDR_WIDTH: u32, DATA_WIDTH: u32, NUM_PARTITIONS: u32, + INIT_SEL: u1 = {u1:0} +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + sel_r: chan in; + + rd_req0_r: chan in; + rd_resp0_s: chan out; + wr_req0_r: chan in; + wr_resp0_s: chan out; + rd_req1_r: chan in; + rd_resp1_s: chan out; + wr_req1_r: chan in; + wr_resp1_s: chan out; + rd_req_s: chan out; + rd_resp_r: chan in; + wr_req_s: chan out; + wr_resp_r: chan in; + + config( + sel_r: chan in, + rd_req0_r: chan in, + rd_resp0_s: chan out, + wr_req0_r: chan in, + wr_resp0_s: chan out, + rd_req1_r: chan in, + rd_resp1_s: chan out, + wr_req1_r: chan in, + wr_resp1_s: chan out, + rd_req_s: chan out, + rd_resp_r: chan in, + wr_req_s: chan out, + wr_resp_r: chan in + ) { + ( + sel_r, + rd_req0_r, rd_resp0_s, wr_req0_r, wr_resp0_s, + rd_req1_r, rd_resp1_s, wr_req1_r, wr_resp1_s, + rd_req_s, rd_resp_r, wr_req_s, wr_resp_r, + ) + } + + init { + RamMuxState { + sel: INIT_SEL, ..zero!() + } + } + + next(state: RamMuxState) { + let tok0 = join(); + + let sel = state.sel; + let (cnt0, cnt1) = (state.cnt0, state.cnt1); + + // receive requests from channel 0 + let (tok1_0, rd_req0, rd_req0_valid) = + recv_if_non_blocking(tok0, rd_req0_r, sel == u1:0, zero!()); + let cnt0 = if rd_req0_valid { cnt0 + u32:1 } else { cnt0 }; + + let (tok1_1, wr_req0, wr_req0_valid) = + recv_if_non_blocking(tok0, wr_req0_r, sel == u1:0, zero!()); + let cnt0 = if wr_req0_valid { cnt0 + u32:1 } else { cnt0 }; + + // receive requests from channel 1 + let (tok1_2, rd_req1, rd_req1_valid) = + recv_if_non_blocking(tok0, rd_req1_r, sel == u1:1, zero!()); + let cnt1 = if rd_req1_valid { cnt1 + u32:1 } else { cnt1 }; + + let (tok1_3, wr_req1, wr_req1_valid) = + recv_if_non_blocking(tok0, wr_req1_r, sel == u1:1, zero!()); + let cnt1 = if wr_req1_valid { cnt1 + u32:1 } else { cnt1 }; + + // receive responses from output channel + let (tok1_4, rd_resp, rd_resp_valid) = + recv_non_blocking(tok0, rd_resp_r, zero!()); + let (tok1_5, wr_resp, wr_resp_valid) = + recv_non_blocking(tok0, wr_resp_r, zero!()); + + let tok1 = join(tok1_0, tok1_1, tok1_2, tok1_3, tok1_4, tok1_5); + + // prepare output values + let (rd_req, rd_req_valid, wr_req, wr_req_valid) = if sel == u1:0 { + (rd_req0, rd_req0_valid, wr_req0, wr_req0_valid) + } else { + (rd_req1, rd_req1_valid, wr_req1, wr_req1_valid) + }; + + // send requests to output channel + let tok2_0 = send_if(tok1, rd_req_s, rd_req_valid, rd_req); + let tok2_1 = send_if(tok1, wr_req_s, wr_req_valid, wr_req); + + // send responses to channel 0 + let rd_resp0_cond = (sel == u1:0 && rd_resp_valid); + let tok2_2 = send_if(tok1, rd_resp0_s, rd_resp0_cond, rd_resp); + let cnt0 = if rd_resp0_cond { cnt0 - u32:1 } else { cnt0 }; + + let wr_resp0_cond = (sel == u1:0 && wr_resp_valid); + let tok2_3 = send_if(tok1, wr_resp0_s, wr_resp0_cond, wr_resp); + let cnt0 = if wr_resp0_cond { cnt0 - u32:1 } else { cnt0 }; + + // send responses to channel 1 + let rd_resp1_cond = (sel == u1:1 && rd_resp_valid); + let tok2_4 = send_if(tok1, rd_resp1_s, rd_resp1_cond, rd_resp); + let cnt1 = if rd_resp1_cond { cnt1 - u32:1 } else { cnt1 }; + + let wr_resp1_cond = (sel == u1:1 && wr_resp_valid); + let tok2_5 = send_if(tok1, wr_resp1_s, wr_resp1_cond, wr_resp); + let cnt1 = if wr_resp1_cond { cnt1 - u32:1 } else { cnt1 }; + + // handle select + let (tok2_6, sel, sel_valid) = + recv_if_non_blocking(tok1, sel_r, cnt0 == u32:0 && cnt1 == u32:0, state.sel); + + RamMuxState { sel, cnt0, cnt1 } + } +} + +const MUX_TEST_SIZE = u32:32; +const MUX_TEST_DATA_WIDTH = u32:8; +const MUX_TEST_ADDR_WIDTH = std::clog2(MUX_TEST_SIZE); +const MUX_TEST_WORD_PARTITION_SIZE = u32:1; +const MUX_TEST_NUM_PARTITIONS = ram::num_partitions(MUX_TEST_WORD_PARTITION_SIZE, MUX_TEST_DATA_WIDTH); + +type MuxTestAddr = uN[MUX_TEST_ADDR_WIDTH]; +type MuxTestData = uN[MUX_TEST_DATA_WIDTH]; + +fn MuxTestWriteWordReq (addr: MuxTestAddr, data: MuxTestData) -> + ram::WriteReq { + ram::WriteWordReq(addr, data) +} + +fn MuxTestReadWordReq(addr: MuxTestAddr) -> + ram::ReadReq { + ram::ReadWordReq(addr) +} + +#[test_proc] +proc RamMuxTest { + terminator: chan out; + sel_s: chan out; + + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + + rd_req0_s: chan out; + rd_resp0_r: chan in; + wr_req0_s: chan out; + wr_resp0_r: chan in; + rd_req1_s: chan out; + rd_resp1_r: chan in; + wr_req1_s: chan out; + wr_resp1_r: chan in; + + config(terminator: chan out) { + let (sel_s, sel_r) = chan("sel"); + + let (rd_req0_s, rd_req0_r) = chan("rd_req0"); + let (rd_resp0_s, rd_resp0_r) = chan("rd_resp0"); + let (wr_req0_s, wr_req0_r) = chan("wr_req0"); + let (wr_resp0_s, wr_resp0_r) = chan("wr_resp0"); + + let (rd_req1_s, rd_req1_r) = chan("rd_req1"); + let (rd_resp1_s, rd_resp1_r) = chan("rd_resp1"); + let (wr_req1_s, wr_req1_r) = chan("rd_req1"); + let (wr_resp1_s, wr_resp1_r) = chan("wr_resp1"); + + let (rd_req_s, rd_req_r) = chan("rd_req"); + let (rd_resp_s, rd_resp_r) = chan("rd_resp"); + let (wr_req_s, wr_req_r) = chan("wr_req"); + let (wr_resp_s, wr_resp_r) = chan("wr_resp"); + + spawn RamMux( + sel_r, rd_req0_r, rd_resp0_s, wr_req0_r, wr_resp0_s, rd_req1_r, rd_resp1_s, wr_req1_r, + wr_resp1_s, rd_req_s, rd_resp_r, wr_req_s, wr_resp_r); + + spawn ram::RamModel( + rd_req_r, rd_resp_s, wr_req_r, wr_resp_s); + ( + terminator, sel_s, rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, rd_req1_s, rd_resp1_r, + wr_req1_s, wr_resp1_r, + ) + } + + init { } + + next(state: ()) { + let tok = join(); + let req = MuxTestWriteWordReq(MuxTestAddr:0, MuxTestData:0xAB); + let tok = send(tok, wr_req0_s, req); + let (tok, _) = recv(tok, wr_resp0_r); + let tok = send(tok, rd_req0_s, MuxTestReadWordReq(req.addr)); + let (tok, resp) = recv(tok, rd_resp0_r); + assert_eq(resp.data, req.data); + + let req = MuxTestWriteWordReq(MuxTestAddr:1, MuxTestData:0xCD); + let tok = send(tok, wr_req1_s, req); + let tok = send(tok, sel_s, u1:1); + let (tok, _) = recv(tok, wr_resp1_r); + let tok = send(tok, rd_req1_s, MuxTestReadWordReq(req.addr)); + let (tok, resp) = recv(tok, rd_resp1_r); + assert_eq(resp.data, req.data); + + let tok = send(tok, terminator, true); + } +} + From c15d82ecad7e67671df7e0c7435ae4b3f0c06e7e Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Tue, 7 Jan 2025 15:00:08 +0100 Subject: [PATCH 52/85] modules/zstd: Fix HuffmanRawWeightsDecoder Signed-off-by: Maciej Torhan --- xls/modules/zstd/BUILD | 3 +- xls/modules/zstd/comp_frame_huffman.x | 21 ++++ xls/modules/zstd/huffman_ctrl.x | 73 ++++++++---- xls/modules/zstd/huffman_data_preprocessor.x | 113 ++++++++++++------- xls/modules/zstd/huffman_decoder.x | 17 ++- xls/modules/zstd/huffman_literals_dec.x | 11 +- xls/modules/zstd/huffman_prescan.x | 28 ++++- xls/modules/zstd/huffman_weights_dec.x | 37 +++--- xls/modules/zstd/literals_decoder.x | 4 +- xls/modules/zstd/zstd_dec_test.x | 43 +++++-- 10 files changed, 241 insertions(+), 109 deletions(-) create mode 100755 xls/modules/zstd/comp_frame_huffman.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 9ee783025c..3616a980ad 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1276,7 +1276,8 @@ xls_dslx_test( "zstd_dec.x", "zstd_dec_test.x", # "zstd_frame_testcases.x", - "comp_frame.x", + # "comp_frame.x", + "comp_frame_huffman.x", ], tags = ["manual"], deps = zstd_dec_deps, diff --git a/xls/modules/zstd/comp_frame_huffman.x b/xls/modules/zstd/comp_frame_huffman.x new file mode 100755 index 0000000000..a83c42577d --- /dev/null +++ b/xls/modules/zstd/comp_frame_huffman.x @@ -0,0 +1,21 @@ +pub struct DataArray{ + data: uN[BITS_PER_WORD][LENGTH], + length: u32, + array_length: u32 +} +pub const FRAMES:DataArray< + u32:64, + u32:12 +>[1] = [DataArray<64, 12>{ + length: u32:93, + array_length: u32:12, + data: uN[64][12]:[uN[64]:0x00704484fd2fb528, uN[64]:0xac033a0002650000, uN[64]:0x1111111111118e00, uN[64]:0x0007000700071011, uN[64]:0x131a053a5606874c, uN[64]:0x93b7146cb45c3584, uN[64]:0x06499215949aa275, uN[64]:0x0132000c0126fd3b, uN[64]:0x15a7b54443de03b8, uN[64]:0x5da6a9b37c005000, uN[64]:0x4e0200656960219d, uN[64]:0x912a65cf0b] +}]; +pub const DECOMPRESSED_FRAMES:DataArray< + u32:64, + u32:14 +>[1] = [DataArray<64, 14>{ + length: u32:112, + array_length: u32:14, + data: uN[64][14]:[uN[64]:0x0a03050a0305000a, uN[64]:0x0605050a0305000a, uN[64]:0x0708050a03050600, uN[64]:0x05040b0c06040c04, uN[64]:0x050a030c0b05040b, uN[64]:0x06040c0408050308, uN[64]:0x0b05040b05040b0c, uN[64]:0x0a030301050a030c, uN[64]:0x090409050a030505, uN[64]:0x040c040507020a0a, uN[64]:0x0602070b03090c06, uN[64]:0x030d0f060b030d0f, uN[64]:0x0f06040c0408050b, uN[64]:0x020909040600030d] +}]; diff --git a/xls/modules/zstd/huffman_ctrl.x b/xls/modules/zstd/huffman_ctrl.x index 036a765525..c9841be1fc 100644 --- a/xls/modules/zstd/huffman_ctrl.x +++ b/xls/modules/zstd/huffman_ctrl.x @@ -59,6 +59,7 @@ struct HuffmanControlAndSequenceState { tree_description_size: uN[AXI_ADDR_W], ctrl: HuffmanControlAndSequenceCtrl, stream_sizes: uN[AXI_ADDR_W][4], + prescan_start_sent: bool, } const JUMP_TABLE_SIZE = u32:6; @@ -172,6 +173,7 @@ pub proc HuffmanControlAndSequence { let (tok, weights_dec_resp, weights_dec_resp_valid) = recv_if_non_blocking(tok, weights_dec_resp_r, state.weights_dec_pending, zero!()); if (weights_dec_resp_valid) { trace_fmt!("Received Weights Decoding response: {:#x}", weights_dec_resp); } else {}; let state = if weights_dec_resp_valid { + trace_fmt!("Tree description size: {:#x}", weights_dec_resp.tree_description_size); State { weights_dec_pending: false, tree_description_size: weights_dec_resp.tree_description_size, @@ -194,12 +196,16 @@ pub proc HuffmanControlAndSequence { let (tok, jump_table_raw, jump_table_valid) = recv_if_non_blocking(tok, mem_rd_resp_r, state.jump_table_dec_pending, zero!()); let stream_sizes = jump_table_raw.data[0:48] as u16[3]; let total_streams_size = state.ctrl.len - state.tree_description_size; - let stream_sizes = uN[AXI_ADDR_W][4]:[stream_sizes[0] as uN[AXI_ADDR_W], stream_sizes[1] as uN[AXI_ADDR_W], stream_sizes[2] as uN[AXI_ADDR_W], total_streams_size - JUMP_TABLE_SIZE as uN[AXI_ADDR_W] - (stream_sizes[0] + stream_sizes[1] + stream_sizes[2]) as uN[AXI_ADDR_W]]; + let stream_sizes = uN[AXI_ADDR_W][4]:[ + stream_sizes[0] as uN[AXI_ADDR_W], + stream_sizes[1] as uN[AXI_ADDR_W], + stream_sizes[2] as uN[AXI_ADDR_W], + total_streams_size - JUMP_TABLE_SIZE as uN[AXI_ADDR_W] - (stream_sizes[0] + stream_sizes[1] + stream_sizes[2]) as uN[AXI_ADDR_W] + ]; if jump_table_valid { trace_fmt!("Received Jump Table: {:#x}", jump_table_raw); - trace_fmt!("total_streams_size: {:#x}", total_streams_size); - trace_fmt!("state.tree_description_size: {:#x}", state.tree_description_size); - trace_fmt!("stream sizes: {:#x}", stream_sizes); + trace_fmt!("Total streams size: {:#x}", total_streams_size); + trace_fmt!("Stream sizes: {:#x}", stream_sizes); } else {}; let state = if do_send_jump_table_req { State { @@ -217,10 +223,29 @@ pub proc HuffmanControlAndSequence { state }; - let start_decoding = ((state.fsm == FSM::DECODING) & (!state.weights_dec_pending) & (!state.stream_dec_pending) & (!state.jump_table_dec_pending) & ((!state.multi_stream_dec_pending) || (state.multi_stream_dec_pending && state.multi_stream_decodings_finished != u3:4))); - send_if(tok, prescan_start_s, start_decoding, true); - send_if(tok, code_builder_start_s, start_decoding, true); - if (start_decoding) { trace_fmt!("Sent START to prescan and code builder"); } else {}; + let start_decoding = ( + (state.fsm == FSM::DECODING) & + (!state.weights_dec_pending) & + (!state.stream_dec_pending) & + (!state.jump_table_dec_pending) & + ( + (!state.multi_stream_dec_pending) || + (state.multi_stream_dec_pending && state.multi_stream_decodings_finished != u3:4) + ) + ); + let send_prescan_start = start_decoding & (!state.prescan_start_sent); + send_if(tok, prescan_start_s, send_prescan_start, true); + send_if(tok, code_builder_start_s, send_prescan_start, true); + if (send_prescan_start) { trace_fmt!("Sent START to prescan and code builder"); } else {}; + + let state = if send_prescan_start { + State { + prescan_start_sent: send_prescan_start, + ..state + } + } else { + state + }; let stream_sizes = state.stream_sizes; let (huffman_stream_addr, huffman_stream_len) = match(state.ctrl.new_config, state.ctrl.multi_stream, state.multi_stream_decodings_finished) { @@ -566,16 +591,16 @@ proc HuffmanControlAndSequence_test { uN[TEST_AXI_ADDR_W]:0x3, ]; - for (i, tok) in u32:0..u32:4 { - trace_fmt!("[TEST] Stream #{}", i); + let (tok, prescan_start) = recv(tok, prescan_start_r); + trace_fmt!("[TEST] Received prescan START"); + assert_eq(true, prescan_start); - let (tok, prescan_start) = recv(tok, prescan_start_r); - trace_fmt!("[TEST] Received prescan START"); - assert_eq(true, prescan_start); + let (tok, code_builder_start) = recv(tok, code_builder_start_r); + trace_fmt!("[TEST] Received code builder START"); + assert_eq(true, code_builder_start); - let (tok, code_builder_start) = recv(tok, code_builder_start_r); - trace_fmt!("[TEST] Received code builder START"); - assert_eq(true, code_builder_start); + for (i, tok) in u32:0..u32:4 { + trace_fmt!("[TEST] Stream #{}", i); let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); trace_fmt!("[TEST] Received AXI reader CTRL"); @@ -641,16 +666,16 @@ proc HuffmanControlAndSequence_test { uN[TEST_AXI_ADDR_W]:0x1F, ]; - for (i, tok) in u32:0..u32:4 { - trace_fmt!("[TEST] Stream #{}", i); + let (tok, prescan_start) = recv(tok, prescan_start_r); + trace_fmt!("[TEST] Received prescan START"); + assert_eq(true, prescan_start); - let (tok, prescan_start) = recv(tok, prescan_start_r); - trace_fmt!("[TEST] Received prescan START"); - assert_eq(true, prescan_start); + let (tok, code_builder_start) = recv(tok, code_builder_start_r); + trace_fmt!("[TEST] Received code builder START"); + assert_eq(true, code_builder_start); - let (tok, code_builder_start) = recv(tok, code_builder_start_r); - trace_fmt!("[TEST] Received code builder START"); - assert_eq(true, code_builder_start); + for (i, tok) in u32:0..u32:4 { + trace_fmt!("[TEST] Stream #{}", i); let (tok, axi_reader_ctrl) = recv(tok, axi_reader_ctrl_r); trace_fmt!("[TEST] Received AXI reader CTRL"); diff --git a/xls/modules/zstd/huffman_data_preprocessor.x b/xls/modules/zstd/huffman_data_preprocessor.x index 445f6fed8d..3b27e39dd0 100644 --- a/xls/modules/zstd/huffman_data_preprocessor.x +++ b/xls/modules/zstd/huffman_data_preprocessor.x @@ -34,7 +34,6 @@ enum HuffmanDataPreprocessorFSM: u2 { IDLE = 0, AWAITING_CONFIG = 1, READ_DATA = 2, - PROCESSING = 3, } pub struct HuffmanDataPreprocessorStart { @@ -45,13 +44,20 @@ pub struct HuffmanDataPreprocessorData { data: Data, data_len: CodeLen, code_length: CodeLen[H_DATA_W], + last: bool, } struct HuffmanDataPreprocessorState { fsm: HuffmanDataPreprocessorFSM, lookahead_config: Config, - data: Data, - data_len: CodeLen, + data_in: Data, + data_in_len: CodeLen, + data_in_last: bool, + data_in_ready: bool, + data_out: Data, + data_out_len: CodeLen, + data_out_last: bool, + remove_prefix: bool, } pub proc HuffmanDataPreprocessor { @@ -115,50 +121,70 @@ pub proc HuffmanDataPreprocessor { State { fsm: FSM::READ_DATA, lookahead_config: config, + remove_prefix: true, ..state } } else { state }; // receive data - let do_read_data = state.fsm == FSM::READ_DATA; + let do_read_data = state.fsm == FSM::READ_DATA && (state.data_in_len < H_DATA_W as CodeLen); let (tok, data, data_valid) = recv_if_non_blocking(tok, data_r, do_read_data, zero!()); // process data let state = if data_valid { - trace_fmt!("Received data {:#x}", data); - let fsm = if data.last { - FSM::PROCESSING - } else { - state.fsm - }; + trace_fmt!("Received data {:#b}", data); + trace_fmt!("Data in state {:#b} (length {})", state.data_in, state.data_in_len); State { - fsm: fsm, - data: state.data | ((rev(data.data) as Data) << state.data_len), - data_len: state.data_len + CodeLen:8, + data_in: state.data_in | ((rev(data.data) as Data) << state.data_in_len), + data_in_len: state.data_in_len + CodeLen:8, + data_in_last: data.last, + data_in_ready: data.last || ((state.data_in_len + CodeLen:8) == (H_DATA_W as CodeLen)), ..state } } else { state }; - let processed_data = if state.fsm == FSM::PROCESSING { - let data_bits = state.data; - let data_bits_len = state.data_len; + let state = if state.data_in_ready && state.data_out_len == CodeLen:0 { + State { + data_out: state.data_in, + data_out_len: state.data_in_len, + data_out_last: state.data_in_last, + data_in: uN[H_DATA_W]:0, + data_in_len: CodeLen:0, + data_in_last: false, + data_in_ready: false, + ..state + } + } else { + state + }; - // remove prefix - let (prefix_len, _) = for (i, (prefix_len, stop)): (u32, (u4, bool)) in range(u32:0, MAX_PREFIX_LEN as u32) { - if stop || (data_bits >> i) as u1 { - ( - prefix_len, - true, - ) - } else { - ( - prefix_len + u4:1, - stop, - ) - } - }((u4:1, false)); + let do_process_data = state.data_out_len > CodeLen:0; - trace_fmt!("Prefix len: {}", prefix_len); + let processed_data = if do_process_data { + let data_bits = state.data_out; + let data_bits_len = state.data_out_len; + trace_fmt!("Processing data {:#b} (length {})", state.data_out, state.data_out_len); + + // remove prefix + let prefix_len = if state.remove_prefix { + let (prefix_len, _) = for (i, (prefix_len, stop)): (u32, (u4, bool)) in range(u32:0, MAX_PREFIX_LEN as u32) { + if stop || (data_bits >> i) as u1 { + ( + prefix_len, + true, + ) + } else { + ( + prefix_len + u4:1, + stop, + ) + } + }((u4:1, false)); + trace_fmt!("Prefix len: {}", prefix_len); + prefix_len + } else { + u4:0 + }; let data_bits = data_bits >> prefix_len; let data_bits_len = data_bits_len - prefix_len as CodeLen; @@ -215,18 +241,23 @@ pub proc HuffmanDataPreprocessor { PreprocessedData { data: data_bits, data_len: data_bits_len, + last: state.data_out_last, code_length: code_lengths, } } else { zero!() }; - let tok = send_if(tok, preprocessed_data_s, state.fsm == FSM::PROCESSING, processed_data); + let tok = send_if(tok, preprocessed_data_s, do_process_data, processed_data); + if do_process_data { + trace_fmt!("Sent preprocessed data {:#x} (length {})", processed_data.data, processed_data.data_len); + } else {}; - let state = if state.fsm == FSM::PROCESSING { + let state = if do_process_data { State { - fsm: FSM::IDLE, - lookahead_config: state.lookahead_config, - ..zero!() + data_out: uN[H_DATA_W]:0, + data_out_len: CodeLen:0, + remove_prefix: processed_data.last, + ..state } } else { state }; @@ -311,6 +342,7 @@ const TEST_PREPROCESSED_DATA = HuffmanDataPreprocessorData[2]:[ HuffmanDataPreprocessorData { data: Data:0b110_010_1_010000_010_110_1_1_010000_010, data_len: CodeLen:30, + last: true, code_length: [ CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, @@ -329,13 +361,14 @@ const TEST_PREPROCESSED_DATA = HuffmanDataPreprocessorData[2]:[ HuffmanDataPreprocessorData { data: Data:0b1_010_100_110_1_010_100_100_001000_1_010_110_1_010_100000_010_101000_1_1_110_010_1, data_len: CodeLen:61, + last: true, code_length: [ CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:1, - CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, - CodeLen:1, CodeLen:9, CodeLen:6, CodeLen:6, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, + CodeLen:1, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, - CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:6, - CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, + CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:6, + CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, CodeLen:0, diff --git a/xls/modules/zstd/huffman_decoder.x b/xls/modules/zstd/huffman_decoder.x index 83bc91959b..154827637a 100644 --- a/xls/modules/zstd/huffman_decoder.x +++ b/xls/modules/zstd/huffman_decoder.x @@ -54,6 +54,7 @@ struct HuffmanDecoderState { symbol_code_len: uN[hcommon::WEIGHT_LOG][SYMBOLS_N], data_len: uN[BUFF_W_LOG2], data: uN[BUFF_W], + data_last: bool, code_length: CodeLen[BUFF_W], decoded_literals: uN[common::SYMBOL_WIDTH][u32:8], decoded_literals_len: u4, @@ -248,6 +249,7 @@ pub proc HuffmanDecoder { fsm: FSM::DECODE, data_len: state.data_len + data.data_len as uN[BUFF_W_LOG2], data: state.data | (data.data as uN[BUFF_W] << state.data_len), + data_last: data.last, code_length: extend_buff_array(state.code_length, state.data_len as u32, data.code_length), ..state } @@ -269,7 +271,8 @@ pub proc HuffmanDecoder { let literals = for (i, literals):(u32, uN[common::SYMBOL_WIDTH][SYMBOLS_N]) in range(u32:0, SYMBOLS_N){ if ( state.symbol_valid[i] && - (data_masked == state.symbol_code[i]) + (data_masked == state.symbol_code[i]) && + (state.code_length[0] == state.symbol_code_len[i] as CodeLen) ) { update(literals, i, i as uN[common::SYMBOL_WIDTH]) } else { @@ -324,8 +327,13 @@ pub proc HuffmanDecoder { let state = if do_send_literals { let fsm = if state.data_len == uN[BUFF_W_LOG2]:0 { - trace_fmt!("{} -> IDLE", state.fsm); - FSM::IDLE + if state.data_last { + trace_fmt!("{} -> IDLE", state.fsm); + FSM::IDLE + } else { + trace_fmt!("{} -> READ_DATA", state.fsm); + FSM::READ_DATA + } } else { trace_fmt!("{} -> DECODE", state.fsm); FSM::DECODE @@ -574,6 +582,7 @@ const TEST_DATA = huffman_data_preprocessor::HuffmanDataPreprocessorData[3]:[ huffman_data_preprocessor::HuffmanDataPreprocessorData { data: huffman_data_preprocessor::Data:0x32a0b682, data_len: CodeLen:30, + last: true, code_length: [ CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, @@ -592,6 +601,7 @@ const TEST_DATA = huffman_data_preprocessor::HuffmanDataPreprocessorData[3]:[ huffman_data_preprocessor::HuffmanDataPreprocessorData { data: huffman_data_preprocessor::Data:0x32a0b682, data_len: CodeLen:30, + last: true, code_length: [ CodeLen:3, CodeLen:1, CodeLen:6, CodeLen:6, CodeLen:4, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:3, CodeLen:1, @@ -610,6 +620,7 @@ const TEST_DATA = huffman_data_preprocessor::HuffmanDataPreprocessorData[3]:[ huffman_data_preprocessor::HuffmanDataPreprocessorData { data: huffman_data_preprocessor::Data:0b1_010_100_110_1_010_100_100_001000_1_010_110_1_010_100000_010_101000_1_1_110_010_1, data_len: CodeLen:61, + last: true, code_length: [ CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:1, CodeLen:1, CodeLen:1, CodeLen:6, CodeLen:3, CodeLen:3, CodeLen:1, CodeLen:3, CodeLen:1, CodeLen:3, diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index ad396a78c6..55589b9992 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -37,11 +37,14 @@ pub type HuffmanLiteralsDecoderReq = ctrl::HuffmanControlAndSequenceCtrl; pub type HuffmanLiteralsDecoderResp = ctrl::HuffmanControlAndSequenceResp; pub type HuffmanLiteralsDecoderStatus = ctrl::HuffmanControlAndSequenceStatus; +pub const RAM_SIZE: u32 = prescan::RAM_SIZE; pub const WEIGHTS_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; pub const WEIGHTS_DATA_WIDTH: u32 = prescan::RAM_ACCESS_WIDTH; +pub const WEIGHTS_PARTITION_WORD_SIZE: u32 = WEIGHTS_DATA_WIDTH; pub const WEIGHTS_NUM_PARTITIONS: u32 = u32:1; pub const PRESCAN_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; pub const PRESCAN_DATA_WIDTH: u32 = prescan::WeightPreScanMetaDataSize(); +pub const PRESCAN_PARTITION_WORD_SIZE: u32 = PRESCAN_DATA_WIDTH; pub const PRESCAN_NUM_PARTITIONS: u32 = u32:1; pub proc HuffmanLiteralsDecoder< @@ -371,7 +374,7 @@ const TEST_MEMORY: TestAxiRamWrReq[7] = [ // Literals #0 // Length: 6 bytes // New config, 1 Stream - // HTD Header: 0x85 (Direct representation, HTD length: 3 + HTD_header (1 byte)) + // HTD Header: 0x84 (Direct representation, HTD length: 3) // Huffman Tree Description // code symbol length weight // N/A 0x03 0 0 @@ -382,7 +385,7 @@ const TEST_MEMORY: TestAxiRamWrReq[7] = [ // 0b1 0x00 1 4 // 0b00001 padding - TestAxiRamWrReq { addr: TestAxiRamAddr:0x0, data: (u16:0b00001_1_01_0000_0001 ++ u24:0x010234 ++ u8:0x85) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + TestAxiRamWrReq { addr: TestAxiRamAddr:0x0, data: (u16:0b00001_1_01_0000_0001 ++ u24:0x100234 ++ u8:0x84) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, // AXI addr: 0x0 ^ ^ ^ // Huffman-coded stream HTD HTD Header @@ -397,7 +400,7 @@ const TEST_MEMORY: TestAxiRamWrReq[7] = [ // Literals #2 // Length: 18 bytes // New config, 4 Streams - // HTD Header: 0x85 (Direct representation, HTD length: 3 + HTD_header (1 byte)) + // HTD Header: 0x84 (Direct representation, HTD length: 3 + HTD_header (1 byte)) // Jump Table: 0x0002_0002_0002 (Stream1: 2 bytes; Stream2: 2 bytes; Stream3: 2 bytes) // Huffman Tree Description // code symbol length weight @@ -408,7 +411,7 @@ const TEST_MEMORY: TestAxiRamWrReq[7] = [ // 0b01 0x01 2 3 // 0b1 0x00 1 4 // 0b00001 padding - TestAxiRamWrReq { addr: TestAxiRamAddr:0x40, data: (u32:0x0002_0002 ++ u24:0x010234 ++ u8:0x85) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, + TestAxiRamWrReq { addr: TestAxiRamAddr:0x40, data: (u32:0x0002_0002 ++ u24:0x100234 ++ u8:0x84) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, // AXI addr: 0x200 ^ ^ ^ // Jump table HTD HTD Header TestAxiRamWrReq { addr: TestAxiRamAddr:0x41, data: (u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u16:0x0002) as TestAxiRamData, mask: TestAxiRamMask:0xFF }, diff --git a/xls/modules/zstd/huffman_prescan.x b/xls/modules/zstd/huffman_prescan.x index 4cc49c9cd5..6acf0284aa 100644 --- a/xls/modules/zstd/huffman_prescan.x +++ b/xls/modules/zstd/huffman_prescan.x @@ -171,6 +171,7 @@ pub proc WeightPreScan next(state: State) { let tok = join(); + trace_fmt!("State {}", state.fsm); let (recv_start, send_addr, write_internal, read_internal, addr) = match state.fsm { FSM::IDLE => (true, false, false, false, u32:0 as ExternalRamAddr), FSM::FIRST_RUN => (false, true, true, false, state.addr as ExternalRamAddr), @@ -184,8 +185,14 @@ pub proc WeightPreScan } }; let (tok1, start) = recv_if(tok, start_r, recv_start, false); - - let (tok2, internal_addr, _) = recv_non_blocking(tok, internal_memory_written_r, state.internal_addr as InternalRamAddr); + if recv_start { + trace_fmt!("Start received"); + } else {}; + + let (tok2, internal_addr, internal_addr_valid) = recv_non_blocking(tok, internal_memory_written_r, state.internal_addr as InternalRamAddr); + if internal_addr_valid { + trace_fmt!("Received internal addr {:#x}", internal_addr); + } else {}; let next_state = match (state.fsm, start, send_addr, state.addr as u32 == MAX_RAM_ADDR - u32:1) { (FSM::IDLE, true, _, _) => State { fsm: FSM::FIRST_RUN, @@ -237,8 +244,14 @@ pub proc WeightPreScan mask: u1:1, }; let tok3 = send_if(tok, read_req_s, send_addr, external_ram_req); + if send_addr { + trace_fmt!("Sent read request {:#x}", external_ram_req); + } else {}; let (tok3, ram_data) = recv_if(tok3, read_rsp_r, send_addr, zero!()); let ram_data = ram_data.data as uN[WEIGHT_LOG][PARALLEL_ACCESS_WIDTH]; + if send_addr { + trace_fmt!("Received read response {:#x}", ram_data); + } else {}; let internal_ram_r_req = InternalReadReq { addr: addr, @@ -249,11 +262,18 @@ pub proc WeightPreScan let meta_data = BitsToInternalStruct(meta_data_flat.data); let tok34 = join(tok3, tok4); + if read_internal { + trace_fmt!("Reading internal memory data: {:#x}", meta_data); + } else {}; + let prescan_output = OutData { weights: ram_data, meta_data: meta_data }; let tok34 = send_if(tok34, weight_s, send_addr, prescan_output); + if send_addr { + trace_fmt!("Sent output {:#x}", prescan_output); + } else {}; let occurance_matrix = for (i, occurance_matrix) in range(u32:0, PARALLEL_ACCESS_WIDTH) { let row = for (j, row) in range(u32:0, MAX_WEIGHT + u32:1) { @@ -288,6 +308,10 @@ pub proc WeightPreScan let tok5 = send_if(tok, internal_write_req_s, write_internal, internal_ram_w_req); let (tok5, _) = recv_if(tok5, internal_write_rsp_r, write_internal, zero!()); send_if(tok5, internal_memory_written_s, state.fsm == FSM::FIRST_RUN, addr as InternalRamAddr); + if write_internal { + trace_fmt!("Internal write {:#x}", _meta_data); + } else {}; + next_state } } diff --git a/xls/modules/zstd/huffman_weights_dec.x b/xls/modules/zstd/huffman_weights_dec.x index 4dd04173b8..e44b0d11d0 100644 --- a/xls/modules/zstd/huffman_weights_dec.x +++ b/xls/modules/zstd/huffman_weights_dec.x @@ -138,20 +138,9 @@ proc HuffmanRawWeightsDecoder< let (tok, mem_rd_resp, mem_rd_resp_valid) = recv_if_non_blocking(tok, mem_rd_resp_r, do_recv_data, zero!()); if do_recv_data && mem_rd_resp_valid { trace_fmt!("[RAW] Received MemReader response {:#x}", mem_rd_resp); + trace_fmt!("[RAW] Data {:#x}", mem_rd_resp.data); } else {}; - // FIXME: support injecting the last implicit weight for Huffman Tree Descriptions larger - // than a single bus width - // - // ^ This is partially done with saving the sum calculated below in the state. - // When the last mem_reader packet is received (received the last chunk of HTD) - // We should calculate the final sum and use it to calculate the `last_weight` of the HTD - // and put it in a correct spot in the `weights` array - - // Calculate the last weight by summing 2^(weight - 1) - // for each weight read from the HTD (excluding 0's) - // The resulting sum must be subtracted from the next power of 2 after the resulting sum. - // The result is the weight of the last literal. const MAX_WEIGHTS_IN_PACKET = AXI_DATA_W >> u32:2; let weights = mem_rd_resp.data as u4[MAX_WEIGHTS_IN_PACKET]; let sum = for (i, sum): (u32, u32) in u32:0..MAX_WEIGHTS_IN_PACKET { @@ -202,18 +191,16 @@ proc HuffmanRawWeightsDecoder< ) as uN[AXI_DATA_W], _ => fail!("unsupported_axi_data_width", uN[AXI_DATA_W]:0), }; - //trace_fmt!("[RAW] Reversed weights: {:#x}", reversed_weights); - //trace_fmt!("[RAW] BUFF_LEN: {:#x}", BUFF_LEN); - //trace_fmt!("[RAW] WEIGHTS_RAM_DATA_W: {:#x}", WEIGHTS_RAM_DATA_W); - //trace_fmt!("[RAW] AXI_DATA_W: {:#x}", AXI_DATA_W); - //trace_fmt!("[RAW] buffer_len: {:#x}", buffer_len); + + if do_recv_data && mem_rd_resp_valid { + trace_fmt!("[RAW] Weights: {:#x}", weights); + } else {}; if do_recv_data && mem_rd_resp_valid { trace_fmt!("[RAW] Weights: {:#x}", weights); } else {}; let (buffer, buffer_len) = if do_recv_data && mem_rd_resp_valid { - //trace_fmt!("[RAW] shift: {:#x}", BUFF_LEN - AXI_DATA_W - buffer_len as u32); ( buffer | ((reversed_weights as uN[BUFF_LEN] << (BUFF_LEN - AXI_DATA_W - buffer_len as u32))), buffer_len + (AXI_DATA_W as uN[BUFF_LEN_LOG2]), @@ -621,7 +608,9 @@ pub proc HuffmanWeightsDecoder< let tok = send(tok, decoded_weights_sel_s, weights_type == WeightsType::FSE); // FSE - trace_fmt!("Decoding FSE Huffman weights"); + if weights_type == WeightsType::FSE { + trace_fmt!("Decoding FSE Huffman weights"); + } else {}; let fse_weights_req = zero!(); let tok = send_if(tok, fse_weights_req_s, weights_type == WeightsType::FSE, fse_weights_req); let (tok, fse_weights_resp) = recv_if(tok, fse_weights_resp_r, weights_type == WeightsType::FSE, zero!()); @@ -633,7 +622,9 @@ pub proc HuffmanWeightsDecoder< }; // RAW - trace_fmt!("Decoding RAW Huffman weights"); + if weights_type == WeightsType::RAW { + trace_fmt!("Decoding RAW Huffman weights"); + } else {}; let raw_weights_req = RawWeightsReq { addr: req.addr, n_symbols: header_byte - u8:127, @@ -651,13 +642,13 @@ pub proc HuffmanWeightsDecoder< WeightsType::RAW => { Resp { status: raw_status, - tree_description_size: (((header_byte - u8:127) >> u8:1) + u8:1) as uN[AXI_ADDR_W], + tree_description_size: (((header_byte - u8:127) >> u8:1) + u8:1) as uN[AXI_ADDR_W] + uN[AXI_ADDR_W]:1, // include header size } }, WeightsType::FSE => { Resp { status: fse_status, - tree_description_size: header_byte as uN[AXI_ADDR_W], + tree_description_size: header_byte as uN[AXI_ADDR_W] + uN[AXI_ADDR_W]:1, // include header size } }, _ => fail!("impossible_weights_type", zero!()), @@ -975,7 +966,7 @@ proc HuffmanWeightsDecoder_test { let (tok, resp) = recv(tok, resp_r); trace_fmt!("[TEST] Received respose {:#x}", resp); assert_eq(HuffmanWeightsDecoderStatus::OKAY, resp.status); - assert_eq(((TEST_DATA[0] - u8:127 + u8:1) >> u32:1) as uN[TEST_AXI_ADDR_W], resp.tree_description_size); + assert_eq((((TEST_DATA[0] - u8:127 + u8:1) >> u32:1) + u8:1) as uN[TEST_AXI_ADDR_W], resp.tree_description_size); // Insert last weight in test data let last_weight_idx = ((TEST_DATA[0] as u32 - u32:127) / u32:2) + u32:1; diff --git a/xls/modules/zstd/literals_decoder.x b/xls/modules/zstd/literals_decoder.x index 1cf493af93..4aab622bfd 100644 --- a/xls/modules/zstd/literals_decoder.x +++ b/xls/modules/zstd/literals_decoder.x @@ -1531,7 +1531,7 @@ proc LiteralsDecoder_test { // Literals #4 (Huffman; 6 bytes) // Header: 0x01_80_42 (0b0000000110_0000000100_00_10) - AxiRamWrReq { addr: AxiRamAddr:0x10, data: (u8:0b0000_0001 ++ u24:0x010234 ++ u8:0x85 ++ u24:0x01_80_42) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x80 + AxiRamWrReq { addr: AxiRamAddr:0x10, data: (u8:0b0000_0001 ++ u24:0x100234 ++ u8:0x84 ++ u24:0x01_80_42) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x80 AxiRamWrReq { addr: AxiRamAddr:0x11, data: u8:0b00001_1_01 as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x88 // Literals #5 (RLE; 12 bytes) @@ -1548,7 +1548,7 @@ proc LiteralsDecoder_test { // Literals #8 (Huffman; 18 bytes) // Header: 0x04_81_06 (0b0000010010_0000010010_01_10) - AxiRamWrReq { addr: AxiRamAddr:0x50, data: (u8:0x02 ++ u24:0x010234 ++ u8:0x85 ++ u24:0x04_81_06) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x280 + AxiRamWrReq { addr: AxiRamAddr:0x50, data: (u8:0x02 ++ u24:0x100234 ++ u8:0x84 ++ u24:0x04_81_06) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x280 AxiRamWrReq { addr: AxiRamAddr:0x51, data: (u8:0b0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u40:0x0002_0002_00) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 0x288 AxiRamWrReq { addr: AxiRamAddr:0x52, data: (u16:0b00001_1_01_0000_0001 ++ u16:0b00001_1_01_0000_0001 ++ u8:0b00001_1_01) as AxiRamData, mask: AxiRamMask:0xFF }, // AXI addr: 290 diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index a115e1f83c..e73e2edffa 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -18,7 +18,6 @@ import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; import xls.modules.zstd.csr_config; import xls.modules.zstd.sequence_executor; -// import xls.modules.zstd.zstd_frame_testcases; import xls.modules.zstd.memory.axi_ram; import xls.modules.zstd.zstd_dec; import xls.modules.zstd.comp_block_dec; @@ -29,7 +28,9 @@ import xls.modules.zstd.parallel_rams; import xls.modules.zstd.literals_buffer; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.ram_mux; -import xls.modules.zstd.comp_frame; +// import xls.modules.zstd.zstd_frame_testcases as comp_frame; +// import xls.modules.zstd.comp_frame; +import xls.modules.zstd.comp_frame_huffman as comp_frame; const TEST_WINDOW_LOG_MAX = u32:30; @@ -83,12 +84,18 @@ const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); +// Huffman weights memory parameters +const HUFFMAN_WEIGHTS_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; const HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; +const HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE: u32 = huffman_literals_dec::WEIGHTS_PARTITION_WORD_SIZE; const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; + // Huffman prescan memory parameters +const HUFFMAN_PRESCAN_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; const HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; const HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; +const HUFFMAN_PRESCAN_RAM_PARTITION_WORD_SIZE: u32 = huffman_literals_dec::PRESCAN_PARTITION_WORD_SIZE; const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; const HISTORY_BUFFER_SIZE_KB = common::HISTORY_BUFFER_SIZE_KB; @@ -287,16 +294,32 @@ proc ZstdDecoderTest { let (reset_s, reset_r) = chan<()>("reset"); // Huffman weights memory - let (huffman_lit_weights_mem_rd_req_s, _huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); - let (_huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); - let (huffman_lit_weights_mem_wr_req_s, _huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); - let (_huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + + spawn ram::RamModel< + HUFFMAN_WEIGHTS_RAM_DATA_W, HUFFMAN_WEIGHTS_RAM_SIZE, HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + huffman_lit_weights_mem_rd_req_r, huffman_lit_weights_mem_rd_resp_s, + huffman_lit_weights_mem_wr_req_r, huffman_lit_weights_mem_wr_resp_s, + ); // Huffman prescan memory - let (huffman_lit_prescan_mem_rd_req_s, _huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); - let (_huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); - let (huffman_lit_prescan_mem_wr_req_s, _huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); - let (_huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + let (huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); + let (huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); + let (huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); + let (huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + + spawn ram::RamModel< + HUFFMAN_PRESCAN_RAM_DATA_W, HUFFMAN_PRESCAN_RAM_SIZE, HUFFMAN_PRESCAN_RAM_PARTITION_WORD_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + huffman_lit_prescan_mem_rd_req_r, huffman_lit_prescan_mem_rd_resp_s, + huffman_lit_prescan_mem_wr_req_r, huffman_lit_prescan_mem_wr_resp_s, + ); // AXI channels for various blocks let (comp_axi_ar_s, comp_axi_ar_r) = chan[AXI_CHAN_N]("comp_axi_ar"); From 72d517d4c9edcc9ab5872305b368d24e783fc4f8 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 16 Jan 2025 15:11:27 +0100 Subject: [PATCH 53/85] Fix decoding multiple frames Signed-off-by: Robert Winkler --- xls/modules/zstd/command_constructor.x | 34 +-- xls/modules/zstd/comp_block_dec.x | 170 +++++++++------ xls/modules/zstd/comp_frame.x | 20 +- xls/modules/zstd/dec_mux.x | 22 +- xls/modules/zstd/fse_dec.x | 2 +- xls/modules/zstd/literals_buffer.x | 2 +- xls/modules/zstd/parallel_rams.x | 15 +- xls/modules/zstd/sequence_dec.x | 34 ++- xls/modules/zstd/sequence_executor.x | 284 ++++++++++++++++++------- xls/modules/zstd/zstd_dec.x | 19 +- xls/modules/zstd/zstd_dec_test.x | 1 + 11 files changed, 403 insertions(+), 200 deletions(-) diff --git a/xls/modules/zstd/command_constructor.x b/xls/modules/zstd/command_constructor.x index 9fd3f9eb9d..35d58f31b3 100644 --- a/xls/modules/zstd/command_constructor.x +++ b/xls/modules/zstd/command_constructor.x @@ -27,7 +27,7 @@ type CopyOrMatchContent = common::CopyOrMatchContent; type CopyOrMatchLength = common::CopyOrMatchLength; type SequenceExecutorPacket = common::SequenceExecutorPacket; -type LiteralsBufferCtrl = common::LiteralsBufferCtrl; +type LiteralsBufferCtrl = common::LiteralsBufferCtrl; type CommandConstructorData = common::CommandConstructorData; type ExtendedBlockDataPacket = common::ExtendedBlockDataPacket; type BlockSyncData = common::BlockSyncData; @@ -42,7 +42,7 @@ struct State { status: Status, received_literals: CopyOrMatchLength, literals_to_receive: CopyOrMatchLength, - sync: BlockSyncData, + command: CommandConstructorData, } pub proc CommandConstructor { @@ -64,24 +64,29 @@ pub proc CommandConstructor { let tok0 = join(); let recv_command = state.status == Status::RECV_COMMAND; - let (tok1_0, command) = - recv_if(tok0, sequence_decoder_r, recv_command, zero!()); + let (tok1_0, command) = recv_if(tok0, sequence_decoder_r, recv_command, state.command); + if recv_command { + trace_fmt!("[CommandConstructor] Received command: {:#x}", command); + } else {}; let recv_literals = state.status == Status::RECV_LITERALS; - let (tok1_1, literals) = - recv_if(tok0, literals_buffer_resp_r, recv_literals, zero!()); + let (tok1_1, literals) = recv_if(tok0, literals_buffer_resp_r, recv_literals, zero!()); + if recv_literals { + trace_fmt!("[CommandConstructor] Received literals: {:#x}", literals); + } else {}; let tok1 = join(tok1_0, tok1_1); let (new_state, do_send_command, do_send_literals_req) = match (state.status) { Status::RECV_COMMAND => { - if command.data.msg_type == SequenceExecutorMessageType::LITERAL { + if (command.data.msg_type == SequenceExecutorMessageType::LITERAL) && + (command.data.length != CopyOrMatchLength:0) { ( State { status: Status::RECV_LITERALS, received_literals: CopyOrMatchLength:0, literals_to_receive: command.data.length, - sync: command.sync, + command: command, }, false, true, ) } else { @@ -108,7 +113,7 @@ pub proc CommandConstructor { let resp = match(state.status) { // sent only if the original message was of type SEQUENCE Status::RECV_COMMAND => ExtendedBlockDataPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, + msg_type: command.data.msg_type, packet: BlockDataPacket { last: command.data.last, last_block: command.sync.last_block, @@ -120,9 +125,9 @@ pub proc CommandConstructor { Status::RECV_LITERALS => ExtendedBlockDataPacket { msg_type: SequenceExecutorMessageType::LITERAL, packet: BlockDataPacket { - last: literals.last, - last_block: state.sync.last_block, - id: state.sync.id, + last: literals.last & command.data.last, + last_block: command.sync.last_block, + id: command.sync.id, data: literals.content, length: literals.length as u32, // FIXME: remove cast after unifying types of 'length' fields } @@ -130,6 +135,9 @@ pub proc CommandConstructor { _ => fail!("resp_match_unreachable", zero!()) }; send_if(tok1, command_aggregator_s, do_send_command, resp); + if do_send_command { + trace_fmt!("[CommandConstructor] Sending command: {:#x}", resp); + } else {}; new_state } @@ -179,7 +187,7 @@ proc FakeLiteralsBuffer { ) }, FakeLiteralsBufferStatus::SEND => { - let length = std::umin(state.literals_left_to_send, CopyOrMatchLength:64); + let length = std::min(state.literals_left_to_send, CopyOrMatchLength:64); let next_left_to_send = state.literals_left_to_send - length; let last = next_left_to_send == CopyOrMatchLength:0; let resp = SequenceExecutorPacket { diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index 9a47caffd1..94a3912ed6 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -512,27 +512,27 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ ExtendedPacket[128]:[ ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x431fba7f9f155239, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:0, data: u64:0x431fba7f9f155239, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xe75b86b1dfe3, length: u32:6 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:0, data: u64:0xe75b86b1dfe3, length: u32:6 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x192, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:0, data: u64:0x192, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xd6c643, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:0, data: u64:0xd6c643, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x223, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:0, data: u64:0x223, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x00, length: u32:1 } + packet: BlockDataPacket { last: true, last_block: false, id: u32:0, data: u64:0x00, length: u32:1 } }, zero!(), ... ] @@ -576,43 +576,43 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ ExtendedPacket[128]:[ ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xa2bbc79280150052, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0xa2bbc79280150052, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2e159be2210a8b13, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x2e159be2210a8b13, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2bcd291994532c42, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x2bcd291994532c42, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x64de1c37a8940c11, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x64de1c37a8940c11, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x9fa347, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x9fa347, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x116, length: u32:4 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x116, length: u32:4 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x9b679780bbc95f95, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x9b679780bbc95f95, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xd90c2f2b9757c107, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0xd90c2f2b9757c107, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x58ba369e427a819d, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:1, data: u64:0x58ba369e427a819d, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0xd27d5a829f, length: u32:5 } + packet: BlockDataPacket { last: true, last_block: false, id: u32:1, data: u64:0xd27d5a829f, length: u32:5 } }, zero!(), ... ] @@ -651,91 +651,127 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ u64:0x40381ea080, u64:0, ... ], - u32:21, + u32:30, ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } + }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x1f50, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x1f50, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76767676, length: u32:4 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x76767676, length: u32:4 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x21a, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x21a, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x2, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x1bee, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x1bee, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x76, length: u32:1 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2026, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x2026, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x1d93, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x1d93, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x76, length: u32:1 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2a39, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x2a39, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x76, length: u32:1 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x3111, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x3111, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x76, length: u32:1 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x76, length: u32:1 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xe76, length: u32:4 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0xe76, length: u32:4 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x303d, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x303d, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x3, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x3, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x36ea, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x36ea, length: u32:3 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x7676767676, length: u32:5 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x7676767676, length: u32:5 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x53be, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x53be, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x14ef, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x14ef, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:2, data: u64:0x0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x2ce2, length: u32:4 } + packet: BlockDataPacket { last: true, last_block: false, id: u32:2, data: u64:0x2ce2, length: u32:4 } }, zero!(), ... ], @@ -772,67 +808,67 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ ExtendedPacket[128]:[ ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5, length: u32:6 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5, length: u32:6 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x2, length: u32:4 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0x2, length: u32:4 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5, length: u32:4 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5, length: u32:4 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0x4c, length: u32:6 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0x4c, length: u32:6 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:3, data: u64:0xf5f5f5f5f5f5f5f5, length: u32:8 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0xf5f5f5f5, length: u32:4 } + packet: BlockDataPacket { last: true, last_block: false, id: u32:3, data: u64:0xf5f5f5f5, length: u32:4 } }, zero!(), ... ] @@ -865,8 +901,12 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ u64:0x1501, u64:0, ... ], - u32:0, + u32:1, ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: true, last_block: false, id: u32:4, data: u64:0x0, length: u32:0 } + }, zero!(), ... ] ), @@ -897,15 +937,23 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ u64:0x1020070, u64:0, ... ], - u32:2, + u32:4, ExtendedPacket[128]:[ + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:5, data: u64:0x0, length: u32:0 } + }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: false, last_block: false, id: u32:1234, data: u64:0xf06, length: u32:3 } + packet: BlockDataPacket { last: false, last_block: false, id: u32:5, data: u64:0xf06, length: u32:3 } + }, + ExtendedPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + packet: BlockDataPacket { last: false, last_block: false, id: u32:5, data: u64:0, length: u32:0 } }, ExtendedPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x2b77, length: u32:4 } + packet: BlockDataPacket { last: true, last_block: false, id: u32:5, data: u64:0x2b77, length: u32:4 } }, zero!(), ... ], @@ -940,7 +988,7 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ ExtendedPacket[128]:[ ExtendedPacket { msg_type: SequenceExecutorMessageType::LITERAL, - packet: BlockDataPacket { last: true, last_block: false, id: u32:1234, data: u64:0x215a, length: u32:2 } + packet: BlockDataPacket { last: true, last_block: false, id: u32:6, data: u64:0x215a, length: u32:2 } }, zero!(), ... ], @@ -1306,7 +1354,7 @@ proc CompressBlockDecoderTest { }(tok); let tok = send(tok, ml_sel_test_s, u1:1); - let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:6, array_size(COMP_BLOCK_DEC_TESTCASES)) { + let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(COMP_BLOCK_DEC_TESTCASES)) { let (input_length, input, output_length, output) = COMP_BLOCK_DEC_TESTCASES[test_i]; trace_fmt!("Loading testcase {}", test_i); @@ -1330,7 +1378,7 @@ proc CompressBlockDecoderTest { let req = Req { addr: uN[TEST_AXI_ADDR_W]:0x100, length: input_length as BlockSize, - id: u32:1234, + id: test_i, last_block: false, }; diff --git a/xls/modules/zstd/comp_frame.x b/xls/modules/zstd/comp_frame.x index 5e1a97dbd4..8376d6bf1d 100644 --- a/xls/modules/zstd/comp_frame.x +++ b/xls/modules/zstd/comp_frame.x @@ -5,17 +5,17 @@ pub struct DataArray{ } pub const FRAMES:DataArray< u32:64, - u32:5 ->[1] = [DataArray<64, 5>{ - length: u32:33, - array_length: u32:5, - data: uN[64][5]:[uN[64]:0x001a3384fd2fb528, uN[64]:0xc1d3500000850000, uN[64]:0xdcf0529b98db8a06, uN[64]:0x308fa3120a430001, uN[64]:0x50] + u32:7 +>[1] = [DataArray<64, 7>{ + length: u32:51, + array_length: u32:7, + data: uN[64][7]:[uN[64]:0x00504784fd2fb528, uN[64]:0xcf95700001150000, uN[64]:0xe17d50b989ac93c4, uN[64]:0x0daf000895a6e608, uN[64]:0xb96010b86f7602a4, uN[64]:0x05b0e051238666e8, uN[64]:0x8470e3] }]; pub const DECOMPRESSED_FRAMES:DataArray< u32:64, - u32:4 ->[1] = [DataArray<64, 4>{ - length: u32:26, - array_length: u32:4, - data: uN[64][4]:[uN[64]:0x529b98db8a06c1d3, uN[64]:0x529b98db8a06dcf0, uN[64]:0x529b98db8a06dcf0, uN[64]:0xdcf0] + u32:10 +>[1] = [DataArray<64, 10>{ + length: u32:80, + array_length: u32:10, + data: uN[64][10]:[uN[64]:0xc4c4cf95cf95cf95, uN[64]:0x93c4c4c4c4c4c4c4, uN[64]:0xacc493c493c493c4, uN[64]:0xc493c493c493c489, uN[64]:0x93c493c489acc493, uN[64]:0x08e17d50b9c493c4, uN[64]:0xc4c4c4cf9595a6e6, uN[64]:0x93c493c4c4c4c4c4, uN[64]:0xc489acc493c493c4, uN[64]:0xc493c493c493c493] }]; diff --git a/xls/modules/zstd/dec_mux.x b/xls/modules/zstd/dec_mux.x index 6f0d1d7f8b..681b1b402d 100644 --- a/xls/modules/zstd/dec_mux.x +++ b/xls/modules/zstd/dec_mux.x @@ -130,7 +130,7 @@ pub proc DecoderMux { (((state.raw_data.packet.id == (state.prev_id + u32:1)) && state.prev_last) || ((state.raw_data.packet.id == state.prev_id) && !state.prev_last))) { assert!(!state.raw_data_valid_next_frame, "raw_packet_valid_in_current_and_next_frame"); - (true, + ((state.raw_data.packet.length as CopyOrMatchLength) != CopyOrMatchLength:0, SequenceExecutorPacket { msg_type: state.raw_data.msg_type, length: state.raw_data.packet.length as CopyOrMatchLength, @@ -153,7 +153,7 @@ pub proc DecoderMux { (((state.rle_data.packet.id == (state.prev_id + u32:1)) && state.prev_last) || ((state.rle_data.packet.id == state.prev_id) && !state.prev_last))) { assert!(!state.rle_data_valid_next_frame, "rle_packet_valid_in_current_and_next_frame"); - (true, + ((state.rle_data.packet.length as CopyOrMatchLength) != CopyOrMatchLength:0, SequenceExecutorPacket { msg_type: state.rle_data.msg_type, length: state.rle_data.packet.length as CopyOrMatchLength, @@ -282,9 +282,7 @@ proc DecoderMuxEmptyRawBlocksTest { let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); send(tok, terminator, true); } @@ -320,9 +318,7 @@ proc DecoderMuxEmptyRleBlocksTest { let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); send(tok, terminator, true); } @@ -361,7 +357,6 @@ proc DecoderMuxEmptyBlockBetweenRegularBlocksOnTheSameInputChannelTest { let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:4 }); @@ -403,7 +398,6 @@ proc DecoderMuxEmptyBlockBetweenRegularBlocksOnDifferentInputChannelsTest { let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x11111111, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x22222222, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x33333333, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0, length: CopyOrMatchLength:0 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xAAAAAAAA, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0xBBBBBBBB, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x00000000, length: CopyOrMatchLength:4 }); @@ -474,19 +468,9 @@ proc DecoderMuxMultipleFramesTest { // Frame #2 let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x44444444, length: CopyOrMatchLength:4 }); let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); + let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); // Frame #3 let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x55555555, length: CopyOrMatchLength:4 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: false, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); - let (tok, data) = recv(tok, output_r); assert_eq(data, SequenceExecutorPacket {last: bool: true, msg_type: SequenceExecutorMessageType::LITERAL, content: CopyOrMatchContent:0x0 , length: CopyOrMatchLength:0 }); send(tok, terminator, true); } diff --git a/xls/modules/zstd/fse_dec.x b/xls/modules/zstd/fse_dec.x index 143cd45b7f..e19943a433 100644 --- a/xls/modules/zstd/fse_dec.x +++ b/xls/modules/zstd/fse_dec.x @@ -343,13 +343,13 @@ pub proc FseDecoder< } }; let do_send_command = ( - (command_data.length != CopyOrMatchLength:0) && ( state.fsm == FseDecoderFSM::SEND_COMMAND_LITERAL || state.fsm == FseDecoderFSM::SEND_COMMAND_SEQUENCE || state.fsm == FseDecoderFSM::SEND_LEFTOVER_LITERALS_REQ ) ); + let command = CommandConstructorData { sync: state.ctrl.sync, data: command_data, diff --git a/xls/modules/zstd/literals_buffer.x b/xls/modules/zstd/literals_buffer.x index b1e02c21c8..868953a593 100644 --- a/xls/modules/zstd/literals_buffer.x +++ b/xls/modules/zstd/literals_buffer.x @@ -709,7 +709,7 @@ proc LiteralsBufferReader< last: ctrl_last, }; - let (read_reqs, read_start, read_len, packet, _) = parallel_rams::sequence_packet_to_read_reqs< + let (read_reqs, read_start, read_len, _, _) = parallel_rams::sequence_packet_to_read_reqs< HISTORY_BUFFER_SIZE_KB, RAM_ADDR_WIDTH, RAM_DATA_WIDTH >( state.hyp_ptr, packet, state.hb_len diff --git a/xls/modules/zstd/parallel_rams.x b/xls/modules/zstd/parallel_rams.x index 24f9718326..7e10796cfb 100644 --- a/xls/modules/zstd/parallel_rams.x +++ b/xls/modules/zstd/parallel_rams.x @@ -443,9 +443,20 @@ pub fn sequence_packet_to_read_reqs< type ReadReq = ram::ReadReq; type Packet = SequenceExecutorPacket; - let max_len = std::umin(seq.length as u32, std::umin(RAM_NUM, hb_len as u32)); + let max_len = std::min(seq.length as u32, std::min(RAM_NUM, std::min(hb_len as u32, seq.content as u32))); let (curr_seq, next_seq, next_seq_valid) = if seq.length > max_len as CopyOrMatchLength { + ( + seq, + Packet { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: seq.length - max_len as CopyOrMatchLength, + content: seq.content, + last: false, + }, + true, + ) + } else if seq.length > seq.content as CopyOrMatchLength { ( Packet { msg_type: SequenceExecutorMessageType::SEQUENCE, @@ -545,7 +556,7 @@ fn test_sequence_packet_to_read_reqs() { RamReadLen:8, Packet { msg_type: SequenceExecutorMessageType::SEQUENCE, - content: CopyOrMatchContent:18, + content: CopyOrMatchContent:10, length: CopyOrMatchLength:1, last: false }, true, diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x index 6f1823df49..e6e1a2eea0 100644 --- a/xls/modules/zstd/sequence_dec.x +++ b/xls/modules/zstd/sequence_dec.x @@ -495,6 +495,13 @@ pub proc SequenceDecoderCtrl< let (tok_recv_scd, conf_resp) = recv(tok_send_scd, scd_resp_r); trace_fmt!("[SequenceDecoderCtrl]: Received decoded Sequence header: {:#x}", conf_resp); + let zero_sequences = (conf_resp.header.sequence_count == u17:0); + if !zero_sequences { + assert!(conf_resp.header.literals_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); + assert!(conf_resp.header.match_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); + assert!(conf_resp.header.offset_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); + } else {}; + // Request decoding lookups let flc_req = FseLookupCtrlReq { addr: req.start_addr + conf_resp.length as Addr, @@ -503,7 +510,6 @@ pub proc SequenceDecoderCtrl< of: (conf_resp.header.offset_mode == CompressionMode::COMPRESSED), }; - let zero_sequences = (conf_resp.header.sequence_count == u17:0); let tok_send_ctrl = send_if(tok_recv_scd, flc_req_s, !zero_sequences, flc_req); if !zero_sequences { trace_fmt!("[SequenceDecoderCtrl]: Sent FseLookupCtrl request: {:#x}", flc_req); @@ -1155,7 +1161,13 @@ const TEST_RAM_DATA = u64[40]:[ u64:0x0, ... ]; -const EXPECTED_OUTPUT = SequenceExecutorPacket[16]:[ +const EXPECTED_OUTPUT = SequenceExecutorPacket[20]:[ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, length: u64:0x0003, @@ -1174,12 +1186,24 @@ const EXPECTED_OUTPUT = SequenceExecutorPacket[16]:[ content: u64:0x0389, last: false, }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, length: u64:0x0003, content: u64:0x013c, last: false, }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, length: u64:0x0003, @@ -1246,6 +1270,12 @@ const EXPECTED_OUTPUT = SequenceExecutorPacket[16]:[ content: u64:0x03a9, last: false, }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, SequenceExecutorPacket { msg_type: SequenceExecutorMessageType::SEQUENCE, length: u64:0x0004, diff --git a/xls/modules/zstd/sequence_executor.x b/xls/modules/zstd/sequence_executor.x index cab106b244..861783ce8d 100644 --- a/xls/modules/zstd/sequence_executor.x +++ b/xls/modules/zstd/sequence_executor.x @@ -135,50 +135,40 @@ pub fn handle_repeated_offset_for_sequences -> (SequenceExecutorPacket, Offset[3]) { type Packet = SequenceExecutorPacket; type Content = uN[RAM_DATA_WIDTH * u32:8]; - let modified_repeat_offsets = if repeat_req { - Offset[3]:[repeat_offsets[1], repeat_offsets[2], repeat_offsets[0] - Offset:1] - } else { - repeat_offsets - }; - let (seq, final_repeat_offsets) = if seq.content == Content:0 { - fail!( - "match_offset_zero_not_allowed", - (zero!(), Offset[3]:[Offset:0, ...])) - } else if seq.content == Content:1 { - let offset = modified_repeat_offsets[0]; - ( - Packet { content: offset as Content, ..seq }, - Offset[3]:[ - offset, repeat_offsets[1], repeat_offsets[2], - ], - ) - } else if seq.content == CopyOrMatchContent:2 { - let offset = modified_repeat_offsets[1]; - ( - Packet { content: offset as Content, ..seq }, - Offset[3]:[ - offset, repeat_offsets[0], repeat_offsets[2], - ], - ) - } else if seq.content == CopyOrMatchContent:3 { - let offset = modified_repeat_offsets[2]; - ( - Packet { content: offset as Content, ..seq }, - Offset[3]:[ - offset, repeat_offsets[0], repeat_offsets[1], - ], - ) + let (offset, repeat_offsets) = if (seq.content <= Content:3) { + let idx = (seq.content - Content:1) as u32; + let idx = if (repeat_req) { + idx + u32:1 + } else { idx }; + + if (idx == u32:0) { + (repeat_offsets[0], repeat_offsets) + } else { + let offset = if idx < u32:3 { repeat_offsets[idx] } else { repeat_offsets[0] - Offset:1 }; + + let repeat_offsets = if idx > u32:1 { + update(repeat_offsets, u32:2, repeat_offsets[1]) + } else {repeat_offsets}; + let repeat_offsets = update(repeat_offsets, u32:1, repeat_offsets[0]); + let repeat_offsets = update(repeat_offsets, u32:0, offset); + + (offset, repeat_offsets) + } } else { - let offset = seq.content as Offset - Offset:3; - ( - Packet { content: offset as Content, ..seq }, - Offset[3]:[ - offset, repeat_offsets[0], repeat_offsets[1], - ], - ) + let offset = (seq.content - Content:3) as Offset; + + let repeat_offsets = update(repeat_offsets, u32:2, repeat_offsets[1]); + let repeat_offsets = update(repeat_offsets, u32:1, repeat_offsets[0]); + let repeat_offsets = update(repeat_offsets, u32:0, offset); + + (offset, repeat_offsets) }; - (seq, final_repeat_offsets) + + ( + Packet { content: offset as Content, ..seq }, + repeat_offsets, + ) } pub proc SequenceExecutor()); + if input_packet_valid { + trace_fmt!("[SequenceExecutor]: received input: {:#x}", input_packet); + } else {}; // ... or our own sequences from the looped channel let do_recv_ram = ( @@ -351,6 +344,9 @@ pub proc SequenceExecutor(packet); - if do_write_output { trace_fmt!("Sending output MemWriter data: {:#x}", output_mem_wr_data_in); } else { }; + if do_write_output { + trace_fmt!("*** Sending output MemWriter data: {:#x}", output_mem_wr_data_in); + } else { }; let tok2_10_1 = send_if(tok1, output_mem_wr_data_in_s, do_write_output, output_mem_wr_data_in); // Ask for response @@ -1040,64 +1038,196 @@ proc SequenceExecutorSequenceTest { next(state: ()) { let tok = join(); - // Print RAM content - // let tok = send(tok, print_start_s, ()); - // let (tok, _) = recv(tok, print_finish_r); + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 0 -----------------------"); let tok = send(tok, input_s, SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: CopyOrMatchLength:1, - content: CopyOrMatchContent:0x31, - last: false + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x2, + content: CopyOrMatchContent:0xcf95, + last: false, }); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(recv_data, TestMemWriterDataPacket { - data: uN[TEST_DATA_W]:0x31, - length: uN[TEST_ADDR_W]:1, - last: false + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 1 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x4, + content: CopyOrMatchContent:0x5, + last: false, }); let tok = send(tok, print_start_s, ()); let (tok, _) = recv(tok, print_finish_r); + trace_fmt!("----------------------- Packet 2 -----------------------"); + let tok = send(tok, input_s, SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: CopyOrMatchLength:3, - content: CopyOrMatchContent:4, - last: false + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x1, + content: CopyOrMatchContent:0xc4, + last: false, }); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(recv_data, TestMemWriterDataPacket { - data: uN[TEST_DATA_W]:0x31, - length: uN[TEST_ADDR_W]:1, - last: false + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 3 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x8, + content: CopyOrMatchContent:0x4, + last: false, }); let tok = send(tok, print_start_s, ()); let (tok, _) = recv(tok, print_finish_r); + trace_fmt!("----------------------- Packet 4 -----------------------"); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(recv_data, TestMemWriterDataPacket { - data: uN[TEST_DATA_W]:0x3131, - length: uN[TEST_ADDR_W]:2, - last: false + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x1, + content: CopyOrMatchContent:0x93, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 5 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x7, + content: CopyOrMatchContent:0x2, + last: false, }); let tok = send(tok, print_start_s, ()); let (tok, _) = recv(tok, print_finish_r); + trace_fmt!("----------------------- Packet 6 -----------------------"); + let tok = send(tok, input_s, SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: CopyOrMatchLength:3, - content: CopyOrMatchContent:7, - last: false + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x2, + content: CopyOrMatchContent:0x89ac, + last: false, }); - let (tok, recv_data) = recv(tok, output_mem_wr_data_in_r); - assert_eq(recv_data, TestMemWriterDataPacket { - data: uN[TEST_DATA_W]:0x313131, - length: uN[TEST_ADDR_W]:3, - last: false + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 7 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x5, + content: CopyOrMatchContent:0xc, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 8 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x0, + content: CopyOrMatchContent:0x0, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 9 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x8, + content: CopyOrMatchContent:0xe, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 10 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x0, + content: CopyOrMatchContent:0x0, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 11 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x5, + content: CopyOrMatchContent:0x2, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 12 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x8, + content: CopyOrMatchContent:0x95a6_e608_e17d_50b9, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 13 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x3, + content: CopyOrMatchContent:0x32, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 14 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, // u1:0, + length: CopyOrMatchLength:0x0, + content: CopyOrMatchContent:0x0, + last: false, + }); + + let tok = send(tok, print_start_s, ()); + let (tok, _) = recv(tok, print_finish_r); + + trace_fmt!("----------------------- Packet 15 -----------------------"); + + let tok = send(tok, input_s, SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, // u1:1, + length: CopyOrMatchLength:0x1a, + content: CopyOrMatchContent:0x3, + last: true }); let tok = send(tok, print_start_s, ()); diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index f88227e88e..ba1c3f961c 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -489,8 +489,6 @@ proc ZstdDecoderInternal< block_addr + block_length }; - trace_fmt!("bh_addr: {:#x}", bh_addr); - (block_addr, block_length, bh_resp.header.last, block_rle_symbol, bh_addr) } else { (state.block_addr, state.block_length, state.block_last, state.block_rle_symbol, state.bh_addr) @@ -595,8 +593,8 @@ proc ZstdDecoderInternal< ( _, _, _) => Fsm::DECODE_COMPRESSED_BLOCK, }; - let req_sent = if !raw_resp_valid && !error { true } else { false }; - let block_id = if raw_resp_valid { state.block_id + u32:1} else {state.block_id }; + let req_sent = if !cmp_resp_valid && !error { true } else { false }; + let block_id = if cmp_resp_valid { state.block_id + u32:1} else {state.block_id }; let state = State {fsm, block_id, csr_wr_req, csr_wr_req_valid, req_sent, ..state}; if fsm == Fsm::DECODE_BLOCK_HEADER { @@ -630,7 +628,7 @@ proc ZstdDecoderInternal< }, Fsm::FINISH => { - // trace_fmt!("[FINISH]"); + trace_fmt!("[FINISH]"); let csr_wr_req_valid = true; let csr_wr_req = CsrWrReq { csr: csr(Csr::STATUS), @@ -1051,11 +1049,6 @@ pub proc ZstdDecoder< type LitBufRamWrReq = ram::WriteReq; type LitBufRamWrResp = ram::WriteResp; - // Complex Block Decoder - cmp_output_s: chan out; - comp_block_req_s: chan out; - comp_block_resp_r: chan in; - init {} config( @@ -1384,12 +1377,10 @@ pub proc ZstdDecoder< // fse_dec_axi_ar_s, fse_dec_axi_r_r, // ); - (cmd_output_s, comp_block_req_s, comp_block_resp_r) + () } - next (state: ()) { - send_if(join(), cmp_output_s, false, zero!()); - } + next (state: ()) { } } const INST_AXI_DATA_W = u32:64; diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index e73e2edffa..70c1969973 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -763,6 +763,7 @@ proc ZstdDecoderTest { assert_eq(final_transfered_bytes, DECOMPRESSED_BYTES); assert_eq(final_output_memory_id, decomp_frame.array_length); for (memory_id, _): (u32, ()) in range(u32:0, decomp_frame.array_length) { + trace_fmt!("Comparing {} output packet: {:#x} ?= {:#x}", memory_id, final_output_memory[memory_id], decomp_frame.data[memory_id]); assert_eq(final_output_memory[memory_id], decomp_frame.data[memory_id]); }(()); From bb02038fd48c1d1c0a938b4ca548f96ef8a99dee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Wed, 8 Jan 2025 16:03:30 +0100 Subject: [PATCH 54/85] Add support for Compressed FSE tables Internal-tag: [#71197] --- xls/modules/zstd/BUILD | 9 +- xls/modules/zstd/comp_block_dec.x | 43 +- xls/modules/zstd/fse_lookup_dec.x | 951 ++++++++++++++++++++-- xls/modules/zstd/fse_table_creator.x | 192 +++-- xls/modules/zstd/ram_demux.x | 48 +- xls/modules/zstd/ram_demux3.x | 4 +- xls/modules/zstd/refilling_shift_buffer.x | 4 +- xls/modules/zstd/sequence_dec.x | 918 +++++++++++++-------- xls/modules/zstd/zstd_dec.x | 35 +- xls/modules/zstd/zstd_dec_test.x | 30 +- 10 files changed, 1749 insertions(+), 485 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 3616a980ad..d8f9a033ff 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1238,6 +1238,7 @@ xls_dslx_library( xls_dslx_test( name = "comp_block_dec_dslx_test", library = ":comp_block_dec_dslx", + size = "large", tags = ["manual"], ) @@ -1471,7 +1472,7 @@ xls_dslx_verilog( library = ":fse_table_creator_dslx", opt_ir_args = { "inline_procs": "true", - "top": "__fse_table_creator__FseTableCreatorInst__FseTableCreator_0__8_16_1_8_32_4_8_16_1_next", + "top": "__fse_table_creator__FseTableCreatorInst__FseTableCreator_0__8_16_1_9_32_1_9_8_1_8_16_1_next", }, verilog_file = "fse_table_creator.v", tags = ["manual"], @@ -1651,7 +1652,7 @@ xls_dslx_verilog( library = ":ram_demux_dslx", opt_ir_args = { "inline_procs": "true", - "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_8_5_next", + "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_0_8_5_next", }, verilog_file = "ram_demux.v", tags = ["manual"], @@ -1661,7 +1662,7 @@ xls_benchmark_ir( name = "ram_demux_opt_ir_benchmark", src = "ram_demux_verilog.opt.ir", benchmark_ir_args = { - "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_8_5_next", + "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_0_8_5_next", }, codegen_args = { "pipeline_stages": "10", @@ -2014,7 +2015,7 @@ xls_dslx_verilog( "multi_proc": "true", }, opt_ir_args = { - "top": "__sequence_dec__FseLookupCtrlInst__FseLookupCtrl_0__32_next" + "top": "__sequence_dec__FseLookupCtrlInst__FseLookupCtrl_0_next" }, dslx_top = "FseLookupCtrlInst", library = ":sequence_dec_dslx", diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index 94a3912ed6..276a54cd03 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -58,6 +58,7 @@ pub proc CompressBlockDecoder< // FSE lookup table RAMs DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, // for literals decoder @@ -108,6 +109,11 @@ pub proc CompressBlockDecoder< type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; @@ -180,6 +186,11 @@ pub proc CompressBlockDecoder< tmp_wr_req_s: chan out, tmp_wr_resp_r: chan in, + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + ll_def_fse_rd_req_s: chan out, ll_def_fse_rd_resp_r: chan in, ll_def_fse_wr_req_s: chan out, @@ -330,6 +341,7 @@ pub proc CompressBlockDecoder< AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_ADDR_W, TMP2_RAM_DATA_W, TMP2_RAM_NUM_PARTITIONS, FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, >( scd_axi_ar_s, scd_axi_r_r, @@ -339,6 +351,7 @@ pub proc CompressBlockDecoder< seq_dec_command_s, dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, @@ -436,9 +449,9 @@ const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); const TEST_FSE_RAM_DATA_W = u32:32; -const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); -const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W; const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); @@ -449,6 +462,12 @@ const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); +const TEST_TMP2_RAM_DATA_W = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_W = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_W; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_W); + const TEST_RAM_SIM_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; const TEST_RAM_INITIALIZED = true; @@ -483,7 +502,7 @@ const COMP_BLOCK_DEC_TESTCASES: (u32, u64[64], u32, ExtendedPacket[128])[7] = [ // raw literals (18) + sequences with 3 predefined tables (2) // // last block generated with: - // ./decodecorpus -pdata2.out -odata2.in -s7110 --block-type=2 --content-size iliteral-type=0 --max-block-size-log=5 + // ./decodecorpus -pdata2.out -odata2.in -s7110 --block-type=2 --content-size --literal-type=0 --max-block-size-log=5 u32:0x1C, u64[64]:[ u64:0x0, u64:0x0, // 0x000 @@ -1022,6 +1041,11 @@ proc CompressBlockDecoderTest { type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; @@ -1159,6 +1183,17 @@ proc CompressBlockDecoderTest { tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, ); + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_SIZE, TEST_TMP2_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED + >( + tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s, + ); + // FSE RAMs let (fse_rd_req_s, fse_rd_req_r) = chan[u32:6]("tmp_rd_req"); let (fse_rd_resp_s, fse_rd_resp_r) = chan[u32:6]("tmp_rd_resp"); @@ -1253,6 +1288,7 @@ proc CompressBlockDecoderTest { // FSE lookup table RAMs TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_ADDR_W, TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_NUM_PARTITIONS, TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, >( req_r, resp_s, @@ -1262,6 +1298,7 @@ proc CompressBlockDecoderTest { axi_ram_ar_s[2], axi_ram_r_r[2], dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, fse_rd_req_s[1], fse_rd_resp_r[1], fse_wr_req_s[1], fse_wr_resp_r[1], ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, diff --git a/xls/modules/zstd/fse_lookup_dec.x b/xls/modules/zstd/fse_lookup_dec.x index 5c2fa5ec80..7518c0d2bc 100644 --- a/xls/modules/zstd/fse_lookup_dec.x +++ b/xls/modules/zstd/fse_lookup_dec.x @@ -31,9 +31,7 @@ pub enum FseLookupDecoderStatus: u1 { ERROR = 1, } -pub struct FseLookupDecoderReq { - addr: uN[AXI_ADDR_W] -} +pub struct FseLookupDecoderReq {} pub struct FseLookupDecoderResp { status: FseLookupDecoderStatus, @@ -41,29 +39,24 @@ pub struct FseLookupDecoderResp { } pub proc FseLookupDecoder< - AXI_DATA_W: u32, AXI_ADDR_W: u32, + AXI_DATA_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_ADDR_W: u32, DPD_RAM_NUM_PARTITIONS: u32, TMP_RAM_DATA_W: u32, TMP_RAM_ADDR_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_DATA_W: u32, TMP2_RAM_ADDR_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, FSE_RAM_DATA_W: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_NUM_PARTITIONS: u32, SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, > { - type Req = FseLookupDecoderReq; + type Req = FseLookupDecoderReq; type Resp = FseLookupDecoderResp; type Status = FseLookupDecoderStatus; type FseTableStart = fse_table_creator::FseStartMsg; - type MemReaderReq = mem_reader::MemReaderReq; - type MemReaderResp = mem_reader::MemReaderResp; - type MemReaderStatus = mem_reader::MemReaderStatus; - type DpdRamWrReq = ram::WriteReq; type DpdRamWrResp = ram::WriteResp; type DpdRamRdReq = ram::ReadReq; type DpdRamRdResp = ram::ReadResp; - type FseRamRdReq = ram::ReadReq; - type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; type FseRamWrResp = ram::WriteResp; @@ -72,8 +65,11 @@ pub proc FseLookupDecoder< type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; - type RefillerStartReq = refilling_shift_buffer::RefillStart; - type RefillerError = refilling_shift_buffer::RefillError; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; @@ -84,10 +80,6 @@ pub proc FseLookupDecoder< req_r: chan in; resp_s: chan out; - start_req_s: chan out; - stop_flush_req_s: chan<()> out; - flushing_done_r: chan<()> in; - fse_pf_dec_req_s: chan out; fse_pf_dec_resp_r: chan in; fse_table_start_s: chan out; @@ -99,9 +91,6 @@ pub proc FseLookupDecoder< req_r: chan in, resp_s: chan out, - mem_rd_req_s: chan out, - mem_rd_resp_r: chan in, - dpd_rd_req_s: chan out, dpd_rd_resp_r: chan in, dpd_wr_req_s: chan out, @@ -112,10 +101,16 @@ pub proc FseLookupDecoder< tmp_wr_req_s: chan out, tmp_wr_resp_r: chan in, - fse_rd_req_s: chan out, - fse_rd_resp_r: chan in, + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + fse_wr_req_s: chan out, fse_wr_resp_r: chan in, + + buffer_ctrl_s: chan out, + buffer_data_out_r: chan in, ) { const CHANNEL_DEPTH = u32:1; @@ -126,27 +121,13 @@ pub proc FseLookupDecoder< DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_DATA_W, TMP2_RAM_ADDR_W, TMP2_RAM_NUM_PARTITIONS, >( fse_table_start_r, fse_table_finish_s, dpd_rd_req_s, dpd_rd_resp_r, - fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + fse_wr_req_s, fse_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, - ); - - let (start_req_s, start_req_r) = chan("start_req"); - let (stop_flush_req_s, stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("stop_flush_req"); - let (buffer_ctrl_s, buffer_ctrl_r) = chan("buffer_ctrl"); - let (buffer_data_out_s, buffer_data_out_r) = chan("buffer_data_out"); - let (flushing_done_s, flushing_done_r) = chan<(), CHANNEL_DEPTH>("flushing_done"); - - spawn refilling_shift_buffer::RefillingShiftBuffer( - mem_rd_req_s, - mem_rd_resp_r, - start_req_r, - stop_flush_req_r, - buffer_ctrl_r, - buffer_data_out_s, - flushing_done_s, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, ); let (fse_pf_dec_req_s, fse_pf_dec_req_r) = chan("fse_pf_dec_req"); @@ -162,9 +143,6 @@ pub proc FseLookupDecoder< ( req_r, resp_s, - start_req_s, - stop_flush_req_s, - flushing_done_r, fse_pf_dec_req_s, fse_pf_dec_resp_r, fse_table_start_s, fse_table_finish_r, ) @@ -174,29 +152,22 @@ pub proc FseLookupDecoder< let tok = join(); let (tok, start_req) = recv(tok, req_r); - // start refilling shift buffer - let tok_dec_pf1 = send(tok, start_req_s, RefillerStartReq { - start_addr: start_req.addr - }); // start FSE probability frequency decoder - let tok_dec_pf2 = send(tok, fse_pf_dec_req_s, FsePFDecReq {}); + let tok = send(tok, fse_pf_dec_req_s, FsePFDecReq {}); // wait for completion from FSE probability frequency decoder - let tok = join(tok_dec_pf1, tok_dec_pf2); - let (tok_dec_resp, pf_dec_res) = recv(tok, fse_pf_dec_resp_r); - - // flush refilling shift buffer (regardless of any errors) - let tok_flush = send(tok_dec_resp, stop_flush_req_s, ()); - recv(tok_flush, flushing_done_r); + let (tok, pf_dec_res) = recv(tok, fse_pf_dec_resp_r); + trace_fmt!("FSE prob decoded"); let pf_dec_ok = pf_dec_res.status == FsePFDecStatus::OK; // run FSE Table creation conditional or previous processing succeeding - let tok = send_if(tok_dec_resp, fse_table_start_s, pf_dec_ok, FseTableStart { + let tok = send_if(tok, fse_table_start_s, pf_dec_ok, FseTableStart { num_symbs: pf_dec_res.symbol_count, accuracy_log: pf_dec_res.accuracy_log, }); // wait for completion from FSE table creator let (tok, ()) = recv_if(tok, fse_table_finish_r, pf_dec_ok, ()); + trace_fmt!("FSE table created"); let resp = if pf_dec_ok { Resp { status: Status::OK, accuracy_log: pf_dec_res.accuracy_log } @@ -212,6 +183,7 @@ const TEST_AXI_DATA_WIDTH = u32:64; const TEST_AXI_ADDR_WIDTH = u32:32; const TEST_AXI_ID_WIDTH = u32:8; const TEST_AXI_DEST_WIDTH = u32:8; +const TEST_SB_LENGTH_WIDTH = refilling_shift_buffer::length_width(TEST_AXI_DATA_WIDTH); const TEST_CASE_RAM_DATA_WIDTH = u32:64; const TEST_CASE_RAM_SIZE = u32:256; @@ -229,9 +201,9 @@ const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_WIDTH); const TEST_FSE_RAM_DATA_WIDTH = u32:32; -const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; const TEST_FSE_RAM_ADDR_WIDTH = std::clog2(TEST_FSE_RAM_SIZE); -const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH / u32:3; +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH; const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_WIDTH); @@ -242,12 +214,19 @@ const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_WIDTH; const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_WIDTH); +const TEST_TMP2_RAM_DATA_WIDTH = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_WIDTH = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_WIDTH; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_WIDTH); + const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; const TEST_RAM_INITIALIZED = true; type FseTableRecord = common::FseTableRecord; -const FSE_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], FseLookupDecoderResp)[10] = [ +const FSE_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], FseLookupDecoderResp)[12] = [ ( u64[64]:[u64:0x72AAAAABBB1D25C0, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ @@ -862,11 +841,792 @@ const FSE_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], ], FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } ), + ( + u64[64]:[u64:0x604FC0502602814, u64:0xE030505040131FF6, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1fc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1fc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1fc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1fc }, + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:9 } + ), + ( + u64[64]:[u64:0x140FE03050504013, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, + zero!(), ... + ], + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:8 } + ), ]; #[test_proc] proc FseLookupDecoderTest { - type Req = FseLookupDecoderReq; + type Req = FseLookupDecoderReq; type Resp = FseLookupDecoderResp; type Status = FseLookupDecoderStatus; @@ -888,11 +1648,20 @@ proc FseLookupDecoderTest { type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type TestcaseRamRdReq = ram::ReadReq; type TestcaseRamRdResp = ram::ReadResp; type TestcaseRamWrReq = ram::WriteReq; type TestcaseRamWrResp = ram::WriteResp; + type RefillStartReq = refilling_shift_buffer::RefillStart; + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type AxiR = axi::AxiR; type AxiAr = axi::AxiAr; @@ -905,6 +1674,9 @@ proc FseLookupDecoderTest { fse_wr_resp_r: chan in; testcase_wr_req_s: chan out; testcase_wr_resp_r: chan in; + refill_req_s: chan out; + stop_flush_req_s: chan<()> out; + flushing_done_r: chan<()> in; config(terminator: chan out) { let (req_s, req_r) = chan("req"); @@ -922,6 +1694,11 @@ proc FseLookupDecoderTest { let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); @@ -932,28 +1709,22 @@ proc FseLookupDecoderTest { let (testcase_wr_req_s, testcase_wr_req_r) = chan("testcase_wr_req"); let (testcase_wr_resp_s, testcase_wr_resp_r) = chan("testcase_wr_resp"); + let (buffer_ctrl_s, buffer_ctrl_r) = chan("buffer_ctrl"); + let (buffer_data_out_s, buffer_data_out_r) = chan("buffer_data_out"); + spawn FseLookupDecoder< - TEST_AXI_DATA_WIDTH, TEST_AXI_ADDR_WIDTH, + TEST_AXI_DATA_WIDTH, TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_ADDR_WIDTH, TEST_TMP2_RAM_NUM_PARTITIONS, TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, >( - req_r, - resp_s, - mem_rd_req_s, - mem_rd_resp_r, - dpd_rd_req_s, - dpd_rd_resp_r, - dpd_wr_req_s, - dpd_wr_resp_r, - tmp_rd_req_s, - tmp_rd_resp_r, - tmp_wr_req_s, - tmp_wr_resp_r, - fse_rd_req_s, - fse_rd_resp_r, - fse_wr_req_s, - fse_wr_resp_r, + req_r, resp_s, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_wr_req_s, fse_wr_resp_r, + buffer_ctrl_s, buffer_data_out_r, ); spawn ram::RamModel< @@ -971,6 +1742,11 @@ proc FseLookupDecoderTest { TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, >(tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_SIZE, TEST_TMP2_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s); + spawn ram::RamModel< TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, @@ -989,9 +1765,21 @@ proc FseLookupDecoderTest { TEST_AXI_DATA_WIDTH, TEST_AXI_ADDR_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH >(mem_rd_req_r, mem_rd_resp_s, testcase_axi_ar_s, testcase_axi_r_r); + let (refill_req_s, refill_req_r) = chan("start_req"); + let (stop_flush_req_s, stop_flush_req_r) = chan<()>("stop_flush_req"); + let (flushing_done_s, flushing_done_r) = chan<()>("flushing_done"); + + spawn refilling_shift_buffer::RefillingShiftBuffer( + mem_rd_req_s, mem_rd_resp_r, + refill_req_r, stop_flush_req_r, + buffer_ctrl_r, buffer_data_out_s, + flushing_done_s, + ); + ( terminator, req_s, resp_r, fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, testcase_wr_req_s, testcase_wr_resp_r, + refill_req_s, stop_flush_req_s, flushing_done_r, ) } @@ -1000,7 +1788,7 @@ proc FseLookupDecoderTest { next(_: ()) { let tok = join(); // This has to be outside of unroll_for!, otherwise typechecker reports type mismatch on identical types - let req_start = Req { addr: uN[TEST_AXI_ADDR_WIDTH]:0x0 }; + let req_start = Req {}; let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(FSE_LOOKUP_DECODER_TESTCASES)) { let (input, output, resp_ok) = FSE_LOOKUP_DECODER_TESTCASES[test_i]; @@ -1018,6 +1806,9 @@ proc FseLookupDecoderTest { }(tok); trace_fmt!("Running FSE lookup decoder on testcase {:x}", test_i); + let tok = send(tok, refill_req_s, RefillStartReq { + start_addr: uN[TEST_AXI_ADDR_WIDTH]:0x0 + }); let tok = send(tok, req_s, req_start); let (tok, resp) = recv(tok, resp_r); assert_eq(resp, resp_ok); @@ -1025,7 +1816,7 @@ proc FseLookupDecoderTest { let tok = for ((i, output_data), tok): ((u32, FseTableRecord), token) in enumerate(output) { let req = FseRamRdReq { addr: i as uN[TEST_FSE_RAM_ADDR_WIDTH], - mask: uN[TEST_FSE_RAM_NUM_PARTITIONS]:0x7, + mask: std::unsigned_max_value(), }; let tok = send(tok, fse_rd_req_s, req); let (tok, resp) = recv(tok, fse_rd_resp_r); @@ -1034,13 +1825,17 @@ proc FseLookupDecoderTest { // erase output for next test to start with clean memory let clear_req = FseRamWrReq { addr: i as uN[TEST_FSE_RAM_ADDR_WIDTH], - mask: uN[TEST_FSE_RAM_NUM_PARTITIONS]:0x7, + mask: std::unsigned_max_value(), data: uN[TEST_FSE_RAM_DATA_WIDTH]:0x0, }; let tok = send(tok, fse_wr_req_s, clear_req); let (tok, _) = recv(tok, fse_wr_resp_r); tok }(tok); + + let tok = send(tok, stop_flush_req_s, ()); + let (tok, ()) = recv(tok, flushing_done_r); + tok }(tok); diff --git a/xls/modules/zstd/fse_table_creator.x b/xls/modules/zstd/fse_table_creator.x index 3eca396d90..2537f13948 100644 --- a/xls/modules/zstd/fse_table_creator.x +++ b/xls/modules/zstd/fse_table_creator.x @@ -44,7 +44,7 @@ enum Status : u4 { struct FseTableCreatorState { status: Status, req: bool, - idx: u8, + idx: u10, // TODO: num_symbs is u8, possibly other fields as well num_symbs: u8, curr_symbol: u8, @@ -94,6 +94,7 @@ pub proc FseTableCreator< FSE_RAM_DATA_WIDTH: u32, FSE_RAM_ADDR_WIDTH: u32, FSE_RAM_NUM_PARTITIONS: u32, // Temp RAM parameters TMP_RAM_DATA_WIDTH: u32, TMP_RAM_ADDR_WIDTH: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_DATA_WIDTH: u32, TMP2_RAM_ADDR_WIDTH: u32, TMP2_RAM_NUM_PARTITIONS: u32, > { type State = FseTableCreatorState; @@ -102,14 +103,19 @@ pub proc FseTableCreator< type FseRamWriteReq = ram::WriteReq; type FseRamWriteResp = ram::WriteResp; - type FseRamReadReq = ram::ReadReq; - type FseRamReadResp = ram::ReadResp; type TmpRamWriteReq = ram::WriteReq; type TmpRamWriteResp = ram::WriteResp; type TmpRamReadReq = ram::ReadReq; type TmpRamReadResp = ram::ReadResp; + type Tmp2RamWriteReq = ram::WriteReq; + type Tmp2RamWriteResp = ram::WriteResp; + type Tmp2RamReadReq = ram::ReadReq; + type Tmp2RamReadResp = ram::ReadResp; + + type TestRamWriteResp = ram::WriteResp; + type IterCtrl = common::FseTableCreatorCtrl; type IterIndex = common::FseTableIndex; @@ -121,8 +127,6 @@ pub proc FseTableCreator< // a response with information that the table has been saved to RAM fse_table_finish_s: chan<()> out; - fse_rd_req_s: chan out; - fse_rd_resp_r: chan in; fse_wr_req_s: chan out; fse_wr_resp_r: chan in; @@ -131,6 +135,11 @@ pub proc FseTableCreator< tmp_wr_req_s: chan out; tmp_wr_resp_r: chan in; + tmp2_rd_req_s: chan out; + tmp2_rd_resp_r: chan in; + tmp2_wr_req_s: chan out; + tmp2_wr_resp_r: chan in; + it_ctrl_s: chan out; it_index_r: chan in; @@ -143,15 +152,18 @@ pub proc FseTableCreator< dpd_rd_resp_r: chan in, // Ram with FSE decoding table - fse_rd_req_s: chan out, - fse_rd_resp_r: chan in, fse_wr_req_s: chan out, fse_wr_resp_r: chan in, tmp_rd_req_s: chan out, tmp_rd_resp_r: chan in, tmp_wr_req_s: chan out, - tmp_wr_resp_r: chan in + tmp_wr_resp_r: chan in, + + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, ) { let (it_ctrl_s, it_ctrl_r) = chan("it_ctrl"); let (it_index_s, it_index_r) = chan("it_index"); @@ -160,8 +172,9 @@ pub proc FseTableCreator< ( dpd_rd_req_s, dpd_rd_resp_r, fse_table_start_r, fse_table_finish_s, - fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + fse_wr_req_s, fse_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, it_ctrl_s, it_index_r ) } @@ -173,15 +186,7 @@ pub proc FseTableCreator< const FSE_RAM_REQ_MASK_ALL = std::unsigned_max_value(); const FSE_RAM_REQ_MASK_SYMBOL = uN[FSE_RAM_NUM_PARTITIONS]:1; const TMP_RAM_REQ_MASK_ALL = std::unsigned_max_value(); - - // Type definitions repeated because of https://github.com/google/xls/issues/1368 - type DpdRamReadReq = ram::ReadReq; - type FseRamWriteReq = ram::WriteReq; - type FseRamWriteResp = ram::WriteResp; - type FseRamReadReq = ram::ReadReq; - type TmpRamWriteReq = ram::WriteReq; - type TestRamWriteResp = ram::WriteResp; - type TmpRamReadReq = ram::ReadReq; + const TMP2_RAM_REQ_MASK_ALL = std::unsigned_max_value(); let tok0 = join(); @@ -193,9 +198,14 @@ pub proc FseTableCreator< state.status == Status::HANDLE_POSITIVE_PROB; let send_dpd_req = get_dpd_data && state.req; + let addr = if send_dpd_req { + checked_cast(state.idx) + } else { + uN[DPD_RAM_ADDR_WIDTH]:0 + }; let tok_dpd_req = send_if(tok0, dpd_rd_req_s, send_dpd_req, DpdRamReadReq { - addr: checked_cast(state.idx), + addr: addr, mask: DPD_RAM_REQ_MASK_ALL }); let get_dpd_resp = get_dpd_data && !state.req; @@ -203,37 +213,41 @@ pub proc FseTableCreator< let handle_negative_prob_req = state.status == Status::HANDLE_NEGATIVE_PROB; let decreased_high_threshold = state.high_threshold - u16:1; - let index_as_symbol_record = FseTableRecord { - symbol: state.idx, - num_of_bits: u8:0, - base: u16:0 - }; - let fse_record_as_bits = fse_record_to_bits(index_as_symbol_record); let fse_wr_req = if handle_negative_prob_req { - FseRamWriteReq { - addr: checked_cast(decreased_high_threshold), - data: checked_cast(fse_record_as_bits), - mask: FSE_RAM_REQ_MASK_SYMBOL + Tmp2RamWriteReq { + addr: checked_cast(decreased_high_threshold), + data: checked_cast(state.idx), + mask: TMP2_RAM_REQ_MASK_ALL, } } else { - zero!() + zero!() }; - let tok3 = send_if(tok0, fse_wr_req_s, handle_negative_prob_req, fse_wr_req); + let tok3 = send_if(tok0, tmp2_wr_req_s, handle_negative_prob_req, fse_wr_req); let handle_negative_prob_resp = (state.status == Status::HANDLE_NEGATIVE_PROB); - let (tok3, _) = recv_if(tok3, fse_wr_resp_r, handle_negative_prob_resp, FseRamWriteResp {}); + let (tok3, _) = recv_if(tok3, tmp2_wr_resp_r, handle_negative_prob_resp, FseRamWriteResp {}); + let addr = if handle_negative_prob_req { + checked_cast(state.idx) + } else { + uN[TMP_RAM_ADDR_WIDTH]:0 + }; let tok5 = send_if(tok0, tmp_wr_req_s, handle_negative_prob_req, TmpRamWriteReq { - addr: checked_cast(state.idx), + addr: addr, data: checked_cast(u16:1), mask: TMP_RAM_REQ_MASK_ALL }); let (tok5, _) = recv_if(tok5, tmp_wr_resp_r, handle_negative_prob_resp, TestRamWriteResp {}); let handle_positive_prob_write_state_desc = (state.status == Status::HANDLE_POSITIVE_PROB_WRITE_STATE_DESC); + let addr = if handle_positive_prob_write_state_desc { + checked_cast(state.idx) + } else { + uN[TMP_RAM_ADDR_WIDTH]:0 + }; let tok6 = send_if(tok0, tmp_wr_req_s, handle_positive_prob_write_state_desc, TmpRamWriteReq { - addr: checked_cast(state.idx), + addr: addr, data: checked_cast(state.dpd_data), mask: TMP_RAM_REQ_MASK_ALL } @@ -252,25 +266,30 @@ pub proc FseTableCreator< let (_, pos) = recv_if(tok0, it_index_r, inner_for_get_pos, zero!()); let inner_for_write_sym = state.status == Status::INNER_FOR_WRITE_SYM; - let tok4 = send_if( tok0, fse_wr_req_s, inner_for_write_sym, - FseRamWriteReq { - addr: checked_cast(state.pos), - data: checked_cast(fse_record_as_bits), - mask: FSE_RAM_REQ_MASK_SYMBOL + let idx = if inner_for_write_sym { + checked_cast(state.idx) + } else { + uN[TMP2_RAM_DATA_WIDTH]:0 + }; + let tok4 = send_if( tok0, tmp2_wr_req_s, inner_for_write_sym, + Tmp2RamWriteReq { + addr: checked_cast(state.pos), + data: idx, + mask: TMP2_RAM_REQ_MASK_ALL, } ); - let (tok4, _) = recv_if(tok4, fse_wr_resp_r, inner_for_write_sym, FseRamWriteResp {}); + let (tok4, _) = recv_if(tok4, tmp2_wr_resp_r, inner_for_write_sym, FseRamWriteResp {}); let last_for = state.status == Status::LAST_FOR; - let tok8 = send_if(tok0, fse_rd_req_s, last_for, - FseRamReadReq { - addr: checked_cast(state.idx), - mask: FSE_RAM_REQ_MASK_SYMBOL + let tok8 = send_if(tok0, tmp2_rd_req_s, last_for, + Tmp2RamReadReq { + addr: checked_cast(state.idx), + mask: TMP2_RAM_REQ_MASK_ALL, } ); - let (tok8, fse_resp) = recv_if(tok8, fse_rd_resp_r, last_for, zero!()); - let fse_record = bits_to_fse_record(fse_resp.data); + let (tok8, fse_resp) = recv_if(tok8, tmp2_rd_resp_r, last_for, zero!()); + let fse_record_symbol = fse_resp.data; let get_state_desc = state.status == Status::GET_STATE_DESC; let symbol = state.curr_symbol; @@ -314,7 +333,7 @@ pub proc FseTableCreator< let send_finish = state.status == Status::SEND_FINISH; let tok11 = send_if(tok0, fse_table_finish_s, send_finish, ()); - trace_fmt!("fse lookup state: {:#x}", state); + // trace_fmt!("fse lookup state: {:#x}", state); if state.req && ( state.status == Status::TEST_NEGATIVE_PROB || @@ -337,21 +356,21 @@ pub proc FseTableCreator< if dpd_resp.data == s16:-1 as u16 { State { status: Status::HANDLE_NEGATIVE_PROB, ..state } } else { - let next_idx = state.idx + u8:1; - if next_idx < state.num_symbs { + let next_idx = state.idx + u10:1; + if next_idx < checked_cast(state.num_symbs) { State { status: Status::TEST_NEGATIVE_PROB, req: true, idx: next_idx, ..state } } else { - State { status: Status::START_ITERATING_POS, req: true, idx: u8:0, ..state } + State { status: Status::START_ITERATING_POS, req: true, idx: u10:0, ..state } } } }, Status::HANDLE_NEGATIVE_PROB => { // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2143-L2146 - let next_idx = state.idx + u8:1; - if next_idx < state.num_symbs { + let next_idx = state.idx + u10:1; + if next_idx < checked_cast(state.num_symbs) { State { status: Status::TEST_NEGATIVE_PROB, req: true, idx: next_idx, high_threshold: decreased_high_threshold, ..state } } else { - State { status: Status::START_ITERATING_POS, req: true, idx: u8:0, high_threshold: decreased_high_threshold, ..state } + State { status: Status::START_ITERATING_POS, req: true, idx: u10:0, high_threshold: decreased_high_threshold, ..state } } }, Status::START_ITERATING_POS => { @@ -361,11 +380,11 @@ pub proc FseTableCreator< if dpd_resp.data as s16 > s16:0 { State { status: Status::HANDLE_POSITIVE_PROB, req: true, ..state } } else { - let next_idx = state.idx + u8:1; - if next_idx < state.num_symbs { + let next_idx = state.idx + u10:1; + if next_idx < checked_cast(state.num_symbs) { State { status: Status::TEST_POSITIVE_PROB, req: true, idx: next_idx, ..state } } else { - State { status: Status::LAST_FOR, idx: u8:0, ..state } + State { status: Status::LAST_FOR, idx: u10:0, ..state } } } }, @@ -386,24 +405,24 @@ pub proc FseTableCreator< State { status: Status::INNER_FOR_GET_POS, inner_for_idx: next_idx, ..state } } else { assert!(pos == IterIndex:0, "corruption_detected_while_decompressing"); - let next_idx = state.idx + u8:1; - if next_idx < state.num_symbs { + let next_idx = state.idx + u10:1; + if next_idx < checked_cast(state.num_symbs) { State { status: Status::TEST_POSITIVE_PROB, req: true, idx: next_idx, ..state } } else { - State { status: Status::LAST_FOR, idx: u8:0, ..state } + State { status: Status::LAST_FOR, idx: u10:0, ..state } } } }, Status::LAST_FOR => { // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2183 - State { status: Status::GET_STATE_DESC, curr_symbol: fse_record.symbol, ..state } + State { status: Status::GET_STATE_DESC, curr_symbol: fse_record_symbol, ..state } }, Status::GET_STATE_DESC => { // https://github.com/facebook/zstd/blob/9f42fa0a043aa389534cf10ff086976c4c6b10a6/doc/educational_decoder/zstd_decompress.c#L2184 State { status: Status::SET_STATE_DESC, state_desc_for_symbol: tmp_resp.data, ..state } }, Status::SET_STATE_DESC => { - let next_idx = state.idx + u8:1; + let next_idx = state.idx + u10:1; if next_idx as u16 < size { State { status: Status::LAST_FOR, idx: next_idx, ..state } } else { @@ -425,9 +444,9 @@ const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_WIDTH); const TEST_FSE_RAM_DATA_WIDTH = u32:32; -const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; const TEST_FSE_RAM_ADDR_WIDTH = std::clog2(TEST_FSE_RAM_SIZE); -const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH / u32:3; +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH; const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_WIDTH); @@ -438,6 +457,13 @@ const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_WIDTH; const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_WIDTH); +const TEST_TMP2_RAM_DATA_WIDTH = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_WIDTH = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_WIDTH; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_WIDTH); + proc FseTableCreatorInst { type DpdRamReadReq = ram::ReadReq; type DpdRamReadResp = ram::ReadResp; @@ -452,6 +478,11 @@ proc FseTableCreatorInst { type TmpRamReadReq = ram::ReadReq; type TmpRamReadResp = ram::ReadResp; + type Tmp2RamWriteReq = ram::WriteReq; + type Tmp2RamWriteResp = ram::WriteResp; + type Tmp2RamReadReq = ram::ReadReq; + type Tmp2RamReadResp = ram::ReadResp; + config( fse_table_start_r: chan in, fse_table_finish_s: chan<()> out, @@ -459,25 +490,30 @@ proc FseTableCreatorInst { dpd_rd_req_s: chan out, dpd_rd_resp_r: chan in, - fse_rd_req_s: chan out, - fse_rd_resp_r: chan in, fse_wr_req_s: chan out, fse_wr_resp_r: chan in, tmp_rd_req_s: chan out, tmp_rd_resp_r: chan in, tmp_wr_req_s: chan out, - tmp_wr_resp_r: chan in + tmp_wr_resp_r: chan in, + + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, ) { spawn FseTableCreator< TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_ADDR_WIDTH, TEST_TMP2_RAM_NUM_PARTITIONS, >( fse_table_start_r, fse_table_finish_s, dpd_rd_req_s, dpd_rd_resp_r, - fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, - tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r + fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s,tmp2_wr_resp_r, ); } @@ -538,6 +574,11 @@ proc FseTableCreatorTest { type TmpRamWriteReq = ram::WriteReq; type TmpRamWriteResp = ram::WriteResp; + type Tmp2RamWriteReq = ram::WriteReq; + type Tmp2RamWriteResp = ram::WriteResp; + type Tmp2RamReadReq = ram::ReadReq; + type Tmp2RamReadResp = ram::ReadResp; + terminator: chan out; fse_table_start_s: chan out; fse_table_finish_r: chan<()> in; @@ -576,6 +617,15 @@ proc FseTableCreatorTest { TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE>( tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_SIZE, TEST_TMP2_RAM_WORD_PARTITION_SIZE>( + tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s); + let (fse_table_start_s, fse_table_start_r) = chan("fse_table_start"); let (fse_table_finish_s, fse_table_finish_r) = chan<()>("fse_table_finish"); @@ -583,11 +633,13 @@ proc FseTableCreatorTest { TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_ADDR_WIDTH, TEST_TMP2_RAM_NUM_PARTITIONS, >( fse_table_start_r, fse_table_finish_s, dpd_rd_req_s, dpd_rd_resp_r, - fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, - tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r + fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r ); ( diff --git a/xls/modules/zstd/ram_demux.x b/xls/modules/zstd/ram_demux.x index 2b188de92b..d7f99ed574 100644 --- a/xls/modules/zstd/ram_demux.x +++ b/xls/modules/zstd/ram_demux.x @@ -38,6 +38,7 @@ pub proc RamDemux< ADDR_WIDTH: u32, DATA_WIDTH: u32, NUM_PARTITIONS: u32, + INSTANCE: u32 = {u32:0}, INIT_SEL: u1 = {u1:0}, QUEUE_LEN: u32 = {u32:5} > { @@ -120,6 +121,7 @@ pub proc RamDemux< // is less or equal to queue length) let (tok1_0, rd_req, rd_req_valid) = recv_non_blocking(tok, rd_req_r, zero!()); let (sel_q_rd_end, sel_q_rd) = if rd_req_valid { + trace_fmt!("[{:x} Received read request: {:#x}", INSTANCE, rd_req); (sel_q_rd_end << u32:1, (sel_q_rd << u32:1) | ((sel as Queue) << u32:1)) } else { (sel_q_rd_end, sel_q_rd) @@ -127,6 +129,7 @@ pub proc RamDemux< let (tok1_1, wr_req, wr_req_valid) = recv_non_blocking(tok, wr_req_r, zero!()); let (sel_q_wr_end, sel_q_wr) = if wr_req_valid { + trace_fmt!("[{:x} Received write request: {:#x}", INSTANCE, wr_req); (sel_q_wr_end << u32:1, (sel_q_wr << u32:1) | ((sel as Queue) << u32:1)) } else { (sel_q_wr_end, sel_q_wr) @@ -135,16 +138,28 @@ pub proc RamDemux< // send requests to output channel 0 let rd_req0_cond = ((sel_q_rd >> u32:1) as u1 == u1:0 && rd_req_valid); let tok1_2 = send_if(tok, rd_req0_s, rd_req0_cond, rd_req); + if rd_req0_cond { + trace_fmt!("[{:x} Sent read request to channel 0: {:#x}", INSTANCE, rd_req); + } else {}; let wr_req0_cond = ((sel_q_wr >> u32:1) as u1 == u1:0 && wr_req_valid); let tok1_3 = send_if(tok, wr_req0_s, wr_req0_cond, wr_req); + if wr_req0_cond { + trace_fmt!("[{:x} Sent write request to channel 0: {:#x}", INSTANCE, wr_req); + } else {}; // send requests to output channel 1 let rd_req1_cond = ((sel_q_rd >> u32:1) as u1 == u1:1 && rd_req_valid); let tok1_4 = send_if(tok, rd_req1_s, rd_req1_cond, rd_req); + if rd_req1_cond { + trace_fmt!("[{:x} Sent read request to channel 1: {:#x}", INSTANCE, rd_req); + } else {}; let wr_req1_cond = ((sel_q_wr >> u32:1) as u1 == u1:1 && wr_req_valid); let tok1_5 = send_if(tok, wr_req1_s, wr_req1_cond, wr_req); + if wr_req1_cond { + trace_fmt!("[{:x} Sent write request to channel 1: {:#x}", INSTANCE, wr_req); + } else {}; // join tokens let tok1 = join(tok1_0, tok1_1, tok1_2, tok1_3, tok1_4, tok1_5); @@ -156,15 +171,28 @@ pub proc RamDemux< // receive responses from output channel 0 let (tok2_0, rd_resp0, rd_resp0_valid) = recv_if_non_blocking(tok1, rd_resp0_r, rd_resp_ch == u1:0, zero!()); + if rd_resp0_valid { + trace_fmt!("[{:x} Received read response on channel 0: {:#x}", INSTANCE, rd_resp0); + } else {}; let (tok2_1, wr_resp0, wr_resp0_valid) = recv_if_non_blocking(tok1, wr_resp0_r, wr_resp_ch == u1:0, zero!()); - + if wr_resp0_valid { + trace_fmt!("[{:x} Received write response on channel 0: {:#x}", INSTANCE, wr_resp0); + } else {}; + // receive responses from output channel 1 let (tok2_2, rd_resp1, rd_resp1_valid) = recv_if_non_blocking(tok1, rd_resp1_r, rd_resp_ch == u1:1, zero!()); + if rd_resp1_valid { + trace_fmt!("[{:x} Received read response on channel 1: {:#x}", INSTANCE, rd_resp1); + } else {}; + let (tok2_3, wr_resp1, wr_resp1_valid) = recv_if_non_blocking(tok1, wr_resp1_r, wr_resp_ch == u1:1, zero!()); - + if wr_resp1_valid { + trace_fmt!("[{:x} Received write response on channel 1: {:#x}", INSTANCE, wr_resp1); + } else {}; + // prepare read output values let (rd_resp, rd_resp_valid) = if rd_resp_ch == u1:0 { (rd_resp0, rd_resp0_valid) @@ -181,15 +209,29 @@ pub proc RamDemux< // send responses to input channel let tok2_4 = send_if(tok1, rd_resp_s, rd_resp_valid, rd_resp); + if rd_resp_valid { + trace_fmt!("[{:x} Sent read response: {:#x}", INSTANCE, rd_resp); + } else {}; + let sel_q_rd_end = if rd_resp_valid { sel_q_rd_end >> u32:1 } else { sel_q_rd_end }; let tok2_5 = send_if(tok1, wr_resp_s, wr_resp_valid, wr_resp); + if wr_resp_valid { + trace_fmt!("[{:x} Sent write response: {:#x}", INSTANCE, wr_resp); + } else {}; + let sel_q_wr_end = if wr_resp_valid { sel_q_wr_end >> u32:1 } else { sel_q_wr_end }; // handle select let (tok1_6, sel, sel_valid) = recv_non_blocking(tok, sel_req_r, sel); + if sel_valid { + trace_fmt!("[{:x} Received select: {:#x}", INSTANCE, sel); + } else {}; let tok1_7 = send_if(tok1_6, sel_resp_s, sel_valid, ()); + if sel_valid { + trace_fmt!("[{:x} Sent select response", INSTANCE); + } else {}; RamDemuxState { sel, sel_q_rd, sel_q_wr, sel_q_rd_end, sel_q_wr_end } } @@ -261,7 +303,7 @@ proc RamDemuxTest { let (wr_resp1_s, wr_resp1_r) = chan("wr_resp1"); spawn RamDemux< - TEST_RAM_ADDR_WIDTH, TEST_RAM_DATA_WIDTH, TEST_RAM_NUM_PARTITIONS, + TEST_RAM_ADDR_WIDTH, TEST_RAM_DATA_WIDTH, TEST_RAM_NUM_PARTITIONS, u32:0, TEST_DEMUX_INIT_SEL, TEST_DEMUX_QUEUE_LEN >( sel_req_r, sel_resp_s, diff --git a/xls/modules/zstd/ram_demux3.x b/xls/modules/zstd/ram_demux3.x index 1548c4aa03..3fd427002e 100644 --- a/xls/modules/zstd/ram_demux3.x +++ b/xls/modules/zstd/ram_demux3.x @@ -79,7 +79,7 @@ pub proc RamDemux3< let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); - spawn ram_demux::RamDemux( + spawn ram_demux::RamDemux( d1_sel_req_r, d1_sel_resp_s, rd_req_r, rd_resp_s, wr_req_r, wr_resp_s, rd_req0_s, rd_resp0_r, wr_req0_s, wr_resp0_r, @@ -89,7 +89,7 @@ pub proc RamDemux3< let (d2_sel_req_s, d2_sel_req_r) = chan("d2_sel_req"); let (d2_sel_resp_s, d2_sel_resp_r) = chan<(), CHANNEL_DEPTH>("d2_sel_resp"); - spawn ram_demux::RamDemux( + spawn ram_demux::RamDemux( d2_sel_req_r, d2_sel_resp_s, tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, rd_req1_s, rd_resp1_r, wr_req1_s, wr_resp1_r, diff --git a/xls/modules/zstd/refilling_shift_buffer.x b/xls/modules/zstd/refilling_shift_buffer.x index 3be573f8ef..7e6c8bcac2 100644 --- a/xls/modules/zstd/refilling_shift_buffer.x +++ b/xls/modules/zstd/refilling_shift_buffer.x @@ -96,7 +96,7 @@ proc RefillingShiftBufferInternal< reader_req_s: chan out; reader_resp_r: chan in; - start_req_r: chan in; + start_req_r: chan in; stop_flush_req_r: chan<()> in; buffer_data_in_s: chan out; buffer_data_out_s: chan out; @@ -108,7 +108,7 @@ proc RefillingShiftBufferInternal< config( reader_req_s: chan out, reader_resp_r: chan in, - start_req_r: chan in, + start_req_r: chan in, stop_flush_req_r: chan<()> in, buffer_ctrl_r: chan in, buffer_data_out_s: chan out, diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x index e6e1a2eea0..294c4855c8 100644 --- a/xls/modules/zstd/sequence_dec.x +++ b/xls/modules/zstd/sequence_dec.x @@ -68,11 +68,10 @@ struct SequenceDecoderState { conf_resp: sequence_conf_dec::SequenceConfDecoderResp, } -struct FseLookupCtrlReq { +struct FseLookupCtrlReq { ll: bool, ml: bool, of: bool, - addr: uN[AXI_ADDR_W], } type AccuracyLog = common::FseAccuracyLog; @@ -82,20 +81,19 @@ struct FseLookupCtrlResp { of_accuracy_log: AccuracyLog, } -struct FseLookupCtrlState { +struct FseLookupCtrlState { decode: bool[3], decode_valid: bool, - addr: uN[AXI_ADDR_W], resp: FseLookupCtrlResp, cnt: u2, } -pub proc FseLookupCtrl { - type Req = FseLookupCtrlReq; +pub proc FseLookupCtrl { + type Req = FseLookupCtrlReq; type Resp = FseLookupCtrlResp; - type State = FseLookupCtrlState; + type State = FseLookupCtrlState; - type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; req_r: chan in; @@ -135,7 +133,6 @@ pub proc FseLookupCtrl { decode: bool[3]:[req.ll, req.of, req.ml], decode_valid: true, cnt: u2:0, - addr: req.addr, ..zero!() } } else { @@ -159,14 +156,11 @@ pub proc FseLookupCtrl { } else {}; // trace_fmt!("Received response from demux"); - let fld_req = FseLookupDecoderReq { addr: state.addr }; - let tok3 = send_if(tok2, fld_req_s, do_set, fld_req); + let tok3 = send_if(tok2, fld_req_s, do_set, FseLookupDecoderReq {}); if do_set { - trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Sent FseLookupDecoder req {:#x}", fld_req); + trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Sent FseLookupDecoder req"); } else {}; - // FIXME: Extract RefillingShiftBuffer from the FseLookupDecoder - // to support decoding multiple FSE Tables let (tok4, fld_resp) = recv_if(tok3, fld_resp_r, do_set, zero!()); if do_set { trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Received FseLookupDecoder resp {:#x}", fld_resp); @@ -191,13 +185,11 @@ pub proc FseLookupCtrl { } } -const INST_AXI_ADDR_W = u32:32; - pub proc FseLookupCtrlInst { - type Req = FseLookupCtrlReq; + type Req = FseLookupCtrlReq; type Resp = FseLookupCtrlResp; - type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; init { } @@ -212,7 +204,7 @@ pub proc FseLookupCtrlInst { demux_req_s: chan out, demux_resp_r: chan<()> in, ) { - spawn FseLookupCtrl( + spawn FseLookupCtrl( req_r, resp_s, fld_req_s, fld_resp_r, demux_req_s, demux_resp_r, @@ -232,7 +224,7 @@ const TEST_FLC_AXI_ADDR_W = u32:32; // // type Addr = uN[TEST_FLC_AXI_ADDR_W]; // -// type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; +// type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; // type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; // type FseLookupDecoderStatus = fse_lookup_dec::FseLookupDecoderStatus; // @@ -390,7 +382,7 @@ pub proc SequenceDecoderCtrl< type SequenceConfDecoderReq = sequence_conf_dec::SequenceConfDecoderReq; type SequenceConfDecoderResp = sequence_conf_dec::SequenceConfDecoderResp; - type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; type RefillingShiftBufferStart = refilling_shift_buffer::RefillStart; @@ -423,6 +415,10 @@ pub proc SequenceDecoderCtrl< fd_rsb_stop_flush_req_s: chan<()> out; fd_rsb_flushing_done_r: chan<()> in; + fld_rsb_start_req_s: chan out; + fld_rsb_stop_flush_req_s: chan<()> out; + fld_rsb_flushing_done_r: chan<()> in; + fd_ctrl_s: chan out; fd_finish_r: chan in; @@ -454,6 +450,10 @@ pub proc SequenceDecoderCtrl< fd_rsb_stop_flush_req_s: chan<()> out, fd_rsb_flushing_done_r: chan<()> in, + fld_rsb_start_req_s: chan out, + fld_rsb_stop_flush_req_s: chan<()> out, + fld_rsb_flushing_done_r: chan<()> in, + fd_ctrl_s: chan out, fd_finish_r: chan in, ) { @@ -462,7 +462,7 @@ pub proc SequenceDecoderCtrl< let (flc_req_s, flc_req_r) = chan("flc_req"); let (flc_resp_s, flc_resp_r) = chan("flc_resp"); - spawn FseLookupCtrl( + spawn FseLookupCtrl( flc_req_r, flc_resp_s, fld_req_s, fld_resp_r, fld_demux_req_s, fld_demux_resp_r, @@ -476,6 +476,7 @@ pub proc SequenceDecoderCtrl< of_demux_req_s, of_demux_resp_r, ml_demux_req_s, ml_demux_resp_r, fd_rsb_start_req_s, fd_rsb_stop_flush_req_s, fd_rsb_flushing_done_r, + fld_rsb_start_req_s, fld_rsb_stop_flush_req_s, fld_rsb_flushing_done_r, fd_ctrl_s, fd_finish_r, ) } @@ -502,9 +503,13 @@ pub proc SequenceDecoderCtrl< assert!(conf_resp.header.offset_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); } else {}; + // Start RefillingShiftBuffer for decoding lookups + let tok_dec_lookup = send(tok_recv_scd, fld_rsb_start_req_s, RefillingShiftBufferStart { + start_addr: req.start_addr + conf_resp.length as Addr, + }); + // Request decoding lookups let flc_req = FseLookupCtrlReq { - addr: req.start_addr + conf_resp.length as Addr, ll: (conf_resp.header.literals_mode == CompressionMode::COMPRESSED), ml: (conf_resp.header.match_mode == CompressionMode::COMPRESSED), of: (conf_resp.header.offset_mode == CompressionMode::COMPRESSED), @@ -515,9 +520,13 @@ pub proc SequenceDecoderCtrl< trace_fmt!("[SequenceDecoderCtrl]: Sent FseLookupCtrl request: {:#x}", flc_req); } else {}; - // Receive response about deoded lookups + // Receive response about decoded lookups let (tok_recv_ctrl, flc_resp) = recv_if(tok_send_ctrl, flc_resp_r, !zero_sequences, zero!()); + // We've finished decoding lookups - flush the corresponding refilling shift buffer + let tok_fld_rsb_flush = send(tok_recv_ctrl, fld_rsb_stop_flush_req_s, ()); + let (tok_fld_rsb_flush_done, ()) = recv(tok_fld_rsb_flush, fld_rsb_flushing_done_r); + // Set proper LL lookup through demux let ll_demux_sel = (conf_resp.header.literals_mode != CompressionMode::PREDEFINED); let tok_ll_demux = send_if(tok_recv_scd, ll_demux_req_s, !zero_sequences, ll_demux_sel); @@ -559,11 +568,13 @@ pub proc SequenceDecoderCtrl< let tok_rsb_flush = send_if(tok_fse_dec, fd_rsb_stop_flush_req_s, !zero_sequences, ()); trace_fmt!("[SequenceDecoderCtrl]: Send flush request"); - let (tok_rsb_flush_done, _) = recv_if(tok_rsb_flush, fd_rsb_flushing_done_r, !zero_sequences, ()); + let (tok_rsb_flush_done, ()) = recv_if(tok_rsb_flush, fd_rsb_flushing_done_r, !zero_sequences, ()); trace_fmt!("[SequenceDecoderCtrl]: Flush done"); + // Send response once both refilling shift buffers have been flushed let resp = SequenceDecoderResp { status: Status::OK }; - send(tok_rsb_flush_done, sd_resp_s, resp); + let tok_flush_done = join(tok_fld_rsb_flush_done, tok_rsb_flush_done); + send(tok_flush_done, sd_resp_s, resp); } } @@ -587,7 +598,7 @@ const SDC_TEST_REFILLING_SB_LENGTH_W = refilling_shift_buffer::length_width(SDC_ // type SequenceConfDecoderResp = sequence_conf_dec::SequenceConfDecoderResp; // type SequenceConfDecoderStatus = sequence_conf_dec::SequenceConfDecoderStatus; // -// type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; +// type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; // type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; // type FseLookupDecoderStatus = fse_lookup_dec::FseLookupDecoderStatus; // @@ -745,6 +756,7 @@ pub proc SequenceDecoder< AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_DEST_W: u32, AXI_ID_W: u32, DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, @@ -767,7 +779,7 @@ pub proc SequenceDecoder< type SequenceConfDecoderReq = sequence_conf_dec::SequenceConfDecoderReq; type SequenceConfDecoderResp = sequence_conf_dec::SequenceConfDecoderResp; - type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; type FseDecoderCtrl = fse_dec::FseDecoderCtrl; @@ -788,6 +800,11 @@ pub proc SequenceDecoder< type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; @@ -801,13 +818,15 @@ pub proc SequenceDecoder< fd_rsb_ctrl_r: chan in; fd_rsb_data_s: chan out; - ll_wr_req_s: chan out; - ll_wr_resp_s: chan in; - ml_wr_req_s: chan out; - ml_wr_resp_s: chan in; - of_wr_req_s: chan out; - of_wr_resp_s: chan in; + dummy_ll_wr_req_s: chan out; + dummy_ll_wr_resp_r: chan in; + dummy_ml_wr_req_s: chan out; + dummy_ml_wr_resp_r: chan in; + dummy_of_wr_req_s: chan out; + dummy_of_wr_resp_r: chan in; + dummy_fse_rd_req_s: chan out; + dummy_fse_rd_resp_r: chan in; dummy_ll_fse_rd_req_r: chan in; dummy_ll_fse_rd_resp_s: chan out; dummy_ll_fse_wr_req_r: chan in; @@ -852,6 +871,11 @@ pub proc SequenceDecoder< tmp_wr_req_s: chan out, tmp_wr_resp_r: chan in, + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + ll_def_fse_rd_req_s: chan out, ll_def_fse_rd_resp_r: chan in, ll_def_fse_wr_req_s: chan out, @@ -883,7 +907,7 @@ pub proc SequenceDecoder< of_fse_wr_resp_r: chan in, ) { const CHANNEL_DEPTH = u32:1; - const READ_BACKWORD = true; + const READ_BACKWARD = true; // Sequence Section Decoder @@ -916,34 +940,64 @@ pub proc SequenceDecoder< let (fld_req_s, fld_req_r) = chan("fse_req"); let (fld_resp_s, fld_resp_r) = chan("fse_resp"); - let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); - let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); + // FseLookupDecoder is not expected to read anything from the lookup + let (dummy_fse_rd_req_s, dummy_fse_rd_req_r) = chan("dummy_fse_rd_req"); + let (dummy_fse_rd_resp_s, dummy_fse_rd_resp_r) = chan("dummy_fse_rd_resp"); let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + let (fld_rsb_start_req_s, fld_rsb_start_req_r) = chan("start_req"); + let (fld_rsb_stop_flush_req_s, fld_rsb_stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("stop_flush_req"); + let (fld_rsb_buffer_ctrl_s, fld_rsb_buffer_ctrl_r) = chan("buffer_ctrl"); + let (fld_rsb_buffer_data_out_s, fld_rsb_buffer_data_out_r) = chan("buffer_data_out"); + let (fld_rsb_flushing_done_s, fld_rsb_flushing_done_r) = chan<(), CHANNEL_DEPTH>("flushing_done"); spawn fse_lookup_dec::FseLookupDecoder< - AXI_DATA_W, AXI_ADDR_W, + AXI_DATA_W, DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_DATA_W, TMP2_RAM_ADDR_W, TMP2_RAM_NUM_PARTITIONS, FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, >( fld_req_r, fld_resp_s, - fld_mem_rd_req_s, fld_mem_rd_resp_r, dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, - fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_wr_req_s, fse_wr_resp_r, + fld_rsb_buffer_ctrl_s, fld_rsb_buffer_data_out_r, + ); + + spawn refilling_shift_buffer::RefillingShiftBuffer( + fld_mem_rd_req_s, fld_mem_rd_resp_r, + fld_rsb_start_req_r, fld_rsb_stop_flush_req_r, + fld_rsb_buffer_ctrl_r, fld_rsb_buffer_data_out_s, + fld_rsb_flushing_done_s, ); // RamDemux3 + + // Dummy channels + let (dummy_ll_fse_rd_req_s, dummy_ll_fse_rd_req_r) = chan("dummy_ll_fse_rd_req"); + let (dummy_ll_fse_rd_resp_s, dummy_ll_fse_rd_resp_r) = chan("dummy_ll_fse_rd_resp"); + let (dummy_ll_fse_wr_req_s, dummy_ll_fse_wr_req_r) = chan("dummy_ll_fse_wr_req"); + let (dummy_ll_fse_wr_resp_s, dummy_ll_fse_wr_resp_r) = chan("dummy_ll_fse_wr_resp"); + let (dummy_ml_fse_rd_req_s, dummy_ml_fse_rd_req_r) = chan("dummy_ml_fse_rd_req"); + let (dummy_ml_fse_rd_resp_s, dummy_ml_fse_rd_resp_r) = chan("dummy_ml_fse_rd_resp"); + let (dummy_ml_fse_wr_req_s, dummy_ml_fse_wr_req_r) = chan("dummy_ml_fse_wr_req"); + let (dummy_ml_fse_wr_resp_s, dummy_ml_fse_wr_resp_r) = chan("dummy_ml_fse_wr_resp"); + let (dummy_of_fse_rd_req_s, dummy_of_fse_rd_req_r) = chan("dummy_of_fse_rd_req"); + let (dummy_of_fse_rd_resp_s, dummy_of_fse_rd_resp_r) = chan("dummy_of_fse_rd_resp"); + let (dummy_of_fse_wr_req_s, dummy_of_fse_wr_req_r) = chan("dummy_of_fse_wr_req"); + let (dummy_of_fse_wr_resp_s, dummy_of_fse_wr_resp_r) = chan("dummy_of_fse_wr_resp"); + let (fse_demux_req_s, fse_demux_req_r) = chan("fse_demux_req"); let (fse_demux_resp_s, fse_demux_resp_r) = chan<(), CHANNEL_DEPTH>("fse_demux_resp"); spawn ram_demux3::RamDemux3( fse_demux_req_r, fse_demux_resp_s, - fse_rd_req_r, fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s, - ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, - of_fse_rd_req_s, of_fse_rd_resp_r, of_fse_wr_req_s, of_fse_wr_resp_r, - ml_fse_rd_req_s, ml_fse_rd_resp_r, ml_fse_wr_req_s, ml_fse_wr_resp_r, + dummy_fse_rd_req_r, dummy_fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s, + dummy_ll_fse_rd_req_s, dummy_ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, + dummy_of_fse_rd_req_s, dummy_of_fse_rd_resp_r, of_fse_wr_req_s, of_fse_wr_resp_r, + dummy_ml_fse_rd_req_s, dummy_ml_fse_rd_resp_r, ml_fse_wr_req_s, ml_fse_wr_resp_r, ); let (ll_demux_req_s, ll_demux_req_r) = chan("ll_demux_req"); @@ -951,21 +1005,16 @@ pub proc SequenceDecoder< let (ll_rd_req_s, ll_rd_req_r) = chan("ll_rd_req"); let (ll_rd_resp_s, ll_rd_resp_r) = chan("ll_rd_resp"); - let (ll_wr_req_s, ll_wr_req_r) = chan("ll_wr_req"); - let (ll_wr_resp_s, ll_wr_resp_r) = chan("ll_wr_resp"); - - let (dummy_ll_fse_rd_req_s, dummy_ll_fse_rd_req_r) = chan("dummy_ll_fse_rd_req"); - let (dummy_ll_fse_rd_resp_s, dummy_ll_fse_rd_resp_r) = chan("dummy_ll_fse_rd_resp"); - let (dummy_ll_fse_wr_req_s, dummy_ll_fse_wr_req_r) = chan("dummy_ll_fse_wr_req"); - let (dummy_ll_fse_wr_resp_s, dummy_ll_fse_wr_resp_r) = chan("dummy_ll_fse_wr_resp"); + let (dummy_ll_wr_req_s, dummy_ll_wr_req_r) = chan("dummy_ll_wr_req"); + let (dummy_ll_wr_resp_s, dummy_ll_wr_resp_r) = chan("dummy_ll_wr_resp"); spawn ram_demux::RamDemux< - FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, u32:1 > ( ll_demux_req_r, ll_demux_resp_s, - ll_rd_req_r, ll_rd_resp_s, ll_wr_req_r, ll_wr_resp_s, + ll_rd_req_r, ll_rd_resp_s, dummy_ll_wr_req_r, dummy_ll_wr_resp_s, ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, - dummy_ll_fse_rd_req_s, dummy_ll_fse_rd_resp_r, dummy_ll_fse_wr_req_s, dummy_ll_fse_wr_resp_r, + ll_fse_rd_req_s, ll_fse_rd_resp_r, dummy_ll_fse_wr_req_s, dummy_ll_fse_wr_resp_r, ); let (ml_demux_req_s, ml_demux_req_r) = chan("ml_demux_req"); @@ -973,21 +1022,16 @@ pub proc SequenceDecoder< let (ml_rd_req_s, ml_rd_req_r) = chan("ml_rd_req"); let (ml_rd_resp_s, ml_rd_resp_r) = chan("ml_rd_resp"); - let (ml_wr_req_s, ml_wr_req_r) = chan("ml_wr_req"); - let (ml_wr_resp_s, ml_wr_resp_r) = chan("ml_wr_resp"); - - let (dummy_ml_fse_rd_req_s, dummy_ml_fse_rd_req_r) = chan("dummy_ml_fse_rd_req"); - let (dummy_ml_fse_rd_resp_s, dummy_ml_fse_rd_resp_r) = chan("dummy_ml_fse_rd_resp"); - let (dummy_ml_fse_wr_req_s, dummy_ml_fse_wr_req_r) = chan("dummy_ml_fse_wr_req"); - let (dummy_ml_fse_wr_resp_s, dummy_ml_fse_wr_resp_r) = chan("dummy_ml_fse_wr_resp"); + let (dummy_ml_wr_req_s, dummy_ml_wr_req_r) = chan("dummy_ml_wr_req"); + let (dummy_ml_wr_resp_s, dummy_ml_wr_resp_r) = chan("dummy_ml_wr_resp"); spawn ram_demux::RamDemux< - FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, u32:2 > ( ml_demux_req_r, ml_demux_resp_s, - ml_rd_req_r, ml_rd_resp_s, ml_wr_req_r, ml_wr_resp_s, + ml_rd_req_r, ml_rd_resp_s, dummy_ml_wr_req_r, dummy_ml_wr_resp_s, ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, - dummy_ml_fse_rd_req_s, dummy_ml_fse_rd_resp_r, dummy_ml_fse_wr_req_s, dummy_ml_fse_wr_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, dummy_ml_fse_wr_req_s, dummy_ml_fse_wr_resp_r, ); let (of_demux_req_s, of_demux_req_r) = chan("of_demux_req"); @@ -995,21 +1039,16 @@ pub proc SequenceDecoder< let (of_rd_req_s, of_rd_req_r) = chan("of_rd_req"); let (of_rd_resp_s, of_rd_resp_r) = chan("of_rd_resp"); - let (of_wr_req_s, of_wr_req_r) = chan("of_wr_req"); - let (of_wr_resp_s, of_wr_resp_r) = chan("of_wr_resp"); - - let (dummy_of_fse_rd_req_s, dummy_of_fse_rd_req_r) = chan("dummy_of_fse_rd_req"); - let (dummy_of_fse_rd_resp_s, dummy_of_fse_rd_resp_r) = chan("dummy_of_fse_rd_resp"); - let (dummy_of_fse_wr_req_s, dummy_of_fse_wr_req_r) = chan("dummy_of_fse_wr_req"); - let (dummy_of_fse_wr_resp_s, dummy_of_fse_wr_resp_r) = chan("dummy_of_fse_wr_resp"); + let (dummy_of_wr_req_s, dummy_of_wr_req_r) = chan("dummy_of_wr_req"); + let (dummy_of_wr_resp_s, dummy_of_wr_resp_r) = chan("dummy_of_wr_resp"); spawn ram_demux::RamDemux< - FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, u32:3 > ( of_demux_req_r, of_demux_resp_s, - of_rd_req_r, of_rd_resp_s, of_wr_req_r, of_wr_resp_s, + of_rd_req_r, of_rd_resp_s, dummy_of_wr_req_r, dummy_of_wr_resp_s, of_def_fse_rd_req_s, of_def_fse_rd_resp_r, of_def_fse_wr_req_s, of_def_fse_wr_resp_r, - dummy_of_fse_rd_req_s, dummy_of_fse_rd_resp_r, dummy_of_fse_wr_req_s, dummy_of_fse_wr_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, dummy_of_fse_wr_req_s, dummy_of_fse_wr_resp_r, ); let (fd_mem_rd_req_s, fd_mem_rd_req_r) = chan("fd_mem_rd_req"); @@ -1026,7 +1065,7 @@ pub proc SequenceDecoder< let (fd_rsb_data_s, fd_rsb_data_r) = chan("fd_rsb_data"); let (fd_rsb_flushing_done_s, fd_rsb_flushing_done_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_flushing_done"); - spawn refilling_shift_buffer::RefillingShiftBuffer ( + spawn refilling_shift_buffer::RefillingShiftBuffer ( fd_mem_rd_req_s, fd_mem_rd_resp_r, fd_rsb_start_req_r, fd_rsb_stop_flush_req_r, fd_rsb_ctrl_r, fd_rsb_data_s, @@ -1056,16 +1095,22 @@ pub proc SequenceDecoder< of_demux_req_s, of_demux_resp_r, ml_demux_req_s, ml_demux_resp_r, fd_rsb_start_req_s, fd_rsb_stop_flush_req_s, fd_rsb_flushing_done_r, + fld_rsb_start_req_s, fld_rsb_stop_flush_req_s, fld_rsb_flushing_done_r, fd_ctrl_s, fd_finish_r, ); ( fd_ctrl_s, fd_finish_r, fd_rsb_ctrl_r, fd_rsb_data_s, - ll_wr_req_s, ll_wr_resp_r, - ml_wr_req_s, ml_wr_resp_r, - of_wr_req_s, of_wr_resp_r, - dummy_ll_fse_rd_req_r, + dummy_ll_wr_req_s, + dummy_ll_wr_resp_r, + dummy_ml_wr_req_s, + dummy_ml_wr_resp_r, + dummy_of_wr_req_s, + dummy_of_wr_resp_r, + dummy_fse_rd_req_s, + dummy_fse_rd_resp_r, + dummy_ll_fse_rd_req_r, dummy_ll_fse_rd_resp_s, dummy_ll_fse_wr_req_r, dummy_ll_fse_wr_resp_s, @@ -1077,30 +1122,31 @@ pub proc SequenceDecoder< dummy_of_fse_rd_resp_s, dummy_of_fse_wr_req_r, dummy_of_fse_wr_resp_s, - ) } next(state: ()) { - send_if(join(), ll_wr_req_s, false, zero!()); - recv_if(join(), ll_wr_resp_s, false, zero!()); - send_if(join(), ml_wr_req_s, false, zero!()); - recv_if(join(), ml_wr_resp_s, false, zero!()); - send_if(join(), of_wr_req_s, false, zero!()); - recv_if(join(), of_wr_resp_s, false, zero!()); - - recv_if(join(), dummy_ll_fse_rd_req_r, false, zero!()); - send_if(join(), dummy_ll_fse_rd_resp_s, false, zero!()); - recv_if(join(), dummy_ll_fse_wr_req_r, false, zero!()); - send_if(join(), dummy_ll_fse_wr_resp_s, false, zero!()); - recv_if(join(), dummy_ml_fse_rd_req_r, false, zero!()); - send_if(join(), dummy_ml_fse_rd_resp_s, false, zero!()); - recv_if(join(), dummy_ml_fse_wr_req_r, false, zero!()); - send_if(join(), dummy_ml_fse_wr_resp_s, false, zero!()); - recv_if(join(), dummy_of_fse_rd_req_r, false, zero!()); - send_if(join(), dummy_of_fse_rd_resp_s, false, zero!()); - recv_if(join(), dummy_of_fse_wr_req_r, false, zero!()); - send_if(join(), dummy_of_fse_wr_resp_s, false, zero!()); + let tok = join(); + send_if(tok, dummy_ll_wr_req_s, false, zero!()); + recv_if(tok, dummy_ll_wr_resp_r, false, zero!()); + send_if(tok, dummy_ml_wr_req_s, false, zero!()); + recv_if(tok, dummy_ml_wr_resp_r, false, zero!()); + send_if(tok, dummy_of_wr_req_s, false, zero!()); + recv_if(tok, dummy_of_wr_resp_r, false, zero!()); + send_if(tok, dummy_fse_rd_req_s, false, zero!()); + recv_if(tok, dummy_fse_rd_resp_r, false, zero!()); + recv_if(tok, dummy_ll_fse_rd_req_r, false, zero!()); + send_if(tok, dummy_ll_fse_rd_resp_s, false, zero!()); + recv_if(tok, dummy_ll_fse_wr_req_r, false, zero!()); + send_if(tok, dummy_ll_fse_wr_resp_s, false, zero!()); + recv_if(tok, dummy_ml_fse_rd_req_r, false, zero!()); + send_if(tok, dummy_ml_fse_rd_resp_s, false, zero!()); + recv_if(tok, dummy_ml_fse_wr_req_r, false, zero!()); + send_if(tok, dummy_ml_fse_wr_resp_s, false, zero!()); + recv_if(tok, dummy_of_fse_rd_req_r, false, zero!()); + send_if(tok, dummy_of_fse_rd_resp_s, false, zero!()); + recv_if(tok, dummy_of_fse_wr_req_r, false, zero!()); + send_if(tok, dummy_of_fse_wr_resp_s, false, zero!()); } } @@ -1125,9 +1171,9 @@ const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_W; const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); const TEST_FSE_RAM_DATA_W = u32:32; -const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); -const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W; const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); const TEST_FSE_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; @@ -1137,151 +1183,340 @@ const TEST_TMP_RAM_ADDR_W = std::clog2(TEST_TMP_RAM_SIZE); const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); -const TEST_RAM_DATA = u64[40]:[ - u64:0x0, u64:0x0, // 0x000 - u64:0x0, u64:0x0, // 0x010 - u64:0x0, u64:0x0, // 0x020 - u64:0x0, u64:0x0, // 0x030 - u64:0x0, u64:0x0, // 0x040 - u64:0x0, u64:0x0, // 0x050 - u64:0x0, u64:0x0, // 0x060 - u64:0x0, u64:0x0, // 0x070 - u64:0x0, u64:0x0, // 0x080 - u64:0x0, u64:0x0, // 0x090 - u64:0x0, u64:0x0, // 0x0A0 - u64:0x0, u64:0x0, // 0x0B0 - u64:0x0, u64:0x0, // 0x0C0 - u64:0x0, u64:0x0, // 0x0D0 - u64:0x0, u64:0x0, // 0x0E0 - u64:0x0, u64:0x0, // 0x0F0 - u64:0x0016A400E6C3000A, // 0x100 - u64:0x225100295B0012D6, // 0x138 - u64:0x1E00123CB813DB80, // 0x140 - u64:0x1026064002C4800A, // 0x148 - u64:0x0, ... -]; - -const EXPECTED_OUTPUT = SequenceExecutorPacket[20]:[ - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0000, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x001c, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x000a, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x0389, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0000, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x013c, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0000, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x0479, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0009, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x001d, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0001, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x024a, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0001, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x032b, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0001, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x02b5, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0002, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0003, - content: u64:0x03a9, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x0, - content: u64:0x0, - last: false, - }, - SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::SEQUENCE, - length: u64:0x0004, - content: u64:0x06c3, - last: true, - }, +const TEST_TMP2_RAM_DATA_W = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_W = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_W; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_W); + +// testcase format: +// - sequences section length +// - sequences section as it appears in memory +// - expected output size +// - expected output +const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[2] = [ + // Test case 0 + // raw literals with sequences with 3 predefined tables + // ./decodecorpus -pdata2.out -odata2.in -s35304 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 + ( + u32:17, + u64[32]:[ + u64:0x0, u64:0x0, + u64:0xBC7C2BA0B0430006, + u64:0x2157643002EA92AA, + u64:0x0000000000000002, + u64:0x0, ... + ], + u32:12, + SequenceExecutorPacket[64]:[ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0004, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0005, + content: u64:0x000b, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0004, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0006, + content: u64:0x0001, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0005, + content: u64:0x0032, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0006, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0009, + content: u64:0x003e, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0009, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0006, + content: u64:0x003d, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x001a, + content: u64:0x0043, + last: true, + }, + zero!(), ... + ] + ), + // testcase 1 + // 2 custom tables with accuracy log 5 and 5, 1 predefined table + ( + u32:32, + u64[32]:[ + u64:0x0, u64:0x0, + u64:0x3D2321013010280D, + u64:0x6B3F7AC0F0D11F40, + u64:0xE80100C6012D0310, + u64:0x6CBFAEE1A0DDEF00, + u64:0x0, ... + ], + u32:26, + SequenceExecutorPacket[64]:[ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0003, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x000e, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x0023, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x00de, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x003a, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0110, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x00b0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x00da, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x0044, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x013f, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x001b, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x0003, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x0031, + last: true, + }, + zero!(), ... + ] + ), + // Test case 2 (WARNING: long test running time) + // 3 custom lookup tables with accuracy log 9, 8 and 9 + // decodecorpus -pdata.out -odata.in -s58745 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 + // ( + // u32:32, + // u64[32]:[ + // u64:0x0, u64:0x0, + // u64:0xFC0502602814A804, + // u64:0x505040131FF60604, + // u64:0xFE01C080140FE030, + // u64:0x4040E65B84521B01, + // u64:0x0, ... + // ], + // u32:7, + // SequenceExecutorPacket[64]:[ + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::LITERAL, + // length: u64:0x0005, + // content: u64:0x0, + // last: false, + // }, + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::SEQUENCE, + // length: u64:0x0004, + // content: u64:0x0006, + // last: false, + // }, + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::SEQUENCE, + // length: u64:0x0004, + // content: u64:0x0002, + // last: false, + // }, + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::LITERAL, + // length: u64:0x0011, + // content: u64:0x0, + // last: false, + // }, + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::SEQUENCE, + // length: u64:0x0004, + // content: u64:0x000a, + // last: false, + // }, + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::LITERAL, + // length: u64:0x002b, + // content: u64:0x0, + // last: false, + // }, + // SequenceExecutorPacket { + // msg_type: SequenceExecutorMessageType::SEQUENCE, + // length: u64:0x0006, + // content: u64:0x0023, + // last: true, + // }, + // zero!(), ... + // ] + // ), ]; type Base = u16; @@ -1483,6 +1718,11 @@ proc SequenceDecoderTest { type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseAddr = uN[TEST_FSE_RAM_ADDR_W]; type FseData = uN[TEST_FSE_RAM_DATA_W]; type FseMask = uN[TEST_FSE_RAM_NUM_PARTITIONS]; @@ -1564,6 +1804,17 @@ proc SequenceDecoderTest { TEST_TMP_RAM_WORD_PARTITION_SIZE >(tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_W, + TEST_TMP2_RAM_SIZE, + TEST_TMP2_RAM_WORD_PARTITION_SIZE + >(tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s); + // RAM with default FSE lookup for Literal Lengths let (ll_sel_test_s, ll_sel_test_r) = chan("ll_test_sel"); @@ -1803,6 +2054,7 @@ proc SequenceDecoderTest { TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_ADDR_W, TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_NUM_PARTITIONS, TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, > ( ss_axi_ar_s, ss_axi_r_r, @@ -1814,6 +2066,7 @@ proc SequenceDecoderTest { dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, @@ -1848,22 +2101,6 @@ proc SequenceDecoderTest { next(state: ()) { let tok = join(); - // FILL THE TEST DATA - let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(TEST_RAM_DATA)) { - let req = InputRamWrReq { - addr: i as InputAddr, - data: TEST_RAM_DATA[i] as InputData, - mask: !InputMask:0, - }; - let tok = send(tok, input0_wr_req_s, req); - let (tok, _) = recv(tok, input0_wr_resp_r); - let tok = send(tok, input1_wr_req_s, req); - let (tok, _) = recv(tok, input1_wr_resp_r); - let tok = send(tok, input2_wr_req_s, req); - let (tok, _) = recv(tok, input2_wr_resp_r); - tok - }(tok); - // FILL THE LL DEFAULT RAM let tok = send(tok, ll_sel_test_s, u1:0); let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(DEFAULT_LL_TABLE)) { @@ -1906,69 +2143,110 @@ proc SequenceDecoderTest { }(tok); let tok = send(tok, ml_sel_test_s, u1:1); - // START DECODING - let tok = send(tok, req_s, Req { - sync: BlockSyncData { - id: u32:0, - last_block: false, - }, - start_addr: uN[TEST_AXI_ADDR_W]:0x100, - end_addr: uN[TEST_AXI_ADDR_W]:0x120, - literals_count: u20:24, - }); - - let tok = for ((i, output), tok): ((u32, SequenceExecutorPacket), token) in enumerate(EXPECTED_OUTPUT) { + // LOAD TESTCASES + let tok = unroll_for! (test_i, tok): (u32, token) in range(u32:0, array_size(SEQ_DEC_TESTCASES)) { + let (seq_len, seq_data, expected_len, expected_data) = SEQ_DEC_TESTCASES[test_i]; + let ADDR_OFFSET = uN[TEST_AXI_ADDR_W]:0x10; + let seq_len_words = std::ceil_div(seq_len + ADDR_OFFSET, u32:8); + // FILL THE TEST DATA + let tok = for (i, tok): (u32, token) in range(u32:0, seq_len_words) { + let req = InputRamWrReq { + addr: i as InputAddr, + data: seq_data[i] as InputData, + mask: !InputMask:0, + }; + let tok = send(tok, input0_wr_req_s, req); + let (tok, _) = recv(tok, input0_wr_resp_r); + let tok = send(tok, input1_wr_req_s, req); + let (tok, _) = recv(tok, input1_wr_resp_r); + let tok = send(tok, input2_wr_req_s, req); + let (tok, _) = recv(tok, input2_wr_resp_r); + tok + }(tok); + + // COUNT THE AMOUNT OF LITERALS + let (tok, literals_count) = for (i, (tok, literals_count)): (u32, (token, u20)) in range(u32:0, expected_len) { + let literals_count = match expected_data[i].msg_type { + SequenceExecutorMessageType::SEQUENCE => literals_count, + SequenceExecutorMessageType::LITERAL => literals_count + expected_data[i].length as u20, + }; + (tok, literals_count) + }((tok, u20:0)); + + // START DECODING + let tok = send(tok, req_s, Req { + sync: BlockSyncData { + id: u32:0, + last_block: false, + }, + start_addr: ADDR_OFFSET, + end_addr: ADDR_OFFSET + seq_len as uN[TEST_AXI_ADDR_W], + literals_count: literals_count, + }); + + let tok = for (i, tok): (u32, token) in range(u32:0, expected_len) { + let output = expected_data[i]; + let (tok, recv_output) = recv(tok, fd_command_r); + trace_fmt!("[{}]: Expected: {:#x}\nGot: {:#x}\n", i, output, recv_output); + assert_eq(output, recv_output.data); + tok + }(tok); + + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: SequenceDecoderStatus::OK + }); + trace_fmt!("DECODE RESPONSE"); + + // START DECODING - ask for more literals - expecting additional empty output packet with + // last set + let ADDITIONAL_LITERALS = u20:123; + let tok = send(tok, req_s, Req { + sync: BlockSyncData { + id: u32:0, + last_block: false, + }, + start_addr: ADDR_OFFSET, + end_addr: ADDR_OFFSET + seq_len as uN[TEST_AXI_ADDR_W], + literals_count: literals_count + ADDITIONAL_LITERALS, + }); + + // Don't read the last output packet from the expected output array + let tok = for (i, tok): (u32, token) in range(u32:0, expected_len - u32:1) { + let output = expected_data[i]; + let (tok, recv_output) = recv(tok, fd_command_r); + trace_fmt!("[{}]: Expected: {:#x}\nGot: {:#x}\n", i, output, recv_output); + assert_eq(output, recv_output.data); + tok + }(tok); + + // The last packet from the expected output array is now expected to have last not set + let expected = SequenceExecutorPacket { + last: false, + ..expected_data[expected_len - u32:1] + }; let (tok, recv_output) = recv(tok, fd_command_r); - trace_fmt!("[{}]: Expected: {:#x}\nGot: {:#x}\n", i, output, recv_output); - assert_eq(output, recv_output.data); - tok - }(tok); - - let (tok, _) = recv(tok, resp_r); - - // START DECODING - ask for more literals - expecting additional empty output packet with - // last set - let tok = send(tok, req_s, Req { - sync: BlockSyncData { - id: u32:0, - last_block: false, - }, - start_addr: uN[TEST_AXI_ADDR_W]:0x100, - end_addr: uN[TEST_AXI_ADDR_W]:0x120, - literals_count: u20:26, - }); - - // Don't read the last output packet from the expected output array - let tok = for (i, tok): (u32, token) in u32:0..(array_size(EXPECTED_OUTPUT) - u32:1) { - let output = EXPECTED_OUTPUT[i]; + trace_fmt!("[LAST-1]: Expected: {:#x}\nGot: {:#x}\n", expected, recv_output); + assert_eq(expected, recv_output.data); + + // This is the actual last output packet + let expected = SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: ADDITIONAL_LITERALS as u64, + content: u64:0x0, + last: true, + }; let (tok, recv_output) = recv(tok, fd_command_r); - trace_fmt!("[{}]: Expected: {:#x}\nGot: {:#x}\n", i, output, recv_output); - assert_eq(output, recv_output.data); + trace_fmt!("[LAST]: Expected: {:#x}\nGot: {:#x}\n", expected, recv_output); + assert_eq(expected, recv_output.data); + + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: SequenceDecoderStatus::OK + }); tok }(tok); - // The last packet from the expected output array is now expected to have last not set - let expected = SequenceExecutorPacket { - last: false, - ..EXPECTED_OUTPUT[array_size(EXPECTED_OUTPUT) - u32:1] - }; - let (tok, recv_output) = recv(tok, fd_command_r); - trace_fmt!("[LAST-1]: Expected: {:#x}\nGot: {:#x}\n", expected, recv_output); - assert_eq(expected, recv_output.data); - - // This is the actual last output packet - let expected = SequenceExecutorPacket { - msg_type: SequenceExecutorMessageType::LITERAL, - length: u64:0x2, - content: u64:0x0, - last: true, - }; - let (tok, recv_output) = recv(tok, fd_command_r); - trace_fmt!("[LAST]: Expected: {:#x}\nGot: {:#x}\n", expected, recv_output); - assert_eq(expected, recv_output.data); - - let (tok, _) = recv(tok, resp_r); - send(tok, terminator, true); } diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index ba1c3f961c..a7c2a9faba 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -946,6 +946,7 @@ pub proc ZstdDecoder< DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, HISTORY_BUFFER_SIZE_KB: u32, @@ -1028,6 +1029,11 @@ pub proc ZstdDecoder< type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; @@ -1085,6 +1091,11 @@ pub proc ZstdDecoder< tmp_wr_req_s: chan out, tmp_wr_resp_r: chan in, + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + fse_rd_req_s: chan[u32:6] out, fse_rd_resp_r: chan[u32:6] in, fse_wr_req_s: chan[u32:6] out, @@ -1257,6 +1268,7 @@ pub proc ZstdDecoder< // FSE lookup table RAMs DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_ADDR_W, TMP2_RAM_DATA_W, TMP2_RAM_NUM_PARTITIONS, FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, >( // MAIN IOs @@ -1272,6 +1284,7 @@ pub proc ZstdDecoder< comp_axi_ram_ar_s[2], comp_axi_ram_r_r[2], dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, fse_rd_req_s[0], fse_rd_resp_r[0], fse_wr_req_s[0], fse_wr_resp_r[0], fse_rd_req_s[1], fse_rd_resp_r[1], fse_wr_req_s[1], fse_wr_resp_r[1], fse_rd_req_s[2], fse_rd_resp_r[2], fse_wr_req_s[2], fse_wr_resp_r[2], @@ -1408,7 +1421,7 @@ const INST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( const INST_FSE_RAM_DATA_W = u32:32; const INST_FSE_RAM_SIZE = u32:256; const INST_FSE_RAM_ADDR_W = std::clog2(INST_FSE_RAM_SIZE); -const INST_FSE_RAM_WORD_PARTITION_SIZE = INST_FSE_RAM_DATA_W / u32:3; +const INST_FSE_RAM_WORD_PARTITION_SIZE = INST_FSE_RAM_DATA_W; const INST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( INST_FSE_RAM_WORD_PARTITION_SIZE, INST_FSE_RAM_DATA_W); @@ -1419,6 +1432,13 @@ const INST_TMP_RAM_WORD_PARTITION_SIZE = INST_TMP_RAM_DATA_W; const INST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( INST_TMP_RAM_WORD_PARTITION_SIZE, INST_TMP_RAM_DATA_W); +const INST_TMP2_RAM_DATA_W = u32:8; +const INST_TMP2_RAM_SIZE = u32:512; +const INST_TMP2_RAM_ADDR_W = std::clog2(INST_TMP2_RAM_SIZE); +const INST_TMP2_RAM_WORD_PARTITION_SIZE = INST_TMP2_RAM_DATA_W; +const INST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_TMP2_RAM_WORD_PARTITION_SIZE, INST_TMP2_RAM_DATA_W); + const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; const HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; @@ -1550,6 +1570,11 @@ proc ZstdDecoderInst { type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; @@ -1604,6 +1629,11 @@ proc ZstdDecoderInst { tmp_wr_req_s: chan out, tmp_wr_resp_r: chan in, + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + fse_rd_req_s: chan[u32:6] out, fse_rd_resp_r: chan[u32:6] in, fse_wr_req_s: chan[u32:6] out, @@ -1674,6 +1704,7 @@ proc ZstdDecoderInst { INST_HB_ADDR_W, INST_HB_DATA_W, INST_HB_NUM_PARTITIONS, INST_HB_SIZE_KB, INST_DPD_RAM_ADDR_W, INST_DPD_RAM_DATA_W, INST_DPD_RAM_NUM_PARTITIONS, INST_TMP_RAM_ADDR_W, INST_TMP_RAM_DATA_W, INST_TMP_RAM_NUM_PARTITIONS, + INST_TMP2_RAM_ADDR_W, INST_TMP2_RAM_DATA_W, INST_TMP2_RAM_NUM_PARTITIONS, INST_FSE_RAM_ADDR_W, INST_FSE_RAM_DATA_W, INST_FSE_RAM_NUM_PARTITIONS, INST_HISTORY_BUFFER_SIZE_KB, INST_AXI_CHAN_N, @@ -1687,6 +1718,8 @@ proc ZstdDecoderInst { dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, + tmp2_wr_req_s, tmp2_wr_resp_r, fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, litbuf_rd_req_s, litbuf_rd_resp_r, diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 70c1969973..43c49b2a01 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -71,9 +71,9 @@ const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); const TEST_FSE_RAM_DATA_W = u32:32; -const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); -const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W; const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); @@ -84,6 +84,13 @@ const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); +const TEST_TMP2_RAM_DATA_W = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_W = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_W; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_W); + // Huffman weights memory parameters const HUFFMAN_WEIGHTS_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; @@ -172,6 +179,11 @@ proc ZstdDecoderTest { type TmpRamWrReq = ram::WriteReq; type TmpRamWrResp = ram::WriteResp; + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; @@ -381,6 +393,17 @@ proc ZstdDecoderTest { tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, ); + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_SIZE, TEST_TMP2_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s, + ); + // FSE RAMs let (fse_rd_req_s, fse_rd_req_r) = chan[u32:6]("fse_rd_req"); let (fse_rd_resp_s, fse_rd_resp_r) = chan[u32:6]("fse_rd_resp"); @@ -476,6 +499,7 @@ proc ZstdDecoderTest { TEST_HB_ADDR_W, TEST_HB_DATA_W, TEST_HB_NUM_PARTITIONS, TEST_HB_SIZE_KB, TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_ADDR_W, TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_NUM_PARTITIONS, TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, HISTORY_BUFFER_SIZE_KB, AXI_CHAN_N, >( @@ -488,6 +512,8 @@ proc ZstdDecoderTest { dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, + tmp2_wr_req_s, tmp2_wr_resp_r, // Channels for accessing FSE tables with muxed default FSE tables [ll_def_fse_rd_req_s, fse_rd_req_s[1], ml_def_fse_rd_req_s, fse_rd_req_s[3], of_def_fse_rd_req_s, fse_rd_req_s[5]], From 73da53983648708e51256ba8ea780b0fe509fafa Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 16 Jan 2025 14:48:44 +0100 Subject: [PATCH 55/85] Add test frame for compressed fse tables Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 5 +++-- xls/modules/zstd/comp_frame_fse_comp.x | 21 +++++++++++++++++++++ xls/modules/zstd/comp_frame_huffman.x | 0 xls/modules/zstd/zstd_dec_test.x | 5 +++-- 4 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 xls/modules/zstd/comp_frame_fse_comp.x mode change 100755 => 100644 xls/modules/zstd/comp_frame_huffman.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index d8f9a033ff..e3f078fc00 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1276,9 +1276,10 @@ xls_dslx_test( srcs = [ "zstd_dec.x", "zstd_dec_test.x", - # "zstd_frame_testcases.x", - # "comp_frame.x", + "zstd_frame_testcases.x", + "comp_frame.x", "comp_frame_huffman.x", + "comp_frame_fse_comp.x", ], tags = ["manual"], deps = zstd_dec_deps, diff --git a/xls/modules/zstd/comp_frame_fse_comp.x b/xls/modules/zstd/comp_frame_fse_comp.x new file mode 100644 index 0000000000..1eb07c06e7 --- /dev/null +++ b/xls/modules/zstd/comp_frame_fse_comp.x @@ -0,0 +1,21 @@ +pub struct DataArray{ + data: uN[BITS_PER_WORD][LENGTH], + length: u32, + array_length: u32 +} +pub const FRAMES:DataArray< + u32:64, + u32:9 +>[1] = [DataArray<64, 9>{ + length: u32:66, + array_length: u32:9, + data: uN[64][9]:[uN[64]:0x00545084fd2fb528, uN[64]:0x4236d000018d0000, uN[64]:0x1d98357537f4050f, uN[64]:0x8d92b5aed6d7791b, uN[64]:0x51538ed729019574, uN[64]:0x701101fb8611a803, uN[64]:0x8acfff857107d159, uN[64]:0x548604b38e0a63fd, uN[64]:0xc551] +}]; +pub const DECOMPRESSED_FRAMES:DataArray< + u32:64, + u32:11 +>[1] = [DataArray<64, 11>{ + length: u32:84, + array_length: u32:11, + data: uN[64][11]:[uN[64]:0x373737f4050f4236, uN[64]:0x3737373737373737, uN[64]:0x3737373737373737, uN[64]:0x3737373737373737, uN[64]:0x373737f4050f4237, uN[64]:0x3737373737373737, uN[64]:0x3737373737373737, uN[64]:0x3737373737373737, uN[64]:0xd6d7791b1d983575, uN[64]:0x290195748d92b5ae, uN[64]:0x51538ed7] +}]; diff --git a/xls/modules/zstd/comp_frame_huffman.x b/xls/modules/zstd/comp_frame_huffman.x old mode 100755 new mode 100644 diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 43c49b2a01..9b2f2016df 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -29,8 +29,9 @@ import xls.modules.zstd.literals_buffer; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.ram_mux; // import xls.modules.zstd.zstd_frame_testcases as comp_frame; -// import xls.modules.zstd.comp_frame; -import xls.modules.zstd.comp_frame_huffman as comp_frame; +// import xls.modules.zstd.comp_frame_huffman as comp_frame; +// import xls.modules.zstd.comp_frame_fse_comp as comp_frame; +import xls.modules.zstd.comp_frame; const TEST_WINDOW_LOG_MAX = u32:30; From 6044dcdb41fb0ae171f3e5cbb40080a535642cc4 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 20 Jan 2025 13:30:39 +0100 Subject: [PATCH 56/85] modules/zstd/zstd_dec: don't use channel arrays for FSE tables access Internal-tag: [#71791] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/zstd_dec.x | 49 ++++++++++++++++++++++++-------- xls/modules/zstd/zstd_dec_test.x | 8 +++--- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index a7c2a9faba..31ab2d643f 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -1096,10 +1096,33 @@ pub proc ZstdDecoder< tmp2_wr_req_s: chan out, tmp2_wr_resp_r: chan in, - fse_rd_req_s: chan[u32:6] out, - fse_rd_resp_r: chan[u32:6] in, - fse_wr_req_s: chan[u32:6] out, - fse_wr_resp_r: chan[u32:6] in, + ll_def_fse_rd_req_s: chan out, + ll_fse_rd_req_s: chan out, + ml_def_fse_rd_req_s: chan out, + ml_fse_rd_req_s: chan out, + of_def_fse_rd_req_s: chan out, + of_fse_rd_req_s: chan out, + + ll_def_fse_rd_resp_r: chan in, + ll_fse_rd_resp_r: chan in, + ml_def_fse_rd_resp_r: chan in, + ml_fse_rd_resp_r: chan in, + of_def_fse_rd_resp_r: chan in, + of_fse_rd_resp_r: chan in, + + ll_def_fse_wr_req_s: chan out, + ll_fse_wr_req_s: chan out, + ml_def_fse_wr_req_s: chan out, + ml_fse_wr_req_s: chan out, + of_def_fse_wr_req_s: chan out, + of_fse_wr_req_s: chan out, + + ll_def_fse_wr_resp_r: chan in, + ll_fse_wr_resp_r: chan in, + ml_def_fse_wr_resp_r: chan in, + ml_fse_wr_resp_r: chan in, + of_def_fse_wr_resp_r: chan in, + of_fse_wr_resp_r: chan in, litbuf_rd_req_s: chan[u32:8] out, litbuf_rd_resp_r: chan[u32:8] in, @@ -1285,12 +1308,12 @@ pub proc ZstdDecoder< dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, - fse_rd_req_s[0], fse_rd_resp_r[0], fse_wr_req_s[0], fse_wr_resp_r[0], - fse_rd_req_s[1], fse_rd_resp_r[1], fse_wr_req_s[1], fse_wr_resp_r[1], - fse_rd_req_s[2], fse_rd_resp_r[2], fse_wr_req_s[2], fse_wr_resp_r[2], - fse_rd_req_s[3], fse_rd_resp_r[3], fse_wr_req_s[3], fse_wr_resp_r[3], - fse_rd_req_s[4], fse_rd_resp_r[4], fse_wr_req_s[4], fse_wr_resp_r[4], - fse_rd_req_s[5], fse_rd_resp_r[5], fse_wr_req_s[5], fse_wr_resp_r[5], + ll_def_fse_rd_req_s, ll_def_fse_rd_resp_r, ll_def_fse_wr_req_s, ll_def_fse_wr_resp_r, + ll_fse_rd_req_s, ll_fse_rd_resp_r, ll_fse_wr_req_s, ll_fse_wr_resp_r, + ml_def_fse_rd_req_s, ml_def_fse_rd_resp_r, ml_def_fse_wr_req_s, ml_def_fse_wr_resp_r, + ml_fse_rd_req_s, ml_fse_rd_resp_r, ml_fse_wr_req_s, ml_fse_wr_resp_r, + of_def_fse_rd_req_s, of_def_fse_rd_resp_r, of_def_fse_wr_req_s, of_def_fse_wr_resp_r, + of_fse_rd_req_s, of_fse_rd_resp_r, of_fse_wr_req_s, of_fse_wr_resp_r, // LITERALS DECODING @@ -1720,8 +1743,10 @@ proc ZstdDecoderInst { tmp_wr_req_s, tmp_wr_resp_r, tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, - fse_rd_req_s, fse_rd_resp_r, - fse_wr_req_s, fse_wr_resp_r, + fse_rd_req_s[0], fse_rd_req_s[1], fse_rd_req_s[2], fse_rd_req_s[3], fse_rd_req_s[4], fse_rd_req_s[5], + fse_rd_resp_r[0], fse_rd_resp_r[1], fse_rd_resp_r[2], fse_rd_resp_r[3], fse_rd_resp_r[4], fse_rd_resp_r[5], + fse_wr_req_s[0], fse_wr_req_s[1], fse_wr_req_s[2], fse_wr_req_s[3], fse_wr_req_s[4], fse_wr_req_s[5], + fse_wr_resp_r[0], fse_wr_resp_r[1], fse_wr_resp_r[2], fse_wr_resp_r[3], fse_wr_resp_r[4], fse_wr_resp_r[5], litbuf_rd_req_s, litbuf_rd_resp_r, litbuf_wr_req_s, litbuf_wr_resp_r, huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 9b2f2016df..92aac6a0f6 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -517,10 +517,10 @@ proc ZstdDecoderTest { tmp2_wr_req_s, tmp2_wr_resp_r, // Channels for accessing FSE tables with muxed default FSE tables - [ll_def_fse_rd_req_s, fse_rd_req_s[1], ml_def_fse_rd_req_s, fse_rd_req_s[3], of_def_fse_rd_req_s, fse_rd_req_s[5]], - [ll_def_fse_rd_resp_r, fse_rd_resp_r[1], ml_def_fse_rd_resp_r, fse_rd_resp_r[3], of_def_fse_rd_resp_r, fse_rd_resp_r[5]], - [ll_def_fse_wr_req_s, fse_wr_req_s[1], ml_def_fse_wr_req_s, fse_wr_req_s[3], of_def_fse_wr_req_s, fse_wr_req_s[5]], - [ll_def_fse_wr_resp_r, fse_wr_resp_r[1], ml_def_fse_wr_resp_r, fse_wr_resp_r[3], of_def_fse_wr_resp_r, fse_wr_resp_r[5]], + ll_def_fse_rd_req_s, fse_rd_req_s[1], ml_def_fse_rd_req_s, fse_rd_req_s[3], of_def_fse_rd_req_s, fse_rd_req_s[5], + ll_def_fse_rd_resp_r, fse_rd_resp_r[1], ml_def_fse_rd_resp_r, fse_rd_resp_r[3], of_def_fse_rd_resp_r, fse_rd_resp_r[5], + ll_def_fse_wr_req_s, fse_wr_req_s[1], ml_def_fse_wr_req_s, fse_wr_req_s[3], of_def_fse_wr_req_s, fse_wr_req_s[5], + ll_def_fse_wr_resp_r, fse_wr_resp_r[1], ml_def_fse_wr_resp_r, fse_wr_resp_r[3], of_def_fse_wr_resp_r, fse_wr_resp_r[5], litbuf_rd_req_s, litbuf_rd_resp_r, litbuf_wr_req_s, litbuf_wr_resp_r, From c425bc8fee8d02926ef9596677be0228159834fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Ob=C5=82onczek?= Date: Mon, 20 Jan 2025 15:48:01 +0000 Subject: [PATCH 57/85] Fix sequence decoding with predefined offset table, add regression test --- xls/modules/zstd/sequence_dec.x | 143 +++++++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 3 deletions(-) diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x index 294c4855c8..a33911ef3b 100644 --- a/xls/modules/zstd/sequence_dec.x +++ b/xls/modules/zstd/sequence_dec.x @@ -540,7 +540,7 @@ pub proc SequenceDecoderCtrl< let (tok_ml_demux, _) = recv_if(tok_ml_demux, ml_demux_resp_r, !zero_sequences, ()); // Set proper OF lookup through demux - let of_demux_sel = (conf_resp.header.match_mode != CompressionMode::PREDEFINED); + let of_demux_sel = (conf_resp.header.offset_mode != CompressionMode::PREDEFINED); let tok_of_demux = send_if(tok_recv_scd, of_demux_req_s, !zero_sequences, of_demux_sel); // Receive response from OF lookup demux let (tok_of_demux, _) = recv_if(tok_of_demux, of_demux_resp_r, !zero_sequences, ()); @@ -1194,7 +1194,7 @@ const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP2_RAM_WORD_PART // - sequences section as it appears in memory // - expected output size // - expected output -const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[2] = [ +const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[3] = [ // Test case 0 // raw literals with sequences with 3 predefined tables // ./decodecorpus -pdata2.out -odata2.in -s35304 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 @@ -1457,7 +1457,144 @@ const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[2] = [ zero!(), ... ] ), - // Test case 2 (WARNING: long test running time) + // test case 2 + // LL - compressed, OF - predefined, ML - compressed + ( + u32:25, + u64[32]:[ + u64:0x0, u64:0x0, + u64:0xDEF00EB70AB0880A, + u64:0xE428228113B02D01, + u64:0x748A16EBB16B9BEC, + u64:0x000000000000003E, + u64:0x0, ... + ], + u32:20, + SequenceExecutorPacket[64]:[ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0002, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0005, + content: u64:0x0004, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0003, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x000d, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0002, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0003, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x000d, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0002, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x0017, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0019, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x0021, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0020, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0006, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x001b, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0004, + content: u64:0x000d, + last: true, + }, + zero!(), ... + ] + ), + // Test case 3 (WARNING: long test running time) // 3 custom lookup tables with accuracy log 9, 8 and 9 // decodecorpus -pdata.out -odata.in -s58745 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 // ( From d016956bd99c0065404b52471ab1e3065fb66b09 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 22 Jan 2025 21:56:29 +0100 Subject: [PATCH 58/85] Add support for RLE and Repeated fse tables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Krzysztof Obłonczek Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 61 +- xls/modules/zstd/common.x | 11 + xls/modules/zstd/comp_lookup_dec.x | 1832 +++++++++++++++++ xls/modules/zstd/fse_lookup_dec.x | 1576 ++------------ xls/modules/zstd/fse_table_creator.x | 8 +- xls/modules/zstd/refilling_shift_buffer_mux.x | 252 +++ xls/modules/zstd/rle_lookup_dec.x | 190 ++ xls/modules/zstd/sequence_dec.x | 231 ++- 8 files changed, 2711 insertions(+), 1450 deletions(-) create mode 100644 xls/modules/zstd/comp_lookup_dec.x create mode 100644 xls/modules/zstd/refilling_shift_buffer_mux.x create mode 100644 xls/modules/zstd/rle_lookup_dec.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index e3f078fc00..4fc18e5743 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1346,9 +1346,9 @@ place_and_route( ) xls_dslx_library( - name = "fse_lookup_dec_dslx", + name = "comp_lookup_dec_dslx", srcs = [ - "fse_lookup_dec.x", + "comp_lookup_dec.x", ], deps = [ "//xls/examples:ram_dslx", @@ -1362,6 +1362,45 @@ xls_dslx_library( ] ) +xls_dslx_test( + name = "comp_lookup_dec_dslx_test", + library = ":comp_lookup_dec_dslx", + tags = ["manual"], +) + +xls_dslx_library( + name = "rle_lookup_dec_dslx", + srcs = [ + "rle_lookup_dec.x", + ], + deps = [ + ":common_dslx", + "//xls/examples:ram_dslx", + "//xls/modules/zstd:refilling_shift_buffer_dslx", + "//xls/modules/zstd:fse_table_creator_dslx", + ] +) + +xls_dslx_test( + name = "rle_lookup_dec_dslx_test", + library = ":rle_lookup_dec_dslx", + tags = ["manual"], +) + +xls_dslx_library( + name = "fse_lookup_dec_dslx", + srcs = [ + "fse_lookup_dec.x", + ], + deps = [ + ":comp_lookup_dec_dslx", + ":rle_lookup_dec_dslx", + ":ram_mux_dslx", + ":refilling_shift_buffer_dslx", + ":refilling_shift_buffer_mux_dslx", + ] +) + xls_dslx_test( name = "fse_lookup_dec_dslx_test", library = ":fse_lookup_dec_dslx", @@ -1985,12 +2024,13 @@ xls_dslx_library( ], deps = [ ":sequence_conf_dec_dslx", - ":fse_lookup_dec_dslx", + ":comp_lookup_dec_dslx", ":ram_demux3_dslx", ":common_dslx", ":fse_dec_dslx", ":ram_mux_dslx", ":fse_table_creator_dslx", + ":fse_lookup_dec_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", "//xls/modules/zstd:refilling_shift_buffer_dslx", @@ -3166,3 +3206,18 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +xls_dslx_library( + name = "refilling_shift_buffer_mux_dslx", + srcs = [ + "refilling_shift_buffer_mux.x" + ], + deps = [ + ":refilling_shift_buffer_dslx" + ] +) + +xls_dslx_test( + name = "refilling_shift_buffer_mux_dslx_test", + library = ":refilling_shift_buffer_mux_dslx", +) diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 725d74a713..8c1a48b143 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -297,3 +297,14 @@ pub struct LiteralsBufferCtrl { last: bool, } +pub enum LookupDecoderStatus: u1 { + OK = u1:0, + ERROR = u1:1, +} + +pub struct LookupDecoderReq {} + +pub struct LookupDecoderResp { + status: LookupDecoderStatus, + accuracy_log: FseAccuracyLog, +} diff --git a/xls/modules/zstd/comp_lookup_dec.x b/xls/modules/zstd/comp_lookup_dec.x new file mode 100644 index 0000000000..628326edf9 --- /dev/null +++ b/xls/modules/zstd/comp_lookup_dec.x @@ -0,0 +1,1832 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.fse_table_creator; +import xls.modules.zstd.refilling_shift_buffer; +import xls.modules.zstd.fse_proba_freq_dec; +import xls.modules.shift_buffer.shift_buffer; + +type AccuracyLog = common::FseAccuracyLog; + +pub proc CompLookupDecoder< + AXI_DATA_W: u32, + DPD_RAM_DATA_W: u32, DPD_RAM_ADDR_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_DATA_W: u32, TMP_RAM_ADDR_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_DATA_W: u32, TMP2_RAM_ADDR_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, + FSE_RAM_DATA_W: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, +> { + type Req = common::LookupDecoderReq; + type Resp = common::LookupDecoderResp; + type Status = common::LookupDecoderStatus; + + type FseTableStart = fse_table_creator::FseStartMsg; + + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type FsePFDecReq = fse_proba_freq_dec::FseProbaFreqDecoderReq; + type FsePFDecResp = fse_proba_freq_dec::FseProbaFreqDecoderResp; + type FsePFDecStatus = fse_proba_freq_dec::FseProbaFreqDecoderStatus; + + req_r: chan in; + resp_s: chan out; + + fse_pf_dec_req_s: chan out; + fse_pf_dec_resp_r: chan in; + fse_table_start_s: chan out; + fse_table_finish_r: chan<()> in; + + init {} + + config( + req_r: chan in, + resp_s: chan out, + + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, + + buffer_ctrl_s: chan out, + buffer_data_out_r: chan in, + ) { + const CHANNEL_DEPTH = u32:1; + + let (fse_table_start_s, fse_table_start_r) = chan("fse_table_start"); + let (fse_table_finish_s, fse_table_finish_r) = chan<(), CHANNEL_DEPTH>("fse_table_finish"); + + spawn fse_table_creator::FseTableCreator< + DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, + TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_DATA_W, TMP2_RAM_ADDR_W, TMP2_RAM_NUM_PARTITIONS, + >( + fse_table_start_r, fse_table_finish_s, + dpd_rd_req_s, dpd_rd_resp_r, + fse_wr_req_s, fse_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + ); + + let (fse_pf_dec_req_s, fse_pf_dec_req_r) = chan("fse_pf_dec_req"); + let (fse_pf_dec_resp_s, fse_pf_dec_resp_r) = chan("fse_pf_dec_resp"); + + spawn fse_proba_freq_dec::FseProbaFreqDecoder< + DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + >( + fse_pf_dec_req_r, fse_pf_dec_resp_s, + buffer_ctrl_s, buffer_data_out_r, + dpd_wr_req_s, dpd_wr_resp_r, + ); + + ( + req_r, resp_s, + fse_pf_dec_req_s, fse_pf_dec_resp_r, + fse_table_start_s, fse_table_finish_r, + ) + } + + next(state: ()) { + let tok = join(); + let (tok, start_req) = recv(tok, req_r); + + // start FSE probability frequency decoder + let tok = send(tok, fse_pf_dec_req_s, FsePFDecReq {}); + + // wait for completion from FSE probability frequency decoder + let (tok, pf_dec_res) = recv(tok, fse_pf_dec_resp_r); + trace_fmt!("FSE prob decoded: {:#x}", pf_dec_res); + + let pf_dec_ok = pf_dec_res.status == FsePFDecStatus::OK; + // run FSE Table creation conditional or previous processing succeeding + let tok = send_if(tok, fse_table_start_s, pf_dec_ok, FseTableStart { + num_symbs: pf_dec_res.symbol_count, + accuracy_log: pf_dec_res.accuracy_log, + }); + // wait for completion from FSE table creator + let (tok, ()) = recv_if(tok, fse_table_finish_r, pf_dec_ok, ()); + trace_fmt!("FSE table created"); + + let resp = if pf_dec_ok { + Resp { status: Status::OK, accuracy_log: pf_dec_res.accuracy_log } + } else { + Resp { status: Status::ERROR, ..zero!() } + }; + send(tok, resp_s, resp); + } +} + + +const TEST_AXI_DATA_WIDTH = u32:64; +const TEST_AXI_ADDR_WIDTH = u32:32; +const TEST_AXI_ID_WIDTH = u32:8; +const TEST_AXI_DEST_WIDTH = u32:8; +const TEST_SB_LENGTH_WIDTH = refilling_shift_buffer::length_width(TEST_AXI_DATA_WIDTH); + +const TEST_CASE_RAM_DATA_WIDTH = u32:64; +const TEST_CASE_RAM_SIZE = u32:256; +const TEST_CASE_RAM_ADDR_WIDTH = std::clog2(TEST_CASE_RAM_SIZE); +const TEST_CASE_RAM_WORD_PARTITION_SIZE = TEST_CASE_RAM_DATA_WIDTH; +const TEST_CASE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_CASE_RAM_DATA_WIDTH); +const TEST_CASE_RAM_BASE_ADDR = u32:0; + +const TEST_DPD_RAM_DATA_WIDTH = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_WIDTH = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_WIDTH; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_WIDTH); + +const TEST_FSE_RAM_DATA_WIDTH = u32:32; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; +const TEST_FSE_RAM_ADDR_WIDTH = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_WIDTH; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_WIDTH); + +const TEST_TMP_RAM_DATA_WIDTH = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_WIDTH = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_WIDTH; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_WIDTH); + +const TEST_TMP2_RAM_DATA_WIDTH = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_WIDTH = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_WIDTH; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_WIDTH); + +const TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_RAM_INITIALIZED = true; + +type FseTableRecord = common::FseTableRecord; + +const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], common::LookupDecoderResp)[12] = [ + ( + u64[64]:[u64:0x72AAAAABBB1D25C0, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x1861862062081932, u64:0xC18628A106184184, u64:0x850720FACC49238, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x40 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + ), + ( + u64[64]:[u64:0x60C3082082085072, u64:0x1C06F8077D850F20, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x7, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x70 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x50 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x58 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + ), + ( + u64[64]:[u64:0x41081C158003A5D0, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x17 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x1101141108088A1, u64:0xA210842108421011, u64:0xAC90E792007A5B4, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x6, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x8 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:6 } + ), + ( + u64[64]:[u64:0x4AF830AC90E7920, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xa }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xe }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0xa }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0xF47FFEBBFF1D25C0, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0xA84DF134544CA40, u64:0xEEC609988403B0C, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x8 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x38100EEC60998840, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0xc }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x6B1CA24D0CE43810, u64:0x6651065104A4DFFD, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x3, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x3, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x24, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x4, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x24, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x4, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x8 }, + FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x8 }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + ), + ( + u64[64]:[u64:0x604FC0502602814, u64:0xE030505040131FF6, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x100 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x104 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x108 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x110 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x114 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x118 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x11c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x120 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x124 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x128 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x12c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x130 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x134 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x138 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x13c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x140 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x144 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x148 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x150 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x154 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x158 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x15c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x160 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x164 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x168 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x16c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x170 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x174 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x178 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x17c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x180 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x184 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x188 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x190 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x194 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x198 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x19c }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1ac }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1bc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1cc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1dc }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e8 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1ec }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f0 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f4 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f8 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1fc }, + FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1fc }, + FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1fc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1fc }, + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:9 } + ), + ( + u64[64]:[u64:0x140FE03050504013, u64:0, ...], + FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x20 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x24 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x28 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x2c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x30 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x34 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x38 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x3c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x44 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x48 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x50 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x54 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x5c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x60 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x64 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x68 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x6c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x70 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x74 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x78 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x7c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x80 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x84 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x88 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x90 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x94 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x98 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x9c }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xac }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xbc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xcc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xdc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xfc }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xec }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf0 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf4 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf8 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, + zero!(), ... + ], + common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:8 } + ), +]; + +#[test_proc] +proc CompLookupDecoderTest { + type Req = common::LookupDecoderReq; + type Resp = common::LookupDecoderResp; + type Status = common::LookupDecoderStatus; + + type MemReaderReq = mem_reader::MemReaderReq; + type MemReaderResp = mem_reader::MemReaderResp; + + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + + type TestcaseRamRdReq = ram::ReadReq; + type TestcaseRamRdResp = ram::ReadResp; + type TestcaseRamWrReq = ram::WriteReq; + type TestcaseRamWrResp = ram::WriteResp; + + type RefillStartReq = refilling_shift_buffer::RefillStart; + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type AxiR = axi::AxiR; + type AxiAr = axi::AxiAr; + + terminator: chan out; + req_s: chan out; + resp_r: chan in; + fse_rd_req_s: chan out; + fse_rd_resp_r: chan in; + fse_wr_req_s: chan out; + fse_wr_resp_r: chan in; + testcase_wr_req_s: chan out; + testcase_wr_resp_r: chan in; + refill_req_s: chan out; + stop_flush_req_s: chan<()> out; + flushing_done_r: chan<()> in; + + config(terminator: chan out) { + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + + let (testcase_rd_req_s, testcase_rd_req_r) = chan("testcase_rd_req"); + let (testcase_rd_resp_s, testcase_rd_resp_r) = chan("testcase_rd_resp"); + let (testcase_wr_req_s, testcase_wr_req_r) = chan("testcase_wr_req"); + let (testcase_wr_resp_s, testcase_wr_resp_r) = chan("testcase_wr_resp"); + + let (buffer_ctrl_s, buffer_ctrl_r) = chan("buffer_ctrl"); + let (buffer_data_out_s, buffer_data_out_r) = chan("buffer_data_out"); + + spawn CompLookupDecoder< + TEST_AXI_DATA_WIDTH, + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_ADDR_WIDTH, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_ADDR_WIDTH, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_ADDR_WIDTH, TEST_TMP2_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_ADDR_WIDTH, TEST_FSE_RAM_NUM_PARTITIONS, + >( + req_r, resp_s, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_wr_req_s, fse_wr_resp_r, + buffer_ctrl_s, buffer_data_out_r, + ); + + spawn ram::RamModel< + TEST_DPD_RAM_DATA_WIDTH, TEST_DPD_RAM_SIZE, TEST_DPD_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_WIDTH, TEST_FSE_RAM_SIZE, TEST_FSE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(fse_rd_req_r, fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s); + + spawn ram::RamModel< + TEST_TMP_RAM_DATA_WIDTH, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_WIDTH, TEST_TMP2_RAM_SIZE, TEST_TMP2_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s); + + spawn ram::RamModel< + TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, + >(testcase_rd_req_r, testcase_rd_resp_s, testcase_wr_req_r, testcase_wr_resp_s); + + let (testcase_axi_r_s, testcase_axi_r_r) = chan("testcase_axi_r"); + let (testcase_axi_ar_s, testcase_axi_ar_r) = chan("testcase_axi_ar"); + + spawn axi_ram::AxiRamReader< + TEST_AXI_ADDR_WIDTH, TEST_AXI_DATA_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH, + TEST_CASE_RAM_SIZE, TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_WIDTH, + TEST_CASE_RAM_ADDR_WIDTH, TEST_CASE_RAM_NUM_PARTITIONS, + >(testcase_axi_ar_r, testcase_axi_r_s, testcase_rd_req_s, testcase_rd_resp_r); + + spawn mem_reader::MemReader< + TEST_AXI_DATA_WIDTH, TEST_AXI_ADDR_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH + >(mem_rd_req_r, mem_rd_resp_s, testcase_axi_ar_s, testcase_axi_r_r); + + let (refill_req_s, refill_req_r) = chan("start_req"); + let (stop_flush_req_s, stop_flush_req_r) = chan<()>("stop_flush_req"); + let (flushing_done_s, flushing_done_r) = chan<()>("flushing_done"); + + spawn refilling_shift_buffer::RefillingShiftBuffer( + mem_rd_req_s, mem_rd_resp_r, + refill_req_r, stop_flush_req_r, + buffer_ctrl_r, buffer_data_out_s, + flushing_done_s, + ); + + ( + terminator, req_s, resp_r, fse_rd_req_s, fse_rd_resp_r, + fse_wr_req_s, fse_wr_resp_r, testcase_wr_req_s, testcase_wr_resp_r, + refill_req_s, stop_flush_req_s, flushing_done_r, + ) + } + + init {} + + next(_: ()) { + let tok = join(); + // This has to be outside of unroll_for!, otherwise typechecker reports type mismatch on identical types + let req_start = Req {}; + + let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(COMP_LOOKUP_DECODER_TESTCASES)) { + let (input, output, resp_ok) = COMP_LOOKUP_DECODER_TESTCASES[test_i]; + + trace_fmt!("Loading testcase {:x}", test_i); + let tok = for ((i, input_data), tok): ((u32, u64), token) in enumerate(input) { + let req = TestcaseRamWrReq { + addr: i as uN[TEST_CASE_RAM_ADDR_WIDTH], + data: input_data as uN[TEST_CASE_RAM_DATA_WIDTH], + mask: uN[TEST_CASE_RAM_NUM_PARTITIONS]:0x1 + }; + let tok = send(tok, testcase_wr_req_s, req); + let (tok, _) = recv(tok, testcase_wr_resp_r); + tok + }(tok); + + trace_fmt!("Running FSE lookup decoder on testcase {:x}", test_i); + let tok = send(tok, refill_req_s, RefillStartReq { + start_addr: uN[TEST_AXI_ADDR_WIDTH]:0x0 + }); + let tok = send(tok, req_s, req_start); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, resp_ok); + + let tok = for ((i, output_data), tok): ((u32, FseTableRecord), token) in enumerate(output) { + let req = FseRamRdReq { + addr: i as uN[TEST_FSE_RAM_ADDR_WIDTH], + mask: std::unsigned_max_value(), + }; + let tok = send(tok, fse_rd_req_s, req); + let (tok, resp) = recv(tok, fse_rd_resp_r); + assert_eq(fse_table_creator::bits_to_fse_record(resp.data), output_data); + + // erase output for next test to start with clean memory + let clear_req = FseRamWrReq { + addr: i as uN[TEST_FSE_RAM_ADDR_WIDTH], + mask: std::unsigned_max_value(), + data: uN[TEST_FSE_RAM_DATA_WIDTH]:0x0, + }; + let tok = send(tok, fse_wr_req_s, clear_req); + let (tok, _) = recv(tok, fse_wr_resp_r); + tok + }(tok); + + let tok = send(tok, stop_flush_req_s, ()); + let (tok, ()) = recv(tok, flushing_done_r); + + tok + }(tok); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/fse_lookup_dec.x b/xls/modules/zstd/fse_lookup_dec.x index 7518c0d2bc..581dcac5d2 100644 --- a/xls/modules/zstd/fse_lookup_dec.x +++ b/xls/modules/zstd/fse_lookup_dec.x @@ -23,20 +23,16 @@ import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.fse_proba_freq_dec; import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.comp_lookup_dec; +import xls.modules.zstd.rle_lookup_dec; +import xls.modules.zstd.refilling_shift_buffer_mux; +import xls.modules.zstd.ram_mux; type AccuracyLog = common::FseAccuracyLog; -pub enum FseLookupDecoderStatus: u1 { - OK = 0, - ERROR = 1, -} - -pub struct FseLookupDecoderReq {} - -pub struct FseLookupDecoderResp { - status: FseLookupDecoderStatus, - accuracy_log: common::FseAccuracyLog -} +pub struct FseLookupDecoderReq { is_rle: bool } +pub type FseLookupDecoderStatus = common::LookupDecoderStatus; +pub type FseLookupDecoderResp = common::LookupDecoderResp; pub proc FseLookupDecoder< AXI_DATA_W: u32, @@ -48,15 +44,14 @@ pub proc FseLookupDecoder< > { type Req = FseLookupDecoderReq; type Resp = FseLookupDecoderResp; - type Status = FseLookupDecoderStatus; - - type FseTableStart = fse_table_creator::FseStartMsg; - type DpdRamWrReq = ram::WriteReq; - type DpdRamWrResp = ram::WriteResp; type DpdRamRdReq = ram::ReadReq; type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; type FseRamWrReq = ram::WriteReq; type FseRamWrResp = ram::WriteResp; @@ -73,23 +68,38 @@ pub proc FseLookupDecoder< type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; - type FsePFDecReq = fse_proba_freq_dec::FseProbaFreqDecoderReq; - type FsePFDecResp = fse_proba_freq_dec::FseProbaFreqDecoderResp; - type FsePFDecStatus = fse_proba_freq_dec::FseProbaFreqDecoderStatus; + type LookupDecoderReq = common::LookupDecoderReq; + type LookupDecoderResp = common::LookupDecoderResp; - req_r: chan in; - resp_s: chan out; - - fse_pf_dec_req_s: chan out; - fse_pf_dec_resp_r: chan in; - fse_table_start_s: chan out; - fse_table_finish_r: chan<()> in; init {} + fse_lookup_dec_req_r: chan in; + fse_lookup_dec_resp_s: chan out; + + comp_lookup_req_s: chan out; + comp_lookup_resp_r: chan in; + + rle_lookup_req_s: chan out; + rle_lookup_resp_r: chan in; + + shift_buffer_sel_req_s: chan out; + shift_buffer_sel_resp_r: chan<()> in; + + fse_ram_sel_req_s: chan out; + + fse_rd_req0_s: chan out; + fse_rd_resp0_r: chan in; + + fse_rd_req1_s: chan out; + fse_rd_resp1_r: chan in; + + fse_rd_req_r: chan in; + fse_rd_resp_s: chan out; + config( - req_r: chan in, - resp_s: chan out, + fse_lookup_dec_req_r: chan in, + fse_lookup_dec_resp_s: chan out, dpd_rd_req_s: chan out, dpd_rd_resp_r: chan in, @@ -109,72 +119,130 @@ pub proc FseLookupDecoder< fse_wr_req_s: chan out, fse_wr_resp_r: chan in, - buffer_ctrl_s: chan out, - buffer_data_out_r: chan in, + shift_buffer_ctrl_s: chan out, + shift_buffer_data_r: chan in, ) { const CHANNEL_DEPTH = u32:1; - let (fse_table_start_s, fse_table_start_r) = chan("fse_table_start"); - let (fse_table_finish_s, fse_table_finish_r) = chan<(), CHANNEL_DEPTH>("fse_table_finish"); + let (shift_buffer_sel_req_s, shift_buffer_sel_req_r) = chan("shift_buffer_sel_req"); + let (shift_buffer_sel_resp_s, shift_buffer_sel_resp_r) = chan<(), CHANNEL_DEPTH>("shift_buffer_sel_resp"); + + let (shift_buffer_ctrl0_s, shift_buffer_ctrl0_r) = chan("shift_buffer_ctrl0"); + let (shift_buffer_data0_s, shift_buffer_data0_r) = chan("shift_buffer_data0"); + + let (shift_buffer_ctrl1_s, shift_buffer_ctrl1_r) = chan("shift_buffer_ctrl1"); + let (shift_buffer_data1_s, shift_buffer_data1_r) = chan("shift_buffer_data1"); + + spawn refilling_shift_buffer_mux::RefillingShiftBufferMux( + shift_buffer_sel_req_r, shift_buffer_sel_resp_s, + shift_buffer_ctrl0_r, shift_buffer_data0_s, + shift_buffer_ctrl1_r, shift_buffer_data1_s, + shift_buffer_ctrl_s, shift_buffer_data_r, + ); + + let (fse_ram_sel_req_s, fse_ram_sel_req_r) = chan("fse_ram_sel_req"); + + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); - spawn fse_table_creator::FseTableCreator< + let (fse_rd_req0_s, fse_rd_req0_r) = chan("fse_rd_req0"); + let (fse_rd_resp0_s, fse_rd_resp0_r) = chan("fse_rd_resp0"); + let (fse_wr_req0_s, fse_wr_req0_r) = chan("fse_wr_req0"); + let (fse_wr_resp0_s, fse_wr_resp0_r) = chan("fse_wr_resp0"); + + let (fse_rd_req1_s, fse_rd_req1_r) = chan("fse_wr_req1"); + let (fse_rd_resp1_s, fse_rd_resp1_r) = chan("fse_wr_resp1"); + let (fse_wr_req1_s, fse_wr_req1_r) = chan("fse_wr_req1"); + let (fse_wr_resp1_s, fse_wr_resp1_r) = chan("fse_wr_resp1"); + + spawn ram_mux::RamMux< + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, + >( + fse_ram_sel_req_r, + fse_rd_req0_r, fse_rd_resp0_s, fse_wr_req0_r, fse_wr_resp0_s, + fse_rd_req1_r, fse_rd_resp1_s, fse_wr_req1_r, fse_wr_resp1_s, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, + ); + + let (comp_lookup_req_s, comp_lookup_req_r) = chan("comp_lookup_req"); + let (comp_lookup_resp_s, comp_lookup_resp_r) = chan("comp_lookup_resp"); + + spawn comp_lookup_dec::CompLookupDecoder< + AXI_DATA_W, DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, - FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, TMP2_RAM_DATA_W, TMP2_RAM_ADDR_W, TMP2_RAM_NUM_PARTITIONS, + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, >( - fse_table_start_r, fse_table_finish_s, - dpd_rd_req_s, dpd_rd_resp_r, - fse_wr_req_s, fse_wr_resp_r, + comp_lookup_req_r, comp_lookup_resp_s, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + + fse_wr_req0_s, fse_wr_resp0_r, + shift_buffer_ctrl0_s, shift_buffer_data0_r, ); - let (fse_pf_dec_req_s, fse_pf_dec_req_r) = chan("fse_pf_dec_req"); - let (fse_pf_dec_resp_s, fse_pf_dec_resp_r) = chan("fse_pf_dec_resp"); + let (rle_lookup_req_s, rle_lookup_req_r) = chan("rle_lookup_req"); + let (rle_lookup_resp_s, rle_lookup_resp_r) = chan("rle_lookup_resp"); - spawn fse_proba_freq_dec::FseProbaFreqDecoder< - DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + spawn rle_lookup_dec::RleLookupDecoder< + AXI_DATA_W, FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, >( - fse_pf_dec_req_r, fse_pf_dec_resp_s, - buffer_ctrl_s, buffer_data_out_r, - dpd_wr_req_s, dpd_wr_resp_r, + rle_lookup_req_r, rle_lookup_resp_s, + fse_wr_req1_s, fse_wr_resp1_r, + shift_buffer_ctrl1_s, shift_buffer_data1_r, ); ( - req_r, resp_s, - fse_pf_dec_req_s, fse_pf_dec_resp_r, - fse_table_start_s, fse_table_finish_r, + fse_lookup_dec_req_r, fse_lookup_dec_resp_s, + comp_lookup_req_s, comp_lookup_resp_r, + rle_lookup_req_s, rle_lookup_resp_r, + + shift_buffer_sel_req_s, shift_buffer_sel_resp_r, + fse_ram_sel_req_s, + + fse_rd_req0_s, fse_rd_resp0_r, + fse_rd_req1_s, fse_rd_resp1_r, + + fse_rd_req_r, fse_rd_resp_s, ) } next(state: ()) { - let tok = join(); - let (tok, start_req) = recv(tok, req_r); - - // start FSE probability frequency decoder - let tok = send(tok, fse_pf_dec_req_s, FsePFDecReq {}); - - // wait for completion from FSE probability frequency decoder - let (tok, pf_dec_res) = recv(tok, fse_pf_dec_resp_r); - trace_fmt!("FSE prob decoded"); - - let pf_dec_ok = pf_dec_res.status == FsePFDecStatus::OK; - // run FSE Table creation conditional or previous processing succeeding - let tok = send_if(tok, fse_table_start_s, pf_dec_ok, FseTableStart { - num_symbs: pf_dec_res.symbol_count, - accuracy_log: pf_dec_res.accuracy_log, - }); - // wait for completion from FSE table creator - let (tok, ()) = recv_if(tok, fse_table_finish_r, pf_dec_ok, ()); - trace_fmt!("FSE table created"); - - let resp = if pf_dec_ok { - Resp { status: Status::OK, accuracy_log: pf_dec_res.accuracy_log } - } else { - Resp { status: Status::ERROR, ..zero!() } - }; - send(tok, resp_s, resp); + let tok0 = join(); + + let (tok1, req) = recv(tok0, fse_lookup_dec_req_r); + + let sel = (req.is_rle == true); + let tok2_0 = send(tok1, shift_buffer_sel_req_s, sel); + let (tok3_0, _) = recv(tok2_0, shift_buffer_sel_resp_r); + + let tok2_1 = send(tok1, fse_ram_sel_req_s, sel); + // let (tok, _) = recv(tok, fse_ram_sel_resp_r); + + let tok3 = join(tok2_1, tok3_0); + + let tok4_0 = send_if(tok3, rle_lookup_req_s, req.is_rle, LookupDecoderReq {}); + let (tok5_0, rle_lookup_resp) = recv_if(tok4_0, rle_lookup_resp_r, req.is_rle, zero!()); + + let tok4_1 = send_if(tok3, comp_lookup_req_s, !req.is_rle, LookupDecoderReq {}); + let (tok5_1, comp_lookup_resp) = recv_if(tok4_1, comp_lookup_resp_r, !req.is_rle, zero!()); + + let tok5 = join(tok5_0, tok5_1); + + let resp = if req.is_rle { rle_lookup_resp } else { comp_lookup_resp }; + let tok6 = send(tok5, fse_lookup_dec_resp_s, resp); + + // unused channels + send_if(tok0, fse_rd_req0_s, false, zero!()); + recv_if(tok0, fse_rd_resp0_r, false, zero!()); + + send_if(tok0, fse_rd_req1_s, false, zero!()); + recv_if(tok0, fse_rd_resp1_r, false, zero!()); + + send_if(tok0, fse_rd_resp_s, false, zero!()); + recv_if(tok0, fse_rd_req_r, false, zero!()); } } @@ -226,1409 +294,123 @@ const TEST_RAM_INITIALIZED = true; type FseTableRecord = common::FseTableRecord; -const FSE_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], FseLookupDecoderResp)[12] = [ +const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], FseLookupDecoderReq, FseLookupDecoderResp)[5] = [ + // RLE ( - u64[64]:[u64:0x72AAAAABBB1D25C0, u64:0, ...], + u64[64]:[u64:0xA, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x0, base: u16:0x0 }, zero!(), ... ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + FseLookupDecoderReq { is_rle: true }, + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:0 } ), ( - u64[64]:[u64:0x1861862062081932, u64:0xC18628A106184184, u64:0x850720FACC49238, u64:0, ...], + u64[64]:[u64:0x2, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x4, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x70 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x40 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x0, base: u16:0x0 }, zero!(), ... ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + FseLookupDecoderReq { is_rle: true }, + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:0 } ), ( - u64[64]:[u64:0x60C3082082085072, u64:0x1C06F8077D850F20, u64:0, ...], + u64[64]:[u64:0x7, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x3, base: u16:0x70 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x48 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x3, base: u16:0x78 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x50 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x4, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x58 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x4, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x68 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x70 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x3, base: u16:0x78 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x50 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x5, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x3, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x7, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x70 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x4, base: u16:0x50 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x6, base: u16:0x40 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0xd, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x58 }, + FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x0, base: u16:0x0 }, zero!(), ... ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + FseLookupDecoderReq { is_rle: true }, + FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:0 } ), + + // COMPRESSED ( - u64[64]:[u64:0x41081C158003A5D0, u64:0, ...], + u64[64]:[u64:0x72AAAAABBB1D25C0, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, + FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x16 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x17 }, zero!(), ... ], + FseLookupDecoderReq { is_rle: false }, FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } ), ( - u64[64]:[u64:0x1101141108088A1, u64:0xA210842108421011, u64:0xAC90E792007A5B4, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xe, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x11, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xc, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x13, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xa, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x15, num_of_bits: u8:0x6, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x18, num_of_bits: u8:0x4, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x19, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x1a, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x1b, num_of_bits: u8:0x3, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x8 }, - zero!(), ... - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:6 } - ), - ( - u64[64]:[u64:0x4AF830AC90E7920, u64:0, ...], + u64[64]:[u64:0x41081C158003A5D0, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x2 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x6 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xa }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0xe }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x12 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x2 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x4 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x6 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0xa }, - zero!(), ... - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } - ), - ( - u64[64]:[u64:0xF47FFEBBFF1D25C0, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x16 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1a }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x1, base: u16:0x1e }, + FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x1 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x2 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x3 }, + FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x4 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x5 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x6 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x7 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x8 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x9 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xa }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xb }, + FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xc }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xd }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xe }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0xf }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x10 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x11 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x12 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x13 }, + FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x5, base: u16:0x0 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x14 }, FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x16 }, + FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x17 }, zero!(), ... ], + FseLookupDecoderReq { is_rle: false }, FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } ), - ( - u64[64]:[u64:0xA84DF134544CA40, u64:0xEEC609988403B0C, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x16, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x8 }, - zero!(), ... - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } - ), - ( - u64[64]:[u64:0x38100EEC60998840, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x8, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0xc }, - zero!(), ... - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } - ), - ( - u64[64]:[u64:0x6B1CA24D0CE43810, u64:0x6651065104A4DFFD, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x3, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x3, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x24, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x6, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x4, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x24, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x4, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x12, num_of_bits: u8:0x4, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x3, base: u16:0x8 }, - FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x8 }, - zero!(), ... - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } - ), - ( - u64[64]:[u64:0x604FC0502602814, u64:0xE030505040131FF6, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x100 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x100 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x100 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x104 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x104 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x104 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x108 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x100 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x108 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x10c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x108 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x104 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x10c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x10c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x108 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x110 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x110 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x110 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x114 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x114 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x110 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x114 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x118 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x118 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x118 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x11c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x11c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x114 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x11c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x120 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x118 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x120 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x124 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x120 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x11c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x124 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x124 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x120 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x128 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x128 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x128 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x124 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x12c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x12c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x128 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x12c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x130 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x130 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x130 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x134 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x134 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x12c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x134 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x138 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x130 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x138 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x13c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x138 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x134 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x13c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x13c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x138 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x140 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x140 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x140 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x13c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x144 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x144 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x140 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x148 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x144 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x148 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x144 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x148 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x14c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x148 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x14c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x14c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x150 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x150 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x150 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x154 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x154 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x154 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x150 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x158 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x158 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x158 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x154 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x15c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x15c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x158 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x160 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x15c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x160 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x15c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x160 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x164 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x160 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x164 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x164 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x168 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x168 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x168 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x16c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x164 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x16c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x16c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x168 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x170 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x170 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x170 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x16c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x174 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x174 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x170 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x178 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x174 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x178 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x174 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x178 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x17c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x178 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x17c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x17c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x180 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x17c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x180 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x184 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x180 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x180 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x184 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x188 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x184 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x188 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x18c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x184 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x188 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x18c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x188 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x18c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x190 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x190 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x190 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x194 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x190 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x194 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x194 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x198 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x194 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x198 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x19c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x198 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x198 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x19c }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x19c }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x19c }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1a8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1a8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1a8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1ac }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1a8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1ac }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1ac }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1ac }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1b8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1b8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1bc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1b8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1bc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1b8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1bc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1bc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1c8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1c8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1c8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1cc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1cc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1cc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1cc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1d8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1d8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1d8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1dc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1d8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1dc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1dc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1dc }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e4 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1e8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1e8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1e8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1e8 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1ec }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1ec }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1ec }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f0 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1ec }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f0 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f0 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f4 }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1f8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f4 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1f8 }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1f8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1f8 }, - FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x2, base: u16:0x1fc }, - FseTableRecord { symbol: u8:0x17, num_of_bits: u8:0x2, base: u16:0x1fc }, - FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1fc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1fc }, - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:9 } - ), - ( - u64[64]:[u64:0x140FE03050504013, u64:0, ...], - FseTableRecord[TEST_FSE_RAM_SIZE]:[ - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x10 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x14 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x18 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x20 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x24 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x28 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x2c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x30 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x34 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x38 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x3c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x40 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x44 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x48 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x4c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x50 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x54 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x58 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x5c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x60 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x64 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x68 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x6c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x70 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x74 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x78 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x7c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x80 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x84 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x88 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x8c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x90 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x94 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x98 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x9c }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xa8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xac }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xb8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xbc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xc8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xcc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xd8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xdc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x2, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xe8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x3, num_of_bits: u8:0x2, base: u16:0xfc }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xec }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf0 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf4 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xf8 }, - FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, - zero!(), ... - ], - FseLookupDecoderResp { status: FseLookupDecoderStatus::OK, accuracy_log: AccuracyLog:8 } - ), ]; #[test_proc] proc FseLookupDecoderTest { type Req = FseLookupDecoderReq; type Resp = FseLookupDecoderResp; - type Status = FseLookupDecoderStatus; type MemReaderReq = mem_reader::MemReaderReq; type MemReaderResp = mem_reader::MemReaderResp; @@ -1787,13 +569,12 @@ proc FseLookupDecoderTest { next(_: ()) { let tok = join(); - // This has to be outside of unroll_for!, otherwise typechecker reports type mismatch on identical types - let req_start = Req {}; - let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(FSE_LOOKUP_DECODER_TESTCASES)) { - let (input, output, resp_ok) = FSE_LOOKUP_DECODER_TESTCASES[test_i]; + let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(COMP_LOOKUP_DECODER_TESTCASES)) { + let (input, output, req, exp_resp) = COMP_LOOKUP_DECODER_TESTCASES[test_i]; trace_fmt!("Loading testcase {:x}", test_i); + let tok = for ((i, input_data), tok): ((u32, u64), token) in enumerate(input) { let req = TestcaseRamWrReq { addr: i as uN[TEST_CASE_RAM_ADDR_WIDTH], @@ -1809,9 +590,10 @@ proc FseLookupDecoderTest { let tok = send(tok, refill_req_s, RefillStartReq { start_addr: uN[TEST_AXI_ADDR_WIDTH]:0x0 }); - let tok = send(tok, req_s, req_start); + + let tok = send(tok, req_s, req); let (tok, resp) = recv(tok, resp_r); - assert_eq(resp, resp_ok); + assert_eq(resp, exp_resp); let tok = for ((i, output_data), tok): ((u32, FseTableRecord), token) in enumerate(output) { let req = FseRamRdReq { diff --git a/xls/modules/zstd/fse_table_creator.x b/xls/modules/zstd/fse_table_creator.x index 2537f13948..5b903d049f 100644 --- a/xls/modules/zstd/fse_table_creator.x +++ b/xls/modules/zstd/fse_table_creator.x @@ -321,13 +321,13 @@ pub proc FseTableCreator< base: new_state_base }; let complete_record_as_bits = fse_record_to_bits(complete_record); - let tok10 = send_if(tok8, fse_wr_req_s, set_state_desc, - FseRamWriteReq { + + let fse_wr_req = FseRamWriteReq { addr: checked_cast(state.idx), data: checked_cast(complete_record_as_bits), mask: FSE_RAM_REQ_MASK_ALL - } - ); + }; + let tok10 = send_if(tok8, fse_wr_req_s, set_state_desc, fse_wr_req); let (tok10, _) = recv_if(tok10, fse_wr_resp_r, set_state_desc, FseRamWriteResp {}); let send_finish = state.status == Status::SEND_FINISH; diff --git a/xls/modules/zstd/refilling_shift_buffer_mux.x b/xls/modules/zstd/refilling_shift_buffer_mux.x new file mode 100644 index 0000000000..e04d5d4b8e --- /dev/null +++ b/xls/modules/zstd/refilling_shift_buffer_mux.x @@ -0,0 +1,252 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file contains a RamMux implementation that can be used to connect +// a single proc with two RAM instances, by using a single RAM interface and +// switching between the RAMs, when requested. The switching occurs only after +// each request has received the corresponding response. +// Additionally, a "naive" implementation is provided that does not ensure +// any synchronization when switching RAMs. + +import xls.modules.zstd.refilling_shift_buffer; + +struct RefillingShiftBufferMuxState { + sel: u1, +} + +pub proc RefillingShiftBufferMux< + AXI_DATA_W: u32, SB_LENGTH_W: u32, + INIT_SEL: u1 = {u1:0}, +>{ + type State = RefillingShiftBufferMuxState; + + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + init { + State { sel: INIT_SEL } + } + + sel_req_r: chan in; + sel_resp_s: chan<()> out; + + ctrl0_r: chan in; + data0_s: chan out; + + ctrl1_r: chan in; + data1_s: chan out; + + ctrl_s: chan out; + data_r: chan in; + + + config ( + sel_req_r: chan in, + sel_resp_s: chan<()> out, + + ctrl0_r: chan in, + data0_s: chan out, + + ctrl1_r: chan in, + data1_s: chan out, + + ctrl_s: chan out, + data_r: chan in, + ) { + ( + sel_req_r, sel_resp_s, + ctrl0_r, data0_s, + ctrl1_r, data1_s, + ctrl_s, data_r, + ) + } + + next (state: State) { + let tok0 = join(); + + let (tok1, sel, sel_valid) = recv_non_blocking(tok0, sel_req_r, state.sel); + let tok2_0 = send(tok0, sel_resp_s, ()); + + let (tok2_0, ctrl0, ctrl0_valid) = recv_if_non_blocking(tok1, ctrl0_r, sel == u1:0, zero!()); + let (tok2_1, ctrl1, ctrl1_valid) = recv_if_non_blocking(tok1, ctrl1_r, sel == u1:1, zero!()); + let tok2 = join(tok2_0, tok2_1); + + let (ctrl, ctrl_valid) = if ctrl0_valid { + (ctrl0, true) + } else if ctrl1_valid { + (ctrl1, true) + } else { + (zero!(), false) + }; + + let tok3 = send_if(tok2, ctrl_s, ctrl_valid, ctrl); + let (tok4, data) = recv_if(tok3, data_r, ctrl_valid, zero!()); + + let do_recv_data0 = (sel == u1:0) && ctrl_valid; + send_if(tok4, data0_s, do_recv_data0, data); + + let do_recv_data1 = (sel == u1:1) && ctrl_valid; + send_if(tok4, data1_s, do_recv_data1, data); + + State { sel } + } +} + +const TEST_AXI_DATA_W = u32:64; +const TEST_SB_LENGTH_W = u32:32; + +proc RefillingShiftBufferStub< + AXI_DATA_W: u32, SB_LENGTH_W: u32 +> { + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type Length = uN[SB_LENGTH_W]; + type Data = uN[AXI_DATA_W]; + + ctrl_r: chan in; + data_s: chan out; + + init { u32:0 } + + config ( + ctrl_r: chan in, + data_s: chan out, + ) { + (ctrl_r, data_s) + } + + next(cnt: u32) { + let tok = join(); + let (tok, ctrl) = recv(tok, ctrl_r); + let tok = send(tok, data_s, SBOutput { data: cnt as Data, length: ctrl.length, error: false }); + cnt + u32:1 + } +} + +#[test_proc] +proc RefillingShitBufferMuxTest +{ + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type Length = uN[TEST_SB_LENGTH_W]; + type Data = uN[TEST_AXI_DATA_W]; + + terminator: chan out; + + sel_req_s: chan out; + sel_resp_r: chan<()> in; + + ctrl0_s: chan out; + data0_r: chan in; + + ctrl1_s: chan out; + data1_r: chan in; + + init {} + + config(terminator: chan out) { + let (sel_req_s, sel_req_r) = chan("sel_req"); + let (sel_resp_s, sel_resp_r) = chan<()>("sel_resp"); + + let (ctrl_s, ctrl_r) = chan("ctrl"); + let (data_s, data_r) = chan("data"); + + let (ctrl0_s, ctrl0_r) = chan("ctrl0"); + let (data0_s, data0_r) = chan("data0"); + + let (ctrl1_s, ctrl1_r) = chan("ctrl1"); + let (data1_s, data1_r) = chan("data1"); + + spawn RefillingShiftBufferMux( + sel_req_r, sel_resp_s, + ctrl0_r, data0_s, + ctrl1_r, data1_s, + ctrl_s, data_r, + ); + + spawn RefillingShiftBufferStub ( + ctrl_r, data_s, + ); + + ( + terminator, + sel_req_s, sel_resp_r, + ctrl0_s, data0_r, + ctrl1_s, data1_r, + ) + } + + next(state: ()) { + let tok = join(); + + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA1 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA2 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA3 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA4 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA5 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA6 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA7 }); + let tok = send(tok, ctrl0_s, SBCtrl { length: Length:0xA8 }); + + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:0, length: Length:0xA1, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:1, length: Length:0xA2, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:2, length: Length:0xA3, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:3, length: Length:0xA4, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:4, length: Length:0xA5, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:5, length: Length:0xA6, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:6, length: Length:0xA7, error: false }); + let (tok, data) = recv(tok, data0_r); + assert_eq(data, SBOutput { data: Data:7, length: Length:0xA8, error: false }); + + let tok = send(tok, sel_req_s, u1:1); + let (tok, _) = recv(tok, sel_resp_r); + + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB1 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB2 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB3 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB4 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB5 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB6 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB7 }); + let tok = send(tok, ctrl1_s, SBCtrl { length: Length:0xB8 }); + + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:8, length: Length:0xB1, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:9, length: Length:0xB2, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:10, length: Length:0xB3, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:11, length: Length:0xB4, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:12, length: Length:0xB5, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:13, length: Length:0xB6, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:14, length: Length:0xB7, error: false}); + let (tok, data) = recv(tok, data1_r); + assert_eq(data, SBOutput { data: Data:15, length: Length:0xB8, error: false}); + + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/rle_lookup_dec.x b/xls/modules/zstd/rle_lookup_dec.x new file mode 100644 index 0000000000..b965d119c2 --- /dev/null +++ b/xls/modules/zstd/rle_lookup_dec.x @@ -0,0 +1,190 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +import std; +import xls.examples.ram; +import xls.modules.zstd.common; +import xls.modules.zstd.refilling_shift_buffer; +import xls.modules.zstd.fse_table_creator; + +pub proc RleLookupDecoder< + AXI_DATA_W: u32, + FSE_RAM_DATA_W: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, +> { + type Req = common::LookupDecoderReq; + type Resp = common::LookupDecoderResp; + + type Status = common::LookupDecoderStatus; + + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + req_r: chan in; + resp_s: chan out; + + fse_wr_req_s: chan out; + fse_wr_resp_r: chan in; + + buffer_ctrl_s: chan out; + buffer_data_r: chan in; + + init {} + + config( + req_r: chan in, + resp_s: chan out, + + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, + + buffer_ctrl_s: chan out, + buffer_data_r: chan in, + ) { + ( + req_r, resp_s, + fse_wr_req_s, fse_wr_resp_r, + buffer_ctrl_s, buffer_data_r, + ) + } + + next(state: ()) { + let tok = join(); + // receive request + let (tok, _) = recv(tok, req_r); + // ask shift buffer for one byte + let tok = send(tok, buffer_ctrl_s, SBCtrl { + length: uN[SB_LENGTH_W]:8 + }); + // receive byte + let (tok, byte) = recv(tok, buffer_data_r); + // write byte to first location in memory + + let fse_wr_req = FseRamWrReq { + addr: uN[FSE_RAM_ADDR_W]:0, + data: fse_table_creator::fse_record_to_bits(common::FseTableRecord { + symbol: byte.data as u8, + num_of_bits: u8:0, + base: u16:0, + }), + mask: all_ones!(), + }; + trace_fmt!("RLE RAM REQUEST: {:#x}", fse_wr_req); + + let tok = send(tok, fse_wr_req_s, fse_wr_req); + // receive write response + let (tok, _) = recv(tok, fse_wr_resp_r); + // send response + let tok = send(tok, resp_s, Resp { + status: if byte.error { Status::ERROR } else { Status::OK }, + accuracy_log: common::FseAccuracyLog:0, + }); + } +} + + +const TEST_AXI_DATA_W = u32:64; +const TEST_SB_LENGTH_W = refilling_shift_buffer::length_width(TEST_AXI_DATA_W); + +const TEST_FSE_RAM_DATA_W = u32:32; +const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; +const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); + +#[test_proc] +proc RleLookupDecoderTest { + type Req = common::LookupDecoderReq; + type Resp = common::LookupDecoderResp; + type Status = common::LookupDecoderStatus; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + terminator: chan out; + + req_s: chan out; + resp_r: chan in; + + fse_wr_req_r: chan in; + fse_wr_resp_s: chan out; + + buffer_ctrl_r: chan in; + buffer_data_s: chan out; + + init {} + + config(terminator: chan out) { + + let (req_s, req_r) = chan("req"); + let (resp_s, resp_r) = chan("resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + let (buffer_ctrl_s, buffer_ctrl_r) = chan("buffer_ctrl"); + let (buffer_data_s, buffer_data_r) = chan("buffer_data"); + + spawn RleLookupDecoder< + TEST_AXI_DATA_W, + TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_NUM_PARTITIONS, + >( + req_r, resp_s, + fse_wr_req_s, fse_wr_resp_r, + buffer_ctrl_s, buffer_data_r, + ); + + ( + terminator, + req_s, resp_r, + fse_wr_req_r, fse_wr_resp_s, + buffer_ctrl_r, buffer_data_s, + ) + } + + next(_: ()) { + let tok = join(); + + let tok = send(tok, req_s, Req {}); + let (tok, buf_req) = recv(tok, buffer_ctrl_r); + assert_eq(buf_req, SBCtrl { + length: uN[TEST_SB_LENGTH_W]:8 + }); + let tok = send(tok, buffer_data_s, SBOutput { + length: uN[TEST_SB_LENGTH_W]:8, + data: uN[TEST_AXI_DATA_W]:0xC5, + error: false, + }); + let (tok, ram_req) = recv(tok, fse_wr_req_r); + assert_eq(ram_req, FseRamWrReq { + addr: uN[TEST_FSE_RAM_ADDR_W]:0, + data: u32:0xC5, + mask: uN[TEST_FSE_RAM_NUM_PARTITIONS]:0x1, + }); + let tok = send(tok, fse_wr_resp_s, FseRamWrResp {}); + let (tok, resp) = recv(tok, resp_r); + assert_eq(resp, Resp { + status: Status::OK, + accuracy_log: common::FseAccuracyLog:0, + }); + send(tok, terminator, true); + } +} diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x index a33911ef3b..b14f088c07 100644 --- a/xls/modules/zstd/sequence_dec.x +++ b/xls/modules/zstd/sequence_dec.x @@ -35,6 +35,7 @@ type SequenceExecutorMessageType = common::SequenceExecutorMessageType; type BlockSyncData = common::BlockSyncData; type CommandConstructorData = common::CommandConstructorData; +type CompressionMode = common::CompressionMode; enum SequenceDecoderStatus: u3 { OK = 0, @@ -69,23 +70,23 @@ struct SequenceDecoderState { } struct FseLookupCtrlReq { - ll: bool, - ml: bool, - of: bool, + ll_mode: CompressionMode, + ml_mode: CompressionMode, + of_mode: CompressionMode, } type AccuracyLog = common::FseAccuracyLog; struct FseLookupCtrlResp { - ll_accuracy_log: AccuracyLog, - ml_accuracy_log: AccuracyLog, - of_accuracy_log: AccuracyLog, + ll_accuracy_log: u7, + ml_accuracy_log: u7, + of_accuracy_log: u7, } struct FseLookupCtrlState { - decode: bool[3], - decode_valid: bool, - resp: FseLookupCtrlResp, + mode: CompressionMode[3], + mode_valid: bool, cnt: u2, + accuracy_logs: u7[3], } pub proc FseLookupCtrl { @@ -125,18 +126,26 @@ pub proc FseLookupCtrl { } next(state: State) { + const PREDEFINED_ACURACY_LOG = u7[3]:[u7:6, u7:5, u7:6]; + let tok0 = join(); - if !state.decode_valid { + if !state.mode_valid { let (tok1_0, req) = recv(tok0, req_r); State { - decode: bool[3]:[req.ll, req.of, req.ml], - decode_valid: true, + mode: CompressionMode[3]:[req.ll_mode, req.of_mode, req.ml_mode], + mode_valid: true, cnt: u2:0, ..zero!() } } else { - let do_set = state.decode[state.cnt]; + let is_rle = (state.mode[state.cnt] == CompressionMode::RLE); + let is_compressed = (state.mode[state.cnt] == CompressionMode::COMPRESSED); + let is_predefined = (state.mode[state.cnt] == CompressionMode::PREDEFINED); + let is_repeated = (state.mode[state.cnt] == CompressionMode::REPEAT); + + let do_set = is_rle || is_compressed; + match(state.cnt) { u2:0 => trace_fmt!("Handling LL"), u2:1 => trace_fmt!("Handling OF"), @@ -156,7 +165,7 @@ pub proc FseLookupCtrl { } else {}; // trace_fmt!("Received response from demux"); - let tok3 = send_if(tok2, fld_req_s, do_set, FseLookupDecoderReq {}); + let tok3 = send_if(tok2, fld_req_s, do_set, FseLookupDecoderReq { is_rle }); if do_set { trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Sent FseLookupDecoder req"); } else {}; @@ -166,20 +175,28 @@ pub proc FseLookupCtrl { trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: Received FseLookupDecoder resp {:#x}", fld_resp); } else {}; - let resp = match(state.cnt) { - u2:0 => FseLookupCtrlResp { ll_accuracy_log: fld_resp.accuracy_log, ..state.resp}, - u2:1 => FseLookupCtrlResp { of_accuracy_log: fld_resp.accuracy_log, ..state.resp}, - u2:2 => FseLookupCtrlResp { ml_accuracy_log: fld_resp.accuracy_log, ..state.resp}, - _ => fail!("impossible_cnt", zero!()), + let accuracy_log = if is_predefined { + PREDEFINED_ACURACY_LOG[state.cnt] + } else if is_repeated { + state.accuracy_logs[state.cnt] + } else if is_rle || is_compressed { + fld_resp.accuracy_log as u7 + } else { + fail!("impossible_case", u7:0) }; - // trace_fmt!("Received response from from FseLookupDecoder {:#x}", fld_resp); + let accuracy_logs = update(state.accuracy_logs, state.cnt, accuracy_log); + trace_fmt!("[SequenceDecoderCtrl/FseLookupCtrl]: accuracy_log: {:#x}, accuracy_logs: {:#x}", accuracy_log, accuracy_logs); if state.cnt >= u2:2 { - let tok5 = send(tok4, resp_s, resp); - zero!() + let tok5 = send(tok4, resp_s, FseLookupCtrlResp { + ll_accuracy_log: accuracy_logs[0], + of_accuracy_log: accuracy_logs[1], + ml_accuracy_log: accuracy_logs[2], + }); + State { accuracy_logs, ..zero!() } } else { - State { cnt: state.cnt + u2:1, resp, ..state} + State { accuracy_logs, cnt: state.cnt + u2:1, ..state} } } } @@ -496,12 +513,6 @@ pub proc SequenceDecoderCtrl< let (tok_recv_scd, conf_resp) = recv(tok_send_scd, scd_resp_r); trace_fmt!("[SequenceDecoderCtrl]: Received decoded Sequence header: {:#x}", conf_resp); - let zero_sequences = (conf_resp.header.sequence_count == u17:0); - if !zero_sequences { - assert!(conf_resp.header.literals_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); - assert!(conf_resp.header.match_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); - assert!(conf_resp.header.offset_mode != CompressionMode::RLE, "unsupported_fse_table_mode"); - } else {}; // Start RefillingShiftBuffer for decoding lookups let tok_dec_lookup = send(tok_recv_scd, fld_rsb_start_req_s, RefillingShiftBufferStart { @@ -510,11 +521,12 @@ pub proc SequenceDecoderCtrl< // Request decoding lookups let flc_req = FseLookupCtrlReq { - ll: (conf_resp.header.literals_mode == CompressionMode::COMPRESSED), - ml: (conf_resp.header.match_mode == CompressionMode::COMPRESSED), - of: (conf_resp.header.offset_mode == CompressionMode::COMPRESSED), + ll_mode: conf_resp.header.literals_mode, + ml_mode: conf_resp.header.match_mode, + of_mode: conf_resp.header.offset_mode, }; + let zero_sequences = (conf_resp.header.sequence_count == u17:0); let tok_send_ctrl = send_if(tok_recv_scd, flc_req_s, !zero_sequences, flc_req); if !zero_sequences { trace_fmt!("[SequenceDecoderCtrl]: Sent FseLookupCtrl request: {:#x}", flc_req); @@ -529,21 +541,24 @@ pub proc SequenceDecoderCtrl< // Set proper LL lookup through demux let ll_demux_sel = (conf_resp.header.literals_mode != CompressionMode::PREDEFINED); - let tok_ll_demux = send_if(tok_recv_scd, ll_demux_req_s, !zero_sequences, ll_demux_sel); + let ll_demux_do_send = !zero_sequences && (conf_resp.header.literals_mode != CompressionMode::REPEAT); + let tok_ll_demux = send_if(tok_recv_scd, ll_demux_req_s, ll_demux_do_send, ll_demux_sel); // Receive response from LL lookup demux - let (tok_ll_demux, _) = recv_if(tok_ll_demux, ll_demux_resp_r, !zero_sequences, ()); + let (tok_ll_demux, _) = recv_if(tok_ll_demux, ll_demux_resp_r, ll_demux_do_send, ()); // Set proper ML lookup through demux let ml_demux_sel = (conf_resp.header.match_mode != CompressionMode::PREDEFINED); - let tok_ml_demux = send_if(tok_recv_scd, ml_demux_req_s, !zero_sequences, ml_demux_sel); + let ml_demux_do_send = !zero_sequences && (conf_resp.header.match_mode != CompressionMode::REPEAT); + let tok_ml_demux = send_if(tok_recv_scd, ml_demux_req_s, ml_demux_do_send, ml_demux_sel); // Receive response from ML lookup demux - let (tok_ml_demux, _) = recv_if(tok_ml_demux, ml_demux_resp_r, !zero_sequences, ()); + let (tok_ml_demux, _) = recv_if(tok_ml_demux, ml_demux_resp_r, ml_demux_do_send, ()); // Set proper OF lookup through demux let of_demux_sel = (conf_resp.header.offset_mode != CompressionMode::PREDEFINED); - let tok_of_demux = send_if(tok_recv_scd, of_demux_req_s, !zero_sequences, of_demux_sel); + let of_demux_do_send = !zero_sequences && (conf_resp.header.offset_mode != CompressionMode::REPEAT); + let tok_of_demux = send_if(tok_recv_scd, of_demux_req_s, of_demux_do_send, of_demux_sel); // Receive response from OF lookup demux - let (tok_of_demux, _) = recv_if(tok_of_demux, of_demux_resp_r, !zero_sequences, ()); + let (tok_of_demux, _) = recv_if(tok_of_demux, of_demux_resp_r, of_demux_do_send, ()); let tok_demux = join(tok_ll_demux, tok_ml_demux, tok_of_demux); @@ -557,9 +572,9 @@ pub proc SequenceDecoderCtrl< sync: req.sync, sequences_count: conf_resp.header.sequence_count as u24, literals_count: req.literals_count, - ll_acc_log: if (conf_resp.header.literals_mode == CompressionMode::PREDEFINED) { u7:6 } else { flc_resp.ll_accuracy_log as u7 }, - of_acc_log: if (conf_resp.header.offset_mode == CompressionMode::PREDEFINED) { u7:5 } else { flc_resp.of_accuracy_log as u7 }, - ml_acc_log: if (conf_resp.header.match_mode == CompressionMode::PREDEFINED) { u7:6 } else { flc_resp.ml_accuracy_log as u7 }, + ll_acc_log: flc_resp.ll_accuracy_log as u7, + of_acc_log: flc_resp.of_accuracy_log as u7, + ml_acc_log: flc_resp.ml_accuracy_log as u7, }; let tok_fse_dec = send(tok_demux, fd_ctrl_s, fd_ctrl); @@ -1194,10 +1209,10 @@ const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP2_RAM_WORD_PART // - sequences section as it appears in memory // - expected output size // - expected output -const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[3] = [ - // Test case 0 - // raw literals with sequences with 3 predefined tables - // ./decodecorpus -pdata2.out -odata2.in -s35304 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 +const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[4] = [ +// // Test case 0 +// // raw literals with sequences with 3 predefined tables +// // ./decodecorpus -pdata2.out -odata2.in -s35304 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 ( u32:17, u64[32]:[ @@ -1594,7 +1609,131 @@ const SEQ_DEC_TESTCASES: (u32, u64[32], u32, SequenceExecutorPacket[64])[3] = [ zero!(), ... ] ), - // Test case 3 (WARNING: long test running time) + // Test case 3 + // LL - compressed, OF - compressed, ML - RLE + ( + u32:0x17, + u64[32]:[ + u64:0x0, u64:0x0, + u64:0x39fb5432a90a409, + u64:0x6b2940007b74a10, + u64:0xaca57e409b057, + u64:0x0, ... + ], + u32:18, + SequenceExecutorPacket[64]:[ + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0002, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0004, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0007, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0001, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0009, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0005, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0009, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0000, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x000b, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0011, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0012, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0004, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0023, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0002, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x000a, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::LITERAL, + length: u64:0x0002, + content: u64:0x0, + last: false, + }, + SequenceExecutorPacket { + msg_type: SequenceExecutorMessageType::SEQUENCE, + length: u64:0x0003, + content: u64:0x0034, + last: true, + }, + zero!(), ... + ] + ), + // Test case N (WARNING: long test running time) // 3 custom lookup tables with accuracy log 9, 8 and 9 // decodecorpus -pdata.out -odata.in -s58745 --block-type=2 --content-size --literal-type=0 --max-block-size-log=7 // ( From 4d863525a55ac58cfe39762f414ed2422e22587f Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 22 Jan 2025 21:59:26 +0100 Subject: [PATCH 59/85] Add test frame for repeated and rle tables Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 1 + xls/modules/zstd/comp_frame_fse_repeated.x | 21 +++++++++++++++++++++ xls/modules/zstd/zstd_dec_test.x | 1 + 3 files changed, 23 insertions(+) create mode 100644 xls/modules/zstd/comp_frame_fse_repeated.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 4fc18e5743..37307f09de 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1280,6 +1280,7 @@ xls_dslx_test( "comp_frame.x", "comp_frame_huffman.x", "comp_frame_fse_comp.x", + "comp_frame_fse_repeated.x", ], tags = ["manual"], deps = zstd_dec_deps, diff --git a/xls/modules/zstd/comp_frame_fse_repeated.x b/xls/modules/zstd/comp_frame_fse_repeated.x new file mode 100644 index 0000000000..37de3b7ddf --- /dev/null +++ b/xls/modules/zstd/comp_frame_fse_repeated.x @@ -0,0 +1,21 @@ +pub struct DataArray{ + data: uN[BITS_PER_WORD][LENGTH], + length: u32, + array_length: u32 +} +pub const FRAMES:DataArray< + u32:64, + u32:12 +>[1] = [DataArray<64, 12>{ + length: u32:92, + array_length: u32:12, + data: uN[64][12]:[uN[64]:0x003e2484fd2fb528, uN[64]:0x02d6790000840000, uN[64]:0xff86117f06110168, uN[64]:0x0000440452dd7eff, uN[64]:0x04b6010674016531, uN[64]:0x001c00b32100001c, uN[64]:0x0100001c00e70100, uN[64]:0x00bd0100001c000d, uN[64]:0x001c003a0100001c, uN[64]:0x0100001c007f0100, uN[64]:0x00690100001d006b, uN[64]:0x993d99b6] +}]; +pub const DECOMPRESSED_FRAMES:DataArray< + u32:64, + u32:8 +>[1] = [DataArray<64, 8>{ + length: u32:62, + array_length: u32:8, + data: uN[64][8]:[uN[64]:0xd6d6d6d6d6d6d6d6, uN[64]:0xd6d6d6d6d6d6d6d6, uN[64]:0xd6d6d6d6d6d6d6d6, uN[64]:0xd6d6d6d6d6d6d6d6, uN[64]:0xd6d6d6d6d6d6d6d6, uN[64]:0xd6d6d6d6d6d6d6d6, uN[64]:0xd6d6656565656565, uN[64]:0xb3b3b3b3d6d6] +}]; diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 92aac6a0f6..52306111ce 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -31,6 +31,7 @@ import xls.modules.zstd.ram_mux; // import xls.modules.zstd.zstd_frame_testcases as comp_frame; // import xls.modules.zstd.comp_frame_huffman as comp_frame; // import xls.modules.zstd.comp_frame_fse_comp as comp_frame; +// import xls.modules.zstd.comp_frame_fse_repeated as comp_frame; import xls.modules.zstd.comp_frame; const TEST_WINDOW_LOG_MAX = u32:30; From 9a733de90c529aa14e121eb6d8ff033ccaf830fa Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Wed, 22 Jan 2025 17:11:42 +0100 Subject: [PATCH 60/85] modules/zstd: Add RamMerge proc Internal-tag: [#71874] Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 7 ++++ xls/modules/zstd/ram_merge.x | 78 ++++++++++++++++++++++++++++++++++++ xls/modules/zstd/zstd_dec.x | 45 +++++++++++++++++---- 3 files changed, 122 insertions(+), 8 deletions(-) create mode 100644 xls/modules/zstd/ram_merge.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 37307f09de..b3b3f968b7 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1242,6 +1242,12 @@ xls_dslx_test( tags = ["manual"], ) +xls_dslx_library( + name = "ram_merge_dslx", + srcs = ["ram_merge.x"], + deps = ["//xls/examples:ram_dslx"], +) + zstd_dec_deps = [ ":axi_csr_accessor_dslx", ":block_header_dec_dslx", @@ -1257,6 +1263,7 @@ zstd_dec_deps = [ ":huffman_literals_dec_dslx", ":literals_buffer_dslx", ":parallel_rams_dslx", + ":ram_merge_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:mem_writer_dslx", diff --git a/xls/modules/zstd/ram_merge.x b/xls/modules/zstd/ram_merge.x new file mode 100644 index 0000000000..c4e306dfa7 --- /dev/null +++ b/xls/modules/zstd/ram_merge.x @@ -0,0 +1,78 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +import xls.examples.ram; + +pub proc RamMerge< + RAM_ADDR_W: u32, + RAM_DATA_W: u32, + RAM_NUM_PARTITIONS: u32 +> { + type ReadReq = ram::ReadReq; + type ReadResp = ram::ReadResp; + type WriteReq = ram::WriteReq; + type WriteResp = ram::WriteResp; + + init {} + + read_side_rd_req_r: chan in; + read_side_rd_resp_s: chan out; + + write_side_wr_req_r: chan in; + write_side_wr_resp_s: chan out; + + merge_side_rd_req_s: chan out; + merge_side_rd_resp_r: chan in; + merge_side_wr_req_s: chan out; + merge_side_wr_resp_r: chan in; + + config( + read_side_rd_req_r: chan in, + read_side_rd_resp_s: chan out, + + write_side_wr_req_r: chan in, + write_side_wr_resp_s: chan out, + + merge_side_rd_req_s: chan out, + merge_side_rd_resp_r: chan in, + merge_side_wr_req_s: chan out, + merge_side_wr_resp_r: chan in, + ) { + ( + read_side_rd_req_r, read_side_rd_resp_s, + + write_side_wr_req_r, write_side_wr_resp_s, + + merge_side_rd_req_s, merge_side_rd_resp_r, + merge_side_wr_req_s, merge_side_wr_resp_r + ) + } + + next (state: ()) { + let tok = join(); + + // Passthrough Requests + let (tok_rd, rd_req, rd_req_valid) = recv_non_blocking(tok, read_side_rd_req_r, zero!()); + let (tok_rd, rd_resp, rd_resp_valid) = recv_non_blocking(tok_rd, merge_side_rd_resp_r, zero!()); + let tok_rd = send_if(tok_rd, merge_side_rd_req_s, rd_req_valid, rd_req); + let tok_rd = send_if(tok_rd, read_side_rd_resp_s, rd_resp_valid, rd_resp); + + let (tok_wr, wr_req, wr_req_valid) = recv_non_blocking(tok, write_side_wr_req_r, zero!()); + let (tok_wr, wr_resp, wr_resp_valid) = recv_non_blocking(tok_wr, merge_side_wr_resp_r, zero!()); + let tok_wr = send_if(tok_wr, merge_side_wr_req_s, wr_req_valid, wr_req); + let tok_wr = send_if(tok_wr, write_side_wr_resp_s, wr_resp_valid, wr_resp); + + let tok_joined = join(tok_rd, tok_wr); + } +} diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index 31ab2d643f..77ddea55f6 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -35,6 +35,7 @@ import xls.modules.zstd.sequence_executor; import xls.modules.zstd.huffman_literals_dec; import xls.modules.zstd.literals_buffer; import xls.modules.zstd.parallel_rams; +import xls.modules.zstd.ram_merge; type BlockSize = common::BlockSize; type BlockType = common::BlockType; @@ -1286,6 +1287,11 @@ pub proc ZstdDecoder< let (cmd_output_s, cmd_output_r) = chan("cmd_output"); + let (huffman_lit_weights_read_side_rd_req_s, huffman_lit_weights_read_side_rd_req_r) = chan("huffman_lit_weights_read_side_rd_req"); + let (huffman_lit_weights_read_side_rd_resp_s, huffman_lit_weights_read_side_rd_resp_r) = chan("huffman_lit_weights_read_side_rd_resp"); + let (huffman_lit_weights_write_side_wr_req_s, huffman_lit_weights_write_side_wr_req_r) = chan("huffman_lit_weights_write_side_wr_req"); + let (huffman_lit_weights_write_side_wr_resp_s, huffman_lit_weights_write_side_wr_resp_r) = chan("huffman_lit_weights_write_side_wr_resp"); + spawn comp_block_dec::CompressBlockDecoder< AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W, // FSE lookup table RAMs @@ -1333,12 +1339,22 @@ pub proc ZstdDecoder< litbuf_wr_req_s[4], litbuf_wr_req_s[5], litbuf_wr_req_s[6], litbuf_wr_req_s[7], litbuf_wr_resp_r[0], litbuf_wr_resp_r[1], litbuf_wr_resp_r[2], litbuf_wr_resp_r[3], litbuf_wr_resp_r[4], litbuf_wr_resp_r[5], litbuf_wr_resp_r[6], litbuf_wr_resp_r[7], - huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, - huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + huffman_lit_weights_read_side_rd_req_s, huffman_lit_weights_read_side_rd_resp_r, + huffman_lit_weights_write_side_wr_req_s, huffman_lit_weights_write_side_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, ); + spawn ram_merge::RamMerge( + // Read side + huffman_lit_weights_read_side_rd_req_r, huffman_lit_weights_read_side_rd_resp_s, + // Write side + huffman_lit_weights_write_side_wr_req_r, huffman_lit_weights_write_side_wr_resp_s, + // Merge side + huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, + huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + ); + // Collecting Packets let (seq_exec_input_s, seq_exec_input_r) = chan("demux_output"); @@ -1465,6 +1481,8 @@ const INST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; const HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; +const HUFFMAN_WEIGHTS_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; +const HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE: u32 = huffman_literals_dec::WEIGHTS_PARTITION_WORD_SIZE; // Huffman prescan memory parameters const HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; const HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; @@ -1480,6 +1498,8 @@ const LITERALS_BUFFER_RAM_DATA_W: u32 = literals_buffer::RAM_DATA_WIDTH; const LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; const LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = LITERALS_BUFFER_RAM_DATA_W; +const INST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const INST_RAM_INITIALIZED = true; proc ZstdDecoderInternalInst { type State = ZstdDecoderInternalState; @@ -1617,6 +1637,8 @@ proc ZstdDecoderInst { type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; + const CHANNEL_DEPTH = u32:1; + init { } config( @@ -1667,12 +1689,6 @@ proc ZstdDecoderInst { litbuf_wr_req_s: chan[u32:8] out, litbuf_wr_resp_r: chan[u32:8] in, - // Huffman weights memory - huffman_lit_weights_mem_rd_req_s: chan out, - huffman_lit_weights_mem_rd_resp_r: chan in, - huffman_lit_weights_mem_wr_req_s: chan out, - huffman_lit_weights_mem_wr_resp_r: chan in, - // Huffman prescan memory huffman_lit_prescan_mem_rd_req_s: chan out, huffman_lit_prescan_mem_rd_resp_r: chan in, @@ -1721,6 +1737,19 @@ proc ZstdDecoderInst { notify_s: chan<()> out, reset_s: chan<()> out, ) { + // FIXME: Remove inline Huffman Weights memory once HuffmanLiteralsDecoder's memory ports are able to be rewritten + let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + spawn ram::RamModel< + HUFFMAN_WEIGHTS_RAM_DATA_W, HUFFMAN_WEIGHTS_RAM_SIZE, HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE, + INST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, INST_RAM_INITIALIZED + >( + huffman_lit_weights_mem_rd_req_r, huffman_lit_weights_mem_rd_resp_s, + huffman_lit_weights_mem_wr_req_r, huffman_lit_weights_mem_wr_resp_s, + ); + spawn ZstdDecoder< INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, INST_REGS_N, INST_WINDOW_LOG_MAX, From a7f5b4e47c7645acc484667e1787e44f7ab36f77 Mon Sep 17 00:00:00 2001 From: Maciej Torhan Date: Fri, 17 Jan 2025 13:33:37 +0100 Subject: [PATCH 61/85] modules/zstd: Implement HuffmanFseWeightsDecoder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Krzysztof Obłonczek Signed-off-by: Maciej Torhan --- xls/modules/zstd/BUILD | 4 + xls/modules/zstd/common.x | 2 +- xls/modules/zstd/huffman_literals_dec.x | 281 +++- xls/modules/zstd/huffman_weights_dec.x | 1431 +++++++++++++++++++-- xls/modules/zstd/refilling_shift_buffer.x | 36 +- 5 files changed, 1621 insertions(+), 133 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index b3b3f968b7..77e7024911 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -3051,6 +3051,10 @@ xls_dslx_library( ], deps = [ "//xls/modules/zstd:huffman_prescan_dslx", + "//xls/modules/zstd:refilling_shift_buffer_dslx", + "//xls/modules/zstd:fse_lookup_dec_dslx", + "//xls/modules/zstd:fse_table_creator_dslx", + "//xls/modules/zstd:math_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", "//xls/examples:ram_dslx", diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 8c1a48b143..377a5aa2c4 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -176,7 +176,7 @@ pub struct FseTableCreatorCtrl { negative_proba_count: FseSymbolCount } -pub fn highest_set_bit(num: uN[N]) -> u16 { std::flog2(num) } +pub fn highest_set_bit(num: uN[N]) -> uN[N] { std::flog2(num) } // SequenceDecoder diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index 55589b9992..b3b650f2ae 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -49,6 +49,9 @@ pub const PRESCAN_NUM_PARTITIONS: u32 = u32:1; pub proc HuffmanLiteralsDecoder< AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + WEIGHTS_DPD_RAM_ADDR_W: u32, WEIGHTS_DPD_RAM_DATA_W: u32, WEIGHTS_DPD_RAM_NUM_PARTITIONS: u32, + WEIGHTS_TMP_RAM_ADDR_W: u32, WEIGHTS_TMP_RAM_DATA_W: u32, WEIGHTS_TMP_RAM_NUM_PARTITIONS: u32, + WEIGHTS_FSE_RAM_ADDR_W: u32, WEIGHTS_FSE_RAM_DATA_W: u32, WEIGHTS_FSE_RAM_NUM_PARTITIONS: u32, WEIGHTS_RAM_ADDR_WIDTH: u32 = {WEIGHTS_ADDR_WIDTH}, WEIGHTS_RAM_DATA_WIDTH: u32 = {WEIGHTS_DATA_WIDTH}, WEIGHTS_RAM_NUM_PARTITIONS: u32 = {WEIGHTS_NUM_PARTITIONS}, @@ -71,6 +74,22 @@ pub proc HuffmanLiteralsDecoder< type PrescanRamWrReq = ram::WriteReq; type PrescanRamWrResp = ram::WriteResp; + // Weights FSE RAMs + type WeightsDpdRamRdReq = ram::ReadReq; + type WeightsDpdRamRdResp = ram::ReadResp; + type WeightsDpdRamWrReq = ram::WriteReq; + type WeightsDpdRamWrResp = ram::WriteResp; + + type WeightsTmpRamRdReq = ram::ReadReq; + type WeightsTmpRamRdResp = ram::ReadResp; + type WeightsTmpRamWrReq = ram::WriteReq; + type WeightsTmpRamWrResp = ram::WriteResp; + + type WeightsFseRamRdReq = ram::ReadReq; + type WeightsFseRamRdResp = ram::ReadResp; + type WeightsFseRamWrReq = ram::WriteReq; + type WeightsFseRamWrResp = ram::WriteResp; + type WeightsDecReq = weights_dec::HuffmanWeightsDecoderReq; type WeightsDecResp = weights_dec::HuffmanWeightsDecoderResp; @@ -98,8 +117,10 @@ pub proc HuffmanLiteralsDecoder< weights_raw_dec_axi_ar_s: chan out, weights_raw_dec_axi_r_r: chan in, // AXI interface - FSE Huffman tree description decoder - weights_fse_dec_axi_ar_s: chan out, - weights_fse_dec_axi_r_r: chan in, + weights_fse_lookup_dec_axi_ar_s: chan out, + weights_fse_lookup_dec_axi_r_r: chan in, + weights_fse_decoder_dec_axi_ar_s: chan out, + weights_fse_decoder_dec_axi_r_r: chan in, // weight memory weights_ram_rd_req_s: chan out, weights_ram_rd_resp_r: chan in, @@ -110,6 +131,19 @@ pub proc HuffmanLiteralsDecoder< prescan_ram_rd_resp_r: chan in, prescan_ram_wr_req_s: chan out, prescan_ram_wr_resp_r: chan in, + // Weights FSE RAMs + weights_dpd_rd_req_s: chan out, + weights_dpd_rd_resp_r: chan in, + weights_dpd_wr_req_s: chan out, + weights_dpd_wr_resp_r: chan in, + weights_tmp_rd_req_s: chan out, + weights_tmp_rd_resp_r: chan in, + weights_tmp_wr_req_s: chan out, + weights_tmp_wr_resp_r: chan in, + weights_fse_rd_req_s: chan out, + weights_fse_rd_resp_r: chan in, + weights_fse_wr_req_s: chan out, + weights_fse_wr_resp_r: chan in, ) { let (prescan_start_s, prescan_start_r) = chan("prescan_start"); let (code_builder_start_s, code_builder_start_r) = chan("code_buider"); @@ -130,8 +164,10 @@ pub proc HuffmanLiteralsDecoder< let (weights_header_dec_mem_rd_resp_s, weights_header_dec_mem_rd_resp_r) = chan("weights_dec_mem_rd_resp"); let (weights_raw_dec_mem_rd_req_s, weights_raw_dec_mem_rd_req_r) = chan("weights_dec_mem_rd_req"); let (weights_raw_dec_mem_rd_resp_s, weights_raw_dec_mem_rd_resp_r) = chan("weights_dec_mem_rd_resp"); - let (weights_fse_dec_mem_rd_req_s, weights_fse_dec_mem_rd_req_r) = chan("weights_dec_mem_rd_req"); - let (weights_fse_dec_mem_rd_resp_s, weights_fse_dec_mem_rd_resp_r) = chan("weights_dec_mem_rd_resp"); + let (weights_fse_lookup_dec_mem_rd_req_s, weights_fse_lookup_dec_mem_rd_req_r) = chan("weights_lookup_dec_mem_rd_req"); + let (weights_fse_lookup_dec_mem_rd_resp_s, weights_fse_lookup_dec_mem_rd_resp_r) = chan("weights_lookup_dec_mem_rd_resp"); + let (weights_fse_decoder_dec_mem_rd_req_s, weights_fse_decoder_dec_mem_rd_req_r) = chan("weights_decoder_dec_mem_rd_req"); + let (weights_fse_decoder_dec_mem_rd_resp_s, weights_fse_decoder_dec_mem_rd_resp_r) = chan("weights_decoder_dec_mem_rd_resp"); // code builder loopback let (weights_pow_sum_loopback_s, weights_pow_sum_loopback_r) = chan("weights_pow_sum_loopback"); @@ -165,21 +201,31 @@ pub proc HuffmanLiteralsDecoder< ); spawn mem_reader::MemReader( - weights_fse_dec_mem_rd_req_r, weights_fse_dec_mem_rd_resp_s, - weights_fse_dec_axi_ar_s, weights_fse_dec_axi_r_r + weights_fse_lookup_dec_mem_rd_req_r, weights_fse_lookup_dec_mem_rd_resp_s, + weights_fse_lookup_dec_axi_ar_s, weights_fse_lookup_dec_axi_r_r + ); + + spawn mem_reader::MemReader( + weights_fse_decoder_dec_mem_rd_req_r, weights_fse_decoder_dec_mem_rd_resp_s, + weights_fse_decoder_dec_axi_ar_s, weights_fse_decoder_dec_axi_r_r ); spawn weights_dec::HuffmanWeightsDecoder< - AXI_ADDR_W, AXI_DATA_W, - WEIGHTS_RAM_ADDR_WIDTH, - WEIGHTS_RAM_DATA_WIDTH, - WEIGHTS_RAM_NUM_PARTITIONS, + AXI_ADDR_W, AXI_DATA_W, AXI_ID_W, + WEIGHTS_RAM_ADDR_WIDTH, WEIGHTS_RAM_DATA_WIDTH, WEIGHTS_RAM_NUM_PARTITIONS, + WEIGHTS_DPD_RAM_ADDR_W, WEIGHTS_DPD_RAM_DATA_W, WEIGHTS_DPD_RAM_NUM_PARTITIONS, + WEIGHTS_TMP_RAM_ADDR_W, WEIGHTS_TMP_RAM_DATA_W, WEIGHTS_TMP_RAM_NUM_PARTITIONS, + WEIGHTS_FSE_RAM_ADDR_W, WEIGHTS_FSE_RAM_DATA_W, WEIGHTS_FSE_RAM_NUM_PARTITIONS, >( weights_dec_req_r, weights_dec_resp_s, weights_header_dec_mem_rd_req_s, weights_header_dec_mem_rd_resp_r, weights_raw_dec_mem_rd_req_s, weights_raw_dec_mem_rd_resp_r, - weights_fse_dec_mem_rd_req_s, weights_fse_dec_mem_rd_resp_r, + weights_fse_lookup_dec_mem_rd_req_s, weights_fse_lookup_dec_mem_rd_resp_r, + weights_fse_decoder_dec_mem_rd_req_s, weights_fse_decoder_dec_mem_rd_resp_r, weights_ram_wr_req_s, weights_ram_wr_resp_r, + weights_dpd_rd_req_s, weights_dpd_rd_resp_r, weights_dpd_wr_req_s, weights_dpd_wr_resp_r, + weights_tmp_rd_req_s, weights_tmp_rd_resp_r, weights_tmp_wr_req_s, weights_tmp_wr_resp_r, + weights_fse_rd_req_s, weights_fse_rd_resp_r, weights_fse_wr_req_s, weights_fse_wr_resp_r, ); spawn prescan::WeightPreScan( @@ -244,6 +290,30 @@ pub const INST_PRESCAN_RAM_ADDR_WIDTH = PRESCAN_ADDR_WIDTH; pub const INST_PRESCAN_RAM_DATA_WIDTH = PRESCAN_DATA_WIDTH; pub const INST_PRESCAN_RAM_NUM_PARTITIONS = PRESCAN_NUM_PARTITIONS; +const INST_WEIGHTS_DPD_RAM_DATA_W = u32:16; +const INST_WEIGHTS_DPD_RAM_SIZE = u32:256; +const INST_WEIGHTS_DPD_RAM_ADDR_W = std::clog2(INST_WEIGHTS_DPD_RAM_SIZE); +const INST_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE = INST_WEIGHTS_DPD_RAM_DATA_W; +const INST_WEIGHTS_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, INST_WEIGHTS_DPD_RAM_DATA_W +); + +const INST_WEIGHTS_FSE_RAM_DATA_W = u32:32; +const INST_WEIGHTS_FSE_RAM_SIZE = u32:256; +const INST_WEIGHTS_FSE_RAM_ADDR_W = std::clog2(INST_WEIGHTS_FSE_RAM_SIZE); +const INST_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE = INST_WEIGHTS_FSE_RAM_DATA_W / u32:3; +const INST_WEIGHTS_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, INST_WEIGHTS_FSE_RAM_DATA_W +); + +const INST_WEIGHTS_TMP_RAM_DATA_W = u32:16; +const INST_WEIGHTS_TMP_RAM_SIZE = u32:256; +const INST_WEIGHTS_TMP_RAM_ADDR_W = std::clog2(INST_WEIGHTS_TMP_RAM_SIZE); +const INST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE = INST_WEIGHTS_TMP_RAM_DATA_W; +const INST_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, INST_WEIGHTS_TMP_RAM_DATA_W +); + proc HuffmanLiteralsDecoderInst { type Ctrl = HuffmanLiteralsDecoderReq; type Resp = HuffmanLiteralsDecoderResp; @@ -259,6 +329,21 @@ proc HuffmanLiteralsDecoderInst { type PrescanRamWrReq = ram::WriteReq; type PrescanRamWrResp = ram::WriteResp; + type WeightsDpdRamRdReq = ram::ReadReq; + type WeightsDpdRamRdResp = ram::ReadResp; + type WeightsDpdRamWrReq = ram::WriteReq; + type WeightsDpdRamWrResp = ram::WriteResp; + + type WeightsTmpRamRdReq = ram::ReadReq; + type WeightsTmpRamRdResp = ram::ReadResp; + type WeightsTmpRamWrReq = ram::WriteReq; + type WeightsTmpRamWrResp = ram::WriteResp; + + type WeightsFseRamRdReq = ram::ReadReq; + type WeightsFseRamRdResp = ram::ReadResp; + type WeightsFseRamWrReq = ram::WriteReq; + type WeightsFseRamWrResp = ram::WriteResp; + config ( ctrl_r: chan in, resp_s: chan out, @@ -271,8 +356,10 @@ proc HuffmanLiteralsDecoderInst { weights_header_dec_axi_r_r: chan in, weights_raw_dec_axi_ar_s: chan out, weights_raw_dec_axi_r_r: chan in, - weights_fse_dec_axi_ar_s: chan out, - weights_fse_dec_axi_r_r: chan in, + weights_fse_lookup_dec_axi_ar_s: chan out, + weights_fse_lookup_dec_axi_r_r: chan in, + weights_fse_decoder_dec_axi_ar_s: chan out, + weights_fse_decoder_dec_axi_r_r: chan in, weights_ram_rd_req_s: chan out, weights_ram_rd_resp_r: chan in, weights_ram_wr_req_s: chan out, @@ -281,9 +368,24 @@ proc HuffmanLiteralsDecoderInst { prescan_ram_rd_resp_r: chan in, prescan_ram_wr_req_s: chan out, prescan_ram_wr_resp_r: chan in, + weights_dpd_rd_req_s: chan out, + weights_dpd_rd_resp_r: chan in, + weights_dpd_wr_req_s: chan out, + weights_dpd_wr_resp_r: chan in, + weights_tmp_rd_req_s: chan out, + weights_tmp_rd_resp_r: chan in, + weights_tmp_wr_req_s: chan out, + weights_tmp_wr_resp_r: chan in, + weights_fse_rd_req_s: chan out, + weights_fse_rd_resp_r: chan in, + weights_fse_wr_req_s: chan out, + weights_fse_wr_resp_r: chan in, ) { spawn HuffmanLiteralsDecoder< INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, + INST_WEIGHTS_DPD_RAM_ADDR_W, INST_WEIGHTS_DPD_RAM_DATA_W, INST_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + INST_WEIGHTS_TMP_RAM_ADDR_W, INST_WEIGHTS_TMP_RAM_DATA_W, INST_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + INST_WEIGHTS_FSE_RAM_ADDR_W, INST_WEIGHTS_FSE_RAM_DATA_W, INST_WEIGHTS_FSE_RAM_NUM_PARTITIONS, INST_WEIGHTS_RAM_ADDR_WIDTH, INST_WEIGHTS_RAM_DATA_WIDTH, INST_WEIGHTS_RAM_NUM_PARTITIONS, INST_PRESCAN_RAM_ADDR_WIDTH, INST_PRESCAN_RAM_DATA_WIDTH, INST_PRESCAN_RAM_NUM_PARTITIONS >( @@ -293,11 +395,18 @@ proc HuffmanLiteralsDecoderInst { jump_table_axi_ar_s, jump_table_axi_r_r, weights_header_dec_axi_ar_s, weights_header_dec_axi_r_r, weights_raw_dec_axi_ar_s, weights_raw_dec_axi_r_r, - weights_fse_dec_axi_ar_s, weights_fse_dec_axi_r_r, + weights_fse_lookup_dec_axi_ar_s, weights_fse_lookup_dec_axi_r_r, + weights_fse_decoder_dec_axi_ar_s, weights_fse_decoder_dec_axi_r_r, weights_ram_rd_req_s, weights_ram_rd_resp_r, weights_ram_wr_req_s, weights_ram_wr_resp_r, prescan_ram_rd_req_s, prescan_ram_rd_resp_r, prescan_ram_wr_req_s, prescan_ram_wr_resp_r, + weights_dpd_rd_req_s, weights_dpd_rd_resp_r, + weights_dpd_wr_req_s, weights_dpd_wr_resp_r, + weights_tmp_rd_req_s, weights_tmp_rd_resp_r, + weights_tmp_wr_req_s, weights_tmp_wr_resp_r, + weights_fse_rd_req_s, weights_fse_rd_resp_r, + weights_fse_wr_req_s, weights_fse_wr_resp_r, ); } @@ -337,6 +446,30 @@ pub const TEST_PRESCAN_RAM_NUM_PARTITIONS = PRESCAN_NUM_PARTITIONS; pub const TEST_PRESCAN_RAM_SIZE = prescan::RAM_SIZE; pub const TEST_PRESCAN_WORD_PARTITION_SIZE = prescan::WeightPreScanMetaDataSize(); +const TEST_WEIGHTS_DPD_RAM_DATA_W = u32:16; +const TEST_WEIGHTS_DPD_RAM_SIZE = u32:256; +const TEST_WEIGHTS_DPD_RAM_ADDR_W = std::clog2(TEST_WEIGHTS_DPD_RAM_SIZE); +const TEST_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE = TEST_WEIGHTS_DPD_RAM_DATA_W; +const TEST_WEIGHTS_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, TEST_WEIGHTS_DPD_RAM_DATA_W +); + +const TEST_WEIGHTS_FSE_RAM_DATA_W = u32:32; +const TEST_WEIGHTS_FSE_RAM_SIZE = u32:256; +const TEST_WEIGHTS_FSE_RAM_ADDR_W = std::clog2(TEST_WEIGHTS_FSE_RAM_SIZE); +const TEST_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE = TEST_WEIGHTS_FSE_RAM_DATA_W / u32:3; +const TEST_WEIGHTS_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, TEST_WEIGHTS_FSE_RAM_DATA_W +); + +const TEST_WEIGHTS_TMP_RAM_DATA_W = u32:16; +const TEST_WEIGHTS_TMP_RAM_SIZE = u32:256; +const TEST_WEIGHTS_TMP_RAM_ADDR_W = std::clog2(TEST_WEIGHTS_TMP_RAM_SIZE); +const TEST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE = TEST_WEIGHTS_TMP_RAM_DATA_W; +const TEST_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, TEST_WEIGHTS_TMP_RAM_DATA_W +); + type TestCtrl = HuffmanLiteralsDecoderReq; type TestResp = HuffmanLiteralsDecoderResp; type TestAxiR = axi::AxiR; @@ -363,6 +496,21 @@ type TestAxiRamData = uN[TEST_AXI_RAM_MODEL_DATA_WIDTH]; type TestAxiRamAddr = uN[TEST_AXI_RAM_MODEL_ADDR_WIDTH]; type TestAxiRamMask = uN[TEST_AXI_RAM_MODEL_NUM_PARTITIONS]; +type TestWeightsDpdRamRdReq = ram::ReadReq; +type TestWeightsDpdRamRdResp = ram::ReadResp; +type TestWeightsDpdRamWrReq = ram::WriteReq; +type TestWeightsDpdRamWrResp = ram::WriteResp; + +type TestWeightsTmpRamRdReq = ram::ReadReq; +type TestWeightsTmpRamRdResp = ram::ReadResp; +type TestWeightsTmpRamWrReq = ram::WriteReq; +type TestWeightsTmpRamWrResp = ram::WriteResp; + +type TestWeightsFseRamRdReq = ram::ReadReq; +type TestWeightsFseRamRdResp = ram::ReadResp; +type TestWeightsFseRamWrReq = ram::WriteReq; +type TestWeightsFseRamWrResp = ram::WriteResp; + // Data for test case // Source: Example from RFC 8878, 4.2.2. Huffman-Coded Streams // https://datatracker.ietf.org/doc/html/rfc8878#huffman_coded_streams @@ -569,8 +717,10 @@ proc HuffmanLiteralsDecoder_test { ram_wr_resp_huffman_weights_header_r : chan in; ram_wr_req_huffman_weights_raw_s : chan out; ram_wr_resp_huffman_weights_raw_r : chan in; - ram_wr_req_huffman_weights_fse_s : chan out; - ram_wr_resp_huffman_weights_fse_r : chan in; + ram_wr_req_huffman_weights_fse_lookup_s : chan out; + ram_wr_resp_huffman_weights_fse_lookup_r : chan in; + ram_wr_req_huffman_weights_fse_decoder_s : chan out; + ram_wr_resp_huffman_weights_fse_decoder_r : chan in; config (terminator: chan out) { let (ctrl_s, ctrl_r) = chan("ctrl"); @@ -584,8 +734,10 @@ proc HuffmanLiteralsDecoder_test { let (weights_header_dec_axi_r_s, weights_header_dec_axi_r_r) = chan("weights_header_dec_axi_r"); let (weights_raw_dec_axi_ar_s, weights_raw_dec_axi_ar_r) = chan("weights_raw_dec_axi_ar"); let (weights_raw_dec_axi_r_s, weights_raw_dec_axi_r_r) = chan("weights_raw_dec_axi_r"); - let (weights_fse_dec_axi_ar_s, weights_fse_dec_axi_ar_r) = chan("weights_fse_dec_axi_ar"); - let (weights_fse_dec_axi_r_s, weights_fse_dec_axi_r_r) = chan("weights_fse_dec_axi_r"); + let (weights_fse_lookup_dec_axi_ar_s, weights_fse_lookup_dec_axi_ar_r) = chan("weights_fse_lookup_dec_axi_ar"); + let (weights_fse_lookup_dec_axi_r_s, weights_fse_lookup_dec_axi_r_r) = chan("weights_fse_lookup_dec_axi_r"); + let (weights_fse_decoder_dec_axi_ar_s, weights_fse_decoder_dec_axi_ar_r) = chan("weights_fse_decoder_dec_axi_ar"); + let (weights_fse_decoder_dec_axi_r_s, weights_fse_decoder_dec_axi_r_r) = chan("weights_fse_decoder_dec_axi_r"); // weights internal memory let (weights_ram_rd_req_s, weights_ram_rd_req_r) = chan("weights_ram_rd_req"); @@ -599,21 +751,62 @@ proc HuffmanLiteralsDecoder_test { let (prescan_ram_rd_req_s, prescan_ram_rd_req_r) = chan("prescan_ram_rd_req"); let (prescan_ram_rd_resp_s, prescan_ram_rd_resp_r) = chan("prescan_ram_rd_resp"); + // Weights FSE RAMs + let (weights_dpd_rd_req_s, weights_dpd_rd_req_r) = chan("weights_dpd_rd_req"); + let (weights_dpd_rd_resp_s, weights_dpd_rd_resp_r) = chan("weights_dpd_rd_resp"); + let (weights_dpd_wr_req_s, weights_dpd_wr_req_r) = chan("weights_dpd_wr_req"); + let (weights_dpd_wr_resp_s, weights_dpd_wr_resp_r) = chan("weights_dpd_wr_resp"); + + spawn ram::RamModel< + TEST_WEIGHTS_DPD_RAM_DATA_W, + TEST_WEIGHTS_DPD_RAM_SIZE, + TEST_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE + >(weights_dpd_rd_req_r, weights_dpd_rd_resp_s, weights_dpd_wr_req_r, weights_dpd_wr_resp_s); + + let (weights_tmp_rd_req_s, weights_tmp_rd_req_r) = chan("weights_tmp_rd_req"); + let (weights_tmp_rd_resp_s, weights_tmp_rd_resp_r) = chan("weights_tmp_rd_resp"); + let (weights_tmp_wr_req_s, weights_tmp_wr_req_r) = chan("weights_tmp_wr_req"); + let (weights_tmp_wr_resp_s, weights_tmp_wr_resp_r) = chan("weights_tmp_wr_resp"); + + spawn ram::RamModel< + TEST_WEIGHTS_TMP_RAM_DATA_W, + TEST_WEIGHTS_TMP_RAM_SIZE, + TEST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE + >(weights_tmp_rd_req_r, weights_tmp_rd_resp_s, weights_tmp_wr_req_r, weights_tmp_wr_resp_s); + + let (weights_fse_rd_req_s, weights_fse_rd_req_r) = chan("weights_tmp_rd_req"); + let (weights_fse_rd_resp_s, weights_fse_rd_resp_r) = chan("weights_tmp_rd_resp"); + let (weights_fse_wr_req_s, weights_fse_wr_req_r) = chan("weights_tmp_wr_req"); + let (weights_fse_wr_resp_s, weights_fse_wr_resp_r) = chan("weights_tmp_wr_resp"); + + spawn ram::RamModel< + TEST_WEIGHTS_FSE_RAM_DATA_W, + TEST_WEIGHTS_FSE_RAM_SIZE, + TEST_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE + >(weights_fse_rd_req_r, weights_fse_rd_resp_s, weights_fse_wr_req_r, weights_fse_wr_resp_s); + spawn HuffmanLiteralsDecoder< TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_DEST_W, + TEST_WEIGHTS_DPD_RAM_ADDR_W, TEST_WEIGHTS_DPD_RAM_DATA_W, TEST_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + TEST_WEIGHTS_TMP_RAM_ADDR_W, TEST_WEIGHTS_TMP_RAM_DATA_W, TEST_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + TEST_WEIGHTS_FSE_RAM_ADDR_W, TEST_WEIGHTS_FSE_RAM_DATA_W, TEST_WEIGHTS_FSE_RAM_NUM_PARTITIONS, TEST_WEIGHTS_RAM_ADDR_WIDTH, TEST_WEIGHTS_RAM_DATA_WIDTH, TEST_WEIGHTS_RAM_NUM_PARTITIONS, - TEST_PRESCAN_RAM_ADDR_WIDTH, TEST_PRESCAN_RAM_DATA_WIDTH, TEST_PRESCAN_RAM_NUM_PARTITIONS + TEST_PRESCAN_RAM_ADDR_WIDTH, TEST_PRESCAN_RAM_DATA_WIDTH, TEST_PRESCAN_RAM_NUM_PARTITIONS, >( ctrl_r, resp_s, decoded_literals_s, axi_ar_s, axi_r_r, jump_table_axi_ar_s, jump_table_axi_r_r, weights_header_dec_axi_ar_s, weights_header_dec_axi_r_r, weights_raw_dec_axi_ar_s, weights_raw_dec_axi_r_r, - weights_fse_dec_axi_ar_s, weights_fse_dec_axi_r_r, + weights_fse_lookup_dec_axi_ar_s, weights_fse_lookup_dec_axi_r_r, + weights_fse_decoder_dec_axi_ar_s, weights_fse_decoder_dec_axi_r_r, weights_ram_rd_req_s, weights_ram_rd_resp_r, weights_ram_wr_req_s, weights_ram_wr_resp_r, prescan_ram_rd_req_s, prescan_ram_rd_resp_r, prescan_ram_wr_req_s, prescan_ram_wr_resp_r, + weights_dpd_rd_req_s, weights_dpd_rd_resp_r, weights_dpd_wr_req_s, weights_dpd_wr_resp_r, + weights_tmp_rd_req_s, weights_tmp_rd_resp_r, weights_tmp_wr_req_s, weights_tmp_wr_resp_r, + weights_fse_rd_req_s, weights_fse_rd_resp_r, weights_fse_wr_req_s, weights_fse_wr_resp_r, ); // Mock RAM for HuffmanLiteralsDecoder MemReader @@ -721,10 +914,35 @@ proc HuffmanLiteralsDecoder_test { ); // Mock RAM for HuffmanWeights fse decoder MemReader - let (ram_rd_req_huffman_weights_fse_s, ram_rd_req_huffman_weights_fse_r) = chan("ram_rd_req_huffman_weights_fse"); - let (ram_rd_resp_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r) = chan("ram_rd_resp_huffman_weights_fse"); - let (ram_wr_req_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r) = chan("ram_wr_req_huffman_weights_fse"); - let (ram_wr_resp_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r) = chan("ram_wr_resp_huffman_weights_fse"); + let (ram_rd_req_huffman_weights_fse_lookup_s, ram_rd_req_huffman_weights_fse_lookup_r) = chan("ram_rd_req_huffman_weights_fse_lookup"); + let (ram_rd_resp_huffman_weights_fse_lookup_s, ram_rd_resp_huffman_weights_fse_lookup_r) = chan("ram_rd_resp_huffman_weights_fse_lookup"); + let (ram_wr_req_huffman_weights_fse_lookup_s, ram_wr_req_huffman_weights_fse_lookup_r) = chan("ram_wr_req_huffman_weights_fse_lookup"); + let (ram_wr_resp_huffman_weights_fse_lookup_s, ram_wr_resp_huffman_weights_fse_lookup_r) = chan("ram_wr_resp_huffman_weights_fse_lookup"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_fse_lookup_r, ram_rd_resp_huffman_weights_fse_lookup_s, ram_wr_req_huffman_weights_fse_lookup_r, ram_wr_resp_huffman_weights_fse_lookup_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + weights_fse_lookup_dec_axi_ar_r, weights_fse_lookup_dec_axi_r_s, + ram_rd_req_huffman_weights_fse_lookup_s, ram_rd_resp_huffman_weights_fse_lookup_r + ); + + let (ram_rd_req_huffman_weights_fse_decoder_s, ram_rd_req_huffman_weights_fse_decoder_r) = chan("ram_rd_req_huffman_weights_fse"); + let (ram_rd_resp_huffman_weights_fse_decoder_s, ram_rd_resp_huffman_weights_fse_decoder_r) = chan("ram_rd_resp_huffman_weights_fse"); + let (ram_wr_req_huffman_weights_fse_decoder_s, ram_wr_req_huffman_weights_fse_decoder_r) = chan("ram_wr_req_huffman_weights_fse"); + let (ram_wr_resp_huffman_weights_fse_decoder_s, ram_wr_resp_huffman_weights_fse_decoder_r) = chan("ram_wr_resp_huffman_weights_fse"); spawn ram::RamModel< TEST_AXI_RAM_MODEL_DATA_WIDTH, @@ -735,15 +953,15 @@ proc HuffmanLiteralsDecoder_test { TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( - ram_rd_req_huffman_weights_fse_r, ram_rd_resp_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r, ram_wr_resp_huffman_weights_fse_s + ram_rd_req_huffman_weights_fse_decoder_r, ram_rd_resp_huffman_weights_fse_decoder_s, ram_wr_req_huffman_weights_fse_decoder_r, ram_wr_resp_huffman_weights_fse_decoder_s ); spawn axi_ram::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( - weights_fse_dec_axi_ar_r, weights_fse_dec_axi_r_s, - ram_rd_req_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r + weights_fse_decoder_dec_axi_ar_r, weights_fse_decoder_dec_axi_r_s, + ram_rd_req_huffman_weights_fse_decoder_s, ram_rd_resp_huffman_weights_fse_decoder_r ); spawn ram::RamModel< @@ -767,7 +985,8 @@ proc HuffmanLiteralsDecoder_test { ram_wr_req_jump_table_s, ram_wr_resp_jump_table_r, ram_wr_req_huffman_weights_header_s, ram_wr_resp_huffman_weights_header_r, ram_wr_req_huffman_weights_raw_s, ram_wr_resp_huffman_weights_raw_r, - ram_wr_req_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r + ram_wr_req_huffman_weights_fse_lookup_s, ram_wr_resp_huffman_weights_fse_lookup_r, + ram_wr_req_huffman_weights_fse_decoder_s, ram_wr_resp_huffman_weights_fse_decoder_r, ) } @@ -788,8 +1007,10 @@ proc HuffmanLiteralsDecoder_test { let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_header_r); let tok = send(tok, ram_wr_req_huffman_weights_raw_s, mem_req); let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_raw_r); - let tok = send(tok, ram_wr_req_huffman_weights_fse_s, mem_req); - let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_r); + let tok = send(tok, ram_wr_req_huffman_weights_fse_lookup_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_lookup_r); + let tok = send(tok, ram_wr_req_huffman_weights_fse_decoder_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_decoder_r); tok }(tok); trace_fmt!("Filling system memory mock done"); diff --git a/xls/modules/zstd/huffman_weights_dec.x b/xls/modules/zstd/huffman_weights_dec.x index e44b0d11d0..bf71a615dc 100644 --- a/xls/modules/zstd/huffman_weights_dec.x +++ b/xls/modules/zstd/huffman_weights_dec.x @@ -14,12 +14,20 @@ import std; -import xls.examples.ram as ram; -import xls.modules.zstd.huffman_prescan as huffman_prescan; -import xls.modules.zstd.memory.axi as axi; -import xls.modules.zstd.memory.axi_ram as axi_ram; -import xls.modules.zstd.memory.mem_reader as mem_reader; -import xls.modules.zstd.ram_mux as ram_mux; +import xls.examples.ram; +import xls.modules.zstd.common ; +import xls.modules.zstd.huffman_prescan; +import xls.modules.zstd.memory.axi; +import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.mem_reader; +import xls.modules.zstd.ram_mux; +import xls.modules.zstd.refilling_shift_buffer; +import xls.modules.zstd.fse_lookup_dec; +import xls.modules.zstd.fse_table_creator; +import xls.modules.zstd.math; + +const HUFFMAN_FSE_MAX_ACCURACY_LOG = u32:9; +const HUFFMAN_FSE_ACCURACY_W = std::clog2(HUFFMAN_FSE_MAX_ACCURACY_LOG + u32:1); struct HuffmanRawWeightsDecoderReq { addr: uN[AXI_ADDR_W], @@ -323,8 +331,522 @@ proc HuffmanRawWeightsDecoder< } } + +enum HuffmanFseDecoderStatus: u1 { + OK = 0, + ERROR = 1, +} + +struct HuffmanFseDecoderCtrl { + acc_log: uN[HUFFMAN_FSE_ACCURACY_W ], + length: u8, +} + +struct HuffmanFseDecoderFinish { + status: HuffmanFseDecoderStatus, +} + +type HuffmanFseTableRecord = common::FseTableRecord; + +struct CommandConstructorData {} + +enum HuffmanFseDecoderFSM : u4 { + RECV_CTRL = 0, + PADDING = 1, + INIT_EVEN_STATE = 2, + INIT_ODD_STATE = 3, + SEND_RAM_EVEN_RD_REQ = 4, + RECV_RAM_EVEN_RD_RESP = 5, + SEND_RAM_ODD_RD_REQ = 6, + RECV_RAM_ODD_RD_RESP = 7, + UPDATE_EVEN_STATE = 8, + UPDATE_ODD_STATE = 9, + DECODE_LAST_WEIGHT = 10, + SEND_WEIGHT = 11, + SEND_WEIGHT_DONE = 12, + FILL_ZEROS = 13, + SEND_FINISH = 14, +} +struct HuffmanFseDecoderState { + fsm: HuffmanFseDecoderFSM, + ctrl: HuffmanFseDecoderCtrl, // decode request + even: u8, + odd: u8, + even_table_record: HuffmanFseTableRecord, // FSE lookup record for even_state + odd_table_record: HuffmanFseTableRecord, // FSE lookup record for odd_state + even_table_record_valid: bool, + odd_table_record_valid: bool, + even_state: u16, // analogous to state1 in educational ZSTD decoder + odd_state: u16, // analogous to state1 in educational ZSTD decoder + // https://github.com/facebook/zstd/blob/fe34776c207f3f879f386ed4158a38d927ff6d10/doc/educational_decoder/zstd_decompress.c#L2069 + read_bits_needed: u7, // how many bits to request from the ShiftBuffer next + sent_buf_ctrl: bool, // have we sent request to ShiftBuffer in this FSM state already? + shift_buffer_error: bool, // sticky flag, asserted if ShiftBuffer returns error in data + // payload, cleared when going to initial state + padding: u4, // how much padding have we consumed (used for checking stream validity) + current_iteration: u8, // which iteration of the FSE-encoded-weights decoding loop are we in: + // https://github.com/facebook/zstd/blob/fe34776c207f3f879f386ed4158a38d927ff6d10/doc/educational_decoder/zstd_decompress.c#L2081 + stream_len: u8, // how long is the FSE-encoded-weights stream, in bytes + stream_empty: bool, // did we ask for more bits than available in the stream (i.e. caused stream underflow)? + // analogous to 'offset < 0' check from educational ZSTD decoder: + // https://github.com/facebook/zstd/blob/fe34776c207f3f879f386ed4158a38d927ff6d10/doc/educational_decoder/zstd_decompress.c#L2089 + last_weight: u1, // whether the last weight is odd (last_weight == 1) or even (last_weight == 0) - + // - analogue to whether we should end up here: + // https://github.com/facebook/zstd/blob/fe34776c207f3f879f386ed4158a38d927ff6d10/doc/educational_decoder/zstd_decompress.c#L2091 + // ...or here: + // https://github.com/facebook/zstd/blob/fe34776c207f3f879f386ed4158a38d927ff6d10/doc/educational_decoder/zstd_decompress.c#L2100 + weights_pow_of_two_sum: u32, // sum of 2^weight for all weights, needed to calculate last weight + last_weight_decoded: bool, // have we decoded last weight? +} + +pub proc HuffmanFseDecoder< + RAM_DATA_W: u32, RAM_ADDR_W: u32, RAM_NUM_PARTITIONS:u32, + WEIGHTS_RAM_DATA_W: u32, WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_NUM_PARTITIONS: u32, + AXI_DATA_W: u32, + REFILLING_SB_DATA_W: u32 = {AXI_DATA_W}, + REFILLING_SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(REFILLING_SB_DATA_W)}, +> { + type Ctrl = HuffmanFseDecoderCtrl; + type Finish = HuffmanFseDecoderFinish; + type Status = HuffmanFseDecoderStatus; + type State = HuffmanFseDecoderState; + type FSM = HuffmanFseDecoderFSM; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + + type RefillingSBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type RefillingSBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + + type WeightsRamWrReq = ram::WriteReq; + type WeightsRamWrResp = ram::WriteResp; + + // Control + ctrl_r: chan in; + finish_s: chan out; + + // Shift buffer + rsb_ctrl_s: chan out; + rsb_data_r: chan in; + + // FSE table RAMs + table_rd_req_s: chan out; + table_rd_resp_r: chan in; + + // Weights RAMs + weights_wr_req_s: chan out; + weights_wr_resp_r: chan in; + + config ( + ctrl_r: chan in, + finish_s: chan out, + rsb_ctrl_s: chan out, + rsb_data_r: chan in, + table_rd_req_s: chan out, + table_rd_resp_r: chan in, + weights_wr_req_s: chan out, + weights_wr_resp_r: chan in, + ) { + ( + ctrl_r, finish_s, + rsb_ctrl_s, rsb_data_r, + table_rd_req_s, table_rd_resp_r, + weights_wr_req_s, weights_wr_resp_r, + ) + } + + init { zero!() } + + next (state: HuffmanFseDecoderState) { + type RamAddr = uN[RAM_ADDR_W]; + const RAM_MASK_ALL = std::unsigned_max_value(); + + let tok = join(); + + // receive ctrl + let (_, ctrl, ctrl_valid) = recv_if_non_blocking(tok, ctrl_r, state.fsm == FSM::RECV_CTRL, zero!()); + if ctrl_valid { + trace_fmt!("ctrl: {:#x}", ctrl); + } else {}; + let state = if ctrl_valid { + HuffmanFseDecoderState { + ctrl: ctrl, + stream_len: ctrl.length * u8:8, + ..state + } + } else { state }; + + // receive ram read response + let do_recv_table_rd_resp = state.fsm == FSM::RECV_RAM_EVEN_RD_RESP || state.fsm == FSM::RECV_RAM_ODD_RD_RESP; + let (_, table_rd_resp, table_rd_resp_valid) = recv_if_non_blocking(tok, table_rd_resp_r, do_recv_table_rd_resp, zero!()); + + let table_record = fse_table_creator::bits_to_fse_record(table_rd_resp.data); + + if table_rd_resp_valid { + trace_fmt!("table_record: {:#x}", table_record); + } else {}; + + // request records + let do_send_ram_rd_req = state.fsm == FSM::SEND_RAM_EVEN_RD_REQ || state.fsm == FSM::SEND_RAM_ODD_RD_REQ; + let ram_rd_req_addr = match (state.fsm) { + FSM::SEND_RAM_EVEN_RD_REQ => state.even_state as RamAddr, + FSM::SEND_RAM_ODD_RD_REQ => state.odd_state as RamAddr, + _ => RamAddr:0, + }; + + let table_req = FseRamRdReq { addr: ram_rd_req_addr, mask: RAM_MASK_ALL }; + + send_if(tok, table_rd_req_s, do_send_ram_rd_req, table_req); + + if do_send_ram_rd_req { + trace_fmt!("table_req: {:#x}", table_req); + } else {}; + + // read bits + let do_read_bits = ( + state.fsm == FSM::PADDING || + state.fsm == FSM::INIT_EVEN_STATE || + state.fsm == FSM::INIT_ODD_STATE || + state.fsm == FSM::UPDATE_EVEN_STATE || + state.fsm == FSM::UPDATE_ODD_STATE + ); + let do_send_buf_ctrl = do_read_bits && !state.sent_buf_ctrl && state.stream_len > u8:0; + + let read_length = if state.read_bits_needed as u8 > state.stream_len { + state.stream_len as u7 + } else { + state.read_bits_needed + }; + + let state = if state.read_bits_needed > u7:0 { + HuffmanFseDecoderState { + stream_empty: state.read_bits_needed as u8 > state.stream_len, + ..state + } + } else { state }; + + if do_send_buf_ctrl { + trace_fmt!("[FseDecoder] Asking for {:#x} data", read_length); + } else {}; + + send_if(tok, rsb_ctrl_s, do_send_buf_ctrl, RefillingSBCtrl { + length: read_length, + }); + + let state = if do_send_buf_ctrl { + HuffmanFseDecoderState { sent_buf_ctrl: do_send_buf_ctrl, ..state } + } else { state }; + + let recv_sb_output = (do_read_bits && state.sent_buf_ctrl); + let (_, buf_data, buf_data_valid) = recv_if_non_blocking(tok, rsb_data_r, recv_sb_output, zero!()); + if buf_data_valid && buf_data.length as u32 > u32:0{ + trace_fmt!("[FseDecoder] Received data {:#x} in state {}", buf_data, state.fsm); + } else { }; + + let state = if do_read_bits & buf_data_valid { + HuffmanFseDecoderState { + sent_buf_ctrl: false, + shift_buffer_error: state.shift_buffer_error | buf_data.error, + stream_len: state.stream_len - buf_data.length as u8, + ..state + } + } else { state }; + + // decode last weight + let max_bits = common::highest_set_bit(state.weights_pow_of_two_sum) + u32:1; + let next_power = u32:1 << max_bits; + let left_over = (next_power - state.weights_pow_of_two_sum); + let last_weight = (common::highest_set_bit(left_over) + u32:1) as u8; + + // write weight + const WEIGHTS_RAM_BYTES = WEIGHTS_RAM_DATA_W as u8 / u8:8; + let iter_mod4_inv = u8:3 - (state.current_iteration & u8:0x3); + let weight = (((state.even as u8) << u32:4) & u8:0xF0) | ((state.odd as u8) & u8:0x0F); + let weights_wr_req = WeightsRamWrReq { + addr: (state.current_iteration / WEIGHTS_RAM_BYTES) as uN[WEIGHTS_RAM_ADDR_W], + data: (weight as uN[WEIGHTS_RAM_DATA_W] << (u8:8 * iter_mod4_inv)), + // mask appropriate byte in 32-bit word with 4-bit slices + mask: uN[WEIGHTS_RAM_NUM_PARTITIONS]:0x3 << (u8:2 * iter_mod4_inv), + }; + let tok = send_if(tok, weights_wr_req_s, state.fsm == FSM::SEND_WEIGHT, weights_wr_req); + if (state.fsm == FSM::SEND_WEIGHT) { + trace_fmt!("Sent weight to RAM: {:#x}", weights_wr_req); + } else {}; + + let (tok, _, weights_wr_resp_valid) = recv_if_non_blocking( + tok, weights_wr_resp_r, state.fsm == FSM::SEND_WEIGHT_DONE, zero!() + ); + + // send finish + send_if(tok, finish_s, state.fsm == FSM::SEND_FINISH, Finish { + status: if state.shift_buffer_error { Status::ERROR } else { Status::OK } + }); + + // update state + match (state.fsm) { + FSM::RECV_CTRL => { + if (ctrl_valid) { + trace_fmt!("[FseDecoder] Moving to PADDING"); + State { + fsm: FSM::PADDING, + ctrl: ctrl, + read_bits_needed: u7:1, + ..state + } + } else { state } + }, + FSM::PADDING => { + if (buf_data_valid) { + let padding = state.padding + u4:1; + assert!(padding <= u4:8, "invalid_padding"); + + let padding_available = (buf_data.data as u1 == u1:0); + if padding_available { + State { + fsm: FSM::PADDING, + read_bits_needed: u7:1, + padding, ..state + } + } else { + trace_fmt!("[FseDecoder] Moving to INIT_LOOKUP_STATE"); + trace_fmt!("padding is: {:#x}", padding); + State { + fsm: FSM::INIT_EVEN_STATE, + read_bits_needed: state.ctrl.acc_log as u7, + ..state + } + } + } else { state } + }, + FSM::INIT_EVEN_STATE => { + if (buf_data_valid) { + trace_fmt!("[FseDecoder] Moving to INIT_ODD_STATE"); + State { + fsm: FSM::INIT_ODD_STATE, + even_state: buf_data.data as u16, + read_bits_needed: state.ctrl.acc_log as u7, + ..state + } + } else { state } + }, + FSM::INIT_ODD_STATE => { + if (buf_data_valid) { + trace_fmt!("[FseDecoder] Moving to SEND_RAM_EVEN_RD_REQ"); + State { + fsm: FSM::SEND_RAM_EVEN_RD_REQ, + odd_state: buf_data.data as u16, + read_bits_needed: u7:0, + ..state + } + } else { state } + }, + FSM::SEND_RAM_EVEN_RD_REQ => { + trace_fmt!("[FseDecoder] Moving to RECV_RAM_EVEN_RD_RESP"); + trace_fmt!("State even: {:#x}", state.even_state); + State { + fsm: FSM::RECV_RAM_EVEN_RD_RESP, + even_table_record_valid: false, + ..state + } + }, + FSM::RECV_RAM_EVEN_RD_RESP => { + // save fse records in state + let state = if table_rd_resp_valid { + State { even_table_record: table_record, even_table_record_valid: true, ..state } + } else { state }; + + if state.even_table_record_valid { + let symbol = state.even_table_record.symbol; + let pow = if symbol != u8:0 { + u32:1 << (symbol - u8:1) + } else { + u32:0 + }; + if state.stream_empty { + trace_fmt!("[FseDecoder] Moving to DECODE_LAST_WEIGHT"); + State { + fsm: FSM::DECODE_LAST_WEIGHT, + even: symbol, + weights_pow_of_two_sum: state.weights_pow_of_two_sum + pow, + ..state + } + } else { + trace_fmt!("[FseDecoder] Moving to SEND_RAM_ODD_RD_REQ"); + State { + fsm: FSM::SEND_RAM_ODD_RD_REQ, + even: symbol, + weights_pow_of_two_sum: state.weights_pow_of_two_sum + pow, + ..state + } + } + } else { state } + }, + FSM::SEND_RAM_ODD_RD_REQ => { + trace_fmt!("[FseDecoder] Moving to RECV_RAM_ODD_RD_RESP"); + trace_fmt!("State odd: {:#x}", state.odd_state); + State { + fsm: FSM::RECV_RAM_ODD_RD_RESP, + odd_table_record_valid: false, + ..state + } + }, + FSM::RECV_RAM_ODD_RD_RESP => { + // save fse records in state + let state = if table_rd_resp_valid { + State { odd_table_record: table_record, odd_table_record_valid: true, ..state } + } else { state }; + + if state.odd_table_record_valid { + let symbol = state.odd_table_record.symbol; + let pow = if symbol != u8:0 { + u32:1 << (symbol - u8:1) + } else { + u32:0 + }; + if state.stream_empty { + trace_fmt!("[FseDecoder] Moving to SEND_WEIGHT"); + State { + fsm: FSM::DECODE_LAST_WEIGHT, + odd: symbol, + weights_pow_of_two_sum: state.weights_pow_of_two_sum + pow, + ..state + } + } else { + trace_fmt!("[FseDecoder] Moving to UPDATE_EVEN_STATE"); + State { + fsm: FSM::UPDATE_EVEN_STATE, + odd: state.odd_table_record.symbol, + weights_pow_of_two_sum: state.weights_pow_of_two_sum + pow, + read_bits_needed: state.even_table_record.num_of_bits as u7, + ..state + } + } + } else { state } + }, + FSM::UPDATE_EVEN_STATE => { + if state.stream_empty { + trace_fmt!("[FseDecoder] Moving to SEND_WEIGHT"); + State { + fsm: FSM::SEND_WEIGHT, + even_state: state.even_table_record.base + buf_data.data as u16, + read_bits_needed: state.odd_table_record.num_of_bits as u7, + last_weight: u1:0, + ..state + } + } else if buf_data_valid || state.stream_len == u8:0 { + trace_fmt!("[FseDecoder] Moving to UPDATE_ODD_STATE"); + State { + fsm: FSM::UPDATE_ODD_STATE, + even_state: state.even_table_record.base + buf_data.data as u16, + read_bits_needed: state.odd_table_record.num_of_bits as u7, + ..state + } + } else { state } + }, + FSM::UPDATE_ODD_STATE => { + if state.stream_empty { + trace_fmt!("[FseDecoder] Moving to SEND_WEIGHT"); + State { + fsm: FSM::SEND_WEIGHT, + odd_state: state.odd_table_record.base + buf_data.data as u16, + read_bits_needed: u7:0, + last_weight: u1:1, + ..state + } + } else if buf_data_valid || state.stream_len == u8:0 { + trace_fmt!("[FseDecoder] Moving to SEND_WEIGHT"); + State { + fsm: FSM::SEND_WEIGHT, + odd_state: state.odd_table_record.base + buf_data.data as u16, + read_bits_needed: u7:0, + ..state + } + } else { state } + }, + FSM::DECODE_LAST_WEIGHT => { + trace_fmt!("[FseDecoder] Moving to SEND_WEIGHT"); + trace_fmt!("[FseDecoder] Last weight {:#x}, weights^2: {}, max_bits: {}, left_over: {}, iteration {}", last_weight, state.weights_pow_of_two_sum, max_bits, left_over, state.current_iteration); + if state.last_weight == u1:0 { + State { + fsm: FSM::SEND_WEIGHT, + even: last_weight, + odd: u8:0, + last_weight_decoded: true, + ..state + } + } else { + State { + fsm: FSM::SEND_WEIGHT, + // even weight should be kept unchanged + odd: last_weight, + last_weight_decoded: true, + ..state + } + } + }, + FSM::SEND_WEIGHT => { + trace_fmt!("[FseDecoder] Current iteration: {}, weights: {} {} {}", state.current_iteration, state.even_state, state.odd_state, weight); + State { + fsm: FSM::SEND_WEIGHT_DONE, + current_iteration: state.current_iteration + u8:1, + ..state + } + }, + FSM::SEND_WEIGHT_DONE => { + if weights_wr_resp_valid { + trace_fmt!("Weights write done"); + let fsm = if state.stream_empty { + if state.last_weight_decoded { + FSM::FILL_ZEROS + } else { + // get second-to-last weight + if state.last_weight == u1:1 { + FSM::SEND_RAM_EVEN_RD_REQ + } else { + FSM::SEND_RAM_ODD_RD_REQ + } + } + } else { + FSM::SEND_RAM_EVEN_RD_REQ + }; + State { + fsm: fsm, + ..state + } + } else { state } + }, + FSM::FILL_ZEROS => { + if state.current_iteration == u8:0x7F { + State { + fsm: FSM::SEND_FINISH, + ..state + } + } else { + State { + fsm: FSM::SEND_WEIGHT, + even: u8:0, + odd: u8:0, + ..state + } + } + }, + FSM::SEND_FINISH => { + trace_fmt!("[FseDecoder] Moving to RECV_CTRL"); + State { + fsm:FSM::RECV_CTRL, + ..zero!() + } + }, + _ => { + fail!("impossible_case", state) + }, + } + } +} + struct HuffmanFseWeightsDecoderReq { - addr: uN[AXI_ADDR_W] + addr: uN[AXI_ADDR_W], + length: u8, } enum HuffmanFseWeightsDecoderStatus: u1 { @@ -336,14 +858,17 @@ struct HuffmanFseWeightsDecoderResp { status: HuffmanFseWeightsDecoderStatus, } -struct HuffmanFseWeightsDecoderState { - placeholder: u1 -} +struct HuffmanFseWeightsDecoderState { } proc HuffmanFseWeightsDecoder< - AXI_ADDR_W: u32, AXI_DATA_W: u32, - WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, - WEIGHTS_RAM_NUM_PARTITIONS: u32 + AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_ID_W: u32, + WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, WEIGHTS_RAM_NUM_PARTITIONS: u32, + DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, + FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + REFILLING_SB_DATA_W: u32 = {AXI_DATA_W}, + REFILLING_SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, > { type Req = HuffmanFseWeightsDecoderReq; type Resp = HuffmanFseWeightsDecoderResp; @@ -356,16 +881,58 @@ proc HuffmanFseWeightsDecoder< type WeightsRamWrReq = ram::WriteReq; type WeightsRamWrResp = ram::WriteResp; + type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; + type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; + + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type RefillingShiftBufferStart = refilling_shift_buffer::RefillStart; + type RefillingShiftBufferError = refilling_shift_buffer::RefillingShiftBufferInput; + type RefillingShiftBufferOutput = refilling_shift_buffer::RefillingShiftBufferOutput; + type RefillingShiftBufferCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + // Control req_r: chan in; resp_s: chan out; - // MemReader interface for fetching Huffman Tree Description - mem_rd_req_s: chan out; - mem_rd_resp_r: chan in; + // Refilling shift buffer for lookup decoder + fld_rsb_start_req_s: chan out; + fld_rsb_stop_flush_req_s: chan<()> out; + fld_rsb_flushing_done_r: chan<()> in; - weights_ram_wr_req_s: chan out; - weights_ram_wr_resp_r: chan in; + // Refilling shift buffer for FSE decoder + fd_rsb_start_req_s: chan out; + fd_rsb_stop_flush_req_s: chan<()> out; + fd_rsb_flushing_done_r: chan<()> in; + + // FSE Lookup Decoder + fld_req_s: chan out; + fld_resp_r: chan in; + + // Huffman FSE Decoder + fd_ctrl_s: chan out; + fd_finish_r: chan in; init { zero!() @@ -377,34 +944,159 @@ proc HuffmanFseWeightsDecoder< resp_s: chan out, // MemReader interface for fetching Huffman Tree Description - mem_rd_req_s: chan out, - mem_rd_resp_r: chan in, + lookup_mem_rd_req_s: chan out, + lookup_mem_rd_resp_r: chan in, + decoder_mem_rd_req_s: chan out, + decoder_mem_rd_resp_r: chan in, // RAM Write interface (goes to Huffman Weights Memory) weights_ram_wr_req_s: chan out, weights_ram_wr_resp_r: chan in, + + // FSE RAMs + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + + fse_rd_req_s: chan out, + fse_rd_resp_r: chan in, + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, ) { + const CHANNEL_DEPTH = u32:1; + + // FseLookupDecoder + let (fld_rsb_start_req_s, fld_rsb_start_req_r) = chan("fd_rsb_start_req"); + let (fld_rsb_stop_flush_req_s, fld_rsb_stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_stop_flush_req"); + let (fld_rsb_ctrl_s, fld_rsb_ctrl_r) = chan("fd_rsb_ctrl"); + let (fld_rsb_data_s, fld_rsb_data_r) = chan("fd_rsb_data"); + let (fld_rsb_flushing_done_s, fld_rsb_flushing_done_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_flushing_done"); + + spawn refilling_shift_buffer::RefillingShiftBuffer ( + lookup_mem_rd_req_s, lookup_mem_rd_resp_r, + fld_rsb_start_req_r, fld_rsb_stop_flush_req_r, + fld_rsb_ctrl_r, fld_rsb_data_s, + fld_rsb_flushing_done_s, + ); + + let (fld_req_s, fld_req_r) = chan("fse_req"); + let (fld_resp_s, fld_resp_r) = chan("fse_resp"); + + spawn fse_lookup_dec::FseLookupDecoder< + AXI_DATA_W, + DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, + TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_DATA_W, TMP2_RAM_ADDR_W, TMP2_RAM_NUM_PARTITIONS, + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, + >( + fld_req_r, fld_resp_s, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_wr_req_s, fse_wr_resp_r, + fld_rsb_ctrl_s, fld_rsb_data_r, + ); + + // Huffman FSE Decoder + let (fd_rsb_start_req_s, fd_rsb_start_req_r) = chan("fd_rsb_start_req"); + let (fd_rsb_stop_flush_req_s, fd_rsb_stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_stop_flush_req"); + let (fd_rsb_ctrl_s, fd_rsb_ctrl_r) = chan("fd_rsb_ctrl"); + let (fd_rsb_data_s, fd_rsb_data_r) = chan("fd_rsb_data"); + let (fd_rsb_flushing_done_s, fd_rsb_flushing_done_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_flushing_done"); + + spawn refilling_shift_buffer::RefillingShiftBuffer ( + decoder_mem_rd_req_s, decoder_mem_rd_resp_r, + fd_rsb_start_req_r, fd_rsb_stop_flush_req_r, + fd_rsb_ctrl_r, fd_rsb_data_s, + fd_rsb_flushing_done_s, + ); + + let (fd_ctrl_s, fd_ctrl_r) = chan("fd_ctrl"); + let (fd_finish_s, fd_finish_r) = chan("fd_finish"); + + spawn HuffmanFseDecoder< + FSE_RAM_DATA_W, FSE_RAM_ADDR_W, FSE_RAM_NUM_PARTITIONS, + WEIGHTS_RAM_DATA_W, WEIGHTS_RAM_ADDR_W, WEIGHTS_RAM_NUM_PARTITIONS, + AXI_DATA_W, + >( + fd_ctrl_r, fd_finish_s, + fd_rsb_ctrl_s, fd_rsb_data_r, + fse_rd_req_s, fse_rd_resp_r, + weights_ram_wr_req_s, weights_ram_wr_resp_r, + ); ( req_r, resp_s, - mem_rd_req_s, mem_rd_resp_r, - weights_ram_wr_req_s, weights_ram_wr_resp_r + fld_rsb_start_req_s, fld_rsb_stop_flush_req_s, fld_rsb_flushing_done_r, + fd_rsb_start_req_s, fd_rsb_stop_flush_req_s, fd_rsb_flushing_done_r, + fld_req_s, fld_resp_r, + fd_ctrl_s, fd_finish_r, ) } next (state: State) { let tok = join(); - let (tok, req) = recv_if(tok, req_r, false, zero!()); + // Receive decoding request + let (tok, req) = recv(tok, req_r); + trace_fmt!("[FSE] Received decoding request {:#x}", req); - // Fetch Data - let tok = send_if(tok, mem_rd_req_s, false, zero!()); - let (tok, mem_rd_resp) = recv_if(tok, mem_rd_resp_r, false, zero!()); + // Decode lookup + let fld_rsb_start_req = RefillingShiftBufferStart { + start_addr: req.addr + uN[AXI_ADDR_W]:1, // skip header byte + }; + let tok = send(tok, fld_rsb_start_req_s, fld_rsb_start_req); + trace_fmt!("[FSE] Sent refilling shift buffer start request {:#x}", fld_rsb_start_req); - // Send to RAM - let tok = send_if(tok, weights_ram_wr_req_s, false, zero!()); - let (tok, _) = recv_if(tok, weights_ram_wr_resp_r, false, zero!()); + let fld_req = FseLookupDecoderReq { + }; + let tok = send(tok, fld_req_s, fld_req); + trace_fmt!("[FSE] Sent FSE lookup decoding request {:#x}", fld_req); + + let (tok, fld_resp) = recv(tok, fld_resp_r); + trace_fmt!("[FSE] Received FSE lookup decoding response {:#x}", fld_resp); + let tok = send(tok, fld_rsb_stop_flush_req_s, ()); + trace_fmt!("[FSE] Sent refilling shift buffer stop flush request"); + + let (tok, _) = recv(tok, fld_rsb_flushing_done_r); + trace_fmt!("[FSE] Received refilling shift buffer flushing done"); + + // Decode weights + let fd_rsb_start_req = RefillingShiftBufferStart { + start_addr: req.addr + uN[AXI_ADDR_W]:1 + req.length as uN[AXI_ADDR_W] + }; + let tok = send(tok, fd_rsb_start_req_s, fd_rsb_start_req); + trace_fmt!("[FSE] Sent refilling shift buffer start request {:#x}", fd_rsb_start_req); + + let fd_ctrl = HuffmanFseDecoderCtrl { + length: req.length - u8:2, // FIXME: replace hard-coded value with FSE header size + acc_log: fld_resp.accuracy_log, + }; + let tok = send(tok, fd_ctrl_s, fd_ctrl); + trace_fmt!("[FSE] Sent FSE decoding request {:#x}", fd_ctrl); + + let (tok, fd_finish) = recv(tok, fd_finish_r); + trace_fmt!("[FSE] Received FSE decoding finish {:#x}", fd_finish); + + let tok = send(tok, fd_rsb_stop_flush_req_s, ()); + trace_fmt!("[FSE] Sent refilling shift buffer stop flush request"); + + let (tok, _) = recv(tok, fd_rsb_flushing_done_r); + trace_fmt!("[FSE] Received refilling shift buffer flushing done"); + + // Send decoding response let tok = send(tok, resp_s, zero!()); zero!() @@ -435,9 +1127,12 @@ pub struct HuffmanWeightsDecoderState { } pub proc HuffmanWeightsDecoder< - AXI_ADDR_W: u32, AXI_DATA_W: u32, - WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, - WEIGHTS_RAM_NUM_PARTITIONS: u32 + AXI_ADDR_W: u32, AXI_DATA_W: u32, AXI_ID_W: u32, + WEIGHTS_RAM_ADDR_W: u32, WEIGHTS_RAM_DATA_W: u32, WEIGHTS_RAM_NUM_PARTITIONS: u32, + DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, + TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, + TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, + FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, > { type Req = HuffmanWeightsDecoderReq; type Resp = HuffmanWeightsDecoderResp; @@ -457,6 +1152,30 @@ pub proc HuffmanWeightsDecoder< type FseWeightsReq = HuffmanFseWeightsDecoderReq; type FseWeightsResp = HuffmanFseWeightsDecoderResp; + // FSE RAMs + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + // Control req_r: chan in; resp_s: chan out; @@ -502,12 +1221,35 @@ pub proc HuffmanWeightsDecoder< raw_weights_mem_rd_resp_r: chan in, // MemReader interface for Fse Huffman Tree Description Decoder - fse_weights_mem_rd_req_s: chan out, - fse_weights_mem_rd_resp_r: chan in, + fse_lookup_weights_mem_rd_req_s: chan out, + fse_lookup_weights_mem_rd_resp_r: chan in, + fse_decoder_weights_mem_rd_req_s: chan out, + fse_decoder_weights_mem_rd_resp_r: chan in, // Muxed internal RAM Write interface (goes to Huffman Weights Memory) weights_ram_wr_req_s: chan out, weights_ram_wr_resp_r: chan in, + + // FSE RAMs + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + + fse_rd_req_s: chan out, + fse_rd_resp_r: chan in, + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, ) { // Decoded Weights select for RamMux let (decoded_weights_sel_s, decoded_weights_sel_r) = chan("decoded_weights_sel"); @@ -525,8 +1267,13 @@ pub proc HuffmanWeightsDecoder< let (raw_weights_ram_wr_resp_s, raw_weights_ram_wr_resp_r) = chan("raw_weights_ram_wr_resp"); // Internal RAM Write interface with decoded Fse Huffman Tree Description - let (fse_weights_ram_wr_req_s, fse_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); - let (fse_weights_ram_wr_resp_s, fse_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp"); + let (fse_weights_ram_wr_req_s, fse_weights_ram_wr_req_r) = chan("raw_weights_ram_wr_req"); + let (fse_weights_ram_wr_resp_s, fse_weights_ram_wr_resp_r) = chan("raw_weights_ram_wr_resp"); + + let (fse_lookup_weights_ram_wr_req_s, fse_lookup_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); + let (fse_lookup_weights_ram_wr_resp_s, fse_lookup_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp"); + let (fse_decoder_weights_ram_wr_req_s, fse_decoder_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); + let (fse_decoder_weights_ram_wr_resp_s, fse_decoder_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp"); let (raw_weights_ram_rd_req_s, raw_weights_ram_rd_req_r) = chan("raw_weights_ram_rd_req"); let (raw_weights_ram_rd_resp_s, raw_weights_ram_rd_resp_r) = chan("raw_weights_ram_rd_resp"); @@ -546,13 +1293,21 @@ pub proc HuffmanWeightsDecoder< ); spawn HuffmanFseWeightsDecoder< - AXI_ADDR_W, AXI_DATA_W, - WEIGHTS_RAM_ADDR_W, WEIGHTS_RAM_DATA_W, - WEIGHTS_RAM_NUM_PARTITIONS + AXI_ADDR_W, AXI_DATA_W, AXI_ID_W, + WEIGHTS_RAM_ADDR_W, WEIGHTS_RAM_DATA_W, WEIGHTS_RAM_NUM_PARTITIONS, + DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, + TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, + TMP2_RAM_ADDR_W, TMP2_RAM_DATA_W, TMP2_RAM_NUM_PARTITIONS, + FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, >( fse_weights_req_r, fse_weights_resp_s, - fse_weights_mem_rd_req_s, fse_weights_mem_rd_resp_r, - fse_weights_ram_wr_req_s, fse_weights_ram_wr_resp_r + fse_lookup_weights_mem_rd_req_s, fse_lookup_weights_mem_rd_resp_r, + fse_decoder_weights_mem_rd_req_s, fse_decoder_weights_mem_rd_resp_r, + fse_weights_ram_wr_req_s, fse_weights_ram_wr_resp_r, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, ); spawn ram_mux::RamMux( @@ -611,7 +1366,10 @@ pub proc HuffmanWeightsDecoder< if weights_type == WeightsType::FSE { trace_fmt!("Decoding FSE Huffman weights"); } else {}; - let fse_weights_req = zero!(); + let fse_weights_req = FseWeightsReq { + addr: req.addr, + length: header_byte, + }; let tok = send_if(tok, fse_weights_req_s, weights_type == WeightsType::FSE, fse_weights_req); let (tok, fse_weights_resp) = recv_if(tok, fse_weights_resp_r, weights_type == WeightsType::FSE, zero!()); @@ -691,6 +1449,30 @@ const INST_WEIGHTS_RAM_SIMULTANEOUS_RW_BEHAVIOR = ram::SimultaneousReadWriteBeha const INST_WEIGHTS_RAM_INITIALIZED = true; const INST_WEIGHTS_RAM_ASSERT_VALID_READ = true; +const INST_DPD_RAM_DATA_W = u32:16; +const INST_DPD_RAM_SIZE = u32:256; +const INST_DPD_RAM_ADDR_W = std::clog2(INST_DPD_RAM_SIZE); +const INST_DPD_RAM_WORD_PARTITION_SIZE = INST_DPD_RAM_DATA_W; +const INST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions(INST_DPD_RAM_WORD_PARTITION_SIZE, INST_DPD_RAM_DATA_W); + +const INST_FSE_RAM_DATA_W = u32:32; +const INST_FSE_RAM_SIZE = u32:256; +const INST_FSE_RAM_ADDR_W = std::clog2(INST_FSE_RAM_SIZE); +const INST_FSE_RAM_WORD_PARTITION_SIZE = INST_FSE_RAM_DATA_W / u32:3; +const INST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions(INST_FSE_RAM_WORD_PARTITION_SIZE, INST_FSE_RAM_DATA_W); + +const INST_TMP_RAM_DATA_W = u32:16; +const INST_TMP_RAM_SIZE = u32:256; +const INST_TMP_RAM_ADDR_W = std::clog2(INST_TMP_RAM_SIZE); +const INST_TMP_RAM_WORD_PARTITION_SIZE = INST_TMP_RAM_DATA_W; +const INST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions(INST_TMP_RAM_WORD_PARTITION_SIZE, INST_TMP_RAM_DATA_W); + +const INST_TMP2_RAM_DATA_W = u32:8; +const INST_TMP2_RAM_SIZE = u32:512; +const INST_TMP2_RAM_ADDR_W = std::clog2(INST_TMP2_RAM_SIZE); +const INST_TMP2_RAM_WORD_PARTITION_SIZE = INST_TMP2_RAM_DATA_W; +const INST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(INST_TMP2_RAM_WORD_PARTITION_SIZE, INST_TMP2_RAM_DATA_W); + proc HuffmanWeightsDecoderInst { // Memory Reader + Input @@ -718,6 +1500,31 @@ proc HuffmanWeightsDecoderInst { type Status = HuffmanWeightsDecoderStatus; type State = HuffmanWeightsDecoderState; + // FSE RAMs + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + + config ( req_r: chan in, resp_s: chan out, @@ -725,21 +1532,47 @@ proc HuffmanWeightsDecoderInst { header_mem_rd_resp_r: chan in, raw_weights_mem_rd_req_s: chan out, raw_weights_mem_rd_resp_r: chan in, - fse_weights_mem_rd_req_s: chan out, - fse_weights_mem_rd_resp_r: chan in, + fse_lookup_weights_mem_rd_req_s: chan out, + fse_lookup_weights_mem_rd_resp_r: chan in, + fse_decoder_weights_mem_rd_req_s: chan out, + fse_decoder_weights_mem_rd_resp_r: chan in, weights_ram_wr_req_s: chan out, weights_ram_wr_resp_r: chan in, + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + fse_rd_req_s: chan out, + fse_rd_resp_r: chan in, + fse_wr_req_s: chan out, + fse_wr_resp_r: chan in, ) { spawn HuffmanWeightsDecoder< - INST_AXI_ADDR_W, INST_AXI_DATA_W, - INST_WEIGHTS_RAM_ADDR_W, INST_WEIGHTS_RAM_DATA_W, - INST_WEIGHTS_RAM_NUM_PARTITIONS + INST_AXI_ADDR_W, INST_AXI_DATA_W, INST_AXI_ID_W, + INST_WEIGHTS_RAM_ADDR_W, INST_WEIGHTS_RAM_DATA_W, INST_WEIGHTS_RAM_NUM_PARTITIONS, + INST_DPD_RAM_ADDR_W, INST_DPD_RAM_DATA_W, INST_DPD_RAM_NUM_PARTITIONS, + INST_TMP_RAM_ADDR_W, INST_TMP_RAM_DATA_W, INST_TMP_RAM_NUM_PARTITIONS, + INST_TMP2_RAM_ADDR_W, INST_TMP2_RAM_DATA_W, INST_TMP2_RAM_NUM_PARTITIONS, + INST_FSE_RAM_ADDR_W, INST_FSE_RAM_DATA_W, INST_FSE_RAM_NUM_PARTITIONS, > ( req_r, resp_s, header_mem_rd_req_s, header_mem_rd_resp_r, raw_weights_mem_rd_req_s, raw_weights_mem_rd_resp_r, - fse_weights_mem_rd_req_s, fse_weights_mem_rd_resp_r, + fse_lookup_weights_mem_rd_req_s, fse_lookup_weights_mem_rd_resp_r, + fse_decoder_weights_mem_rd_req_s, fse_decoder_weights_mem_rd_resp_r, weights_ram_wr_req_s, weights_ram_wr_resp_r, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, ); } @@ -748,6 +1581,7 @@ proc HuffmanWeightsDecoderInst { next (state: ()) { } } +const TEST_RAM_N = u32:4; const TEST_AXI_ADDR_W = u32:32; const TEST_AXI_DATA_W = u32:64; @@ -772,10 +1606,36 @@ const TEST_WEIGHTS_RAM_SIMULTANEOUS_RW_BEHAVIOR = ram::SimultaneousReadWriteBeha const TEST_WEIGHTS_RAM_INITIALIZED = true; const TEST_WEIGHTS_RAM_ASSERT_VALID_READ = true; -const TEST_INPUT_ADDR = uN[TEST_AXI_ADDR_W]:0x40; +const TEST_DPD_RAM_DATA_W = u32:16; +const TEST_DPD_RAM_SIZE = u32:256; +const TEST_DPD_RAM_ADDR_W = std::clog2(TEST_DPD_RAM_SIZE); +const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_W; +const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); + +const TEST_FSE_RAM_DATA_W = u32:32; +const TEST_FSE_RAM_SIZE = u32:256; +const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); +const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W / u32:3; +const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); +const TEST_FSE_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; + +const TEST_TMP_RAM_DATA_W = u32:16; +const TEST_TMP_RAM_SIZE = u32:256; +const TEST_TMP_RAM_ADDR_W = std::clog2(TEST_TMP_RAM_SIZE); +const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; +const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); + +const TEST_TMP2_RAM_DATA_W = u32:8; +const TEST_TMP2_RAM_SIZE = u32:512; +const TEST_TMP2_RAM_ADDR_W = std::clog2(TEST_TMP2_RAM_SIZE); +const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_W; +const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_W); + +// RAW weights +const TEST_RAW_INPUT_ADDR = uN[TEST_AXI_ADDR_W]:0x40; // Weights sum is 1010, so the last one will be 14 -const TEST_DATA = u8[65]:[ +const TEST_RAW_DATA = u8[65]:[ // len x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF u8:248, u8:0xB__6, u8:0x8__5, u8:0x6__A, u8:0x9__C, u8:0x0__C, u8:0xA__9, u8:0x0__0, u8:0xD__0, // 0x0x u8:0x6__E, u8:0x3__9, u8:0x8__4, u8:0x7__C, u8:0xC__2, u8:0x4__2, u8:0xB__A, u8:0x4__E, // 0x1x @@ -787,7 +1647,263 @@ const TEST_DATA = u8[65]:[ u8:0x3__3, u8:0xA__8, u8:0xE__E, u8:0x4__B, u8:0x0__0, u8:0x0__0, u8:0x0__0, u8:0x0__0, // 0x7x ]; -const TEST_DATA_LAST_WEIGHT = u8:0xA; +const TEST_RAW_DATA_LAST_WEIGHT = u8:0xA; + +// FSE weights +const TEST_FSE_INPUT_ADDR = uN[TEST_AXI_ADDR_W]:0x200; + +// Testcase format - tuple of: +// - array of: header (first byte) + FSE bitstream +// - array of: expected weights RAM contents +const TESTCASES_FSE: (u8[32], u8[128])[7] = [ + ( + u8[32]:[ + u8:10, + u8:0xC0, u8:0x25, u8:0x1D, u8:0x49, u8:0x6E, u8:0xC2, u8:0xFF, u8:0xFF, + u8:0xEE, u8:0x06, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x01, u8:0x12, u8:0x34, u8:0x56, u8:0, ... + ], + ), + ( + u8[32]:[ + u8:15, + u8:0xC0, u8:0x25, u8:0x1D, u8:0x9B, u8:0x1E, u8:0xAD, u8:0xFE, u8:0xFF, + u8:0x7F, u8:0x67, u8:0xFE, u8:0xD3, u8:0xFF, u8:0xCE, u8:0x05, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x10, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x30, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x50, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x01, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x02, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x04, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x06, u8:0, ... + ], + ), + ( + u8[32]:[ + u8:23, + u8:0x90, u8:0x25, u8:0x49, u8:0x3A, u8:0xEB, u8:0x3B, u8:0xBD, u8:0x7E, + u8:0xD6, u8:0x5D, u8:0x3C, u8:0xB3, u8:0x66, u8:0x77, u8:0xA8, u8:0xBB, + u8:0x25, u8:0x76, u8:0xBA, u8:0xFF, u8:0x20, u8:0xA8, u8:0x01, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x10, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x02, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x30, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x04, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x50, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x06, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x70, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x08, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x01, u8:0x00, + u8:0x00, u8:0x90, u8:0, ... + ], + ), + ( + u8[32]:[ + u8:8, + u8:0xF0, u8:0x39, u8:0xFF, u8:0x23, u8:0x45, u8:0x55, u8:0xCF, u8:0x99, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x20, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x01, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x10, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x03, u8:0, ... + ], + ), + ( + u8[32]:[ + u8:24, + u8:0xB0, u8:0xA5, u8:0x92, u8:0x0E, u8:0x14, u8:0x3B, u8:0x7B, u8:0x58, + u8:0xED, u8:0xB0, u8:0x1D, u8:0x9C, u8:0x43, u8:0x82, u8:0xC5, u8:0x8E, + u8:0xD3, u8:0x38, u8:0x36, u8:0x87, u8:0x73, u8:0x08, u8:0x58, u8:0x02, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x20, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x10, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x10, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x07, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x10, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x05, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x10, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x02, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x01, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x01, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x80, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x01, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x60, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x01, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x30, u8:0, ... + ], + ), + ( + u8[32]:[ + u8:9, + u8:0xE0, u8:0xE9, u8:0x40, u8:0x0D, u8:0x80, u8:0x0A, u8:0x10, u8:0x59, + u8:0x04, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x03, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x20, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x01, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x10, u8:0, ... + ], + ), + ( + u8[32]:[ + u8:9, + u8:0xF0, u8:0x19, u8:0x03, u8:0x23, u8:0x7D, u8:0x9F, u8:0xD7, u8:0xB5, + u8:0x06, u8:0, ... + ], + u8[128]:[ + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x10, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x30, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x01, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x02, u8:0, ... + ], + ), +]; #[test_proc] proc HuffmanWeightsDecoder_test { @@ -817,13 +1933,37 @@ proc HuffmanWeightsDecoder_test { type Status = HuffmanWeightsDecoderStatus; type State = HuffmanWeightsDecoderState; + // FSE RAMs + type DpdRamRdReq = ram::ReadReq; + type DpdRamRdResp = ram::ReadResp; + type DpdRamWrReq = ram::WriteReq; + type DpdRamWrResp = ram::WriteResp; + + type TmpRamRdReq = ram::ReadReq; + type TmpRamRdResp = ram::ReadResp; + type TmpRamWrReq = ram::WriteReq; + type TmpRamWrResp = ram::WriteResp; + + type Tmp2RamRdReq = ram::ReadReq; + type Tmp2RamRdResp = ram::ReadResp; + type Tmp2RamWrReq = ram::WriteReq; + type Tmp2RamWrResp = ram::WriteResp; + + type FseRamRdReq = ram::ReadReq; + type FseRamRdResp = ram::ReadResp; + type FseRamWrReq = ram::WriteReq; + type FseRamWrResp = ram::WriteResp; + + type MemAxiAr = axi::AxiAr; + type MemAxiR = axi::AxiR; + terminator: chan out; req_s: chan out; resp_r: chan in; - input_ram_wr_req_s: chan[3] out; - input_ram_wr_resp_r: chan[3] in; + input_ram_wr_req_s: chan[TEST_RAM_N] out; + input_ram_wr_resp_r: chan[TEST_RAM_N] in; weights_ram_rd_req_s: chan out; weights_ram_rd_resp_r: chan in; @@ -832,12 +1972,12 @@ proc HuffmanWeightsDecoder_test { // Input Memory - let (input_ram_rd_req_s, input_ram_rd_req_r) = chan[3]("input_ram_rd_req"); - let (input_ram_rd_resp_s, input_ram_rd_resp_r) = chan[3]("input_ram_rd_resp"); - let (input_ram_wr_req_s, input_ram_wr_req_r) = chan[3]("input_ram_wr_req"); - let (input_ram_wr_resp_s, input_ram_wr_resp_r) = chan[3]("input_ram_wr_resp"); + let (input_ram_rd_req_s, input_ram_rd_req_r) = chan[TEST_RAM_N]("input_ram_rd_req"); + let (input_ram_rd_resp_s, input_ram_rd_resp_r) = chan[TEST_RAM_N]("input_ram_rd_resp"); + let (input_ram_wr_req_s, input_ram_wr_req_r) = chan[TEST_RAM_N]("input_ram_wr_req"); + let (input_ram_wr_resp_s, input_ram_wr_resp_r) = chan[TEST_RAM_N]("input_ram_wr_resp"); - unroll_for! (i, _) in range(u32:0, u32:3) { + unroll_for! (i, _) in range(u32:0, TEST_RAM_N) { spawn ram::RamModel< TEST_RAM_DATA_W, TEST_RAM_SIZE, TEST_RAM_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_RW_BEHAVIOR, TEST_RAM_INITIALIZED, @@ -850,10 +1990,10 @@ proc HuffmanWeightsDecoder_test { // Input Memory Axi Reader - let (axi_ar_s, axi_ar_r) = chan[3]("axi_ar"); - let (axi_r_s, axi_r_r) = chan[3]("axi_r"); + let (axi_ar_s, axi_ar_r) = chan[TEST_RAM_N]("axi_ar"); + let (axi_r_s, axi_r_r) = chan[TEST_RAM_N]("axi_r"); - unroll_for! (i, _) in range(u32:0, u32:3) { + unroll_for! (i, _) in range(u32:0, TEST_RAM_N) { spawn axi_ram::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, @@ -866,10 +2006,10 @@ proc HuffmanWeightsDecoder_test { // Input Memory Reader - let (mem_rd_req_s, mem_rd_req_r) = chan[3]("mem_rd_req"); - let (mem_rd_resp_s, mem_rd_resp_r) = chan[3]("mem_rd_resp"); + let (mem_rd_req_s, mem_rd_req_r) = chan[TEST_RAM_N]("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan[TEST_RAM_N]("mem_rd_resp"); - unroll_for! (i, _) in range(u32:0, u32:3) { + unroll_for! (i, _) in range(u32:0, TEST_RAM_N) { spawn mem_reader::MemReader< TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, >( @@ -899,16 +2039,69 @@ proc HuffmanWeightsDecoder_test { let (req_s, req_r) = chan("req"); let (resp_s, resp_r) = chan("resp"); + // FSE RAMs + let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + + spawn ram::RamModel< + TEST_DPD_RAM_DATA_W, + TEST_DPD_RAM_SIZE, + TEST_DPD_RAM_WORD_PARTITION_SIZE + >(dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s); + + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + + spawn ram::RamModel< + TEST_TMP_RAM_DATA_W, + TEST_TMP_RAM_SIZE, + TEST_TMP_RAM_WORD_PARTITION_SIZE + >(tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s); + + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + + spawn ram::RamModel< + TEST_TMP2_RAM_DATA_W, + TEST_TMP2_RAM_SIZE, + TEST_TMP2_RAM_WORD_PARTITION_SIZE + >(tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s); + + let (fse_rd_req_s, fse_rd_req_r) = chan("fse_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan("fse_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan("fse_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan("fse_wr_resp"); + + spawn ram::RamModel< + TEST_FSE_RAM_DATA_W, + TEST_FSE_RAM_SIZE, + TEST_FSE_RAM_WORD_PARTITION_SIZE + >(fse_rd_req_r, fse_rd_resp_s, fse_wr_req_r, fse_wr_resp_s); + spawn HuffmanWeightsDecoder< - TEST_AXI_ADDR_W, TEST_AXI_DATA_W, - TEST_WEIGHTS_RAM_ADDR_W, TEST_WEIGHTS_RAM_DATA_W, - TEST_WEIGHTS_RAM_NUM_PARTITIONS + TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_ID_W, + TEST_WEIGHTS_RAM_ADDR_W, TEST_WEIGHTS_RAM_DATA_W, TEST_WEIGHTS_RAM_NUM_PARTITIONS, + TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, + TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, + TEST_TMP2_RAM_ADDR_W, TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, > ( req_r, resp_s, mem_rd_req_s[0], mem_rd_resp_r[0], mem_rd_req_s[1], mem_rd_resp_r[1], mem_rd_req_s[2], mem_rd_resp_r[2], + mem_rd_req_s[3], mem_rd_resp_r[3], weights_ram_wr_req_s, weights_ram_wr_resp_r, + dpd_rd_req_s, dpd_rd_resp_r, dpd_wr_req_s, dpd_wr_resp_r, + tmp_rd_req_s, tmp_rd_resp_r, tmp_wr_req_s, tmp_wr_resp_r, + tmp2_rd_req_s, tmp2_rd_resp_r, tmp2_wr_req_s, tmp2_wr_resp_r, + fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, ); ( @@ -926,29 +2119,30 @@ proc HuffmanWeightsDecoder_test { let tok = join(); + // RAW weights + // Fill input RAM - for (i, tok) in range(u32:0, (array_size(TEST_DATA) + TEST_DATA_PER_RAM_WRITE - u32:1) / TEST_DATA_PER_RAM_WRITE) { + for (i, tok) in range(u32:0, (array_size(TEST_RAW_DATA) + TEST_DATA_PER_RAM_WRITE - u32:1) / TEST_DATA_PER_RAM_WRITE) { let ram_data = for (j, ram_data) in range(u32:0, TEST_DATA_PER_RAM_WRITE) { let data_idx = i * TEST_DATA_PER_RAM_WRITE + j; - if (data_idx < array_size(TEST_DATA)) { - ram_data | ((TEST_DATA[data_idx] as uN[TEST_RAM_DATA_W]) << (u32:8 * j)) + if (data_idx < array_size(TEST_RAW_DATA)) { + ram_data | ((TEST_RAW_DATA[data_idx] as uN[TEST_RAM_DATA_W]) << (u32:8 * j)) } else { ram_data } }(uN[TEST_RAM_DATA_W]:0); let input_ram_wr_req = InputBufferRamWrReq { - addr: (TEST_INPUT_ADDR / u32:8) + i as uN[TEST_RAM_ADDR_W], + addr: (TEST_RAW_INPUT_ADDR / u32:8) + i as uN[TEST_RAM_ADDR_W], data: ram_data, mask: !uN[TEST_RAM_NUM_PARTITIONS]:0, }; - let tok = send(tok, input_ram_wr_req_s[0], input_ram_wr_req); - let (tok, _) = recv(tok, input_ram_wr_resp_r[0]); - let tok = send(tok, input_ram_wr_req_s[1], input_ram_wr_req); - let (tok, _) = recv(tok, input_ram_wr_resp_r[1]); - let tok = send(tok, input_ram_wr_req_s[2], input_ram_wr_req); - let (tok, _) = recv(tok, input_ram_wr_resp_r[2]); + let tok = unroll_for! (i, tok) in range(u32:0, TEST_RAM_N) { + let tok = send(tok, input_ram_wr_req_s[i], input_ram_wr_req); + let (tok, _) = recv(tok, input_ram_wr_resp_r[i]); + tok + }(tok); trace_fmt!("[TEST] Sent RAM write request to input RAMs {:#x}", input_ram_wr_req); @@ -957,7 +2151,7 @@ proc HuffmanWeightsDecoder_test { // Send decoding request let req = Req { - addr: TEST_INPUT_ADDR, + addr: TEST_RAW_INPUT_ADDR, }; let tok = send(tok, req_s, req); trace_fmt!("[TEST] Sent request {:#x}", req); @@ -966,15 +2160,15 @@ proc HuffmanWeightsDecoder_test { let (tok, resp) = recv(tok, resp_r); trace_fmt!("[TEST] Received respose {:#x}", resp); assert_eq(HuffmanWeightsDecoderStatus::OKAY, resp.status); - assert_eq((((TEST_DATA[0] - u8:127 + u8:1) >> u32:1) + u8:1) as uN[TEST_AXI_ADDR_W], resp.tree_description_size); + assert_eq((((TEST_RAW_DATA[0] - u8:127) >> u32:1) + u8:2) as uN[TEST_AXI_ADDR_W], resp.tree_description_size); // Insert last weight in test data - let last_weight_idx = ((TEST_DATA[0] as u32 - u32:127) / u32:2) + u32:1; + let last_weight_idx = ((TEST_RAW_DATA[0] as u32 - u32:127) / u32:2) + u32:1; let last_weight_entry = ( - TEST_DATA[last_weight_idx] | - (TEST_DATA_LAST_WEIGHT << (u32:4 * (u32:1 - ((TEST_DATA[0] - u8:127) as u1 as u32)))) + TEST_RAW_DATA[last_weight_idx] | + (TEST_RAW_DATA_LAST_WEIGHT << (u32:4 * (u32:1 - ((TEST_RAW_DATA[0] - u8:127) as u1 as u32)))) ); - let test_data = update(TEST_DATA, last_weight_idx, last_weight_entry); + let test_data = update(TEST_RAW_DATA, last_weight_idx, last_weight_entry); // Check output RAM let tok = for (i, tok) in range(u32:0, u32:32) { @@ -995,13 +2189,82 @@ proc HuffmanWeightsDecoder_test { }; let tok = send(tok, weights_ram_rd_req_s, weights_ram_rd_req); let (tok, weights_ram_rd_resp) = recv(tok, weights_ram_rd_resp_r); - trace_fmt!("[TEST] Weights RAM content - addr: {:#x} data: {:#x}", i, weights_ram_rd_resp.data); + trace_fmt!("[TEST] Weights RAM content - addr: {:#x} data: expected {:#x}, got {:#x}", i, expected_value, weights_ram_rd_resp.data); assert_eq(expected_value, weights_ram_rd_resp.data); tok }(tok); + + // FSE-encoded weights + unroll_for! (i, tok) in range(u32:0, array_size(TESTCASES_FSE)) { + let (TEST_FSE_DATA, TEST_FSE_WEIGHTS) = TESTCASES_FSE[i]; + // Fill input RAM + for (i, tok) in range(u32:0, (array_size(TEST_FSE_DATA) + TEST_DATA_PER_RAM_WRITE - u32:1) / TEST_DATA_PER_RAM_WRITE) { + let ram_data = for (j, ram_data) in range(u32:0, TEST_DATA_PER_RAM_WRITE) { + let data_idx = i * TEST_DATA_PER_RAM_WRITE + j; + if (data_idx < array_size(TEST_FSE_DATA)) { + ram_data | ((TEST_FSE_DATA[data_idx] as uN[TEST_RAM_DATA_W]) << (u32:8 * j)) + } else { + ram_data + } + }(uN[TEST_RAM_DATA_W]:0); + + let input_ram_wr_req = InputBufferRamWrReq { + addr: (TEST_FSE_INPUT_ADDR / u32:8) + i as uN[TEST_RAM_ADDR_W], + data: ram_data, + mask: !uN[TEST_RAM_NUM_PARTITIONS]:0, + }; + + let tok = unroll_for! (i, tok) in range(u32:0, TEST_RAM_N) { + let tok = send(tok, input_ram_wr_req_s[i], input_ram_wr_req); + let (tok, _) = recv(tok, input_ram_wr_resp_r[i]); + tok + }(tok); + + trace_fmt!("[TEST] Sent RAM write request to input RAMs {:#x}", input_ram_wr_req); + + tok + }(tok); + + // Send decoding request + let req = Req { + addr: TEST_FSE_INPUT_ADDR, + }; + let tok = send(tok, req_s, req); + trace_fmt!("[TEST] Sent request {:#x}", req); + + // Receive response + let (tok, resp) = recv(tok, resp_r); + trace_fmt!("[TEST] Received respose {:#x}", resp); + assert_eq(HuffmanWeightsDecoderStatus::OKAY, resp.status); + assert_eq((TEST_FSE_DATA[0] + u8:1) as uN[TEST_AXI_ADDR_W], resp.tree_description_size); + + // Check output RAM + let tok = for (i, tok) in range(u32:0, u32:32) { + let expected_value = ( + TEST_FSE_WEIGHTS[4*i + u32:0] ++ + TEST_FSE_WEIGHTS[4*i + u32:1] ++ + TEST_FSE_WEIGHTS[4*i + u32:2] ++ + TEST_FSE_WEIGHTS[4*i + u32:3] + ); + + let weights_ram_rd_req = WeightsRamRdReq { + addr: i as uN[TEST_WEIGHTS_RAM_ADDR_W], + mask: !uN[TEST_WEIGHTS_RAM_NUM_PARTITIONS]:0, + }; + let tok = send(tok, weights_ram_rd_req_s, weights_ram_rd_req); + let (tok, weights_ram_rd_resp) = recv(tok, weights_ram_rd_resp_r); + trace_fmt!("[TEST] Weights RAM content - addr: {:#x} data: expected {:#x}, got {:#x}", i, expected_value, weights_ram_rd_resp.data); + + assert_eq(expected_value, weights_ram_rd_resp.data); + + tok + }(tok); + tok + }(tok); + send(tok, terminator, true); } } diff --git a/xls/modules/zstd/refilling_shift_buffer.x b/xls/modules/zstd/refilling_shift_buffer.x index 7e6c8bcac2..ced9665439 100644 --- a/xls/modules/zstd/refilling_shift_buffer.x +++ b/xls/modules/zstd/refilling_shift_buffer.x @@ -142,9 +142,9 @@ proc RefillingShiftBufferInternal< let flush_amount_bits = std::min(DATA_W as BufferSize, state.bits_to_flush); // send "flushing done" notification once we complete it send_if(tok, flushing_done_s, flushing && flushing_end, ()); - // if (flushing && flushing_end) { - // trace_fmt!("Sent done on the flushing done channel"); - // } else {}; + if (flushing && flushing_end) { + trace_fmt!("Sent done on the flushing done channel"); + } else {}; // snooping logic for the ShiftBuffer control channel // recv and immediately send out control packets heading for ShiftBuffer, @@ -161,9 +161,9 @@ proc RefillingShiftBufferInternal< }; let do_send_ctrl = (flushing && flush_amount_bits > BufferSize:0) || snoop_ctrl_valid; send_if(tok, snoop_ctrl_s, do_send_ctrl, ctrl_packet); - // if do_send_ctrl { - // trace_fmt!("Sent snooped/injected control packet: {:#x}", ctrl_packet); - // } else {}; + if do_send_ctrl { + trace_fmt!("Sent snooped/injected control packet: {:#x}", ctrl_packet); + } else {}; // snoop data output packet (for keeping track how many bits in ShiftBuffer are occupied) let (_, snoop_data, snoop_data_valid) = recv_non_blocking(tok, snoop_data_out_r, zero!()); @@ -184,14 +184,14 @@ proc RefillingShiftBufferInternal< length: REFILL_SIZE, }; send_if(tok, reader_req_s, do_refill_cycle, mem_req); - // if (do_refill_cycle) { - // trace_fmt!("[{:#x}] Sent request for data to memory: {:#x}", INSTANCE, mem_req); - // } else {}; + if (do_refill_cycle) { + trace_fmt!("[{:#x}] Sent request for data to memory: {:#x}", INSTANCE, mem_req); + } else {}; // receive data from memory let (_, reader_resp, reader_resp_valid) = recv_non_blocking(tok, reader_resp_r, zero!()); - // if reader_resp_valid { - // trace_fmt!("[{:#x}] Received data from memory: {:#x}", INSTANCE, reader_resp); - // } else {}; + if reader_resp_valid { + trace_fmt!("[{:#x}] Received data from memory: {:#x}", INSTANCE, reader_resp); + } else {}; // always send some data regardless of the reader_resp.status to allow for all requests // to complete (possibly with invalid data) since the response channel queue must be empty for // flushing to work correctly @@ -205,9 +205,9 @@ proc RefillingShiftBufferInternal< // ShiftBuffer fast enough, apart from that since part of the condition `do_buffer_refill` // is `buf_will_have_enough_space` it should not block send_if(tok, buffer_data_in_s, do_buffer_refill, data_packet); - // if (do_buffer_refill) { - // trace_fmt!("Sent data to the ShiftBuffer: {:#x}", data_packet); - // } else {}; + if (do_buffer_refill) { + trace_fmt!("Sent data to the ShiftBuffer: {:#x}", data_packet); + } else {}; // length of additional data that will be inserted into the ShiftBuffer *in the future* // once all pending memory requests are served @@ -272,9 +272,9 @@ proc RefillingShiftBufferInternal< length: snoop_data.length, error: axi_error && reads_error_bits, }); - // if forward_snooped_data { - // trace_fmt!("[{:#x}] Forwarded snooped data output packet: {:#x}", INSTANCE, snoop_data); - // } else {}; + if forward_snooped_data { + trace_fmt!("[{:#x}] Forwarded snooped data output packet: {:#x}", INSTANCE, snoop_data); + } else {}; // FSM let next_state = match (state.fsm) { From f50d268a43d81e533462e52c109810fb412906f5 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Fri, 24 Jan 2025 17:07:50 +0100 Subject: [PATCH 62/85] Count the length of the section with probability frequencies Signed-off-by: Robert Winkler --- xls/modules/zstd/fse_proba_freq_dec.x | 40 ++++++++++++++++++++++++-- xls/modules/zstd/huffman_weights_dec.x | 5 ++-- 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/xls/modules/zstd/fse_proba_freq_dec.x b/xls/modules/zstd/fse_proba_freq_dec.x index 5daf857aef..fa75571494 100644 --- a/xls/modules/zstd/fse_proba_freq_dec.x +++ b/xls/modules/zstd/fse_proba_freq_dec.x @@ -49,11 +49,20 @@ pub enum FseProbaFreqDecoderStatus: u1 { ERROR = 1, } +const MAX_CONSUMED_FSE_BITS = FSE_MAX_SYMBOLS * FSE_MAX_ACCURACY_LOG; +const CONSUMED_FSE_BITS_WIDTH = std::clog2(MAX_CONSUMED_FSE_BITS); +pub type ConsumedFseBits = uN[CONSUMED_FSE_BITS_WIDTH]; + +const MAX_CONSUMED_FSE_BYTES = MAX_CONSUMED_FSE_BITS / u32:8; +const CONSUMED_FSE_BYTES_WIDTH = std::clog2(MAX_CONSUMED_FSE_BYTES); +pub type ConsumedFseBytes = uN[CONSUMED_FSE_BYTES_WIDTH]; + pub struct FseProbaFreqDecoderReq {} pub struct FseProbaFreqDecoderResp { status: FseProbaFreqDecoderStatus, accuracy_log: AccuracyLog, symbol_count: SymbolCount, + consumed_bytes: ConsumedFseBytes, } enum Fsm : u4 { @@ -89,7 +98,9 @@ struct State { // using up more probability points than were available data_invalid: bool, // number of bits read from RefillingShiftBuffer modulo 8 - read_bits_mod8: u3 + read_bits_mod8: u3, + // number of bits requested from the ShiftBuffer + read_bits: ConsumedFseBits, } // Adapter for input data, converting the data to a shift buffer input type @@ -254,6 +265,8 @@ pub proc FseProbaFreqDecoder< }; let (tok1_1, out_data) = recv_if(tok0, buff_out_data_r, do_buff_data_recv, zero!()); let data_invalid = state.data_invalid || out_data.error; + + let read_bits = state.read_bits + out_data.length as ConsumedFseBits; let read_bits_mod8 = state.read_bits_mod8 + out_data.length as u3; let (tok1_2, written_symbol_count, written_symb_count_valid) = @@ -292,6 +305,7 @@ pub proc FseProbaFreqDecoder< remaining_proba, written_symbol_count, data_invalid, + read_bits, read_bits_mod8, ..state }, @@ -303,7 +317,12 @@ pub proc FseProbaFreqDecoder< (true, BufferCtrl { length: bit_width as Length }), (false, zero!()), (false, zero!()), - State { fsm: Fsm::RECV_SYMBOL, written_symbol_count, ..state }, + State { + fsm: Fsm::RECV_SYMBOL, + written_symbol_count, + read_bits, + read_bits_mod8, + ..state }, ) }, Fsm::RECV_SYMBOL => { @@ -351,6 +370,7 @@ pub proc FseProbaFreqDecoder< remaining_proba, remainder, data_invalid, + read_bits, read_bits_mod8, ..state }, @@ -372,6 +392,7 @@ pub proc FseProbaFreqDecoder< symbol_count, remaining_proba, remainder, + read_bits, read_bits_mod8, ..state }, @@ -393,6 +414,7 @@ pub proc FseProbaFreqDecoder< symbol_count, remaining_proba, remainder, + read_bits, read_bits_mod8, ..state } @@ -432,6 +454,7 @@ pub proc FseProbaFreqDecoder< remainder: zero!(), written_symbol_count, data_invalid, + read_bits, read_bits_mod8, ..state }, @@ -450,6 +473,7 @@ pub proc FseProbaFreqDecoder< zero_proba_count, next_recv_zero, data_invalid, + read_bits, read_bits_mod8, ..state }, @@ -477,6 +501,8 @@ pub proc FseProbaFreqDecoder< written_symbol_count, zero_proba_count, symbol_count, + read_bits, + read_bits_mod8, ..state }, ) @@ -491,6 +517,8 @@ pub proc FseProbaFreqDecoder< zero_proba_count: SymbolCount:0, written_symbol_count, symbol_count, + read_bits, + read_bits_mod8, ..state }, ) @@ -504,6 +532,8 @@ pub proc FseProbaFreqDecoder< zero_proba_count, symbol_count, written_symbol_count, + read_bits, + read_bits_mod8, ..state }, ) @@ -521,6 +551,8 @@ pub proc FseProbaFreqDecoder< (false, zero!()), State { fsm: Fsm::CONSUME_PADDING, + read_bits, + read_bits_mod8, ..state } ) @@ -543,6 +575,7 @@ pub proc FseProbaFreqDecoder< status: if state.data_invalid { Status::ERROR } else { Status::OK }, accuracy_log: state.accuracy_log, symbol_count: state.symbol_count, + consumed_bytes: checked_cast(read_bits >> 3), }), zero!() ) @@ -710,6 +743,7 @@ proc FseProbaFreqDecoderTest { status: FseProbaFreqDecoderStatus::OK, accuracy_log: AccuracyLog:8, symbol_count: SymbolCount:12, + consumed_bytes: ConsumedFseBytes:6, }); // check that the proc consumed the padding by sending request @@ -762,6 +796,7 @@ proc FseProbaFreqDecoderTest { status: FseProbaFreqDecoderStatus::OK, accuracy_log: AccuracyLog:9, symbol_count: SymbolCount:2, + consumed_bytes: ConsumedFseBytes:2, }); for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { @@ -798,6 +833,7 @@ proc FseProbaFreqDecoderTest { status: FseProbaFreqDecoderStatus::OK, accuracy_log: AccuracyLog:9, symbol_count: SymbolCount:2, + consumed_bytes: ConsumedFseBytes:2, }); for ((i, exp_val), tok): ((u32, RamData), token) in enumerate(EXPECTED_RAM_CONTENTS) { diff --git a/xls/modules/zstd/huffman_weights_dec.x b/xls/modules/zstd/huffman_weights_dec.x index bf71a615dc..6c7b3aed36 100644 --- a/xls/modules/zstd/huffman_weights_dec.x +++ b/xls/modules/zstd/huffman_weights_dec.x @@ -1059,8 +1059,7 @@ proc HuffmanFseWeightsDecoder< let tok = send(tok, fld_rsb_start_req_s, fld_rsb_start_req); trace_fmt!("[FSE] Sent refilling shift buffer start request {:#x}", fld_rsb_start_req); - let fld_req = FseLookupDecoderReq { - }; + let fld_req = FseLookupDecoderReq {}; let tok = send(tok, fld_req_s, fld_req); trace_fmt!("[FSE] Sent FSE lookup decoding request {:#x}", fld_req); @@ -1081,7 +1080,7 @@ proc HuffmanFseWeightsDecoder< trace_fmt!("[FSE] Sent refilling shift buffer start request {:#x}", fd_rsb_start_req); let fd_ctrl = HuffmanFseDecoderCtrl { - length: req.length - u8:2, // FIXME: replace hard-coded value with FSE header size + length: req.length - checked_cast(fld_resp.consumed_bytes), acc_log: fld_resp.accuracy_log, }; let tok = send(tok, fd_ctrl_s, fd_ctrl); From cce77a5b70186a94637c53252aaea1a453a30d29 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Fri, 24 Jan 2025 17:19:50 +0100 Subject: [PATCH 63/85] Adjust the design to the changed HuffmanWeightsDecoder Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 3 +- xls/modules/zstd/comp_block_dec.x | 719 ++++++++++++++-------- xls/modules/zstd/comp_frame_huffman_fse.x | 21 + xls/modules/zstd/comp_lookup_dec.x | 55 +- xls/modules/zstd/fse_lookup_dec.x | 23 +- xls/modules/zstd/huffman_literals_dec.x | 98 ++- xls/modules/zstd/huffman_prescan.x | 15 +- xls/modules/zstd/huffman_weights_dec.x | 403 ++++++------ xls/modules/zstd/literals_decoder.x | 413 ++++++++++++- xls/modules/zstd/zstd_dec.x | 189 ++++-- xls/modules/zstd/zstd_dec_test.x | 199 ++++-- 11 files changed, 1520 insertions(+), 618 deletions(-) create mode 100644 xls/modules/zstd/comp_frame_huffman_fse.x diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 77e7024911..747d0d1deb 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1286,6 +1286,7 @@ xls_dslx_test( "zstd_frame_testcases.x", "comp_frame.x", "comp_frame_huffman.x", + "comp_frame_huffman_fse.x", "comp_frame_fse_comp.x", "comp_frame_fse_repeated.x", ], @@ -3052,7 +3053,7 @@ xls_dslx_library( deps = [ "//xls/modules/zstd:huffman_prescan_dslx", "//xls/modules/zstd:refilling_shift_buffer_dslx", - "//xls/modules/zstd:fse_lookup_dec_dslx", + "//xls/modules/zstd:comp_lookup_dec_dslx", "//xls/modules/zstd:fse_table_creator_dslx", "//xls/modules/zstd:math_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index 276a54cd03..0cf51ff320 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -55,13 +55,18 @@ pub proc CompressBlockDecoder< // AXI parameters AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, - // FSE lookup table RAMs - DPD_RAM_ADDR_W: u32, DPD_RAM_DATA_W: u32, DPD_RAM_NUM_PARTITIONS: u32, - TMP_RAM_ADDR_W: u32, TMP_RAM_DATA_W: u32, TMP_RAM_NUM_PARTITIONS: u32, - TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, - FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + // FSE lookup table RAMs for sequences + SEQ_DPD_RAM_ADDR_W: u32, SEQ_DPD_RAM_DATA_W: u32, SEQ_DPD_RAM_NUM_PARTITIONS: u32, + SEQ_TMP_RAM_ADDR_W: u32, SEQ_TMP_RAM_DATA_W: u32, SEQ_TMP_RAM_NUM_PARTITIONS: u32, + SEQ_TMP2_RAM_ADDR_W: u32, SEQ_TMP2_RAM_DATA_W: u32, SEQ_TMP2_RAM_NUM_PARTITIONS: u32, + SEQ_FSE_RAM_ADDR_W: u32, SEQ_FSE_RAM_DATA_W: u32, SEQ_FSE_RAM_NUM_PARTITIONS: u32, // for literals decoder + HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_DPD_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_TMP_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_FSE_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS: u32, + HISTORY_BUFFER_SIZE_KB: u32 = {common::HISTORY_BUFFER_SIZE_KB}, // FSE proba @@ -72,16 +77,16 @@ pub proc CompressBlockDecoder< AXI_DATA_W_DIV8: u32 = {AXI_DATA_W / u32:8}, // Huffman weights memory parameters - HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_ADDR_WIDTH}, - HUFFMAN_WEIGHTS_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_DATA_WIDTH}, + HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = {huffman_literals_dec::WEIGHTS_ADDR_WIDTH}, + HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = {huffman_literals_dec::WEIGHTS_DATA_WIDTH}, HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::WEIGHTS_NUM_PARTITIONS}, // Huffman prescan memory parameters - HUFFMAN_PRESCAN_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::PRESCAN_ADDR_WIDTH}, - HUFFMAN_PRESCAN_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::PRESCAN_DATA_WIDTH}, + HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = {huffman_literals_dec::PRESCAN_ADDR_WIDTH}, + HUFFMAN_PRESCAN_RAM_DATA_W: u32 = {huffman_literals_dec::PRESCAN_DATA_WIDTH}, HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::PRESCAN_NUM_PARTITIONS}, // Literals buffer memory parameters - LITERALS_BUFFER_RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, - LITERALS_BUFFER_RAM_DATA_WIDTH: u32 = {literals_buffer::RAM_DATA_WIDTH}, + LITERALS_BUFFER_RAM_ADDR_W: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, + LITERALS_BUFFER_RAM_DATA_W: u32 = {literals_buffer::RAM_DATA_WIDTH}, LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = {literals_buffer::RAM_NUM_PARTITIONS}, > { type Req = CompressBlockDecoderReq; @@ -99,25 +104,45 @@ pub proc CompressBlockDecoder< type MemAxiW = axi::AxiW; type MemAxiB = axi::AxiB; - type DpdRamRdReq = ram::ReadReq; - type DpdRamRdResp = ram::ReadResp; - type DpdRamWrReq = ram::WriteReq; - type DpdRamWrResp = ram::WriteResp; - - type TmpRamRdReq = ram::ReadReq; - type TmpRamRdResp = ram::ReadResp; - type TmpRamWrReq = ram::WriteReq; - type TmpRamWrResp = ram::WriteResp; - - type Tmp2RamRdReq = ram::ReadReq; - type Tmp2RamRdResp = ram::ReadResp; - type Tmp2RamWrReq = ram::WriteReq; - type Tmp2RamWrResp = ram::WriteResp; - - type FseRamRdReq = ram::ReadReq; - type FseRamRdResp = ram::ReadResp; - type FseRamWrReq = ram::WriteReq; - type FseRamWrResp = ram::WriteResp; + type SeqDpdRamRdReq = ram::ReadReq; + type SeqDpdRamRdResp = ram::ReadResp; + type SeqDpdRamWrReq = ram::WriteReq; + type SeqDpdRamWrResp = ram::WriteResp; + + type SeqTmpRamRdReq = ram::ReadReq; + type SeqTmpRamRdResp = ram::ReadResp; + type SeqTmpRamWrReq = ram::WriteReq; + type SeqTmpRamWrResp = ram::WriteResp; + + type SeqTmp2RamRdReq = ram::ReadReq; + type SeqTmp2RamRdResp = ram::ReadResp; + type SeqTmp2RamWrReq = ram::WriteReq; + type SeqTmp2RamWrResp = ram::WriteResp; + + type SeqFseRamRdReq = ram::ReadReq; + type SeqFseRamRdResp = ram::ReadResp; + type SeqFseRamWrReq = ram::WriteReq; + type SeqFseRamWrResp = ram::WriteResp; + + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; type LiteralsHeaderDecoderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; type LiteralsBlockType = literals_block_header_dec::LiteralsBlockType; @@ -126,18 +151,19 @@ pub proc CompressBlockDecoder< type LiteralsBufCtrl = common::LiteralsBufferCtrl; type CommandConstructorData = common::CommandConstructorData; - type HuffmanWeightsReadReq = ram::ReadReq; - type HuffmanWeightsReadResp = ram::ReadResp; - type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; - type HuffmanPrescanReadReq = ram::ReadReq; - type HuffmanPrescanReadResp = ram::ReadResp; - type HuffmanPrescanWriteReq = ram::WriteReq; + + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; - type LitBufRamRdReq = ram::ReadReq; - type LitBufRamRdResp = ram::ReadResp; - type LitBufRamWrReq = ram::WriteReq; + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; type LitBufRamWrResp = ram::WriteResp; type AxiAddrW = uN[AXI_ADDR_W]; @@ -176,50 +202,50 @@ pub proc CompressBlockDecoder< fd_axi_r_r: chan in, // RAMs for FSE decoder - dpd_rd_req_s: chan out, - dpd_rd_resp_r: chan in, - dpd_wr_req_s: chan out, - dpd_wr_resp_r: chan in, - - tmp_rd_req_s: chan out, - tmp_rd_resp_r: chan in, - tmp_wr_req_s: chan out, - tmp_wr_resp_r: chan in, - - tmp2_rd_req_s: chan out, - tmp2_rd_resp_r: chan in, - tmp2_wr_req_s: chan out, - tmp2_wr_resp_r: chan in, - - ll_def_fse_rd_req_s: chan out, - ll_def_fse_rd_resp_r: chan in, - ll_def_fse_wr_req_s: chan out, - ll_def_fse_wr_resp_r: chan in, - - ll_fse_rd_req_s: chan out, - ll_fse_rd_resp_r: chan in, - ll_fse_wr_req_s: chan out, - ll_fse_wr_resp_r: chan in, - - ml_def_fse_rd_req_s: chan out, - ml_def_fse_rd_resp_r: chan in, - ml_def_fse_wr_req_s: chan out, - ml_def_fse_wr_resp_r: chan in, - - ml_fse_rd_req_s: chan out, - ml_fse_rd_resp_r: chan in, - ml_fse_wr_req_s: chan out, - ml_fse_wr_resp_r: chan in, - - of_def_fse_rd_req_s: chan out, - of_def_fse_rd_resp_r: chan in, - of_def_fse_wr_req_s: chan out, - of_def_fse_wr_resp_r: chan in, - - of_fse_rd_req_s: chan out, - of_fse_rd_resp_r: chan in, - of_fse_wr_req_s: chan out, - of_fse_wr_resp_r: chan in, + dpd_rd_req_s: chan out, + dpd_rd_resp_r: chan in, + dpd_wr_req_s: chan out, + dpd_wr_resp_r: chan in, + + tmp_rd_req_s: chan out, + tmp_rd_resp_r: chan in, + tmp_wr_req_s: chan out, + tmp_wr_resp_r: chan in, + + tmp2_rd_req_s: chan out, + tmp2_rd_resp_r: chan in, + tmp2_wr_req_s: chan out, + tmp2_wr_resp_r: chan in, + + ll_def_fse_rd_req_s: chan out, + ll_def_fse_rd_resp_r: chan in, + ll_def_fse_wr_req_s: chan out, + ll_def_fse_wr_resp_r: chan in, + + ll_fse_rd_req_s: chan out, + ll_fse_rd_resp_r: chan in, + ll_fse_wr_req_s: chan out, + ll_fse_wr_resp_r: chan in, + + ml_def_fse_rd_req_s: chan out, + ml_def_fse_rd_resp_r: chan in, + ml_def_fse_wr_req_s: chan out, + ml_def_fse_wr_resp_r: chan in, + + ml_fse_rd_req_s: chan out, + ml_fse_rd_resp_r: chan in, + ml_fse_wr_req_s: chan out, + ml_fse_wr_resp_r: chan in, + + of_def_fse_rd_req_s: chan out, + of_def_fse_rd_resp_r: chan in, + of_def_fse_wr_req_s: chan out, + of_def_fse_wr_resp_r: chan in, + + of_fse_rd_req_s: chan out, + of_fse_rd_resp_r: chan in, + of_fse_wr_req_s: chan out, + of_fse_wr_resp_r: chan in, // Literals decoder channels @@ -248,8 +274,12 @@ pub proc CompressBlockDecoder< huffman_weights_raw_axi_r_r: chan in, // AXI Huffman Weights FSE Decoder (manager) - huffman_weights_fse_axi_ar_s: chan out, - huffman_weights_fse_axi_r_r: chan in, + huffman_weights_fse_lookup_dec_axi_ar_s: chan out, + huffman_weights_fse_lookup_dec_axi_r_r: chan in, + + // AXI Huffman Weights FSE Decoder (manager) + huffman_weights_fse_decoder_dec_axi_ar_s: chan out, + huffman_weights_fse_decoder_dec_axi_r_r: chan in, // Literals buffer internal memory rd_req_m0_s: chan out, @@ -297,6 +327,25 @@ pub proc CompressBlockDecoder< huffman_lit_prescan_mem_wr_req_s: chan out, huffman_lit_prescan_mem_wr_resp_r: chan in, + huffman_lit_weights_dpd_rd_req_s: chan out, + huffman_lit_weights_dpd_rd_resp_r: chan in, + huffman_lit_weights_dpd_wr_req_s: chan out, + huffman_lit_weights_dpd_wr_resp_r: chan in, + + huffman_lit_weights_tmp_rd_req_s: chan out, + huffman_lit_weights_tmp_rd_resp_r: chan in, + huffman_lit_weights_tmp_wr_req_s: chan out, + huffman_lit_weights_tmp_wr_resp_r: chan in, + + huffman_lit_weights_tmp2_rd_req_s: chan out, + huffman_lit_weights_tmp2_rd_resp_r: chan in, + huffman_lit_weights_tmp2_wr_req_s: chan out, + huffman_lit_weights_tmp2_wr_resp_r: chan in, + + huffman_lit_weights_fse_rd_req_s: chan out, + huffman_lit_weights_fse_rd_resp_r: chan in, + huffman_lit_weights_fse_wr_req_s: chan out, + huffman_lit_weights_fse_wr_resp_r: chan in, ) { // TODO: for consistency all MemReaders should be in toplevel ZSTD decoder // so we should move them up in the hierarchy from LiteralsDecoder @@ -312,7 +361,13 @@ pub proc CompressBlockDecoder< spawn literals_decoder::LiteralsDecoder< HISTORY_BUFFER_SIZE_KB, - AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W + AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W, + HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W, HUFFMAN_WEIGHTS_DPD_RAM_DATA_W, HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W, HUFFMAN_WEIGHTS_TMP_RAM_DATA_W, HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W, HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W, HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W, HUFFMAN_WEIGHTS_FSE_RAM_DATA_W, HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_RAM_ADDR_W, HUFFMAN_WEIGHTS_RAM_DATA_W, HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS, + HUFFMAN_PRESCAN_RAM_ADDR_W, HUFFMAN_PRESCAN_RAM_DATA_W, HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS, >( lit_header_axi_ar_s, lit_header_axi_r_r, raw_lit_axi_ar_s, raw_lit_axi_r_r, @@ -320,17 +375,30 @@ pub proc CompressBlockDecoder< huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, - huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + huffman_weights_fse_lookup_dec_axi_ar_s, huffman_weights_fse_lookup_dec_axi_r_r, + huffman_weights_fse_decoder_dec_axi_ar_s, huffman_weights_fse_decoder_dec_axi_r_r, lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, lit_buf_ctrl_r, lit_buf_out_s, - rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, - rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, - wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, - wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, + rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, + rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, + rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r, + wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s, + wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, + wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, + wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, ); let (seq_dec_req_s, seq_dec_req_r) = chan("seq_dec_req"); @@ -339,10 +407,10 @@ pub proc CompressBlockDecoder< spawn sequence_dec::SequenceDecoder< AXI_ADDR_W, AXI_DATA_W, AXI_DEST_W, AXI_ID_W, - DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, - TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, - TMP2_RAM_ADDR_W, TMP2_RAM_DATA_W, TMP2_RAM_NUM_PARTITIONS, - FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, + SEQ_DPD_RAM_ADDR_W, SEQ_DPD_RAM_DATA_W, SEQ_DPD_RAM_NUM_PARTITIONS, + SEQ_TMP_RAM_ADDR_W, SEQ_TMP_RAM_DATA_W, SEQ_TMP_RAM_NUM_PARTITIONS, + SEQ_TMP2_RAM_ADDR_W, SEQ_TMP2_RAM_DATA_W, SEQ_TMP2_RAM_NUM_PARTITIONS, + SEQ_FSE_RAM_ADDR_W, SEQ_FSE_RAM_DATA_W, SEQ_FSE_RAM_NUM_PARTITIONS, >( scd_axi_ar_s, scd_axi_r_r, fld_axi_ar_s, fld_axi_r_r, @@ -427,12 +495,12 @@ pub proc CompressBlockDecoder< } } -const TEST_CASE_RAM_DATA_WIDTH = u32:64; +const TEST_CASE_RAM_DATA_W = u32:64; const TEST_CASE_RAM_SIZE = u32:256; -const TEST_CASE_RAM_ADDR_WIDTH = std::clog2(TEST_CASE_RAM_SIZE); -const TEST_CASE_RAM_WORD_PARTITION_SIZE = TEST_CASE_RAM_DATA_WIDTH / u32:8; +const TEST_CASE_RAM_ADDR_W = std::clog2(TEST_CASE_RAM_SIZE); +const TEST_CASE_RAM_WORD_PARTITION_SIZE = TEST_CASE_RAM_DATA_W / u32:8; const TEST_CASE_RAM_NUM_PARTITIONS = ram::num_partitions( - TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_CASE_RAM_DATA_WIDTH); + TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_CASE_RAM_DATA_W); const TEST_CASE_RAM_BASE_ADDR = u32:0; const TEST_AXI_DATA_W = u32:64; @@ -441,54 +509,85 @@ const TEST_AXI_ID_W = u32:4; const TEST_AXI_DEST_W = u32:4; const TEST_AXI_DATA_W_DIV8 = TEST_AXI_DATA_W / u32:8; -const TEST_DPD_RAM_DATA_W = u32:16; -const TEST_DPD_RAM_SIZE = u32:256; -const TEST_DPD_RAM_ADDR_W = std::clog2(TEST_DPD_RAM_SIZE); -const TEST_DPD_RAM_WORD_PARTITION_SIZE = TEST_DPD_RAM_DATA_W; -const TEST_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( - TEST_DPD_RAM_WORD_PARTITION_SIZE, TEST_DPD_RAM_DATA_W); - -const TEST_FSE_RAM_DATA_W = u32:32; -const TEST_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; -const TEST_FSE_RAM_ADDR_W = std::clog2(TEST_FSE_RAM_SIZE); -const TEST_FSE_RAM_WORD_PARTITION_SIZE = TEST_FSE_RAM_DATA_W; -const TEST_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( - TEST_FSE_RAM_WORD_PARTITION_SIZE, TEST_FSE_RAM_DATA_W); - -const TEST_TMP_RAM_DATA_W = u32:16; -const TEST_TMP_RAM_SIZE = u32:256; -const TEST_TMP_RAM_ADDR_W = std::clog2(TEST_TMP_RAM_SIZE); -const TEST_TMP_RAM_WORD_PARTITION_SIZE = TEST_TMP_RAM_DATA_W; -const TEST_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( - TEST_TMP_RAM_WORD_PARTITION_SIZE, TEST_TMP_RAM_DATA_W); - -const TEST_TMP2_RAM_DATA_W = u32:8; -const TEST_TMP2_RAM_SIZE = u32:512; -const TEST_TMP2_RAM_ADDR_W = std::clog2(TEST_TMP2_RAM_SIZE); -const TEST_TMP2_RAM_WORD_PARTITION_SIZE = TEST_TMP2_RAM_DATA_W; -const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_W); +const TEST_SEQ_DPD_RAM_DATA_W = u32:16; +const TEST_SEQ_DPD_RAM_SIZE = u32:256; +const TEST_SEQ_DPD_RAM_ADDR_W = std::clog2(TEST_SEQ_DPD_RAM_SIZE); +const TEST_SEQ_DPD_RAM_WORD_PARTITION_SIZE = TEST_SEQ_DPD_RAM_DATA_W; +const TEST_SEQ_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_SEQ_DPD_RAM_WORD_PARTITION_SIZE, TEST_SEQ_DPD_RAM_DATA_W); + +const TEST_SEQ_FSE_RAM_DATA_W = u32:32; +const TEST_SEQ_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; +const TEST_SEQ_FSE_RAM_ADDR_W = std::clog2(TEST_SEQ_FSE_RAM_SIZE); +const TEST_SEQ_FSE_RAM_WORD_PARTITION_SIZE = TEST_SEQ_FSE_RAM_DATA_W; +const TEST_SEQ_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_SEQ_FSE_RAM_WORD_PARTITION_SIZE, TEST_SEQ_FSE_RAM_DATA_W); + +const TEST_SEQ_TMP_RAM_DATA_W = u32:16; +const TEST_SEQ_TMP_RAM_SIZE = u32:256; +const TEST_SEQ_TMP_RAM_ADDR_W = std::clog2(TEST_SEQ_TMP_RAM_SIZE); +const TEST_SEQ_TMP_RAM_WORD_PARTITION_SIZE = TEST_SEQ_TMP_RAM_DATA_W; +const TEST_SEQ_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_SEQ_TMP_RAM_WORD_PARTITION_SIZE, TEST_SEQ_TMP_RAM_DATA_W); + +const TEST_SEQ_TMP2_RAM_DATA_W = u32:8; +const TEST_SEQ_TMP2_RAM_SIZE = u32:512; +const TEST_SEQ_TMP2_RAM_ADDR_W = std::clog2(TEST_SEQ_TMP2_RAM_SIZE); +const TEST_SEQ_TMP2_RAM_WORD_PARTITION_SIZE = TEST_SEQ_TMP2_RAM_DATA_W; +const TEST_SEQ_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions(TEST_SEQ_TMP2_RAM_WORD_PARTITION_SIZE, TEST_SEQ_TMP2_RAM_DATA_W); const TEST_RAM_SIM_RW_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; const TEST_RAM_INITIALIZED = true; const HISTORY_BUFFER_SIZE_KB = common::HISTORY_BUFFER_SIZE_KB; -const HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; -const HUFFMAN_WEIGHTS_RAM_DATA_WIDTH: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; -const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; -// Huffman prescan memory parameters -const HUFFMAN_PRESCAN_RAM_ADDR_WIDTH: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; -const HUFFMAN_PRESCAN_RAM_DATA_WIDTH: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; -const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; -// Literals buffer memory parameters -const LITERALS_BUFFER_RAM_ADDR_WIDTH: u32 = parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB); -const LITERALS_BUFFER_RAM_SIZE: u32 = parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB); -const LITERALS_BUFFER_RAM_DATA_WIDTH: u32 = literals_buffer::RAM_DATA_WIDTH; -const LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; -const LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = LITERALS_BUFFER_RAM_DATA_WIDTH; - -const AXI_CHAN_N = u32:10; - +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W = u32:16; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W = u32:32; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W / u32:3; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W = u32:16; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W = u32:8; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE = u32:512; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; +const TEST_HUFFMAN_WEIGHTS_RAM_SIZE = huffman_literals_dec::RAM_SIZE; +const TEST_HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; +const TEST_HUFFMAN_WEIGHTS_RAM_WORD_PARTITION_SIZE = huffman_literals_dec::WEIGHTS_PARTITION_WORD_SIZE; +const TEST_HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; + +const TEST_HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; +const TEST_HUFFMAN_PRESCAN_RAM_SIZE = huffman_literals_dec::RAM_SIZE; +const TEST_HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; +const TEST_HUFFMAN_PRESCAN_RAM_WORD_PARTITION_SIZE = huffman_literals_dec::PRESCAN_PARTITION_WORD_SIZE; +const TEST_HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; + +const TEST_LITERALS_BUFFER_RAM_ADDR_W: u32 = parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB); +const TEST_LITERALS_BUFFER_RAM_SIZE: u32 = parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB); +const TEST_LITERALS_BUFFER_RAM_DATA_W: u32 = literals_buffer::RAM_DATA_WIDTH; +const TEST_LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; +const TEST_LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = TEST_LITERALS_BUFFER_RAM_DATA_W; + +const AXI_CHAN_N = u32:11; // testcase format: // - block length (without block header, essentially length of sequences + literals sections), @@ -1031,51 +1130,73 @@ proc CompressBlockDecoderTest { type MemAxiW = axi::AxiW; type MemAxiB = axi::AxiB; - type DpdRamRdReq = ram::ReadReq; - type DpdRamRdResp = ram::ReadResp; - type DpdRamWrReq = ram::WriteReq; - type DpdRamWrResp = ram::WriteResp; + type SeqDpdRamRdReq = ram::ReadReq; + type SeqDpdRamRdResp = ram::ReadResp; + type SeqDpdRamWrReq = ram::WriteReq; + type SeqDpdRamWrResp = ram::WriteResp; - type TmpRamRdReq = ram::ReadReq; - type TmpRamRdResp = ram::ReadResp; - type TmpRamWrReq = ram::WriteReq; - type TmpRamWrResp = ram::WriteResp; + type SeqTmpRamRdReq = ram::ReadReq; + type SeqTmpRamRdResp = ram::ReadResp; + type SeqTmpRamWrReq = ram::WriteReq; + type SeqTmpRamWrResp = ram::WriteResp; - type Tmp2RamRdReq = ram::ReadReq; - type Tmp2RamRdResp = ram::ReadResp; - type Tmp2RamWrReq = ram::WriteReq; - type Tmp2RamWrResp = ram::WriteResp; + type SeqTmp2RamRdReq = ram::ReadReq; + type SeqTmp2RamRdResp = ram::ReadResp; + type SeqTmp2RamWrReq = ram::WriteReq; + type SeqTmp2RamWrResp = ram::WriteResp; - type FseRamRdReq = ram::ReadReq; - type FseRamRdResp = ram::ReadResp; - type FseRamWrReq = ram::WriteReq; - type FseRamWrResp = ram::WriteResp; + type SeqFseRamRdReq = ram::ReadReq; + type SeqFseRamRdResp = ram::ReadResp; + type SeqFseRamWrReq = ram::WriteReq; + type SeqFseRamWrResp = ram::WriteResp; type LiteralsHeaderDecoderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; type LiteralsBlockType = literals_block_header_dec::LiteralsBlockType; type LiteralsDecReq = literals_decoder::LiteralsDecoderCtrlReq; type LiteralsDecResp = literals_decoder::LiteralsDecoderCtrlResp; type LiteralsBufCtrl = common::LiteralsBufferCtrl; + type SequenceExecutorPacket = common::SequenceExecutorPacket; type CommandConstructorData = common::CommandConstructorData; - type HuffmanWeightsReadReq = ram::ReadReq; - type HuffmanWeightsReadResp = ram::ReadResp; - type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; - type HuffmanPrescanReadReq = ram::ReadReq; - type HuffmanPrescanReadResp = ram::ReadResp; - type HuffmanPrescanWriteReq = ram::WriteReq; + + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; - type LitBufRamRdReq = ram::ReadReq; - type LitBufRamRdResp = ram::ReadResp; - type LitBufRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; + + type LitBufRamRdReq = ram::ReadReq; + type LitBufRamRdResp = ram::ReadResp; + type LitBufRamWrReq = ram::WriteReq; type LitBufRamWrResp = ram::WriteResp; - type TestcaseRamRdReq = ram::ReadReq; - type TestcaseRamRdResp = ram::ReadResp; - type TestcaseRamWrReq = ram::WriteReq; + type TestcaseRamRdReq = ram::ReadReq; + type TestcaseRamRdResp = ram::ReadResp; + type TestcaseRamWrReq = ram::WriteReq; type TestcaseRamWrResp = ram::WriteResp; terminator: chan out; @@ -1086,22 +1207,22 @@ proc CompressBlockDecoderTest { axi_ram_wr_resp_r: chan[AXI_CHAN_N] in; ll_sel_test_s: chan out; - ll_def_test_rd_req_s: chan out; - ll_def_test_rd_resp_r: chan in; - ll_def_test_wr_req_s: chan out; - ll_def_test_wr_resp_r: chan in; + ll_def_test_rd_req_s: chan out; + ll_def_test_rd_resp_r: chan in; + ll_def_test_wr_req_s: chan out; + ll_def_test_wr_resp_r: chan in; ml_sel_test_s: chan out; - ml_def_test_rd_req_s: chan out; - ml_def_test_rd_resp_r: chan in; - ml_def_test_wr_req_s: chan out; - ml_def_test_wr_resp_r: chan in; + ml_def_test_rd_req_s: chan out; + ml_def_test_rd_resp_r: chan in; + ml_def_test_wr_req_s: chan out; + ml_def_test_wr_resp_r: chan in; of_sel_test_s: chan out; - of_def_test_rd_req_s: chan out; - of_def_test_rd_resp_r: chan in; - of_def_test_wr_req_s: chan out; - of_def_test_wr_resp_r: chan in; + of_def_test_rd_req_s: chan out; + of_def_test_rd_resp_r: chan in; + of_def_test_wr_req_s: chan out; + of_def_test_wr_resp_r: chan in; init {} config(terminator: chan out) { @@ -1112,16 +1233,84 @@ proc CompressBlockDecoderTest { let (cmd_constr_out_s, cmd_constr_out_r) = chan("cmd_constr_out"); // Huffman weights memory - let (huffman_lit_weights_mem_rd_req_s, _huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); - let (_huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); - let (huffman_lit_weights_mem_wr_req_s, _huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); - let (_huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); // Huffman prescan memory - let (huffman_lit_prescan_mem_rd_req_s, _huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); - let (_huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); - let (huffman_lit_prescan_mem_wr_req_s, _huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); - let (_huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + let (huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); + let (huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); + let (huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); + let (huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + + let (huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_req_r) = chan("huffman_lit_weights_dpd_rd_req"); + let (huffman_lit_weights_dpd_rd_resp_s, huffman_lit_weights_dpd_rd_resp_r) = chan("huffman_lit_weights_dpd_rd_resp_r"); + let (huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_req_r) = chan("huffman_lit_weights_dpd_wr_req"); + let (huffman_lit_weights_dpd_wr_resp_s, huffman_lit_weights_dpd_wr_resp_r) = chan("huffman_lit_weights_dpd_wr_resp"); + + let (huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_req_r) = chan("huffman_lit_weights_tmp_rd_req"); + let (huffman_lit_weights_tmp_rd_resp_s, huffman_lit_weights_tmp_rd_resp_r) = chan("huffman_lit_weights_tmp_rd_resp"); + let (huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_req_r) = chan("huffman_lit_weights_tmp_wr_req"); + let (huffman_lit_weights_tmp_wr_resp_s, huffman_lit_weights_tmp_wr_resp_r) = chan("huffman_lit_weights_tmp_wr_resp"); + + let (huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_req_r) = chan("huffman_lit_weights_tmp2_rd_req"); + let (huffman_lit_weights_tmp2_rd_resp_s, huffman_lit_weights_tmp2_rd_resp_r) = chan("huffman_lit_weights_tmp2_rd_resp"); + let (huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_req_r) = chan("huffman_lit_weights_tmp2_wr_req"); + let (huffman_lit_weights_tmp2_wr_resp_s, huffman_lit_weights_tmp2_wr_resp_r) = chan("huffman_lit_weights_tmp2_wr_resp"); + + let (huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_req_r) = chan("huffman_lit_weights_fse_rd_req"); + let (huffman_lit_weights_fse_rd_resp_s, huffman_lit_weights_fse_rd_resp_r) = chan("huffman_lit_weights_fse_rd_resp_r"); + let (huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_req_r) = chan("huffman_lit_weights_fse_wr_req"); + let (huffman_lit_weights_fse_wr_resp_s, huffman_lit_weights_fse_wr_resp_r) = chan("huffman_lit_weights_fse_wr_resp"); + + spawn ram::RamModel( + huffman_lit_weights_dpd_rd_req_r, huffman_lit_weights_dpd_rd_resp_s, + huffman_lit_weights_dpd_wr_req_r, huffman_lit_weights_dpd_wr_resp_s, + ); + + spawn ram::RamModel( + huffman_lit_weights_tmp_rd_req_r, huffman_lit_weights_tmp_rd_resp_s, + huffman_lit_weights_tmp_wr_req_r, huffman_lit_weights_tmp_wr_resp_s, + ); + + spawn ram::RamModel( + huffman_lit_weights_tmp2_rd_req_r, huffman_lit_weights_tmp2_rd_resp_s, + huffman_lit_weights_tmp2_wr_req_r, huffman_lit_weights_tmp2_wr_resp_s, + ); + + spawn ram::RamModel( + huffman_lit_weights_fse_rd_req_r, huffman_lit_weights_fse_rd_resp_s, + huffman_lit_weights_fse_wr_req_r, huffman_lit_weights_fse_wr_resp_s, + ); + + spawn ram::RamModel( + huffman_lit_prescan_mem_rd_req_r, huffman_lit_prescan_mem_rd_resp_s, + huffman_lit_prescan_mem_wr_req_r, huffman_lit_prescan_mem_wr_resp_s + ); + + spawn ram::RamModel( + huffman_lit_weights_mem_rd_req_r, huffman_lit_weights_mem_rd_resp_s, + huffman_lit_weights_mem_wr_req_r, huffman_lit_weights_mem_wr_resp_s + ); // AXI channels for various blocks let (axi_ram_rd_req_s, axi_ram_rd_req_r) = chan[AXI_CHAN_N]("axi_ram_rd_req"); @@ -1132,14 +1321,14 @@ proc CompressBlockDecoderTest { let (axi_ram_r_s, axi_ram_r_r) = chan[AXI_CHAN_N]("axi_ram_r"); unroll_for! (i, ()): (u32, ()) in range(u32:0, AXI_CHAN_N) { spawn ram::RamModel< - TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_WORD_PARTITION_SIZE, + TEST_CASE_RAM_DATA_W, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED >( axi_ram_rd_req_r[i], axi_ram_rd_resp_s[i], axi_ram_wr_req_r[i], axi_ram_wr_resp_s[i] ); spawn axi_ram::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_CASE_RAM_SIZE, - TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_ADDR_WIDTH + TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_W, TEST_CASE_RAM_ADDR_W >( axi_ram_ar_r[i], axi_ram_r_s[i], axi_ram_rd_req_s[i], axi_ram_rd_resp_r[i] ); @@ -1152,7 +1341,7 @@ proc CompressBlockDecoderTest { let (litbuf_wr_resp_s, litbuf_wr_resp_r) = chan[u32:8]("litbuf_wr_resp"); unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:8) { spawn ram::RamModel< - LITERALS_BUFFER_RAM_DATA_WIDTH, LITERALS_BUFFER_RAM_SIZE, LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE, + TEST_LITERALS_BUFFER_RAM_DATA_W, TEST_LITERALS_BUFFER_RAM_SIZE, TEST_LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED >( litbuf_rd_req_r[i], litbuf_rd_resp_s[i], litbuf_wr_req_r[i], litbuf_wr_resp_s[i] @@ -1161,47 +1350,47 @@ proc CompressBlockDecoderTest { // RAMs for FSE decoder // DPD RAM - let (dpd_rd_req_s, dpd_rd_req_r) = chan("dpd_rd_req"); - let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); - let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); - let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); - spawn ram::RamModel("dpd_rd_req"); + let (dpd_rd_resp_s, dpd_rd_resp_r) = chan("dpd_rd_resp"); + let (dpd_wr_req_s, dpd_wr_req_r) = chan("dpd_wr_req"); + let (dpd_wr_resp_s, dpd_wr_resp_r) = chan("dpd_wr_resp"); + spawn ram::RamModel( dpd_rd_req_r, dpd_rd_resp_s, dpd_wr_req_r, dpd_wr_resp_s, ); // TMP RAM - let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); - let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); - let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); - let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); + let (tmp_rd_req_s, tmp_rd_req_r) = chan("tmp_rd_req"); + let (tmp_rd_resp_s, tmp_rd_resp_r) = chan("tmp_rd_resp"); + let (tmp_wr_req_s, tmp_wr_req_r) = chan("tmp_wr_req"); + let (tmp_wr_resp_s, tmp_wr_resp_r) = chan("tmp_wr_resp"); spawn ram::RamModel< - TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_SIZE, TEST_TMP_RAM_WORD_PARTITION_SIZE, + TEST_SEQ_TMP_RAM_DATA_W, TEST_SEQ_TMP_RAM_SIZE, TEST_SEQ_TMP_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED >( tmp_rd_req_r, tmp_rd_resp_s, tmp_wr_req_r, tmp_wr_resp_s, ); - let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); - let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); - let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); - let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); + let (tmp2_rd_req_s, tmp2_rd_req_r) = chan("tmp2_rd_req"); + let (tmp2_rd_resp_s, tmp2_rd_resp_r) = chan("tmp2_rd_resp"); + let (tmp2_wr_req_s, tmp2_wr_req_r) = chan("tmp2_wr_req"); + let (tmp2_wr_resp_s, tmp2_wr_resp_r) = chan("tmp2_wr_resp"); spawn ram::RamModel< - TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_SIZE, TEST_TMP2_RAM_WORD_PARTITION_SIZE, + TEST_SEQ_TMP2_RAM_DATA_W, TEST_SEQ_TMP2_RAM_SIZE, TEST_SEQ_TMP2_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED >( tmp2_rd_req_r, tmp2_rd_resp_s, tmp2_wr_req_r, tmp2_wr_resp_s, ); // FSE RAMs - let (fse_rd_req_s, fse_rd_req_r) = chan[u32:6]("tmp_rd_req"); - let (fse_rd_resp_s, fse_rd_resp_r) = chan[u32:6]("tmp_rd_resp"); - let (fse_wr_req_s, fse_wr_req_r) = chan[u32:6]("tmp_wr_req"); - let (fse_wr_resp_s, fse_wr_resp_r) = chan[u32:6]("tmp_wr_resp"); + let (fse_rd_req_s, fse_rd_req_r) = chan[u32:6]("tmp_rd_req"); + let (fse_rd_resp_s, fse_rd_resp_r) = chan[u32:6]("tmp_rd_resp"); + let (fse_wr_req_s, fse_wr_req_r) = chan[u32:6]("tmp_wr_req"); + let (fse_wr_resp_s, fse_wr_resp_r) = chan[u32:6]("tmp_wr_resp"); unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:6) { spawn ram::RamModel< - TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_SIZE, TEST_FSE_RAM_WORD_PARTITION_SIZE, + TEST_SEQ_FSE_RAM_DATA_W, TEST_SEQ_FSE_RAM_SIZE, TEST_SEQ_FSE_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIM_RW_BEHAVIOR, TEST_RAM_INITIALIZED >( fse_rd_req_r[i], fse_rd_resp_s[i], fse_wr_req_r[i], fse_wr_resp_s[i] @@ -1212,20 +1401,18 @@ proc CompressBlockDecoderTest { let (ll_sel_test_s, ll_sel_test_r) = chan("ll_sel_test"); - let (ll_def_test_rd_req_s, ll_def_test_rd_req_r) = chan("ll_def_test_rd_req"); - let (ll_def_test_rd_resp_s, ll_def_test_rd_resp_r) = chan("ll_def_test_rd_resp"); - let (ll_def_test_wr_req_s, ll_def_test_wr_req_r) = chan("ll_def_test_wr_req"); - let (ll_def_test_wr_resp_s, ll_def_test_wr_resp_r) = chan("ll_def_test_wr_resp"); + let (ll_def_test_rd_req_s, ll_def_test_rd_req_r) = chan("ll_def_test_rd_req"); + let (ll_def_test_rd_resp_s, ll_def_test_rd_resp_r) = chan("ll_def_test_rd_resp"); + let (ll_def_test_wr_req_s, ll_def_test_wr_req_r) = chan("ll_def_test_wr_req"); + let (ll_def_test_wr_resp_s, ll_def_test_wr_resp_r) = chan("ll_def_test_wr_resp"); - let (ll_def_fse_rd_req_s, ll_def_fse_rd_req_r) = chan("ll_def_fse_rd_req"); - let (ll_def_fse_rd_resp_s, ll_def_fse_rd_resp_r) = chan("ll_def_fse_rd_resp"); - let (ll_def_fse_wr_req_s, ll_def_fse_wr_req_r) = chan("ll_def_fse_wr_req"); - let (ll_def_fse_wr_resp_s, ll_def_fse_wr_resp_r) = chan("ll_def_fse_wr_resp"); + let (ll_def_fse_rd_req_s, ll_def_fse_rd_req_r) = chan("ll_def_fse_rd_req"); + let (ll_def_fse_rd_resp_s, ll_def_fse_rd_resp_r) = chan("ll_def_fse_rd_resp"); + let (ll_def_fse_wr_req_s, ll_def_fse_wr_req_r) = chan("ll_def_fse_wr_req"); + let (ll_def_fse_wr_resp_s, ll_def_fse_wr_resp_r) = chan("ll_def_fse_wr_resp"); spawn ram_mux::RamMux< - TEST_FSE_RAM_ADDR_W, - TEST_FSE_RAM_DATA_W, - TEST_FSE_RAM_NUM_PARTITIONS, + TEST_SEQ_FSE_RAM_ADDR_W, TEST_SEQ_FSE_RAM_DATA_W, TEST_SEQ_FSE_RAM_NUM_PARTITIONS, >( ll_sel_test_r, ll_def_test_rd_req_r, ll_def_test_rd_resp_s, ll_def_test_wr_req_r, ll_def_test_wr_resp_s, @@ -1237,20 +1424,18 @@ proc CompressBlockDecoderTest { let (ml_sel_test_s, ml_sel_test_r) = chan("ml_sel_test"); - let (ml_def_test_rd_req_s, ml_def_test_rd_req_r) = chan("ml_def_test_rd_req"); - let (ml_def_test_rd_resp_s, ml_def_test_rd_resp_r) = chan("ml_def_test_rd_resp"); - let (ml_def_test_wr_req_s, ml_def_test_wr_req_r) = chan("ml_def_test_wr_req"); - let (ml_def_test_wr_resp_s, ml_def_test_wr_resp_r) = chan("ml_def_test_wr_resp"); + let (ml_def_test_rd_req_s, ml_def_test_rd_req_r) = chan("ml_def_test_rd_req"); + let (ml_def_test_rd_resp_s, ml_def_test_rd_resp_r) = chan("ml_def_test_rd_resp"); + let (ml_def_test_wr_req_s, ml_def_test_wr_req_r) = chan("ml_def_test_wr_req"); + let (ml_def_test_wr_resp_s, ml_def_test_wr_resp_r) = chan("ml_def_test_wr_resp"); - let (ml_def_fse_rd_req_s, ml_def_fse_rd_req_r) = chan("ml_def_fse_rd_req"); - let (ml_def_fse_rd_resp_s, ml_def_fse_rd_resp_r) = chan("ml_def_fse_rd_resp"); - let (ml_def_fse_wr_req_s, ml_def_fse_wr_req_r) = chan("ml_def_fse_wr_req"); - let (ml_def_fse_wr_resp_s, ml_def_fse_wr_resp_r) = chan("ml_def_fse_wr_resp"); + let (ml_def_fse_rd_req_s, ml_def_fse_rd_req_r) = chan("ml_def_fse_rd_req"); + let (ml_def_fse_rd_resp_s, ml_def_fse_rd_resp_r) = chan("ml_def_fse_rd_resp"); + let (ml_def_fse_wr_req_s, ml_def_fse_wr_req_r) = chan("ml_def_fse_wr_req"); + let (ml_def_fse_wr_resp_s, ml_def_fse_wr_resp_r) = chan("ml_def_fse_wr_resp"); spawn ram_mux::RamMux< - TEST_FSE_RAM_ADDR_W, - TEST_FSE_RAM_DATA_W, - TEST_FSE_RAM_NUM_PARTITIONS, + TEST_SEQ_FSE_RAM_ADDR_W, TEST_SEQ_FSE_RAM_DATA_W, TEST_SEQ_FSE_RAM_NUM_PARTITIONS, >( ml_sel_test_r, ml_def_test_rd_req_r, ml_def_test_rd_resp_s, ml_def_test_wr_req_r, ml_def_test_wr_resp_s, @@ -1262,20 +1447,18 @@ proc CompressBlockDecoderTest { let (of_sel_test_s, of_sel_test_r) = chan("of_sel_test"); - let (of_def_test_rd_req_s, of_def_test_rd_req_r) = chan("of_def_test_rd_req"); - let (of_def_test_rd_resp_s, of_def_test_rd_resp_r) = chan("of_def_test_rd_resp"); - let (of_def_test_wr_req_s, of_def_test_wr_req_r) = chan("of_def_test_wr_req"); - let (of_def_test_wr_resp_s, of_def_test_wr_resp_r) = chan("of_def_test_wr_resp"); + let (of_def_test_rd_req_s, of_def_test_rd_req_r) = chan("of_def_test_rd_req"); + let (of_def_test_rd_resp_s, of_def_test_rd_resp_r) = chan("of_def_test_rd_resp"); + let (of_def_test_wr_req_s, of_def_test_wr_req_r) = chan("of_def_test_wr_req"); + let (of_def_test_wr_resp_s, of_def_test_wr_resp_r) = chan("of_def_test_wr_resp"); - let (of_def_fse_rd_req_s, of_def_fse_rd_req_r) = chan("of_def_fse_rd_req"); - let (of_def_fse_rd_resp_s, of_def_fse_rd_resp_r) = chan("of_def_fse_rd_resp"); - let (of_def_fse_wr_req_s, of_def_fse_wr_req_r) = chan("of_def_fse_wr_req"); - let (of_def_fse_wr_resp_s, of_def_fse_wr_resp_r) = chan("of_def_fse_wr_resp"); + let (of_def_fse_rd_req_s, of_def_fse_rd_req_r) = chan("of_def_fse_rd_req"); + let (of_def_fse_rd_resp_s, of_def_fse_rd_resp_r) = chan("of_def_fse_rd_resp"); + let (of_def_fse_wr_req_s, of_def_fse_wr_req_r) = chan("of_def_fse_wr_req"); + let (of_def_fse_wr_resp_s, of_def_fse_wr_resp_r) = chan("of_def_fse_wr_resp"); spawn ram_mux::RamMux< - TEST_FSE_RAM_ADDR_W, - TEST_FSE_RAM_DATA_W, - TEST_FSE_RAM_NUM_PARTITIONS, + TEST_SEQ_FSE_RAM_ADDR_W, TEST_SEQ_FSE_RAM_DATA_W, TEST_SEQ_FSE_RAM_NUM_PARTITIONS, >( of_sel_test_r, of_def_test_rd_req_r, of_def_test_rd_resp_s, of_def_test_wr_req_r, of_def_test_wr_resp_s, @@ -1285,11 +1468,16 @@ proc CompressBlockDecoderTest { spawn CompressBlockDecoder< TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, - // FSE lookup table RAMs - TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, - TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, - TEST_TMP2_RAM_ADDR_W, TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_NUM_PARTITIONS, - TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, + + TEST_SEQ_DPD_RAM_ADDR_W, TEST_SEQ_DPD_RAM_DATA_W, TEST_SEQ_DPD_RAM_NUM_PARTITIONS, + TEST_SEQ_TMP_RAM_ADDR_W, TEST_SEQ_TMP_RAM_DATA_W, TEST_SEQ_TMP_RAM_NUM_PARTITIONS, + TEST_SEQ_TMP2_RAM_ADDR_W, TEST_SEQ_TMP2_RAM_DATA_W, TEST_SEQ_TMP2_RAM_NUM_PARTITIONS, + TEST_SEQ_FSE_RAM_ADDR_W, TEST_SEQ_FSE_RAM_DATA_W, TEST_SEQ_FSE_RAM_NUM_PARTITIONS, + + TEST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS, >( req_r, resp_s, cmd_constr_out_s, @@ -1312,6 +1500,7 @@ proc CompressBlockDecoderTest { axi_ram_ar_s[7], axi_ram_r_r[7], axi_ram_ar_s[8], axi_ram_r_r[8], axi_ram_ar_s[9], axi_ram_r_r[9], + axi_ram_ar_s[10], axi_ram_r_r[10], litbuf_rd_req_s[0], litbuf_rd_req_s[1], litbuf_rd_req_s[2], litbuf_rd_req_s[3], litbuf_rd_req_s[4], litbuf_rd_req_s[5], litbuf_rd_req_s[6], litbuf_rd_req_s[7], litbuf_rd_resp_r[0], litbuf_rd_resp_r[1], litbuf_rd_resp_r[2], litbuf_rd_resp_r[3], @@ -1324,6 +1513,14 @@ proc CompressBlockDecoderTest { huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, ); ( @@ -1350,10 +1547,10 @@ proc CompressBlockDecoderTest { trace_fmt!("Filling LL default FSE table"); let tok = send(tok, ll_sel_test_s, u1:0); let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_LL_TABLE)) { - let req = FseRamWrReq { - addr: i as uN[TEST_FSE_RAM_ADDR_W], + let req = SeqFseRamWrReq { + addr: i as uN[TEST_SEQ_FSE_RAM_ADDR_W], data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_LL_TABLE[i]), - mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + mask: !uN[TEST_SEQ_FSE_RAM_NUM_PARTITIONS]:0, }; let tok = send(tok, ll_def_test_wr_req_s, req); let (tok, _) = recv(tok, ll_def_test_wr_resp_r); @@ -1365,10 +1562,10 @@ proc CompressBlockDecoderTest { trace_fmt!("Filling OF default FSE table"); let tok = send(tok, of_sel_test_s, u1:0); let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_OF_TABLE)) { - let req = FseRamWrReq { - addr: i as uN[TEST_FSE_RAM_ADDR_W], + let req = SeqFseRamWrReq { + addr: i as uN[TEST_SEQ_FSE_RAM_ADDR_W], data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_OF_TABLE[i]), - mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + mask: !uN[TEST_SEQ_FSE_RAM_NUM_PARTITIONS]:0, }; let tok = send(tok, of_def_test_wr_req_s, req); let (tok, _) = recv(tok, of_def_test_wr_resp_r); @@ -1380,10 +1577,10 @@ proc CompressBlockDecoderTest { trace_fmt!("Filling ML default FSE table"); let tok = send(tok, ml_sel_test_s, u1:0); let tok = unroll_for! (i, tok): (u32, token) in range(u32:0, array_size(sequence_dec::DEFAULT_ML_TABLE)) { - let req = FseRamWrReq { - addr: i as uN[TEST_FSE_RAM_ADDR_W], + let req = SeqFseRamWrReq { + addr: i as uN[TEST_SEQ_FSE_RAM_ADDR_W], data: fse_table_creator::fse_record_to_bits(sequence_dec::DEFAULT_ML_TABLE[i]), - mask: !uN[TEST_FSE_RAM_NUM_PARTITIONS]:0, + mask: !uN[TEST_SEQ_FSE_RAM_NUM_PARTITIONS]:0, }; let tok = send(tok, ml_def_test_wr_req_s, req); let (tok, _) = recv(tok, ml_def_test_wr_resp_r); @@ -1397,8 +1594,8 @@ proc CompressBlockDecoderTest { trace_fmt!("Loading testcase {}", test_i); let tok = for ((i, input_data), tok): ((u32, u64), token) in enumerate(input) { let req = TestcaseRamWrReq { - addr: i as uN[TEST_CASE_RAM_ADDR_WIDTH], - data: input_data as uN[TEST_CASE_RAM_DATA_WIDTH], + addr: i as uN[TEST_CASE_RAM_ADDR_W], + data: input_data as uN[TEST_CASE_RAM_DATA_W], mask: !uN[TEST_CASE_RAM_NUM_PARTITIONS]:0 }; // Write to all RAMs diff --git a/xls/modules/zstd/comp_frame_huffman_fse.x b/xls/modules/zstd/comp_frame_huffman_fse.x new file mode 100644 index 0000000000..7732b115cd --- /dev/null +++ b/xls/modules/zstd/comp_frame_huffman_fse.x @@ -0,0 +1,21 @@ +pub struct DataArray{ + data: uN[BITS_PER_WORD][LENGTH], + length: u32, + array_length: u32 +} +pub const FRAMES:DataArray< + u32:64, + u32:8 +>[1] = [DataArray<64, 8>{ + length: u32:64, + array_length: u32:8, + data: uN[64][8]:[uN[64]:0x007e4f84fd2fb528, uN[64]:0x00068e00017d0000, uN[64]:0xd5764f39f0080008, uN[64]:0x04000400045c4f40, uN[64]:0xcfefff3e7fefff00, uN[64]:0x5dff77afbdffef3f, uN[64]:0x1de190b0000301fb, uN[64]:0x807e83a8084e0c21] +}]; +pub const DECOMPRESSED_FRAMES:DataArray< + u32:64, + u32:16 +>[1] = [DataArray<64, 16>{ + length: u32:126, + array_length: u32:16, + data: uN[64][16]:[uN[64]:0xe6e6e6e6e6e6e6e6, uN[64]:0xe6e6e6e6e680e6e6, uN[64]:0xe6e6e6b3e6e6e6e6, uN[64]:0xe6e6e6e6e6e6e6e6, uN[64]:0x80e6e6e6e6e6e6e6, uN[64]:0xe6e6e6e6e6e6e6e6, uN[64]:0xe6b3e6e6e6e6e6e6, uN[64]:0xe6e6e6e6e6e6e6e6, uN[64]:0xe6e6e6e6b3b3e6e6, uN[64]:0xe6e6e6b3e6e6e6b3, uN[64]:0xe6e6e6e6e6e6b3e6, uN[64]:0xe6e6e6e6e6e6e6e6, uN[64]:0xe6e6e6e6e6e6e6b3, uN[64]:0xb3e6e6b3b3e6b3e6, uN[64]:0xe6e6e6e6e6e6e6e6, uN[64]:0xe6e6b3e6e6b3] +}]; diff --git a/xls/modules/zstd/comp_lookup_dec.x b/xls/modules/zstd/comp_lookup_dec.x index 628326edf9..fd18e038b0 100644 --- a/xls/modules/zstd/comp_lookup_dec.x +++ b/xls/modules/zstd/comp_lookup_dec.x @@ -25,6 +25,15 @@ import xls.modules.zstd.fse_proba_freq_dec; import xls.modules.shift_buffer.shift_buffer; type AccuracyLog = common::FseAccuracyLog; +type ConsumedFseBytes = fse_proba_freq_dec::ConsumedFseBytes; + +pub type CompLookupDecoderReq = common::LookupDecoderReq; +pub type CompLookupDecoderStatus = common::LookupDecoderStatus; +pub struct CompLookupDecoderResp { + status: CompLookupDecoderStatus, + accuracy_log: AccuracyLog, + consumed_bytes: ConsumedFseBytes, +} pub proc CompLookupDecoder< AXI_DATA_W: u32, @@ -34,9 +43,9 @@ pub proc CompLookupDecoder< FSE_RAM_DATA_W: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_NUM_PARTITIONS: u32, SB_LENGTH_W: u32 = {refilling_shift_buffer::length_width(AXI_DATA_W)}, > { - type Req = common::LookupDecoderReq; - type Resp = common::LookupDecoderResp; - type Status = common::LookupDecoderStatus; + type Req = CompLookupDecoderReq; + type Resp = CompLookupDecoderResp; + type Status = CompLookupDecoderStatus; type FseTableStart = fse_table_creator::FseStartMsg; @@ -158,7 +167,11 @@ pub proc CompLookupDecoder< trace_fmt!("FSE table created"); let resp = if pf_dec_ok { - Resp { status: Status::OK, accuracy_log: pf_dec_res.accuracy_log } + Resp { + status: Status::OK, + accuracy_log: pf_dec_res.accuracy_log, + consumed_bytes: pf_dec_res.consumed_bytes, + } } else { Resp { status: Status::ERROR, ..zero!() } }; @@ -214,7 +227,7 @@ const TEST_RAM_INITIALIZED = true; type FseTableRecord = common::FseTableRecord; -const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], common::LookupDecoderResp)[12] = [ +const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE], CompLookupDecoderResp)[12] = [ ( u64[64]:[u64:0x72AAAAABBB1D25C0, u64:0, ...], FseTableRecord[TEST_FSE_RAM_SIZE]:[ @@ -252,7 +265,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:3} ), ( u64[64]:[u64:0x1861862062081932, u64:0xC18628A106184184, u64:0x850720FACC49238, u64:0, ...], @@ -387,7 +400,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x9, num_of_bits: u8:0x6, base: u16:0x40 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:7, consumed_bytes: ConsumedFseBytes:21} ), ( u64[64]:[u64:0x60C3082082085072, u64:0x1C06F8077D850F20, u64:0, ...], @@ -522,7 +535,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0xb, num_of_bits: u8:0x3, base: u16:0x58 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:7 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:7, consumed_bytes: ConsumedFseBytes:13 } ), ( u64[64]:[u64:0x41081C158003A5D0, u64:0, ...], @@ -561,7 +574,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x17 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:3 } ), ( u64[64]:[u64:0x1101141108088A1, u64:0xA210842108421011, u64:0xAC90E792007A5B4, u64:0, ...], @@ -632,7 +645,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x1c, num_of_bits: u8:0x3, base: u16:0x8 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:6 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:6, consumed_bytes: ConsumedFseBytes:19 } ), ( u64[64]:[u64:0x4AF830AC90E7920, u64:0, ...], @@ -671,7 +684,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x1, num_of_bits: u8:0x1, base: u16:0xa }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:3 } ), ( u64[64]:[u64:0xF47FFEBBFF1D25C0, u64:0, ...], @@ -710,7 +723,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x0, num_of_bits: u8:0x0, base: u16:0x15 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:3 } ), ( u64[64]:[u64:0xA84DF134544CA40, u64:0xEEC609988403B0C, u64:0, ...], @@ -749,7 +762,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x14, num_of_bits: u8:0x3, base: u16:0x8 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:10 } ), ( u64[64]:[u64:0x38100EEC60998840, u64:0, ...], @@ -788,7 +801,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x7, num_of_bits: u8:0x2, base: u16:0xc }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:6 } ), ( u64[64]:[u64:0x6B1CA24D0CE43810, u64:0x6651065104A4DFFD, u64:0, ...], @@ -827,7 +840,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0xf, num_of_bits: u8:0x3, base: u16:0x8 }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:5 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:5, consumed_bytes: ConsumedFseBytes:10 } ), ( u64[64]:[u64:0x604FC0502602814, u64:0xE030505040131FF6, u64:0, ...], @@ -1345,7 +1358,7 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x10, num_of_bits: u8:0x2, base: u16:0x1fc }, FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0x1fc }, ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:9 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:9, consumed_bytes: ConsumedFseBytes:10 } ), ( u64[64]:[u64:0x140FE03050504013, u64:0, ...], @@ -1608,15 +1621,15 @@ const COMP_LOOKUP_DECODER_TESTCASES: (u64[64], FseTableRecord[TEST_FSE_RAM_SIZE] FseTableRecord { symbol: u8:0x5, num_of_bits: u8:0x2, base: u16:0xfc }, zero!(), ... ], - common::LookupDecoderResp { status: common::LookupDecoderStatus::OK, accuracy_log: AccuracyLog:8 } + CompLookupDecoderResp { status: CompLookupDecoderStatus::OK, accuracy_log: AccuracyLog:8, consumed_bytes: ConsumedFseBytes:7 } ), ]; #[test_proc] proc CompLookupDecoderTest { - type Req = common::LookupDecoderReq; - type Resp = common::LookupDecoderResp; - type Status = common::LookupDecoderStatus; + type Req = CompLookupDecoderReq; + type Resp = CompLookupDecoderResp; + type Status = CompLookupDecoderStatus; type MemReaderReq = mem_reader::MemReaderReq; type MemReaderResp = mem_reader::MemReaderResp; @@ -1793,7 +1806,7 @@ proc CompLookupDecoderTest { tok }(tok); - trace_fmt!("Running FSE lookup decoder on testcase {:x}", test_i); + trace_fmt!("Running COMP lookup decoder on testcase {:x}", test_i); let tok = send(tok, refill_req_s, RefillStartReq { start_addr: uN[TEST_AXI_ADDR_WIDTH]:0x0 }); diff --git a/xls/modules/zstd/fse_lookup_dec.x b/xls/modules/zstd/fse_lookup_dec.x index 581dcac5d2..85664be982 100644 --- a/xls/modules/zstd/fse_lookup_dec.x +++ b/xls/modules/zstd/fse_lookup_dec.x @@ -68,17 +68,19 @@ pub proc FseLookupDecoder< type SBOutput = refilling_shift_buffer::RefillingShiftBufferOutput; type SBCtrl = refilling_shift_buffer::RefillingShiftBufferCtrl; + type CompLookupDecoderReq = comp_lookup_dec::CompLookupDecoderReq; + type CompLookupDecoderResp = comp_lookup_dec::CompLookupDecoderResp; + type LookupDecoderReq = common::LookupDecoderReq; type LookupDecoderResp = common::LookupDecoderResp; - init {} fse_lookup_dec_req_r: chan in; fse_lookup_dec_resp_s: chan out; - comp_lookup_req_s: chan out; - comp_lookup_resp_r: chan in; + comp_lookup_req_s: chan out; + comp_lookup_resp_r: chan in; rle_lookup_req_s: chan out; rle_lookup_resp_r: chan in; @@ -164,8 +166,8 @@ pub proc FseLookupDecoder< fse_rd_req_s, fse_rd_resp_r, fse_wr_req_s, fse_wr_resp_r, ); - let (comp_lookup_req_s, comp_lookup_req_r) = chan("comp_lookup_req"); - let (comp_lookup_resp_s, comp_lookup_resp_r) = chan("comp_lookup_resp"); + let (comp_lookup_req_s, comp_lookup_req_r) = chan("comp_lookup_req"); + let (comp_lookup_resp_s, comp_lookup_resp_r) = chan("comp_lookup_resp"); spawn comp_lookup_dec::CompLookupDecoder< AXI_DATA_W, @@ -226,12 +228,17 @@ pub proc FseLookupDecoder< let tok4_0 = send_if(tok3, rle_lookup_req_s, req.is_rle, LookupDecoderReq {}); let (tok5_0, rle_lookup_resp) = recv_if(tok4_0, rle_lookup_resp_r, req.is_rle, zero!()); - let tok4_1 = send_if(tok3, comp_lookup_req_s, !req.is_rle, LookupDecoderReq {}); - let (tok5_1, comp_lookup_resp) = recv_if(tok4_1, comp_lookup_resp_r, !req.is_rle, zero!()); + let tok4_1 = send_if(tok3, comp_lookup_req_s, !req.is_rle, CompLookupDecoderReq {}); + let (tok5_1, comp_lookup_resp) = recv_if(tok4_1, comp_lookup_resp_r, !req.is_rle, zero!()); let tok5 = join(tok5_0, tok5_1); - let resp = if req.is_rle { rle_lookup_resp } else { comp_lookup_resp }; + let resp = if req.is_rle { rle_lookup_resp } else { + Resp { + status: comp_lookup_resp.status, + accuracy_log: comp_lookup_resp.accuracy_log + } + }; let tok6 = send(tok5, fse_lookup_dec_resp_s, resp); // unused channels diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index b3b650f2ae..825fbc05b6 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -37,20 +37,26 @@ pub type HuffmanLiteralsDecoderReq = ctrl::HuffmanControlAndSequenceCtrl; pub type HuffmanLiteralsDecoderResp = ctrl::HuffmanControlAndSequenceResp; pub type HuffmanLiteralsDecoderStatus = ctrl::HuffmanControlAndSequenceStatus; -pub const RAM_SIZE: u32 = prescan::RAM_SIZE; -pub const WEIGHTS_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; -pub const WEIGHTS_DATA_WIDTH: u32 = prescan::RAM_ACCESS_WIDTH; -pub const WEIGHTS_PARTITION_WORD_SIZE: u32 = WEIGHTS_DATA_WIDTH; -pub const WEIGHTS_NUM_PARTITIONS: u32 = u32:1; +pub const RAM_SIZE = prescan::RAM_SIZE; +pub const WEIGHTS_ADDR_WIDTH = prescan::RAM_ADDR_WIDTH; +pub const WEIGHTS_DATA_WIDTH = prescan::RAM_ACCESS_WIDTH; +pub const WEIGHTS_PARTITION_WORD_SIZE = WEIGHTS_DATA_WIDTH / u32:8; +pub const WEIGHTS_NUM_PARTITIONS = ram::num_partitions(WEIGHTS_PARTITION_WORD_SIZE, WEIGHTS_DATA_WIDTH); +// pub const WEIGHTS_NUM_PARTITIONS: u32 = u32:1; + pub const PRESCAN_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; pub const PRESCAN_DATA_WIDTH: u32 = prescan::WeightPreScanMetaDataSize(); pub const PRESCAN_PARTITION_WORD_SIZE: u32 = PRESCAN_DATA_WIDTH; -pub const PRESCAN_NUM_PARTITIONS: u32 = u32:1; +pub const PRESCAN_NUM_PARTITIONS = ram::num_partitions(PRESCAN_PARTITION_WORD_SIZE, PRESCAN_DATA_WIDTH); + +// pub const PRESCAN_NUM_PARTITIONS: u32 = u32:1; pub proc HuffmanLiteralsDecoder< AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, WEIGHTS_DPD_RAM_ADDR_W: u32, WEIGHTS_DPD_RAM_DATA_W: u32, WEIGHTS_DPD_RAM_NUM_PARTITIONS: u32, WEIGHTS_TMP_RAM_ADDR_W: u32, WEIGHTS_TMP_RAM_DATA_W: u32, WEIGHTS_TMP_RAM_NUM_PARTITIONS: u32, + WEIGHTS_TMP2_RAM_ADDR_W: u32, WEIGHTS_TMP2_RAM_DATA_W: u32, WEIGHTS_TMP2_RAM_NUM_PARTITIONS: u32, + WEIGHTS_FSE_RAM_ADDR_W: u32, WEIGHTS_FSE_RAM_DATA_W: u32, WEIGHTS_FSE_RAM_NUM_PARTITIONS: u32, WEIGHTS_RAM_ADDR_WIDTH: u32 = {WEIGHTS_ADDR_WIDTH}, WEIGHTS_RAM_DATA_WIDTH: u32 = {WEIGHTS_DATA_WIDTH}, @@ -69,6 +75,7 @@ pub proc HuffmanLiteralsDecoder< type WeightsRamRdResp = ram::ReadResp; type WeightsRamWrReq = ram::WriteReq; type WeightsRamWrResp = ram::WriteResp; + type PrescanRamRdReq = ram::ReadReq; type PrescanRamRdResp = ram::ReadResp; type PrescanRamWrReq = ram::WriteReq; @@ -85,6 +92,11 @@ pub proc HuffmanLiteralsDecoder< type WeightsTmpRamWrReq = ram::WriteReq; type WeightsTmpRamWrResp = ram::WriteResp; + type WeightsTmp2RamRdReq = ram::ReadReq; + type WeightsTmp2RamRdResp = ram::ReadResp; + type WeightsTmp2RamWrReq = ram::WriteReq; + type WeightsTmp2RamWrResp = ram::WriteResp; + type WeightsFseRamRdReq = ram::ReadReq; type WeightsFseRamRdResp = ram::ReadResp; type WeightsFseRamWrReq = ram::WriteReq; @@ -136,10 +148,17 @@ pub proc HuffmanLiteralsDecoder< weights_dpd_rd_resp_r: chan in, weights_dpd_wr_req_s: chan out, weights_dpd_wr_resp_r: chan in, + weights_tmp_rd_req_s: chan out, weights_tmp_rd_resp_r: chan in, weights_tmp_wr_req_s: chan out, weights_tmp_wr_resp_r: chan in, + + weights_tmp2_rd_req_s: chan out, + weights_tmp2_rd_resp_r: chan in, + weights_tmp2_wr_req_s: chan out, + weights_tmp2_wr_resp_r: chan in, + weights_fse_rd_req_s: chan out, weights_fse_rd_resp_r: chan in, weights_fse_wr_req_s: chan out, @@ -215,6 +234,7 @@ pub proc HuffmanLiteralsDecoder< WEIGHTS_RAM_ADDR_WIDTH, WEIGHTS_RAM_DATA_WIDTH, WEIGHTS_RAM_NUM_PARTITIONS, WEIGHTS_DPD_RAM_ADDR_W, WEIGHTS_DPD_RAM_DATA_W, WEIGHTS_DPD_RAM_NUM_PARTITIONS, WEIGHTS_TMP_RAM_ADDR_W, WEIGHTS_TMP_RAM_DATA_W, WEIGHTS_TMP_RAM_NUM_PARTITIONS, + WEIGHTS_TMP2_RAM_ADDR_W, WEIGHTS_TMP2_RAM_DATA_W, WEIGHTS_TMP2_RAM_NUM_PARTITIONS, WEIGHTS_FSE_RAM_ADDR_W, WEIGHTS_FSE_RAM_DATA_W, WEIGHTS_FSE_RAM_NUM_PARTITIONS, >( weights_dec_req_r, weights_dec_resp_s, @@ -225,6 +245,7 @@ pub proc HuffmanLiteralsDecoder< weights_ram_wr_req_s, weights_ram_wr_resp_r, weights_dpd_rd_req_s, weights_dpd_rd_resp_r, weights_dpd_wr_req_s, weights_dpd_wr_resp_r, weights_tmp_rd_req_s, weights_tmp_rd_resp_r, weights_tmp_wr_req_s, weights_tmp_wr_resp_r, + weights_tmp2_rd_req_s, weights_tmp2_rd_resp_r, weights_tmp2_wr_req_s, weights_tmp2_wr_resp_r, weights_fse_rd_req_s, weights_fse_rd_resp_r, weights_fse_wr_req_s, weights_fse_wr_resp_r, ); @@ -314,6 +335,14 @@ const INST_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( INST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, INST_WEIGHTS_TMP_RAM_DATA_W ); +const INST_WEIGHTS_TMP2_RAM_DATA_W = u32:8; +const INST_WEIGHTS_TMP2_RAM_SIZE = u32:512; +const INST_WEIGHTS_TMP2_RAM_ADDR_W = std::clog2(INST_WEIGHTS_TMP2_RAM_SIZE); +const INST_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE = INST_WEIGHTS_TMP2_RAM_DATA_W; +const INST_WEIGHTS_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, INST_WEIGHTS_TMP2_RAM_DATA_W +); + proc HuffmanLiteralsDecoderInst { type Ctrl = HuffmanLiteralsDecoderReq; type Resp = HuffmanLiteralsDecoderResp; @@ -324,6 +353,7 @@ proc HuffmanLiteralsDecoderInst { type WeightsRamRdResp = ram::ReadResp; type WeightsRamWrReq = ram::WriteReq; type WeightsRamWrResp = ram::WriteResp; + type PrescanRamRdReq = ram::ReadReq; type PrescanRamRdResp = ram::ReadResp; type PrescanRamWrReq = ram::WriteReq; @@ -339,6 +369,11 @@ proc HuffmanLiteralsDecoderInst { type WeightsTmpRamWrReq = ram::WriteReq; type WeightsTmpRamWrResp = ram::WriteResp; + type WeightsTmp2RamRdReq = ram::ReadReq; + type WeightsTmp2RamRdResp = ram::ReadResp; + type WeightsTmp2RamWrReq = ram::WriteReq; + type WeightsTmp2RamWrResp = ram::WriteResp; + type WeightsFseRamRdReq = ram::ReadReq; type WeightsFseRamRdResp = ram::ReadResp; type WeightsFseRamWrReq = ram::WriteReq; @@ -350,32 +385,46 @@ proc HuffmanLiteralsDecoderInst { decoded_literals_s: chan out, axi_ar_s: chan out, axi_r_r: chan in, + jump_table_axi_ar_s: chan out, jump_table_axi_r_r: chan in, + weights_header_dec_axi_ar_s: chan out, weights_header_dec_axi_r_r: chan in, + weights_raw_dec_axi_ar_s: chan out, weights_raw_dec_axi_r_r: chan in, + weights_fse_lookup_dec_axi_ar_s: chan out, weights_fse_lookup_dec_axi_r_r: chan in, weights_fse_decoder_dec_axi_ar_s: chan out, weights_fse_decoder_dec_axi_r_r: chan in, + weights_ram_rd_req_s: chan out, weights_ram_rd_resp_r: chan in, weights_ram_wr_req_s: chan out, weights_ram_wr_resp_r: chan in, + prescan_ram_rd_req_s: chan out, prescan_ram_rd_resp_r: chan in, prescan_ram_wr_req_s: chan out, prescan_ram_wr_resp_r: chan in, + weights_dpd_rd_req_s: chan out, weights_dpd_rd_resp_r: chan in, weights_dpd_wr_req_s: chan out, weights_dpd_wr_resp_r: chan in, + weights_tmp_rd_req_s: chan out, weights_tmp_rd_resp_r: chan in, weights_tmp_wr_req_s: chan out, weights_tmp_wr_resp_r: chan in, + + weights_tmp2_rd_req_s: chan out, + weights_tmp2_rd_resp_r: chan in, + weights_tmp2_wr_req_s: chan out, + weights_tmp2_wr_resp_r: chan in, + weights_fse_rd_req_s: chan out, weights_fse_rd_resp_r: chan in, weights_fse_wr_req_s: chan out, @@ -385,10 +434,12 @@ proc HuffmanLiteralsDecoderInst { INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, INST_WEIGHTS_DPD_RAM_ADDR_W, INST_WEIGHTS_DPD_RAM_DATA_W, INST_WEIGHTS_DPD_RAM_NUM_PARTITIONS, INST_WEIGHTS_TMP_RAM_ADDR_W, INST_WEIGHTS_TMP_RAM_DATA_W, INST_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + INST_WEIGHTS_TMP2_RAM_ADDR_W, INST_WEIGHTS_TMP2_RAM_DATA_W, INST_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + INST_WEIGHTS_FSE_RAM_ADDR_W, INST_WEIGHTS_FSE_RAM_DATA_W, INST_WEIGHTS_FSE_RAM_NUM_PARTITIONS, INST_WEIGHTS_RAM_ADDR_WIDTH, INST_WEIGHTS_RAM_DATA_WIDTH, INST_WEIGHTS_RAM_NUM_PARTITIONS, INST_PRESCAN_RAM_ADDR_WIDTH, INST_PRESCAN_RAM_DATA_WIDTH, INST_PRESCAN_RAM_NUM_PARTITIONS - >( + >( ctrl_r, resp_s, decoded_literals_s, axi_ar_s, axi_r_r, @@ -405,6 +456,8 @@ proc HuffmanLiteralsDecoderInst { weights_dpd_wr_req_s, weights_dpd_wr_resp_r, weights_tmp_rd_req_s, weights_tmp_rd_resp_r, weights_tmp_wr_req_s, weights_tmp_wr_resp_r, + weights_tmp2_rd_req_s, weights_tmp2_rd_resp_r, + weights_tmp2_wr_req_s, weights_tmp2_wr_resp_r, weights_fse_rd_req_s, weights_fse_rd_resp_r, weights_fse_wr_req_s, weights_fse_wr_resp_r, ); @@ -438,8 +491,9 @@ const TEST_AXI_RAM_MODEL_NUM = u32:1; pub const TEST_WEIGHTS_RAM_SIZE = prescan::RAM_SIZE; pub const TEST_WEIGHTS_RAM_ADDR_WIDTH = WEIGHTS_ADDR_WIDTH; pub const TEST_WEIGHTS_RAM_DATA_WIDTH = WEIGHTS_DATA_WIDTH; + pub const TEST_WEIGHTS_RAM_NUM_PARTITIONS = WEIGHTS_NUM_PARTITIONS; -pub const TEST_WEIGHTS_WORD_PARTITION_SIZE = TEST_WEIGHTS_RAM_DATA_WIDTH; +pub const TEST_WEIGHTS_WORD_PARTITION_SIZE = WEIGHTS_PARTITION_WORD_SIZE; pub const TEST_PRESCAN_RAM_ADDR_WIDTH = PRESCAN_ADDR_WIDTH; pub const TEST_PRESCAN_RAM_DATA_WIDTH = PRESCAN_DATA_WIDTH; pub const TEST_PRESCAN_RAM_NUM_PARTITIONS = PRESCAN_NUM_PARTITIONS; @@ -470,6 +524,14 @@ const TEST_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, TEST_WEIGHTS_TMP_RAM_DATA_W ); +const TEST_WEIGHTS_TMP2_RAM_DATA_W = u32:8; +const TEST_WEIGHTS_TMP2_RAM_SIZE = u32:512; +const TEST_WEIGHTS_TMP2_RAM_ADDR_W = std::clog2(TEST_WEIGHTS_TMP2_RAM_SIZE); +const TEST_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE = TEST_WEIGHTS_TMP2_RAM_DATA_W; +const TEST_WEIGHTS_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, TEST_WEIGHTS_TMP2_RAM_DATA_W +); + type TestCtrl = HuffmanLiteralsDecoderReq; type TestResp = HuffmanLiteralsDecoderResp; type TestAxiR = axi::AxiR; @@ -506,6 +568,11 @@ type TestWeightsTmpRamRdResp = ram::ReadResp; type TestWeightsTmpRamWrReq = ram::WriteReq; type TestWeightsTmpRamWrResp = ram::WriteResp; +type TestWeightsTmp2RamRdReq = ram::ReadReq; +type TestWeightsTmp2RamRdResp = ram::ReadResp; +type TestWeightsTmp2RamWrReq = ram::WriteReq; +type TestWeightsTmp2RamWrResp = ram::WriteResp; + type TestWeightsFseRamRdReq = ram::ReadReq; type TestWeightsFseRamRdResp = ram::ReadResp; type TestWeightsFseRamWrReq = ram::WriteReq; @@ -774,6 +841,17 @@ proc HuffmanLiteralsDecoder_test { TEST_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE >(weights_tmp_rd_req_r, weights_tmp_rd_resp_s, weights_tmp_wr_req_r, weights_tmp_wr_resp_s); + let (weights_tmp2_rd_req_s, weights_tmp2_rd_req_r) = chan("weights_tmp_rd_req"); + let (weights_tmp2_rd_resp_s, weights_tmp2_rd_resp_r) = chan("weights_tmp_rd_resp"); + let (weights_tmp2_wr_req_s, weights_tmp2_wr_req_r) = chan("weights_tmp_wr_req"); + let (weights_tmp2_wr_resp_s, weights_tmp2_wr_resp_r) = chan("weights_tmp_wr_resp"); + + spawn ram::RamModel< + TEST_WEIGHTS_TMP2_RAM_DATA_W, + TEST_WEIGHTS_TMP2_RAM_SIZE, + TEST_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE + >(weights_tmp2_rd_req_r, weights_tmp2_rd_resp_s, weights_tmp2_wr_req_r, weights_tmp2_wr_resp_s); + let (weights_fse_rd_req_s, weights_fse_rd_req_r) = chan("weights_tmp_rd_req"); let (weights_fse_rd_resp_s, weights_fse_rd_resp_r) = chan("weights_tmp_rd_resp"); let (weights_fse_wr_req_s, weights_fse_wr_req_r) = chan("weights_tmp_wr_req"); @@ -789,10 +867,11 @@ proc HuffmanLiteralsDecoder_test { TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_DEST_W, TEST_WEIGHTS_DPD_RAM_ADDR_W, TEST_WEIGHTS_DPD_RAM_DATA_W, TEST_WEIGHTS_DPD_RAM_NUM_PARTITIONS, TEST_WEIGHTS_TMP_RAM_ADDR_W, TEST_WEIGHTS_TMP_RAM_DATA_W, TEST_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + TEST_WEIGHTS_TMP2_RAM_ADDR_W, TEST_WEIGHTS_TMP2_RAM_DATA_W, TEST_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, TEST_WEIGHTS_FSE_RAM_ADDR_W, TEST_WEIGHTS_FSE_RAM_DATA_W, TEST_WEIGHTS_FSE_RAM_NUM_PARTITIONS, TEST_WEIGHTS_RAM_ADDR_WIDTH, TEST_WEIGHTS_RAM_DATA_WIDTH, TEST_WEIGHTS_RAM_NUM_PARTITIONS, TEST_PRESCAN_RAM_ADDR_WIDTH, TEST_PRESCAN_RAM_DATA_WIDTH, TEST_PRESCAN_RAM_NUM_PARTITIONS, - >( + >( ctrl_r, resp_s, decoded_literals_s, axi_ar_s, axi_r_r, jump_table_axi_ar_s, jump_table_axi_r_r, @@ -806,6 +885,7 @@ proc HuffmanLiteralsDecoder_test { prescan_ram_wr_req_s, prescan_ram_wr_resp_r, weights_dpd_rd_req_s, weights_dpd_rd_resp_r, weights_dpd_wr_req_s, weights_dpd_wr_resp_r, weights_tmp_rd_req_s, weights_tmp_rd_resp_r, weights_tmp_wr_req_s, weights_tmp_wr_resp_r, + weights_tmp2_rd_req_s, weights_tmp2_rd_resp_r, weights_tmp2_wr_req_s, weights_tmp2_wr_resp_r, weights_fse_rd_req_s, weights_fse_rd_resp_r, weights_fse_wr_req_s, weights_fse_wr_resp_r, ); diff --git a/xls/modules/zstd/huffman_prescan.x b/xls/modules/zstd/huffman_prescan.x index 6acf0284aa..47487a45c6 100644 --- a/xls/modules/zstd/huffman_prescan.x +++ b/xls/modules/zstd/huffman_prescan.x @@ -92,6 +92,8 @@ fn struct_to_bots_to_struct_qtest(x: WeightPreScanMetaData) -> bool { pub const RAM_SIZE = MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH * u32:8 / WEIGHT_LOG; pub const RAM_ADDR_WIDTH = {std::clog2(RAM_SIZE)}; pub const RAM_ACCESS_WIDTH = PARALLEL_ACCESS_WIDTH * WEIGHT_LOG; +const RAM_PARTITION_SIZE = RAM_ACCESS_WIDTH / u32:8; +const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_PARTITION_SIZE, RAM_ACCESS_WIDTH); const MAX_RAM_ADDR = MAX_SYMBOL_COUNT/PARALLEL_ACCESS_WIDTH; enum WeightPreScanFSM: u2 { @@ -124,7 +126,7 @@ pub proc WeightPreScan type OutData = WeightPreScanOutput; - type ReadReq = ram::ReadReq; + type ReadReq = ram::ReadReq; type ReadResp = ram::ReadResp; type InternalRamAddr = uN[RAM_ADDR_WIDTH]; @@ -241,7 +243,7 @@ pub proc WeightPreScan let external_ram_req = ReadReq { addr: addr, - mask: u1:1, + mask: !uN[RAM_NUM_PARTITIONS]:0, }; let tok3 = send_if(tok, read_req_s, send_addr, external_ram_req); if send_addr { @@ -323,9 +325,9 @@ proc Prescan_test{ type PrescanOut = WeightPreScanOutput; - type ReadReq = ram::ReadReq; + type ReadReq = ram::ReadReq; type ReadResp = ram::ReadResp; - type WriteReq = ram::WriteReq; + type WriteReq = ram::WriteReq; type WriteResp = ram::WriteResp<>; type InternalReadReq = ram::ReadReq; @@ -338,6 +340,7 @@ proc Prescan_test{ external_ram_resp: chan in; start_prescan: chan out; prescan_response: chan in; + init{()} config (terminator: chan out) { // Emulate external memory @@ -345,7 +348,7 @@ proc Prescan_test{ let (RAMExternalWriteResp_s, RAMExternalWriteResp_r) = chan("Write_channel_resp"); let (RAMExternalReadReq_s, RAMExternalReadReq_r) = chan("Read_channel_req"); let (RAMExternalReadResp_s, RAMExternalReadResp_r) = chan("Read_channel_resp"); - spawn ram::RamModel( + spawn ram::RamModel( RAMExternalReadReq_r, RAMExternalReadResp_s, RAMExternalWriteReq_r, RAMExternalWriteResp_s ); @@ -379,7 +382,7 @@ proc Prescan_test{ let external_w_req = WriteReq { addr: i as uN[RAM_ADDR_WIDTH], data: data_to_send, - mask: u1:1 + mask: !uN[RAM_NUM_PARTITIONS]:0 }; send(tok, external_ram_req, external_w_req); recv(tok, external_ram_resp); diff --git a/xls/modules/zstd/huffman_weights_dec.x b/xls/modules/zstd/huffman_weights_dec.x index 6c7b3aed36..287cf7ba17 100644 --- a/xls/modules/zstd/huffman_weights_dec.x +++ b/xls/modules/zstd/huffman_weights_dec.x @@ -22,7 +22,7 @@ import xls.modules.zstd.memory.axi_ram; import xls.modules.zstd.memory.mem_reader; import xls.modules.zstd.ram_mux; import xls.modules.zstd.refilling_shift_buffer; -import xls.modules.zstd.fse_lookup_dec; +import xls.modules.zstd.comp_lookup_dec; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.math; @@ -881,8 +881,8 @@ proc HuffmanFseWeightsDecoder< type WeightsRamWrReq = ram::WriteReq; type WeightsRamWrResp = ram::WriteResp; - type FseLookupDecoderReq = fse_lookup_dec::FseLookupDecoderReq; - type FseLookupDecoderResp = fse_lookup_dec::FseLookupDecoderResp; + type CompLookupDecoderReq = comp_lookup_dec::CompLookupDecoderReq; + type CompLookupDecoderResp = comp_lookup_dec::CompLookupDecoderResp; type DpdRamRdReq = ram::ReadReq; type DpdRamRdResp = ram::ReadResp; @@ -927,8 +927,8 @@ proc HuffmanFseWeightsDecoder< fd_rsb_flushing_done_r: chan<()> in; // FSE Lookup Decoder - fld_req_s: chan out; - fld_resp_r: chan in; + fld_req_s: chan out; + fld_resp_r: chan in; // Huffman FSE Decoder fd_ctrl_s: chan out; @@ -976,7 +976,7 @@ proc HuffmanFseWeightsDecoder< ) { const CHANNEL_DEPTH = u32:1; - // FseLookupDecoder + // CompLookupDecoder let (fld_rsb_start_req_s, fld_rsb_start_req_r) = chan("fd_rsb_start_req"); let (fld_rsb_stop_flush_req_s, fld_rsb_stop_flush_req_r) = chan<(), CHANNEL_DEPTH>("fd_rsb_stop_flush_req"); let (fld_rsb_ctrl_s, fld_rsb_ctrl_r) = chan("fd_rsb_ctrl"); @@ -990,10 +990,10 @@ proc HuffmanFseWeightsDecoder< fld_rsb_flushing_done_s, ); - let (fld_req_s, fld_req_r) = chan("fse_req"); - let (fld_resp_s, fld_resp_r) = chan("fse_resp"); + let (fld_req_s, fld_req_r) = chan("fse_req"); + let (fld_resp_s, fld_resp_r) = chan("fse_resp"); - spawn fse_lookup_dec::FseLookupDecoder< + spawn comp_lookup_dec::CompLookupDecoder< AXI_DATA_W, DPD_RAM_DATA_W, DPD_RAM_ADDR_W, DPD_RAM_NUM_PARTITIONS, TMP_RAM_DATA_W, TMP_RAM_ADDR_W, TMP_RAM_NUM_PARTITIONS, @@ -1059,7 +1059,7 @@ proc HuffmanFseWeightsDecoder< let tok = send(tok, fld_rsb_start_req_s, fld_rsb_start_req); trace_fmt!("[FSE] Sent refilling shift buffer start request {:#x}", fld_rsb_start_req); - let fld_req = FseLookupDecoderReq {}; + let fld_req = CompLookupDecoderReq {}; let tok = send(tok, fld_req_s, fld_req); trace_fmt!("[FSE] Sent FSE lookup decoding request {:#x}", fld_req); @@ -1266,18 +1266,15 @@ pub proc HuffmanWeightsDecoder< let (raw_weights_ram_wr_resp_s, raw_weights_ram_wr_resp_r) = chan("raw_weights_ram_wr_resp"); // Internal RAM Write interface with decoded Fse Huffman Tree Description - let (fse_weights_ram_wr_req_s, fse_weights_ram_wr_req_r) = chan("raw_weights_ram_wr_req"); - let (fse_weights_ram_wr_resp_s, fse_weights_ram_wr_resp_r) = chan("raw_weights_ram_wr_resp"); - - let (fse_lookup_weights_ram_wr_req_s, fse_lookup_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); - let (fse_lookup_weights_ram_wr_resp_s, fse_lookup_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp"); - let (fse_decoder_weights_ram_wr_req_s, fse_decoder_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); - let (fse_decoder_weights_ram_wr_resp_s, fse_decoder_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp"); + let (fse_weights_ram_wr_req_s, fse_weights_ram_wr_req_r) = chan("fse_weights_ram_wr_req"); + let (fse_weights_ram_wr_resp_s, fse_weights_ram_wr_resp_r) = chan("fse_weights_ram_wr_resp_s"); let (raw_weights_ram_rd_req_s, raw_weights_ram_rd_req_r) = chan("raw_weights_ram_rd_req"); let (raw_weights_ram_rd_resp_s, raw_weights_ram_rd_resp_r) = chan("raw_weights_ram_rd_resp"); + let (fse_weights_ram_rd_req_s, fse_weights_ram_rd_req_r) = chan("fse_weights_ram_rd_req"); let (fse_weights_ram_rd_resp_s, fse_weights_ram_rd_resp_r) = chan("fse_weights_ram_rd_resp"); + let (weights_ram_rd_req_s, weights_ram_rd_req_r) = chan("weights_ram_rd_req"); let (weights_ram_rd_resp_s, weights_ram_rd_resp_r) = chan("weights_ram_rd_resp"); @@ -1658,247 +1655,247 @@ const TESTCASES_FSE: (u8[32], u8[128])[7] = [ ( u8[32]:[ u8:10, - u8:0xC0, u8:0x25, u8:0x1D, u8:0x49, u8:0x6E, u8:0xC2, u8:0xFF, u8:0xFF, + u8:0xC0, u8:0x25, u8:0x1D, u8:0x49, u8:0x6E, u8:0xC2, u8:0xFF, u8:0xFF, u8:0xEE, u8:0x06, u8:0, ... ], u8[128]:[ - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x01, u8:0x12, u8:0x34, u8:0x56, u8:0, ... ], ), ( u8[32]:[ u8:15, - u8:0xC0, u8:0x25, u8:0x1D, u8:0x9B, u8:0x1E, u8:0xAD, u8:0xFE, u8:0xFF, + u8:0xC0, u8:0x25, u8:0x1D, u8:0x9B, u8:0x1E, u8:0xAD, u8:0xFE, u8:0xFF, u8:0x7F, u8:0x67, u8:0xFE, u8:0xD3, u8:0xFF, u8:0xCE, u8:0x05, u8:0, ... ], u8[128]:[ - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x10, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x30, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x50, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x01, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x02, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x04, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x10, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x30, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x50, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x01, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x02, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x04, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x06, u8:0, ... ], ), ( u8[32]:[ u8:23, - u8:0x90, u8:0x25, u8:0x49, u8:0x3A, u8:0xEB, u8:0x3B, u8:0xBD, u8:0x7E, - u8:0xD6, u8:0x5D, u8:0x3C, u8:0xB3, u8:0x66, u8:0x77, u8:0xA8, u8:0xBB, + u8:0x90, u8:0x25, u8:0x49, u8:0x3A, u8:0xEB, u8:0x3B, u8:0xBD, u8:0x7E, + u8:0xD6, u8:0x5D, u8:0x3C, u8:0xB3, u8:0x66, u8:0x77, u8:0xA8, u8:0xBB, u8:0x25, u8:0x76, u8:0xBA, u8:0xFF, u8:0x20, u8:0xA8, u8:0x01, u8:0, ... ], u8[128]:[ - u8:0x00, u8:0x10, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x02, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x30, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x04, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x50, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x06, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x70, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x08, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x01, u8:0x00, + u8:0x00, u8:0x10, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x02, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x30, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x04, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x50, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x06, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x70, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x08, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x01, u8:0x00, u8:0x00, u8:0x90, u8:0, ... ], - ), + ), ( u8[32]:[ u8:8, u8:0xF0, u8:0x39, u8:0xFF, u8:0x23, u8:0x45, u8:0x55, u8:0xCF, u8:0x99, u8:0, ... ], u8[128]:[ - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x20, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x01, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x10, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x20, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x01, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x10, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, 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u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x10, u8:0, ... ], ), ( u8[32]:[ u8:9, - u8:0xF0, u8:0x19, u8:0x03, u8:0x23, u8:0x7D, u8:0x9F, u8:0xD7, u8:0xB5, + u8:0xF0, u8:0x19, u8:0x03, u8:0x23, u8:0x7D, u8:0x9F, u8:0xD7, u8:0xB5, u8:0x06, u8:0, ... ], u8[128]:[ - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x10, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x00, u8:0x00, - u8:0x00, u8:0x00, u8:0x30, u8:0x00, - u8:0x00, u8:0x00, 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u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x01, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, + u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x00, u8:0x02, u8:0, ... ], ), diff --git a/xls/modules/zstd/literals_decoder.x b/xls/modules/zstd/literals_decoder.x index 4aab622bfd..f242d9bd68 100644 --- a/xls/modules/zstd/literals_decoder.x +++ b/xls/modules/zstd/literals_decoder.x @@ -614,14 +614,22 @@ pub proc LiteralsDecoder< HISTORY_BUFFER_SIZE_KB: u32, // AXI parameters AXI_DATA_W: u32, AXI_ADDR_W: u32, AXI_ID_W: u32, AXI_DEST_W: u32, + + HUFFMAN_WEIGHTS_DPD_RAM_ADDR_WIDTH: u32, HUFFMAN_WEIGHTS_DPD_RAM_DATA_WIDTH: u32, HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_TMP_RAM_ADDR_WIDTH: u32, HUFFMAN_WEIGHTS_TMP_RAM_DATA_WIDTH: u32, HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_WIDTH: u32, HUFFMAN_WEIGHTS_TMP2_RAM_DATA_WIDTH: u32, HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_FSE_RAM_ADDR_WIDTH: u32, HUFFMAN_WEIGHTS_FSE_RAM_DATA_WIDTH: u32, HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS: u32, + // Huffman weights memory parameters HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_ADDR_WIDTH}, HUFFMAN_WEIGHTS_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::WEIGHTS_DATA_WIDTH}, HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::WEIGHTS_NUM_PARTITIONS}, + // Huffman prescan memory parameters HUFFMAN_PRESCAN_RAM_ADDR_WIDTH: u32 = {huffman_literals_dec::PRESCAN_ADDR_WIDTH}, HUFFMAN_PRESCAN_RAM_DATA_WIDTH: u32 = {huffman_literals_dec::PRESCAN_DATA_WIDTH}, HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = {huffman_literals_dec::PRESCAN_NUM_PARTITIONS}, + // Literals buffer memory parameters LITERALS_BUFFER_RAM_ADDR_WIDTH: u32 = {parallel_rams::ram_addr_width(HISTORY_BUFFER_SIZE_KB)}, LITERALS_BUFFER_RAM_SIZE: u32 = {parallel_rams::ram_size(HISTORY_BUFFER_SIZE_KB)}, @@ -645,11 +653,32 @@ pub proc LiteralsDecoder< type HuffmanWeightsReadResp = ram::ReadResp; type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; type HuffmanPrescanReadResp = ram::ReadResp; type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; config ( @@ -678,8 +707,10 @@ pub proc LiteralsDecoder< huffman_weights_raw_axi_r_r: chan in, // AXI Huffman Weights FSE Decoder (manager) - huffman_weights_fse_axi_ar_s: chan out, - huffman_weights_fse_axi_r_r: chan in, + huffman_weights_fse_lookup_dec_axi_ar_s: chan out, + huffman_weights_fse_lookup_dec_axi_r_r: chan in, + huffman_weights_fse_decoder_dec_axi_ar_s: chan out, + huffman_weights_fse_decoder_dec_axi_r_r: chan in, // Literals Decoder control lit_ctrl_req_r: chan in, @@ -734,6 +765,26 @@ pub proc LiteralsDecoder< huffman_lit_prescan_mem_rd_resp_r: chan in, huffman_lit_prescan_mem_wr_req_s: chan out, huffman_lit_prescan_mem_wr_resp_r: chan in, + + huffman_lit_weights_dpd_rd_req_s: chan out, + huffman_lit_weights_dpd_rd_resp_r: chan in, + huffman_lit_weights_dpd_wr_req_s: chan out, + huffman_lit_weights_dpd_wr_resp_r: chan in, + + huffman_lit_weights_tmp_rd_req_s: chan out, + huffman_lit_weights_tmp_rd_resp_r: chan in, + huffman_lit_weights_tmp_wr_req_s: chan out, + huffman_lit_weights_tmp_wr_resp_r: chan in, + + huffman_lit_weights_tmp2_rd_req_s: chan out, + huffman_lit_weights_tmp2_rd_resp_r: chan in, + huffman_lit_weights_tmp2_wr_req_s: chan out, + huffman_lit_weights_tmp2_wr_resp_r: chan in, + + huffman_lit_weights_fse_rd_req_s: chan out, + huffman_lit_weights_fse_rd_resp_r: chan in, + huffman_lit_weights_fse_wr_req_s: chan out, + huffman_lit_weights_fse_wr_resp_r: chan in, ) { type HeaderReq = literals_block_header_dec::LiteralsHeaderDecoderReq; type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; @@ -798,6 +849,10 @@ pub proc LiteralsDecoder< spawn huffman_literals_dec::HuffmanLiteralsDecoder< AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W, + HUFFMAN_WEIGHTS_DPD_RAM_ADDR_WIDTH, HUFFMAN_WEIGHTS_DPD_RAM_DATA_WIDTH, HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_TMP_RAM_ADDR_WIDTH, HUFFMAN_WEIGHTS_TMP_RAM_DATA_WIDTH, HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_WIDTH, HUFFMAN_WEIGHTS_TMP2_RAM_DATA_WIDTH, HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_FSE_RAM_ADDR_WIDTH, HUFFMAN_WEIGHTS_FSE_RAM_DATA_WIDTH, HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS, HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH, HUFFMAN_WEIGHTS_RAM_DATA_WIDTH, HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS, HUFFMAN_PRESCAN_RAM_ADDR_WIDTH, HUFFMAN_PRESCAN_RAM_DATA_WIDTH, HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS >( @@ -806,11 +861,20 @@ pub proc LiteralsDecoder< huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, - huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + huffman_weights_fse_lookup_dec_axi_ar_s, huffman_weights_fse_lookup_dec_axi_r_r, + huffman_weights_fse_decoder_dec_axi_ar_s, huffman_weights_fse_decoder_dec_axi_r_r, huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, ); // Literals Buffer @@ -856,10 +920,42 @@ const INST_AXI_DEST_W:u32 = u32:4; const INST_HUFFMAN_WEIGHTS_RAM_ADDR_WIDTH = huffman_literals_dec::INST_WEIGHTS_RAM_ADDR_WIDTH; const INST_HUFFMAN_WEIGHTS_RAM_DATA_WIDTH = huffman_literals_dec::INST_WEIGHTS_RAM_DATA_WIDTH; const INST_HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS = huffman_literals_dec::INST_WEIGHTS_RAM_NUM_PARTITIONS; + const INST_HUFFMAN_PRESCAN_RAM_ADDR_WIDTH = huffman_literals_dec::INST_PRESCAN_RAM_ADDR_WIDTH; const INST_HUFFMAN_PRESCAN_RAM_DATA_WIDTH = huffman_literals_dec::INST_PRESCAN_RAM_DATA_WIDTH; const INST_HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS = huffman_literals_dec::INST_PRESCAN_RAM_NUM_PARTITIONS; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_WIDTH = u32:16; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE = u32:256; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_WIDTH = std::clog2(INST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_WIDTH; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_WIDTH +); +const INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_WIDTH = u32:32; +const INST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE = u32:256; +const INST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_WIDTH = std::clog2(INST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_WIDTH / u32:3; +const INST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_WIDTH +); + +const INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_WIDTH = u32:16; +const INST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE = u32:256; +const INST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_WIDTH = std::clog2(INST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_WIDTH; +const INST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_WIDTH +); + +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_WIDTH = u32:8; +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE = u32:512; +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_WIDTH = std::clog2(INST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_WIDTH; +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_WIDTH +); + proc LiteralsDecoderInst { type ReadReq = ram::ReadReq; type ReadResp = ram::ReadResp; @@ -877,11 +973,32 @@ proc LiteralsDecoderInst { type HuffmanWeightsReadResp = ram::ReadResp; type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; - type HuffmanPrescanReadReq = ram::ReadReq; + + type HuffmanPrescanReadReq = ram::ReadReq; type HuffmanPrescanReadResp = ram::ReadResp; type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; + type HeaderResp = literals_block_header_dec::LiteralsHeaderDecoderResp; config ( @@ -901,7 +1018,7 @@ proc LiteralsDecoderInst { huffman_jump_table_axi_ar_s: chan out, huffman_jump_table_axi_r_r: chan in, - // AXI Huffman Weights header Decoder (manager) + // AXI Huffman Weights Header Decoder (manager) huffman_weights_header_axi_ar_s: chan out, huffman_weights_header_axi_r_r: chan in, @@ -910,8 +1027,10 @@ proc LiteralsDecoderInst { huffman_weights_raw_axi_r_r: chan in, // AXI Huffman Weights FSE Decoder (manager) - huffman_weights_fse_axi_ar_s: chan out, - huffman_weights_fse_axi_r_r: chan in, + huffman_weights_fse_lookup_dec_axi_ar_s: chan out, + huffman_weights_fse_lookup_dec_axi_r_r: chan in, + huffman_weights_fse_decoder_dec_axi_ar_s: chan out, + huffman_weights_fse_decoder_dec_axi_r_r: chan in, // Literals Decoder control lit_ctrl_req_r: chan in, @@ -922,6 +1041,7 @@ proc LiteralsDecoderInst { lit_buf_ctrl_r: chan in, lit_buf_out_s: chan out, + // Internal memory rd_req_m0_s: chan out, rd_req_m1_s: chan out, rd_req_m2_s: chan out, @@ -964,22 +1084,59 @@ proc LiteralsDecoderInst { huffman_lit_prescan_mem_rd_req_s: chan out, huffman_lit_prescan_mem_rd_resp_r: chan in, huffman_lit_prescan_mem_wr_req_s: chan out, - huffman_lit_prescan_mem_wr_resp_r: chan in + huffman_lit_prescan_mem_wr_resp_r: chan in, + + huffman_lit_weights_dpd_rd_req_s: chan out, + huffman_lit_weights_dpd_rd_resp_r: chan in, + huffman_lit_weights_dpd_wr_req_s: chan out, + huffman_lit_weights_dpd_wr_resp_r: chan in, + + huffman_lit_weights_tmp_rd_req_s: chan out, + huffman_lit_weights_tmp_rd_resp_r: chan in, + huffman_lit_weights_tmp_wr_req_s: chan out, + huffman_lit_weights_tmp_wr_resp_r: chan in, + + huffman_lit_weights_tmp2_rd_req_s: chan out, + huffman_lit_weights_tmp2_rd_resp_r: chan in, + huffman_lit_weights_tmp2_wr_req_s: chan out, + huffman_lit_weights_tmp2_wr_resp_r: chan in, + + huffman_lit_weights_fse_rd_req_s: chan out, + huffman_lit_weights_fse_rd_resp_r: chan in, + huffman_lit_weights_fse_wr_req_s: chan out, + huffman_lit_weights_fse_wr_resp_r: chan in, ) { - spawn LiteralsDecoder ( + > ( + // AXI Literals Header Decoder (manager) lit_header_axi_ar_s, lit_header_axi_r_r, + // AXI Raw Literals Decoder (manager) raw_lit_axi_ar_s, raw_lit_axi_r_r, + // AXI Huffman Literals Decoder (manager) huffman_lit_axi_ar_s, huffman_lit_axi_r_r, + // AXI Huffman Jump Table Decoder (manager) huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, + // AXI Huffman Weights Header Decoder (manager) huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, + // AXI Huffman Weights RAW Decoder (manager) huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, - huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + // AXI Huffman Weights FSE Decoder (manager) + huffman_weights_fse_lookup_dec_axi_ar_s, huffman_weights_fse_lookup_dec_axi_r_r, + huffman_weights_fse_decoder_dec_axi_ar_s, huffman_weights_fse_decoder_dec_axi_r_r, + // Literals Decoder control lit_ctrl_req_r, lit_ctrl_resp_s, lit_ctrl_header_s, + // Literals Decoder output control lit_buf_ctrl_r, lit_buf_out_s, + // Internal memory rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s, rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s, rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r, @@ -988,10 +1145,24 @@ proc LiteralsDecoderInst { wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s, wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r, wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r, + // Huffman weights memory huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, + // Huffman prescan memory huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, ); } @@ -1053,6 +1224,46 @@ const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::Sim const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_INITIALIZED = true; const TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ASSERT_VALID_READ = true; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_DATA_WIDTH = u32:16; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_ADDR_WIDTH = std::clog2(TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_SIZE); +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_DATA_WIDTH; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_DATA_WIDTH); +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_INITIALIZED = true; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_ASSERT_VALID_READ = true; + +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_DATA_WIDTH = u32:32; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_ADDR_WIDTH = std::clog2(TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_SIZE); +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_DATA_WIDTH / u32:3; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_DATA_WIDTH); +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_INITIALIZED = true; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_ASSERT_VALID_READ = true; + +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_DATA_WIDTH = u32:16; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_ADDR_WIDTH = std::clog2(TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_SIZE); +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_DATA_WIDTH; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_DATA_WIDTH); +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_INITIALIZED = true; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_ASSERT_VALID_READ = true; + +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_DATA_WIDTH = u32:8; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_SIZE = u32:512; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_ADDR_WIDTH = std::clog2(TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_SIZE); +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_DATA_WIDTH; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_DATA_WIDTH); +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR = ram::SimultaneousReadWriteBehavior::READ_BEFORE_WRITE; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_INITIALIZED = true; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_ASSERT_VALID_READ = true; + #[test_proc] proc LiteralsDecoder_test { // LiteralsBuffer internal memory @@ -1083,6 +1294,26 @@ proc LiteralsDecoder_test { type HuffmanPrescanRamWrReq = ram::WriteReq; type HuffmanPrescanRamWrResp = ram::WriteResp; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; + // Control and output type CtrlReq = LiteralsDecoderCtrlReq; type CtrlResp = LiteralsDecoderCtrlResp; @@ -1124,8 +1355,10 @@ proc LiteralsDecoder_test { ram_wr_resp_huffman_weights_header_r : chan in; ram_wr_req_huffman_weights_raw_s : chan out; ram_wr_resp_huffman_weights_raw_r : chan in; - ram_wr_req_huffman_weights_fse_s : chan out; - ram_wr_resp_huffman_weights_fse_r : chan in; + ram_wr_req_huffman_weights_fse_lookup_dec_s : chan out; + ram_wr_resp_huffman_weights_fse_lookup_dec_r : chan in; + ram_wr_req_huffman_weights_fse_decoder_dec_s : chan out; + ram_wr_resp_huffman_weights_fse_decoder_dec_r : chan in; config (terminator: chan out) { let (lit_header_axi_ar_s, lit_header_axi_ar_r) = chan("lit_header_axi_ar"); @@ -1136,18 +1369,26 @@ proc LiteralsDecoder_test { let (huffman_lit_axi_ar_s, huffman_lit_axi_ar_r) = chan("huffman_lit_axi_ar"); let (huffman_lit_axi_r_s, huffman_lit_axi_r_r) = chan("huffman_lit_axi_r"); + let (huffman_jump_table_axi_ar_s, huffman_jump_table_axi_ar_r) = chan("huffman_jump_table_axi_ar"); let (huffman_jump_table_axi_r_s, huffman_jump_table_axi_r_r) = chan("huffman_jump_table_axi_r"); + let (huffman_weights_header_axi_ar_s, huffman_weights_header_axi_ar_r) = chan("huffman_weights_header_axi_ar"); let (huffman_weights_header_axi_r_s, huffman_weights_header_axi_r_r) = chan("huffman_weights_header_axi_r"); + let (huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_ar_r) = chan("huffman_weights_raw_axi_ar"); let (huffman_weights_raw_axi_r_s, huffman_weights_raw_axi_r_r) = chan("huffman_weights_raw_axi_r"); - let (huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_ar_r) = chan("huffman_weights_fse_axi_ar"); - let (huffman_weights_fse_axi_r_s, huffman_weights_fse_axi_r_r) = chan("huffman_weights_fse_axi_r"); + + let (huffman_weights_fse_lookup_dec_axi_ar_s, huffman_weights_fse_lookup_dec_axi_ar_r) = chan("huffman_weights_fse_lookup_dec_axi_ar"); + let (huffman_weights_fse_lookup_dec_axi_r_s, huffman_weights_fse_lookup_dec_axi_r_r) = chan("huffman_weights_fse_lookup_dec_axi_r_r"); + + let (huffman_weights_fse_decoder_dec_axi_ar_s, huffman_weights_fse_decoder_dec_axi_ar_r) = chan("huffman_weights_fse_decoder_dec_axi_ar"); + let (huffman_weights_fse_decoder_dec_axi_r_s, huffman_weights_fse_decoder_dec_axi_r_r) = chan("huffman_weights_fse_decoder_dec_axi_r"); let (ctrl_req_s, ctrl_req_r) = chan("ctrl_req"); let (ctrl_resp_s, ctrl_resp_r) = chan("ctrl_resp"); let (ctrl_header_s, ctrl_header_r) = chan("ctrl_header"); + let (buf_ctrl_s, buf_ctrl_r) = chan("buf_ctrl"); let (buf_out_s, buf_out_r) = chan("buf_out"); @@ -1169,12 +1410,35 @@ proc LiteralsDecoder_test { let (huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); let (huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + let (huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_req_r) = chan("huffman_lit_weights_dpd_rd_req"); + let (huffman_lit_weights_dpd_rd_resp_s, huffman_lit_weights_dpd_rd_resp_r) = chan("huffman_lit_weights_dpd_rd_resp"); + let (huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_req_r) = chan("huffman_lit_weights_dpd_wr_req"); + let (huffman_lit_weights_dpd_wr_resp_s, huffman_lit_weights_dpd_wr_resp_r) = chan("huffman_lit_weights_dpd_wr_resp"); + + let (huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_req_r) = chan("huffman_lit_weights_tmp_rd_req"); + let (huffman_lit_weights_tmp_rd_resp_s, huffman_lit_weights_tmp_rd_resp_r) = chan("huffman_lit_weights_tmp_rd_resp"); + let (huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_req_r) = chan("huffman_lit_weights_tmp_wr_req"); + let (huffman_lit_weights_tmp_wr_resp_s, huffman_lit_weights_tmp_wr_resp_r) = chan("huffman_lit_weights_tmp_wr_resp"); + + let (huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_req_r) = chan("huffman_lit_weights_tmp2_rd_req"); + let (huffman_lit_weights_tmp2_rd_resp_s, huffman_lit_weights_tmp2_rd_resp_r) = chan("huffman_lit_weights_tmp2_rd_resp"); + let (huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_req_r) = chan("huffman_lit_weights_tmp2_wr_req"); + let (huffman_lit_weights_tmp2_wr_resp_s, huffman_lit_weights_tmp2_wr_resp_r) = chan("huffman_lit_weights_tmp2_wr_resp"); + + let (huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_req_r) = chan("huffman_lit_weights_fse_rd_req"); + let (huffman_lit_weights_fse_rd_resp_s, huffman_lit_weights_fse_rd_resp_r) = chan("huffman_lit_weights_fse_rd_resp"); + let (huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_req_r) = chan("huffman_lit_weights_fse_wr_req"); + let (huffman_lit_weights_fse_wr_resp_s, huffman_lit_weights_fse_wr_resp_r) = chan("huffman_lit_weights_fse_wr_resp"); + spawn LiteralsDecoder< TEST_HISTORY_BUFFER_SIZE_KB, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_DEST_W, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_NUM_PARTITIONS, TEST_HUFFMAN_WEIGHTS_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_WEIGHTS_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_WEIGHTS_RAM_MODEL_NUM_PARTITIONS, TEST_HUFFMAN_PRESCAN_RAM_MODEL_ADDR_WIDTH, TEST_HUFFMAN_PRESCAN_RAM_MODEL_DATA_WIDTH, TEST_HUFFMAN_PRESCAN_RAM_MODEL_NUM_PARTITIONS, - TEST_LITERALS_BUFFER_RAM_MODEL_ADDR_WIDTH, TEST_LITERALS_BUFFER_RAM_MODEL_SIZE, TEST_LITERALS_BUFFER_RAM_MODEL_DATA_WIDTH, TEST_LITERALS_BUFFER_RAM_MODEL_NUM_PARTITIONS > ( lit_header_axi_ar_s, lit_header_axi_r_r, raw_lit_axi_ar_s, raw_lit_axi_r_r, @@ -1182,7 +1446,8 @@ proc LiteralsDecoder_test { huffman_jump_table_axi_ar_s, huffman_jump_table_axi_r_r, huffman_weights_header_axi_ar_s, huffman_weights_header_axi_r_r, huffman_weights_raw_axi_ar_s, huffman_weights_raw_axi_r_r, - huffman_weights_fse_axi_ar_s, huffman_weights_fse_axi_r_r, + huffman_weights_fse_lookup_dec_axi_ar_s, huffman_weights_fse_lookup_dec_axi_r_r, + huffman_weights_fse_decoder_dec_axi_ar_s, huffman_weights_fse_decoder_dec_axi_r_r, ctrl_req_r, ctrl_resp_s, ctrl_header_s, buf_ctrl_r, buf_out_s, ram_rd_req_s[0], ram_rd_req_s[1], ram_rd_req_s[2], ram_rd_req_s[3], @@ -1197,6 +1462,14 @@ proc LiteralsDecoder_test { huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, ); spawn ram_printer::RamPrinter< @@ -1438,11 +1711,11 @@ proc LiteralsDecoder_test { ram_rd_req_huffman_weights_raw_s, ram_rd_resp_huffman_weights_raw_r ); - // Mock RAM for HuffmanWeights fse decoder MemReader - let (ram_rd_req_huffman_weights_fse_s, ram_rd_req_huffman_weights_fse_r) = chan("ram_rd_req_huffman_weights_fse"); - let (ram_rd_resp_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r) = chan("ram_rd_resp_huffman_weights_fse"); - let (ram_wr_req_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r) = chan("ram_wr_req_huffman_weights_fse"); - let (ram_wr_resp_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r) = chan("ram_wr_resp_huffman_weights_fse"); + // Mock RAM for HuffmanWeights FseLookupDecoder MemReader + let (ram_rd_req_huffman_weights_fse_lookup_dec_s, ram_rd_req_huffman_weights_fse_lookup_dec_r) = chan("ram_rd_req_huffman_weights_fse_lookup_dec"); + let (ram_rd_resp_huffman_weights_fse_lookup_dec_s, ram_rd_resp_huffman_weights_fse_lookup_dec_r) = chan("ram_rd_resp_huffman_weights_fse_lookup_dec"); + let (ram_wr_req_huffman_weights_fse_lookup_dec_s, ram_wr_req_huffman_weights_fse_lookup_dec_r) = chan("ram_wr_req_huffman_weights_fse_lookup_dec"); + let (ram_wr_resp_huffman_weights_fse_lookup_dec_s, ram_wr_resp_huffman_weights_fse_lookup_dec_r) = chan("ram_wr_resp_huffman_weights_fse_lookup_dec"); spawn ram::RamModel< TEST_AXI_RAM_MODEL_DATA_WIDTH, @@ -1453,15 +1726,43 @@ proc LiteralsDecoder_test { TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( - ram_rd_req_huffman_weights_fse_r, ram_rd_resp_huffman_weights_fse_s, ram_wr_req_huffman_weights_fse_r, ram_wr_resp_huffman_weights_fse_s + ram_rd_req_huffman_weights_fse_lookup_dec_r, ram_rd_resp_huffman_weights_fse_lookup_dec_s, + ram_wr_req_huffman_weights_fse_lookup_dec_r, ram_wr_resp_huffman_weights_fse_lookup_dec_s ); spawn axi_ram::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( - huffman_weights_fse_axi_ar_r, huffman_weights_fse_axi_r_s, - ram_rd_req_huffman_weights_fse_s, ram_rd_resp_huffman_weights_fse_r + huffman_weights_fse_lookup_dec_axi_ar_r, huffman_weights_fse_lookup_dec_axi_r_s, + ram_rd_req_huffman_weights_fse_lookup_dec_s, ram_rd_resp_huffman_weights_fse_lookup_dec_r + ); + + // Mock RAM for HuffmanWeights FseDecoder MemReader + let (ram_rd_req_huffman_weights_fse_decoder_dec_s, ram_rd_req_huffman_weights_fse_decoder_dec_r) = chan("ram_rd_req_huffman_weights_fse_decoder_dec"); + let (ram_rd_resp_huffman_weights_fse_decoder_dec_s, ram_rd_resp_huffman_weights_fse_decoder_dec_r) = chan("ram_rd_resp_huffman_weights_fse_decoder_dec"); + let (ram_wr_req_huffman_weights_fse_decoder_dec_s, ram_wr_req_huffman_weights_fse_decoder_dec_r) = chan("ram_wr_req_huffman_weights_fse_decoder_dec"); + let (ram_wr_resp_huffman_weights_fse_decoder_dec_s, ram_wr_resp_huffman_weights_fse_decoder_dec_r) = chan("ram_wr_resp_huffman_weights_fse_decoder_dec"); + + spawn ram::RamModel< + TEST_AXI_RAM_MODEL_DATA_WIDTH, + TEST_AXI_RAM_MODEL_SIZE, + TEST_AXI_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_AXI_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_AXI_RAM_MODEL_INITIALIZED, + TEST_AXI_RAM_MODEL_ASSERT_VALID_READ, + TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + ram_rd_req_huffman_weights_fse_decoder_dec_r, ram_rd_resp_huffman_weights_fse_decoder_dec_s, + ram_wr_req_huffman_weights_fse_decoder_dec_r, ram_wr_resp_huffman_weights_fse_decoder_dec_s + ); + + spawn axi_ram::AxiRamReader< + TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, + TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH + > ( + huffman_weights_fse_decoder_dec_axi_ar_r, huffman_weights_fse_decoder_dec_axi_r_s, + ram_rd_req_huffman_weights_fse_decoder_dec_s, ram_rd_resp_huffman_weights_fse_decoder_dec_r ); // Huffman weigths memory @@ -1492,6 +1793,59 @@ proc LiteralsDecoder_test { huffman_lit_prescan_mem_wr_req_r, huffman_lit_prescan_mem_wr_resp_s ); + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_DATA_WIDTH, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_SIZE, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_INITIALIZED, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_ASSERT_VALID_READ, + TEST_HUFFMAN_WEIGHTS_DPD_RAM_MODEL_ADDR_WIDTH + > ( + huffman_lit_weights_dpd_rd_req_r, huffman_lit_weights_dpd_rd_resp_s, + huffman_lit_weights_dpd_wr_req_r, huffman_lit_weights_dpd_wr_resp_s + ); + + + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_DATA_WIDTH, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_SIZE, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_INITIALIZED, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_ASSERT_VALID_READ, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_MODEL_ADDR_WIDTH + > ( + huffman_lit_weights_tmp_rd_req_r, huffman_lit_weights_tmp_rd_resp_s, + huffman_lit_weights_tmp_wr_req_r, huffman_lit_weights_tmp_wr_resp_s + ); + + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_DATA_WIDTH, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_SIZE, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_INITIALIZED, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_ASSERT_VALID_READ, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_MODEL_ADDR_WIDTH + > ( + huffman_lit_weights_tmp2_rd_req_r, huffman_lit_weights_tmp2_rd_resp_s, + huffman_lit_weights_tmp2_wr_req_r, huffman_lit_weights_tmp2_wr_resp_s + ); + + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_DATA_WIDTH, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_SIZE, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_WORD_PARTITION_SIZE, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_SIMULTANEOUS_READ_WRITE_BEHAVIOR, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_INITIALIZED, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_ASSERT_VALID_READ, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_MODEL_ADDR_WIDTH + > ( + huffman_lit_weights_fse_rd_req_r, huffman_lit_weights_fse_rd_resp_s, + huffman_lit_weights_fse_wr_req_r, huffman_lit_weights_fse_wr_resp_s + ); + ( terminator, ctrl_req_s, ctrl_resp_r, ctrl_header_r, @@ -1503,7 +1857,8 @@ proc LiteralsDecoder_test { ram_wr_req_huffman_jump_table_s, ram_wr_resp_huffman_jump_table_r, ram_wr_req_huffman_weights_header_s, ram_wr_resp_huffman_weights_header_r, ram_wr_req_huffman_weights_raw_s, ram_wr_resp_huffman_weights_raw_r, - ram_wr_req_huffman_weights_fse_s, ram_wr_resp_huffman_weights_fse_r + ram_wr_req_huffman_weights_fse_lookup_dec_s, ram_wr_resp_huffman_weights_fse_lookup_dec_r, + ram_wr_req_huffman_weights_fse_decoder_dec_s, ram_wr_resp_huffman_weights_fse_decoder_dec_r ) } @@ -1741,8 +2096,10 @@ proc LiteralsDecoder_test { let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_header_r); let tok = send(tok, ram_wr_req_huffman_weights_raw_s, mem_req); let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_raw_r); - let tok = send(tok, ram_wr_req_huffman_weights_fse_s, mem_req); - let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_r); + let tok = send(tok, ram_wr_req_huffman_weights_fse_lookup_dec_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_lookup_dec_r); + let tok = send(tok, ram_wr_req_huffman_weights_fse_decoder_dec_s, mem_req); + let (tok, _) = recv(tok, ram_wr_resp_huffman_weights_fse_decoder_dec_r); tok }(tok); diff --git a/xls/modules/zstd/zstd_dec.x b/xls/modules/zstd/zstd_dec.x index 77ddea55f6..b0c0d67a06 100644 --- a/xls/modules/zstd/zstd_dec.x +++ b/xls/modules/zstd/zstd_dec.x @@ -950,6 +950,11 @@ pub proc ZstdDecoder< TMP2_RAM_ADDR_W: u32, TMP2_RAM_DATA_W: u32, TMP2_RAM_NUM_PARTITIONS: u32, FSE_RAM_ADDR_W: u32, FSE_RAM_DATA_W: u32, FSE_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_DPD_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_TMP_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS: u32, + HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W: u32, HUFFMAN_WEIGHTS_FSE_RAM_DATA_W: u32, HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS: u32, + HISTORY_BUFFER_SIZE_KB: u32, AXI_CHAN_N: u32, @@ -1046,11 +1051,32 @@ pub proc ZstdDecoder< type HuffmanWeightsReadResp = ram::ReadResp; type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; type HuffmanPrescanReadResp = ram::ReadResp; type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; + type LitBufRamRdReq = ram::ReadReq; type LitBufRamRdResp = ram::ReadResp; type LitBufRamWrReq = ram::WriteReq; @@ -1142,7 +1168,27 @@ pub proc ZstdDecoder< huffman_lit_prescan_mem_wr_req_s: chan out, huffman_lit_prescan_mem_wr_resp_r: chan in, - //// AXI Output Writer (manager) + huffman_lit_weights_dpd_rd_req_s: chan out, + huffman_lit_weights_dpd_rd_resp_r: chan in, + huffman_lit_weights_dpd_wr_req_s: chan out, + huffman_lit_weights_dpd_wr_resp_r: chan in, + + huffman_lit_weights_tmp_rd_req_s: chan out, + huffman_lit_weights_tmp_rd_resp_r: chan in, + huffman_lit_weights_tmp_wr_req_s: chan out, + huffman_lit_weights_tmp_wr_resp_r: chan in, + + huffman_lit_weights_tmp2_rd_req_s: chan out, + huffman_lit_weights_tmp2_rd_resp_r: chan in, + huffman_lit_weights_tmp2_wr_req_s: chan out, + huffman_lit_weights_tmp2_wr_resp_r: chan in, + + huffman_lit_weights_fse_rd_req_s: chan out, + huffman_lit_weights_fse_rd_resp_r: chan in, + huffman_lit_weights_fse_wr_req_s: chan out, + huffman_lit_weights_fse_wr_resp_r: chan in, + + // AXI Output Writer (manager) output_axi_aw_s: chan out, output_axi_w_s: chan out, output_axi_b_r: chan in, @@ -1294,11 +1340,16 @@ pub proc ZstdDecoder< spawn comp_block_dec::CompressBlockDecoder< AXI_DATA_W, AXI_ADDR_W, AXI_ID_W, AXI_DEST_W, - // FSE lookup table RAMs + DPD_RAM_ADDR_W, DPD_RAM_DATA_W, DPD_RAM_NUM_PARTITIONS, TMP_RAM_ADDR_W, TMP_RAM_DATA_W, TMP_RAM_NUM_PARTITIONS, TMP2_RAM_ADDR_W, TMP2_RAM_DATA_W, TMP2_RAM_NUM_PARTITIONS, FSE_RAM_ADDR_W, FSE_RAM_DATA_W, FSE_RAM_NUM_PARTITIONS, + + HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W, HUFFMAN_WEIGHTS_DPD_RAM_DATA_W, HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W, HUFFMAN_WEIGHTS_TMP_RAM_DATA_W, HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W, HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W, HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W, HUFFMAN_WEIGHTS_FSE_RAM_DATA_W, HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS, >( // MAIN IOs @@ -1331,6 +1382,7 @@ pub proc ZstdDecoder< comp_axi_ram_ar_s[7], comp_axi_ram_r_r[7], comp_axi_ram_ar_s[8], comp_axi_ram_r_r[8], comp_axi_ram_ar_s[9], comp_axi_ram_r_r[9], + comp_axi_ram_ar_s[10], comp_axi_ram_r_r[10], litbuf_rd_req_s[0], litbuf_rd_req_s[1], litbuf_rd_req_s[2], litbuf_rd_req_s[3], litbuf_rd_req_s[4], litbuf_rd_req_s[5], litbuf_rd_req_s[6], litbuf_rd_req_s[7], litbuf_rd_resp_r[0], litbuf_rd_resp_r[1], litbuf_rd_resp_r[2], litbuf_rd_resp_r[3], @@ -1343,6 +1395,14 @@ pub proc ZstdDecoder< huffman_lit_weights_write_side_wr_req_s, huffman_lit_weights_write_side_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, ); spawn ram_merge::RamMerge( @@ -1401,34 +1461,6 @@ pub proc ZstdDecoder< notify_s, reset_s, ); - - // // Sequence config (section header) decoder's memory reader - // let (scd_mem_rd_req_s, scd_mem_rd_req_r) = chan("scd_mem_rd_req"); - // let (scd_mem_rd_resp_s, scd_mem_rd_resp_r) = chan("scd_mem_rd_resp"); - - // spawn mem_reader::MemReader( - // scd_mem_rd_req_r, scd_mem_rd_resp_s, - // scd_axi_ar_s, scd_axi_r_r, - // ); - - // // FSE lookup decoder's memory reader for RefillingShiftBuffer - // let (fse_lookup_mem_rd_req_s, fse_lookup_mem_rd_req_r) = chan("fse_lookup_mem_rd_req"); - // let (fse_lookup_mem_rd_resp_s, fse_lookup_mem_rd_resp_r) = chan("fse_lookup_mem_rd_resp"); - - // spawn mem_reader::MemReader( - // fse_lookup_mem_rd_req_r, fse_lookup_mem_rd_resp_s, - // fse_lookup_axi_ar_s, fse_lookup_axi_r_r, - // ); - - // // FSE decoder's memory reader for RefillingShiftBuffer - // let (fse_dec_mem_rd_req_s, fse_dec_mem_rd_req_r) = chan("scd_mem_rd_req"); - // let (fse_dec_mem_rd_resp_s, fse_dec_mem_rd_resp_r) = chan("scd_mem_rd_resp"); - - // spawn mem_reader::MemReader( - // fse_dec_mem_rd_req_r, fse_dec_mem_rd_resp_s, - // fse_dec_axi_ar_s, fse_dec_axi_r_r, - // ); - () } @@ -1488,8 +1520,36 @@ const HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH const HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W = u32:16; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE = u32:256; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W = std::clog2(INST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W; +const INST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W); + +const INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W = u32:32; +const INST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE = u32:256; +const INST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W = std::clog2(INST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W; +const INST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W); + +const INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W = u32:16; +const INST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE = u32:256; +const INST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W = std::clog2(INST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W; +const INST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W); + +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W = u32:8; +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE = u32:512; +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W = std::clog2(INST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE); +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE = INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W; +const INST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + INST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W); + const INST_HISTORY_BUFFER_SIZE_KB = u32:64; -const INST_AXI_CHAN_N = u32:10; +const INST_AXI_CHAN_N = u32:11; // Literals buffer memory parameters const LITERALS_BUFFER_RAM_ADDR_W: u32 = parallel_rams::ram_addr_width(INST_HISTORY_BUFFER_SIZE_KB); @@ -1632,12 +1692,31 @@ proc ZstdDecoderInst { type HuffmanWeightsReadResp = ram::ReadResp; type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; + type HuffmanPrescanReadReq = ram::ReadReq; type HuffmanPrescanReadResp = ram::ReadResp; type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; - const CHANNEL_DEPTH = u32:1; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; init { } @@ -1695,7 +1774,27 @@ proc ZstdDecoderInst { huffman_lit_prescan_mem_wr_req_s: chan out, huffman_lit_prescan_mem_wr_resp_r: chan in, - //// AXI Output Writer (manager) + huffman_lit_weights_dpd_rd_req_s: chan out, + huffman_lit_weights_dpd_rd_resp_r: chan in, + huffman_lit_weights_dpd_wr_req_s: chan out, + huffman_lit_weights_dpd_wr_resp_r: chan in, + + huffman_lit_weights_tmp_rd_req_s: chan out, + huffman_lit_weights_tmp_rd_resp_r: chan in, + huffman_lit_weights_tmp_wr_req_s: chan out, + huffman_lit_weights_tmp_wr_resp_r: chan in, + + huffman_lit_weights_tmp2_rd_req_s: chan out, + huffman_lit_weights_tmp2_rd_resp_r: chan in, + huffman_lit_weights_tmp2_wr_req_s: chan out, + huffman_lit_weights_tmp2_wr_resp_r: chan in, + + huffman_lit_weights_fse_rd_req_s: chan out, + huffman_lit_weights_fse_rd_resp_r: chan in, + huffman_lit_weights_fse_wr_req_s: chan out, + huffman_lit_weights_fse_wr_resp_r: chan in, + + // AXI Output Writer (manager) output_axi_aw_s: chan out, output_axi_w_s: chan out, output_axi_b_r: chan in, @@ -1738,10 +1837,11 @@ proc ZstdDecoderInst { reset_s: chan<()> out, ) { // FIXME: Remove inline Huffman Weights memory once HuffmanLiteralsDecoder's memory ports are able to be rewritten - let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); - let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); - let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); - let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); + let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); + let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); + let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + spawn ram::RamModel< HUFFMAN_WEIGHTS_RAM_DATA_W, HUFFMAN_WEIGHTS_RAM_SIZE, HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE, INST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, INST_RAM_INITIALIZED @@ -1754,10 +1854,17 @@ proc ZstdDecoderInst { INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_AXI_ID_W, INST_AXI_DEST_W, INST_REGS_N, INST_WINDOW_LOG_MAX, INST_HB_ADDR_W, INST_HB_DATA_W, INST_HB_NUM_PARTITIONS, INST_HB_SIZE_KB, + INST_DPD_RAM_ADDR_W, INST_DPD_RAM_DATA_W, INST_DPD_RAM_NUM_PARTITIONS, INST_TMP_RAM_ADDR_W, INST_TMP_RAM_DATA_W, INST_TMP_RAM_NUM_PARTITIONS, INST_TMP2_RAM_ADDR_W, INST_TMP2_RAM_DATA_W, INST_TMP2_RAM_NUM_PARTITIONS, INST_FSE_RAM_ADDR_W, INST_FSE_RAM_DATA_W, INST_FSE_RAM_NUM_PARTITIONS, + + INST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W, INST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W, INST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + INST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W, INST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W, INST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + INST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W, INST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W, INST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + INST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W, INST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W, INST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS, + INST_HISTORY_BUFFER_SIZE_KB, INST_AXI_CHAN_N, >( @@ -1782,6 +1889,14 @@ proc ZstdDecoderInst { huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, output_axi_aw_s, output_axi_w_s, output_axi_b_r, ram_rd_req_0_s, ram_rd_req_1_s, ram_rd_req_2_s, ram_rd_req_3_s, ram_rd_req_4_s, ram_rd_req_5_s, ram_rd_req_6_s, ram_rd_req_7_s, diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 52306111ce..a47531ca34 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -94,18 +94,46 @@ const TEST_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( TEST_TMP2_RAM_WORD_PARTITION_SIZE, TEST_TMP2_RAM_DATA_W); // Huffman weights memory parameters -const HUFFMAN_WEIGHTS_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; -const HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; -const HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; -const HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE: u32 = huffman_literals_dec::WEIGHTS_PARTITION_WORD_SIZE; -const HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; +const TEST_HUFFMAN_WEIGHTS_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; +const TEST_HUFFMAN_WEIGHTS_RAM_ADDR_W: u32 = huffman_literals_dec::WEIGHTS_ADDR_WIDTH; +const TEST_HUFFMAN_WEIGHTS_RAM_DATA_W: u32 = huffman_literals_dec::WEIGHTS_DATA_WIDTH; +const TEST_HUFFMAN_WEIGHTS_RAM_WORD_PARTITION_SIZE: u32 = huffman_literals_dec::WEIGHTS_PARTITION_WORD_SIZE; +const TEST_HUFFMAN_WEIGHTS_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::WEIGHTS_NUM_PARTITIONS; // Huffman prescan memory parameters -const HUFFMAN_PRESCAN_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; -const HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; -const HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; -const HUFFMAN_PRESCAN_RAM_PARTITION_WORD_SIZE: u32 = huffman_literals_dec::PRESCAN_PARTITION_WORD_SIZE; -const HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; +const TEST_HUFFMAN_PRESCAN_RAM_SIZE: u32 = huffman_literals_dec::RAM_SIZE; +const TEST_HUFFMAN_PRESCAN_RAM_ADDR_W: u32 = huffman_literals_dec::PRESCAN_ADDR_WIDTH; +const TEST_HUFFMAN_PRESCAN_RAM_DATA_W: u32 = huffman_literals_dec::PRESCAN_DATA_WIDTH; +const TEST_HUFFMAN_PRESCAN_RAM_WORD_PARTITION_SIZE: u32 = huffman_literals_dec::PRESCAN_PARTITION_WORD_SIZE; +const TEST_HUFFMAN_PRESCAN_RAM_NUM_PARTITIONS: u32 = huffman_literals_dec::PRESCAN_NUM_PARTITIONS; + +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W = u32:16; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W = u32:32; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE = u32:1 << common::FSE_MAX_ACCURACY_LOG; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W = u32:16; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE = u32:256; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W); + +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W = u32:8; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE = u32:512; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W = std::clog2(TEST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE); +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE = TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W; +const TEST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS = ram::num_partitions( + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W); const HISTORY_BUFFER_SIZE_KB = common::HISTORY_BUFFER_SIZE_KB; @@ -116,7 +144,7 @@ const LITERALS_BUFFER_RAM_DATA_W: u32 = literals_buffer::RAM_DATA_WIDTH; const LITERALS_BUFFER_RAM_NUM_PARTITIONS: u32 = literals_buffer::RAM_NUM_PARTITIONS; const LITERALS_BUFFER_RAM_WORD_PARTITION_SIZE: u32 = LITERALS_BUFFER_RAM_DATA_W; -const AXI_CHAN_N = u32:10; +const AXI_CHAN_N = u32:11; const TEST_MOCK_OUTPUT_RAM_SIZE:u32 = TEST_RAM_SIZE; @@ -194,15 +222,36 @@ proc ZstdDecoderTest { type SequenceExecutorPacket = common::SequenceExecutorPacket; type CommandConstructorData = common::CommandConstructorData; - type HuffmanWeightsReadReq = ram::ReadReq; - type HuffmanWeightsReadResp = ram::ReadResp; - type HuffmanWeightsWriteReq = ram::WriteReq; + type HuffmanWeightsReadReq = ram::ReadReq; + type HuffmanWeightsReadResp = ram::ReadResp; + type HuffmanWeightsWriteReq = ram::WriteReq; type HuffmanWeightsWriteResp = ram::WriteResp; - type HuffmanPrescanReadReq = ram::ReadReq; - type HuffmanPrescanReadResp = ram::ReadResp; - type HuffmanPrescanWriteReq = ram::WriteReq; + + type HuffmanPrescanReadReq = ram::ReadReq; + type HuffmanPrescanReadResp = ram::ReadResp; + type HuffmanPrescanWriteReq = ram::WriteReq; type HuffmanPrescanWriteResp = ram::WriteResp; + type HuffmanWeightsDpdRamRdReq = ram::ReadReq; + type HuffmanWeightsDpdRamRdResp = ram::ReadResp; + type HuffmanWeightsDpdRamWrReq = ram::WriteReq; + type HuffmanWeightsDpdRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmpRamRdReq = ram::ReadReq; + type HuffmanWeightsTmpRamRdResp = ram::ReadResp; + type HuffmanWeightsTmpRamWrReq = ram::WriteReq; + type HuffmanWeightsTmpRamWrResp = ram::WriteResp; + + type HuffmanWeightsTmp2RamRdReq = ram::ReadReq; + type HuffmanWeightsTmp2RamRdResp = ram::ReadResp; + type HuffmanWeightsTmp2RamWrReq = ram::WriteReq; + type HuffmanWeightsTmp2RamWrResp = ram::WriteResp; + + type HuffmanWeightsFseRamRdReq = ram::ReadReq; + type HuffmanWeightsFseRamRdResp = ram::ReadResp; + type HuffmanWeightsFseRamWrReq = ram::WriteReq; + type HuffmanWeightsFseRamWrResp = ram::WriteResp; + type LitBufRamRdReq = ram::ReadReq; type LitBufRamRdResp = ram::ReadResp; type LitBufRamWrReq = ram::WriteReq; @@ -308,31 +357,83 @@ proc ZstdDecoderTest { let (reset_s, reset_r) = chan<()>("reset"); // Huffman weights memory - let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); - let (huffman_lit_weights_mem_rd_resp_s, huffman_lit_weights_mem_rd_resp_r) = chan("huffman_lit_weights_mem_rd_resp"); - let (huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_req_r) = chan("huffman_lit_weights_mem_wr_req"); - let (huffman_lit_weights_mem_wr_resp_s, huffman_lit_weights_mem_wr_resp_r) = chan("huffman_lit_weights_mem_wr_resp"); + let (huffman_lit_weights_rd_req_s, huffman_lit_weights_rd_req_r) = chan("huffman_lit_weights_rd_req"); + let (huffman_lit_weights_rd_resp_s, huffman_lit_weights_rd_resp_r) = chan("huffman_lit_weights_rd_resp"); + let (huffman_lit_weights_wr_req_s, huffman_lit_weights_wr_req_r) = chan("huffman_lit_weights_wr_req"); + let (huffman_lit_weights_wr_resp_s, huffman_lit_weights_wr_resp_r) = chan("huffman_lit_weights_wr_resp"); spawn ram::RamModel< - HUFFMAN_WEIGHTS_RAM_DATA_W, HUFFMAN_WEIGHTS_RAM_SIZE, HUFFMAN_WEIGHTS_RAM_PARTITION_WORD_SIZE, + TEST_HUFFMAN_WEIGHTS_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_RAM_SIZE, TEST_HUFFMAN_WEIGHTS_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED >( - huffman_lit_weights_mem_rd_req_r, huffman_lit_weights_mem_rd_resp_s, - huffman_lit_weights_mem_wr_req_r, huffman_lit_weights_mem_wr_resp_s, + huffman_lit_weights_rd_req_r, huffman_lit_weights_rd_resp_s, + huffman_lit_weights_wr_req_r, huffman_lit_weights_wr_resp_s, ); // Huffman prescan memory - let (huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_req_r) = chan("huffman_lit_prescan_mem_rd_req"); - let (huffman_lit_prescan_mem_rd_resp_s, huffman_lit_prescan_mem_rd_resp_r) = chan("huffman_lit_prescan_mem_rd_resp"); - let (huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_req_r) = chan("huffman_lit_prescan_mem_wr_req"); - let (huffman_lit_prescan_mem_wr_resp_s, huffman_lit_prescan_mem_wr_resp_r) = chan("huffman_lit_prescan_mem_wr_resp"); + let (huffman_lit_prescan_rd_req_s, huffman_lit_prescan_rd_req_r) = chan("huffman_lit_prescan_rd_req"); + let (huffman_lit_prescan_rd_resp_s, huffman_lit_prescan_rd_resp_r) = chan("huffman_lit_prescan_rd_resp"); + let (huffman_lit_prescan_wr_req_s, huffman_lit_prescan_wr_req_r) = chan("huffman_lit_prescan_wr_req"); + let (huffman_lit_prescan_wr_resp_s, huffman_lit_prescan_wr_resp_r) = chan("huffman_lit_prescan_wr_resp"); + + spawn ram::RamModel< + TEST_HUFFMAN_PRESCAN_RAM_DATA_W, TEST_HUFFMAN_PRESCAN_RAM_SIZE, TEST_HUFFMAN_PRESCAN_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + huffman_lit_prescan_rd_req_r, huffman_lit_prescan_rd_resp_s, + huffman_lit_prescan_wr_req_r, huffman_lit_prescan_wr_resp_s, + ); + + let (huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_req_r) = chan("huffman_lit_weights_dpd_rd_req"); + let (huffman_lit_weights_dpd_rd_resp_s, huffman_lit_weights_dpd_rd_resp_r) = chan("huffman_lit_weights_dpd_rd_resp_r"); + let (huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_req_r) = chan("huffman_lit_weights_dpd_wr_req"); + let (huffman_lit_weights_dpd_wr_resp_s, huffman_lit_weights_dpd_wr_resp_r) = chan("huffman_lit_weights_dpd_wr_resp"); + + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_DPD_RAM_SIZE, TEST_HUFFMAN_WEIGHTS_DPD_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + huffman_lit_weights_dpd_rd_req_r, huffman_lit_weights_dpd_rd_resp_s, + huffman_lit_weights_dpd_wr_req_r, huffman_lit_weights_dpd_wr_resp_s, + ); + + let (huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_req_r) = chan("huffman_lit_weights_tmp_rd_req"); + let (huffman_lit_weights_tmp_rd_resp_s, huffman_lit_weights_tmp_rd_resp_r) = chan("huffman_lit_weights_tmp_rd_resp"); + let (huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_req_r) = chan("huffman_lit_weights_tmp_wr_req"); + let (huffman_lit_weights_tmp_wr_resp_s, huffman_lit_weights_tmp_wr_resp_r) = chan("huffman_lit_weights_tmp_wr_resp"); + + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_TMP_RAM_SIZE, TEST_HUFFMAN_WEIGHTS_TMP_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + huffman_lit_weights_tmp_rd_req_r, huffman_lit_weights_tmp_rd_resp_s, + huffman_lit_weights_tmp_wr_req_r, huffman_lit_weights_tmp_wr_resp_s, + ); + + let (huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_req_r) = chan("huffman_lit_weights_tmp2_rd_req"); + let (huffman_lit_weights_tmp2_rd_resp_s, huffman_lit_weights_tmp2_rd_resp_r) = chan("huffman_lit_weights_tmp2_rd_resp"); + let (huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_req_r) = chan("huffman_lit_weights_tmp2_wr_req"); + let (huffman_lit_weights_tmp2_wr_resp_s, huffman_lit_weights_tmp2_wr_resp_r) = chan("huffman_lit_weights_tmp2_wr_resp"); + + spawn ram::RamModel< + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_SIZE, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_WORD_PARTITION_SIZE, + TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED + >( + huffman_lit_weights_tmp2_rd_req_r, huffman_lit_weights_tmp2_rd_resp_s, + huffman_lit_weights_tmp2_wr_req_r, huffman_lit_weights_tmp2_wr_resp_s, + ); + + let (huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_req_r) = chan("huffman_lit_weights_fse_rd_req"); + let (huffman_lit_weights_fse_rd_resp_s, huffman_lit_weights_fse_rd_resp_r) = chan("huffman_lit_weights_fse_rd_resp_r"); + let (huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_req_r) = chan("huffman_lit_weights_fse_wr_req"); + let (huffman_lit_weights_fse_wr_resp_s, huffman_lit_weights_fse_wr_resp_r) = chan("huffman_lit_weights_fse_wr_resp"); spawn ram::RamModel< - HUFFMAN_PRESCAN_RAM_DATA_W, HUFFMAN_PRESCAN_RAM_SIZE, HUFFMAN_PRESCAN_RAM_PARTITION_WORD_SIZE, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_FSE_RAM_SIZE, TEST_HUFFMAN_WEIGHTS_FSE_RAM_WORD_PARTITION_SIZE, TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED >( - huffman_lit_prescan_mem_rd_req_r, huffman_lit_prescan_mem_rd_resp_s, - huffman_lit_prescan_mem_wr_req_r, huffman_lit_prescan_mem_wr_resp_s, + huffman_lit_weights_fse_rd_req_r, huffman_lit_weights_fse_rd_resp_s, + huffman_lit_weights_fse_wr_req_r, huffman_lit_weights_fse_wr_resp_s, ); // AXI channels for various blocks @@ -435,9 +536,7 @@ proc ZstdDecoderTest { let (ll_def_fse_wr_resp_s, ll_def_fse_wr_resp_r) = chan("ll_def_fse_wr_resp"); spawn ram_mux::RamMux< - TEST_FSE_RAM_ADDR_W, - TEST_FSE_RAM_DATA_W, - TEST_FSE_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, >( ll_sel_test_r, ll_def_test_rd_req_r, ll_def_test_rd_resp_s, ll_def_test_wr_req_r, ll_def_test_wr_resp_s, @@ -460,9 +559,7 @@ proc ZstdDecoderTest { let (ml_def_fse_wr_resp_s, ml_def_fse_wr_resp_r) = chan("ml_def_fse_wr_resp"); spawn ram_mux::RamMux< - TEST_FSE_RAM_ADDR_W, - TEST_FSE_RAM_DATA_W, - TEST_FSE_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, >( ml_sel_test_r, ml_def_test_rd_req_r, ml_def_test_rd_resp_s, ml_def_test_wr_req_r, ml_def_test_wr_resp_s, @@ -485,9 +582,7 @@ proc ZstdDecoderTest { let (of_def_fse_wr_resp_s, of_def_fse_wr_resp_r) = chan("of_def_fse_wr_resp"); spawn ram_mux::RamMux< - TEST_FSE_RAM_ADDR_W, - TEST_FSE_RAM_DATA_W, - TEST_FSE_RAM_NUM_PARTITIONS, + TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, >( of_sel_test_r, of_def_test_rd_req_r, of_def_test_rd_resp_s, of_def_test_wr_req_r, of_def_test_wr_resp_s, @@ -499,10 +594,17 @@ proc ZstdDecoderTest { TEST_AXI_DATA_W, TEST_AXI_ADDR_W, TEST_AXI_ID_W, TEST_AXI_DEST_W, TEST_REGS_N, TEST_WINDOW_LOG_MAX, TEST_HB_ADDR_W, TEST_HB_DATA_W, TEST_HB_NUM_PARTITIONS, TEST_HB_SIZE_KB, + TEST_DPD_RAM_ADDR_W, TEST_DPD_RAM_DATA_W, TEST_DPD_RAM_NUM_PARTITIONS, TEST_TMP_RAM_ADDR_W, TEST_TMP_RAM_DATA_W, TEST_TMP_RAM_NUM_PARTITIONS, TEST_TMP2_RAM_ADDR_W, TEST_TMP2_RAM_DATA_W, TEST_TMP2_RAM_NUM_PARTITIONS, TEST_FSE_RAM_ADDR_W, TEST_FSE_RAM_DATA_W, TEST_FSE_RAM_NUM_PARTITIONS, + + TEST_HUFFMAN_WEIGHTS_DPD_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_DPD_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_DPD_RAM_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_TMP_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_TMP_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_TMP_RAM_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_TMP2_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_TMP2_RAM_NUM_PARTITIONS, + TEST_HUFFMAN_WEIGHTS_FSE_RAM_ADDR_W, TEST_HUFFMAN_WEIGHTS_FSE_RAM_DATA_W, TEST_HUFFMAN_WEIGHTS_FSE_RAM_NUM_PARTITIONS, + HISTORY_BUFFER_SIZE_KB, AXI_CHAN_N, >( csr_axi_aw_r, csr_axi_w_r, csr_axi_b_s, csr_axi_ar_r, csr_axi_r_s, @@ -525,10 +627,19 @@ proc ZstdDecoderTest { litbuf_rd_req_s, litbuf_rd_resp_r, litbuf_wr_req_s, litbuf_wr_resp_r, - huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_resp_r, - huffman_lit_weights_mem_wr_req_s, huffman_lit_weights_mem_wr_resp_r, - huffman_lit_prescan_mem_rd_req_s, huffman_lit_prescan_mem_rd_resp_r, - huffman_lit_prescan_mem_wr_req_s, huffman_lit_prescan_mem_wr_resp_r, + huffman_lit_weights_rd_req_s, huffman_lit_weights_rd_resp_r, + huffman_lit_weights_wr_req_s, huffman_lit_weights_wr_resp_r, + huffman_lit_prescan_rd_req_s, huffman_lit_prescan_rd_resp_r, + huffman_lit_prescan_wr_req_s, huffman_lit_prescan_wr_resp_r, + huffman_lit_weights_dpd_rd_req_s, huffman_lit_weights_dpd_rd_resp_r, + huffman_lit_weights_dpd_wr_req_s, huffman_lit_weights_dpd_wr_resp_r, + huffman_lit_weights_tmp_rd_req_s, huffman_lit_weights_tmp_rd_resp_r, + huffman_lit_weights_tmp_wr_req_s, huffman_lit_weights_tmp_wr_resp_r, + huffman_lit_weights_tmp2_rd_req_s, huffman_lit_weights_tmp2_rd_resp_r, + huffman_lit_weights_tmp2_wr_req_s, huffman_lit_weights_tmp2_wr_resp_r, + huffman_lit_weights_fse_rd_req_s, huffman_lit_weights_fse_rd_resp_r, + huffman_lit_weights_fse_wr_req_s, huffman_lit_weights_fse_wr_resp_r, + output_axi_aw_s, output_axi_w_s, output_axi_b_r, // RAMs for SequenceExecutor From d2fb888e1f668f15d4b2e7011d46898765f82d07 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 29 Jan 2025 14:28:41 +0100 Subject: [PATCH 64/85] Remove duplicate fifo.v file Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 4 ++-- xls/modules/zstd/fifo.v | 52 ----------------------------------------- 2 files changed, 2 insertions(+), 54 deletions(-) delete mode 100644 xls/modules/zstd/fifo.v diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 747d0d1deb..95686b28ff 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -2598,7 +2598,7 @@ verilog_library( name = "huffman_prescan_verilog_lib", srcs = [ ":huffman_prescan.v", - "fifo.v" + "xls_fifo_wrapper.v" ], tags = ["manual"], ) @@ -2684,7 +2684,7 @@ verilog_library( name = "huffman_code_builder_verilog_lib", srcs = [ ":huffman_code_builder.v", - "fifo.v" + "xls_fifo_wrapper.v" ], tags = ["manual"], ) diff --git a/xls/modules/zstd/fifo.v b/xls/modules/zstd/fifo.v deleted file mode 100644 index 3a1633b093..0000000000 --- a/xls/modules/zstd/fifo.v +++ /dev/null @@ -1,52 +0,0 @@ -module xls_fifo_wrapper ( -clk, rst, -push_ready, push_data, push_valid, -pop_ready, pop_data, pop_valid); - parameter Width = 32, - Depth = 32, - EnableBypass = 0, - RegisterPushOutputs = 1, - RegisterPopOutputs = 1; - localparam AddrWidth = $clog2(Depth) + 1; - input wire clk; - input wire rst; - output wire push_ready; - input wire [Width-1:0] push_data; - input wire push_valid; - input wire pop_ready; - output wire [Width-1:0] pop_data; - output wire pop_valid; - - // Require depth be 1 and bypass disabled. - initial begin - if (EnableBypass || Depth != 1 || !RegisterPushOutputs || RegisterPopOutputs) begin - // FIFO configuration not supported. - // $fatal(1); - end - end - - - reg [Width-1:0] mem; - reg full; - - assign push_ready = !full; - assign pop_valid = full; - assign pop_data = mem; - - always @(posedge clk) begin - if (rst == 1'b1) begin - full <= 1'b0; - end else begin - if (push_valid && push_ready) begin - mem <= push_data; - full <= 1'b1; - end else if (pop_valid && pop_ready) begin - mem <= mem; - full <= 1'b0; - end else begin - mem <= mem; - full <= full; - end - end - end -endmodule From 5c414bffb125f5f870ee653a083eb03c44e9fd8b Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 29 Jan 2025 14:31:28 +0100 Subject: [PATCH 65/85] Move test files to a separate directory Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 10 +++++----- xls/modules/zstd/{ => data}/comp_frame.x | 0 xls/modules/zstd/{ => data}/comp_frame_fse_comp.x | 0 xls/modules/zstd/{ => data}/comp_frame_fse_repeated.x | 0 xls/modules/zstd/{ => data}/comp_frame_huffman.x | 0 xls/modules/zstd/{ => data}/comp_frame_huffman_fse.x | 0 xls/modules/zstd/zstd_dec_test.x | 8 ++++---- 7 files changed, 9 insertions(+), 9 deletions(-) rename xls/modules/zstd/{ => data}/comp_frame.x (100%) rename xls/modules/zstd/{ => data}/comp_frame_fse_comp.x (100%) rename xls/modules/zstd/{ => data}/comp_frame_fse_repeated.x (100%) rename xls/modules/zstd/{ => data}/comp_frame_huffman.x (100%) rename xls/modules/zstd/{ => data}/comp_frame_huffman_fse.x (100%) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 95686b28ff..4bc079e952 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1284,11 +1284,11 @@ xls_dslx_test( "zstd_dec.x", "zstd_dec_test.x", "zstd_frame_testcases.x", - "comp_frame.x", - "comp_frame_huffman.x", - "comp_frame_huffman_fse.x", - "comp_frame_fse_comp.x", - "comp_frame_fse_repeated.x", + "data/comp_frame.x", + "data/comp_frame_huffman.x", + "data/comp_frame_huffman_fse.x", + "data/comp_frame_fse_comp.x", + "data/comp_frame_fse_repeated.x", ], tags = ["manual"], deps = zstd_dec_deps, diff --git a/xls/modules/zstd/comp_frame.x b/xls/modules/zstd/data/comp_frame.x similarity index 100% rename from xls/modules/zstd/comp_frame.x rename to xls/modules/zstd/data/comp_frame.x diff --git a/xls/modules/zstd/comp_frame_fse_comp.x b/xls/modules/zstd/data/comp_frame_fse_comp.x similarity index 100% rename from xls/modules/zstd/comp_frame_fse_comp.x rename to xls/modules/zstd/data/comp_frame_fse_comp.x diff --git a/xls/modules/zstd/comp_frame_fse_repeated.x b/xls/modules/zstd/data/comp_frame_fse_repeated.x similarity index 100% rename from xls/modules/zstd/comp_frame_fse_repeated.x rename to xls/modules/zstd/data/comp_frame_fse_repeated.x diff --git a/xls/modules/zstd/comp_frame_huffman.x b/xls/modules/zstd/data/comp_frame_huffman.x similarity index 100% rename from xls/modules/zstd/comp_frame_huffman.x rename to xls/modules/zstd/data/comp_frame_huffman.x diff --git a/xls/modules/zstd/comp_frame_huffman_fse.x b/xls/modules/zstd/data/comp_frame_huffman_fse.x similarity index 100% rename from xls/modules/zstd/comp_frame_huffman_fse.x rename to xls/modules/zstd/data/comp_frame_huffman_fse.x diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index a47531ca34..c56032cc0b 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -29,10 +29,10 @@ import xls.modules.zstd.literals_buffer; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.ram_mux; // import xls.modules.zstd.zstd_frame_testcases as comp_frame; -// import xls.modules.zstd.comp_frame_huffman as comp_frame; -// import xls.modules.zstd.comp_frame_fse_comp as comp_frame; -// import xls.modules.zstd.comp_frame_fse_repeated as comp_frame; -import xls.modules.zstd.comp_frame; +// import xls.modules.zstd.data.comp_frame_huffman as comp_frame; +// import xls.modules.zstd.data.comp_frame_fse_comp as comp_frame; +// import xls.modules.zstd.data.comp_frame_fse_repeated as comp_frame; +import xls.modules.zstd.data.comp_frame; const TEST_WINDOW_LOG_MAX = u32:30; From 54aef6a1231c64c0e10724199034bfd3b6042f42 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 29 Jan 2025 15:08:43 +0100 Subject: [PATCH 66/85] Move shift_buffer to zstd directory Signed-off-by: Robert Winkler --- xls/modules/shift_buffer/BUILD | 285 ------------------ xls/modules/shift_buffer/fixme.x | 52 ---- xls/modules/shift_buffer/math.x | 97 ------ xls/modules/shift_buffer/shift_buffer_inst.x | 71 ----- xls/modules/zstd/BUILD | 269 +++++++++++++++-- xls/modules/zstd/common.x | 2 +- xls/modules/zstd/comp_lookup_dec.x | 2 +- xls/modules/zstd/fse_lookup_dec.x | 2 +- xls/modules/zstd/fse_proba_freq_dec.x | 2 +- xls/modules/zstd/math.x | 32 +- xls/modules/zstd/refilling_shift_buffer.x | 2 +- xls/modules/zstd/sequence_dec.x | 2 +- .../{shift_buffer => zstd}/shift_buffer.x | 56 +++- 13 files changed, 329 insertions(+), 545 deletions(-) delete mode 100644 xls/modules/shift_buffer/BUILD delete mode 100644 xls/modules/shift_buffer/fixme.x delete mode 100644 xls/modules/shift_buffer/math.x delete mode 100644 xls/modules/shift_buffer/shift_buffer_inst.x rename xls/modules/{shift_buffer => zstd}/shift_buffer.x (94%) diff --git a/xls/modules/shift_buffer/BUILD b/xls/modules/shift_buffer/BUILD deleted file mode 100644 index 201bbf6fcc..0000000000 --- a/xls/modules/shift_buffer/BUILD +++ /dev/null @@ -1,285 +0,0 @@ -# Copyright 2024 The XLS Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# This is a pipeline-aware data buffer. The implementation aligns incoming data -# before it enters the buffer and mutates its state. - -load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route") -load("@rules_hdl//synthesis:build_defs.bzl", "benchmark_synth", "synthesize_rtl") -load("@rules_hdl//verilog:providers.bzl", "verilog_library") -load( - "//xls/build_rules:xls_build_defs.bzl", - "xls_benchmark_ir", - "xls_benchmark_verilog", - "xls_dslx_ir", - "xls_dslx_library", - "xls_dslx_opt_ir", - "xls_dslx_test", - "xls_dslx_verilog", - "xls_ir_opt_ir", - "xls_ir_verilog", -) - -package( - default_applicable_licenses = ["//:license"], - default_visibility = ["//xls:xls_users"], - licenses = ["notice"], -) - -xls_dslx_library( - name = "fixme_dslx", - srcs = ["fixme.x"], -) - -xls_dslx_test( - name = "fixme_dslx_test", - library = ":fixme_dslx", -) - -xls_dslx_library( - name = "math_dslx", - srcs = ["math.x"], - deps = [":fixme_dslx"] -) - -xls_dslx_test( - name = "math_dslx_test", - library = ":math_dslx", -) - -## ShiftBuffer - -xls_dslx_library( - name = "shift_buffer_dslx", - srcs = ["shift_buffer.x"], - deps = [ - ":math_dslx", - ":fixme_dslx", - ], -) - -xls_dslx_test( - name = "shift_buffer_dslx_test", - library = ":shift_buffer_dslx", -) - -xls_dslx_library( - name = "shift_buffer_inst_dslx", - srcs = ["shift_buffer_inst.x"], - deps = [ - ":shift_buffer_dslx", - ], -) - -# ShiftBufferAligner - -xls_dslx_verilog( - name = "shift_buffer_aligner_verilog", - codegen_args = { - "module_name": "ShiftBufferAligner", - "generator": "pipeline", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, - dslx_top = "ShiftBufferAlignerInst", - library = ":shift_buffer_inst_dslx", - opt_ir_args = { - "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferAlignerInst__ShiftBufferAligner_0__64_128_7_next", - }, - verilog_file = "shift_buffer_aligner.v", -) - -xls_benchmark_ir( - name = "shift_buffer_aligner_opt_ir_benchmark", - src = ":shift_buffer_aligner_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, -) - -verilog_library( - name = "shift_buffer_aligner_verilog_lib", - srcs = [ - ":shift_buffer_aligner.v", - ], -) - -synthesize_rtl( - name = "shift_buffer_aligner_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - top_module = "ShiftBufferAligner", - deps = [ - ":shift_buffer_aligner_verilog_lib", - ], -) - -benchmark_synth( - name = "shift_buffer_aligner_benchmark_synth", - synth_target = ":shift_buffer_aligner_synth_asap7", -) - -place_and_route( - name = "shift_buffer_aligner_place_and_route", - clock_period = "650", - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":shift_buffer_aligner_synth_asap7", - target_die_utilization_percentage = "5", -) - -xls_benchmark_verilog( - name = "shift_buffer_aligner_verilog_benchmark", - verilog_target = "shift_buffer_aligner_verilog", -) - -## ShiftBufferStorage - -xls_dslx_verilog( - name = "shift_buffer_storage_verilog", - codegen_args = { - "module_name": "ShiftBufferStorage", - "generator": "pipeline", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, - dslx_top = "ShiftBufferStorageInst", - library = ":shift_buffer_inst_dslx", - opt_ir_args = { - "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferStorageInst__ShiftBufferStorage_0__64_7_next", - }, - verilog_file = "shift_buffer_storage.v", -) - -xls_benchmark_ir( - name = "shift_buffer_storage_opt_ir_benchmark", - src = ":shift_buffer_storage_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, -) - -verilog_library( - name = "shift_buffer_storage_verilog_lib", - srcs = [ - ":shift_buffer_storage.v", - ], -) - -synthesize_rtl( - name = "shift_buffer_storage_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - top_module = "ShiftBufferStorage", - deps = [ - ":shift_buffer_storage_verilog_lib", - ], -) - -benchmark_synth( - name = "shift_buffer_storage_benchmark_synth", - synth_target = ":shift_buffer_storage_synth_asap7", -) - -place_and_route( - name = "shift_buffer_storage_place_and_route", - clock_period = "650", - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":shift_buffer_storage_synth_asap7", - target_die_utilization_percentage = "5", -) - -xls_benchmark_verilog( - name = "shift_buffer_storage_verilog_benchmark", - verilog_target = "shift_buffer_storage_verilog", -) - -## ShiftBuffer - -xls_dslx_verilog( - name = "shift_buffer_verilog", - codegen_args = { - "module_name": "ShiftBuffer", - "generator": "pipeline", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, - dslx_top = "ShiftBufferInst", - library = ":shift_buffer_inst_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferInst__ShiftBuffer_0__ShiftBufferStorage_0__64_7_next", - }, - verilog_file = "shift_buffer.v", -) - -xls_benchmark_ir( - name = "shift_buffer_opt_ir_benchmark", - src = ":shift_buffer_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, -) - -verilog_library( - name = "shift_buffer_verilog_lib", - srcs = [ - ":shift_buffer.v", - ], -) - -synthesize_rtl( - name = "shift_buffer_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - top_module = "ShiftBuffer", - deps = [ - ":shift_buffer_verilog_lib", - ], -) - -benchmark_synth( - name = "shift_buffer_benchmark_synth", - synth_target = ":shift_buffer_synth_asap7", -) - -place_and_route( - name = "shift_buffer_place_and_route", - clock_period = "650", - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":shift_buffer_synth_asap7", - target_die_utilization_percentage = "5", -) - -xls_benchmark_verilog( - name = "shift_buffer_verilog_benchmark", - verilog_target = "shift_buffer_verilog", -) diff --git a/xls/modules/shift_buffer/fixme.x b/xls/modules/shift_buffer/fixme.x deleted file mode 100644 index 9fa79247c1..0000000000 --- a/xls/modules/shift_buffer/fixme.x +++ /dev/null @@ -1,52 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -pub fn fast_if(cond: bool, arg1: uN[N], arg2: uN[N]) -> uN[N] { - let mask = if cond { !bits[N]:0 } else { bits[N]:0 }; - (arg1 & mask) | (arg2 & !mask) -} - -pub fn fast_if_tuple_2 - (cond: bool, arg1: (uN[N], uN[M]), arg2: (uN[N], uN[M])) -> (uN[N], uN[M]) { - (fast_if(cond, arg1.0, arg2.0), fast_if(cond, arg1.1, arg2.1)) -} - -pub fn fast_if_tuple_3 - (cond: bool, arg1: (uN[N], uN[M], uN[O]), arg2: (uN[N], uN[M], uN[O])) - -> (uN[N], uN[M], uN[O]) { - (fast_if(cond, arg1.0, arg2.0), fast_if(cond, arg1.1, arg2.1), fast_if(cond, arg1.2, arg2.2)) -} - -#[test] -fn fast_if_test() { - assert_eq(if true { u32:1 } else { u32:5 }, fast_if(true, u32:1, u32:5)); - assert_eq(if false { u32:1 } else { u32:5 }, fast_if(false, u32:1, u32:5)); - - assert_eq( - if true { - trace_fmt!("if: true"); - u16:74 - } else { - trace_fmt!("if: false"); - u16:32 - }, - fast_if(true, { - trace_fmt!("fast_if: true"); - u16:74 - }, { - trace_fmt!("fast_if: false"); - u16:32 - }) - ); -} diff --git a/xls/modules/shift_buffer/math.x b/xls/modules/shift_buffer/math.x deleted file mode 100644 index 057a843556..0000000000 --- a/xls/modules/shift_buffer/math.x +++ /dev/null @@ -1,97 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -import std; -import xls.modules.shift_buffer.fixme; - -// Log-depth shift bits left -pub fn logshiftl(n: bits[N], r: bits[R]) -> bits[N] { - for (i, y) in u32:0..R { - fixme::fast_if(r[i+:u1], { y << (bits[R]:1 << i) }, { y }) - }(n as bits[N]) -} - -#[test] -fn logshiftl_test() { - // Test varying base - assert_eq(logshiftl(bits[64]:0, bits[6]:3), bits[64]:0 << u32:3); - assert_eq(logshiftl(bits[64]:1, bits[6]:3), bits[64]:1 << u32:3); - assert_eq(logshiftl(bits[64]:2, bits[6]:3), bits[64]:2 << u32:3); - assert_eq(logshiftl(bits[64]:3, bits[6]:3), bits[64]:3 << u32:3); - assert_eq(logshiftl(bits[64]:4, bits[6]:3), bits[64]:4 << u32:3); - - // Test varying exponent - assert_eq(logshiftl(bits[64]:50, bits[6]:0), bits[64]:50 << u32:0); - assert_eq(logshiftl(bits[64]:50, bits[6]:1), bits[64]:50 << u32:1); - assert_eq(logshiftl(bits[64]:50, bits[6]:2), bits[64]:50 << u32:2); - assert_eq(logshiftl(bits[64]:50, bits[6]:3), bits[64]:50 << u32:3); - assert_eq(logshiftl(bits[64]:50, bits[6]:4), bits[64]:50 << u32:4); - - // Test overflow - let max = std::unsigned_max_value(); - assert_eq(logshiftl(max, u4:4), max << u4:4); - assert_eq(logshiftl(max, u4:5), max << u4:5); - assert_eq(logshiftl(max, u4:15), max << u4:15); - assert_eq(logshiftl(bits[24]:0xc0ffee, u8:12), bits[24]:0xfee000); -} - - -// Log-depth shift bits right -pub fn logshiftr(n: bits[N], r: bits[R]) -> bits[N] { - for (i, y) in u32:0..R { - fixme::fast_if(r[i+:u1], { y >> (bits[R]:1 << i) }, { y }) - }(n as bits[N]) -} - -#[test] -fn logshiftr_test() { - // Test varying base - assert_eq(logshiftr(bits[64]:0x0fac4e782, bits[6]:3), bits[64]:0x0fac4e782 >> u32:3); - assert_eq(logshiftr(bits[64]:0x1fac4e782, bits[6]:3), bits[64]:0x1fac4e782 >> u32:3); - assert_eq(logshiftr(bits[64]:0x2fac4e782, bits[6]:3), bits[64]:0x2fac4e782 >> u32:3); - assert_eq(logshiftr(bits[64]:0x3fac4e782, bits[6]:3), bits[64]:0x3fac4e782 >> u32:3); - assert_eq(logshiftr(bits[64]:0x4fac4e782, bits[6]:3), bits[64]:0x4fac4e782 >> u32:3); - - // Test varying exponent - assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:0), bits[64]:0x50fac4e782 >> u32:0); - assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:1), bits[64]:0x50fac4e782 >> u32:1); - assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:2), bits[64]:0x50fac4e782 >> u32:2); - assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:3), bits[64]:0x50fac4e782 >> u32:3); - assert_eq(logshiftr(bits[64]:0x50fac4e782, bits[6]:4), bits[64]:0x50fac4e782 >> u32:4); - - // Test overflow - let max = std::unsigned_max_value(); - assert_eq(logshiftr(max, u4:4), max >> u4:4); - assert_eq(logshiftr(max, u4:5), max >> u4:5); - assert_eq(logshiftr(max, u4:15), max >> u4:15); - assert_eq(logshiftr(bits[24]:0xc0ffee, u8:12), bits[24]:0x000c0f); -} - -// Return given value with m first bits masked -pub fn mask(n: bits[N], m: bits[M]) -> bits[N] { - n & (std::mask_bits() >> (N as bits[M] - m)) -} - -#[test] -fn mask_test() { - assert_eq(mask(u8:0b11111111, u4:0), u8:0b00000000); - assert_eq(mask(u8:0b11111111, u4:1), u8:0b00000001); - assert_eq(mask(u8:0b11111111, u4:2), u8:0b00000011); - assert_eq(mask(u8:0b11111111, u4:4), u8:0b00001111); - assert_eq(mask(u8:0b11111111, u4:8), u8:0b11111111); - assert_eq(mask(u8:0b11111111, u4:9), u8:0b00000000); // FIXME: sketchy result, I would expect - // 0b11111111 -} - - diff --git a/xls/modules/shift_buffer/shift_buffer_inst.x b/xls/modules/shift_buffer/shift_buffer_inst.x deleted file mode 100644 index 44c2df8be9..0000000000 --- a/xls/modules/shift_buffer/shift_buffer_inst.x +++ /dev/null @@ -1,71 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -import std; -import xls.modules.shift_buffer.shift_buffer; - -const TEST_DATA_WIDTH = u32:64; -const TEST_DATA_WIDTH_X2 = u32:128; -const TEST_LENGTH_WIDTH = std::clog2(TEST_DATA_WIDTH) + u32:1; - -proc ShiftBufferInst { - type Input = shift_buffer::ShiftBufferPacket; - type Ctrl = shift_buffer::ShiftBufferCtrl; - type Output = shift_buffer::ShiftBufferOutput; - input_r: chan> in; - ctrl_r: chan> in; - output_s: chan> out; - - config(input_r: chan> in, - ctrl_r: chan> in, - output_s: chan> out) { - - spawn shift_buffer::ShiftBuffer(ctrl_r, input_r, output_s); - - (input_r, ctrl_r, output_s) - } - - init { } - - next(state: ()) {} -} - -proc ShiftBufferAlignerInst { - type Input = shift_buffer::ShiftBufferPacket; - type Inter = shift_buffer::ShiftBufferPacket; - - config(input: chan in, inter: chan out) { - spawn shift_buffer::ShiftBufferAligner(input, inter); - } - - init { } - - next(state: ()) { } -} - -proc ShiftBufferStorageInst { - type Ctrl = shift_buffer::ShiftBufferCtrl; - type Inter = shift_buffer::ShiftBufferPacket; - type Output = shift_buffer::ShiftBufferOutput; - - config(ctrl: chan in, inter: chan in, output: chan out) { - spawn shift_buffer::ShiftBufferStorage(ctrl, inter, output); - } - - init { } - - next(state: ()) { } -} - - diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 4bc079e952..c1bc01988d 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -151,6 +151,237 @@ place_and_route( target_die_utilization_percentage = "10", ) +xls_dslx_library( + name = "shift_buffer_dslx", + srcs = ["shift_buffer.x"], + deps = [ + ":math_dslx", + ], +) + +xls_dslx_test( + name = "shift_buffer_dslx_test", + library = ":shift_buffer_dslx", + tags = ["manual"], +) + +xls_dslx_verilog( + name = "shift_buffer_aligner_verilog", + codegen_args = { + "module_name": "ShiftBufferAligner", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferAlignerInst", + library = ":shift_buffer_dslx", + opt_ir_args = { + "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferAlignerInst__ShiftBufferAligner_0__64_128_7_next", + }, + verilog_file = "shift_buffer_aligner.v", + tags = ["manual"], +) + +xls_benchmark_ir( + name = "shift_buffer_aligner_opt_ir_benchmark", + src = ":shift_buffer_aligner_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, + tags = ["manual"], +) + +verilog_library( + name = "shift_buffer_aligner_verilog_lib", + srcs = [ + ":shift_buffer_aligner.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "shift_buffer_aligner_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBufferAligner", + deps = [ + ":shift_buffer_aligner_verilog_lib", + ], + tags = ["manual"], +) + +benchmark_synth( + name = "shift_buffer_aligner_benchmark_synth", + synth_target = ":shift_buffer_aligner_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "shift_buffer_aligner_place_and_route", + clock_period = "650", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_aligner_synth_asap7", + target_die_utilization_percentage = "5", + tags = ["manual"], +) + +xls_benchmark_verilog( + name = "shift_buffer_aligner_verilog_benchmark", + verilog_target = "shift_buffer_aligner_verilog", + tags = ["manual"], +) + +xls_dslx_verilog( + name = "shift_buffer_storage_verilog", + codegen_args = { + "module_name": "ShiftBufferStorage", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferStorageInst", + library = ":shift_buffer_dslx", + opt_ir_args = { + "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferStorageInst__ShiftBufferStorage_0__64_7_next", + }, + verilog_file = "shift_buffer_storage.v", + tags = ["manual"], +) + +xls_benchmark_ir( + name = "shift_buffer_storage_opt_ir_benchmark", + src = ":shift_buffer_storage_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, + tags = ["manual"], +) + +verilog_library( + name = "shift_buffer_storage_verilog_lib", + srcs = [ + ":shift_buffer_storage.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "shift_buffer_storage_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBufferStorage", + deps = [ + ":shift_buffer_storage_verilog_lib", + ], + tags = ["manual"], +) + +benchmark_synth( + name = "shift_buffer_storage_benchmark_synth", + synth_target = ":shift_buffer_storage_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "shift_buffer_storage_place_and_route", + clock_period = "650", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_storage_synth_asap7", + target_die_utilization_percentage = "5", + tags = ["manual"], +) + +xls_benchmark_verilog( + name = "shift_buffer_storage_verilog_benchmark", + verilog_target = "shift_buffer_storage_verilog", + tags = ["manual"], +) + +xls_dslx_verilog( + name = "shift_buffer_verilog", + codegen_args = { + "module_name": "ShiftBuffer", + "generator": "pipeline", + "delay_model": "asap7", + "pipeline_stages": "2", + "reset": "rst", + "worst_case_throughput": "1", + "use_system_verilog": "false", + }, + dslx_top = "ShiftBufferInst", + library = ":shift_buffer_dslx", + opt_ir_args = { + "inline_procs": "true", + "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferInst__ShiftBuffer_0__ShiftBufferStorage_0__64_7_next", + }, + verilog_file = "shift_buffer.v", + tags = ["manual"], +) + +xls_benchmark_ir( + name = "shift_buffer_opt_ir_benchmark", + src = ":shift_buffer_verilog.opt.ir", + benchmark_ir_args = { + "pipeline_stages": "2", + "delay_model": "asap7", + }, + tags = ["manual"], +) + +verilog_library( + name = "shift_buffer_verilog_lib", + srcs = [ + ":shift_buffer.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "shift_buffer_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + top_module = "ShiftBuffer", + deps = [ + ":shift_buffer_verilog_lib", + ], + tags = ["manual"], +) + +benchmark_synth( + name = "shift_buffer_benchmark_synth", + synth_target = ":shift_buffer_synth_asap7", + tags = ["manual"], +) + +place_and_route( + name = "shift_buffer_place_and_route", + clock_period = "650", + core_padding_microns = 2, + min_pin_distance = "0.5", + placement_density = "0.30", + stop_after_step = "global_routing", + synthesized_rtl = ":shift_buffer_synth_asap7", + target_die_utilization_percentage = "5", + tags = ["manual"], +) + +xls_benchmark_verilog( + name = "shift_buffer_verilog_benchmark", + verilog_target = "shift_buffer_verilog", + tags = ["manual"], +) + cc_library( name = "data_generator", srcs = ["data_generator.cc"], @@ -178,7 +409,7 @@ xls_dslx_library( "common.x", ], deps = [ - "//xls/modules/shift_buffer:shift_buffer_dslx", + ":shift_buffer_dslx", "//xls/examples:ram_dslx", ], ) @@ -971,7 +1202,7 @@ xls_dslx_library( ":common_dslx", ":ram_wr_handler_dslx", ":refilling_shift_buffer_dslx", - "//xls/modules/shift_buffer:shift_buffer_dslx", + ":shift_buffer_dslx", "//xls/examples:ram_dslx", ], ) @@ -1147,7 +1378,7 @@ xls_dslx_library( name = "refilling_shift_buffer_dslx", srcs = ["refilling_shift_buffer.x"], deps = [ - "//xls/modules/shift_buffer:shift_buffer_dslx", + ":shift_buffer_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -1360,14 +1591,14 @@ xls_dslx_library( "comp_lookup_dec.x", ], deps = [ + ":shift_buffer_dslx", + ":common_dslx", + ":fse_table_creator_dslx", + ":refilling_shift_buffer_dslx", + ":fse_proba_freq_dec_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:axi_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", - "//xls/modules/zstd:common_dslx", - "//xls/modules/zstd:fse_table_creator_dslx", - "//xls/modules/zstd:refilling_shift_buffer_dslx", - "//xls/modules/zstd:fse_proba_freq_dec_dslx", - "//xls/modules/shift_buffer:shift_buffer_dslx", ] ) @@ -1384,9 +1615,9 @@ xls_dslx_library( ], deps = [ ":common_dslx", + ":refilling_shift_buffer_dslx", + ":fse_table_creator_dslx", "//xls/examples:ram_dslx", - "//xls/modules/zstd:refilling_shift_buffer_dslx", - "//xls/modules/zstd:fse_table_creator_dslx", ] ) @@ -1842,7 +2073,7 @@ xls_dslx_library( ":common_dslx", ":math_dslx", ":fse_table_creator_dslx", - "//xls/modules/zstd:refilling_shift_buffer_dslx", + ":refilling_shift_buffer_dslx", "//xls/examples:ram_dslx", ], ) @@ -2040,10 +2271,10 @@ xls_dslx_library( ":ram_mux_dslx", ":fse_table_creator_dslx", ":fse_lookup_dec_dslx", + ":shift_buffer_dslx", + ":refilling_shift_buffer_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", - "//xls/modules/zstd:refilling_shift_buffer_dslx", - "//xls/modules/shift_buffer:shift_buffer_dslx", ], ) @@ -3051,15 +3282,15 @@ xls_dslx_library( "huffman_weights_dec.x", ], deps = [ - "//xls/modules/zstd:huffman_prescan_dslx", - "//xls/modules/zstd:refilling_shift_buffer_dslx", - "//xls/modules/zstd:comp_lookup_dec_dslx", - "//xls/modules/zstd:fse_table_creator_dslx", - "//xls/modules/zstd:math_dslx", + ":math_dslx", + ":huffman_prescan_dslx", + ":refilling_shift_buffer_dslx", + ":comp_lookup_dec_dslx", + ":fse_table_creator_dslx", + ":ram_mux_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", "//xls/examples:ram_dslx", - ":ram_mux_dslx", ], ) diff --git a/xls/modules/zstd/common.x b/xls/modules/zstd/common.x index 377a5aa2c4..3174ee6a40 100644 --- a/xls/modules/zstd/common.x +++ b/xls/modules/zstd/common.x @@ -14,7 +14,7 @@ import std; import xls.examples.ram; -import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.shift_buffer; pub const DATA_WIDTH = u32:64; pub const MAX_ID = u32::MAX; diff --git a/xls/modules/zstd/comp_lookup_dec.x b/xls/modules/zstd/comp_lookup_dec.x index fd18e038b0..5b32b1fc4e 100644 --- a/xls/modules/zstd/comp_lookup_dec.x +++ b/xls/modules/zstd/comp_lookup_dec.x @@ -22,7 +22,7 @@ import xls.modules.zstd.memory.axi_ram; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.fse_proba_freq_dec; -import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.shift_buffer; type AccuracyLog = common::FseAccuracyLog; type ConsumedFseBytes = fse_proba_freq_dec::ConsumedFseBytes; diff --git a/xls/modules/zstd/fse_lookup_dec.x b/xls/modules/zstd/fse_lookup_dec.x index 85664be982..6c586c0713 100644 --- a/xls/modules/zstd/fse_lookup_dec.x +++ b/xls/modules/zstd/fse_lookup_dec.x @@ -22,7 +22,7 @@ import xls.modules.zstd.memory.axi_ram; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.fse_proba_freq_dec; -import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.shift_buffer; import xls.modules.zstd.comp_lookup_dec; import xls.modules.zstd.rle_lookup_dec; import xls.modules.zstd.refilling_shift_buffer_mux; diff --git a/xls/modules/zstd/fse_proba_freq_dec.x b/xls/modules/zstd/fse_proba_freq_dec.x index fa75571494..6a8665e096 100644 --- a/xls/modules/zstd/fse_proba_freq_dec.x +++ b/xls/modules/zstd/fse_proba_freq_dec.x @@ -19,7 +19,7 @@ import std; import xls.examples.ram; import xls.modules.zstd.common; -import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.shift_buffer; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.ram_wr_handler as ram_wr; diff --git a/xls/modules/zstd/math.x b/xls/modules/zstd/math.x index 1b9a8dd1db..7e733dc94a 100644 --- a/xls/modules/zstd/math.x +++ b/xls/modules/zstd/math.x @@ -14,21 +14,10 @@ import std; -fn fast_if(cond: bool, arg1: uN[N], arg2: uN[N]) -> uN[N] { - let mask = if cond { !bits[N]:0 } else { bits[N]:0 }; - (arg1 & mask) | (arg2 & !mask) -} - -#[test] -fn fast_if_test() { - assert_eq(if true { u32:1 } else { u32:5 }, fast_if(true, u32:1, u32:5)); - assert_eq(if false { u32:1 } else { u32:5 }, fast_if(false, u32:1, u32:5)); -} - // Log-depth shift bits left pub fn logshiftl(n: bits[N], r: bits[R]) -> bits[N] { for (i, y) in u32:0..R { - fast_if(r[i+:u1], { y << (bits[R]:1 << i) }, { y }) + if r[i+:u1] { y << (bits[R]:1 << i) } else { y } }(n as bits[N]) } @@ -56,10 +45,11 @@ fn logshiftl_test() { assert_eq(logshiftl(bits[24]:0xc0ffee, u8:12), bits[24]:0xfee000); } + // Log-depth shift bits right pub fn logshiftr(n: bits[N], r: bits[R]) -> bits[N] { for (i, y) in u32:0..R { - fast_if(r[i+:u1], { y >> (bits[R]:1 << i) }, { y }) + if r[i+:u1] { y >> (bits[R]:1 << i) } else { y } }(n as bits[N]) } @@ -86,3 +76,19 @@ fn logshiftr_test() { assert_eq(logshiftr(max, u4:15), max >> u4:15); assert_eq(logshiftr(bits[24]:0xc0ffee, u8:12), bits[24]:0x000c0f); } + +// Return given value with m first bits masked +pub fn mask(n: bits[N], m: bits[M]) -> bits[N] { + n & (std::mask_bits() >> (N as bits[M] - m)) +} + +#[test] +fn mask_test() { + assert_eq(mask(u8:0b11111111, u4:0), u8:0b00000000); + assert_eq(mask(u8:0b11111111, u4:1), u8:0b00000001); + assert_eq(mask(u8:0b11111111, u4:2), u8:0b00000011); + assert_eq(mask(u8:0b11111111, u4:4), u8:0b00001111); + assert_eq(mask(u8:0b11111111, u4:8), u8:0b11111111); + assert_eq(mask(u8:0b11111111, u4:9), u8:0b00000000); // FIXME: sketchy result, I would expect + // 0b11111111 +} diff --git a/xls/modules/zstd/refilling_shift_buffer.x b/xls/modules/zstd/refilling_shift_buffer.x index ced9665439..39001d600f 100644 --- a/xls/modules/zstd/refilling_shift_buffer.x +++ b/xls/modules/zstd/refilling_shift_buffer.x @@ -18,7 +18,7 @@ import std; -import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.shift_buffer; import xls.modules.zstd.memory.mem_reader; diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x index b14f088c07..e84dd54f57 100644 --- a/xls/modules/zstd/sequence_dec.x +++ b/xls/modules/zstd/sequence_dec.x @@ -26,7 +26,7 @@ import xls.modules.zstd.ram_demux; import xls.modules.zstd.ram_mux; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.fse_dec; -import xls.modules.shift_buffer.shift_buffer; +import xls.modules.zstd.shift_buffer; import xls.modules.zstd.fse_table_creator; diff --git a/xls/modules/shift_buffer/shift_buffer.x b/xls/modules/zstd/shift_buffer.x similarity index 94% rename from xls/modules/shift_buffer/shift_buffer.x rename to xls/modules/zstd/shift_buffer.x index add66ffe3e..b392825292 100644 --- a/xls/modules/shift_buffer/shift_buffer.x +++ b/xls/modules/zstd/shift_buffer.x @@ -13,8 +13,7 @@ // limitations under the License. import std; -import xls.modules.shift_buffer.fixme; -import xls.modules.shift_buffer.math; +import xls.modules.zstd.math; pub enum ShiftBufferStatus : u1 { OK = 0, @@ -467,6 +466,59 @@ pub proc ShiftBuffer { next(state: ()) { } } +const INST_DATA_WIDTH = u32:64; +const INST_DATA_WIDTH_X2 = u32:128; +const INST_LENGTH_WIDTH = std::clog2(INST_DATA_WIDTH) + u32:1; + +proc ShiftBufferInst { + type Input = ShiftBufferPacket; + type Ctrl = ShiftBufferCtrl; + type Output = ShiftBufferOutput; + input_r: chan> in; + ctrl_r: chan> in; + output_s: chan> out; + + config(input_r: chan> in, + ctrl_r: chan> in, + output_s: chan> out) { + + spawn ShiftBuffer(ctrl_r, input_r, output_s); + + (input_r, ctrl_r, output_s) + } + + init { } + + next(state: ()) {} +} + +proc ShiftBufferAlignerInst { + type Input = ShiftBufferPacket; + type Inter = ShiftBufferPacket; + + config(input: chan in, inter: chan out) { + spawn ShiftBufferAligner(input, inter); + } + + init { } + + next(state: ()) { } +} + +proc ShiftBufferStorageInst { + type Ctrl = ShiftBufferCtrl; + type Inter = ShiftBufferPacket; + type Output = ShiftBufferOutput; + + config(ctrl: chan in, inter: chan in, output: chan out) { + spawn ShiftBufferStorage(ctrl, inter, output); + } + + init { } + + next(state: ()) { } +} + const TEST_DATA_WIDTH = u32:64; const TEST_LENGTH_WIDTH = std::clog2(TEST_DATA_WIDTH) + u32:1; // TODO: other places in the code use length_width(TEST_DATA_WIDTH) which is clog2(TEST_DATA_WIDTH + 1) instead, why clog2(TEST_DATA_WIDTH) + 1 here? From 72486435cfe9cfd64aeab5405ce9409533621286 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 26 Mar 2025 22:43:54 +0100 Subject: [PATCH 67/85] Adjust BUILD files to the recent changes in the toolchain Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 186 +++++------------- xls/modules/zstd/memory/BUILD | 342 ++++++---------------------------- 2 files changed, 101 insertions(+), 427 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index c1bc01988d..107f2d5e7e 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -33,7 +33,6 @@ package( ) CLOCK_PERIOD_PS = "750" -# Clock periods for modules that exceed the 750ps critical path in IR benchmark common_codegen_args = { "delay_model": "asap7", @@ -43,6 +42,8 @@ common_codegen_args = { "clock_period_ps": CLOCK_PERIOD_PS, "clock_margin_percent": "20", "multi_proc": "true", + "fifo_module": "", + "materialize_internal_fifos": "true", } xls_dslx_library( @@ -67,7 +68,6 @@ xls_dslx_library( xls_dslx_test( name = "buffer_dslx_test", - dslx_test_args = {"compare": "jit"}, library = ":buffer_dslx", tags = ["manual"], ) @@ -84,15 +84,12 @@ xls_dslx_library( xls_dslx_test( name = "window_buffer_dslx_test", - dslx_test_args = {"compare": "jit"}, library = ":window_buffer_dslx", tags = ["manual"], ) window_buffer_codegen_args = common_codegen_args | { "module_name": "WindowBuffer64", - "clock_period_ps": "0", - "pipeline_stages": "1", "worst_case_throughput": "2", } @@ -108,10 +105,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "window_buffer_opt_ir_benchmark", src = ":window_buffer_verilog.opt.ir", - benchmark_ir_args = window_buffer_codegen_args | { - "pipeline_stages": "10", - "top": "__window_buffer__WindowBuffer64__WindowBuffer_0__64_32_48_next", - }, + benchmark_ir_args = window_buffer_codegen_args, tags = ["manual"], ) @@ -167,20 +161,9 @@ xls_dslx_test( xls_dslx_verilog( name = "shift_buffer_aligner_verilog", - codegen_args = { - "module_name": "ShiftBufferAligner", - "generator": "pipeline", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, + codegen_args = common_codegen_args, dslx_top = "ShiftBufferAlignerInst", library = ":shift_buffer_dslx", - opt_ir_args = { - "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferAlignerInst__ShiftBufferAligner_0__64_128_7_next", - }, verilog_file = "shift_buffer_aligner.v", tags = ["manual"], ) @@ -188,10 +171,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "shift_buffer_aligner_opt_ir_benchmark", src = ":shift_buffer_aligner_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, + benchmark_ir_args = common_codegen_args, tags = ["manual"], ) @@ -221,7 +201,7 @@ benchmark_synth( place_and_route( name = "shift_buffer_aligner_place_and_route", - clock_period = "650", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", @@ -237,22 +217,16 @@ xls_benchmark_verilog( tags = ["manual"], ) +shift_buffer_storage_codegen_args = common_codegen_args | { + "clock_period_ps": "0", + "pipeline_stages": "2", +} + xls_dslx_verilog( name = "shift_buffer_storage_verilog", - codegen_args = { - "module_name": "ShiftBufferStorage", - "generator": "pipeline", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, + codegen_args = shift_buffer_storage_codegen_args, dslx_top = "ShiftBufferStorageInst", library = ":shift_buffer_dslx", - opt_ir_args = { - "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferStorageInst__ShiftBufferStorage_0__64_7_next", - }, verilog_file = "shift_buffer_storage.v", tags = ["manual"], ) @@ -260,10 +234,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "shift_buffer_storage_opt_ir_benchmark", src = ":shift_buffer_storage_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, + benchmark_ir_args = shift_buffer_storage_codegen_args, tags = ["manual"], ) @@ -293,7 +264,7 @@ benchmark_synth( place_and_route( name = "shift_buffer_storage_place_and_route", - clock_period = "650", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", @@ -309,23 +280,17 @@ xls_benchmark_verilog( tags = ["manual"], ) +# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS +SHIFT_BUFFER_CLOCK_PERIOD_PS = "1000" +shift_buffer_codegen_args = common_codegen_args | { + "clock_period_ps": SHIFT_BUFFER_CLOCK_PERIOD_PS, +} + xls_dslx_verilog( name = "shift_buffer_verilog", - codegen_args = { - "module_name": "ShiftBuffer", - "generator": "pipeline", - "delay_model": "asap7", - "pipeline_stages": "2", - "reset": "rst", - "worst_case_throughput": "1", - "use_system_verilog": "false", - }, + codegen_args = shift_buffer_codegen_args, dslx_top = "ShiftBufferInst", library = ":shift_buffer_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__xls_modules_shift_buffer_shift_buffer__ShiftBufferInst__ShiftBuffer_0__ShiftBufferStorage_0__64_7_next", - }, verilog_file = "shift_buffer.v", tags = ["manual"], ) @@ -333,10 +298,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "shift_buffer_opt_ir_benchmark", src = ":shift_buffer_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "2", - "delay_model": "asap7", - }, + benchmark_ir_args = shift_buffer_codegen_args, tags = ["manual"], ) @@ -366,7 +328,7 @@ benchmark_synth( place_and_route( name = "shift_buffer_place_and_route", - clock_period = "650", + clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", @@ -460,6 +422,7 @@ verilog_library( name = "frame_header_dec_verilog_lib", srcs = [ ":frame_header_dec.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -555,6 +518,7 @@ verilog_library( name = "block_header_dec_verilog_lib", srcs = [ ":block_header_dec.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -633,6 +597,7 @@ verilog_library( name = "raw_block_dec_verilog_lib", srcs = [ ":raw_block_dec.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -710,6 +675,7 @@ verilog_library( name = "rle_block_dec_verilog_lib", srcs = [ ":rle_block_dec.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -787,6 +753,7 @@ verilog_library( name = "dec_mux_verilog_lib", srcs = [ ":dec_mux.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -903,10 +870,6 @@ xls_dslx_verilog( codegen_args = sequence_executor_codegen_args, dslx_top = "SequenceExecutorZstd", library = ":sequence_executor_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__sequence_executor__SequenceExecutorZstd__SequenceExecutor_0__16_64_64_0_0_0_13_8192_65536_next", - }, tags = ["manual"], verilog_file = "sequence_executor.v", ) @@ -930,6 +893,7 @@ verilog_library( name = "sequence_executor_lib", srcs = [ ":sequence_executor.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1009,6 +973,7 @@ verilog_library( name = "axi_csr_accessor_verilog_lib", srcs = [ ":axi_csr_accessor.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1085,6 +1050,7 @@ verilog_library( name = "csr_config_verilog_lib", srcs = [ ":csr_config.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1163,6 +1129,7 @@ verilog_library( name = "ram_rw_handler_verilog_lib", srcs = [ ":ram_rw_handler.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1233,10 +1200,6 @@ xls_dslx_verilog( }, dslx_top = "FseProbaFreqDecoderInst", library = ":fse_proba_freq_dec_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__fse_proba_freq_dec__FseProbaFreqDecoderInst__FseProbaFreqDecoder_0__64_7_8_10_1_next", - }, verilog_file = "fse_proba_freq_dec.v", tags = ["manual"], ) @@ -1247,7 +1210,6 @@ xls_benchmark_ir( benchmark_ir_args = { "pipeline_stages": "10", "delay_model": "asap7", - "inline_procs": "true", "reset": "rst", # FIXME: update ram rewrite #"ram_configurations": "ram:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( @@ -1271,6 +1233,7 @@ verilog_library( name = "fse_proba_freq_dec_lib", srcs = [ ":fse_proba_freq_dec.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1338,7 +1301,6 @@ xls_benchmark_ir( tags = ["manual"], ) - xls_dslx_library( name = "sequence_conf_dec_dslx", srcs = ["sequence_conf_dec.x"], @@ -1406,7 +1368,6 @@ xls_benchmark_ir( src = ":refilling_shift_buffer_internal_verilog.opt.ir", benchmark_ir_args = { "pipeline_stages": "10", - "inline_procs": "false", }, tags = ["manual"], ) @@ -1415,6 +1376,7 @@ verilog_library( name = "refilling_shift_buffer_internal_verilog_lib", srcs = [ ":refilling_shift_buffer_internal.v", + ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1469,7 +1431,7 @@ xls_dslx_library( xls_dslx_test( name = "comp_block_dec_dslx_test", library = ":comp_block_dec_dslx", - size = "large", + size = "enormous", tags = ["manual"], ) @@ -1521,6 +1483,7 @@ xls_dslx_test( "data/comp_frame_fse_comp.x", "data/comp_frame_fse_repeated.x", ], + size = "large", tags = ["manual"], deps = zstd_dec_deps, ) @@ -1542,10 +1505,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "zstd_dec_internal_opt_ir_benchmark", src = ":zstd_dec_internal_verilog.opt.ir", - benchmark_ir_args = { - "top": "__zstd_dec__ZstdDecoderInternalInst__ZstdDecoderInternal_0__16_64_8_4_16_next", - "pipeline_stages": "10", - }, + benchmark_ir_args = zstd_dec_internal_codegen_args, tags = ["manual"], ) @@ -1750,10 +1710,6 @@ xls_dslx_verilog( }, dslx_top = "FseTableCreatorInst", library = ":fse_table_creator_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__fse_table_creator__FseTableCreatorInst__FseTableCreator_0__8_16_1_9_32_1_9_8_1_8_16_1_next", - }, verilog_file = "fse_table_creator.v", tags = ["manual"], ) @@ -1930,10 +1886,6 @@ xls_dslx_verilog( }, dslx_top = "RamDemuxInst", library = ":ram_demux_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__ram_demux__RamDemuxInst__RamDemux_0__5_8_0_0_8_5_next", - }, verilog_file = "ram_demux.v", tags = ["manual"], ) @@ -2108,7 +2060,6 @@ xls_benchmark_ir( benchmark_ir_args = { "delay_model": "asap7", "pipeline_stages": "3", - "inline_procs": "false" }, tags = ["manual"], ) @@ -2197,7 +2148,6 @@ xls_benchmark_ir( benchmark_ir_args = { "delay_model": "asap7", "pipeline_stages": "3", - "inline_procs": "false" }, tags = ["manual"], ) @@ -2206,7 +2156,6 @@ verilog_library( name = "ram_demux3_verilog_lib", srcs = [ ":ram_demux3.v", - ":xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -2310,8 +2259,6 @@ xls_benchmark_ir( benchmark_ir_args = { "delay_model": "asap7", "pipeline_stages": "6", - "inline_procs": "false", - "multi_proc": "true", }, tags = ["manual"], ) @@ -2344,10 +2291,6 @@ xls_dslx_verilog( }, dslx_top = "RleLiteralsDecoderInst", library = ":rle_literals_dec_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__rle_literals_dec__RleLiteralsDecoderInst__RleLiteralsDecoder_0__64_next", - }, verilog_file = "rle_literals_dec.v", tags = ["manual"], ) @@ -2523,13 +2466,10 @@ xls_dslx_verilog( "reset": "rst", "worst_case_throughput": "1", "use_system_verilog": "false", + "multi_proc": "true", }, dslx_top = "LiteralsBufferInst", library = ":literals_buffer_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__literals_buffer__LiteralsBufferInst__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next" - }, verilog_file = "literals_buffer.v", tags = ["manual"], ) @@ -2621,9 +2561,6 @@ literals_decoder_ctrl_codegen_args = common_codegen_args | { xls_dslx_verilog( name = "literals_decoder_ctrl_verilog", codegen_args = literals_decoder_ctrl_codegen_args, - opt_ir_args = { - "inline_procs": "false", - }, dslx_top = "LiteralsDecoderCtrlInst", library = ":literals_decoder_dslx", verilog_file = "literals_decoder_ctrl.v", @@ -2635,7 +2572,6 @@ xls_benchmark_ir( src = ":literals_decoder_ctrl_verilog.opt.ir", benchmark_ir_args = literals_decoder_ctrl_codegen_args | { "multi_proc": "true", - "inline_procs": "false", }, tags = ["manual"], ) @@ -2699,10 +2635,6 @@ xls_dslx_verilog( }, dslx_top = "LiteralsDecoderInst", library = ":literals_decoder_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__xls_modules_zstd_literals_buffer__LiteralsDecoderInst__LiteralsDecoder_0__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next", - }, verilog_file = "literals_decoder.v", tags = ["manual"], ) @@ -2714,8 +2646,6 @@ xls_benchmark_ir( "pipeline_stages": "10", "worst_case_throughput": "2", "delay_model": "asap7", - "inline_procs": "true", - "top": "__xls_modules_zstd_literals_buffer__LiteralsDecoderInst__LiteralsDecoder_0__LiteralsBuffer_0__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next", }, tags = ["manual"], ) @@ -2829,7 +2759,6 @@ verilog_library( name = "huffman_prescan_verilog_lib", srcs = [ ":huffman_prescan.v", - "xls_fifo_wrapper.v" ], tags = ["manual"], ) @@ -2915,7 +2844,6 @@ verilog_library( name = "huffman_code_builder_verilog_lib", srcs = [ ":huffman_code_builder.v", - "xls_fifo_wrapper.v" ], tags = ["manual"], ) @@ -2966,7 +2894,6 @@ xls_dslx_test( huffman_axi_reader_codegen_args = common_codegen_args | { "module_name": "HuffmanAxiReader", - "pipeline_stages": "8", "clock_period_ps": "750", "worst_case_throughput": "4", } @@ -2976,10 +2903,6 @@ xls_dslx_verilog( codegen_args = huffman_axi_reader_codegen_args, dslx_top = "HuffmanAxiReaderInst", library = ":huffman_axi_reader_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__huffman_axi_reader__HuffmanAxiReaderInst__HuffmanAxiReader_0__16_8_3_64_4_4_next", - }, tags = ["manual"], verilog_file = "huffman_axi_reader.v", ) @@ -3058,10 +2981,6 @@ xls_dslx_verilog( codegen_args = huffman_data_preprocessor_codegen_args, dslx_top = "HuffmanDataPreprocessor", library = ":huffman_data_preprocessor_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "", - }, tags = ["manual"], verilog_file = "huffman_data_preprocessor.v", ) @@ -3139,10 +3058,6 @@ xls_dslx_verilog( codegen_args = huffman_decoder_codegen_args, dslx_top = "HuffmanDecoder", library = ":huffman_decoder_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "", - }, tags = ["manual"], verilog_file = "huffman_decoder.v", ) @@ -3225,10 +3140,6 @@ xls_dslx_verilog( codegen_args = huffman_ctrl_codegen_args, dslx_top = "HuffmanControlAndSequenceInst", library = ":huffman_ctrl_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__huffman_ctrl__HuffmanControlAndSequenceInst__HuffmanControlAndSequence_0__32_64_next", - }, tags = ["manual"], verilog_file = "huffman_ctrl.v", ) @@ -3298,6 +3209,7 @@ xls_dslx_test( name = "huffman_weights_dec_dslx_test", library = ":huffman_weights_dec_dslx", tags = ["manual"], + size = "large", ) huffman_weights_dec_codegen_args = common_codegen_args | { @@ -3305,6 +3217,7 @@ huffman_weights_dec_codegen_args = common_codegen_args | { "pipeline_stages": "25", "clock_period_ps": "750", "worst_case_throughput": "17", + "multi_proc": "true" } xls_dslx_verilog( @@ -3313,8 +3226,7 @@ xls_dslx_verilog( dslx_top = "HuffmanWeightsDecoderInst", library = ":huffman_weights_dec_dslx", opt_ir_args = { - "inline_procs": "true", - "top": "__huffman_weights_dec__HuffmanWeightsDecoderInst__HuffmanWeightsDecoder_0__32_64_6_32_8_next", + "top": "__huffman_weights_dec__HuffmanWeightsDecoderInst__HuffmanWeightsDecoder_0__32_64_8_8_16_1_8_32_4_9_8_1_8_16_1_6_32_8_next", }, tags = ["manual"], verilog_file = "huffman_weights_dec.v", @@ -3396,16 +3308,12 @@ huffman_literals_dec_codegen_args = common_codegen_args | { } xls_dslx_verilog( - name = "huffman_literals_dec_verilog", - codegen_args = huffman_literals_dec_codegen_args, - dslx_top = "HuffmanLiteralsDecoderInst", - library = ":huffman_literals_dec_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__xls_modules_zstd_huffman_decoder__HuffmanLiteralsDecoderInst__HuffmanLiteralsDecoder_0__HuffmanDecoder_0_next", - }, - tags = ["manual"], - verilog_file = "huffman_literals_dec.v", + name = "huffman_literals_dec_verilog", + codegen_args = huffman_literals_dec_codegen_args, + dslx_top = "HuffmanLiteralsDecoderInst", + library = ":huffman_literals_dec_dslx", + tags = ["manual"], + verilog_file = "huffman_literals_dec.v", ) xls_benchmark_ir( diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index e9ab9c0119..f5553c9eee 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -55,11 +55,6 @@ xls_dslx_test( CLOCK_PERIOD_PS = "750" -# Clock periods for modules that exceed the 750ps critical path in IR benchmark -AXI_READER_CLOCK_PERIOD_PS = "1800" - -MEM_READER_CLOCK_PERIOD_PS = "2600" - common_codegen_args = { "delay_model": "asap7", "reset": "rst", @@ -68,6 +63,13 @@ common_codegen_args = { "clock_period_ps": CLOCK_PERIOD_PS, "clock_margin_percent": "20", "multi_proc": "true", + "streaming_channel_data_suffix": "_data", + "fifo_module": "", + "materialize_internal_fifos": "true", + + # TODO: This should be adjusted when per channel separation of IO options is enabled + "flop_inputs_kind": "skid", + "flop_outputs_kind": "skid", } xls_dslx_library( @@ -86,12 +88,10 @@ xls_dslx_test( tags = ["manual"], ) +# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS +AXI_READER_CLOCK_PERIOD_PS = "1700" + axi_reader_codegen_args = common_codegen_args | { - "module_name": "axi_reader", - "pipeline_stages": "2", - "streaming_channel_data_suffix": "_data", - "flop_inputs_kind": "skid", - "flop_outputs_kind": "skid", "clock_period_ps": AXI_READER_CLOCK_PERIOD_PS, } @@ -107,10 +107,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "axi_reader_opt_ir_benchmark", src = ":axi_reader_verilog.opt.ir", - benchmark_ir_args = axi_reader_codegen_args | { - "pipeline_stages": "10", - "top": "__axi_reader__AxiReaderInst__AxiReader_0__16_32_4_4_4_3_2_14_next", - }, + benchmark_ir_args = axi_reader_codegen_args, tags = ["manual"], ) @@ -140,7 +137,7 @@ benchmark_synth( place_and_route( name = "axi_reader_place_and_route", - clock_period = CLOCK_PERIOD_PS, + clock_period = AXI_READER_CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", @@ -164,74 +161,9 @@ xls_dslx_test( tags = ["manual"], ) -axi_stream_remove_empty_internal_codegen_args = common_codegen_args | { - "module_name": "axi_stream_remove_empty_internal", - "pipeline_stages": "1", -} - -xls_dslx_verilog( - name = "axi_stream_remove_empty_internal_verilog", - codegen_args = axi_stream_remove_empty_internal_codegen_args, - dslx_top = "AxiStreamRemoveEmptyInternalInst", - library = ":axi_stream_remove_empty_dslx", - tags = ["manual"], - verilog_file = "axi_stream_remove_empty_internal.v", -) - -xls_benchmark_ir( - name = "axi_stream_remove_empty_internal_opt_ir_benchmark", - src = ":axi_stream_remove_empty_internal_verilog.opt.ir", - benchmark_ir_args = axi_stream_remove_empty_internal_codegen_args | { - "pipeline_stages": "10", - "top": "__axi_stream_remove_empty__AxiStreamRemoveEmptyInternalInst__AxiStreamRemoveEmptyInternal_0__32_4_6_32_32_next", - }, - tags = ["manual"], -) - -verilog_library( - name = "axi_stream_remove_empty_internal_verilog_lib", - srcs = [ - ":axi_stream_remove_empty_internal.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "axi_stream_remove_empty_internal_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "axi_stream_remove_empty_internal", - deps = [ - ":axi_stream_remove_empty_internal_verilog_lib", - ], -) - -benchmark_synth( - name = "axi_stream_remove_empty_internal_benchmark_synth", - synth_target = ":axi_stream_remove_empty_internal_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "axi_stream_remove_empty_internal_place_and_route", - clock_period = CLOCK_PERIOD_PS, - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":axi_stream_remove_empty_internal_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "10", -) - -axi_stream_remove_empty_codegen_args = common_codegen_args | { - "module_name": "axi_stream_remove_empty", - "pipeline_stages": "2", -} - xls_dslx_verilog( name = "axi_stream_remove_empty_verilog", - codegen_args = axi_stream_remove_empty_codegen_args, + codegen_args = common_codegen_args, dslx_top = "AxiStreamRemoveEmptyInst", library = ":axi_stream_remove_empty_dslx", tags = ["manual"], @@ -242,7 +174,6 @@ verilog_library( name = "axi_stream_remove_empty_verilog_lib", srcs = [ ":axi_stream_remove_empty.v", - "//xls/modules/zstd:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -275,14 +206,9 @@ place_and_route( target_die_utilization_percentage = "10", ) -remove_empty_bytes_codegen_args = common_codegen_args | { - "module_name": "remove_empty_bytes", - "pipeline_stages": "2", -} - xls_dslx_verilog( name = "remove_empty_bytes_verilog", - codegen_args = remove_empty_bytes_codegen_args, + codegen_args = common_codegen_args, dslx_top = "RemoveEmptyBytesInst", library = ":axi_stream_remove_empty_dslx", tags = ["manual"], @@ -292,10 +218,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "remove_empty_bytes_opt_ir_benchmark", src = ":remove_empty_bytes_verilog.opt.ir", - benchmark_ir_args = remove_empty_bytes_codegen_args | { - "top": "__axi_stream_remove_empty__RemoveEmptyBytesInst__RemoveEmptyBytes_0__32_4_6_32_9_32_next", - "pipeline_stages": "10", - }, + benchmark_ir_args = common_codegen_args, tags = ["manual"], ) @@ -349,14 +272,9 @@ xls_dslx_test( tags = ["manual"], ) -axi_stream_downscaler_codegen_args = common_codegen_args | { - "module_name": "axi_stream_downscaler", - "pipeline_stages": "2", -} - xls_dslx_verilog( name = "axi_stream_downscaler_verilog", - codegen_args = axi_stream_downscaler_codegen_args, + codegen_args = common_codegen_args, dslx_top = "AxiStreamDownscalerInst", library = ":axi_stream_downscaler_dslx", tags = ["manual"], @@ -366,10 +284,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "axi_stream_downscaler_opt_ir_benchmark", src = ":axi_stream_downscaler_verilog.opt.ir", - benchmark_ir_args = axi_stream_downscaler_codegen_args | { - "pipeline_stages": "10", - "top": "__axi_stream_downscaler__AxiStreamDownscalerInst__AxiStreamDownscaler_0__8_8_128_16_32_4_4_3_next", - }, + benchmark_ir_args = common_codegen_args, tags = ["manual"], ) @@ -424,29 +339,25 @@ xls_dslx_test( library = ":axi_ram_dslx", ) +# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS +AXI_RAM_READER_CLOCK_PERIOD_PS = "850" +axi_ram_reader_codegen_args = common_codegen_args | { + "clock_period_ps": AXI_RAM_READER_CLOCK_PERIOD_PS, + "ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 5, + ram_name = "ram", + rd_req = "axi_ram__rd_req_s", + rd_resp = "axi_ram__rd_resp_r", + wr_req = "axi_ram__wr_req_s", + wr_resp = "axi_ram__wr_resp_r", + ), +} + xls_dslx_verilog( name = "axi_ram_verilog", - codegen_args = { - "module_name": "AxiRam", - "delay_model": "asap7", - "ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, - ram_name = "ram", - rd_req = "axi_ram__rd_req_s", - rd_resp = "axi_ram__rd_resp_r", - wr_req = "axi_ram__wr_req_s", - wr_resp = "axi_ram__wr_resp_r", - ), - "pipeline_stages": "8", - "reset": "rst", - "use_system_verilog": "false", - }, + codegen_args = axi_ram_reader_codegen_args, dslx_top = "AxiRamReaderInstWithEmptyWrites", library = ":axi_ram_dslx", - opt_ir_args = { - "inline_procs": "true", - "top": "__axi_ram__AxiRamReaderInstWithEmptyWrites__AxiRamReader_0__AxiRamReaderResponder_0__32_32_4_5_6_8_8_32768_7_32_5_6_4_100_next", - }, tags = ["manual"], verilog_file = "axi_ram.v", ) @@ -462,10 +373,7 @@ verilog_library( xls_benchmark_ir( name = "axi_ram_opt_ir_benchmark", src = ":axi_ram_verilog.opt.ir", - benchmark_ir_args = { - "pipeline_stages": "4", - "delay_model": "asap7", - }, + benchmark_ir_args = axi_ram_reader_codegen_args, tags = ["manual"], ) @@ -515,74 +423,11 @@ xls_dslx_test( tags = ["manual"], ) -mem_reader_internal_codegen_args = common_codegen_args | { - "module_name": "mem_reader_internal", - "pipeline_stages": "10", -} - -xls_dslx_verilog( - name = "mem_reader_internal_verilog", - codegen_args = mem_reader_internal_codegen_args, - dslx_top = "MemReaderInternalInst", - library = ":mem_reader_dslx", - tags = ["manual"], - verilog_file = "mem_reader_internal.v", -) - -xls_benchmark_ir( - name = "mem_reader_internal_opt_ir_benchmark", - src = ":mem_reader_internal_verilog.opt.ir", - benchmark_ir_args = common_codegen_args | { - "pipeline_stages": "10", - "top": "__mem_reader__MemReaderInternalInst__MemReaderInternal_0__16_128_16_8_8_2_2_16_64_8_next", - }, - tags = ["manual"], -) - -verilog_library( - name = "mem_reader_internal_verilog_lib", - srcs = [ - ":mem_reader_internal.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "mem_reader_internal_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "mem_reader_internal", - deps = [ - ":mem_reader_internal_verilog_lib", - ], -) - -benchmark_synth( - name = "mem_reader_internal_benchmark_synth", - synth_target = ":mem_reader_internal_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "mem_reader_internal_place_and_route", - clock_period = CLOCK_PERIOD_PS, - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":mem_reader_internal_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "10", -) +# FIXME: Improve the proc to achieve CLOCK_PERIOD_PS +MEM_READER_CLOCK_PERIOD_PS = "2600" mem_reader_codegen_args = common_codegen_args | { "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, - "module_name": "mem_reader", - "pipeline_stages": "4", - "streaming_channel_data_suffix": "_data", - "flop_inputs_kind": "skid", - "flop_outputs_kind": "skid", - "materialize_internal_fifos": "true", } xls_dslx_verilog( @@ -602,6 +447,13 @@ verilog_library( tags = ["manual"], ) +xls_benchmark_ir( + name = "mem_reader_opt_ir_benchmark", + src = ":mem_reader_verilog.opt.ir", + benchmark_ir_args = mem_reader_codegen_args, + tags = ["manual"], +) + synthesize_rtl( name = "mem_reader_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", @@ -630,25 +482,22 @@ place_and_route( target_die_utilization_percentage = "10", ) -mem_reader_adv_codegen_args = common_codegen_args | { - "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, - "module_name": "mem_reader_adv", - "pipeline_stages": "4", - "streaming_channel_data_suffix": "_data", - "flop_inputs_kind": "skid", - "flop_outputs_kind": "skid", - "materialize_internal_fifos": "true", -} - xls_dslx_verilog( name = "mem_reader_adv_verilog", - codegen_args = mem_reader_adv_codegen_args, + codegen_args = mem_reader_codegen_args, dslx_top = "MemReaderAdvInst", library = ":mem_reader_dslx", tags = ["manual"], verilog_file = "mem_reader_adv.v", ) +xls_benchmark_ir( + name = "mem_reader_adv_opt_ir_benchmark", + src = ":mem_reader_adv_verilog.opt.ir", + benchmark_ir_args = mem_reader_codegen_args, + tags = ["manual"], +) + verilog_library( name = "mem_reader_adv_verilog_lib", srcs = [ @@ -701,17 +550,9 @@ xls_dslx_test( tags = ["manual"], ) -axi_writer_codegen_args = common_codegen_args | { - "module_name": "axi_writer", - "pipeline_stages": "1", - "streaming_channel_data_suffix": "_data", - "flop_inputs_kind": "skid", - "flop_outputs_kind": "skid", -} - xls_dslx_verilog( name = "axi_writer_verilog", - codegen_args = axi_writer_codegen_args, + codegen_args = common_codegen_args, dslx_top = "AxiWriterInst", library = ":axi_writer_dslx", tags = ["manual"], @@ -721,10 +562,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "axi_writer_opt_ir_benchmark", src = ":axi_writer_verilog.opt.ir", - benchmark_ir_args = axi_writer_codegen_args | { - "pipeline_stages": "10", - "top": "__axi_writer__AxiWriterInst__AxiWriter_0__16_32_4_4_4_2_next", - }, + benchmark_ir_args = common_codegen_args, tags = ["manual"], ) @@ -798,10 +636,7 @@ xls_dslx_verilog( xls_benchmark_ir( name = "axi_stream_add_empty_opt_ir_benchmark", src = ":axi_stream_add_empty_verilog.opt.ir", - benchmark_ir_args = axi_stream_add_empty_codegen_args | { - "pipeline_stages": "10", - "top": "__axi_stream_add_empty__AxiStreamAddEmptyInst__AxiStreamAddEmpty_0__16_32_4_2_32_32_next", - }, + benchmark_ir_args = axi_stream_add_empty_codegen_args, tags = ["manual"], ) @@ -859,78 +694,9 @@ xls_dslx_test( library = ":mem_writer_dslx", ) -mem_writer_internal_codegen_args = common_codegen_args | { - "module_name": "mem_writer_internal", - "pipeline_stages": "2", -} - -xls_dslx_verilog( - name = "mem_writer_internal_verilog", - codegen_args = mem_writer_internal_codegen_args, - dslx_top = "MemWriterInternalInst", - library = ":mem_writer_dslx", - tags = ["manual"], - verilog_file = "mem_writer_internal.v", -) - -xls_benchmark_ir( - name = "mem_writer_internal_opt_ir_benchmark", - src = ":mem_writer_internal_verilog.opt.ir", - benchmark_ir_args = common_codegen_args | { - "pipeline_stages": "10", - "top": "__mem_writer__MemWriterInternalInst__MemWriterInternal_0__16_32_4_4_4_2_next", - }, - tags = ["manual"], -) - -verilog_library( - name = "mem_writer_internal_verilog_lib", - srcs = [ - ":mem_writer_internal.v", - ], - tags = ["manual"], -) - -synthesize_rtl( - name = "mem_writer_internal_synth_asap7", - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", - tags = ["manual"], - top_module = "mem_writer_internal", - deps = [ - ":mem_writer_internal_verilog_lib", - ], -) - -benchmark_synth( - name = "mem_writer_internal_benchmark_synth", - synth_target = ":mem_writer_internal_synth_asap7", - tags = ["manual"], -) - -place_and_route( - name = "mem_writer_internal_place_and_route", - clock_period = CLOCK_PERIOD_PS, - core_padding_microns = 2, - min_pin_distance = "0.5", - placement_density = "0.30", - stop_after_step = "global_routing", - synthesized_rtl = ":mem_writer_internal_synth_asap7", - tags = ["manual"], - target_die_utilization_percentage = "10", -) - -mem_writer_codegen_args = common_codegen_args | { - "module_name": "mem_writer", - "pipeline_stages": "10", - "streaming_channel_data_suffix": "_data", - "flop_inputs_kind": "skid", - "flop_outputs_kind": "skid", - "materialize_internal_fifos": "true", -} - xls_dslx_verilog( name = "mem_writer_verilog", - codegen_args = mem_writer_codegen_args, + codegen_args = common_codegen_args, dslx_top = "MemWriterInst", library = ":mem_writer_dslx", tags = ["manual"], From b4c7a36d479ebd2e9fbf118222bad1c98d75f829 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 26 Mar 2025 22:44:15 +0100 Subject: [PATCH 68/85] Adjust design to the recent changes in the toolchain Signed-off-by: Robert Winkler --- xls/modules/zstd/comp_block_dec.x | 3 ++- xls/modules/zstd/huffman_axi_reader.x | 6 +++--- xls/modules/zstd/huffman_literals_dec.x | 10 +++++----- xls/modules/zstd/memory/axi_ram.x | 7 +++++-- 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index 0cf51ff320..3c8df70fe7 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -1588,7 +1588,8 @@ proc CompressBlockDecoderTest { }(tok); let tok = send(tok, ml_sel_test_s, u1:1); - let tok = unroll_for!(test_i, tok): (u32, token) in range(u32:0, array_size(COMP_BLOCK_DEC_TESTCASES)) { + // TODO: Enable more test cases when posssible. Currently their number is limited to lower the RAM consumption + let tok = unroll_for!(test_i, tok): (u32, token) in u32[2]:[u32:0, u32:4] { let (input_length, input, output_length, output) = COMP_BLOCK_DEC_TESTCASES[test_i]; trace_fmt!("Loading testcase {}", test_i); diff --git a/xls/modules/zstd/huffman_axi_reader.x b/xls/modules/zstd/huffman_axi_reader.x index 5166789228..5030d9f14f 100644 --- a/xls/modules/zstd/huffman_axi_reader.x +++ b/xls/modules/zstd/huffman_axi_reader.x @@ -63,10 +63,10 @@ pub proc HuffmanAxiReader out, data_s: chan out, ) { - let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); - let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); + let (mem_rd_req_s, mem_rd_req_r) = chan("mem_rd_req"); + let (mem_rd_resp_s, mem_rd_resp_r) = chan("mem_rd_resp"); - spawn mem_reader::MemReader ( + spawn mem_reader::MemReader ( mem_rd_req_r, mem_rd_resp_s, axi_ar_s, diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index 825fbc05b6..171b05f994 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -204,27 +204,27 @@ pub proc HuffmanLiteralsDecoder< jump_table_mem_rd_resp_r, ); - spawn mem_reader::MemReader( + spawn mem_reader::MemReader( jump_table_mem_rd_req_r, jump_table_mem_rd_resp_s, jump_table_axi_ar_s, jump_table_axi_r_r ); - spawn mem_reader::MemReader( + spawn mem_reader::MemReader( weights_header_dec_mem_rd_req_r, weights_header_dec_mem_rd_resp_s, weights_header_dec_axi_ar_s, weights_header_dec_axi_r_r ); - spawn mem_reader::MemReader( + spawn mem_reader::MemReader( weights_raw_dec_mem_rd_req_r, weights_raw_dec_mem_rd_resp_s, weights_raw_dec_axi_ar_s, weights_raw_dec_axi_r_r ); - spawn mem_reader::MemReader( + spawn mem_reader::MemReader( weights_fse_lookup_dec_mem_rd_req_r, weights_fse_lookup_dec_mem_rd_resp_s, weights_fse_lookup_dec_axi_ar_s, weights_fse_lookup_dec_axi_r_r ); - spawn mem_reader::MemReader( + spawn mem_reader::MemReader( weights_fse_decoder_dec_mem_rd_req_r, weights_fse_decoder_dec_mem_rd_resp_s, weights_fse_decoder_dec_axi_ar_s, weights_fse_decoder_dec_axi_r_r ); diff --git a/xls/modules/zstd/memory/axi_ram.x b/xls/modules/zstd/memory/axi_ram.x index 4886028a9c..edea056195 100644 --- a/xls/modules/zstd/memory/axi_ram.x +++ b/xls/modules/zstd/memory/axi_ram.x @@ -108,7 +108,9 @@ proc AxiRamReaderRequester< //if ar_bundle_valid { // trace_fmt!("{:#x}", ar_bundle); //} else {}; - let tok = send_if(tok, sync_s, ar_bundle_valid && !ar_bundle_ok, Sync { + + let error = ar_bundle_valid && !ar_bundle_ok; + let tok = send_if(tok, sync_s, error, Sync { id: ar_bundle.id, resp: AxiReadResp::SLVERR, last: true, @@ -156,7 +158,7 @@ proc AxiRamReaderRequester< ) }; - let tok = send_if(tok, sync_s, state.status == Status::READ_BURST, Sync { + let tok = send_if(tok, sync_s, !error && state.status == Status::READ_BURST, Sync { do_recv_ram_resp: do_read_from_ram, read_data_size: read_data_size, read_data_offset: read_data_offset, @@ -707,6 +709,7 @@ proc AxiRamReaderTest { AxiAxBurst::WRAP => { (axi_ar_bundle.addr + j * (u32:1 << (axi_ar_bundle.size as u32))) % (TEST_RAM_SIZE * (TEST_RAM_DATA_W / u32:8)) }, + _ => fail!("invalid_burst_mode", TestAxiAddr:0), }; // create expected data using RAM data let (expected_data, addr_valid) = for (k, (expected_data, addr_valid)): (u32, (uN[TEST_AXI_DATA_W], bool)) in range(u32:0, TEST_AXI_DATA_W / u32:8) { From d008483884ac6b1e8da0d9719ad607446a6f9306 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 7 Apr 2025 16:50:39 +0200 Subject: [PATCH 69/85] xls/modules/zstd/BUILD: Format with buildifer Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 299 ++++++++++++++++++++--------------------- 1 file changed, 149 insertions(+), 150 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 107f2d5e7e..e2c9011ea6 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -164,8 +164,8 @@ xls_dslx_verilog( codegen_args = common_codegen_args, dslx_top = "ShiftBufferAlignerInst", library = ":shift_buffer_dslx", - verilog_file = "shift_buffer_aligner.v", tags = ["manual"], + verilog_file = "shift_buffer_aligner.v", ) xls_benchmark_ir( @@ -186,11 +186,11 @@ verilog_library( synthesize_rtl( name = "shift_buffer_aligner_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "ShiftBufferAligner", deps = [ ":shift_buffer_aligner_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -207,14 +207,14 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":shift_buffer_aligner_synth_asap7", - target_die_utilization_percentage = "5", tags = ["manual"], + target_die_utilization_percentage = "5", ) xls_benchmark_verilog( name = "shift_buffer_aligner_verilog_benchmark", - verilog_target = "shift_buffer_aligner_verilog", tags = ["manual"], + verilog_target = "shift_buffer_aligner_verilog", ) shift_buffer_storage_codegen_args = common_codegen_args | { @@ -227,8 +227,8 @@ xls_dslx_verilog( codegen_args = shift_buffer_storage_codegen_args, dslx_top = "ShiftBufferStorageInst", library = ":shift_buffer_dslx", - verilog_file = "shift_buffer_storage.v", tags = ["manual"], + verilog_file = "shift_buffer_storage.v", ) xls_benchmark_ir( @@ -249,11 +249,11 @@ verilog_library( synthesize_rtl( name = "shift_buffer_storage_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "ShiftBufferStorage", deps = [ ":shift_buffer_storage_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -270,18 +270,19 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":shift_buffer_storage_synth_asap7", - target_die_utilization_percentage = "5", tags = ["manual"], + target_die_utilization_percentage = "5", ) xls_benchmark_verilog( name = "shift_buffer_storage_verilog_benchmark", - verilog_target = "shift_buffer_storage_verilog", tags = ["manual"], + verilog_target = "shift_buffer_storage_verilog", ) # FIXME: Improve the proc to achieve CLOCK_PERIOD_PS SHIFT_BUFFER_CLOCK_PERIOD_PS = "1000" + shift_buffer_codegen_args = common_codegen_args | { "clock_period_ps": SHIFT_BUFFER_CLOCK_PERIOD_PS, } @@ -291,8 +292,8 @@ xls_dslx_verilog( codegen_args = shift_buffer_codegen_args, dslx_top = "ShiftBufferInst", library = ":shift_buffer_dslx", - verilog_file = "shift_buffer.v", tags = ["manual"], + verilog_file = "shift_buffer.v", ) xls_benchmark_ir( @@ -313,11 +314,11 @@ verilog_library( synthesize_rtl( name = "shift_buffer_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "ShiftBuffer", deps = [ ":shift_buffer_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -334,14 +335,14 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":shift_buffer_synth_asap7", - target_die_utilization_percentage = "5", tags = ["manual"], + target_die_utilization_percentage = "5", ) xls_benchmark_verilog( name = "shift_buffer_verilog_benchmark", - verilog_target = "shift_buffer_verilog", tags = ["manual"], + verilog_target = "shift_buffer_verilog", ) cc_library( @@ -351,6 +352,7 @@ cc_library( data = [ "@zstd//:decodecorpus", ], + tags = ["manual"], deps = [ "//xls/common:subprocess", "//xls/common/file:filesystem", @@ -362,7 +364,6 @@ cc_library( "@com_google_absl//absl/time", "@com_google_absl//absl/types:span", ], - tags = ["manual"], ) xls_dslx_library( @@ -823,8 +824,8 @@ xls_dslx_library( ], deps = [ ":common_dslx", - ":ram_printer_dslx", ":parallel_rams_dslx", + ":ram_printer_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:mem_writer_dslx", ], @@ -918,9 +919,9 @@ place_and_route( name = "sequence_executor_place_and_route", clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, - min_pin_distance = "0.4", die_height_microns = 120, die_width_microns = 120, + min_pin_distance = "0.4", placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":sequence_executor_asap7", @@ -1111,8 +1112,8 @@ xls_dslx_verilog( opt_ir_args = { "top": "__ram_wr_handler__RamWrRespHandlerInst__RamWrRespHandler_0__32_next", }, - verilog_file = "ram_rw_handler.v", tags = ["manual"], + verilog_file = "ram_rw_handler.v", ) xls_benchmark_ir( @@ -1137,11 +1138,11 @@ verilog_library( synthesize_rtl( name = "ram_rw_handler_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "RamWrRespHandler", deps = [ ":ram_rw_handler_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -1158,8 +1159,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":ram_rw_handler_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -1200,8 +1201,8 @@ xls_dslx_verilog( }, dslx_top = "FseProbaFreqDecoderInst", library = ":fse_proba_freq_dec_dslx", - verilog_file = "fse_proba_freq_dec.v", tags = ["manual"], + verilog_file = "fse_proba_freq_dec.v", ) xls_benchmark_ir( @@ -1225,8 +1226,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "fse_proba_freq_dec_verilog_benchmark", - verilog_target = "fse_proba_freq_dec_verilog", tags = ["manual"], + verilog_target = "fse_proba_freq_dec_verilog", ) verilog_library( @@ -1241,11 +1242,11 @@ verilog_library( synthesize_rtl( name = "fse_proba_freq_dec_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "FseProbaFreqDec", deps = [ ":fse_proba_freq_dec_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -1262,8 +1263,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "detailed_routing", synthesized_rtl = ":fse_proba_freq_dec_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -1281,7 +1282,6 @@ xls_dslx_test( tags = ["manual"], ) - xls_dslx_verilog( name = "literals_block_header_dec_verilog", codegen_args = window_buffer_codegen_args, @@ -1305,8 +1305,8 @@ xls_dslx_library( name = "sequence_conf_dec_dslx", srcs = ["sequence_conf_dec.x"], deps = [ - "//xls/modules/zstd/memory:mem_reader_dslx", ":common_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -1355,7 +1355,7 @@ xls_dslx_test( xls_dslx_verilog( name = "refilling_shift_buffer_internal_verilog", codegen_args = common_codegen_args | { - "module_name": "RefillingShiftBufferInternalInst" + "module_name": "RefillingShiftBufferInternalInst", }, dslx_top = "RefillingShiftBufferInternalInst", library = ":refilling_shift_buffer_dslx", @@ -1413,25 +1413,25 @@ xls_dslx_library( name = "comp_block_dec_dslx", srcs = ["comp_block_dec.x"], deps = [ - "//xls/examples:ram_dslx", - "//xls/modules/zstd/memory:mem_reader_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", - ":fse_proba_freq_dec_dslx", - ":literals_block_header_dec_dslx", + ":command_constructor_dslx", ":common_dslx", + ":fse_proba_freq_dec_dslx", ":huffman_literals_dec_dslx", - ":parallel_rams_dslx", + ":literals_block_header_dec_dslx", ":literals_buffer_dslx", - ":sequence_dec_dslx", ":literals_decoder_dslx", - ":command_constructor_dslx", + ":parallel_rams_dslx", + ":sequence_dec_dslx", + "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) xls_dslx_test( name = "comp_block_dec_dslx_test", - library = ":comp_block_dec_dslx", size = "enormous", + library = ":comp_block_dec_dslx", tags = ["manual"], ) @@ -1473,17 +1473,17 @@ xls_dslx_library( xls_dslx_test( name = "zstd_dec_dslx_test", + size = "large", srcs = [ - "zstd_dec.x", - "zstd_dec_test.x", - "zstd_frame_testcases.x", "data/comp_frame.x", - "data/comp_frame_huffman.x", - "data/comp_frame_huffman_fse.x", "data/comp_frame_fse_comp.x", "data/comp_frame_fse_repeated.x", + "data/comp_frame_huffman.x", + "data/comp_frame_huffman_fse.x", + "zstd_dec.x", + "zstd_dec_test.x", + "zstd_frame_testcases.x", ], - size = "large", tags = ["manual"], deps = zstd_dec_deps, ) @@ -1551,15 +1551,15 @@ xls_dslx_library( "comp_lookup_dec.x", ], deps = [ - ":shift_buffer_dslx", ":common_dslx", + ":fse_proba_freq_dec_dslx", ":fse_table_creator_dslx", ":refilling_shift_buffer_dslx", - ":fse_proba_freq_dec_dslx", + ":shift_buffer_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:axi_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", - ] + ], ) xls_dslx_test( @@ -1575,10 +1575,10 @@ xls_dslx_library( ], deps = [ ":common_dslx", - ":refilling_shift_buffer_dslx", ":fse_table_creator_dslx", + ":refilling_shift_buffer_dslx", "//xls/examples:ram_dslx", - ] + ], ) xls_dslx_test( @@ -1594,11 +1594,11 @@ xls_dslx_library( ], deps = [ ":comp_lookup_dec_dslx", - ":rle_lookup_dec_dslx", ":ram_mux_dslx", ":refilling_shift_buffer_dslx", ":refilling_shift_buffer_mux_dslx", - ] + ":rle_lookup_dec_dslx", + ], ) xls_dslx_test( @@ -1632,8 +1632,8 @@ xls_dslx_verilog( }, dslx_top = "FseTableIterator", library = ":fse_table_iterator_dslx", - verilog_file = "fse_table_iterator.v", tags = ["manual"], + verilog_file = "fse_table_iterator.v", ) xls_benchmark_ir( @@ -1657,11 +1657,11 @@ verilog_library( synthesize_rtl( name = "fse_table_iterator_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "FseTableIterator", deps = [ ":fse_table_iterator_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -1678,8 +1678,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":fse_table_iterator_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -1710,8 +1710,8 @@ xls_dslx_verilog( }, dslx_top = "FseTableCreatorInst", library = ":fse_table_creator_dslx", - verilog_file = "fse_table_creator.v", tags = ["manual"], + verilog_file = "fse_table_creator.v", ) xls_benchmark_ir( @@ -1726,8 +1726,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "fse_table_creator_verilog_benchmark", - verilog_target = "fse_table_creator_verilog", tags = ["manual"], + verilog_target = "fse_table_creator_verilog", ) verilog_library( @@ -1741,11 +1741,11 @@ verilog_library( synthesize_rtl( name = "fse_table_creator_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "FseTableCreator", deps = [ ":fse_table_creator_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -1762,8 +1762,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":fse_table_creator_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -1792,8 +1792,8 @@ xls_dslx_verilog( }, dslx_top = "CommandConstructor", library = ":command_constructor_dslx", - verilog_file = "command_constructor.v", tags = ["manual"], + verilog_file = "command_constructor.v", ) xls_benchmark_ir( @@ -1808,8 +1808,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "command_constructor_verilog_benchmark", - verilog_target = "command_constructor_verilog", tags = ["manual"], + verilog_target = "command_constructor_verilog", ) verilog_library( @@ -1823,11 +1823,11 @@ verilog_library( synthesize_rtl( name = "command_constructor_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "CommandConstructor", deps = [ ":command_constructor_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -1844,8 +1844,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":command_constructor_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -1886,8 +1886,8 @@ xls_dslx_verilog( }, dslx_top = "RamDemuxInst", library = ":ram_demux_dslx", - verilog_file = "ram_demux.v", tags = ["manual"], + verilog_file = "ram_demux.v", ) xls_benchmark_ir( @@ -1913,11 +1913,11 @@ verilog_library( synthesize_rtl( name = "ram_demux_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "RamDemux", deps = [ ":ram_demux_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -1934,8 +1934,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":ram_demux_synth_asap7", - target_die_utilization_percentage = "5", tags = ["manual"], + target_die_utilization_percentage = "5", ) xls_dslx_verilog( @@ -1964,8 +1964,8 @@ xls_dslx_verilog( opt_ir_args = { "top": "__ram_demux__RamDemuxNaiveInst__RamDemuxNaive_0__5_8_0_8_next", }, - verilog_file = "ram_demux_naive.v", tags = ["manual"], + verilog_file = "ram_demux_naive.v", ) xls_benchmark_ir( @@ -1991,11 +1991,11 @@ verilog_library( synthesize_rtl( name = "ram_demux_naive_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "RamDemuxNaive", deps = [ ":ram_demux_naive_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2012,8 +2012,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":ram_demux_naive_synth_asap7", - target_die_utilization_percentage = "5", tags = ["manual"], + target_die_utilization_percentage = "5", ) xls_dslx_library( @@ -2023,8 +2023,8 @@ xls_dslx_library( ], deps = [ ":common_dslx", - ":math_dslx", ":fse_table_creator_dslx", + ":math_dslx", ":refilling_shift_buffer_dslx", "//xls/examples:ram_dslx", ], @@ -2046,10 +2046,10 @@ xls_dslx_verilog( "use_system_verilog": "false", }, dslx_top = "FseDecoderInst", + library = ":fse_dec_dslx", opt_ir_args = { - "top": "__fse_dec__FseDecoderInst__FseDecoder_0__64_8_32_4_64_7_next" + "top": "__fse_dec__FseDecoderInst__FseDecoder_0__64_8_32_4_64_7_next", }, - library = ":fse_dec_dslx", tags = ["manual"], verilog_file = "fse_dec.v", ) @@ -2138,8 +2138,8 @@ xls_dslx_verilog( }, dslx_top = "RamDemux3Inst", library = ":ram_demux3_dslx", - verilog_file = "ram_demux3.v", tags = ["manual"], + verilog_file = "ram_demux3.v", ) xls_benchmark_ir( @@ -2193,7 +2193,7 @@ place_and_route( xls_dslx_library( name = "ram_mux_dslx", srcs = [ - "ram_mux.x" + "ram_mux.x", ], deps = [ "//xls/examples:ram_dslx", @@ -2209,21 +2209,21 @@ xls_dslx_test( xls_dslx_library( name = "sequence_dec_dslx", srcs = [ - "sequence_dec.x" + "sequence_dec.x", ], deps = [ - ":sequence_conf_dec_dslx", - ":comp_lookup_dec_dslx", - ":ram_demux3_dslx", ":common_dslx", + ":comp_lookup_dec_dslx", ":fse_dec_dslx", - ":ram_mux_dslx", - ":fse_table_creator_dslx", ":fse_lookup_dec_dslx", - ":shift_buffer_dslx", + ":fse_table_creator_dslx", + ":ram_demux3_dslx", + ":ram_mux_dslx", ":refilling_shift_buffer_dslx", - "//xls/modules/zstd/memory:mem_reader_dslx", + ":sequence_conf_dec_dslx", + ":shift_buffer_dslx", "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -2244,13 +2244,13 @@ xls_dslx_verilog( "use_system_verilog": "false", "multi_proc": "true", }, - opt_ir_args = { - "top": "__sequence_dec__FseLookupCtrlInst__FseLookupCtrl_0_next" - }, dslx_top = "FseLookupCtrlInst", library = ":sequence_dec_dslx", - verilog_file = "fse_lookup_ctrl.v", + opt_ir_args = { + "top": "__sequence_dec__FseLookupCtrlInst__FseLookupCtrl_0_next", + }, tags = ["manual"], + verilog_file = "fse_lookup_ctrl.v", ) xls_benchmark_ir( @@ -2291,8 +2291,8 @@ xls_dslx_verilog( }, dslx_top = "RleLiteralsDecoderInst", library = ":rle_literals_dec_dslx", - verilog_file = "rle_literals_dec.v", tags = ["manual"], + verilog_file = "rle_literals_dec.v", ) xls_benchmark_ir( @@ -2316,11 +2316,11 @@ verilog_library( synthesize_rtl( name = "rle_literals_dec_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "rle_literals_dec", deps = [ ":rle_literals_dec_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2337,8 +2337,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":rle_literals_dec_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -2365,13 +2365,13 @@ xls_dslx_verilog( "reset": "rst", "use_system_verilog": "false", }, - opt_ir_args = { - "top": "__raw_literals_dec__RawLiteralsDecoderInst__RawLiteralsDecoder_0__16_64_next" - }, dslx_top = "RawLiteralsDecoderInst", library = ":raw_literals_dec_dslx", - verilog_file = "raw_literals_dec.v", + opt_ir_args = { + "top": "__raw_literals_dec__RawLiteralsDecoderInst__RawLiteralsDecoder_0__16_64_next", + }, tags = ["manual"], + verilog_file = "raw_literals_dec.v", ) xls_benchmark_ir( @@ -2380,15 +2380,15 @@ xls_benchmark_ir( benchmark_ir_args = { "pipeline_stages": "10", "delay_model": "asap7", - "top": "__raw_literals_dec__RawLiteralsDecoderInst__RawLiteralsDecoder_0__16_64_next" + "top": "__raw_literals_dec__RawLiteralsDecoderInst__RawLiteralsDecoder_0__16_64_next", }, tags = ["manual"], ) xls_benchmark_verilog( name = "raw_literals_dec_verilog_benchmark", - verilog_target = "raw_literals_dec_verilog", tags = ["manual"], + verilog_target = "raw_literals_dec_verilog", ) verilog_library( @@ -2402,11 +2402,11 @@ verilog_library( synthesize_rtl( name = "raw_literals_dec_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "RawLiteralsDecoder", deps = [ ":raw_literals_dec_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2423,8 +2423,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":raw_literals_dec_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -2434,8 +2434,8 @@ xls_dslx_library( ], deps = [ ":common_dslx", - ":ram_printer_dslx", ":parallel_rams_dslx", + ":ram_printer_dslx", "//xls/examples:ram_dslx", ], ) @@ -2470,8 +2470,8 @@ xls_dslx_verilog( }, dslx_top = "LiteralsBufferInst", library = ":literals_buffer_dslx", - verilog_file = "literals_buffer.v", tags = ["manual"], + verilog_file = "literals_buffer.v", ) xls_benchmark_ir( @@ -2486,8 +2486,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "literals_buffer_verilog_benchmark", - verilog_target = "literals_buffer_verilog", tags = ["manual"], + verilog_target = "literals_buffer_verilog", ) verilog_library( @@ -2501,11 +2501,11 @@ verilog_library( synthesize_rtl( name = "literals_buffer_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "LiteralsBuffer", deps = [ ":literals_buffer_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2522,8 +2522,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":literals_buffer_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -2532,18 +2532,18 @@ xls_dslx_library( "literals_decoder.x", ], deps = [ - "//xls/examples:ram_dslx", - "//xls/modules/zstd/memory:axi_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", - "//xls/modules/zstd/memory:mem_reader_dslx", ":common_dslx", - ":literals_buffer_dslx", + ":huffman_literals_dec_dslx", ":literals_block_header_dec_dslx", + ":literals_buffer_dslx", ":parallel_rams_dslx", ":ram_printer_dslx", ":raw_literals_dec_dslx", ":rle_literals_dec_dslx", - ":huffman_literals_dec_dslx", + "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:axi_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -2563,16 +2563,16 @@ xls_dslx_verilog( codegen_args = literals_decoder_ctrl_codegen_args, dslx_top = "LiteralsDecoderCtrlInst", library = ":literals_decoder_dslx", - verilog_file = "literals_decoder_ctrl.v", tags = ["manual"], + verilog_file = "literals_decoder_ctrl.v", ) xls_benchmark_ir( name = "literals_decoder_ctrl_opt_ir_benchmark", src = ":literals_decoder_ctrl_verilog.opt.ir", benchmark_ir_args = literals_decoder_ctrl_codegen_args | { - "multi_proc": "true", - }, + "multi_proc": "true", + }, tags = ["manual"], ) @@ -2587,11 +2587,11 @@ verilog_library( synthesize_rtl( name = "literals_decoder_ctrl_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "LiteralsDecoderCtrl", deps = [ ":literals_decoder_ctrl_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2608,8 +2608,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":literals_decoder_ctrl_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_verilog( @@ -2635,8 +2635,8 @@ xls_dslx_verilog( }, dslx_top = "LiteralsDecoderInst", library = ":literals_decoder_dslx", - verilog_file = "literals_decoder.v", tags = ["manual"], + verilog_file = "literals_decoder.v", ) xls_benchmark_ir( @@ -2652,8 +2652,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "literals_decoder_verilog_benchmark", - verilog_target = "literals_decoder_verilog", tags = ["manual"], + verilog_target = "literals_decoder_verilog", ) verilog_library( @@ -2667,11 +2667,11 @@ verilog_library( synthesize_rtl( name = "literals_decoder_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "LiteralsDecoder", deps = [ ":literals_decoder_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2688,8 +2688,8 @@ place_and_route( placement_density = "0.30", stop_after_step = "global_routing", synthesized_rtl = ":literals_decoder_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -2706,10 +2706,10 @@ xls_dslx_library( "huffman_prescan.x", ], deps = [ - "//xls/examples:ram_dslx", - "//xls/dslx/stdlib:acm_random_dslx", ":common_dslx", ":huffman_common_dslx", + "//xls/dslx/stdlib:acm_random_dslx", + "//xls/examples:ram_dslx", ], ) @@ -2724,13 +2724,12 @@ prescan_codegen_args = common_codegen_args | { "pipeline_stages": "16", "clock_period_ps": "750", "worst_case_throughput": "1", - "ram_configurations": - "InternalRam:1R1W:huffman_prescan__internal_read_req_s" + - ":huffman_prescan__internal_read_rsp_r:" + - "huffman_prescan__internal_write_req_s:" + - "huffman_prescan__internal_write_rsp_r:5", - "io_constraints" : "huffman_prescan__read_req_s:send:" + - "huffman_prescan__read_rsp_r:recv:5:5", + "ram_configurations": "InternalRam:1R1W:huffman_prescan__internal_read_req_s" + + ":huffman_prescan__internal_read_rsp_r:" + + "huffman_prescan__internal_write_req_s:" + + "huffman_prescan__internal_write_rsp_r:5", + "io_constraints": "huffman_prescan__read_req_s:send:" + + "huffman_prescan__read_rsp_r:recv:5:5", } xls_dslx_verilog( @@ -2738,8 +2737,8 @@ xls_dslx_verilog( codegen_args = prescan_codegen_args, dslx_top = "WeightPreScan", library = ":huffman_prescan_dslx", - verilog_file = "huffman_prescan.v", tags = ["manual"], + verilog_file = "huffman_prescan.v", ) xls_benchmark_ir( @@ -2751,8 +2750,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "huffman_prescan_verilog_benchmark", - verilog_target = "huffman_prescan_verilog", tags = ["manual"], + verilog_target = "huffman_prescan_verilog", ) verilog_library( @@ -2766,11 +2765,11 @@ verilog_library( synthesize_rtl( name = "huffman_prescan_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "HuffmanPrescan", deps = [ ":huffman_prescan_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2786,8 +2785,8 @@ place_and_route( min_pin_distance = "0.5", placement_density = "0.30", synthesized_rtl = ":huffman_prescan_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -2796,10 +2795,10 @@ xls_dslx_library( "huffman_code_builder.x", ], deps = [ - "//xls/examples:ram_dslx", - "//xls/dslx/stdlib:acm_random_dslx", ":common_dslx", ":huffman_common_dslx", + "//xls/dslx/stdlib:acm_random_dslx", + "//xls/examples:ram_dslx", ], ) @@ -2814,8 +2813,8 @@ huffman_code_builder_codegen_args = common_codegen_args | { "pipeline_stages": "8", "clock_period_ps": "750", "worst_case_throughput": "1", - "io_constraints" : "huffman_code_builder__weight_r:recv:" + - "huffman_code_builder__codes_s:send:2:2", + "io_constraints": "huffman_code_builder__weight_r:recv:" + + "huffman_code_builder__codes_s:send:2:2", } xls_dslx_verilog( @@ -2823,8 +2822,8 @@ xls_dslx_verilog( codegen_args = huffman_code_builder_codegen_args, dslx_top = "WeightCodeBuilder", library = ":huffman_code_builder_dslx", - verilog_file = "huffman_code_builder.v", tags = ["manual"], + verilog_file = "huffman_code_builder.v", ) xls_benchmark_ir( @@ -2836,8 +2835,8 @@ xls_benchmark_ir( xls_benchmark_verilog( name = "huffman_code_builder_verilog_benchmark", - verilog_target = "huffman_code_builder_verilog", tags = ["manual"], + verilog_target = "huffman_code_builder_verilog", ) verilog_library( @@ -2851,11 +2850,11 @@ verilog_library( synthesize_rtl( name = "huffman_code_builder_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], top_module = "HuffmanCodeBuilder", deps = [ ":huffman_code_builder_verilog_lib", ], - tags = ["manual"], ) benchmark_synth( @@ -2871,8 +2870,8 @@ place_and_route( min_pin_distance = "0.5", placement_density = "0.30", synthesized_rtl = ":huffman_code_builder_synth_asap7", - target_die_utilization_percentage = "10", tags = ["manual"], + target_die_utilization_percentage = "10", ) xls_dslx_library( @@ -3193,23 +3192,23 @@ xls_dslx_library( "huffman_weights_dec.x", ], deps = [ - ":math_dslx", - ":huffman_prescan_dslx", - ":refilling_shift_buffer_dslx", ":comp_lookup_dec_dslx", ":fse_table_creator_dslx", + ":huffman_prescan_dslx", + ":math_dslx", ":ram_mux_dslx", - "//xls/modules/zstd/memory:mem_reader_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + ":refilling_shift_buffer_dslx", "//xls/examples:ram_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:mem_reader_dslx", ], ) xls_dslx_test( name = "huffman_weights_dec_dslx_test", + size = "large", library = ":huffman_weights_dec_dslx", tags = ["manual"], - size = "large", ) huffman_weights_dec_codegen_args = common_codegen_args | { @@ -3217,7 +3216,7 @@ huffman_weights_dec_codegen_args = common_codegen_args | { "pipeline_stages": "25", "clock_period_ps": "750", "worst_case_throughput": "17", - "multi_proc": "true" + "multi_proc": "true", } xls_dslx_verilog( @@ -3281,7 +3280,6 @@ xls_dslx_library( "huffman_literals_dec.x", ], deps = [ - "//xls/modules/zstd/memory:axi_ram_dslx", ":common_dslx", ":huffman_axi_reader_dslx", ":huffman_code_builder_dslx", @@ -3290,6 +3288,7 @@ xls_dslx_library( ":huffman_data_preprocessor_dslx", ":huffman_decoder_dslx", ":huffman_prescan_dslx", + "//xls/modules/zstd/memory:axi_ram_dslx", ], ) @@ -3308,12 +3307,12 @@ huffman_literals_dec_codegen_args = common_codegen_args | { } xls_dslx_verilog( - name = "huffman_literals_dec_verilog", - codegen_args = huffman_literals_dec_codegen_args, - dslx_top = "HuffmanLiteralsDecoderInst", - library = ":huffman_literals_dec_dslx", - tags = ["manual"], - verilog_file = "huffman_literals_dec.v", + name = "huffman_literals_dec_verilog", + codegen_args = huffman_literals_dec_codegen_args, + dslx_top = "HuffmanLiteralsDecoderInst", + library = ":huffman_literals_dec_dslx", + tags = ["manual"], + verilog_file = "huffman_literals_dec.v", ) xls_benchmark_ir( @@ -3362,11 +3361,11 @@ place_and_route( xls_dslx_library( name = "refilling_shift_buffer_mux_dslx", srcs = [ - "refilling_shift_buffer_mux.x" + "refilling_shift_buffer_mux.x", ], deps = [ - ":refilling_shift_buffer_dslx" - ] + ":refilling_shift_buffer_dslx", + ], ) xls_dslx_test( From 5ab3fa9a96dfd8684ae9dc8a35c8f77ca1036767 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 7 Apr 2025 16:51:15 +0200 Subject: [PATCH 70/85] xls/modules/zstd/memory/BUILD: Format with buildifer Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/BUILD | 1 + 1 file changed, 1 insertion(+) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index f5553c9eee..acfd13f700 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -341,6 +341,7 @@ xls_dslx_test( # FIXME: Improve the proc to achieve CLOCK_PERIOD_PS AXI_RAM_READER_CLOCK_PERIOD_PS = "850" + axi_ram_reader_codegen_args = common_codegen_args | { "clock_period_ps": AXI_RAM_READER_CLOCK_PERIOD_PS, "ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( From ebcae1ef73c6c693f80e69c6f8a97ea1ffb763e6 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Apr 2025 12:32:50 +0200 Subject: [PATCH 71/85] modules/zstd/memory: Add missing module names Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/memory/BUILD | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index acfd13f700..39e2f52040 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -93,6 +93,7 @@ AXI_READER_CLOCK_PERIOD_PS = "1700" axi_reader_codegen_args = common_codegen_args | { "clock_period_ps": AXI_READER_CLOCK_PERIOD_PS, + "module_name": "axi_reader", } xls_dslx_verilog( @@ -163,7 +164,7 @@ xls_dslx_test( xls_dslx_verilog( name = "axi_stream_remove_empty_verilog", - codegen_args = common_codegen_args, + codegen_args = common_codegen_args | {"module_name": "axi_stream_remove_empty"}, dslx_top = "AxiStreamRemoveEmptyInst", library = ":axi_stream_remove_empty_dslx", tags = ["manual"], @@ -208,7 +209,7 @@ place_and_route( xls_dslx_verilog( name = "remove_empty_bytes_verilog", - codegen_args = common_codegen_args, + codegen_args = common_codegen_args | {"module_name": "remove_empty_bytes"}, dslx_top = "RemoveEmptyBytesInst", library = ":axi_stream_remove_empty_dslx", tags = ["manual"], @@ -274,7 +275,7 @@ xls_dslx_test( xls_dslx_verilog( name = "axi_stream_downscaler_verilog", - codegen_args = common_codegen_args, + codegen_args = common_codegen_args | {"module_name": "axi_stream_downscaler"}, dslx_top = "AxiStreamDownscalerInst", library = ":axi_stream_downscaler_dslx", tags = ["manual"], @@ -429,6 +430,7 @@ MEM_READER_CLOCK_PERIOD_PS = "2600" mem_reader_codegen_args = common_codegen_args | { "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, + "module_name": "mem_reader", } xls_dslx_verilog( @@ -485,7 +487,7 @@ place_and_route( xls_dslx_verilog( name = "mem_reader_adv_verilog", - codegen_args = mem_reader_codegen_args, + codegen_args = mem_reader_codegen_args | {"module_name": "mem_reader_adv"}, dslx_top = "MemReaderAdvInst", library = ":mem_reader_dslx", tags = ["manual"], @@ -553,7 +555,7 @@ xls_dslx_test( xls_dslx_verilog( name = "axi_writer_verilog", - codegen_args = common_codegen_args, + codegen_args = common_codegen_args | {"module_name": "axi_writer"}, dslx_top = "AxiWriterInst", library = ":axi_writer_dslx", tags = ["manual"], @@ -697,7 +699,7 @@ xls_dslx_test( xls_dslx_verilog( name = "mem_writer_verilog", - codegen_args = common_codegen_args, + codegen_args = common_codegen_args | {"module_name": "mem_writer"}, dslx_top = "MemWriterInst", library = ":mem_writer_dslx", tags = ["manual"], From 5a4323dcaf5d4dd8ffa193eb7fa2e08aab8a7bcc Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Apr 2025 12:32:13 +0200 Subject: [PATCH 72/85] modules/zstd: Rename axi_ram->axi_ram_reader Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 14 +++--- xls/modules/zstd/comp_block_dec.x | 4 +- xls/modules/zstd/comp_lookup_dec.x | 4 +- xls/modules/zstd/fse_lookup_dec.x | 4 +- xls/modules/zstd/huffman_literals_dec.x | 14 +++--- xls/modules/zstd/huffman_weights_dec.x | 4 +- xls/modules/zstd/literals_decoder.x | 18 ++++---- xls/modules/zstd/memory/BUILD | 45 ++++++++++--------- .../memory/{axi_ram.x => axi_ram_reader.x} | 0 xls/modules/zstd/sequence_dec.x | 8 ++-- xls/modules/zstd/zstd_dec_test.x | 10 ++--- 11 files changed, 63 insertions(+), 62 deletions(-) rename xls/modules/zstd/memory/{axi_ram.x => axi_ram_reader.x} (100%) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index e2c9011ea6..f364c56bb4 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1423,7 +1423,7 @@ xls_dslx_library( ":parallel_rams_dslx", ":sequence_dec_dslx", "//xls/examples:ram_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -1460,7 +1460,7 @@ zstd_dec_deps = [ "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", "//xls/modules/zstd/memory:mem_writer_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", ] xls_dslx_library( @@ -1558,7 +1558,7 @@ xls_dslx_library( ":shift_buffer_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:axi_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", ], ) @@ -2222,7 +2222,7 @@ xls_dslx_library( ":refilling_shift_buffer_dslx", ":sequence_conf_dec_dslx", ":shift_buffer_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -2542,7 +2542,7 @@ xls_dslx_library( ":rle_literals_dec_dslx", "//xls/examples:ram_dslx", "//xls/modules/zstd/memory:axi_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -3199,7 +3199,7 @@ xls_dslx_library( ":ram_mux_dslx", ":refilling_shift_buffer_dslx", "//xls/examples:ram_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", "//xls/modules/zstd/memory:mem_reader_dslx", ], ) @@ -3288,7 +3288,7 @@ xls_dslx_library( ":huffman_data_preprocessor_dslx", ":huffman_decoder_dslx", ":huffman_prescan_dslx", - "//xls/modules/zstd/memory:axi_ram_dslx", + "//xls/modules/zstd/memory:axi_ram_reader_dslx", ], ) diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index 3c8df70fe7..a94658ba12 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -14,7 +14,7 @@ import std; import xls.examples.ram; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.common; import xls.modules.zstd.huffman_literals_dec; import xls.modules.zstd.parallel_rams; @@ -1326,7 +1326,7 @@ proc CompressBlockDecoderTest { >( axi_ram_rd_req_r[i], axi_ram_rd_resp_s[i], axi_ram_wr_req_r[i], axi_ram_wr_resp_s[i] ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_W, TEST_CASE_RAM_ADDR_W >( diff --git a/xls/modules/zstd/comp_lookup_dec.x b/xls/modules/zstd/comp_lookup_dec.x index 5b32b1fc4e..b6414ea7c4 100644 --- a/xls/modules/zstd/comp_lookup_dec.x +++ b/xls/modules/zstd/comp_lookup_dec.x @@ -18,7 +18,7 @@ import xls.examples.ram; import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; import xls.modules.zstd.memory.mem_reader; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.fse_proba_freq_dec; @@ -1756,7 +1756,7 @@ proc CompLookupDecoderTest { let (testcase_axi_r_s, testcase_axi_r_r) = chan("testcase_axi_r"); let (testcase_axi_ar_s, testcase_axi_ar_r) = chan("testcase_axi_ar"); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_WIDTH, TEST_AXI_DATA_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_ADDR_WIDTH, TEST_CASE_RAM_NUM_PARTITIONS, diff --git a/xls/modules/zstd/fse_lookup_dec.x b/xls/modules/zstd/fse_lookup_dec.x index 6c586c0713..47eeaaab9a 100644 --- a/xls/modules/zstd/fse_lookup_dec.x +++ b/xls/modules/zstd/fse_lookup_dec.x @@ -18,7 +18,7 @@ import xls.examples.ram; import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; import xls.modules.zstd.memory.mem_reader; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.refilling_shift_buffer; import xls.modules.zstd.fse_proba_freq_dec; @@ -544,7 +544,7 @@ proc FseLookupDecoderTest { let (testcase_axi_r_s, testcase_axi_r_r) = chan("testcase_axi_r"); let (testcase_axi_ar_s, testcase_axi_ar_r) = chan("testcase_axi_ar"); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_WIDTH, TEST_AXI_DATA_WIDTH, TEST_AXI_DEST_WIDTH, TEST_AXI_ID_WIDTH, TEST_CASE_RAM_SIZE, TEST_CASE_RAM_BASE_ADDR, TEST_CASE_RAM_DATA_WIDTH, TEST_CASE_RAM_ADDR_WIDTH, TEST_CASE_RAM_NUM_PARTITIONS, diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index 171b05f994..81819e9e75 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -25,7 +25,7 @@ import xls.modules.zstd.huffman_prescan as prescan; import xls.modules.zstd.huffman_ctrl as ctrl; import xls.modules.zstd.huffman_weights_dec as weights_dec; import xls.modules.zstd.memory.axi as axi; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.memory.mem_reader as mem_reader; import xls.examples.ram; @@ -907,7 +907,7 @@ proc HuffmanLiteralsDecoder_test { ram_rd_req_huffman_r, ram_rd_resp_huffman_s, ram_wr_req_huffman_r, ram_wr_resp_huffman_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -933,7 +933,7 @@ proc HuffmanLiteralsDecoder_test { ram_rd_req_jump_table_r, ram_rd_resp_jump_table_s, ram_wr_req_jump_table_r, ram_wr_resp_jump_table_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -959,7 +959,7 @@ proc HuffmanLiteralsDecoder_test { ram_rd_req_huffman_weights_header_r, ram_rd_resp_huffman_weights_header_s, ram_wr_req_huffman_weights_header_r, ram_wr_resp_huffman_weights_header_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -985,7 +985,7 @@ proc HuffmanLiteralsDecoder_test { ram_rd_req_huffman_weights_raw_r, ram_rd_resp_huffman_weights_raw_s, ram_wr_req_huffman_weights_raw_r, ram_wr_resp_huffman_weights_raw_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1011,7 +1011,7 @@ proc HuffmanLiteralsDecoder_test { ram_rd_req_huffman_weights_fse_lookup_r, ram_rd_resp_huffman_weights_fse_lookup_s, ram_wr_req_huffman_weights_fse_lookup_r, ram_wr_resp_huffman_weights_fse_lookup_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1036,7 +1036,7 @@ proc HuffmanLiteralsDecoder_test { ram_rd_req_huffman_weights_fse_decoder_r, ram_rd_resp_huffman_weights_fse_decoder_s, ram_wr_req_huffman_weights_fse_decoder_r, ram_wr_resp_huffman_weights_fse_decoder_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( diff --git a/xls/modules/zstd/huffman_weights_dec.x b/xls/modules/zstd/huffman_weights_dec.x index 287cf7ba17..3abea16e08 100644 --- a/xls/modules/zstd/huffman_weights_dec.x +++ b/xls/modules/zstd/huffman_weights_dec.x @@ -18,7 +18,7 @@ import xls.examples.ram; import xls.modules.zstd.common ; import xls.modules.zstd.huffman_prescan; import xls.modules.zstd.memory.axi; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.memory.mem_reader; import xls.modules.zstd.ram_mux; import xls.modules.zstd.refilling_shift_buffer; @@ -1990,7 +1990,7 @@ proc HuffmanWeightsDecoder_test { let (axi_r_s, axi_r_r) = chan[TEST_RAM_N]("axi_r"); unroll_for! (i, _) in range(u32:0, TEST_RAM_N) { - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, diff --git a/xls/modules/zstd/literals_decoder.x b/xls/modules/zstd/literals_decoder.x index f242d9bd68..110757a7ce 100644 --- a/xls/modules/zstd/literals_decoder.x +++ b/xls/modules/zstd/literals_decoder.x @@ -21,7 +21,7 @@ import xls.modules.zstd.common as common; import xls.modules.zstd.literals_block_header_dec as literals_block_header_dec; import xls.modules.zstd.literals_buffer as literals_buffer; import xls.modules.zstd.memory.axi as axi; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.memory.mem_reader as mem_reader; import xls.modules.zstd.parallel_rams as parallel_rams; import xls.modules.zstd.ram_printer as ram_printer; @@ -1573,7 +1573,7 @@ proc LiteralsDecoder_test { ram_rd_req_header_r, ram_rd_resp_header_s, ram_wr_req_header_r, ram_wr_resp_header_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1599,7 +1599,7 @@ proc LiteralsDecoder_test { ram_rd_req_raw_r, ram_rd_resp_raw_s, ram_wr_req_raw_r, ram_wr_resp_raw_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1625,7 +1625,7 @@ proc LiteralsDecoder_test { ram_rd_req_huffman_r, ram_rd_resp_huffman_s, ram_wr_req_huffman_r, ram_wr_resp_huffman_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1651,7 +1651,7 @@ proc LiteralsDecoder_test { ram_rd_req_huffman_jump_table_r, ram_rd_resp_huffman_jump_table_s, ram_wr_req_huffman_jump_table_r, ram_wr_resp_huffman_jump_table_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1677,7 +1677,7 @@ proc LiteralsDecoder_test { ram_rd_req_huffman_weights_header_r, ram_rd_resp_huffman_weights_header_s, ram_wr_req_huffman_weights_header_r, ram_wr_resp_huffman_weights_header_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1703,7 +1703,7 @@ proc LiteralsDecoder_test { ram_rd_req_huffman_weights_raw_r, ram_rd_resp_huffman_weights_raw_s, ram_wr_req_huffman_weights_raw_r, ram_wr_resp_huffman_weights_raw_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1730,7 +1730,7 @@ proc LiteralsDecoder_test { ram_wr_req_huffman_weights_fse_lookup_dec_r, ram_wr_resp_huffman_weights_fse_lookup_dec_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( @@ -1757,7 +1757,7 @@ proc LiteralsDecoder_test { ram_wr_req_huffman_weights_fse_decoder_dec_r, ram_wr_resp_huffman_weights_fse_decoder_dec_s ); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_RAM_ADDR_W, TEST_AXI_RAM_DATA_W, TEST_AXI_RAM_DEST_W, TEST_AXI_RAM_ID_W, TEST_AXI_RAM_MODEL_SIZE, TEST_AXI_RAM_MODEL_BASE_ADDR, TEST_AXI_RAM_MODEL_DATA_WIDTH, TEST_AXI_RAM_MODEL_ADDR_WIDTH > ( diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index 39e2f52040..6830997678 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -326,8 +326,8 @@ place_and_route( ) xls_dslx_library( - name = "axi_ram_dslx", - srcs = ["axi_ram.x"], + name = "axi_ram_reader_dslx", + srcs = ["axi_ram_reader.x"], deps = [ ":axi_dslx", "//xls/examples:ram_dslx", @@ -336,73 +336,74 @@ xls_dslx_library( ) xls_dslx_test( - name = "axi_ram_dslx_test", - library = ":axi_ram_dslx", + name = "axi_ram_reader_dslx_test", + library = ":axi_ram_reader_dslx", ) # FIXME: Improve the proc to achieve CLOCK_PERIOD_PS AXI_RAM_READER_CLOCK_PERIOD_PS = "850" axi_ram_reader_codegen_args = common_codegen_args | { + "module_name": "axi_ram_reader", "clock_period_ps": AXI_RAM_READER_CLOCK_PERIOD_PS, "ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( latency = 5, ram_name = "ram", - rd_req = "axi_ram__rd_req_s", - rd_resp = "axi_ram__rd_resp_r", - wr_req = "axi_ram__wr_req_s", - wr_resp = "axi_ram__wr_resp_r", + rd_req = "axi_ram_reader__rd_req_s", + rd_resp = "axi_ram_reader__rd_resp_r", + wr_req = "axi_ram_reader__wr_req_s", + wr_resp = "axi_ram_reader__wr_resp_r", ), } xls_dslx_verilog( - name = "axi_ram_verilog", + name = "axi_ram_reader_verilog", codegen_args = axi_ram_reader_codegen_args, dslx_top = "AxiRamReaderInstWithEmptyWrites", - library = ":axi_ram_dslx", + library = ":axi_ram_reader_dslx", tags = ["manual"], - verilog_file = "axi_ram.v", + verilog_file = "axi_ram_reader.v", ) verilog_library( - name = "axi_ram_verilog_lib", + name = "axi_ram_reader_verilog_lib", srcs = [ - ":axi_ram.v", + ":axi_ram_reader.v", ], tags = ["manual"], ) xls_benchmark_ir( - name = "axi_ram_opt_ir_benchmark", - src = ":axi_ram_verilog.opt.ir", + name = "axi_ram_reader_opt_ir_benchmark", + src = ":axi_ram_reader_verilog.opt.ir", benchmark_ir_args = axi_ram_reader_codegen_args, tags = ["manual"], ) synthesize_rtl( - name = "axi_ram_synth_asap7", + name = "axi_ram_reader_synth_asap7", standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", tags = ["manual"], - top_module = "AxiRam", + top_module = "axi_ram_reader", deps = [ - ":axi_ram_verilog_lib", + ":axi_ram_reader_verilog_lib", ], ) benchmark_synth( - name = "axi_ram_benchmark_synth", - synth_target = ":axi_ram_synth_asap7", + name = "axi_ram_reader_benchmark_synth", + synth_target = ":axi_ram_reader_synth_asap7", tags = ["manual"], ) place_and_route( - name = "axi_ram_place_and_route", + name = "axi_ram_reader_place_and_route", clock_period = "750", core_padding_microns = 2, min_pin_distance = "0.5", placement_density = "0.30", stop_after_step = "global_routing", - synthesized_rtl = ":axi_ram_synth_asap7", + synthesized_rtl = ":axi_ram_reader_synth_asap7", tags = ["manual"], target_die_utilization_percentage = "10", ) diff --git a/xls/modules/zstd/memory/axi_ram.x b/xls/modules/zstd/memory/axi_ram_reader.x similarity index 100% rename from xls/modules/zstd/memory/axi_ram.x rename to xls/modules/zstd/memory/axi_ram_reader.x diff --git a/xls/modules/zstd/sequence_dec.x b/xls/modules/zstd/sequence_dec.x index e84dd54f57..cbe89c439a 100644 --- a/xls/modules/zstd/sequence_dec.x +++ b/xls/modules/zstd/sequence_dec.x @@ -17,7 +17,7 @@ import std; import xls.examples.ram; import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.memory.mem_reader; import xls.modules.zstd.sequence_conf_dec; import xls.modules.zstd.fse_lookup_dec; @@ -2256,7 +2256,7 @@ proc SequenceDecoderTest { let (ss_axi_ar_s, ss_axi_ar_r) = chan("ss_axi_ar"); let (ss_axi_r_s, ss_axi_r_r) = chan("ss_axi_r"); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_INPUT_RAM_SIZE >( @@ -2283,7 +2283,7 @@ proc SequenceDecoderTest { let (fl_axi_ar_s, fl_axi_ar_r) = chan("fl_axi_ar"); let (fl_axi_r_s, fl_axi_r_r) = chan("fl_axi_r"); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_INPUT_RAM_SIZE >( @@ -2311,7 +2311,7 @@ proc SequenceDecoderTest { let (fd_axi_ar_s, fd_axi_ar_r) = chan("fd_axi_ar"); let (fd_axi_r_s, fd_axi_r_r) = chan("fd_axi_r"); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_INPUT_RAM_SIZE >( diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index c56032cc0b..423518c268 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -18,7 +18,7 @@ import xls.modules.zstd.common; import xls.modules.zstd.memory.axi; import xls.modules.zstd.csr_config; import xls.modules.zstd.sequence_executor; -import xls.modules.zstd.memory.axi_ram; +import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.zstd_dec; import xls.modules.zstd.comp_block_dec; import xls.modules.zstd.sequence_dec; @@ -451,7 +451,7 @@ proc ZstdDecoderTest { TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED >(comp_ram_rd_req_r[i], comp_ram_rd_resp_s[i], comp_ram_wr_req_r[i], comp_ram_wr_resp_s[i]); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W >(comp_axi_ar_r[i], comp_axi_r_s[i], comp_ram_rd_req_s[i], comp_ram_rd_resp_r[i]); @@ -679,17 +679,17 @@ proc ZstdDecoderTest { TEST_RAM_SIMULTANEOUS_READ_WRITE_BEHAVIOR, TEST_RAM_INITIALIZED, > (raw_ram_rd_req_r, raw_ram_rd_resp_s, raw_ram_wr_req_r, raw_ram_wr_resp_s); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, >(fh_axi_ar_r, fh_axi_r_s, fh_ram_rd_req_s, fh_ram_rd_resp_r); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, >(bh_axi_ar_r, bh_axi_r_s, bh_ram_rd_req_s, bh_ram_rd_resp_r); - spawn axi_ram::AxiRamReader< + spawn axi_ram_reader::AxiRamReader< TEST_AXI_ADDR_W, TEST_AXI_DATA_W, TEST_AXI_DEST_W, TEST_AXI_ID_W, TEST_RAM_SIZE, TEST_RAM_BASE_ADDR, TEST_RAM_DATA_W, TEST_RAM_ADDR_W, >(raw_axi_ar_r, raw_axi_r_s, raw_ram_rd_req_s, raw_ram_rd_resp_r); From 4fc5ba11d9560c3e1e4422fc523bef703d9b8f93 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Mon, 12 May 2025 20:09:32 +0200 Subject: [PATCH 73/85] modules/zstd: Remove RESET CSR Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/README.md | 14 ++------ xls/modules/zstd/img/ZSTD_decoder_wrapper.png | Bin 123219 -> 113685 bytes xls/modules/zstd/zstd_dec.x | 32 +++++------------- xls/modules/zstd/zstd_dec_test.x | 20 ++--------- 4 files changed, 13 insertions(+), 53 deletions(-) diff --git a/xls/modules/zstd/README.md b/xls/modules/zstd/README.md index 0842d65c49..b60d630408 100644 --- a/xls/modules/zstd/README.md +++ b/xls/modules/zstd/README.md @@ -45,9 +45,8 @@ The registers are defined below: | ---- | ------- | ----------- | | Status | 0x0 | Keeps the code describing the current state of the ZSTD Decoder | | Start | 0x8 | Writing `1` when the decoder is in the `IDLE` state starts the decoding process | -| Reset | 0x10 | Writing `1` will reset the decoder to the `IDLE` state | -| Input Buffer | 0x18 | Keeps the base address for the input buffer that is used for storing the frame to decode | -| Output Buffer | 0x20 | Keeps the base address for the output buffer, ZSTD Decoder will write the decoded frame into memory starting from this address. | +| Input Buffer | 0x10 | Keeps the base address for the input buffer that is used for storing the frame to decode | +| Output Buffer | 0x18 | Keeps the base address for the output buffer, ZSTD Decoder will write the decoded frame into memory starting from this address. | ### Status codes @@ -68,15 +67,6 @@ The following is a list of all available status codes that can be written in the | RAW_BLOCK_ERROR | 10 | Failure in communication with the memory | | RLE_BLOCK_OK | 11 | Successfully decoded RLE data block | -### Reset handling - -The expected behavior of the `Reset` CSR cannot be achieved solely in the DSLX code. -As of [cb2829ab](https://github.com/google/xls/commit/cb2829ab809c58f21d957a47e400456a8c8f8db1), the XLS toolchain does not support resetting the proc network on the DSLX level. -As a workaround for this issue, the `ZstdDec` proc defines a `reset` output channel that sends a pulse when there is a write to the `Reset` CSR. -The Verilog code that integrates the decoder in a target system must connect this output back to the standard `rst` input of the decoder. -If any external reset signal exists and is intended to be used with the decoder, it should be OR-ed with the `reset` channel output before connecting to the decoder's `rst` input. -Please refer to the diagram of the Verilog wrapper in the [Testing Methodology](#testing-methodology) chapter for example reset connection. - ## Controlling the decoder from the software The configuration done by the software must be carried out when the decoder is in the `IDLE` state. diff --git a/xls/modules/zstd/img/ZSTD_decoder_wrapper.png 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z0|LUd-yzsP|70>eJv46L3qs0ui5&-3j#nJl;>?7dg=;$rH}{KOr4!qZe*z{nIw~g5 z_bd_T*!!8euof)!HHp?~^ePc*Ny6&&+eseV&lP7krGuO=(*J}57i0oX34A1mY@1<( znnnPvBgzv3%fC5vlGYow3J18abVeJiT~Yp4{?=_dhRqf<51dR>NEnB@L}F(*v<@yL zyqo4;hf>K!g^QYh4*}Pg@5rx=E*FT4ToJfX!Ms|rT)PL5_CI3qLzqEk1CnbfC;7w` zHrZ9&&@~QD30qQ$E-a2(=ch;oh0KPC6&K-x9a<}>_iY`P07DkI(VL!S$^n2ev3BiBx*m8Q40r^$#tc=D}RXvG{5Jzis zhB3xbAs?f(*eM>Fe!e~5I%^0Di_0M+-q%i zezcVs;ia+xL;%3A%F$o+u5kNG3mq7*KFD)g4sm{SkJ3Mwe>8d3k$Rg;vbo=r9oo$& zeDF@X&Ga0v?W{ws&wy6A%`Nkz0p4>hB=;Wzdk(<1|0QAtRf&ASf-h~9LVw$HP?dnv z6SAV~CjSaFPE0QB3y=#uR{h1l?KRNyKg<8eNS!(qJdoZq$GgA(JL?BCDueh$79eQ< z%CaCzm_U3P`E0}I1fBBliT<;Y|Ln-WW0L=f)_-*5Pt^J!t99ai{x37X-p4rCNc`pa U3>(c: Csr) -> uN[LOG2_REGS_N] { @@ -189,7 +188,6 @@ proc ZstdDecoderInternal< output_mem_wr_resp_r: chan in; notify_s: chan<()> out; - reset_s: chan<()> out; init { zero!() @@ -227,7 +225,6 @@ proc ZstdDecoderInternal< output_mem_wr_resp_r: chan in, notify_s: chan<()> out, - reset_s: chan<()> out, ) { ( csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, @@ -237,7 +234,7 @@ proc ZstdDecoderInternal< rle_req_s, rle_resp_r, comp_block_req_s, comp_block_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, - notify_s, reset_s, + notify_s, ) } @@ -254,12 +251,6 @@ proc ZstdDecoderInternal< let (tok1_0, csr_change, csr_change_valid) = recv_non_blocking(tok0, csr_change_r, zero!()); let is_start = (csr_change_valid && (csr_change.csr == csr(Csr::START))); - let is_reset = (csr_change_valid && (csr_change.csr == csr(Csr::RESET))); - let tok = send_if(tok0, reset_s, is_reset, ()); - if is_reset { - trace_fmt!("[[RESET]]"); - } else {}; - if csr_change_valid { trace_fmt!("[CSR CHANGE] {:#x}", csr_change); } else {}; @@ -721,7 +712,6 @@ proc ZstdDecoderInternalTest { output_mem_wr_resp_s: chan out; notify_r: chan<()> in; - reset_r: chan<()> in; init {} @@ -751,7 +741,6 @@ proc ZstdDecoderInternalTest { let (output_mem_wr_resp_s, output_mem_wr_resp_r) = chan("output_mem_wr_resp"); let (notify_s, notify_r) = chan<()>("notify"); - let (reset_s, reset_r) = chan<()>("reset"); spawn ZstdDecoderInternal( csr_rd_req_s, csr_rd_resp_r, csr_wr_req_s, csr_wr_resp_r, csr_change_r, @@ -761,7 +750,7 @@ proc ZstdDecoderInternalTest { rle_req_s, rle_resp_r, comp_block_req_s, comp_block_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, - notify_s, reset_s, + notify_s, ); ( @@ -773,7 +762,7 @@ proc ZstdDecoderInternalTest { rle_req_r, rle_resp_s, comp_block_req_r, comp_block_resp_s, output_mem_wr_req_r, output_mem_wr_resp_s, - notify_r, reset_r, + notify_r, ) } @@ -1228,7 +1217,6 @@ pub proc ZstdDecoder< ram_wr_resp_7_r: chan in, notify_s: chan<()> out, - reset_s: chan<()> out, ) { const CHANNEL_DEPTH = u32:1; @@ -1458,7 +1446,7 @@ pub proc ZstdDecoder< rle_req_s, rle_resp_r, comp_block_req_s, comp_block_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, - notify_s, reset_s, + notify_s, ); () @@ -1623,7 +1611,6 @@ proc ZstdDecoderInternalInst { // IRQ notify_s: chan<()> out, - reset_s: chan<()> out, ) { spawn ZstdDecoderInternal< INST_AXI_DATA_W, INST_AXI_ADDR_W, INST_REGS_N, @@ -1635,7 +1622,7 @@ proc ZstdDecoderInternalInst { rle_req_s, rle_resp_r, comp_req_s, comp_resp_r, output_mem_wr_req_s, output_mem_wr_resp_r, - notify_s, reset_s, + notify_s, ); } @@ -1834,7 +1821,6 @@ proc ZstdDecoderInst { ram_wr_resp_7_r: chan in, notify_s: chan<()> out, - reset_s: chan<()> out, ) { // FIXME: Remove inline Huffman Weights memory once HuffmanLiteralsDecoder's memory ports are able to be rewritten let (huffman_lit_weights_mem_rd_req_s, huffman_lit_weights_mem_rd_req_r) = chan("huffman_lit_weights_mem_rd_req"); @@ -1906,7 +1892,7 @@ proc ZstdDecoderInst { ram_wr_req_4_s, ram_wr_req_5_s, ram_wr_req_6_s, ram_wr_req_7_s, ram_wr_resp_0_r, ram_wr_resp_1_r, ram_wr_resp_2_r, ram_wr_resp_3_r, ram_wr_resp_4_r, ram_wr_resp_5_r, ram_wr_resp_6_r, ram_wr_resp_7_r, - notify_s, reset_s, + notify_s, ); } diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 423518c268..151d3f15e3 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -311,7 +311,6 @@ proc ZstdDecoderTest { of_def_test_wr_resp_r: chan in; notify_r: chan<()> in; - reset_r: chan<()> in; init {} @@ -354,7 +353,6 @@ proc ZstdDecoderTest { let (hb_ram_wr_resp_s, hb_ram_wr_resp_r) = chan[8]("hb_ram_wr_resp"); let (notify_s, notify_r) = chan<()>("notify"); - let (reset_s, reset_r) = chan<()>("reset"); // Huffman weights memory let (huffman_lit_weights_rd_req_s, huffman_lit_weights_rd_req_r) = chan("huffman_lit_weights_rd_req"); @@ -652,7 +650,7 @@ proc ZstdDecoderTest { hb_ram_wr_resp_r[0], hb_ram_wr_resp_r[1], hb_ram_wr_resp_r[2], hb_ram_wr_resp_r[3], hb_ram_wr_resp_r[4], hb_ram_wr_resp_r[5], hb_ram_wr_resp_r[6], hb_ram_wr_resp_r[7], - notify_s, reset_s, + notify_s, ); unroll_for! (i, ()): (u32, ()) in range(u32:0, u32:8) { @@ -706,7 +704,7 @@ proc ZstdDecoderTest { ll_sel_test_s, ll_def_test_rd_req_s, ll_def_test_rd_resp_r, ll_def_test_wr_req_s, ll_def_test_wr_resp_r, ml_sel_test_s, ml_def_test_rd_req_s, ml_def_test_rd_resp_r, ml_def_test_wr_req_s, ml_def_test_wr_resp_r, of_sel_test_s, of_def_test_rd_req_s, of_def_test_rd_resp_r, of_def_test_wr_req_s, of_def_test_wr_resp_r, - notify_r, reset_r, + notify_r, ) } @@ -792,20 +790,6 @@ proc ZstdDecoderTest { last: u1:1, }; - // reset the decoder - trace_fmt!("Sending reset"); - let tok = send(tok, csr_axi_aw_s, axi::AxiAw { - addr: csr_addr(zstd_dec::Csr::RESET), - ..addr_req - }); - let tok = send(tok, csr_axi_w_s, axi::AxiW { - data: uN[TEST_AXI_DATA_W]:0x1, - ..data_req - }); - trace_fmt!("Sent reset"); - let (tok, _) = recv(tok, csr_axi_b_r); - // Wait for reset notification before issuing further CSR writes - let (tok, _) = recv(tok, reset_r); // configure input buffer address let tok = send(tok, csr_axi_aw_s, axi::AxiAw { addr: csr_addr(zstd_dec::Csr::INPUT_BUFFER), From e4ab1f731ab1c7a86757f84a8bc7c1b9b647be1d Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 8 Apr 2025 10:06:32 +0200 Subject: [PATCH 74/85] modules/zstd: fix bazel targets * Use materialize_internal_fifos when possible * Disable the above option for procs with loopback channels * Add missing module names * Add xls_fifo_wrapper verilog dependency to the synthesis of the procs without materialized internal fifos Signed-off-by: Pawel Czarnecki Co-authored-by: Wojciech Sipak --- xls/modules/zstd/BUILD | 54 +- xls/modules/zstd/rtl/BUILD | 47 ++ xls/modules/zstd/rtl/xls_fifo_wrapper.v | 67 +++ xls/modules/zstd/rtl/zstd_dec_wrapper.v | 743 ++++++++++++++++++++++++ 4 files changed, 896 insertions(+), 15 deletions(-) create mode 100644 xls/modules/zstd/rtl/BUILD create mode 100644 xls/modules/zstd/rtl/xls_fifo_wrapper.v create mode 100644 xls/modules/zstd/rtl/zstd_dec_wrapper.v diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index f364c56bb4..d80a9bb0af 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -42,7 +42,6 @@ common_codegen_args = { "clock_period_ps": CLOCK_PERIOD_PS, "clock_margin_percent": "20", "multi_proc": "true", - "fifo_module": "", "materialize_internal_fifos": "true", } @@ -161,7 +160,7 @@ xls_dslx_test( xls_dslx_verilog( name = "shift_buffer_aligner_verilog", - codegen_args = common_codegen_args, + codegen_args = common_codegen_args | {"module_name": "ShiftBufferAligner"}, dslx_top = "ShiftBufferAlignerInst", library = ":shift_buffer_dslx", tags = ["manual"], @@ -220,6 +219,7 @@ xls_benchmark_verilog( shift_buffer_storage_codegen_args = common_codegen_args | { "clock_period_ps": "0", "pipeline_stages": "2", + "module_name": "ShiftBufferStorage", } xls_dslx_verilog( @@ -285,6 +285,7 @@ SHIFT_BUFFER_CLOCK_PERIOD_PS = "1000" shift_buffer_codegen_args = common_codegen_args | { "clock_period_ps": SHIFT_BUFFER_CLOCK_PERIOD_PS, + "module_name": "ShiftBuffer", } xls_dslx_verilog( @@ -423,7 +424,7 @@ verilog_library( name = "frame_header_dec_verilog_lib", srcs = [ ":frame_header_dec.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -519,7 +520,7 @@ verilog_library( name = "block_header_dec_verilog_lib", srcs = [ ":block_header_dec.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -598,7 +599,7 @@ verilog_library( name = "raw_block_dec_verilog_lib", srcs = [ ":raw_block_dec.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -676,7 +677,7 @@ verilog_library( name = "rle_block_dec_verilog_lib", srcs = [ ":rle_block_dec.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -754,7 +755,7 @@ verilog_library( name = "dec_mux_verilog_lib", srcs = [ ":dec_mux.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -894,7 +895,7 @@ verilog_library( name = "sequence_executor_lib", srcs = [ ":sequence_executor.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -974,7 +975,7 @@ verilog_library( name = "axi_csr_accessor_verilog_lib", srcs = [ ":axi_csr_accessor.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1051,7 +1052,7 @@ verilog_library( name = "csr_config_verilog_lib", srcs = [ ":csr_config.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1106,6 +1107,7 @@ xls_dslx_verilog( "pipeline_stages": "1", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "RamWrRespHandlerInst", library = ":ram_wr_handler_dslx", @@ -1130,7 +1132,7 @@ verilog_library( name = "ram_rw_handler_verilog_lib", srcs = [ ":ram_rw_handler.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1198,6 +1200,7 @@ xls_dslx_verilog( "pipeline_stages": "6", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "FseProbaFreqDecoderInst", library = ":fse_proba_freq_dec_dslx", @@ -1234,7 +1237,7 @@ verilog_library( name = "fse_proba_freq_dec_lib", srcs = [ ":fse_proba_freq_dec.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1284,7 +1287,9 @@ xls_dslx_test( xls_dslx_verilog( name = "literals_block_header_dec_verilog", - codegen_args = window_buffer_codegen_args, + codegen_args = common_codegen_args | { + "module_name": "LiteralsBlockHeaderDecoder", + }, dslx_top = "LiteralsHeaderDecoderInst", library = ":literals_block_header_dec_dslx", tags = ["manual"], @@ -1319,7 +1324,9 @@ xls_dslx_test( xls_dslx_verilog( name = "sequence_conf_dec_verilog", - codegen_args = window_buffer_codegen_args, + codegen_args = common_codegen_args | { + "module_name": "SequenceConfDecoder", + }, dslx_top = "SequenceConfDecoderInst", library = ":sequence_conf_dec_dslx", tags = ["manual"], @@ -1376,7 +1383,7 @@ verilog_library( name = "refilling_shift_buffer_internal_verilog_lib", srcs = [ ":refilling_shift_buffer_internal.v", - ":xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", ], tags = ["manual"], ) @@ -1629,6 +1636,7 @@ xls_dslx_verilog( "pipeline_stages": "1", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "FseTableIterator", library = ":fse_table_iterator_dslx", @@ -1707,6 +1715,7 @@ xls_dslx_verilog( "pipeline_stages": "4", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "FseTableCreatorInst", library = ":fse_table_creator_dslx", @@ -1789,6 +1798,7 @@ xls_dslx_verilog( "pipeline_stages": "2", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "CommandConstructor", library = ":command_constructor_dslx", @@ -1883,6 +1893,7 @@ xls_dslx_verilog( "pipeline_stages": "6", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "RamDemuxInst", library = ":ram_demux_dslx", @@ -1958,6 +1969,7 @@ xls_dslx_verilog( "pipeline_stages": "6", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "RamDemuxNaiveInst", library = ":ram_demux_dslx", @@ -2044,6 +2056,7 @@ xls_dslx_verilog( "pipeline_stages": "8", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "FseDecoderInst", library = ":fse_dec_dslx", @@ -2135,6 +2148,7 @@ xls_dslx_verilog( "reset": "rst", "use_system_verilog": "false", "multi_proc": "true", + "materialize_internal_fifos": "true", }, dslx_top = "RamDemux3Inst", library = ":ram_demux3_dslx", @@ -2243,6 +2257,7 @@ xls_dslx_verilog( "reset": "rst", "use_system_verilog": "false", "multi_proc": "true", + "materialize_internal_fifos": "true", }, dslx_top = "FseLookupCtrlInst", library = ":sequence_dec_dslx", @@ -2288,6 +2303,7 @@ xls_dslx_verilog( "reset": "rst", "worst_case_throughput": "1", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "RleLiteralsDecoderInst", library = ":rle_literals_dec_dslx", @@ -2364,6 +2380,7 @@ xls_dslx_verilog( "pipeline_stages": "1", "reset": "rst", "use_system_verilog": "false", + "materialize_internal_fifos": "true", }, dslx_top = "RawLiteralsDecoderInst", library = ":raw_literals_dec_dslx", @@ -2467,6 +2484,7 @@ xls_dslx_verilog( "worst_case_throughput": "1", "use_system_verilog": "false", "multi_proc": "true", + "materialize_internal_fifos": "true", }, dslx_top = "LiteralsBufferInst", library = ":literals_buffer_dslx", @@ -2632,6 +2650,7 @@ xls_dslx_verilog( "reset": "rst", "worst_case_throughput": "2", "use_system_verilog": "false", + "materialize_internal_fifos": "false", # TODO: set to true once this option works with loopback channels }, dslx_top = "LiteralsDecoderInst", library = ":literals_decoder_dslx", @@ -2671,6 +2690,7 @@ synthesize_rtl( top_module = "LiteralsDecoder", deps = [ ":literals_decoder_verilog_lib", + "//xls/modules/zstd/rtl:xls_fifo_wrapper_verilog_lib", ], ) @@ -2730,6 +2750,7 @@ prescan_codegen_args = common_codegen_args | { "huffman_prescan__internal_write_rsp_r:5", "io_constraints": "huffman_prescan__read_req_s:send:" + "huffman_prescan__read_rsp_r:recv:5:5", + "materialize_internal_fifos": "false", # TODO: remove once this option works with loopback channels } xls_dslx_verilog( @@ -2769,6 +2790,7 @@ synthesize_rtl( top_module = "HuffmanPrescan", deps = [ ":huffman_prescan_verilog_lib", + "//xls/modules/zstd/rtl:xls_fifo_wrapper_verilog_lib", ], ) @@ -3304,6 +3326,7 @@ huffman_literals_dec_codegen_args = common_codegen_args | { "clock_period_ps": "0", "worst_case_throughput": "0", "minimize_worst_case_throughput": "true", + "materialize_internal_fifos": "false", # TODO: remove once this option works with loopback channels } xls_dslx_verilog( @@ -3337,6 +3360,7 @@ synthesize_rtl( top_module = "HuffmanLiteralsDecoder", deps = [ ":huffman_literals_dec_verilog_lib", + "//xls/modules/zstd/rtl:xls_fifo_wrapper_verilog_lib", ], ) diff --git a/xls/modules/zstd/rtl/BUILD b/xls/modules/zstd/rtl/BUILD new file mode 100644 index 0000000000..9ca9c83ee3 --- /dev/null +++ b/xls/modules/zstd/rtl/BUILD @@ -0,0 +1,47 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Collection of simulation sources + +This package exports verilog sources required by the ZSTD Decoder in the verilog +tests. + +The sources contain: + * Wrapper for the ZSTD Decoder used in the verilog tests + * Verilog implementation of the channel fifo + +""" + +load("@rules_hdl//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//xls:xls_users"], + licenses = ["notice"], +) + +exports_files( + [ + "zstd_dec_wrapper.v", + "xls_fifo_wrapper.v", + ], +) + +verilog_library( + name = "xls_fifo_wrapper_verilog_lib", + srcs = [ + ":xls_fifo_wrapper.v", + ], + tags = ["manual"], +) diff --git a/xls/modules/zstd/rtl/xls_fifo_wrapper.v b/xls/modules/zstd/rtl/xls_fifo_wrapper.v new file mode 100644 index 0000000000..ccb60535af --- /dev/null +++ b/xls/modules/zstd/rtl/xls_fifo_wrapper.v @@ -0,0 +1,67 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// simple fifo implementation +module xls_fifo_wrapper ( +clk, rst, +push_ready, push_data, push_valid, +pop_ready, pop_data, pop_valid); + parameter int Width = 32, + Depth = 32, + EnableBypass = 0, + RegisterPushOutputs = 1, + RegisterPopOutputs = 1; + localparam int AddrWidth = $clog2(Depth) + 1; + input wire clk; + input wire rst; + output wire push_ready; + input wire [Width-1:0] push_data; + input wire push_valid; + input wire pop_ready; + output wire [Width-1:0] pop_data; + output wire pop_valid; + + // Require depth be 1 and bypass disabled. + //initial begin + // if (EnableBypass || Depth != 1 || !RegisterPushOutputs || RegisterPopOutputs) begin + // // FIFO configuration not supported. + // $fatal(1); + // end + //end + + + reg [Width-1:0] mem; + reg full; + + assign push_ready = !full; + assign pop_valid = full; + assign pop_data = mem; + + always @(posedge clk) begin + if (rst == 1'b1) begin + full <= 1'b0; + end else begin + if (push_valid && push_ready) begin + mem <= push_data; + full <= 1'b1; + end else if (pop_valid && pop_ready) begin + mem <= mem; + full <= 1'b0; + end else begin + mem <= mem; + full <= full; + end + end + end +endmodule diff --git a/xls/modules/zstd/rtl/zstd_dec_wrapper.v b/xls/modules/zstd/rtl/zstd_dec_wrapper.v new file mode 100644 index 0000000000..8a616f3f23 --- /dev/null +++ b/xls/modules/zstd/rtl/zstd_dec_wrapper.v @@ -0,0 +1,743 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This module wraps the ZSTD Decoder verilog sources generated from DSLX to +// form a DUT with consistent IO. +// The wrapper also contains an AXI crossbar module for merging the traffic +// from multiple AXI Managers comming from the ZSTD Decoder into a single AXI +// master that could be e.g. routed to the memory. + +`default_nettype none + +module zstd_dec_wrapper #( + parameter int AXI_DATA_W = 64, + parameter int AXI_ADDR_W = 16, + parameter int S_AXI_ID_W = 4, + parameter int M_AXI_ID_W = 6, + parameter int AXI_STRB_W = 8, + parameter int AWUSER_WIDTH = 1, + parameter int WUSER_WIDTH = 1, + parameter int BUSER_WIDTH = 1, + parameter int ARUSER_WIDTH = 1, + parameter int RUSER_WIDTH = 1 +) ( + input wire clk, + input wire rst, + + // AXI Manager interface for the memory connection + output wire [M_AXI_ID_W-1:0] memory_axi_aw_awid, + output wire [AXI_ADDR_W-1:0] memory_axi_aw_awaddr, + output wire [7:0] memory_axi_aw_awlen, + output wire [2:0] memory_axi_aw_awsize, + output wire [1:0] memory_axi_aw_awburst, + output wire memory_axi_aw_awlock, + output wire [3:0] memory_axi_aw_awcache, + output wire [2:0] memory_axi_aw_awprot, + output wire [3:0] memory_axi_aw_awqos, + output wire [3:0] memory_axi_aw_awregion, + output wire [AWUSER_WIDTH-1:0] memory_axi_aw_awuser, + output wire memory_axi_aw_awvalid, + input wire memory_axi_aw_awready, + output wire [AXI_DATA_W-1:0] memory_axi_w_wdata, + output wire [AXI_STRB_W-1:0] memory_axi_w_wstrb, + output wire memory_axi_w_wlast, + output wire [WUSER_WIDTH-1:0] memory_axi_w_wuser, + output wire memory_axi_w_wvalid, + input wire memory_axi_w_wready, + input wire [M_AXI_ID_W-1:0] memory_axi_b_bid, + input wire [2:0] memory_axi_b_bresp, + input wire [BUSER_WIDTH-1:0] memory_axi_b_buser, + input wire memory_axi_b_bvalid, + output wire memory_axi_b_bready, + output wire [M_AXI_ID_W-1:0] memory_axi_ar_arid, + output wire [AXI_ADDR_W-1:0] memory_axi_ar_araddr, + output wire [7:0] memory_axi_ar_arlen, + output wire [2:0] memory_axi_ar_arsize, + output wire [1:0] memory_axi_ar_arburst, + output wire memory_axi_ar_arlock, + output wire [3:0] memory_axi_ar_arcache, + output wire [2:0] memory_axi_ar_arprot, + output wire [3:0] memory_axi_ar_arqos, + output wire [3:0] memory_axi_ar_arregion, + output wire [ARUSER_WIDTH-1:0] memory_axi_ar_aruser, + output wire memory_axi_ar_arvalid, + input wire memory_axi_ar_arready, + input wire [M_AXI_ID_W-1:0] memory_axi_r_rid, + input wire [AXI_DATA_W-1:0] memory_axi_r_rdata, + input wire [2:0] memory_axi_r_rresp, + input wire memory_axi_r_rlast, + input wire [RUSER_WIDTH-1:0] memory_axi_r_ruser, + input wire memory_axi_r_rvalid, + output wire memory_axi_r_rready, + + // AXI Subordinate interface for the CSR access + input wire [S_AXI_ID_W-1:0] csr_axi_aw_awid, + input wire [AXI_ADDR_W-1:0] csr_axi_aw_awaddr, + input wire [7:0] csr_axi_aw_awlen, + input wire [2:0] csr_axi_aw_awsize, + input wire [1:0] csr_axi_aw_awburst, + input wire csr_axi_aw_awlock, + input wire [3:0] csr_axi_aw_awcache, + input wire [2:0] csr_axi_aw_awprot, + input wire [3:0] csr_axi_aw_awqos, + input wire [3:0] csr_axi_aw_awregion, + input wire [AWUSER_WIDTH-1:0] csr_axi_aw_awuser, + input wire csr_axi_aw_awvalid, + output wire csr_axi_aw_awready, + input wire [AXI_DATA_W-1:0] csr_axi_w_wdata, + input wire [AXI_STRB_W-1:0] csr_axi_w_wstrb, + input wire csr_axi_w_wlast, + input wire [WUSER_WIDTH-1:0] csr_axi_w_wuser, + input wire csr_axi_w_wvalid, + output wire csr_axi_w_wready, + output wire [S_AXI_ID_W-1:0] csr_axi_b_bid, + output wire [2:0] csr_axi_b_bresp, + output wire [BUSER_WIDTH-1:0] csr_axi_b_buser, + output wire csr_axi_b_bvalid, + input wire csr_axi_b_bready, + input wire [S_AXI_ID_W-1:0] csr_axi_ar_arid, + input wire [AXI_ADDR_W-1:0] csr_axi_ar_araddr, + input wire [7:0] csr_axi_ar_arlen, + input wire [2:0] csr_axi_ar_arsize, + input wire [1:0] csr_axi_ar_arburst, + input wire csr_axi_ar_arlock, + input wire [3:0] csr_axi_ar_arcache, + input wire [2:0] csr_axi_ar_arprot, + input wire [3:0] csr_axi_ar_arqos, + input wire [3:0] csr_axi_ar_arregion, + input wire [ARUSER_WIDTH-1:0] csr_axi_ar_aruser, + input wire csr_axi_ar_arvalid, + output wire csr_axi_ar_arready, + output wire [S_AXI_ID_W-1:0] csr_axi_r_rid, + output wire [AXI_DATA_W-1:0] csr_axi_r_rdata, + output wire [2:0] csr_axi_r_rresp, + output wire csr_axi_r_rlast, + output wire [RUSER_WIDTH-1:0] csr_axi_r_ruser, + output wire csr_axi_r_rvalid, + input wire csr_axi_r_rready, + + output wire notify_data, + output wire notify_vld, + input wire notify_rdy +); + + /* + * MemReader AXI interfaces + */ + // RawBlockDecoder + wire raw_block_decoder_axi_ar_arvalid; + wire raw_block_decoder_axi_ar_arready; + wire [S_AXI_ID_W-1:0] raw_block_decoder_axi_ar_arid; + wire [AXI_ADDR_W-1:0] raw_block_decoder_axi_ar_araddr; + wire [ 3:0] raw_block_decoder_axi_ar_arregion; + wire [ 7:0] raw_block_decoder_axi_ar_arlen; + wire [ 2:0] raw_block_decoder_axi_ar_arsize; + wire [ 1:0] raw_block_decoder_axi_ar_arburst; + wire [ 3:0] raw_block_decoder_axi_ar_arcache; + wire [ 2:0] raw_block_decoder_axi_ar_arprot; + wire [ 3:0] raw_block_decoder_axi_ar_arqos; + + wire raw_block_decoder_axi_r_rvalid; + wire raw_block_decoder_axi_r_rready; + wire [S_AXI_ID_W-1:0] raw_block_decoder_axi_r_rid; + wire [AXI_DATA_W-1:0] raw_block_decoder_axi_r_rdata; + wire [ 2:0] raw_block_decoder_axi_r_rresp; + wire raw_block_decoder_axi_r_rlast; + + + // BlockHeaderDecoder + wire block_header_decoder_axi_ar_arvalid; + wire block_header_decoder_axi_ar_arready; + wire [S_AXI_ID_W-1:0] block_header_decoder_axi_ar_arid; + wire [AXI_ADDR_W-1:0] block_header_decoder_axi_ar_araddr; + wire [ 3:0] block_header_decoder_axi_ar_arregion; + wire [ 7:0] block_header_decoder_axi_ar_arlen; + wire [ 2:0] block_header_decoder_axi_ar_arsize; + wire [ 1:0] block_header_decoder_axi_ar_arburst; + wire [ 3:0] block_header_decoder_axi_ar_arcache; + wire [ 2:0] block_header_decoder_axi_ar_arprot; + wire [ 3:0] block_header_decoder_axi_ar_arqos; + + wire block_header_decoder_axi_r_rvalid; + wire block_header_decoder_axi_r_rready; + wire [S_AXI_ID_W-1:0] block_header_decoder_axi_r_rid; + wire [AXI_DATA_W-1:0] block_header_decoder_axi_r_rdata; + wire [ 2:0] block_header_decoder_axi_r_rresp; + wire block_header_decoder_axi_r_rlast; + + + // FrameHeaderDecoder + wire frame_header_decoder_axi_ar_arvalid; + wire frame_header_decoder_axi_ar_arready; + wire [S_AXI_ID_W-1:0] frame_header_decoder_axi_ar_arid; + wire [AXI_ADDR_W-1:0] frame_header_decoder_axi_ar_araddr; + wire [ 3:0] frame_header_decoder_axi_ar_arregion; + wire [ 7:0] frame_header_decoder_axi_ar_arlen; + wire [ 2:0] frame_header_decoder_axi_ar_arsize; + wire [ 1:0] frame_header_decoder_axi_ar_arburst; + wire [ 3:0] frame_header_decoder_axi_ar_arcache; + wire [ 2:0] frame_header_decoder_axi_ar_arprot; + wire [ 3:0] frame_header_decoder_axi_ar_arqos; + + wire frame_header_decoder_axi_r_rvalid; + wire frame_header_decoder_axi_r_rready; + wire [S_AXI_ID_W-1:0] frame_header_decoder_axi_r_rid; + wire [AXI_DATA_W-1:0] frame_header_decoder_axi_r_rdata; + wire [ 2:0] frame_header_decoder_axi_r_rresp; + wire frame_header_decoder_axi_r_rlast; + + + /* + * MemWriter AXI interfaces + */ + + // Output Writer + wire [S_AXI_ID_W-1:0] output_axi_aw_awid; + wire [AXI_ADDR_W-1:0] output_axi_aw_awaddr; + wire [ 2:0] output_axi_aw_awsize; + wire [ 7:0] output_axi_aw_awlen; + wire [ 1:0] output_axi_aw_awburst; + wire output_axi_aw_awvalid; + wire output_axi_aw_awready; + + wire [AXI_DATA_W-1:0] output_axi_w_wdata; + wire [AXI_STRB_W-1:0] output_axi_w_wstrb; + wire output_axi_w_wlast; + wire output_axi_w_wvalid; + wire output_axi_w_wready; + + wire [S_AXI_ID_W-1:0] output_axi_b_bid; + wire [ 2:0] output_axi_b_bresp; + wire output_axi_b_bvalid; + wire output_axi_b_bready; + + /* + * XLS Channels representing AXI interfaces + */ + + localparam int XlsAxiAwW = AXI_ADDR_W + S_AXI_ID_W + 3 + 2 + 8; + localparam int XlsAxiWW = AXI_DATA_W + AXI_STRB_W + 1; + localparam int XlsAxiBW = 3 + S_AXI_ID_W; + localparam int XlsAxiArW = S_AXI_ID_W + AXI_ADDR_W + 4 + 8 + 3 + 2 + 4 + 3 + 4; + localparam int XlsAxiRW = S_AXI_ID_W + AXI_DATA_W + 3 + 1; + // CSR + wire [XlsAxiAwW-1:0] zstd_dec__csr_axi_aw; + wire zstd_dec__csr_axi_aw_rdy; + wire zstd_dec__csr_axi_aw_vld; + wire [XlsAxiWW-1:0] zstd_dec__csr_axi_w; + wire zstd_dec__csr_axi_w_rdy; + wire zstd_dec__csr_axi_w_vld; + wire [ XlsAxiBW-1:0] zstd_dec__csr_axi_b; + wire zstd_dec__csr_axi_b_rdy; + wire zstd_dec__csr_axi_b_vld; + wire [XlsAxiArW-1:0] zstd_dec__csr_axi_ar; + wire zstd_dec__csr_axi_ar_rdy; + wire zstd_dec__csr_axi_ar_vld; + wire [ XlsAxiRW-1:0] zstd_dec__csr_axi_r; + wire zstd_dec__csr_axi_r_rdy; + wire zstd_dec__csr_axi_r_vld; + + // Frame Header Decoder + wire [XlsAxiArW-1:0] zstd_dec__fh_axi_ar; + wire zstd_dec__fh_axi_ar_rdy; + wire zstd_dec__fh_axi_ar_vld; + wire [ XlsAxiRW-1:0] zstd_dec__fh_axi_r; + wire zstd_dec__fh_axi_r_rdy; + wire zstd_dec__fh_axi_r_vld; + + // Block Header Decoder + wire [XlsAxiArW-1:0] zstd_dec__bh_axi_ar; + wire zstd_dec__bh_axi_ar_rdy; + wire zstd_dec__bh_axi_ar_vld; + wire [ XlsAxiRW-1:0] zstd_dec__bh_axi_r; + wire zstd_dec__bh_axi_r_rdy; + wire zstd_dec__bh_axi_r_vld; + + // Raw Block Decoder + wire [XlsAxiArW-1:0] zstd_dec__raw_axi_ar; + wire zstd_dec__raw_axi_ar_rdy; + wire zstd_dec__raw_axi_ar_vld; + wire [ XlsAxiRW-1:0] zstd_dec__raw_axi_r; + wire zstd_dec__raw_axi_r_rdy; + wire zstd_dec__raw_axi_r_vld; + + // Output Memory Interface + wire [XlsAxiAwW-1:0] zstd_dec__output_axi_aw; + wire zstd_dec__output_axi_aw_rdy; + wire zstd_dec__output_axi_aw_vld; + wire [XlsAxiWW-1:0] zstd_dec__output_axi_w; + wire zstd_dec__output_axi_w_rdy; + wire zstd_dec__output_axi_w_vld; + wire [XlsAxiBW-1:0] zstd_dec__output_axi_b; + wire zstd_dec__output_axi_b_rdy; + wire zstd_dec__output_axi_b_vld; + + /* + * Mapping XLS Channels to AXI channels fields + */ + + // CSR + assign zstd_dec__csr_axi_aw = { + csr_axi_aw_awid, + csr_axi_aw_awaddr, + csr_axi_aw_awsize, + csr_axi_aw_awlen, + csr_axi_aw_awburst + }; + assign zstd_dec__csr_axi_aw_vld = csr_axi_aw_awvalid; + assign csr_axi_aw_awready = zstd_dec__csr_axi_aw_rdy; + assign zstd_dec__csr_axi_w = { + csr_axi_w_wdata, + csr_axi_w_wstrb, + csr_axi_w_wlast + }; + assign zstd_dec__csr_axi_w_vld = csr_axi_w_wvalid; + assign csr_axi_w_wready = zstd_dec__csr_axi_w_rdy; + assign { + csr_axi_b_bresp, + csr_axi_b_bid + } = zstd_dec__csr_axi_b; + assign csr_axi_b_bvalid = zstd_dec__csr_axi_b_vld; + assign zstd_dec__csr_axi_b_rdy = csr_axi_b_bready; + assign zstd_dec__csr_axi_ar = { + csr_axi_ar_arid, + csr_axi_ar_araddr, + csr_axi_ar_arregion, + csr_axi_ar_arlen, + csr_axi_ar_arsize, + csr_axi_ar_arburst, + csr_axi_ar_arcache, + csr_axi_ar_arprot, + csr_axi_ar_arqos + }; + assign zstd_dec__csr_axi_ar_vld = csr_axi_ar_arvalid; + assign csr_axi_ar_arready = zstd_dec__csr_axi_ar_rdy; + assign { + csr_axi_r_rid, + csr_axi_r_rdata, + csr_axi_r_rresp, + csr_axi_r_rlast + } = zstd_dec__csr_axi_r; + assign csr_axi_r_rvalid = zstd_dec__csr_axi_r_vld; + assign zstd_dec__csr_axi_r_rdy = csr_axi_r_rready; + + // Frame Header Decoder + assign { + frame_header_decoder_axi_ar_arid, + frame_header_decoder_axi_ar_araddr, + frame_header_decoder_axi_ar_arregion, + frame_header_decoder_axi_ar_arlen, + frame_header_decoder_axi_ar_arsize, + frame_header_decoder_axi_ar_arburst, + frame_header_decoder_axi_ar_arcache, + frame_header_decoder_axi_ar_arprot, + frame_header_decoder_axi_ar_arqos + } = zstd_dec__fh_axi_ar; + assign frame_header_decoder_axi_ar_arvalid = zstd_dec__fh_axi_ar_vld; + assign zstd_dec__fh_axi_ar_rdy = frame_header_decoder_axi_ar_arready; + assign zstd_dec__fh_axi_r = { + frame_header_decoder_axi_r_rid, + frame_header_decoder_axi_r_rdata, + frame_header_decoder_axi_r_rresp, + frame_header_decoder_axi_r_rlast}; + assign zstd_dec__fh_axi_r_vld = frame_header_decoder_axi_r_rvalid; + assign frame_header_decoder_axi_r_rready = zstd_dec__fh_axi_r_rdy; + + // Block Header Decoder + assign { + block_header_decoder_axi_ar_arid, + block_header_decoder_axi_ar_araddr, + block_header_decoder_axi_ar_arregion, + block_header_decoder_axi_ar_arlen, + block_header_decoder_axi_ar_arsize, + block_header_decoder_axi_ar_arburst, + block_header_decoder_axi_ar_arcache, + block_header_decoder_axi_ar_arprot, + block_header_decoder_axi_ar_arqos + } = zstd_dec__bh_axi_ar; + assign block_header_decoder_axi_ar_arvalid = zstd_dec__bh_axi_ar_vld; + assign zstd_dec__bh_axi_ar_rdy = block_header_decoder_axi_ar_arready; + assign zstd_dec__bh_axi_r = { + block_header_decoder_axi_r_rid, + block_header_decoder_axi_r_rdata, + block_header_decoder_axi_r_rresp, + block_header_decoder_axi_r_rlast}; + assign zstd_dec__bh_axi_r_vld = block_header_decoder_axi_r_rvalid; + assign block_header_decoder_axi_r_rready = zstd_dec__bh_axi_r_rdy; + + // Raw Block Decoder + assign { + raw_block_decoder_axi_ar_arid, + raw_block_decoder_axi_ar_araddr, + raw_block_decoder_axi_ar_arregion, + raw_block_decoder_axi_ar_arlen, + raw_block_decoder_axi_ar_arsize, + raw_block_decoder_axi_ar_arburst, + raw_block_decoder_axi_ar_arcache, + raw_block_decoder_axi_ar_arprot, + raw_block_decoder_axi_ar_arqos + } = zstd_dec__raw_axi_ar; + assign raw_block_decoder_axi_ar_arvalid = zstd_dec__raw_axi_ar_vld; + assign zstd_dec__raw_axi_ar_rdy = raw_block_decoder_axi_ar_arready; + assign zstd_dec__raw_axi_r = { + raw_block_decoder_axi_r_rid, + raw_block_decoder_axi_r_rdata, + raw_block_decoder_axi_r_rresp, + raw_block_decoder_axi_r_rlast}; + assign zstd_dec__raw_axi_r_vld = raw_block_decoder_axi_r_rvalid; + assign raw_block_decoder_axi_r_rready = zstd_dec__raw_axi_r_rdy; + + // Output Writer + assign { + output_axi_aw_awid, + output_axi_aw_awaddr, + output_axi_aw_awsize, + output_axi_aw_awlen, + output_axi_aw_awburst + } = zstd_dec__output_axi_aw; + assign output_axi_aw_awvalid = zstd_dec__output_axi_aw_vld; + assign zstd_dec__output_axi_aw_rdy = output_axi_aw_awready; + assign { + output_axi_w_wdata, + output_axi_w_wstrb, + output_axi_w_wlast + } = zstd_dec__output_axi_w; + assign output_axi_w_wvalid = zstd_dec__output_axi_w_vld; + assign zstd_dec__output_axi_w_rdy = output_axi_w_wready; + assign zstd_dec__output_axi_b = { + output_axi_b_bresp, + output_axi_b_bid + }; + assign zstd_dec__output_axi_b_vld = output_axi_b_bvalid; + assign output_axi_b_bready = zstd_dec__output_axi_b_rdy; + + assign csr_axi_b_buser = 1'b0; + assign csr_axi_r_ruser = 1'b0; + assign notify_data = notify_vld; + + /* + * ZSTD Decoder instance + */ + ZstdDecoder ZstdDecoder ( + .clk(clk), + .rst(rst), + + // CSR Interface + .zstd_dec__csr_axi_aw_r(zstd_dec__csr_axi_aw), + .zstd_dec__csr_axi_aw_r_vld(zstd_dec__csr_axi_aw_vld), + .zstd_dec__csr_axi_aw_r_rdy(zstd_dec__csr_axi_aw_rdy), + .zstd_dec__csr_axi_w_r(zstd_dec__csr_axi_w), + .zstd_dec__csr_axi_w_r_vld(zstd_dec__csr_axi_w_vld), + .zstd_dec__csr_axi_w_r_rdy(zstd_dec__csr_axi_w_rdy), + .zstd_dec__csr_axi_b_s(zstd_dec__csr_axi_b), + .zstd_dec__csr_axi_b_s_vld(zstd_dec__csr_axi_b_vld), + .zstd_dec__csr_axi_b_s_rdy(zstd_dec__csr_axi_b_rdy), + .zstd_dec__csr_axi_ar_r(zstd_dec__csr_axi_ar), + .zstd_dec__csr_axi_ar_r_vld(zstd_dec__csr_axi_ar_vld), + .zstd_dec__csr_axi_ar_r_rdy(zstd_dec__csr_axi_ar_rdy), + .zstd_dec__csr_axi_r_s(zstd_dec__csr_axi_r), + .zstd_dec__csr_axi_r_s_vld(zstd_dec__csr_axi_r_vld), + .zstd_dec__csr_axi_r_s_rdy(zstd_dec__csr_axi_r_rdy), + + // FrameHeaderDecoder + .zstd_dec__fh_axi_ar_s(zstd_dec__fh_axi_ar), + .zstd_dec__fh_axi_ar_s_vld(zstd_dec__fh_axi_ar_vld), + .zstd_dec__fh_axi_ar_s_rdy(zstd_dec__fh_axi_ar_rdy), + .zstd_dec__fh_axi_r_r(zstd_dec__fh_axi_r), + .zstd_dec__fh_axi_r_r_vld(zstd_dec__fh_axi_r_vld), + .zstd_dec__fh_axi_r_r_rdy(zstd_dec__fh_axi_r_rdy), + + // BlockHeaderDecoder + .zstd_dec__bh_axi_ar_s(zstd_dec__bh_axi_ar), + .zstd_dec__bh_axi_ar_s_vld(zstd_dec__bh_axi_ar_vld), + .zstd_dec__bh_axi_ar_s_rdy(zstd_dec__bh_axi_ar_rdy), + .zstd_dec__bh_axi_r_r(zstd_dec__bh_axi_r), + .zstd_dec__bh_axi_r_r_vld(zstd_dec__bh_axi_r_vld), + .zstd_dec__bh_axi_r_r_rdy(zstd_dec__bh_axi_r_rdy), + + // RawBlockDecoder + .zstd_dec__raw_axi_ar_s(zstd_dec__raw_axi_ar), + .zstd_dec__raw_axi_ar_s_vld(zstd_dec__raw_axi_ar_vld), + .zstd_dec__raw_axi_ar_s_rdy(zstd_dec__raw_axi_ar_rdy), + .zstd_dec__raw_axi_r_r(zstd_dec__raw_axi_r), + .zstd_dec__raw_axi_r_r_vld(zstd_dec__raw_axi_r_vld), + .zstd_dec__raw_axi_r_r_rdy(zstd_dec__raw_axi_r_rdy), + + // Output Writer + .zstd_dec__output_axi_aw_s(zstd_dec__output_axi_aw), + .zstd_dec__output_axi_aw_s_vld(zstd_dec__output_axi_aw_vld), + .zstd_dec__output_axi_aw_s_rdy(zstd_dec__output_axi_aw_rdy), + .zstd_dec__output_axi_w_s(zstd_dec__output_axi_w), + .zstd_dec__output_axi_w_s_vld(zstd_dec__output_axi_w_vld), + .zstd_dec__output_axi_w_s_rdy(zstd_dec__output_axi_w_rdy), + .zstd_dec__output_axi_b_r(zstd_dec__output_axi_b), + .zstd_dec__output_axi_b_r_vld(zstd_dec__output_axi_b_vld), + .zstd_dec__output_axi_b_r_rdy(zstd_dec__output_axi_b_rdy), + + // Other ports + .zstd_dec__notify_s_vld(notify_vld), + .zstd_dec__notify_s_rdy(notify_rdy) + ); + + assign frame_header_decoder_axi_r_rresp[2] = '0; + assign block_header_decoder_axi_r_rresp[2] = '0; + assign raw_block_decoder_axi_r_rresp[2] = '0; + assign output_axi_b_bresp[2] = '0; + assign memory_axi_b_bresp[2] = '0; + assign memory_axi_r_rresp[2] = '0; + /* + * AXI Interconnect + */ + axi_crossbar_wrapper #( + .DATA_WIDTH(AXI_DATA_W), + .ADDR_WIDTH(AXI_ADDR_W), + .M00_ADDR_WIDTH(AXI_ADDR_W), + .M00_BASE_ADDR(32'd0), + .STRB_WIDTH(AXI_STRB_W), + .S_ID_WIDTH(S_AXI_ID_W), + .M_ID_WIDTH(M_AXI_ID_W) + ) axi_memory_interconnect ( + .clk(clk), + .rst(rst), + + /* + * AXI Subordinate interfaces + */ + // FrameHeaderDecoder + .s00_axi_awid('0), + .s00_axi_awaddr('0), + .s00_axi_awlen('0), + .s00_axi_awsize('0), + .s00_axi_awburst('0), + .s00_axi_awlock('0), + .s00_axi_awcache('0), + .s00_axi_awprot('0), + .s00_axi_awqos('0), + .s00_axi_awuser('0), + .s00_axi_awvalid('0), + .s00_axi_awready(), + .s00_axi_wdata('0), + .s00_axi_wstrb('0), + .s00_axi_wlast('0), + .s00_axi_wuser('0), + .s00_axi_wvalid(), + .s00_axi_wready(), + .s00_axi_bid(), + .s00_axi_bresp(), + .s00_axi_buser(), + .s00_axi_bvalid(), + .s00_axi_bready('0), + .s00_axi_arid(frame_header_decoder_axi_ar_arid), + .s00_axi_araddr(frame_header_decoder_axi_ar_araddr), + .s00_axi_arlen(frame_header_decoder_axi_ar_arlen), + .s00_axi_arsize(frame_header_decoder_axi_ar_arsize), + .s00_axi_arburst(frame_header_decoder_axi_ar_arburst), + .s00_axi_arlock('0), + .s00_axi_arcache(frame_header_decoder_axi_ar_arcache), + .s00_axi_arprot(frame_header_decoder_axi_ar_arprot), + .s00_axi_arqos(frame_header_decoder_axi_ar_arqos), + .s00_axi_aruser('0), + .s00_axi_arvalid(frame_header_decoder_axi_ar_arvalid), + .s00_axi_arready(frame_header_decoder_axi_ar_arready), + .s00_axi_rid(frame_header_decoder_axi_r_rid), + .s00_axi_rdata(frame_header_decoder_axi_r_rdata), + .s00_axi_rresp(frame_header_decoder_axi_r_rresp[1:0]), + .s00_axi_rlast(frame_header_decoder_axi_r_rlast), + .s00_axi_ruser(), + .s00_axi_rvalid(frame_header_decoder_axi_r_rvalid), + .s00_axi_rready(frame_header_decoder_axi_r_rready), + + // BlockHeaderDecoder + .s01_axi_awid('0), + .s01_axi_awaddr('0), + .s01_axi_awlen('0), + .s01_axi_awsize('0), + .s01_axi_awburst('0), + .s01_axi_awlock('0), + .s01_axi_awcache('0), + .s01_axi_awprot('0), + .s01_axi_awqos('0), + .s01_axi_awuser('0), + .s01_axi_awvalid('0), + .s01_axi_awready(), + .s01_axi_wdata('0), + .s01_axi_wstrb('0), + .s01_axi_wlast('0), + .s01_axi_wuser('0), + .s01_axi_wvalid(), + .s01_axi_wready(), + .s01_axi_bid(), + .s01_axi_bresp(), + .s01_axi_buser(), + .s01_axi_bvalid(), + .s01_axi_bready('0), + .s01_axi_arid(block_header_decoder_axi_ar_arid), + .s01_axi_araddr(block_header_decoder_axi_ar_araddr), + .s01_axi_arlen(block_header_decoder_axi_ar_arlen), + .s01_axi_arsize(block_header_decoder_axi_ar_arsize), + .s01_axi_arburst(block_header_decoder_axi_ar_arburst), + .s01_axi_arlock('0), + .s01_axi_arcache(block_header_decoder_axi_ar_arcache), + .s01_axi_arprot(block_header_decoder_axi_ar_arprot), + .s01_axi_arqos(block_header_decoder_axi_ar_arqos), + .s01_axi_aruser('0), + .s01_axi_arvalid(block_header_decoder_axi_ar_arvalid), + .s01_axi_arready(block_header_decoder_axi_ar_arready), + .s01_axi_rid(block_header_decoder_axi_r_rid), + .s01_axi_rdata(block_header_decoder_axi_r_rdata), + .s01_axi_rresp(block_header_decoder_axi_r_rresp[1:0]), + .s01_axi_rlast(block_header_decoder_axi_r_rlast), + .s01_axi_ruser(), + .s01_axi_rvalid(block_header_decoder_axi_r_rvalid), + .s01_axi_rready(block_header_decoder_axi_r_rready), + + // RawBlockDecoder + .s02_axi_awid('0), + .s02_axi_awaddr('0), + .s02_axi_awlen('0), + .s02_axi_awsize('0), + .s02_axi_awburst('0), + .s02_axi_awlock('0), + .s02_axi_awcache('0), + .s02_axi_awprot('0), + .s02_axi_awqos('0), + .s02_axi_awuser('0), + .s02_axi_awvalid('0), + .s02_axi_awready(), + .s02_axi_wdata('0), + .s02_axi_wstrb('0), + .s02_axi_wlast('0), + .s02_axi_wuser('0), + .s02_axi_wvalid(), + .s02_axi_wready(), + .s02_axi_bid(), + .s02_axi_bresp(), + .s02_axi_buser(), + .s02_axi_bvalid(), + .s02_axi_bready('0), + .s02_axi_arid(raw_block_decoder_axi_ar_arid), + .s02_axi_araddr(raw_block_decoder_axi_ar_araddr), + .s02_axi_arlen(raw_block_decoder_axi_ar_arlen), + .s02_axi_arsize(raw_block_decoder_axi_ar_arsize), + .s02_axi_arburst(raw_block_decoder_axi_ar_arburst), + .s02_axi_arlock('0), + .s02_axi_arcache(raw_block_decoder_axi_ar_arcache), + .s02_axi_arprot(raw_block_decoder_axi_ar_arprot), + .s02_axi_arqos(raw_block_decoder_axi_ar_arqos), + .s02_axi_aruser('0), + .s02_axi_arvalid(raw_block_decoder_axi_ar_arvalid), + .s02_axi_arready(raw_block_decoder_axi_ar_arready), + .s02_axi_rid(raw_block_decoder_axi_r_rid), + .s02_axi_rdata(raw_block_decoder_axi_r_rdata), + .s02_axi_rresp(raw_block_decoder_axi_r_rresp[1:0]), + .s02_axi_rlast(raw_block_decoder_axi_r_rlast), + .s02_axi_ruser(), + .s02_axi_rvalid(raw_block_decoder_axi_r_rvalid), + .s02_axi_rready(raw_block_decoder_axi_r_rready), + + // SequenceExecutor + .s03_axi_awid(output_axi_aw_awid), + .s03_axi_awaddr(output_axi_aw_awaddr), + .s03_axi_awlen(output_axi_aw_awlen), + .s03_axi_awsize(output_axi_aw_awsize), + .s03_axi_awburst(output_axi_aw_awburst), + .s03_axi_awlock('0), + .s03_axi_awcache('0), + .s03_axi_awprot('0), + .s03_axi_awqos('0), + .s03_axi_awuser('0), + .s03_axi_awvalid(output_axi_aw_awvalid), + .s03_axi_awready(output_axi_aw_awready), + .s03_axi_wdata(output_axi_w_wdata), + .s03_axi_wstrb(output_axi_w_wstrb), + .s03_axi_wlast(output_axi_w_wlast), + .s03_axi_wuser('0), + .s03_axi_wvalid(output_axi_w_wvalid), + .s03_axi_wready(output_axi_w_wready), + .s03_axi_bid(output_axi_b_bid), + .s03_axi_bresp(output_axi_b_bresp), + .s03_axi_buser(), + .s03_axi_bvalid(output_axi_b_bvalid), + .s03_axi_bready(output_axi_b_bready), + .s03_axi_arid('0), + .s03_axi_araddr('0), + .s03_axi_arlen('0), + .s03_axi_arsize('0), + .s03_axi_arburst('0), + .s03_axi_arlock('0), + .s03_axi_arcache('0), + .s03_axi_arprot('0), + .s03_axi_arqos('0), + .s03_axi_aruser('0), + .s03_axi_arvalid('0), + .s03_axi_arready(), + .s03_axi_rid(), + .s03_axi_rdata(), + .s03_axi_rresp(), + .s03_axi_rlast(), + .s03_axi_ruser(), + .s03_axi_rvalid(), + .s03_axi_rready('0), + + /* + * AXI Manager interface + */ + // Outside-facing AXI interface of the ZSTD Decoder + .m00_axi_awid(memory_axi_aw_awid), + .m00_axi_awaddr(memory_axi_aw_awaddr), + .m00_axi_awlen(memory_axi_aw_awlen), + .m00_axi_awsize(memory_axi_aw_awsize), + .m00_axi_awburst(memory_axi_aw_awburst), + .m00_axi_awlock(memory_axi_aw_awlock), + .m00_axi_awcache(memory_axi_aw_awcache), + .m00_axi_awprot(memory_axi_aw_awprot), + .m00_axi_awqos(memory_axi_aw_awqos), + .m00_axi_awregion(memory_axi_aw_awregion), + .m00_axi_awuser(memory_axi_aw_awuser), + .m00_axi_awvalid(memory_axi_aw_awvalid), + .m00_axi_awready(memory_axi_aw_awready), + .m00_axi_wdata(memory_axi_w_wdata), + .m00_axi_wstrb(memory_axi_w_wstrb), + .m00_axi_wlast(memory_axi_w_wlast), + .m00_axi_wuser(memory_axi_w_wuser), + .m00_axi_wvalid(memory_axi_w_wvalid), + .m00_axi_wready(memory_axi_w_wready), + .m00_axi_bid(memory_axi_b_bid), + .m00_axi_bresp(memory_axi_b_bresp[1:0]), + .m00_axi_buser(memory_axi_b_buser), + .m00_axi_bvalid(memory_axi_b_bvalid), + .m00_axi_bready(memory_axi_b_bready), + .m00_axi_arid(memory_axi_ar_arid), + .m00_axi_araddr(memory_axi_ar_araddr), + .m00_axi_arlen(memory_axi_ar_arlen), + .m00_axi_arsize(memory_axi_ar_arsize), + .m00_axi_arburst(memory_axi_ar_arburst), + .m00_axi_arlock(memory_axi_ar_arlock), + .m00_axi_arcache(memory_axi_ar_arcache), + .m00_axi_arprot(memory_axi_ar_arprot), + .m00_axi_arqos(memory_axi_ar_arqos), + .m00_axi_arregion(memory_axi_ar_arregion), + .m00_axi_aruser(memory_axi_ar_aruser), + .m00_axi_arvalid(memory_axi_ar_arvalid), + .m00_axi_arready(memory_axi_ar_arready), + .m00_axi_rid(memory_axi_r_rid), + .m00_axi_rdata(memory_axi_r_rdata), + .m00_axi_rresp(memory_axi_r_rresp[1:0]), + .m00_axi_rlast(memory_axi_r_rlast), + .m00_axi_ruser(memory_axi_r_ruser), + .m00_axi_rvalid(memory_axi_r_rvalid), + .m00_axi_rready(memory_axi_r_rready) + ); + +endmodule : zstd_dec_wrapper From bc0808e8a90e107ace1c4f721258d9ece07539e9 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Wed, 9 Apr 2025 16:15:03 +0200 Subject: [PATCH 75/85] CI/modules-zstd: Remove step for running CC tests No longer applicable - there are no CC tests in ZSTD module Signed-off-by: Pawel Czarnecki --- .github/workflows/modules-zstd.yml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/.github/workflows/modules-zstd.yml b/.github/workflows/modules-zstd.yml index 4cd6162fa7..f82b5cd010 100644 --- a/.github/workflows/modules-zstd.yml +++ b/.github/workflows/modules-zstd.yml @@ -47,11 +47,6 @@ jobs: run: | bazel test -c opt --test_output=errors -- $(bazel query 'filter(".*_dslx_test", kind(rule, //xls/modules/zstd/...))') - - name: Test ZSTD Module - CC Tests (opt) - if: ${{ !cancelled() }} - run: | - bazel test -c opt --test_output=errors -- $(bazel query 'filter(".*_cc_test", kind(rule, //xls/modules/zstd/...))') - - name: Build ZSTD verilog targets (opt) if: ${{ !cancelled() }} run: | From 4f2e1891eb14b2153afa9185933119e45d8f501e Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Tue, 13 May 2025 18:59:46 +0200 Subject: [PATCH 76/85] modules/zstd: add license Signed-off-by: Wojciech Sipak --- xls/modules/zstd/data/comp_frame.x | 14 ++++++++++++++ xls/modules/zstd/data/comp_frame_fse_comp.x | 14 ++++++++++++++ xls/modules/zstd/data/comp_frame_fse_repeated.x | 14 ++++++++++++++ xls/modules/zstd/data/comp_frame_huffman.x | 14 ++++++++++++++ xls/modules/zstd/data/comp_frame_huffman_fse.x | 14 ++++++++++++++ 5 files changed, 70 insertions(+) diff --git a/xls/modules/zstd/data/comp_frame.x b/xls/modules/zstd/data/comp_frame.x index 8376d6bf1d..399c7258f2 100644 --- a/xls/modules/zstd/data/comp_frame.x +++ b/xls/modules/zstd/data/comp_frame.x @@ -1,3 +1,17 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + pub struct DataArray{ data: uN[BITS_PER_WORD][LENGTH], length: u32, diff --git a/xls/modules/zstd/data/comp_frame_fse_comp.x b/xls/modules/zstd/data/comp_frame_fse_comp.x index 1eb07c06e7..696bbadff4 100644 --- a/xls/modules/zstd/data/comp_frame_fse_comp.x +++ b/xls/modules/zstd/data/comp_frame_fse_comp.x @@ -1,3 +1,17 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + pub struct DataArray{ data: uN[BITS_PER_WORD][LENGTH], length: u32, diff --git a/xls/modules/zstd/data/comp_frame_fse_repeated.x b/xls/modules/zstd/data/comp_frame_fse_repeated.x index 37de3b7ddf..f9b84897e9 100644 --- a/xls/modules/zstd/data/comp_frame_fse_repeated.x +++ b/xls/modules/zstd/data/comp_frame_fse_repeated.x @@ -1,3 +1,17 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + pub struct DataArray{ data: uN[BITS_PER_WORD][LENGTH], length: u32, diff --git a/xls/modules/zstd/data/comp_frame_huffman.x b/xls/modules/zstd/data/comp_frame_huffman.x index a83c42577d..e1b524265b 100644 --- a/xls/modules/zstd/data/comp_frame_huffman.x +++ b/xls/modules/zstd/data/comp_frame_huffman.x @@ -1,3 +1,17 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + pub struct DataArray{ data: uN[BITS_PER_WORD][LENGTH], length: u32, diff --git a/xls/modules/zstd/data/comp_frame_huffman_fse.x b/xls/modules/zstd/data/comp_frame_huffman_fse.x index 7732b115cd..13ff0f45f8 100644 --- a/xls/modules/zstd/data/comp_frame_huffman_fse.x +++ b/xls/modules/zstd/data/comp_frame_huffman_fse.x @@ -1,3 +1,17 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + pub struct DataArray{ data: uN[BITS_PER_WORD][LENGTH], length: u32, From d9f692f84d5fb2c7d87ec707694dfe7697f95608 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Tue, 20 May 2025 16:21:24 +0200 Subject: [PATCH 77/85] Style changes Improve formatting, wording and fix lint issues Co-authored-by: Dominik Lau Co-authored-by: Szymon Gizler Signed-off-by: Wojciech Sipak --- xls/modules/zstd/README.md | 493 +++++++++++++++-------- xls/modules/zstd/comp_block_dec.x | 1 - xls/modules/zstd/huffman_literals_dec.x | 1 - xls/modules/zstd/memory/README.md | 16 +- xls/modules/zstd/memory/axi_ram_reader.x | 2 - xls/modules/zstd/ram_mux.x | 1 - xls/modules/zstd/zstd_dec_test.x | 1 - 7 files changed, 326 insertions(+), 189 deletions(-) diff --git a/xls/modules/zstd/README.md b/xls/modules/zstd/README.md index b60d630408..fb079592e3 100644 --- a/xls/modules/zstd/README.md +++ b/xls/modules/zstd/README.md @@ -1,9 +1,10 @@ # ZSTD decoder -The ZSTD decoder decompresses the correctly formed ZSTD frames and blocks. -It implements the [RFC 8878](https://www.rfc-editor.org/rfc/rfc8878.html) decompression algorithm. -An overview of the decoder architecture is presented in the diagram below. -The decoder comprises: +The ZSTD decoder decompresses the correctly formed ZSTD frames and blocks. It +implements the [RFC 8878](https://www.rfc-editor.org/rfc/rfc8878.html) +decompression algorithm. An overview of the decoder architecture is presented in +the diagram below. The decoder comprises: + * Memory Readers * Memory Writer, * Control and Status Registers, @@ -13,33 +14,39 @@ The decoder comprises: * Command Aggregator, The Decoder interacts with the environment through a set of ports: + * Memory Interface (AXI) * CSR Interface (AXI) * Notify line -The software controls the core through registers accessible through the `CSR Interface`. -The CSRs are used to configure the decoder and to start the decoding process. +The software controls the core through registers accessible through the `CSR +Interface`. The CSRs are used to configure the decoder and to start the decoding +process. ZSTD frames to decode are placed in a memory that should be connected to decoder's `Memory Interface`. Once the decoding process is started, the decoder: -1. Reads the configuration from the CSRs, -2. Decodes the Frame Header, -3. Decodes the Block Header, -4. Decodes the Block Data with the correct processing unit picked based on the Block Type from the Block Header, -4. Aggregates the processing unit results in the correct order into a stream and routes it to the history buffer, -5. Assembles the data block outputs based on the history buffer contents and updates the history, -6. Prepares the final output of the decoder and writes it to the memory, -7. (Optional) Calculates checksum and compares it against the checksum read from the frame.[^2] - -![](img/ZSTD_decoder.png) +1. Reads the configuration from the CSRs, +2. Decodes the Frame Header, +3. Decodes the Block Header, +4. Decodes the Block Data with the correct processing unit picked based on the + Block Type from the Block Header, +5. Aggregates the processing unit results in the correct order into a stream + and routes it to the history buffer, +6. Assembles the data block outputs based on the history buffer contents and + updates the history, +7. Prepares the final output of the decoder and writes it to the memory, +8. (Optional) Calculates checksum and compares it against the checksum read + from the frame.[^2] + +![brief data flow diagram of ZstdDecoder](img/ZSTD_decoder.png) ## Registers description -The ZSTD Decoder operation is based on the values stored in a set of CSRs accessible to the user through the AXI bus. -The registers are defined below: +The ZSTD Decoder operation is based on the values stored in a set of CSRs +accessible to the user through the AXI bus. The registers are defined below: | Name | Address | Description | | ---- | ------- | ----------- | @@ -50,7 +57,8 @@ The registers are defined below: ### Status codes -The following is a list of all available status codes that can be written in the `Status` register. +The following is a list of all available status codes that can be written in the +`Status` register. | Name | Value | Description | | ---- | ------- | ----------- | @@ -69,34 +77,44 @@ The following is a list of all available status codes that can be written in the ## Controlling the decoder from the software -The configuration done by the software must be carried out when the decoder is in the `IDLE` state. -It is the only time when the decoder will be able to take the configuration values from the CSRs and use those in the decoding process. +The configuration done by the software must be carried out when the decoder is +in the `IDLE` state. It is the only time when the decoder will be able to take +the configuration values from the CSRs and use those in the decoding process. -The software should first read the `Status` register to confirm that the decoder is in the `IDLE` state. -In case it is not in the `IDLE` state, it is possible to reset the decoder by writing `1` to the `Reset` register. -Please note that this will stop ongoing decoding and all progress will be lost. +The software should first read the `Status` register to confirm that the decoder +is in the `IDLE` state. -Then, the software has to reserve the memory for the input buffer and write the frame to decode there. -The address of the buffer should be written into `Input Buffer` register so that the decoder will know where to look for the frame to decode. +Then, the software has to reserve the memory for the input buffer and write the +frame to decode there. The address of the buffer should be written into `Input +Buffer` register so that the decoder will know where to look for the frame to +decode. -The next step is to reserve the memory space for the decoded frame where the Decoder will write the decompressed data. -The address to that buffer should be written to the `Output Buffer` register. +The next step is to reserve the memory space for the decoded frame where the +Decoder will write the decompressed data. The address to that buffer should be +written to the `Output Buffer` register. -Finally, it is possible to start the decoding process by writing `1` to the `Start` register. -This orders the Decoder to read the configuration CSRs and start reading and decoding data stored in the input buffer. -The Decoder transitions to the `RUNNING` state and then to other states that describe the status of the last operation finished in the decoder (see #status-codes for other possible status codes) which will be visible in the `Status` register. +Finally, it is possible to start the decoding process by writing `1` to the +`Start` register. This orders the Decoder to read the configuration CSRs and +start reading and decoding data stored in the input buffer. The Decoder +transitions to the `RUNNING` state and then to other states that describe the +status of the last operation finished in the decoder (see #status-codes for +other possible status codes) which will be visible in the `Status` register. -When the decoding process is finished the Decoder transitions back to the `IDLE` state and signals this on the `Notify` IRQ line. -The decoded data is stored under the address configured previously in the `Output Buffer` register. +When the decoding process is finished the Decoder transitions back to the `IDLE` +state and signals this on the `Notify` IRQ line. The decoded data is stored +under the address configured previously in the `Output Buffer` register. -In case an error occurs during the decoding process it is also signaled on the `Notify` IRQ line and the error code is written to the `Status` CSR. +In case an error occurs during the decoding process it is also signaled on the +`Notify` IRQ line and the error code is written to the `Status` CSR. ## ZSTD decoder architecture ### Top level Proc -This state machine is responsible for controlling the operation of the whole decoder. -It uses the configuration data from the CSRs, connects all underlying modules and sends processing requests to those based on the state of the machine. -The states defined for the processing of the ZSTD frame are as follows: + +This state machine is responsible for controlling the operation of the whole +decoder. It uses the configuration data from the CSRs, connects all underlying +modules and sends processing requests to those based on the state of the +machine. The states defined for the processing of the ZSTD frame are as follows: ```mermaid stateDiagram @@ -143,185 +161,277 @@ stateDiagram ERROR --> IDLE ``` -After going through the initial stage of reading the configuration from the CSRs, the decoder sends the processing requests to the underlying parts of the decoder. -The processing requests contain the addresses in the memory where particular parts of the encoded ZSTD frames reside. -The decoder, based on responses from consecutive internal modules, calculates offsets from the base address that was written to `Input Buffer` CSR and forms the requests for the next internal modules, e.g.: for `BlockHeaderDecoder` or any of the processing units (`RawBlockDecoder`, `RleBlockDecoder`, `CompressedBlockDecoder`). - -Each of the internal modules waits for the processing request. -Once received, the module fetches the data from the memory starting from the address received in the processing request. -`MemReader` procs are used by those modules to communicate with the external memory through the AXI interface. -Internal modules decode the acquired parts of the frame and return responses with the results back to the top level proc. - -The processing units also output the decoded blocks of data through a stream-based interface to the `SequenceExecutor` proc. -This proc performs the last step of the decoding before the final output is sent out back to the memory under the address stored in the `Output Buffer` CSR by the `MemWriter` proc. -Once the decoding process is completed and the decoded frame is written back to the memory, the decoder sends the `Notify` signal and transitions back to the `IDLE` state. +After going through the initial stage of reading the configuration from the +CSRs, the decoder sends the processing requests to the underlying parts of the +decoder. The processing requests contain the addresses in the memory where +particular parts of the encoded ZSTD frames reside. The decoder, based on +responses from consecutive internal modules, calculates offsets from the base +address that was written to `Input Buffer` CSR and forms the requests for the +next internal modules, e.g.: for `BlockHeaderDecoder` or any of the processing +units (`RawBlockDecoder`, `RleBlockDecoder`, `CompressedBlockDecoder`). + +Each of the internal modules waits for the processing request. Once received, +the module fetches the data from the memory starting from the address received +in the processing request. `MemReader` procs are used by those modules to +communicate with the external memory through the AXI interface. Internal modules +decode the acquired parts of the frame and return responses with the results +back to the top level proc. + +The processing units also output the decoded blocks of data through a +stream-based interface to the `SequenceExecutor` proc. This proc performs the +last step of the decoding before the final output is sent out back to the memory +under the address stored in the `Output Buffer` CSR by the `MemWriter` proc. +Once the decoding process is completed and the decoded frame is written back to +the memory, the decoder sends the `Notify` signal and transitions back to the +`IDLE` state. ### Internal modules #### FrameHeaderDecoder + This proc receives requests with the address of the beginning of the ZSTD frame. -It then reads the frame data from the memory and starts parsing the frame header. -If the magic number is not detected or the frame header is invalid, the proc will send a response with an error code. -Otherwise, it will put the frame header into internal DSLX representation, calculate the length of the header and send those as a response with `OKAY` status. +It then reads the frame data from the memory and starts parsing the frame +header. If the magic number is not detected or the frame header is invalid, the +proc will send a response with an error code. Otherwise, it will put the frame +header into internal DSLX representation, calculate the length of the header and +send those as a response with `OKAY` status. #### BlockHeaderDecoder -ZSTD block header size is always 3 bytes. -BlockHeaderDecoder always reads 4 bytes of data. -It extracts the information on block type, size and whether the block is the last one in the ZSTD frame and puts that data in the response. -The additional byte is also placed in the response as an optimization for the RleBlockDecoder. + +ZSTD block header size is always 3 bytes. BlockHeaderDecoder always reads 4 +bytes of data. It extracts the information on block type, size and whether the +block is the last one in the ZSTD frame and puts that data in the response. The +additional byte is also placed in the response as an optimization for the +RleBlockDecoder. #### RawBlockDecoder + This proc passes the data read from the memory directly to its output channel. -It preserves the block ID and attaches a tag, stating that the data contains literals and should be placed in the history buffer unchanged, to each data output. +It preserves the block ID and attaches a tag, stating that the data contains +literals and should be placed in the history buffer unchanged, to each data +output. #### RleBlockDecoder -This proc receives a tuple (s, N), where s is an 8-bit symbol and N is an accompanying `symbol_count`. -It does not have to read the 8-bit symbol from the memory because `BlockHeaderDecoder` did that before and passed the symbol in the processing request to the `RleBlockDecoder`. -The proc produces `N*s` repeats of the given symbol. -This step preserves the block ID and attaches the literals tag to all its outputs. + +This proc receives a tuple (s, N), where s is an 8-bit symbol and N is an +accompanying `symbol_count`. It does not have to read the 8-bit symbol from the +memory because `BlockHeaderDecoder` did that before and passed the symbol in the +processing request to the `RleBlockDecoder`. The proc produces `N*s` repeats of +the given symbol. This step preserves the block ID and attaches the literals tag +to all its outputs. #### CompressedBlockDecoder[^1] + This part of the design is responsible for decoding the compressed data blocks. -It ingests the bytes stream, and internally translates and interprets incoming data. -Only this part of the design creates data chunks tagged both with `literals` and/or `copy`. -This step preserves the block ID. -More in-depth description can be found in [Compressed block decoder architecture](#compressed-block-decoder-architecture) paragraph of this doc. +It ingests the bytes stream, and internally translates and interprets incoming +data. Only this part of the design creates data chunks tagged both with +`literals` and/or `copy`. This step preserves the block ID. More in-depth +description can be found in [Compressed block decoder +architecture](#compressed-block-decoder-architecture1) paragraph of this doc. #### Commands aggregator (DecMux) -This stage takes the output from either RAW, RLE or CompressedBlockDecoder and sends it to the History buffer and command execution stage. -This stage orders streams based on the ID value assigned by the top level proc. -It is expected that single base decoders (RAW, RLE, compressed block decoder) will be continuously transmitting a single ID to the point of sending the `last` signal which marks the last packet of currently decoded block. -That ID can change only when mux receives the `last` signal or `last` and `last_block` signals. -It works as a priority mux that waits for a stream with the expected ID. -It continues to read that stream until the `last` signal is set, then it switches to the next stream ID. +This stage takes the output from either RAW, RLE or CompressedBlockDecoder and +sends it to the History buffer and command execution stage. This stage orders +streams based on the ID value assigned by the top level proc. It is expected +that single base decoders (RAW, RLE, compressed block decoder) will be +continuously transmitting a single ID to the point of sending the `last` signal +which marks the last packet of currently decoded block. That ID can change only +when mux receives the `last` signal or `last` and `last_block` signals. + +It works as a priority mux that waits for a stream with the expected ID. It +continues to read that stream until the `last` signal is set, then it switches +to the next stream ID. -The command aggregator starts by waiting for `ID = 0`, after receiving the `last` signal it expects `ID = 1` and so on. -Only when both `last` and `last_block` are set the command aggregator will wait for `ID = 0`. +The command aggregator starts by waiting for `ID = 0`, after receiving the +`last` signal it expects `ID = 1` and so on. Only when both `last` and +`last_block` are set the command aggregator will wait for `ID = 0`. #### History buffer and command execution (SequenceExecutor) -This stage receives data which is tagged either `literals` or `copy`. -This stage will show the following behavior, depending on the tag: + +This stage receives data which is tagged either `literals` or `copy`. This stage +will show the following behavior, depending on the tag: + * `literals` - * Packet contents placed as newest in the history buffer, - * Packet contents copied to the decoder's output, + * Packet contents placed as newest in the history buffer, + * Packet contents copied to the decoder's output, * `copy` - * Wait for all previous writes to be completed, - * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the decoder's output, - * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the history buffer as the newest. + * Wait for all previous writes to be completed, + * Copy `copy_length` literals starting `offset _length` from the newest in + history buffer to the decoder's output, + * Copy `copy_length` literals starting `offset _length` from the newest in + history buffer to the history buffer as the newest. + +### Compressed block decoder architecture[^1] {#compressed-block-decoder-architecture1} -### Compressed block decoder architecture[^1] -This part of the design is responsible for processing the compressed blocks up to the `literals`/`copy` command sequence. -This sequence is then processed by the history buffer to generate the expected data output. -An overview of the architecture is provided in the diagram below. -The architecture is split into 2 paths: the literals path and the sequence path. -Architecture is split into 3 paths: literals path, FSE encoded Huffman trees and sequence path. -Literals path uses Huffman trees to decode some types of compressed blocks: Compressed and Treeless blocks. +This part of the design is responsible for processing the compressed blocks up +to the `literals`/`copy` command sequence. This sequence is then processed by +the history buffer to generate the expected data output. An overview of the +architecture is provided in the diagram below. The architecture is split into 2 +paths: the literals path and the sequence path. Architecture is split into 3 +paths: literals path, FSE encoded Huffman trees and sequence path. Literals path +uses Huffman trees to decode some types of compressed blocks: Compressed and +Treeless blocks. -![](img/ZSTD_compressed_block_decoder.png) +![data flow diagram of compressed block decoder](img/ZSTD_compressed_block_decoder.png) #### Compressed block dispatcher -This proc parses literals section headers to calculate block compression format, Huffmman tree size (if applicable based on compression format), compressed and regenerated sizes for literals. -If compressed block format is `Compressed_Literals_Block`, dispatcher reads Huffman tree header byte from Huffman bitstream, and directs expected number of bytes to the Huffman tree decoder. -Following this step, the proc sends an appropriate number of bytes to the literals decoder dispatcher. -After sending literals to literals decompression, it redirects the remaining bytes to the sequence parsing stages. +This proc parses literals section headers to calculate block compression format, +Huffmman tree size (if applicable based on compression format), compressed and +regenerated sizes for literals. If compressed block format is +`Compressed_Literals_Block`, dispatcher reads Huffman tree header byte from +Huffman bitstream, and directs expected number of bytes to the Huffman tree +decoder. Following this step, the proc sends an appropriate number of bytes to +the literals decoder dispatcher. + +After sending literals to literals decompression, it redirects the remaining +bytes to the sequence parsing stages. #### Command Constructor -This stage takes literals length, offset length and copy length. -When `literals length` is greater than 0, it will send a request to the literals buffer to obtain `literals length` literals and then send them to the history buffer. -Then based on the offset and copy length it either creates a match command using the provided offset and match lengths, or uses repeated offset and updates the repeated offset memory. -Formed commands are sent to the Commands aggregator (mux). + +This stage takes literals length, offset length and copy length. When `literals +length` is greater than 0, it will send a request to the literals buffer to +obtain `literals length` literals and then send them to the history buffer. Then +based on the offset and copy length it either creates a match command using the +provided offset and match lengths, or uses repeated offset and updates the +repeated offset memory. Formed commands are sent to the Commands aggregator +(mux). #### Literals path architecture -![](img/ZSTD_compressed_block_literals_decoder.png) +![data flow diagram of literals decoder](img/ZSTD_compressed_block_literals_decoder.png) ##### Literals decoder dispatcher -This proc parses and consumes the literals section header. -Based on the received values it passes the remaining bytes to RAW/RLE/Huffman tree/Huffman code decoders. -It also controls the 4 stream operation mode [4-stream mode in RFC](https://www.rfc-editor.org/rfc/rfc8878.html#name-jump_table). -All packets sent to the Huffman bitstream buffer will be tagged either `in_progress` or `finished`. -If the compressed literals use the 4 streams encoding, the dispatcher will send the `finished` tag 4 times, each time a fully compressed stream is sent to the bitstream buffer. +This proc parses and consumes the literals section header. Based on the received +values it passes the remaining bytes to RAW/RLE/Huffman tree/Huffman code +decoders. It also controls the 4 stream operation mode [4-stream mode in +RFC](https://www.rfc-editor.org/rfc/rfc8878.html#name-jump_table). + +All packets sent to the Huffman bitstream buffer will be tagged either +`in_progress` or `finished`. If the compressed literals use the 4 streams +encoding, the dispatcher will send the `finished` tag 4 times, each time a fully +compressed stream is sent to the bitstream buffer. ##### RAW Literals + This stage simply passes the incoming bytes as literals to the literals buffer. ##### RLE Literals -This stage works similarly to the [RLE stage](#rle-decoder) for RLE data blocks. + +This stage works similarly to the [RLE stage](#rleblockdecoder) for RLE data +blocks. ##### Huffman bitstream buffer -This stage takes data from the literals decoder dispatcher and stores it in the buffer memory. -Once the data with the `finished` tag set is received, this stage sends a tuple containing (start, end) positions for the current bitstream to the Huffman codes decoder. -This stage receives a response from the Huffman codes decoder when decoding is done and all bits got processed. -Upon receiving this message, the buffer will reclaim free space. + +This stage takes data from the literals decoder dispatcher and stores it in the +buffer memory. Once the data with the `finished` tag set is received, this stage +sends a tuple containing (start, end) positions for the current bitstream to the +Huffman codes decoder. This stage receives a response from the Huffman codes +decoder when decoding is done and all bits got processed. Upon receiving this +message, the buffer will reclaim free space. ##### Huffman codes decoder -This stage receives bitstream pointers from the Huffman bitstream buffer and Huffman tree configuration from the Huffman tree builder. -It accesses the bitstream buffers memory to retrieve bitstream data in reversed byte order and runs it through an array of comparators to decode Huffman code to correct literals values. + +This stage receives bitstream pointers from the Huffman bitstream buffer and +Huffman tree configuration from the Huffman tree builder. It accesses the +bitstream buffers memory to retrieve bitstream data in reversed byte order and +runs it through an array of comparators to decode Huffman code to correct +literals values. ##### Literals buffer + This stage receives data either from RAW, RLE or Huffman decoder and stores it. -Upon receiving the literals copy command from the Command Constructor for `N` number of bytes, it provides a reply with `N` literals. +Upon receiving the literals copy command from the Command Constructor for `N` +number of bytes, it provides a reply with `N` literals. #### FSE Huffman decoder architecture -![](img/ZSTD_compressed_block_Huffman_decoder.png) +![data flow diagram of weight decoders](img/ZSTD_compressed_block_Huffman_decoder.png) ##### Huffman tree decoder dispatcher -This stage parses and consumes the Huffman tree description header. -Based on the value of the Huffman descriptor header, it passes the tree description to the FSE decoder or to direct weight extraction. + +This stage parses and consumes the Huffman tree description header. Based on the +value of the Huffman descriptor header, it passes the tree description to the +FSE decoder or to direct weight extraction. ##### FSE weight decoder + This stage performs multiple functions. -1. It decodes and builds the FSE distribution table. -2. It stores all remaining bitstream data. -3. After receiving the last byte, it translates the bitstream to Huffman weights using 2 interleaved FSE streams. + +1. It decodes and builds the FSE distribution table. +2. It stores all remaining bitstream data. +3. After receiving the last byte, it translates the bitstream to Huffman + weights using 2 interleaved FSE streams. ##### Direct weight decoder -This stage takes the incoming bytes and translates them to the stream of Huffman tree weights. -The first byte of the transfer defines the number of symbols to be decoded. + +This stage takes the incoming bytes and translates them to the stream of Huffman +tree weights. The first byte of the transfer defines the number of symbols to be +decoded. ##### Weight aggregator -This stage receives tree weights either from the FSE decoder or the direct decoder and transfers them to Huffman tree builder. -This stage also resolves the number of bits of the final weight and the max number of bits required in the tree representation. -This stage will emit the weights and number of symbols of the same weight before the current symbol for all possible byte values. + +This stage receives tree weights either from the FSE decoder or the direct +decoder and transfers them to Huffman tree builder. This stage also resolves the +number of bits of the final weight and the max number of bits required in the +tree representation. This stage will emit the weights and number of symbols of +the same weight before the current symbol for all possible byte values. ##### Huffman tree builder -This stage takes `max_number_of_bits` (maximal length of Huffman code) as the first value, then the number of symbols with lower weight for each possible weight (11 bytes), followed by a tuple (number of preceding symbols with the same weight, symbol's_weight). -It's expected to receive weights for all possible byte values in the correct order. -Based on this information, this stage will configure the Huffman codes decoder. + +This stage takes `max_number_of_bits` (maximal length of Huffman code) as the +first value, then the number of symbols with lower weight for each possible +weight (11 bytes), followed by a tuple (number of preceding symbols with the +same weight, symbol's_weight). It's expected to receive weights for all possible +byte values in the correct order. Based on this information, this stage will +configure the Huffman codes decoder. #### Sequence path architecture -![](img/ZSTD_compressed_block_sequence_decoder.png) +![data flow diagram of sequence decoder](img/ZSTD_compressed_block_sequence_decoder.png) ##### Sequence Header parser and dispatcher -This stage parses and consumes `Sequences_Section_Header`. -Based on the parsed data, it redirects FSE description to the FSE table decoder and triggers Literals FSE, Offset FSE or Match FSE decoder to reconfigure its values based on the FSE table decoder. -After parsing the FSE tables, this stage buffers bitstream and starts sending bytes, starting from the last one received as per ZSTD format. -Bytes are sent to all decoders at the same time. -This stage monitors and triggers sequence decoding phases starting from initialization, followed by decode and state advance. -FSE decoders send each other the number of bits they read. + +This stage parses and consumes `Sequences_Section_Header`. Based on the parsed +data, it redirects FSE description to the FSE table decoder and triggers +Literals FSE, Offset FSE or Match FSE decoder to reconfigure its values based on +the FSE table decoder. After parsing the FSE tables, this stage buffers +bitstream and starts sending bytes, starting from the last one received as per +ZSTD format. Bytes are sent to all decoders at the same time. This stage +monitors and triggers sequence decoding phases starting from initialization, +followed by decode and state advance. FSE decoders send each other the number of +bits they read. ##### Literals FSE decoder -This stage reconfigures its FSE table when triggered from [sequence header parse and dispatcher](#sequence-header-parser-and-dispatcher). -It initializes its state as the first FSE decoder. -In the decode phase, this stage is the last one to decode extra raw bits from the bitstream, and the number of ingested bits is transmitted to all other decoders. -This stage is the first stage to get a new FSE state from the bitstream, and it transmits the number of bits it used. + +This stage reconfigures its FSE table when triggered from [sequence header parse +and dispatcher](#sequence-header-parser-and-dispatcher). It initializes its +state as the first FSE decoder. In the decode phase, this stage is the last one +to decode extra raw bits from the bitstream, and the number of ingested bits is +transmitted to all other decoders. This stage is the first stage to get a new +FSE state from the bitstream, and it transmits the number of bits it used. ##### Offset FSE decoder -This stage reconfigures its FSE table when triggered from [sequence header parse and dispatcher](#sequence-header-parser-and-dispatcher). -It initializes its state as the second FSE decoder. -In the decode phase, this stage is the first one to decode extra raw bits from bitstream, and the number of ingested bits is transmitted to all other decoders. -This stage is the last decoder to update its FSE state after the decode phase, and it transmits the number of used bits to other decoders. + +This stage reconfigures its FSE table when triggered from [sequence header parse +and dispatcher](#sequence-header-parser-and-dispatcher). It initializes its +state as the second FSE decoder. In the decode phase, this stage is the first +one to decode extra raw bits from bitstream, and the number of ingested bits is +transmitted to all other decoders. This stage is the last decoder to update its +FSE state after the decode phase, and it transmits the number of used bits to +other decoders. ##### Match FSE decoder -This stage reconfigures its FSE table when triggered from [sequence header parse and dispatcher](#sequence-header-parser-and-dispatcher). -It initializes its state as the last FSE decoder. -In the decode phase, this stage is the second one to decode extra raw bits from the bitstream, and the number of ingested bits is transmitted to all other decoders. -This stage is the second stage to update its state after the decode phase, and the number of used bits is sent to all other decoders. + +This stage reconfigures its FSE table when triggered from [sequence header parse +and dispatcher](#sequence-header-parser-and-dispatcher). It initializes its +state as the last FSE decoder. In the decode phase, this stage is the second one +to decode extra raw bits from the bitstream, and the number of ingested bits is +transmitted to all other decoders. This stage is the second stage to update its +state after the decode phase, and the number of used bits is sent to all other +decoders. ## Testing methodology @@ -330,22 +440,30 @@ Testing of the `ZSTD decoder` is carried out on two levels: * Decoder components * Integrated decoder -Each component of the decoder is tested individually in DSLX tests. -Testing on the DSLX level allows the creation of small test cases that test for positive outcomes of a given part of the design. -When need be, those test cases can be also modified by the user to better understand how the component operates. +Each component of the decoder is tested individually in DSLX tests. Testing on +the DSLX level allows the creation of small test cases that test for positive +outcomes of a given part of the design. When need be, those test cases can be +also modified by the user to better understand how the component operates. Tests of the integrated ZSTD decoder are carried out on DSLX and Verilog levels. The objective of those is to verify the functionality of the decoder as a whole. -Testing setup for the ZSTD decoder is based on comparing the simulated decoding results against the decoding of the reference library. -Currently, due to the restrictions from the ZSTD frame generator, it is possible to test only the positive cases (decoding valid ZSTD frames). - -ZstdDecoder's main communication interfaces are the AXI buses. -Due to the way XLS handles the codegen of DSLX channels that model the AXI channels, the particular ports of the AXI channels are not represented correctly. -This enforces the introduction of a Verilog wrapper that maps the ports generated by XLS into proper AXI ports (see AXI peripherals [README](memory/README.md) for more information). -Additionally, the wrapper is used to mux multiple AXI interfaces from `Memory Readers` and `Memory Writer` into a single outside-facing AXI interface (`Memory Interface`) that can be connected to the external memory. -The mux is implemented by a third-party [AXI Crossbar](https://github.com/alexforencich/verilog-axi). - -![](img/ZSTD_decoder_wrapper.png) +Testing setup for the ZSTD decoder is based on comparing the simulated decoding +results against the decoding of the reference library. Currently, due to the +restrictions from the ZSTD frame generator, it is possible to test only the +positive cases (decoding valid ZSTD frames). + +ZstdDecoder's main communication interfaces are the AXI buses. Due to the way +XLS handles the codegen of DSLX channels that model the AXI channels, the +particular ports of the AXI channels are not represented correctly. This +enforces the introduction of a Verilog wrapper that maps the ports generated by +XLS into proper AXI ports (see AXI peripherals [README](memory/README.md) for +more information). Additionally, the wrapper is used to mux multiple AXI +interfaces from `Memory Readers` and `Memory Writer` into a single +outside-facing AXI interface (`Memory Interface`) that can be connected to the +external memory. The mux is implemented by a third-party [AXI +Crossbar](https://github.com/alexforencich/verilog-axi). + +![diagram of interfaces of decoder and its wrapper](img/ZSTD_decoder_wrapper.png) ### Failure points @@ -356,42 +474,65 @@ The design will fail the tests under the following conditions: * Straightforward failures: * Top Level State Machine transitions to `ERROR` state * Simulation encounters `assert!()` or `fail!()` statements - * The decoding result from the simulation has a different size than the results from the reference library - * The decoding result from the simulation has different contents than the results from the reference library + * The decoding result from the simulation has a different size than the + results from the reference library + * The decoding result from the simulation has different contents than the + results from the reference library Currently, all mentioned conditions lead to an eventual test failure. #### Failures in ZSTD Decoder components -It is important to note that some of the errors (e.g. errors in magic number or frame header decoding) are easy to trigger in the integration test cases by manual modification of the generated ZSTD frames. -However, the majority of the errors require modification of the deeper parts of the raw ZSTD frame which is significantly harder. -Because of that, it is better to rely on DSLX tests for the individual components where inputs for the test cases are smaller, easier to understand and modify when needed. +It is important to note that some of the errors (e.g. errors in magic number or +frame header decoding) are easy to trigger in the integration test cases by +manual modification of the generated ZSTD frames. However, the majority of the +errors require modification of the deeper parts of the raw ZSTD frame which is +significantly harder. Because of that, it is better to rely on DSLX tests for +the individual components where inputs for the test cases are smaller, easier to +understand and modify when needed. + +The components of the ZSTD decoder can fail on `assert!()` and `fail!()` +statements or propagate specific error states to the Top Level Proc and cause it +to transition to the `ERROR` state. Upon entering the `ERROR` state, the decoder +will write a specific error code to the `Status` CSR and send a `Notify` signal +to the output. The interacting software can then read the code from the register +and properly handle the error. -The components of the ZSTD decoder can fail on `assert!()` and `fail!()` statements or propagate specific error states to the Top Level Proc and cause it to transition to the `ERROR` state. -Upon entering the `ERROR` state, the decoder will write a specific error code to the `Status` CSR and send a `Notify` signal to the output. -The interacting software can then read the code from the register and properly handle the error. +The following enumeration will describe how to trigger each possible ZSTD +Decoder error. -The following enumeration will describe how to trigger each possible ZSTD Decoder error. +The `ERROR` state can be encountered under the following conditions when running +Top Level Proc Verilog tests but also in DSLX tests for the specific components: -The `ERROR` state can be encountered under the following conditions when running Top Level Proc Verilog tests but also in DSLX tests for the specific components: * Corrupted data on the frame header decoding stage - * Provide data for the decoding with the first 4 bytes not being the valid `Magic Number` (0xFD2FB528) + * Provide data for the decoding with the first 4 bytes not being the valid +`Magic Number` (0xFD2FB528) * Set the `Reserved bit` in the frame header descriptor - * Set `Window Size` in frame header to value greater than `max window size` calculated from current `WINDOW_LOG_MAX` (by default in Top Level Proc tests `Window Size` must be greater than `0x78000000` to trigger the error) + * Set `Window Size` in frame header to value greater than `max window size` +calculated from current `WINDOW_LOG_MAX` (by default in Top Level Proc tests +`Window Size` must be greater than `0x78000000` to trigger the error) * Corrupted data during Block Header decoding * Set the `Block Type` of any block in the ZSTD frame to `RESERVED` The `assert!()` or `fail!()` will occur in: -* RawBlockDecoder - * Receive `BlockDataPacket` with `ID` different than the previous packet which did not have the `last` flag set -* DecoderMux - * At the beginning of the simulation or after receiving `ExtendedBlockDataPacket` with `last` and `last_block` (decoding new ZSTD frame) set receive on channels `raw_r`, `rle_r` and `cmp_r` `ExtendedBlockDataPackets` without any of those having `ID==0` - * Receive `ExtendedBlockDataPacket` with a smaller `ID` than any of the previously processed packets during the current ZSTD frame decoding -* SequenceExecutor - * Receive `SequenceExecutorPacket` with `msg_type==SEQUENCE` and `content` field with value: `0` + +* RawBlockDecoder + * Receive `BlockDataPacket` with `ID` different than the previous packet + which did not have the `last` flag set +* DecoderMux + * At the beginning of the simulation or after receiving + `ExtendedBlockDataPacket` with `last` and `last_block` (decoding new + ZSTD frame) set receive on channels `raw_r`, `rle_r` and `cmp_r` + `ExtendedBlockDataPackets` without any of those having `ID==0` + * Receive `ExtendedBlockDataPacket` with a smaller `ID` than any of the + previously processed packets during the current ZSTD frame decoding +* SequenceExecutor + * Receive `SequenceExecutorPacket` with `msg_type==SEQUENCE` and `content` + field with value: `0` There are also several `impossible cases` covered by `fail!()`. -Those are mostly enforced by the type checker for the `match` expressions to cover unreachable cases. +Those are mostly enforced by the type checker for the `match` expressions to +cover unreachable cases. This is done for example in: * Frame header decoder diff --git a/xls/modules/zstd/comp_block_dec.x b/xls/modules/zstd/comp_block_dec.x index a94658ba12..f40cfad3cb 100644 --- a/xls/modules/zstd/comp_block_dec.x +++ b/xls/modules/zstd/comp_block_dec.x @@ -1636,4 +1636,3 @@ proc CompressBlockDecoderTest { send(tok, terminator, true); } } - diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index 81819e9e75..b60cadedad 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -1233,4 +1233,3 @@ proc HuffmanLiteralsDecoder_test { // literals_last: true, // }, //]; - diff --git a/xls/modules/zstd/memory/README.md b/xls/modules/zstd/memory/README.md index 6a0e4aedfb..37c20c45a3 100644 --- a/xls/modules/zstd/memory/README.md +++ b/xls/modules/zstd/memory/README.md @@ -16,7 +16,7 @@ structures will not match the expected AXI bus signature. To interface with other AXI peripherals, additional Verilog wrappers may be needed to split the flattened bit vector into individual signals. -# Data Structures +## Data Structures As noted, the procs in this directory use channels with dedicated structures to represent AXI bus signals in DSLX. For instance, the AXI read @@ -27,7 +27,7 @@ to receive the read data. These channels are represented by the `AxiAr` and The structures used to represent AXI4 Stream interface can be found in the `axi_st.x` file. -# Main components +## Main components The primary components of this directory are `MemReader` and `MemWriter`, which facilitate issuing read and write transactions on the AXI bus. @@ -38,7 +38,8 @@ The `MemReader` includes several procs that can be used individually: - `AxiReader`: Handles the creation of AXI transactions, managing unaligned addresses and issuing additional transactions when crossing the 4KB boundary - or when the read request is longer than maximum possible burst size on the AXI bus + or when the read request is longer than maximum possible burst size on the + AXI bus - `AxiStreamDownscaler`: An optional proc available in `MemReaderAdv`, enabling DSLX designs to connect to a wider AXI bus. @@ -48,15 +49,16 @@ The `MemReader` includes several procs that can be used individually: The `MemWriter` proc is organised in a similar manner, it consists of: -- `AxiWriter`: Handles the creation of AXI write transactions, managing unaligned - addresses and issuing additional transactions when crossing the 4KB boundary, - or when the write request is longer than maximum possible burst size on the AXI bus +- `AxiWriter`: Handles the creation of AXI write transactions, managing + unaligned addresses and issuing additional transactions when crossing the 4KB + boundary, or when the write request is longer than maximum possible burst size + on the AXI bus - `AxiStreamAddEmpty`: Adds empty data bits in the stream of data to write. It is used to shift the data in the stream to facilitate writes to unaligned addresses. -# Usage +## Usage The list below shows the usage of the `MemReader` proc: diff --git a/xls/modules/zstd/memory/axi_ram_reader.x b/xls/modules/zstd/memory/axi_ram_reader.x index edea056195..9c6926712d 100644 --- a/xls/modules/zstd/memory/axi_ram_reader.x +++ b/xls/modules/zstd/memory/axi_ram_reader.x @@ -758,5 +758,3 @@ proc AxiRamReaderTest { send(tok, terminator, true); } } - - diff --git a/xls/modules/zstd/ram_mux.x b/xls/modules/zstd/ram_mux.x index 25d785a69f..a4cde3e576 100644 --- a/xls/modules/zstd/ram_mux.x +++ b/xls/modules/zstd/ram_mux.x @@ -235,4 +235,3 @@ proc RamMuxTest { let tok = send(tok, terminator, true); } } - diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 151d3f15e3..989ba75cd8 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -898,4 +898,3 @@ proc ZstdDecoderTest { send(tok, terminator, true); } } - From bafb36f36a5f81785b1a3afad7c9ae314b6025f3 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Wed, 21 May 2025 16:34:27 +0200 Subject: [PATCH 78/85] add targets for generating test frames MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Pawel Czarnecki Co-authored-by: Krzysztof Obłonczek --- dependency_support/pip_requirements.in | 1 + dependency_support/pip_requirements_lock.txt | 99 ++++++++++++ xls/modules/zstd/BUILD | 33 ++++ xls/modules/zstd/data_generator.py | 66 ++++++++ xls/modules/zstd/zstd_frame_dslx.py | 155 +++++++++++++++++++ 5 files changed, 354 insertions(+) create mode 100644 xls/modules/zstd/data_generator.py create mode 100644 xls/modules/zstd/zstd_frame_dslx.py diff --git a/dependency_support/pip_requirements.in b/dependency_support/pip_requirements.in index 804306558e..034b9d393c 100644 --- a/dependency_support/pip_requirements.in +++ b/dependency_support/pip_requirements.in @@ -13,6 +13,7 @@ pyyaml==6.0.1 # We build most of z3 ourselves but building python is really complicated. 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--hash=sha256:f2d4380bf5f62daabd7b751ea2339c1a21d1c9463f1feb7fc2bdcea2c29c3160 \ + --hash=sha256:f3513916e8c645d0610815c257cbfd3242adfd5c4cfa78be514e5a3ebb42a41b \ + --hash=sha256:f8346bfa098532bc1fb6c7ef06783e969d87a99dd1d2a5a18a892c1d7a643c58 \ + --hash=sha256:f83fa6cae3fff8e98691248c9320356971b59678a17f20656a9e59cd32cee6d8 \ + --hash=sha256:fa6ce8b52c5987b3e34d5674b0ab529a4602b632ebab0a93b07bfb4dfc8f8a33 \ + --hash=sha256:fb2b1ecfef1e67897d336de3a0e3f52478182d6a47eda86cbd42504c5cbd009a \ + --hash=sha256:fc9ca1c9718cb3b06634c7c8dec57d24e9438b2aa9a0f02b8bb36bf478538880 \ + --hash=sha256:fd30d9c67d13d891f2360b2a120186729c111238ac63b43dbd37a5a40670b8ca \ + --hash=sha256:fd7699e8fd9969f455ef2926221e0233f81a2542921471382e77a9e2f2b57f4b \ + --hash=sha256:fe3b385d996ee0822fd46528d9f0443b880d4d05528fd26a9119a54ec3f91c69 + # via -r dependency_support/pip_requirements.in diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index d80a9bb0af..be61cb8c9f 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -17,6 +17,7 @@ load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route") load("@rules_hdl//synthesis:build_defs.bzl", "benchmark_synth", "synthesize_rtl") load("@rules_hdl//verilog:providers.bzl", "verilog_library") +load("@xls_pip_deps//:requirements.bzl", "requirement") load( "//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_ir", @@ -367,6 +368,15 @@ cc_library( ], ) +py_library( + name = "data_generator_py", + srcs = ["data_generator.py"], + deps = [ + "//xls/common:runfiles", + "@zstd//:decodecorpus", + ], +) + xls_dslx_library( name = "common_dslx", srcs = [ @@ -1442,6 +1452,29 @@ xls_dslx_test( tags = ["manual"], ) +py_binary( + name = "zstd_test_frames_generator", + srcs = ["zstd_frame_dslx.py"], + imports = ["."], + main = "zstd_frame_dslx.py", + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + requirement("zstandard"), + "//xls/common:runfiles", + ":data_generator_py", + "@com_google_protobuf//:protobuf_python", + ], +) + +genrule( + name = "zstd_test_frames_generate", + srcs = [], + outs = ["zstd_frame_testcases.x"], + cmd = "$(location :zstd_test_frames_generator) --seed 36 -n 1 --btype COMPRESSED -o $@", + tools = [":zstd_test_frames_generator"], +) + xls_dslx_library( name = "ram_merge_dslx", srcs = ["ram_merge.x"], diff --git a/xls/modules/zstd/data_generator.py b/xls/modules/zstd/data_generator.py new file mode 100644 index 0000000000..46a74acbfc --- /dev/null +++ b/xls/modules/zstd/data_generator.py @@ -0,0 +1,66 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Module for generating and decompressing test frames.""" + +import pathlib +import enum + +from xls.common import runfiles +import subprocess +import zstandard + +class BlockType(enum.Enum): + """Enum encoding of ZSTD block types.""" + + RAW = 0 + RLE = 1 + COMPRESSED = 2 + RANDOM = 3 + + def __str__(self): + return self.name + + @staticmethod + def from_string(s): + try: + return BlockType[s] + except KeyError as e: + raise ValueError(str(e)) from e + +def CallDecodecorpus(args): + decodecorpus = pathlib.Path( + runfiles.get_path("decodecorpus", repository = "zstd") + ) + cmd = args + cmd.insert(0, str(decodecorpus)) + cmd_concat = " ".join(cmd) + subprocess.run(cmd_concat, shell=True, check=True) + +def DecompressFrame(data): + dctx = zstandard.ZstdDecompressor() + return dctx.decompress(data) + +def GenerateFrame(seed, btype, output_path): + args = [] + args.append("-s" + str(seed)) + if (btype != BlockType.RANDOM): + args.append("--block-type=" + str(btype.value)) + args.append("--content-size") + # Test payloads up to 16KB + args.append("--max-content-size-log=14") + args.append("-p" + output_path) + args.append("-vvvvvvv") + + CallDecodecorpus(args) diff --git a/xls/modules/zstd/zstd_frame_dslx.py b/xls/modules/zstd/zstd_frame_dslx.py new file mode 100644 index 0000000000..5304e07f45 --- /dev/null +++ b/xls/modules/zstd/zstd_frame_dslx.py @@ -0,0 +1,155 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""ZSTD test frame generator for DSLX tests. + +This module interacts with the data_generator module and underlying +Decodecorpus in order to generate inputs and expected outputs for the ZSTD +Decoder tests in DSLX. + +It generates the ZSTD frame and then decodes it with the reference ZSTD +library. Both the encoded frame and decoded data are written to a DSLX file by +converting raw bytes of the frame and decoded data into DSLX structures. + +Resulting file can be included in the ZSTD Decoder DSLX test and used as the +inputs and expected output for the testbench. +""" + +import argparse +import math +import random +import tempfile +import pathlib + +from xls.modules.zstd import data_generator + + +def GenerateTestData(seed, btype): + with tempfile.NamedTemporaryFile() as tmp: + data_generator.GenerateFrame(seed, btype, tmp.name) + tmp.seek(0) + return tmp.read() + + +def Bytes2DSLX(frames, bytes_per_word, array_name): + """Converts a list of byte frames to a DSLX constant array declaration. + + Args: + frames (List[bytes]): List of byte sequences representing frames. + bytes_per_word (int): Number of bytes per word in the output format. + array_name (str): Name of the resulting DSLX constant array. + + Returns: + str: A string containing the DSLX constant array declaration. + """ + frames_hex = [] + maxlen = max(len(frame) for frame in frames) + maxlen_size = math.ceil(maxlen / bytes_per_word) + bits_per_word = bytes_per_word * 8 + for i, frame in enumerate(frames): + frame_hex = [] + for i in range(0, len(frame), bytes_per_word): + # reverse byte order to make them little endian + word = bytes(reversed(frame[i : i + bytes_per_word])).hex() + frame_hex.append(f"uN[{bits_per_word}]:0x{word}") + + array_length = len(frame_hex) + if len(frame) < maxlen: + frame_hex += [f"uN[{bits_per_word}]:0x0", "..."] + + frame_array = ( + f"DataArray<{bits_per_word}, {maxlen_size}>{{\n" + f" length: u32:{len(frame)},\n" + f" array_length: u32:{array_length},\n" + f" data: uN[{bits_per_word}][{maxlen_size}]:[{', '.join(frame_hex)}]\n" + f"}}" + ) + frames_hex.append(frame_array) + + frames_str = ",\n".join(frames_hex) + frames_array = ( + f"pub const {array_name}:DataArray<\n" + f" u32:{bits_per_word},\n" + f" u32:{maxlen_size}\n" + f">[{len(frames_hex)}] = [{frames_str}];\n" + ) + return frames_array + + +def GenerateDataStruct(): + return ( + "pub struct DataArray{\n" + " data: uN[BITS_PER_WORD][LENGTH],\n" + " length: u32,\n" + " array_length: u32\n" + "}\n" + ) + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument( + "-n", help="Number of testcases to generate", type=int, default=1 + ) + parser.add_argument( + "--seed", help="Seed for the testcases generator", type=int, default=0 + ) + parser.add_argument( + "--btype", + help=( + "Block types allowed in the generated testcases. If multiple block types " + "are supplied, generated testcases will cycle through them" + ), + type=data_generator.BlockType.from_string, + choices=list(data_generator.BlockType), + default=data_generator.BlockType.RANDOM, + nargs="+", + ) + parser.add_argument( + "-o", + "--output", + help="Filename of the DSLX output file", + type=pathlib.Path, + default=pathlib.Path("frames_test_data.x"), + ) + parser.add_argument( + "--bytes-per-word", + help="Width of a word in memory, in bytes", + type=int, + default=8, + ) + args = parser.parse_args() + + random.seed(args.seed) + byte_frames = [ + GenerateTestData(random.randrange(2**32), args.btype[i % len(args.btype)]) + for i in range(args.n) + ] + with open(args.output, "w") as dslx_output: + dslx_output.write(GenerateDataStruct()) + + dslx_frames = Bytes2DSLX(byte_frames, args.bytes_per_word, "FRAMES") + dslx_output.write(dslx_frames) + + byte_frames_decompressed = list( + map(data_generator.DecompressFrame, byte_frames) + ) + dslx_frames_decompressed = Bytes2DSLX( + byte_frames_decompressed, args.bytes_per_word, "DECOMPRESSED_FRAMES" + ) + dslx_output.write(dslx_frames_decompressed) + + +if __name__ == "__main__": + main() From 45dc6aa95ed0725a0b66c23279acdafb5910af1a Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Fri, 23 May 2025 09:51:16 +0200 Subject: [PATCH 79/85] Bump zstd Signed-off-by: Robert Winkler --- dependency_support/pip_requirements.in | 2 +- dependency_support/pip_requirements_lock.txt | 150 +++++++------------ 2 files changed, 53 insertions(+), 99 deletions(-) diff --git a/dependency_support/pip_requirements.in b/dependency_support/pip_requirements.in index 034b9d393c..6ec69c187a 100644 --- a/dependency_support/pip_requirements.in +++ b/dependency_support/pip_requirements.in @@ -13,7 +13,7 @@ pyyaml==6.0.1 # We build most of z3 ourselves but building python is really complicated. Just # use pypi version z3-solver==4.14.0.0 -zstandard==0.23.0 +zstandard==0.19.0 # Note: numpy and scipy version availability seems to differ between Ubuntu # versions that we want to support (e.g. 18.04 vs 20.04), so we accept a diff --git a/dependency_support/pip_requirements_lock.txt b/dependency_support/pip_requirements_lock.txt index a63ef9ffcd..cadc770f13 100644 --- a/dependency_support/pip_requirements_lock.txt +++ b/dependency_support/pip_requirements_lock.txt @@ -541,102 +541,56 @@ z3-solver==4.14.0.0 \ --hash=sha256:c10f899c6a876e3a50e9b2c4927604c2c3da3cca672b8ed3b7db1bc97259e47f \ --hash=sha256:e6ae32bc1cf4d25b96f790755d790a23118e8a09b9b6060e32238fe6ff43606d # via -r dependency_support/pip_requirements.in -zstandard==0.23.0 \ - --hash=sha256:034b88913ecc1b097f528e42b539453fa82c3557e414b3de9d5632c80439a473 \ - --hash=sha256:0a7f0804bb3799414af278e9ad51be25edf67f78f916e08afdb983e74161b916 \ - --hash=sha256:11e3bf3c924853a2d5835b24f03eeba7fc9b07d8ca499e247e06ff5676461a15 \ - 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--hash=sha256:a65e0119ad39e855427520f7829618f78eb2824aa05e63ff19b466080cd99210 \ + --hash=sha256:aa9087571729c968cd853d54b3f6e9d0ec61e45cd2c31e0eb8a0d4bdbbe6da2f \ + --hash=sha256:aef0889417eda2db000d791f9739f5cecb9ccdd45c98f82c6be531bdc67ff0f2 \ + --hash=sha256:b253d0c53c8ee12c3e53d181fb9ef6ce2cd9c41cbca1c56a535e4fc8ec41e241 \ + --hash=sha256:b80f6f6478f9d4ca26daee6c61584499493bf97950cfaa1a02b16bb5c2c17e70 \ + --hash=sha256:be6329b5ba18ec5d32dc26181e0148e423347ed936dda48bf49fb243895d1566 \ + --hash=sha256:c7560f622e3849cc8f3e999791a915addd08fafe80b47fcf3ffbda5b5151047c \ + --hash=sha256:d1a7a716bb04b1c3c4a707e38e2dee46ac544fff931e66d7ae944f3019fc55b8 \ + --hash=sha256:d63b04e16df8ea21dfcedbf5a60e11cbba9d835d44cb3cbff233cfd037a916d5 \ + --hash=sha256:d777d239036815e9b3a093fa9208ad314c040c26d7246617e70e23025b60083a \ + --hash=sha256:e892d3177380ec080550b56a7ffeab680af25575d291766bdd875147ba246a91 \ + --hash=sha256:e9c90a44470f2999779057aeaf33461cbd8bb59d8f15e983150d10bb260e16e0 \ + --hash=sha256:f097dda5d4f9b9b01b3c9fa2069f9c02929365f48f341feddf3d6b32510a2f93 \ + --hash=sha256:f4ebfe03cbae821ef994b2e58e4df6a087470cc522aca502614e82a143365d45 # via -r dependency_support/pip_requirements.in From 9ef6f9ca3e28e9bbee7bb83437b155fbbf369c5c Mon Sep 17 00:00:00 2001 From: Szymon Gizler Date: Fri, 23 May 2025 12:29:45 +0200 Subject: [PATCH 80/85] Rename *.v to *.sv --- xls/modules/zstd/BUILD | 22 +++++++++---------- xls/modules/zstd/rtl/BUILD | 6 ++--- ...xls_fifo_wrapper.v => xls_fifo_wrapper.sv} | 0 ...zstd_dec_wrapper.v => zstd_dec_wrapper.sv} | 0 4 files changed, 14 insertions(+), 14 deletions(-) rename xls/modules/zstd/rtl/{xls_fifo_wrapper.v => xls_fifo_wrapper.sv} (100%) rename xls/modules/zstd/rtl/{zstd_dec_wrapper.v => zstd_dec_wrapper.sv} (100%) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index be61cb8c9f..44720fa8f5 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -434,7 +434,7 @@ verilog_library( name = "frame_header_dec_verilog_lib", srcs = [ ":frame_header_dec.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -530,7 +530,7 @@ verilog_library( name = "block_header_dec_verilog_lib", srcs = [ ":block_header_dec.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -609,7 +609,7 @@ verilog_library( name = "raw_block_dec_verilog_lib", srcs = [ ":raw_block_dec.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -687,7 +687,7 @@ verilog_library( name = "rle_block_dec_verilog_lib", srcs = [ ":rle_block_dec.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -765,7 +765,7 @@ verilog_library( name = "dec_mux_verilog_lib", srcs = [ ":dec_mux.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -905,7 +905,7 @@ verilog_library( name = "sequence_executor_lib", srcs = [ ":sequence_executor.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -985,7 +985,7 @@ verilog_library( name = "axi_csr_accessor_verilog_lib", srcs = [ ":axi_csr_accessor.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -1062,7 +1062,7 @@ verilog_library( name = "csr_config_verilog_lib", srcs = [ ":csr_config.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -1142,7 +1142,7 @@ verilog_library( name = "ram_rw_handler_verilog_lib", srcs = [ ":ram_rw_handler.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -1247,7 +1247,7 @@ verilog_library( name = "fse_proba_freq_dec_lib", srcs = [ ":fse_proba_freq_dec.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) @@ -1393,7 +1393,7 @@ verilog_library( name = "refilling_shift_buffer_internal_verilog_lib", srcs = [ ":refilling_shift_buffer_internal.v", - "//xls/modules/zstd/rtl:xls_fifo_wrapper.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", ], tags = ["manual"], ) diff --git a/xls/modules/zstd/rtl/BUILD b/xls/modules/zstd/rtl/BUILD index 9ca9c83ee3..4447877821 100644 --- a/xls/modules/zstd/rtl/BUILD +++ b/xls/modules/zstd/rtl/BUILD @@ -33,15 +33,15 @@ package( exports_files( [ - "zstd_dec_wrapper.v", - "xls_fifo_wrapper.v", + "zstd_dec_wrapper.sv", + "xls_fifo_wrapper.sv", ], ) verilog_library( name = "xls_fifo_wrapper_verilog_lib", srcs = [ - ":xls_fifo_wrapper.v", + ":xls_fifo_wrapper.sv", ], tags = ["manual"], ) diff --git a/xls/modules/zstd/rtl/xls_fifo_wrapper.v b/xls/modules/zstd/rtl/xls_fifo_wrapper.sv similarity index 100% rename from xls/modules/zstd/rtl/xls_fifo_wrapper.v rename to xls/modules/zstd/rtl/xls_fifo_wrapper.sv diff --git a/xls/modules/zstd/rtl/zstd_dec_wrapper.v b/xls/modules/zstd/rtl/zstd_dec_wrapper.sv similarity index 100% rename from xls/modules/zstd/rtl/zstd_dec_wrapper.v rename to xls/modules/zstd/rtl/zstd_dec_wrapper.sv From 7b3568ba296f60e9b7a3b061acb591eaca996eb7 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 29 May 2025 14:19:21 +0200 Subject: [PATCH 81/85] remove data generation with decodecorpus Let's use predefined data first and only then add zstd as dependency. Signed-off-by: Wojciech Sipak --- dependency_support/pip_requirements.in | 1 - dependency_support/pip_requirements_lock.txt | 53 ------- xls/modules/zstd/BUILD | 55 ------- xls/modules/zstd/data_generator.cc | 111 ------------- xls/modules/zstd/data_generator.h | 37 ----- xls/modules/zstd/data_generator.py | 66 -------- xls/modules/zstd/zstd_frame_dslx.py | 155 ------------------- 7 files changed, 478 deletions(-) delete mode 100644 xls/modules/zstd/data_generator.cc delete mode 100644 xls/modules/zstd/data_generator.h delete mode 100644 xls/modules/zstd/data_generator.py delete mode 100644 xls/modules/zstd/zstd_frame_dslx.py diff --git a/dependency_support/pip_requirements.in b/dependency_support/pip_requirements.in index 6ec69c187a..804306558e 100644 --- a/dependency_support/pip_requirements.in +++ b/dependency_support/pip_requirements.in @@ -13,7 +13,6 @@ pyyaml==6.0.1 # We build most of z3 ourselves but building python is really complicated. Just # use pypi version z3-solver==4.14.0.0 -zstandard==0.19.0 # Note: numpy and scipy version availability seems to differ between Ubuntu # versions that we want to support (e.g. 18.04 vs 20.04), so we accept a diff --git a/dependency_support/pip_requirements_lock.txt b/dependency_support/pip_requirements_lock.txt index cadc770f13..dc895c7f19 100644 --- a/dependency_support/pip_requirements_lock.txt +++ b/dependency_support/pip_requirements_lock.txt @@ -541,56 +541,3 @@ z3-solver==4.14.0.0 \ --hash=sha256:c10f899c6a876e3a50e9b2c4927604c2c3da3cca672b8ed3b7db1bc97259e47f \ --hash=sha256:e6ae32bc1cf4d25b96f790755d790a23118e8a09b9b6060e32238fe6ff43606d # via -r dependency_support/pip_requirements.in -zstandard==0.19.0 \ - --hash=sha256:04c298d381a3b6274b0a8001f0da0ec7819d052ad9c3b0863fe8c7f154061f76 \ - --hash=sha256:0fde1c56ec118940974e726c2a27e5b54e71e16c6f81d0b4722112b91d2d9009 \ - --hash=sha256:126aa8433773efad0871f624339c7984a9c43913952f77d5abeee7f95a0c0860 \ - --hash=sha256:1a4fb8b4ac6772e4d656103ccaf2e43e45bd16b5da324b963d58ef360d09eb73 \ - --hash=sha256:2e4812720582d0803e84aefa2ac48ce1e1e6e200ca3ce1ae2be6d410c1d637ae \ - --hash=sha256:2f01b27d0b453f07cbcff01405cdd007e71f5d6410eb01303a16ba19213e58e4 \ - --hash=sha256:31d12fcd942dd8dbf52ca5f6b1bbe287f44e5d551a081a983ff3ea2082867863 \ - --hash=sha256:3c927b6aa682c6d96225e1c797f4a5d0b9f777b327dea912b23471aaf5385376 \ - --hash=sha256:3d5bb598963ac1f1f5b72dd006adb46ca6203e4fb7269a5b6e1f99e85b07ad38 \ - --hash=sha256:401508efe02341ae681752a87e8ac9ef76df85ef1a238a7a21786a489d2c983d \ - --hash=sha256:4514b19abe6dbd36d6c5d75c54faca24b1ceb3999193c5b1f4b685abeabde3d0 \ - --hash=sha256:47dfa52bed3097c705451bafd56dac26535545a987b6759fa39da1602349d7ba \ - --hash=sha256:4fa496d2d674c6e9cffc561639d17009d29adee84a27cf1e12d3c9be14aa8feb \ - --hash=sha256:55a513ec67e85abd8b8b83af8813368036f03e2d29a50fc94033504918273980 \ - --hash=sha256:55b3187e0bed004533149882ef8c24e954321f3be81f8a9ceffe35099b82a0d0 \ - --hash=sha256:593f96718ad906e24d6534187fdade28b611f8ed06e27ba972ba48aecec45fc6 \ - --hash=sha256:5e21032efe673b887464667d09406bab6e16d96b09ad87e80859e3a20b6745b6 \ - --hash=sha256:60a86b7b2b1c300779167cf595e019e61afcc0e20c4838692983a921db9006ac \ - --hash=sha256:619f9bf37cdb4c3dc9d4120d2a1003f5db9446f3618a323219f408f6a9df6725 \ - --hash=sha256:660b91eca10ee1b44c47843894abe3e6cfd80e50c90dee3123befbf7ca486bd3 \ - --hash=sha256:67710d220af405f5ce22712fa741d85e8b3ada7a457ea419b038469ba379837c \ - --hash=sha256:6caed86cd47ae93915d9031dc04be5283c275e1a2af2ceff33932071f3eeff4d \ - --hash=sha256:6d2182e648e79213b3881998b30225b3f4b1f3e681f1c1eaf4cacf19bde1040d \ - --hash=sha256:72758c9f785831d9d744af282d54c3e0f9db34f7eae521c33798695464993da2 \ - --hash=sha256:74c2637d12eaacb503b0b06efdf55199a11b1d7c580bd3dd9dfe84cac97ef2f6 \ - --hash=sha256:755020d5aeb1b10bffd93d119e7709a2a7475b6ad79c8d5226cea3f76d152ce0 \ - --hash=sha256:7ccc4727300f223184520a6064c161a90b5d0283accd72d1455bcd85ec44dd0d \ - --hash=sha256:81ab21d03e3b0351847a86a0b298b297fde1e152752614138021d6d16a476ea6 \ - --hash=sha256:8371217dff635cfc0220db2720fc3ce728cd47e72bb7572cca035332823dbdfc \ - --hash=sha256:876567136b0359f6581ecd892bdb4ca03a0eead0265db73206c78cff03bcdb0f \ - --hash=sha256:879411d04068bd489db57dcf6b82ffad3c5fb2a1fdd30817c566d8b7bedee442 \ - --hash=sha256:898500957ae5e7f31b7271ace4e6f3625b38c0ac84e8cedde8de3a77a7fdae5e \ - --hash=sha256:8c9ca56345b0c5574db47560603de9d05f63cce5dfeb3a456eb60f3fec737ff2 \ - --hash=sha256:8ec2c146e10b59c376b6bc0369929647fcd95404a503a7aa0990f21c16462248 \ - --hash=sha256:8f7c68de4f362c1b2f426395fe4e05028c56d0782b2ec3ae18a5416eaf775576 \ - --hash=sha256:909bdd4e19ea437eb9b45d6695d722f6f0fd9d8f493e837d70f92062b9f39faf \ - --hash=sha256:9d97c713433087ba5cee61a3e8edb54029753d45a4288ad61a176fa4718033ce \ - --hash=sha256:a65e0119ad39e855427520f7829618f78eb2824aa05e63ff19b466080cd99210 \ - --hash=sha256:aa9087571729c968cd853d54b3f6e9d0ec61e45cd2c31e0eb8a0d4bdbbe6da2f \ - --hash=sha256:aef0889417eda2db000d791f9739f5cecb9ccdd45c98f82c6be531bdc67ff0f2 \ - --hash=sha256:b253d0c53c8ee12c3e53d181fb9ef6ce2cd9c41cbca1c56a535e4fc8ec41e241 \ - --hash=sha256:b80f6f6478f9d4ca26daee6c61584499493bf97950cfaa1a02b16bb5c2c17e70 \ - --hash=sha256:be6329b5ba18ec5d32dc26181e0148e423347ed936dda48bf49fb243895d1566 \ - --hash=sha256:c7560f622e3849cc8f3e999791a915addd08fafe80b47fcf3ffbda5b5151047c \ - --hash=sha256:d1a7a716bb04b1c3c4a707e38e2dee46ac544fff931e66d7ae944f3019fc55b8 \ - --hash=sha256:d63b04e16df8ea21dfcedbf5a60e11cbba9d835d44cb3cbff233cfd037a916d5 \ - --hash=sha256:d777d239036815e9b3a093fa9208ad314c040c26d7246617e70e23025b60083a \ - --hash=sha256:e892d3177380ec080550b56a7ffeab680af25575d291766bdd875147ba246a91 \ - --hash=sha256:e9c90a44470f2999779057aeaf33461cbd8bb59d8f15e983150d10bb260e16e0 \ - --hash=sha256:f097dda5d4f9b9b01b3c9fa2069f9c02929365f48f341feddf3d6b32510a2f93 \ - --hash=sha256:f4ebfe03cbae821ef994b2e58e4df6a087470cc522aca502614e82a143365d45 - # via -r dependency_support/pip_requirements.in diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 44720fa8f5..f8c8e56cab 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -17,7 +17,6 @@ load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route") load("@rules_hdl//synthesis:build_defs.bzl", "benchmark_synth", "synthesize_rtl") load("@rules_hdl//verilog:providers.bzl", "verilog_library") -load("@xls_pip_deps//:requirements.bzl", "requirement") load( "//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_ir", @@ -347,36 +346,6 @@ xls_benchmark_verilog( verilog_target = "shift_buffer_verilog", ) -cc_library( - name = "data_generator", - srcs = ["data_generator.cc"], - hdrs = ["data_generator.h"], - data = [ - "@zstd//:decodecorpus", - ], - tags = ["manual"], - deps = [ - "//xls/common:subprocess", - "//xls/common/file:filesystem", - "//xls/common/file:get_runfile_path", - "//xls/common/status:status_macros", - "@com_google_absl//absl/algorithm:container", - "@com_google_absl//absl/status:statusor", - "@com_google_absl//absl/strings", - "@com_google_absl//absl/time", - "@com_google_absl//absl/types:span", - ], -) - -py_library( - name = "data_generator_py", - srcs = ["data_generator.py"], - deps = [ - "//xls/common:runfiles", - "@zstd//:decodecorpus", - ], -) - xls_dslx_library( name = "common_dslx", srcs = [ @@ -1452,29 +1421,6 @@ xls_dslx_test( tags = ["manual"], ) -py_binary( - name = "zstd_test_frames_generator", - srcs = ["zstd_frame_dslx.py"], - imports = ["."], - main = "zstd_frame_dslx.py", - tags = ["manual"], - visibility = ["//xls:xls_users"], - deps = [ - requirement("zstandard"), - "//xls/common:runfiles", - ":data_generator_py", - "@com_google_protobuf//:protobuf_python", - ], -) - -genrule( - name = "zstd_test_frames_generate", - srcs = [], - outs = ["zstd_frame_testcases.x"], - cmd = "$(location :zstd_test_frames_generator) --seed 36 -n 1 --btype COMPRESSED -o $@", - tools = [":zstd_test_frames_generator"], -) - xls_dslx_library( name = "ram_merge_dslx", srcs = ["ram_merge.x"], @@ -1522,7 +1468,6 @@ xls_dslx_test( "data/comp_frame_huffman_fse.x", "zstd_dec.x", "zstd_dec_test.x", - "zstd_frame_testcases.x", ], tags = ["manual"], deps = zstd_dec_deps, diff --git a/xls/modules/zstd/data_generator.cc b/xls/modules/zstd/data_generator.cc deleted file mode 100644 index 98b1eb4dba..0000000000 --- a/xls/modules/zstd/data_generator.cc +++ /dev/null @@ -1,111 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -#include "xls/modules/zstd/data_generator.h" - -#include -#include -#include -#include // NOLINT -#include -#include -#include -#include - -#include "absl/algorithm/container.h" -#include "absl/status/statusor.h" -#include "absl/strings/str_cat.h" -#include "absl/strings/str_join.h" -#include "absl/time/time.h" -#include "absl/types/span.h" -#include "xls/common/file/filesystem.h" -#include "xls/common/file/get_runfile_path.h" -#include "xls/common/status/status_macros.h" -#include "xls/common/subprocess.h" - -namespace xls::zstd { - -static std::string CreateNameForGeneratedFile( - absl::Span args, std::string_view ext, - std::optional prefix) { - std::string output; - - if (prefix.has_value()) { - absl::StrAppend(&output, prefix.value(), "_"); - } - absl::StrAppend(&output, absl::StrJoin(args, "")); - - std::erase(output, ' '); - absl::c_replace(output, '-', '_'); - absl::c_replace(output, '=', '_'); - - output += ext; - - return output; -} - -static absl::StatusOr CallDecodecorpus( - absl::Span args, - const std::optional& cwd = std::nullopt, - std::optional timeout = std::nullopt) { - XLS_ASSIGN_OR_RETURN(std::filesystem::path path, - xls::GetXlsRunfilePath("external/zstd/decodecorpus")); - - std::vector cmd = {path}; - cmd.insert(cmd.end(), args.begin(), args.end()); - return SubprocessErrorAsStatus(xls::InvokeSubprocess(cmd)); -} - -absl::StatusOr> GenerateFrameHeader(int seed, bool magic) { - std::array args; - args[0] = "-s" + std::to_string(seed); - args[1] = (magic) ? "" : "--no-magic"; - args[2] = "--frame-header-only"; - std::filesystem::path output_path = - std::filesystem::temp_directory_path() / - std::filesystem::path( - CreateNameForGeneratedFile(absl::MakeSpan(args), ".zstd", "fh")); - args[3] = "-p" + std::string(output_path); - - XLS_ASSIGN_OR_RETURN(auto result, CallDecodecorpus(args)); - XLS_ASSIGN_OR_RETURN(auto raw_data, xls::GetFileContents(output_path)); - std::remove(output_path.c_str()); - return std::vector(raw_data.begin(), raw_data.end()); -} - -absl::StatusOr> GenerateFrame(int seed, BlockType btype) { - std::vector args; - args.push_back("-s" + std::to_string(seed)); - if (btype != BlockType::RANDOM) { - args.push_back("--block-type=" + std::to_string(static_cast(btype))); - } - if (btype == BlockType::RLE) { - args.push_back("--content-size"); - } - // Test payloads up to 16KB - args.push_back("--max-content-size-log=14"); - std::filesystem::path output_path = - std::filesystem::temp_directory_path() / - std::filesystem::path( - CreateNameForGeneratedFile(absl::MakeSpan(args), ".zstd", "frame")); - args.push_back("-p" + std::string(output_path)); - - XLS_ASSIGN_OR_RETURN(auto result, CallDecodecorpus(args)); - XLS_ASSIGN_OR_RETURN(auto raw_data, xls::GetFileContents(output_path)); - std::remove(output_path.c_str()); - return std::vector(raw_data.begin(), raw_data.end()); -} - -} // namespace xls::zstd diff --git a/xls/modules/zstd/data_generator.h b/xls/modules/zstd/data_generator.h deleted file mode 100644 index a3967a1317..0000000000 --- a/xls/modules/zstd/data_generator.h +++ /dev/null @@ -1,37 +0,0 @@ -// Copyright 2024 The XLS Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -#ifndef XLS_MODULES_ZSTD_DATA_GENERATOR_H_ -#define XLS_MODULES_ZSTD_DATA_GENERATOR_H_ - -#include -#include - -#include "absl/status/statusor.h" - -namespace xls::zstd { - -enum class BlockType { - RAW, - RLE, - COMPRESSED, - RANDOM, -}; - -absl::StatusOr> GenerateFrameHeader(int seed, bool magic); -absl::StatusOr> GenerateFrame(int seed, BlockType btype); - -} // namespace xls::zstd - -#endif // XLS_MODULES_ZSTD_DATA_GENERATOR_H_ diff --git a/xls/modules/zstd/data_generator.py b/xls/modules/zstd/data_generator.py deleted file mode 100644 index 46a74acbfc..0000000000 --- a/xls/modules/zstd/data_generator.py +++ /dev/null @@ -1,66 +0,0 @@ -# Copyright 2024 The XLS Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -"""Module for generating and decompressing test frames.""" - -import pathlib -import enum - -from xls.common import runfiles -import subprocess -import zstandard - -class BlockType(enum.Enum): - """Enum encoding of ZSTD block types.""" - - RAW = 0 - RLE = 1 - COMPRESSED = 2 - RANDOM = 3 - - def __str__(self): - return self.name - - @staticmethod - def from_string(s): - try: - return BlockType[s] - except KeyError as e: - raise ValueError(str(e)) from e - -def CallDecodecorpus(args): - decodecorpus = pathlib.Path( - runfiles.get_path("decodecorpus", repository = "zstd") - ) - cmd = args - cmd.insert(0, str(decodecorpus)) - cmd_concat = " ".join(cmd) - subprocess.run(cmd_concat, shell=True, check=True) - -def DecompressFrame(data): - dctx = zstandard.ZstdDecompressor() - return dctx.decompress(data) - -def GenerateFrame(seed, btype, output_path): - args = [] - args.append("-s" + str(seed)) - if (btype != BlockType.RANDOM): - args.append("--block-type=" + str(btype.value)) - args.append("--content-size") - # Test payloads up to 16KB - args.append("--max-content-size-log=14") - args.append("-p" + output_path) - args.append("-vvvvvvv") - - CallDecodecorpus(args) diff --git a/xls/modules/zstd/zstd_frame_dslx.py b/xls/modules/zstd/zstd_frame_dslx.py deleted file mode 100644 index 5304e07f45..0000000000 --- a/xls/modules/zstd/zstd_frame_dslx.py +++ /dev/null @@ -1,155 +0,0 @@ -# Copyright 2024 The XLS Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -"""ZSTD test frame generator for DSLX tests. - -This module interacts with the data_generator module and underlying -Decodecorpus in order to generate inputs and expected outputs for the ZSTD -Decoder tests in DSLX. - -It generates the ZSTD frame and then decodes it with the reference ZSTD -library. Both the encoded frame and decoded data are written to a DSLX file by -converting raw bytes of the frame and decoded data into DSLX structures. - -Resulting file can be included in the ZSTD Decoder DSLX test and used as the -inputs and expected output for the testbench. -""" - -import argparse -import math -import random -import tempfile -import pathlib - -from xls.modules.zstd import data_generator - - -def GenerateTestData(seed, btype): - with tempfile.NamedTemporaryFile() as tmp: - data_generator.GenerateFrame(seed, btype, tmp.name) - tmp.seek(0) - return tmp.read() - - -def Bytes2DSLX(frames, bytes_per_word, array_name): - """Converts a list of byte frames to a DSLX constant array declaration. - - Args: - frames (List[bytes]): List of byte sequences representing frames. - bytes_per_word (int): Number of bytes per word in the output format. - array_name (str): Name of the resulting DSLX constant array. - - Returns: - str: A string containing the DSLX constant array declaration. - """ - frames_hex = [] - maxlen = max(len(frame) for frame in frames) - maxlen_size = math.ceil(maxlen / bytes_per_word) - bits_per_word = bytes_per_word * 8 - for i, frame in enumerate(frames): - frame_hex = [] - for i in range(0, len(frame), bytes_per_word): - # reverse byte order to make them little endian - word = bytes(reversed(frame[i : i + bytes_per_word])).hex() - frame_hex.append(f"uN[{bits_per_word}]:0x{word}") - - array_length = len(frame_hex) - if len(frame) < maxlen: - frame_hex += [f"uN[{bits_per_word}]:0x0", "..."] - - frame_array = ( - f"DataArray<{bits_per_word}, {maxlen_size}>{{\n" - f" length: u32:{len(frame)},\n" - f" array_length: u32:{array_length},\n" - f" data: uN[{bits_per_word}][{maxlen_size}]:[{', '.join(frame_hex)}]\n" - f"}}" - ) - frames_hex.append(frame_array) - - frames_str = ",\n".join(frames_hex) - frames_array = ( - f"pub const {array_name}:DataArray<\n" - f" u32:{bits_per_word},\n" - f" u32:{maxlen_size}\n" - f">[{len(frames_hex)}] = [{frames_str}];\n" - ) - return frames_array - - -def GenerateDataStruct(): - return ( - "pub struct DataArray{\n" - " data: uN[BITS_PER_WORD][LENGTH],\n" - " length: u32,\n" - " array_length: u32\n" - "}\n" - ) - - -def main(): - parser = argparse.ArgumentParser() - parser.add_argument( - "-n", help="Number of testcases to generate", type=int, default=1 - ) - parser.add_argument( - "--seed", help="Seed for the testcases generator", type=int, default=0 - ) - parser.add_argument( - "--btype", - help=( - "Block types allowed in the generated testcases. If multiple block types " - "are supplied, generated testcases will cycle through them" - ), - type=data_generator.BlockType.from_string, - choices=list(data_generator.BlockType), - default=data_generator.BlockType.RANDOM, - nargs="+", - ) - parser.add_argument( - "-o", - "--output", - help="Filename of the DSLX output file", - type=pathlib.Path, - default=pathlib.Path("frames_test_data.x"), - ) - parser.add_argument( - "--bytes-per-word", - help="Width of a word in memory, in bytes", - type=int, - default=8, - ) - args = parser.parse_args() - - random.seed(args.seed) - byte_frames = [ - GenerateTestData(random.randrange(2**32), args.btype[i % len(args.btype)]) - for i in range(args.n) - ] - with open(args.output, "w") as dslx_output: - dslx_output.write(GenerateDataStruct()) - - dslx_frames = Bytes2DSLX(byte_frames, args.bytes_per_word, "FRAMES") - dslx_output.write(dslx_frames) - - byte_frames_decompressed = list( - map(data_generator.DecompressFrame, byte_frames) - ) - dslx_frames_decompressed = Bytes2DSLX( - byte_frames_decompressed, args.bytes_per_word, "DECOMPRESSED_FRAMES" - ) - dslx_output.write(dslx_frames_decompressed) - - -if __name__ == "__main__": - main() From 3880499d0cc551024b80a4760b1d57e23a9f8be7 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Fri, 30 May 2025 10:54:25 +0200 Subject: [PATCH 82/85] Fix type checking in huffman_prescan.x Signed-off-by: Robert Winkler --- xls/modules/zstd/huffman_literals_dec.x | 8 ++------ xls/modules/zstd/huffman_prescan.x | 27 ++++++++++++------------- 2 files changed, 15 insertions(+), 20 deletions(-) diff --git a/xls/modules/zstd/huffman_literals_dec.x b/xls/modules/zstd/huffman_literals_dec.x index b60cadedad..22f328688d 100644 --- a/xls/modules/zstd/huffman_literals_dec.x +++ b/xls/modules/zstd/huffman_literals_dec.x @@ -29,10 +29,6 @@ import xls.modules.zstd.memory.axi_ram_reader; import xls.modules.zstd.memory.mem_reader as mem_reader; import xls.examples.ram; -pub fn WeightPreScanMetaDataSize() -> u32 { - prescan::WeightPreScanMetaDataSize() -} - pub type HuffmanLiteralsDecoderReq = ctrl::HuffmanControlAndSequenceCtrl; pub type HuffmanLiteralsDecoderResp = ctrl::HuffmanControlAndSequenceResp; pub type HuffmanLiteralsDecoderStatus = ctrl::HuffmanControlAndSequenceStatus; @@ -45,7 +41,7 @@ pub const WEIGHTS_NUM_PARTITIONS = ram::num_partitions(WEIGHTS_PARTITION_WORD_SI // pub const WEIGHTS_NUM_PARTITIONS: u32 = u32:1; pub const PRESCAN_ADDR_WIDTH: u32 = prescan::RAM_ADDR_WIDTH; -pub const PRESCAN_DATA_WIDTH: u32 = prescan::WeightPreScanMetaDataSize(); +pub const PRESCAN_DATA_WIDTH: u32 = prescan::WEIGHT_PRESCAN_METADATA_SIZE; pub const PRESCAN_PARTITION_WORD_SIZE: u32 = PRESCAN_DATA_WIDTH; pub const PRESCAN_NUM_PARTITIONS = ram::num_partitions(PRESCAN_PARTITION_WORD_SIZE, PRESCAN_DATA_WIDTH); @@ -498,7 +494,7 @@ pub const TEST_PRESCAN_RAM_ADDR_WIDTH = PRESCAN_ADDR_WIDTH; pub const TEST_PRESCAN_RAM_DATA_WIDTH = PRESCAN_DATA_WIDTH; pub const TEST_PRESCAN_RAM_NUM_PARTITIONS = PRESCAN_NUM_PARTITIONS; pub const TEST_PRESCAN_RAM_SIZE = prescan::RAM_SIZE; -pub const TEST_PRESCAN_WORD_PARTITION_SIZE = prescan::WeightPreScanMetaDataSize(); +pub const TEST_PRESCAN_WORD_PARTITION_SIZE = prescan::WEIGHT_PRESCAN_METADATA_SIZE; const TEST_WEIGHTS_DPD_RAM_DATA_W = u32:16; const TEST_WEIGHTS_DPD_RAM_SIZE = u32:256; diff --git a/xls/modules/zstd/huffman_prescan.x b/xls/modules/zstd/huffman_prescan.x index 47487a45c6..6a8338cd27 100644 --- a/xls/modules/zstd/huffman_prescan.x +++ b/xls/modules/zstd/huffman_prescan.x @@ -53,14 +53,13 @@ const COUNTER_WIDTH = hcommon::COUNTER_WIDTH; type WeightPreScanMetaData = hcommon::WeightPreScanMetaData; type WeightPreScanOutput = hcommon::WeightPreScanOutput; -pub fn WeightPreScanMetaDataSize() -> u32 { +pub const WEIGHT_PRESCAN_METADATA_SIZE = (COUNTER_WIDTH as u32) * (PARALLEL_ACCESS_WIDTH as u32) + (MAX_WEIGHT as u32) + u32:1 + - (COUNTER_WIDTH as u32) * (MAX_WEIGHT as u32 + u32:1) -} + (COUNTER_WIDTH as u32) * (MAX_WEIGHT as u32 + u32:1); fn InternalStructToBits< - BITS: u32 = {WeightPreScanMetaDataSize()}, + BITS: u32 = {WEIGHT_PRESCAN_METADATA_SIZE}, OCCURANCE_WIDTH: u32 ={COUNTER_WIDTH * PARALLEL_ACCESS_WIDTH}, > (internalStruct: WeightPreScanMetaData) -> bits[BITS] { (internalStruct.weights_count as bits[COUNTER_WIDTH * (MAX_WEIGHT + u32:1)] ++ @@ -69,7 +68,7 @@ fn InternalStructToBits< } fn BitsToInternalStruct< - BITS: u32 = {WeightPreScanMetaDataSize()}, + BITS: u32 = {WEIGHT_PRESCAN_METADATA_SIZE}, OCCURANCE_WIDTH: u32 ={COUNTER_WIDTH * PARALLEL_ACCESS_WIDTH}, > (rawBits: bits[BITS]) -> WeightPreScanMetaData { WeightPreScanMetaData { @@ -80,7 +79,7 @@ fn BitsToInternalStruct< } #[quickcheck(test_count=50000)] -fn bits_to_struct_to_bits_qtest(x: bits[WeightPreScanMetaDataSize()]) -> bool { +fn bits_to_struct_to_bits_qtest(x: bits[WEIGHT_PRESCAN_METADATA_SIZE]) -> bool { x == InternalStructToBits(BitsToInternalStruct(x)) } @@ -131,11 +130,11 @@ pub proc WeightPreScan type InternalRamAddr = uN[RAM_ADDR_WIDTH]; type InternalData = WeightPreScanMetaData; - type InternalRamData = bits[WeightPreScanMetaDataSize()]; + type InternalRamData = bits[WEIGHT_PRESCAN_METADATA_SIZE]; type InternalReadReq = ram::ReadReq; - type InternalReadResp = ram::ReadResp<{WeightPreScanMetaDataSize()}>; - type InternalWriteReq = ram::WriteReq; + type InternalReadResp = ram::ReadResp; + type InternalWriteReq = ram::WriteReq; type InternalWriteResp = ram::WriteResp; start_r: chan in; @@ -328,12 +327,12 @@ proc Prescan_test{ type ReadReq = ram::ReadReq; type ReadResp = ram::ReadResp; type WriteReq = ram::WriteReq; - type WriteResp = ram::WriteResp<>; + type WriteResp = ram::WriteResp; type InternalReadReq = ram::ReadReq; - type InternalReadResp = ram::ReadResp<{WeightPreScanMetaDataSize()}>; - type InternalWriteReq = ram::WriteReq; - type InternalWriteResp = ram::WriteResp<>; + type InternalReadResp = ram::ReadResp; + type InternalWriteReq = ram::WriteReq; + type InternalWriteResp = ram::WriteResp; terminator: chan out; external_ram_req: chan out; @@ -357,7 +356,7 @@ proc Prescan_test{ let (RAMInternalWriteResp_s, RAMInternalWriteResp_r) = chan("Internal_write_channel_resp"); let (RAMInternalReadReq_s, RAMInternalReadReq_r) = chan("Internal_read_channel_req"); let (RAMInternalReadResp_s, RAMInternalReadResp_r) = chan("Internal_read_channel_resp"); - spawn ram::RamModel<{WeightPreScanMetaDataSize()}, RAM_SIZE, {WeightPreScanMetaDataSize()}>( + spawn ram::RamModel( RAMInternalReadReq_r, RAMInternalReadResp_s, RAMInternalWriteReq_r, RAMInternalWriteResp_s ); From 8f32ca9513d883affc75161a555a397954dffc5f Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 3 Jun 2025 17:40:02 +0200 Subject: [PATCH 83/85] Mark long DSLX tests as local Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index f8c8e56cab..001b36234b 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -1418,7 +1418,10 @@ xls_dslx_test( name = "comp_block_dec_dslx_test", size = "enormous", library = ":comp_block_dec_dslx", - tags = ["manual"], + tags = [ + "local", + "manual", + ], ) xls_dslx_library( @@ -1469,7 +1472,10 @@ xls_dslx_test( "zstd_dec.x", "zstd_dec_test.x", ], - tags = ["manual"], + tags = [ + "local", + "manual", + ], deps = zstd_dec_deps, ) @@ -2222,7 +2228,10 @@ xls_dslx_library( xls_dslx_test( name = "sequence_dec_dslx_test", library = ":sequence_dec_dslx", - tags = ["manual"], + tags = [ + "local", + "manual", + ], ) xls_dslx_verilog( @@ -3208,7 +3217,10 @@ xls_dslx_test( name = "huffman_weights_dec_dslx_test", size = "large", library = ":huffman_weights_dec_dslx", - tags = ["manual"], + tags = [ + "local", + "manual", + ], ) huffman_weights_dec_codegen_args = common_codegen_args | { From 2838baa29f5505c17b033614716851a429561f23 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Mon, 2 Jun 2025 17:05:23 +0200 Subject: [PATCH 84/85] Add suffix to long P&R targets The CI setup for the zstd module uses a bazel query to find groups of targets that share a common suffix. By appending `_skip` to a target name, the query no longer matches it, effectively excluding that target from the CI run. Signed-off-by: Robert Winkler --- xls/modules/zstd/BUILD | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 001b36234b..f22eaac8ac 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -2687,8 +2687,9 @@ benchmark_synth( tags = ["manual"], ) +# TODO: Remove _skip suffix after fixing long P&R time. Used now to skip this target in CI. place_and_route( - name = "literals_decoder_place_and_route", + name = "literals_decoder_place_and_route_skip", clock_period = "750", core_padding_microns = 2, min_pin_distance = "0.5", @@ -3024,8 +3025,9 @@ benchmark_synth( tags = ["manual"], ) +# TODO: Remove _skip suffix after fixing long P&R time. Used now to skip this target in CI. place_and_route( - name = "huffman_data_preprocessor_place_and_route", + name = "huffman_data_preprocessor_place_and_route_skip", clock_period = "750", core_padding_microns = 2, min_pin_distance = "0.5", @@ -3101,8 +3103,9 @@ benchmark_synth( tags = ["manual"], ) +# TODO: Remove _skip suffix after fixing long P&R time. Used now to skip this target in CI. place_and_route( - name = "huffman_decoder_place_and_route", + name = "huffman_decoder_place_and_route_skip", clock_period = "750", core_padding_microns = 2, min_pin_distance = "0.5", @@ -3360,8 +3363,9 @@ benchmark_synth( tags = ["manual"], ) +# TODO: Remove _skip suffix after fixing long P&R time. Used now to skip this target in CI. place_and_route( - name = "huffman_literals_dec_place_and_route", + name = "huffman_literals_dec_place_and_route_skip", clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", From 484cc69a32a6653b7001a8aabc884e839eb09561 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Mon, 9 Jun 2025 23:35:43 +0200 Subject: [PATCH 85/85] Make filter rules more strict Make Bazel queries stricter so that target names must end exactly with the specified suffix, without allowing any additional characters after it. Signed-off-by: Robert Winkler --- .github/workflows/modules-zstd.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/modules-zstd.yml b/.github/workflows/modules-zstd.yml index f82b5cd010..4272e4b91b 100644 --- a/.github/workflows/modules-zstd.yml +++ b/.github/workflows/modules-zstd.yml @@ -45,17 +45,17 @@ jobs: - name: Test ZSTD Module - DSLX Tests (opt) if: ${{ !cancelled() }} run: | - bazel test -c opt --test_output=errors -- $(bazel query 'filter(".*_dslx_test", kind(rule, //xls/modules/zstd/...))') + bazel test -c opt --test_output=errors -- $(bazel query 'filter("_dslx_test$", kind(rule, //xls/modules/zstd/...))') - name: Build ZSTD verilog targets (opt) if: ${{ !cancelled() }} run: | - bazel build -c opt -- $(bazel query 'filter(".*_verilog", kind(rule, //xls/modules/zstd/...))') + bazel build -c opt -- $(bazel query 'filter("_verilog$", kind(rule, //xls/modules/zstd/...))') - name: Build and run ZSTD IR benchmark rules (opt) if: ${{ !cancelled() }} run: | - for target in $(bazel query 'filter(".*_ir_benchmark$", kind(rule, //xls/modules/zstd/...))'); + for target in $(bazel query 'filter("_ir_benchmark$", kind(rule, //xls/modules/zstd/...))'); do echo "running $target"; bazel run -c opt $target -- --logtostderr; @@ -64,7 +64,7 @@ jobs: - name: Build and run synthesis benchmarks of the ZSTD module (opt) if: ${{ !cancelled() }} run: | - for target in $(bazel query 'filter(".*_benchmark_synth$", kind(rule, //xls/modules/zstd/...))'); + for target in $(bazel query 'filter("_benchmark_synth$", kind(rule, //xls/modules/zstd/...))'); do echo "running $target"; bazel run -c opt $target -- --logtostderr; @@ -73,4 +73,4 @@ jobs: - name: Build ZSTD place and route targets (opt) if: ${{ !cancelled() }} run: | - bazel build -c opt -- $(bazel query 'filter(".*_place_and_route", kind(rule, //xls/modules/zstd/...))') + bazel build -c opt -- $(bazel query 'filter("_place_and_route$", kind(rule, //xls/modules/zstd/...))')

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