It looks like j68_dpram_2048x20 is actually comprised of 4 upper bits plus 16 lower bits. I am not sure whether the port A (micro-instruction) reader cares about the lower 16 bits. Those 16-bits are then written to in two 8-bit halves.
This odd access conditions make the synthesizer struggle with this block, which eventually takes up a lot of logic and gets synthesized in a mix of many logic cells (>6000), logic registers (>1000) and one M9K cell.
The reset pin makes things more awkward too for the synthesizer. That pin can actually be removed without breaking the upper logic.
If the upper 4-bits are independent of the lower 16-bits, it would be good to break this memory in two, instead of sharing it.
It looks like j68_dpram_2048x20 is actually comprised of 4 upper bits plus 16 lower bits. I am not sure whether the port A (micro-instruction) reader cares about the lower 16 bits. Those 16-bits are then written to in two 8-bit halves.
This odd access conditions make the synthesizer struggle with this block, which eventually takes up a lot of logic and gets synthesized in a mix of many logic cells (>6000), logic registers (>1000) and one M9K cell.
The reset pin makes things more awkward too for the synthesizer. That pin can actually be removed without breaking the upper logic.
If the upper 4-bits are independent of the lower 16-bits, it would be good to break this memory in two, instead of sharing it.