Indexed addressing mode on 24bit misassembly

[fachat]

There is one problem as seen in fachat/upet_ioext@aa628d0
where this code
62 A:043d 9f 00 00 01 sta IOEXT_BASE+BANK<<15,x
is misassembled.

The opcode seems to be right ($9f = abs long x-indexed https://undisbeliever.net/snesdev/65816-opcodes.html#sta-store-accumulator-to-memory )
But the address is not. It should be $77000, as BANK is 14, and IOEXT_BASE is $7000

Both variables are defined already in pass1 before that place (so should be known)

[fachat]

I think the problem is the following.

1. the priority of the shift operator is wrong. It seems to be less than addition, so the address is first added, then shifted
2. the shift somehow only does 17 bits....

The following change results in this:
62 A:043d 9f 00 70 01 sta IOEXT_BASE+(BANK<<15),x

This correctly adds the IOEXT_BASE of $7000 to a value of $10000, which is wrong.
...
meh user error. It should be IOCOMPBANK instead of BANK (which is the actual BANK register).

But still 1. holds - shift seems lower prio than add.
62 A:043d 9f 00 00 07 sta IOEXT_BASE+IOCOMPBANK<<15,x
62 A:043d 9f 00 00 07 sta IOCOMPBANK<<15+IOEXT_BASE,x

but correct is still
62 A:043d 9f 00 70 07 sta IOEXT_BASE+(IOCOMPBANK<<15),x