diff --git a/README.md b/README.md
index 13fe34cb0..f73b3b3cf 100644
--- a/README.md
+++ b/README.md
@@ -95,9 +95,10 @@ For the following systems, the Bluespec toolchain is available
 as a package that can be installed with the standard package manager:
 
 * ArchLinux AUR: [`bluespec-git`](https://aur.archlinux.org/packages/bluespec-git/) ([among others](https://aur.archlinux.org/packages/?K=bluespec))
+* Fedora ([Terra Repository](https://terrapkg.com/)): [`bsc`](https://github.com/terrapkg/packages/tree/frawhide/anda/buildsys/bsc)
 * Gentoo GURU and LiGurOS: [`sci-electronics/bluespec`](https://gitweb.gentoo.org/repo/proj/guru.git/tree/sci-electronics/bluespec)
+* Homebrew: [`bsc`](https://formulae.brew.sh/formula/bsc)
 * Nix/NixOS: [`bluespec`](https://search.nixos.org/packages?channel=20.09&from=0&size=50&sort=relevance&query=bluespec)
-* Fedora ([Terra Repository](https://terrapkg.com/)): [`bsc`](https://github.com/terrapkg/packages/tree/frawhide/anda/buildsys/bsc)
 
 You can also use the [Repology search engine](https://repology.org/project/bluespec/versions)
 to check for Bluespec packages for your system.
diff --git a/src/Libraries/Base1/Foldable.bs b/src/Libraries/Base1/Foldable.bs
new file mode 100644
index 000000000..4982f7556
--- /dev/null
+++ b/src/Libraries/Base1/Foldable.bs
@@ -0,0 +1,185 @@
+package Foldable where
+
+import qualified Array
+import qualified List
+import qualified ListN
+import qualified Vector
+
+--@ \index{Foldable@\te{Foldable} (type class)}
+--@ The class of container types that can be folded to a summary value.
+--@ A minimal complete definition need only implement \te{foldr}; all
+--@ other methods have defaults derived from \te{foldr}, but instances
+--@ may override them for efficiency.
+--@ \begin{libverbatim}
+--@ typeclass Foldable #(type t);
+--@   function b foldr(function b fn(a x, b z), b z, t#(a) xs);
+--@   function b foldl(function b fn(b z, a x), b z, t#(a) xs);
+--@   function m#(b) foldrM(function m#(b) fn(a x, b z), b z, t#(a) xs)
+--@     provisos (Monad#(m));
+--@   function m#(b) foldlM(function m#(b) fn(b z, a x), b z, t#(a) xs)
+--@     provisos (Monad#(m));
+--@   function f#(void) traverse_(function f#(b) fn(a x), t#(a) xs)
+--@     provisos (Applicative#(f));
+--@   function f#(void) sequenceA_(t#(f#(a)) xs)
+--@     provisos (Applicative#(f));
+--@   function m#(void) mapM_(function m#(b) fn(a x), t#(a) xs)
+--@     provisos (Monad#(m));
+--@   function m#(void) sequence_(t#(m#(a)) xs)
+--@     provisos (Monad#(m));
+--@   function List#(a) toList(t#(a) xs);
+--@   function Bool elem(a x, t#(a) xs)
+--@     provisos (Eq#(a));
+--@   function Integer length(t#(a) xs);
+--@   function Bool null(t#(a) xs);
+--@ endtypeclass
+--@ \end{libverbatim}
+class Foldable t where
+  foldr :: (a -> b -> b) -> b -> t a -> b
+
+  foldl :: (b -> a -> b) -> b -> t a -> b
+  foldl f z0 xs = foldr (\ x k z -> k (f z x)) id xs z0
+
+  -- Monadic right fold: like \te{foldr} but the step function returns
+  -- an action and the accumulator threads through the monadic context.
+  foldrM :: (Monad m) => (a -> b -> m b) -> b -> t a -> m b
+  foldrM f z0 xs = foldr (\ x k z -> f x z `bind` k) pure xs z0
+
+  -- Monadic left fold: like \te{foldl} but the step function returns
+  -- an action and the accumulator threads through the monadic context.
+  foldlM :: (Monad m) => (b -> a -> m b) -> b -> t a -> m b
+  foldlM f z0 xs = foldr (\ x k z -> f z x `bind` k) pure xs z0
+
+  -- The `_` traversal helpers sequence the actions left-to-right and
+  -- discard the rebuilt container. They only need \te{Foldable} (no
+  -- \te{Traversable}) because the action sequencing can be expressed
+  -- via \te{foldr}.
+  traverse_ :: (Applicative f) => (a -> f b) -> t a -> f ()
+  traverse_ f = foldr (\ x acc -> f x *> acc) (pure ())
+
+  sequenceA_ :: (Applicative f) => t (f a) -> f ()
+  sequenceA_ = foldr (*>) (pure ())
+
+  mapM_ :: (Monad m) => (a -> m b) -> t a -> m ()
+  mapM_ = traverse_
+
+  sequence_ :: (Monad m) => t (m a) -> m ()
+  sequence_ = sequenceA_
+
+  toList :: t a -> List a
+  toList = foldr Cons Nil
+
+  elem :: (Eq a) => a -> t a -> Bool
+  elem x = foldr (\ y acc -> y == x || acc) False
+
+  length :: t a -> Integer
+  length = foldr (\ _ n -> n + 1) 0
+
+  null :: t a -> Bool
+  null = foldr (\ _ _ -> False) True
+
+instance Foldable Array where
+  foldr = Array.foldr
+  foldl = Array.foldl
+  toList = Array.arrayToList
+
+instance Foldable List where
+  foldr = List.foldr
+  foldl = List.foldl
+  mapM_ = List.mapM_
+  toList = id
+  length = List.length
+  null = List.null
+
+instance Foldable (ListN.ListN n) where
+  foldr = ListN.foldr
+  foldl = ListN.foldl
+  mapM_ = ListN.mapM_
+  toList = ListN.toList
+  length _ = valueOf n
+  null _ = valueOf n == 0
+
+instance Foldable (Vector.Vector n) where
+  foldr = Vector.foldr
+  foldl = Vector.foldl
+  mapM_ = Vector.mapM_
+  toList = Vector.toList
+  length _ = valueOf n
+  null _ = valueOf n == 0
+
+instance Foldable Maybe where
+  foldr _ z Invalid   = z
+  foldr f z (Valid x) = f x z
+  foldl _ z Invalid   = z
+  foldl f z (Valid x) = f z x
+  toList Invalid   = Nil
+  toList (Valid x) = Cons x Nil
+  length Invalid   = 0
+  length (Valid _) = 1
+  null Invalid   = True
+  null (Valid _) = False
+
+--@ \index{Foldable1@\te{Foldable1} (type class)}
+--@ Fold operations that require the container to be non-empty.
+--@ This is seperated from \te{Foldable} because fixed-size containers
+--@ (e.g.\ \te{Vector n}, \te{ListN n}) may require an extra proviso to
+--@ assert non-zero size, not needed by the corresponding \te{Foldable}
+--@ instances.
+--@ \begin{libverbatim}
+--@ typeclass Foldable1 #(type t)
+--@   provisos (Foldable#(t));
+--@   function a foldr1(function a fn(a x, a y), t#(a) xs);
+--@   function a foldl1(function a fn(a x, a y), t#(a) xs);
+--@   function a fold(function a fn(a x, a y), t#(a) xs);
+--@   function m#(a) foldM(function m#(a) f(a x, a y), t#(a) xs)
+--@     provisos (Monad#(m));
+--@   function m#(a) folduM(function m#(a) f(a x, a y),
+--@                         function m#(a) g(a x), t#(a) xs)
+--@     provisos (Monad#(m));
+--@ endtypeclass
+--@ \end{libverbatim}
+class (Foldable t) => Foldable1 t where
+  foldr1 :: (a -> a -> a) -> t a -> a
+  foldl1 :: (a -> a -> a) -> t a -> a
+
+  -- Tree redunction over a non-empty container.
+  fold :: (a -> a -> a) -> t a -> a
+  fold = foldr1
+
+  -- Monadic tree reduction over a non-empty container.
+  -- First argument combines pairs of leaves.
+  -- No transformation at singleton leaves.
+  foldM :: (Functor t, Monad m) => (a -> a -> m a) -> t a -> m a
+  foldM f xs =
+    let liftF ma mb = ma `bind` \ a -> mb `bind` \ b -> f a b
+    in fold liftF $ fmap pure xs
+
+  -- Monadic tree reduction over a non-empty container.
+  -- First argument combines pairs of leaves.
+  -- Second argument is applied to singleton leaves.
+  folduM :: (Functor t, Monad m) =>
+            (a -> a -> m a) -> (a -> m a) -> t a -> m a
+  folduM f g xs = folduM f g $ toList xs
+
+instance (Add 1 m n) => Foldable1 (ListN.ListN n) where
+  foldr1 = ListN.foldr1
+  foldl1 = ListN.foldl1
+  fold = ListN.fold
+  foldM = ListN.foldM
+
+instance (Add 1 m n) => Foldable1 (Vector.Vector n) where
+  foldr1 = Vector.foldr1
+  foldl1 = Vector.foldl1
+  fold = Vector.fold
+  foldM = Vector.foldM
+
+instance Foldable1 List where
+  foldr1 = List.foldr1
+  foldl1 = List.foldl1
+  fold = List.fold
+  foldM = List.foldM
+  folduM = List.folduM
+
+instance Foldable1 Array where
+  foldr1 = Array.foldr1
+  foldl1 = Array.foldl1
+  fold = Array.fold
diff --git a/src/Libraries/Base1/ListN.bs b/src/Libraries/Base1/ListN.bs
index 9aaeddd51..7bf157d17 100644
--- a/src/Libraries/Base1/ListN.bs
+++ b/src/Libraries/Base1/ListN.bs
@@ -83,6 +83,15 @@ instance (Bits a sa, Mul n sa nsa) => Bits (ListN n a) nsa
 --X    provisos( Eq#( a_type ) ) ;
 --X \end{libverbatim}
 
+--X A ListN is a Functor: it can be mapped over.
+instance Functor (ListN n) where
+  fmap = map
+
+--X Applicative for a ListN corresponds to zipping.
+instance Applicative (ListN n) where
+  pure = replicate
+  liftA2 = zipWith
+
 {-
 flatN :: (Add k x m) => Integer -> List (Bit k) -> Bit m
 flatN n Nil = 0
diff --git a/src/Libraries/Base1/Traversable.bs b/src/Libraries/Base1/Traversable.bs
new file mode 100644
index 000000000..c48923049
--- /dev/null
+++ b/src/Libraries/Base1/Traversable.bs
@@ -0,0 +1,46 @@
+package Traversable where
+
+import qualified List
+import qualified ListN
+import qualified Vector
+
+import Foldable
+
+--@ \index{Traversable@\te{Traversable} (type class)}
+--@ The class of containers that can be traversed in an \te{Applicative}
+--@ context. Mirrors Haskell's \te{Data.Traversable}. \te{mapM} and
+--@ \te{sequence} are the conventional \te{Monad}-specialised aliases;
+--@ instances may override them to dispatch directly to the per-type
+--@ monadic helpers (\te{Vector.mapM}, \te{ListN.sequence}, ...) when
+--@ that's preferable.
+class (Functor t, Foldable t) => Traversable t where
+  traverse :: (Applicative f) => (a -> f b) -> t a -> f (t b)
+  sequenceA :: (Applicative f) => t (f a) -> f (t a)
+  sequenceA = traverse id
+  mapM :: (Monad m) => (a -> m b) -> t a -> m (t b)
+  mapM = traverse
+  sequence :: (Monad m) => t (m a) -> m (t a)
+  sequence = traverse id
+
+instance Traversable List where
+  traverse _ Nil = pure Nil
+  traverse f (Cons x rest) = liftA2 Cons (f x) (traverse f rest)
+  mapM = List.mapM
+
+instance Traversable (ListN.ListN n) where
+  traverse f xs = fmap ListN.toListN (traverse f (ListN.toList xs))
+  mapM = ListN.mapM
+  sequence = ListN.sequence
+
+instance Traversable (Vector.Vector n) where
+  traverse f v = fmap Vector.toVector (traverse f (Vector.toList v))
+  mapM = Vector.mapM
+  sequence = Vector.sequence
+
+instance Traversable Maybe where
+  traverse _ Invalid   = pure Invalid
+  traverse f (Valid x) = fmap Valid (f x)
+
+-- The `_` variants of these helpers (\te{traverse_}, \te{sequenceA_},
+-- \te{mapM_}, \te{sequence_}) live in \te{Foldable}: they only need
+-- \te{Foldable} since they don't rebuild the container.
diff --git a/src/Libraries/Base1/Vector.bs b/src/Libraries/Base1/Vector.bs
index 2f60e36a0..f514a205e 100644
--- a/src/Libraries/Base1/Vector.bs
+++ b/src/Libraries/Base1/Vector.bs
@@ -89,6 +89,15 @@ instance (FShow a) => FShow (Vector n a)
             elements = Vector.foldr insertSpace (fshow "") fmts
         in  $format "<V " elements " >"
 
+--@ A vector is a Functor: it can be mapped over.
+instance Functor (Vector n) where
+  fmap = map
+
+--@ Applicative for a vector corresponds to zipping.
+instance Applicative (Vector n) where
+  pure = replicate
+  liftA2 = zipWith
+
 -- This is used to construct an array with uninitialized elements
 -- and still mark the array as uninitialized until the user updates
 -- it with real values (since the update to insert the uninit elems
@@ -463,8 +472,6 @@ unzip (V v) = letseq (as, bs) = Array.unzip v
 map :: (a -> b) -> Vector n a -> Vector n b
 map f (V v) = V (Array.map f v)
 
-instance Functor (Vector n) where
-  fmap = map
 
 --@ The ``fold'' family of functions reduces a vector by applying a
 --@ function over all its elements.
diff --git a/src/Libraries/Base1/depends.mk b/src/Libraries/Base1/depends.mk
index b7292df2c..eaa521792 100644
--- a/src/Libraries/Base1/depends.mk
+++ b/src/Libraries/Base1/depends.mk
@@ -5,7 +5,7 @@
 $(BUILDDIR)/ActionSeq.bo:	ActionSeq.bs $(BUILDDIR)/List.bo $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Array.bo:	Array.bsv $(BUILDDIR)/List.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Assert.bo:	Assert.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
-$(BUILDDIR)/CShow.bo:	CShow.bs $(BUILDDIR)/ListN.bo $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
+$(BUILDDIR)/CShow.bo:	CShow.bs $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Clocks.bo:	Clocks.bsv $(BUILDDIR)/List.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/ConfigReg.bo:	ConfigReg.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Connectable.bo:	Connectable.bs $(BUILDDIR)/Vector.bo $(BUILDDIR)/ListN.bo $(BUILDDIR)/Inout.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
@@ -19,6 +19,7 @@ $(BUILDDIR)/FIFOLevel.bo:	FIFOLevel.bsv $(BUILDDIR)/FIFOF_.bo $(BUILDDIR)/GetPut
 $(BUILDDIR)/FShow.bo:	FShow.bsv $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/FoldFIFO.bo:	FoldFIFO.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/FoldFIFOF.bo:	FoldFIFOF.bs $(BUILDDIR)/FIFOF.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
+$(BUILDDIR)/Foldable.bo:	Foldable.bs $(BUILDDIR)/Array.bo $(BUILDDIR)/List.bo $(BUILDDIR)/ListN.bo $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Fork.bo:	Fork.bs $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/GetPut.bo:	GetPut.bs $(BUILDDIR)/FIFO.bo $(BUILDDIR)/FIFOF.bo $(BUILDDIR)/Connectable.bo $(BUILDDIR)/Clocks.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Inout.bo:	Inout.bsv $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
@@ -36,7 +37,8 @@ $(BUILDDIR)/Real.bo:	Real.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/RegFile.bo:	RegFile.bs $(BUILDDIR)/ConfigReg.bo $(BUILDDIR)/List.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Reserved.bo:	Reserved.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/RevertingVirtualReg.bo:	RevertingVirtualReg.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
-$(BUILDDIR)/SShow.bo:	SShow.bs $(BUILDDIR)/ListN.bo $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
+$(BUILDDIR)/SShow.bo:	SShow.bs $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/SplitPorts.bo:	SplitPorts.bs $(BUILDDIR)/List.bo $(BUILDDIR)/Vector.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
+$(BUILDDIR)/Traversable.bo:	Traversable.bs $(BUILDDIR)/List.bo $(BUILDDIR)/ListN.bo $(BUILDDIR)/Vector.bo $(BUILDDIR)/Foldable.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/TreeMap.bo:	TreeMap.bs $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
 $(BUILDDIR)/Vector.bo:	Vector.bs $(BUILDDIR)/List.bo $(BUILDDIR)/Array.bo $(BUILDDIR)/Prelude.bo $(BUILDDIR)/PreludeBSV.bo
diff --git a/src/comp/AVeriQuirks.hs b/src/comp/AVeriQuirks.hs
index c09ab72bb..72e843309 100644
--- a/src/comp/AVeriQuirks.hs
+++ b/src/comp/AVeriQuirks.hs
@@ -286,14 +286,26 @@ aQExp top (APrim aid t p es) | p == PrimAdd || p == PrimSub = do
 -- All multipliers should already be assigned directly to a
 -- def, and they should all have output size equal to the
 -- sum of the input sizes.  We check those properties here.
+-- The arguments must be in named defs (via mkDefS) so that Verilog
+-- evaluates their width-sensitive subexpressions (e.g. negation in
+-- sign-magnitude arithmetic) in the correct narrow context rather than
+-- the wider result context.
 aQExp top x@(APrim aid t p es) | p == PrimMul =
     if top
     then if ((aSize t) == (sum (map aSize es)))
-         then do es' <- mapM (aQExp False) es
+         then do es' <- mapM mkDefS es
                  return (APrim aid t p es')
          else internalError $ "aQExp: PrimMul result size is ill-typed: " ++ (show x)
     else internalError $ "aQExp: PrimMul does not feed into a def: " ++ (show x)
 
+-- PrimQuot and PrimRem have the same width-context issue as PrimMul:
+-- when arguments are complex expressions (e.g. sign-magnitude negations),
+-- Verilog evaluates them in the result width rather than the operand width.
+-- Forcing arguments into named defs gives each the correct narrow context.
+aQExp top x@(APrim aid t p es) | p == PrimQuot || p == PrimRem = do
+    es' <- mapM mkDefS es
+    return (APrim aid t p es')
+
 -- For PrimMux and PrimPriMux operators,
 aQExp top x@(APrim aid t p es) | p == PrimMux || p == PrimPriMux = do
     when debug $ traceM("aQExp PrimMux PrimPriMux: " ++ ppReadable x)
diff --git a/src/comp/FlagsDecode.hs b/src/comp/FlagsDecode.hs
index fa1e75564..952f5b122 100644
--- a/src/comp/FlagsDecode.hs
+++ b/src/comp/FlagsDecode.hs
@@ -511,7 +511,7 @@ traceflags = [
 
 defaultFlags :: String -> Flags
 defaultFlags bluespecdir = Flags {
-        aggImpConds = False,
+        aggImpConds = True,
         allowIncoherentMatches = False,
         backend = Nothing,
         bdir = Nothing,
@@ -611,7 +611,7 @@ defaultFlags bluespecdir = Flags {
         rstGate = False,
         ruleNameCheck = True,
         satBackend = SAT_Yices,
-        schedConds = False,
+        schedConds = True,
         schedDOT = False,
         schedQueries = [],
         showCSyntax = False,
diff --git a/src/comp/IExpandUtils.hs b/src/comp/IExpandUtils.hs
index 89ba288f5..3712fe9c4 100644
--- a/src/comp/IExpandUtils.hs
+++ b/src/comp/IExpandUtils.hs
@@ -2444,6 +2444,11 @@ extendHeap = do s <- get
                 mapM_ copycell ((uncurry enumFromTo) (bounds oldheap))
 -}
 
+improveCellName :: HExpr -> Maybe Id -> G (Maybe Id)
+improveCellName _ mi@(Just i)
+  | not $ isPreludePosition $ getPosition i = return mi
+improveCellName e _ = inferName e
+
 addHeapCell :: String -> HeapCell -> G (HeapPointer, HeapData)
 addHeapCell tag cell = do
   s <- get
@@ -2454,7 +2459,8 @@ addHeapCell tag cell = do
   return (p, HeapData ref)
 
 addHeapUnev :: String -> IType -> HExpr -> Maybe Id -> G HExpr
-addHeapUnev tag t e cell_name = do
+addHeapUnev tag t e cell_name_orig = do
+ cell_name <- improveCellName e cell_name_orig
  let newcell = (HUnev { hc_hexpr = e, hc_name = cell_name })
  cross <- getCross
  (p, r) <- addHeapCell tag newcell
@@ -2467,7 +2473,8 @@ addHeapUnev tag t e cell_name = do
 
 -- add an expression to the heap, noting it is WHNF
 addHeapWHNF :: String -> IType -> PExpr -> Maybe Id -> G HExpr
-addHeapWHNF tag t pe cell_name = do
+addHeapWHNF tag t pe@(P _ e) cell_name_orig = do
+  cell_name <- improveCellName e cell_name_orig
   let newcell = (HWHNF { hc_pexpr = pe, hc_name = cell_name })
   (p, r) <- addHeapCell tag newcell
   let result = IRefT t p r
diff --git a/testsuite/bsc.arrays/dynamic/arrays_dynamic.exp b/testsuite/bsc.arrays/dynamic/arrays_dynamic.exp
index 5f3812a78..1cd3bcf5c 100644
--- a/testsuite/bsc.arrays/dynamic/arrays_dynamic.exp
+++ b/testsuite/bsc.arrays/dynamic/arrays_dynamic.exp
@@ -151,12 +151,16 @@ compile_verilog_pass ActionVecShortIndex.bsv {} {-aggressive-conditions}
 compare_verilog sysActionVecShortIndex.v
 
 # When an array selection is used as the condition for an Action,
-# the merging of the out-of-bounds with the last element *does* happen.
+# the merging of the out-of-bounds with the last element used to happen,
+# but sinced we changed the evaluator to preserver array selection
+# (rather than turn into if-then-else immediately) we are able to
+# decide how to handle out-of-bounds selection at a later point and,
+# in this case, can perform no Action.
 #
-compile_verilog_pass VecCondAction.bsv
+# The output is specific to aggr-conds being on, so ensure it is
+compile_verilog_pass VecCondAction.bsv {} {-aggressive-conditions}
 #
-# The f$ENQ signal is True when idx==3
-# XXX Fix this bug?
+# This checks that f$ENQ signal is False when idx==3
 #
 compare_verilog sysVecCondAction.v
 
diff --git a/testsuite/bsc.arrays/dynamic/sysVecCondAction.v.expected b/testsuite/bsc.arrays/dynamic/sysVecCondAction.v.expected
index 740edb13d..51653bbb3 100644
--- a/testsuite/bsc.arrays/dynamic/sysVecCondAction.v.expected
+++ b/testsuite/bsc.arrays/dynamic/sysVecCondAction.v.expected
@@ -51,7 +51,7 @@ module sysVecCondAction(CLK,
   wire f$CLR, f$DEQ, f$ENQ, f$FULL_N;
 
   // remaining internal signals
-  reg CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1;
+  reg SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6;
 
   // submodule f
   FIFO2 #(.width(32'd8), .guarded(1'd1)) f(.RST(RST_N),
@@ -83,8 +83,8 @@ module sysVecCondAction(CLK,
   // submodule f
   assign f$D_IN = 8'd0 ;
   assign f$ENQ =
-	     f$FULL_N &&
-	     CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 ;
+	     (!SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6 || f$FULL_N) &&
+	     SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6 ;
   assign f$DEQ = 1'b0 ;
   assign f$CLR = 1'b0 ;
 
@@ -92,12 +92,11 @@ module sysVecCondAction(CLK,
   always@(idx or rgs_0 or rgs_1 or rgs_2)
   begin
     case (idx)
-      2'd0: CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 = rgs_0;
-      2'd1: CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 = rgs_1;
-      2'd2: CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 = rgs_2;
+      2'd0: SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6 = rgs_0;
+      2'd1: SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6 = rgs_1;
+      2'd2: SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6 = rgs_2;
       2'd3:
-	  CASE_idx_0_rgs_0_1_rgs_1_2_rgs_2_3_DONTCARE_DO_ETC__q1 =
-	      1'b0 /* unspecified value */ ;
+	  SEL_ARR_rgs_0_rgs_1_rgs_2_idx___d6 = 1'b0 /* unspecified value */ ;
     endcase
   end
 
diff --git a/testsuite/bsc.bluesim/interactive/mkTop_glob.out.expected b/testsuite/bsc.bluesim/interactive/mkTop_glob.out.expected
index 9dc16f77b..354978ba0 100644
--- a/testsuite/bsc.bluesim/interactive/mkTop_glob.out.expected
+++ b/testsuite/bsc.bluesim/interactive/mkTop_glob.out.expected
@@ -1,5 +1,5 @@
 *
-{b__h268 signal} {CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {count {module with value}} {level1 module} {mid1 module} {mid2 module} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
+{CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {count {module with value}} {count__h149 signal} {level1 module} {mid1 module} {mid2 module} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
 -------
 mid?.CAN_FIRE_*
 {mid1.CAN_FIRE_RL_incr signal} {mid1.CAN_FIRE_RL_sub1_flip signal} {mid1.CAN_FIRE_RL_wrap signal} {mid2.CAN_FIRE_RL_incr signal} {mid2.CAN_FIRE_RL_sub1_flip signal} {mid2.CAN_FIRE_RL_wrap signal}
@@ -14,7 +14,7 @@ RL_[di]*
 {CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {mid1 module} {mid2 module} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
 -------
 mid[0-9].*
-{mid1.b__h235 signal} {mid1.CAN_FIRE_RL_incr signal} {mid1.CAN_FIRE_RL_sub1_flip signal} {mid1.CAN_FIRE_RL_wrap signal} {mid1.count {module with value}} {mid1.limit signal} {mid1.RL_incr rule} {mid1.RL_sub1_flip rule} {mid1.RL_wrap rule} {mid1.sub1_x {module with value}} {mid1.WILL_FIRE_RL_incr signal} {mid1.WILL_FIRE_RL_sub1_flip signal} {mid1.WILL_FIRE_RL_wrap signal} {mid2.b__h235 signal} {mid2.CAN_FIRE_RL_incr signal} {mid2.CAN_FIRE_RL_sub1_flip signal} {mid2.CAN_FIRE_RL_wrap signal} {mid2.count {module with value}} {mid2.limit signal} {mid2.RL_incr rule} {mid2.RL_sub1_flip rule} {mid2.RL_wrap rule} {mid2.sub1_x {module with value}} {mid2.WILL_FIRE_RL_incr signal} {mid2.WILL_FIRE_RL_sub1_flip signal} {mid2.WILL_FIRE_RL_wrap signal}
+{mid1.CAN_FIRE_RL_incr signal} {mid1.CAN_FIRE_RL_sub1_flip signal} {mid1.CAN_FIRE_RL_wrap signal} {mid1.count {module with value}} {mid1.count__h170 signal} {mid1.limit signal} {mid1.RL_incr rule} {mid1.RL_sub1_flip rule} {mid1.RL_wrap rule} {mid1.sub1_x {module with value}} {mid1.WILL_FIRE_RL_incr signal} {mid1.WILL_FIRE_RL_sub1_flip signal} {mid1.WILL_FIRE_RL_wrap signal} {mid2.CAN_FIRE_RL_incr signal} {mid2.CAN_FIRE_RL_sub1_flip signal} {mid2.CAN_FIRE_RL_wrap signal} {mid2.count {module with value}} {mid2.count__h170 signal} {mid2.limit signal} {mid2.RL_incr rule} {mid2.RL_sub1_flip rule} {mid2.RL_wrap rule} {mid2.sub1_x {module with value}} {mid2.WILL_FIRE_RL_incr signal} {mid2.WILL_FIRE_RL_sub1_flip signal} {mid2.WILL_FIRE_RL_wrap signal}
 -------
 *1
 {level1 module} {mid1 module}
@@ -23,7 +23,7 @@ m*[12].RL_*
 {mid1.RL_incr rule} {mid1.RL_sub1_flip rule} {mid1.RL_wrap rule} {mid2.RL_incr rule} {mid2.RL_sub1_flip rule} {mid2.RL_wrap rule}
 -------
 ?[!ie]*
-{b__h268 signal} {CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {count {module with value}} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
+{CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {count {module with value}} {count__h149 signal} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
 -------
 *FIRE_RL_?[]a-zA-Z]*[-npw-z]*
 {CAN_FIRE_RL_done signal} {WILL_FIRE_RL_done signal}
diff --git a/testsuite/bsc.bluesim/interactive/mkTop_hier.out.expected b/testsuite/bsc.bluesim/interactive/mkTop_hier.out.expected
index 54242ed7e..f5532f284 100644
--- a/testsuite/bsc.bluesim/interactive/mkTop_hier.out.expected
+++ b/testsuite/bsc.bluesim/interactive/mkTop_hier.out.expected
@@ -2,7 +2,7 @@ sim pwd
 .
 -------
 sim ls
-{b__h268 signal} {CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {count {module with value}} {level1 module} {mid1 module} {mid2 module} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
+{CAN_FIRE_RL_done signal} {CAN_FIRE_RL_incr signal} {count {module with value}} {count__h149 signal} {level1 module} {mid1 module} {mid2 module} {RL_done rule} {RL_incr rule} {WILL_FIRE_RL_done signal} {WILL_FIRE_RL_incr signal}
 -------
 sim ls mid?.CAN_FIRE_*
 {mid1.CAN_FIRE_RL_incr signal} {mid1.CAN_FIRE_RL_sub1_flip signal} {mid1.CAN_FIRE_RL_wrap signal} {mid2.CAN_FIRE_RL_incr signal} {mid2.CAN_FIRE_RL_sub1_flip signal} {mid2.CAN_FIRE_RL_wrap signal}
diff --git a/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.out.expected b/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.out.expected
index ac82c4826..af3f2e377 100644
--- a/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.out.expected
+++ b/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.out.expected
@@ -44,10 +44,11 @@
         59: 2 gets 09
         78: 1 gets 04
         60: 2 gets 04
-        61: 2 gets 11
         81: 1 gets 02
+        61: 2 gets 11
         62: 2 gets 2c
         84: 1 gets 01
         87: 1 gets 20
         90: 1 gets 30
-         0: 1 gets 24
+        93: 1 gets 18
+         0: 1 gets 12
diff --git a/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.v.out.expected b/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.v.out.expected
index fc910da02..69fe1b51b 100644
--- a/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.v.out.expected
+++ b/testsuite/bsc.bsv_examples/mcd_Rand/mkTop.v.out.expected
@@ -42,13 +42,14 @@
         57: 2 gets 2f
         58: 2 gets 27
         59: 2 gets 09
-        60: 2 gets 04
         78: 1 gets 04
-        61: 2 gets 11
+        60: 2 gets 04
         81: 1 gets 02
+        61: 2 gets 11
         62: 2 gets 2c
         84: 1 gets 01
         87: 1 gets 20
         90: 1 gets 30
-         0: 1 gets 24
-         3: 1 gets 12
+        93: 1 gets 18
+         0: 1 gets 12
+         3: 1 gets 29
diff --git a/testsuite/bsc.bsv_examples/mcd_Rand/rand.exp b/testsuite/bsc.bsv_examples/mcd_Rand/rand.exp
index befc7f4e0..72efe7512 100644
--- a/testsuite/bsc.bsv_examples/mcd_Rand/rand.exp
+++ b/testsuite/bsc.bsv_examples/mcd_Rand/rand.exp
@@ -1,7 +1,9 @@
 
+# The output is specific to aggr-conds being on, so ensure it is
+
 # Bluesim
-test_c_only_bsv_multi Top mkTop {mkRandTop}
+test_c_only_bsv_multi_options Top mkTop {mkRandTop} {-aggressive-conditions}
 
 # Verilog outputs a few coincident edges differently
-test_veri_only_bsv_multi Top mkTop {mkRandTop} mkTop.v.out.expected
+test_veri_only_bsv_multi_options Top mkTop {mkRandTop} {-aggressive-conditions} mkTop.v.out.expected
 
diff --git a/testsuite/bsc.bsv_examples/mesa/spiless-tx-bsv-cocoon/MesaTxLpm.bsv b/testsuite/bsc.bsv_examples/mesa/spiless-tx-bsv-cocoon/MesaTxLpm.bsv
index f65acbda0..0f34f906f 100644
--- a/testsuite/bsc.bsv_examples/mesa/spiless-tx-bsv-cocoon/MesaTxLpm.bsv
+++ b/testsuite/bsc.bsv_examples/mesa/spiless-tx-bsv-cocoon/MesaTxLpm.bsv
@@ -36,7 +36,10 @@ endmodule
 
 typedef Tuple2#(ILpm, LPMMemoryWires) ILPM0;
 
- (* synthesize *)
+(* synthesize *)
+// Aggressive conditions leads to too many users of "sram.read"
+// because of the exported "snd" interface, so we disable it
+(* options="-no-aggressive-conditions" *)
 module mkMesaTxLpm0(ILPM0);
    LPMMemoryStub stub <- mkStub;
    let sram = stub.mem;
diff --git a/testsuite/bsc.bsv_examples/mimo/mimo.exp b/testsuite/bsc.bsv_examples/mimo/mimo.exp
index 699713fc6..c2dab7381 100644
--- a/testsuite/bsc.bsv_examples/mimo/mimo.exp
+++ b/testsuite/bsc.bsv_examples/mimo/mimo.exp
@@ -1,4 +1,6 @@
 test_c_veri_bsv Basic sysBasic.expected
-test_c_veri_bsv TrafficREG sysTrafficREG.expected
-test_c_veri_bsv TrafficBRAM sysTrafficBRAM.expected
+# Aggressive conditions can be enabled, but it changes the output,
+# so the expected file would need to be audited and updated
+test_c_veri_bsv_modules_options TrafficREG {} {-no-aggressive-conditions}
+test_c_veri_bsv_modules_options TrafficBRAM {} {-no-aggressive-conditions}
 
diff --git a/testsuite/bsc.bsv_examples/mimo/sysTrafficBRAM.expected b/testsuite/bsc.bsv_examples/mimo/sysTrafficBRAM.out.expected
similarity index 100%
rename from testsuite/bsc.bsv_examples/mimo/sysTrafficBRAM.expected
rename to testsuite/bsc.bsv_examples/mimo/sysTrafficBRAM.out.expected
diff --git a/testsuite/bsc.bsv_examples/mimo/sysTrafficREG.expected b/testsuite/bsc.bsv_examples/mimo/sysTrafficREG.out.expected
similarity index 100%
rename from testsuite/bsc.bsv_examples/mimo/sysTrafficREG.expected
rename to testsuite/bsc.bsv_examples/mimo/sysTrafficREG.out.expected
diff --git a/testsuite/bsc.bugs/bluespec_inc/b1894/b1894.exp b/testsuite/bsc.bugs/bluespec_inc/b1894/b1894.exp
index d719320c6..0fcf0b66b 100644
--- a/testsuite/bsc.bugs/bluespec_inc/b1894/b1894.exp
+++ b/testsuite/bsc.bugs/bluespec_inc/b1894/b1894.exp
@@ -18,8 +18,7 @@ if { $ctest == 1 } {
     # backend, and only then if the user has specified that it's OK
     # for the Verilog and Bluesim backends to diverge).
     #
-    set def_id [regexp_match mkTop.cxx {DEF_v__h(\d+) = DEF_AVMeth_s_m;}]
-    find_regexp mkTop.cxx [append {2047u \& \(\(\(\(\(tUInt32\)\(\(tUInt8\)0u\)\) << 3u\) \| \(\(\(tUInt32\)\(DEF_cond__h\d+\)\) << 2u\)\) \| \(tUInt32\)\(DEF_v__h} $def_id {\)\);}]
+    find_regexp mkTop.cxx {2047u \& \(\(\(\(\(tUInt32\)\(\(tUInt8\)0u\)\) << 3u\) \| \(\(\(tUInt32\)\(DEF_cond__h\d+\)\) << 2u\)\) \| \(tUInt32\)\(DEF_AVMeth_s_m\)\);}
 }
 
 # Also test that BSC fully initializes DEF_AVMeth_s_m
diff --git a/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected b/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected
index 4fa3a069c..caa9c7492 100644
--- a/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected
+++ b/testsuite/bsc.bugs/bluespec_inc/b292/mkDesign.v.expected
@@ -85,10 +85,6 @@ module mkDesign(clk,
   wire [7 : 0] i_multiplicand$D_IN;
   wire i_multiplicand$EN;
 
-  // remaining internal signals
-  wire [7 : 0] x__h663, x__h814, x__h874;
-  wire [3 : 0] x__h851, x__h896;
-
   // value method done
   assign done = i_done_reg ;
 
@@ -99,7 +95,7 @@ module mkDesign(clk,
   assign i_acc$D_IN =
 	     (shift_and_add_load && i_count == 4'd0) ?
 	       8'd0 :
-	       (i_mult[0] ? x__h814 : i_acc) ;
+	       (i_mult[0] ? i_acc + i_multiplicand : i_acc) ;
   assign i_acc$EN =
 	     shift_and_add_load && i_count == 4'd0 ||
 	     i_enable && i_count != 4'd4 ;
@@ -108,7 +104,7 @@ module mkDesign(clk,
   assign i_count$D_IN =
 	     (shift_and_add_load && i_count == 4'd0) ?
 	       4'd0 :
-	       ((i_enable && i_count != 4'd4) ? x__h896 : 4'd0) ;
+	       ((i_enable && i_count != 4'd4) ? i_count + 4'd1 : 4'd0) ;
   assign i_count$EN = 1'd1 ;
 
   // register i_done_reg
@@ -127,25 +123,20 @@ module mkDesign(clk,
   assign i_mult$D_IN =
 	     (shift_and_add_load && i_count == 4'd0) ?
 	       shift_and_add_b :
-	       x__h851 ;
+	       { 1'd0, i_mult[3:1] } ;
   assign i_mult$EN =
 	     shift_and_add_load && i_count == 4'd0 ||
 	     i_enable && i_count != 4'd4 ;
 
   // register i_multiplicand
   assign i_multiplicand$D_IN =
-	     (shift_and_add_load && i_count == 4'd0) ? x__h663 : x__h874 ;
+	     (shift_and_add_load && i_count == 4'd0) ?
+	       { 4'b0, shift_and_add_a } :
+	       { i_multiplicand[6:0], 1'd0 } ;
   assign i_multiplicand$EN =
 	     shift_and_add_load && i_count == 4'd0 ||
 	     i_enable && i_count != 4'd4 ;
 
-  // remaining internal signals
-  assign x__h663 = { 4'b0, shift_and_add_a } ;
-  assign x__h814 = i_acc + i_multiplicand ;
-  assign x__h851 = { 1'd0, i_mult[3:1] } ;
-  assign x__h874 = { i_multiplicand[6:0], 1'd0 } ;
-  assign x__h896 = i_count + 4'd1 ;
-
   // handling of inlined registers
 
   always@(posedge clk)
diff --git a/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected b/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected
index 493ba1aa3..b9f22a2d7 100644
--- a/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected
+++ b/testsuite/bsc.bugs/bluespec_inc/b302/mkDesign.v.expected
@@ -46,108 +46,90 @@ module mkDesign(clk,
   wire [10 : 0] result;
 
   // remaining internal signals
-  wire [5 : 0] _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55,
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56,
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57,
-	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58,
-	       _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59,
-	       x__h144,
-	       x__h146,
-	       x__h240,
-	       x__h242,
-	       x__h336,
-	       x__h338,
-	       x__h432,
-	       x__h434,
-	       x__h528,
-	       x__h530,
-	       y__h147;
-  wire [4 : 0] IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54,
+  wire [5 : 0] _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45,
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36,
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27,
+	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18,
+	       _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9;
+  wire [4 : 0] IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42,
 	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4,
-	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53,
+	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d33,
 	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3,
-	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52,
+	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d24,
 	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2,
-	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51,
+	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d15,
 	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1,
-	       _theResult_____1_snd__h939,
-	       notB__h48,
-	       quotient__h63;
+	       _theResult_____1_snd__h755,
+	       notB__h260,
+	       quotient__h275;
 
   // value method result
   assign result =
 	     { result_a[9:5] >= result_b,
-	       _theResult_____1_snd__h939,
-	       quotient__h63 } ;
+	       _theResult_____1_snd__h755,
+	       quotient__h275 } ;
 
   // remaining internal signals
-  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 =
+  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42 =
 	     { IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4[3:0],
 	       result_a[0] } ;
   assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC__q4 =
-	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[5] ?
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[4:0] :
-	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 ;
-  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 =
+	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36[5] ?
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36[4:0] :
+	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d33 ;
+  assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d33 =
 	     { IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3[3:0],
 	       result_a[1] } ;
   assign IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC__q3 =
-	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[5] ?
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[4:0] :
-	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 ;
-  assign IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 =
+	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27[5] ?
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27[4:0] :
+	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d24 ;
+  assign IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d24 =
 	     { IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2[3:0],
 	       result_a[2] } ;
   assign IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC__q2 =
-	     _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[5] ?
-	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[4:0] :
-	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 ;
-  assign IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 =
+	     _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18[5] ?
+	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18[4:0] :
+	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d15 ;
+  assign IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d15 =
 	     { IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1[3:0],
 	       result_a[3] } ;
   assign IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC__q1 =
-	     _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[5] ?
-	       _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[4:0] :
+	     _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9[5] ?
+	       _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9[4:0] :
 	       result_a[8:4] ;
-  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55 =
-	     x__h144 + 6'd1 ;
-  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56 =
-	     x__h240 + 6'd1 ;
-  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57 =
-	     x__h336 + 6'd1 ;
-  assign _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58 =
-	     x__h432 + 6'd1 ;
-  assign _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59 =
-	     x__h528 + 6'd1 ;
-  assign _theResult_____1_snd__h939 =
-	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[5] ?
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[4:0] :
-	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 ;
-  assign notB__h48 = ~result_b ;
-  assign quotient__h63 =
-	     { _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d59[5],
-	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d58[5],
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d57[5],
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d56[5],
-	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d55[5] } ;
-  assign x__h144 = x__h146 + y__h147 ;
-  assign x__h146 =
+  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45 =
 	     { 1'd0,
-	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d54 } ;
-  assign x__h240 = x__h242 + y__h147 ;
-  assign x__h242 =
+	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42 } +
+	     { 1'd0, notB__h260 } +
+	     6'd1 ;
+  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36 =
 	     { 1'd0,
-	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d53 } ;
-  assign x__h336 = x__h338 + y__h147 ;
-  assign x__h338 =
+	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_B_ETC___d33 } +
+	     { 1'd0, notB__h260 } +
+	     6'd1 ;
+  assign _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27 =
 	     { 1'd0,
-	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d52 } ;
-  assign x__h432 = x__h434 + y__h147 ;
-  assign x__h434 =
+	       IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_P_ETC___d24 } +
+	     { 1'd0, notB__h260 } +
+	     6'd1 ;
+  assign _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18 =
 	     { 1'd0,
-	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d51 } ;
-  assign x__h528 = x__h530 + y__h147 ;
-  assign x__h530 = { 1'd0, result_a[8:4] } ;
-  assign y__h147 = { 1'd0, notB__h48 } ;
+	       IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_ETC___d15 } +
+	     { 1'd0, notB__h260 } +
+	     6'd1 ;
+  assign _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9 =
+	     { 1'd0, result_a[8:4] } + { 1'd0, notB__h260 } + 6'd1 ;
+  assign _theResult_____1_snd__h755 =
+	     _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45[5] ?
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45[4:0] :
+	       IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCA_ETC___d42 ;
+  assign notB__h260 = ~result_b ;
+  assign quotient__h275 =
+	     { _0_CONCAT_result_a_BITS_8_TO_4_PLUS_0_CONCAT_IN_ETC___d9[5],
+	       _0_CONCAT_IF_0_CONCAT_result_a_BITS_8_TO_4_PLUS_ETC___d18[5],
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_result_a_BITS_ETC___d27[5],
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_r_ETC___d36[5],
+	       _0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_IF_0_CONCAT_I_ETC___d45[5] } ;
 endmodule  // mkDesign
 
diff --git a/testsuite/bsc.bugs/bluespec_inc/b893/b893.exp b/testsuite/bsc.bugs/bluespec_inc/b893/b893.exp
index 7b7dd39de..0f5ee9e27 100644
--- a/testsuite/bsc.bugs/bluespec_inc/b893/b893.exp
+++ b/testsuite/bsc.bugs/bluespec_inc/b893/b893.exp
@@ -1,9 +1,8 @@
+# BSC used to disable aggressive-conditions entirely inside a method,
+# rather than only when the condition contains an argument of the method.
+# This tests that BSC does lift inside a method when possible.
+
 if {$vtest == 1} {
-  compile_verilog_pass Bug893.bsv
-  # If this test fails, that might be good!
-  # Examine the Verilog to see if the expression for RDY_get has
-  # changed from "f1$EMPTY_N && f2$EMPTY_N" to something more like
-  # "(r ? f1$EMPTY_N : f2$EMPTY_N)"
-  find_n_strings sysBug893.v {assign RDY_get = f1$EMPTY_N && f2$EMPTY_N ;} 1
+    compile_verilog_pass Bug893.bsv {} {-aggressive-conditions}
+    find_n_strings sysBug893.v {assign RDY_get = r ? f1$EMPTY_N : f2$EMPTY_N ;} 1
 }
-
diff --git a/testsuite/bsc.codegen/case/case.exp b/testsuite/bsc.codegen/case/case.exp
index 3f746786a..bc1f99506 100644
--- a/testsuite/bsc.codegen/case/case.exp
+++ b/testsuite/bsc.codegen/case/case.exp
@@ -62,7 +62,7 @@ if { $ctest == 1 } {
   \}}
 
     find_regexp sysIfElseCase_Inline.cxx {
-  switch \(DEF_x__h[0-9]+\) \{
+  switch \(DEF_r_idx___d[0-9]+\) \{
   case \(tUInt8\)0u\:
     DEF_IF_r_idx_EQ_0_THEN_0_ELSE_IF_r_idx_EQ_1_THEN_r_ETC___d[0-9]+ \= \(tUInt8\)0u\;
     break\;
@@ -127,7 +127,7 @@ if { $vtest == 1 } {
 # (The arm for index 5 has been merged with the default.)
 if { $ctest == 1 } {
     find_regexp sysDupResult.cxx {
-  switch \(DEF_x__h[0-9]+\) \{
+  switch \(DEF_r_idx___d[0-9]+\) \{
   case \(tUInt8\)0u\:
   case \(tUInt8\)2u\:
   case \(tUInt8\)6u\:
diff --git a/testsuite/bsc.evaluator/sysShiftMult.ats.expected b/testsuite/bsc.evaluator/sysShiftMult.ats.expected
index e63461be2..82f846b43 100644
--- a/testsuite/bsc.evaluator/sysShiftMult.ats.expected
+++ b/testsuite/bsc.evaluator/sysShiftMult.ats.expected
@@ -45,25 +45,25 @@ y :: ABSTRACT:  Prelude.VReg = RegN
 			       port types=D_IN -> Prelude.Bit 32
 					  Q_OUT -> Prelude.Bit 32
 -- AP local definitions
-x__h177 :: Bit 32;
-x__h177  = x_BITS_28_TO_0___h184 ++ 3'd0;
--- IdProp x__h177[IdP_keep]
-x__h145 :: Bit 32;
-x__h145  = x_BITS_29_TO_0___h174 ++ 2'd0;
--- IdProp x__h145[IdP_keep]
-x_BITS_28_TO_0___h184 :: Bit 29;
-x_BITS_28_TO_0___h184  = extract x___d1 32'd28 32'd0;
--- IdProp x_BITS_28_TO_0___h184[IdP_keep]
-x_BITS_29_TO_0___h174 :: Bit 30;
-x_BITS_29_TO_0___h174  = extract x___d1 32'd29 32'd0;
--- IdProp x_BITS_29_TO_0___h174[IdP_keep]
+x_BITS_28_TO_0_CONCAT_0___d5 :: Bit 32;
+x_BITS_28_TO_0_CONCAT_0___d5  = x_BITS_28_TO_0___h154 ++ 3'd0;
+-- IdProp x_BITS_28_TO_0_CONCAT_0___d5[IdP_from_rhs]
+x_BITS_29_TO_0_CONCAT_0___d3 :: Bit 32;
+x_BITS_29_TO_0_CONCAT_0___d3  = x_BITS_29_TO_0___h131 ++ 2'd0;
+-- IdProp x_BITS_29_TO_0_CONCAT_0___d3[IdP_from_rhs]
+x_BITS_28_TO_0___h154 :: Bit 29;
+x_BITS_28_TO_0___h154  = extract x___d1 32'd28 32'd0;
+-- IdProp x_BITS_28_TO_0___h154[IdP_keep]
+x_BITS_29_TO_0___h131 :: Bit 30;
+x_BITS_29_TO_0___h131  = extract x___d1 32'd29 32'd0;
+-- IdProp x_BITS_29_TO_0___h131[IdP_keep]
 x___d1 :: Bit 32;
 x___d1  = x.read;
 -- IdProp x___d1[IdP_from_rhs]
 -- AP rules
 rule RL_unnamed "":
  when 1'd1
-  ==> { x.write x__h145; y.write x__h177; }
+  ==> { x.write x_BITS_29_TO_0_CONCAT_0___d3; y.write x_BITS_28_TO_0_CONCAT_0___d5; }
 []
 clock domain = Just (0), resets = [0]
 -- AP scheduling pragmas
diff --git a/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected
index 1ace575a0..c2834ce68 100755
--- a/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected
+++ b/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected
@@ -5,5 +5,5 @@ Verilog file created: subtractor.v
 code generation for mkDifference starts
 Error: "EResources.bs", line 43, column 13: (G0002)
   `m.minus' needs more than 1 ports for the following uses:
-      `m.minus b__h230 b__h231' at "EResources.bs", line 43, column 13
-      `m.minus b__h231 b__h230' at "EResources.bs", line 43, column 13
+      `m.minus x__h369 y__h370' at "EResources.bs", line 43, column 13
+      `m.minus y__h370 x__h369' at "EResources.bs", line 43, column 13
diff --git a/testsuite/bsc.lib/Foldable/Foldable.exp b/testsuite/bsc.lib/Foldable/Foldable.exp
new file mode 100644
index 000000000..536cdb82c
--- /dev/null
+++ b/testsuite/bsc.lib/Foldable/Foldable.exp
@@ -0,0 +1,4 @@
+
+# tests for the Foldable and Foldable1 library classes
+test_c_veri FoldableTest
+test_c_veri Foldable1Test
diff --git a/testsuite/bsc.lib/Foldable/Foldable1Test.bs b/testsuite/bsc.lib/Foldable/Foldable1Test.bs
new file mode 100644
index 000000000..b2430b0a7
--- /dev/null
+++ b/testsuite/bsc.lib/Foldable/Foldable1Test.bs
@@ -0,0 +1,55 @@
+package Foldable1Test where
+
+import Foldable
+import qualified Vector
+import qualified ListN
+
+-- Exercise the Foldable1 class (folds over non-empty containers).
+
+{-# verilog sysFoldable1Test #-}
+sysFoldable1Test :: Module Empty
+sysFoldable1Test =
+  module
+    rules
+      "test": when True ==> action
+        let l :: List (Int 32)
+            l = Cons 5 (Cons 6 (Cons 7 Nil))
+            v :: Vector.Vector 4 (Int 32)
+            v = Vector.toVector (Cons 1 (Cons 2 (Cons 3 (Cons 4 Nil))))
+            ln :: ListN.ListN 4 (Int 32)
+            ln = ListN.toListN (Cons 10 (Cons 20 (Cons 30 (Cons 40 Nil))))
+
+        $display "-- fold --"
+        $display "%0d" (fold (+) v)           -- 10
+        $display "%0d" (fold (+) ln)          -- 100
+        $display "%0d" (fold (+) l)           -- 18
+
+        $display "-- foldr1/foldl1 --"
+        $display "%0d" (foldr1 (-) v)         -- -2
+        $display "%0d" (foldl1 (-) v)         -- -8
+
+        $display "-- foldM (Maybe monad) --"
+        let r1 :: Maybe (Int 32)
+            r1 = foldM (\ a b -> Valid (a + b)) v
+        case r1 of
+          Valid s -> $display "%0d" s         -- 10
+          Invalid -> $display "none"
+
+        $display "-- folduM (Maybe monad) --"
+        -- g (the single-leaf function) is only applied to an odd element
+        -- left over while pairing. v has even length so g is unused: the
+        -- pairwise sums collapse to the plain total, 10.
+        let r2 :: Maybe (Int 32)
+            r2 = folduM (\ a b -> Valid (a + b)) (\ x -> Valid (x * 10)) v
+        case r2 of
+          Valid s -> $display "%0d" s         -- 10
+          Invalid -> $display "none"
+        -- l has odd length, so 7 is left over and gets g (x10): the
+        -- reduction is ((5+6) + (7*10)) = 81.
+        let r3 :: Maybe (Int 32)
+            r3 = folduM (\ a b -> Valid (a + b)) (\ x -> Valid (x * 10)) l
+        case r3 of
+          Valid s -> $display "%0d" s         -- 81
+          Invalid -> $display "none"
+
+        $finish 0
diff --git a/testsuite/bsc.lib/Foldable/FoldableTest.bs b/testsuite/bsc.lib/Foldable/FoldableTest.bs
new file mode 100644
index 000000000..ea8a59390
--- /dev/null
+++ b/testsuite/bsc.lib/Foldable/FoldableTest.bs
@@ -0,0 +1,61 @@
+package FoldableTest where
+
+import Foldable
+import qualified List
+import qualified Vector
+import qualified ListN
+
+-- Exercise the Foldable class over its various instances.
+
+showInt :: Integer -> Action
+showInt n = $display "%0d" ((fromInteger n) :: Int 32)
+
+{-# verilog sysFoldableTest #-}
+sysFoldableTest :: Module Empty
+sysFoldableTest =
+  module
+    rules
+      "test": when True ==> action
+        let l :: List (Int 32)
+            l = Cons 5 (Cons 6 (Cons 7 Nil))
+            v :: Vector.Vector 4 (Int 32)
+            v = Vector.toVector (Cons 1 (Cons 2 (Cons 3 (Cons 4 Nil))))
+            ln :: ListN.ListN 4 (Int 32)
+            ln = ListN.toListN (Cons 10 (Cons 20 (Cons 30 (Cons 40 Nil))))
+            mj :: Maybe (Int 32)
+            mj = Valid 99
+            mn :: Maybe (Int 32)
+            mn = Invalid
+
+        $display "-- foldr/foldl --"
+        $display "%0d" (foldr (+) 0 v)        -- 10
+        $display "%0d" (foldl (-) 0 v)        -- -10
+        $display "%0d" (foldr (+) 0 ln)       -- 100
+        $display "%0d" (foldr (+) 0 l)        -- 18
+        $display "%0d" (foldr (+) 0 mj)       -- 99
+        $display "%0d" (foldr (+) 0 mn)       -- 0
+
+        $display "-- length/null --"
+        showInt (length v)                    -- 4
+        showInt (length l)                    -- 3
+        showInt (length mn)                   -- 0
+        $display "%b %b" (null v) (null mn)   -- 0 1
+
+        $display "-- elem --"
+        $display "%b %b" (elem 3 v) (elem 7 v)  -- 1 0
+
+        $display "-- toList --"
+        showInt (List.length (toList v))      -- 4
+        $display "%0d" (foldr (+) 0 (toList ln))  -- 100
+
+        $display "-- mapM_ (Action) --"
+        mapM_ (\ x -> $display "%0d" x) v
+
+        $display "-- foldrM (Maybe monad) --"
+        let r :: Maybe (Int 32)
+            r = foldrM (\ x acc -> Valid (x + acc)) 0 v
+        case r of
+          Valid s -> $display "%0d" s         -- 10
+          Invalid -> $display "none"
+
+        $finish 0
diff --git a/testsuite/bsc.lib/Foldable/Makefile b/testsuite/bsc.lib/Foldable/Makefile
new file mode 100644
index 000000000..b953e8132
--- /dev/null
+++ b/testsuite/bsc.lib/Foldable/Makefile
@@ -0,0 +1,5 @@
+# for "make clean" to work everywhere
+
+CONFDIR = $(realpath ../..)
+
+include $(CONFDIR)/clean.mk
diff --git a/testsuite/bsc.lib/Foldable/sysFoldable1Test.out.expected b/testsuite/bsc.lib/Foldable/sysFoldable1Test.out.expected
new file mode 100644
index 000000000..136402744
--- /dev/null
+++ b/testsuite/bsc.lib/Foldable/sysFoldable1Test.out.expected
@@ -0,0 +1,12 @@
+-- fold --
+10
+100
+18
+-- foldr1/foldl1 --
+-2
+-8
+-- foldM (Maybe monad) --
+10
+-- folduM (Maybe monad) --
+10
+81
diff --git a/testsuite/bsc.lib/Foldable/sysFoldableTest.out.expected b/testsuite/bsc.lib/Foldable/sysFoldableTest.out.expected
new file mode 100644
index 000000000..616d20170
--- /dev/null
+++ b/testsuite/bsc.lib/Foldable/sysFoldableTest.out.expected
@@ -0,0 +1,24 @@
+-- foldr/foldl --
+10
+-10
+100
+18
+99
+0
+-- length/null --
+4
+3
+0
+0 1
+-- elem --
+1 0
+-- toList --
+4
+100
+-- mapM_ (Action) --
+1
+2
+3
+4
+-- foldrM (Maybe monad) --
+10
diff --git a/testsuite/bsc.lib/Traversable/Makefile b/testsuite/bsc.lib/Traversable/Makefile
new file mode 100644
index 000000000..b953e8132
--- /dev/null
+++ b/testsuite/bsc.lib/Traversable/Makefile
@@ -0,0 +1,5 @@
+# for "make clean" to work everywhere
+
+CONFDIR = $(realpath ../..)
+
+include $(CONFDIR)/clean.mk
diff --git a/testsuite/bsc.lib/Traversable/Traversable.exp b/testsuite/bsc.lib/Traversable/Traversable.exp
new file mode 100644
index 000000000..e53f89f47
--- /dev/null
+++ b/testsuite/bsc.lib/Traversable/Traversable.exp
@@ -0,0 +1,3 @@
+
+# tests for the Traversable library class
+test_c_veri TraversableTest
diff --git a/testsuite/bsc.lib/Traversable/TraversableTest.bs b/testsuite/bsc.lib/Traversable/TraversableTest.bs
new file mode 100644
index 000000000..428fe6800
--- /dev/null
+++ b/testsuite/bsc.lib/Traversable/TraversableTest.bs
@@ -0,0 +1,84 @@
+package TraversableTest where
+
+import Foldable
+import Traversable
+import qualified Vector
+import qualified ListN
+
+-- Exercise the Traversable class over its instances.
+
+-- Sum a container's elements via Foldable, for display.
+sumF :: (Foldable t) => t (Int 32) -> Int 32
+sumF = foldr (+) 0
+
+-- A step that fails (returns Invalid) for elements >= the limit.
+below :: Int 32 -> Int 32 -> Maybe (Int 32)
+below limit x = if x < limit then Valid x else Invalid
+
+{-# verilog sysTraversableTest #-}
+sysTraversableTest :: Module Empty
+sysTraversableTest =
+  module
+    rules
+      "test": when True ==> action
+        let v :: Vector.Vector 4 (Int 32)
+            v = Vector.toVector (Cons 1 (Cons 2 (Cons 3 (Cons 4 Nil))))
+            ln :: ListN.ListN 4 (Int 32)
+            ln = ListN.toListN (Cons 10 (Cons 20 (Cons 30 (Cons 40 Nil))))
+            l :: List (Int 32)
+            l = Cons 5 (Cons 6 (Cons 7 Nil))
+            -- Vector of Maybes, all valid.
+            vmj :: Vector.Vector 4 (Maybe (Int 32))
+            vmj = Vector.toVector
+                    (Cons (Valid 1) (Cons (Valid 2)
+                     (Cons (Valid 3) (Cons (Valid 4) Nil))))
+            -- Vector of Maybes, one invalid.
+            vmn :: Vector.Vector 4 (Maybe (Int 32))
+            vmn = Vector.toVector
+                    (Cons (Valid 1) (Cons Invalid
+                     (Cons (Valid 3) (Cons (Valid 4) Nil))))
+
+        $display "-- traverse (Vector, all valid) --"
+        case traverse (\ x -> Valid (x + 1)) v of
+          Valid w -> $display "%0d" (sumF w)   -- 14
+          Invalid -> $display "none"
+
+        $display "-- traverse (Vector, fails) --"
+        case traverse (below 3) v of
+          Valid w -> $display "%0d" (sumF w)
+          Invalid -> $display "none"           -- none (3, 4 >= 3)
+
+        $display "-- traverse (List) --"
+        case traverse (\ x -> Valid (x + 1)) l of
+          Valid w -> $display "%0d" (sumF w)   -- 21
+          Invalid -> $display "none"
+
+        $display "-- traverse (ListN) --"
+        case traverse (\ x -> Valid (x + 1)) ln of
+          Valid w -> $display "%0d" (sumF w)   -- 104
+          Invalid -> $display "none"
+
+        $display "-- sequenceA (Vector of Maybe) --"
+        case sequenceA vmj of
+          Valid w -> $display "%0d" (sumF w)   -- 10
+          Invalid -> $display "none"
+        case sequenceA vmn of
+          Valid w -> $display "%0d" (sumF w)
+          Invalid -> $display "none"           -- none
+
+        $display "-- sequence (alias) --"
+        case sequence vmj of
+          Valid w -> $display "%0d" (sumF w)   -- 10
+          Invalid -> $display "none"
+
+        $display "-- mapM (Vector, Maybe monad) --"
+        case mapM (below 100) v of
+          Valid w -> $display "%0d" (sumF w)   -- 10
+          Invalid -> $display "none"
+
+        $display "-- traverse (Maybe) --"
+        case traverse (\ x -> Valid (x + 1)) (Valid 41) of
+          Valid (Valid y) -> $display "%0d" y  -- 42
+          _ -> $display "none"
+
+        $finish 0
diff --git a/testsuite/bsc.lib/Traversable/sysTraversableTest.out.expected b/testsuite/bsc.lib/Traversable/sysTraversableTest.out.expected
new file mode 100644
index 000000000..cee10b4da
--- /dev/null
+++ b/testsuite/bsc.lib/Traversable/sysTraversableTest.out.expected
@@ -0,0 +1,17 @@
+-- traverse (Vector, all valid) --
+14
+-- traverse (Vector, fails) --
+none
+-- traverse (List) --
+21
+-- traverse (ListN) --
+104
+-- sequenceA (Vector of Maybe) --
+10
+none
+-- sequence (alias) --
+10
+-- mapM (Vector, Maybe monad) --
+10
+-- traverse (Maybe) --
+42
diff --git a/testsuite/bsc.lib/listn/ApplicativeListN.bs b/testsuite/bsc.lib/listn/ApplicativeListN.bs
new file mode 100644
index 000000000..b629fe523
--- /dev/null
+++ b/testsuite/bsc.lib/listn/ApplicativeListN.bs
@@ -0,0 +1,50 @@
+package ApplicativeListN where
+
+import ListN
+
+-- Test the Functor and Applicative instances for ListN.
+
+incr :: Int 16 -> Int 16
+incr x = x + 1
+
+{-# verilog sysApplicativeListN #-}
+sysApplicativeListN :: Module Empty
+sysApplicativeListN =
+  module
+    let sh :: String -> ListN 4 (Int 16) -> Action
+        sh lbl v =
+          $display (lbl + ": %0d %0d %0d %0d")
+                   (v !! 0) (v !! 1) (v !! 2) (v !! 3)
+    rules
+      "test": when True ==> action
+        let a :: ListN 4 (Int 16)
+            a = genWith fromInteger              -- 0 1 2 3
+            b :: ListN 4 (Int 16)
+            b = replicate 10                     -- 10 10 10 10
+
+        -- Functor: fmap maps a function over the ListN.
+        let f :: ListN 4 (Int 16)
+            f = fmap incr a                      -- 1 2 3 4
+
+        -- Applicative: pure broadcasts a single value.
+        let p :: ListN 4 (Int 16)
+            p = pure 7                           -- 7 7 7 7
+
+        -- Applicative: liftA2 zips two ListNs with a binary function.
+        let s :: ListN 4 (Int 16)
+            s = liftA2 (+) a b                   -- 10 11 12 13
+            m :: ListN 4 (Int 16)
+            m = liftA2 (*) a (pure 2)            -- 0 2 4 6
+
+        -- Applicative: <*> applies a ListN of functions pointwise.
+        let ap :: ListN 4 (Int 16)
+            ap = pure incr <*> a                 -- 1 2 3 4
+
+        sh "a" a
+        sh "b" b
+        sh "f" f
+        sh "p" p
+        sh "s" s
+        sh "m" m
+        sh "ap" ap
+        $finish 0
diff --git a/testsuite/bsc.lib/listn/Makefile b/testsuite/bsc.lib/listn/Makefile
new file mode 100644
index 000000000..b953e8132
--- /dev/null
+++ b/testsuite/bsc.lib/listn/Makefile
@@ -0,0 +1,5 @@
+# for "make clean" to work everywhere
+
+CONFDIR = $(realpath ../..)
+
+include $(CONFDIR)/clean.mk
diff --git a/testsuite/bsc.lib/listn/liblistn.exp b/testsuite/bsc.lib/listn/liblistn.exp
new file mode 100644
index 000000000..777abd699
--- /dev/null
+++ b/testsuite/bsc.lib/listn/liblistn.exp
@@ -0,0 +1,2 @@
+
+test_c_veri ApplicativeListN
diff --git a/testsuite/bsc.lib/listn/sysApplicativeListN.out.expected b/testsuite/bsc.lib/listn/sysApplicativeListN.out.expected
new file mode 100644
index 000000000..ffdfcbaa3
--- /dev/null
+++ b/testsuite/bsc.lib/listn/sysApplicativeListN.out.expected
@@ -0,0 +1,7 @@
+a: 0 1 2 3
+b: 10 10 10 10
+f: 1 2 3 4
+p: 7 7 7 7
+s: 10 11 12 13
+m: 0 2 4 6
+ap: 1 2 3 4
diff --git a/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected b/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected
index d7939673a..c065356dc 100644
--- a/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected
@@ -9,7 +9,8 @@ order: [_write, _read, RL_the_r_propagate]
 
 === resources (BypassReg sysBypassReg):
 [(the_r_the_r.read, [(the_r_the_r.read, 1)]),
- (the_r_the_r.write, [(the_r_the_r.write x__h131, 1)]),
+ (the_r_the_r.write,
+  [(the_r_the_r.write IF_the_r_the_rw_whas_THEN_the_r_the_rw_wget_EL_ETC___d3, 1)]),
  (the_r_the_rw.wget, [(the_r_the_rw.wget, 1)]),
  (the_r_the_rw.whas, [(the_r_the_rw.whas, 1)]),
  (the_r_the_rw.wset, [(the_r_the_rw.wset _write_1, 1)])]
diff --git a/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected b/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected
index 79f7c43d0..cab9657d0 100644
--- a/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [_write, _read, RL_the_r_propagate]
 
 === resources (ConfigReg2 sysConfigReg):
 [(the_r_the_r.read, [(the_r_the_r.read, 1)]),
- (the_r_the_r.write, [(the_r_the_r.write x__h151, 1)]),
+ (the_r_the_r.write, [(the_r_the_r.write the_r_the_rw_wget____d2, 1)]),
  (the_r_the_rw.wget, [(the_r_the_rw.wget, 1)]),
  (the_r_the_rw.whas, [(the_r_the_rw.whas, 1)]),
  (the_r_the_rw.wset, [(the_r_the_rw.wset _write_1, 1)])]
diff --git a/testsuite/bsc.lib/rwire/mkTestENBypassWire2.v1.v.expected b/testsuite/bsc.lib/rwire/mkTestENBypassWire2.v1.v.expected
index 41a4a64cc..7c0d982fd 100644
--- a/testsuite/bsc.lib/rwire/mkTestENBypassWire2.v1.v.expected
+++ b/testsuite/bsc.lib/rwire/mkTestENBypassWire2.v1.v.expected
@@ -29,6 +29,9 @@ module mkTestENBypassWire2(CLK,
   input  CLK;
   input  RST_N;
 
+  // inlined wires
+  wire [31 : 0] testWire$wget;
+
   // register counter
   reg [31 : 0] counter;
   wire [31 : 0] counter$D_IN;
@@ -40,7 +43,9 @@ module mkTestENBypassWire2(CLK,
 
   // remaining internal signals
   wire [63 : 0] counter_MUL_counter___d5;
-  wire [31 : 0] testWire__read__h212;
+
+  // inlined wires
+  assign testWire$wget = toggle ? counter_MUL_counter___d5[31:0] : 32'd0 ;
 
   // register counter
   assign counter$D_IN = counter + 32'd1 ;
@@ -52,8 +57,6 @@ module mkTestENBypassWire2(CLK,
 
   // remaining internal signals
   assign counter_MUL_counter___d5 = counter * counter ;
-  assign testWire__read__h212 =
-	     toggle ? counter_MUL_counter___d5[31:0] : 32'd0 ;
 
   // handling of inlined registers
 
@@ -88,7 +91,7 @@ module mkTestENBypassWire2(CLK,
   always@(negedge CLK)
   begin
     #0;
-    if (RST_N != `BSV_RESET_VALUE) $display("Wire: %h", testWire__read__h212);
+    if (RST_N != `BSV_RESET_VALUE) $display("Wire: %h", testWire$wget);
   end
   // synopsys translate_on
 endmodule  // mkTestENBypassWire2
diff --git a/testsuite/bsc.lib/vector/ApplicativeVector.bs b/testsuite/bsc.lib/vector/ApplicativeVector.bs
new file mode 100644
index 000000000..7aa2f0861
--- /dev/null
+++ b/testsuite/bsc.lib/vector/ApplicativeVector.bs
@@ -0,0 +1,50 @@
+package ApplicativeVector where
+
+import Vector
+
+-- Test the Functor and Applicative instances for Vector.
+
+incr :: Int 16 -> Int 16
+incr x = x + 1
+
+{-# verilog sysApplicativeVector #-}
+sysApplicativeVector :: Module Empty
+sysApplicativeVector =
+  module
+    let sh :: String -> Vector 4 (Int 16) -> Action
+        sh lbl v =
+          $display (lbl + ": %0d %0d %0d %0d")
+                   (v !! 0) (v !! 1) (v !! 2) (v !! 3)
+    rules
+      "test": when True ==> action
+        let a :: Vector 4 (Int 16)
+            a = genWith fromInteger              -- 0 1 2 3
+            b :: Vector 4 (Int 16)
+            b = replicate 10                     -- 10 10 10 10
+
+        -- Functor: fmap maps a function over the vector.
+        let f :: Vector 4 (Int 16)
+            f = fmap incr a                      -- 1 2 3 4
+
+        -- Applicative: pure broadcasts a single value.
+        let p :: Vector 4 (Int 16)
+            p = pure 7                           -- 7 7 7 7
+
+        -- Applicative: liftA2 zips two vectors with a binary function.
+        let s :: Vector 4 (Int 16)
+            s = liftA2 (+) a b                   -- 10 11 12 13
+            m :: Vector 4 (Int 16)
+            m = liftA2 (*) a (pure 2)            -- 0 2 4 6
+
+        -- Applicative: <*> applies a vector of functions pointwise.
+        let ap :: Vector 4 (Int 16)
+            ap = pure incr <*> a                 -- 1 2 3 4
+
+        sh "a" a
+        sh "b" b
+        sh "f" f
+        sh "p" p
+        sh "s" s
+        sh "m" m
+        sh "ap" ap
+        $finish 0
diff --git a/testsuite/bsc.lib/vector/libvector.exp b/testsuite/bsc.lib/vector/libvector.exp
index 31039fedd..418c0321d 100644
--- a/testsuite/bsc.lib/vector/libvector.exp
+++ b/testsuite/bsc.lib/vector/libvector.exp
@@ -14,3 +14,5 @@ test_c_veri_bsv ZeroVector
 test_c_veri_bsv FromChunksTest
 
 test_c_veri_bs_modules ConcatTuple {}
+
+test_c_veri ApplicativeVector
diff --git a/testsuite/bsc.lib/vector/sysApplicativeVector.out.expected b/testsuite/bsc.lib/vector/sysApplicativeVector.out.expected
new file mode 100644
index 000000000..ffdfcbaa3
--- /dev/null
+++ b/testsuite/bsc.lib/vector/sysApplicativeVector.out.expected
@@ -0,0 +1,7 @@
+a: 0 1 2 3
+b: 10 10 10 10
+f: 1 2 3 4
+p: 7 7 7 7
+s: 10 11 12 13
+m: 0 2 4 6
+ap: 1 2 3 4
diff --git a/testsuite/bsc.mcd/LevelFifo/LevelFifo.exp b/testsuite/bsc.mcd/LevelFifo/LevelFifo.exp
index 38218559b..2d81dbc43 100644
--- a/testsuite/bsc.mcd/LevelFifo/LevelFifo.exp
+++ b/testsuite/bsc.mcd/LevelFifo/LevelFifo.exp
@@ -32,8 +32,13 @@ test_c_only_bsv SyncFIFOCountTest sysSyncFIFOCountTest.c.out.expected
 test_veri_only_bsv LevelFIFOTest1
 test_c_only_bsv LevelFIFOTest1 sysLevelFIFOTest1.c.out.expected
 
-test_veri_only_bsv SyncLevelFIFOTest {} $iverilog09_bug
-test_c_only_bsv SyncLevelFIFOTest sysSyncLevelFIFOTest.c.out.expected
+# The output differs depending on whether aggr-conds is on;
+# we ensure that it is off, to match the current expected file.
+# This could be changed to aggr-conds on, but the output would
+# need to be audited to ensure that it is correct.
+#
+test_veri_only_bsv_modules_options SyncLevelFIFOTest {} {-no-aggressive-conditions} {} $iverilog09_bug
+test_c_only_bsv_modules_options SyncLevelFIFOTest {} {-no-aggressive-conditions} sysSyncLevelFIFOTest.c.out.expected
 
 
 ##
diff --git a/testsuite/bsc.misc/lambda_calculus/lambda_calculus.exp b/testsuite/bsc.misc/lambda_calculus/lambda_calculus.exp
index da69a9e2b..8da6488a7 100644
--- a/testsuite/bsc.misc/lambda_calculus/lambda_calculus.exp
+++ b/testsuite/bsc.misc/lambda_calculus/lambda_calculus.exp
@@ -59,7 +59,8 @@ compare_file_filter_ids lc-sysStructs.out
 # Test for lifting if condition in action
 if { $vtest == 1 } {
 
-compile_verilog_pass MergeIf.bsv {} $opts
+# Output differs if aggr-conds is on, so ensure it is
+compile_verilog_pass MergeIf.bsv {} "$opts -aggressive-conditions"
 compare_file_filter_ids lc-sysMergeIf.out
 
 # XXX Nothing merges here yet, because the defs are not inlined
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysDynArrSelWithImplCond.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysDynArrSelWithImplCond.out.expected
index 6950a44cc..4ea4d5078 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysDynArrSelWithImplCond.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysDynArrSelWithImplCond.out.expected
@@ -31,28 +31,21 @@ dim_sysDynArrSelWithImplCond =
 meth_get_sysDynArrSelWithImplCond :: MOD_sysDynArrSelWithImplCond -> Bit #8;
 meth_get_sysDynArrSelWithImplCond =
     (\ (state0 :: MOD_sysDynArrSelWithImplCond) ->
-     let { (def__element_first__h710 :: Bit #8) =
-	       meth_first_FIFO2 (inst_fs_3__sysDynArrSelWithImplCond state0)
-	 ; (def__element_first__h704 :: Bit #8) =
-	       meth_first_FIFO2 (inst_fs_2__sysDynArrSelWithImplCond state0)
-	 ; (def__element_first__h698 :: Bit #8) =
-	       meth_first_FIFO2 (inst_fs_1__sysDynArrSelWithImplCond state0)
-	 ; (def__element_first__h692 :: Bit #8) =
+     let { (def_fs_0_first____d1 :: Bit #8) =
 	       meth_first_FIFO2 (inst_fs_0__sysDynArrSelWithImplCond state0)
-	 ; (def_x__h558 :: Bit #2) = meth_read_RegN (inst_idx__sysDynArrSelWithImplCond state0)
+	 ; (def_idx___d6 :: Bit #2) = meth_read_RegN (inst_idx__sysDynArrSelWithImplCond state0)
+	 ; (def_fs_1_first____d2 :: Bit #8) = meth_first_FIFO2 (inst_fs_1__sysDynArrSelWithImplCond state0)
+	 ; (def_fs_2_first____d3 :: Bit #8) = meth_first_FIFO2 (inst_fs_2__sysDynArrSelWithImplCond state0)
+	 ; (def_fs_3_first____d4 :: Bit #8) = meth_first_FIFO2 (inst_fs_3__sysDynArrSelWithImplCond state0)
 	 ; (def_ARR_fs_0_first_fs_1_first_fs_2_first_fs_3_first___d5 :: Array #4 (Bit #8)) =
-	       buildArray4
-		   def__element_first__h692
-		   def__element_first__h698
-		   def__element_first__h704
-		   def__element_first__h710
+	       buildArray4 def_fs_0_first____d1 def_fs_1_first____d2 def_fs_2_first____d3 def_fs_3_first____d4
 	 }
-     in arraySelect def_ARR_fs_0_first_fs_1_first_fs_2_first_fs_3_first___d5 def_x__h558);
+     in arraySelect def_ARR_fs_0_first_fs_1_first_fs_2_first_fs_3_first___d5 def_idx___d6);
 
 meth_RDY_get_sysDynArrSelWithImplCond :: MOD_sysDynArrSelWithImplCond -> Bool;
 meth_RDY_get_sysDynArrSelWithImplCond =
     (\ (state0 :: MOD_sysDynArrSelWithImplCond) ->
-     let { (def_x__h558 :: Bit #2) = meth_read_RegN (inst_idx__sysDynArrSelWithImplCond state0)
+     let { (def_idx___d6 :: Bit #2) = meth_read_RegN (inst_idx__sysDynArrSelWithImplCond state0)
 	 ; (def_fs_0_i_notEmpty____d7 :: Bit #1) =
 	       meth_i_notEmpty_FIFO2 (inst_fs_0__sysDynArrSelWithImplCond state0)
 	 ; (def_fs_1_i_notEmpty____d8 :: Bit #1) =
@@ -63,12 +56,12 @@ meth_RDY_get_sysDynArrSelWithImplCond =
 	       meth_i_notEmpty_FIFO2 (inst_fs_3__sysDynArrSelWithImplCond state0)
 	 }
      in bitToBool
-	    (if (primEQ def_x__h558 (0 :: Bit #2))
+	    (if (primEQ def_idx___d6 (0 :: Bit #2))
 	     then def_fs_0_i_notEmpty____d7
-	     else if (primEQ def_x__h558 (1 :: Bit #2))
+	     else if (primEQ def_idx___d6 (1 :: Bit #2))
 		  then def_fs_1_i_notEmpty____d8
-		  else if (primEQ def_x__h558 (2 :: Bit #2))
+		  else if (primEQ def_idx___d6 (2 :: Bit #2))
 		       then def_fs_2_i_notEmpty____d9
-		       else if (primEQ def_x__h558 (3 :: Bit #2)) then def_fs_3_i_notEmpty____d10 else (1 :: Bit #1)));
+		       else if (primEQ def_idx___d6 (3 :: Bit #2)) then def_fs_3_i_notEmpty____d10 else (1 :: Bit #1)));
 
 -----
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysExtract.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysExtract.out.expected
index 4e471a87b..79453fcbc 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysExtract.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysExtract.out.expected
@@ -34,10 +34,10 @@ dim_sysExtract =
 rule_RL_do_static_sysExtract :: MOD_sysExtract -> (Bool, MOD_sysExtract, ());
 rule_RL_do_static_sysExtract =
     (\ (state0 :: MOD_sysExtract) ->
-     let { (def_src1__h124 :: Bit #12) = meth_read_RegUN (inst_src1__sysExtract state0)
+     let { (def_src1__h109 :: Bit #12) = meth_read_RegUN (inst_src1__sysExtract state0)
 	 ; (act1 :: (Bool, MOD_RegUN #8, ())) =
 	       meth_write_RegUN
-		   ((primExtract def_src1__h124 (9 :: Bit #32) (2 :: Bit #32)) :: Bit #8)
+		   ((primExtract def_src1__h109 (9 :: Bit #32) (2 :: Bit #32)) :: Bit #8)
 		   (inst_snk1__sysExtract state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysExtract) = state0 { inst_snk1__sysExtract = snd3 act1 }
@@ -47,11 +47,13 @@ rule_RL_do_static_sysExtract =
 rule_RL_do_dynamic_sysExtract :: MOD_sysExtract -> (Bool, MOD_sysExtract, ());
 rule_RL_do_dynamic_sysExtract =
     (\ (state0 :: MOD_sysExtract) ->
-     let { (def_i2__h246 :: Bit #4) = meth_read_RegUN (inst_lo_idx__sysExtract state0)
-	 ; (def_i1__h245 :: Bit #4) = meth_read_RegUN (inst_hi_idx__sysExtract state0)
-	 ; (def_bs__h244 :: Bit #12) = meth_read_RegUN (inst_src2__sysExtract state0)
-	 ; (def_x__h238 :: Bit #8) = ((primExtract def_bs__h244 def_i1__h245 def_i2__h246) :: Bit #8)
-	 ; (act1 :: (Bool, MOD_RegUN #8, ())) = meth_write_RegUN def_x__h238 (inst_snk2__sysExtract state0)
+     let { (def_i2__h226 :: Bit #4) = meth_read_RegUN (inst_lo_idx__sysExtract state0)
+	 ; (def_i1__h225 :: Bit #4) = meth_read_RegUN (inst_hi_idx__sysExtract state0)
+	 ; (def_bs__h224 :: Bit #12) = meth_read_RegUN (inst_src2__sysExtract state0)
+	 ; (def_src2_BITS_hi_idx_TO_lo_idx___d6 :: Bit #8) =
+	       ((primExtract def_bs__h224 def_i1__h225 def_i2__h226) :: Bit #8)
+	 ; (act1 :: (Bool, MOD_RegUN #8, ())) =
+	       meth_write_RegUN def_src2_BITS_hi_idx_TO_lo_idx___d6 (inst_snk2__sysExtract state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysExtract) = state0 { inst_snk2__sysExtract = snd3 act1 }
 	 }
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysMergeIf.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysMergeIf.out.expected
index 9b9d2fed8..bd490c5c3 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysMergeIf.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysMergeIf.out.expected
@@ -43,14 +43,14 @@ dim_sysMergeIf =
 rule_RL_r1_sysMergeIf :: MOD_sysMergeIf -> (Bool, MOD_sysMergeIf, ());
 rule_RL_r1_sysMergeIf =
     (\ (state0 :: MOD_sysMergeIf) ->
-     let { (def_s1__h527 :: Bit #1) = meth_read_RegN (inst_s1__sysMergeIf state0)
+     let { (def_s1__h472 :: Bit #1) = meth_read_RegN (inst_s1__sysMergeIf state0)
 	 ; (def_f3_i_notFull____d1 :: Bit #1) = meth_i_notFull_FIFO2 (inst_f3__sysMergeIf state0)
-	 ; (def_f2_i_notFull____d2 :: Bit #1) = meth_i_notFull_FIFO2 (inst_f2__sysMergeIf state0)
-	 ; (def_f1_i_notFull____d3 :: Bit #1) = meth_i_notFull_FIFO2 (inst_f1__sysMergeIf state0)
-	 ; (def_f2_i_notFull_AND_f1_i_notFull___d4 :: Bool) =
-	       (bitToBool def_f2_i_notFull____d2) && (bitToBool def_f1_i_notFull____d3)
-	 ; (def_f3_i_notFull_AND_f2_i_notFull_AND_f1_i_notFull___d5 :: Bool) =
-	       (bitToBool def_f3_i_notFull____d1) && def_f2_i_notFull_AND_f1_i_notFull___d4
+	 ; (def_f2_i_notFull____d3 :: Bit #1) = meth_i_notFull_FIFO2 (inst_f2__sysMergeIf state0)
+	 ; (def_f1_i_notFull____d4 :: Bit #1) = meth_i_notFull_FIFO2 (inst_f1__sysMergeIf state0)
+	 ; (def_IF_s1_THEN_f2_i_notFull_ELSE_f1_i_notFull___d5 :: Bit #1) =
+	       if (bitToBool def_s1__h472) then def_f2_i_notFull____d3 else def_f1_i_notFull____d4
+	 ; (def_f3_i_notFull_AND_IF_s1_THEN_f2_i_notFull_ELSE__ETC___d6 :: Bool) =
+	       (bitToBool def_f3_i_notFull____d1) && (bitToBool def_IF_s1_THEN_f2_i_notFull_ELSE_f1_i_notFull___d5)
 	 ; (act1 :: (Bool, MOD_RegN #17, ())) = meth_write_RegN (5 :: Bit #17) (inst_a__sysMergeIf state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysMergeIf) = state0 { inst_a__sysMergeIf = snd3 act1 }
@@ -63,16 +63,16 @@ rule_RL_r1_sysMergeIf =
 	 ; (act4 :: (Bool, MOD_RegN #17, ())) = meth_write_RegN (7 :: Bit #17) (inst_c__sysMergeIf state0)
 	 ; (guard4 :: Bool) = fst3 act4
 	 ; (state4 :: MOD_sysMergeIf) = state0 { inst_c__sysMergeIf = snd3 act4 }
-	 ; (guard5 :: Bool) = if (bitToBool def_s1__h527) then guard3 else guard4
-	 ; (state5 :: MOD_sysMergeIf) = if (bitToBool def_s1__h527) then state3 else state4
+	 ; (guard5 :: Bool) = if (bitToBool def_s1__h472) then guard3 else guard4
+	 ; (state5 :: MOD_sysMergeIf) = if (bitToBool def_s1__h472) then state3 else state4
 	 ; (act6 :: (Bool, MOD_FIFO2 #17, ())) = meth_enq_FIFO2 (22 :: Bit #17) (inst_f3__sysMergeIf state5)
 	 ; (guard6 :: Bool) = guard5 && (fst3 act6)
 	 ; (state6 :: MOD_sysMergeIf) = state5 { inst_f3__sysMergeIf = snd3 act6 }
 	 ; (act7 :: (Bool, MOD_FIFO2 #17, ())) = meth_enq_FIFO2 (12 :: Bit #17) (inst_f1__sysMergeIf state6)
-	 ; (guard7 :: Bool) = if (not (bitToBool def_s1__h527)) then guard6 && (fst3 act7) else guard6
+	 ; (guard7 :: Bool) = if (not (bitToBool def_s1__h472)) then guard6 && (fst3 act7) else guard6
 	 ; (state7 :: MOD_sysMergeIf) =
-	       if (not (bitToBool def_s1__h527)) then state6 { inst_f1__sysMergeIf = snd3 act7 } else state6
+	       if (not (bitToBool def_s1__h472)) then state6 { inst_f1__sysMergeIf = snd3 act7 } else state6
 	 }
-     in mktuple (def_f3_i_notFull_AND_f2_i_notFull_AND_f1_i_notFull___d5 && guard7) state7 ());
+     in mktuple (def_f3_i_notFull_AND_IF_s1_THEN_f2_i_notFull_ELSE__ETC___d6 && guard7) state7 ());
 
 -----
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysMethod_Split.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysMethod_Split.out.expected
index 0c544bb8c..3226905d4 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysMethod_Split.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysMethod_Split.out.expected
@@ -27,29 +27,35 @@ meth_m_sysMethod_Split =
     (\ (state0 :: MOD_sysMethod_Split) ->
      let { (def_c__h144 :: Bit #1) = meth_read_RegUN (inst_c__sysMethod_Split state0) }
      in if (bitToBool def_c__h144)
-	then let { (def_x__h224 :: Bit #8) = meth_read_RegUN (inst_rg1__sysMethod_Split state0)
-		 ; (def_x__h251 :: Bit #8) = meth_read_RegUN (inst_rg2__sysMethod_Split state0)
-		 ; (def_x__h174 :: Bit #8) = primAdd def_x__h224 (3 :: Bit #8)
-		 ; (def_x__h249 :: Bit #8) = primAdd def_x__h251 (2 :: Bit #8)
-		 ; (def_x__h222 :: Bit #8) = primAdd def_x__h224 (1 :: Bit #8)
+	then let { (def_rg2___d5 :: Bit #8) = meth_read_RegUN (inst_rg2__sysMethod_Split state0)
+		 ; (def_rg1___d2 :: Bit #8) = meth_read_RegUN (inst_rg1__sysMethod_Split state0)
+		 ; (def_rg1_PLUS_3___d3 :: Bit #8) = primAdd def_rg1___d2 (3 :: Bit #8)
+		 ; (def_rg1_PLUS_1___d7 :: Bit #8) = primAdd def_rg1___d2 (1 :: Bit #8)
+		 ; (def_rg2_PLUS_2___d8 :: Bit #8) = primAdd def_rg2___d5 (2 :: Bit #8)
 		 ; (act1 :: (Bool, MOD_RegUN #8, ())) =
-		       meth_write_RegUN def_x__h174 (inst_rg1__sysMethod_Split state0)
+		       meth_write_RegUN def_rg1_PLUS_3___d3 (inst_rg1__sysMethod_Split state0)
 		 ; (guard1 :: Bool) = fst3 act1
 		 ; (state1 :: MOD_sysMethod_Split) = state0 { inst_rg1__sysMethod_Split = snd3 act1 }
 		 }
-	     in mktuple guard1 state1 (if (bitToBool def_c__h144) then def_x__h222 else def_x__h249)
+	     in mktuple
+		    guard1
+		    state1
+		    (if (bitToBool def_c__h144) then def_rg1_PLUS_1___d7 else def_rg2_PLUS_2___d8)
 	else if (not (bitToBool def_c__h144))
-	     then let { (def_x__h224 :: Bit #8) = meth_read_RegUN (inst_rg1__sysMethod_Split state0)
-		      ; (def_x__h251 :: Bit #8) = meth_read_RegUN (inst_rg2__sysMethod_Split state0)
-		      ; (def_x__h226 :: Bit #8) = primAdd def_x__h251 (4 :: Bit #8)
-		      ; (def_x__h249 :: Bit #8) = primAdd def_x__h251 (2 :: Bit #8)
-		      ; (def_x__h222 :: Bit #8) = primAdd def_x__h224 (1 :: Bit #8)
+	     then let { (def_rg2___d5 :: Bit #8) = meth_read_RegUN (inst_rg2__sysMethod_Split state0)
+		      ; (def_rg1___d2 :: Bit #8) = meth_read_RegUN (inst_rg1__sysMethod_Split state0)
+		      ; (def_rg2_PLUS_4___d6 :: Bit #8) = primAdd def_rg2___d5 (4 :: Bit #8)
+		      ; (def_rg1_PLUS_1___d7 :: Bit #8) = primAdd def_rg1___d2 (1 :: Bit #8)
+		      ; (def_rg2_PLUS_2___d8 :: Bit #8) = primAdd def_rg2___d5 (2 :: Bit #8)
 		      ; (act1 :: (Bool, MOD_RegUN #8, ())) =
-			    meth_write_RegUN def_x__h226 (inst_rg2__sysMethod_Split state0)
+			    meth_write_RegUN def_rg2_PLUS_4___d6 (inst_rg2__sysMethod_Split state0)
 		      ; (guard1 :: Bool) = fst3 act1
 		      ; (state1 :: MOD_sysMethod_Split) = state0 { inst_rg2__sysMethod_Split = snd3 act1 }
 		      }
-		  in mktuple guard1 state1 (if (bitToBool def_c__h144) then def_x__h222 else def_x__h249)
+		  in mktuple
+			 guard1
+			 state1
+			 (if (bitToBool def_c__h144) then def_rg1_PLUS_1___d7 else def_rg2_PLUS_2___d8)
 	     else nullUpd);
 
 meth_RDY_m_sysMethod_Split :: MOD_sysMethod_Split -> Bool;
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysMethods.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysMethods.out.expected
index 7a2bfcd99..472f68e83 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysMethods.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysMethods.out.expected
@@ -22,15 +22,15 @@ dim_sysMethods =
 rule_RL_flip_sysMethods :: MOD_sysMethods -> (Bool, MOD_sysMethods, ());
 rule_RL_flip_sysMethods =
     (\ (state0 :: MOD_sysMethods) ->
-     let { (def_b__h117 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
-	 ; (def_b__h116 :: Bit #51) = meth_read_RegN (inst_x__sysMethods state0)
-	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_b__h117 (0 :: Bit #51)
-	 ; (def_x_ULE_y___d3 :: Bool) = primULE def_b__h116 def_b__h117
+     let { (def_y__h360 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
+	 ; (def_x__h359 :: Bit #51) = meth_read_RegN (inst_x__sysMethods state0)
+	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_y__h360 (0 :: Bit #51)
+	 ; (def_x_ULE_y___d3 :: Bool) = primULE def_x__h359 def_y__h360
 	 ; (def_NOT_x_ULE_y_AND_NOT_y_EQ_0___d7 :: Bool) = (not def_x_ULE_y___d3) && (not def_y_EQ_0___d5)
-	 ; (act1 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h117 (inst_x__sysMethods state0)
+	 ; (act1 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_y__h360 (inst_x__sysMethods state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysMethods) = state0 { inst_x__sysMethods = snd3 act1 }
-	 ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h116 (inst_y__sysMethods state1)
+	 ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_x__h359 (inst_y__sysMethods state1)
 	 ; (guard2 :: Bool) = guard1 && (fst3 act2)
 	 ; (state2 :: MOD_sysMethods) = state1 { inst_y__sysMethods = snd3 act2 }
 	 }
@@ -39,12 +39,12 @@ rule_RL_flip_sysMethods =
 rule_RL_sub_sysMethods :: MOD_sysMethods -> (Bool, MOD_sysMethods, ());
 rule_RL_sub_sysMethods =
     (\ (state0 :: MOD_sysMethods) ->
-     let { (def_b__h117 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
-	 ; (def_b__h116 :: Bit #51) = meth_read_RegN (inst_x__sysMethods state0)
-	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_b__h117 (0 :: Bit #51)
-	 ; (def_x_ULE_y___d3 :: Bool) = primULE def_b__h116 def_b__h117
+     let { (def_y__h360 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
+	 ; (def_x__h359 :: Bit #51) = meth_read_RegN (inst_x__sysMethods state0)
+	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_y__h360 (0 :: Bit #51)
+	 ; (def_x_ULE_y___d3 :: Bool) = primULE def_x__h359 def_y__h360
 	 ; (def_x_ULE_y_AND_NOT_y_EQ_0___d8 :: Bool) = def_x_ULE_y___d3 && (not def_y_EQ_0___d5)
-	 ; (def_y_MINUS_x___d9 :: Bit #51) = primSub def_b__h117 def_b__h116
+	 ; (def_y_MINUS_x___d9 :: Bit #51) = primSub def_y__h360 def_x__h359
 	 ; (act1 :: (Bool, MOD_RegN #51, ())) =
 	       meth_write_RegN def_y_MINUS_x___d9 (inst_y__sysMethods state0)
 	 ; (guard1 :: Bool) = fst3 act1
@@ -59,8 +59,8 @@ meth_result_sysMethods =
 meth_RDY_result_sysMethods :: MOD_sysMethods -> Bool;
 meth_RDY_result_sysMethods =
     (\ (state0 :: MOD_sysMethods) ->
-     let { (def_b__h117 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
-	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_b__h117 (0 :: Bit #51)
+     let { (def_y__h360 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
+	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_y__h360 (0 :: Bit #51)
 	 }
      in def_y_EQ_0___d5);
 
@@ -82,8 +82,8 @@ meth_start_sysMethods =
 meth_RDY_start_sysMethods :: MOD_sysMethods -> Bool;
 meth_RDY_start_sysMethods =
     (\ (state0 :: MOD_sysMethods) ->
-     let { (def_b__h117 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
-	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_b__h117 (0 :: Bit #51)
+     let { (def_y__h360 :: Bit #51) = meth_read_RegN (inst_y__sysMethods state0)
+	 ; (def_y_EQ_0___d5 :: Bool) = primEQ def_y__h360 (0 :: Bit #51)
 	 }
      in def_y_EQ_0___d5);
 
@@ -92,7 +92,7 @@ meth_start_and_result_sysMethods =
     (\ (arg_start_and_result_num1 :: Bit #51) ->
      (\ (arg_start_and_result_num2 :: Bit #51) ->
       (\ (state0 :: MOD_sysMethods) ->
-       let { (def_b__h116 :: Bit #51) = meth_read_RegN (inst_x__sysMethods state0)
+       let { (def_x__h359 :: Bit #51) = meth_read_RegN (inst_x__sysMethods state0)
 	   ; (act1 :: (Bool, MOD_RegN #51, ())) =
 		 meth_write_RegN arg_start_and_result_num1 (inst_x__sysMethods state0)
 	   ; (guard1 :: Bool) = fst3 act1
@@ -102,7 +102,7 @@ meth_start_and_result_sysMethods =
 	   ; (guard2 :: Bool) = guard1 && (fst3 act2)
 	   ; (state2 :: MOD_sysMethods) = state1 { inst_y__sysMethods = snd3 act2 }
 	   }
-       in mktuple guard2 state2 def_b__h116)));
+       in mktuple guard2 state2 def_x__h359)));
 
 meth_RDY_start_and_result_sysMethods :: MOD_sysMethods -> Bool;
 meth_RDY_start_and_result_sysMethods =
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected
index 493d98266..7b9d63614 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysMultiArityConcat.out.expected
@@ -28,12 +28,12 @@ dim_sysMultiArityConcat =
 rule_RL_d_sysMultiArityConcat :: MOD_sysMultiArityConcat -> (Bool, MOD_sysMultiArityConcat, ());
 rule_RL_d_sysMultiArityConcat =
     (\ (state0 :: MOD_sysMultiArityConcat) ->
-     let { (def__read__h37 :: Bit #3) = meth_read_RegUN (inst_src1__sysMultiArityConcat state0)
-	 ; (def__read__h87 :: Bit #5) = meth_read_RegUN (inst_src3__sysMultiArityConcat state0)
-	 ; (def__read__h62 :: Bit #4) = meth_read_RegUN (inst_src2__sysMultiArityConcat state0)
+     let { (def_src1___d1 :: Bit #3) = meth_read_RegUN (inst_src1__sysMultiArityConcat state0)
+	 ; (def_src2___d2 :: Bit #4) = meth_read_RegUN (inst_src2__sysMultiArityConcat state0)
+	 ; (def_src3___d3 :: Bit #5) = meth_read_RegUN (inst_src3__sysMultiArityConcat state0)
 	 ; (act1 :: (Bool, MOD_RegUN #12, ())) =
 	       meth_write_RegUN
-		   (primConcat def__read__h37 (primConcat def__read__h62 def__read__h87))
+		   (primConcat def_src1___d1 (primConcat def_src2___d2 def_src3___d3))
 		   (inst_snk__sysMultiArityConcat state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysMultiArityConcat) = state0 { inst_snk__sysMultiArityConcat = snd3 act1 }
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected
index 2861363ff..61225fc28 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysStructs.out.expected
@@ -46,19 +46,20 @@ dim_sysStructs =
 rule_RL_add_em_sysStructs :: MOD_sysStructs -> (Bool, MOD_sysStructs, ());
 rule_RL_add_em_sysStructs =
     (\ (state0 :: MOD_sysStructs) ->
-     let { (def_x__h549 :: Bit #9) = meth_read_RegN (inst_a__sysStructs state0)
-	 ; (def_x__h557 :: Bit #9) = meth_read_RegN (inst_b__sysStructs state0)
-	 ; (def_x__h541 :: Bit #9) = primAdd def_x__h549 def_x__h557
-	 ; (def_x__h529 :: Bit #9) = primAdd def_x__h541 (4 :: Bit #9)
-	 ; (def_s__h482 :: Bit #1) = meth_read_RegN (inst_s__sysStructs state0)
-	 ; (act1 :: (Bool, MOD_RegN #9, ())) = meth_write_RegN def_x__h529 (inst_a__sysStructs state0)
+     let { (def_a__h504 :: Bit #9) = meth_read_RegN (inst_a__sysStructs state0)
+	 ; (def_b__h512 :: Bit #9) = meth_read_RegN (inst_b__sysStructs state0)
+	 ; (def_s__h444 :: Bit #1) = meth_read_RegN (inst_s__sysStructs state0)
+	 ; (def_a_PLUS_b___d4 :: Bit #9) = primAdd def_a__h504 def_b__h512
+	 ; (def_a_PLUS_b_PLUS_4___d5 :: Bit #9) = primAdd def_a_PLUS_b___d4 (4 :: Bit #9)
+	 ; (act1 :: (Bool, MOD_RegN #9, ())) =
+	       meth_write_RegN def_a_PLUS_b_PLUS_4___d5 (inst_a__sysStructs state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysStructs) = state0 { inst_a__sysStructs = snd3 act1 }
 	 ; (act2 :: (Bool, MOD_RegN #1, ())) = meth_write_RegN (0 :: Bit #1) (inst_s__sysStructs state1)
 	 ; (guard2 :: Bool) = guard1 && (fst3 act2)
 	 ; (state2 :: MOD_sysStructs) = state1 { inst_s__sysStructs = snd3 act2 }
 	 }
-     in mktuple ((bitToBool def_s__h482) && guard2) state2 ());
+     in mktuple ((bitToBool def_s__h444) && guard2) state2 ());
 
 rule_RL_tss_sysStructs :: MOD_sysStructs -> (Bool, MOD_sysStructs, ());
 rule_RL_tss_sysStructs =
diff --git a/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected b/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected
index 76df74ea6..b8f66649d 100644
--- a/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected
+++ b/testsuite/bsc.misc/lambda_calculus/lc-sysTb.out.expected
@@ -31,22 +31,22 @@ dim_sysTb =
 rule_RL_r0_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ());
 rule_RL_r0_sysTb =
     (\ (state0 :: MOD_sysTb) ->
-     let { (def_b__h532 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0)
-	 ; (def_b__h543 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0)
-	 ; (def_x__h979 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0)
-	 ; (def_b__h612 :: Bit #51) = noinline_add def_b__h532 (3 :: Bit #51)
-	 ; (def_b__h703 :: Bit #51) = noinline_add def_b__h543 (2 :: Bit #51)
+     let { (def_c1__h532 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0)
+	 ; (def_c2__h543 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0)
+	 ; (def_state___d2 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0)
 	 ; (def_gcd_RDY_start____d1 :: Bool) = meth_RDY_start_sysMethods (inst_gcd__sysTb state0)
-	 ; (def_state_EQ_0___d3 :: Bool) = primEQ def_x__h979 (0 :: Bit #2)
+	 ; (def_add___d7 :: Bit #51) = noinline_add def_c1__h532 (3 :: Bit #51)
+	 ; (def_add___d8 :: Bit #51) = noinline_add def_c2__h543 (2 :: Bit #51)
+	 ; (def_state_EQ_0___d3 :: Bool) = primEQ def_state___d2 (0 :: Bit #2)
 	 ; (def_gcd_RDY_start_AND_state_EQ_0___d4 :: Bool) = def_gcd_RDY_start____d1 && def_state_EQ_0___d3
 	 ; (act1 :: (Bool, MOD_sysMethods, ())) =
-	       meth_start_sysMethods def_b__h532 def_b__h543 (inst_gcd__sysTb state0)
+	       meth_start_sysMethods def_c1__h532 def_c2__h543 (inst_gcd__sysTb state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysTb) = state0 { inst_gcd__sysTb = snd3 act1 }
-	 ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h612 (inst_c1__sysTb state1)
+	 ; (act2 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_add___d7 (inst_c1__sysTb state1)
 	 ; (guard2 :: Bool) = guard1 && (fst3 act2)
 	 ; (state2 :: MOD_sysTb) = state1 { inst_c1__sysTb = snd3 act2 }
-	 ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h703 (inst_c2__sysTb state2)
+	 ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_add___d8 (inst_c2__sysTb state2)
 	 ; (guard3 :: Bool) = guard2 && (fst3 act3)
 	 ; (state3 :: MOD_sysTb) = state2 { inst_c2__sysTb = snd3 act3 }
 	 ; (act4 :: (Bool, MOD_RegN #2, ())) = meth_write_RegN (1 :: Bit #2) (inst_state__sysTb state3)
@@ -58,18 +58,19 @@ rule_RL_r0_sysTb =
 rule_RL_r1_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ());
 rule_RL_r1_sysTb =
     (\ (state0 :: MOD_sysTb) ->
-     let { (def_b__h532 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0)
-	 ; (def_b__h543 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0)
-	 ; (def_x__h979 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0)
-	 ; (def_b__h612 :: Bit #51) = noinline_add def_b__h532 (3 :: Bit #51)
-	 ; (def_b__h703 :: Bit #51) = noinline_add def_b__h543 (2 :: Bit #51)
-	 ; (def_state_EQ_1___d9 :: Bool) = primEQ def_x__h979 (1 :: Bit #2)
+     let { (def_c1__h532 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0)
+	 ; (def_c2__h543 :: Bit #51) = meth_read_RegN (inst_c2__sysTb state0)
+	 ; (def_state___d2 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0)
+	 ; (def_add___d7 :: Bit #51) = noinline_add def_c1__h532 (3 :: Bit #51)
+	 ; (def_add___d8 :: Bit #51) = noinline_add def_c2__h543 (2 :: Bit #51)
+	 ; (def_state_EQ_1___d9 :: Bool) = primEQ def_state___d2 (1 :: Bit #2)
 	 ; (act1 :: (Bool, MOD_sysMethods, Bit #51)) =
-	       meth_start_and_result_sysMethods def_b__h532 def_b__h543 (inst_gcd__sysTb state0)
+	       meth_start_and_result_sysMethods def_c1__h532 def_c2__h543 (inst_gcd__sysTb state0)
 	 ; (guard1 :: Bool) = fst3 act1
 	 ; (state1 :: MOD_sysTb) = state0 { inst_gcd__sysTb = snd3 act1 }
-	 ; (def_b__h854 :: Bit #51) = thd act1
-	 ; (def_gcd_start_and_result_0_PLUS_1___d11 :: Bit #51) = primAdd def_b__h854 (1 :: Bit #51)
+	 ; (def_gcd_start_and_result___d10 :: Bit #51) = thd act1
+	 ; (def_gcd_start_and_result_0_PLUS_1___d11 :: Bit #51) =
+	       primAdd def_gcd_start_and_result___d10 (1 :: Bit #51)
 	 ; (act2 :: (Bool, MOD_RegN #51, ())) =
 	       meth_write_RegN
 		   (primConcat
@@ -81,10 +82,10 @@ rule_RL_r1_sysTb =
 		   (inst_rg__sysTb state1)
 	 ; (guard2 :: Bool) = guard1 && (fst3 act2)
 	 ; (state2 :: MOD_sysTb) = state1 { inst_rg__sysTb = snd3 act2 }
-	 ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h612 (inst_c1__sysTb state2)
+	 ; (act3 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_add___d7 (inst_c1__sysTb state2)
 	 ; (guard3 :: Bool) = guard2 && (fst3 act3)
 	 ; (state3 :: MOD_sysTb) = state2 { inst_c1__sysTb = snd3 act3 }
-	 ; (act4 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_b__h703 (inst_c2__sysTb state3)
+	 ; (act4 :: (Bool, MOD_RegN #51, ())) = meth_write_RegN def_add___d8 (inst_c2__sysTb state3)
 	 ; (guard4 :: Bool) = guard3 && (fst3 act4)
 	 ; (state4 :: MOD_sysTb) = state3 { inst_c2__sysTb = snd3 act4 }
 	 ; (act5 :: (Bool, MOD_RegN #2, ())) = meth_write_RegN (2 :: Bit #2) (inst_state__sysTb state4)
@@ -96,11 +97,11 @@ rule_RL_r1_sysTb =
 rule_RL_r2_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ());
 rule_RL_r2_sysTb =
     (\ (state0 :: MOD_sysTb) ->
-     let { (def_x__h979 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0)
+     let { (def_state___d2 :: Bit #2) = meth_read_RegN (inst_state__sysTb state0)
 	 ; (def_gcd_RDY_result____d14 :: Bool) = meth_RDY_result_sysMethods (inst_gcd__sysTb state0)
 	 ; (def_gcd_result____d17 :: Bit #51) = meth_result_sysMethods (inst_gcd__sysTb state0)
 	 ; (def_gcd_result__7_PLUS_1___d18 :: Bit #51) = primAdd def_gcd_result____d17 (1 :: Bit #51)
-	 ; (def_state_EQ_2___d15 :: Bool) = primEQ def_x__h979 (2 :: Bit #2)
+	 ; (def_state_EQ_2___d15 :: Bool) = primEQ def_state___d2 (2 :: Bit #2)
 	 ; (def_gcd_RDY_result__4_AND_state_EQ_2_5___d16 :: Bool) =
 	       def_gcd_RDY_result____d14 && def_state_EQ_2___d15
 	 ; (act1 :: (Bool, MOD_RegN #51, ())) =
@@ -120,9 +121,9 @@ rule_RL_r2_sysTb =
 rule_RL_exit_sysTb :: MOD_sysTb -> (Bool, MOD_sysTb, ());
 rule_RL_exit_sysTb =
     (\ (state0 :: MOD_sysTb) ->
-     let { (def_b__h532 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0)
-	 ; (def_c1_ULE_100___d21 :: Bool) = primULE def_b__h532 (100 :: Bit #51)
-	 ; (def_v__h1058 :: Bit #64) = (primAny :: Bit #64)
+     let { (def_c1__h532 :: Bit #51) = meth_read_RegN (inst_c1__sysTb state0)
+	 ; (def_c1_ULE_100___d21 :: Bool) = primULE def_c1__h532 (100 :: Bit #51)
+	 ; (def_TASK_time___d23 :: Bit #64) = (primAny :: Bit #64)
 	 }
      in mktuple (not def_c1_ULE_100___d21) state0 ());
 
diff --git a/testsuite/bsc.misc/method_conditions/method_conditions.exp b/testsuite/bsc.misc/method_conditions/method_conditions.exp
index 7ca995fa6..96f27a637 100644
--- a/testsuite/bsc.misc/method_conditions/method_conditions.exp
+++ b/testsuite/bsc.misc/method_conditions/method_conditions.exp
@@ -167,11 +167,11 @@ check_positions sysMethodConds_CaseCond
 # This example CSE's the COND condition into the signals for the design
 # (case-stmt reconstruction is doing CSE that needs to be aware of non-CSE props)
 #
-compile_verilog_pass MethodConds_VecSelCond.bsv {} $opts
+# The output differs when aggressive conditions is off, so ensure it is on
+compile_verilog_pass MethodConds_VecSelCond.bsv {} "$opts -aggressive-conditions"
 # Check that the conditions are in the Verilog
 find_regexp sysMethodConds_VecSelCond.v \
-    {reg CASE\_idx\_0\_cs\_0\_1\_cs\_1\_2\_cs\_2\_3\_DONTCARE\_DONTCARE\_\_q1\,
-      COND\_RL\_r\_s\_am1\_1\;}
+    {reg COND\_RL\_r\_s\_am1\_1, SEL\_ARR\_cs\_0\_cs\_1\_cs\_2\_idx\_\_\_d6\;}
 # XXX This code could be shared with with "CASE_...__q1" rather than inlined
 # XXX (what happens is that it's inlined, but VeriQuirks lifts it back up,
 # XXX so maybe VeriQuirks needs to do a better job of CSE in the lifted exprs)
diff --git a/testsuite/bsc.misc/sal/CTX_sysDynArrSelWithImplCond.sal.expected b/testsuite/bsc.misc/sal/CTX_sysDynArrSelWithImplCond.sal.expected
index 8b538c4c9..94cbd8ac4 100644
--- a/testsuite/bsc.misc/sal/CTX_sysDynArrSelWithImplCond.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysDynArrSelWithImplCond.sal.expected
@@ -19,31 +19,31 @@ BEGIN
      #) ;
   
   meth_get (state0 : STATE) : Bit{8}!T =
-    LET def__element_first__h710 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_3)
-    IN LET def__element_first__h704 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_2)
-    IN LET def__element_first__h698 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_1)
-    IN LET def__element_first__h692 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_0)
-    IN LET def_x__h558 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_idx)
+    LET def_fs_0_first____d1 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_0)
+    IN LET def_idx___d6 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_idx)
+    IN LET def_fs_1_first____d2 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_1)
+    IN LET def_fs_2_first____d3 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_2)
+    IN LET def_fs_3_first____d4 : Bit{8}!T = CTX_FIFO2{8}!meth_first(state0.inst_fs_3)
     IN LET def_ARR_fs_0_first_fs_1_first_fs_2_first_fs_3_first___d5 : ARRAY [0..3] OF Bit{8}!T =
-	     [[ i : [0..3] ] def__element_first__h692 ] WITH [1] := def__element_first__h698
-	     WITH [2] := def__element_first__h704
-	     WITH [3] := def__element_first__h710
+	     [[ i : [0..3] ] def_fs_0_first____d1 ] WITH [1] := def_fs_1_first____d2
+	     WITH [2] := def_fs_2_first____d3
+	     WITH [3] := def_fs_3_first____d4
     IN ArrayPrim1{Bit{8}!T;4,2}!arrSelect(def_ARR_fs_0_first_fs_1_first_fs_2_first_fs_3_first___d5,
-					  def_x__h558) ;
+					  def_idx___d6) ;
   
   meth_RDY_get (state0 : STATE) : BOOLEAN =
-    LET def_x__h558 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_idx)
+    LET def_idx___d6 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_idx)
     IN LET def_fs_0_i_notEmpty____d7 : Bit{1}!T = CTX_FIFO2{8}!meth_i_notEmpty(state0.inst_fs_0)
     IN LET def_fs_1_i_notEmpty____d8 : Bit{1}!T = CTX_FIFO2{8}!meth_i_notEmpty(state0.inst_fs_1)
     IN LET def_fs_2_i_notEmpty____d9 : Bit{1}!T = CTX_FIFO2{8}!meth_i_notEmpty(state0.inst_fs_2)
     IN LET def_fs_3_i_notEmpty____d10 : Bit{1}!T = CTX_FIFO2{8}!meth_i_notEmpty(state0.inst_fs_3)
-    IN Prim!bitToBool(IF Prim1{2}!primEQ(def_x__h558, Bit{2}!mkConst(0))
+    IN Prim!bitToBool(IF Prim1{2}!primEQ(def_idx___d6, Bit{2}!mkConst(0))
 			THEN def_fs_0_i_notEmpty____d7
-			ELSE IF Prim1{2}!primEQ(def_x__h558, Bit{2}!mkConst(1))
+			ELSE IF Prim1{2}!primEQ(def_idx___d6, Bit{2}!mkConst(1))
 			       THEN def_fs_1_i_notEmpty____d8
-			       ELSE IF Prim1{2}!primEQ(def_x__h558, Bit{2}!mkConst(2))
+			       ELSE IF Prim1{2}!primEQ(def_idx___d6, Bit{2}!mkConst(2))
 				      THEN def_fs_2_i_notEmpty____d9
-				      ELSE IF Prim1{2}!primEQ(def_x__h558, Bit{2}!mkConst(3))
+				      ELSE IF Prim1{2}!primEQ(def_idx___d6, Bit{2}!mkConst(3))
 					     THEN def_fs_3_i_notEmpty____d10
 					     ELSE Bit{1}!mkConst(1)
 					   ENDIF
diff --git a/testsuite/bsc.misc/sal/CTX_sysExtract.sal.expected b/testsuite/bsc.misc/sal/CTX_sysExtract.sal.expected
index 41ef92793..1e39047b1 100644
--- a/testsuite/bsc.misc/sal/CTX_sysExtract.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysExtract.sal.expected
@@ -21,19 +21,19 @@ BEGIN
      #) ;
   
   rule_RL_do_static (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_src1__h124 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_src1)
+    LET def_src1__h109 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_src1)
     IN LET act1 : [ CTX_RegUN{8}!STATE, Unit!T ] =
-	     CTX_RegUN{8}!meth_write(Prim2{12,8}!primExtract(def_src1__h124), state0.inst_snk1)
+	     CTX_RegUN{8}!meth_write(Prim2{12,8}!primExtract(def_src1__h109), state0.inst_snk1)
     IN LET state1 : STATE = state0 WITH .inst_snk1 := act1.1
     IN ( TRUE, state1 ) ;
   
   rule_RL_do_dynamic (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_i2__h246 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_lo_idx)
-    IN LET def_i1__h245 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_hi_idx)
-    IN LET def_bs__h244 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_src2)
-    IN LET def_x__h238 : Bit{8}!T = Prim2{12,8}!primExtract(def_bs__h244)
+    LET def_i2__h226 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_lo_idx)
+    IN LET def_i1__h225 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_hi_idx)
+    IN LET def_bs__h224 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_src2)
+    IN LET def_src2_BITS_hi_idx_TO_lo_idx___d6 : Bit{8}!T = Prim2{12,8}!primExtract(def_bs__h224)
     IN LET act1 : [ CTX_RegUN{8}!STATE, Unit!T ] =
-	     CTX_RegUN{8}!meth_write(def_x__h238, state0.inst_snk2)
+	     CTX_RegUN{8}!meth_write(def_src2_BITS_hi_idx_TO_lo_idx___d6, state0.inst_snk2)
     IN LET state1 : STATE = state0 WITH .inst_snk2 := act1.1
     IN ( TRUE, state1 ) ;
   
diff --git a/testsuite/bsc.misc/sal/CTX_sysMergeIf.sal.expected b/testsuite/bsc.misc/sal/CTX_sysMergeIf.sal.expected
index f0d45c6ae..f82d9fa37 100644
--- a/testsuite/bsc.misc/sal/CTX_sysMergeIf.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysMergeIf.sal.expected
@@ -27,14 +27,14 @@ BEGIN
      #) ;
   
   rule_RL_r1 (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_s1__h527 : Bit{1}!T = CTX_RegN{1}!meth_read(state0.inst_s1)
+    LET def_s1__h472 : Bit{1}!T = CTX_RegN{1}!meth_read(state0.inst_s1)
     IN LET def_f3_i_notFull____d1 : Bit{1}!T = CTX_FIFO2{17}!meth_i_notFull(state0.inst_f3)
-    IN LET def_f2_i_notFull____d2 : Bit{1}!T = CTX_FIFO2{17}!meth_i_notFull(state0.inst_f2)
-    IN LET def_f1_i_notFull____d3 : Bit{1}!T = CTX_FIFO2{17}!meth_i_notFull(state0.inst_f1)
-    IN LET def_f2_i_notFull_AND_f1_i_notFull___d4 : BOOLEAN =
-	     Prim!bitToBool(def_f2_i_notFull____d2) AND Prim!bitToBool(def_f1_i_notFull____d3)
-    IN LET def_f3_i_notFull_AND_f2_i_notFull_AND_f1_i_notFull___d5 : BOOLEAN =
-	     Prim!bitToBool(def_f3_i_notFull____d1) AND def_f2_i_notFull_AND_f1_i_notFull___d4
+    IN LET def_f2_i_notFull____d3 : Bit{1}!T = CTX_FIFO2{17}!meth_i_notFull(state0.inst_f2)
+    IN LET def_f1_i_notFull____d4 : Bit{1}!T = CTX_FIFO2{17}!meth_i_notFull(state0.inst_f1)
+    IN LET def_IF_s1_THEN_f2_i_notFull_ELSE_f1_i_notFull___d5 : Bit{1}!T =
+	     IF Prim!bitToBool(def_s1__h472) THEN def_f2_i_notFull____d3 ELSE def_f1_i_notFull____d4 ENDIF
+    IN LET def_f3_i_notFull_AND_IF_s1_THEN_f2_i_notFull_ELSE__ETC___d6 : BOOLEAN =
+	     Prim!bitToBool(def_f3_i_notFull____d1) AND Prim!bitToBool(def_IF_s1_THEN_f2_i_notFull_ELSE_f1_i_notFull___d5)
     IN LET act1 : [ CTX_RegN{17}!STATE, Unit!T ] =
 	     CTX_RegN{17}!meth_write(Bit{17}!mkConst(5), state0.inst_a)
     IN LET state1 : STATE = state0 WITH .inst_a := act1.1
@@ -47,15 +47,15 @@ BEGIN
     IN LET act4 : [ CTX_RegN{17}!STATE, Unit!T ] =
 	     CTX_RegN{17}!meth_write(Bit{17}!mkConst(7), state0.inst_c)
     IN LET state4 : STATE = state0 WITH .inst_c := act4.1
-    IN LET state5 : STATE = IF Prim!bitToBool(def_s1__h527) THEN state3 ELSE state4 ENDIF
+    IN LET state5 : STATE = IF Prim!bitToBool(def_s1__h472) THEN state3 ELSE state4 ENDIF
     IN LET act6 : [ CTX_FIFO2{17}!STATE, Unit!T ] =
 	     CTX_FIFO2{17}!meth_enq(Bit{17}!mkConst(22), state5.inst_f3)
     IN LET state6 : STATE = state5 WITH .inst_f3 := act6.1
     IN LET act7 : [ CTX_FIFO2{17}!STATE, Unit!T ] =
 	     CTX_FIFO2{17}!meth_enq(Bit{17}!mkConst(12), state6.inst_f1)
     IN LET state7 : STATE =
-	     IF (NOT Prim!bitToBool(def_s1__h527)) THEN state6 WITH .inst_f1 := act7.1 ELSE state6 ENDIF
-    IN ( def_f3_i_notFull_AND_f2_i_notFull_AND_f1_i_notFull___d5, state7 ) ;
+	     IF (NOT Prim!bitToBool(def_s1__h472)) THEN state6 WITH .inst_f1 := act7.1 ELSE state6 ENDIF
+    IN ( def_f3_i_notFull_AND_IF_s1_THEN_f2_i_notFull_ELSE__ETC___d6, state7 ) ;
   
 END
 
diff --git a/testsuite/bsc.misc/sal/CTX_sysMethod_Split.sal.expected b/testsuite/bsc.misc/sal/CTX_sysMethod_Split.sal.expected
index 6dd2225e3..19aa12d46 100644
--- a/testsuite/bsc.misc/sal/CTX_sysMethod_Split.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysMethod_Split.sal.expected
@@ -17,29 +17,33 @@ BEGIN
   meth_m (state0 : STATE) : [ STATE, Bit{8}!T ] =
     LET def_c__h144 : Bit{1}!T = CTX_RegUN{1}!meth_read(state0.inst_c)
     IN IF Prim!bitToBool(def_c__h144)
-	 THEN LET def_x__h224 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg1)
-	      IN LET def_x__h251 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg2)
-	      IN LET def_x__h174 : Bit{8}!T = Prim1{8}!primAdd(def_x__h224, Bit{8}!mkConst(3))
-	      IN LET def_x__h249 : Bit{8}!T = Prim1{8}!primAdd(def_x__h251, Bit{8}!mkConst(2))
-	      IN LET def_x__h222 : Bit{8}!T = Prim1{8}!primAdd(def_x__h224, Bit{8}!mkConst(1))
-	      IN LET act1 : [ CTX_RegUN{8}!STATE, Unit!T ] = CTX_RegUN{8}!meth_write(def_x__h174, state0.inst_rg1)
+	 THEN LET def_rg2___d5 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg2)
+	      IN LET def_rg1___d2 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg1)
+	      IN LET def_rg1_PLUS_3___d3 : Bit{8}!T = Prim1{8}!primAdd(def_rg1___d2, Bit{8}!mkConst(3))
+	      IN LET def_rg1_PLUS_1___d7 : Bit{8}!T = Prim1{8}!primAdd(def_rg1___d2, Bit{8}!mkConst(1))
+	      IN LET def_rg2_PLUS_2___d8 : Bit{8}!T = Prim1{8}!primAdd(def_rg2___d5, Bit{8}!mkConst(2))
+	      IN LET act1 : [ CTX_RegUN{8}!STATE, Unit!T ] =
+		       CTX_RegUN{8}!meth_write(def_rg1_PLUS_3___d3, state0.inst_rg1)
 	      IN LET state1 : STATE = state0 WITH .inst_rg1 := act1.1
-	      IN ( state1, IF Prim!bitToBool(def_c__h144) THEN def_x__h222 ELSE def_x__h249 ENDIF )
+	      IN ( state1,
+		   IF Prim!bitToBool(def_c__h144) THEN def_rg1_PLUS_1___d7 ELSE def_rg2_PLUS_2___d8 ENDIF )
 	 ELSE IF (NOT Prim!bitToBool(def_c__h144))
-		THEN LET def_x__h224 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg1)
-		     IN LET def_x__h251 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg2)
-		     IN LET def_x__h226 : Bit{8}!T = Prim1{8}!primAdd(def_x__h251, Bit{8}!mkConst(4))
-		     IN LET def_x__h249 : Bit{8}!T = Prim1{8}!primAdd(def_x__h251, Bit{8}!mkConst(2))
-		     IN LET def_x__h222 : Bit{8}!T = Prim1{8}!primAdd(def_x__h224, Bit{8}!mkConst(1))
+		THEN LET def_rg2___d5 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg2)
+		     IN LET def_rg1___d2 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg1)
+		     IN LET def_rg2_PLUS_4___d6 : Bit{8}!T = Prim1{8}!primAdd(def_rg2___d5, Bit{8}!mkConst(4))
+		     IN LET def_rg1_PLUS_1___d7 : Bit{8}!T = Prim1{8}!primAdd(def_rg1___d2, Bit{8}!mkConst(1))
+		     IN LET def_rg2_PLUS_2___d8 : Bit{8}!T = Prim1{8}!primAdd(def_rg2___d5, Bit{8}!mkConst(2))
 		     IN LET act1 : [ CTX_RegUN{8}!STATE, Unit!T ] =
-			      CTX_RegUN{8}!meth_write(def_x__h226, state0.inst_rg2)
+			      CTX_RegUN{8}!meth_write(def_rg2_PLUS_4___d6, state0.inst_rg2)
 		     IN LET state1 : STATE = state0 WITH .inst_rg2 := act1.1
-		     IN ( state1, IF Prim!bitToBool(def_c__h144) THEN def_x__h222 ELSE def_x__h249 ENDIF )
-		ELSE LET def_x__h224 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg1)
-		     IN LET def_x__h251 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg2)
-		     IN LET def_x__h249 : Bit{8}!T = Prim1{8}!primAdd(def_x__h251, Bit{8}!mkConst(2))
-		     IN LET def_x__h222 : Bit{8}!T = Prim1{8}!primAdd(def_x__h224, Bit{8}!mkConst(1))
-		     IN ( state0, IF Prim!bitToBool(def_c__h144) THEN def_x__h222 ELSE def_x__h249 ENDIF )
+		     IN ( state1,
+			  IF Prim!bitToBool(def_c__h144) THEN def_rg1_PLUS_1___d7 ELSE def_rg2_PLUS_2___d8 ENDIF )
+		ELSE LET def_rg2___d5 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg2)
+		     IN LET def_rg1___d2 : Bit{8}!T = CTX_RegUN{8}!meth_read(state0.inst_rg1)
+		     IN LET def_rg1_PLUS_1___d7 : Bit{8}!T = Prim1{8}!primAdd(def_rg1___d2, Bit{8}!mkConst(1))
+		     IN LET def_rg2_PLUS_2___d8 : Bit{8}!T = Prim1{8}!primAdd(def_rg2___d5, Bit{8}!mkConst(2))
+		     IN ( state0,
+			  IF Prim!bitToBool(def_c__h144) THEN def_rg1_PLUS_1___d7 ELSE def_rg2_PLUS_2___d8 ENDIF )
 	      ENDIF
        ENDIF ;
   
diff --git a/testsuite/bsc.misc/sal/CTX_sysMethods.sal.expected b/testsuite/bsc.misc/sal/CTX_sysMethods.sal.expected
index 92efa1180..ca4cef4de 100644
--- a/testsuite/bsc.misc/sal/CTX_sysMethods.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysMethods.sal.expected
@@ -13,25 +13,25 @@ BEGIN
      #) ;
   
   rule_RL_flip (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_b__h117 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
-    IN LET def_b__h116 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x)
-    IN LET def_y_EQ_0___d5 : BOOLEAN = Prim1{51}!primEQ(def_b__h117, Bit{51}!mkConst(0))
-    IN LET def_x_ULE_y___d3 : BOOLEAN = Prim1{51}!primULE(def_b__h116, def_b__h117)
+    LET def_y__h360 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
+    IN LET def_x__h359 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x)
+    IN LET def_y_EQ_0___d5 : BOOLEAN = Prim1{51}!primEQ(def_y__h360, Bit{51}!mkConst(0))
+    IN LET def_x_ULE_y___d3 : BOOLEAN = Prim1{51}!primULE(def_x__h359, def_y__h360)
     IN LET def_NOT_x_ULE_y_AND_NOT_y_EQ_0___d7 : BOOLEAN =
 	     (NOT def_x_ULE_y___d3) AND (NOT def_y_EQ_0___d5)
-    IN LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h117, state0.inst_x)
+    IN LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_y__h360, state0.inst_x)
     IN LET state1 : STATE = state0 WITH .inst_x := act1.1
-    IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h116, state1.inst_y)
+    IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_x__h359, state1.inst_y)
     IN LET state2 : STATE = state1 WITH .inst_y := act2.1
     IN ( def_NOT_x_ULE_y_AND_NOT_y_EQ_0___d7, state2 ) ;
   
   rule_RL_sub (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_b__h117 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
-    IN LET def_b__h116 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x)
-    IN LET def_y_EQ_0___d5 : BOOLEAN = Prim1{51}!primEQ(def_b__h117, Bit{51}!mkConst(0))
-    IN LET def_x_ULE_y___d3 : BOOLEAN = Prim1{51}!primULE(def_b__h116, def_b__h117)
+    LET def_y__h360 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
+    IN LET def_x__h359 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x)
+    IN LET def_y_EQ_0___d5 : BOOLEAN = Prim1{51}!primEQ(def_y__h360, Bit{51}!mkConst(0))
+    IN LET def_x_ULE_y___d3 : BOOLEAN = Prim1{51}!primULE(def_x__h359, def_y__h360)
     IN LET def_x_ULE_y_AND_NOT_y_EQ_0___d8 : BOOLEAN = def_x_ULE_y___d3 AND (NOT def_y_EQ_0___d5)
-    IN LET def_y_MINUS_x___d9 : Bit{51}!T = Prim1{51}!primSub(def_b__h117, def_b__h116)
+    IN LET def_y_MINUS_x___d9 : Bit{51}!T = Prim1{51}!primSub(def_y__h360, def_x__h359)
     IN LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] =
 	     CTX_RegN{51}!meth_write(def_y_MINUS_x___d9, state0.inst_y)
     IN LET state1 : STATE = state0 WITH .inst_y := act1.1
@@ -40,8 +40,8 @@ BEGIN
   meth_result (state0 : STATE) : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x) ;
   
   meth_RDY_result (state0 : STATE) : BOOLEAN =
-    LET def_b__h117 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
-    IN Prim1{51}!primEQ(def_b__h117, Bit{51}!mkConst(0)) ;
+    LET def_y__h360 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
+    IN Prim1{51}!primEQ(def_y__h360, Bit{51}!mkConst(0)) ;
   
   meth_start (arg_start_num1, arg_start_num2 : Bit{51}!T, state0 : STATE) : [ STATE, Unit!T ] =
     LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(arg_start_num1, state0.inst_x)
@@ -52,19 +52,19 @@ BEGIN
     IN ( state2, Unit!unit ) ;
   
   meth_RDY_start (state0 : STATE) : BOOLEAN =
-    LET def_b__h117 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
-    IN Prim1{51}!primEQ(def_b__h117, Bit{51}!mkConst(0)) ;
+    LET def_y__h360 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_y)
+    IN Prim1{51}!primEQ(def_y__h360, Bit{51}!mkConst(0)) ;
   
   meth_start_and_result (arg_start_and_result_num1, arg_start_and_result_num2 : Bit{51}!T,
 			 state0 : STATE) : [ STATE, Bit{51}!T ] =
-    LET def_b__h116 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x)
+    LET def_x__h359 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_x)
     IN LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] =
 	     CTX_RegN{51}!meth_write(arg_start_and_result_num1, state0.inst_x)
     IN LET state1 : STATE = state0 WITH .inst_x := act1.1
     IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] =
 	     CTX_RegN{51}!meth_write(arg_start_and_result_num2, state1.inst_y)
     IN LET state2 : STATE = state1 WITH .inst_y := act2.1
-    IN ( state2, def_b__h116 ) ;
+    IN ( state2, def_x__h359 ) ;
   
   meth_RDY_start_and_result (state0 : STATE) : BOOLEAN = TRUE ;
   
diff --git a/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected b/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected
index 0f84a344a..28dc4488b 100644
--- a/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysMultiArityConcat.sal.expected
@@ -17,12 +17,12 @@ BEGIN
      #) ;
   
   rule_RL_d (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def__read__h37 : Bit{3}!T = CTX_RegUN{3}!meth_read(state0.inst_src1)
-    IN LET def__read__h87 : Bit{5}!T = CTX_RegUN{5}!meth_read(state0.inst_src3)
-    IN LET def__read__h62 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_src2)
+    LET def_src1___d1 : Bit{3}!T = CTX_RegUN{3}!meth_read(state0.inst_src1)
+    IN LET def_src2___d2 : Bit{4}!T = CTX_RegUN{4}!meth_read(state0.inst_src2)
+    IN LET def_src3___d3 : Bit{5}!T = CTX_RegUN{5}!meth_read(state0.inst_src3)
     IN LET act1 : [ CTX_RegUN{12}!STATE, Unit!T ] =
-	     CTX_RegUN{12}!meth_write(Prim2{3,9}!primConcat(def__read__h37,
-							    Prim2{4,5}!primConcat(def__read__h62, def__read__h87)),
+	     CTX_RegUN{12}!meth_write(Prim2{3,9}!primConcat(def_src1___d1,
+							    Prim2{4,5}!primConcat(def_src2___d2, def_src3___d3)),
 				      state0.inst_snk)
     IN LET state1 : STATE = state0 WITH .inst_snk := act1.1
     IN ( TRUE, state1 ) ;
diff --git a/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected b/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected
index 5d740e7c3..9518420ed 100644
--- a/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysStructs.sal.expected
@@ -29,17 +29,18 @@ BEGIN
      #) ;
   
   rule_RL_add_em (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_x__h549 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_a)
-    IN LET def_x__h557 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_b)
-    IN LET def_x__h541 : Bit{9}!T = Prim1{9}!primAdd(def_x__h549, def_x__h557)
-    IN LET def_x__h529 : Bit{9}!T = Prim1{9}!primAdd(def_x__h541, Bit{9}!mkConst(4))
-    IN LET def_s__h482 : Bit{1}!T = CTX_RegN{1}!meth_read(state0.inst_s)
-    IN LET act1 : [ CTX_RegN{9}!STATE, Unit!T ] = CTX_RegN{9}!meth_write(def_x__h529, state0.inst_a)
+    LET def_a__h504 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_a)
+    IN LET def_b__h512 : Bit{9}!T = CTX_RegN{9}!meth_read(state0.inst_b)
+    IN LET def_s__h444 : Bit{1}!T = CTX_RegN{1}!meth_read(state0.inst_s)
+    IN LET def_a_PLUS_b___d4 : Bit{9}!T = Prim1{9}!primAdd(def_a__h504, def_b__h512)
+    IN LET def_a_PLUS_b_PLUS_4___d5 : Bit{9}!T = Prim1{9}!primAdd(def_a_PLUS_b___d4, Bit{9}!mkConst(4))
+    IN LET act1 : [ CTX_RegN{9}!STATE, Unit!T ] =
+	     CTX_RegN{9}!meth_write(def_a_PLUS_b_PLUS_4___d5, state0.inst_a)
     IN LET state1 : STATE = state0 WITH .inst_a := act1.1
     IN LET act2 : [ CTX_RegN{1}!STATE, Unit!T ] =
 	     CTX_RegN{1}!meth_write(Bit{1}!mkConst(0), state1.inst_s)
     IN LET state2 : STATE = state1 WITH .inst_s := act2.1
-    IN ( Prim!bitToBool(def_s__h482), state2 ) ;
+    IN ( Prim!bitToBool(def_s__h444), state2 ) ;
   
   rule_RL_tss (state0 : STATE) : [ BOOLEAN, STATE ] =
     LET def_t1___d8 : Bit{12}!T = CTX_RegUN{12}!meth_read(state0.inst_t1)
diff --git a/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected b/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected
index 09a411442..a2f5775ea 100644
--- a/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected
+++ b/testsuite/bsc.misc/sal/CTX_sysTb.sal.expected
@@ -19,21 +19,21 @@ BEGIN
      #) ;
   
   rule_RL_r0 (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_b__h532 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1)
-    IN LET def_b__h543 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2)
-    IN LET def_x__h979 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state)
-    IN LET def_b__h612 : Bit{51}!T = CTX_module_add!fn(def_b__h532, Bit{51}!mkConst(3))
-    IN LET def_b__h703 : Bit{51}!T = CTX_module_add!fn(def_b__h543, Bit{51}!mkConst(2))
+    LET def_c1__h532 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1)
+    IN LET def_c2__h543 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2)
+    IN LET def_state___d2 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state)
     IN LET def_gcd_RDY_start____d1 : BOOLEAN = CTX_sysMethods!meth_RDY_start(state0.inst_gcd)
-    IN LET def_state_EQ_0___d3 : BOOLEAN = Prim1{2}!primEQ(def_x__h979, Bit{2}!mkConst(0))
+    IN LET def_add___d7 : Bit{51}!T = CTX_module_add!fn(def_c1__h532, Bit{51}!mkConst(3))
+    IN LET def_add___d8 : Bit{51}!T = CTX_module_add!fn(def_c2__h543, Bit{51}!mkConst(2))
+    IN LET def_state_EQ_0___d3 : BOOLEAN = Prim1{2}!primEQ(def_state___d2, Bit{2}!mkConst(0))
     IN LET def_gcd_RDY_start_AND_state_EQ_0___d4 : BOOLEAN =
 	     def_gcd_RDY_start____d1 AND def_state_EQ_0___d3
     IN LET act1 : [ CTX_sysMethods!STATE, Unit!T ] =
-	     CTX_sysMethods!meth_start(def_b__h532, def_b__h543, state0.inst_gcd)
+	     CTX_sysMethods!meth_start(def_c1__h532, def_c2__h543, state0.inst_gcd)
     IN LET state1 : STATE = state0 WITH .inst_gcd := act1.1
-    IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h612, state1.inst_c1)
+    IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_add___d7, state1.inst_c1)
     IN LET state2 : STATE = state1 WITH .inst_c1 := act2.1
-    IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h703, state2.inst_c2)
+    IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_add___d8, state2.inst_c2)
     IN LET state3 : STATE = state2 WITH .inst_c2 := act3.1
     IN LET act4 : [ CTX_RegN{2}!STATE, Unit!T ] =
 	     CTX_RegN{2}!meth_write(Bit{2}!mkConst(1), state3.inst_state)
@@ -41,26 +41,26 @@ BEGIN
     IN ( def_gcd_RDY_start_AND_state_EQ_0___d4, state4 ) ;
   
   rule_RL_r1 (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_b__h532 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1)
-    IN LET def_b__h543 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2)
-    IN LET def_x__h979 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state)
-    IN LET def_b__h612 : Bit{51}!T = CTX_module_add!fn(def_b__h532, Bit{51}!mkConst(3))
-    IN LET def_b__h703 : Bit{51}!T = CTX_module_add!fn(def_b__h543, Bit{51}!mkConst(2))
-    IN LET def_state_EQ_1___d9 : BOOLEAN = Prim1{2}!primEQ(def_x__h979, Bit{2}!mkConst(1))
+    LET def_c1__h532 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1)
+    IN LET def_c2__h543 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c2)
+    IN LET def_state___d2 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state)
+    IN LET def_add___d7 : Bit{51}!T = CTX_module_add!fn(def_c1__h532, Bit{51}!mkConst(3))
+    IN LET def_add___d8 : Bit{51}!T = CTX_module_add!fn(def_c2__h543, Bit{51}!mkConst(2))
+    IN LET def_state_EQ_1___d9 : BOOLEAN = Prim1{2}!primEQ(def_state___d2, Bit{2}!mkConst(1))
     IN LET act1 : [ CTX_sysMethods!STATE, Bit{51}!T ] =
-	     CTX_sysMethods!meth_start_and_result(def_b__h532, def_b__h543, state0.inst_gcd)
+	     CTX_sysMethods!meth_start_and_result(def_c1__h532, def_c2__h543, state0.inst_gcd)
     IN LET state1 : STATE = state0 WITH .inst_gcd := act1.1
-    IN LET def_b__h854 : Bit{51}!T = act1.2
+    IN LET def_gcd_start_and_result___d10 : Bit{51}!T = act1.2
     IN LET def_gcd_start_and_result_0_PLUS_1___d11 : Bit{51}!T =
-	     Prim1{51}!primAdd(def_b__h854, Bit{51}!mkConst(1))
+	     Prim1{51}!primAdd(def_gcd_start_and_result___d10, Bit{51}!mkConst(1))
     IN LET act2 : [ CTX_RegN{51}!STATE, Unit!T ] =
 	     CTX_RegN{51}!meth_write(Prim2{50,1}!primConcat(Prim2{51,50}!primExtract(def_gcd_start_and_result_0_PLUS_1___d11),
 							    Bit{1}!mkConst(0)),
 				     state1.inst_rg)
     IN LET state2 : STATE = state1 WITH .inst_rg := act2.1
-    IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h612, state2.inst_c1)
+    IN LET act3 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_add___d7, state2.inst_c1)
     IN LET state3 : STATE = state2 WITH .inst_c1 := act3.1
-    IN LET act4 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_b__h703, state3.inst_c2)
+    IN LET act4 : [ CTX_RegN{51}!STATE, Unit!T ] = CTX_RegN{51}!meth_write(def_add___d8, state3.inst_c2)
     IN LET state4 : STATE = state3 WITH .inst_c2 := act4.1
     IN LET act5 : [ CTX_RegN{2}!STATE, Unit!T ] =
 	     CTX_RegN{2}!meth_write(Bit{2}!mkConst(2), state4.inst_state)
@@ -68,12 +68,12 @@ BEGIN
     IN ( def_state_EQ_1___d9, state5 ) ;
   
   rule_RL_r2 (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_x__h979 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state)
+    LET def_state___d2 : Bit{2}!T = CTX_RegN{2}!meth_read(state0.inst_state)
     IN LET def_gcd_RDY_result____d14 : BOOLEAN = CTX_sysMethods!meth_RDY_result(state0.inst_gcd)
     IN LET def_gcd_result____d17 : Bit{51}!T = CTX_sysMethods!meth_result(state0.inst_gcd)
     IN LET def_gcd_result__7_PLUS_1___d18 : Bit{51}!T =
 	     Prim1{51}!primAdd(def_gcd_result____d17, Bit{51}!mkConst(1))
-    IN LET def_state_EQ_2___d15 : BOOLEAN = Prim1{2}!primEQ(def_x__h979, Bit{2}!mkConst(2))
+    IN LET def_state_EQ_2___d15 : BOOLEAN = Prim1{2}!primEQ(def_state___d2, Bit{2}!mkConst(2))
     IN LET def_gcd_RDY_result__4_AND_state_EQ_2_5___d16 : BOOLEAN =
 	     def_gcd_RDY_result____d14 AND def_state_EQ_2___d15
     IN LET act1 : [ CTX_RegN{51}!STATE, Unit!T ] =
@@ -87,9 +87,9 @@ BEGIN
     IN ( def_gcd_RDY_result__4_AND_state_EQ_2_5___d16, state2 ) ;
   
   rule_RL_exit (state0 : STATE) : [ BOOLEAN, STATE ] =
-    LET def_b__h532 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1)
-    IN LET def_c1_ULE_100___d21 : BOOLEAN = Prim1{51}!primULE(def_b__h532, Bit{51}!mkConst(100))
-    IN LET def_v__h1058 : Bit{64}!T = Bit{64}!undef
+    LET def_c1__h532 : Bit{51}!T = CTX_RegN{51}!meth_read(state0.inst_c1)
+    IN LET def_c1_ULE_100___d21 : BOOLEAN = Prim1{51}!primULE(def_c1__h532, Bit{51}!mkConst(100))
+    IN LET def_TASK_time___d23 : Bit{64}!T = Bit{64}!undef
     IN ( NOT def_c1_ULE_100___d21, state0 ) ;
   
 END
diff --git a/testsuite/bsc.misc/sal/sal.exp b/testsuite/bsc.misc/sal/sal.exp
index c9423922b..35a25eef5 100644
--- a/testsuite/bsc.misc/sal/sal.exp
+++ b/testsuite/bsc.misc/sal/sal.exp
@@ -73,7 +73,8 @@ compare_file_filter_ids CTX_sysStructs.sal
 # Test for lifting if condition in action
 if { $vtest == 1 } {
 
-compile_verilog_pass MergeIf.bsv {} $opts
+# Output differs if aggr-conds is on, so ensure it is
+compile_verilog_pass MergeIf.bsv {} "$opts -aggressive-conditions"
 compare_file_filter_ids CTX_sysMergeIf.sal
 
 # XXX Nothing merges here yet, because the defs are not inlined
diff --git a/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected
index 6250eeeb0..3c77e5980 100644
--- a/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected
+++ b/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected
@@ -17,7 +17,7 @@ arg info  [clockarg default_clock;, resetarg default_reset;]
 -- APackage resets
 [(0, { wire:  RST_N })]
 -- AP state elements
-rg :: ABSTRACT:  PreludeBSV._PreludeBSV.VRWire110 = RWire
+rg :: ABSTRACT:  PreludeBSV._PreludeBSV.VRWire103 = RWire
 						    (VModInfo
 						     RWire
 						     clock clk();
@@ -43,14 +43,14 @@ rg :: ABSTRACT:  PreludeBSV._PreludeBSV.VRWire110 = RWire
 							       WVAL -> Prelude.Bit 8
 -- AP local definitions
 rg_whas_CONCAT_rg_wget___d3 :: Bit 9;
-rg_whas_CONCAT_rg_wget___d3  = rg_whas____d1 ++ wget__h65;
+rg_whas_CONCAT_rg_wget___d3  = rg_whas____d1 ++ rg_wget____d2;
 -- IdProp rg_whas_CONCAT_rg_wget___d3[IdP_from_rhs]
 rg_whas____d1 :: Bit 1;
 rg_whas____d1  = rg.whas;
 -- IdProp rg_whas____d1[IdP_from_rhs]
-wget__h65 :: Bit 8;
-wget__h65  = rg.wget;
--- IdProp wget__h65[IdP_keep]
+rg_wget____d2 :: Bit 8;
+rg_wget____d2  = rg.wget;
+-- IdProp rg_wget____d2[IdP_from_rhs]
 -- AP rules
 rule RL_r "r":
  when 1'd1
diff --git a/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected
index 7fbca1f3a..5d88c8eb0 100644
--- a/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected
+++ b/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected
@@ -85,14 +85,14 @@ i :: ABSTRACT:  MethodActionValue.Ifc­ = mkMethodActionValue_Sub
 					 port types=m -> Prelude.Bit 8
 -- AP local definitions
 i_m_PLUS_8___d2 :: Bit 8;
-i_m_PLUS_8___d2  = v__h90 + 8'd8;
+i_m_PLUS_8___d2  = i_m___d1 + 8'd8;
 -- IdProp i_m_PLUS_8___d2[IdP_from_rhs]
 i_m_MINUS_1___d3 :: Bit 8;
-i_m_MINUS_1___d3  = v__h90 - 8'd1;
+i_m_MINUS_1___d3  = i_m___d1 - 8'd1;
 -- IdProp i_m_MINUS_1___d3[IdP_from_rhs]
-v__h90 :: Bit 8;
-v__h90  = i.m;
--- IdProp v__h90[IdP_keep]
+i_m___d1 :: Bit 8;
+i_m___d1  = i.m;
+-- IdProp i_m___d1[IdP_from_rhs]
 -- AP rules
 rule RL_r "r":
  when 1'd1
diff --git a/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected
index b65caf951..d6a707799 100644
--- a/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected
+++ b/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected
@@ -34,14 +34,14 @@ rg :: ABSTRACT:  Prelude.VReg = RegUN
 					   Q_OUT -> Prelude.Bit 8
 -- AP local definitions
 rg_PLUS_8___d2 :: Bit 8;
-rg_PLUS_8___d2  = x__h140 + 8'd8;
+rg_PLUS_8___d2  = rg___d1 + 8'd8;
 -- IdProp rg_PLUS_8___d2[IdP_from_rhs]
 rg_MINUS_1___d3 :: Bit 8;
-rg_MINUS_1___d3  = x__h140 - 8'd1;
+rg_MINUS_1___d3  = rg___d1 - 8'd1;
 -- IdProp rg_MINUS_1___d3[IdP_from_rhs]
-x__h140 :: Bit 8;
-x__h140  = rg.read;
--- IdProp x__h140[IdP_keep]
+rg___d1 :: Bit 8;
+rg___d1  = rg.read;
+-- IdProp rg___d1[IdP_from_rhs]
 -- AP rules
 rule RL_r "r":
  when 1'd1
diff --git a/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected
index 1daa65fd9..d0c8e5f88 100644
--- a/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected
+++ b/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected
@@ -19,11 +19,11 @@ arg info  [clockarg default_clock;, resetarg default_reset;]
 -- AP state elements
 -- AP local definitions
 fnNoInline_PLUS_8___d2 :: Bit 8;
-fnNoInline_PLUS_8___d2  = x__h46 + 8'd8;
+fnNoInline_PLUS_8___d2  = fnNoInline___d1 + 8'd8;
 -- IdProp fnNoInline_PLUS_8___d2[IdP_from_rhs]
-x__h46 :: Bit 8;
-x__h46  = NoInline.fnNoInline 8'd0;
--- IdProp x__h46[IdP_keep]
+fnNoInline___d1 :: Bit 8;
+fnNoInline___d1  = NoInline.fnNoInline 8'd0;
+-- IdProp fnNoInline___d1[IdP_from_rhs]
 -- AP rules
 rule RL_r "r":
  when 1'd1
diff --git a/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected
index ec3ea8d73..dc109698b 100644
--- a/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected
+++ b/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected
@@ -19,14 +19,14 @@ arg info  [clockarg default_clock;, resetarg default_reset;]
 -- AP state elements
 -- AP local definitions
 TASK_sformatAV_PLUS_8___d3 :: Bit 32;
-TASK_sformatAV_PLUS_8___d3  = v__h42 + 32'd8;
+TASK_sformatAV_PLUS_8___d3  = TASK_sformatAV___d2 + 32'd8;
 -- IdProp TASK_sformatAV_PLUS_8___d3[IdP_from_rhs]
 signed_0___d1 :: Bit 32;
 signed_0___d1  = Prelude.$signed 32'd0;
 -- IdProp signed_0___d1[IdP_from_rhs,IdP_signed]
-v__h42 :: Bit 32;
-v__h42  = Prelude.$sformatAV#0;
--- IdProp v__h42[IdP_keep]
+TASK_sformatAV___d2 :: Bit 32;
+TASK_sformatAV___d2  = Prelude.$sformatAV#0;
+-- IdProp TASK_sformatAV___d2[IdP_from_rhs]
 -- AP rules
 rule RL_r "r":
  when 1'd1
diff --git a/testsuite/bsc.options/bsc.path_dup_bdir.out.expected b/testsuite/bsc.options/bsc.path_dup_bdir.out.expected
index aa1668308..d20798314 100644
--- a/testsuite/bsc.options/bsc.path_dup_bdir.out.expected
+++ b/testsuite/bsc.options/bsc.path_dup_bdir.out.expected
@@ -10,6 +10,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -p foo::foo:bar:foo:baz:baz:foo -bdir bar
 
 Flags:
+    -aggressive-conditions
     -bdir bar
     -i BLUESPECDIR
     -lift
diff --git a/testsuite/bsc.options/bsc.path_dup_no_bdir.out.expected b/testsuite/bsc.options/bsc.path_dup_no_bdir.out.expected
index 19c627289..04231ad6b 100644
--- a/testsuite/bsc.options/bsc.path_dup_no_bdir.out.expected
+++ b/testsuite/bsc.options/bsc.path_dup_no_bdir.out.expected
@@ -7,6 +7,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -p foo::foo:bar:foo:baz:baz:foo
 
 Flags:
+    -aggressive-conditions
     -i BLUESPECDIR
     -lift
     -o a.out
diff --git a/testsuite/bsc.options/bsc.path_nonidentical_dup_no_bdir.out.expected b/testsuite/bsc.options/bsc.path_nonidentical_dup_no_bdir.out.expected
index 6294bb9bb..446d4f82e 100644
--- a/testsuite/bsc.options/bsc.path_nonidentical_dup_no_bdir.out.expected
+++ b/testsuite/bsc.options/bsc.path_nonidentical_dup_no_bdir.out.expected
@@ -14,6 +14,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -p foo:foo/:./foo:bar/../foo:./foo/../foo:baz:./baz:./baz/bar/../../foo/
 
 Flags:
+     -aggressive-conditions
      -i   BLUESPECDIR
      -lift
      -o   a.out
diff --git a/testsuite/bsc.options/bsc.print-flags-raw.out.expected b/testsuite/bsc.options/bsc.print-flags-raw.out.expected
index 06f45808f..7dbd6e4f8 100644
--- a/testsuite/bsc.options/bsc.print-flags-raw.out.expected
+++ b/testsuite/bsc.options/bsc.print-flags-raw.out.expected
@@ -1,5 +1,5 @@
 Flags {
-	aggImpConds = False,
+	aggImpConds = True,
 	allowIncoherentMatches = False,
 	backend = Nothing,
 	bdir = Nothing,
@@ -92,7 +92,7 @@ Flags {
 	rstGate = False,
 	ruleNameCheck = True,
 	satBackend = SAT_Yices,
-	schedConds = False,
+	schedConds = True,
 	schedDOT = False,
 	schedQueries = [],
 	showCSyntax = False,
diff --git a/testsuite/bsc.options/bsc.print-flags.out.expected b/testsuite/bsc.options/bsc.print-flags.out.expected
index a21973114..b3652b51a 100644
--- a/testsuite/bsc.options/bsc.print-flags.out.expected
+++ b/testsuite/bsc.options/bsc.print-flags.out.expected
@@ -2,6 +2,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags
 
 Flags:
+    -aggressive-conditions
     -i BLUESPECDIR
     -lift
     -o a.out
diff --git a/testsuite/bsc.options/bsc.simdir_invalid_no_backend.out.expected b/testsuite/bsc.options/bsc.simdir_invalid_no_backend.out.expected
index f430e6aa4..9e17d3215 100644
--- a/testsuite/bsc.options/bsc.simdir_invalid_no_backend.out.expected
+++ b/testsuite/bsc.options/bsc.simdir_invalid_no_backend.out.expected
@@ -8,6 +8,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -simdir INVALID
 
 Flags:
+     -aggressive-conditions
      -i   BLUESPECDIR
      -lift
      -o   a.out
diff --git a/testsuite/bsc.options/bsc.test_bsc_option.out.expected b/testsuite/bsc.options/bsc.test_bsc_option.out.expected
index 4e1f67298..22293024f 100644
--- a/testsuite/bsc.options/bsc.test_bsc_option.out.expected
+++ b/testsuite/bsc.options/bsc.test_bsc_option.out.expected
@@ -2,6 +2,7 @@ Invoking command line:
 bsc -print-flags -vsearch foo -steps 12345678 -i BLUESPECDIR
 
 Flags:
+    -aggressive-conditions
     -i BLUESPECDIR
     -lift
     -o a.out
diff --git a/testsuite/bsc.options/bsc.vdir_invalid_no_backend.out.expected b/testsuite/bsc.options/bsc.vdir_invalid_no_backend.out.expected
index 58c6e49f8..47930c254 100644
--- a/testsuite/bsc.options/bsc.vdir_invalid_no_backend.out.expected
+++ b/testsuite/bsc.options/bsc.vdir_invalid_no_backend.out.expected
@@ -15,6 +15,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -vdir INVALID
 
 Flags:
+     -aggressive-conditions
      -i   BLUESPECDIR
      -lift
      -o   a.out
diff --git a/testsuite/bsc.options/messages/flag-test.out.expected b/testsuite/bsc.options/messages/flag-test.out.expected
index 34eb39d87..ce16bd9db 100644
--- a/testsuite/bsc.options/messages/flag-test.out.expected
+++ b/testsuite/bsc.options/messages/flag-test.out.expected
@@ -2,6 +2,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -suppress-warnings G0001:G0002 -suppress-warnings NONE -suppress-warnings T1234:T0001 -suppress-warnings T0002:T0003:T0001
 
 Flags:
+     -aggressive-conditions
      -i   BLUESPECDIR
      -lift
      -o   a.out
diff --git a/testsuite/bsc.options/messages/flag-test2.out.expected b/testsuite/bsc.options/messages/flag-test2.out.expected
index 41ff7e194..40840915e 100644
--- a/testsuite/bsc.options/messages/flag-test2.out.expected
+++ b/testsuite/bsc.options/messages/flag-test2.out.expected
@@ -2,6 +2,7 @@ Invoking command line:
 bsc -i BLUESPECDIR -print-flags -suppress-warnings G0001:G0002 -suppress-warnings ALL -suppress-warnings T1234:T0001 -suppress-warnings T0002:T0003:T0001
 
 Flags:
+     -aggressive-conditions
      -i   BLUESPECDIR
      -lift
      -o   a.out
diff --git a/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected
index 0d1b8badb..10afe74c4 100644
--- a/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected
@@ -10,11 +10,11 @@ order: [a1_T, a2, a1_F]
 === resources (SplitIfMeth mkSplitIfMeth):
 [(b.read, [(b.read, 1)]),
  (x.read, [(x.read, 1)]),
- (x.write, [(x.write b__h252, 1)]),
+ (x.write, [(x.write y__h201, 1)]),
  (y.read, [(y.read, 1)]),
- (y.write, [(y.write b__h272, 1)]),
+ (y.write, [(y.write z__h225, 1)]),
  (z.read, [(z.read, 1)]),
- (z.write, [(z.write b__h253, 1)])]
+ (z.write, [(z.write x__h202, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected
index 60c6983d7..c2842b2ee 100644
--- a/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected
@@ -45,7 +45,7 @@ order: [RL_rA, RL_rB]
 -----
 
 === resources (AVArgUse_C sysAVArgUse_C):
-[(dut.m, [(dut.m b__h178 32'd1, 1), (dut.m 32'd5 b__h178, 1)]),
+[(dut.m, [(dut.m r1__h275 32'd1, 1), (dut.m 32'd5 r1__h275, 1)]),
  (r1.read, [(r1.read, 1)]),
  (r1.write, [(r1.write r1_PLUS_1___d4, 1)])]
 
diff --git a/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected
index 433516b26..61a1e33fd 100644
--- a/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected
@@ -43,7 +43,7 @@ order: [RL_rB, RL_rA]
 -----
 
 === resources (AVArgUse_SBR sysAVArgUse_SBR):
-[(dut.m, [(dut.m b__h178 32'd1, 1), (dut.m 32'd5 b__h178, 1)]),
+[(dut.m, [(dut.m r1__h275 32'd1, 1), (dut.m 32'd5 r1__h275, 1)]),
  (r1.read, [(r1.read, 1)]),
  (r1.write, [(r1.write r1_PLUS_1___d4, 1)])]
 
diff --git a/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected
index 2e071bfc5..ea28ea8ff 100644
--- a/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected
@@ -11,10 +11,10 @@ order: [RL_init, RL_gcd_flip, RL_gcd_stop, RL_gcd_sub]
 [(gcd_done.read, [(gcd_done.read, 1)]),
  (gcd_done.write, [(gcd_done.write 1'd0, 1), (gcd_done.write 1'd1, 1)]),
  (gcd_x.read, [(gcd_x.read, 1)]),
- (gcd_x.write, [(gcd_x.write b__h187, 1), (gcd_x.write 64'd105198692842362, 1)]),
+ (gcd_x.write, [(gcd_x.write gcd_y__h125, 1), (gcd_x.write 64'd105198692842362, 1)]),
  (gcd_y.read, [(gcd_y.read, 1)]),
  (gcd_y.write,
-  [(gcd_y.write b__h186, 1),
+  [(gcd_y.write gcd_x__h124, 1),
    (gcd_y.write gcd_y_MINUS_gcd_x___d18, 1),
    (gcd_y.write 64'd445628814024366, 1)]),
  (started.read, [(started.read, 1)]),
diff --git a/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected
index d04cd62bd..ae108bd42 100644
--- a/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected
@@ -12,7 +12,7 @@ order: [RL_do_enq, RL_do_otherwise]
  (f.i_notFull, [(f.i_notFull, 1)]),
  (f.notFull, [(f.notFull, 1)]),
  (rg.read, [(rg.read, 1)]),
- (rg.write, [(rg.write x__h234, 1), (rg.write x__h261, 1)])]
+ (rg.write, [(rg.write rg_MINUS_1___d3, 1), (rg.write rg_PLUS_1___d6, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected
index 2121d514e..d53e8bee5 100644
--- a/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected
@@ -14,9 +14,9 @@ order: [RL_do1, RL_do2]
 === resources (SharedPortsRegFile sysSharedPortsRegFile):
 [(idx1.read, [(idx1.read, 1)]),
  (idx2.read, [(idx2.read, 1)]),
- (rf.sub, [(rf.sub i__h411, 2), (rf.sub i__h443, 1)]),
+ (rf.sub, [(rf.sub idx2___d5, 2), (rf.sub idx1___d1, 1)]),
  (rg.read, [(rg.read, 1)]),
- (rg.write, [(rg.write x__h418, 1), (rg.write x__h449, 1)])]
+ (rg.write, [(rg.write rg_MINUS_1___d4, 1), (rg.write rg_PLUS_1___d8, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected
index 7dbabc005..884e11b02 100644
--- a/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected
@@ -25,14 +25,14 @@ order: [RL_enq,
  (bypass_fifo_result.wget, [(bypass_fifo_result.wget, 1)]),
  (bypass_fifo_result.whas, [(bypass_fifo_result.whas, 1)]),
  (bypass_fifo_result.wset,
-  [(if bypass_fifo_the_fifof_i_notEmpty_OR_bypass_fif_ETC___d20 then
-      bypass_fifo_result.wset IF_bypass_fifo_the_fifof_i_notEmpty_THEN_bypas_ETC___d6,
+  [(if bypass_fifo_the_fifof_i_notEmpty_OR_bypass_fif_ETC___d3 then
+      bypass_fifo_result.wset IF_bypass_fifo_the_fifof_i_notEmpty_THEN_bypas_ETC___d7,
     1)]),
  (bypass_fifo_the_fifof.deq,
-  [(if bypass_fifo_deqw_whas_AND_bypass_fifo_the_fifo_ETC___d11 then bypass_fifo_the_fifof.deq, 1)]),
+  [(if bypass_fifo_deqw_whas_AND_bypass_fifo_the_fifo_ETC___d12 then bypass_fifo_the_fifof.deq, 1)]),
  (bypass_fifo_the_fifof.enq,
-  [(if bypass_fifo_enqw_whas_AND_bypass_fifo_the_fifo_ETC___d10 then
-      bypass_fifo_the_fifof.enq x__h367,
+  [(if bypass_fifo_enqw_whas_AND_bypass_fifo_the_fifo_ETC___d11 then
+      bypass_fifo_the_fifof.enq IF_bypass_fifo_enqw_whas_THEN_bypass_fifo_enqw_ETC___d6,
     1)]),
  (bypass_fifo_the_fifof.first, [(bypass_fifo_the_fifof.first, 1)]),
  (bypass_fifo_the_fifof.i_notEmpty, [(bypass_fifo_the_fifof.i_notEmpty, 1)]),
diff --git a/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected
index c48e48fc1..d65f4f084 100644
--- a/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected
@@ -50,7 +50,7 @@ order: [handleIBufferRequest,
     1)]),
  (cacheAddrQueue_caq_the_fifof.enq,
   [(if cacheAddrQueue_caq_enqw_whas_AND_cacheAddrQueu_ETC___d11 then
-      cacheAddrQueue_caq_the_fifof.enq x__h315,
+      cacheAddrQueue_caq_the_fifof.enq IF_cacheAddrQueue_caq_enqw_whas_THEN_cacheAddr_ETC___d6,
     1)]),
  (cacheAddrQueue_caq_the_fifof.first, [(cacheAddrQueue_caq_the_fifof.first, 1)]),
  (cacheAddrQueue_caq_the_fifof.i_notEmpty, [(cacheAddrQueue_caq_the_fifof.i_notEmpty, 1)]),
@@ -60,7 +60,7 @@ order: [handleIBufferRequest,
  (responseQueue_rq_enqw.wget, [(responseQueue_rq_enqw.wget, 1)]),
  (responseQueue_rq_enqw.whas, [(responseQueue_rq_enqw.whas, 1)]),
  (responseQueue_rq_enqw.wset,
-  [(responseQueue_rq_enqw.wset handleCacheResponse_data_BITS_32_TO_0_8_CONCAT_ETC___d30, 1)]),
+  [(responseQueue_rq_enqw.wset handleCacheResponse_data_BITS_32_TO_0_7_CONCAT_ETC___d29, 1)]),
  (responseQueue_rq_result.wget, [(responseQueue_rq_result.wget, 1)]),
  (responseQueue_rq_result.whas, [(responseQueue_rq_result.whas, 1)]),
  (responseQueue_rq_result.wset,
diff --git a/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected
index b10da78c1..f618bb271 100644
--- a/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [b, RL_c, RL_d, a]
 
 === resources (SeqEx1 mkSeqEx1):
 [(r1.read, [(r1.read, 1)]),
- (r1.write, [(r1.write x__h291, 1), (r1.write x__h335, 1)]),
+ (r1.write, [(r1.write r1_PLUS_2___d3, 1), (r1.write r1_PLUS_1___d4, 1)]),
  (r2.write, [(r2.write rw2_whas____d5, 1)]),
  (rw1.whas, [(rw1.whas, 1)]),
  (rw1.wset, [(rw1.wset 1'd1, 1)]),
diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected
index c9d7e3503..3c7e41916 100644
--- a/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [RL_Good]
 
 === resources (ResourceOneRuleOK sysResourceOneRuleOK):
 [(a.sub, [(a.sub 8'd0, 5), (a.sub 8'd1, 4), (a.sub 8'd2, 3), (a.sub 8'd3, 2), (a.sub 8'd4, 1)]),
- (r.write, [(r.write x__h283, 1)])]
+ (r.write, [(r.write a_sub_0_PLUS_a_sub_1_PLUS_a_sub_2_PLUS_a_sub_3_ETC___d9, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected
index 7f6df25c6..fcc72811b 100644
--- a/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected
@@ -19,7 +19,7 @@ order: [RL_A, RL_B]
 
 === resources (ResourcePredicates sysResourcePredicates):
 [(a.sub, [(a.sub 2'd0, 2), (a.sub 2'd2, 1)]),
- (a.upd, [(a.upd 2'd1 x__h252, 1), (a.upd 2'd3 x__h269, 1)])]
+ (a.upd, [(a.upd 2'd1 a_sub_0___d1, 1), (a.upd 2'd3 a_sub_2___d3, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected
index bae099650..db5d3f24a 100644
--- a/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected
@@ -153,14 +153,14 @@ order: [RL_contend,
 -----
 
 === resources (ResourceTwoRulesCond sysResourceTwoRulesCond):
-[(dest_0.write, [(if do_write_0__h1695 then dest_0.write x__h1930, 1)]),
- (dest_1.write, [(if do_write_1__h1996 then dest_1.write x__h2007, 1)]),
- (dest_2.write, [(if do_write_2__h2071 then dest_2.write x__h2082, 1)]),
- (dest_3.write, [(if do_write_3__h2146 then dest_3.write x__h2157, 1)]),
- (dest_4.write, [(if do_write_4__h2221 then dest_4.write x__h2232, 1)]),
- (dest_5.write, [(if do_write_5__h2296 then dest_5.write x__h2307, 1)]),
- (dest_6.write, [(if do_write_6__h2371 then dest_6.write x__h2382, 1)]),
- (dest_7.write, [(if do_write_7__h2446 then dest_7.write x__h2457, 1)]),
+[(dest_0.write, [(if do_write_0__h1196 then dest_0.write rf_sub_0___d2, 1)]),
+ (dest_1.write, [(if do_write_1__h1465 then dest_1.write rf_sub_1___d4, 1)]),
+ (dest_2.write, [(if do_write_2__h1516 then dest_2.write rf_sub_2___d6, 1)]),
+ (dest_3.write, [(if do_write_3__h1567 then dest_3.write rf_sub_3___d8, 1)]),
+ (dest_4.write, [(if do_write_4__h1618 then dest_4.write rf_sub_4___d10, 1)]),
+ (dest_5.write, [(if do_write_5__h1669 then dest_5.write rf_sub_5___d12, 1)]),
+ (dest_6.write, [(if do_write_6__h1720 then dest_6.write rf_sub_6___d14, 1)]),
+ (dest_7.write, [(if do_write_7__h1771 then dest_7.write rf_sub_7___d16, 1)]),
  (do_write_0.read, [(do_write_0.read, 1)]),
  (do_write_1.read, [(do_write_1.read, 1)]),
  (do_write_2.read, [(do_write_2.read, 1)]),
diff --git a/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected
index 88c4e8df6..f126d0694 100644
--- a/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected
@@ -20,7 +20,8 @@ order: [RL_aa, RL_ab, RL_bb]
  (ua.read, [(ua.read, 1)]),
  (ub.read, [(ub.read, 1)]),
  (uc.read, [(uc.read, 1)]),
- (uc.write, [(uc.write x__h320, 1), (uc.write x__h404, 1), (uc.write x__h419, 1)])]
+ (uc.write,
+  [(uc.write uc_PLUS_1___d7, 1), (uc.write uc_PLUS_2___d15, 1), (uc.write uc_PLUS_3___d18, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected
index 547e91d42..154e90c08 100644
--- a/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected
@@ -20,7 +20,8 @@ order: [RL_aa, RL_ab, RL_bb]
  (ua.read, [(ua.read, 1)]),
  (ub.read, [(ub.read, 1)]),
  (uc.read, [(uc.read, 1)]),
- (uc.write, [(uc.write x__h320, 1), (uc.write x__h404, 1), (uc.write x__h419, 1)])]
+ (uc.write,
+  [(uc.write uc_PLUS_1___d7, 1), (uc.write uc_PLUS_2___d15, 1), (uc.write uc_PLUS_3___d18, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected
index fdae0fe97..2dbe03a13 100644
--- a/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected
@@ -18,7 +18,8 @@ order: [RL_aa, RL_ab, RL_bb]
 === resources (TruncateTest_sat-stp sysAddTest):
 [(ua.read, [(ua.read, 1)]),
  (uc.read, [(uc.read, 1)]),
- (uc.write, [(uc.write x__h185, 1), (uc.write x__h272, 1), (uc.write x__h283, 1)])]
+ (uc.write,
+  [(uc.write uc_PLUS_1___d5, 1), (uc.write uc_PLUS_2___d7, 1), (uc.write uc_PLUS_3___d10, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected
index 9cb82d7c3..e5dfb0a64 100644
--- a/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected
@@ -18,7 +18,8 @@ order: [RL_aa, RL_ab, RL_bb]
 === resources (TruncateTest_sat-yices sysAddTest):
 [(ua.read, [(ua.read, 1)]),
  (uc.read, [(uc.read, 1)]),
- (uc.write, [(uc.write x__h185, 1), (uc.write x__h272, 1), (uc.write x__h283, 1)])]
+ (uc.write,
+  [(uc.write uc_PLUS_1___d5, 1), (uc.write uc_PLUS_2___d7, 1), (uc.write uc_PLUS_3___d10, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected
index a878e91d5..639a11066 100644
--- a/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected
@@ -14,7 +14,8 @@ order: [RL_aa, RL_ab, RL_bb]
 === resources (Word64Test_sat-stp sysWord64Test):
 [(ua.read, [(ua.read, 1)]),
  (uc.read, [(uc.read, 1)]),
- (uc.write, [(uc.write x__h248, 1), (uc.write x__h307, 1), (uc.write x__h373, 1)])]
+ (uc.write,
+  [(uc.write uc_PLUS_1___d5, 1), (uc.write uc_PLUS_2___d7, 1), (uc.write uc_PLUS_3___d13, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected
index 12e4eb985..cda56dc2c 100644
--- a/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected
@@ -14,7 +14,8 @@ order: [RL_aa, RL_ab, RL_bb]
 === resources (Word64Test_sat-yices sysWord64Test):
 [(ua.read, [(ua.read, 1)]),
  (uc.read, [(uc.read, 1)]),
- (uc.write, [(uc.write x__h248, 1), (uc.write x__h307, 1), (uc.write x__h373, 1)])]
+ (uc.write,
+  [(uc.write uc_PLUS_1___d5, 1), (uc.write uc_PLUS_2___d7, 1), (uc.write uc_PLUS_3___d13, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected
index 58ccc52b8..88d52717d 100644
--- a/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected
@@ -14,10 +14,12 @@ order: [readCount, RL_driveCounter, incCount]
 
 === resources (SBRCount mkSBRCount):
 [(counter.read, [(counter.read, 1)]),
- (counter.write, [(counter.write x__h240, 1), (counter.write 26'd0, 1)]),
+ (counter.write,
+  [(counter.write IF_counterWire_whas_THEN_counterWire_wget_ELSE_ETC___d5, 1),
+   (counter.write 26'd0, 1)]),
  (counterWire.wget, [(counterWire.wget, 1)]),
  (counterWire.whas, [(counterWire.whas, 1)]),
- (counterWire.wset, [(counterWire.wset new_value__h188, 1)])]
+ (counterWire.wset, [(counterWire.wset counter___d1, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected
index b8526def3..04873723f 100644
--- a/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected
@@ -43,12 +43,12 @@ order: [clearGo, first, deq, RL_doit, RL_doit_1, RL_doit_2, RL_doit_3, RL_doit_4
  (gos_5.write, [(if setGo_index_EQ_5___d31 then gos_5.write 1'd1, 1)]),
  (outf.deq, [(outf.deq, 1)]),
  (outf.enq,
-  [(outf.enq b__h1799, 1),
-   (outf.enq b__h1902, 1),
-   (outf.enq b__h2002, 1),
-   (outf.enq b__h2102, 1),
-   (outf.enq b__h2202, 1),
-   (outf.enq b__h2302, 1)]),
+  [(outf.enq cntrs_0__h1647, 1),
+   (outf.enq cntrs_1__h1740, 1),
+   (outf.enq cntrs_2__h1815, 1),
+   (outf.enq cntrs_3__h1890, 1),
+   (outf.enq cntrs_4__h1965, 1),
+   (outf.enq cntrs_5__h2040, 1)]),
  (outf.first, [(outf.first, 1)]),
  (outf.i_notEmpty, [(outf.i_notEmpty, 1)]),
  (outf.i_notFull, [(outf.i_notFull, 1)])]
diff --git a/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected
index a84cd6573..8072a0b2a 100644
--- a/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected
@@ -63,12 +63,12 @@ order: [clearGo, first, deq, RL_doit, RL_doit_1, RL_doit_2, RL_doit_3, RL_doit_4
  (gos_5.write, [(if setGo_index_EQ_5___d31 then gos_5.write 1'd1, 1)]),
  (outf.deq, [(outf.deq, 1)]),
  (outf.enq,
-  [(outf.enq b__h1711, 1),
-   (outf.enq b__h1814, 1),
-   (outf.enq b__h1914, 1),
-   (outf.enq b__h2014, 1),
-   (outf.enq b__h2114, 1),
-   (outf.enq b__h2214, 1)]),
+  [(outf.enq cntrs_0__h1575, 1),
+   (outf.enq cntrs_1__h1668, 1),
+   (outf.enq cntrs_2__h1743, 1),
+   (outf.enq cntrs_3__h1818, 1),
+   (outf.enq cntrs_4__h1893, 1),
+   (outf.enq cntrs_5__h1968, 1)]),
  (outf.first, [(outf.first, 1)]),
  (outf.i_notEmpty, [(outf.i_notEmpty, 1)]),
  (outf.i_notFull, [(outf.i_notFull, 1)])]
diff --git a/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected
index 0a365265f..84098fb0a 100644
--- a/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected
@@ -43,12 +43,12 @@ order: [clearGo, first, deq, RL_doit, RL_doit_1, RL_doit_2, RL_doit_3, RL_doit_4
  (gos_5.write, [(if setGo_index_EQ_5___d31 then gos_5.write 1'd1, 1)]),
  (outf.deq, [(outf.deq, 1)]),
  (outf.enq,
-  [(outf.enq b__h1705, 1),
-   (outf.enq b__h1810, 1),
-   (outf.enq b__h1912, 1),
-   (outf.enq b__h2014, 1),
-   (outf.enq b__h2116, 1),
-   (outf.enq b__h2216, 1)]),
+  [(outf.enq cntrs_0__h1569, 1),
+   (outf.enq cntrs_1__h1664, 1),
+   (outf.enq cntrs_2__h1741, 1),
+   (outf.enq cntrs_3__h1818, 1),
+   (outf.enq cntrs_4__h1895, 1),
+   (outf.enq cntrs_5__h1970, 1)]),
  (outf.first, [(outf.first, 1)]),
  (outf.i_notEmpty, [(outf.i_notEmpty, 1)]),
  (outf.i_notFull, [(outf.i_notFull, 1)])]
diff --git a/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected
index 15a5404ad..92bed1693 100644
--- a/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected
@@ -56,12 +56,12 @@ order: [clearGo,
  (gos_5.write, [(if setGo_index_EQ_5___d34 then gos_5.write 1'd1, 1)]),
  (outf.deq, [(outf.deq, 1)]),
  (outf.enq,
-  [(outf.enq b__h1847, 1),
-   (outf.enq b__h1945, 1),
-   (outf.enq b__h2041, 1),
-   (outf.enq b__h2141, 1),
-   (outf.enq b__h2241, 1),
-   (outf.enq b__h2341, 1)]),
+  [(outf.enq cntrs_0__h1694, 1),
+   (outf.enq cntrs_1__h1783, 1),
+   (outf.enq cntrs_2__h1854, 1),
+   (outf.enq cntrs_3__h1929, 1),
+   (outf.enq cntrs_4__h2004, 1),
+   (outf.enq cntrs_5__h2079, 1)]),
  (outf.first, [(outf.first, 1)]),
  (outf.i_notEmpty, [(outf.i_notEmpty, 1)]),
  (outf.i_notFull, [(outf.i_notFull, 1)]),
diff --git a/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected
index 25da95807..a30991b40 100644
--- a/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected
@@ -90,12 +90,12 @@ order: [clearGo,
  (gos_5.write, [(if setGo_index_EQ_5___d36 then gos_5.write 1'd1, 1)]),
  (outf.deq, [(outf.deq, 1)]),
  (outf.enq,
-  [(outf.enq b__h1910, 1),
-   (outf.enq b__h2008, 1),
-   (outf.enq b__h2104, 1),
-   (outf.enq b__h2200, 1),
-   (outf.enq b__h2300, 1),
-   (outf.enq b__h2400, 1)]),
+  [(outf.enq cntrs_0__h1751, 1),
+   (outf.enq cntrs_1__h1840, 1),
+   (outf.enq cntrs_2__h1911, 1),
+   (outf.enq cntrs_3__h1982, 1),
+   (outf.enq cntrs_4__h2057, 1),
+   (outf.enq cntrs_5__h2132, 1)]),
  (outf.first, [(outf.first, 1)]),
  (outf.i_notEmpty, [(outf.i_notEmpty, 1)]),
  (outf.i_notFull, [(outf.i_notFull, 1)]),
diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected
index 6745b9dc1..177997c82 100644
--- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [RL_test_rule_1, RL_test_rule_2]
 
 === resources (DescendingUrgencyAttribute1 sysDescendingUrgencyAttribute1):
 [(count_r.read, [(count_r.read, 1)]),
- (count_r.write, [(count_r.write x__h100, 1), (count_r.write x__h127, 1)])]
+ (count_r.write, [(count_r.write count_r_PLUS_2___d2, 1), (count_r.write count_r_PLUS_3___d3, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected
index e865c0317..f6c385fab 100644
--- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [RL_test_rule_1, RL_test_rule_2]
 
 === resources (DescendingUrgencyAttribute2 sysDescendingUrgencyAttribute2):
 [(count_r.read, [(count_r.read, 1)]),
- (count_r.write, [(count_r.write x__h100, 1), (count_r.write x__h127, 1)])]
+ (count_r.write, [(count_r.write count_r_PLUS_2___d2, 1), (count_r.write count_r_PLUS_3___d3, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected
index 18283f759..24e72bf6a 100644
--- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected
@@ -12,11 +12,11 @@ order: [RL_test_rule_2, RL_test_rule_2_1, RL_test_rule_2_2, RL_test_rule_1]
 
 === resources (DescendingUrgencyAttributeForLoop sysDescendingUrgencyAttributeForLoop):
 [(count.read, [(count.read, 1)]),
- (count.write, [(count.write x__h489, 1), (count.write x__h268, 1)]),
+ (count.write, [(count.write count_PLUS_2___d2, 1), (count.write count_PLUS_1___d7, 1)]),
  (count_1.read, [(count_1.read, 1)]),
- (count_1.write, [(count_1.write x__h553, 1), (count_1.write x__h328, 1)]),
+ (count_1.write, [(count_1.write count_1_PLUS_2___d4, 1), (count_1.write count_1_PLUS_1___d8, 1)]),
  (count_2.read, [(count_2.read, 1)]),
- (count_2.write, [(count_2.write x__h598, 1), (count_2.write x__h394, 1)])]
+ (count_2.write, [(count_2.write count_2_PLUS_2___d6, 1), (count_2.write count_2_PLUS_1___d9, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected
index d32b06473..d8442582c 100644
--- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected
@@ -13,10 +13,10 @@ order: [RL_test_rule_2_T_T, RL_test_rule_2_T_F, RL_test_rule_1, RL_test_rule_2_F
 === resources (DescendingUrgencyAttributeSplitIf sysDescendingUrgencyAttributeSplitIf):
 [(count_r.read, [(count_r.read, 1)]),
  (count_r.write,
-  [(count_r.write x__h210, 1),
-   (count_r.write x__h241, 1),
-   (count_r.write x__h244, 1),
-   (count_r.write x__h248, 1)]),
+  [(count_r.write count_r_PLUS_2___d2, 1),
+   (count_r.write count_r_PLUS_4___d6, 1),
+   (count_r.write count_r_PLUS_5___d9, 1),
+   (count_r.write count_r_PLUS_3___d11, 1)]),
  (p_r.read, [(p_r.read, 1)]),
  (q_r.read, [(q_r.read, 1)])]
 
diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected
index 34b3cb918..7f3e33572 100644
--- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [RL_test_rule_1, RL_m_test_rule_2]
 
 === resources (DescendingUrgencyAttributeSubModule1 sysDescendingUrgencyAttributeSubModule1):
 [(count_r.read, [(count_r.read, 1)]),
- (count_r.write, [(count_r.write x__h152, 1), (count_r.write x__h102, 1)])]
+ (count_r.write, [(count_r.write count_r_PLUS_3___d2, 1), (count_r.write count_r_PLUS_2___d3, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected
index e46085ea6..c59b60a6e 100644
--- a/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected
@@ -9,7 +9,7 @@ order: [bar, baz]
 
 === resources (IfcIfcWarning sysIfcIfcWarning):
 [(the_r.read, [(the_r.read, 1)]),
- (the_r.write, [(the_r.write x__h108, 1), (the_r.write x__h134, 1)])]
+ (the_r.write, [(the_r.write the_r_PLUS_1___d2, 1), (the_r.write the_r_PLUS_2___d3, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected
index 21b39b533..7fd50ba94 100644
--- a/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected
@@ -12,7 +12,7 @@ order: [bar, RL_baz]
 -----
 
 === resources (IfcRuleWarning sysIfcRuleWarning):
-[(the_r.read, [(the_r.read, 1)]), (the_r.write, [(the_r.write x__h97, 1)])]
+[(the_r.read, [(the_r.read, 1)]), (the_r.write, [(the_r.write the_r_PLUS_1___d2, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected
index 611ce3461..98e6b512b 100644
--- a/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected
+++ b/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected
@@ -32,10 +32,10 @@ order: [RL_theRuleOne, RL_theRuleTwo, RL_theRuleThree, RL_theRuleFour]
 === resources (MinimalRuleWarnings sysMinimalRuleWarnings):
 [(the_r.read, [(the_r.read, 1)]),
  (the_r.write,
-  [(the_r.write x__h113, 1),
-   (the_r.write x__h145, 1),
-   (the_r.write x__h162, 1),
-   (the_r.write x__h181, 1)])]
+  [(the_r.write the_r_PLUS_23___d4, 1),
+   (the_r.write the_r_PLUS_2___d7, 1),
+   (the_r.write the_r_BITS_6_TO_0_0_CONCAT_0_1_MINUS_13___d12, 1),
+   (the_r.write the_r_PLUS_1___d15, 1)])]
 
 -----
 
diff --git a/testsuite/bsc.verilog/sysMips.out.expected b/testsuite/bsc.verilog/sysMips.out.expected
index d3f913f93..d07450c4e 100644
--- a/testsuite/bsc.verilog/sysMips.out.expected
+++ b/testsuite/bsc.verilog/sysMips.out.expected
@@ -1,8 +1,68 @@
 Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaaaaaa
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
 Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
 Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaa8caa
 Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaa8caa
 Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaa8caa
+Warning: RegFile 'top.ram_arr' -- Read address is out of bounds: 0x2aaa8caa
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
 Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
 0x0000063d
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
                 5730
+Warning: RegFile 'top.cpu_rf' -- Read address is out of bounds: 0x00
diff --git a/testsuite/bsc.verilog/verilog.exp b/testsuite/bsc.verilog/verilog.exp
index 6d9d37291..9326af21f 100644
--- a/testsuite/bsc.verilog/verilog.exp
+++ b/testsuite/bsc.verilog/verilog.exp
@@ -25,7 +25,8 @@ test_c_only Misc
 
 # Bluesim also generates warnings that Verilog can't
 test_veri_only Mips sysMips.v.out.expected
-test_c_only Mips
+# The warnings depend on if aggr-conds is on, so ensure it is
+test_c_only_bs_modules_options Mips {} {-aggressive-conditions}
 #test_syn Mips 
 
 test_veri_only Oper sysOper.v.out.expected
diff --git a/testsuite/config/unix.exp b/testsuite/config/unix.exp
index 4f81a7bb1..d52e41ddd 100644
--- a/testsuite/config/unix.exp
+++ b/testsuite/config/unix.exp
@@ -2616,6 +2616,12 @@ proc test_c_only { module {expected ""} {cbug ""} {sort_output 0} } {
     test_c_veri_internal $module {} "bs" 1 0 $expected $cbug "" $sort_output
 }
 
+# test the C simulator output via simulation with compile options
+proc test_c_only_bs_modules_options { top modules gen_options {expected ""} {cbug ""} {link_options ""} {sim_options ""} {sort_output 0} } {
+    set sysmod sys$top
+    test_c_veri_worker_int $top $sysmod $modules "bs" 1 0 $gen_options $link_options $sim_options $expected $cbug "" $sort_output
+}
+
 # compile link and test the C simulator output
 proc test_c_only_bsv { module {expected ""} {cbug ""} {sort_output 0} } {
     test_c_veri_internal $module {} "bsv" 1 0 $expected $cbug "" $sort_output