Segmentation fault while processing blif

[Vadimatorik]

Hi, this is my first time using this app. My goal is to create the most optimized seven-segment display decoder circuit possible (I've already simplified it on paper and want to make sure there's no more efficient solution). However, I've encountered a problem. The app crashes with a segmentation fault. The incident report is below.

System: Ubuntu 24.04.3 LTS

Actions for install:

apt install libreadline-dev
git clone https://github.com/berkeley-abc/abc.git
cd abc
make -j

Test file:

.model seg_7
.inputs X3 X2 X1 X0
.outputs G F E D C B A
.exdc
.names X3 X2 X1 X0
1010 -
1011 -
1100 -
1101 -
1110 -
1111 -
.end
.names X3 X2 X1 X0 A
0000 1
0010 1
0011 1
0101 1
0110 1
0111 1
1000 1
1001 1
.names X3 X2 X1 X0 B
0000 1
0001 1
0010 1
0011 1
0100 1
0111 1
1000 1
1001 1
.names X3 X2 X1 X0 C
0000 1
0001 1
0011 1
0100 1
0101 1
0110 1
0111 1
1000 1
1001 1
.names X3 X2 X1 X0 D
0000 1
0010 1
0011 1
0101 1
0110 1
1000 1
1001 1
.names X3 X2 X1 X0 E
0000 1
0010 1
0110 1
1000 1
.names X3 X2 X1 X0 F
0000 1
0100 1
0101 1
0110 1
1000 1
1001 1
.names X3 X2 X1 X0 G
0010 1
0011 1
0100 1
0101 1
0110 1
1000 1
1001 1
.end

I tried to simply generate statistics and a verlog file:

./abc/abc  -c "read_blif seg_7.blif; write_verilog seg_7_optimized.v; print_stats"
======== ABC command line "read_blif seg_7.blif; write_verilog seg_7_optimized.v; print_stats"
Warning: The design contains EXDC network.
Segmentation fault (core dumped)

If I delete this section, everything works:

.exdc
.names X3 X2 X1 X0
1010 -
1011 -
1100 -
1101 -
1110 -
1111 -
.end

Run:

./abc/abc  -c "read_blif seg_7.blif; write_verilog seg_7_optimized.v; print_stats"
======== ABC command line "read_blif seg_7.blif; write_verilog seg_7_optimized.v; print_stats"
seg_7                         : i/o =    4/    7  lat =    0  nd =     7  edge =     28  cube =    49  lev = 1

I want to point out that I'm only interested in the input range from 0 to 9. I don't need the range from 10 to 15 inclusive. Such values ​​will never be returned.

[tkoenig1]

exdc is not supported, it seems.

What you can do is to create a PLA file including the "don't case" parts, run that through "espresso -S1 -Dso" to take care of the external don't cares, and then load that into ABC. Note that ABC only supports a very limited subset of the actual PLA syntax, but it recognizes the output of espresso.