Testcse moodle3.ucsd.edu altera.com hung-wei tseng add $t5, $t1, $a2 thealexspindler@gmail.com new pass IFIDEXMWB1CPI4 why? 1. CPI 2. What stages does it need (IF, ID, EX, M, WB)? 3. Highlight the datapath for each clock cycle * Explain the values for all wires along the datapath PCWriteCond PCSource PCWrite forD MemRead MemWrite MemWrite MemtoReg IRWrite Instruction[25-0] opcode rs rt Instruction register 0 M u X 1 PC Memory Data Regster Sign extend Shift elft 2 0 1 2 3 ALU Zero ALU results ALU OP ALU Control 0 1 2 PC Source Outputs Control Op [5-0] #1
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cse moodle3.ucsd.edu
altera.com
hung-wei tseng
add $t5, $t1, $a2
thealexspindler@gmail.com new pass
IFIDEXMWB1CPI4
why?
* Explain the values for all wires along the datapath
PCWriteCond PCSource
PCWrite forD
MemRead
MemWrite
MemWrite
MemtoReg
IRWrite
Instruction[25-0]
opcode rs rt Instruction register
0 M u X 1
PC Memory Data Regster
Sign extend Shift elft 2
0 1 2 3
ALU
Zero
ALU results ALU OP
ALU Control
0 1 2
PC Source Outputs
Control
Op [5-0]
From: Alex Spindler Alex.Spindler@calbaptist.edu