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Lane E — Tally & routing (SW-E1..E5): derived tally, arbiter wiring, TSL spec reconciliation, RT-12 output crosspoint, clean/aux taps #118

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Parallel lane across engine tally + input/output TSL + the RT-12 seam (shared with the decoupled-routing backlog).

  • SW-E1 L — Internally-derived tally: per-tick recursive contributes-to-program derivation (both transition sources, keyer fill+key, stinger cover, nested compositions) — ADR-MV006
  • SW-E2 M — Wire TallyArbiter into the run loop + spawn run_tally_ingest (replaces the SetTallyOverride echo) — ADR-MV006
  • SW-E3 M — TSL codec spec reconciliation + golden on-wire vectors (six verified wire-visible deviations incl. v5.0 DLE 0xFE, CONTROL bit order, invented framing dropped) — ADR-MV006
  • SW-E4 L — RT-12 output←program crosspoint bridge (RouteIntent::Output + Command::RouteOutput + PacketRouter::move_sink; shared with CTL-6/GPU-5c; see RT-12 in decoupled-routing-backlog) — ADR-0054/R010
  • SW-E5 M — Clean-feed/aux tap taxonomy {program, clean, preview, me[n], aux[j]}; clean anchored at the verified pre-overlay ProgramSlot — ADR-0054

Design docs: production-switcher brief · media-playout brief · SW backlog · work-schedule SW stream — all delivered in PR #112. Implementation starts only after the design PR is reviewed/merged and the operator green-lights coding.

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    claimed:claudeActively being worked by the Claude devices/display program — do not pick upenhancementNew feature or requestswitcherProduction switcher program — briefs + ADR-0054..0059 + SW backlog (PR #112)

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