Lane A — Engine switcher core (SW-A1..A7): programs root, Tick hook, render-plan resolver, PVW bus, transitions wave 1, on-clock DSK/FTB, commands

[aperim-agent]

Serial lane (owns runtime.rs/drive.rs/pipeline.rs — LANE-CORE territory; items land in order).

• SW-A1 M — [[programs]] schema root + crosspoint cross-validation (lands MP-5) — ADR-M012
• SW-A2 M — Tick-widened per-tick control hook + pure SwitcherState value machine at the frame-boundary seam — ADR-0054
• SW-A3 L — Render-plan resolver fn(scene_states, switcher_state, tick) → placements (allocation-pooled, synchronous) — ADR-0054
• SW-A4 L — PVW bus: second compose against the SAME tick + per-bus preview slot + cue/pre-warm arm (WARM-ON-ARM, is_primed-gated) — ADR-P007
• SW-A5 L — Transition engine wave 1: cut/mix/dip + auto/T-bar + flip-flop; progress = f(tick), integer-frame durations, complete-then-degrade — ADR-0055
• SW-A6 L — On-clock DSK + FTB master stage (deps: SW-B4, SW-B5, SW-C3) — ADR-0054/0056
• SW-A7 L — Switcher Command variants + frame-boundary drain + correlated outcome events — ADR-0054/RT008

Invariant posture: transitions are pure per-tick render state sampled by the protected output clock — nothing in this lane may pace, await, or allocate on the clock thread (inv #1/#10); chaos/soak gates per ADR-R011.

Design docs: production-switcher brief · media-playout brief · SW backlog · work-schedule SW stream — all delivered in PR #112. Implementation starts only after the design PR is reviewed/merged and the operator green-lights coding.

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